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Semi-insulating gallium arsenide-deep trapping levels, dislocations and backgating Tang, Wade Wai Chung 1984

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SEMI-INSULATING GALLIUM ARSENIDE-DEEP TRAPPING LEVELS, DISLOCATIONS AND BACKGATING by WADE WAI CHUNG TANG B.Sc, Simon Fraser University, 1982 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES i n the Department of E l e c t r i c a l Engineering We accept t h i s thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA December, 1984 ©Wade Wai Chung Tang, 1984 9? In presenting t h i s thesis i n p a r t i a l f u l f i l m e n t of the requirements for an advanced degree at the University of B r i t i s h Columbia, I agree that the Library s h a l l make i t f r e e l y available for reference and study. I further agree that permission for extensive copying of t h i s thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. I t i s understood that copying or publication of t h i s thesis for f i n a n c i a l gain s h a l l not be allowed without my written permission. Department of ELECTRICAL ENGINEERING The University of B r i t i s h Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date DEC. 23 , 1984 E-6 (3/81) ABSTRACT Work i s reported on three topics r e l a t i n g to problems which hold back the development of GaAs integrated c i r c u i t s . These topics are deep trapping l e v e l s i n the s t a r t i n g semi-insulating GaAs, the e f f e c t of d i s l o c a t i o n s on device c h a r a c t e r i s t i c s , and backgating. (The l a t t e r i s the influence of voltages on nearby contacts on device performance). Deep trapping l e v e l s i n undoped semi-insulating liquid-encapsulated— Czochralskl GaAs grown in the <100> d i r e c t i o n were characterized using photocurrent deep l e v e l transient spectroscopy (photocurrent-DLTS). Three electron l e v e l s were found using photocurrent-DLTS i n the temperature range 200K to 400K. By using Cr electrodes, instead of Au-Ge electrodes, i t became possible to extend the experiment to a higher temperature range than previously used in this laboratory, and hence to observe the trap known as EL2. This trap has not previously been observed i n undoped l i q u i d -encapsulated-Czochralski GaAs by using photocurrent-DLTS. The p o s s i b i l i t y of an e f f e c t of d i s l o c a t i o n s on device c h a r a c t e r i s t i c s was investigated using a d i s l o c a t i o n etch procedure and measurements on an array of MESFET. Due to problems i n c o n t r o l l i n g the f a b r i c a t i o n processes, the scatter was such that no c o r r e l a t i o n between device c h a r a c t e r i s t i c s and the distance to nearest d i s l o c a t i o n would be established. However, scatter of threshold voltage was larger for devices fabricated on areas of honeycomb-like d i s l o c a t i o n s network as opposed to areas with unconnected wavy l i n e s of d i s l o c a t i o n . - i i i -Backgating (which causes unwanted communication between devices) was investigated in conjunction with substrate conduction measurement. A model was proposed for the e f f e c t as present i n the devices used in t h i s experiment. - i v -TABLE OF CONTENTS P age ABSTRACT i i LIST OF TABLES v LIST OF FIGURES . . . . v i ACKNOWLEDGEMENTS. i x 1. INTRODUCTION 1 2. OVERVIEW OF SI GaAs '3 2.1 Introduction 3 2.2 Substrate Compensation Mechanism 4 2.3 The Nature of the Deep Donor Level EL2 5 3. PHOTOCURRENT DEEP LEVEL TRANSIENT SPECTROSCOPY 7 3.1 Introduction to Deep Level Transient Spectroscopy 7 3.2 B r i e f Reviewof Published Work on PhotocWent-DLTS 11 3.3 Basic P r i n c i p l e s of Photocurrent-DLTS. " 12 3.4 Experimental Procedures 16 3.5 Results 21 4. DISLOCATIONS AND DEVICE CHARACTERISTICS 38 4.1 Introduction 38 4.2 B r i e f Review of Published Work 39 4.3 Description of Mask and Device Fabrication 44 4.3.1 Substrate Preparation 46 4.3.2 Ion Implantation 46 4.3.3 Post-Implant Anneal 49 4.3.4 M e t a l l i z a t i o n 49 4.4 Measurements • 50 4.5 Results 54 5. BACKGATING IN GaAs 68 5.1 Introduction . . . . . 68 5.2 Experimental Procedures and Results 70 6. CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK 84 REFERENCES 86 APPENDIX 93 - v -LIST OF TABLES . P age 3.1 Values of Ep and a calculated from F i g . 3.15 for the drops detected by photocurrent-DLTS 34 3.2 Relative peak height of PI to P2 37 4.1 Settings for Si 3N 1 + f i l m deposition by PECVD 47 4.2 Setting f or oxygen ashing using Plasma-Therm system 48 - v i -LIST OF FIGURES Page 3.1 Basic p r i n c i p l e of Capacitance-DLTS (a) Steady state (b) Trap f i l l i n g cycle (c) Trap emptying cycle 8 3.2 Transient current observed for sample 184-Cr at 300 K. E x c i t a t i o n l i g h t pulse turned off at t = 0 sec 13 3.3 B(= rmax/t^) versus «(= t 2 / t A ) 17 3.4 Absorption of l i g h t (670 nm) i n GaAs at 300 K 18 3.5 Sample structures used i n photocurrent-DLTS experiment (a) planar structure (b) thin sandwich structure 20 3.6 Block diagram of photocurrent-DLTS set-up . 22 3.7 Vacuum chamber used i n the photocurrent-DLTS experiment 23 3.8 Graph of Temperature vs dark leakage current and r a t i o of photocurrent to dark leakage current of (a) sample 63T42 (b) sample 51-Cr 24 3.9 A photocurrent-DLTS spectrum for sample 51-Cr (Rate Window = 40 ms) 26 3.10 A photocurrent-DLTS spectrum for sample 86-Cr (Rate Window = 40 ms) 27 3.11 A photocurrent-DLTS spectrum for sample 152-Cr (Rate Window = 40 ms) . . . . 28 3.12 A photocurrent-DLTS spectrum for sample 184-Cr (Rate Window = 40 ms) . . . 29 3.13 A photocurrent-DLTS spectrum for sample 86-T ( p o s i t i v e bias, Rate Window = 20 ms) 30 3.14 A photocurrent-DLTS spectrum for sample 86-T (negative bias, Rate Window = 20 ms) 31 3.15 A c t i v a t i o n energy plot for traps detected by photocurrent-DLTS 33 - v i i -P age 4.1 Etch p i t structure i n sample 283-S11 showing (a) honeycomb-like network and (b) wavy l i n e s 40 4.2 Mask for device array 45 4.3 Fab r i a t i o n sequence for the MESFET array 51 4.4 MESFET array on sample 283-S11 (magnified 300X) 55 4.5 IDS - VDS c n a r a c t e r i s t i c s o f MESFET from device array on sample 283-S11. V G g bias: -0.2V/step 57 4.6 T y p i c a l 1 D S - V G S c h a r a c t e r i s t i c for sample 283-S11 58 4.7 V a r i a t i o n of V f c h across the three MESFET arrays on sample 283-S11 59 4.8 MESFET array a f t e r d i s l o c a t i o n etch (a) L e f t half of the array showing network structure (b) Right half of the array showing le s s e r organize l i n e structure 60 4.9 P l o t of V T R vs distance to nearest p i t for MESFET from sample 283-S11 61 4.10 Histograms of the d i s t r i b u t i o n of Vt* for FET along the (a) L e f t half of 3rd array ( F i g . 4.8) (b) Right half of 3 rd array 63 4.11 Histograms of the d i s t r i b u t i o n of leakage current f o r FET along the (a) L e f t half of 3rd array (b) Right half of 3 rd array 64 4.12 P l o t of V t h vs l o c a l d i s l o c a t i o n density for. MESFET from sample 283-S11 65 4.13 P l o t of I D S (@ V G g = OV) vs l o c a l d i s l o c a t i o n density f o r MESFET from sample 283-S11 66 5.1 MESFET of sample 45-592 71 5.2 MESFET of sample 123-5131 71 5.3 Block diagram of backgating experimental set up 73 5.4 T y p i c a l Ij)g~V Dg c h a r a c t e r i s t i c s of sample 123-5131 with V G varying 74 - v i i i -Page 5.5 T y p i c a l I Ds~ VDS c h a r a c t e r i s t i c s o f sample 123-5131 with Vgg varying 75 5.6 T y p i c a l Ijjg-VQg c h a r a c t e r i s t i c s of sample 123-5131 76 5.7 Ty p i c a l I D S _ V G S c h a r a c t e r i s t i c s of sample 45-592 77 5.8 Ty p i c a l plot of I D S vs V B G for sample 123-5131 78 5.9 Ty p i c a l plot of I D S vs V B G for sample 123-5131 7 9 5.10 T y p i c a l plot of I B G vs V B G for sample 45-592 81 5.11 T y p i c a l plot of I R r vs V R r for sample 123-5131 82 ACKNOWLEDGEMENTS I thank my supervisor, Dr. L. Young, for his patience, guidance, and encouragement during the course of my work. Dr. W. Lau and Mr. K. Lowe are thanked for t h e i r h e l p f u l advice and Mr. D. Hutcheon i s thanked for his assistance i n f a b r i c a t i n g the device array i n the d i s l o c a t i o n experiment. I thank Messrs. I. Abdel-Motaleb, S. Dindo, W. Dur t l e r , D. Hui, and K. Tan for t h e i r h e l p f u l discussions. Mr. D. Hui i s also thanked for his assistance i n preparing some of the figures as i s Mr. S. Dindo for his assistance i n the DLTS experiment. Appreciation i s also due to Mr. G. Needham of Cominco Limited, B.C., who supplied the GaAs wafers; Messrs. A. Leugner and L. Kjolby, who maintained the equipment i n the lab;' and Ms. Charlotte Stevenson, who typed the manuscript. F i n a n c i a l support provided by the B r i t i s h Columbia Science Council and by the Natural Sciences and Engineering Research Council of Canada i s g r a t e f u l l y acknowledged. 1 CHAPTER 1 INTRODUCTION The need for high frequency c i r c u i t s i n systems such as radar, microwave telecommunication and super-computers has promoted active research i n gallium arsenide integrated c i r c u i t s (GaAs IC). In order for large scale GaAs IC to be f e a s i b l e , homogeneous, thermally stable substrates and a well-characterized f a b r i c a t i o n process are required. Among the several c r y s t a l growing techniques a v a i l a b l e , liquid-encapsulated-Czochralski (LEC) GaAs i s emerging as the best choice. One advantage i s that semi-insulating (SI) wafers can be produced without chromium doping, so that the s e l e c t i v e multiple d i r e c t ion implantation process can be applied without problems due to the r e d i s t r i b u t i o n of Cr [1,2] such as occur i n Cr-doped SI horizontal Bridgman (HB) grown GaAs. Chapter 2 gives a overview of SI GaAs. I t i s desirable that,before a s t a r t i n g wafer i s used as a substrate for IC f a b r i c a t i o n , the deep trapping l e v e l spectrum should be known and the thermal s t a b i l i t y should be proven. Chapter 3 covers the f i r s t objective of the work which was to characterize undoped SI<100> LEC GaAs as received from Cominco by a method c a l l e d photocurrent deep l e v e l transient spectroscopy. The second objective was to investigate the e f f e c t s of d i s l o c a t i o n s on device c h a r a c t e r i s t i c s . LEC GaAs has a high d i s l o c a t i o n density, t y p i c a l l y lO^-lO^/cm 2. I f d i s l o c a t i o n s should a f f e c t device c h a r a c t e r i s t i c s , t h i s high density would become a major problem. To study t h i s , an array of metal-semiconductor-field-effect-transistors (MESFET) and Schottky pads was designed and fab r i c a t e d . Chapter 4 describes the measurements made to seek a c o r r e l a t i o n between d i s l o c a t i o n s and devic c h a r a c t e r i s t i c s . The thi r d objective was to study the phenomena of substrate conduction and backgating i n SI substrates. Backgating can harmful to the operation of IC because i t indue es unwanted crosstalk between devices. The e f f e c t of backgating and the current-voltage c h a r a c t e r i s t i c s of electrodes on SI GaAs i s discussed i n Chapter 5. F i n a l l y , chapter 6 contains the summary and conclusions. 3 CHAPTER 2 OVERVIEW OF SI GaAs 2.1 Introduction GaAs technolgies have received increasing attention over the past few years for high frequency applications. The two basic advantages of GaAs over S i for IC f a b r i c a t i o n are: 1) the higher electron mobility and satur-ated v e l o c i t y i n GaAs can provide a two to six times p o t e n t i a l speed advan-tage over S i , and 2) the a v a i l a b i l i t y of GaAs as a semi-insulating substrate gives better i s o l a t i o n between devices than the p-n junction i s o l a t i o n i n S i . D i r e c t ion implantation into SI substrates i s presently one of the better techniques for GaAs IC f a b r i c a t i o n . Formation of the active region by ion implantation i n SI substrates i s desirable because of i t s p o t e n t i a l as a r e l i a b l e , high y i e l d and low cost technology. However, the inhomogen-i t y , and variable q u a l i t y of SI GaAs substrates i s a major l i m i t a t i o n at present. The production of SI GaAs by the HB technique started i n the 1960' s [3,4]. In the HB technique, GaAs i s synthesized inside a furnace by the vapor transport of As from an elemental source to Ga contained i n a quartz boat. The c r y s t a l growth i s i n i t i a t e d by moving the boat slowly down the furnace i n a temperature gradient so as to cool down the GaAs melt from one end. SI ingots are produced i f Cr i s added to the melt prior to cooling [3] or i f the ingots are exposed to an oxygen atmosphere i n the growth ampoule [4]. 4 L i q u i d encapsulation was f i r s t demonstrated by Metz et a l . [5] and was developed by M u l l i n et a l . [6] to produce GaAs ingots by the LEC tech-nique. In the LEC growth technique, the GaAs melt i s contained i n a high-p u r i t y quartz or p y r o l y t i c boron n i t r i d e c r u c i b l e , and encapsulated with a layer of molten B 20 3. The presence of the B 20 3, together with high argon pressure on top, prevent s i g n i f i c a n t loss of As during c r y s t a l growth. Growth i s i n i t i a t e d by immersing a GaAs seed through the B 2 0 3 i n t o the melt, and the c r y s t a l i s grown by slowly withdrawing the seed from the melt. Both the seed and the c r u c i b l e are rotating during the c r y s t a l p u l l i n g process. An important advantage of the LEC method i s that SI ingots can be attained without any i n t e n t i o n a l doping. Another a t t r a c t i v e feature of the LEC technique i s that the ingots produced can be c y l i n d r i c a l shaped with large diameter, whereas the ingots from HB method are the shape of the boat (D shaped) with the diameter usually less than 2 inches. The main disadvantage of LEC i s that ingots produced generally have a factor of 10 higher d i s l o c a t i o n density as compared to those grown by HB. 2.2 Substrate Compensation Mechanism The SI behaviour of GaAs i s generally believed to be due to compensation of shallow impurities by deep l e v e l s [7-9]. A model proposed by Martin et a l . [7] indicated that compensation comes from the presence of a deep donor l e v e l , l a b e l l e d as EL2 [17], i n undoped materials, and from th i s deep donor l e v e l and a Cr-related deep acceptor l e v e l i n Cr-doped materials. For undoped materials, the concentration of deep donor l e v e l s N needed to achieve SI behaviour can be determined from the charge 5 n e u t r a l i t y equation derived by Johnson et a l . [9]: n2+n(N -N„)-n. 2 A D 1 -N c (2.1) " ( W W " 1 1 ! where n, N., N^, and N_ are the concentrations of electrons, shallow accep-A D DD ' v t o r s , shallow donors, and deep donor l e v e l s (EL2), r e s p e c t i v e l y , n^ i s the i n t r i n s i c c a r r i e r concentration, N i s the e f f e c t i v e density of states i n constant and T i s the temperature. According the Eq. (2.1), with N A ~ N D = 10 i 5cm~ 3, Johnson et a l . believe that the semi-insulating behaviour (n,p « 10 7cm - 3) can be obtained when i s between 1.5xlOi5cm~3 and 5xlO J-6cm- 3 . Holmes et a l . [8] found that the concentration of deep donor EL2 i n GaAs depends on the As concentration i n the melt during growth. The EL2 density increased from about 5x lO i 5cm - 3 to 1.7x1016cm"3 as the As atom f r a c t i o n increased from 0.48 to 0.51. In addition, SI materials can be obtained only i f the As concentration i n the melt l i e s between a atom f r a c t i o n of 0.475 and 0.534. Below the c r i t i c a l As concentration (0.475) the material was p-type due to excess acceptors, while the r e s i s t i v i t y decreased sharply above 0.535 As atom f r a c t i o n as a r e s u l t of an increase i n the f r e e - e l e c t r o n concentration contributed from the high deep donor concentration. conduction band, E -E 'C EL2 i s the a c t i v a t i o n energy of EL2, k i s the Boltzmann 2.3 The Nature of the Deep Donor L e v e l EL2 EL2 has been observed, by various techniques, i n bulk and vapor phase 6 e p i t a x i a l GaAs [15,17,23,26,52] and Its thermal a c t i v a t i o n energy can be expressed as [7]: AE = E - E = 0.759 - (2.37 x IO-1*;*-*}! eV (2.2) The donor nature of t h i s l e v e l had been proven by Mircea et a l . [10]. In e a r l i e r work t h i s l e v e l was thought i n c o r r e c t l y to be due to oxygen and was considered to be an acceptor. This mistake arose because SI GaAs can be grown by the HB technique, provided the growth i s carried out i n an oxygen atmosphere [4]. A paper by Huber et a l . [11] gave evidence for the non-assignment of EL2 to oxygen in which the density of oxygen-related traps are an order lower than that of EL2 density. Holmes et a l . [8] suggested that EL2 i s probably associated with an i n t r i n s i c defect such as an As i n t e r s t i t i a l and a Ga vacant s i t e . Lagowski et a l . [12] at MIT suggested that EL2 i s created in a two-step process: 1) a Ga vacancy i s incorporated into the l a t t i c e ' during c r y s t a l growth, and 2) t h i s vacancy in t e r a c t s with an As atom during the post growth cooling/annealing process to form the a n t i s i t e defect As . This model i s supported quite well by the r e s u l t of Ga Holmes et a l . [8]. The exact o r i g i n of deep l e v e l EL2 i s s t i l l a subject of current debate. I t i s generally believed by authors such as Webers et a l . [13], E l l i o t t et a l . [14], and Lagowski et a l . [12] that t h i s l e v e l i s an As a n t i s i t e defect while Martin et a l . [15] favour the model of a point Ga defect complex involving As . 7 CHAPTER 3 PHOTOCURREMT DEEP LEVEL TRANSIENT SPECTROSCOPY 3.1 Introduction to Deep L e v e l Transient Spectroscopy Deep l e v e l transient spectroscopy (DLTS) was introduced by Lang [16] in 1974. I t i s a method of invest i g a t i n g deep trapping l e v e l s i n semiconductors. In i t s o r i g i n a l conception, the bias V(t) of a Schottky diode (or p-n junction) i s r e p e t i t i v e l y modulated from forward to reverse as the temperature of the sample i s varied. In the forward bias portion of the pulse, traps i n the depletion region are f i l l e d with c a r r i e r s . During the reverse bias portion of the pulse, traps i n the depletion region are emptied at a rate which depends upon the trap's energy l e v e l E^,, c a r r i e r emission rate e and the temperature T of the sample. The l i b e r a t i o n of these trapped c a r r i e r s r e s u l t s i n a relaxation of the depletion width and hence a transient of capacitance with a p a r t i c u l a r time constant T ( F i g . 3.1). The transient capacitance C(t) i s processed with a dual channel boxcar averager at two preset sampling times ti and t 2 - These two sampling times define a rate window of the system. At a p a r t i c u l a r temperature, the time constant of a deep l e v e l equals the rate window and AC = C ( t x ) - C ( t 2 ) reaches a maximum. Thus, a peak i n the spectrum of AC versus T i s obtained. Usually peaks w i l l appear i n the spectrum, each corresponding to a p a r t i c u l a r trap l e v e l . This o r i g i n a l form of DLTS i s known as capacitance-DLTS. By selecting d i f f e r e n t rate windows and repeating the temperature scan, a set of ( T , T ) can be obtained for a p a r t i c u l a r trapping l e v e l . V ( t ) B t ime ( b ) • 0 p + • © n u e DLTS TRANSIENT time F i g . 3 , 1 Basic p r i n c i p l e of capacitance-DLTS (a) Steady s t a t e (b) Trap f i l l i n g c y c l e (c) Trap emptying c y c l e 9 From the p r i n c i p l e of detailed balance, the time constant of a trap can be given as (with an assumption of single degeneracy) where AE = E = E - E_ (the energy difference between conduction band and n c T the trapping level) for electron traps with y = 2.28xlO 2 0cm - 2S - iK~ 2 [17], or AE = Ep = E^ - Ey (the energy diffe r e n c e between the trapping l e v e l and the valence band) for hole traps with y = 1.7xl0 2 lcm~ 2S - iK~ 2 [18], and o i s the capture cross section. Eq. (3.1) can be rewritten as So by p l o t t i n g Jin ( T 2 T ) versus 1/T (data obtained from DLTS scans) of a p a r t i c u l a r trap, a straight l i n e with a slope of AE/k and a y-axis crossing of -£n(o"Y) can be obtained. This l i n e i s c a l l e d the signature l i n e of that p a r t i c u l a r trap. From this signature l i n e , the a c t i v a t i o n energy AE and the capture cross section a can then be resolved. The trap density can be estimated using the following equation [19]: x = ( a y T 2 ) - 1 exp(AE/kT) (3.1) £n(T 2x) = M (I) - *n(cTY) (3.2) ND CX {2C AC-(AC) 2} OO (3.3) N, T C 2 ( C -C ) 2 10 where i s the net ionzed donor density, C q i s the capacitance right a f t e r the bias i s changed from forward to reverse, C i s the capacitance when the CO e q 2N 1/2 transient reaches steady state, AC = C - C , and C, = {7^=——-r} i s the - o» X l 2 ( E p - E T ) J capacitance corresponding to the non-ionized region of the depletion layer. Since the introduction of capacitance-DLTS, other types of DLTS have been described. Channel conductance DLTS (C-DLTS) was presented by A l d e r s t e i n [20] in 1976. The structure used i n this technique i s a MESFET. The p r i n c i p l e of C-DLTS i s very s i m i l a r to that of capacitance-DLTS with the exception that the change i n drain-source current of a MESFET i s monitored instead of the change i n capacitance of a Schottky diode. These two kinds of DLTS are only applicable to conductive substrates with c a r r i e r s i n j e c t e d by e l e c t r i c a l means. For SI substrates, where the free c a r r i e r concentra-ti o n i s very small, photocurrent-DLTS can be used. Photocurrent-DLTS, termed as o p t i c a l transient current spectroscopy by Hurtes et a l . [21] and photo-induced transient spectroscopy by Fairman et a l . [22], i s applicable to high r e s i s t i v i t y substrates with c a r r i e r s generated o p t i c a l l y . With d i r e c t implantation into SI substrates ( e s p e c i a l l y undoped LEC grown) emer-ging as the leading technology for IC f a b r i c a t i o n , traps in SI substrates are well worth studying and photocurrent-DLTS i s a useful method to investigate these traps. In section 3.2, a b r i e f review of photocurrent-DLTS on SI GaAs i s presented while i n the rest of the chapter, the experimental procedure of 11 photocurrent-DLTS and the re s u l t s obtained from undoped SI <100> LEC GaAs as received from Cominco are described. 3.2 B r i e f review of published work on photocurrent-DLTS Some of the publications on traps i n SI GaAs detected using photocur-rent-DLTS are: Bois [23]; Fairman, O l i v e r and Morin [22,24,32]; Deveaud and Toulouse [25]; Itoh and Yanai [26];' Rhee, Bhattacharya and Koyama [27]; Yuba, Gamo and Namba [28]; Ogawa, Kamiya and Yanai [29]; and O l i v e r , Fairman and Chen [30]. Photocurrent-DLTS was also applied to e p i t a x i a l layers on top of SI substrate by Hurtes et a l . [21,31]; Yuba et a l . [28]; Fairman et a l . [22,24,32] and Itoh et a l . [26]. Traps detected by these authors using photocurrent-DLTS are l i s t e d i n the appendix. The trap that i s believed to be associated with Cr, which was l a b e l l e d HLI by Mitonneau et a l . [18], i s generally found i n Cr doped samples and absent i n undoped samples. The electron trap EL2, which plays a c r i t i c a l role i n the semi-insulating behaviour of undoped GaAs substrates, has been found i n SI GaAs using photocurrent-DLTS only by Martin et a l . [23], Itoh et a l . [26] and Hurtes et a l . [31]. However, only Martin et a l . applied photocurrent-DLTS d i r e c t l y to SI GaAs substrate. Hurtes et a l . used samples with an undoped vapour phase e p i t a x i a l (VPE) GaAs layer on top of Cr-doped SI GaAs (The undoped layer exhibited a h i g h - r e s i s t i v i t y region near the substrate, whereas the remaining part was conducting and n-type). As shown i n the appendix, for Hurtes et a l ; EL2 was found i n n-type VPE with high r e s i s t i v i t y buffer layer on SI GaAs and not i n high r e s i s t i v i t y buffer layer on SI GaAs, so EL2 i n thi s case was properly present i n the n-type VPE layer. The structure which 12 was used by Itoh et a l . consisted of two contacts on the same side of a SI substrate, and one of the metal contact was separated from the SI substrate with a n-layer, so traps observed in the paper by Itoh et a l . may have originated from the n-layer, n-layer-SI substrate interface or the SI substrate. Over a l l , information on traps i n as-grown undoped SI LEC GaAs i s very l i m i t e d compared to other types of GaAs substrates. A l l the above quoted papers on photocurrent-DLTS, except those by O l i v e r et a l . [30] and Fairman et a l [32] , were dealing with either Cr-doped SI GaAs or e p i t a x i a l layer on top of Cr-doped SI GaAs. This may be one of the reasons why EL2 has not been reported frequently i n SI GaAs using photocurrent-DLTS, because the Cr-related l e v e l HLI i s the dominant l e v e l i n Cr-doped GaAs and EL2 could possible be compensated by HLI when a Cr-doped SI GaAs i s used. 3 .3 Basic P r i n c i p l e s of Photocurrent-DLTS During a l i g h t e x c i t a t i o n pulse, electron-hole pairs are generated which populate traps i n the sample. Af t e r the l i g h t pulse, a transient current due to emission of c a r r i e r s from traps can be observed, as shown i n F i g . 3.2. During the duration when the l i g h t i s o f f , the occupation of a trap with density N T can be written as [34] n f c(t) = {n f c(0) - n t(«)} e x p { - ( e n + e p) t} + n.O) (3.4) where n t ( o ) , the occupation of the trap just when the l i g h t i s removed (t=0) can be described by (under condition of high e x c i t a t i o n [7]) 13 0 50 100 TIME (ms) F i g . 3 . 2 T r a n s i e n t c u r r e n t observed f o r sample 184-Cr at 3 3 0 K. E x c i t a t i o n l i g h t pulse turned o f f a t t = 0 sec. 14 a v - i n t(0) = NT{1 + ^ } (3.5) n n where a /a . and v /v are the electron/hole capture cross section, and n p n p thermal v e l o c i t y , r e s p e c t i v e l y . n t(°°), the occupation of the trap at dark, steady state (t=°°) can be written as n t(») = NT{1 + ^ } (3.6) P where e /e i s the electron/hole emission rate constant. I f one assumes the n p f r e e - c a r r i e r d e n s i t i e s are n e g l i g i b l e (when compared to the emitted c a r r i e r s ) i n the sample when the l i g h t i s o f f , the decay current i ( t ) during the l i g h t - o f f cycle i s given by [20] i ( t ) = { e n n t ( t ) + e p ( N T - n t( t) } (3.7) where q i s the e l e c t r o n i c charge, w the active thickness of the layer from which the c a r r i e r s are reemitted from traps, and A the area of the contact. A f t e r s u b s t i t u t i n g Eq. (3.4) into Eq. (3.7), Eq. (3.7) becomes -(e +e ) t i ( t ) = - ^ { ( e ^ e )(n t(0)+{n t(0)-n t(co)}e n p ) + N^ ,e } (3.8) 15 However, i n DLTS, one i s concerned only about the change of the sig n a l during the l i g h t - o f f cycle, so any term i n Eq. (3.8) that i s not rela t e d to time w i l l be substracted out and Eq. (3.8) can be re-written as ( a f t e r combining with Eqs. (3.5) and 3.6)) qWAN„ a v - 1 e ~ 1 y t ) = - g - I { e n - e H ( l + f i ) " (1+^) } exp(-t/T) (3.9) n n p where x = l / ( e + e ) i s defined as the time constant of the trap. n p r For an electron trap a » a and e » e (so t ~ l / e ). Eq. (3.9) n p n p n ' reduces to y t ) = ^ N T T - i e x p ( - t / T ) (3.10) and the output of the boxcar averager ( A i ^ = ^ ( t ^ ) - I p C ^ ) ) qWAN Aip x - ^ e x p e t ^ x ) - exp(-t 2/T)} (3.11) When the temperature T of the sample i s varied, A i ^ also varies because T i s dependent on the temperature. A i ^ reaches a maxima, with 6 A i D SAip respect to T, when =0. By solving — r — - = 0, x (the value of x at 6T 6T max which the maxima occurs) i s found to s a t i s f y the following equation [12] (1 - t,/x ) exp(-t_/x ) = ( l - t . / x ) exp(-t 0/x ) (3.12) 1 max r T. max 2 max r v 2 max This implies x can be obtained once t, and t 0 are set (as shown i n e max 1 2 16 F i g . 3.3). a and E -E can be determined from Eq. (3.2) as described in n L» l section 3.1 For a hole trap o^>>a^ and e p » e n > E c l ' (3.9) again reduces to Eqs. (3.10) and (3.11) with the exception that T ~ l / e . According to Eq. P (3.11) , with t 1 < t 2 , both electron and hole traps should induce p o s i t i v e peaks i n the DLTS spectrum ( i f the assumption of a » x (a » a ) and n p p n e n » e ^ ( e ^ » e n ) for electron (hole) traps are v a l i d ) . To d i s t i n g u i s h between hole and electron traps, the structure of 86-T ( F i g . 3.5(b)) was used. I n t r i n s i c l i g h t from a 670 nm LED creates electron-hole pairs just underneath the top metal contact ( F i g . 3.4). For a negative bias applied to the electrodes, electrons are moved from the active region underneath the gate into the bulk and captured by d i f f e r e n t electron traps. So for negative bias, the transient current i n the DLTS spectrum would be mostly contributed from c a r r i e r s re-emitted from electron traps. S i m i l a r l y , i f a p o s i t i v e bias i s applied, holes are moved into the bulk and get captured by hole traps and in t h i s case, re-emitted c a r r i e r s from hole traps would be the dominant contributor to the transient current. The type of trap of a p a r t i c u l a r peak can then be resolved by comparing the respective peak i n the two spectra obtained using these two biases, and determining which i s the dominant peak. For example, i f the peak has a much higher amplitude i n the spectra obtained by using negative bias than p o s i t i v e bias, then this peak would probably be caused by an electron trap. 3.3 Experimental Procedures Specimens were fabricated using pieces from four wafers from four d i f f e r e n t ingots. The four wafers were a l l undoped SI LEC GaAs (grown i n the <100> direction) from Cominco and they were l a b e l l e d 51-T128, 86-S37, 152-S67 and 184-S72. (The f i r s t number s p e c i f i e s the ingot from which the wafer was cut while the second number s p e c i f i e s the wafer p o s i t i o n with respect to either the seed S or t a i l T of the ingot). From the r e s i s t i v i t y data supplied by Cominco, wafers 152-S67 and 184-S72 were deemed thermally stable and 51-T128 thermally unstable. (Thermally stable implies that the wafer does not lose i t s high r e s i s t i v i t y during high temperature anneal). For ingot 86, s l i c e s from the t a i l end are stable while those from the seed end are unstable so the thermal s t a b i l i t y status of wafer 86-S37 i s not c e r t a i n . F i g . 3.5 shows the d i f f e r e n t sample structures that were used i n t h i s experiment. Cr Schottky planar pads ( F i g . 3.5(a)) were fabricated on pieces of wafers 51-T128, 86-S37, 152-S67, and 184-S72 and l a b e l l e d as 51-Cr, 86-Cr, 152-Cr and 184-Cr, respectively. Cr Schottky pads (sandwich s t y l e as shown in F i g . 3.5(b)) were fabricated on a thinned piece of wafer 86-S37 and l a b e l l e d 86-T. The piece of thinned wafer was obtained by grinding a piece of as-received wafer (~500um thick) in a s i l i c o n carbide s l u r r y on a glass plate followed by a chemical etch i n a s o l u t i o n of 4H 2S0i t + 1H20 + 1H 20 2 for two minutes. In addition, two Au-Ge ohmic planar pad samples (having the same structure as i n F i g . 3.5(a)) l a b e l l e d 63-T42 and 82-S14 that were used i n Lowe's work [33] were also b r i e f l y looked at i n this experiment. The f a b r i c a t i o n steps of the Cr-Schottky samples are the same as those described i n section 4.34(iv) while section 4.34(v) describes the steps for the Au-Ge ohmic sample. 40|jm (b) F i g * 3 -5 Sample s t r u c t u r e s used i n photocurrent-DLTS experiment (a) Planar s t r u c t u r e (b) Thin sandwich s t r u c t u r e 21 The DLTS experimental set-up was developed during the course of t h i s work. This included improvement on e l e c t r i c a l shielding to reduce external noise and improvement on vacuum chamber and thermocouple system features to increase the temperature measurement accuracy. A block diagram of the experimental set-up i s shown i n F i g . 3.6. The sample i s mounted inside a l i g h t t i g ht vacuum chamber ( F i g . 3.7) using a two probe sample holder. (A two probe sample holder was designed and used so that no wire bonding i s needed and much time can be saved). A constant bias V i s established between the two electrodes using an Anatek regulated power supply and the sample i s illuminated with r e p e t i t i v e pulses of l i g h t generated by a HEMT 3300 GaAsP 670 nm l i g h t emitting diode with bias sup-p l i e d by an IEC F33 pulse generator. V a r i a t i o n of temperature of the sample i s done using l i q u i d nitrogen to cool and a power t r a n s i s t o r to heat with the temperature monitored by a copper-constantan thermocouple. The current from the sample i s amplified by a EG6G 181 current s e n s i t i v e a m p l i f ier, and then fed into a EG6G 165/162 dual gated integrator-boxcar averager for s i g -nal processing. The y-channel of a HP 7044A x-y recorder i s used to record the output of the boxcar averager and the x-channel records the thermocouple voltage of the sample. 3.4 Results In e a r l i e r work by Lowe [33], Au-Ge ohmic contact samples (63-T42 and 82-S14) were used. Except for Martin et a l . [23] and Rhee et a l . [27] , a l l the other papers mentioned in section 3.2 used either Schottky to ohmic ANATEK MODEL 25-20 Chamber-sample r LED IEC F33 PULSE GENERATOR "TRIGGER PAR 165,162 BOXCAR AVERA GER PAR 181 CURRENT AMPLIF IER TEMPERATURE HP 70AAA X-Y RECORDER F i g * 3.6 Block diagram of photocurrent-DLTS set-up ro ro LIQUID N 2 CRYOSTICK ELECTRICAL FEEDTHRQUGHS SAMPLE HOLDER LED TO VACUUM PUMP F i g . 3 . 7 Vacuum chamber used i n the photocurrent-DLTS experiment ro 500 £ LU cr cr ZD U LU o 0 ** 1 f I I I I I 4 I i \ 1 30 ( a ) 10 5 60 90 TEMPERATURE IC) 33 > O -n "0 X o 6 i o tr 33 JO m x : or < AO 20 X 0^-30 200 100 JK 2 CD r n o tz 33 m ( b ) 60 90 TEMPERATURE (C) F i g . 3 . 8 G r a p h o f t e m p e r a t u r e v s d a r k l e a k a g e c u r r e n t and r a t i o o f p n o t o c u r r e n t t o d a r k l e a k a g * c u r r e n t o f ( a ) Sample 63T4-2 ( b ) Sample 5 1 - C r 25 devices or ohmic to ohmic devices. Rhee et a l . used Au Schottky to Schottky devices while Martin et a l . used Cr Schottky to Schottky (same structure as shown in F i g . 3.5(b)) and referred to Au-Ge ohmic electrodes giving "more complicated r e s u l t s " . Figure 3.8 shows the comparison between the dark leakage of a Au-Ge ohmic sample (63-T42) to that of a Cr-Schottky sample (51-Cr). The dark leakage current f o r 63-T42 r i s e s r a p i d l y once a tempera-ture of 340K i s reached and the assumption of n e g l i g i b l e free c a r r i e r s (thermally generated) taken i n Eq. (3.7) i s no longer v a l i d and this w i l l introduce error to the photocurrent-DLTS a n a l y s i s . So for high temperature scan, Schottky-Schottky pads would be a better choice to use than ohmic pads. T y p i c a l photocurrent-DLTS spectra, obtained i n the temperature range 220K to 400K, of samples 51-Cr, 86-Cr, 152-Cr, and 184-Cr are shown i n F i g s . 3.9 to 3.12, r e s p e c t i v e l y . As the spectra show, a l l the samples revealed the same three traps i n t h i s temperature range. To determine whether these traps are electron or hole types, sample 86-T was used. F i g s . 3.13 and 3.14 show spectrum for sample 86-T obtained using negative and p o s i t i v e bias, r e s p e c t i v e l y . I t can be seen that the peak heights of peaks TP1, TP2 and TP3 i n the spectrum obtained using negative bias are at le a s t ten times higher than that obtained using p o s i t i v e bias. This indicates that these observed peaks are due to electron traps. I n t e r e s t i n g l y , both of the spectra obtained using p o s i t i v e and negative bias on 86-T show a negative peak (AI<0) at ~350K. I f a trap follows the approximation that e » e and n p a » a or e » e and o >>a , then only p o s i t i v e peaks should appear i n n p p n p n r photocurrent DLTS spectra. However, i f e ~ e , then Eq. (3.11) i s no ho AI=2nA TEMPERATURE (Kl F i g . 3.10 A p h o t o c u r r e n t - D L T S s p e c t r u m f o r s a m p l e 8 6 - C r ( R a t e windowrMO ms) N 3 00 AI=2nA ro TP3 TPA F i g . 3 . 1 3 A photocurrent-DLTS spectrum f o r sample 8 6 - T ( P o s i t i v e b i a s , r a t e window:20 ms) TEMPERATURE (Kl TPA F i g . 3.14 A p h o t o c u r r e n t - D L T S s p e c t r u m f o r sample 86-T ( N e g a t i v e b i a s , r a t e window:20 ms) Table 3.1 Values of and a calculated from F i g . 3.15 for the traps detected by photocurrent-DLTS Label E T[eV] Capture cross section o (cm 2) n API 0.80 4.9 X AP2 0.72 1.3 X 1 0 " i 2 AP3 0.53 2.1 X IO" * 2 BP1 0.80 1.9 X IO - 1** BP2 0.72 3.4 X IO"* 2 BP3 0.52 1.2 X 1 0 " i 2 CP1 0.76 1 X 10"  i k CP2 0.71 4 X 10"^ 2 CP 3 0.53 7 X 1 0 " i 3 DPI 0.79 2.9 X 1 0 " ^ DP2 0.72 5.8 X 1 0 " A 2 DP3 0.50 2.9 X io- * 3TP 4 0.65 3 X 1 0 " i 5 CM AP13P1 CP1.DP1 EL2 EL12 TPA O 0 51-Cr 86-Cr 152-Cr 18A-Cr 86-T EL3 AF3.BP3 CR3,DF3 «// // tt/o L/ / t-/ A/* ELA 2.5 3.5 1000/T I K"11 4.5 F i g . 3-15 A c t i v a t i o n energy p l o t f o r traps detected using photcurrent-DLTS CO CO 34 longer v a l i d and negative peaks can occur. For a trap to have negative peak, the condition i(°°) - i(0) > 0 must be s a t i s f i e d . This implies (from Eq. (3.8)) either a v e e < e and < — 3.13(a) n p a v e or e < e p n and e a v J l < P P e a v p n n 3.13(b) so for a trap with an electron emission rate smaller than the hole emission rate while having an electron capture cross section greater than the hole capture cross section, a negative peak would occur. S i m i l a r l y , the symmet-r i c a l case also gives a negative peak. Ogawa et a l . [29] describes t h i s as being a trap i n t e r a c t i n g with both bands. The Arrhenius plots of £nT 2x versus 1/T for a l l the above observed traps are shown i n F i g . 3.15. For comparison purpose, several signature l i n e s of traps c l a s s i f e i d by Martin et a l . [17] are also shown in the same fi g u r e . The values of the apparent a c t i v a t i o n energy E^ , and the capture cross sections a were calculated (using Eq. (3.2)) from the data i n F i g . 3.15 and are l i s t e d i n Table 3.1. The possible a s s o c i a t i o n of observed traps can be summarized as follows: AP1,BP1,CP1,DP1 EL 2 AP2,BP2,CP2,DP2 EL12 35 AP3,BP3,CP3,DP3 EL4 TP4 0 2 related donor trap as described i n O l i v e r et a l . [16] and Ogawa et a l . [15] In t h i s experiment, trap PI observed i n undoped SI LEC GaAs i s assoc-ia t e d with the major donor l e v e l EL2. EL2 i s sometimes described as the dominant l e v e l (Section 2.3) in V.P.E. and bulk (both conductive and semi-insulating) material, however, PI observed in this experiment i s at most comparable with and not dominant over other l e v e l s . The reason could be that the presence of a negative peak close by PI ( f o r example TP4) i n the spectrum and the superposition of PI with the negative peak reduces and r e s t r i c t s the peak height of PI. EL12 and EL4 have not been frequently observed by other authors. Both of these traps had been observed by Lowe [33] i n previous study at U.B.C. on undoped SI LEC GaAs and EL4 had been i d e n t i f i e d by Fairman et a l . [32] i n Cr-doped Bridgman GaAs. A negative peak ( i d e n t i f i e d as TP4 i n t h i s experiment) was also observed by Fairman et a l . [32] i n Cr-doped SI LEC and i n Bridgman GaAs and by O l i v e r et a l . [30] i n undoped SI LEC GaAs. O l i v e r et a l . believe t h i s negative peak i s an oxygen-related l e v e l with oxygen coming from the wet (high water content ~ lOOOppm) B 20 3 encapsulant layer during c r y s t a l growth and that t h i s l e v e l , together with EL2, i s responsible for the compensation e f f e c t i n undoped SI LEC GaAs. The e f f e c t of water content of the B 20 3 layer on LEC GaAs was also investigated by Rumsby et a l . [35] , and they observed that high 36 r e s i s t i v i t y c r y s t a l s were obtained when a wet B 20 3 layer was used while low r e s i s t i v i t y c r y s t a l s were obtained with a dry B 2 0 3 layer. Therefore, the water content i n B 20 3 may have some e f f e c t on the compensation mechanism i n LEC GaAs as O l i v i e r et a l [30] proposed and the negative peak (TP4) observed 0 i n the photocurrent-DLTS spectra may be the r e s u l t of the water content i n B 2 0 3 . The r e l a t i v e heights of the peaks for P1(EL2) and P2(EL12) for samples from d i f f e r e n t s l i c e s are compared in Table 3.2. The sample 51-Cr, believed to be thermally unstable, has the lowest r a t i o of PI to P2 when compared to the other samples which are e i t h e r d e f i n i t e l y indicated to be thermally stable (152-Cr and 184-Cr) or half way on the ingot between stable s l i c e s and unstable s l i c e s (86-Cr). I t has been shown by Ta et a l . [36] that for undoped SI LEC GaAs, thermal s t a b i l i t y i s achieved only f o r samples with stoichiometric or A s - r i c h composition. Having low concentration of P1(EL2), and with EL2 believed to be a As complex, sample 51-Cr i s Ga expected to have high Ga/As melt composition during growth and therefore thermally unstable. S i m i l a r l y , f o r 86-Cr, the Ga/As melt composition must have changed from high i n the seed end of the ingot to low i n the t a i l end. The above r e s u l t i s very i n t e r e s t i n g because i t implies that the thermal s t a b i l i t y of a GaAs ingot can be ascertained not only by measuring r e s i s t i v i t y before and after high temperature anneal but also by comparing r e l a t i v e peak heights of a photocurrent-DLTS spectrum. 37 Table 3.2 Re l a t i v e peak height of PI to P2 Sample Relative peak height of PI to P2 (x .= 40ms) Average r e l a t i v e peak height of PI/P2 (over 5 scans) 51-Cr 0.18 0.21 86-Cr 0.97 0.98 152-Cr 2.0 2.25 184-Cr 0.79 0.81 To summarize, the following conclusions can be made: (1) Three electron l e v e l s were found i n a l l four s l i c e s , from four d i f f e r e n t ingots, supplied by Cominco. The r e s u l t suggests that these three l e v e l s are c h a r a c t e r i s t i c s of GaAs wafers from Cominco. The a c t i v a t i o n energies of these l e v e l s were found to be 0.80, 0.72, 0.52 eV and they were associated with electron l e v e l s EL2, EL12 and EL4, res p e c t i v e l y . (2) A negative peak that was observed previously by other authors [30,32] was also detected i n this experiment. This l e v e l i s believed, by O l i v e r et a l . [30], to be responsible, together with EL2, for compensating shallow acceptors i n undoped SI LEC GaAs. (3) Thermally stable s l i c e s were shown to have higher r e l a t i v e peak height r a t i o of Pi (0.80 eV) to P2 (0.72 eV) than that i n thermally unstable s l i c e s . Hence, thermally u n s t a b i l i t y could have been caused by under compensation due to the lower concentration of EL2. 38 CHAPTER 4 DISLOCATIONS AND DEVICE CHARACTERISTICS 4.1 Introduction Large diameter (50-75mm) LEC GaAs s l i c e s generally have a high d i s l o c a t i o n density (10 4-10 5cm" 2). By contrast Czochralski-Si i s nowadays nominally d i s l o c a t i o n free. As the demand for GaAs i n high speed IC ap p l i c a t i o n increases, the question of the e f f e c t of d i s l o c a t i o n s on device c h a r a c t e r i s t i c s becomes important. D i s l o c a t i o n s have been known for some time to have harmful e f f e c t s on li g h t - e m i t t i n g diodes and lasers i n which they cause nonradiative recombina-tio n regions [37], For GaAs MESFET, the possible e f f e c t s of d i s l o c a t i o n s on device c h a r a c t e r i s t i c s , i n p a r t i c u l a r on threshold voltage, are c r u c i a l to the development of large scale IC. Published work i s not i n agreement on the influence of these defects on threshold voltage. A b r i e f review of published work i s presented i n section 4.2. A primary cause of d i s l o c a t i o n s i n GaAs i s believed to be thermally induced stress o r i g i n a t i n g from a x i a l and r a d i a l temperature gradients dui>-ing c r y s t a l growth [38]. D i s l o c a t i o n densities and t h e i r v a r i a t i o n s i n GaAs can be obtained from the etch p i t densities (EPD) using a molten KOH etch [39] or a A-B etch [40]. For large diameter (50-75mm) undoped SI LEC GaAs, EPD v a r i a t i o n across the diameter generally follows a W pattern for wafers near the seed end of an ingot and i t could e i t h e r follow a W pattern or a U pattern for wafers near the t a i l end of an ingot ( f o r example, see Ref. 41). 39 On a microscopic scale, the d i s l o c a t i o n s form a honeycomb-like network of c e l l s with diameter of the c e l l s ranging from 100um to 500jjm (corresponding to EPD of approximately l x l 0 5 c m " 2 ) . When the EPD i s less than 2xl0 1 +cnF 2, t h i s network takes on a new structure where the etch p i t s form v i s i b l e wavy l i n e s ( F i g . 4.1). Chen et a l . [41] reported that these d i s l o c a t i o n net-works were formed to minimize the s t r a i n energy, of the GaAs c r y s t a l . To have a conductive n-channel, the implanted ions ( S i i n this experiment) should s e t t l e on a Ga s i t e during post-implantation annealing i n order to act as an n-type dopant. Thus the concentration of Ga vacancies a f f e c t s the amount of a c t i v a t i o n of implanted ions. Heinke and Queissen [42] have shown that d i s l o c a t i o n s i n GaAs act as a sink of nearby defects i n which defects surrounding a d i s l o c a t i o n are gettered into the d i s l o c a t i o n core. Whether or not t h i s kind of defect gettering around a d i s l o c a t i o n has any e f f e c t on the a c t i v a t i o n e f f i c i e n c y of implanted ions and hence the threshold voltage i s s t i l l not c l e a r . In the present work, MESFET were fabr icated on an undoped SlO.00^LEC GaAs sample, using f a c i l i t i e s a v a i l a b l e at U.B.C, and the scatter of device c h a r a c t e r i s t i c s was investigated with respect to the d i s l o c a t i o n d i s t r i b u t i o n on the same sample. 4 .2 B r i e f Review of Published Work Several papers discussed the e f f e c t of c r y s t a l growth parameters on LEC GaAs c r y s t a l . The e f f e c t of ambient gas on undoped LEC GaAs was reported by Emori et a l . [43]. D i s l o c a t i o n densities were found to decrease when krypton was used instead of argon, nitrogen or helium. Ta et a l . [44] ( b ) F i g . 4 .1 E t c h p i t s t r u c t u r e i n s a m p l e 2 8 3 -S11 s h o w i n g ( a ) h o n e y c o m b - l i k e n e t w o r k and ( b ) wavy l i n e s 41 and Holmes et a l . [45] found that SI GaAs pulled from stoichiometric or As-r i c h melts showed excellent s t a b i l i t y to heat treatment while SI Ga-rich materials exhibited p-type conversion. Chen et a l . [41] showed the use of good diameter c o n t r o l , thick B 2 0 3 encapsulating layers, s l i g h t l y A s - r i c h melts and low ambient pressure gave d i s l o c a t i o n densities as low as 6000 cm - 2. Improved LEC techniques have been described i n the past several years i n an attempt to obtain low and homogeneous d i s l o c a t i o n density GaAs. By applying a v e r t i c a l magnetic f i e l d to the GaAs melt, Terashima et a l . [46] and Osaka et a l . [47] showed that temperature fl u c t u a t i o n s i n the melt were greatly reduced and therefore, more homogeneous c r y s t a l s can be obtained. To achieve a low temperature gradient around the growing c r y s t a l , Shimada et a l . [48,49] developed a new LEC technique which reduced the temperature gradient by heating the B 20 3 encapsulant layer through a window on the susceptor wall and by setting up a thermal b a f f l e above the c r u c i b l e . Using t h i s technique, a d i s l o c a t i o n density of 1000cm - 2 was observed by Shimada et a l . i n 2-in-diameter undoped SI GaAs. Nearly d i s l o c a t i o n - f r e e GaAs (20-35 mm diameter) was reported by Jacob et a l . [50] when the c r y s t a l was heavily doped with indium or antimony. I t i s believed [50,67] that the addition of In or Sb increased the resistance of the c r y s t a l to the generation and propagation of d i s l o c a t i o n s during growth. The r e l a t i o n s h i p between EL2 concentration d i s t r i b u t i o n and di s l o c a -t i o n d i s t r i b u t i o n i n a GaAs wafer have been studied by a number of authors. Holmes et a l . [51] reported the pattern of EL2 concentration and d i s l o c a t i o n density across the wafers toward the seed end of 3-in-diameter SI<100>LEC GaAs ingots was the same (that i s , they both have a W-shaped pattern across 42 the wafer). This r e l a t i o n was not observed for wafers near the t a i l end or along the ingot. Martin et a l . [52] observed that EL2 concentration and d i s l o c a t i o n density had the same pattern across wafers but not along the ingot. Both Holmes et a l . and Martin et a l . did not claim d i r e c t quantitative c o r r e l a t i o n between EL2 concentration and d i s l o c a t i o n density. Brozet et a l . [53] reported s i m i l a r r e s u l t s as that above by using high s p a t i a l r e s o l u t i o n near infrared absorption. In addition, they observed fin e structure superimposed on to the EL2 concentration v a r i a t i o n and t h i s f i n e structure can be related to gettering of EL2 (or defects) to d i s l o c a t i o n cores. Hasegawa et a l . [19] reported good c o r r e l a t i o n on undoped conductive n-type LEC GaAs, both seed end and t a i l end, for wafers with EPD higher than 2xl0 5cm~ 2. However, with EPD les s than 2 x l 0 5 c m - 2 , Hasegawa et a l . reported that the EL2 density was almost independent of the EPD. For Martin et a l . , Holmes et a l . , and Brozel et a l . the concentration of EL2 was determined by near infrared o p t i c a l absorption while for Hawegawa et a l . , EL2 concentration was determined using capacitance DLTS. The e f f e c t of d i s l o c a t i o n on leakage current across wafers of undoped SK10OLEC GaAs was studied by Miyazawa et a l . [54], Matsumura et a l . [55], and Matusmoto et a l . [56]. I t was found that for wafers near the seed end, the leakage current was inversely proportional to etch p i t density. Further-more, Matsumoto et a l . did not observe this c o r r e l a t i o n between d i s l o c a t i o n density and leakage current for wafers near the t a i l end and found that a high temperature anneal s i g n i f i c a n t l y smooths out the inhomogeneity of leakage current across a wafer. The d i s l o c a t i o n e f f e c t on H a l l mobility and r e s i s t i v i t y was also looked at [55,57,58] and H a l l mobility was shown to be 43 proportional to the logarithm of the EPD while r e s i s t i v i t y was inversely proportional to EPD. The e l e c t r i c a l homogeneity of the S i implanted layer i n undoped SI<100>LEC GaAs was investigated by Honda et a l . [59], both sheet resistance and sheet c a r r i e r concentration were found to be c l o s e l y correla-ted with the d i s l o c a t i o n density d i s t r i b u t i o n . Contrary to the r e s u l t reported by Matsumura et a l . [55] , Blunt et a l . [60] reported that the d i s -l o c a t i o n density was d i r e c t l y proportional to that of sheet resistance. However, Blunt et a l . used Cr-doped SI<001>LEC GaAs while Matsumura et a l . used undoped SI<L00>LEC GaAs. The question of whether d i s l o c a t i o n s have any deleterious e f f e c t s on MESFET performance has been studied by several groups recently. For undoped SI<100>LEC GaAs, Nanish et a l . [61] reported that FET fabricated on high EPD area showed high drain source current and low threshold voltage (V , ) DS tn as compared to those on low EPD area. The v a r i a t i o n of I across a Cr-doped SK100XLEC GaAs was shown [62] to have s i m i l a r r e s u l t s as in the undoped case. Recent publications by Miyazaiwa et a l . [63,64] reported that the V of a FET ( f a b r i c a t e d on Cr doped SK100XLEC GaAs) was dependent on the distance between the FET and the nearest d i s l o c a t i o n (etch p i t ) . MESFET located l e s s than 50um from a d i s l o c a t i o n exhibited lower V , than those far th from a d i s l o c a t i o n . Furthermore, the threshold voltage standard deviation oV ^ w a s shown [65] to be affected by the d i s l o c a t i o n c e l l network and not the d i s l o c a t i o n density. MESFET also exhibited lower and higher V , J DS th when they were located in the central parts of the d i s l o c a t i o n c e l l network than when they were near the d i s l o c a t i o n network c e l l w a l l . On the other hand, no d i r e c t evidence of d i s l o c a t i o n e f f e c t s on V were observed [66] 44 for MESFET on Cr-doped SI<1L1>HB GaAs; but i n th i s case, nonuniformity of V between wafers from difference ingots was a more serious problem. F i n a l l y , a recent paper by Winston et a l . [67] reported a contradictory r e s u l t to that of Miyazawa et a l . [63,64]. Winston et a l . observed no c o r r e l a t i o n between a t r a n s i s t o r ' s V , and i t s distance to a nearest th d i s l o c a t i o n for either In-alloyed LED GaAs (IN„ n^Ga- QQ-TAS) or u . u u J u • y y / conventional LEC GaAs and that the V , was more uniform on low-dislocation th In-alloyed LEC GaAs than on hi g h e r - d i s l o c a t i o n conventional LEC GaAs. 4.3 D e s c r i p t i o n of Mask and Device F a b r i c a t i o n An array of te s t i n g devices was designed and a r u b y l i t h copy of the array was made. The r u b y l i t h was sent to P r e c i s i o n Photomask Lt d . of Quebec for f a b r i c a t i o n of the photographic mask. The device array was stepped and repeated to f i l l the mask (2.5inx2.5 in) . The design consisted of an array of MESFET and an array of Schottky pads; gate length, channel width and drain source distance of these MESFET were 4 pm, 25pm, and 10urn, re s p e c t i v e l y . A gate length of 4pm was used to assure high y i e l d . A dimension of 50pmxl00pm was used for the gate and drain and source contact pads so that there i s enough room to manipulate the probes i n a multi-probe s t a t i o n to contact the appropriate pads without the probes shorting each other. The separation between the gate of two adjacent FET was 110 pm. The dimension for the Schottky pad was 140pmxl20pm with a separation of 10pm between pads. Six patterns were designed for use i n f a b r i c a t i n g the array with multiple d i r e c t s e l e c t i v e ion implantation as the process. The required six patterns were grouped into a single mask (as shown in F i g . 4.2) to save 45 (F) (E) (D) (o TJuiriJTJTTiriTLTTrTrTTiJtrTr^ TrTrirTJTr (B) ImiJTfTfLT^ (A) 200 j Jm F i g . 4.2 Mask f o r device a r r a y 46 money. From F i g . 4.2, pattern A i s the r e g i s t r a t i o n marks, pattern B i s the n-implant, pattern C i s the n + implant and ohmic contacts, pattern D i s the gate m e t a l l i z a t i o n , pattern E i s the Schottky pads, and pattern F i s the metal connection that could be used to connect an array of FET together for future surface analysis studies. 4.3.1 Substrate Preparation A piece of wafer (1.5cmxO.9cm) was cut from an undoped SI<100>LEC GaAs s l i c e ( l a b e l l e d 283-S11) from Cominco. F a b r i c a t i o n began with the following precleaning procedure (provided to this group by Mr. G. Needham of Cominco): i ) A two part degreasing consisting of a 5 minute b o i l i n g acetone bath and a 5 minute b o i l i n g isopropanol bath. i i ) A GaAs etch consisting of a 4 minute immersion in a f i l t e r e d 1% ALCONOX (Monosodium dihydrogen phosphate) solution at 25 °C and followed by a 15 second rinse in DI water. i i i ) An oxide etch consisting of a 30 second immersion i n 1H202:1NH1+0H:240H20 and followed by a 15 second rinse in DI water. iv) A f i n a l b o i l i n g isopropanol bath for 2 minutes, the wafer then being immediately put into the Plasma-Therm system for SigN^ deposition. 4.3.2 Ion Implantation An SijN^ f i l m of 900A thickness was deposited on the wafer by plasma-enchanced-chemical-vapour-deposition (PECVD) technique using the Plasma-Therm HFS 500E RF system ( F i g . 4.3a). The thickness of the f i l m was measured by an ellipsometer controlled by PDP8e. This Si3N4 f i l m would 47 remain throughout the process so as to protect the GaAs surface. Settings of the Plasma-Therm system for the deposition are shown i n Table 4.1. Table 4.1 Settings for S i 3 N . f i l m deposition by PECVD NH3 flow rate 75 SCCM He flow rate 500 SCCM 5% S 3N 4/He 500 SCCM Pressure 1525 um Temp, of Substrate 308 °C R.F. Power 100 W Deposition Time 6 min. The f i l m was then annealed at 850°C for 14.5 minutes i n flowing N 2 (1 liter/minute) i n a Mini Brute s i l i c a tube furnace. No evidence of cracking of the f i l m was observed a f t e r heat treatment. In the next step, windows were opened i n the Si 3N, + f i l m for n-implant with the following procedure. i ) The Si 3N l + f i l m was cleaned by a 5 minute b o i l i n g t richloethylene bath, a 5 minute b o i l i n g acetone bath and a 5 minute b o i l i n g TRANSENE 100 bath. The wafer was then put into a Statham SD6 oven at 200°C for 30 minutes to eliminate water content on top of f i l m . 48 i i ) Shipley AZ1450J photoresist was deposited onto the SigN^ f i l m , baked at 100°C i n the Statham SD6 oven for 25 minutes, wafer was then aligned to appropriate mask and exposure to UV l i g h t for 30 seconds using a Kasper mask aligner, followed by a 2 minute photoresist development and then a DI water rinse ( F i g . 4.3 b) . i i i ) Etching of SigN^ through windows for 9 minutes (at an etch rate of 50A/min) i n buffered HF reduced the thickness of Si 3 N i t f i l m under the windows by 450A ( F i g . 4.3C). iv) A Si implant was done to produce an n-layer with an energy of 120 kev and a dose of 3.38x10 i 2cm~ 2 using the U.B.C. Extrion 200 Ion implanter. Removal of the photoresist a f t e r implant was done by oxygen ashing i n the Plasma-Therm system. Table 4.2 shows the settings that were used ( F i g . 4.3d) Table 4.2 Settings for oxygen ashing using Plasma-Therm 0 2 flow rate 200 SCCM pressure 250 um Temp, of Substrate 120° C R.F. power 200 W Ashing time 25 minutes 49 v) Step ( i ) , ( i i ) and ( i v ) were repeated again for the n + implant. In t h i s case, an energy of 100 eV and a dose of 3.37xlO i 3cm - 3 were used ( F i g . 4.3e) . 4.3.3 Post-implant anneal Following implantation, a S i 0 2 layer 0.1um thick was deposited (by RF sputtering i n a Perkin-Elmer 3140 RF system) to serve as an anneal cap ( F i g . 4.3f). Annealing was done in a Mini Brute furnace at 850°C f o r 20 minutes i n flowing N 2 (1 l i t e r / m i n u t e ) . The S i 0 2 f i l m was then removed by a 1 minute buffered HF etch. 4.3.4 M e t a l l i z a t i o n Ohmic contacts of Ni on top of AuGe (88% Au, 12% Ge) were put down using the following procedure. i ) Windows for the ohmic contacts were opened by repeating step ( i ) , ( i i ) and ( i i i ) of section 4.3.2 ( F i g . 4.3g). i i ) Photoresist was then removed by acetone and step ( i ) and ( i i ) of section 4.3.2 were repeated together with a 2 minutes chlorobenzene soak i n room temperature before photoresist development to re-define the ohmic contact window. This step i s necessary because while doing a SigN^ etch, the buffered HF also weakens the photoresist and the o r i g i n a l layer of photoresist i s then no longer able to l i f t o f f the heavy layer of Au-Ge/Ni. The chorobenzene soak i s used to strengthen the top layer of the photoresist to the developer so that an undercut 50 edge p r o f i l e can be obtained upon photoresist development and l i f t - o f f of metal l a t e r would be easier ( F i g . 4.3h). i i i ) E l e c t r o n beam evaporation of AuGe/Ni to a t o t a l thickness of 2000A using Veeco VE 400 ( F i g . 4.3i). iv) L i f t o f f of unnecessary metal by immersion i n 1112 remover and ohmic contacts were then alloyed for 10 minutes i n a Mini Brute furnace pre-heated to 450°C with flowing N 2 ( F i g . 4.3j) . v) Gate m e t a l l i z a t i o n was done by repeating step ( i ) , ( i i ) and ( i i i ) of thi s section. The l i f t o f f procedure was then performed a f t e r a layer of 2000A thick of A l was deposited ( F i g . 4.3k,l) . To obtain arrays of Schottky pads, step (v) of th i s section, with Cr as the metal, was repeated. 4.4 Measurements A f t e r the MESFET was made, the drain-source current ( I n c ) versus drain-source voltage (V ) c h a r a c t e r i s t i c s were studied using a Tektronix Do 577 curve tracer with connection to the FET made under a multi-manipulator probing system. I versus gate voltage (V ) c h a r a c t e r i s t i c s for every DS GS MESFET were then measured. In th i s measurement, the wafer was put inside the probing system with the MESFET under study properly connected. A fixed V of 2V (from an Anatek regulated power supply model 25-20) was applied to the drain ohmic pad while the output of the source pad was taken to an EG&G 181 current a m p l i f i e r . A V of 2V was used so as to assure that the MESFET U b was operating i n the saturation region. The two adjacent FET to the FET under study were pinched o f f by the a p p l i c a t i o n of -1.5V to t h e i r gate so 51 / / / / / / / / / / / S i a N A / / / I I I I I I I ! SI GaAs (a) S i 3 N A deposition \\ \\\ > \ \ R E S I S T ^ ^ \ I I I I 1 I I I I / S i . ^ / / / / / / / / / / / SI GaAs (b) photoresist development \\ \ \ / / / / \ \ RESIST. \T / h i I l\ I , i , . r, , , i l / / S i 3 N A / / / SI GaAs (c) Si^N A etch for implant w \ \ / / \ \ R E S I S T \ \ \ / / / / / / / / ' / / S ' 3 N 4 / / / n - _LAYER SI GaAs (d) channel implant F i g . 4 . 3 F a b r i c a t i o n sequence f o r the MESFET a r r a y 52 \ \ \\\ \\\ i A \RESIST\W \ \ ) \ , , , '/ / S i g N A / / / T I + n 1 - + i nSI GoAs ( e ) n* implant 5 i 0 2 ~r~r ! n "1 1 r i n i _ * i  1 n SI GaAs (f ) encapsulation and anneal 113? I i \\\ i I t n + J._n...j n + \ \RESIST\\ \ / / S i 3 N A / / / SI GaAs (g) resist development for Si3N^ e tch 77^ 1 chloro benzene modified layer 1A \ \\ / / i WRESISTW \ //SiaNA / / / + i n 1 + 1 i n L _ n _ . i n j i 1 ! J SI GaAs  ( h ) resist development for ohmic metallization F i g . 4 . 3 c o n t ' d 53 • • i r • • • • • * :: METAL: :: i l l TT • • \ \ \ \ \ • • • \W / / / URESISTW /// I • • • > j 1 • * * • 1 9 9 9 . | • * • » 1 / / S i ^ / / / + n J + n SI GaAs ( i) source-drain metallization 77>r/W]rTTTTl 17^ ! n + ! n ! i ! n SI GaAs ( j ) removal of resist (lift-off) T^/I I l\n~TTTT\ \ \ \ \ \ \ \ RESISTv \ \ \\Trrr\Aiis\^Li 11 ! n i n i n + SI GaAs ( k) resist development for gate metallization HWIII 1 : : : : &8I : : : : ! / / S i 3 N A / / / n i _ _ n _ _ • n* i i SI GaAs ( I) gate metallization F i g . 4 . 3 cont'd 54 i s o l a t i o n of the FET can be obtained. The gate bias V was then varied GS from zero to a pinchoff voltage at which no I can be observed. An I -V Do D GS plot was made for each MESFET using the HP7044A X-Y recorder. From each plot the I at zero gate bias and the threshold voltage (which the author Do defined as the gate voltage at which an I of 2uA i s observed) were Do resolved. F i n a l l y , the dark leakage current between adjacent Cr-Schottky pads were measured by applying a bias of 6V and the dark leakage current was recorded using the EG&G181 current amplifier. After a l l the measurements, the sample was sent to Cominco for a molten KOH etch. In the d i s l o c a t i o n etch, the sample was put inside a n i c k e l c r u c i b l e , KOH beads were then put on top of the sample, the c r u c i b l e was then put i n s i d e an oven, af t e r an etch time of 5 minutes at 500°C, the sample was taken out, cooled down, and rinsed with DI water. Af t e r the d i s l o c a t i o n etch, several measurements were made: F i r s t , the distance between each MESFET and the nearest etch p i t were recorded;" then the l o c a l etch p i t density i n a 200umx200um area centered at each MESFET were col l e c t e d ; f i n a l l y , the d i s l o c a t i o n network structure over the whole sample were recorded. 4.5 Results On the 0.9cmxl.5cm sample, 3 arrays of MESFET with approximately 120 FET per array were fabricated. Out of these 366 MESFET, 260 MESFET were fu n c t i o n a l , the remaining 106 non-functional MESFET having bad gate alignment so that the channel could not be pinched o f f . F i g . 4.4 shows part F i g . 4.4 MESFET a r r a y on sample 283 - S 1 1 (Magnified 300X) 56 of a fabricated MESFET array. A t y p i c a l I -V c h a r a c t e r i s t i c s for these Uo Uo MESFET are shown i n F i g . 4.5. Hysteresis loops i n the ^g-Vpg curves of F i g . 4.5 are often observed in GaAs MESFET [33,68], They are a t t r i b u t e d to trapping and re-emitting of c a r r i e r s from deep l e v e l traps present i n the channel region. A t y p i c a l I- -V curve of these MESFET i s shown i n F i g . DS GS 4.6. F i g . 4.7 shows the v a r i a t i o n of V , f o r the 3 MESFET arrays across the th sample. I t can be seen that the scattering of V , i s more noticeable for th MESFET located on the l e f t half of the sample. Figure 4.8 shows one of the array of MESFET (3rd array) a f t e r the d i s l o c a t i o n etch. The etch removed the m e t a l l i z a t i o n and the SigN^ f i l m , but the l o c a t i o n of ohmic pads and hence the l o c a t i o n of the gates are s t i l l c l e a r l y v i s i b l e . To check the r e l a t i o n s h i p of V with distance to the nearest d i s l o c a t i o n , a scatter plot of V against the gate-to-nearest-pit distance f o r a l l the functional MESFET was made. F i g . 4.9 indicates that there i s no d i r e c t dependence of MESFET V , on i t s distance from a nearest d i s l o c a t i o n . th This r e s u l t agrees with that found by Winston et a l . [67] and disagrees with that by Miyasawa et a l . [64]. According to Winston et a l . , one of the possible reasons for Miyasawa et a l . to observe a c o r r e l a t i o n between Vth and distance to nearest d i s l o c a t i o n i s that t h e i r study consisted of data from randomly selected MESFET along the diameter of a whole wafer so their finding was the r e s u l t of superimposing d i s t r i b u t i o n s from regions of d i f f e r e n t d i s l o c a t i o n density and V ^. 1° 8 e t a true microscopic r e l a t i o n s h i p between a MESFET's V ^ and i t s distance to a nearest d i s l o c a t i o n , Winston et a l . [67] suggested a small limited area should be investigated instead of a large area where the EPD may vary considerably. 57 F i g . 4.5 I r i c - v r 1 Q c h a r a c t e r i s t i c s o f MESFET f r o m t h e d e v i c e a r r a y on s a m p l e 283-S11. V__ b i a s : - 0 . 2 V/ s t e p 58 F i g . 4 . 6 T y p i c a l I D S - V G S c h a r a c t e r i s t i c s f o r sample 283-S11 ++ ++++ \ v v + + * + + ++ + 3 0 4 8 6 6 8 4 1 0 2 1 2 0 D l s t . a c r o s s t h e 1 s t a r r a y ( . 1 1 E - 3 m) 2 5 4 5 6 5 8 5 1 0 5 1 2 5 D l s t . a c r o s s t h e 2 n d a r r a y C . 1 1 E - 3 m) ~ 2 . 7 5 > I w 2 . 2 a - 1 . 6 5 o > o 1 . 1 . 5 5 :* * + + + % * + + A *" +*> 2 5 4 5 6 5 8 5 1 0 5 1 2 5 D l s t . a c r o s s 3 r d a r r a y ( . 1 1 E - 3 m) F i g . 4.7 V a r i a t i o n o f V T H across the three MESFET a r r a y s on sample 283-S11 F i g . 4 . 8 MESFET a r r a y a f t e r d i s l o c a t i o n e t c h ( a ) L e f t h a l f o f t h e a r r a y s h o w i n g n e t w o r k s t r u c t u r e ( b ) R i g h t h a l f o f t h e a r r a y s h o w i n g l e s s e r o r g a n i z e d l i n e s t r u c t u r e O 2.75 2.3 1.85 1.4 ,95 -0 20 40 60 60 D i s t . to nearest p i t (microns) 100 F i g * 4 . 9 P l o t of V T H vs d i s t a n c e to nearest p i t f o r MESFET from sample 283-S11 62 As F i g . 4.8 shows, the d i s l o c a t i o n networks change from the honeycomb-like structures on the left-hand half of the 3rd MESFET array ( F i g . 4.8a) to wavy l i n e s on the r i g h t - h a l f ( F i g . 4.8b). Two histograms of the d i s t r i b u t i o n of V along the 3rd MESFET array i s shown in F i g . 4.10. F i g . 4.10a i s for those MESFET on areas with honeycomb network structures and F i g . 4.10b i s for those on areas with wavy l i n e s . Figure 4.10 indicates that scattering of MESFET V ^ could be dependent upon the d i s l o c a t i o n network i n which the scattering i s more noticeable in areas with honeycomb d i s l o c a t i o n network structures. This r e s u l t has also been observed before by I s h i i et a l . [65]. F i g . 4.11 shows two histograms of the d i s t r i b u t i o n of leakage current along the 3 rd Schottky pad array. The scattering i s again more severe for pads on areas with honeycomb networks than those on areas without the honeycomb networks. Therefore, from the observation above, the d i s l o c a t i o n network may be one of the major causes for device c h a r a c t e r i s t i c s scattering i n undoped LEC-GaAs. A plot of MESFET V ^ versus the l o c a l EPD i s shown i n F i g . 4.12. Local EPD i n t h i s experiment was the amount of etch p i t s located in an area of 200umx200um centered on each MESFET. F i g . 4.13 shows a plot of MESFET I at zero gate bias versus l o c a l EPD. From Figs. 4.12 and 4.13 no dependent of V f c h and I on l o c a l EPD can be observed. To summarize, no d i r e c t c o r r e l a t i o n between device c h a r a c t e r i s t i c s and d i s l o c a t i o n s was found. The scatter of device c h a r a c t e r i s t i c s was more severe in areas of organized c e l l u l a r network structures implying that highly uniform and low d i s l o c a t i o n s (to avoid the formation of c e l l u l a r network structures) GaAs c r y s t a l s are required for future d i r e c t 63 E C UJ 10 0 -1.0 -15 TH -2.0 ( V) -25 ( a ) QJ r --£ uJ E Lu 10 H 5 • °-1.0 -1.5 TH -2D IV) -Z5 (b) F i g . 4 . 1 0 H i s t o g r a m s o f t h e d i s t r i b u t i o n o f V T H f o r FET a l o n g t h e ( a ) L e f t h a l f o f 3 r d a r r a y ( F i g . 4 . 8 ) ( b ) R i g h t h a l f o f 3 r d a r r a y Q J r -- £ L U £ U -D C 0 4 5 6 7 8 9 LEAKAGE CURRENT ( pA ) 10 ( a) 2$ r -E ^ 0 — i — i — i r 6 7 4 5 LEAKAGE CURRENT(pAl (b) F i g . 4 .11 H i s t o g r a m s o f t h e d i s t r i b u t i o n o f l e a k a g e c u r r e n t f o r FET a l o n g t h e ( a ) L e f t h a l f o f 3 r d a r r a y ( b ) R i g h t h a l f o f 3 rd a r r a y 2 . 7 5 10 2 0 3 0 4 0 L o c a l d i s l o c a t i o n d e n s i t y ( . 2 5 E 4 / c m ^ 2 ) 5 0 F i g . 4.12 P l o t o f V T H v s l o c a l d i s l o c a t i o n d e n s i t y f o r . M E S F E T from sample 2 8 3 - S 1 1 450 n 0 10 20 30 40 Local d i s l o c a t i o n density (.25E4/cm~2) F i g . 4.13 P l o t o f I D S ( g V Q S=0 V ) vs l o c a l d i s l o c a t i o n d e n s i t y f o r MESFET from sample 283-S11 67 implantation large scale i n t e g r a t i o n technology. V a r i a t i o n of the MESFET V ^ i n t h i s experiment i s larger than those reported by other authors [63-51]. The scatter of device c h a r a c t e r i s t i c s i n this experiment was probably p a r t l y due to f a b r i c a t i o n process induced inhomogenity. This experiment serves as i n i t i a l run for the study of the e f f e c t s of d i s l o c a t i o n s on device fabricated on undoped SI LEC GaAs using d i r e c t implantation technology at U.B.C. In future studies, the contribution to the scatter from substrate and process induced inhomogenity should be separated and analyzed, and the r e s u l t s obtained i n this experiment can then be used for comparison purposes. 68 CHAPTER 5 BACKGATING IN GaAs MESFET 5.1 Introduction The v a r i a t i o n of MESFET drain current c h a r a c t e r i s t i c s due to a nega-t i v e bias applied to a contact on the back of a substrate or nearby on the front face i s known as backgating [69-73]. In integrated c i r c u i t s , backgat-ing could cause unwanted communication between devices with unpredictable r e s u l t s even though SI substrates were used. This undesirable influence of backgating can be minimized by various means: (1) high r e s i s t i v i t y , therm-a l l y stable s l i c e s should be used so that no surface conversion can take place during high temperature anneal, (2) c r i t i c a l components should be placed far enough away from a negative voltage source so that the FET i s le s s s e n s i t i v e to backgating, and (3) device i s o l a t i o n can be increased by proton bombardment i n s e l e c t i v e areas of SI substrate as proposed by D'Avanzo [79]. However, backgating remains a problem i n the development of GaAs IC. In the f i r s t published work, the backgate bias (V ) was applied to BG electrodes on the back of substrate and changes i n I were observed for samples fabricated on an e p i t a x i a l layer on Cr-doped SI GaAs [74,75]. A space charge region i s present at the e p i t a x i a l layer-SI substrate interface and i t s modulation was believed to be involved i n backgating. This space charge region was shown to be affected by the nature of the trapping l e v e l s i n the i n t e r f a c e [75]. When a negative bias i s applied to the backgating electrode, the space charge region expands by an amount which depends on the concentrations of the trapping l e v e l s . The expansion of the i n t e r f a c e space charge region decreases the active channel and thus cause a decrease i n Recently, backgating has been studied in ion implanted MESFET on SI substrate with the backgating contact on the same side of the wafer as the FET. Kocat and Stolte [70] reported that the electron l e v e l EL2 i s involved i n backgating for undoped SI LEC GaAs while both EL2 and the Cr-related hole trap mentioned i n Ch. 2 are involved for Cr-doped SI GaAs. B i r r i t t e l l a et a l . [76] investigated backgating with the source voltage of a FET biased by a pulse t r a i n . Backgating was found to be more severe for low duty cycle than high duty cycle. In f a c t , for a duty cycle of 1 0 - 3 and an average backgate-source bias of -2.5V, the drain current was reduced by 40 percent while no change was observed at unit duty cycle. Lee et a l . [72] and Miers et a l . [73] have discussed the r e l a t i o n s h i p between backgating and substrate conduction. They propose that for high r e s i s t i v i t y materials, at low backgating voltages, the substrate conduction i s controlled by the thermally generated c a r r i e r s so that an ohmic I-V r e l a t i o n i s expected. When the applied voltage reaches a c r i t i c a l value, the current was found to r i s e sharply and this was believed to be the occurrence of a t r a p - f i l l e d -l i m i t at a voltage V . V i s reached when the injected c a r r i e r s from the TFL TFL backgate f i l l e d up the deep traps i n the substrate [77]. Lee et a l . [72] observed that the V of substrate conduction coincided with the onset Tr L voltage of the backgating e f f e c t (V ). For Miers et a l . [73], with a V BTH uo of 2.5V, good agreement between V,,-,, and V was observed in SI LEC GaAs D i n l r L but not i n Cr-doped HB GaAs. However, at a V of lOOmV, good c o r r e l a t i o n 70 was observed in both LEC and HB materials. According to the two papers above, a V and V of 5V i s generally obtained for a separation of 30pm BTH TFL to 40pm between the sidegate and MESFET. Due to the good c o r r e l a t i o n between V and V observed by Lee et a l . and Miers et a l . , they BTH TFL concluded that c a r r i e r i n j e c t i o n into the substrate i s d i r e c t l y related to the backgating e f f e c t . A more recent paper ( a l s o by the same group as Lee et a l . [72]) by Chang et a l . [78] studied the substrate conduction phenomenon i n more d e t a i l . They believe that the V observed by Lee et TFL a l . [72] and Miers et a l . [73] was much too low to s a t i s f y the requirement of f i l l i n g up a l l the deep l e v e l s i n the SI GaAs between the backgate and the MESFET. Instead, Chang et a l . proposed that the deep l e v e l EL2 outdiffuses during high temperature anneal and leaving behind a thin uncompensated layer (p-type) on the surface between the backgate and the FET. Current conduction between the backgate and the FET then takes place on the surface depletion region of this p layer. 5.2 Experimental Procedures and Results To investigate device i s o l a t i o n and substrate (or surface) conduction in MESFET fabricated on SI<100>LEC GaAs at U.B.C, backgating experiments were performed using a contact nearby on the front face. The devices used i n t h i s experiment were fabricated by Tarr [81] and Lau [82] and were measured for other purposes by Lowe [33]. Two t r a n s i s t o r s are shown i n F i g . 5.1, they are part of a test array that was fabricated on s l i c e 45-S92. The MESFET with the 500pm wide and 20pm long gate was used in this study. The large ohmic pad shown on the l e f t hand side (700pm separation) was used as the F i g . 5.2 MESFET o f sample 123-S131 72 backgating electrode. In F i g . 5.2, the t r a n s i s t o r i n the middle i s an exam-ple of the second structure that was also examined i n t h i s experiment. This type of FET has a 20pm wide and 3 pm long gate and was fabricated on s l i c e 123-S131. An ohmic pad placed 250 pra from the MESFET was used as a backgating electrode. Both structures, samples 45-S92 and 123-S131, were fabricated using d i r e c t ion implantation. The active layer of 45-S92 was activated by annealing at 800°C f o r 20 minutes while 123-S131 was annealed at 850°C, using S i 0 2 cap i n both cases. The complete f a b r i c a t i o n procedure of these devices i s given i n Ref. 33. A block diagram of the experimental set up i s shown in F i g . 5.3. Fi g . 5.4 shows a t y p i c a l I n -V c h a r a c t e r i s t i c s of sample 123-S131 with V. c stepped from 0 to -8V and V__ held at 0V. F i g . 5.5 shows the I -V n p JSG DS DS c h a r a c t e r i s t i c s 'of the same sample with V at 0V and V „ stepped from 0 to GS BG -12V. The r e s u l t from F i g . 5.5 shows that the backgating influence was strong and can even pinch o ff the active channel i f a large enough backgating bias i s present nearby. A plot of I_. -V with V stepped from DS GS BG 0 to -8V i s shown i n F i g . 5.6 and i t shows a clear dependence of V ^ on V . The r e s u l t s from Figs. 5.5 and 5.6 confirm the e f f e c t of V on device BG c h a r a c t e r i s t i c s as reported i n many papers [69-76]. F i g . 5.7 shows the 1 -V c h a r a c t e r i s t i c s for sample 45-S92 with V n_ stepped from 0 to -30V. DS Go BG Comparison of F i g s . 5.6 and 5.7 shows that the magnitude of backgating e f f e c t s i s dependent on the separation between the device and sidegate. V__„ of approximately -5V was found i n reports by Lee et a l . [72], Miers BTH [73] and B i r r i t t e l l a et a l . [76]. The MESFET i n th i s experiment have V-,-,.. Bin « 0V ( F i g s . 5.8 and 5.9). That i s , the onset of backgating occurred with SAMPLE BACKGATE HP A145A SEMICONDUCTOR PARAMETER ANALYZER HP 7475A PLOTTER 1 11—[ • -==. r-1 4-t=i » 1 1 WENTWORTH MULTI-PROBES STATION F i g . 5 . 3 B l o c k - d i a g r a m o f b a c k g a t i n g e x p e r i m e n t a l s e t up V B G = 0 V . J N V D S = 1.25V 00 VO 80 these p a r t i c u l a r samples as soon as there existed a negatively biased contact nearby. One major difference between the f a b r i c a t i o n procedure was that S i 0 2 was used as the encapsulant i n this experiment while Sigt^ was used by the above authors. To investigate current conduction in the SI substrate, the backgating current (I__) was measured as a function of V . Figs. 5.10 and 5.11 show BG BG the I -V__ plots for samples 45-S92 and 123-S131, res p e c t i v e l y . The I BG BG BG rose slowly at low V but when a c e r t a i n threshold voltage (V ) was BG TFL reached a sudden r i s e was observed. The value of VriTr,T obtained i n t h i s TFL experiment was generally greater than -30 V where V of the same samples BTH were approximately OV. The disagreement between V and V implies that BTH TFL the backgating e f f e c t s observed i n t h i s experiment were of d i f f e r e n t o r i g i n than those reported by Lee et a l . [72] and Miers [73] who observed a close c o r r e l a t i o n between V and V . A surface conversion model [78] may TFL BTH explain the observation made i n this experiment. I t has been shown by Makram-Ebeid et a l . [80] that the deep l e v e l EL2 concentration decreased by two orders of magnitude to 10 i l +/cm 3 under the surface after a high temperature anneal and that caused t h i s surface layer to be under-compensated. The o u t d i f f u s i o n of EL2 thus induced a thin p-layer under the surface and therefore created a n +-p-n + junction between the backgate electrode and the ohmic contact of the MESFET. As soon as a negative bias was applied to the backgate, the p-n + junction at the substrate-active channel interface would be reverse biased so the depletion region would widen and i n turn reduced the active layer. For t h i s model, the backgating i s f e l t by the FET immediately a f t e r the a p p l i c a t i o n of a negative bias and 00 to 83 V i s therefore OV. The I at low backgating bias could be the leakage BTH BG current through the n +-p-n + junction. The sudden r i s e i n I could be due BG to the breakdown of the reverse biased p-n + junction or the conduction i n the surface depletion region of the p-layer after injected c a r r i e r s f i l l e d a l l the deep l e v e l s . To summarize: (1) I„„ decreased as V„„ increased and correspondingly the V , of MESFET DS BG th are s e n s i t i v e to a negatively biased contact nearby. (2) V was found to be OV while V was greater than -30V for devices i n BTH TFL t h i s experiment. A good c o r r e l a t i o n between V and V was observed by BTH TFL Lee et a l . [72] and Miers et a l . [73]. This difference i s probably due to the use of S i 0 2 as encapsulant for samples 45-S92 and 123-S131 instead of S I 3 V (3) A surface conversion model was presented in which backgating in t h i s experiment was explained by a p-layer formed a f t e r a high temperature a c t i v a t i o n anneal. 84 CHAPTER 6 CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK In conclusion, the following observations can be made: (1) The DLTS experimental set up was improved during the course of t h i s work. Using t h i s experiment, three electron traps were detected i n a l l four s l i c e s from four d i f f e r e n t SI GaAs ingots. This suggests that these traps are c h a r a c t e r i s t i c s of GaAs from Cominco. The a c t i v a t i o n energies of these l e v e l s were found to be 0.80, 0.72 and 0.52 eV. These l e v e l s were associated with, as c l a s s i f i e d by Martin et a l [17], EL2, ELI2, and EL4, r e s p e c t i v e l y . A negative peak corresponding to a trap with an electron a c t i v a t i o n energy of 0.65 eV was detected i n the t h i n sample 86-T. A negative peak with s i m i l a r a c t i v a t i o n energy was observed by O l i v e r et a l . [30] and Fairman et a l . [32]. This l e v e l i s believed by these authors to be responsible, together with EL2, for compensating shallow acceptors i n undoped SI LEC GaAs. Thermally stable s l i c e s obtained from Cominco were shown to have higher peak height r a t i o of PI (0.80eV) to P2 (0.72 eV) than thermally unstable s l i c e s . For future work, the photocurrent-DLTS measurement should be extended to study process induced traps. For example, ion implantation induced traps and stress induced traps. (2) In the i n v e s t i g a t i o n of d i s l o c a t i o n s and device c h a r a c t e r i s t i c s , the scatter of the threshold voltage V ^ was found to be higher on areas of c e l l u l a r d i s l o c a t i o n networks than on areas with just wavy l i n e s of d i s l o c a t i o n s . V a r i a t i o n of device c h a r a c t e r i s t i c s was p a r t l y due to process induced inhomogenity and no c o r r e l a t i o n between device c h a r a c t e r i s t i c s and 85 d i s l o c a t i o n s was established. In future study of the e f f e c t of d i s l o c a t i o n s , a whole wafer should be used so that the macroscopic v a r i a t i o n can be examined along with the microscopic v a r i a t i o n . The experiment should also be designed to eliminate as far as possible the inhomogenity contributed from the f a b r i c a t i o n process. (3) In the backgating experiment, the e f f e c t of nearby contacts on I of MESFET were examined. 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Young, Second Annual report for B r i t i s h Columbia Science Council Grant #51 (RC-5 ) , 4 (1983). .0 93 Appendix - Some deep l e v e l s i n SI GaAs reported in the l i t e r a t u r e (a detected by photocurrent-DLTS) Author E T[eV] Capture Assoc i a t i o n Material Cross with trap Section c l a s s i f i e d a [ cm2] by [3,4] Martin et a l . 0.9 2 . 2 X 1 0 - 1 4 HL1 Cr-doped Bridgman GaAs [23] 0.74 6 . 3 x l 0 _ i 5 EL2 Cr-doped Bridgman GaAs 0.57 5 . 4 x l 0 - i 3 EL 3 Cr-doped Bridgman GaAs 0.35 5. 5 x l O - 1 5 EL 5 Cr-doped Bridgman GaAs 0.34 2 . 7 x l 0 - 1 4 EL 6 Cr-doped Bridgman GaAs 0.27 2.05xl0- i l + HL12 Cr-doped Bridgman GaAs Fairman et a l . 0.9 2xl0" i l t HL1 A l l * [22,24,32] 0.83 2 x l 0 _ i 3 HL10 Cr-doped LEC GaAs 0.65(N)** l x l 0 - i 3 A l l * 0.60 1x10" 1 2 EL3 Cr-doped LEC GaAs 0.51(N)** 1x10"-i 2 EL4 Cr-doped Bridgman GaAs 0.34 4xl 0 - 1 1 + EL 6 A l l * 0.34 6 x l 0 ~ 1 3 VPE layer on Cr-doped GaAs 0.30 7 X 1 0 - 1 1 * HL12 Cr-doped LEC & Bridgman GaAs 0.26 2x l 0 " * 2 Cr-doped Bridgman GaAs 0.15 Cr-doped LEC GaAs 0.14 l x l 0 - i 6 VPE layer on Cr-doped GaAs * Cr-doped LEC & Bridgman GaAs and VPE layer on Cr-doped GaAs ** Negative Peak as discussed i n section 3.4 Deveaud et a l . 0.87 2 x l 0 - 1 5 HL1 Cr-doped Bridgman GaAs [25] 0.5 3 x l 0 " i 9 Cr-doped Bridgman GaAs Ito h et a l • 0.98 1.3xl0~ 1 3 HL1 n"-VPE layer with buffer [26] layer on Cr-doped GaAs 0.89 1.8xl0" 1 1 + HL1 ri"-VPE layer on Cr-doped GaAs 0.75 2.7xl0 - x l + EL2 n"-VPE layer on Cr-doped GaAs 0.62 1.5xl0 - 1 ,» HL3 ri"-VPE layer with buffer 8.6xl0~ 1 3 layer on Cr-doped GaAs 0.60 EL3 ri"-VPE layer with and without buffer layer on Cr-doped GaAs 0.42 Not Given n --VPE layer on Cr-doped GaAs 0.41 1.4xl0"15 HL4 n~-VPE layer with buffer layer on CT-doped GaAs 94 Author E T[eV] Capture Cross Section o [ cm2] Association with trap c l a s s i f i e d by [3,4] Material Rhee et a l . 0.90 2 . 1 x l 0 - 1 2 Cr-doped GaAs [27] 0.85 1 . 3 x l 0 - 1 3 HLI Cr-doped GaAs 0.73 1.3xl0~ i 7 Cr-doped GaAs 0.17 3 . 9 x l 0 - 2 2 Cr-doped GaAs Yuba et a l . 0.88 5.5xl0~ 1 3 ELI Cr-doped Bridgman before and [28] a f t e r S i implantation 0.86 1 . 2 x l 0 - i l HL3 Cr-doped Bridgman af t e r SI 1 . 2 x l 0 - 1 3 implantation 0.54 EL 3 Cr-doped Bridgman before and af t e r S i implantation 0.48 5.8xl0 - i l + HL4 Cr-doped Bridgman before and 9.2xl0~ i 3 a f t e r S i implantation 0.34 EL6 Cr-doped Bridgman before and a f t e r S i implantation O l i v e r et a l . 0.83 Not Given HL10 undoped LEC GaAs grown with [30] dry B263 0.65(N) Not Given undoped LEC GaAs grown with wet B 20 3 0.57 Not Given undoped LEC GaAs 0.34 Not Given undoped LEC GaAs 0.28 Not Given undoped LEC GaAs 0.15 Not Given undoped LEC GaAs Hurtes et a l . 0.90 Not Given HLI high r e s i s t i v i t y VPE layer on [21,31] Cr-doped Bridgman 0.81 Not Given EL 2 n-VPE layer with high r e s i s t i v i t y buffer layer on Cr-doped Bridgman 0.56 Not Given HL8 high r e s i s t i v i t y VPE buffer layer on Cr-doped Bridgman 0.54 Not Given EL 3 n-VPE layer with high r e s i s t i v i t y buffer layer on Cr-doped Bridgman 0.41 Not Given HL4 n-VPE layer with high r e s i s t i v i t y buffer layer on Cr-doped Bridgman 0.32 Not Given EL 6 Both type of samples 95 Author E T[eV] Capture Cross Section a [ cm2] Association with trap c l a s s i f i e d by [3,4] Material K. Lowe [3] 0.87 2. 5 x l 0 - 9 ELI 2 undoped LEC GaAs 0.59 5 x l 0 - i l EL4 undoped LEC GaAs 0.50 1.6xl0 - l l f EL 3 undoped LEC GaAs 0.38 3.2xl0 _ i l + HL6 undoped LEC GaAs 0.32 2 . 5 x l O _ i 3 EL 8 undoped LEC GaAs 

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