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A compact, flexible controller for PWM inverters Mauch, Konrad 1984

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A COMPACT, FLEXIBLE CONTROLLER FOR PWM INVERTERS By KONRAD MAUCH B.A.Sc, The University of B r i t i s h Columbia, 1977 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE i n THE FACULTY OF GRADUATE STUDIES Department of E l e c t r i c a l Engineering We accept t h i s thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA May 1984 ©K o n r a d Mauch, 1984 In p r e s e n t i n g t h i s t h e s i s i n p a r t i a l f u l f i l m e n t o f the requirements f o r an advanced degree at the U n i v e r s i t y o f B r i t i s h Columbia, I agree t h a t the L i b r a r y s h a l l make i t f r e e l y a v a i l a b l e f o r r e f e r e n c e and study. I f u r t h e r agree t h a t p e r m i s s i o n f o r e x t e n s i v e copying o f t h i s t h e s i s f o r s c h o l a r l y purposes may be granted by the head o f my department o r by h i s or her r e p r e s e n t a t i v e s . I t i s understood t h a t copying or p u b l i c a t i o n of t h i s t h e s i s f o r f i n a n c i a l g a i n s h a l l not be allowed without my w r i t t e n p e r m i s s i o n . Department o f E l e c t r i c a l Engineering The U n i v e r s i t y o f B r i t i s h Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date May 24. 1984 DE-6 (3/81) ABSTRACT A f l e x i b l e , low cost inve r t e r c o n t r o l l e r for use i n variable speed AC motor drives has been designed. O r i g i n a l l y designed f o r use i n a submersible thruster drive, the c o n t r o l l e r has been found to have po t e n t i a l for use i n other drives as we l l . Low cost and small s i z e are made possible by the use of large scale integrated c i r c u i t s . F l e x i b i l i t y i n a vari e t y of motor drive applications i s achieved by using a microcomputer as the heart of the c o n t r o l l e r . In comparison to other c o n t r o l l e r s f o r PWM in v e r t e r s , this c o n t r o l l e r has the following d i s t i n c t i v e features: i ) The c o n t r o l l e r can operate the inv e r t e r to output frequencies of 400 Hz or more as opposed to maximum frequency l i m i t s of 120 Hz to 200 Hz for other c o n t r o l l e r s . i i ) The c o n t r o l l e r i s programmed i n the C high l e v e l programming language instead of the assembly language used i n other microcomputer based c o n t r o l l e r s . This allows the c o n t r o l l e r to be adapted more r a p i d l y to new ap p l i c a t i o n s , i i i ) The c o n t r o l l e r i s smaller and has a lower component count than most other c o n t r o l l e r s . As a r e s u l t the c o n t r o l l e r should be more r e l i a b l e , easier to package, and less expensive. i i After a review of AC drive technology, the objectives and the basic a l t e r n a t i v e s i n the design of the c o n t r o l l e r are presented. The c i r c u i t design and software design of the c o n t r o l l e r are discussed. Two applications of the i n v e r t e r c o n t r o l l e r are presented and the success of the design i n these two applications i s evaluated. Conclusions are presented on the o v e r a l l success of the design and suggestions are made for improvements and further work. i i i Table of Contents Abstract i i L i s t of Figures v i Acknowledgements v i i i Chapter 1 Introduction 1 1.1 Motivation for Thesis Project 3 1.2 Scope and Objectives of Thesis Project 4 1.3 Outline of Thesis 6 1.4 Summary 8 Chapter 2 Review of Variable Frequency AC Drive Technology 10 2.1 C l a s s i f i c a t i o n of Inverter Drives 10 2.2 Inverter Power Switching Devices 15 2.3 Variable Frequency Operation of Induction Motors 18 2.4 Control of the Inverter Waveform 31 Chapter 3 Inverter C o n t r o l l e r Design Considerations 46 3.1 Basic System Requirements 49 3.2 Requirements f o r Other Applications 53 3.3 C o n t r o l l e r Functions 57 3.4 Inverter C o n t r o l l e r Design Alternatives 62 3.5 Torque and Speed Control 63 3.6 System Protection 65 3.7 Pulse Width Modulation 68 3.8 Basic C o n t r o l l e r Architecture 84 Chapter 4 C o n t r o l l e r Hardware Design 87 4.1 Microcomputer C i r c u i t 88 4.2 Interface to HEF4752V PWM Generator IC 96 i v 4.3 Remainder of Controller C i r c u i t 112 4.4 Inverter C o n t r o l l e r C i r c u i t Board 114 Chapter 5 Inverter C o n t r o l l e r Software Design 118 5.1 Software Development System 119 5.2 Description of Controller Software 121 5.3 Software Implementation 130 5.4 Evaluation of Software Development Using the C Language 134 Chapter 6 Applications of the Inverter C o n t r o l l e r 140 6.1 Submersible Thruster Drive 141 6.2 Linear Induction Motor Drive 145 6.3 LIM Drive Protective Functions 148 6.4 LIM Drive Control Panel Functions 150 6.5 Evaluation of LIM Drive 151 6.6 Conclusion 154 Chapter 7 Conclusion 155 References 160 Appendix 167 v L i s t of Figures 1. Block Diagram of Typical AC Drive System 2 2. Inverter Controller 8 3. Basic Inverter Bridge C i r c u i t 11 4. Inverter Switching Sequence 11 5. Basic Inverter Types 12 6. PWM Inverter Output Voltage Waveform 14 7. Induction Machine Torque-Speed Curve 19 8. Torque-Speed Curves at Different Stator Frequencies 19 9. Standard Equivalent C i r c u i t f o r the Induction Machine 20 10. Torque Envelope for Constant Volts/Hz Operation 22 11. Torque-Speed Curve Showing P u l l Out 25 12. Torque-Speed Curves f o r Current and Voltage Source Operation 27 13. Machine Equivalent C i r c u i t f o r Harmonics 34 14. Triangle Intercept Pulse Width Modulation 39 15. PWM Waveform Having Quarter and Half Wave Symmetry 43 16. I.S.E. Submersibles 48 17. Control Loop for Controlled S l i p Drive 59 18. Software Intensive PWM Waveform Generator 69 19. Counter/Timer Based PWM Waveform Generator 70 20. Programmable Counter/Timer Output Waveforms 71 21. Memory Intensive PWM Waveform Generator 74 22. Prototype PWM Waveform Generator - Part 1 77 23. Prototype PWM Waveform Generator - Part 2 78 v i 24. Inverter C o n t r o l l e r Architecture 85 25. Microcomputer Section of Inverter Controller 93 26. P h i l i p s HEF4752V Inputs and Outputs 97 27. D i g i t a l l y Controlled Frequency Synthesizer 104 28. Programmable Frequency Synthesizer 107 29. General Block Diagram of Am9513 Counter/Timer IC 108 30. Remainder of Inverter C o n t r o l l e r C i r c u i t 113 31. Memory and I/O Map for Inverter C o n t r o l l e r 115 32. Inverter C o n t r o l l e r C i r c u i t Board Layout 116 33. State T r a n s i t i o n Diagram 123 34. Errors i n Control Flow 124 35. F i n i t e State Machine Model of Inverter C o n t r o l l e r 126 36. Submersible Thruster Drive 142 37. Motor Line Current 144 38. S i m p l i f i e d Schematic of LIM Inverter 147 v i i Acknowledgements I wish to thank Dr. M.R. Ito for h i s advice and comments on t h i s t h e s i s . Thanks are also due to Dr. L.M. Wedepohl f o r h i s supervision of the B.C. Science Council grants under which much of the work described i n th i s thesis was performed. My colleague Frank Peabody made many useful suggestions and was a great help i n the construction and testing of the inverter c o n t r o l l e r . My work on t h i s project has received f i n a n c i a l support from the Transportation Development Agency, the National Science and Engineering Research Council, and the B.C. Science Council. v i i i Chapter 1 Introduction Variable speed drives using AC induction motors are find i n g increasing use i n a va r i e t y of ap p l i c a t i o n s . The increased cost of energy and the move to increased automation has led to the i n s t a l l a t i o n of variable speed AC drives i n systems which previously used f i x e d speed motors and mechanical means of c o n t r o l l i n g output. At the same time the decline i n the cost of the e l e c t r o n i c s i n AC drives has made them competitive with DC drives i n many of the applications where var i a b l e speed motors have t r a d i t i o n a l l y been used. AC drives have several advantages over DC dri v e s . An AC induction motor i s t y p i c a l l y smaller, l i g h t e r , and cheaper than a DC motor of the same power r a t i n g . The maximum speed of an AC induction motor i s not l i m i t e d by the commutation problems experienced by a DC motor. It i s therefore possible to design high speed AC induction motors that have a very high power to weight r a t i o . The absence of a commutator and brushes reduces the maintenance required f o r an AC drive and allows i t to be used i n environments where a DC drive can't be used. While AC var i a b l e speed drives based on stator voltage c o n t r o l , s l i p energy recovery, or cycloconverters are a v a i l a b l e [1], the majority of AC drives are based on variable frequency operation 1 with a three phase i n v e r t e r . The three phase invert e r accepts standard f i x e d frequency, f i x e d voltage power from the u t i l i t y l i n e and converts i t to variable frequency, variable voltage power which i s fed to the AC motor. INVERTER CONTROL SECTION Figure 1 Block Diagram of Typical AC Drive System An Inverter system can be divided into two sections, a power processing section and a control section, as shown i n Figure 1. A t y p i c a l power processing section consists of an input r e c t i f i e r that converts the input power to DC on an i n t e r n a l bus and a set of power switching devices that switch the DC bus on to the three output l i n e s of the i n v e r t e r . The switching devices have usually been s i l i c o n c o n t r o l l e d r e c t i f i e r s (SCRs) but power t r a n s i s t o r s and power MOSFETs are incr e a s i n g l y used. The con t r o l section controls the opening and c l o s i n g of the e l e c t r o n i c switches i n 2 order to produce the appropriate AC waveforms on the output l i n e s . In a d d i t i o n , i t performs necessary sequencing and supervisory functions and accepts control inputs from the system control panel. The c o n t r o l l e r section has been based on a mix of analog and medium scale d i g i t a l integrated c i r c u i t s . However, microcomputers are now being used i n some invert e r c o n t r o l l e r s . 1.1 Motivation for Thesis Project Inverters for AC drives are normally packaged and sold for use i n standard i n d u s t r i a l environments with standard s q u i r r e l cage induction motors. Specialized applications requiring unusual packaging or unusual output voltages and frequencies i n most cases require an i n v e r t e r system that i s custom designed. For example, International Submarine Engineering of Port Moody, B.C. had a need for AC drives to power the thrusters on unmanned submersibles produced by the company. Suitable drives were not commercially a v a i l a b l e . As a r e s u l t , the Science Council of B.C. funded the development of a s u i t a b l e drive by the Department of E l e c t r i c a l Engineering at UBC [2,3]. The drive had to be packaged to withstand submersion to depths of up to 1000 meters and yet i t also had to be compact since four drives were required on a r e l a t i v e l y small submersible. The inv e r t e r was required to supply frequencies of up to 400 Hz so that compact, high speed thruster motors could be used. F i n a l l y , the i n v e r t e r c o n t r o l l e r had to be f l e x i b l e enough to accomodate 3 changes i n the control strategy due to possible changes i n ei t h e r the power conversion section design or the submersible control system design. 1.2 Scope and Objectives of Thesis Project This thesis discusses the design of the inverter c o n t r o l l e r for the submersible thruster drive developed at UBC. The design requirements for t h i s c o n t r o l l e r (small s i z e , wide frequency range, f l e x i b i l i t y i n control strategy) were such that i t could serve as the basis for an inver t e r c o n t r o l l e r applicable to a va r i e t y of future a p p l i c a t i o n s . Therefore, one of the primary objectives of the design was to allow the maximum amount of f l e x i b i l i t y i n a p p l i c a t i o n wherever t h i s did not c o n f l i c t with the other objectives that the c o n t r o l l e r be compact and that i t be p r a c t i c a l to manufacture i n terms of cost and a v a i l a b i l i t y of components. The basic design objectives set f o r the inver t e r c o n t r o l l e r were the following: The c o n t r o l l e r should i . c o ntrol pulse-width modulated inverters using t r a n s i s t o r s , power MOSFETs, or t h y r i s t o r s as switches; 4 i i . operate over an inve r t e r frequency range of 3 Hz to 400 Hz; i i i . perform as many functions as possible by means of computer software written i n a hi g h - l e v e l programming language; i v . handle common open-loop and closed-loop motor control s t r a t e g i e s ; v. occupy l e s s than 200 cm of printed c i r c u i t board; v i . cost less than $200 i n parts and d i r e c t labor. The inve r t e r c o n t r o l l e r designed to meet the above objectives has several advantages over i n v e r t e r c o n t r o l l e r s described i n the l i t e r a t u r e or incorporated i n commercially a v a i l a b l e AC drives. Very few c o n t r o l l e r s for pulse width modulated inverters that have been described i n the l i t e r a t u r e operate above an output frequency of 250 Hz. There do not appear to be any commercially av a i l a b l e pulse width modulated inverters that operate above 250 Hz. Yet the advent of f a s t power t r a n s i s t o r s and power MOSFETs allows the design of p r a c t i c a l pulse width modulated inverters operating to 400 Hz and beyond. Operation at these high frequencies has advantages i n many ap p l i c a t i o n s . Many in v e r t e r c o n t r o l l e r designs presented i n the l i t e r a t u r e are 5 based on microcomputers and claim to have considerable f l e x i b i l i t y i n a p p l i c a t i o n . However, a l l of them appear to be programmed i n assembly language, which s u b s t a n t i a l l y increases the cost of software development for a new a p p l i c a t i o n . In addition, many seem to have been designed only f o r laboratory use and are unsuitable for i n d u s t r i a l use i n terms of cost, complexity, and s i z e . Controllers i n commercially a v a i l a b l e units meet the cost and s i z e constraints imposed by the market but lack the kind of f l e x i b i l i t y that would allow them to be e a s i l y reconfigured for a new a p p l i c a t i o n . The c o n t r o l l e r design r e s u l t i n g from the objectives l i s t e d above, takes a middle path. It retains the f l e x i b i l i t y of having functions performed by microcomputer software, and adds the advantages of high l e v e l language programming. But, by judicious p a r t i t i o n i n g of functions between hardware and software, and by using the minimum number of components, i t manages to meet the cost and s i z e requirements for a p r a c t i c a l system. 1.3 Outline of Thesis In order to set the design of the i n v e r t e r c o n t r o l l e r i n context, and to explain some of the s p e c i a l i z e d vocabulary and concepts, Chapter 2 i s devoted to a review of AC drive technology. The three main types of inverters are b r i e f l y described and the c h a r a c t e r i s t i c s of the semiconductor power switches used i n inverters are discussed. Then operation of AC induction motors from a v a r i a b l e frequency source i s discussed to provide some 6 i n s i g h t into the control aspects of AC drives. F i n a l l y , the e f f e c t s of the non-sinusoidal i n v e r t e r waveforms on motor operation are discussed along with techniques f o r reducing these e f f e c t s . A det a i l e d discussion of the design requirements f o r the inver t e r c o n t r o l l e r and the possible design tradeoffs i s presented i n Chapter 3. This i s followed by consideration of the a l t e r n a t i v e methods of implementing the c o n t r o l l e r functions and by presentation of the basic architecture of the c o n t r o l l e r . Chapter 4 describes the c i r c u i t design of the inverter c o n t r o l l e r i n d e t a i l . Chapter 5 discusses the software design of the c o n t r o l l e r and presents an evaluation of the success of high l e v e l language programming i n t h i s a p p l i c a t i o n . Two applications of the i n v e r t e r c o n t r o l l e r are described i n Chapter 6. The f i r s t a p p l i c a t i o n i s the submersible thruster drive which was the o r i g i n a l motivation for the development of the c o n t r o l l e r . The second a p p l i c a t i o n i s a drive f o r an experimental l i n e a r induction motor. The success of the i n v e r t e r c o n t r o l l e r i n these two applications i s evaluated. Chapter 7 ends the thesis and supplies some conclusions on the success of the in v e r t e r c o n t r o l l e r design. Some suggestions for improvements i n the design and for future work with the invert e r c o n t r o l l e r are also presented. 7 Figure 2 Inve r t e r C o n t r o l l e r 1.4 Summary The end product of t h i s t h e s i s project i s shown i n Figure 2. The i n v e r t e r c o n t r o l l e r i s housed on a s i n g l e p r i n t e d c i r c u i t board approximately 7.5 cm by 21.5 cm. The small s i z e i s made p o s s i b l e by the use of l a r g e s c a l e i n t e g r a t e d c i r c u i t s . F l e x i b i l i t y i n a v a r i e t y of a p p l i c a t i o n s i s achieved by using a microcomputer as the heart of the c o n t r o l l e r . The c o n t r o l l e r can be adapted to a new a p p l i c a t i o n simply by changing the microcomputer's program. The program i s w r i t t e n i n the C programming language which s u b s t a n t i a l l y reduces the program development time and s u b s t a n t i a l l y i n c r e a s e s the a b i l i t y to modify and maintain the program when compared to w r i t i n g programs i n assembly language. 8 The i n v e r t e r c o n t r o l l e r meets or exceeds i t s o r i g i n a l design objectives. In comparison to other inverter c o n t r o l l e r s that have been described, t h i s c o n t r o l l e r i s unique i n i t s combination of good performance and broad range of a p p l i c a t i o n with low cost and small s i z e . In addition i t i s the one of the few pulse width modulated i n v e r t e r c o n t r o l l e r s that operates beyond 250 Hz. This makes i t useful i n applications where high frequency motors or transformers are used to reduce si z e and weight. This c o n t r o l l e r has been used i n the prototype submersible drive and i n an i n v e r t e r for a l i n e a r induction motor drive. It i s probable that both of these applications w i l l end up i n production. Further applications of the c o n t r o l l e r are being planned. 9 Chapter 2 Review of Variable Frequency AC Drive Technology Variable frequency AC motor drives were made p r a c t i c a l by the invention of the s i l i c o n c o n t r o l l e d r e c t i f i e r ( t h y r i s t o r ) i n the l a t e 1950's. Since that time, AC drive technology has progressed s i g n i f i c a n t l y . The design of the inve r t e r c o n t r o l l e r i s based on these developments i n AC drive technology. This chapter presents a review of some aspects of t h i s technology i n order to provide some context f o r the design of the inve r t e r c o n t r o l l e r and to introduce concepts and terminology which w i l l be used i n l a t e r chapters. 2.1 C l a s s i f i c a t i o n of Inverter Drives The basic three phase in v e r t e r bridge c i r c u i t i s shown i n Figure 3. A set of symmetrical three phase waveforms can be generated by operating the switches i n the sequence shown i n Figure 4. By varying the switching rate, the output frequency of the i n v e r t e r can be v a r i e d . In motor drive applications the output voltage of the i n v e r t e r must also be varied. The method used to vary the output voltage provides a convenient means for c l a s s i f y i n g the d i f f e r e n t types of inve r t e r motor drives. In the Variable Voltage Input Inverter (Figure 5-1), the voltage 10 • o S1 S2 S3 F i g u r e 3 B a s i c I n v e r t e r Bridge C i r c u i t DC V s< V S5 V S6 THREE PHASE INVERTER Switches Conducting F i g u r e 4 I n v e r t e r S w i t c h i n g Sequence 1 1 DC' 30 AC-DC-3 0 AC' Chopper Phase Controlled Rectifier Variable Voltage DC Bus Inverter Varjable Voltage Variable Frequency Square Waves 1) VARIABLE VOLTAGE INPUT INVERTER Chopper Phase Controlled Rectifier —Variable Current 2 ) CURRENT SOURCE INVERTER Variable Current Variable Frequency Square Waves DC-3 0 AC- Rectifier JL Fixed Voltage DC Bus PWM Inverter 3) PULSE WIDTH MODULATED INVERTER Variable Voltage Variable Frequency Pulse Width Modulated Waveforms F i g u r e 5 B a s i c I n v e r t e r T y p e s 12 on the DC bus feeding the inver t e r bridge i s varied i n order to vary the output voltage. Depending on the nature of the power source, the voltage c o n t r o l can be performed by a phase co n t r o l l e d r e c t i f i e r or by a chopper. Since the output of the inver t e r consists of vari a b l e amplitude square waves with a six-step pattern, t h i s type of i n v e r t e r i s also c a l l e d a "s i x - s t e p " or "square wave" i n v e r t e r . The Current Source Inverter (Figure 5-2) d i f f e r s from the Variable Voltage Input Inverter i n that the DC bus i s designed to act as a current source rather than a voltage source. The phase co n t r o l l e d r e c t i f i e r or chopper at the input regulates the bus current rather than the bus voltage. The output of the inver t e r consists of square waves of current rather than square waves of voltage. The Current Source Inverter i s a t t r a c t i v e when the inverter uses t h y r i s t o r s as switching elements since the commutation c i r c u i t s are simple and r e l a t i v e l y slow t h y r i s t o r s can be used [4]. Also the Current Source Inverter allows regeneration of energy back to the AC l i n e with no extra c i r c u i t r y . When the machine i s acting as a generator, the inverte r switching sequence with respect to the machine terminal voltage i s adjusted so that the voltage on the DC bus i s reversed. The f i r i n g angle of the phase controlled r e c t i f i e r i s then retarded so that power flows from the DC bus back into the AC source i n the same fashion as a four quadrant DC d r i v e . The Current Source drive i s not normally used with t r a n s i s t o r 13 or power MOSFET based inverters since commutation and device switching speed do not pose any problems. Time Figure 6 PWM Inverter Output Voltage Waveform The Pulse Width Modulated (PWM) Inverter (Figure 5-3) operates from a fi x e d voltage DC bus. The output voltage i s controlled by turning the switches on and off many times within a hal f cycle of the output wave as shown i n Figure 6. By varying the r a t i o of on time to off time, the output voltage can be varied. This v a r i a t i o n i n the duty cycle can also be used to con t r o l the harmonic content of the output waveform. The PWM in v e r t e r has the advantages that i t has a very simple input power conversion section, i f any i s required at a l l , and i t can change voltage r a p i d l y since the time constant of the DC bus f i l t e r does not 14 a f f e c t the speed of response. A PWM i n v e r t e r presents a high power fa c t o r to the AC power source since a phase c o n t r o l l e d r e c t i f i e r i s not required at the input. The PWM i n v e r t e r does require f a s t switches which exhibit low switching losses and therefore i s better suited to use with t r a n s i s t o r s and power MOSFETs than with SCRs. The design of the c o n t r o l l e r i s strongly influenced by the type of d r i v e . In the Variable Input Voltage and Current Source inv e r t e r s , the i n v e r t e r switching sequence i s simple and can be c o n t r o l l e d by something as simple as an up/down counter driven by a variable frequency clock. The input power converters to these drives must be c o n t r o l l e d i n order to produce the desired DC bus voltage or current. The PWM i n v e r t e r has a much more complex invert e r switching pattern and therefore requires a more complex c o n t r o l l e r but a separate c o n t r o l l e r for the input power converter i s not required. 2.2 Inverter Power Switching Devices The power switches used i n inverters intended for motor drives are s o l i d state semiconductor devices. In the past, the t h y r i s t o r has been the most commonly used switching device and i t i s s t i l l used extensively i n higher power drives. The t h y r i s t o r can be switched on by a low power pulse into i t s gate terminal but i t can only be turned off by interrupting the current flow through i t for a c e r t a i n period. In induction machine drives, 1 5 this i n t e r r u p t i o n of current flow, c a l l e d commutation, does not occur n a t u r a l l y as i t does i n phase co n t r o l l e d r e c t i f i e r s . As a r e s u l t , the i n v e r t e r c i r c u i t must include some means to force the current flowing through the t h y r i s t o r to zero so that the t h y r i s t o r commutates. These forced commutation c i r c u i t s add considerably to the complexity of t h y r i s t o r based i n v e r t e r s . In a d d i t i o n , the period of time required f o r the complete commutation can be as long as 100 microseconds which places l i m i t a t i o n s on the maximum switching frequency of the i n v e r t e r . A normal t h y r i s t o r blocks voltage i n both di r e c t i o n s when i t i s o f f . However most i n v e r t e r c i r c u i t s require voltage blocking i n only one d i r e c t i o n . Assymetrical t h y r i s t o r s and reverse conducting t h y r i s t o r s have been designed which have l i t t l e or no voltage blocking c a p a b i l i t y i n one d i r e c t i o n . As a r e s u l t , other parameters, p a r t i c u l a r l y the time required to commutate the device, can be improved. Inverters using these newer devices are beginning to appear on the market. Another v a r i a t i o n on the standard t h y r i s t o r i s the gate turn off t h y r i s t o r . This device can be turned off by applying a large reverse gate current. This s i m p l i f i e s the design of the i n v e r t e r somewhat and eliminates bulky forced commutation components. Again, in v e r t e r s using gate turn off t h y r i s t o r s as switches are appearing on the market. In low to medium power a p p l i c a t i o n s , the b i p o l a r power t r a n s i s t o r 16 i s begining to supplant the t h y r i s t o r as the inverter power switch. Transistors which can block 1000 v o l t s and conduct 300 amperes are now a v a i l a b l e so t r a n s i s t o r i z e d drives with ratings up to 150 kilowatts can be manufactured without the need to p a r a l l e l devices. The switching of the t r a n s i s t o r i s completely c o n t r o l l e d by the current applied to the base, therefore no external commutation c i r c u i t s are required. Transistors switch more quickly than t h y r i s t o r s so they are better suited to inverters which have high switching frequencies. At power l e v e l s below 5 kilowatts, power MOSFETs are sometimes used as the power switching devices. These devices are very easy to c o n t r o l , requiring very l i t t l e gate power. They also have very high switching speeds which makes them sui t a b l e f o r use i n high frequency i n v e r t e r s . Power MOSFETs are s t i l l r e l a t i v e l y expensive so t h e i r a p p l i c a t i o n i n motor drives i s presently l i m i t e d to experimental systems and to s p e c i a l purpose systems which require t h e i r s p e c i a l c h a r a c t e r i s t i c s . The design of the i n v e r t e r c o n t r o l l e r must take into account the type of power switching devices used. A c o n t r o l l e r for an \ i n v e r t e r using t h y r i s t o r s must properly sequence the f i r i n g of the main t h y r i s t o r s and the t h y r i s t o r s i n the forced commutation c i r c u i t i n order to ensure proper commutation of the t h y r i s t o r s . Inverters based on power t r a n s i s t o r s are easier to control but the c o n t r o l l e r must allow f o r the switching time of the 17 t r a n s i s t o r s . In large power tr a n s i s t o r s there can be as much as 20 microseconds between the time that base current i s removed from the device and the time that c o l l e c t o r current f a l l s to zero. If a t r a n s i s t o r i n one leg of an i n v e r t e r i s turned on before the other t r a n s i s t o r i n the same leg i s completely o f f , a short c i r c u i t w i l l occur across the DC bus and p o t e n t i a l l y damaging "shoot through" currents w i l l flow through the two t r a n s i s t o r s . Power MOSFETs are the easiest of the three types of devices to control since they require very l i t t l e drive power and switch extremely f a s t . The c o n t r o l l e r can treat them pretty much as i d e a l switches. 2.3 Variable Frequency Operation of Induction Motors The three phase induction motor operating from a f i x e d frequency voltage source has the f a m i l i a r torque-speed curve shown i n Figure 7. If the source frequency i s varied and the motor airgap fl u x i s kept constant, the torque-speed curve remains the same except that i t i s translated to the l e f t or r i g h t . I f torque/speed curves are plotted f or a range of frequencies, a family of curves as shown i n Figure 8 r e s u l t s . These curves show that v a r i a b l e speed operation i s possible with the induction machine r e t a i n i n g b a s i c a l l y the same properties that i t has when i t i s running with low s l i p at 50 or 60 Hz. 18 F i g u r e 7 I n d u c t i o n M a c h i n e T o r q u e - S p e e d C u r v e + Torque Reverse Regenerat ion -Speed-Reve rse Motor ing Forward Motor ing +Speed vvvvvvv F o r w a r d Regenera t ion Torque F i g u r e 8 T o r q u e - S p e e d C u r v e s a t D i f f e r e n t S t a t o r F r e q u e n c i e s 1 9 Rs Ls —nmn. t Rc Vim Ilm,r Figure 9 Standard Equivalent C i r c u i t f o r the Induction Machine In f a c t , the torque produced by the i n d u c t i o n machine does not fundamentally depend on the s t a t o r frequency ( w e ) . The torque equation f o r the i n d u c t i o n machine operating from a voltage source can be developed from the standard equivalent c i r c u i t f o r the i n d u c t i o n machine (Figure 9 ) : (1) Rotor input power = I r 2 R r / s (2) Electromagnetic torque = Te = Rotor input power/w e [5] (3) I r 2 = V L m 2 ( ( w e L r ) 2 + ( R r / s ) 2 ) <4> l V L m l = w e I m I i n (5) Airgap Flux = 0 = ImLm 20 <6> s = w s l i p / w e (7) Te = 02Rr/w s l i p  ( L r 2 + ( R r / W s l i p ) 2 ) When wg^^p i s small (the normal operating condition), R r / W s i i p » L r and the machine torque can be approximated as: (8) Te = 0 2w s l i p/Rr Thus the torque depends on s l i p frequency and airgap flux but not on the stator frequency. Control schemes f o r induction motor drives attempt to control the machine airgap f l u x or the s l i p frequency i n order to con t r o l torque. Most drives used i n i n d u s t r i a l applications use a simple open loop control strategy c a l l e d constant volts/Hz c o n t r o l . If the stator impedance i s ignored, airgap f l u x i s proportional to the stator voltage divided by the stator frequency. Thus approximate constant airgap flux operation can be maintained by maintaining the r a t i o of stator voltage to stator frequency constant. The value of the r a t i o i s usually set to the nominal stator voltage (e.g. 440 v o l t s ) divided by the normal operating frequency (e.g. 60 Hz). At low stator frequencies the voltage drop across the stator resistance becomes an important f a c t o r and reduces the airgap f l u x l e v e l i f constant stator volts/Hz i s maintained. A boost i n the volts/Hz r a t i o i s sometimes added at low frequencies to compensate f o r the stator resistance drop. However, the magnitude of the stator voltage drop depends on the stator current so a f i x e d boost i n volts/Hz r a t i o w i l l not 21 compensate for a l l load conditions. Most inverters have a maximum output voltage determined by the inverte r supply voltage. Once th i s maximum voltage i s reached i n constant volts/Hz operation, any further increase i n frequency w i l l r e s u l t i n the airgap f l u x decreasing l i n e a r l y with increasing frequency. As a r e s u l t the peak torque c a p a b i l i t y of the machine w i l l drop off at a rate proportional to the square of the frequency. The torque envelope f o r the induction machine operating under constant volts/Hz control i s shown i n Figure 10. Per Unit Torque U) - i . o Figure 10 Torque Envelope f or Constant Volts/Hz Operation As long as the load torque of the machine i s within t h i s envelope, the speed w i l l be r e l a t i v e l y i n s e n s i t i v e to load torque v a r i a t i o n s since the machine torque/speed curve i s quite steep 2 2 when operating at low s l i p frequencies. The machine c h a r a c t e r i s t i c s thus resemble those of a DC shunt wound machine. Constant volts/Hz operation i s only an approximation to true constant airgap flux operation since the ef f e c t s of the stator impedance are ignored. True constant airgap f l u x operation o f f e r s improvements i n both s t a t i c and dynamic performance over simple constant volts/Hz operation [6]. However some means of determining the airgap f l u x i s required. Direct measurement using H a l l - e f f e c t devices [7] or flux sensing c o i l s [8] i n s t a l l e d i n the machine i s possible but depends on the a v a i l a b i l i t y of machines with these sensors i n s t a l l e d . Direct c a l c u l a t i o n of the airgap f l u x using terminal voltages and currents and the parameters of the machine's equivalent c i r c u i t has also been described i n the l i t e r a t u r e [9]. This technique does not require s p e c i a l machines but does require voltage and current feedback as well as a p r i o r i knowledge of the machine's parameters. Due to the increased complexity of true f l u x control and the r e l a t i v e l y modest requirements of most i n d u s t r i a l v ariable speed drives, the constant volts/Hz drive i s s t i l l the most commonly used AC d r i v e . AC drive systems which r e l y on the control of motor s l i p frequency have also been designed [ 1 0 ] . In the controlled s l i p frequency drive, the stator frequency i s determined by adding the desired s l i p frequency to the motor mechanical frequency which i s measured by a tachometer. Two methods of torque control are commonly used i n co n t r o l l e d s l i p d r i v e s . In the f i r s t technique, 23 the airgap flux i s maintained approximately constant through constant volts/Hz operation and torque i s co n t r o l l e d by varying the s l i p frequency. A l t e r n a t i v e l y , the s l i p frequency i s maintained at a fi x e d value and the torque i s co n t r o l l e d by varying the stator voltage which i n turn varies the airgap f l u x . The c o n t r o l l e d s l i p drive has poor speed regulation since the motor b a s i c a l l y increases i t s speed u n t i l the load torque matches the machine torque but i t has f a i r l y good torque regulation c h a r a c t e r i s t i c s since torque can be d i r e c t l y c ontrolled by the s l i p frequency or stator voltage. As a re s u l t the s l i p c o n t r o l l e d drive has been used i n t r a c t i o n applications such as e l e c t r i c vehicles [11] and the Canadian Advanced Light Rapid Transit System [12] where torque control rather than speed co n t r o l i s desired. The s l i p frequency c o n t r o l l e d drive requires s l i p frequency feedback from the motor. Normally a tachometer i s used to measure the rotor speed which provides an i n d i r e c t measure of s l i p frequency. However, since s l i p frequency i s the small difference between the rotor r o t a t i o n a l frequency and the stator frequency, a very accurate tachometer i s required. These tachometers add s i g n i f i c a n t l y to the cost of the drive system and make the system le s s rugged. Attempts have been made to use lower cost tachometers [13] or to ca l c u l a t e the s l i p d i r e c t l y from machine terminal voltages and currents [14]. The co n t r o l l e d s l i p drive i s inherently protected against the p o s s i b i l i t y of " p u l l out" i n which an increase i n load torque causes the s l i p frequency to increase beyond the point for maximum torque' ( p u l l out torque) and enter the p o s i t i v e l y sloped portion of the torque/speed curve as shown i n Figure 11. Figure 11 Torque/Speed Curve Showing P u l l Out Operation on the p o s i t i v e l y sloped portion of the torque/speed curve i s characterized by poor e f f i c i e n c y and power f a c t o r , high stator currents, and poor speed regulation. Drives not equipped with s l i p frequency c o n t r o l attempt to prevent p u l l out i n a v a r i e t y of ways. Most open loop constant volts/Hz drives have adjustable a c c e l e r a t i o n and deceleration rates so that d i f f e r e n t 25 load i n e r t i a s can be accomodated without exceeding the maximum torque c a p a b i l i t y of the machine. Stator current l i m i t s which cause a decrease i n stator frequency when the current l i m i t i s exceeded act as an approximate form of s l i p frequency c o n t r o l . A better approximation i s achieved when the r e a l component of stator current i s used as the i n d i c a t o r of s l i p since t h i s eliminates the e f f e c t of the magnetizing current [15]. The machine power fa c t o r has also been used as an easy to measure in d i c a t o r of s l i p [16]. AC drives running from current source inverters present a s p e c i a l control problem. If the induction motor equivalent c i r c u i t of Figure 9 i s fed by a current source d e l i v e r i n g a stator current Is, the machine torque equations are developed as follows: (9) Te = 3/w e(Ir 2Rr/s) (10) I r 2 = Is 2w e 2Lm 2 w e 2(Lm + L r ) 2 + ( R r / s ) 2 (11) Te = 3Is 2Lm 2Rrw s l i p w s l i p 2(Lm+Lr) 2+Rr 2 This torque equation can be rewritten i n terms of per-unit s l i p and with the inductances replaced by t h e i r impedances to allow comparison with the standard torque equation for the induction machine operating from a voltage source: 26 (12) Current source operation T = 3/w eIs 2Xm 2Rr/s (Xm+Xr) 2+(Rr/s) 2 (13) Voltage source operation [17] T = 3/w eVs 2Rr/s (Rs+Rr/s) 2+(Xs+Xr) 2 ij 11 i i 0 0.9 1.0 Machine Speed (per unit) Figure 12 Torque-Speed Curves f o r Current and Voltage Source Operation Figure 12 shows torque-speed curves, generated with the equations above, f o r an induction machine running from a voltage source and a current source. The dotted l i n e on the current source curve 27 indicates the t h e o r e t i c a l curve. However that curve r e s u l t s i n very high airgap f l u x l e v e l s when the s l i p i s small since Rr/s becomes very large and most of the stator current flows through the magnetizing inductance Lm rather than into the rotor c i r c u i t . In a r e a l machine, the i r o n saturates and the torque curve shown as a s o l i d l i n e r e s u l t s . The machine can operate at rated torque at e i t h e r point A or point B on the constant current torque/speed curve. Operation at point A on the negatively sloped portion of the torque speed curve corresponds to the operating region i n which the machine i r o n i s saturated and the machine i s running i n e f f i c i e n t l y . Therefore operation at point B on the p o s i t i v e l y sloped portion of the curve i s d e s i r a b l e . However th i s curve r e s u l t s i n s t a t i c a l l y unstable operation since any transient perturbation i n load torque causes the machine to e i t h e r slow down to a h a l t or speed up so that i t enters the stable negatively sloped portion of the torque/speed curve. As a r e s u l t , current source AC drives are usually operated under some type of closed loop c o n t r o l . Controlled s l i p frequency operation with control of torque by v a r i a t i o n of the stator current i s a common cont r o l technique [18, 19]. The dynamics of AC drives have been i n t e n s i v e l y studied as engineers attempt to design AC drives with the same fa s t response as DC d r i v e s . The standard per-phase equivalent c i r c u i t of the induction motor (Figure 9) i s a good representation of the 28 machine under steady state conditions but i s not accurate under transient conditions. The two axis or d-q model used for synchronous machine transient analysis can also be used for induction machine transient analysis [20]. Krause and Thomas have developed the induction machine equations f o r d-q coordinates i n a reference frame r o t a t i n g with angular v e l o c i t y we [21] as Ve. Ls Vol, — " 1<Jfe.L.rv» X Us 0 L.TYIP (w e - Wy-)Lm L V 0 Lmp Rr+Lrp Ur p = d/dt operator Ls = Stator leakage plus magnetizing inductance Lr = Rotor leakage plus magnetizing inductance wr = Rotor angular v e l o c i t y These d i f f e r e n t i a l equations r e s u l t i n a mathematically non-linear state equation since the rotor frequency wr varies with the operating point. In addition the machine inductances and resistances are not constant parameters since they change due to magnetic saturation and motor heating. As a r e s u l t general t r a n s f e r functions f o r the induction machine are not possible since the pole and zero locations depend on the operating points. Instead, transfer functions are derived by 29 l i n e a r i z i n g around an operating point to obtain a l i n e a r small s i g n a l model [22,23]. Poles and zeroes for the l i n e a r model can be determined at a va r i e t y of operating points and plotted on a root locus diagram i n order to determine regions of p o t e n t i a l i n s t a b i l i t y and to give some in s i g h t into the nature of the system response. The major r e s u l t s of these studies can be summarized as follows: (1) The rotor speed response to step changes i n load torque, input voltage, or input frequency i s approximately f i r s t order when the machine and load have high i n e r t i a . The time constant i s [24] <15> T " J w s l i p nTo where J = t o t a l i n e r t i a of machine plus load n = number of machine pole pairs To = f u l l load machine torque per pole w s l i p = S^*-P frequency at f u l l load torque (2) The trend i n rotor speed response i s towards a second order type as machine and load i n e r t i a decreases. Some l i g h t l y loaded machines a c t u a l l y go into steady state rotor speed o s c i l l a t i o n s when operated at low stator frequency [25]. These o s c i l l a t i o n s can sometimes be induced i n otherwise stable machines 30 by i n t e r a c t i o n with the f i l t e r elements i n the inve r t e r ' s DC bus [26]. (3) Very good dynamic performance can be achieved by an induction motor drive i f the stator currents are co n t r o l l e d i n a d-q reference frame rotating at the v e l o c i t y of the rotor flux vector. The d-axis vector i s aligned with the flux vector so that the d-axis stator current e f f e c t i v e l y controls the machine f l u x . When the d-axis current i s aligned i n t h i s fashion, the q-axis current d i r e c t l y controls the machine torque. This " f i e l d oriented c o n t r o l " [27] allows independent con t r o l of f l u x and torque since the two current vectors are orthogonal. This i s analogous to the control of a separately excited DC machine where the f i e l d current controls the machine flux and the armature current controls the machine torque. Most other induction motor control co n t r o l schemes do not succeed i n decoupling the control variables f o r f l u x and torque so a change i n the setpoint fo r one w i l l cause a transient perturbation i n the other. 2.4 Control of the Inverter Waveform The output waveform generated by the inverter i s usually non-sinusoidal. Since induction machines are designed to operate 31 with sinusoidal currents, the e f f e c t s of operation with non-sinusoidal currents must be evaluated to determine how machine performance i s af f e c t e d . For the purpose of an a l y s i s , the induction machine can be considered to be a l i n e a r system as long as magnetic saturation i s ignored [28]. The waveform can therefore be decomposed into a fundamental component and a set of harmonic components by Fourier analysis and the machine response can be determined for each harmonic i n d i v i d u a l l y . The t o t a l response i s obtained by summing the responses to the fundamental and harmonic components. Waveforms from a properly operating inverter are symmetrical and have no DC o f f s e t . As a r e s u l t the waveform has no DC component and no even harmonics. In addition, the t r i p l e n harmonics (harmonics of order 3k where k i s a p o s i t i v e integer) i n a three phase system are a l l i n phase (zero sequence) and so produce no machine f l u x . As a r e s u l t they w i l l not a f f e c t the machine's torque. If the machine i s connected i n a wye configuration, no t r i p l e n harmonic w i l l flow i n the windings. Of the remaining harmonics, those of order 6k+l produce machine fl u x that rotates i n the same d i r e c t i o n as the fundamental f l u x ( p o s i t i v e sequence) while those of order 6k-l produce machine flux that rotates i n the opposite d i r e c t i o n to to the fundamental flux (negative sequence). The equivalent c i r c u i t of the induction machine shown i n Figure 9 can be used to develop a simpler c i r c u i t which i s v a l i d for the 32 harmonic components of the e x c i t a t i o n waveform. The s l i p f o r the harmonic components i s (16) s = kwg - w. rotor where wg i s the fundamental stator frequency k i s the order of the harmonic component w. rotor i s the rotor mechanical frequency From t h i s equation i t i s apparent that the s l i p for the harmonic components i s close to 1 since the lowest harmonic component i s of order k = 5. This means that the harmonic components of the machine current w i l l not be greatly affected by the load on the machine. At most operating frequencies the input impedance seen by the harmonic components i s dominated by the reactances i n the c i r c u i t since the reactances increase with frequency while the resistances remain constant (ignoring skin e f f e c t f or the moment). The impedance of the magnetizing branch i s very large at harmonic frequencies and as a r e s u l t i t s e f f e c t on harmonic currents i s small. If the machine resistances and i t s magnetizing branch are neglected, the equivalent c i r c u i t can be reduced to the leakage reactances as shown i n Figure 13. 33 o o-m m L I m m L2 Figure 13 Machine Equivalent C i r c u i t f or Harmonics Using t h i s approximate equivalent c i r c u i t , the harmonic currents flowing into the machine can be calculated as follows: (17) k(X :+X 2) where i ^ = magnitude of current harmonic of order k v^ = magnitude of voltage harmonic of order k X^, X 2 = stator and rotor leakage reactances at fundamental frequency The induction machine acts as a low pass f i l t e r which attenuates higher 34 order current harmonics. Since the voltage harmonics i n invert e r waveforms decrease i n magnitude as t h e i r order increases, the net re s u l t i s that machine performance i s primarily affected by the low order harmonics i n the waveform. In an invert e r with a six-step (square wave) waveform, the voltage waveform can be expressed by the following Fourier s e r i e s : (18) v ( t ) = V^sinwt + l/5sin5wt + l/7sin7wt + 1 / l l s i n l l w t + ... ) The dominant harmonics are the f i f t h and seventh. The f i f t h harmonic produces f l u x r o t a t i n g i n the opposite d i r e c t i o n to the fundamental f l u x . The f l u x produced by the seventh harmonic rotates i n the same d i r e c t i o n as the fundamental f l u x . Under normal operating conditions, the rotor rotates at approximately synchronous speed and therefore the rotor bars cut the rotating f i f t h and seventh harmonic fluxes at the s i x t h harmonic frequency. As a r e s u l t s i x t h harmonic currents are induced i n the rotor. These currents i n t e r a c t with the fundamental flux to produce a pulsating torque at the s i x t h harmonic frequency [29]. The torque has zero average value. This pulsating torque represents the major e f f e c t that harmonics have on machine torque. The magnitude of th i s harmonic torque depends on the magnitude of the f i f t h and seventh harmonic currents. High leakage reactance machines fed from a voltage source inverter have the smallest torque pulsations since 35 harmonic currents are attenuated by the motor leakage reactance. On the other hand, motors fed from a current source i n v e r t e r have the largest torque pulsations since the motor i s fed a square wave of current i n which the harmonic currents are not attenuated at a l l . An average machine fed from a voltage source i n v e r t e r has torque pulsations with a magnitude of about 0.1 p.u. [30]. The e f f e c t of the torque pulsations on o v e r a l l system performance depends on rotor and load i n e r t i a and on operating speed. On one hand, a low i n e r t i a machine operating at low speed ( a few Hertz ) may a c t u a l l y rotate i n a series of steps or jerks. On the other hand, a high i n e r t i a machine running at high speeds ( 50 Hertz ) may not be noticeably affected by the pulsating torque. In intermediate s i t u a t i o n s , the pulsating torque may be noticeable as a v i b r a t i o n that can increase wear on couplings and gears. Since harmonic currents add l i t t l e i f anything to the machine's output power, t h e i r e f f e c t i s seen primarily as an increase i n the machine's e l e c t r i c a l losses. The flux generated by the harmonic currents causes an increase i n the core loss and the stray losses i n the machine. The increase i n core l o s s has been found to be small; on the order of 10% [31]. The stray losses i n the machine have been found to be as much as two or three times greater when the machine i s running from a non-sinusoidal source [32]. Fortunately, the stray loss i s a small f r a c t i o n of the machine's t o t a l losses so a large increase does not severely 36 impair the machine's e f f i c i e n c y . The main source of increased motor losses, however, i s harmonic copper loss e s . Skin e f f e c t i n most induction machine stators i s n e g l i g i b l e since the windings i n most cases consist of insulated wire of r e l a t i v e l y small cross section. As a r e s u l t , the a d d i t i o n a l copper losses i n the stator are: oo The skin e f f e c t i n the rotor bars, on the other hand, i s s i g n i f i c a n t , p a r t i c u l a r l y i f the rotor i s of deep-bar construction. As a r e s u l t , the rotor resistance increases with frequency. According to Alger [33] the increase i n rotor resistance i s approximately proportional to the square root of the frequency. As a r e s u l t , the major increase i n copper losses occurs i n the r o t o r . Kliman [34] calculates an increase of 15% to 60% i n stator copper losses depending on the p a r t i c u l a r waveform applied but c a l c u l a t e s an increase of 90% to 270% i n rotor copper losses. Kliman's values are v a l i d only for the machine and waveforms he analyzed since losses are very s e n s i t i v e to the p a r t i c u l a r harmonic content of the waveform, and to the leakage reactance, (19) k>l where 1^ = rms value of the kth harmonic current 37 rotor resistance, and rotor bar height of the motor. However, his figures are i n l i n e with other studies which indicate that t o t a l machine losses when operating from a non-sinusoidal source can be from 1.1 to 3 times the losses when running from a sinusoidal source. The increased losses i n the i n v e r t e r driven motor r e s u l t s i n increased heating of the motor, p a r t i c u l a r l y since the motors often run at reduced speed which lessens the a i r flow through the machine. The increased heating can r e s u l t i n accelerated aging of the motor i n s u l a t i o n and thus shorten the service l i f e of the machine. This problem can be dealt with by choosing a machine with a higher power rating than required or by applying forced a i r cooling but i t i s more desirable to control the inverter's output waveform to minimize the harmonic losses. The output waveshape of a Variable Voltage Input inverter or a standard Current Source i n v e r t e r cannot e a s i l y be changed. However, the six-step square wave supplied by these inverters usually increases machine losses by l e s s than 20%. The main problem with the waveform of these i n v e r t e r s , p a r t i c u l a r l y the Current Source i n v e r t e r , i s the production of s i x t h harmonic torque pulsations. Some Current Source inverters do modulate t h e i r output current at low output frequencies i n order to reduce these torque pulsations. The output waveform of a pulse width modulated (PWM) i n v e r t e r , on 38 the other hand, can increase machine losses s u b s t a n t i a l l y . Fortunately, by adopting a suitable modulation technique, the harmonic content of the output waveform can be adjusted to reduce losses to an acceptable l e v e l . A v a r i e t y of modulation techniques are described i n the l i t e r a t u r e . Perhaps the oldest i s the " t r i a n g l e intercept" or "subharmonic" technique [35]. In t h i s technique, a s i n u s o i d a l voltage (the reference) i s compared with a higher frequency t r i a n g u l a r voltage (the c a r r i e r ) . The intersections of the two waveforms are used to determine the switching instants for the pulse width modulated waveform as shown i n Figure 14. The 'an J l f ID 1 0 T 2 /, 3 v H r j, dc u Figure 14 Triangle Intercept Pulse Width Modulation r e s u l t i n g pulse width modulated waveform has a harmonic spectrum consisting of a fundamental component at the frequency of the reference waveform and harmonic components centered around multiples of the c a r r i e r frequency [36]. The amplitude and frequency of the fundamental component i s changed by varying the amplitude and frequency of the reference waveform. To produce a three phase output, a three phase set of reference waveforms i s compared with the c a r r i e r . The c a r r i e r waveform i s commonly synchronized to the reference to avoid subharmonic beats caused by the changing phase r e l a t i o n s h i p between the c a r r i e r and reference [37]. The c a r r i e r frequency i s chosen to be an odd multiple of three times the reference frequency (e.g. 21 or 27). This ensures that the modulated waveform i s always symmetrical and, as long as the motor neutral i s n ' t grounded, the harmonics at multiples of the c a r r i e r frequency won't generate any motor currents since they are t r i p l e n harmonics. In that case the harmonics occur i n sidebands around the c a r r i e r frequency and i t s harmonics. The most important harmonics occur at: (19) f c + 2f ref (20) and 2f„ + f c — ref where f £ = c a r r i e r frequency f r e £ = reference frequency 40 Harmonics also occur i n sidebands around higher multiples of the c a r r i e r frequency but they do not have much ef f e c t on machine performance. Obviously, by choosing a suitably high c a r r i e r frequency, the harmonic currents can be reduced to any desired l e v e l since the machine acts as a low pass f i l t e r . However, the switching devices i n the in v e r t e r may have switching speed l i m i t a t i o n s . This i s p a r t i c u l a r l y true f o r t h y r i s t o r s which are usually l i m i t e d to maximum switching frequencies i n the range of 500 Hz to 1500 Hz. Transistors, on the other hand, can be used e f f e c t i v e l y up to 5 or 6 kHz, so PWM inverters using t r a n s i s t o r s can produce output waveforms with low current harmonics. Power MOSFETs can switch at very high frequencies and so can produce waveforms with e s s e n t i a l l y no harmonic currents. To deal with the problem of maximum switching frequency l i m i t s , multi-mode modulation s t r a t e g i e s are often used i n which the r a t i o between c a r r i e r and reference frequency i s lowered as the reference frequency i s increased so that the switching frequency i s kept below the maximum l i m i t [38]. The amplitude of the fundamental l i n e to l i n e voltage at f u l l modulation (when the amplitude of the reference equals that of the c a r r i e r ) i s (21) vTv n r/2 41 where V-DC = i n v e r t e r DC bus voltage The magnitude of the fundamental component of the unmodulated six-step square wave i s which i s 27% greater. In order to make f u l l use of the KVA r a t i n g of the i n v e r t e r i t i s desirable to make a t r a n s i t i o n from the f u l l y modulated PWM wavefom to the unmodulated six-step waveform. In order to do t h i s , pulses are merged or "dropped" u n t i l the six step waveform i s reached. Some care must be taken i n the manner i n which pulses are dropped to ensure that sudden jumps i n the fundamental do not occur. Various strategies f o r pulse dropping have been described i n the l i t e r a t u r e [39], [40]. The t r i a n g l e intercept form of modulation i s well suited to analog implementation, although the implementation becomes more complex when c a r r i e r synchronization to the reference i s required and the r a t i o s between c a r r i e r and reference frequencies are changed to keep inverter switching frequency under some l i m i t . D i g i t a l implementations of t h i s type of modulation are also possible, e i t h e r by storing pre-calculated switching patterns i n memory and reading them out as required or by d i r e c t l y c a l c u l a t i n g the switching instants during inverter operation. However, d i g i t a l implementation of pulse width modulated (22) V T 2 V D C/TT 42 c o n t r o l l e r s introduces the p o s s i b i l i t y of other modulation techniques. ^Switching ^ Angle Figure 15 PWM Waveform Having Quarter and Half Wave Symmetry The harmonic content of a pulse width modulated waveform of the type shown i n Figure 15, which has quarter and half wave symmetry, i s [41]: M (23) a n = 2 VDC 1 + 2 ^ ( - l ) k c o s n t * k k=l where a n = amplitude of the nth harmonic M = number of switching instants per quarter cycle = angle of the kth switching instant 43 U s i n g n u m e r i c a l t e c h n i q u e s i t i s p o s s i b l e t o c h o o s e t h e M s w i t c h i n g a n g l e s p e r q u a r t e r c y c l e t o c o n t r o l t h e a m p l i t u d e o f t h e h a r m o n i c s . F o r e x a m p l e , P a t e l a n d H o f t [42] c a l c u l a t e d t h e s w i t c h i n g a n g l e s r e q u i r e d t o c o n t r o l t h e a m p l i t u d e o f t h e f u n d a m e n t a l w h i l e r e d u c i n g t h e a m p l i t u d e s o f M - l h a r m o n i c s t o z e r o . B u j a a n d I n d r i [43] a n d o t h e r s c a l c u l a t e d t h e s w i t c h i n g a n g l e s r e q u i r e d t o c o n t r o l t h e a m p l i t u d e o f t h e f u n d a m e n t a l w h i l e m i n i m i z i n g a p e r f o r m a n c e c r i t e r i o n s u c h a s w h i c h i s p r o p o r t i o n a l t o t h e t o t a l r m s v a l u e o f t h e h a r m o n i c c u r r e n t s i n t h e m o t o r . M i n i m i z i n g t h i s c r i t e r i o n s h o u l d a l s o m i n i m i z e m a c h i n e c o p p e r l o s s i f s k i n e f f e c t i s i g n o r e d . S w i t c h i n g a n g l e s a r e c a l c u l a t e d f o r a r a n g e o f f u n d a m e n t a l a m p l i t u d e s r a n g i n g f r o m z e r o t o m a x i m u m a n d a r e s t o r e d i n t h e PWM c o n t r o l l e r . T h e c o n t r o l l e r t h e n l o o k s u p t h e s e t o f a n g l e s f o r t h e d e s i r e d i n v e r t e r o u t p u t v o l t a g e a n d u s e s t h e m t o g e n e r a t e t h e r e q u i r e d s w i t c h i n g f r e q u e n c y [44]. T h e s e p r o g r a m m e d w a v e f o r m s h a v e b e e n f o u n d t o p r o d u c e l o w e r l o s s e s i n t h e m a c h i n e t h a n t h e t r i a n g l e i n t e r c e p t w a v e f o r m s w h e n t h e n u m b e r o f p u l s e s p e r c y c l e i s s m a l l [45]. T h u s t h e y a r e u s e f u l w i t h i n v e r t e r s e m p l o y i n g t h y r i s t o r s w h i c h a r e r e s t r i c t e d oo (24) n=3 44 i n the maximum switching frequency. They are also of use when the inve r t e r must produce high fundamental frequencies (e.g. 400 Hz). 4 5 Chapter 3 Inverter C o n t r o l l e r Design Considerations This chapter discusses the design of the i n v e r t e r c o n t r o l l e r from a high l e v e l or systems perspective. The design requirements f o r the i n v e r t e r c o n t r o l l e r and the possible design tradeoffs are discussed i n d e t a i l . This i s followed by consideration of the a l t e r n a t i v e methods of implementing the c o n t r o l l e r functions and by presentation of the basic architecture of the c o n t r o l l e r . The det a i l e d design of the i n v e r t e r c o n t r o l l e r hardware and software i s discussed i n succeeding chapters. The c o n t r o l l e r design i s based on a microcomputer i n order to give the c o n t r o l l e r a considerable amount of programmability. The d i v i s i o n of c o n t r o l l e r functions between hardware and software was given c a r e f u l a t t e n t i o n . Some functions, such as the c o n t r o l l e r sequencing function or the control panel i n t e r f a c e function, can be performed by software with no s a c r i f i c e i n performance and with a considerable gain i n f l e x i b i l i t y . Other functions are more time c r i t i c a l and had to be analyzed c a r e f u l l y to determine a good tradeoff between hardware and software. In p a r t i c u l a r , the functions associated with pulse width modulation required close a t t e n t i o n . Software intensive PWM generation techniques had d i f f i c u l t y i n meeting performance requirements while more hardware oriented techniques required a large number of 46 components. Fortunately, a s o l u t i o n presented i t s e l f i n the form of a large scale integrated c i r c u i t that generates three phase PWM waveforms. Curiously, t h i s IC, the P h i l i p s HEF4752V, has been almost e n t i r e l y ignored i n the l i t e r a t u r e on inverter c o n t r o l l e r s . Papers are s t i l l published describing complex PWM waveform generation c i r c u i t s that appear to have no performance advantages over t h i s IC. This thesis appears to be the f i r s t d e scription of a microprocessor based inver t e r c o n t r o l l e r that makes use of t h i s IC. One advantage of the care taken i n defining the inver t e r c o n t r o l l e r functions and d i v i d i n g them between hardware and software i s that the c o n t r o l l e r architecture can be kept quite simple without major s a c r i f i c e i n performance or f l e x i b i l i t y . As mentioned, the c o n t r o l l e r has a microcomputer at i t s heart. The other major components of the c o n t r o l l e r are analog and d i g i t a l input ports to the microcomputer, d i g i t a l output ports from the microcomputer, and the PWM waveform generation IC. With the exception of the PWM waveform generation, the c o n t r o l l e r functions are primarily performed by microcomputer software with some assistance from simple hardware components i n cases where speed of response i s c r i t i c a l . 4 7 M»TtWt*CUMWWOITl WW 01 UNf ' F i g u r e 16 I.S . E . S u b m e r s i b l e s 3.1 Basic System Requirements The i n i t i a l a p p l i c a t i o n of the invert e r c o n t r o l l e r was to cont r o l thruster drives for submersibles produced by International Submarine Engineering. Figure 16 shows the submersibles produced by I.S.E. Some of the submersibles are autonomous but most are run with a tether that c a r r i e s control signals and three phase AC power from the surface and returns telemetry from the submersible to the surface. Each submersible has up to four thrusters to allow complete control of the submersible's motion. Depending on the s i z e of the submersible, the power ra t i n g of each thruster i s from 1.5 horsepower to 5 horsepower. International Submarine Engineering has used a va r i e t y of motors to power the thrusters. The smaller thrusters have used s i n g l e phase unive r s a l motors with speed control by con t r o l l e d r e c t i f i c a t i o n . Larger thrusters have used three phase AC motors with speed co n t r o l achieved by a variable p i t c h p r o p e l l o r s . The thrusters on one series of submersibles use var i a b l e speed hydraulic motors with one large AC motor running a hydraulic pump. Each of these techniques has disadvantages, e i t h e r from a r e l i a b i l i t y or a cost aspect. Variable frequency speed control of AC motors with an in v e r t e r was considered by ISE, but no suitable inverters could be found. The inverters cannot be on the surface because the cable required to carry the power to the i n d i v i d u a l thrusters would be too heavy 49 and too c o s t l y . Therefore, compact inverters that can withstand submersion to 1000 meters are required so that they can be i n s t a l l e d d i r e c t l y on the submersible. A development project was started i n 1980, within the Department of E l e c t r i c a l Engineering at UBC, to develop an inver t e r drive to meet the requirements of the submersible a p p l i c a t i o n . The basic i n v e r t e r configuration chosen was a PWM inver t e r using power MOSFETs or power t r a n s i s t o r s as switches. This r e s u l t s i n a minimum number of components i n the inver t e r since a sin g l e r e c t i f i e r bridge can be used for a l l four inverters on a submersible and no commutation c i r c u i t s are required. Power tr a n s i s t o r s and power MOSFETs are a v a i l a b l e i n the power ratings required f o r t h i s a p p l i c a t i o n . Each t r a n s i s t o r or MOSFET switch i s c o n t r o l l e d by a dr i v e r c i r c u i t which interfaces to the c o n t r o l l e r v i a an opto-coupler. The in v e r t e r i s designed to be packaged i n the same housing as the thruster motor. The e n t i r e motor housing i s f i l l e d with o i l to compensate for the external water pressure so the motor housing does not have to withstand any pressure. It i s doubtful that the integrated c i r c u i t s and other components used i n the c o n t r o l l e r w i l l work submerged i n o i l . As a r e s u l t , the c o n t r o l l e r s f o r the four inverters have to be i n s t a l l e d i n the pressure housing used to contain the other e l e c t r o n i c c i r c u i t s i n the submersible. This places p a r t i c u l a r l y severe 50 requirements on the size of the c o n t r o l l e r since space i n the pressure housing i s a valuable commodity. The need for high r e l i a b i l i t y and quick repair i n the submersible a p p l i c a t i o n also encourages a design that uses a minimum number of components and i s compact enough to be placed on one printed c i r c u i t card that can be swapped i f a c o n t r o l l e r malfunction occurs. In order to make use of compact high speed motors, the inverter drive must operate at frequencies up to 400 Hertz. Smooth control i s required i n both forward and reverse directions from the 400 Hz maximum output frequency down to a few Hertz so that the submersible can be manoeuvered i n confined spaces. However, extremely rapid changes i n motor speed are not required and there i s no need f o r precise c o n t r o l of motor torque or speed. Therefore, an open-loop constant volts/Hz control strategy i s acceptable. The i n v e r t e r i s designed to detect overcurrent conditions which occur i f the thruster propeller becomes jammed. The inver t e r sends an overcurrent s i g n a l to the c o n t r o l l e r , which must respond by shutting down the i n v e r t e r . The thruster speed and d i r e c t i o n commands are sent down to the submersible on a s e r i a l data l i n k . C i r c u i t r y on the submersible converts the s e r i a l data to p a r a l l e l data consisting of 8 b i t words. The in v e r t e r c o n t r o l l e r must accept t h i s p a r a l l e l data as i t s c o n t r o l input. In addition, i t i s desirable to have some means of c o n t r o l l i n g the in v e r t e r with potentiometers and switches for the purposes of t e s t i n g and maintenance. 51 To summarize, the basic requirements f o r the invert e r c o n t r o l l e r for the submersible a p p l i c a t i o n are the following: 1. The c o n t r o l l e r must supply pulse width modulated switching signals for each of the s i x invert e r switches. Each switching s i g n a l must drive the LED i n an opto-coupler. 2. The c o n t r o l l e r must operate the invert e r over an output frequency range of 3 to 400 Hz and be capable of reversing the phase sequence f o r b i d i r e c t i o n a l operation of the motor. 3. The c o n t r o l l e r must implement an open-loop constant volts/Hz co n t r o l scheme for the motor dr i v e . 4. The c o n t r o l l e r must accept a d i g i t a l (TTL compatible) overcurrent s i g n a l from the in v e r t e r and shut down the inverte r on receipt of the s i g n a l . 5. The c o n t r o l l e r must accept 8 b i t p a r a l l e l data (TTL compatible) as i t s speed and d i r e c t i o n commands. It should also have provision to accept an analog voltage input as a speed command. 6. The c o n t r o l l e r must f i t within the pressure housing 52 of an ISE submersible. This means i t must consist of one or more of the 218 mm. by 77 mm. c i r c u i t cards used by ISE f o r i t s own e l e c t r o n i c c i r c u i t s . I d e a l l y the c o n t r o l l e r should f i t on one card. 7. Since the c o n t r o l l e r i s i n s t a l l e d i n a sealed housing and operates only when the vehicle i s submerged, non hermetic, commercial temperature range (0 C to 70 C) components may be used. It i s desirable but not mandatory that the c o n t r o l l e r operate from a single 5 Volt power supply. 3.2 Requirements For Other Applications If the inverter c o n t r o l l e r i s to be used i n applications other than submersible drives, some a d d i t i o n a l c a p a b i l i t i e s must be added to the c o n t r o l l e r . Deciding exactly what c a p a b i l i t i e s are to be added requires c a r e f u l consideration of how the a d d i t i o n a l c a p a b i l i t y w i l l a f f e c t the s i z e and cost of the c o n t r o l l e r . Also, the addi t i o n of some functions requires considerable design e f f o r t which may not be warranted by the value of the a d d i t i o n a l functions. For instance, to add the c a p a b i l i t y to control Variable Voltage Input and Current Source inverters would s u b s t a n t i a l l y increase the complexity of the c o n t r o l l e r and increase the time required to design i t . However, PWM inverters can be used i n almost a l l i n v e r t e r applications involving power 53 l e v e l s below 200 kW. Therefore the addition of these c a p a b i l i t i e s i s not r e a l l y warranted by the l i m i t e d number of a d d i t i o n a l applications made possible by t h e i r i n c l u s i o n . Other c a p a b i l i t i e s can be added at less cost. For example, the a b i l i t y to control inverters using t h y r i s t o r s as switches would be advantageous i n higher power and higher voltage applications where suitable t r a n s i s t o r s or power MOSFETs are not a v a i l a b l e . To add t h i s c a p a b i l i t y , the c o n t r o l l e r must generate separate control signals to turn on ( f i r e ) the t h y r i s t o r and turn off (commutate) the t h y r i s t o r . In addition the c o n t r o l l e r must in s e r t appropriate delays so that s u f f i c i e n t time i s allowed f o r t h y r i s t o r commutation before the other t h y r i s t o r i n the same inverte r leg i s f i r e d . These requirements are not d i f f i c u l t to meet, so t h i s i s a c a p a b i l i t y that should be added. The submersible a p p l i c a t i o n places no p a r t i c u l a r demands on inverter waveshape since torque pulsations don't pose a problem and the seawater surrounding the motor acts as a good sink for the a d d i t i o n a l heat generated by the current harmonics. However, waveshaping i s desirable i n many other applications i n order to reduce losses and torque pulsations. Although the submersible drive can operate open-loop, other applications w i l l require some form of closed loop c o n t r o l . Ideally, the c o n t r o l l e r should be designed so that i t can handle high performance control strategies such as f i e l d oriented 54 c o n t r o l . The c o n t r o l l e r could then be used i n servo drives f o r robots and machine t o o l s . However, c o n t r o l l e r s for these high performance drives are complex and require a wide bandwidth. Examples described i n the l i t e r a t u r e have required dual 8 b i t microcomputers [46] or a sing l e high speed 16 b i t microprocessor [47] along with considerable support c i r c u i t r y . Even with the use of a 16 b i t microprocessor, the control bandwidth was only wide enough to allow closed loop operation up to a stator frequency of 100 Hz. The i n c l u s i o n of a c a p a b i l i t y f o r servo type control of AC motors i n the c o n t r o l l e r would make i t too large f o r the submersible a p p l i c a t i o n and would require a major design e f f o r t . It i s better to design a s p e c i a l purpose c o n t r o l l e r for servo applications than to attempt to squeeze servo c a p a b i l i t i e s into a general purpose inverter c o n t r o l l e r . Fortunately, simple speed control loops or s l i p frequency control loops are not as demanding on c o n t r o l l e r bandwidth. They can be implemented f a i r l y e a s i l y i f the c o n t r o l l e r i s based on a microprocessor. Provision must be made, however, to accept feedback signals such as stator currents or rotor speed. In some ap p l i c a t i o n s , parameters such as the acceleration and deceleration rate or the volts/Hz r a t i o must be adjusted to match a p a r t i c u l a r load. The c o n t r o l l e r should have some provision for manual adjustment of such parameters. The c o n t r o l l e r should be equipped with a d d i t i o n a l protective 55 features to prevent inverter f a i l u r e due to conditions such as overcurrent or overheating. For example, when a high i n e r t i a load i s decelerated, energy i s regenerated back on to the DC bus of the i n v e r t e r . If th i s energy i s not dissipated or returned to the AC source, i t w i l l cause an overvoltage on the DC bus which w i l l eventually cause f a i l u r e of invert e r components. To avoid t h i s , the c o n t r o l l e r can be designed sense the bus voltage and switch i n a b a l l a s t r e s i s t o r to absorb the regenerated energy i f the bus voltage exceeds a c e r t a i n l i m i t . F i n a l l y , the c o n t r o l l e r must meet some cost constraints. Even though many of the applications of the c o n t r o l l e r w i l l be s p e c i a l i z e d , economic considerations w i l l s t i l l apply. It i s d i f f i c u l t to set a target p r i c e f o r the c o n t r o l l e r since cost breakdowns for commercial inver t e r drives are not a v a i l a b l e . However, an estimate can be made based on the wholesale prices of some inverters and some assumptions on the d i v i s i o n of costs within these i n v e r t e r s . The target price based on th i s estimate i s $200 for parts and d i r e c t labor. To summarize, the a d d i t i o n a l c a p a b i l i t i e s that should be added to the submersible c o n t r o l l e r to make i t usable i n other applications are the following: 1) The c o n t r o l l e r should be able to control t h y r i s t o r inverters as well as t r a n s i s t o r and power MOSFET in v e r t e r s . 5 6 2) The c o n t r o l l e r should use a PWM strategy that reduces harmonic currents i n the motor i n order to reduce torque pulsations and harmonic losses. 3) The c o n t r o l l e r should provide for the implementation of simple closed-loop c o n t r o l schemes that do not require complex c i r c u i t s or wide c o n t r o l l e r bandwidth. 4) The c o n t r o l l e r should allow for manual adjustment of parameters such as a c c e l e r a t i o n and deceleration rates, volts/Hz r a t i o , and maximum output frequency. 5) The c o n t r o l l e r should have provision to protect the inv e r t e r against f a i l u r e due to overvoltage, overcurrent, and overheating. 6) The c o n t r o l l e r should cost no more than $200 f o r parts and d i r e c t labor. 3.3 Controller Functions The basic functions to be performed by the PWM inverter c o n t r o l l e r can be grouped into the following categories: 1) System management and sequencing 57 2) Torque/speed control 3) PWM waveform generation 4) Control panel i n t e r f a c e 5) Monitoring and protection The system management and sequencing functions perform the operations required to take the drive through i t s various operating modes such as s t a r t up, shut down, acce l e r a t i o n , deceleration, and reversing. During system s t a r t up, for example, i t i s often necessary to turn on power supplies i n the i n v e r t e r i n a defined order so that the i n v e r t e r switches do not become active before t h e i r control signals become v a l i d . Also, the DC bus f i l t e r capacitor may have to be precharged before the main contactor i s closed to apply power to the DC bus i n order to prevent large inrush currents. S i m i l a r l y , shut down of the drive requires that a sequence of operations be performed. Sequencing i s also required during i n v e r t e r operation. For instance, i f the drive i s commanded to go from f u l l speed forward to f u l l speed reverse, the c o n t r o l l e r must f i r s t decelerate the motor to a stop at a controlled rate, then reverse the i n v e r t e r phase sequence, and then accelerate the motor at a c o n t r o l l e d rate to the maximum speed. 58 The torque/speed control functions implement the o v e r a l l closed loop control strategy f o r the d r i v e . These functions accept feedback signals from sensors such as tachometers and they receive c o n t r o l setpoints from the system management functions. The difference between the setpoint and the feedback value i s applied to a con t r o l algorithm. The control algorithm produces setpoint values f o r the inver t e r frequency and volts/Hz r a t i o which are sent to the PWM waveform generation functions. Limiter Signal Conditioning Volts/Hz ^ Command ~ Accelerator Pedal Rotor Frequency Rotor * 1 Calculator Frequency V Slip Frequency Voltage Command Stator Frequency. Command Pulse Width Modulator Optical Shaft Encoder Pulse? DC Volts In 11 P.W.M. Inverter II Induction Motor Figure 17 Control Loop for Controlled S l i p Drive As an example of a t y p i c a l c o n t r o l loop, consider the c o n t r o l l e d s l i p drive shown i n block diagram form i n Figure 17. This drive has been used as a t r a c t i o n drive i n an e l e c t r i c v e h i c l e [48]. 59 The c o n t r o l l e r measures the rotor frequency using an o p t i c a l shaft encoder and adds a constant s l i p frequency to produce the stator frequency setpoint. The c o n t r o l l e r receives a volts/Hz setpoint s i g n a l from a potentiometer attached to the vehicle accelerator pedal. The volts/Hz signal i s l i m i t e d so that i t cannot exceed a value which would r e s u l t i n magnetic saturation of the motor. In t h i s simple control loop, motor torque i s con t r o l l e d by the volts/Hz r a t i o set by the accelerator pedal. Motor speed w i l l increase u n t i l the motor torque i s balanced by the load torque. The PWM waveform generation functions produce the control signals that cause the inve r t e r switches to turn on and o f f . The functions must accept setpoints f or the inve r t e r output frequency and volts/Hz r a t i o and then apply a modulation technique such as the t r i a n g l e intercept technique to produce an output waveform of the desired frequency and voltage. Since the c o n t r o l l e r must control six i n v e r t e r switches at switching frequencies which may be several k i l o h e r t z , the PWM generation functions must be very f a s t . Due to l i m i t a t i o n s of the switching devices i n the inverter, the PWM functions must also ensure that c e r t a i n timing requirements are met by the generated control s i g n a l s . For example, the switching frequency must normally be kept below the l i m i t at which device switching losses begin to overheat the device. At the same time i t i s desirable to keep the switching frequency as 60 close to the l i m i t as possible so that the waveform harmonics are at the highest possible frequency. In t h y r i s t o r i n v e r t e r s , a switch must normally be on f o r a c e r t a i n minimum length of time i n order to ensure that the commutation c i r c u i t s can recharge for the next commutation. Thus the PWM generation functions must eliminate a l l c o n t r o l pulses shorter than t h i s minimum time. F i n a l l y , the PWM generation functions must i n s e r t delays between the turning off of one switch i n a leg of the invert e r and the turning on of the other switch i n the leg to ensure that no conduction overlap occurs. The control panel i n t e r f a c e functions represent those functions that communicate with the "outside world". In a conventional i n d u s t r i a l drive they read setpoints from potentiometers and switches on a con t r o l panel and send information to i n d i c a t o r lamps, meters, and displays on the panel. In embedded drives such as the submersible thrusters, they handle the communication between the invert e r c o n t r o l l e r and the system that i s supplying the c o n t r o l commands. The monitoring and protection functions monitor the inverter and take protective action i f conditions occur which may cause damage to the drive. The actions must be t a i l o r e d to the f a u l t condition. For example, i f a large and rap i d l y increasing overcurrent, i n d i c a t i v e of a short c i r c u i t , i s detected, the inverte r must be immediately shut down. On the other hand, i f a moderate overcurrent i s detected when the drive i s ac c e l e r a t i n g , 61 i n d i c a t i v e of too rapid a c c e l e r a t i o n , the appropriate action i s to reduce the rate of a c c e l e r a t i o n . The monitoring and protection functions may also perform s e l f checks on the c o n t r o l l e r and perform diagnostics i n the event of a drive f a u l t . For instance, i f the in v e r t e r shuts down, the diagnostic functions w i l l i n d i c a t e what conditions caused the shutdown on a control panel dis p l a y . 3.4 Inverter C o n t r o l l e r Design Alternatives The c o n t r o l l e r s i n many inverters currently i n production are based on a mix of CMOS l o g i c c i r c u i t s and analog integrated c i r c u i t s . For the past several years however, research and development has centred on microprocessor based designs. Some of these new microprocessor based c o n t r o l l e r s are beginning to appear i n production [49], Microprocessor based c o n t r o l l e r s are a t t r a c t i v e because they allow more r e l i a b l e and f l e x i b l e c o n t r o l l e r s to be b u i l t at a lower cost. The increased r e l i a b i l i t y comes from the s u b s t i t u t i o n of LSI components for the small scale integrated c i r c u i t s used previously. The reduction i n component count and number of interconnections r e s u l t s i n a more r e l i a b l e system. The increase i n f l e x i b i l i t y comes from the a b i l i t y to change c o n t r o l l e r c h a r a c t e r i s t i c s by a l t e r i n g the microprocessor software rather than making modifications to hardware. Since a microprocessor 6 2 based c o n t r o l l e r uses less components than a c o n t r o l l e r based on small scale integrated c i r c u i t s , i t i s normally considerably cheaper to manufacture. However, the cost of software development must be considered when comparing the cost of a microprocessor based c o n t r o l l e r to the cost of a c o n t r o l l e r based s t r i c t l y on hardware. Since the design requirements f o r our project emphasized a small, f l e x i b l e and r e l i a b l e i n v e r t e r c o n t r o l l e r , one of the f i r s t design decisions was to base the c o n t r o l l e r on a microcomputer. With t h i s decision made, i t i s necessary to p a r t i t i o n the c o n t r o l l e r functions between those functions that are to be c a r r i e d out e n t i r e l y by software and those functions that are to be c a r r i e d out by a u x i l i a r y hardware under control of the microcomputer. Some functions such as the system management and sequencing functions and the control panel i n t e r f a c e functions are well suited to a software implementation. Others, such as the torque/speed control functions, the system protection functions, and the PWM waveform generation functions, require a closer examination of the tradeoffs between software and hardware implementation. 3.5 Torque and Speed Control Torque/speed control functions have t r a d i t i o n a l l y been implemented as analog feedback co n t r o l loops with operational a m p l i f i e r c i r c u i t s providing proportional or proportional plus i n t e g r a l 63 c o n t r o l . These c i r c u i t s are simple and have more than enough bandwidth for motor control a p p l i c a t i o n s . Moreover, an analog implementation i s inherently p a r a l l e l ; multiple feedback loops can be closed or feedback signals can be f i l t e r e d simply by adding more components. However, analog c i r c u i t s tend to d r i f t with time and temperature. Also, they are designed to implement only one control scheme. Adopting a new control scheme requires redesign and rewiring of the c i r c u i t . A software based control loop, using d i g i t a l c ontrol algorithms, i s d r i f t free and can be changed simply by reprogramming. However i t i s d i f f i c u l t to duplicate the bandwidth and inherent p a r a l l e l i s m of the analog c i r c u i t with algorithms running on a si n g l e processor. Fortunately the bandwidth requirements of many motor control loops are f a i r l y low. For example, as discussed i n the previous chapter, the open loop speed response of a loaded induction motor i s dominated by a si n g l e electromechanical time constant. This time constant i s on the order of 20 to 60 milliseconds f o r a small ( 3 to 15 horsepower ), unloaded machine [50] and w i l l increase to several times t h i s value when the machine i s loaded. Assuming that the closed loop bandwidth of a speed control loop doesn't exceed the motor's open loop bandwidth, the loop bandwidth w i l l be on the order of 5 to 10 Hertz. For good response, sample rates for d i g i t a l c ontrol loops are usually set at 10 to 20 times the loop bandwidth [51, 52]. Thus a sample i n t e r v a l of 5 to 20 milliseconds can be expected f o r a speed con t r o l loop. This i s not beyond the c a p a b i l i t i e s of a 64 microprocessor, p a r t i c u l a r l y i f the control algorithm i s kept simple. In our case, the inverter c o n t r o l l e r i s intended for use i n a v a r i e t y of a p p l i c a t i o n s . It i s d i f f i c u l t to predict exactly the co n t r o l requirements of each p o t e n t i a l a p p l i c a t i o n . Therefore, the f l e x i b i l i t y inherent i n the software based control loop i s very a t t r a c t i v e . As a r e s u l t i t was decided that the basic c o n t r o l l e r would contain no analog control loops. Instead, an analog to d i g i t a l converter would be included to accept analog feedback and setpoint signals and the feedback control would be c a r r i e d out by programs i n the microprocessor. 3.6 System Protection Whether a p a r t i c u l a r system protection function can be handled by the microprocessor or must be performed by external c i r c u i t r y i s determined by the nature of the f a u l t condition the function i s supposed to deal with and by the design of the i n v e r t e r . Common fa u l t conditions that the protection functions must deal with are the following: a) Inverter shoot through or motor short c i r c u i t . An inve r t e r shoot through occurs when both switching devices i n one leg of the i n v e r t e r are on simultaneously. This can occur because of a defective device or inc o r r e c t switching s i g n a l s . A shoot through or motor short c i r c u i t i s characterized by a very rapid r i s e i n 65 current through one or more of the switching devices i n the i n v e r t e r . The magnitude of the current i s l i m i t e d only by the impedance of the wiring. b) Open motor phase. If a motor phase i s opened during operation, the current i n the other phases increases and thus some of the inverter switches w i l l carry increased current. The rate of r i s e and magnitude of the f a u l t current are not as large as for a short c i r c u i t . c) Motor overload. The motor can draw a current greater than the inverter r a t i n g i f the motor i s loaded beyond the drive's r a t i n g or i f the motor a c c e l e r a t i o n or deceleration rate i s too high. The rate of r i s e of current i s l i m i t e d by the speed that the motor s l i p frequency changes. d) Bus overvoltage on regeneration. When i n e r t i a l loads are decelerated, the k i n e t i c energy of the load i s regenerated back on to the DC bus of the i n v e r t e r . This energy must ei t h e r be dissipated or fed back to the AC bus. Otherwise the energy w i l l simply go into charging the bus f i l t e r capacitor u n t i l the bus voltage i s high enough to cause a breakdown i n some component. e) Inverter overheating. Improper i n s t a l l a t i o n of the i n v e r t e r or a f a i l u r e i n the cooling system can cause the i n v e r t e r to overheat. 6 6 The normal protective action when a shoot through, motor short, or open motor phase occurs, i s to turn the inve r t e r switches off as r a p i d l y as possible. If the f a u l t currents have a short r i s e time and the i n v e r t e r switches are t r a n s i s t o r s or power MOSFETs, the inve r t e r must be switched o f f i n a few microseconds i n order to prevent damage to the switching devices. Even with the use of an interrupt input i t i s d i f f i c u l t for a microprocessor to respond t h i s quickly. Therefore external protective c i r c u i t s are required to deal with these f a u l t s . However, a signal must be sent to the microprocessor, informing i t of the occurrence of the f a u l t . In the case of a motor overload, the speed of response does not have to be as f a s t since the rate of r i s e of f a u l t current i s lower and the magnitude of the f a u l t current i s lower. The required response depends on the exact nature of the f a u l t . In t h i s case the microprocessor can monitor the motor l i n e current and take the appropriate c o r r e c t i v e a c t i o n . A l t e r n a t i v e l y , i f the monitoring of motor current consumes too much processor time, external c i r c u i t s can be used to compare motor current to a l i m i t and send an interrupt sig n a l to the microprocessor i f the l i m i t i s exceeded. When an AC drive i s regenerating, the rate of r i s e of voltage on the DC bus i s l i m i t e d by the bus f i l t e r capacitor. The bus f i l t e r capacitor i s normally quite large and there i s normally a s u b s t a n t i a l safety margin on the bus voltage. As a r e s u l t there i s ample time f o r the microprocessor to take protective action once i t detects that the bus voltage has exceeded a l i m i t . Again, an external c i r c u i t that interrupts the microprocessor when the bus voltage exceeds the l i m i t can be used i f the continuous monitoring of bus voltage places too much of a demand on processor time. Overheating occurs very slowly when compared to the time span over which the other f a u l t conditions can occur. As a r e s u l t , the microprocessor can handle the protection function quite e a s i l y by sampling the inve r t e r temperature once every few seconds and turning the inve r t e r off i f the temperature exceeds a maximum l i m i t . 3.7 Pulse Width Modulation The pulse width modulation functions present more of a challenge to the microprocessor. Consider the software intensive pulsewidth modulation scheme shown i n Figure 18. The microcomputer programs the programmable timer so that i t generates an output with a frequency 360 times the output frequency of the i n v e r t e r . The programmable timer therefore interrupts the microcomputer 360 times per cycle of the inve r t e r output waveform. Each time the microcomputer i s interrupted, i t sends the switching pattern f o r the next i n t e r v a l of the i n v e r t e r output waveform to the p a r a l l e l output port. The r e s o l u t i o n of t h i s PWM scheme i s one degree since a l l pulses must be multiples 68 of one degree ( l/360th of a cycle ) long. This i s a r e l a t i v e l y coarse r e s o l u t i o n for a PWM waveform. Nevertheless, the demands on the microprocessor are quite severe. At an inverter frequency of 60 Hertz, the processor i s interrupted every 46 microseconds. Within the 46 microsecond i n t e r v a l the microprocessor must service the i n t e r r u p t , send the new switching pattern to the output port, and determine the switching pattern for the next i n t e r v a l . In addition, some time must be reserved for the other functions that the i n v e r t e r c o n t r o l l e r must perform. Casteel and Hoft [53] found that an I n t e l 8080 based c o n t r o l l e r using a PWM scheme s i m i l a r to the one just described would only operate to 55 Hertz despite the f a c t that a l l the switching waveforms were pre-calculated and stored i n memory and the c o n t r o l l e r performed no functions other than PWM waveform generation. j ~ i _ n _ n Clock Microcomputer Interrupt Input Data Programmable Timer Timer Out Data Parallel Output Port - A -A" -J3 -B -C •C Switching Signals To Inverter Figure 18 Software Intensive PWM Waveform Generator Obviously some of the PWM waveform generation must be performed by a u x i l i a r y hardware, p a r t i c u l a r l y since inverter output frequencies up to 400 Hertz are required. One approach i s to make use of programmable timers to generate the PWM pulses. The block diagram for one such system i s shown i n Figure 19. CLOCK Microcomputer. Interrupt Input Freq. Gen. Counter Phase A Counter Phase B Counter Phase C Counter Interrupt Counter Delay Time Am 9513 Programmable Counter/Timer ••A Upper -•A Lower » Delay Time - * B Upper - * B Lower Delay Time -•C Upper -#C Lower Figure 19 Counter/Timer Based PWM Waveform Generator The counter/timer 1C used i n t h i s design i s the Advanced Micro Devices Am 9513. The counters i n t h i s device can be set up so that each counter i s loaded a l t e r n a t e l y from one of two r e g i s t e r s upon reaching terminal count. In addition the counter output l i n e toggles at each terminal count. This allows the counters to be used as pulse width modulators. One r e g i s t e r i s loaded with the 70 "on time" of the pulse and the other r e g i s t e r i s loaded with the "off time", producing PWM waveforms such as those shown i n Figure 20. Phase A Phase B Phase C Interrupt Register 1 Count Register 1 Count Register 1 Count xLoad New Count Values Register 2 Count Register 2 Count Register 2 Count NT ^Load New Count Values Figure 20 Programmable Counter/Timer Output Waveforms In order to vary the duty cycle of the PWM waveform over a cycle of the the fundamental frequency, the microprocessor i s interrupted by the interrupt counter which generates pulses at the c a r r i e r frequency of the PWM waveform. On each i n t e r r u p t , the microprocessor loads new duty cycle values into the counter r e g i s t e r s . The inve r t e r output frequency i s determined by the Frequency Generator counter which i s programmed to supply a clock waveform which has a frequency which i s a multiple of the inver t e r output frequency. This clock frequency i s then counted 71 by the Phase Counters which generate the PWM signals and the Interupt Counter which generates the processor i n t e r r u p t s . The PWM signals generated by the counter/timer IC have only two states which means that one switch i n an inve r t e r leg must always be on. As a r e s u l t , extra c i r c u i t s must be added to i n s e r t the dead time required between the turning off of one switch i n an inver t e r leg and the turning on of the other switch. In t h i s PWM generation technique, the microprocessor must respond at a rate determined by the c a r r i e r frequency of the PWM waveform. In t h y r i s t o r based i n v e r t e r s , the c a r r i e r frequency i s usually kept below one k i l o h e r t z and the processor has a reasonable amount of time between interrupts to perform other tasks. Inverters using t r a n s i s t o r s or power MOSFETs as switches, on the other hand, may have maximum switching frequencies of 5 k i l o h e r t z or more. In t h i s case the time between interrupts which can be devoted to other tasks becomes rather short. Despite t h i s problem, several modulators using programmable timers i n conjunction with a microprocessor have been described i n the l i t e r a t u r e [54, 55, 56]. For most of these designs, the inve r t e r switching frequency i s l i m i t e d to a maximum of less than two k i l o h e r t z . In a d d i t i o n , many of them are designed s t r i c t l y as PWM modulators since there i s n ' t enough processing time a v a i l a b l e to carry out the other functions of an inve r t e r c o n t r o l l e r . In that case, the c o n t r o l l e r becomes a multimicroprocessor system with one microprocessor dedicated to the generation of the PWM signals and one or more other microprocesors dedicated to the 72 other c o n t r o l l e r functions [57]. Such an approach can d e l i v e r excellent performance but i s l i k e l y to be too large and complex fo r the submersible drive a p p l i c a t i o n . An a l t e r n a t i v e PWM scheme i s shown i n Figure 21. In t h i s case the switching waveform f o r an e n t i r e cycle i s stored i n read/write memory as a b i t pattern. This b i t pattern i s then read out of memory to the inverter switches at a rate proportional to the desired i n v e r t e r output frequency. By providing two banks of memory, one bank can be generating the inver t e r switching signals while the other bank i s being loaded with a new waveform by the microprocessor. This approach has the advantage that the microprocessor only has to update the waveform when a change i n inve r t e r output voltage i s required. Thus, when the inve r t e r i s running at constant frequency, the processor i s free to carry out other tasks. The microprocessor must generate new waveforms when the inve r t e r i s changing frequency i n order to maintain the volts/Hz r a t i o but there i s no absolute requirement on processor response time. Slow microprocessor response simply r e s u l t s i n a low slew rate for inverter output frequency. The maximum possible inve r t e r output frequency i s determined by the length of the waveform storage memory and by i t s access time. If we assume the memory i s 2048 locations long and the minimum time between accesses to successive locations i s 500 nanoseconds, 73 Programmable Counter/Timer Micro-Processor Used To Select Source Of Waveform Memory Addresses Inverter Output Frequency Command Memory Dota Outputs Used To Select Waveform Ram Which Contains Current Waveform F i g u r e 21 Memory I n t e n s i v e PWM Waveform G e n e r a t o r then the minimum length of one inverter output cycle i s 1024 microseconds. This corresponds to an inver t e r output frequency of approximately one k i l o h e r t z . The length of the the waveform storage memory determines the r e s o l u t i o n possible i n the inverter switching i n t e r v a l s . For example, a memory with 2048 locations provides a r e s o l u t i o n of 0.176 degrees i n the inver t e r switching angles and allows a minimum pulsewidth that i s approximately .0005 of the period of the fundamental. This kind of r e s o l u t i o n i s more than adequate over most of the i n v e r t e r operating range but, s u r p r i s i n g l y , may not be good enough at low output frequencies. Consider the case where the inver t e r output frequency i s 5 Hertz and the desired switching ( c a r r i e r ) frequency i s 1000 Hertz. There w i l l be 200 pulses per cycle of the inver t e r output waveform. Each pulse can only take on one of ten (2048/200) d i s c r e t e widths. This only allows coarse control of the output voltage. By using memories with short access times, the length of the waveform storage memory can be increased s u b s t a n t i a l l y (up to 16384 locations) while s t i l l allowing i n v e r t e r operation to 400 or 500 Hertz. This a l l e v i a t e s the r e s o l u t i o n problem at low inver t e r output frequencies but also increases the time required to load a new waveform i n t o the waveform memory. A number of PWM c o n t r o l l e r s based on some v a r i a t i o n of the basic scheme just discussed have been described [58, 59, 60]. Probably the p r i n c i p a l drawback to a l l of them i s the large number of 75 components required to implement t h i s technique. At an early stage i n the development of the c o n t r o l l e r f o r the submersible drive, a prototype PWM waveform generator of the type just described was constructed i n order to gain some f a m i l i a r i t y with this technique and to evaluate i t s s u i t a b i l i t y f o r the submersible drive a p p l i c a t i o n . The prototype was constructed on an I n t e l SDK-85 microcomputer evaluation board which uses the I n t e l 8085 microprocessor. Schematics for the PWM generator portions of the c i r c u i t are shown i n Figures 22 and 23. The two waveform memory banks each consist of three IK x 1 RAMs organized as 1024 locations containing three b i t s each. The memory length i s too short for good r e s o l u t i o n at low inve r t e r output frequencies but was considered adequate for i n i t i a l experimentation. The RAM bank that i s currently supplying the inve r t e r switching signals i s addressed by a 10 b i t counter formed from 74LS163 binary counters. The counter i s clocked by a frequency synthesizer c i r c u i t c o n s i s t i n g of a CD4046 phase locked loop and an I n t e l 8253 counter/timer. A frequency synthesizer i s used so that the output frequency can be changed i n small f i x e d s i z e increments. In t h i s design the increment was 0.5 Hz. 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CAT CJft CA^ 5 2 5 C 10 |l 14 1} 74L<>^7 (s) 4 7 . 9 : 12-T T I Z 3 * 2.5 <» 1011 14 n 741.^ 1-j 7 ( ? ) 4 7 9 12. •' More.1 FOE AIL 'CW)7'l • © — = £ : B I T 1 oF Feer4> (BAUtuvrrtvH) ® C0UU6CTED TO <^ UP. J © COHUECTfeO TO Vcc |Ad> U l IA2. IA^  IA4 IAS IA7 IA& IA<) 2A4> 2AI 2AZ 2A^ 2A4 2A5 ZAU 2A7 2Afc 2A<) OPER.No. DATE REVISION OPER.No. DATE REVISION KEY PROCESS OPERATION PREPARED BY AKCHIDB DATE ORIG. ISSUE MAKHI7 SEQUENCE TOOLING RELATIONSHIP APPROVED BY DATE SHEET 2. OF ^ MAf I4/«I EEV.FW. K.ktAuflH C A - OPERATION F R E Q U E N C Y S Y N T H E S I Z E R & A D D R E S S G E N E R A T I O N OPER. NO. ELEMENTS ELEMENTS ELEMENTS F i g u r e 22 P r o t o t y p e PWM Waveform G e n e r a t o r P a r t 1 OPER.No. DATE REVISION OPER.No. DATE REVISION KEY PROCESS OPERATION PREPARED BY AfcOHIPE DATE ORIG. ISSUE SEQUENCE TOOLING RELATIONSHIP APPROVED BY DATE SHEET 3 OF 5 MAY U OPERATION OPER. NO. ELEMENTS ELEMENTS ELEMENTS VAYEfOELM EANf? AMD OUTPUT F i g u r e 2 3 P r o t o t y p e PWM Waveform G e n e r a t o r P a r t 2 The 8085 microprocessor selects the RAM bank that i s currently supplying the in v e r t e r signals with the BANKSWITCH s i g n a l . This s i g n a l controls a set of 74LS157 multiplexers that apply the counter outputs to the currently a c t i v e RAM bank's address l i n e s and apply the 8085 address l i n e s to the other RAM bank. Another 74LS157 applies appropriate c o n t r o l signals to the RAM banks. The RAM bank that i s not currently supplying the inverter switching signals i s set up so that the microprocessor can write data to i t . The microprcessor loads the RAM bank with the next switching pattern to be generated. In th i s design, the PWM technique employed i s the harmonic elimination technique developed by Patel and Hoft. The required switching angles to eliminate the 5th, 7th, and 11th harmonics while c o n t r o l l i n g the amplitude of the fundamental at 5% i n t e r v a l s from 0 to 100% are l i s t e d i n Patel's thesis [61]. These values were used to develop switching patterns for the f i r s t 90 degrees of the three phase output waveform. These 20 patterns were then stored i n EPROM. Due to the quarter and h a l f wave symmetry of the PWM switching patterns, i t i s easy to generate the switching patterns f o r the remaining 270 degrees of the three phase waveform from the stored switching pattern f o r the f i r s t 90 degrees. When the d i r e c t i o n of r o t a t i o n must be reversed, the phase sequence of the generated three phase waveform i s reversed by loading the switching pattern into RAM i n descending order from the highest RAM address to the lowest RAM address. 79 The PWM modulator was tested with both t r a n s i s t o r and power MOSFET i n v e r t e r s . On the whole the performance was s a t i s f a c t o r y . However, there were a few problems. At low frequencies there were high peak currents i n the in v e r t e r switches. This was due to the fac t that the PWM technique chosen only eliminated the 5th, 7th, and 11th harmonics and exercised no control over the remaining higher order harmonics. This problem can be resolved by adopting a PWM technique that controls more of the harmonics at low output frequencies. For example, the harmonic eli m i n a t i o n technique could be extended to eliminate the 5th, 7th, 11th, 13th, 17th, and 19th harmonics. This would probably require a longer waveforn memory i n order to allow for the a d d i t i o n a l r e s o l u t i o n required i n the switching angles. A less t r a c t a b l e problem i s the amount of c i r c u i t r y required to implement t h i s PWM generator. The equivalent ( i n board space) of approximately 30 16 pin ICs were required for the PWM generator. This does not include the microprocessor and i t s associated components such as program storage EPROM, RAM, and bus d r i v e r s . After adding these components and the components required to support the other i n v e r t e r c o n t r o l l e r functions, the t o t a l chip count would probably approach the equivalent of 50 16 p i n ICs. A c o n t r o l l e r with t h i s many components would require two or three of the 218 mm. by 77 mm. c i r c u i t cards that are to be used i n the submersible. The i d e a l way to reduce the chip count i s to integrate the PWM 80 generator on to a single chip. At the time that the design of the inve r t e r c o n t r o l l e r was started (Spring of 1981), f a c i l i t i e s were not available at UBC for the design and f a b r i c a t i o n of an integrated c i r c u i t of the required complexity. PWM c i r c u i t s that were commercially a v a i l a b l e were designed for switching power supplies and were completely unsuitable for three phase i n v e r t e r a p p l i c a t i o n s . It appeared that a r e l a t i v e l y high component count for the PWM generator would have to be accepted. Fortunately, just as the design of an improved version of the PWM generator just described was beginning, a PWM generator IC designed s p e c i f i c a l l y f o r AC motor drive applications was announced. The HEF4752 AC Motor Co n t r o l l e r IC [62] i s manufactured by P h i l i p s and i s d i s t r i b u t e d i n North America by Signet i c s . Samples of t h i s device and a l l the a v a i l a b l e documentation on the device were obtained i n order to assess i t s s u i t a b i l i t y for our a p p l i c a t i o n . The device has the following basic features: a) It uses a "regular sampling" PWM technique [63]. This produces a waveform and harmonic content s i m i l a r to that produced by the t r i a n g l e intercept PWM technique. b) The c a r r i e r frequency to fundamental frequency r a t i o i s changed i n integer steps at d i s c r e t e points i n the output frequency range i n order to keep the c a r r i e r frequency between a minimum and 81 maximum value. This prevents both very low c a r r i e r frequencies which would r e s u l t i n increased harmonic currents and very high c a r r i e r frequencies which would re s u l t i n increased i n v e r t e r switching losses. c) Signals can be generated to control t h y r i s t o r inverters as well as t r a n s i s t o r and power MOSFET in v e r t e r s . d) Inputs are availabe to control the invert e r output frequency, the volts/Hz r a t i o , the maximum c a r r i e r frequency, the phase sequence of the three phase waveform, and the delay between the switching of the upper and lower devices i n an in v e r t e r l e g . The maximum in v e r t e r output frequency that the device can produce i s s p e c i f i e d as 200 Hz i n the documentation. However, i n tests on samples from two d i f f e r e n t production l o t s , a l l devices worked to output frequencies well above 400 Hz. On the whole the HEF4752 seems to meet our needs admirably. There are only two drawbacks to the use of the device. F i r s t , one must accept the PWM strategy chosen by the designers of the IC since the device i s not programmable. However, the technique used gives very good r e s u l t s so t h i s i s only a disadvantage i n research applications where the e f f e c t s of d i f f e r e n t modulation techniques are being evaluated. Since the invert e r c o n t r o l l e r i s designed 82 p r i m a r i l y f or i n d u s t r i a l use, t h i s i s not a severe handicap i n our case. The second problem i s that the control signals f or the inve r t e r output frequency, volts/Hz r a t i o , and maximum c a r r i e r frequency are frequencies. For use i n a microprocessor based system i t would be better i f the device had a p a r a l l e l d i g i t a l input instead which would accept binary numbers as control inputs. Such a device has been designed by Hitachi [64] but i t i s not a v a i l a b l e on the open market. However, d i g i t a l l y c o n t r o l l e d frequency generators are r e l a t i v e l y easy to design so t h i s i n t e r f a c i n g problem i s not a major obstacle to the use of the HEF4752. Since the use of the HEF4752 PWM generator IC r e s u l t s i n a substantial reduction i n the chip count of the inve r t e r c o n t r o l l e r and also reduces the software design e f f o r t and since the use of the device presents no s i g n i f i c a n t disadvantages, i t was decided to base the PWM generation portion of the i n v e r t e r c o n t r o l l e r on this device. The primary r i s k with this decision i s that the device i s a v a i l a b l e only from a single source. If the device were to be discontinued or i f the design of the device was changed so that i t no longer operated to 400 Hz, the inve r t e r c o n t r o l l e r would have to be completely redesigned. Since the applications of t h i s i n v e r t e r c o n t r o l l e r are i n s p e c i a l i z e d , low volume applications i t i s possible to buy enough of the devices i n advance to ensure a s u f f i c i e n t supply for several years of 83 production. 3.8 Basic C o n t r o l l e r Architecture With the basic tradeoffs made on what c o n t r o l l e r functions w i l l be performed by software and what functions w i l l be performed by dedicated hardware, i t i s possible to develop a system architecture f o r the in v e r t e r c o n t r o l l e r . This architecture i s shown i n Figure 24. The basic components of the system are: a) Microcomputer. This i s the heart of the c o n t r o l l e r and consists of the microprocessor, i t s clock c i r c u i t , RAM, EPROM, and any required buffer c i r c u i t s . It also includes interrupt inputs f or a real-time clock and for f a u l t signals from the inv e r t e r . b) Real-time clock. This interrupts the microcomputer at regular i n t e r v a l s . It i s used i n c o n t r o l l e r functions that need timing information. For example,when the in v e r t e r i s started, the DC bus capacitor must be allowed to charge through a r e s i s t o r for a defined time before the main contactor applies power to the DC bus. c) A/D converter. This i s used to accept inputs such as control setpoints and signals from the invert e r and motor. d) P a r a l l e l input port. This can be used ei t h e r as an input f o r 84 A/D Converter CO Input Port Microcomputer Microcomputer Data Bus Output Port • f i t ? Real Time Clock Programmable Frequency Generator Pulse Width Modulator IC Opto-coupler Drivers f t f I f t F i g u r e 24 I n v e r t e r C o n t r o l l e r A r c h i t e c t u r e p a r a l l e l binary data from a higher l e v e l c o n t r o l l e r or as inputs f o r switches and other i n d i v i d u a l binary s i g n a l s . e) P a r a l l e l output p o r t . This i s used as an output f o r c o n t r o l s i g n a l s f o r the PWM generator IC and f o r i n v e r t e r components such as c o n t a c t o r s . f ) Programmable frequency generator. This supplies the command frequencies f o r i n v e r t e r output frequency, volts/Hz r a t i o , and maximum device s w i t c h i n g frequency to the PWM generator IC under c o n t r o l of the microcomputer. g) Pulse Width Modulator IC. The P h i l l i p s HEF4752 generates the i n v e r t e r s w i t c h i n g waveforms under the c o n t r o l of the microcomputer. h) Opto-coupler d r i v e r s . These supply the current to d r i v e the opto-couplers on the c i r c u i t s that c o n t r o l the i n v e r t e r switching devices. Given t h i s b a s i c a r c h i t e c t u r e , i t i s now p o s s i b l e to discuss i n d e t a i l the design of the i n v e r t e r c o n t r o l l e r hardware. 86 Chapter 4 Cont r o l l e r Hardware Design With the basic architecture of the invert e r c o n t r o l l e r defined, and the decisions made on implementation of c o n t r o l l e r functions, the next step was the detai l e d design of the c o n t r o l l e r c i r c u i t . The design was c a r r i e d out with close attention to the number of integrated c i r c u i t s required. The goal was to obtain acceptable performance from a minimum number of ICs so that the c o n t r o l l e r would be r e l i a b l e , compact, and inexpensive The goal was achieved through use of large scale integrated c i r c u i t s . The microcomputer i n the c o n t r o l l e r consists of an Int e l 8085 microprocessor, a 4 kbyte EPROM memory, and an In t e l 8156 IC that provides read/write memory and I/O l i n e s . The microcomputer i s interfaced to an ADC0808 analog to d i g i t a l converter IC that provides eight analog input l i n e s to the c o n t r o l l e r . The microcomputer i s also interfaced to the HEF4752V PWM generator IC that a c t u a l l y generates the invert e r switching s i g n a l s . The c o n t r o l l e r i s very compact, f i t t i n g on a single 7.5 cm by 21.5 cm printed c i r c u i t board. Only 18 integrated c i r c u i t s are required, r e s u l t i n g i n an estimated parts cost (including the c i r c u i t board) of under $160 when the parts are purchased i n 87 small q u a n t i t i e s . The d i r e c t labor cost to assemble the c o n t r o l l e r board i s estimated to be under $25. Published descriptions of i n v e r t e r c o n t r o l l e r s r a r e l y include information on the s i z e or cost of the design. However, based on what information i s a v a i l a b l e , i t i s apparent that the c o n t r o l l e r described i n t h i s thesis i s among the most compact and least expensive. Despite the small s i z e and low cost of the c o n t r o l l e r hardware, the performance and f l e x i b i l i t y of the c o n t r o l l e r are more than adequate. The c o n t r o l l e r can c o n t r o l PWM inverters using t r a n s i s t o r s , power MOSFETs, or t h y r i s t o r s as switches over a frequency range of at l e a s t 2 Hz to 400 Hz with a r e s o l u t i o n of 0.5 Hz. The volts/Hz r a t i o can be adjusted over at least a 10 to 1 range. Analog and d i g i t a l inputs are a v a i l a b l e f o r c o n t r o l and feedback s i g n a l s . Four interrupt inputs are a v a i l a b l e for f a u l t signals from the i n v e r t e r . Nine d i g i t a l output l i n e s are a v a i l a b l e to c o n t r o l i n v e r t e r and control panel components. F i n a l l y , there i s provision i n the design to expand the c o n t r o l l e r since the microcomputer data l i n e s , control l i n e s , and low order address l i n e s are brought to connectors on the edge of the printed c i r c u i t board. 4.1 Microcomputer C i r c u i t This stage started with the s e l e c t i o n of the microcomputer components. Three factors influenced the choice of 88 microprocessor. In ascending order of importance, they are: i ) the speed and computational power of the microprocessor i i ) the number and size of chips required f o r a complete microcomputer system i i i ) the a v a i l a b i l i t y of low cost software and hardware development tools The f a s t e r and more powerful the microprocessor, the more the c o n t r o l l e r can do before serious degradation of response time occurs. Computational power i s most important when the c o n t r o l l e r i s performing closed loop c o n t r o l . Control algorithms make heavy use of multiply and divide operations. If the time required f o r these operations can be decreased, e i t h e r the control loop bandwidth or the complexity of the con t r o l algorithm can be increased. Minimizing the number and s i z e of chips required to make up a complete microcomputer i s important because of the s i z e constraints imposed by the submersible a p p l i c a t i o n . A s i n g l e chip microcomputer i s the best choice i n th i s regard. A microprocessor that can function with a few highly integrated support chips makes an acceptable second choice. 89 The a v a i l a b i l i t y of good, low cost software and hardware development tools for the microprocessor i s important for two reasons. F i r s t , the budget f o r the development of the inverter c o n t r o l l e r was not large enough to allow the purchase of expensive microcomputer development systems. Development had to be performed with equipment already a v a i l a b l e at UBC or with equipment that could be purchased at low cost. Second, once the design was complete, i t was to be transferred to a small company which would manufacture submersible drives and other AC motor drives based on t h i s c o n t r o l l e r . Since one of the virtues of the c o n t r o l l e r i s i t s programmability, the company also has to have software development f a c i l i t i e s for the microprocessor. Again, money was not a v a i l a b l e f o r the company to purchase an expensive software development system. The combination of the three factors narrowed the l i s t of p o t e n t i a l microprocessors considerably. The 16 b i t microprocessors r e a d i l y a v a i l a b l e at the time (the l a t t e r half of 1981) required too many support chips and, with the exception of the T l 9900, were not supported by the microcomputer development f a c i l i t i e s at UBC. The s i t u a t i o n has changed. Newer microprocessors such as the I n t e l 80188 have most of t h e i r support c i r c u i t s integrated on the microprocessor chip. In addition, inexpensive personal computers can be used to develop software for the 80188 since many of them use the software compatible I n t e l 8088 microprocessor. 90 Single chip microcomputers also had to be eliminated due to the lack of low cost development f a c i l i t i e s . Again t h i s s i t u a t i o n has changed. Cross-assemblers which run on personal computers are now a v a i l a b l e f o r several s i n g l e chip computers. Of the microprocessors f or which hardware and software development f a c i l i t i e s were a v a i l a b l e at UBC, the Intel 8085 microprocessor was the most a t t r a c t i v e f o r t h i s a p p l i c a t i o n . The 8085 b a s i c a l l y has the same i n s t r u c t i o n set as the I n t e l 8080 microprocessor. A large amount of development software i s ava i l a b l e for the 8080 family of microprocessors. At UBC, assemblers and a compiler f o r the PL/M programming language are a v a i l a b l e . Relocating macro-assemblers and compilers for the C, Pascal, Forth, Fortran, and Basic programming languages are ava i l a b l e on personal computers that use the popular CP/M operating system. On the hardware side, the 8085 has support chips a v a i l a b l e which allow the construction of a small microcomputer system with I/O ports, EPROM and RAM memory, and a programmable timer, using only three or four ICs. For an 8 b i t microprocessor, the 8085 has an unusually powerful in t e r r u p t system which has 5 interrupt inputs and on-chip p r i o r i t y a r b i t r a t i o n . This i s a useful feature since the design of the inver t e r protection functions c a l l s f o r the use of i n t e r r u p t signals generated by f a u l t detection c i r c u i t s i n the i n v e r t e r . 91 A f i n a l advantage of the 8085 was f a m i l i a r i t y . I had used the 8085 i n other microprocessor based systems and was f a m i l i a r with i t s assembly language and hardware features. Therefore the design time on t h i s project could be devoted to tasks other than learning about a new microprocessor. The major drawback to the use of the 8085 microprocessor i s i t s r e l a t i v e l y l i m i t e d processing power. The 8085 i s not as powerful as the new 16 b i t microprocessors or some of the new single chip microcomputers such as the In t e l 8051. Its most notable deficiency i s the lack of multiply and divide i n s t r u c t i o n s i n i t s i n s t r u c t i o n set. However, previous experience with the processor and some preliminary estimates of the processing requirements f o r the inverter c o n t r o l l e r a p p l i c a t i o n suggested that the processing power of the 8085 would be adequate. This has proved to be true for the applications i n which the invert e r c o n t r o l l e r has been used to date. With the microprocessor chosen, design of the remainder of the microcomputer section of the c o n t r o l l e r could proceed. The schematic diagram f o r the microcomputer section i s shown i n Figure 25. The 8085 has i n t e r n a l clock generation c i r c u i t s so only a c r y s t a l and two small capacitors are required to complete the clock generator. A l l versions of the invert e r c o n t r o l l e r b u i l t to date have used an 8085 running at a 3 MHz clock frequency. However i t 92 J 1 1 rr^ I.IK vv RI "GO u(7T")— O—flay* - G i D — o a * o * — G D f « —( )to -GiD Figure 25 Microcomputer Section of Inverter C o n t r o l l e r would be very easy to upgrade to the 8085A-2 which runs at c lock frequencies up to 5 MHz i f an a p p l i c a t i o n required the extra speed. The power-on reset c i r c u i t i n t h i s design i s convent ional . P r o v i s i o n i s made for the add i t i on of a reset switch or some other external reset s i g n a l source. The 8085 has f i v e i n t e r r u p t i n p u t s . In the i n v e r t e r c o n t r o l l e r , the TRAP i n t e r r u p t input , which i s non-maskable and has highest p r i o r i t y , i s dedicated to f a u l t s i gna l s from the i n v e r t e r . The INT 7.5 i n t e r r u p t , which i s next highest i n p r i o r i t y , i s dedicated to the rea l - t ime c lock s i g n a l , as described below. The INT 6.5 input can be connected e i t h e r to the END OF CONVERSION s i g n a l from the A/D convertor or to f a u l t s i gna l s from the i n v e r t e r . The remaining two i n p u t s , INT 5.5 and INTR, can a l so be connected to f a u l t s igna l s from the i n v e r t e r . The I n t e l 8156 RAM and I/O Expander IC suppl ies the microcomputer with 256 bytes of read/wri te memory, 22 b i d i r e c t i o n a l I/O l i n e s , and a rea l - t ime c l o c k . At f i r s t g lance, 256 bytes of read /wr i te memory appears i n s u f f i c i e n t . However, the i n v e r t e r c o n t r o l l e r has no need to s tore large amounts of informat ion . During the i n i t i a l design of the c o n t r o l l e r i t was estimated that the number of v a r i a b l e s to be stored at any one time would not exceed 50 and that most of these would be s i n g l e byte v a r i a b l e s . This estimate has been borne out i n p r a c t i c e , l ack of read/wri te 94 memory has not proved to be a problem so f a r . The I/O l i n e s on the 8156 are organized into two eight l i n e ports (Port A and Port B) and one six l i n e port (Port C). Port B and Port C are set up as output ports. Five l i n e s from these ports are used f o r c o n t r o l functions within the c o n t r o l l e r . The remaining l i n e s are a v a i l a b l e to c o n t r o l components such as contactors i n the i n v e r t e r or to control i n d i c a t o r lamps on the control panel. Port A i s set up as an input port. Its eight l i n e s are a v a i l a b l e for use as a p a r a l l e l d i g i t a l input to accept speed commands from the submersible c o n t r o l l e r . The eight l i n e s can also be used to accept i n d i v i d u a l l o g i c inputs from switches or comparators. The 8156 i s equipped with a 14 b i t programmable counter/timer. In t h i s design the input to the counter i s a clock frequency from an Am9513 counter/timer IC on the c o n t r o l l e r board. The output of the counter i s connected to the INT 7.5 interrupt input on the microprocessor. The counter i s programmed to act as a real-time clock which interrupts the microcomputer at regular i n t e r v a l s . I n t e l manufactures a companion chip to the 8156, the 8755, which incorporates EPROM memory and more I/O l i n e s . However the chip only conta ins 2K bytes of EPROM yet i s packaged i n a 40 pin package. For about the same board area i t i s possible to include a 2732 EPROM which contains 4K bytes and the 8212 l a t c h required to demultiplex the 8085 address bus. This was the option chosen 95 since the extra I/O l i n e s provided by the 8755 were not required. So f a r , 4K bytes of EPROM has proved adequate for program storage. However, f i t t i n g the program into t h i s space has occasionally been a b i t of a squeeze. Programs for more complex applications of the c o n t r o l l e r are l i k e l y to require more storage. At the time, the 2732 was the highest capacity EPROM that was r e a d i l y a v a i l a b l e . Since that time, EPROMs with capacities up to 32K byte have appeared on the market. These devices use a 28 pin package that i s la r g e r than the 24 pin package used by the 2732. However i t should be possible to f i t one of these devices on the same board by replacing the 8212 la t c h , which i s housed i n a 24 pin package, with a 74LS373 la t c h which i s housed i n a smaller 20 p i n package. 4.2 Interface to the HEF4752V PWM Generator IC The microcomputer i s interfaced to two other elements of the inverter c o n t r o l l e r ; the PWM generator IC and the analog to d i g i t a l converter. The int e r f a c e to the P h i l i p s HEF4752V PWM generator IC i s the more complex of the two. The HEF4752V (Figure 26 [65]) has 7 single b i t binary control inputs and 4 clock frequency c o n t r o l inputs. The 7 single b i t inputs are l a b e l l e d I, K, L, CW, A, B, and C by the manufacturer. Four of these inputs can be t i e d permanently high or low. The l o g i c l e v e l on input I determines whether 96 0BC1 1 u 28 V D D 0BM2 2 27 OBC2 0BM1 3 26 VAV RCT 4 25 1 CW 5 24 L OCT 6 23 RSYN K 7 HEF4752V 22 OYM1 ORM1 8 21 OYM2 ORM2 9 20 OYC1 ORC1 10 19 OYC2 ORC2 11 18 CSP FCT 12 17 VCT A 13 * 16 C VSS 14 15 B 7Z76992 HEF4752VP: 28-lead DIL; plastic (SOT-117). HEF4752VO: 28-lead DIL; ceramic (SOT-135). PINNING tnputt; group I Inputs; group II 24- L data 12 - FCT frequency clock 25- I data 17-VCT voltage clock 7 - K data 4 - RCT reference clock 5-CW data 6 - OCT output delay 13 - A data clock 15-B data 16-C data Outputs; group I 23 - RSYN R-phase synchronization 26 - VAV average voltage 18 - CSP current sampling pulses Outputs; group II 8 -ORM1 R-phase main 9 -ORM2 R-phase main 10 -ORC1 R-phase commutation 11 -ORC2 R-phase commutation 22 -OYM1 Y-phase main 21 -OYM2 Y-ph8$e main 20 -OYC1 Y-phase commutation 19 -OYC2 Y-phase commutation 3 -OBM1 B-phase main 2 -OBM2 B-phase main 1 -OBC1 B-phase commutation 27 -OBC2 B-phase commutation SUPPLY VOLTAGE rating recommended operating HEF4752V -0,5 to 18 4,5 to 12,5 V FAMILY DATA see Family Specifications Figure 26 P h i l i p s HEF4752V Inputs and Outputs 97 t h e o u t p u t s i g n a l s p r o d u c e d b y t h e I C a r e o f a t y p e s u i t a b l e f o r d r i v i n g a t r a n s i s t o r ( o r p o w e r M O S F E T ) i n v e r t e r o r o f a t y p e s u i t a b l e f o r d r i v i n g a t h y r i s t o r i n v e r t e r . I n t h e t r a n s i s t o r m o d e t h e s i g n a l t o t u r n a s w i t c h i n g d e v i c e o n i s m a i n t a i n e d c o n t i n u o u s l y d u r i n g t h e i n t e r v a l t h a t t h e d e v i c e i s o n . I n t h e t h y r i s t o r mode t h e o u t p u t s i g n a l t o t u r n a d e v i c e o n b e c o m e s a p u l s e t r a i n . T h i s f a c i l i t a t e s t h e u s e o f p u l s e t r a n s f o r m e r s f o r v o l t a g e i s o l a t i o n . I n t h e i n v e r t e r c o n t r o l l e r , t h i s i n p u t i s t i e d e i t h e r h i g h o r l o w b y a j u m p e r , d e p e n d i n g o n w h a t t y p e o f i n v e r t e r i s t o b e c o n t r o l l e d . I n p u t K i s u s e d w i t h o n e o f t h e c l o c k f r e q u e n c y c o n t r o l i n p u t s t o c o n t r o l t h e d e l a y o r i n t e r l o c k p e r i o d b e t w e e n t h e s w i t c h i n g o f t w o d e v i c e s i n t h e s a m e l e g o f t h e i n v e r t e r . A g a i n t h i s i n p u t c a n b e t i e d e i t h e r h i g h o r l o w b y a j u m p e r , d e p e n d i n g o n t h e i n t e r l o c k p e r i o d d e s i r e d . I n p u t s B a n d C a r e u s e d o n l y d u r i n g t h e t e s t i n g o f t h e d e v i c e b y t h e m a n u f a c t u r e r . I n t h e i n v e r t e r c o n t r o l l e r t h e y a r e b o t h t i e d l o w . T h e r e m a i n i n g t h r e e s i n g l e b i t i n p u t s m u s t b e c o n t r o l l e d b y t h e m i c r o p r o c e s s o r . T h e L i n p u t i s a n o n / o f f c o n t r o l . When L i s l o w , t h e o u t p u t o f i n v e r t e r s w i t c h i n g s i g n a l s f r o m t h e I C i s d i s a b l e d . T h e o u t p u t s w h i c h c o n t r o l i n v e r t e r s w i t c h i n g go l o w . W h e n L i s h i g h , t h e i n v e r t e r s w i t c h i n g s i g n a l s a r e e n a b l e d . T h i s i n p u t a l l o w s a l l t h e i n v e r t e r s w i t c h e s t o b e t u r n e d o f f i n t h e e v e n t o f a f a u l t o r i n c a s e s w h e r e t h e i n v e r t e r i s t o b e i n a c t i v e . T h e CW i n p u t c o n t r o l s t h e p h a s e s e q u e n c e o f t h e t h r e e p h a s e w a v e f o r m g e n e r a t e d b y t h i s I C . T h i s i s u s e d t o c o n t r o l t h e d i r e c t i o n o f m o t o r r o t a t i o n . F i n a l l y , t h e A i n p u t i s u s e d t o 98 reset the HEF4752V IC to a defined i n i t i a l state when the c o n t r o l l e r i s f i r s t switched on. These three inputs are connected to Port B on the 8156 so that they can be controlled by the microcomputer. The four clock frequency inputs to the HEF4752V are l a b e l l e d FCT, VCT, RCT, and OCT by the manufacturer. Two of these clock frequencies are normally kept constant f o r a p a r t i c u l a r a p p l i c a t i o n . The frequency of the RCT clock sets l i m i t s to the maximum and minimum invert e r switching frequencies over a wide range of invert e r output frequencies. This i s done by changing the r a t i o of c a r r i e r (switching) frequency to modulation (output) frequency i n discrete steps as the output frequency changes. The ra t i o s used by the chip are 168, 120, 84, 60, 42, 30, 21, and 15. The s e l e c t i o n of the RCT clock frequency (f^rjx^ determines the output frequencies at which the c a r r i e r to modulation frequency r a t i o s w i l l be changed. The formula for se l e c t i n g fRCT i s (25) fRCT = 2 8 0 x fs(max) where f s ( m a x ) i - s the desired maximum switching frequency. The value for f R f j j w i l l be d i f f e r e n t f o r inverters using d i f f e r e n t types of switching devices but w i l l remain constant for a p a r t i c u l a r a p p l i c a t i o n . The OCT clock frequency input i s used i n conjunction with the 99 binary input K to set the i n t e r l o c k delay period required between the on time of one switch i n an in v e r t e r leg and the on time of the other switch i n the le g . When the K input i s low, the formula for the i n t e r l o c k delay period i s (26) Interlock delay (seconds) = 8/fQ^^, where fgcT ^ s t n e frequency of the OCT clock. When the K input i s high, the formula f o r the i n t e r l o c k delay period i s (27) Interlock delay (seconds) = 16/fQ,-.rp The i n t e r l o c k delay period required w i l l vary depending on the switching speed of the power devices i n the i n v e r t e r . However, the i n t e r l o c k delay period w i l l not vary for a p a r t i c u l a r a p p l i cation so fgrj^ can be kept constant f o r that a p p l i c a t i o n . The remaining two clock frequency control inputs require variable clock frequencies. The FCT clock input controls the invert e r output frequency. The formula r e l a t i n g the clock frequency f-pCT t o t' i e o u t P u t frequency f Q u t i s (28) fFCT = 3 3 6 0 x fout In the submersible drive, f Q u t (and therefore fp^T^ varies from about 2 Hz to 400 Hz. This i s a range of 200 : 1. 100 The VCT clock input controls the i n v e r t e r volts/Hz r a t i o . The nominal value of the VCT clock frequency fyrj^ determines the output frequency at which the i n v e r t e r achieves 100% modulation. This nominal value can be calculated as follows: (29) f V C T(nom) = 6720 x f o u t ( 1 0 0 % modulation) With fycT f i x e d at t h i s value, the inverter output voltage w i l l be a l i n e a r function of the output frequency up to the 100% modulation point. After that, the voltage r i s e s i n a non-linear fashion as the i n v e r t e r waveform makes the t r a n s i t i o n from a sinusoidal PWM waveform to an unmodulated s i x step square wave. Depending on the motor being driven, the frequency at which 100% modulation i s desired can range from 50 Hz to 400 Hz. Thus VCT must be variable over about a 10 to 1 range. In addition, v a r i a t i o n i n the volts/Hz s e t t i n g may be required during operation at low frequencies due to the increased e f f e c t of the stator resistance IR drop on the a i r gap f l u x . The method of generating the clock frequencies f o r the FCT and VCT inputs requires some consideration. The FCT input requires p a r t i c u l a r a t t e n t i o n . The output frequency of the i n v e r t e r must be c o n t r o l l e d over a range of 2 Hz to 400 Hz. In addition, the frequency must be changed i n small steps. Each step change i n inve r t e r output frequency i s also a step change i n motor s l i p frequency. This change i n s l i p frequency causes a change i n 101 motor torque and therefore i n motor current. If the step i s too large, large transient currents w i l l occur. Step changes i n frequency should be kept to a f r a c t i o n of the normal s l i p frequency. A 0.5 Hz step s i z e i s a good choice for small induction motors. This r e s u l t s i n the requirement that the fprjx c l ° c k source generate approximately 800 frequencies evenly spaced between 6720 Hz (2 Hz output) and 1,344,000 Hz (400 Hz output). In the case of the VCT si g n a l i t i s desirable to be able to change i t s frequency i n small steps (for example, 5%) around the nominal frequency. This a b i l i t y i s required when the c o n t r o l l e r i s performing closed loop co n t r o l of machine a i r gap f l u x or when the c o n t r o l l e r i s compensating f o r fluctuations i n the input voltage to the i n v e r t e r . The frequency range required f o r the VCT clock i s from 336,000 Hz (100% modulation at 50 Hz output frequency) to 2,688,000 Hz (100% modulation at 400 Hz output frequency). Generat ion of the FCT and VCT clock frequencies under control of the microcomputer can be achieved by three techniques: i ) programmable counter d i v i d i n g a f i x e d clock frequency i i ) binary rate m u l t i p l i e r d i v i d i n g a f i x e d clock frequency i i i ) phase-locked loop frequency m u l t i p l i e r operated as a 102 d i g i t a l l y c o n t r o l l e d frequency synthesizer Using a programmable counter i s not a viable a l t e r n a t i v e , however, because the clock frequency must be several hundred megahertz i n order to achieve the required frequency r e s o l u t i o n for the FCT s i g n a l . Even the coarser r e s o l u t i o n of the VCT s i g n a l would s t i l l require a clock frequency of 40 to 50 MHz. While a high frequency programmable d i v i d e r c i r c u i t could be b u i l t using ECL components, i t would have a high parts count and would not be easy to i n t e r f a c e to the microcomputer. A binary rate m u l t i p l i e r generates output pulses at a frequency that i s re l a t e d to the input clock frequency by a r a t i o n a l f r a c t i o n . For example, a 12 b i t rate m u l t i p l i e r has the following r e l a t i o n s h i p between input and output frequencies: < 3 0> fout = f i n x N/4096 where N i s an integer between 0 and 4095. In t h i s case a high clock frequency i s not necessary i n order to obtain the required r e s o l u t i o n . However, the output pulses generated by a rate m u l t i p l i e r are usually not evenly spaced. This i s because the rate m u l t i p l i e r generates i t s output pulses by l e t t i n g some of the input pulses pass to the output and suppressing the remainder. Thus the formula for f Q u t given above i s only true as an average. This could pose a problem i f a rate m u l t i p l i e r i s used to generate the co n t r o l frequencies f o r the 103 HEF4752. The HEF4752V uses the control frequencies to control the timing of the switching pulses i t generates. It i s possible that the i r r e g u l a r spacing of the pulses produced by a rate m u l t i p l i e r w i l l propagate through to the switching pulses and r e s u l t i n a PWM waveform with noticeable j i t t e r . Unfortunately, the s p e c i f i c a t i o n sheet supplied f o r the HEF4752V provides no information on t h i s point. In addition, the a p p l i c a t i o n example supplied by the manufacturer consists of an analog i n v e r t e r c o n t r o l l e r which generates the co n t r o l frequencies f o r the HEF4752V by means of voltage to frequency converters. Thus no information i s provided on the requirements f or con t r o l frequencies generated by d i g i t a l means. Relerence Loop Filter Frequency Phase Comparator Voltage Controlled Oscillator Output Frequency T Programmable Counter (Divide by N) N Figure 27 D i g i t a l l y Controlled Frequency Synthesizer 104 The d i g i t a l l y c o n t r o l l e d frequency synthesizer (Figure 27) consists of a phase-locked loop with a programmable counter i n i t s feedback path. The output frequency f Q u t of the frequency synthesizer i s (31) f Q u t = N x f r e f where N i s the d i v i s o r programmed in t o the counter and f r e f i s the reference frequency applied to the phase comparator. In t h i s case the r e s o l u t i o n i s dependent on the length of the progammable counter. The range of frequencies that can be generated i s b a s i c a l l y l i m i t e d by the range of the voltage co n t r o l l e d o s c i l l a t o r (VCO) i n the phase-locked loop. Modern d i g i t a l phase comparators allow the loop to remain i n phase lock over the f u l l VCO frequency range [66], Quick preliminary designs were ca r r i e d out for frequency generators based on rate m u l t i p l i e r s and on frequency synthesizers, to estimate the number of ICs each approach would require. It was estimated that the rate m u l t i p l i e r approach would require between 7 and 10 16 pin ICs. The estimate for the frequency synthesizer approach was 5 or 6 16 p i n ICs plus a 40 pin IC. However, the 40 p i n IC used by the frequency synthesizer had some a d d i t i o n a l c a p a b i l i t i e s which would be useful i n other parts of the c o n t r o l l e r design. Thus there was not much to choose between the two a l t e r n a t i v e s i n terms of board space 105 required. As already discussed, the rate m u l t i p l i e r approach has the disadvantage that i t produces an output i n which the pulses are unequally spaced, which may cause j i t t e r i n the switching s i g n a l s . The pulses produced by the frequency synthesizer, on the other hand, are equally spaced. The frequency synthesizer approach therefore appeared to be less r i s k y , p a r t i c u l a r l y since i t had been used s u c c e s s f u l l y i n the prototype c o n t r o l l e r described i n the previous chapter. As a r e s u l t , the decision was made to use the frequency synthesizer technique to generate the FCT and VCT clock frequencies. Figure 28 shows the schematic diagram f o r the frequency synthesizer c i r c u i t used to generate the FCT and VCT clock frequencies. The programmable counters which are used to set the output frequencies of the synthesizer are contained i n the Advanced Micro Devices Am9513 Counter/Timer IC (see Figure 29 [67]). This device contains f i v e 16 b i t programmable counters which can be loaded by the microcomputer. In a d d i t i on there i s another 4 b i t frequency d i v i d e r (FOUT) which can be set up by commands from the microcomputer. In the in v e r t e r c o n t r o l l e r design, the 9513 i s supplied the 3 MHz microcomputer clock s i g n a l . The FOUT div i d e r i s set up to divide t h i s clock frequency by f i v e to supply a 600 kHz clock s i g n a l to the real-time clock i n the 8156 106 CLOCK 51GNM T O U S n ! R I A L -T IME CLOCK AND A/D C O N V E R T E R F i g u r e 2 8 Programmable F r e q u e n c y S y n t h e s i z e r 'ST?) SOURCE 1-5 GATE 1-S X1 • X2 • OBO-OB7 ' OBS-DB1S ' WR" • RD • c/B • C5 • OSCILLATOR 16-BIT COUNTER FREQUENCY SCALER 4-BIT COUNTER FOUT DIVIDER INPUT SELECT LOGIC S-BIT COMMAND REGISTER 6-BIT DATA POINTER BUS BUFFER AND MUX - V . i BUS INTERFACE CONTROL 8-BIT STATUS REGISTER 16-BIT MASTER MODE REGISTER POWER ON RESET : COUNTER S LOGIC GROUP COUNTER 4 LOGIC GROUP i — r COUNTER 3 LOGIC GROUP 1 I COUNTER 2 LOGIC GROUP COUNTER 1 LOGIC GROUP OUTS Figure 29 General Block Diagram f o r Am9513 Counter/Timer IC and to the A/D convertor. Counter 1 i n the 9513 i s programmed to divide the 3 MHz clock s i g n a l to produce a 1680 Hz reference frequency for the phase locked loops. Counter 3 i s programmed to divide the 3 MHz clock s i g n a l to produce the RCT con t r o l frequency for the HEF4752V PWM waveform generator IC. The remaining three counters are i n the feedback loops of the frequency synthesizers. Two separate frequency synthesizers are required to generate the FCT clock frequency. This i s due to component l i m i t a t i o n s . The CD4046 phase-locked loop IC contains both a phase comparator and a VCO. The VCO has a frequency range of about 1000 to 1 but i s 108 l i m i t e d to a maximum output frequency of between 500 kHz and 1 MHz when operating from a 5 v o l t supply [68]. The maximum frequency required f o r the FCT s i g n a l i s 1.344 MHz. It i s possible to use the phase comparator i n the CD4046 with another VCO such as the 74LS628 TTL VCO IC. The 74LS628 can supply frequencies well i n excess of the required 1.344 MHz but i t s frequency range i s l i m i t e d to about 10 to 1 [69], The frequency range required for the FCT clock frequency i s at least 200 to 1. Thus we have one VCO which has the required frequency range but can't supply the required maximum frequency while another VCO w i l l supply the required maximum frequency but doesn't have the frequency range required. The s o l u t i o n i s to use two frequency synthesizers. The synthesizer associated with Counter 2 i n the 9513 uses the VCO i n the CD4046 and generates FCT frequencies from 6720 Hz (2 Hz output frequency) to 403,200 Hz (120 Hz output frequency). The other frequency synthesizer, associated with Counter 5 i n the 9513, uses the phase comparator i n a CD4046 i n conjunction with a 74LS628 VCO to generate the FCT frequencies from 403,200 Hz to 1.344 MHz (400 Hz output frequency). Some simple l o g i c c i r c u i t s , c o n t r o l l e d by signals from the microcomputer (FCT SELECT), select signals from one of the FCT sources to send to the PWM generator IC. The operating ranges of the two frequency synthesizers overlap around the frequency where switching occurs (403,200 Hz) and they are phase locked to a common reference frequency so switching from one synthesizer to the other i s completely 109 " g l i t c h " f r e e . Only a single frequency synthesizer i s required f o r the generation of the VCT clock frequency. However, since a maximum frequency of 2.688 MHz i s required, the synthesizer consists of the phase comparator section of a CD4046 used with a 74LS628 VCO. Counter 4 i n the 9513 i s used as the counter i n the feedback path of the VCT synthesizer. It w i l l soon be possible to considerably si m p l i f y the design of the FCT and VCT frequency synthesizers. A high speed s i l i c o n gate CMOS version of the metal gate CMOS CD4046 phase-locked loop IC should be a v a i l a b l e by mid 1984. The new high speed s i l i c o n gate CMOS ICs normally run ten times as f a s t as t h e i r older metal gate counterparts. Therefore i t should be possible to do away with one of the FCT frequency synthesizers and with the 74LS628 VCO i n the VCT synthesizer. Besides reducing the chip count, th i s change w i l l also make one of the counters i n the Am 9513 and two output l i n e s on the 8156 av a i l a b l e for other uses. The design of the loop f i l t e r s f o r the phase-locked loops follows the guidelines given by the manufacturer of the CD4046 phase-locked loop IC [70]. The r i s e time of the VCO cont r o l voltage for a step change i n the frequency command i s about 20 milliseconds. There i s no noticeable ringing or overshoot. This speed of response has been more than adequate f or a l l of the applications of the inverte r c o n t r o l l e r to date. The maximum 110 rate of change of inve r t e r frequency i n these applications has been l i m i t e d to 200 Hz/sec due to l i m i t a t i o n s on the current that the inve r t e r can supply. It i s possible that an a p p l i c a t i o n i n which the inve r t e r c o n t r o l l e r i s performing fast closed loop speed co n t r o l of a low i n e r t i a motor might encounter some problems due to the lag i n the phase-locked loop response. In that case i t may be necessary to redesign the synthesizers so that they run at higher frequencies so that loop f i l t e r s with shorter time constants can be employed. The outputs of the synthesizers would then be divided down to get the frequencies required by the HEF4752V. With the phase-locked loop reference frequency set at 1680 Hz, the programming of the frequency synthesizers i s quite easy. The counters c o n t r o l l i n g the FCT synthesizers are loaded with an integer equal to twice the desired inverter output frequency. The rati o n a l e f or t h i s can be seen from the following: i ) Required FCT frequency = 3360 x f. in v e r t e r i i ) Synthesizer output frequency = N x f reference i i i ) If f reference = 1680 and N = 2 x f. inver t e r then synthesizer output frequency = 3360 x f. i n v e r t e r This provides a 0.5 Hz r e s o l u t i o n i n the inve r t e r output frequency. The counter c o n t r o l l i n g the VCT synthesizer i s loaded 111 with an integer equal to 4 times the inverter frequency at which 100 % modulation of the PWM waveform i s to occur. The ra t i o n a l e for t h i s i s s i m i l a r to that given f o r the FCT frequency synthesizer. 4.3 Remainder of Con t r o l l e r C i r c u i t The remainder of the invert e r c o n t r o l l e r c i r c u i t i s shown i n Figure 30. The analog to d i g i t a l converter used i n th i s design i s a National ADC0808. This device has eight analog input channels that accept unipolar voltages between 0 and 5 v o l t s . The convertor has 8 b i t r e s o l u t i o n and completes a conversion i n about 100 microseconds. The primary reason for choosing this converter was that i t incorporated an eight input multiplexer and an A/D converter into a single package that interfaced r e a d i l y to the 8085 microcomputer. The convertor r e s o l u t i o n and input voltage range have proved adequate i n a l l applications to date. The OCT s i g n a l to the HEF4752V PWM generator IC i s supplied by the 3MHz microcomputer clock. Since the K input to the HEF4752V can be jumpered high or low, the user can select i n t e r l o c k delay periods of either 2.7 microseconds or 5.3 microseconds. These delays are adequate for inverters based on power MOSFETs or f a s t power t r a n s i s t o r s . Provision i s made to supply an off-board OCT si g n a l f or those cases where a longer i n t e r l o c k delay period i s required. 112 />-» - /» Q - < ! M S ) r ft? - s Q—(53' |~|—(iwT) J -(Foe)' i — & — ' - T O 4ZD" *-(Z> c UI6 ADcogpg WJIHI )  «(j«D «(iwo)  ••GIF) "( )->°. "0<>. . . P " O — kz)» '•o-i5» CD« 'On i - PI -Qi-fi a a D rj d a B J V E R T E P , S W I T C H I N G S I G N A L S T O O P T O - H O U P L £ R S F i g u r e 30 R e m a i n d e r o f I n v e r t e r C o n t r o l l e r C i r c u i t The i n v e r t e r switching signals supplied by the HEF4752 are f i r s t buffered by a CD4050 IC and then sent to a 7416 open-collector i n v e r t i n g d r i v e r which supplies the current required to drive the LEDs i n the opto-couplers on the dr i v e r boards f o r the inverter switches. The 7416 could also drive pulse transformers i f required. The commutation signals generated by the HEF4752V for use i n t h y r i s t o r inverters are brought to connectors on the invert e r c o n t r o l l e r board but are not buffered i n any way. Figure 31 shows the memory and I/O maps for the inverter c o n t r o l l e r . The address decoding was kept very simple i n order to minimize the c o n t r o l l e r chip count. However, some I/O addresses are a v a i l a b l e f o r external devices which can be interfaced to the microcomputer i n the invert e r c o n t r o l l e r . One a p p l i c a t i o n of the in v e r t e r c o n t r o l l e r has made use of t h i s feature to i n t e r f a c e a keypad and alphanumeric display to the c o n t r o l l e r . 4.4 Inverter Controller C i r c u i t Board After the design of the invert e r c o n t r o l l e r was completed, a wire-wrapped prototype was constructed. This prototype was debugged and then used to test the f i r s t version of the in v e r t e r c o n t r o l l e r software. Once i t was clear that the design was free of errors and met the basic requirements outlined i n Chapter 3, the schematics f o r the c o n t r o l l e r , along with s p e c i f i c a t i o n s on the printed c i r c u i t board format used by International Submarine Engineering, were sent to a company which s p e c i a l i z e s i n printed 114 MEMORY MAP O O O O O F F F IOOO IOFF I 100 2 7 3 2 E P R O M 8156 RAM U N U S E D F F F F I/O MAP 0 0 O F 10 15 16 IF 20 2 F 30 3 F 4 0 41 42 7'F 8 0 8 7 88 FF AVA ILABLE FOR E X T E R N A L DEVICES 8156 P O R T S AND R E G I S T E R S N O T USED A V A I L A B L E FOR E X T E R N A L DEV ICES NOT USED AM95I3 REGISTERS NOT USED A D C 0 8 0 8 DATA REGISTER & C H A N N E L S E L E C T A D D R E S S E S NOT USED F i g u r e 31 Memory and I/O Map F o r I n v e r t e r C o n t r o l l e r 115 CTl O O • — RI 11"- ch n't 5 C -— »i taa*K 'li mas U3 8256 S613 p 1 F i g u r e 32 I n v e r t e r C o n t r o l l e r C i r c u i t B o a r d L a y o u t c i r c u i t board layout. The company was successful i n f i t t i n g the ent i r e c o n t r o l l e r on one printed c i r c u i t board. The basic layout of the printed c i r c u i t board i s shown i n Figure 32. The most frequently used l i n e s from the c o n t r o l l e r are brought to the edge connector PI. Less used l i n e s are brought to the ribbon cable header P2. While the layout shown i s i d e a l f o r the submersible a p p l i c a t i o n , and i s acceptable for other stand-alone a p p l i c a t i o n s , the card shape and edge connector format are non-standard and therefore not very good for applications where the inverter c o n t r o l l e r i s part of a larger system. However the area of the i n v e r t e r c o n t r o l l e r board i s almost i d e n t i c a l to that of the printed c i r c u i t boards used i n the STD microcomputer bus system. Therefore i t should be possible to redesign the i n v e r t e r c o n t r o l l e r to f i t on an STD bus card. The c o n t r o l l e r could then be used as a peripheral device by a STD bus microcomputer or, a l t e r n a t i v e l y , the inver t e r c o n t r o l l e r could make use of the wide range of commercially a v a i l a b l e STD bus cards to expand i t s own c a p a b i l i t i e s . 117 Chapter 5 Inverter C o n t r o l l e r Software Design The inve r t e r c o n t r o l l e r software consists of components which are used i n v i r t u a l l y a l l applications and components which are s p e c i f i c to p a r t i c u l a r a p p l i c a t i o n s . This chapter w i l l concentrate on the design of of those components, such as c o n t r o l l e r and inve r t e r i n i t i a l i z a t i o n , c o n t r o l l e r sequencing, and co n t r o l of motor a c c e l e r a t i o n , deceleration, and reversing, which are common to a l l a p p l i c a t i o n s . The following chapter discusses applications of the inve r t e r c o n t r o l l e r and the design of some of the software components s p e c i f i c to these a p p l i c a t i o n s . One of the d i s t i n g u i s h i n g features of the software i s that i t i s written i n C, which i s a h i g h - l e v e l programming language. Other microprocessor based i n v e r t e r c o n t r o l l e r s described i n the l i t e r a t u r e have been programmed i n assembly language. Besides making software development easier and f a s t e r , the use of a high l e v e l language r e s u l t s i n a c o n t r o l l e r program that i s easier to document, maintain, and modify than the equivalent assembly language program. The c o n t r o l l e r software i s designed, as f a r as possible, i n a modular fashion i n order to further enhance the a b i l i t y to maintain and modify the software. Another unique aspect of the software design of the i n v e r t e r 1 1 8 c o n t r o l l e r i s that i t i s organized as a f i n i t e state machine. While the state machine approach to software design has been used i n a vari e t y of ap p l i c a t i o n s , i t does not appear to have been used previously i n c o n t r o l l e r s f o r power e l e c t r o n i c equipment. Designing the in v e r t e r c o n t r o l l e r software as a f i n i t e state machine i s considerably less prone to error than the more ad hoc techniques commonly used to design the software f o r power e l e c t r o n i c equipment. 5.1 Software Development System One of the goals of t h i s project i s to design the inverter c o n t r o l l e r so that i t can be e a s i l y and quickly adapted to a new drive a p p l i c a t i o n . Performing many of the c o n t r o l l e r functions with computer software w i l l help to achieve that goal i f the process of developing the software Is made quick and easy. In addition the software should be designed so that i t i s easy to maintain and modify. These requirements provide a strong incentive for the use of a high l e v e l programming language. However, the machine language code produced by the t r a n s l a t i o n of the high l e v e l language source code must be e f f i c i e n t i n terms of execution speed and storage requirements. Reasonable execution speed i s required i n order that the c o n t r o l l e r can carry out a l l i t s required functions without serious degradation of i t s speed of response. Fortunately, the use of the P h i l i p s HEF4752V PWM waveform generator IC considerably reduces the required execution speed since many of the speed c r i t i c a l c o n t r o l l e r functions are 119 peformed by t h i s IC. Compact code i s required so that the c o n t r o l l e r program can f i t into the l i m i t e d EPROM space on the c o n t r o l l e r card. A number of high l e v e l languages were considered f o r t h i s project. In f a c t , some i n i t i a l software development work was done using the PL/M cross-compiler available on the UBC computer system. However, the C language [71] was f i n a l l y chosen as the programming language f o r t h i s project. Benchmark tests of high l e v e l language compilers have shown that C compilers are t y p i c a l l y among the best i n producing e f f i c i e n t machine language code for the 8080 family of microcomputers [72, 73, 74], The C language has features such as b i t manipulation and s h i f t i n g i n s t r u c t i o n s which make i t a good assembly language replacement, yet i t also has high l e v e l language f a c i l i t i e s , such as control structures and data typing, which support a structured approach to program design. A f i n a l advantage of the C language i s that inexpensive compilers are a v a i l a b l e for most microprocessors. Thus a change i n the microprocessor used i n the i n v e r t e r c o n t r o l l e r w i l l not r e s u l t i n the obsolescence of a l l the software developed f o r the c o n t r o l l e r . As discussed i n the previous chapter, i t was important to have a low cost software development system f o r t h i s p r o j ect. The development system used c e r t a i n l y meets this requirement. It i s based on an Apple II personal computer equipped with a Z-80 co-processor card that allows i t to run programs written for the 120 CP/M operating system. The development software consists of a C compiler which generates I n t e l 8080/8085 assembly language, a reloc a t i n g assembler and l i n k e r for the 8080/8085, and a text editor for e d i t i n g the source f i l e s . An EPROM programmer card that plugs into the Apple II i s used to store the object code into a 2732 EPROM. The e n t i r e system, including the computer, a p r i n t e r , the EPROM programmer, and the development software, can be purchased for under $5000. 5.2 Description of Controller Software In any software development project i t i s h e l p f u l to use some form of system model as the basis f o r the design. The nature of the model w i l l depend on the nature of the project. In the design of a numerical analysis program the model i s l i k e l y to be the mathematical algorithm that the program i s supposed to carry out. In a data processing a p p l i c a t i o n , the model may consist of data flow graphs and descriptions of data structures. A good model f o r the invert e r c o n t r o l l e r software i s the f i n i t e state machine [75]. A f i n i t e state machine i s a system which i s i n one of a f i n i t e number of states at any one time. The machine makes a t r a n s i t i o n from one state to another as a r e s u l t of some event. The state that the system moves to on a state t r a n s i t i o n i s determined only by the system's present state and the occurrence of a p a r t i c u l a r event or combination of events during the present state. The f i n i t e state machine model has been used 121 i n a number of c o n t r o l oriented software designs, including an i n d u s t r i a l sewing machine c o n t r o l l e r [76], process control [77], and a c o n t r o l l e r for a hybrid e l e c t r i c vehicle [78]. The operation of a f i n i t e state machine (FSM) can be described g r a p h i c a l l y by the use of a state t r a n s i t i o n diagram (Figure 33). The diagram consists of c i r c l e s , each of which represents a state, and l i n e s i n d i c a t i n g t r a n s i t i o n s among stat e s . Each state represents an operating mode i n which the tasks being performed do not change. The l i n e s i n d i c a t i n g t r a n s i t i o n s are marked with the condition that causes the change of state. The condition could be the value of an input or program v a r i a b l e , an i n t e r r u p t , or simply the completion of a l l the tasks within the present state. The state t r a n s i t i o n diagram e x p l i c i t l y shows the conditions that cause a change of c o n t r o l while suppressing much of the d e t a i l about the functions performed within each state. This makes i t a useful t o o l when designing c o n t r o l l e r s where much of the design involves determining the correct control sequence. It i s also possible to i d e n t i f y errors i n c o n t r o l flow from t h i s diagram. The diagram at the top of Figure 34 shows an inconsistent FSM where more than one t r a n s i t i o n i s possible from state 1 when condition A i s true. The middle diagram shows an incomplete FSM where the t r a n s i t i o n s for A and B not true are not s p e c i f i e d . F i n a l l y , the bottom diagram shows an FSM with an unreachable state. State 4 w i l l never be reached since D i s always f a l s e i n 122 F i g u r e 33 S t a t e T r a n s i t i o n D i a g r a m 123 F i g u r e 34 E r r o r s i n C o n t r o l Flow 124 state 2. Real systems often have many states and many possible t r a n s i t i o n s among them. It i s very easy to to design a system with a l l of the above errors i f a state t r a n s i t i o n diagram i s not used as an a i d i n detecting and eliminating them. The state t r a n s i t i o n diagram for the basic FSM model of the inverter c o n t r o l l e r i s shown i n Figure 35. When power i s applied to the i n v e r t e r c o n t r o l l e r , i t enters the INITIALIZATION st a t e . Within t h i s state, the c o n t r o l l e r software configures the 8156 RAM-I/O chip and the 9513 counter/timer chip to the operating modes required for proper c o n t r o l l e r operation, loads and s t a r t s a l l the counters, and c a r r i e s out the reset sequence required for the HEF4752V PWM waveform generator IC. The software also i n i t i a l i z e s any variables requiring e x p l i c i t i n i t i a l i z a t i o n and enables those interrupt inputs that are recognized by the c o n t r o l l e r . Once t h i s i s done the c o n t r o l l e r can begin i n i t i a l i z i n g the i n v e r t e r . The actions required to i n i t i a l i z e the i n v e r t e r depend on the design of the i n v e r t e r . However they may include c l o s i n g a contactor to connect the i n v e r t e r to the AC supply, i n i t i a l i z i n g the f a u l t detection c i r c u i t s , performing some i n i t i a l diagnostic checks, and s e t t i n g the displays on the control panel to t h e i r i n i t i a l c o ndition. Once the i n i t i a l i z a t i o n process i s complete, the software makes an unconditional t r a n s i t i o n to the OFF state. In t h i s state the 125 P O W E R O N R E S E T INITIALIZATION ON/OFr SWITCH • OFF LEGEND: FC - FREQUENCY COMMAND PF - PRESENT FREQUENCY PDIR - P R E S E N T DIRECTION DIRCMND - DIRECTION COMMAND I N I T I A L I Z A T I O N C O M P L E T E F C >JPF A N D O N A N D P D I R • O I R C M W D OFF . O N / O F F S W I T C H . O N ACCELERATING [ SYSTEK . RtSET O N / O F F S W I T C H « OFF F C > 3 H Z A M O ON STOPPED , F C | F C > P F 1 AND O N AND \ P D I R = D I R C H N D • P F A N D O N AND P D \ R = D I R C M N D WO \ R E S E T F C t^HZ A N D O N FAULT PF £ . 1 M 2 FC < PF O R O F F O R PDIR * DIRCMND ' F O P F ' A N D OW A N B PDIR = DlROANQ> Fc-PF A N D O N AND I Pu\R = OlRCrlND F C <• P F ' O R O F F O R P D I R * D I R C M N D C O N S T A N T S P E E D ENTER. F R O M ANY V T A T E UPON R E C E I P T O F F A U L T I N T E R R U P T F C ^ P F O R ( O F F A N O PF 7 3HZl O R (PD1R.+ DIRCHN& AND P F ? (zui) DECELERATING ' F C - PF ' A N D O M A N D PDIR « D I R C M W O F i g u r e 35 F i n i t e S t a t e M a c h i n e M o d e l o f I n v e r t e r C o n t r o l l e r program simply waits f o r a signal to turn the drive on. This s i g n a l , marked as the ON/OFF SWITCH on the diagram, may a c t u a l l y come from a physical switch, or i t may come as a command from a higher l e v e l c o n t r o l l e r . When the s i g n a l to turn the drive on i s received, the software makes a t r a n s i t i o n to the STOPPED state. In the STOPPED state the program determines the required d i r e c t i o n of motor r o t a t i o n and sets the CW cont r o l input to the HEF4752V accordingly. The program also monitors the frequency command input to determine whether the frequency command i s greater than the lower l i m i t of 3 Hz. If i t i s , the program makes a t r a n s i t i o n to the ACCELERATING state. At t h i s point the HEF4752V outputs are enabled by s e t t i n g the L control input high and the drive begins operation. During the time that the program i s i n the ACCELERATING state, the invert e r frequency i s incremented at a constant rate so that the motor accelerates. The in v e r t e r frequency i s continually compared to the frequency command. If i t becomes equal to the frequency command, a t r a n s i t i o n i s made to the CONSTANT SPEED state. A l t e r n a t i v e l y , i f the frequency command i s changed so that the inverte r frequency exceeds i t , or i f the drive i s commanded to change d i r e c t i o n or to turn o f f , a t r a n s i t i o n i s made to the DECELERATING state. Assuming that a t r a n s i t i o n to the CONSTANT SPEED state has been made, the program ceases incrementing the frequency and simply 127 monitors the frequency command, d i r e c t i o n command, and ON/OFF SWITCH commands. If the frequency command i s changed so that i t i s greater than the invert e r frequency, the software makes a t r a n s i t i o n back to the ACCELERATING st a t e . If the frequency command i s changed so that i t i s less than the inverter frequency, or i f the drive i s commanded to turn off or reverse d i r e c t i o n , the software makes a t r a n s i t i o n to the DECELERATING state. If the t r a n s i t i o n to the DECELERATING state i s made, the program begins to decrement the in v e r t e r frequency. If the drive i s being commanded to reverse d i r e c t i o n or to turn o f f , decrementing w i l l continue u n t i l the i n v e r t e r frequency reaches 3 Hz. At that point a t r a n s i t i o n i s made back to the STOPPED state and the inverte r switching signals are disabled. A l t e r n a t i v e l y , i f the c o n t r o l l e r i s i n the DECELERATING state simply because the frequency command i s less than the invert e r frequency, decrementing i s continued u n t i l the invert e r frequency i s less than or equal to the frequency command. If the in v e r t e r frequency i s equal to the frequency command, a t r a n s i t i o n i s made to the CONSTANT SPEED state. If the frequency command i s changed so that i t becomes greater than the in v e r t e r frequency, a t r a n s i t i o n i s made to the ACCELERATING st a t e . Many i n v e r t e r f a u l t conditions can be dealt with by software within one of the states already discussed. For example, i f the acc e l e r a t i o n or deceleration rate causes the invert e r current 128 l i m i t to be exceeded, the software i n the ACCELERATING or DECELERATING state can reduce the rate at which the inverter frequency i s changed. S i m i l a r l y , i f the DC bus voltage exceeds i t s l i m i t during deceleration because of energy regenerated from the motor, software i n the DECELERATING state can take corrective action such as cl o s i n g a contactor to connect a b a l l a s t r e s i s t o r across the DC bus. Serious drive f a u l t s , such as a motor short c i r c u i t , require actions which a l t e r the normal sequencing of the f i n i t e state machine. Therefore a FAULT state i s added which i s entered from any of the other states when a f a u l t interrupt i s received on the TRAP input of the 8085. The f i n i t e state machine can also be designed to enter the FAULT state on receipt of a "panic stop" signal from the con t r o l panel. In the FAULT state, the in v e r t e r switching signals are disabled i n order to shut the inverter o f f , the contactor ( i f any) connecting the in v e r t e r to the AC supply i s opened, and any f a u l t i n d i c a t o r s on the control panel are act i v a t e d . The c o n t r o l l e r stays i n the FAULT state u n t i l i t i s reset, at which time i t enters the INITIALIZATION state. This f i n i t e state machine model i s quite simple. However i t s c a p a b i l i t i e s are s u f f i c i e n t for applications such as the submersible thruster drive. The f i n i t e state machine properly handles sequencing of the thruster drive for any combination of commands. For example, i f the d i r e c t i o n command i s changed while the drive i s operating, the drive w i l l decelerate to a stop, the 129 phase sequence of the switching waveform w i l l be reversed, and the drive w i l l accelerate u n t i l the invert e r frequency matches the commanded frequency. S i m i l a r l y , i f the drive i s commanded to turn off while operating, i t w i l l decelerate to a stop, disable the i n v e r t e r switching s i g n a l s , and then wait f o r a command to turn i t s e l f on. In a more complex drive, t h i s model serves as a useful framework to which the ad d i t i o n a l functions required by the drive can be added. 5.3 Software Implementation A l i s t i n g of the con t r o l program for a submersible thruster drive i s given i n Appendix 1. Much of the program i s devoted to c o n t r o l l i n g the hardware on the inverter c o n t r o l l e r board. These device s p e c i f i c portions of the program are not overly i n t e r e s t i n g and so w i l l not be discussed. However, i t i s of i n t e r e s t to see how the f i n i t e state machine model of the c o n t r o l l e r i s a c t u a l l y implemented i n the program. The function main(), which implements the state sequencer of the f i n i t e state machine i s l i s t e d below. /* Main function f i r s t i n i t i a l i z e s the system and then loops continuously */ main() { i n i t i a l i z e O ; ^implements the INITIALIZATION state */ while (ALWAYS) { c l o c k t i c k = 0; /* c l o c k t i c k set to 1 by int75() i n t e r r u p t service routine which handles real-time clock*/ i f ( f a u l t f l a g == TRUE) / * f a u l t f l a g set to TRUE by trap() interrupt 130 } service routine which handles f a u l t interrupts */ nexstate = FAULTSTATE; switch (nexstate) /* State sequencer */ { case OFFSTATE : off(); break; case STOPSTATE : stopped(); break; case ACCSTATE : a c c e l e r a t i n g ( ) ; break; case DECSTATE : dec e l e r a t i n g ( ) ; break; case CONSTSTATE : constantspeed(); break; case FAULTSTATE : f a u l t ( ) ; break; default : f a u l t ( ) ; break; } while (!clockt i c k ) ; /* Loop while waiting f o r next real-time clock i n t e r r u p t , then go through state sequencer again*/ } The function main() i s entered a f t e r power i s applied to the c o n t r o l l e r or the c o n t r o l l e r i s reset. I t c a l l s the i n i t i a l i z e ( ) function which c a r r i e s out the actions required for the INITIALIZATION state. One of these actions i s to set up the real-time clock to interrupt the microprocessor every 5 milliseconds. This real-time clock interrupt i s used to drive the state sequencer. After every clock i n t e r r u p t , the sequencer uses the switch control statement to select a function to execute depending on the value of the variable nexstate which 131 represents the next state to be entered from the present state of the f i n i t e state machine. The function selected c a r r i e s out the actions required f o r the new state and determines the new value for the var i a b l e nexstate so that the proper state t r a n s i t i o n w i l l be made on the next pass through the state sequencer. One exception to the practice of determining the next state i n the function performing the actions of the present state i s the t r a n s i t i o n to the FAULT state. The interrupt handler routine f o r the TRAP int e r r u p t input, which receives f a u l t i n t e r r u p t s , sets a f l a g v a r i a b l e (faultflag) that i s checked by the state sequencer. If faultflag i s set, the state sequencer sets nexstate to the value required to enter the FAULT state. Determining the t r a n s i t i o n to the FAULT state within the state sequencer eliminates redundant statements i n the functions for each state since the presence of a f a u l t always causes a t r a n s i t i o n to the FAULT state no matter what the present state of the system. The acceleratingO function, l i s t e d below, which c a r r i e s out the actions required i n the ACCELERATING state, i s representative of the functions f o r the other states. /* accelerating function */ /* Carries out functions required while i n v e r t e r i s increasing i t s frequency */ accelerating() { i f ( f a u l t f l a g == FALSE) /*Activate the in v e r t e r switching s t a r t Q ; signals i f no f a u l t has occurred */ 132 /* check i f t r a n s i t i o n to another state i s required */ i f ( o f f_or_rev()) nexstate = DECSTATE; else i f ( p o s _ f r e q _ e r r o r ( ) ) nexstate = DECSTATE; else i f ( z e r o _ f r e q _ e r r o r ( ) ) nexsTate ~^ CONSTSTATE; else { /* nexstate = ACCSTATE; */ i n c _ f requency(); } } The function f i r s t enables the i n v e r t e r switching signals i f no inv e r t e r f a u l t has occurred. This action may be redundant since the switching signals may already be enabled but i t does no harm. Then a series of checks are performed to determine i f a t r a n s i t i o n to a state other than the present state i s required. This i s done by a series of c a l l s to lower l e v e l functions which each perform a test and return a value of TRUE or FALSE. For instance, the function o f f _ o r _ r e v ( ) checks whether the c o n t r o l l e r i s being commanded to turn the drive o f f or reverse i t s d i r e c t i o n . If a change of state i s required, the code for the new state i s stored i n the v a r i a b l e nexstate and the function returns to the state sequencer to wait for the next clock i n t e r r u p t . If no change of state i s required, a function i s c a l l e d to increment the i n v e r t e r frequency by 0.5 Hz and then the a c c e l e r a t i n g ( ) function returns to the state sequencer. It should be noted that the c o n t r o l l e r software i s written i n a top-down, modular fashion. At the top of the hierarchy i s the state sequencer function main() which c a l l s the function 1 3 3 associated with the present state of the f i n i t e state machine. This function i n turn c a l l s lower l e v e l functions to perform i t s tasks. The d e t a i l s of accessing I/O ports, masking out b i t s i n status r e g i s t e r s and other hardware and a p p l i c a t i o n s p e c i f i c operations are hidden i n the low l e v e l functions. This makes the program easier to understand since the reader i s not inundated with low l e v e l d e t a i l when tr y i n g to follow the o v e r a l l operation of the program. It also makes i t easier to adapt to changes i n the hardware or the a p p l i c a t i o n since only the low l e v e l functions have to be rewritten. Some assembly language support functions are required i n a d d i t i o n to the program l i s t e d i n Appendix 1, which i s written almost e n t i r e l y i n C. One of these functions i s c a l l e d the run-time header. I t contains the code, executed immediately a f t e r a system reset, which i n i t i a l i z e s the stack pointer and then c a l l s the function main() i n the c o n t r o l program. The run-time header also contains the code required upon entry to, and e x i t from, an interrupt service routine. The other functions give the C program access to the 8085 I/O i n s t r u c t i o n s (IN and OUT) and to the i n s t r u c t i o n s which co n t r o l the interrupt system (EI, DI, RIM, and SIM). 5.4 Evaluation of Software Development Using the C Language Microprocessor based i n v e r t e r c o n t r o l l e r s that have been described i n the l i t e r a t u r e appear to have been programmed i n 134 asssembly language. Indeed, the use of assembly language to program c o n t r o l l e r s f o r power conversion equipment i s almost u n i v e r s a l . The reason normally given f or the use of assembly language i s that the maximum possible execution speed i s required f o r the program. Sometimes l i m i t a t i o n s i n memory size or the lack of a high l e v e l language compiler are c i t e d as reasons for the use of assembly language. These l a s t two reasons are no longer very v a l i d since memory costs are now very low and high l e v e l language compilers are av a i l a b l e f o r many microprocessors. However, the question of execution speed remains. It i s true that a program written i n C w i l l execute more slowly than the equivalent assembly language program i f the assembly language programmer i s reasonably competent. However i f the C program i s fast enough to meet a l l the requirements of the a p p l i c a t i o n , i t i s immaterial that the assembly language program would be f a s t e r . In that case the advantages of programming i n a high l e v e l language predominate. The C program for the submersible thruster drive, described i n the previous section, operates with a 5 millisecond real-time clock i n t e r v a l and has some time to spare. A considerably more complicated program, written f or a l i n e a r induction motor drive a p p l i c a t i o n , operates with a 10 millisecond real-time clock i n t e r v a l and also has time to spare. In both cases the response time i s more than adequate. Interrupt service routines to handle f a u l t s requiring very f a s t response are 135 p a r t l y coded i n assembly language but these constitute a small portion of the e n t i r e program. The primary reason why a high l e v e l language l i k e C can be used s u c c e s s f u l l y i n th i s i n v e r t e r c o n t r o l l e r i s that the PWM waveform generation IC unloads a large number of speed c r i t i c a l operations from the microprocessor. Another contributing factor i s the use of the f i n i t e state machine as a software design t o o l . The f i n i t e state machine model encourages an organized and structured approach to the software design which i n turn r e s u l t s i n a simple, clean, and e f f i c i e n t program. It i s l i k e l y that some future a p p l i c a t i o n s , involving closed loop control of motor torque or speed, w i l l need to make more use of assembly language i n order to achieve adequate loop bandwidth. Even i n those cases however, i t makes sense to write the majority of the program i n a language l i k e C and write only the speed c r i t i c a l sections of the program i n assembly language. The control program f o r the submersible thruster drive consists of about 180 l i n e s of C language code (ignoring comments) and about 40 l i n e s of assembly language code. There are about another 60 l i n e s of assembly language code i n the support functions. Of the C language code, about 80 l i n e s consist of d e f i n i t i o n s and declarations which don't generate any machine language. The machine language program, produced a f t e r compiling, assembling and l i n k i n g the source programs, f i t s into 136 less than 2K bytes of EPROM. The program f o r the l i n e a r induction motor drive a p p l i c a t i o n barely f i t s i nto 4K bytes of EPROM a f t e r some rewriting of the program to make i t more memory e f f i c i e n t . Future applications w i l l d e f i n i t e l y need more EPROM space on the c o n t r o l l e r card. The advantages of a high l e v e l language are i n the time required to develop a program and i n the a b i l i t y to maintain and modify the program. The control program f o r the submersible thruster drive took about a month to write and debug. This i s i n l i n e with published estimates that programs are produced at a rate of about 10 l i n e s per day. When the program for the l i n e a r induction motor drive was written, much of the program f o r the submersible thruster drive could be used d i r e c t l y , so t h i s program also took about a month to write despite the fact that i t i s about twice as long as the program for the submersible thruster d r i v e . If the programs had been written i n assembly language i t i s probable that the development time for the submersible thruster program would have been at l e a s t two months and that i t would have been considerably more d i f f i c u l t to use thi s program as a basis f o r the development of the l i n e a r induction motor drive program. Certainly the top down, modular structure of the programs would be more d i f f i c u l t to achieve i f the programs were written i n assembly language. Debugging a program written i n a high l e v e l language i s d i f f e r e n t than debugging a program written i n assembly language. In the 137 absence of high l e v e l debugging tools that are integrated with the compiler, there i s l i t t l e to be gained from the use of i n - c i r c u i t emulators, single stepping, and breakpoints since the res u l t s don't mean much i n terms of the high l e v e l language program. In cases where the target system has an in t e r f a c e to a p r i n t e r or a terminal, the high l e v e l language program can be "instrumented" with statements to p r i n t out information on the execution of the program. In the case of the inverter c o n t r o l l e r t h i s f a c i l i t y was not a v a i l a b l e . Instead, debugging consisted of thinking c a r e f u l l y about the observed problems i n the operation of the c o n t r o l l e r , r e l a t i n g them to a section of the program which could cause the problem, f i n d i n g and correcting the error, and then reloading the recompiled program into EPROM to v e r i f y that the diagnosis was c o r r e c t . The process was a c t u a l l y less p a i n f u l than i t appears. Since the high l e v e l language program was shorter than the equivalent assembly language program, and allowed the program design to be expressed more n a t u r a l l y , there were fewer program errors to s t a r t with. The high l e v e l language program was easier to read and understand, and was better structured than the average assembly language program. Thus i t was easier to i s o l a t e the section of the program responsible for a problem and easier to f i n d the program error i n that section of program. F i n a l l y , the need to recompile the program and reprogram the EPROM encouraged an organized, e f f i c i e n t approach to debugging and proper, documented r e p a i r s . In contrast, the fast turn-around possible 1 3 8 when debugging i n assembly language often encourages t r i a l and error approaches to debugging and the use of quick, undocumented machine language "patches" to correct e r r o r s . On balance, the decision to use a high l e v e l language i n t h i s project seems to be j u s t i f i e d . The programs produced to date meet the speed requirements of the a p p l i c a t i o n s . More demanding applications can be dealt with by using a f a s t e r version of the 8085 microprocessor, redesigning the c o n t r o l l e r to use a more powerful microprocessor, or writing some speed c r i t i c a l portions of the program i n assembly language. Based on experience with previous assembly language programming projects, development of a high l e v e l language program proceeds at least twice as quickly as development of the equivalent assembly language program. The economic implications are obvious. 1 3 9 Chapter 6 Applications of the Inverter C o n t r o l l e r So f a r the in v e r t e r c o n t r o l l e r has been used i n two d i f f e r e n t a p p l i c a t i o n s . The f i r s t i s the submersible thruster drive which was the o r i g i n a l motivation f o r the design of the c o n t r o l l e r . The second i s a c o n t r o l l e r for a l i n e a r induction motor drive. This chapter i s devoted to describing these two drives since they demonstrate the f l e x i b i l i t y and p r a c t i c a l i t y of the in v e r t e r c o n t r o l l e r i n r e a l i s t i c a p p l i c a t i o n s . Both drives make use of the wide frequency range of the c o n t r o l l e r . The submersible drive operates over a range of 3 to 400 Hz and the l i n e a r induction motor drive runs over a range of 3 to 600 Hz. The small s i z e and low parts count of the inverter c o n t r o l l e r are p a r t i c u l a r advantages i n the submersible a p p l i c a t i o n where compactness and r e l i a b i l i t y are extremely important. In the l i n e a r induction motor drive, the programmability of the c o n t r o l l e r i s a strong asset since the drive i s used i n experimental work where parameters such as maximum inv e r t e r frequency, volts/Hz r a t i o , current l i m i t setpoint, and ac c e l e r a t i o n and deceleration rates must be changed for d i f f e r e n t machines. The two drives are both viable products that can compete e f f e c t i v e l y with commercially a v a i l a b l e a l t e r n a t i v e s . In the 140 case of the submersible thruster drive, there do not appear to be any other thruster drives based on induction motors on the market. The c l o s e s t competitors are drives based on brushless DC motors. The AC motor drive i s smaller and cheaper than the brushless DC drive. In a d d i t i o n , the i n v e r t e r c o n t r o l l e r allows for considerably more f l e x i b i l i t y i n drive c h a r a c t e r i s t i c s than the less sophisticated c o n t r o l l e r s used by brushless DC drives. The only commercially a v a i l a b l e i n v e r t e r that was i d e n t i f i e d as possibly s u i t a b l e f o r the l i n e a r induction motor drive i s based on outdated technology. In terms of cost and performance i t cannot compete with the drive described i n t h i s chapter. Both drives currently exist as prototypes which have been extensively lab tested. Both are i n the process of being designed into commercial systems. 6.1 Submersible Thruster Drive The submersible thruster drive (see Figure 36) i s a small drive rated at 1.5 HP. A compact 400 Hz induction motor, o r i g i n a l l y designed for a i r c r a f t a p p l i c a t i o n s , i s used i n conjunction with a power MOSFET i n v e r t e r . A gear reduction i s used between the motor shaft and the propellor shaft of the d r i v e . As mentioned i n Chapter 3, the i n v e r t e r and motor can be mounted i n a common o i l f i l l e d housing. A l t e r n a t i v e l y , the i n v e r t e r and motor can be i n s t a l l e d i n separate housings on the submersible. The c o n t r o l l e r card i s i n s t a l l e d i n the submersible's e l e c t r o n i c s 141 canister which i s f i l l e d with a i r at one atmosphere pressure. A l l signals between the invert e r and the c o n t r o l l e r pass through opto-isolators so the inverter and c o n t r o l l e r are e l e c t r i c a l l y i s o l a t e d from each other. Figure 36 Submersible Thruster Drive The c o n t r o l strategy for this drive i s simple, using open-loop constant volts/Hz c o n t r o l of stator voltage and f i x e d a c c e l e r a t i o n and deceleration rates. In a thruster a p p l i c a t i o n , a more complex con t r o l strategy i s unnecessary. In the prototype, the motor speed command i s entered v i a a s l i d e potentiometer connected to the A/D converter. The output of the A/D converter i s interpreted as a signed binary number i n off s e t 1 4 2 binary format. Thus the potentiometer i s used to command speeds i n both di r e c t i o n s of r o t a t i o n . The software that reads and interprets the speed command i s i n one d i s t i n c t module which can be modified to deal with speed commands i n the format supplied by the designers of the submersible. In addition to the s l i d e potentiometer, the c o n t r o l l e r f o r the prototype drive i s also equipped with a switch to turn the inverte r on and off and a pushbutton that causes a hardware reset of the microcomputer i n the c o n t r o l l e r . Three LED lamps are i n s t a l l e d to i n d i c a t e that the c o n t r o l l e r i s on, that the inverte r i s on, and that a f a u l t has occurred. Since a c c e l e r a t i o n and deceleration rates are f i x e d and the i n e r t i a of the load does not change, protection against overcurrent due to too rapid a change i n invert e r frequency i s not required. Also, no s i g n i f i c a n t regeneration occurs when the drive decelerates since the load i s d i s s i p a t i v e rather than i n e r t i a l . As a r e s u l t no protection i s required against an overvoltage on the DC bus due to regenerated energy. Of the f a u l t s which can occur, the most common i s jamming of the propellor by a stray piece of rope or f i s h n e t . The invert e r i s equipped with a f a s t acting current l i m i t c i r c u i t that shuts o ff the switching devices and sends a f a u l t s i g n a l to the in v e r t e r c o n t r o l l e r i f the drive jams. The in v e r t e r c o n t r o l l e r software enters the FAULT state on receipt of the f a u l t s i g n a l from the inverte r and disables the invert e r switching s i g n a l s . In some 1 4 3 versions of the software, the c o n t r o l l e r e x i t s the FAULT s t a t e when the speed command i s reduced to zero so that the operator can attempt to r e s t a r t the d r i v e once the p r o p e l l o r i s unjammed. The t h r u s t e r d r i v e has been through an extensive s e r i e s of tank t e s t s . The d r i v e has been operated at a constant speed continuously f o r two weeks. I t has als o been conti n u o u s l y c y c l e d from f u l l speed i n one d i r e c t i o n to f u l l speed i n the other d i r e c t i o n f o r a per i o d of three days. F i n a l l y , a rope has been thrown i n t o the p r o p e l l o r of the t h r u s t e r to cause the d r i v e to jam. The d r i v e shut down properly and was r e s t a r t e d once the rope was removed. Figure 37 Motor Line Current ( V e r t i c a l : 5 A/div H o r i z o n t a l : 2 msec/div) Figure 37 shows the motor l i n e current f o r the t h r u s t e r d r i v e . As can be seen, the waveform i s b a s i c a l l y s i n u s o i d a l . When the 144 drive i s operated at very low speeds no cogging or v i b r a t i o n can be observed, i n d i c a t i n g that harmonic torques are very small. Representatives of International Submarine Engineering who have seen demonstrations of the thruster drive have been impressed by i t s small s i z e and good performance. They p a r t i c u l a r l y l i k e d the smooth low speed performance of the drive; apparently the drives they are currently using do not perform well at low speeds. At present, International Submarine Engineering i s designing a new sumersible which w i l l make use of t h i s d r i v e . 6.2 Linear Induction Motor Drive Cetec Engineering of Burnaby B.C. i s developing l i n e a r induction motors (LIMs) for use i n i n d u s t r i a l equipment such as c i r c u l a r saws, shakers, and grinders. Due to size constraints on the motors, the maximum pole p i t c h on the LIMs i s l i m i t e d . Therefore, to a t t a i n the required speeds on the driven portion of the machine, the LIM stator frequency must be r e l a t i v e l y high - up to 600 Hz i n some cases. In some equipment the LIM speed must be va r i a b l e . These two requirements suggest that a va r i a b l e frequency i n v e r t e r be used as the LIM power supply. Cetec attempted to f i n d a commercially a v a i l a b l e i n v e r t e r that would meet t h e i r requirements. Most inverters were not capable of operating above 120 Hz. One serie s of inverters was found that operated to 400 Hz but i t was based on t h y r i s t o r switches 145 and used a rather i n e f f i c i e n t complementary commutation scheme to switch off the devices. At 400 Hz the commutation losses were so high that the invert e r output power rating was substantialy decreased. As a r e s u l t the inverters having the required output power ra t i n g were large and expensive. Cetec decided to fund development of an in v e r t e r , using more modern technology, that would be smaller and less expensive and would have the f l e x i b i l i t y required for t h e i r development program. The f i r s t version of the invert e r was rated at 25 KVA; a 160 KVA version i s now being b u i l t . The invert e r i s of the PWM type and uses t r a n s i s t o r s as the power switching devices. The in v e r t e r c o n t r o l l e r described i n th i s thesis i s used to control the inve r t e r . The cont r o l strategy employed i s b a s i c a l l y an open-loop constant volts/Hz type. However, the c o n t r o l l e r can be switched into a closed-loop speed control mode i n which the c o n t r o l l e r changes the inv e r t e r frequency so that the difference between a setpoint l e v e l from a potentiometer and a feedback si g n a l from a speed sensor i s smaller than some preset error band. This co n t r o l mode i s intended f o r some LIM applications where the motor speed must be kept approximately constant with changes i n load. The speed control loop i s not p a r t i c u l a r l y accurate or fa s t but i t should meet the requirement of the LIM ap p l i c a t i o n . 146 FAULT HALL E F F E C T C U R R E N T C U R R E N T SENSORS TO INVERTER C O N T R O L L E R F i g u r e 38 S i m p l i f i e d S c h e m a t i c o f L I M I n v e r t e r 6.3 LIM Drive Protective Functions A s i m p l i f i e d schematic of the in v e r t e r i s shown i n Figure 38. The protective c i r c u i t r y i n th i s i n v e r t e r i s considerably more complex than i n the invert e r for the submersible drive. A sensor across the DC bus monitors the bus voltage. If the bus voltage exceeds a maximum l i m i t , the sensor sends a f a u l t s i g n a l to the inverte r c o n t r o l l e r . The invert e r c o n t r o l l e r then switches load r e s i s t o r s across the DC bus to absorb regenerated energy. Once the bus voltage has dropped below a lower l i m i t , the bus voltage sensor removes the f a u l t s i g n a l and the invert e r c o n t r o l l e r disconnects the load r e s i s t o r s from the DC bus. Protection against short c i r c u i t s and shoot throughs i s provided by inductor L I . It l i m i t s the rate of r i s e of the f a u l t current and, through the secondary c o i l on the inductor, sends a f a u l t s i g n a l to the in v e r t e r c o n t r o l l e r . This f a u l t s i g n a l goes to the TRAP interrupt input of the microcomputer. When the TRAP inter r u p t occurs, the f i r s t a c t i o n taken by the microcomputer i s to switch off a l l the invert e r switching devices. After that, the c o n t r o l l e r enters the FAULT state u n t i l the c o n t r o l l e r i s reset. The time from the i n i t i a t i o n of a f a u l t to the removal of inverte r switching signals i s very short - about 15 to 20 microseconds. The design of the current l i m i t i n g inductor (LI) i s coordinated with the overcurrent c h a r a c t e r i s t i c s of the inverter t r a n s i s t o r s , and the time required to switch them o f f , to ensure that f a u l t currents do not r i s e to damaging l e v e l s 148 before the t r a n s i s t o r s are able to turn o f f . The TRAP interrupt input also receives a si g n a l from an Emergency Stop pushbutton. This pushbutton can be used by the operator i n sit u a t i o n s where the drive must be shut down immediately. The normal i n v e r t e r on/off switch causes a controlled shut down i n which the invert e r c o n t r o l l e r f i r s t decelerates the machine to a s t a n d s t i l l . In some emergencies that can take too long. The H a l l E f f e c t current sensors on the inverter output l i n e s provide protection against i n v e r t e r overloads. The current sensor signals are r e c t i f i e d and summed to produce a sing l e current s i g n a l which i s sent to one of the A/D channels on the inverter c o n t r o l l e r . The in v e r t e r c o n t r o l l e r compares t h i s current feedback s i g n a l to a preset l i m i t . If an overcurrent i s detected, the c o n t r o l l e r takes corrective a c t i o n . The nature of the protective a c t i o n depends on the magnitude of the overcurrent and the current state of the c o n t r o l l e r . For example, i f the overcurrent i s r e l a t i v e l y small and the c o n t r o l l e r i s i n the ACCELERATING state, the c o n t r o l l e r w i l l simply decrease the rate of change of invert e r frequency. On the other hand, i f the overcurrent i s large, the c o n t r o l l e r w i l l shut down the in v e r t e r . 149 6.4 LIM Drive Control Panel Functions The LIM drive i n v e r t e r i s designed for use i n research and development. As a r e s u l t i t has provision f o r many more adjustments than the submersible thruster drive or a standard i n d u s t r i a l v a r i a b l e speed drive. The control panel i s equipped with a ten turn potentiometer to set the in v e r t e r frequency, a switch to set the phase sequence, and a switch to turn the inverte r on or o f f . In addition, provision i s made to set the maximum in v e r t e r frequency, the volts/Hz r a t i o , the ac c e l e r a t i o n and deceleration rates, and the current l i m i t setpoint. These adjustments are made by potentiometers which are connected to the A/D channels of the invert e r c o n t r o l l e r . The maximum in v e r t e r frequency can be set between 90 and 600 Hz. The potentiometer that sets the in v e r t e r frequency has a range from the minimum frequency (3 Hz) to the maximum frequency. The frequency r e s o l u t i o n i s maintained at 0.5 Hz. i n t e r n a l l y but, because of the 8 b i t r e s o l u t i o n of the A/D converters which read the potentiometers, the frequency can only be set with a res o l u t i o n of 2 or 3 Hz when the maximum frequency l i m i t i s 600 Hz. This does not present a problem i n the applications i n which t h i s i n v e r t e r i s used. The volts/Hz r a t i o can be adjusted so that the in v e r t e r PWM waveform reaches 100% modulation over a range from 50 Hz to 500 Hz. The acc e l e r a t i o n and deceleration rates, which are r e a l l y rates of change of in v e r t e r frequency, can be adjusted from 10 Hz/second to 200 Hz/second. 150 In order to display the various setpoints and data such as the i n v e r t e r frequency and l i n e current, an alphanumeric display i s i n s t a l l e d i n the c o n t r o l panel. The display i s a c t u a l l y a commercially a v a i l a b l e keypad/display card intended for STD bus computer systems. The card i s interfaced to the microcomputer address, data, and c o n t r o l l i n e s which are brought to connectors on the i n v e r t e r c o n t r o l l e r card. The keypad on the display card i s used to s e l e c t the data to be displayed. The alphanumeric display i s also used to display diagnostic messages when an inv e r t e r f a u l t occurs. 6.5 Evaluation of the LIM Drive The 25 KVA version of the LIM drive i n v e r t e r has been i n use at Cetec's laboratory for the past four months. To date the unit has performed s a t i s f a c t o r i l y . A l l the protective functions work as designed and have a c t u a l l y protected the i n v e r t e r against f a u l t s i n the l i n e a r induction motor. The c o n t r o l panel adjustments and the display also work properly. The closed-loop speed control has not been tested yet because no speed sensor has been i n s t a l l e d on any of the l i n e a r induction motors. It i s i n t e r e s t i n g to compare t h i s design to a modern commercial design. The Mitsubishi Freqrol-E [80,81] i s a modern t r a n s i s t o r i n v e r t e r that i s s i m i l a r i n many respects to the 25 KVA LIM i n v e r t e r . In f a c t , the same t r a n s i s t o r s are used i n the two 151 i n v e r t e r s . The Mitsubishi i n v e r t e r has been successful i n the market due to i t s compactness and good price/performance r a t i o . It i s representative of the state of the art i n general purpose AC drives. The Mitsubishi i n v e r t e r operates over a frequency range of 6 to 60 Hz or 6 to 120 Hz with resolutions of 0.5 Hz and 1 Hz r e s p e c t i v e l y . This frequency range i s considerably l e s s than that of the LIM i n v e r t e r but the frequency r e s o l u t i o n i s comparable. The Mitsubishi i n v e r t e r allows s e l e c t i o n of 16 d i f f e r e n t volts/Hz r a t i o s . The range of r a t i o s that can be selected i s considerably smaller than the range possible with the LIM i n v e r t e r . The a c c e l e r a t i o n and deceleration rates of the Mitsubishi i n v e r t e r can be varied over a wide range from about 120 Hz/second to less than 1 Hz/second. The LIM i n v e r t e r has a narrower range since the very slow rates of change were not required. However, the in v e r t e r c o n t r o l l e r could e a s i l y be programmed to produce lower rates of change. The protective functions incorporated i n the Mitsubishi i n v e r t e r are very s i m i l a r to those of the LIM i n v e r t e r . This i s not e n t i r e l y accidental since the design of the LIM i n v e r t e r i s based on i n d u s t r i a l p r a c t i c e . The Mitsubishi i n v e r t e r does not have the display c a p a b i l i t i e s of the LIM i n v e r t e r . An analog output proportional to frequency i s supplied which can drive a meter. In addition, some i n d i c a t o r lamps are used to i n d i c a t e f a u l t conditions. 152 From the preceding discussion i t i s c l e a r that the LIM i n v e r t e r i s competitive i n performance and features with commercial drives. When the in v e r t e r c o n t r o l l e r s of the Mitsubishi drive and the LIM drive are compared, some of the advantages of the LIM drive become apparent. The Mitsubishi i n v e r t e r c o n t r o l l e r i s based on a custom LSI IC but the c o n t r o l l e r board i s s t i l l about three times larger than the c o n t r o l l e r board for the LIM drive and contains many more components. Despite the use of LSI c i r c u i t s , many of the c o n t r o l l e r functions are s t i l l c a r r i e d out by analog integrated c i r c u i t s and small scale d i g i t a l integrated c i r c u i t s . This r e l i a n c e on hardware makes the Mitsubishi i n v e r t e r f a r less f l e x i b l e than the LIM i n v e r t e r . New control modes such as closed-loop speed control can't be added without redesigning the hardware. In contrast the c o n t r o l l e r i n the LIM drive can be reprogrammed rather e a s i l y since most control functions are c a r r i e d out by microcomputer software. F i n a l l y , the Mitsubishi i n v e r t e r has no p r o v i s i o n for i n t e r f a c i n g to a d i g i t a l system. As a r e s u l t i t i s hard to integrate i t into systems which operate under computer c o n t r o l . In contrast, the c o n t r o l l e r i n the LIM i n v e r t e r can be r e a d i l y interfaced to d i g i t a l systems and can be programmed to work under the control of a supervisory computer. As mentioned, a 160 KVA version of the LIM i n v e r t e r i s currently being b u i l t . It uses the same c o n t r o l l e r as the 25 KVA i n v e r t e r . This i n v e r t e r w i l l be used i n f i e l d tests of Cetec's equipment. 153 Assuming successful completion of f i e l d t e s t s , a s i m p l i f i e d version of t h i s i n v e r t e r , without a l l the adjustment c a p a b i l i t i e s , w i l l be used i n production versions of Cetec's equipment. 6.6 Conclusion The two applications discussed i n t h i s chapter i l l u s t r a t e the wide range of AC drives that can be designed using the in v e r t e r c o n t r o l l e r described i n t h i s t h e s i s . The two applications span a power range from 1.5 KW to 160 KW and involve the use of both power MOSFETs and t r a n s i s t o r s as the in v e r t e r power switches. Control panel and protection functions range from very simple i n the submersible thruster to quite complex i n the LIM drive. However these two applications do not come close to exhausting the c a p a b i l i t i e s of the invert e r c o n t r o l l e r . Drives using other control strategies such as co n t r o l l e d s l i p and other switching devices such as t h y r i s t o r s can be designed using t h i s i n v e r t e r c o n t r o l l e r . 154 Chapter 7 Conclusion An in v e r t e r c o n t r o l l e r has been described which has the following features: i . The c o n t r o l l e r controls PWM inverters using t r a n s i s t o r s , power MOSFETs, or t h y r i s t o r s as switches. i i . I t operates over an i n v e r t e r frequency range of at l e a s t 2 Hz to 600 Hz. i i i . Most of the c o n t r o l functions, with the exception of the generation of the PWM waveform, are performed by microcomputer software written i n the C programming language. i v . The pulse width modulated i n v e r t e r switching waveforms are generated by a large scale integrated c i r c u i t which i s c o n t r o l l e d by the microcomputer i n the i n v e r t e r c o n t r o l l e r . v. The i n v e r t e r c o n t r o l l e r i s contained on a single 7.5 cm by 21.5 cm (161 cm ) printed c i r c u i t board. The cost of parts and d i r e c t labor for the c o n t r o l l e r i s under $200. 155 The inve r t e r c o n t r o l l e r meets or exceeds the design objectives set out for i t i n Chapter 1 and Chapter 3. It has been used suc c e s s f u l l y i n two ap p l i c a t i o n s ; a submersible thruster drive and a l i n e a r induction motor drive. O v e r a l l , this i n v e r t e r c o n t r o l l e r design must be considered a success. The approach taken to the design of t h i s i n v e r t e r c o n t r o l l e r i s d i f f e r e n t than the approach taken i n much of the l i t e r a t u r e on PWM inverter c o n t r o l l e r s published i n the l a s t three or four years. Many of these papers (see, for example, papers by Green and Boys [81], Rajashekara and V i t h a y a t h i l [82], Pollman [83], Varnovitsky [84], and Buja and F i o r i n i [85]) concentrate on the design of the PWM waveform generator, studiously ignoring the a v a i l a b i l i t y of a p e r f e c t l y s a t i s f a c t o r y PWM generator i n LSI form. As a r e s u l t , the PWM generator dominates the design both i n terms of component count and design e f f o r t . The other functions required i n an inve r t e r c o n t r o l l e r often seem to be added as an afterthought, i f they are included at a l l . In contrast, a more balanced and "top down" approach was taken i n the design described i n t h i s t h e s i s . Design started with a c a r e f u l d e f i n i t i o n of a l l the objectives that the design had to meet and then proceeded with an evaluation of the methods av a i l a b l e to meet these objectives. The evaluation placed emphasis on f l e x i b i l i t y , compactness, and economy rather than on sheer performance or on novelty. 156 Another aspect of the design which distinguishes i t from many of the designs i n the l i t e r a t u r e i s the way that the i n v e r t e r c o n t r o l l e r can be rap i d l y adapted to new ap p l i c a t i o n s . This c a p a b i l i t y was achieved by a serie s of conscious design decisions throughout the design process. During the i n i t i a l system design, the design was pa r t i t i o n e d so that most c o n t r o l l e r functions are ca r r i e d out by microcomputer software with the c o n t r o l l e r hardware perfroming support functions. The microcomputer i n the c o n t r o l l e r was chosen with an eye to the a v a i l a b i l i t y of good, low cost software development t o o l s . F i n a l l y , the decision was made to write the software i n the C programming language i n order to speed the program development process. The f l e x i b i l i t y of t h i s i n v e r t e r c o n t r o l l e r i s not achieved e n t i r e l y without cost. The software intensive nature of the c o n t r o l l e r , the use of a microcomputer that has been a v a i l a b l e long enough to have good software development t o o l s , and the use of a high l e v e l programming language, combine to make the c o n t r o l l e r slower than i t otherwise might be. This w i l l p r i m a r i l y a f f e c t the c o n t r o l l e r ' s performance i n applications involving closed-loop c o n t r o l . However the dynamics of many AC drives are dominated by a high i n e r t i a load. In these cases a fas t c o n t r o l loop i s not required so the inverter c o n t r o l l e r can be used as a closed-loop c o n t r o l l e r . On the hardware side, t h i s i n v e r t e r c o n t r o l l e r i s distinguished by i t s compactness, achieved through the use of large scale 157 integrated c i r c u i t s . As noted i n the previous chapter, t h i s c o n t r o l l e r i s approximately one t h i r d the s i z e of the c o n t r o l l e r f o r a modern commercial t r a n s i s t o r i n v e r t e r , yet i s capable of better performance. However, the rapid development i n integrated c i r c u i t technology since the hardware design was completed now allows for some sub s t a n t i a l improvements i n the hardware design. As discussed i n Chapter 4, the frequency synthesizer that generates control signals for the PWM waveform generator IC can be s u b s t a n t i a l l y s i m p l i f i e d by using a new s i l i c o n gate version of the 4046 phase locked loop IC. In addition, the 4K byte 2732 EPROM can be replaced by a higher density EPROM such as the 2764 or 27128. A more d r a s t i c change would be to replace the I n t e l 8085 microprocessor with an I n t e l 80188 microprocessor. The 80188 has better computational c a p a b i l i t i e s than the 8085, i n p a r t i c u l a r i t has multiply and divide operations i n i t s i n s t r u c t i o n set. These operations are p a r t i c u l a r l y useful i n closed-loop control algorithms. In addition, the 80188 has b u i l t i n counter/timers that would be very useful when i n t e r f a c i n g the c o n t r o l l e r to sensors such as o p t i c a l shaft encoders. Since the software for the i n v e r t e r c o n t r o l l e r i s written primarily i n the C programming language, the transfer of software to the new microprocessor should be f a i r l y straightforward. Another possible improvement i s to redesign the i n v e r t e r c o n t r o l l e r printed c i r c u i t board to conform to the configuration 158 for a microcomputer system bus such as the STD bus. This would allow the c o n t r o l l e r to be r e a d i l y interfaced to microcomputer cards and various I/O cards. Some i n t e r e s t i n g i n v e r t e r c o n t r o l l e r designs would then be possible since some of the c o n t r o l l e r functions could then be transferred from the c o n t r o l l e r card to another microcomputer, thereby improving system throughput. For example, an AC servo drive could be designed with the c o n t r o l l e r card carrying out the PWM waveform generation and system protection functions under control of a microcomputer which would carry out the closed-loop c o n t r o l functions. The s c a l a r decoupled co n t r o l algorithm recently described by Bose [86] would be s u i t a b l e for a c o n t r o l l e r with t h i s type of a r c h i t e c t u r e . There i s also considerable p o t e n t i a l f o r further work with the c o n t r o l l e r operating i n i t s stand-alone form. Since the c o n t r o l l e r i s e a s i l y reprogrammed, i t can be used i n a v a r i e t y of AC drive a p p l i c a t i o n s . For example, a c o n t r o l l e d s l i p c ontrol scheme could be implemented f o r t r a c t i o n applications such as e l e c t r i c automobile or t r o l l e y bus d r i v e s . The maintenance and r e l i a b i l i t y advantages of a s i n g l e board inver t e r c o n t r o l l e r would be as a t t r a c t i v e i n these t r a c t i o n applications as i n the submersible thruster drive a p p l i c a t i o n . 159 References 1. B.K. Bose, "Adjustable Speed AC Drives - A Technology Status Review", IEEE Proceedings, v o l . 70, No. 2, pp. 116-135, February 1982 2. F. Peabody and K. Mauch, "A.C. Variable Speed Drives For Specialty Applications", F i n a l Report on B.C. Science Council Project #56 (RC-2), September 1981 3. F. Peabody, "A.C. Variable Speed Drives For Specialty Applications", F i n a l Report on B.C. Scince Council Project #37 (RC-5), September 1982 4. K.P. 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Ito, "A Multimicroprocessor AC Drive C o n t r o l l e r " , i n Conference Record IEEE Industry Applications Society 1980 Annual Meeting, pp. 634-640 58. W.J. Tuten, "Microprocessor C o n t r o l l e r f o r Integrated Power Module Inverter", i n Conference Record of the 1977 IEEE/IAS International Semiconductor Power Converter Conference, pp. 471-476 59. E. Dwyer and B.T. Ooi, "A Lookup Table Based Microprocessor C o n t r o l l e r f o r a Three Phase PWM Inverter" i n Conference Record of the IEEE/ IECI 1979 Conference on I n d u s t r i a l Applications of Microprocessors, pp. 19-22 60. L. Humblet, F. De Buck, B. Verbecke, P. De Valck, 11 A Re a l i s a t i o n Example of a Microprocessor Driven PWM Transistor Inverter", i n Conference Record of IEE Power D i v i s i o n 2nd International Conference on E l e c t r i c a l Variable Speed Drives, pp. 151-156, 1979 61. H.S. Pat e l , " T h y r i s t o r Inverter Harmonic Elimination Using Optimization Techniques", Ph.D. D i s s e r t a t i o n , University of Missouri-Columbia, 1971 62. Signetics Corporation, P h i l l i p s AC Motor Co n t r o l l e r Product Information, A p r i l 1981 63. S.R. Bowes and B.M. B i r d , "Novel Approach to the Analysis and Synthesis of Modulation Processes i n Power Convertors", Proceedings of the IEE, v o l . 122, no. 5, pp. 507-513, May 1975 64. S. Morinaga et. a l . , "Microprocessor Control System with I/O Processing LSI f o r Motor Drive PWM Inverter", i n Conference Record of IEEE/IAS 1981 Annual Meeting, pp. 1197-1202 65. P h i l i p s LOCMOS HE4000B I.C. Family, Signetics Corp., Sunnyvale CA, p. 689, September 1981 66. F.M. Gardner, Phaselock Techniques, 2nd ed., New York: Wiley, 1979, Chapter 6 67. Am9500 Peripheral Products Interface Guide, Advanced Micro Devices, Sunnyvale CA, p. 4-48, 1980 68. COS/MOS Integrated C i r c u i t s , RCA Corp., Somerville NJ, p. 179, 1980 164 69. 1981 Supplement to the TTL Data Book f o r Design Engineers, Texas Instruments Inc., Dallas TX, p. 149, 1981 70. "The RCA COS/MOS Phase-Locked-Loop: A V e r s a t i l e Building Block f o r Micro-Power D i g i t a l and Analog App l i c a t i o n s " , RCA Applications Note ICAN-6101, RCA Corp., Somerville NJ, 1981 71. B.W. Kernighan and D.M. R i t c h i e , The C Programming Language, Englewood C l i f f s NJ: Prentice-Hall, 1978 72. J . Gilbreath, "A High-Level Language Benchmark", BYTE, v o l . 6, no. 9, pp. 180-198, September 1981 73. J . Gilbreath and G. Gilbreath, "Eratosthenes Rev i s i t e d : Once More through the Sieve", BYTE, v o l . 8, no. 1, pp. 283-326, January 1983 74. G.E. Anderson and K.C. Shumate, "Selecting a Programming Language, Compiler, and Support Environment: Method and Example", Computer, v o l . 15, no. 8, pp. 29-36, August 1982 75. S.T. Allworth, Introduction to Real-Time Software Design, New York: Springer Verlag, 1981, pp. 100-109 76. J.V. Landau, "State Description Techniques Applied to I n d u s t r i a l Machine Control", Computer, v o l . 12, no. 2, pp. 32-40, February 1979 77. J.G Gander and H.U. L i e c h t i , "State Language for Real-Time Process Control", Microprocessors and Microsystems, v o l . 5, no. 1, pp. 27-28, Jan/Feb 1981 78. H.A. Sutherland, B.K. Bose and C.B. Somuah, "A State Language fo r Sequencing i n a Hybrid E l e c t r i c Vehicle", IEEE Trans. Ind. E l e c t r o n i c s , v o l . IE-30, no. 4, pp. 318-322, November 1983 79 Mitsubishi VVVF Transistor Inverter Freqrol-E Service Manual, Mitsubishi E l e c t r i c Corp., Tokyo 80. E. Ohno et. a l . , "General Purpose Variable Frequency Inverter Using Integrated Power Module and LSI", i n Conference Record IEEE 1982 Power El e c t r o n i c s S p e c i a l i s t s Conference, pp. 478-487 81. R.M. Green and J.T. Boys, "Implementation of Pulsewidth Modulated Inverter Modulation Strategies", IEEE Trans. Ind. Applications, v o l . IA-18, no. 2, pp. 138-145, March/April 1982 82. K.S. Rajashekara and J . V i t h a y a t h i l , "Microprocessor Based Sinusoidal PWM Inverter by PWM Transfer", IEEE Trans. Ind. E l e c t r o n i c s , v o l . IE-29, no. 1, pp. 46-51, Feb. 1982 83. A. Pollman, "A D i g i t a l Pulsewidth Modulator Employing Advanced 165 Modulation Techniques", IEEE Trans. Ind. Applications, v o l . IA no. 3, pp. 409-413, May/June 1983 84. M. Varnovitsky, "A Microcomputer-Based Control Signal Generator for a Three-Phase Switching Power Inverter", IEEE Trans Ind. Applications, v o l . IA-19, no. 2, pp. 228-234 March/April 1983 85. G.S. Buja and P. F i o r i n i , "Microcomputer Control of PWM Inverters" IEEE Trans. Ind. E l e c t r o n i c s , v o l . IE-29, no.3, pp. 212-216, August 1982 86. B.K. Bose, "Scalar Decoupled Control of Induction Motors", IEEE Trans. Ind. Applications, v o l . IA-20, no. 1, pp. 216-225, January/February 1984 166 Appendix Control Program f o r _1 kW MOSFET Inverter f o r  Submersible Thruster Drives /* This program controls the operation of a PWM invert e r used to supply power to a variable speed induction motor drive. The actual pulse width modulation i s performed by a s p e c i a l purpose integrated c i r c u i t manufactured by Signetics. The control program performs the o v e r a l l sequencing and control functions required by the drive. On power up, the control program enters an i n i t i a l i z a t i o n routine [ i n t i a l i z e ( ) ] which performs various i n i t i a l i z a t i o n functions. The PWM IC i s con t r o l l e d by a set of va r i a b l e frequency pulse t r a i n s which determine the in v e r t e r output frequency (FCT), v o l t s per Hertz r a t i o (VCT) and maximum device switching frequency (RCT). These frequencies are supplied by a computer co n t r o l l e d frequency synthesizer consisting of an AMD 9513 counter/timer, 4046 phase locked loop chips, and 74LS628 VCO chips. The f i r s t part of the i n i t i a l i z a t i o n simply sets up the 9513 counter/timer IC so that the proper frequencies can be generated. The timer i n the 8156 RAM-I/0 chip i s set up to interrupt the 8085 microprocessor every 5 milliseconds. The PWM chip i s also reset i n the i n i t i a l i z a t i o n routine and some variables are i n i t i a l i z e d . After the i n i t i a l i z a t i o n routine, the c o n t r o l l e r acts as a simple state machine. The c o n t r o l l e r i s always i n one of the following states: 1. OFF The on/off switch i s off and the invert e r i s o f f . The speed control has no e f f e c t . 2. STOPPED The on/off switch i s on and the speed co n t r o l i s i n the zero p o s i t i o n . The i n v e r t e r i s o f f . 3. ACCELERATING The on/off switch i s on and the speed control i s commanding an in v e r t e r frequency higher than the present inve r t e r frequency. The invert e r frequency i s incremented by 0.5 Hz every time t h i s state i s entered. Since the state machine sequencing i s c o n t r o l l e d by the 5 millisecond clock interrupt t h i s corresponds to an ac c e l e r a t i o n rate of 100 Hz/sec. 4. CONSTANT SPEED The on/off switch i s on and the speed control i s commanding an in v e r t e r frequency equal to the present inve r t e r frequency. 167 5. DECELERATING This state i s entered when a) The on/off switch i s turned off while the in v e r t e r i s operating b) The on/off switch i s on and the speed control i s requesting a motor speed i n the opposite d i r e c t i o n to the present d i r e c t i o n . c) The on/off switch i s on and the speed control i s commanding an inverte r frequency lower than the present i n v e r t e r frequency. The i n v e r t e r frequency i s decreased by 0.5 Hz on every entry into t h i s s t a t e . This corresponds to a deceleration rate of 100 Hz/sec. 6. FAULT This state i s entered a f t e r the TRAP inte r r u p t on the 8085 has received FAULTNUM of overcurrent signals from the i n v e r t e r . To prevent a widely spaced set of overcurrent signals (possibly created by noise) from eventually causing the in v e r t e r to enter the f a u l t state, the counter keeping track of the number of overcurrent signals i s decremented on every 5 milli s e c o n d timer i n t e r r u p t . As a r e s u l t , the count w i l l only increase i f there i s a rapid succession of overcurrent signals as wou occur i n a r e a l f a u l t . The in v e r t e r i s off i n the f a u l t s t ate. The c o n t r o l l e r waits u n t i l the speed co n t r o l i s reset to zero and then causes a t r a n s i t i o n to the stopped state so that the in v e r t e r can be restarted i f desired. /* D e f i n i t i o n of Constant Values */ /* I n t e l 8156 RAM/10 chip r e g i s t e r addresses (I/O mapped) */ //define COM_STATUS_8156 0x10 //•define PORTA 0x11 //define PORTB 0x12 //define PORTC 0x13 //define TIMER_LSB 0x14 //define TIMER_MSB 0x15 /* AMD 9513 Counter/Timer chip r e g i s t e r addresses (I/O mapped) */ //define COMMAND_REG_9513 0X41 //define DATA_REG_9513 0x40 /* AMD 9513 i n t e r n a l r e g i s t e r s */ 168 //define MASTER MODE 0x17 //define CNTR1MODE 0x01 //define CNTR1LOAD 0x09 //define CNTR2MODE 0x02 //define CNTR2LOAD 0x0a //define CNTR3MODE 0x03 //define CNTR3LOAD Ox Ob //define CNTR4M0DE 0x04 //define CNTR4L0AD OxOc //define CNTR5MODE 0x05 //define CNTR5L0AD OxOd //define REFREG CNTR1L0AD //define FREQREG1 CNTR2L0AD //define FREQREG2 CNTR5L0AD //define VCTREG CNTR4L0AD //define RCTREG CNTR3L0AD //def ine START 9513 0x7F /* 9513 s t a r t command */ /* National ADC 0808 analog to d i g i t a l converter addresses (I/O mapped)*/ //define ADC 0x80 //define ADCO 0x80 /* A/D Converter */ /* Channel 0 Address */ /* Some macros to handle various inputs and outputs */ //define FREQ_SPEED_POT_SETTING adcin(ADCO) /* Frequency/Speed control pot connected to A/D channel 0 */ //define FORWARD output(P0RTB,portb=0xl0 | portb) //define REVERSE output (PORTB ,portb=0xEF & portb) /* CW input (phase sequence) to PWM chip i s from p i n 4 of port B */ //define RESET_PWM_CHIP output(PORTB,portb=0x4 | portb) //define PWM_CHIP_RESET_OFF output(P0RTB,portb=0xFB & portb) /* A input (reset) to PWM chip i s from pin 2 of port B */ 169 //define SELECT_LO_FREQ_FCT out put (PORTC, 0x01) //define SELE CT_HI_FREQ_F CT output (PORTC, 0x02) /* Active frequency synthesizer for generation of FCT i s selected by */ /* pins 0 and 1 on Port C */ /* Macros for switch states */ //define ON 0x1 /* ON/OFF switch must be at +5V when ON */ //define OFF 0x0 /* Macros for i n v e r t e r operation states */ //define OFFSTATE 0x0 //define STOPSTATE 0x1 //define ACCSTATE 0x2 //define DECSTATE 0x3 //define CONSTSTATE 0x4 //define FAULTSTATE 0x5 //define INTERRUPT MASK OxlB /* Only Int 7.5 enabled */ /* some macros for various wait times */ //def ine HALFSEC 50000 /* app. 0.5 seconds */ //define HUNDREDMICROSEC 10 /* app. 100 microseconds */ /* some simple macros f o r flags and l o g i c a l switches */ //define TRUE 1 //define FALSE 0 //define FWD 1 //define REV 0 //define FAULTNUMBER 5 /* number of overcurrent interrupts required to shut down the i n v e r t e r */ /* External Variables */ char c l o c k t i c k ; /* f l a g to i n d i c a t e that a 5 millisecond clock interrupt has occurred */ char nexstate; /* contains number corresponding to the state the inverter c o n t r o l l e r i s to enter */ char f a u l t f l a g ; /* f l a g to i n d i c a t e that the i n v e r t e r i s to enter the f a u l t state */ char ovccount; /* contains count of the number of overcurrent interrupts received from the i n v e r t e r on the 8085 TRAP input */ char p r _ d i r e c t i o n ; /* f l a g i n d i c a t i n g present phase sequence of i n v e r t e r */ char directioncommand; /* f l a g i n d i c a t i n g phase sequence setpoint */ i n t pr_frequency; /* contains present i n v e r t e r output frequency */ i n t freqload; /* contains value to be loaded into 9513 to set 170 i n v e r t e r output frequency */ i n t frequencycommand; /* contains inve r t e r frequency setpoint */ i n t oldvalue; /* contains previous value of speed pot s e t t i n g */ char portb; /* contains status of Port B i n 8156 I/O RAM chip */ /* Main function f i r s t i n i t i a l i z e s the system and then loops continuously */ main() { i n i t i a l i z e ( ) ; while (ON) { c l o c k t i c k = 0; /* c l o c k t i c k set to 1 by int75() */ i f ( f a u l t f l a g == TRUE) nexstate = FAULTSTATE; switch (nexstate) /* State sequencer */ { case OFFSTATE : o f f ( ) ; break; case STOPSTATE : stopped(); break; case ACCSTATE : a c c e l e r a t i n g ( ) ; break; case DECSTATE : de c e l e r a t i n g ( ) ; break; case CONSTSTATE : constantspeed(); break; case FAULTSTATE : f a u l t ( ) ; break; default : f a u l t ( ) ; break; } while (!clocktick) ; /* Loop while waiting f o r next clock i n t e r r u p t * / } i n i t i a l i z e ( ) { /* I n i t i a l i z e 9513 Counter/Timer */ 171 output(C0MMAND_REG_9513, OxFF); /* Master reset for 9513 */ /* Master Mode Register */ s e t u p _ 9 5 1 3(MASTER M O D E , 0 x c 3 0 0 ) ; /* Set up 9513 f o r : /* - BCD d i v i s i o n on the scaler /* - 8 b i t data bus /* - FOUT = Fl/3 /* - Comparators and Time of Day disabled */ */ */ */ */ /* Counter 1 */ setup 9513(CNTRlMODE,0xB23); /* Counter 1 set up f o r r e p e t i t i i v e count from load r e g i s t e r with */ /* source = F l */ setup_9513(CNTRlLOAD,1784); /* Counter 1 set to divide by 1784 to produce a 841 Hz reference */ /* frequency for the PLLs */ /* Counter 2 */ s e tup_9 513(CNTR2M0DE,Ox 2 2 3); /* Counter 2 set up for r e p e t i t i v e count from load r e g i s t e r with */ /* source = SRC2. Acts as control r e g i s t e r f o r the low frequency */ /* FCT o s c i l l a t o r . */ /* Inverter output frequency = Counter 2 Load Register/2 */ /* Counter 3 */ setup_9513(CNTR3M0DE,OxB23); /* Counter 3 set up for r e p e t i t i v e count from load r e g i s t e r with */ /* source = F l . Counter 3 i s the RCT frequency source. I t i s */ /* set to 280*fswitch */ setup_9513(CNTR3L0AD,1); /* RCT i n i t i a l i z e d to 1.5 MHz. Inverter switching frequency i s */ /* about 5.5 kHz. */ /* Counter 4 */ 172 se tup_9 513(CNTR4M0DE,0x4 2 3); /* Counter 4 i s set up f o r r e p e t i t i v e count from the load r e g i s t e r /* with source = SRC4. Counter 4 i s the control r e g i s t e r for the /* VCT o s c i l l a t o r . VCT frequency = 1682 * Counter 4 load r e g i s t e r setup_9513(VCTREG, 1600); /* Set VCT for 100% modulation at 400 HZ /* Counter 5 */ setup_9513(CNTR5M0DE,0x523); /* Counter 5 i s set up for r e p e t i t i v e count from the load r e g i s t e r /* with source = SRC5. Counter 5 i s the control r e g i s t e r f o r the /* high frequency FCT o s c i l l a t o r . /* Inverter output frequency = Counter 5 load register/2 /* 8156 I/O - Timer I n i t i a l i z a t i o n */ output(TIMERJLSB, 0x88); output(TIMER_MSB, 0xD3); output(C0M_STATUS_8156, OxCE); /* 8156 Timer set to divide by 5000 (200 Hz out) /* 8156 Port A = input, Port B = output, Port C = output /* i n i t i a l i z e some variables */ portb = ovccount = 0; f a u l t f l a g = FALSE; /* i n i t i a l i z e i n v e r t e r frequency to 3 Hz */ pr_frequency = 3; setup_9513(FREQREGl,6); setup_9513(FREQREG2,6); SELECT_L0_FREQ_FCT; /* Start 9513 */ output(COMMAND_REG_9513, START_9513); /* I n i t i a l i z e PWM chip */ RESET_PWM_CHIP; wait(HALFSEC); PWM_CHIP_RESET_OFF; /* Set up i n i t i a l state */ nexstate = 0FFSTATE; /* Set up interrupt mask and enable interrupts */ 173 sim(INTERRUPT_MASK); enable(); } /* adcin Function */ /* Returns 8 b i t value (as i n t ) from A/D channel whose address i s */ /* s p e c i f i e d by "num" */ adcin(num) char num; { output(num,0); wait(HUNDREDMICROSEC); return(input(ADC)); } /* wait Function */ /* Acts as a delay function. Delays approximately "time" * 10 */ /* microseconds when used with a 3 MHz 8085 . */ wait(time) unsigned time; { //asm POP H POP D PUSH D PUSH H LOOP: XRA A DCX D NOP ORA D ORA E JNZ LOOP //endasm } /* int75 function */ /* Interrupt service routine. Responds to timer interrupt and gets */ /* speed command from A/D converter. Then calculates the frequency */ /* and d i r e c t i o n setpoints */ int75() { 174 i n t newvalue, raw; newvalue=FREQ_SPEED_POT_SETTING; if(abs(newvalue-oldvalue) > 1) /* Check f o r s i g n i f i c a n t change i n */ oldvalue=newvalue; /* value. */ /* Frequency setpoint i s input as an 8 b i t signed number i n o f f s e t binary format */ i f ((raw = oldvalue - 128) > 0) /* convert to standard format and */ directioncommand = FWD; /* determine d i r e c t i o n setpoint */ else directioncommand = REV; i f ((raw = abs(raw) - 9) < 0) frequencycommand =3; /* A deadband i s l e f t around the zero point */ else frequencycommand = (raw*10)/3 +3; /* max frequency = 400 Hz */ i f (ovccount > 0) /* Make sure that a widely spaced set of overcurrent*/ ovccount—; /* interrupts don't shut down the in v e r t e r */ c l o c k t i c k = 1; } /* trap function */ /* Trap interrupt service routine counts the number of overcurrent interrupts received from the i n v e r t e r . If the number exceeds a l i m i t , the inverter i s shut off and the f a u l t f l a g i s set */ t r a p Q { i f (-H-ovccount > FAULTNUMBER) { stop(); f a u l t f l a g = TRUE; } } /* o f f function */ /* Carries out the functions required for the invert e r o ff state */ o f f ( ) { stop(); i f ( o n _ o f f _ s w i t c h ( ) == ON) nexstate = ST0PSTATE; /*else nexstate = OFFSTATE;*/ } /* stopped function */ /* Carries out the functions required for the in v e r t e r stopped state */ 175 stopped() { s t o p Q ; if(directioncommand == FWD) { FORWARD; pr _ d i r e c t i o n = FWD; } else { REVERSE; p r _ d i r e c t i o n = REV; } freqload =6; /* Set invert e r frequency to 3 Hz */ setfrequency(freqload); /* determine next state */ i f (on_off_switch() == OFF) nexstate = OFFSTATE; else if(frequencycommand>3) nexstate = ACCSTATE; else /* nexstate = STOPSTATE*/; } /* accelerating function */ /* Carries out functions required while inve r t e r i s increasing i t s frequency */ acc e l e r a t i n g ( ) { i f ( f a u l t f l a g == FALSE) s t a r t ( ) ; /* check i f t r a n s i t i o n to another state i s required */ i f ( o f f_or_rev()) nexstate = DECSTATE; else i f ( p o s _ f r e q _ e r r o r ( ) ) nexstate = DECSTATE; else i f ( z e r o _ f r e q _ e r r o r ( ) ) nexstate = CONSTSTATE; else { /* nexstate = ACCSTATE; */ i n c _ f requency(); } } /* constantspeed function */ constantspeed() 176 { i f ( f a u l t f l a g == FALSE) s t a r t ( ) ; i f ( o f f _ o r _ r e v ( ) ) nexstate = DECSTATE; else i f ( p o s _ f r e q _ e r r o r ( ) ) nexstate = DECSTATE; else i f ( n e g _ f r e q _ e r r o r ( ) ) nexstate = ACCSTATE; else /* nexstate = CONSTSTATE;*/; } /* decelerating function */ decelerating() { i f ( f a u l t f l a g == FALSE) s t a r t ( ) ; if(pr_frequency < 3) nexstate = STOPSTATE; else i f ( o f f _ o r _ r e v ( ) ) { /* nexstate = DECSTATE; */ dec_f requency(); } else i f ( p o s _ f r e q _ e r r o r ( ) ) { /* nexstate = DECSTATE; */ dec_f requency(); } else i f ( n e g _ f r e q _ e r r o r ( ) ) nexstate = ACCSTATE; else nexstate = CONSTSTATE; } /* Functions implementing various tests required to determine the next */ /* state or actions to be c a r r i e d out */ of f_or_rev( ) { return(on_off_switch()==OFF||directioncommand!=pr_direction); } pos_freq_error() { return(frequencycommand < pr_frequency); } zero_f req_error() { return(frequencycommand == pr_f requency); 177 } neg_f req_error() { return(pr frequency < frequencycommand); /* inc_frequency function */ /* Increases inve r t e r frequency by 0.5 Hz */ i n c _ f requency() { freqload++; setfrequency(freqload); } /* dec_frequency function */ /* As for inc_frequency except frequency i s decreased */ dec_f requency() { f r e q l o a d — ; setfrequency(freqload); } /* setfrequency function */ /* Programs 9513 f o r desired frequency and s e l e c t s appropriate VCO for */ /* FCT generation. */ setfrequency(value) i n t value; { pr_f requency=value/2; d i s a b l e ( ) ; /*disable interrupts */ s y n c l Q ; /* synchronize to 9513 counter to avoid contention over access to load r e g i s t e r */ setup_9 513(FREQREG1.value); sync2(); /* synchronize again */ setup_9513(FREQREG2,value) ; enable(); /* reenable interrupts */ i f ( v a l u e > 250) /* i f in v e r t e r frequency > 125 Hz */ SELECT_HI_FREQ_FCT; /* use high frequency VCO */ else SELECT_LO_FREQ_FCT; } /* syncl() function */ /* Synchronizes loading of new count for counter #2 (FREQREG1) with s t a r t of new count i n counter #2, thus avoiding c o n f l i c t over use of Load r e g i s t e r */ syncl() 178 { //asm IN 41H ; READ 9513 STATUS REG ANI 4 ; MASK OFF COUNTER 2 OUTPUT STATUS BIT MOV B,A ; SAVE IT Ml: IN 41H ANI 4 ; KEEP CHECKING COUNTER 2 OUTPUT FOR A CMP B ; CHANGE JZ Ml ; CHANGE INDICATES START OF NEW COUNT //endasm } /* sync2() function */ /* As for syncl() except checking counter #5 (FREQREG2) */ sync2() { //asm IN 41H ANI 20H MOV B,A M2: IN 41H ANI 20H CMP B JZ M2 //endasm } /* f a u l t function */ /* Wait u n t i l the frequency setpoint i s reduced to 3 Hz. Then reset the f a u l t variables ( f a u l t f l a g & ovccount) and set up the c o n t r o l l e r to enter the "stopped" s t a t e . */ f a u l t ( ) { while ( frequencycommand > 3 ) on_overcurrent_indicator(); f a u l t f l a g = FALSE; ovccount = 0; of f _ o v e r c u r r e n t _ i n d i c a t o r ( ) ; nexstate = STOPSTATE; } /* Functions to read switch status or to output control signals */ on_off_switch() /* Inverter on-off switch connected to pin 0 */ { ~ /* of Port A */ //asm IN 11H ANI 1 MOV L,A 179 MVI #endasm } H,0 s t a r t ( ) /* L input (on/off) to PWM chip i s from p i n 3 of */ { /* Port B. Green LED (on/off i n d i c a t o r ) i s */ /* connected to pin 0 of Port B */ output(PORTB,portb=0x9|portb); } S t O p Q { output(PORTB,portb= 0xF6 & portb); } on_overcurrent_indicator() { output(PORTB,portb=0x2|portb); } /* Yellow LED connected to p i n 1 of Port B */ of f_overcurrent_indicator() { output(PORTB,portb= OxFD & portb); } setup_9513(reg,val) i n t r { //asm #endasm } /* Loads a 16 b i t value into the frequency */ v a l ; /* control r e g i s t e r s of POP H ; return address POP D ; v a l POP B 5 reg PUSH B PUSH D PUSH H MOV A,C OUT 41H ;9513 command r e g i s t e r MOV A,E OUT 40H ;9513 data r e g i s t e r MOV A,D OUT 4 OH ;9513 data r e g i s t e r 180 

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