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GaAs material investigation for integrated circuits fabrication Dindo, Salam 1985

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GaAs MATERIAL INVESTIGATION FOR INTEGRATED CIRCUITS FABRICATION By SALAM DINDO B.A.Sc, The University of British Columbia, 1982 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE i n THE FACULTY OF GRADUATE STUDIES Department of Electrical Engineering We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA October 1985 © Salam Dindo, 1985 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date DE-6(3/81) ABSTRACT The primary objective of the work described in this thesis was to study the influence of undoped LEC GaAs substrate material from various suppliers on the performance of ion implanted and annealed active layers. Optical transient current spectroscopy (OTCS) was investigated as a qualification test for GaAs substrates. Deep level spectra of the substrates before ion implantation were obtained. It was found that while the OTCS spectra of high pressure grown GaAs from two suppliers were similar, that of the low pressure material showed different relative concentration of traps. The use of OTCS was further extended to study trap concentration as a function of surface treatment. It was found that the use of chemical etchants reduces the concentration of some levels, possibly those located on the surface as opposed to bulk traps. Surface damage was found to enhance the negative peak in the OTCS spectrum. The deep levels spectra were found to be affected by the geometry of the device and the type of electrode material. Channel current deep level transient spectroscopy (DLTS) was used to study both process- and substrate-induced deep levels in ion implanted MESFET channels. The spectra of process-induced traps were found to be different according to the encapsulant used. Silicon dioxide (both RF sputtered and plasma enhanced chemically vapor deposited (PECVD)) was found to induce a variety of process related defects. This is believed to be because s i l i c o n dioxide is permeable to gallium and hence does not preserve the stoichiometry - i i i -of ion implanted GaAs during high temperature anneals. Deep level spectra of MESFETs annealed using si l i c o n nitride, on the other hand, were found to contain single traps related to the defects in the starting material. For implants through sil i c o n nitride, a high concentration of the main electron trap EL2 was found, whereas implants directly into the surface resulted in the level EL12. Comparison of the characteristics of the variety of LEC undoped GaAs material show that they differed widely and had inhomogeneous properties. For example, compared to the high pressure grown GaAs, the Litton*s low pressure substrate had lower activation, mobility, drain current and threshold voltage, good confinement of the scatter in the same characteristics, low concentration of deep levels, and the least backgating effect which makes i t promising for IC fabrication. Comparison of the high pressure grown material from two suppliers showed that Cominco's recent material had good mobility, activation, relatively high scatter of threshold voltage, high concentration of deep levels, and was affected by backgating. In comparison, Sumitomo's material showed thermal instability, less scatter of threshold voltage, less mobility and deep level concentrations, and similar backgating characteristics. Substrate grown three years earlier showed higher diffusion of dopant, different deep levels, and better backgating characteristics. Finally, a substrate which had failed the qualification test by a device manufacturer showed minimal diffusion t a i l s and threshold voltage scatter, the highest concentration of deep levels, and substantial backgating. - iv -TABLE OF CONTENTS Page ABSTRACT i i LIST OF TABLES v i LIST OF FIGURES v i i ACKNOWLEDGEMENTS ix INTRODUCTION 1 GROWTH AND PROPERTIES OF SEMI-INSULATING GALLIUM ARSENIDE 3 Introduction 3 GaAs Crystal Growth Techniques 3 Impurities and Their Role in Undoped LEC GaAs... 6 Relation of Melt Stoichiometry to Compensation and Thermal Stability of GaAs 8 2.5 Recent Advances in the Growth of Undoped LEC GaAs 10 3. OPTICAL TRANSIENT CURRENT SPECTROSCOPY INVESTIGATION OF VARIOUS GaAs SUBSTRATES 13 3.1 Introduction to Optical Transient Current Spectroscopy...... 13 3.2 Theory of Optical Transient Current Spectroscopy 14 3.3 Experimental Procedure 19 3.4 Results.... 21 3.4.1 OTCS Spectra of GaAs Substrates From Three Vendors... 24 3.4.2 Identification of the Peaks 27 3.4.3 Effects of Varying Sample Geometry on OTCS Spectra... 33 - v -Page 3.4.4 Effect of Varying the Electrode Material 35 3.4.5 Effect of GaAs Surface Damage on the OTCS Spectrum... 39 3.5 Summary 44 4. INVESTIGATION OF PROCESS-INDUCED DEEP LEVELS IN ION IMPLANTED MESFETs 45 4.1 Introduction 45 4.2 Principle of Channel Current DLTS 47 4.3 Experimental Procedure 52 4.4 Results 54 5. INFLUENCE OF VARIOUS LEC UNDOPED GaAs SUBSTRATES ON THE CHARACTERISTICS OF ION IMPLANTED AND ANNEALED ACTIVE LAYERS 66 5.1 Introduction 66 5.2 Description of the Diagnostic Test Pattern 69 5.3 Diagnostic Pattern Fabrication 69 5.4 Measurements on the Diagnostic Test Pattern 75 5.5 Results of Active Layer Evaluation 78 5.6 Results on Deep Levels 89 5.7 Results on Backgating 98 5.8 Discussion of Results 101 5.9 Summary 106 6. CONCLUSIONS AND SUGGESTIONS FOR FURTHER WORK 107 REFERENCES 110 - v i -LIST OF TABLES Page 2.1 Order of magnitudes of some common impurities found in SI, undoped, LEC GaAs 7 3.1 Activation energies, capture cross sections, and possible identities of the deep levels found using OTCS (Pl-8) in SI, undoped, LEC GaAs 29 3.2 Deep levels in SI GaAs reported in the literature (as detected by OTCS (PITS)). VPE = Vapour Phase Epitaxy 30 4.1 Activation energies, capture cross sections, and possible identities of the deep levels found using channel current DLTS in MESFETs fabricated using four processes (Q1-4.R1,SI,Tl-4) 62 4.2 Some deep levels in s i l i c o n implanted GaAs reported in the literature 64 5.1 Comparison of the active ion implanted layers parameters of five GaAs samples 80 5.2 DLTS data on the traps found by channel current DLTS 96 5.3 Concentration of traps found by channel current DLTS 96 5.4 Comparison of the calculated values of effective straggle (AR"), diffusion coefficient (D'), pinchoff voltage (V ), and threshold voltage (V t^) of five GaAs samples 105 - v i i -LIST OF FIGURES Page 3.1 Geometry of (a) planar and (b) sandwich structures used in OTCS 20 3.2 Block diagram of the OTCS setup 22 3.3 Vacuum chamber used in the OTCS experiment 23 3.4 OTCS spectra of SI undoped LEC GaAs from three vendors (Rate Window = 8.5 msec) 25 3.5 OTCS spectra of SI undoped LEC GaAs substrates from two vendors subjected to chemical etch (Rate Window = 8.5 msec) 26 3.6 Activation energy plots for traps detected using OTCS 28 3.7 OTCS spectra of different planar sample geometries (Rate Window = 18.9 msec) 34 3.8 OTCS spectra of samples prepared with different electrodes (Rate Window = 38.8 msec) 36 3.9 Current vs. voltage for planar specimens with different electrodes 38 3.10 Signature line plots for the data of figure 3.9 (Labels same as in figure 3.9) 40 3.11 OTCS spectra of sandwich structures with a negative bias on the top illuminated electrode (Rate Window = 75.5 msec) 42 3.12 OTCS spectra of a planar structure (a) before and after chemical etch (b) after light abrasion (c) after chemical etch (Rate Window = 75.5 msec) 43 4.1 Schematic diagram showing the channel current DLTS measurement system 48 4.2 Transient responses of the drain current to an applied gate voltage 49 4.3 Block diagram of channel current DLTS system 55 - v i i i -Page 4.4 Channel current DLTS spectrum for MESFETs prepared using process 1 56 4.5 Channel current DLTS spectrum for MESFETs prepared using process II 57 4.6 Channel current DLTS spectrum for MESFETs prepared using process III 58 4.7 Channel current DLTS spectrum for MESFETs prepared using process IV 59 4.8 Signature line plots for channel current DLTS data of processes I-III 60 4.9 Signature line plots for channel current DLTS data of process IV 61 5.1 The diagnostic test pattern 70 5.2 Fabrication sequence for the diagnostic test pattern 72 5.3 Typical I D S - V D S characteristics of MESFETs in the diagnotic test pattern 79 5.4 As-implanted, calculated, and measured carrier density profiles and d r i f t mobility profiles 82 5.5 Channel current DLTS spectra for MESFETs fabricated on five substrates (Rate Window = 49.7 msec) 90 5.6 Signature line plots of the channel current DLTS data 95 5.7 Comparison of normalized drain current versus backgating voltage for five GaAs samples 100 ACKNOWLEDGEMENTS I thank my supervisor, Dr. L. Young, for his guidance and for suggesting many of the ideas of my work. Mr. Wade Tang is to be thanked for his assistance in the DLTS experiments and for his helpful discussions. I also thank Messrs. I.A. Motaleb, P. Townsley, and K. Tan for their assistance in fabrication; D. Hui for writing the software routines used to prepare some of the figures; W.C. Rutherford for proofreading my thesis; and W. Durtler, M. LeNoble, N. Jaeger, and P. Neilson for the helpful discussions. Appreciation is also due to Messrs. R.F. Redden and R.P. Bult of Cominco Ltd., and K. Lowe of Bell Northern Research for supplying some GaAs wafers; A. Lakhani of Allied Bendix Aerospace for preparing some of the samples used in the channel current DLTS measurements; A. Leugner and L. Kjolby, who maintained the equipment in the lab; and Ms. M. Depuit who typed the manuscript. Financial support provided by the British Columbia Science Council and by the Natural Sciences and Engineering Research Council of Canada is also acknowledged. 1 CHAPTER 1 INTRODUCTION Formation of uniformly doped impurity layers in bulk grown GaAs substrates for integrated circuit (IC) fabrication by ion implantation offers more advantages than the use of doped epitaxial grown layers because of the ease, precise control and reproducibility of the implantation process. Of the two available bulk crystal growth methods, Horizontal Bridgman (HB) and Liquid-Encapsulated Czochralski (LEC), the former has found decreasing applications in IC fabrication because of the limitation of the size and shape of HB substrates, and because of low device yield. LEC grown GaAs, on the other hand, is becoming the dominant choice for IC fabrication because two to four inch diameter wafers can be grown, and because semi-insulating (SI) GaAs can be made without intentional addition of impurities. The objectives of this thesis are to investigate undoped LEC GaAs substrates for IC fabrication. GaAs wafers from different vendors were obtained. The deep trapping levels in SI GaAs wafers were investigated using Optical Transient Current Spectroscopy (OTCS). Deep levels in ion implanted MESFETs fabricated using several different processing techniques were investigated by channel current Deep Level Transient Spectroscopy (DLTS). The processing techniques applied for MESFET fabrication included: ( 1 ) ion implantation directly into GaAs; and ( 2 ) ion implantation through Plasma Enhanced Chemically Vapor Deposited (PECVD) si l i c o n nitride film. Several dielectric capping materials for high temperature anneals were used: ( 1 ) RF 2 sputtered silicon dixoide; (2) PECVD silicon dioxide; and (3) PECVD silicon nitride. Active layer parameters of various ion implanted substrates were investigated and compared. The measurements used to assess the MESFETs were: (1) threshold voltage and drain current magnitudes and scatter; (2) sheet resistance, Hall mobility and undepleted carrier concentration; (3) carrier and d r i f t mobility profiling, and (4) backgating. The contents of the thesis are as follows: Chapter 2 gives an overview of SI GaAs crystal growth techniques with particular emphasis on undoped LEC GaAs technology. In Chapter 2, a review is presented on deep levels in the starting SI GaAs materials, and a comparison is made of the OTCS spectra of GaAs substrates from different suppliers. Influence of surface treatment on the OTCS spectra is also investigated. Chapter 4 details the results of deep level investigation in the MESFETs fabricated by the four different processing techniques described above. The objective being to find and compare process-induced deep levels. Chapter 5 contains a comparison of MESFETs made by the same process at the same time on GaAs wafers from three suppliers, including: (1) low and high pressure grown substrates; (2) high pressure grown substrates from two suppliers; and (3) two high pressure grown substrates from the same supplier which were grown at two different time periods. In addition, a substrate is investigated which did not pass qualification tests by a device manufacturer. Finally, Chapter 6 gives conclusions and suggestions for future work. 3 CHAPTER 2 GROWTH AND PROPERTIES OF SEMI-INSULATING GALLIUM ARSENIDE 2.1 Introduction Semi-insulating GaAs is used for the production of high performance electronic devices such as high speed d i g i t a l integrated circuits, f i e l d effect transistors, charge coupled devices and monolithic microwave integrated c i r c u i t s . For large scale integrated circuit GaAs technology to develop reliably many problems related to the reproducible growth of high quality crystals remain to be solved. To achieve high electrical yields of GaAs ICs [1] i t is essential to develop GaAs subtrates with low density of dislocations and impurities, high r e s i s t i v i t y and good thermal s t a b i l i t y , high activation of the implanted species, and homogeneous doping profiles. 2.2 GaAs Crystal Growth Techniques There are two main GaAs crystal growth techniques: the Horizontal Bridgman (HB) and the Liquid-Encapsulated Czochralski (LEC) [2,3,4]. In the former, a quartz boat which contains gallium is sealed inside a quartz ampoule f i l l e d with an inert gas. Arsenic is placed at the neck of the ampoule, and a temperature gradient is established such that the arsenic starts to sublimate (614°C) and the temperature of gallium is held at 1235°C, the melting point of GaAs. After the arsenic evaporates and reacts with gallium to form a GaAs melt, either the ampoule or the heaters are slowly moved so that the GaAs is cooled at one end as the temperature gradient moves 4 along the boat; the growth then proceeds in the <111> direction. The resulting ingot takes the shape of the boat truncated by the liquid surface i.e., i t is D shaped. The wafers have to be cut at an angle to yield <100> material. A variety of impurities are introduced into the ingots in the quartz s i l i c a boat container. The predominant type of impurity is silic o n , usually in the 10 1 6 - 10 1 7 cm-3 range [5]. To make the HB GaAs semi-insulating, a deep acceptor impurity, usually chromium, has to be incorporated into the melt at approximately 10 1 7 cm-3 so as to balance the donor impurity level. Problems arise because of inhomogeneous FET performance in HB GaAs because of the nonuniformity in the chromium concentration resulting from the disagreement between the cutting plane and the growth plane [6]. As an alternative to quartz boats, Pyrolitic Boron Nitride (PBN) boats have been used in an attempt to achieve higher purity GaAs [5], somewhat better performance was reported, but nevertheless, the resulting electrical yields for Ion implantation remain generally low [1]. The LEC technique [7] is used for the growth of III-V compounds with one volatile constituent. In this method, the melt is prepared by a compounding process [3] where gallium and arsenic are placed below a boric oxide (B 20 3) encapsulant and the entire assembly is heated. The temperature is held at the melting point of GaAs, and the seed is lowered through the molten encapsulant into the GaAs melt. In addition, an overpressure of an inert gas, typically argon, is applied to prevent the arsenic from bubbling through the boric oxide. Both the seed and the crucible are rotated slowly in the opposite directions at predetermined rotational speeds so as to reduce radial and slice-to-slice nonuniformities [8]. A slow pull rate i s applied 5 to the seed and <100> GaAs round ingots 2-4 inches in diameter are grown. To reduce contamination of GaAs with si l i c o n , PBN rather than quartz crucibles are used [9]. The resulting s i l i c o n concentration is reduced from 10 1 6 to 10 1 5 cm - 3. Another reason for not using quartz is that the boric oxide reacts with s i l i c o n resulting in losing the clear v i s i b i l i t y through the encapsulant which is an essential requirement in GaAs melt growth. With a quartz crucible, the boric oxide turns grey, opaque, and becomes f u l l of bubbles [9], evidence of undesirable reaction of the melt with the surroundings. With a PBN crucible, the boric oxide remains clear and scum free. Growth of highly resistive GaAs depends directly on the boric oxide preparation before growth; the encapsulant has to be heat treated and vacuum baked to reduce the water content and prevent contamination of the melt with oxygen. Unlike HB GaAs ingots, LEC GaAs ingots are round, cylindrical and can be semi-insulating without intentional doping. Though i t is necessary to add chromium to the GaAs melt when grown with quartz crucibles, the same material grown with PBN crucibles is sufficiently high in r e s i s t i v i t y to make i t acceptable for device fabrication. The major advantages of undoped over chromium doped LEC GaAs are the following: (1) the lower concentration of the ionized impurities leads to higher electron mobilities in the ion implanted region; and (2) the absence of large r e s i s t i v i t y changes which are typically caused by the redistribution of chromium during high temperature annealing. Undoped LEC GaAs is gradually emerging as a high quality and reproducible material for fabrication of ion implanted active layers. 6 2.3 Impurities and Their Role in Undoped LEC GaAs The principal source of residual impurities in undoped LEC GaAs is the interaction of the melt with the crucible and the boric oxide encapsulant [10]. Investigation of the various impurities using spectroscopic techniques [1,11,12] revealed the existence of contaminants in undoped LEC GaAs grown with PBN crucibles, and substrate-to-substrate as well as ingot-to-ingot variations in concentration. Table 2.1 shows the order of magnitude of some of the impurities. Boron, which is believed to be inactive in GaAs [11], is introduced into the melt through reaction with the boric oxide. Oxygen is believed to be substitional in the arsenic sublattice giving rise to a deep donor level. Its origin is traced to the water levels ("wetness") of the boric oxide. It was only recently concluded [13] that oxygen is not associated with the main electron trap EL2 which is responsible for the semi-insulating property of GaAs. Chromium, an unintentional impurity, creates a deep acceptor level [4] when i t occupies substitutional sites in the gallium sublattice. Silicon i s a shallow donor and has consistently lower concentration when a PBN rather than a quartz crucible is used. Carbon is observed at high concentrations i n GaAs, and is believed to arise from the PBN crucible and from the close proximity of the melt to the hot graphite furnace parts [10]. This impurity forms a shallow acceptor and together with the deep donor antisite defect [14] tends to compensate the GaAs. Sulfur arises from the arsenic source element [1] and forms a shallow donor. Magnesium and manganese are shallow acceptors introduced from the s i l i c o n nitride coracle [1] and the bulk material [2] respectively. Iron and copper impurities are deep acceptors 7 Table 2.1. Order of magnitudes of some common impurities found in SI, undoped, LEC GaAs Impurity Log (concentration/cm3) Boron 15 Oxygen 16 Chromium 14 Silicon 15 Carbon 16 Sulfur 15 Magnesium 15 Manganese 15 Iron 15 Copper 15 Selenium 15 Tellurium 15 8 with potentially degrading effects on the ion implanted layer. The former has been demonstrated to cause interface traps between the active layer and the substrate [15] whereas the latter moves rapidly at low temperatures causing effective reduction of the diffusion length of n-type GaAs [4]. Copper contamination of GaAs takes place during crystal growth as a result of contact with the puller's brass material [5]. 2.4 Relation of the Melt Stoichiometry to Compensation and Thermal  Stability of GaAs GaAs melt composition is an important growth parameter which affects both r e s i s t i v i t y [10,16] and the concentration of the midgap level EL2 [16] which is now believed to be the antisite defect arsenic on gallium site [14]. Stoichiometry variations in GaAs substrates generate various native defects which recently have been found to influence the ion Implanted carrier concentration profiles and electrical activation [17]. Recent results on re s i s t i v i t y data [16] have shown that using dry boric oxide (500 ppm HgO), and above a c r i t i c a l arsenic concentration of 0.48 atom fraction of the melt, the GaAs material is semi-insulating and thermally stable up to about 0.53 (As atomic fraction). For compositions where the arsenic atom fraction i s above 0.53, the re s i s t i v i t y drops due to increase in the free electron concentration. On the other hand, below the c r i t i c a l arsenic concentration, GaAs turns p-type. This can be explained by reasoning that the EL2 concentration increases with increasing As/Ga and VQ^/V^S R A T * - O S [1^]> a n c* a balance is made with the residual carbon acceptors [18] so as to make the material semi-insulating. The material becomes p-type below the c r i t i c a l composition because the EL2 concentration becomes lower than that of the 9 shallow acceptors, and becomes n-type for compositions above 0.53 As atom fraction because the EL2 concentration is higher than the shallow acceptors concentration. Significantly different results are obtained when using wet boric oxide (2000 ppm H 20). Recent results [19] have shown that in this case above a c r i t i c a l arsenic concentration of 0.42 atom fraction of the melt, the GaAs material remains semi-insulating up to an arsenic atom fraction of 0.48. The impurities concentration in the melt for boron, oxygen, and carbon are different from typical levels obtained with dry boric oxide. Lower concentration for both boron and carbon were found, but the concentration of oxygen predictably was larger. The compensation in this case is expected to be different because of the lowering in the concentration of both EL2 (due to different melt composition) and carbon and the increase in the density of oxygen donors. The thermal st a b i l i t y of undoped SI GaAs is also strongly influenced by the stoichiometry of the melt. Conversion of the thin surface layer of GaAs to a conducting state, believed to be p-type, after thermal treatment was previously attributed to out-diffusion and pileup of residual acceptors, such as, manganese [20], and an increase in carbon levels due to solvents used during substrate preparation [12]. Recent results indicate that high thermal st a b i l i t y for undoped LEC GaAs can only be achieved with stoichiometric or arsenic rich compositions [10]. For gallium rich melts and dry boric oxide, the sheet resistance is observed to decrease rapidly following high temperature anneal. Surface conversion results when the EL2 concentration at the surface f a l l s below the residual acceptor concentration, 10 and the surface becomes p-type. This mechanism is probably enhanced by the outdiffusion of gallium and/or arsenic defects to the surface. 2.5 Recent Advances in the Growth of Undoped LEC GaAs Major efforts in the past few years have been concentrated on developing a controlled and reproducible growth technique of high quality undoped LEC GaAs crystals. One such effort aims at purifying the material using a special computer controlled d i s t i l l a t i o n process [21]. In this technique, the arsenic pressure inside the growth chamber is abruptly decreased to near one atmospheric pressure; this creates bubbling in the boric oxide encapsulant as gases which include water, compounds of carbon and water, compounds of sili c o n and water, and excess arsenic are released from the melt. This bubbling process is repeated until the electrical conductivity of the melt is appreciably decreased. GaAs crystals are grown at low pressure (6 atm), and low temperature gradient in the melt (50°C/cm) is achieved by using thermal reflectors. With both sil i c o n dioxide and PBN crucibles, highly homogeneous and highly resistive (lxlO 8 ohm-cm) ingots were obtained. The wafers are characterized with low dislocation density (8xl0 3 -lxlO 4 cm - 2) with a U-shaped distribution. An alternative to the high pressure growth synthesis which is in common use is a recent low pressure growth technique which is said by i t s advocates to be more efficient [22]. The advantages of low pressure growth techniques are that the cycle times are significantly shorter, the maximum crucible temperature is lower, the melt capacity is larger, and the melt stoichiometry can be better controlled. Though the quality of the material 11 has not been f u l l y proven, recent results of GaAs grown using quartz crucibles indicate similar thermal stability for arsenic rich melts (As/Ga = 1.02-1.04 atomic) and dry boric oxide (500 ppm water). The activation and mobility of sili c o n implanted material indicates similar results compared to the high pressure grown GaAs. The work for this thesis includes tests on a GaAs wafer grown at low pressure. More recently, attempts were made to reduce the dislocation density in semi-insulating GaAs crystals [23,24], The principle involved is to grow the crystal under a low temperature gradient and under a low pressure (5 atm), as this further lowers the temperature gradient by decreasing the convection heat transfer. The improvements made are found in: (1) reducing the arsenic escape by increasing the thickness of the boric oxide encapsulant; (2) reducing the temperature gradient at the boric oxide and the GaAs melt interface; (3) reducing the temperature gradient of the boric oxide i t s e l f by opening windows bored in the susceptor cylinder to directly heat this layer [24], and by setting a thermal baffle above the crucible [23]. As a result of those improvements, very low dislocation densities of approximately 1000/cm2 with uniform distribution, and homogeneous high r e s i s t i v i t i e s (108 ohm-cm) were obtained for two inch diameter wafers. Another technique which is successfully applied to obtain dislocation free crystals is based on adding large amounts of indium or indium arsenide (0.1 mol% - 0.4 mol%) to the GaAs melt [12]. Those additions are found to be effective in suppressing the generation of microdefects which are responsible for the formation of dislocations. This improvement, along with reducing the temperature gradient at the solid/liquid interface, is necessary to prevent 12 the generation and multiplication of dislocations from localized thermal stresses. The resulting quality of the ion implanted layers' uniformity indicate better homogeneity than conventional undoped LEC GaAs crystals. Finally, the application of a vertical magnetic f i e l d [25,26] has been attempted recently to enhance the uniformity and to reduce the dislocation density of high pressure LEC PBN grown GaAs. The effect of the magnetic f i e l d , which is supplied by a super-conducting c o i l , is to suppress the temperature fluctuations through the molten GaAs. More importantly, laminar thermal convection which degrades both the microscopic and macroscopic homogeneity of crystals has been reduced. Uniformity in the GaAs melt i s enhanced by optimizing the seed rotation as this adds forced convection to the melt. It is expected that those improvements can enhance the quality of the GaAs substrates for ion implantation. 13 CHAPTER 3 OPTICAL TRANSIENT CURRENT SPECTROSCOPY INVESTIGATION OF VARIOUS GaAs SUBSTRATES 3.1 Introduction to Optical Transient Current Spectroscopy Optical Transient Current Spectroscopy (OTCS), often referred to as Photo Induced Transient Spectroscopy (PITS) [27], is a member of the class of Deep Level Transient Spectroscopy (DLTS) techniques. Its advantage is that i t can be applied to semi-insulating GaAs (which is the starting material for integrated circuit (IC) fabrication). The aim is to obtain information on deep trapping levels which may be of fundamental interest and would certainly be of practical interest i f i t could help in diagnosing the suitability of the material for IC fabrication. The OTCS method was introduced by Hurtes, Boulou, Mitonneau, and Bois [28], by Fairman, Morin and Oliver [29], and by Martin and Bois [30]. This method is suitable for the investigation of deep trapping levels in high r e s i s t i v i t y epitaxial layers and semi-insulating GaAs substrates to which other deep trapping level spectroscopy methods [31] are not applicable. Several GaAs materials have been investigated using OTCS; for example, chromium doped Bridgman GaAs was investigated by Hurtes [28], Devaeaud [32], Fairman [1,29,33], and Martin [30], Chromium doped LEC GaAs was investigated by Fairman [1,29,33], whereas undoped LEC GaAs was examined by Oliver [34], K. Lowe [35], and W. Tang [36]. GaAs grown by Vapor Phase Epitaxy (VPE) on chromium doped substrates was investigated by Itoh [37], Fairman [1,29,33], 14 and Hurtes [28]. OTCS was further used to search for deep levels in other materials such as, indium phosphide (InP) [27], and lead iodide (Pbl 2) [38] which is an insulator. As a result of the application of OTCS to the study of GaAs substrate material, several significant deep levels were observed. For example, the deep level EL2 [39,40] has been observed by Martin [30], and Tang [36]. Chromium related deep levels which are responsible for the semi-insulating behaviour of chromium doped GaAs were detected (as HL1) by several investigators [1,28,29,32,33,37,41]. Other deep levels due to impurities or native defects [42] (and with distribution affected by dislocations [43]) were also detected, and are believed to cause problems of variable threshold voltage [44], hysteresis [45], frequency dependent transconductance [46], and noise [47] in GaAs ICs. 3.2 Theory of Optical Transient Current Spectroscopy The theory of OTCS was proposed by Hurtes et a l . [28] and then developed by Martin et a l . [30]. It is based on a depletion layer model where the current is determined by the charge transport across a depletion layer by electrons or holes released from traps. Thus an electron trap ( i . e . a centre which communicates only with the conduction band) may capture an electron during illumination and lose i t afterwards. The contribution which the electron makes to the terminal current as i t crosses the depletion layer is as i f this layer acted as an insulator separating the conducting (or semi-conducting region) from the electrodes. A hole trap behaves similarly. Once gone the carriers are not replaced because the concentration of 15 electrons and holes in the reverse biased junction depletion region are low. Assuming that the probability f that a trap is occupied by an electron, the following rate equations are defined [48]: rate of electron capture = r = n N_ (1-f) V a a T n n rate of electron emission = r, = N J e T* e n rate of hole capture = r = p N„, f V 0 F c v T p p rate of hole emission = r , = N_(l-f) e a T p where n(p) is the density of electrons (holes), V n(V^) is the thermal velocity of electrons (holes), a n(°p) Is the electron (hole) capture cross section, and is the total population of the trap. Imposing the steady state condition that r - r, = r - r, yields: a b c d J e + a V p f , ( i + n P / ) - ! ss v e + a V nJ p n n Given that the current during illumination has reached a steady value and that at time t=0 the illumination i s removed one finds: e + o V ( p + 6 ) o V W> - t 1 + e" + /v" (.' + „'))-' ' (' + j¥>- 1. ' « 'n^p ^ p n n 0 0 n n n 16 e + 6 V p e f (°° ) = f l + — —:— P T T P | l"" 1 K f 1 + — I - 1 , for no recapture in the dark, p n n p where n(p) is the equilibrium concentration in the dark of electrons (holes) and 6 « 6 i s the excess number of electrons and holes generated by the n p l igh t . The current i ( t ) is given by r^  and r^, K t ) = S-O. N T (e n f ( t ) + e (1-f(t))) where A is the area of the contact and W is the width of the layer. So Ai ( t ) = i ( t ) - i ( » ) = H_|_H. N T (e n ( f ( t ) - f ( » ) ) ) + e p ( ( l - f ( t ) ) - ( l - f ( » ) ) ) From — = - fe + ( l - f )e with solution dt n p f ( t ) = f ( « ) + (f(0) - f ( » ) ) exp - t / t where 1/t = e n + e p , we obtain: e + a V (p+5 ) e + a V P p n n 0 0 17 Hurtes et a l . treated the case of large 6 ^ = 6 ^ during illumination and no recapture in the dark to obtain: Ai(t) = a-A^N T(e n-e ) [(1 - ( l + ! i ) "1 ] ex P (-t/x ) n p p For electron traps where a /a » 1 and e » e , and for hole traps where v n p n p' r a la » 1 and e » e , then the current reduces to: p n p n Ai(t) = N T T " 1 e x p C-t/T) where T = l / e n for electron traps, and T = l / e p f° r hole trap. For the case of a boxcar's sampling whose output is AI(t) = A ( i ( t l ) - i ( t 2 ) ) where A_ is the boxcar's amplification, the current difference i s : a l ( t ) = Ag N T T " 1 ( e x p C - ^ / x ) - e x p ( - t 2 / x ) ) By differentiating the current difference with respect to i and setting the result to zero, the value of maximum x can be solved: m 18 ^ 1 = 0 = ( 1 - W e x p C - t ^ x ^ - ( l - t 2 / T n ) ex P(-t 2/. m) can be solved for once and t 2 are set; and when the boxcar's time constant i s set to this value, a maximum Ai(t) is registered at a characteristic temperature Tffl. Data on the activation energy AE and capture cross section a can be obtained by Inserting the sets of characteristic temperatures for each time constant into the equation defining the time constant of traps: T = (a y T ) - 1 exp(AE/kT) where AE is the difference from the conduction band to the trapping level energy for electron traps, and is the difference between the trapping level and the valence band for hole traps, y is a constant defined as 2.28*1020 cm - 2 S - 1 k - 2 for electron traps and 1.70*1021 cm"2 S"1 k - 2 for hole traps. While electron and hole traps give rise to positive peaks as the boxcar's output is swept through a temperature range of 150K to 400K, nevertheless, negative peaks are seen in various undoped LEC GaAs samples. They are obtained i f e > e and (a V /a V ) > (e /e ), or i f both 3 n p v p p n n / v n p " inequalities are reversed. The possible mechanism [49,50] is that a centre which gives a negative peak gives a steady state dark current due to i t s pumping out f i r s t an electron then a hole. When the illumination ceases, one of these events occurs more slowly, and i f the traps are le f t in the condition which requires the slow process as the next step, the current w i l l i n i t i a l l y be low i.e. a negative peak is produced. 19 3.3 Experimental Procedure Semi-insulating GaAs starting substrate materials investigated in this work were obtained from Cominco Ltd. and Bell Northern Research (BNR). A l l the substrates were LEC undoped wafers grown in the <100> direction. Three wafers labelled 344S10 (sheet r e s i s t i v i t y = 2.8*108 ohms/square, mobility = 6700 cm2/v sec, etch pits = 27000/cm2), 453S74 and 453S75 (sheet r e s i s t i v i t y = 3.1xl0 8 ohms/square, mobility = 6100 cm2/v sec, etch pits = 39000/cm2) were obtained from Cominco. The f i r s t number in the label represents the ingot number, and the letter S (for seed) indicates that the last number stands for the slice number in the ingot counted from the seed end. Wafer #453S74 was reported (by BNR) to have been etched about 10 um using the following chemical etch: Hj SO^  ^ O j ^ O (4:1:1 by volume). A single wafer from Sumitomo was obtained which was grown at high pressure the same way as those from Cominco. The wafer was labelled 400600-1, and re s i s t i v i t y > 107 ohm.cm. No data were obtained for mobility and etch pit density. A single wafer from Litton was obtained. This was grown at low pressure. The wafer was taken from boule 2052, slice 2-9, and had the following specifications: r e s i s t i v i t y = 1.37x10s ohm.cm, mobility = 2810 cnr^/v sec, and etch pit density = 30000/cm2. A l l wafers were 2 inches in diameter. Two types of test devices for OTCS were used. These were the planar and the sandwich type (figure 3.1). In the planar type the electrodes were evaporated side by side on one surface, and in the sandwich type they were evaporated on opposite surfaces. The electrodes were [3] either chromium or gold-germanium (Ge = 12%wt + Au=88%wt) unalloyed or alloyed at 450°C in flowing nitrogen. The chromium and unalloyed Au/Ge form a Schottky barrier. Fig. 3.1 Geometry of (a) planar and (b) sandwich structures used in OTCS 21 The alloyed Au/Ge produces an n+ layer just under the contact (due to Ge). Some samples were thinned by grinding them in a silicon carbide slurry on a glass plate followed by a chemical etch in a solution of HgSO^ +HgO2+H20 (4:1:1 by volume) for two minutes. The block diagram of the experimental setup is shown in figure 3.2. The samples were mounted on a liquid nitrogen cooled finger (KRYOSTIK model 1320H) in an evacuated light-tight chamber as shown in figure 3.3 with contact probes for electrical connections. A power transistor was used to heat the samples. A copper-constantan thermocouple for temperature measurement was mounted on the sample holder close to the device. Light pulses were provided by a GaAsP 670 nm LED. A fixed voltage bias (typically ±7 VDC) was applied to the sample, and the current was amplified with an EG&G 181 current sensitive amplifier followed by an EG&G dual gate boxcar. The output of the boxcar and of the thermocouple (through an amplifier) were recorded on an X-Y recorder. 3.4 Results The main practical question about the OTCS technique is whether i t can usefully be employed to test the suitability of a particular batch of material for device fabrication. In addition to obtaining information about deep trapping levels, the use of OTCS here is further extended to investigate several effects on the DLTS spectrum, such as, the effects of chemical etch, surface damage, different test structures, varying contact geometry, and choice of electrode material. ANATEK MODEL 25-20 Chamber-sample LED C Z H IEC F33 PULSE GENERATOR TEMPERATURE TRIGGER PAR 165,162 BOXCAR AVERAGER HP 70AAA X-Y RECORDER PAR 161 CURRENT AMPLIFIER Fig. 3.2 Block diagram of the OTCS setup Fig. 3.3 Vacuum chamber used in the OTCS experiment 24 3.4.1 OTCS Spectra of GaAs Substrates From Three Vendors Figure 3.4(a,b,c) shows the OTCS spectra of devices made on slices of Cominco's, Sumitomo's, and Litton's GaAs respectively. The test samples used here were the planar type with chromium electrodes (length = 30 um, width = 600 um). The spectrum of Cominco's GaAs was similar to test devices tested earlier [36] except in the high temperature range where the magnitude of the negative peak was larger, and peak 1 appears much smaller in magnitude. No information on how typical the GaAs substrates from Sumitomo and Litton is known. The OTCS spectra of Cominco and Sumitomo GaAs substrates show the same traps and with similar relative heights. Both substrates were high pressure LEC material. The OTCS spectrum of the Litton substrate, low pressure grown LEC, was considerably different in that although i t shows a similar set of peaks, the relative peak heights are different. Figures 3.5(a,b) show the DLTS spectra of samples of both Cominco and Sumitomo before and after chemical etch in a mixture of sulfuric acid, water, and hydrogen peroxide (4:1:1 by volume). Though peaks 1 to 4 are unaffected by the surface etch, peaks 5 to 8 were considerably reduced in amplitude. This indicates that the unaffected peaks were due to deep levels present in the bulk of the substrates, whereas the affected defects were enhanced by surface conditions such as damage, oxides, and chemical treatment. These results demonstrate that the OTCS technique is useful in the investigation of surface etching treatments much as are used in the fabrication of devices to remove damage or contaminated surfaces. Fig. 3.4 OTCS spectra of SI undoped LEC GaAs from three vendors (Rate Window = 8.5msec) 26 (a) Cominco sample 15. 10. (b). Sumitomo sample Fig. 3.5 OTCS spectra of SI undoped LEC GaAs substrates from two vendors subjected to chemical etch (Rate Window = 8.5msec) 27 3.4.2 Identification of the Peaks Table 3.1 shows activation energies and capture cross sections of a l l the OTCS peaks found in this work. Figure 3.6 shows the signature lines of the OTCS peaks. Table 3.2 shows the data on traps found by previous investigators. The peak labelled 1 was identified from i t s signature line i n figure 3.6 by comparison with the well known compilation of data given by Martin et a l . [51] as being due to the main electron trap EL2. This peak has been reported many times using various forms of DLTS on conducting material but curiously not too often for semi-insulating material. This is presumably because most authors have used Au+Ge electrodes and these, as opposed to chromium, give inconveniently high dark currents at the temperatures necessary to observe EL2. Peak 3 and the broad peak 4 have signature lines on either side of Martin et al.'s EL12. According to Martin, Lang et a l . [52] have also observed this level which is probably due to an impurity. Polarity change on the sandwich type specimen [36] gave a greater peak for negative voltage on the illuminated electrode indicating an electron trap. The broad peak 5 is often found with another peak 6 (for example figure 3.5a). Those two peaks are closest to EL3 and EL4 respectively in Martin et al.'s DLTS data. They used capacitance DLTS [48] on conducting as-grown MBE (molecular beam epitaxy) material to obtain the level EL4. Fairman et a l . [33] identified as EL4 a centre which gave one of the two negative OTCS peaks which they observed in Cr-doped semi-insulating Bridgman sli c e s . Peak 7 is found to closely resemble Martin et al.'s EL6, while peak 8 is found to be a hole trap from polarity measurement on thin samples [36]. 29 Table 3.1 Activation energies, capture cross sections, and possible identities of the deep levels found using OTCS (Pl-8) in semi-insulating, undoped, LEC GaAs. label activation energy capture cross section possible identity (ev) (cm2) PI 0.87 1.05 x i o - 1 2 EL2 P2 0.65 3.00 x 10 - 1 2 negative peak P3 0.79 3.69 x 10~ 1 2 EL12 ? P4 0.76 2.12 x 10 - 1 2 ELI2 ? P5 0.59 3.46 x i o - 1 2 EL3 ? P6 0.52 2.90 x i o - 1 3 EL4 P7 0.38 3.20 x i o - 1 4 EL6 P8 0.32 2.50 x 10 - 1 3 HL6 Table 3.2 Deep levels in SI GaAs reported in the literature (as detected by OTCS (PITS)). VPE = vapour phase expitaxial layer. Authors W0 a(cm2) Identi-fication Materials Martin et a l . 0.9 2.2xl0 - 1 , + HL1 Cr-doped Bridgman GaAs [30] 0.74 6.3xl0~ 1 5 EL2 0.57 5.4*10 - 1 3 EL3 0.35 5.5xl0 - 1 5 EL 5 0.34 2.7X10" 1 4 EL6 0.27 2.05* l O - 1 4 ELI 2 Fairman et a l . 0.9 2X10" 1 4 HLl A l l * [1,29,33] 0.83 2x l 0 - 1 3 HL10 Cr-doped LEC GaAs 0.65(N)** l x l O - 1 3 A l l * 0.60 l x l O " 1 2 EL3 Cr-doped LEC GaAs 0.51(n)** l x l O - 1 2 EL4 Cr-doped Bridgman GaAs 0.34 4X10 - 1 1* EL6 A l l * 0.34 6xl0~ 1 3 VPE layer on Cr-doped GaAs 0.30 7xl0- 1 4 HL12 Cr-doped LEC & Bridgman GaAs 31 0.26 2 x l 0 - 1 2 Cr-doped Bridgman GaAs 0.15 8X10 - 1 4 Cr-doped LEC GaAs 0.14 l x l O - 1 6 VPE layer on Cr-doped GaAs **negatlve peak *Cr-doped LEC & Bridgman GaAs and VPE layer on Cr-doped GaAs Deveaud et a l . 0.87 1 . 3 x l 0 - 1 7 HL1 Cr-doped Bridgman GaAs [32] 0.5 3 x l 0 " 1 9 Itoh et a l . 0.98 1.3xlO - 1 3 HL1 VPE(n-) [37] 0.89 1.8xl0 - 1" HL1 0.75 2.7xl0- 1 4 EL2 0.62 1.5xl0 _ 1 1 + HL3 0.60 8 . 6 x l 0 - 1 3 EL3 0.42 Not Given 0.41 1.4xl0" 1 5 HL4 -Rhee et a l . 0.90 2 . 1 x l 0 - 1 2 Cr-doped GaAs [27] 0.85 1.3xl0~ 1 3 HL1 0.73 1 . 3 x l 0 - 1 7 0.17 3.9xl0" 2 2 Oliver et a l . [34] 0.83 Not Given HL10 undoped LEC GaAs grown with dry B 20 3 32 0.65(N) undoped LEC GaAs grown with wet B 20 3 0.57 undoped LEC GaAs 0.34 0.28 0.15 Hurtes et a l . 0.90 Not Given HL1 high r e s i s t i v i t y VPE layer [28] on Cr-doped Bridgman 0.81 EL2 n-VPE layer with high Cr-doped Bridgman 0.56 HL8 high r e s i s t i v i t y VPE buffer layer on Cr-doped Bridgman 0.54 EL3 n-VPE layer with high re s i s t i v i t y buffer layer on Cr-doped Bridgman 0.41 HL4 n-VPE layer with high re s i s t i v i t y buffer layer on Cr-doped Bridgman 0.32 EL6 both type of samples 33 The peak labelled 2 is the negative peak and uncritical application of the equations for positive peaks gave activation energy 0.65 eV and capture cross section of 3 x l 0 - 1 5 cm2. Oliver et a l . [34] found using OTCS (their PITS) a strong negative peak with planar specimens made from undoped LEC GaAs grown with wet boric oxide, but not in slices grown with dry boric oxide. They found AE = 0.65 eV and suggested that this level was related to oxygen impurity and was partly responsible for the semi-insulating condition (since this was enhanced when wet boric oxide was used). Fairman et a l . [33] using vapor phase epitaxial layers and Cr-doped Horizontal Bridgman crystals obtained similar results with AE = 0.65 eV and a = 3><10""13 cm2. Ogawa et a l . [49] also using OTCS found a minor negative peak in samples of unstated geometry using undoped LEC. In the previous paper by Itoh et a l . [37] using OTCS on Cr-doped Horizontal Bridgman slices no such negative peak or even low valley is seen (their figure 4) using an ungated FET with one Au+Ge contact on n+ gate pad and the other on semi-insulating sustrate with or without a semi-insulating buffer layer. 3.4.3 Effects of Varying Sample Geometry on OTCS Spectra The effect of varying the contact spacing and width of the planar samples was investigated. Other authors have used varying spacings e.g. 500 um (Hurtes et a l . [53]), 5 um (Fairman et a l . [33]), 20 um (Itoh et a l . [37]) and a l i t t l e over 10 um (Rhee et a l . [41]). Results of OTCS spectra for two different widths W = 300 and 600 p,m and two different spacings L = 30 and 60 um are shown in figures 3.7(a,b,c). With L = 60 um (Figure 3.7c) the right hand peak is very pronounced where i t was a mere shoulder with L = 30 um. 34 T °K P3 F i g . 3.7 OTCS s p e c t r a of d i f f e r e n t planar sample geometri (Rate Window = 18.9msec) 35 (It lies between peak 1 (not appearing at higher temperature) and peak 4.) The negative peak was even less pronounced for L = 60 um than for L = 30 um, perhaps because the positive peak which was more pronounced is close enough to interfere by giving a reduction in the net increase in current with time after illumination. Peak 4 which is the prominent peak on the two L = 30 devices, Is now a mere shoulder on the 60 um device. The difference in the spectra for different geometries can be associated with the different sampling regions due to the different geometry. 3.4.4 Effect of Varying the Electrode Material In the f i r s t work by Hurtes et a l . [28], alloyed Au+Ge electrodes were used, whereas Martin et a l . [30] used chromium electrodes for his sandwich sample structures because they noted that gold-germanium electrodes gave more complicated results. In earlier work [35] in this laboratory, alloyed gold-germanium electrodes were used, and they were found to result in too large dark currents which made OTCS measurements above room temperature very d i f f i c u l t . In later work [36], chromium electrodes were used and resulted in reduced leakage currents. To investigate the difference in electrode material and preparation on the OTCS spectrum, four samples were prepared with two types of electrode material, Cr and Au+Ge. A l l devices were of planar type using a gateless MESFET structure with L = 30 um, and W = 600 um. Two samples with Cr and Au+Ge contacts were alloyed for ten minutes at 450°C. The OTCS spectra of the four devices which were made from Cominco's GaAs material are shown i n Figure 3.8(a,b,c,d). The range of the OTCS scans were limited to those P5 T'K T K (b) Au+Ge unalloyed electrodes (d) Au+Ge alloyed electrodes Fig. 3.8 OTCS spectra of samples prepared with different electrodes (Rate Window = 38.8msec) 37 obtained for Au+Ge scans. The unalloyed Cr and Au+Ge electrodes gave the same two broad peaks but with different amplitudes. On alloying the Cr sample, the peak heights were a l l reduced, and the broad peak (combination of peaks 5 and 6) on the unalloyed sample, has now become distinct with peak 5 dominating. The Au+Ge specimen on alloying gave also an OTCS spectrum with some of the peaks such as, peak 6, reduced much in amplitude. In addition, the two low temperature peaks 7 and 8 amplitudes were different in both types of alloyed samples: whereas peak 7 (electron trap) remained in the Cr alloyed sample, peak 8 (hole trap) remained in the AuGe alloyed samples. The results indicate that the deep levels are affected by the high temperature treatment upon alloying, and that the type of electrode seems to influence the results. One might also expect unalloyed Au+Ge and chromium to behave similarly, both acting as Schottky diodes. Au electrodes, used by some authors [41] would presumably be similar. On alloying the Au+Ge, the n+ layer due to Ge doping may be presumed to act as an efficient source of electrons. The heat treatment of the chromium electrodes was done for completeness and because chromium or related metal gates on MESFETs would quite normally receive the heat treatment applied to the Au+Ge source and drain electrodes. To help elucidate the effects of the nature of the contacts on the spectrum observed by OTCS, dark current vs. voltage curves were obtained using an HP 4145A semiconductor parameter analyzer. Data for Au+Ge and Cr electrodes before and after heat treatment at 450°C for 10 minutes are given i n figures 3.9(a,b,c,d) for various temperatures. The current voltage curves for Cr ( f i g . 3.9a and 3.9c) are consistent with back to back diodes with 38 F i g . 3 .9 C u r r e n t v s . v o l t a g e f o r p l a n a r specimens w i t h d i f f e r e n t e l e c t r o d e s 39 poorly saturating reverse current. On heat treatment the current decreased considerably. Those for Au+Ge (figure 3.9b and 3.9d) before heat treatment also appeared consistent with back to back poorly saturating diodes but s t i l l giving more current than Cr. After heat treatment the Au+Ge, the current voltage curves were f a i r l y linear up to 0.5 uA with 10 volts between electrodes separated by 60 um. Arrhenius plots of log a t 7 volts (as used in OTCS) vs. 1/T in figure 3.10 show the relative values of the currents and the activation energies. The slope of the data for Au+Ge changed slightly on alloying giving apparent activation energies of about 0.76 eV and 0.8 eV before and after. With chromium the slope changed from a value corresonding to 0.84 eV to one giving 0.72 eV. 3.4.5 Effect of GaAs Surface Damage on the OTCS Spectrum Previous work by Tang [36] has revealed that the relative peak heights changed for sandwich specimens than from planar ones. In particular, he found that the negative peak was much more accentuated for the sandwich than the planar sample. The question that arises then is whether the difference between sandwich and planar specimens were due to the geometry or whether the fabrication process affected the results (since Tang prepared his thin samples by abrading i t so that the surface was damaged). To investigate these factors, thin sandwich samples were prepared by mounting the wafer fragment on a sil i c o n slice with black wax and then abrading with a slurry of 400 grade carborundum. The specimens were then removed from the sil i c o n with hot trichloroethylene and etched bri e f l y in the sulfuric acid and hydrogen peroxide mixture used previously. Two such thin sandwich samples were 2.8 3.0 3.2 3.4 1000/T Fig. 3.10 Signature line plots for the data of figure 3.9 (Labels same as in figure 3.9) 41 prepared with the top electrode in each case either on the abraded side or the polished side. In additon, another two thick sandwich sructures ( i . e . starting wafer thickness = 450 um) were prepared where one of them was given a token grind, while the other merely degreased. The results of the OTCS spectra are shown in figure 3.11(a,b,c,d) for each of the above stated cases. In the case of the thin sandwich structures (figure 3.11a and 3.11b), for the sample where the abraded side was on top, the positive peaks were somewhat attenuated whereas the negative peak increased somewhat in amplitude compared to the sample with the polished side on top. This effect is attributed to grinding which was followed by surface etch. To demonstrate the effect of surface abrasion only (no etch), figure 3.lid shows the spectrum of the thick sandwich sample which was given a token grind. Compared to the thick sandwich structure which was merely degreased (figure 3.11c), the positive peaks were slightly attenuated whereas the negative peak has increased significantly in magnitude. To verify that the negative peak was affected by surface damage, and to investigate separately the effect of surface etch on the negative peak, a planar specimen was prepared this time. To start with, the spectrum of the sample, as i s , (i.e. with no etching or grinding) was recorded as shown in figure 3.12a. The same sample was then etched by about 1 um using a mixture of sulfuric acid, hydrogen peroxide, and water (4:1:1) by volume). The OTCS spectrum indicated no difference (shown in circles in figure 3.12a). The sample was then lightly abraded using a carborundum slurry. The negative peak, figure 3.12b, was significantly accentuated. The sample showed almost the same starting OTCS spectrum, figure 3.12c, after the sample was etched. From these findings i t can be concluded that the negative P2 (b) abraded side on top, thickness = 120um (d) abraded side on top, thickness = 500um Fig. 3.11 OTCS spectra of sandwich structures with a negative £ bias on the top illuminated electrode (Rate Window = 75.5msec) 5 43 Fig. 3.12 OTCS spectra of a planar structure (a) before and after chemical etch (b) after light abrasion (c) aft< chemical etch (Rate Window = 75.5msec) 44 peak is associated with the damage done to GaAs by the abrasion process. 3.5 Summary From the above study, i t was shown that the OTCS technique is a useful tool for the evaluation of GaAs material. The OTCS spectra were shown to be different for high and low pressure LEC grown GaAs. Some of the peaks were found to be dependent on the surface condition, as i t was shown that the concentration of some of the deep levels were attenuated after the top surface layer was removed. The nature of the OTCS spectrum was found to be influenced by the electrodes, sample geometry, and fabrication method. Finally, surface damage was shown to affect the negative peak. Before this chapter is concluded, i t is useful to point out that the theory of OTCS based on the depletion layer model of Hurtes [28] (described in section 3.2) may not be totally applicable for the study of transients. For example in the case of transients resulting from a sandwich structure, the depletion layer w i l l be confined to a small depth below the surface, while the bulk remains undepleted. Other models are now available [50] which provide for possible alternative description of the observed transients. 45 CHAPTER 4 INVESTIGATION OF PROCESS-INDUCED DEEP LEVELS IN ION IMPLANTED MESFETs 4.1 Introduction Despite the recent advances which have been made in the f i e l d of MESFETs IC technology, there are s t i l l many problems concerning the s t a b i l i t y of such devices due to the presence of deep level defects and impurities both those i n i t i a l l y present in the substrate material and those induced by the fabrication process. It has been widely reported [5,54-59] that traps in the MESFET channel and in particular those at the interface of the channel and the semi-insulating substrate can cause such effects as looping in the drain I-V characteristics, low transconductance at saturation, low drain-source breakdown, low power gain, and large noise figures. Those effects were found in particular for active layers made by epitaxial growth over chromium doped gallium arsenide substrates because chromium tended to react with the active layer and form hole traps which contribute to the formation of an interface space charge region which in turn affect the channel width [59]. To isolate the active layer from the substrate, high purity epitaxial buffer layers were used to keep the deep levels in the substrate from diffusing into the MESFET channel. However, i t was found [60] that for a l l buffer layer thicknesses (1-3 n m ) , chromium, copper, and iron s t i l l were able to diffuse and resulted in a large number of deep levels at the active layer and buffer (A/B) interface. Some of the problems with deep trapping levels in epitaxial layers and 46 at the A/B interface are no longer present in the case of ion implantation in undoped LEC GaAs substrates. Nevertheless, the problems of the newer technology s t i l l include those due to the presence of the many impurities [33,8] in undoped LEC GaAs substrates, and due to defects either present i n the starting material or induced by the process steps. Process-induced defects in MESFET channels arise from several factors: (1) irradiation damage due to silicon ion implantation (used as n-type dopants), and whether the implantation was done directly into the surface or through a thin dielectric film; (2) the high temperature annealing stage required to remove the implantation damage and allow si l i c o n to reach vacant gallium sites; (3) the type of encapsulant used; and (4) the chemical treatment of the surface. Of those factors, the f i r s t factor is important, since implants through si l i c o n dioxide or si l i c o n nitride can introduce unwanted atoms such as oxygen and nitrogen into the active layer by knock-on mechanisms [61] Inducing serious defects. Also, the type of encapsulant which is used to preserve the GaAs stoichiometry during high temperature anneal is important. Studies have shown [62] that the implanted atoms redistribute by diffusion more with a si l i c o n dioxide than a si l i c o n nitride cap. Also, the s i l i c o n dioxide encapsulant does not preserve the substrates stoichiometry as well as si l i c o n nitride since i t is known that gallium can diffuse through the s i l i c o n dioxide. Problems of enhanced diffusion of defects are also caused by the encapsulants as a result of stresses due to thermal expansion mismatch between the dielectric cap and GaAs. There is an extensive literature on electron and hole deep levels in GaAs [63] and on their effects on device characteristics. Recent papers 47 specifically on deep levels in ion implanted undoped semi-insulating GaAs include Sriram et a l . [64,65], Rhee et a l . [41,66] and Hickmott [45]. In this chapter, deep levels in silicon implanted MESFETS fabricated by four procedures are investigated by channel current DLTS. The four cases include effects of implants directly into GaAs and through silicon nitrde film, and also effects of three types of encapsulants. 4.2 Principle of Channel Current DLTS Channel current DLTS is a technique which allows the investigation of the deep level traps in ion implanted MESFET channels. The principle is illustrated in figure 4.1. A small bias (50 mV DC) is applied between the drain and source so that the FET operates in the linear region. A reverse bias voltage is placed on the gate such that the channel is nearly pinched off. Pulses of voltage taking the gate to near zero bias are applied. The basic idea is that majority carrier traps are f i l l e d by carriers which are allowed to enter the previously depleted channel during the positive going voltage pulse. When the gate voltage returns to i t s more negative value the negative charge due to the trapped electrons partially compensates the positive space charge density in the depleted region. To maintain the fixed voltage drop across the region i t must therefore become i n i t i a l l y wider than before. The channel is therefore narrowed and the drain current is less. As the occupancy returns to normal the drain current increases (with the time constant depopulation emission process) as illustrated in figure 4.2. Hole traps give the reverse sign of effect (the hole trap occupancy can be changed because the quasi Fermi level for holes communicates with the gate Fermi DLTS detection circuitry Current Amplifier Voltage pulse supply DS H ' l i i D |^zero bias depletion widthj|w Q ion implanted active channel \ Interface ^•depletion layers Semi-insulating GaAs Fig. 4.1 Schematic diagram showing the channel current DLTS measurement system 00 V (t) V1 i (t) DS 4 11 (t) I3(t) I2(t) gate voltage t ime V. (a) electron trap > t ime (b) hole trap present time Fig. 4.2 Transient responses of the drain current to an applied gate voltage 50 level). The depletion width which is modulated by the traps is obtained for any time t after the lapse of the zero bias pulse [64] as: AW(t) = - W(t) N A W ( t ) = "2 W N I ( W 2 - " W 2 0 ) ^ P ^ n 0 ( 4 , 1 A ) oo n ' oo for an electron trap. The corresponding expression for a hole trap: + N A W ( t ) = 2 W N I CW2~ ~ ^ c ) ^ " V ^ <4'1B> on D i m * where N is the total concentration of the trap, N Q 1^  is the donor level T density at steady state depletion width, Wq and are the depletion widths at zero gate and steady state depletion widths respectively. The channel current for an arbitrary doping profile i s : k I D S = / (q u(x) n(x)) (Z/L)V D S dx (4.2) where u(x) is the d r i f t mobility in the channel, n(x) is the free carrier concentration, Z is the channel width, L is the effective channel length, and k is the channel thickness. For a small change in depletion width, (4.2) 51 b e c o m e s : A I D S = (q u ( x ) n ( x ) ) ( z / L ) V D g AW ( 4 . 3 ) T h i s e x p r e s s i o n c a n be c o m b i n e d w i t h ( 4 . 1 A ) t o o b t a i n t h e t r a n s i e n t c u r r e n t e q u a t i o n f o r a n e l e c t r o n t r a p : - (q u(x)) l w «, , , , ' , , A I D S = 2W ( Z / L > V D S N T ( W - " W o ) ^ " V ^ ( 4 ' 4 A ) The c o r r e s p o n d i n g e x p r e s s i o n f o r a h o l e t r a p : (q u ( x ) ) | W c o A IDS = —-2W <Z/L>VDS N T ^ ~ W 0 ) ^ " V ^ <4'4B> The c u r r e n t i s s a m p l e d a t two t i m e i n s t a n t s , t^ a n d t 2 b y t h e b o x c a r a v e r a g e r w h i c h g i v e s a n o u t p u t : v 0 ( t ) - A B R ( i ^ C t i ) - I D S ( t 2 ) ) ( 4 . 5 ) w h e r e A g i s t h e a m p l i f i c a t i o n o f t h e b o x c a r , and R i s t h e c u r r e n t t o v o l t a g e c o n v e r s i o n f a c t o r i n t h e c u r r e n t a m p l i f i e r . U t i l i z i n g t h e e x p r e s s i o n s i n e q u a t i o n ( 4 . 4 A ) , t h e o u t p u t c u r r e n t b e c o m e s : 52 (q u(x)) | W < x 2W 00 (exp(-t 1/-c)-exp(-t 2/T) (A.6) v 0 ( t ) - " ABR gj - (Z/L)V D S N T (UJ - W q2). The information about the traps i s obtained by the DLTS circuitry as i n section 3.2. The trap activation energy and capture cross section are obtained by plotting (T 2 m T) vs. (1000/T m), where Tffl is the characteristic temperature of the peak in the DLTS spectrum. The boxcar rate window in the case of channel current DLTS is obtained by differentiating (4.6) with respect to x, setting the result to zero, and solving for x^: Tm = 1 / e n = ( t l " *2> 1 M t - i / t ^ ) (4.7) Unlike OTCS, positive peaks In channel DLTS correspond to hole traps, while negative peaks indicate electron traps. This technique is therefore unambiguous with respect to the type of the deep level. Also, In contrast to OTCS where the concentration of the traps are d i f f i c u l t to obtain because not a l l the levels are occupied during optical excitation, the concentration of traps in channel current DLTS can be estimated since during electrical excitation a l l the deep levels in the sampled region undergo periodical f i l l i n g and emptying. The concentration can be estimated by solving for N^ , in equation ( 4 . 6 ) . 4.3 Experimental Procedure Four sets of long channel devices ("Fat FETs") were used for channel 53 current DLTS, each fabricated using a different procedure. Substrates from the following ingots of Cominco were used: #43, #51, #123, #175 and #344. The f i r s t set of fat FETs were fabricated by Lowe [35] with a gate length of 100 um and a gate width of 200 um. The channel was implated with 3*1012 cm-3  2 8 Si at 100 keV directly into the GaAs surface. A 600 nm RF sputtered silicon dioxide mask was used to block the sil i c o n implant where isolation was needed. The implant damage was furnace annealed at 850°C for 20 minutes using a 170 nm RF sputtered silicon dioxide as an encapsulant. The second set of fat FET's (L = 120 um, W = 180 um) were implanted with 3.38*1012 cm - 2 using 2 8 S i at 125 keV through a 40 nm layer of PECVD si l i c o n nitride film. A Photoresist mask was used for selective ion implantation. The dielectric film was laid down in a Plasmatherm Inc. Multiversion machine with NHg and Sit^ in He. The film was thickened to 80 nm before furnace anneal at 850°C for 25 minutes. The third set of MESFETs had identical geometry to that of set 2. The channel was implanted with 2 8 Si directly into the GaAs surface at 100 keV with a dose of 2.25x10*2 cm - 2. The devices were annealed identically to set 2, using an 80 nm PECVD sili c o n nitride films. The fourth and f i n a l set of devices were supplied by Allied Bendix Aerospace Corporation. The fat FETs (L = 200 um, W = 200 um) were implanted with 3xl0 1 2 cm-2 of 2 9 Si at 60 keV directly into the GaAs surface. The wafer was furnace annealed at 850°C for 15 minutes under 250 nm PECVD silicon dioxide. The GaAs was reported to have been obtained from Cominco Ltd. The source and drain of the a l l the devices were Au+Ge alloyed at 450°C, while the gates were aluminum. The experimental setup for channel 54 current DLTS shown in figure 4.3 is similar to the OTCS setup described previously. 4.4 Results Channel current DLTS spectra are given in figures 4.4-4.7 for MESFETs made using the four processes described above. Arrhenius plots are given i n figures 4.8 and 4.9 for the channel current DLTS peaks. Table 4.1 summarizes the DLTS data. The two sets of devi ces made with RF sputtered and PECVD silicon dioxide cap (processes I and IV respectively) each gave four peaks corresponding to four defects. The resulting traps were different. In process IV, two of the peaks were hole traps (T2 and T4), while the other two were electron traps (Tl and T3). Since none of them were found in the starting material by OTCS (table 3.1) the four traps were thus likely to be process induced. The two hole traps may have originated from metal impurity diffusion from the substrate into the active layer during high temperature anneal. In process I, with an RF sputtered sil i c o n dioxide cap, the peaks were a l l electron traps. Two of these peaks, Ql and Q2 are the same as the two peaks P4 and P5 found in the starting material by OTCS (table 3.1), and they are probably to be identified on the basis of activation energy with EL12 and EL3 respectively found by Martin et a l . [48]. The other two peaks Q3 and Q4 were not observed in the starting material and are, therefore, process-induced defects. For devices implanted directly into GaAs and annealed under PECVD VOLTAGE SUPPLY chamber-T sample I I thermocouple — I out PULSE Isyry GENERATOR X-Y PLOTTER AMPLI FI ER trig BOXCAR out in Fig. 4.3 Block diagram of channel current DLTS system 4.4 Channel current DLTS spectrum for MESFETs prepared using process -50 ; 4.7 Channel c u r r e n t DLTS spectrum f o r MESFETs prepared u s i n g p r o c e s s IV Fig. 4.8 Signature line plots for DLTS data of processes I-III Os o -.THIS WORK - MARTIN et a l / HL1 EL2 / ' / ' / / / / / / / ' / EL12 / / / HL3 EL3 EL 4 / / / / / / / / / / / T4 T3 T2 T1 EL6 / / HL6 / / 2 1000/T F i g . 4 .9 Signature l i n e p l o t s f o r DLTS data of process IV 62 Table 4.1 Activation energies, capture cross sections, and possible identities of the deep levels found by channel current DLTS in MESFETs fabricated by four processes (Ql-4,Rl,S1,T1-T4). label activation energy capture cross section possible identity (ev) (cm2) Ql 0.74 2.67 x 10 - 1 3 P4 and EL12 Q2 0.57 4.47 x 10" 1 2 P5 and EL3 Q3 0.28 1.66 x i o - 1 6 -Q4 0.24 1.45 x 10 - 1 6 -RI 0.85 4.30 x i o - 1 3 PI and EL2 SI 0.74 2.10 x i o - 1 3 Tl 0.69 2.3 x l O " 1 2 electron trap T2 0.57 3.44 x 10 - 1 7 hole trap T3 0.78 1.015x IO" 1 3 electron trap T4 0.911 1.55 x l O - 1 3 hole trap 63 silicon nitride cap (process III) only one peak, SI (AE = 0.74 eV), was found. This peak was observed in the starting material by OTCS as P4 and is believed to be EL12. For devices implanted through PECVD sili c o n nitride (process II) only RI (AE = 0.85 eV) was observed. This peak was found by OTCS as PI and is Martin et al.'s [48] EL2. Relating these results to previous work (table 4.2), Sriram et a l . [64,65] used devices with si l i c o n implanted directly into semi-insulating undoped LEC GaAs at doses of 2 to 5.5*1012 cm - 2 at 100 to 325 keV and annealed at 860°C under "phosphorus s i l i c a t e " glass. Using channel current DLTS, they found six levels of which three were process-induced. Their defect A is probably our level Q4. Rhee and Bhattacharya [41] implanted sili c o n directly into Cr-doped semi-insulating LEC GaAs at does of 10 1 2 and 10 1 3 cm - 2 at 100 keV and annealed under silox cap. They found three electron traps of which one was present in their starting material. In a further paper [66] they found two dominant levels (0.52 eV electron trap and an 0.15 eV hole trap) in directly implanted material, these centres being absent on implantation through Silox. Jervis et a l . [67] compared the traps produced by implantation (a) direct and (b) through si l i c o n nitride into epitaxial and chromium doped semi-insulating wafers (probably Bridgman). They annealed under sil i c o n nitride. Using capacitance DLTS with both electrical and optical excitation, they found an increase in EL2 on implanting through sili c o n nitride. As regards a mechanism to account for the extra EL2 found in devices made by process II, i t is suggested that when implantation is done through s i l i c o n nitride, knocked-on nitrogen atoms [68] compete with displaced 64 Table 4.2 Some deep levels in sili c o n implanted GaAs reported in the literature. label activation energy capture cross section possible identity (ev) (cm2) (reference) A 0.23 1.90 x 10 - 1 7 unknown [64] B 0.22 1.17 x 10~ 1 5 EL14 C 0.53 1.60 x l O " 1 2 EL4 D 0.85 1.00 x l O - 9 New E 0.64 5.90 x l O " 1 4 Cr complex F 0.75 1.50 x lQ~lk EL2 A 0.52 ± 0.01 (1.20-1.60) x 10~18 [41] B 0.17 ± 0.01 (5.20-5.50) x l o ~ 2 3 C 0.21 3.10 x 10 - 2 1 EB2 0.83 2.20 x 10 - 1 3 EL2 [67] EB3 0.90 3.00 x 10 - 1 1 EB4 0.71 8.30 x 10 - 1 3 EB7 0.30 1.70 x l O " 1 4 EB6 0.41 2.60 x 10 - 1 3 65 arsenic atoms for vacant arsenic sites (since both nitrogen and arsenic belong to group 5 elements). The pre-empted arsenic atoms could adopt vacant arsenic sites to produce As which i s , or is associated with, E L 2 . With silicon dioxide as encapsulant, the loss of gallium is to be expected to have some effect on the type of defects produced. Perhaps occupation of the vacant gallium sites by impurities from the silicon dioxide film or from metal traces in the substrate is responsible for the process-induced hole and electron traps. One of the traps, P4 or E L 1 2 , is probably associated to gallium vacancy concentration since i t was present in processes I and III (under silicon dioxide and silicon nitrde caps) but not in process II (implanted through sil i c o n nitride) where gallium vacancy was reduced due to the formation of the anti-site defect. To summarize the main results: 1 . The number and nature of deep levels are influenced by the type of the annealing cap. Annealing with a si l i c o n nitride cap is observed to remove a l l but one defect in the starting substrate and does not cause process-induced levels. Annealing under a sil i c o n dioxide cap leads to the formation of several process-induced traps which give detrimental effects on the devices characteristics. 2 . For a different encapsulant, for example, RF sputtered and PECVD silic o n dioxide, the resulting number and nature of deep levels are different. 3 . For implantation through sil i c o n nitride, the channel was found to contain a larger concentration of E L 2 . This trap Is undesirable in MESFETs since i t can cause d r i f t in the DC characteristics. 66 CHAPTER 5 INFLUENCE OF VARIOUS LEC UNDOPED GaAs SUBSTRATES ON THE CHARACTERISTICS OF ION IMPLANTED AND ANNEALED ACTIVE LAYERS 5.1 Introduction With the emergence of advanced GaAs integrated circuit technologies, stringent demands are placed on the GaAs material in order to make high quality devices reproducibly. The advantages of ion implantation into bulk material over the use of epitaxial technology l i e in the ab i l i t y to form planar device structures easily by selective doping [69], precise tailoring of the implant profile [70], and cost effectiveness. However, the influence of the bulk grown substrate material on the properties and characteristics of the ion implanted and annealed active layers remains a major concern. It is known that GaAs substrates can influence the active layer performance in several ways, such as: (1) variations in activation efficiency, mobility, and doping profiles which in turn produce variations in pinchoff voltage and drain current [71-75]; (2) degraded d r i f t mobility at the active layer-substrate interface due to traps caused by impurities [15] has adverse effects on transconductance and noise figure; (3) backgating (and sidegating) effect [72,76] can severely limit circuit performance; (4) problems with surface conversion and thermal instability of GaAs are due to improper compensation [77]. These substrate-related problems have prompted the use of qualification tests or pre-screening of substrates for ion implantation. 67 Suppliers of substrate materials check their material through measurement of substrate r e s i s t i v i t y , Hall mobility, and thermal s t a b i l i t y , and quality control checks involving device fabrication for GaAs substrates are largely performed by the device manufacturers [78]. Typical qualification tests of GaAs substrates require [33] (1) reproducibly high resistance substrates which can withstand high temperature (850°C) anneal without surface conversion; (2) low background doping compared to shallow donor and acceptor impurities; (3) high electrical activation and carrier mobility with abrupt doping profiles for bare surface n-type implants; and (4) low dislocation and defect densities. One test [70] which has been used to qualify substrates involves ion implantation with an inert gas such as argon to simulate damage caused by n-type implants, followed by high temperature capped anneal; the substrate qualifies i f i t remains semi-insulating. Other tests involve measurement of the electron concentration profile after ion implantation and annealing of silicon and checking that the doping profile is similar to that of a control sample. These tests aim at reproducibly obtaining high quality active layers with the following properties [79,15]: 1. reproducible and well controlled carrier profiles, 2. high undepleted carrier concentration, 3. high d r i f t mobility (> 4500 cm2/v sec) which stays constant or rises through the channel-substrate interface, 4. controlled drain currents and pinchoff voltages with minimal nonuniformities, and 5. stable and high resistance substrates after high temperature 68 processing. Undoped LEC bulk grown GaAs substrates are preferred for fabrication over Bridgman or Cr-doped material because the latter tends to exhibit poor performance in active layer properties such as lower activation and mobility, drain current and threshold voltage nonuniformity, and thermal conversion associated with chromium in the substrates [72,74,77,79]. With LEC undoped GaAs substrates, improvement of reproducibility of active layer properties compared to chromium doped LEC GaAs has been reported [71] as uniformity from ingot to ingot has been markedly improved and the problem of surface conversion has been eliminated. However, i t is expected that undoped LEC GaAs material from different sources should exhibit differences in quality and performance. Also some suppliers may change their growth procedures to obtain semi-insulating wafers and to pass qualifying tests. It is the objective of this chapter to investigate undoped LEC GaAs substrates: (1) from different suppliers; (2) for differences between low pressure and high pressure grown material; and (3) from recent and earlier eras from one supplier. In addition, a substrate Is also analyzed which did not pass the qualification tests of a device manufactuer, but did pass the screening test of the supplier. The following parameters are sought to charcterize GaAs substrates for this investigation: 1. sheet resistance, Hall mobility, activation, 2. doping profile, undepleted carrier concentration, and zero gate bias depletion width, 3. d r i f t mobility, 4. deep levels in MESFETs channel, and 69 5. backgating effect. 5.2 Description of the Diagnostic Test Pattern The test pattern which is shown in figure 5.1 was developed by N.G. Tarr [80] based on that reported by Immorlica [81]. Occupying the centre of the pattern is a Van der Pauw cross used for measuring the n-implant sheet resistance, Hall mobility, and undepleted carrier concentration. A similar cross is provided in the top l e f t hand side to allow similar measurements for the heavily doped n +-implant used for ohmic contacts. A Schottky diode on the lower right hand corner Is used to measure implant profiles. There are also four MESFETs with different dimensions, labelled T1-T4. MESFET T3 is a fat FET with a gate length far greater than source-gate and drain-gate spacings; i t is used to profile the d r i f t mobility in the ion implanted channel. MESFET T4 is used for investigating deep levels by channel current DLTS. Finally, MESFETs Tl and T2 are used primarily to determine the drain current and threshold voltage variations. 5.3 Diagnostic Pattern Fabrication Fabrication was carried out on five substrate slices of undoped LEC GaAs. Two of the slices B, and C from Sumitomo (high pressure LEC GaAs) and Litton (low pressure LEC GaAs) respectively were obtained from 2" wafers. The remaining three slices were obtained from 3" wafers supplied by Cominco (high pressure grown): Substrate A-686 is a recent wafer grown in 1985, substrate B-727 is also a recent wafer which failed the screening tests of a device manufacturer, and f i n a l l y substrate A-184 is from an earlier era grown T1 (I0x500um) T2 (I0x200um) T3 ( 100x200um) Schottky diode ( I00x4l0um) o F i g . 5.1 The d i a g n o s t i c t e s t p a t t e r n 71 in 1982. A l l slices were fabricated identically so that different substrate effects can be observed. Ten to twelve test patterns (each 5 mm x 5 mm) are fabricated on each slice (20 mm x 15 mm) to average the various measurements. The f i r s t step in fabrication was to degrease for five minutes in boiling trichloroethylene, acetone, and isopropanol. This was followed with four minutes cleaning in a 1% Alconox solution (monosodium dihydrogen phosphate). Afterwards the slices were rinsed for 15 seconds in de-ionized (DI) water. The surface was then etched one micron by dipping in a mixture of ammonium hydroxide, hydrogen perioxide, DI water (5:2:240 by volume) for five minutes. After rinsing the slices for 15 seconds in DI water, the slices were bathed for two minutes in boiling isopropanol. At this stage (figure 5.2a), the slices were a l l ready for processing. In the next fabrication stage, registration marks were opened in the slices, Photoresist (Shipley AZ1450J) was spun to a uniform thickness of 1.5 microns, baked for 30 minutes at 65°C, and exposed to UV light through the appropriate mask for 1.5 minutes. The registration marks were then etched 1000A with the ammonium hydroxide solution used above for 30 seconds (figure 5.2b). With the photoresist removed by boiling acetone, the slices were similarly patterned using an n-implant mask. Windows were opened through the photoresist to allow ion implantation directly into the GaAs surface (figure 5.2c). The samples were then a l l ion implanted with 2 8 S i using a dose of 2.2xl0 1 2/cm 2 at 100 keV. Afterwards, the photoresist was removed by dipping the slices in acetone; the stubborn remainder was removed by oxygen plasma in the Plasmtherm system. Preparing the samples for high temperature anneal 72 SI GaAs (A) Wafer pre-clean '/// SI GaAs (B) Registration mark etch SI GaAs (C) Opening windows for ion-implantation Fig. 5.2 Fabrication sequence for the diagnostic test pattern N-CHANNEL SI GaAs (D) Encapsulation and annealing / APR / PR / j K-CHANNEL j SI GaAs (E) Opening windows for gold-germanium contacts (F) Evaporation of gold germanium Ar/ j N-CHANNEL j SI GaAs (G) L i f t o f f of photo-resist, and alloying ' / / / / / '///// j N-CHANNEL | SI GaAs (H) evaporation of aluminium. Fig. 5.2 cont'd 75 consisted of degreasing the slices, laying down a 900A to lOOOA film of PECVD silic o n nitride on both surfaces of the wafer (figure 5.2d) and annealing in a Mini Brute s i l i c a tube furnace at 825°C for 25 minutes. After the anneal, the top silicon nitride film was removed by freon plasma in the Plasmatherm system. The n +-implant was here foregone to simplify the processing steps. In the next step (figure 5.2e), the slices were degreased and patterned with the ohmic contacts mask. Au+Ge (88%Au+12%Ge) was evaporated to a thickness of 2000A (figure 5.2f). This was followed with boiling in acetone to get metal l i f t o f f (figure 5.2g) and alloying for two minutes at 435°C in the Mini Brute furnace. In the f i n a l step (figure 5.2h), the slices were patterned with the Schottky gate metal mask, and 2000A of aluminum was evaporated into the slices and then followed by l i f t o f f to form Schottky gate contacts. 5.4 Measurements on the Diagnostic Test Pattern A l l the measurements carried out here were non-destructive and meant to give information on the properties of the ion implanted and annealed active layers. A useful tool that fa c i l i t a t e d a number of measurements is the HP 4145A Semiconductor Parameter Analyzer. Measurements of MESFETs characteristics were programmed into the internal computer. In this manner, measurement of I, , or drain current at zero gate voltage was obtained from ass I vs. V . Measurement of the threshold voltage was accomplished by DS GS measuring the gate voltage at which the drain current was roughly 5 ua. Measurement of the transconductance was obtained by plotting the drain current versus gate voltage and determining the slope at each point. 76 Measurement of the sheet resistance was made using the central Van der Pauw cross of figure 5.1 with the technique in [82]. A current (1 ma) was passed between two adjacent terminals such as A and B using an HP 6186A DC current source, while the voltage between the other adjacent terminals C and D was measured by a sensitive (Fluke 8050) voltmeter. The active layer sheet resistance, Rg, was obtained by solving: R s = (*/ln2) ( V ^ ) The Hall mobility of the active layer was measured by using the same Van der Pauw cross structure. The sample was placed in a miniature probe holder and placed in a magnet (Alpha Scientific Laboratories) such that a magnetic f i e l d , B, (0-.2 Tesla) was applied normally to the sample. A constant current (100 ua) was applied between two opposite terminals, such as A and C, while the voltage was monitored at the remaining opposite terminals B and D. The average Hall mobility was obtained by solving: UH = < VBD / RS B IAC ) The undepleted carrier concentration was then calculated from the sheet resistance and Hall mobility: N uc " (1/C* UHV The doping profile was obtained by using the Schottky diode in figure 77 5.1 and performing gate capacitance versus reverse bias voltage measurement and calculating the electron concentration n(x) versus depth x (e.g. [83]): n(x) = (C 3/qeA 2) (dV/dC) where e is the permittivity of GaAs, A is the area of the diode, and C is the gate capacitance. This capacitance was measured by a HP 4275A Multi-Frequency LCR Meter which is interfaced to a HP 9812 computer, and the doping was profiled by two software routines, HFCVN and NWALLN, supplied by HP. The d r i f t mobility profile was measured using the fat FET (T3) following the method of Pucel and Krumm [84]. With the FET biased in the linear mode such that i t is well below saturation (V = 50 mV), the Do transconductance, dlpg/dV^g, was recorded by the HP 4145A Semiconductor Parameter Analyzer, the gate capacitance vesus reverse bias voltage was recorded by the HP 4275 LCR Meter, and with the doping profile obtained above, the dr i f t mobility u(x) was given by: u(x) = (L/C V D S) (dI D S/dV G S) where L is the gate length. For the particular FET geometry used, the channel resistance was much greater than the contact resistances associated with the drain and source, and those factors were thus ignored in the mobility measurement. The backgating measurements were accomplished using the HP 4145A 78 Semiconductor Parametric Analyzer. MESFET Tl was used as the active device, and the adjacent pad A of the Van der Pauw cross (500 um separation) was used as the sidegate electrode. The Parameter Analyzer was programmed to plot the drain current with both the gate and source grounded versus the backgating voltage as i t was swept from +20 V to -30 V. The data were stored and replotted on the HP 9816 computer so that the drain current was normalized to I, with the backgating electrode disconnected, dss The last measurement was the deep levels in the MESFET channels. That was performed using the channel current DLTS technique described in the last Chapter. 5.5 Results of Active Layer Evaluation Typical ^"Vpg characteristics of the four MESFETs in each test pattern are shown in figure 5.3. ^gg *-s n o t t n e same In the four transistors because of the different gate lengths and widths in each device. The linear region of the characteristics does not have a steep slope which i s a consequence of not using an n +-implant to reduce the source and drain contact resistances. The drain current at saturation is almost constant with increasing drain voltage which is desirable in MESFETs. Because of the light doping of the channel, no breakdown in the drain current occurs for drain voltages below 10 volts. Table 5.1 presents results on the average drain current and threshold voltage and their scatter for MESFET Tl (L = 10 um, W = 500 pm). The averaging was done over 10 to 12 devices which are spaced horizontally and vertically by 5 mm, and so the scatter reflects macroscopic (as opposed to microscopic) inhomogeneity in the slices. The table also 1 0 (mA) 79 F i g . 5.3 T y p i c a l I - V c h a r a c t e r i s t i c s of MESFETs in the d i a g n o s t i c t e s t p a t t e r n 80 Table 5.1 Comparison of the active ion implanted layers parameters of five GaAs samples. Parameter A-686 A-727 A-184 I. (Tl) dss v ' Scatter (I,, ) dss Vth (Tl) Scatter (Vth) Rs Scatter (Rs) UH N uc W 0 W l N max Activation 9.25 ma 1.25 ma -2.00 V 170 mV 1584 125 4542 8.7E11 1186 A 2478 A 1.32E17 66.2 % 7.82 ma 0.61 ma -1.71 V 66 mV 1672 76 4693 8.0E11 1107 A 2389 A 1.22E17 61.5 % 11.21 ma 1.46 ma -2.21 V 130 mV 1370 82 4530 1.0E12 1215 A 2700 A 1.26E16 63.0 % 9.58 ma 1.00 ma -1.74 V 94 mV 1282 85 4751 1.0E12 949 A 2501 A 1.36E17 68.4 % 7.73 ma 0.94 ma -1.50 V 90 mV 1553 132 4683 8.6E11 1065 A 2383 A 1.12E17 56.1 % 81 shows the average sheet resistance (R^) and i t s scatter, Hall mobility (U ), S H undepleted carrier concentration (N^,), zero gate bias depletion width ( WQ)» the doping profile depth at a doping level of 10 1 6 (Wj), the peak carrier concentration N , and activation of the 5 samples. The information of the max' r last four entries in table 5.1 were obtained from the doping profiles of the five samples determined by C-V carrier profiling. The doping profiles of the five substrates and the d r i f t mobilities are shown in figures 5.4(a-e). The as-implanted profile was calculated knowing that the implant depth R^ is 850A and the standard deviation AR^ is 442A for an energy of 100 keV, and a dose, Ds, of 2.2xl0 1 2 cm - 2; n(x) is (e.g. [4]): (x—R ) 2 n(x) = — EXP{ -2—4 (5.1) 1/2 (2it) AR 2(AR ) 2 P P The theoretical peak carrier concentration is the factor multiplying the exponential in equation (5.1). The measured peak carrier concentration (from C-V measurements) can then be divided by that obtained for the as-implanted profile to obtain activation in table 5.1. The calculated doping profile, on the other hand, was estimated by including the effects of the time, t, of the anneal and also be taking into account the diffusion coefficient, D, of s i l i c o n in GaAs (Yamazaki et a l . [85]). The effective straggle is increased by diffusion at high temperatures and becomes [85,86]: f 9 1 AR' = ((AR ) + 2 D t) P v P Fig. 5 . 4 As-implanted, calculated, and measured carrier density profiles and dr i f t mobility profiles l.E+18 toooo 7 I.E+17 < s u c o •7 7 t. «• c • c l.E+16 h o u I.E+15 .7 • ' l I I. 11 ' • ' 1 • \ • _i 1 1 1 I , 0 IOOO "Z « « > \ < fi U too * 0 . 1 .2 .3 Depth (micron) .4 .5 (b) A-727 (Cominco) Fig. 5.4 cont'd oo Cencantrttton (cm"—3) <78 Concantratton (cm--3) C o n c a n t r s t t o n (cn<"—3) M o b i l i t y (cm "2/vsec) 98 87 where t is 1500 sec and D = 3 x l 0 - l b cm2/sec. This effective straggle replaces AR in equation (5.1) and the resulting calculated profile is P generally flatter than the as-implanted profile. Examination of the parameters in table 5.1 and the doping profiles reveals wide variations between the substrates. Concentrating f i r s t on Cominco's material, i t is seen that their most recent wafer A-727 has the least scatter in the threshold voltage, drain current and sheet resistance among a l l the samples. This makes i t desirable. The fact that the drain current measured was one of the lowest is explained by the doping profile (figure 5.4b) which shows that the electron density as a function of depth i s the closest to the calculated doping profile and therefore the channel is narrower. An interesting feature of this sample is the fact that the dip i n the peak carrier concentration, N m a x » was not accompanied with a long diffusion t a i l as compared to other samples from the same vendor. This may be caused by substantial compensation of s i l i c o n in the channel. Nevertheless, the d r i f t mobility of this substrate can be seen in figure 5.4b to be rising towards the interface, reaching 5100 cm2/v sec near the semi-insulating substrate. On the other hand, comparison of Cominco's samples from different eras, A-686 (1985) and A-184 (1982), both of which were qualified for fabrication, show differences with respect to the drain current magnitude and the threshold voltage which are evident by examining table 5.1. The differences can be explained by comparing the doping profiles of the samples in figures 5.4a and 5.4c where i t can be seen that extensive diffusion has taken place for sample A-184 making i t s channel the widest, and 88 as a consequence, the drain current and threshold voltage of A-184 is the highest of a l l the five samples. Unlike A-727, there is substantially higher scattering of the threshold voltage, drain current, and sheet resistance in both A-686 and A-727. The d r i f t mobility profile for A-686 can be seen in figure 5 . 4 a to be rising to a value fo 6200 cm2/v sec towards the interface, while for A-184 the d r i f t mobility shown in figure 5 . 4 c is constant ( 5 0 0 0 cm2/v sec) towards the interface. The better mobility, better activation, and smaller diffusion t a i l of the recent sample, A-686 shows that the vendor has changed the growth conditions to improve his material. A-727 which is rather different from A-686 though they were both grown at close periods of time indicate that one or more growth parameters were not adequately controlled. Sample B from Sumitomo showed substantially different charcteristics. Compared to Cominco's recent material (A-686) i t had similar drain currents, and similarly controlled diffusion t a i l s in the doping profile. However, high activation is obtained as indicated by the better peak carrier concentration. Also, substantially less depletion width under the gate is observed (949A compared to 1186A for A - 6 8 6 ) . The scatter in the drain current and of the threshold voltage was better controlled, perhaps as a result of a lower dislocation density in this 2" wafer than Cominco's 3 " wafers. However, the d r i f t mobility of this sample (figure 5 . 4 d ) was constant ( 4 3 0 0 cm2/v sec) toward the interface, which was far lower than any of Cominco's material. Sample C from Litton had the lowest percentage activation, drain current, and threshold voltage in comparison to Cominco's and Sumitomo's high 89 pressure grown substrates. The scatter of the threshold voltage and drain current, however, was confined to reasonably good values similar to sample B. The depletion width under the gate and the diffusion of the carriers were adequately controlled as in A-727. However, as a consequence of lower activation, the threshold voltage was lower than A-727. The d r i f t mobility profile shown in figure 5.4e reaches a value of 4200 cm2/v sec which is the lowest amongst the five samples. 5.6 Results on Deep Levels The MESFETs used for this test were made essentially following process III described in the previous chapter i.e. direct Implantation into GaAs and annealing under PECVD silicon nitride cap. Another refinement was now introduced in that capping was done also on the back side so as to prevent As loss on this surface. It was found in the previous chapter that only a single level, Sl, was present in the MESFET channels prepared by process III. In addition, i t was found using OTCS that this trap was present in the starting material as EL12, and hence was not process-induced. In this experiment, a l l processing steps are identical and hence deep levels other than Sl present in the five GaAs MESFET channels may be concluded to be substrate-induced. Results of channel current DLTS spectra on MESFET T4 (L = 50 um, W = 425 um) for the five samples from three vendors are shown in figures 5.5a to 5.5e. Arrhenius plots of the traps obtained are shown in figure 5.6. Tables 5.2 and 5.3 provide the DLTS data and concentration of the traps. Examination of the DLTS spectra of the five substrates reveal a number of substrate-induced defects. Focussing f i r s t on 1 i SI i • i 200 250 300 350 400 0 T K - (a) A-686 (Cominco) F i g . 5.5 Channel c u r r e n t DLTS spectra f o r MESFETs f a b r i c a t e d on f i v e s u b s t r a t e s (Rate Window = 49.7msec) S2 S3 (b) A-727 (Cominco) Fig. 5.5 cont'd S2 200 250 300 T°K S3 (c) A-184 (Cominco) F i g . 5.5 cont'd -2 < 3 200 250 1 S1 L_ 300 T°K (d) B (Sumitomo) Fig. 5.5 cont'd S4 (e) C ( L i t t o n ) F i g . 5.5 cont'd THIS MARTIN EL6 / HL6 / / 4 1000/T g. 5.6 Signature l i n e p l o t s of the channel c u r r e n t DLTS data 96 Table 5.2 DLTS data on the traps found by channel current DLTS. Trap Level Activation Energy Capture Cross Section Type Identity Sl S2 S3 S4 S5 0.74 eV 0.52 eV 0.87 eV 0.69 eV 2.1X10- 1 3 cm2 3.62xl0 - 1 6 cm2 5xlO - l i + cm2 2.3* 1 0 - 1 2 cm2 electron electron hole trap electron hole trap EL12 Cr ? Table 5.3 Concentration of the traps found by channel current DLTS. concentration of traps (cm - 3) Substrate Type S l S2 S3 S4 S5 A-686 A-727 A-184 B C 8.7xl0 1 1 + 1.98* 10 1 4 1.89x10* 4 2.13* 10 1 5 5.32xl0 1 3 1.7xl0li+ 1.90* 10 1 4 2.17xl0llt 97 Cominco's material, the DLTS spectrum of sample A-686 reveal that there are two traps one of which is Sl (EL12) at a relatively high concentration (8.7E14cm-3). The second trap is substrate-induced and occurs at a high temperature (T > 400 K) beyond the range of the experimental setup, and therefore information about the activation energy, capture cross section and possible identification of the peak could not be obtained. However, i t can be seen that the concentration of that level Is high and in addition, at that temperature, i t was observed that there was substantial lagging of the rise time of the drain current in response to changes in the gate voltage. The above traps are expected to be in the channel region and not at the interface since the d r i f t mobility was high toward the interface with the semi-insulating substrate. A rather different spectrum was observed for sample A-727 in figure 5.5b. Three substrate-induced defects were found, two of which were hole traps. The level Sl was not found but instead, another electron trap, S2, occurs in the vi c i n i t y with much smaller capture cross section and closer to the conduction band as seen in table 5.2. The main feature of the spectrum is the dominant hole trap S3 with an activation energy of 0.87 eV. This could be due to an impurity, possibly chromium, and occurred at a relatively high concentration (2.13E15 cm - 3). Another hole trap S6 was found with a much smaller concentration (1.9E14 cm - 3) but could not be identified since the peak was too broad for i t s characteristic temperature to be obtained accurately. It is possible that the limited diffusion of the ion implanted si l i c o n found in this sample in comparison to other samples from this vendor was due to the high concentration of the hole trap S3 which acts as an 98 acceptor and compensates donors in the channel. The hole traps appearing in this sample, but which were not observed in A-686 although both substrates were recent indicates possible contamination during growth. The DLTS spectrum of sample A-184, the substrate which was grown three years earlier displayed similar traps to A-727. Two traps were found, S2 and S3, the second of which showed smaller concentration (5.32E13 cm - 3). These findings indicate again that vendor A has changed some of the growth parameters over the three year period, as the DLTS spectra of A-686 and A-184 are entirely different. While he succeeded in reducing the impurities of his undoped substrate material (evidenced by the absence of hole traps in A-686), the control of the growth environment was apparently inadvertently lost during the growth of his recent substrate A-727. Sample B of Sumitomo displayed a DLTS spectrum similar to the material investigated in the previous chapter for process III. The level SI was found with a small concentration (1.9E14 cm - 3) and no substrate induced defects were found. Sample C of Litton did not show the level SI, but another electron level appeared in the vi c i n i t y , S4, at a small concentration, (1.90E14 cm - 3), which was not present in the starting material. 5.7 Results on Backgating Backgating is the phenomenon where the drain current of a MESFET is modified by the application of a bias voltage to a nearby electrode separated from the active device by the semi-insulating substrate. This phenomenon occurs when the channel interface with the bulk is modulated in thickness as a result of backgating bias with the semi-insulating separating layer acting 99 as a dielectric [87]. The severity of the backgating effect is dictated by the separation of the nearby devices, thermal stability of the substrate, the degree of isolation between devices, and the material properties of the semi-insulating substrate. Lee et a l . [88] and Miers et a l . [76] found a backgating voltage threshold which coincided with a trap f i l l e d limit voltage where carriers injected from the backgating voltage f i l l the traps in the substrate. Beyond the threshold, substrate conduction causes cross-talk between devices. However, agreement between the backgating threshold and the trap f i l l e d limit voltage is not conclusive in the literature as the results of Blum and Fleshner [89], and Tang [36] found l i t t l e or no threshold for capless annealed and silicon dioxide cap annealed devices respectively; both suggest p-type surface conversion caused by the outdiffusion of EL2 as a probable cause of surface conduction giving rise to backgating. Ogawa and Kamiya [90] studied both HB (chromium compensated) and undoped LEC substrates and found gradual reduction in drain current as soon as backgating potential is applied for HB substrates; a threshold was however found in undoped LEC GaAs. In this study, backgating (sidegating) due to bias on a contact 500 um away from an active device, T l , was investigated for the undoped LEC GaAs from different vendors. Results of normalized drain current (with respect to I. ) as a function of sidegating bias from +20 V to -30 V for the 5 sub-Q S S strate materials are shown in figure 5.7. As a l l processing steps are the same, expected variations in the sidegating behaviour are attributed to material differences. It can be seen from figure 5.7 that three substrates, A-727, A-686, and sample B were affected by backgating bias at +5 V, with Fig. 5.7 Comparison of normalized drain current versus backgating voltage for five GaAs samples g o 101 sample A-727 showing considerable backgating effect as the drain current reduce to half at of -30 V; this makes i t unqualified for active device fabrication. It is likely that the dominant hole trap S3 found in A-727 which behaves as an acceptor could form a p-type layer on the surface i n addition to the outdiffusion of EL2 reasoned by [89,36] and therefore enhancing substrate conduction. On the other hand, Cominco's earlier sample, A-184, was affected differently by backgating, and the threshold of backgating is found to be -5 V, which agrees with Lee et a l . [88]. The low pressure grown sample C, appears in this experiment to have the best backgating characteristics, the backgating voltage threshold for this sample is -16 V, which makes i t attractive for high density fabrication. This study shows that the backgating effect is very much material dependent which can explain the disagreement in the experimental findings of backgating in the literature. 5.8 Discussion of the Results Comparison of various undoped LEC GaAs material has shown that the electrical characteristics of ion implanted active layers, such as, activation efficiency, mobility, doping profile control, and uniformity is a function of the starting material. One of the main differences in the active layer characteristics of the five substrates studied here was shown to be the carrier concentration profiles. Deviations from the calculated doping profiles occur as a result of variations in the depletion width under the gate, the doping efficiency, and the diffusion t a i l s . The depletion width under the gate is [91]: 102 2 e V W 0 <l(N_. + NT) bi u / 2 where V is the b u i l t - i n potential (0.8 V for GaAs), N is the doping bi concentration and is the total concentration of traps, and e is the permittivity of GaAs. Changes in the depletion width can occur as a result of variations in doping efficiency and residual defects just under the surface. Doping efficiency is the ratio of the net donor concentration from the implanted silicon dose. The net donor concentration in undoped GaAs is the amount of the si l i c o n which is ele c t r i c a l l y active plus the number of shallow donors N , minus the amount of both shallow and deep acceptors (N , S G S3. N^ a). Deep donors do not affect activation since they are ele c t r i c a l l y neutral in the undepleted channel [71]. The extent of diffusion t a i l s are affected by [92] the annealing temperature, stresses caused by the annealing cap, implant dose, and stoichiometry of the substrate. With a l l parameters the same, different extents of dopant diffusion in the five substrates examined were caused by stoichiometry differences affected by the varying concentration of impurities, defects, and vacancies. It has been reported that inhomogeneity in the doping profiles, which in turn produces variations in threshold voltages and drain currents, may be caused by the dislocations in the substrates. For example, Nanishi et a l . [93] reported that high dislocation density increases the drain current and reduces the threshold voltage in undoped LEC GaAs. Ishi i et a l . [94] focussed on the effect of dislocation networks on the active layer parameters 103 and found that the threshold voltage scatter was correlated with dislocation c e l l networks and not with dislocation density. In the central part of the dislocation network the drain current was decreased whereas the threshold voltage increased. More recently, however, Winston et a l . [95] found no correlation between threshold voltage and the active layer vicinity to the nearest dislocation for both conventional LEC GaAs and indium alloyed GaAs substrates. They reported however more uniform threshold voltages for lower dislocation density In-alloyed GaAs than the higher dislocation density LEC GaAs. The extent of diffusion of the Implanted species, the pinch-off voltages, and threshold voltages were calculated from the measured capacitance-voltage profiling to determine the extent of variations In the substrates investigated. The effective straggle, AR'^ , was calculated from both N aud the diffusion depths at a doping concentration of 10 1 6, W^ , which were tabulated in table 5.1 and solved for in the following equation: The value of the corresponding diffusion coefficient, D', was then calculated from the effective straggle: 10 1 6 = N Exp( -2(AR" ) 2 max AR" = (AR 2 + 2 D ' t ) 1 / 2 P V P The pinchoff voltage was calculated by integrating the charges under the gate 104 that had to be depleted numerically [91]: CO V = M n(x)'xdx P £ 0 where n(x)' is the Gaussian profile f i t t e d to the capacitance-voltage (C-V) profile obtained for each substrate. Finally, the threshold voltage was calculated by subtracting the b u i l t - i n potential from the pinchoff voltage. The results are given in table 5.4 where the calculated pinchoff voltage and threshold voltages of the calculated and as-implanted profiles are also given. The calculated threshold voltages can be seen to approximately match those experimentally derived in table 5.1 with the exception of sample B where the experimental threshold voltage was lower. This indicates that the C-V profile when integrated over the channel length gives more charges in the depletion region than there actually are. This discrepancy must be caused by a degree of n-type surface conversion. For the other samples, the slight difference in threshold voltage is due to variations in the depletion width at zero gate voltage under the gate as indicated in table 5.1. From the circuit design stand-point, control of the threshold voltage is required for the Schottky Diode Field Effect Logic (SDFL) should be within ±200 mV. This allows thickness variations only in the order of 80A-100A [71]. This means for the samples studied that the measured straggle has to be within that thickness variation from the design or control sample. A l l the samples investigated here had a threshold voltage scatter within the required limit for the SDFL c i r c u i t . For LSI circuits, however, considerably 105 Table 5.4 Comparison of the calculated values of effective straggle (ARp), diffusion coefficient (D'), pinchoff voltage (V p), and threshold voltage (V t^) of five GaAs samples. Profile AR" N D' V V.. p max p tn A cm-3 cm 2sec - 1 volts volts A-686 717 1.32xl0 w A-727 688 1.22xl0 1 7 A-184 822 1.26xl0 1 7 B 723 1.36xl0 1 7 C 699 1.12xl0 1 7 LSS 442 2.00xl0 1 7 Calculated 534 1.64X101 1 0 . 6 x l 0 - 1 5 -2.91 -2.11 9.24xl0 - 1 5 -2.58 -1.78 1 6 x l 0 - 1 5 -3.18 -2.38 10.9xl0 - 1 5 -3.03 -2.23 9.72X10 - 1 5 -2.39 -1.59 0 -2.61 -1.81 3 x i o - l 5 -2.63 -1.83 106 more stringent demands are placed on the threshold voltage so that standard deviation must remain within ±50 mV [71]. This requires better substrate quality and reproducibility than presently available. 5.9 Summary Undoped LEC GaAs was investigated for suitability of IC applications. The following results were obtained: 1. Comparison of the low pressure and high pressure growth materials showed that while the active layer properties of the low pressure grown GaAs was poorer in mobility and activation compared to the high pressure material, i t nevertheless had good homogeneity, low deep level concentrations, and excellent backgating characteristics. 2. Comparison of the high pressure grown GaAs from different suppliers showed that there are differences in the material which resulted i n differences in doping profiles, mobilities, deep levels, backgating characteristics, and surface conversion. 3. Comparison of the substrates grown at different times from one supplier revealed that the vendor had changed the 'recipe' over the time period examined as the latest material showed worse backgating characteristics, lower diffusion, and entirely different substrate-induced deep levels. 4. Examination of the substrate which was rejected by a device manufacturer revealed that while i t showed better controlled doping profiles and homogeneity, the sample had low el e c t r i c a l activation, high concentration of undesirable deep levels, and substantial backgating. 107 CHAPTER 6 CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK In the work reported in this thesis a wide range of diagnostic tools including carrier concentration and d r i f t mobility profiling in MESFETs, backgating, and deep level spectroscopic techniques were used to characterize commerically available undoped LEC GaAs. The following observations can be made: 1. Investigation of various GaAs substrates by OTCS revealed that eight traps, P1-P8, were present with P2 being a negative peak. The relative concentration of traps in high and low pressure grown GaAs were found to be different. The OTCS technique was found to be sensitive to GaAs surface treatment, for example, some peaks were attenuated in amplitude following surface etch, whereas the amplitude of the negative peak was increased after surface grinding. The OTCS spectra were affected by the sample geometry and type of electrodes. For future work, i t is suggested that the amplitudes of the eight traps found here should be obtained as a function of position in a GaAs substrate with a scanning OTCS system now under construction in our laboratory. The results of this study can then be correlated with the dislocation density distribution. 2. Investigation of deep levels after silicon ion implantation by channel current DLTS revealed that process-induced defects appear in MESFETs furnace annealed with sil i c o n dioxide encapsulant. Furnace annealing with PECVD sili c o n nitride cap, however, did not cause process-induced defects. 108 For future work i t is suggested that deep levels in MESFETs annealed with and without cap using rapid thermal annealing (RTA) should be investigated. The results can shed light into the role of heating and cooling rates of the two annealing processes on defect generation. 3 . Investigation of MESFETs fabricated identically on various LEC undoped GaAs revealed that some of them had defects which were not present i n the starting material and may therefore be concluded to be substrate-induced. It is believed that stoichiometry differences in various substrates play a role in inducing defects after ion implantation and annealing. For future study i t is suggested that surface analysis by Secondary Ion Mass Spectroscopy (SIMS) for example should be carried out in various substrates to investigate the relation between stoichiometry and substrate-induced defects. 4 . It was concluded in chapter 5 that backgating is dependent on the type of GaAs material used. One of the samples which showed substantial backgating had a dominant hole trap which could have played a role. Other samples had different deep level compositions and showed different extents of backgating severity. To investigate whether backgating is influenced by traps, i t is suggested for future work that the technique of channel current DLTS be modified to investigate deep levels at the interface of the channel and the semi-insulating substrate. The modification requires that a constant negative bias be applied to the gate of a MESFET so that the channel is nearly pinched off while electrical pulses are applied to the backgating electrode. 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