UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

GaAs material investigation for integrated circuits fabrication Dindo, Salam 1985

You don't seem to have a PDF reader installed, try download the pdf

Item Metadata

Download

Media
[if-you-see-this-DO-NOT-CLICK]
UBC_1985_A7 D55.pdf [ 4.41MB ]
[if-you-see-this-DO-NOT-CLICK]
Metadata
JSON: 1.0096234.json
JSON-LD: 1.0096234+ld.json
RDF/XML (Pretty): 1.0096234.xml
RDF/JSON: 1.0096234+rdf.json
Turtle: 1.0096234+rdf-turtle.txt
N-Triples: 1.0096234+rdf-ntriples.txt
Original Record: 1.0096234 +original-record.json
Full Text
1.0096234.txt
Citation
1.0096234.ris

Full Text

GaAs MATERIAL INVESTIGATION FOR INTEGRATED CIRCUITS FABRICATION  By SALAM DINDO B.A.Sc, The University of B r i t i s h Columbia, 1982  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF  MASTER OF A P P L I E D  SCIENCE  in THE FACULTY OF GRADUATE STUDIES Department of E l e c t r i c a l Engineering  We accept this thesis as conforming to the required standard  THE UNIVERSITY OF BRITISH COLUMBIA October 1985 © Salam Dindo, 1985  In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may  be granted by the head of my  department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission.  Department The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date  DE-6(3/81)  ABSTRACT  The primary objective of the work described i n this thesis was  to  study the influence of undoped LEC GaAs substrate material from various suppliers on the performance of ion implanted Optical transient current spectroscopy  (OTCS) was  q u a l i f i c a t i o n test for GaAs substrates. before ion implantation were obtained.  and annealed active l a y e r s . investigated as a  Deep l e v e l spectra of the substrates It was  found that while the OTCS  spectra of high pressure grown GaAs from two suppliers were s i m i l a r , that of the low pressure material showed different r e l a t i v e concentration of traps. The use of OTCS was  further extended to study trap concentration as a  function of surface treatment.  It was  found that the use of chemical  etchants reduces the concentration of some l e v e l s , possibly those located on the surface as opposed to bulk traps.  Surface damage was  the negative peak i n the OTCS spectrum.  found to enhance  The deep levels spectra were found  to be affected by the geometry of the device and the type of electrode material. Channel current deep l e v e l transient spectroscopy  (DLTS) was  used to  study both process- and substrate-induced  deep levels i n ion implanted MESFET  channels.  traps were found to be different  The spectra of process-induced  according to the encapsulant  used.  S i l i c o n dioxide (both RF sputtered  plasma enhanced chemically vapor deposited (PECVD)) was variety of process related defects.  and  found to induce a  This i s believed to be because s i l i c o n  dioxide i s permeable to gallium and hence does not preserve the stoichiometry  - iii -  of ion implanted GaAs during high temperature anneals.  Deep l e v e l spectra of  MESFETs annealed using s i l i c o n n i t r i d e , on the other hand, were found to contain single traps related to the defects i n the starting material.  For  implants through s i l i c o n n i t r i d e , a high concentration of the main electron trap EL2 was found, whereas implants d i r e c t l y into the surface resulted i n the l e v e l EL12. Comparison of the c h a r a c t e r i s t i c s of the variety of LEC undoped GaAs material show that they d i f f e r e d widely and had inhomogeneous properties. For example, compared to the high pressure grown GaAs, the Litton*s low pressure substrate had lower a c t i v a t i o n , mobility, drain current and threshold voltage, good confinement of the scatter i n the same c h a r a c t e r i s t i c s , low concentration of deep l e v e l s , and the least backgating e f f e c t which makes i t promising for IC f a b r i c a t i o n .  Comparison of the high  pressure grown material from two suppliers showed that Cominco's recent material had good mobility, a c t i v a t i o n , r e l a t i v e l y high scatter of threshold voltage, high concentration of deep l e v e l s , and was affected by backgating. In comparison, Sumitomo's material showed thermal i n s t a b i l i t y , less scatter of threshold voltage, less mobility and deep l e v e l concentrations, and s i m i l a r backgating c h a r a c t e r i s t i c s .  Substrate grown three years e a r l i e r  showed higher d i f f u s i o n of dopant, d i f f e r e n t deep l e v e l s , and better backgating c h a r a c t e r i s t i c s .  F i n a l l y , a substrate which had f a i l e d the  q u a l i f i c a t i o n test by a device manufacturer showed minimal d i f f u s i o n t a i l s and threshold voltage scatter, the highest concentration of deep l e v e l s , and substantial backgating.  - iv -  TABLE OF CONTENTS Page  ABSTRACT  i i  LIST OF TABLES  vi  LIST OF FIGURES  vii  ACKNOWLEDGEMENTS  ix  INTRODUCTION  1  GROWTH AND PROPERTIES OF SEMI-INSULATING GALLIUM ARSENIDE  3  Introduction  3  GaAs Crystal Growth Techniques  3  Impurities and Their Role i n Undoped LEC GaAs...  6  Relation of Melt Stoichiometry to Compensation and Thermal S t a b i l i t y of GaAs 2.5 3.  Recent Advances i n the Growth of Undoped LEC GaAs  8 10  OPTICAL TRANSIENT CURRENT SPECTROSCOPY INVESTIGATION OF VARIOUS GaAs SUBSTRATES  13  3.1  Introduction to Optical Transient Current Spectroscopy......  13  3.2  Theory of Optical Transient Current Spectroscopy  14  3.3  Experimental Procedure  19  3.4  Results....  21  3.4.1  OTCS Spectra of GaAs Substrates From Three Vendors...  24  3.4.2  I d e n t i f i c a t i o n of the Peaks  27  3.4.3  Effects of Varying Sample Geometry on OTCS Spectra...  33  - v -  Page  3.5 4.  5.  6.  3.4.4  Effect of Varying the Electrode Material  35  3.4.5  Effect of GaAs Surface Damage on the OTCS Spectrum...  39  Summary  44  INVESTIGATION OF PROCESS-INDUCED DEEP LEVELS IN ION IMPLANTED MESFETs  45  4.1  Introduction  45  4.2  Principle of Channel Current DLTS  47  4.3  Experimental Procedure  52  4.4  Results  54  INFLUENCE OF VARIOUS LEC UNDOPED GaAs SUBSTRATES ON THE CHARACTERISTICS OF ION IMPLANTED AND ANNEALED ACTIVE LAYERS  66  5.1  Introduction  66  5.2  Description of the Diagnostic Test Pattern  69  5.3  Diagnostic Pattern Fabrication  69  5.4  Measurements on the Diagnostic Test Pattern  75  5.5  Results of Active Layer Evaluation  78  5.6  Results on Deep Levels  89  5.7  Results on Backgating  98  5.8  Discussion of Results  101  5.9  Summary  106  CONCLUSIONS AND SUGGESTIONS FOR FURTHER WORK  REFERENCES  107 110  - vi LIST OF TABLES Page 2.1 3.1  3.2  4.1  4.2 5.1  Order of magnitudes of some common impurities found i n SI, undoped, LEC GaAs  7  Activation energies, capture cross sections, and possible i d e n t i t i e s of the deep levels found using OTCS (Pl-8) i n SI, undoped, LEC GaAs  29  Deep levels i n SI GaAs reported i n the l i t e r a t u r e (as detected by OTCS (PITS)). VPE = Vapour Phase Epitaxy  30  Activation energies, capture cross sections, and possible i d e n t i t i e s of the deep levels found using channel current DLTS i n MESFETs fabricated using four processes (Q1-4.R1,SI,Tl-4)  62  Some deep levels i n s i l i c o n implanted i n the l i t e r a t u r e  64  Comparison of the active ion implanted parameters of f i v e GaAs samples  GaAs reported layers 80  5.2  DLTS data on the traps found by channel current DLTS  96  5.3  Concentration of traps found by channel current DLTS  96  5.4  Comparison of the calculated values of e f f e c t i v e straggle (AR"), d i f f u s i o n c o e f f i c i e n t (D'), pinchoff voltage (V ), and threshold voltage (V ^) of f i v e GaAs samples t  105  - viiLIST OF FIGURES Page 3.1  Geometry of (a) planar and (b) sandwich structures used i n OTCS  20  3.2  Block diagram of the OTCS setup  22  3.3  Vacuum chamber used i n the OTCS experiment  23  3.4  OTCS spectra of SI undoped LEC GaAs from three vendors (Rate Window = 8.5 msec) OTCS spectra of SI undoped LEC GaAs substrates from two vendors subjected to chemical etch (Rate Window = 8.5 msec)  26  3.6  Activation energy plots f o r traps detected using OTCS  28  3.7  OTCS spectra of d i f f e r e n t planar sample geometries (Rate Window = 18.9 msec)  34  OTCS spectra of samples prepared with d i f f e r e n t electrodes (Rate Window = 38.8 msec)  36  Current vs. voltage for planar specimens with d i f f e r e n t electrodes  38  Signature l i n e plots for the data of figure 3.9 (Labels same as i n figure 3.9)  40  OTCS spectra of sandwich structures with a negative bias on the top illuminated electrode (Rate Window = 75.5 msec)  42  OTCS spectra of a planar structure (a) before and after chemical etch (b) after l i g h t abrasion (c) after chemical etch (Rate Window = 75.5 msec)  43  Schematic diagram showing the channel current DLTS measurement system  48  Transient responses of the drain current to an applied gate voltage  49  Block diagram of channel current DLTS system  55  3.5  3.8 3.9 3.10 3.11  3.12  4.1 4.2 4.3  25  - viii Page 4.4 4.5 4.6  4.7  4.8 4.9  Channel current DLTS spectrum for MESFETs prepared using process 1  56  Channel current DLTS spectrum for MESFETs prepared using process II  57  Channel current DLTS spectrum for MESFETs prepared using process I I I  58  Channel current DLTS spectrum for MESFETs prepared using process IV  59  Signature l i n e plots for channel current DLTS data of processes I-III  60  Signature l i n e plots for channel current DLTS data of process IV  61  5.1  The diagnostic test pattern  70  5.2  Fabrication sequence for the diagnostic test pattern  72  5.3  Typical I - V c h a r a c t e r i s t i c s of MESFETs i n the diagnotic test pattern As-implanted, calculated, and measured c a r r i e r density p r o f i l e s and d r i f t mobility p r o f i l e s  5.4 5.5  D  S  D S  79 82  Channel current DLTS spectra for MESFETs fabricated on f i v e substrates (Rate Window = 49.7 msec)  90  5.6  Signature l i n e plots of the channel current DLTS data  95  5.7  Comparison of normalized drain current versus backgating voltage for f i v e GaAs samples  100  ACKNOWLEDGEMENTS  I thank my supervisor, Dr. L. Young, for his guidance and f o r suggesting many of the ideas of my work. Mr. Wade Tang i s to be thanked for his assistance i n the DLTS experiments and for his helpful discussions. I also thank Messrs. I.A. Motaleb, P. Townsley, and K. Tan for t h e i r assistance i n f a b r i c a t i o n ; D. Hui for writing the software routines used to prepare some of the figures; W.C.  Rutherford for proofreading my thesis; and  W. Durtler, M. LeNoble, N. Jaeger, and P. Neilson for the helpful discussions. Appreciation i s also due to Messrs. R.F. Redden and R.P. Bult of Cominco Ltd., and K. Lowe of B e l l Northern Research for supplying some GaAs wafers; A. Lakhani of A l l i e d Bendix Aerospace for preparing some of the samples used i n the channel current DLTS measurements; A. L. Kjolby, who maintained the equipment  Leugner and  i n the lab; and Ms. M.  Depuit who  typed the manuscript. Financial support provided by the B r i t i s h Columbia Science Council and by the Natural Sciences and Engineering Research Council of Canada i s also acknowledged.  1  CHAPTER 1  INTRODUCTION  Formation of uniformly doped impurity layers i n bulk grown GaAs substrates for integrated c i r c u i t (IC) f a b r i c a t i o n by ion implantation offers more advantages than the use of doped e p i t a x i a l grown layers because of the ease, precise control and r e p r o d u c i b i l i t y of the implantation process.  Of  the two available bulk c r y s t a l growth methods, Horizontal Bridgman (HB)  and  Liquid-Encapsulated  Czochralski (LEC), the former has found decreasing  applications i n IC f a b r i c a t i o n because of the l i m i t a t i o n of the size and shape of HB substrates, and because of low device y i e l d .  LEC grown GaAs, on  the other hand, i s becoming the dominant choice for IC fabrication because two to four inch diameter wafers can be grown, and because semi-insulating (SI) GaAs can be made without  i n t e n t i o n a l addition of impurities.  The objectives of this thesis are to investigate undoped LEC GaAs substrates for IC f a b r i c a t i o n . obtained.  GaAs wafers from different vendors were  The deep trapping levels i n SI GaAs wafers were investigated using  Optical Transient Current Spectroscopy  (OTCS).  Deep levels i n ion implanted  MESFETs fabricated using several d i f f e r e n t processing techniques were investigated by channel current Deep Level Transient Spectroscopy  (DLTS). (1)  The processing techniques applied for MESFET f a b r i c a t i o n included:  ion  implantation d i r e c t l y into GaAs; and ( 2 ) ion implantation through Plasma Enhanced Chemically Vapor Deposited  (PECVD) s i l i c o n n i t r i d e f i l m .  Several  d i e l e c t r i c capping materials for high temperature anneals were used:  (1)  RF  2  sputtered s i l i c o n dixoide; (2) PECVD s i l i c o n dioxide; and (3) PECVD s i l i c o n nitride.  Active layer parameters of various ion implanted  investigated and compared.  substrates were  The measurements used to assess the MESFETs were:  (1) threshold voltage and drain current magnitudes and scatter; (2) sheet resistance, Hall mobility and undepleted  c a r r i e r concentration; (3) c a r r i e r  and d r i f t mobility p r o f i l i n g , and (4) backgating. The contents of the thesis are as follows:  Chapter 2 gives an  overview of SI GaAs c r y s t a l growth techniques with particular emphasis on undoped LEC GaAs technology.  In Chapter 2, a review i s presented on deep  levels i n the starting SI GaAs materials, and a comparison i s made of the OTCS spectra of GaAs substrates from different suppliers. surface treatment  Influence of  on the OTCS spectra i s also investigated. Chapter 4  d e t a i l s the results of deep l e v e l investigation i n the MESFETs fabricated by the four different processing techniques described above. being to find and compare process-induced  deep l e v e l s .  The objective  Chapter 5 contains a  comparison of MESFETs made by the same process at the same time on GaAs wafers from three suppliers, including:  (1) low and high pressure grown  substrates; (2) high pressure grown substrates from two suppliers; and  (3)  two high pressure grown substrates from the same supplier which were grown at two d i f f e r e n t time periods.  In addition, a substrate i s investigated which  did not pass q u a l i f i c a t i o n tests by a device manufacturer. 6 gives conclusions and suggestions for future work.  F i n a l l y , Chapter  3  CHAPTER 2  GROWTH AND PROPERTIES OF SEMI-INSULATING GALLIUM ARSENIDE  2.1  Introduction Semi-insulating GaAs i s used for the production of high performance  electronic devices such as high speed d i g i t a l integrated c i r c u i t s , f i e l d e f f e c t t r a n s i s t o r s , charge coupled devices and monolithic microwave integrated c i r c u i t s .  For large scale integrated c i r c u i t GaAs technology to  develop r e l i a b l y many problems related to the reproducible growth of high quality crystals remain to be solved.  To achieve high e l e c t r i c a l yields of  GaAs ICs [1] i t i s essential to develop GaAs subtrates with low density of dislocations and impurities, high r e s i s t i v i t y and good thermal high a c t i v a t i o n of the implanted  2.2  stability,  species, and homogeneous doping  profiles.  GaAs Crystal Growth Techniques There are two main GaAs c r y s t a l growth techniques:  the Horizontal  Bridgman (HB) and the Liquid-Encapsulated Czochralski (LEC) [2,3,4].  In  the former, a quartz boat which contains gallium i s sealed inside a quartz ampoule f i l l e d with an inert gas. Arsenic i s placed at the neck of the ampoule, and a temperature gradient i s established such that the arsenic starts to sublimate (614°C) and the temperature of gallium i s held at 1235°C, the melting point of GaAs.  After the arsenic evaporates  and reacts with  gallium to form a GaAs melt, either the ampoule or the heaters are slowly moved so that the GaAs i s cooled at one end as the temperature gradient moves  4  along the boat; the growth then proceeds i n the <111> d i r e c t i o n .  The  resulting ingot takes the shape of the boat truncated by the l i q u i d surface i . e . , i t i s D shaped. material.  The wafers have to be cut at an angle to y i e l d <100>  A variety of impurities are introduced into the ingots i n the  quartz s i l i c a boat container. usually i n the 1 0  16  - 10  17  cm  The predominant -3  type of impurity i s s i l i c o n ,  range [5]. To make the HB GaAs  semi-insulating, a deep acceptor impurity, usually chromium, has to be incorporated into the melt at approximately 1 0 donor impurity l e v e l .  17  cm  -3  so as to balance the  Problems arise because of inhomogeneous FET  performance i n HB GaAs because of the nonuniformity i n the chromium concentration resulting from the disagreement between the cutting plane and the growth plane [6]. As an alternative to quartz boats, P y r o l i t i c Boron N i t r i d e (PBN) boats have been used i n an attempt to achieve higher purity GaAs [5], somewhat better performance was reported, but nevertheless, the r e s u l t i n g e l e c t r i c a l yields for Ion implantation remain generally low [1]. The LEC technique [7] i s used for the growth of III-V compounds with one v o l a t i l e constituent.  In this method, the melt i s prepared by a  compounding process [3] where gallium and arsenic are placed below a b o r i c oxide ( B 0 ) encapsulant and the entire assembly i s heated. 2  3  The temperature  i s held at the melting point of GaAs, and the seed i s lowered through the molten encapsulant into the GaAs melt.  In addition, an overpressure of an  inert gas, t y p i c a l l y argon, i s applied to prevent the arsenic from bubbling through the boric oxide.  Both the seed and the crucible are rotated slowly  in the opposite directions at predetermined r o t a t i o n a l speeds so as to reduce r a d i a l and s l i c e - t o - s l i c e nonuniformities [8]. A slow p u l l rate i s applied  5  to the seed and <100> GaAs round ingots 2-4 inches i n diameter are grown. To reduce contamination of GaAs with s i l i c o n , PBN rather than quartz crucibles are used [9]. 10  16  to 1 0  15  cm . -3  The resulting s i l i c o n concentration i s reduced from  Another reason for not using quartz i s that the boric  oxide reacts with s i l i c o n resulting i n losing the clear v i s i b i l i t y  through  the encapsulant which i s an essential requirement i n GaAs melt growth.  With  a quartz crucible, the boric oxide turns grey, opaque, and becomes f u l l of bubbles  [9], evidence of undesirable reaction of the melt with the  surroundings. free.  With a PBN c r u c i b l e , the boric oxide remains clear and scum  Growth of highly r e s i s t i v e GaAs depends d i r e c t l y on the boric oxide  preparation before growth;  the encapsulant has to be heat treated and vacuum  baked to reduce the water content and prevent contamination of the melt with oxygen. Unlike HB GaAs ingots, LEC GaAs ingots are round, c y l i n d r i c a l and can be semi-insulating without intentional doping.  Though i t i s necessary to add  chromium to the GaAs melt when grown with quartz crucibles, the same material grown with PBN crucibles i s s u f f i c i e n t l y acceptable for device f a b r i c a t i o n .  high i n r e s i s t i v i t y to make i t  The major advantages of undoped over  chromium doped LEC GaAs are the following:  (1) the lower concentration of  the ionized impurities leads to higher electron mobilities i n the ion implanted region; and (2) the absence of large r e s i s t i v i t y changes which are typically annealing.  caused by the r e d i s t r i b u t i o n of chromium during high  temperature  Undoped LEC GaAs i s gradually emerging as a high quality and  reproducible material for f a b r i c a t i o n of ion implanted active layers.  6  2.3  Impurities and Their Role i n Undoped LEC GaAs The p r i n c i p a l source of residual impurities i n undoped LEC GaAs i s the  i n t e r a c t i o n of the melt with the crucible and the boric oxide encapsulant [10].  Investigation of the various impurities using spectroscopic  techniques  [1,11,12] revealed the existence of contaminants i n undoped LEC GaAs grown with PBN  c r u c i b l e s , and substrate-to-substrate  variations i n concentration.  Table 2.1  as well as ingot-to-ingot  shows the order of magnitude of some  of the impurities. Boron, which i s believed to be inactive i n GaAs [11], i s introduced into the melt through reaction with the boric oxide.  Oxygen i s believed to  be s u b s t i t i o n a l i n the arsenic sublattice giving r i s e to a deep donor l e v e l . Its o r i g i n i s traced to the water levels ("wetness") of the boric oxide. was  It  only recently concluded [13] that oxygen i s not associated with the main  electron trap EL2 which i s responsible for the semi-insulating property of GaAs.  Chromium, an unintentional impurity, creates a deep acceptor  when i t occupies s u b s t i t u t i o n a l s i t e s i n the gallium s u b l a t t i c e .  rather  Carbon i s observed at high concentrations  GaAs, and i s believed to arise from the PBN  [4]  Silicon i s  a shallow donor and has consistently lower concentration when a PBN than a quartz crucible i s used.  level  in  crucible and from the close  proximity of the melt to the hot graphite furnace parts [10].  This  impurity  forms a shallow acceptor and together with the deep donor a n t i s i t e defect [14] tends to compensate the GaAs.  Sulfur arises from the arsenic source  element [1] and forms a shallow donor. acceptors  introduced  Magnesium and manganese are shallow  from the s i l i c o n n i t r i d e coracle [1] and the bulk  material [2] respectively.  Iron and copper impurities are deep acceptors  7  Table 2.1.  Order of magnitudes of some common impurities found i n SI, undoped, LEC GaAs  Impurity  Log (concentration/cm ) 3  Boron  15  Oxygen  16  Chromium  14  Silicon  15  Carbon  16  Sulfur  15  Magnesium  15  Manganese  15  Iron  15  Copper  15  Selenium  15  Tellurium  15  8  with p o t e n t i a l l y degrading  effects on the ion implanted  layer.  The former  has been demonstrated to cause interface traps between the active layer and the substrate [15] whereas the l a t t e r moves rapidly at low temperatures causing e f f e c t i v e reduction of the d i f f u s i o n length of n-type GaAs [4]. Copper contamination  of GaAs takes place during c r y s t a l growth as a result of  contact with the puller's brass material [5].  2.4  Relation of the Melt Stoichiometry to Compensation and Thermal S t a b i l i t y of GaAs GaAs melt composition  i s an important  growth parameter which affects  both r e s i s t i v i t y [10,16] and the concentration of the midgap l e v e l EL2 [16] which i s now believed to be the a n t i s i t e defect arsenic on gallium s i t e [14]. Stoichiometry variations i n GaAs substrates generate various native defects which recently have been found to influence the ion Implanted c a r r i e r concentration p r o f i l e s and e l e c t r i c a l a c t i v a t i o n [17].  Recent results on  r e s i s t i v i t y data [16] have shown that using dry boric oxide (500 ppm HgO), and above a c r i t i c a l arsenic concentration of 0.48 atom f r a c t i o n of the melt, the GaAs material i s semi-insulating and thermally stable up to about 0.53 (As atomic f r a c t i o n ) .  For compositions  where the arsenic atom f r a c t i o n i s  above 0.53, the r e s i s t i v i t y drops due to increase i n the free electron concentration.  On the other hand, below the c r i t i c a l arsenic concentration,  GaAs turns p-type.  This can be explained by reasoning that the EL2  concentration increases with increasing As/Ga and balance i s made with the residual carbon acceptors material semi-insulating.  VQ^/V^S  R  A  T  *-  O  S  [1^]>  anc  *  [18] so as to make the  The material becomes p-type below the c r i t i c a l  composition because the EL2 concentration becomes lower than that of the  a  9  shallow acceptors, and becomes n-type for compositions  above 0.53  f r a c t i o n because the EL2 concentration i s higher than the shallow  As atom acceptors  concentration. S i g n i f i c a n t l y different results are obtained when using wet boric oxide (2000 ppm H 0).  Recent results [19] have shown that i n this case above  2  a c r i t i c a l arsenic concentration of 0.42  atom f r a c t i o n of the melt, the GaAs  material remains semi-insulating up to an arsenic atom f r a c t i o n of 0.48.  The  impurities concentration i n the melt for boron, oxygen, and carbon are different from t y p i c a l levels obtained with dry boric oxide.  Lower  concentration for both boron and carbon were found, but the concentration of oxygen predictably was  larger.  The compensation i n this case i s expected to  be d i f f e r e n t because of the lowering i n the concentration of both EL2 (due to different melt composition) and carbon and the increase i n the density of oxygen donors. The thermal s t a b i l i t y of undoped SI GaAs i s also strongly influenced by the stoichiometry of the melt. GaAs to a conducting was  Conversion of the thin surface layer of  state, believed to be p-type, after thermal treatment  previously attributed to out-diffusion and pileup of residual acceptors,  such as, manganese [20], and an increase i n carbon levels due to solvents used during substrate preparation [12].  Recent results indicate that high  thermal s t a b i l i t y for undoped LEC GaAs can only be achieved stoichiometric or arsenic r i c h compositions  [10].  with  For gallium r i c h melts and  dry boric oxide, the sheet resistance i s observed to decrease rapidly following high temperature anneal.  Surface conversion results when the  concentration at the surface f a l l s below the residual acceptor  EL2  concentration,  10  and the surface becomes p-type.  This mechanism i s probably enhanced by the  outdiffusion of gallium and/or arsenic defects to the surface.  2.5  Recent Advances i n the Growth of Undoped LEC GaAs Major e f f o r t s i n the past few years have been concentrated on  developing a controlled and reproducible growth technique of high q u a l i t y undoped LEC GaAs c r y s t a l s .  One such e f f o r t aims at purifying the material  using a special computer controlled d i s t i l l a t i o n process technique, decreased  [21].  In this  the arsenic pressure inside the growth chamber i s abruptly to near one atmospheric pressure; this creates bubbling i n the  b o r i c oxide encapsulant  as gases which include water, compounds of carbon and  water, compounds of s i l i c o n and water, and excess arsenic are released from the melt.  This bubbling process i s repeated u n t i l the e l e c t r i c a l  conductivity of the melt i s appreciably decreased.  GaAs crystals are grown  at low pressure (6 atm), and low temperature gradient i n the melt (50°C/cm) i s achieved by using thermal r e f l e c t o r s .  With both s i l i c o n dioxide and PBN  c r u c i b l e s , highly homogeneous and highly r e s i s t i v e ( l x l O obtained. (8xl0  3  8  ohm-cm) ingots were  The wafers are characterized with low dislocation density  -lxlO  4  cm ) with a U-shaped d i s t r i b u t i o n . -2  An a l t e r n a t i v e to the high pressure growth synthesis which i s i n common use i s a recent low pressure growth technique which i s said by i t s advocates to be more e f f i c i e n t techniques  [22].  The advantages of low pressure growth  are that the cycle times are s i g n i f i c a n t l y shorter, the maximum  crucible temperature i s lower, the melt capacity i s larger, and the melt stoichiometry can be better c o n t r o l l e d .  Though the q u a l i t y of the material  11  has not been f u l l y proven, recent results of GaAs grown using quartz crucibles indicate similar thermal s t a b i l i t y for arsenic r i c h melts (As/Ga = 1.02-1.04 atomic) and dry boric oxide (500 ppm water).  The activation and  mobility of s i l i c o n implanted material indicates similar results compared to the high pressure grown GaAs.  The work for this thesis includes tests on a  GaAs wafer grown at low pressure. More recently, attempts were made to reduce the dislocation density i n semi-insulating GaAs crystals [23,24], c r y s t a l under a low temperature  gradient and under a low pressure (5 atm), as  this further lowers the temperature heat transfer.  The p r i n c i p l e involved i s to grow the  gradient by decreasing the convection  The improvements made are found i n :  (1) reducing the arsenic  escape by increasing the thickness of the boric oxide encapsulant; (2) reducing the temperature  gradient at the boric oxide and the GaAs melt  interface; (3) reducing the temperature  gradient of the boric oxide i t s e l f by  opening windows bored i n the susceptor cylinder to d i r e c t l y heat this layer [24], and by setting a thermal b a f f l e above the crucible [23].  As a r e s u l t  of those improvements, very low d i s l o c a t i o n densities of approximately 1000/cm with uniform d i s t r i b u t i o n , and homogeneous high r e s i s t i v i t i e s (10 2  ohm-cm) were obtained f o r two inch diameter  8  wafers.  Another technique which i s successfully applied to obtain dislocation free crystals i s based on adding large amounts of indium or indium arsenide (0.1 mol% - 0.4 mol%) to the GaAs melt [12].  Those additions are found to be  e f f e c t i v e i n suppressing the generation of microdefects which are responsible for the formation of d i s l o c a t i o n s . temperature  This improvement, along with reducing the  gradient at the s o l i d / l i q u i d interface, i s necessary to prevent  12  the  generation and m u l t i p l i c a t i o n of dislocations from l o c a l i z e d thermal  stresses.  The resulting quality of the ion implanted layers' uniformity  indicate better homogeneity than conventional undoped LEC GaAs c r y s t a l s . F i n a l l y , the application of a v e r t i c a l magnetic f i e l d  [25,26] has been  attempted recently to enhance the uniformity and to reduce the dislocation density of high pressure LEC PBN grown GaAs.  The effect of the magnetic  f i e l d , which i s supplied by a super-conducting c o i l , i s to suppress the temperature fluctuations through the molten GaAs.  More importantly, laminar  thermal convection which degrades both the microscopic and macroscopic homogeneity of crystals has been reduced.  Uniformity i n the GaAs melt i s  enhanced by optimizing the seed rotation as this adds forced convection to the  melt.  It i s expected that those improvements can enhance the quality of  the  GaAs substrates for ion implantation.  13  CHAPTER 3  OPTICAL TRANSIENT CURRENT SPECTROSCOPY INVESTIGATION OF VARIOUS GaAs SUBSTRATES  3.1  Introduction to Optical Transient Current Optical Transient Current Spectroscopy  Photo Induced Transient Spectroscopy Deep Level Transient Spectroscopy  Spectroscopy (OTCS), often referred to as  (PITS) [27], i s a member of the class of  (DLTS) techniques.  Its advantage i s that  i t can be applied to semi-insulating GaAs (which i s the starting material f o r integrated c i r c u i t  (IC) f a b r i c a t i o n ) .  deep trapping levels which may  The aim i s to obtain information on  be of fundamental interest and would c e r t a i n l y  be of p r a c t i c a l interest i f i t could help i n diagnosing the s u i t a b i l i t y of the material for IC f a b r i c a t i o n . The OTCS method was  introduced by Hurtes, Boulou, Mitonneau, and Bois  [28], by Fairman, Morin and Oliver [29], and by Martin and Bois [30].  This  method i s suitable for the i n v e s t i g a t i o n of deep trapping levels i n high r e s i s t i v i t y e p i t a x i a l layers and semi-insulating GaAs substrates to which other deep trapping l e v e l spectroscopy methods [31] are not applicable. Several GaAs materials have been investigated using OTCS; for example, chromium doped Bridgman GaAs was  investigated by Hurtes [28], Devaeaud [32],  Fairman [1,29,33], and Martin [30], Chromium doped LEC GaAs was investigated by Fairman [1,29,33], whereas undoped LEC GaAs was K. Lowe [35], and W. Tang [36]. chromium doped substrates was  examined by Oliver [34],  GaAs grown by Vapor Phase Epitaxy (VPE)  on  investigated by Itoh [37], Fairman [1,29,33],  14  and Hurtes [28].  OTCS was  further used to search for deep levels i n other  materials such as, indium phosphide (InP)  [27], and lead iodide ( P b l ) 2  [38]  which i s an i n s u l a t o r . As a result of the application of OTCS to the study of GaAs substrate material, several s i g n i f i c a n t deep levels were observed. deep l e v e l EL2  For example, the  [39,40] has been observed by Martin [30], and Tang [36].  Chromium related deep levels which are responsible for the semi-insulating behaviour of chromium doped GaAs were detected investigators [1,28,29,32,33,37,41].  (as HL1) by several  Other deep levels due to impurities or  native defects [42] (and with d i s t r i b u t i o n affected by dislocations [43]) were also detected, and are believed to cause problems of variable threshold voltage  [44], hysteresis [45], frequency dependent transconductance [46], and  noise [47] i n GaAs ICs.  3.2  Theory of Optical Transient Current The theory of OTCS was  Spectroscopy  proposed by Hurtes et a l . [28] and then  developed by Martin et a l . [30].  It i s based on a depletion layer model  where the current i s determined by the charge transport across a depletion layer by electrons or holes released from traps.  Thus an electron trap ( i . e .  a centre which communicates only with the conduction band) may electron during i l l u m i n a t i o n and lose i t afterwards.  capture  an  The contribution which  the electron makes to the terminal current as i t crosses the depletion layer i s as i f this layer acted as an insulator separating the conducting semi-conducting region) from the electrodes.  (or  A hole trap behaves s i m i l a r l y .  Once gone the c a r r i e r s are not replaced because the concentration of  15  electrons and holes i n the reverse biased junction depletion region are low. Assuming that the p r o b a b i l i t y f that a trap i s occupied by an electron, the following rate equations are defined [48]:  rate of electron capture  = r a  = n N_ (1-f) V a T n n  rate of electron emission  = r, = N J e T* n  rate of hole capture  =r  rate of hole emission  = r , = N_(l-f) e a T p  F  e  c  = p N„, f V 0 T p p v  where n(p) i s the density of electrons (holes), V (V^) i s the thermal n  v e l o c i t y of electrons (holes), section, and  a n  ( ° p ) Is the electron (hole) capture cross  i s the t o t a l population of the trap.  Imposing the steady  state condition that r - r, = r - r , y i e l d s : a b c d J  f  ss  , (i v  +  e  + a V p P/)-! e + a V n p n n n  J  Given that the current during i l l u m i n a t i o n has reached a steady value and that at time t=0 the i l l u m i n a t i o n i s removed one finds:  e + o V ( p + 6 )  W> - t  1 +  oV  " p+ / vn" n(.' „'))-' ' (' j¥>. ' « 'n^p n n n +  e  0+ 0  1  ^  16  e + 6 V p f(°°) = f l + — — : — l"" p n n P  P |  1  e f1 +—I p  K  T T  -  1  , for no recapture i n the dark,  where n(p) is the equilibrium concentration i n the dark of electrons (holes) and 6 « 6 i s the excess number of electrons and holes generated by the n p light. The current i ( t ) i s given by r^ and r^, Kt)  = S-O. N ( e f ( t ) + e ( 1 - f ( t ) ) ) T  n  where A i s the area of the contact and W i s the width of the l a y e r .  Ai(t)  = i(t) - i ( » ) =  H_|_H.  N (e (f(t) - f(»))) T  n  From — = - f e + ( l - f ) e with solution dt n p  f ( t ) = f ( « ) + (f(0) - f ( » ) ) exp - t / t  where 1/t = e  n  + e , we obtain: p  e  e  + p  a  V P  n n  00  +  a  V (p+5 )  So  + e ((l-f(t))-(l-f(»))) p  17  Hurtes et a l . treated the case of large 6 ^ = 6 ^ during i l l u m i n a t i o n and no recapture  i n the dark to obtain:  Ai(t)  =a-A^N (e -e T  ) [(1  n  - ( l + ! i ) "1 ] e x p  n p  For electron traps where a /a » n p v  a la » p n  1 and e  Ai(t)  p  »  =  where T = l / e  1 and e  »  n  (-t/x )  e , and for hole traps where p' r  e , then the current reduces to: n  N  T  T"  1  expC-t/T)  for electron traps, and T = l / p f ° hole trap. e  n  P  r  For the case  of a boxcar's sampling whose output i s  AI(t) = A ( i (  t l  ) - i(t )) 2  where A_ i s the boxcar's amplification, the current difference i s : a  l(t)  = Ag  N  T  T"  1  (expC-^/x)  -  exp(-t /x)) 2  By d i f f e r e n t i a t i n g the current difference with respect to i and setting the r e s u l t to zero, the value of maximum x  can be solved: m  18  ^1  = 0 = (1-W  can be solved for once  expC-t^x^  and t  2  - (l-t /T ) 2  ex (-t /. )  n  P  2  m  are set; and when the boxcar's time constant  i s set to this value, a maximum A i ( t ) i s registered at a c h a r a c t e r i s t i c temperature T . ffl  Data on the a c t i v a t i o n energy AE and capture cross section a  can be obtained by Inserting the sets of c h a r a c t e r i s t i c temperatures for each time constant into the equation defining the time constant of traps:  T = (a y T )  - 1  exp(AE/kT)  where AE i s the difference from the conduction band to the trapping l e v e l energy for electron traps, and i s the difference between the trapping l e v e l and the valence band for hole traps, cm  S  -2  -1  k  - 2  y i s a constant defined as 2.28*10  for electron traps and 1.70*10  cm"  21  2  S"  1  k  -2  20  for hole traps.  While electron and hole traps give r i s e to positive peaks as the boxcar's output i s swept through a temperature range of 150K  to 400K,  nevertheless, negative peaks are seen i n various undoped LEC GaAs samples. They are obtained i f e > e n p 3  i n e q u a l i t i e s are reversed.  and (a V /a V ) > (e /e ), or i f both p p n n n p" v  /  v  The possible mechanism [49,50] i s that a centre  which gives a negative peak gives a steady state dark current due to i t s pumping out f i r s t an electron then a hole.  When the illumination ceases,  one  of these events occurs more slowly, and i f the traps are l e f t i n the condition which requires the slow process as the next step, the current w i l l i n i t i a l l y be low i . e . a negative peak i s produced.  19  3.3  Experimental  Procedure  Semi-insulating GaAs starting substrate materials investigated i n this work were obtained from Cominco Ltd. and B e l l Northern Research (BNR). A l l the substrates were LEC undoped wafers grown i n the <100> d i r e c t i o n . wafers labelled 344S10 (sheet r e s i s t i v i t y = 2.8*10  8  ohms/square, mobility =  6700 cm2/v sec, etch p i t s = 27000/cm ), 453S74 and 453S75 (sheet 2  = 3.1xl0  8  Three  resistivity  ohms/square, mobility = 6100 cm /v sec, etch pits = 39000/cm ) were 2  obtained from Cominco.  2  The f i r s t number i n the label represents the ingot  number, and the l e t t e r S (for seed) indicates that the last number stands f o r the s l i c e number i n the ingot counted from the seed end. Wafer #453S74 was reported (by BNR) to have been etched about 10 um using the following chemical etch:  Hj SO^ ^ O j ^ O  (4:1:1 by volume).  A single wafer from  Sumitomo was obtained which was grown at high pressure the same way as those from Cominco.  The wafer was labelled 400600-1, and r e s i s t i v i t y > 10 ohm.cm. 7  No data were obtained for mobility and etch p i t density. L i t t o n was obtained.  This was grown at low pressure.  A single wafer from  The wafer was taken  from boule 2052, s l i c e 2-9, and had the following s p e c i f i c a t i o n s : r e s i s t i v i t y = 1.37x10  s  density = 30000/cm . 2  ohm.cm, mobility = 2810 cnr^/v sec, and etch p i t A l l wafers were 2 inches i n diameter.  Two types of test devices f o r OTCS were used.  These were the planar  and the sandwich type (figure 3.1). In the planar type the electrodes were evaporated side by side on one surface, and i n the sandwich type they were evaporated on opposite surfaces.  The electrodes were [3] either chromium or  gold-germanium (Ge = 12%wt + Au=88%wt) unalloyed or alloyed at 450°C i n flowing nitrogen.  The chromium and unalloyed Au/Ge form a Schottky b a r r i e r .  F i g . 3.1 Geometry of (a) planar and (b) sandwich structures used in OTCS  21  The alloyed Au/Ge produces an n+ layer just under the contact (due to Ge). Some samples were thinned by grinding them i n a s i l i c o n carbide slurry on a glass plate followed by a chemical etch i n a solution of HgSO^+HgO2+H20 (4:1:1 by volume) for two minutes. The block diagram of the experimental setup i s shown i n figure  3.2.  The samples were mounted on a l i q u i d nitrogen cooled finger (KRYOSTIK model 1320H) i n an evacuated  l i g h t - t i g h t chamber as shown i n figure 3.3  contact probes for e l e c t r i c a l connections. heat the samples.  A copper-constantan  A power transistor was used to  thermocouple for temperature  measurement was mounted on the sample holder close to the device. pulses were provided by a GaAsP 670 nm LED. ±7 VDC)  was  with  Light  A fixed voltage bias ( t y p i c a l l y  applied to the sample, and the current was amplified with an EG&G  181 current sensitive amplifier followed by an EG&G dual gate boxcar.  The  output of the boxcar and of the thermocouple (through an amplifier) were recorded on an X-Y  3.4  recorder.  Results The main p r a c t i c a l question about the OTCS technique i s whether i t can  u s e f u l l y be employed to test the s u i t a b i l i t y of a particular batch of material for device f a b r i c a t i o n .  In addition to obtaining information about  deep trapping l e v e l s , the use of OTCS here i s further extended to investigate several effects on the DLTS spectrum, such as, the effects of chemical etch, surface damage, different test structures, varying contact geometry, and choice of electrode material.  ANATEK  IEC F33  MODEL  PULSE  25-20  GENERATOR  TEMPERATURE  TRIGGER Chambersample  LED  CZH  PAR 165,162 BOXCAR AVERAGER  PAR 161 CURRENT AMPLIFIER  Fig. 3.2  Block diagram of the OTCS setup  HP 70AAA X-Y RECORDER  Fig. 3.3  Vacuum chamber used in the OTCS experiment  24  3.4.1  OTCS Spectra of GaAs Substrates From Three Vendors Figure 3.4(a,b,c) shows the OTCS spectra of devices made on s l i c e s of  Cominco's, Sumitomo's, and Litton's GaAs respectively. The test samples used here were the planar type with chromium electrodes (length = 30 um, width = 600 um).  The spectrum of Cominco's GaAs was  similar to test devices tested  e a r l i e r [36] except i n the high temperature range where the magnitude of the negative peak was information on how known.  larger, and peak 1 appears much smaller i n magnitude.  No  t y p i c a l the GaAs substrates from Sumitomo and L i t t o n i s  The OTCS spectra of Cominco and Sumitomo GaAs substrates show the  same traps and with similar r e l a t i v e heights.  Both substrates were high  pressure LEC material.  The OTCS spectrum of the L i t t o n substrate, low  pressure grown LEC, was  considerably different i n that although i t shows a  similar set of peaks, the r e l a t i v e peak heights are d i f f e r e n t .  Figures  3.5(a,b) show the DLTS spectra of samples of both Cominco and Sumitomo before and after chemical etch i n a mixture of s u l f u r i c acid, water, and hydrogen peroxide  (4:1:1 by volume).  Though peaks 1 to 4 are unaffected by the  surface etch, peaks 5 to 8 were considerably reduced i n amplitude.  This  indicates that the unaffected peaks were due to deep levels present i n the bulk of the substrates, whereas the affected defects were enhanced by surface conditions such as damage, oxides, and chemical treatment. These results demonstrate that the OTCS technique  i s useful i n the investigation of surface  etching treatments much as are used i n the f a b r i c a t i o n of devices to remove damage or contaminated surfaces.  F i g . 3.4 OTCS spectra of SI undoped LEC GaAs from three vendors (Rate Window = 8.5msec)  26  (a) Cominco sample  15.  10.  (b). Sumitomo sample  F i g . 3.5 OTCS spectra of SI undoped LEC GaAs substrates from two vendors subjected to chemical etch (Rate Window = 8.5msec)  27  3.4.2  I d e n t i f i c a t i o n of the Peaks Table 3.1 shows activation energies and capture cross sections of a l l  the OTCS peaks found i n this work. the OTCS peaks. investigators.  Figure 3.6 shows the signature lines of  Table 3.2 shows the data on traps found by previous The peak labelled 1 was  i d e n t i f i e d from i t s signature l i n e i n  figure 3.6 by comparison with the well known compilation of data given by Martin et a l . [51] as being due to the main electron trap EL2.  This peak has  been reported many times using various forms of DLTS on conducting material but curiously not too often for semi-insulating material.  This i s presumably  because most authors have used Au+Ge electrodes and these, as opposed to chromium, give inconveniently high dark currents at the temperatures necessary to observe EL2. Peak 3 and the broad peak 4 have signature lines on either side of Martin et a l . ' s EL12. observed  According to Martin, Lang et a l . [52] have also  this l e v e l which i s probably due to an impurity.  Polarity change on  the sandwich type specimen [36] gave a greater peak for negative voltage on the illuminated electrode indicating an electron trap. The broad peak 5 i s often found with another peak 6 (for example figure 3.5a).  Those two peaks are closest to EL3 and EL4 respectively i n  Martin et a l . ' s DLTS data. as-grown MBE  They used capacitance DLTS [48] on  conducting  (molecular beam epitaxy) material to obtain the l e v e l  EL4.  Fairman et a l . [33] i d e n t i f i e d as EL4 a centre which gave one of the negative OTCS peaks which they observed slices.  two  i n Cr-doped semi-insulating Bridgman  Peak 7 i s found to closely resemble Martin et a l . ' s EL6, while peak  8 i s found to be a hole trap from p o l a r i t y measurement on thin samples [36].  29  Table 3.1  label  Activation energies, capture cross sections, and possible i d e n t i t i e s of the deep levels found using OTCS (Pl-8) i n semi-insulating, undoped, LEC GaAs.  a c t i v a t i o n energy (ev)  capture cross section (cm )  possible i d e n t i t y  2  io  - 1 2  PI  0.87  1.05 x  P2  0.65  3.00 x 1 0  P3  0.79  3.69 x 10~  P4  0.76  2.12 x 1 0  P5  0.59  3.46 x  io  - 1 2  EL3 ?  P6  0.52  2.90 x  io  - 1 3  EL4  P7  0.38  3.20 x  io  - 1 4  EL6  P8  0.32  2.50 x 1 0  - 1 2  EL2 negative peak  12  EL12 ?  - 1 2  ELI2 ?  - 1 3  HL6  Table 3.2  Deep levels i n SI GaAs reported i n the l i t e r a t u r e (as detected by OTCS (PITS)). VPE = vapour phase e x p i t a x i a l layer.  Authors  W  0  Identification  a(cm ) 2  Martin et a l .  0.9  2.2xl0  [30]  0.74  6.3xl0~  0.57  5.4*10  0.35  5.5xl0  0.34  2.7X10"  0.27  2.05* l O  Fairman et a l .  0.9  2X10"  [1,29,33]  0.83  2xl0  - 1 3  0.65(N)**  lxlO  - 1 3  0.60  lxlO"  0.51(n)**  lxlO  0.34  4X10 *  0.34  6xl0~  13  0.30  7xl0-  14  -1,+  14  15  -13  -15  14  - 1 4  HL1  Materials  Cr-doped Bridgman GaAs  EL2 EL3 EL 5 EL6 ELI 2  HLl  All*  HL10  Cr-doped LEC GaAs All*  1 2  EL3  Cr-doped LEC GaAs  - 1 2  EL4  Cr-doped Bridgman GaAs  EL6  All*  -11  VPE layer on Cr-doped GaAs HL12  Cr-doped LEC & Bridgman GaAs  31  0.26  2xl0  0.15  8X10  0.14  lxlO  Cr-doped Bridgman GaAs  - 1 2  Cr-doped LEC GaAs  -14  VPE layer on Cr-doped GaAs  - 1 6  **negatlve peak  *Cr-doped LEC & Bridgman GaAs and VPE layer on Cr-doped GaAs  Deveaud et a l .  0.87  1.3xl0  [32]  0.5  3xl0"  Itoh et a l .  0.98  1.3xlO  [37]  0.89  1.8xl0 "  HL1  0.75  2.7xl0-  EL2  0.62  1.5xl0  0.60  8.6xl0  0.42  Not Given  0.41  1.4xl0"  Rhee et a l .  0.90  2.1xl0  [27]  0.85  1.3xl0~  0.73  1.3xl0  0.17  3.9xl0"  0.83  Not Given  Oliver et a l . [34]  - 1 7  HL1  Cr-doped Bridgman GaAs  - 1 3  HL1  VPE(n-)  1 9  - 1  1 4  _11+  - 1 3  15  HL3 EL3  HL4  Cr-doped GaAs  - 1 2  13  -  HL1  - 1 7  2 2  HL10  undoped LEC GaAs grown with dry  B 0 2  3  32  0.65(N)  undoped LEC GaAs grown with wet B 0 2  0.57  3  undoped LEC GaAs  0.34 0.28 0.15  Hurtes et a l .  0.90  Not Given  HL1  [28]  high r e s i s t i v i t y VPE layer on Cr-doped Bridgman  0.81  EL2  n-VPE layer with high Cr-doped Bridgman  0.56  HL8  high r e s i s t i v i t y VPE buffer layer on Cr-doped Bridgman  0.54  EL3  n-VPE layer with high r e s i s t i v i t y buffer layer on Cr-doped Bridgman  0.41  HL4  n-VPE layer with high r e s i s t i v i t y buffer layer on Cr-doped Bridgman  0.32  EL6  both type of samples  33  The peak labelled 2 i s the negative peak and u n c r i t i c a l application of the equations for positive peaks gave a c t i v a t i o n energy 0.65 eV and capture cross section of 3 x l 0  - 1 5  cm . 2  Oliver et a l . [34] found using OTCS (their  PITS) a strong negative peak with planar specimens made from undoped LEC GaAs grown with wet boric oxide, but not i n s l i c e s grown with dry boric oxide. They found AE = 0.65 eV and suggested that this l e v e l was related to oxygen impurity and was partly responsible for the semi-insulating condition (since this was enhanced when wet boric oxide was used).  Fairman et a l . [33] using  vapor phase e p i t a x i a l layers and Cr-doped Horizontal Bridgman crystals obtained similar results with AE = 0.65 eV and a = 3><10"" cm . 13  2  Ogawa et a l .  [49] also using OTCS found a minor negative peak i n samples of unstated geometry using undoped LEC. In the previous paper by Itoh et a l . [37] using OTCS on Cr-doped Horizontal Bridgman s l i c e s no such negative peak or even low valley i s seen (their figure 4) using an ungated FET with one Au+Ge contact on n+ gate pad and the other on semi-insulating sustrate with or without a semi-insulating buffer layer.  3.4.3  Effects of Varying Sample Geometry on OTCS Spectra The effect of varying the contact spacing and width of the planar  samples was investigated.  Other authors have used varying spacings e.g. 500  um (Hurtes et a l . [53]), 5 um (Fairman et a l . [33]), 20 um (Itoh et a l . [37]) and a l i t t l e over 10 um (Rhee et a l . [41]).  Results of OTCS spectra for two  d i f f e r e n t widths W = 300 and 600 p,m and two d i f f e r e n t spacings L = 30 and 60 um are shown i n figures 3.7(a,b,c). With L = 60 um (Figure 3.7c) the right hand peak i s very pronounced where i t was a mere shoulder with L = 30 um.  34  T °K  P3  Fig.  3.7  OTCS s p e c t r a  ( R a t e Window =  of d i f f e r e n t  18.9msec)  planar  sample  geometri  35  (It l i e s between peak 1 (not appearing  at higher temperature) and peak 4.)  The negative peak was even less pronounced for L = 60 um than for L = 30 um, perhaps because the positive peak which was more pronounced i s close enough to i n t e r f e r e by giving a reduction i n the net increase i n current with time a f t e r i l l u m i n a t i o n . Peak 4 which i s the prominent peak on the two L = 30 devices, Is now a mere shoulder  on the 60 um device.  The difference i n the  spectra for different geometries can be associated with the different sampling regions due to the different geometry.  3.4.4  Effect of Varying the Electrode Material In the f i r s t work by Hurtes et a l . [28], alloyed Au+Ge electrodes were  used, whereas Martin et a l . [30] used chromium electrodes for his sandwich sample structures because they noted that gold-germanium electrodes gave more complicated  results.  In e a r l i e r work [35] i n this laboratory, alloyed  gold-germanium electrodes were used, and they were found to result i n too large dark currents which made OTCS measurements above room temperature very difficult.  In l a t e r work [36], chromium electrodes were used and resulted i n  reduced leakage currents. To investigate the difference i n electrode material and preparation on the OTCS spectrum, four samples were prepared with two types of electrode material, Cr and Au+Ge.  A l l devices were of planar type using a gateless  MESFET structure with L = 30 um, and W = 600 um.  Two samples with Cr and  Au+Ge contacts were alloyed for ten minutes at 450°C.  The OTCS spectra of  the four devices which were made from Cominco's GaAs material are shown i n Figure 3.8(a,b,c,d).  The range of the OTCS scans were limited to those  P5  T'K  (b) Au+Ge unalloyed electrodes  T  K  (d) Au+Ge alloyed electrodes  Fig. 3.8 OTCS spectra of samples prepared with d i f f e r e n t electrodes (Rate Window = 38.8msec)  37  obtained for Au+Ge scans.  The unalloyed Cr and Au+Ge electrodes gave the  same two broad peaks but with different amplitudes.  On a l l o y i n g the Cr  sample, the peak heights were a l l reduced, and the broad peak (combination of peaks 5 and 6) on the unalloyed sample, has now become d i s t i n c t with peak 5 dominating.  The Au+Ge specimen on a l l o y i n g gave also an OTCS spectrum with  some of the peaks such as, peak 6, reduced much i n amplitude.  In addition,  the two low temperature peaks 7 and 8 amplitudes were different i n both types of alloyed samples:  whereas peak 7 (electron trap) remained i n the Cr  alloyed sample, peak 8 (hole trap) remained i n the AuGe alloyed  samples.  The results indicate that the deep levels are affected by the high temperature  treatment upon a l l o y i n g , and that the type of electrode seems to  influence the r e s u l t s .  One might also expect unalloyed Au+Ge and chromium to  behave s i m i l a r l y , both acting as Schottky diodes. some authors [41] would presumably be s i m i l a r .  Au electrodes, used by  On a l l o y i n g the Au+Ge, the n+  layer due to Ge doping may be presumed to act as an e f f i c i e n t source of electrons.  The heat treatment of the chromium electrodes was done for  completeness and because chromium or related metal gates on MESFETs would quite normally receive the heat treatment applied to the Au+Ge source and drain electrodes. To help elucidate the effects of the nature of the contacts on the spectrum observed by OTCS, dark current vs. voltage curves were obtained using an HP 4145A semiconductor parameter analyzer.  Data for Au+Ge and Cr  electrodes before and after heat treatment at 450°C for 10 minutes are given i n figures 3.9(a,b,c,d) for various temperatures.  The current voltage curves  for Cr ( f i g . 3.9a and 3.9c) are consistent with back to back diodes with  38  Fig.  3.9  different  Current  vs. voltage  electrodes  for planar  specimens  with  39  poorly saturating reverse current. considerably. also appeared  On heat treatment the current decreased  Those for Au+Ge (figure 3.9b  and 3.9d) before heat  treatment  consistent with back to back poorly saturating diodes but  giving more current than Cr.  still  After heat treatment the Au+Ge, the current  voltage curves were f a i r l y linear up to 0.5 uA with 10 volts between electrodes separated by 60 um.  Arrhenius plots of log  used i n OTCS) vs. 1/T i n figure 3.10 and the activation energies.  a t  7 volts (as  show the r e l a t i v e values of the currents  The slope of the data for Au+Ge changed  s l i g h t l y on a l l o y i n g giving apparent a c t i v a t i o n energies of about 0.76 0.8 eV before and a f t e r . corresonding to 0.84  3.4.5  eV and  With chromium the slope changed from a value  eV to one giving 0.72  eV.  Effect of GaAs Surface Damage on the OTCS Spectrum Previous work by Tang [36] has revealed that the r e l a t i v e peak heights  changed for sandwich specimens than from planar ones.  In p a r t i c u l a r , he  found that the negative peak was much more accentuated for the sandwich than the planar sample.  The question that arises then i s whether the difference  between sandwich and planar specimens were due to the geometry or whether the f a b r i c a t i o n process affected the results (since Tang prepared his thin samples by abrading i t so that the surface was damaged).  To investigate  these factors, thin sandwich samples were prepared by mounting the wafer fragment on a s i l i c o n s l i c e with black wax and then abrading with a slurry of 400 grade carborundum.  The specimens were then removed from the s i l i c o n with  hot trichloroethylene and etched b r i e f l y i n the s u l f u r i c acid and hydrogen peroxide mixture used previously. Two  such thin sandwich samples were  2.8  3.0  3.2  3.4  1000/T F i g . 3.10  Signature l i n e plots for the data of figure 3.9  (Labels same as in figure 3.9)  41  prepared with the top electrode i n each case either on the abraded side or the polished side.  In additon, another two thick sandwich sructures ( i . e .  s t a r t i n g wafer thickness = 450 um) were prepared where one of them was a token grind, while the other merely degreased.  given  The results of the OTCS  spectra are shown i n figure 3.11(a,b,c,d) for each of the above stated cases. In the case of the thin sandwich structures (figure 3.11a sample where the abraded side was  and 3.11b), for the  on top, the positive peaks were somewhat  attenuated whereas the negative peak increased somewhat i n amplitude  compared  to the sample with the polished side on top.  This effect i s attributed to  grinding which was followed by surface etch.  To demonstrate the effect of  surface abrasion only (no etch), figure 3 . l i d shows the spectrum of the thick sandwich sample which was given a token grind. sandwich structure which was merely degreased  Compared to the thick (figure 3.11c), the positive  peaks were s l i g h t l y attenuated whereas the negative peak has increased s i g n i f i c a n t l y i n magnitude.  To v e r i f y that the negative peak was affected by  surface damage, and to investigate separately the effect of surface etch on the negative peak, a planar specimen was  prepared this time.  To start with,  the spectrum of the sample, as i s , ( i . e . with no etching or grinding) was recorded as shown i n figure 3.12a.  The same sample was  then etched by about  1 um using a mixture of s u l f u r i c acid, hydrogen peroxide, and water (4:1:1) by volume).  The OTCS spectrum indicated no difference (shown i n c i r c l e s i n  figure 3.12a). slurry.  The sample was  then l i g h t l y abraded using a carborundum  The negative peak, figure 3.12b, was  s i g n i f i c a n t l y accentuated.  The  sample showed almost the same s t a r t i n g OTCS spectrum, figure 3.12c, after the sample was  etched.  From these findings i t can be concluded that the negative  P2  (b) abraded side on top, thickness = 120um  (d) abraded side on top, thickness = 500um  Fig. 3.11 OTCS spectra of sandwich structures with a negative bias on the top illuminated electrode (Rate Window = 75.5msec)  £  43  5  F i g . 3.12  OTCS spectra of a planar structure (a) before  and after chemical etch (b) after l i g h t abrasion (c) aft< chemical etch (Rate Window = 75.5msec)  44  peak i s associated with the damage done to GaAs by the abrasion  3.5  process.  Summary From the above study, i t was  shown that the OTCS technique i s a useful  tool for the evaluation of GaAs material.  The OTCS spectra were shown to be  d i f f e r e n t for high and low pressure LEC grown GaAs.  Some of the peaks were  found to be dependent on the surface condition, as i t was concentration of some of the deep levels were attenuated surface layer was  removed.  shown that the after the top  The nature of the OTCS spectrum was  found to be  influenced by the electrodes, sample geometry, and f a b r i c a t i o n method. F i n a l l y , surface damage was  shown to affect the negative peak.  Before this chapter i s concluded, i t i s useful to point out that the theory of OTCS based on the depletion layer model of Hurtes [28] i n section 3.2) may  (described  not be t o t a l l y applicable for the study of transients.  For example i n the case of transients r e s u l t i n g from a sandwich structure, the depletion layer w i l l be confined to a small depth below the surface, while the bulk remains undepleted.  Other models are now  available [50] which  provide for possible alternative description of the observed transients.  45  CHAPTER 4  INVESTIGATION OF PROCESS-INDUCED DEEP LEVELS IN ION IMPLANTED MESFETs  4.1  Introduction Despite the recent advances which have been made i n the f i e l d of  MESFETs IC technology, there are s t i l l many problems concerning  the s t a b i l i t y  of such devices due to the presence of deep l e v e l defects and impurities both those i n i t i a l l y present f a b r i c a t i o n process.  i n the substrate material and those induced by  It has been widely reported  the  [5,54-59] that traps i n the  MESFET channel and i n p a r t i c u l a r those at the interface of the channel and the semi-insulating substrate can cause such effects as looping i n the drain I-V c h a r a c t e r i s t i c s , low transconductance at saturation, low breakdown, low power gain, and large noise figures.  drain-source  Those effects were found  i n p a r t i c u l a r for active layers made by e p i t a x i a l growth over chromium doped gallium arsenide substrates because chromium tended to react with the active layer and form hole traps which contribute to the formation of an interface space charge region which i n turn a f f e c t the channel width [59].  To i s o l a t e  the active layer from the substrate, high purity e p i t a x i a l buffer layers were used to keep the deep levels i n the substrate from d i f f u s i n g into the MESFET channel.  However, i t was  found [60] that for a l l buffer layer  thicknesses  (1-3 n m ) , chromium, copper, and iron s t i l l were able to d i f f u s e and resulted i n a large number of deep levels at the active layer and buffer  (A/B)  interface. Some of the problems with deep trapping levels i n e p i t a x i a l layers and  46  at the A/B  interface are no longer present i n the case of ion implantation i n  undoped LEC GaAs substrates. technology  Nevertheless, the problems of the newer  s t i l l include those due to the presence of the many impurities  [33,8] i n undoped LEC GaAs substrates, and due to defects either present i n the s t a r t i n g material or induced by the process steps.  Process-induced  defects i n MESFET channels arise from several factors:  (1) i r r a d i a t i o n  damage due to s i l i c o n ion implantation (used as n-type dopants), and whether the implantation was  done d i r e c t l y into the surface or through a thin  d i e l e c t r i c f i l m ; (2) the high temperature annealing stage required to remove the implantation damage and allow s i l i c o n to reach vacant gallium s i t e s ; the type of encapsulant  (3)  used; and (4) the chemical treatment of the surface.  Of those factors, the f i r s t factor i s important,  since implants  through  s i l i c o n dioxide or s i l i c o n n i t r i d e can introduce unwanted atoms such as oxygen and nitrogen into the active layer by knock-on mechanisms [61] Inducing serious defects.  Also, the type of encapsulant  which i s used to  preserve the GaAs stoichiometry during high temperature anneal i s important. Studies have shown [62] that the implanted  atoms redistribute by d i f f u s i o n  more with a s i l i c o n dioxide than a s i l i c o n n i t r i d e cap. dioxide encapsulant  Also, the s i l i c o n  does not preserve the substrates stoichiometry as well as  s i l i c o n n i t r i d e since i t i s known that gallium can diffuse through the s i l i c o n dioxide.  Problems of enhanced d i f f u s i o n of defects are also caused  by the encapsulants  as a result of stresses due to thermal expansion mismatch  between the d i e l e c t r i c cap and GaAs. There i s an extensive l i t e r a t u r e on electron and hole deep levels i n GaAs [63] and on their effects on device c h a r a c t e r i s t i c s .  Recent papers  47  s p e c i f i c a l l y on deep levels i n ion implanted  undoped semi-insulating GaAs  include Sriram et a l . [64,65], Rhee et a l . [41,66] and Hickmott [45]. this chapter, deep levels i n s i l i c o n implanted  In  MESFETS fabricated by four  procedures are investigated by channel current DLTS.  The four cases include  e f f e c t s of implants d i r e c t l y into GaAs and through s i l i c o n nitrde f i l m , and also effects of three types of encapsulants.  4.2  P r i n c i p l e of Channel Current DLTS Channel current DLTS i s a technique which allows the investigation of  the deep l e v e l traps i n ion implanted i l l u s t r a t e d i n figure 4.1.  MESFET channels.  The p r i n c i p l e i s  A small bias (50 mV DC) i s applied between the  drain and source so that the FET operates i n the linear region.  A reverse  bias voltage i s placed on the gate such that the channel i s nearly off.  pinched  Pulses of voltage taking the gate to near zero bias are applied.  The  basic idea i s that majority c a r r i e r traps are f i l l e d by c a r r i e r s which are allowed  to enter the previously depleted channel during the positive going  voltage pulse.  When the gate voltage returns to i t s more negative value the  negative charge due to the trapped electrons p a r t i a l l y compensates the positive space charge density i n the depleted region.  To maintain the fixed  voltage drop across the region i t must therefore become i n i t i a l l y wider than before.  The channel i s therefore narrowed and the drain current i s l e s s .  As  the occupancy returns to normal the drain current increases (with the time constant  depopulation  emission process) as i l l u s t r a t e d i n figure 4.2.  Hole  traps give the reverse sign of effect (the hole trap occupancy can be changed because the quasi Fermi l e v e l f o r holes communicates with the gate Fermi  DLTS detection circuitry  Current Amplifier Voltage pulse supply  DS  H'lii D |^zero bias depletion widthj|w  ion implanted active channel  Q  \ Interface ^•depletion layers  Semi-insulating GaAs  F i g . 4.1  Schematic diagram showing the channel current DLTS measurement system 00  V (t) gate  voltage  V1 t ime i  (t) DS 4  V.  11 (t)  (a) electron trap  I3(t) I2(t)  >  t ime  (b) hole trap present  time  Fig. 4.2  Transient responses of the drain current to an applied gate voltage  50  level). The depletion width which i s modulated by the traps i s obtained for any time t after the lapse of the zero bias pulse [64] as:  AW(t)  =  -  W(t)  N A W ( t )  =  "2 W  N oo  I ( n ' oo  for an electron trap.  + A W ( t )  -  "  W 2  0  )  ^ P ^ n  The corresponding  0  (  ,  1  A  )  expression for a hole trap:  2W N I C ~ ~^c) ^ " V ^  <' >  W2  =  4  N on  where N  W 2  4 1B  *  D i m  is the t o t a l concentration of the trap, N  Q  1^ i s the donor l e v e l  T density at steady state depletion width, W  q  and  are the depletion widths  at zero gate and steady state depletion widths respectively. The channel current for an arbitrary doping p r o f i l e i s :  k I  D S  = /  (q u(x) n(x)) ( Z / L ) V  DS  dx  (4.2)  where u(x) i s the d r i f t mobility i n the channel, n(x) i s the free c a r r i e r concentration, Z i s the channel width, L i s the e f f e c t i v e channel length, and k i s the channel thickness.  For a small change i n depletion width,  (4.2)  51  becomes:  AI  D  = (q u ( x ) n ( x ) ) ( z / L ) V  S  This expression equation  f o r an electron  ,  expression  (q  DS  The c u r r e n t  =  (  2W  =  The c o r r e s p o n d i n g  A I  (4.3)  u(x))|  —-2W  to obtain the transient  current  trap:  w  DS  AW  c a n be combined w i t h ( 4 . 1 A )  - ( q u(x))l «, A I  D g  Z / L  ,  > DS V  N  , '  T ( - "  f o r a hole  W  W  ,  ,  o ) ^ " V ^  (  4  '  4  A  )  trap:  W c o  <  Z/L  > DS V  N  T ^  ~ 0 W  i s s a m p l e d a t two t i m e i n s t a n t s ,  )^ " V ^ t^ a n d t  2  <' > 4 4B  by the boxcar  averager  which gives an output:  v (t) 0  where  - A R( i ^ C t i ) - I B  D S  (t ))  Ag i s the a m p l i f i c a t i o n of the boxcar,  conversion equation  factor  (4.4A),  i n the current the output  (4.5)  2  amplifier.  current  becomes:  and R i s the c u r r e n t Utilizing  to  voltage  the expressions i n  52  (q u(x)) | gj - (Z/L)V W<x  v (t) - " A R 0  B  2W  DS  N  T  (UJ  - W 2). q  00  (exp(-t /-c)-exp(-t /T)  (A.6)  2  1  The information about the traps i s obtained by the DLTS c i r c u i t r y as i n section 3.2.  The trap a c t i v a t i o n energy and capture cross section are  obtained by p l o t t i n g ( T T ) vs. ( 1 0 0 0 / T ) , where T 2  m  m  ffl  temperature of the peak i n the DLTS spectrum.  i s the c h a r a c t e r i s t i c  The boxcar rate window i n the  case of channel current DLTS i s obtained by d i f f e r e n t i a t i n g ( 4 . 6 ) with respect to x, setting the result to zero, and solving for x^:  T  m  =  1 / e  n  =  ( t  l  " *2>  1  Mt-i/t^)  (4.7)  Unlike OTCS, positive peaks In channel DLTS correspond negative peaks indicate electron traps.  to hole traps, while  This technique i s therefore  unambiguous with respect to the type of the deep l e v e l .  Also, In contrast to  OTCS where the concentration of the traps are d i f f i c u l t to obtain because not a l l the levels are occupied during o p t i c a l e x c i t a t i o n , the concentration of traps i n channel current DLTS can be estimated  since during e l e c t r i c a l  e x c i t a t i o n a l l the deep levels i n the sampled region undergo p e r i o d i c a l f i l l i n g and emptying. i n equation  4.3  The concentration can be estimated by solving f o r N^,  (4.6).  Experimental  Procedure  Four sets of long channel devices ("Fat FETs") were used for channel  53  current DLTS, each fabricated using a different procedure.  Substrates from  the following ingots of Cominco were used:  #175  #43,  #51,  #123,  and #344.  The f i r s t set of fat FETs were fabricated by Lowe [35] with a gate length of 100 um and a gate width of 200 um. 2 8  The channel was  Si at 100 keV d i r e c t l y into the GaAs surface.  implated with 3*10  12  cm  -3  A 600 nm RF sputtered  s i l i c o n dioxide mask was used to block the s i l i c o n implant where i s o l a t i o n was needed.  The implant damage was furnace annealed at 850°C for 20 minutes  using a 170 nm RF sputtered s i l i c o n dioxide as an encapsulant. The second set of fat FET's (L = 120 um, W = 180 um) were implanted with 3.38*10  cm  12  -2  using  silicon nitride film. implantation.  2 8  S i at 125 keV through a 40 nm layer of PECVD  A Photoresist mask was used for selective ion  The d i e l e c t r i c f i l m was  Multiversion machine with NHg  l a i d down i n a Plasmatherm Inc.  and S i t ^ i n He.  The f i l m was  thickened to 80  nm before furnace anneal at 850°C for 25 minutes. The t h i r d set of MESFETs had i d e n t i c a l geometry to that of set 2. channel was implanted with with a dose of 2.25x10*  2  2 8  Si d i r e c t l y into the GaAs surface at 100 keV  cm . -2  The  The devices were annealed i d e n t i c a l l y to set  2, using an 80 nm PECVD s i l i c o n n i t r i d e f i l m s . The fourth and f i n a l set of devices were supplied by A l l i e d Bendix Aerospace Corporation. with 3 x l 0 was  1 2  cm  -2  of  2 9  The f a t FETs (L = 200 um, W = 200 um) were implanted  Si at 60 keV d i r e c t l y into the GaAs surface.  The wafer  furnace annealed at 850°C for 15 minutes under 250 nm PECVD s i l i c o n  dioxide.  The GaAs was reported to have been obtained from Cominco Ltd.  The source and drain of the a l l the devices were Au+Ge alloyed at 450°C, while the gates were aluminum.  The experimental setup for channel  54  current DLTS shown i n figure 4.3 i s similar to the OTCS setup described previously.  4.4  Results Channel current DLTS spectra are given i n figures 4.4-4.7 for MESFETs  made using the four processes described above.  Arrhenius plots are given i n  figures 4.8 and 4.9 for the channel current DLTS peaks.  Table 4.1 summarizes  the DLTS data. The two sets of devi ces made with RF sputtered and PECVD s i l i c o n dioxide cap (processes I and IV respectively) each gave four peaks corresponding to four defects.  The resulting traps were d i f f e r e n t .  In  process IV, two of the peaks were hole traps (T2 and T4), while the other two were electron traps ( T l and T3).  Since none of them were found i n the  starting material by OTCS (table 3.1) the four traps were thus l i k e l y to be process induced.  The two hole traps may have originated from metal impurity  d i f f u s i o n from the substrate into the active layer during high  temperature  anneal. In process I, with an RF sputtered s i l i c o n dioxide cap, the peaks were a l l electron traps.  Two of these peaks, Ql and Q2 are the same as the two  peaks P4 and P5 found i n the s t a r t i n g material by OTCS (table 3.1), and they are probably to be i d e n t i f i e d on the basis of a c t i v a t i o n energy with EL12  and  EL3 respectively found by Martin et a l . [48].  Q4  The other two peaks Q3 and  were not observed i n the starting material and are, therefore, process-induced defects. For devices implanted d i r e c t l y into GaAs and annealed under PECVD  out  VOLTAGE SUPPLY  PULSE Isyry trig GENERATOR  BOXCAR  out chamber-T sample  X-Y PLOTTER  I I  I  thermocouple —  AMPLI FI ER  Fig. 4.3  Block diagram of channel current DLTS system  in  4.4  Channel current DLTS spectrum for MESFETs prepared using  process  -50  ;  4.7  C h a n n e l c u r r e n t DLTS s p e c t r u m  f o r MESFETs p r e p a r e d  using  process  IV  Os  Fig. 4.8  Signature line plots for DLTS data of processes I-III  o  EL12 HL3 EL3 / / /  HL1 EL2 -.THIS  WORK  / '  / ' /  EL 4 / /  EL6 /  /  - MARTIN et a l / / / / / / / ' /  /  /  / /  / /  / / /  T4 T3 T2 T1  2 1000/T  Fig.  4.9  Signature  line  plots  f o r DLTS d a t a  o f p r o c e s s IV  HL6 / /  62  Table 4.1  label  Activation energies, capture cross sections, and possible i d e n t i t i e s of the deep levels found by channel current DLTS i n MESFETs fabricated by four processes (Ql-4,Rl,S1,T1-T4). a c t i v a t i o n energy (ev)  capture cross section (cm )  possible i d e n t i t y  2  Ql  0.74  2.67 x 1 0  P4 and EL12  Q2  0.57  4.47 x 10"  Q3  0.28  1.66 x i o  -  Q4  0.24  1.45 x 1 0  - 1 6  RI  0.85  4.30 x i o  -  1  3  SI  0.74  2.10 x i o  -  1  3  Tl  0.69  2.3  1 2  T2  0.57  3.44 x 1 0  T3  0.78  1.015x I O "  T4  0.911  1.55 x l O  - 1 3  x lO"  P5 and EL3  12  1  - 1 7  1 3  - 1 3  6  -  PI and EL2  electron trap hole trap electron trap hole trap  63  s i l i c o n n i t r i d e cap (process III) only one peak, SI (AE = 0.74 found.  eV), was  This peak was observed i n the starting material by OTCS as P4 and i s  believed to be EL12.  For devices implanted through PECVD s i l i c o n n i t r i d e  (process II) only RI (AE = 0.85  eV) was observed.  This peak was found by  OTCS as PI and i s Martin et a l . ' s [48] EL2. Relating these results to previous work (table 4.2), Sriram et a l . [64,65] used devices with s i l i c o n implanted d i r e c t l y into semi-insulating undoped LEC GaAs at doses of 2 to 5.5*10  12  cm  -2  at 100 to 325 keV and  annealed at 860°C under "phosphorus s i l i c a t e " glass.  Using channel current  DLTS, they found s i x levels of which three were process-induced. defect A i s probably our l e v e l Q4.  Their  Rhee and Bhattacharya [41] implanted  s i l i c o n d i r e c t l y into Cr-doped semi-insulating LEC GaAs at does of 1 0 10  13  cm  -2  at 100 keV and annealed under s i l o x cap.  12  and  They found three electron  traps of which one was present i n their starting material.  In a further  paper [66] they found two dominant levels (0.52 eV electron trap and an  0.15  eV hole trap) i n d i r e c t l y implanted material, these centres being absent on implantation through Silox.  Jervis et a l . [67] compared the traps produced  by implantation (a) direct and (b) through s i l i c o n n i t r i d e into e p i t a x i a l and chromium doped semi-insulating wafers (probably Bridgman). under s i l i c o n n i t r i d e . o p t i c a l excitation,  They annealed  Using capacitance DLTS with both e l e c t r i c a l and  they found an increase i n EL2 on implanting through  silicon nitride. As regards a mechanism to account for the extra EL2 found i n devices made by process I I , i t i s suggested that when implantation i s done through s i l i c o n n i t r i d e , knocked-on nitrogen atoms [68] compete with displaced  64  Table 4.2  label  Some deep levels i n s i l i c o n implanted literature.  a c t i v a t i o n energy (ev)  GaAs reported i n the  capture cross section (cm )  possible identity (reference)  2  A  0.23  1.90 x 1 0  B  0.22  1.17 x 10~  C  0.53  1.60 x l O "  D  0.85  1.00 x l O  E  0.64  5.90 x l O "  F  0.75  1.50  A  0.52 ± 0.01  (1.20-1.60) x 10~  B  0.17 ± 0.01  (5.20-5.50) x l o ~  C  0.21  3.10 x 1 0  EB2  0.83  2.20 x 1 0  EB3  0.90  3.00 x 1 0  EB4  0.71  8.30 x 1 0  EB7  0.30  1.70 x l O "  EB6  0.41  2.60 x 1 0  x  lQ~  unknown [64]  - 1 7  EL14  15  EL4  1 2  New  - 9  Cr complex  1 4  EL2  lk  18  [41]  2 3  -21  - 1 3  - 1 1  - 1 3  1 4  - 1 3  EL2 [67]  65  arsenic atoms for vacant arsenic s i t e s (since both nitrogen and arsenic belong to group 5 elements).  The pre-empted arsenic atoms could adopt vacant  arsenic sites to produce As which i s , or i s associated with, E L 2 . With s i l i c o n dioxide as encapsulant,  the loss of gallium i s to be  expected to have some effect on the type of defects produced.  Perhaps  occupation of the vacant gallium s i t e s by impurities from the s i l i c o n dioxide f i l m or from metal traces i n the substrate i s responsible for the processinduced hole and electron traps.  One of the traps, P4 or E L 1 2 , i s probably  associated to gallium vacancy concentration since i t was present i n processes I and III (under s i l i c o n dioxide and s i l i c o n nitrde caps) but not i n process II (implanted  through s i l i c o n n i t r i d e ) where gallium vacancy was  reduced due  to the formation of the a n t i - s i t e defect. To summarize the main r e s u l t s : 1.  The number and nature of deep levels are influenced by the type of  the annealing cap.  Annealing with a s i l i c o n n i t r i d e cap i s observed to  remove a l l but one defect i n the s t a r t i n g substrate and does not cause process-induced  levels.  Annealing under a s i l i c o n dioxide cap leads to the  formation of several process-induced  traps which give detrimental effects on  the devices c h a r a c t e r i s t i c s . 2.  For a d i f f e r e n t encapsulant,  for example, RF sputtered and PECVD  s i l i c o n dioxide, the resulting number and nature of deep levels are different. 3.  For implantation through s i l i c o n n i t r i d e , the channel was  contain a larger concentration of E L 2 .  found to  This trap Is undesirable i n MESFETs  since i t can cause d r i f t i n the DC c h a r a c t e r i s t i c s .  66  CHAPTER 5  INFLUENCE OF VARIOUS LEC UNDOPED GaAs SUBSTRATES ON THE CHARACTERISTICS OF ION IMPLANTED AND ANNEALED ACTIVE LAYERS  5.1  Introduction With the emergence of advanced GaAs integrated c i r c u i t  technologies,  stringent demands are placed on the GaAs material i n order to make high quality devices reproducibly.  The advantages of ion implantation into bulk  material over the use of e p i t a x i a l technology l i e i n the a b i l i t y to form planar device structures e a s i l y by s e l e c t i v e doping [69], precise t a i l o r i n g of the implant p r o f i l e [70], and cost effectiveness.  However, the influence  of the bulk grown substrate material on the properties and c h a r a c t e r i s t i c s of the ion implanted and annealed active layers remains a major concern. It i s known that GaAs substrates can influence the active layer performance i n several ways, such as:  (1) variations i n a c t i v a t i o n  e f f i c i e n c y , mobility, and doping p r o f i l e s which i n turn produce variations i n pinchoff voltage and drain current  [71-75]; (2) degraded d r i f t mobility at  the active layer-substrate interface due to traps caused by impurities [15] has adverse effects on transconductance and noise figure; (3) backgating (and sidegating) e f f e c t [72,76] can severely l i m i t c i r c u i t performance; (4) problems with surface conversion improper compensation [77].  and thermal i n s t a b i l i t y of GaAs are due to  These substrate-related problems have prompted  the use of q u a l i f i c a t i o n tests or pre-screening implantation.  of substrates for ion  67  Suppliers of substrate materials check their material through measurement of substrate r e s i s t i v i t y , Hall mobility, and thermal s t a b i l i t y , and quality control checks involving device fabrication for GaAs substrates are largely performed by the device manufacturers [78].  Typical  q u a l i f i c a t i o n tests of GaAs substrates require [33] (1) reproducibly high resistance substrates which can withstand high temperature (850°C) anneal without  surface conversion; (2) low background doping compared to shallow  donor and acceptor impurities; (3) high e l e c t r i c a l a c t i v a t i o n and  carrier  mobility with abrupt doping p r o f i l e s for bare surface n-type implants; (4) low dislocation and defect d e n s i t i e s . One  and  test [70] which has been used  to qualify substrates involves ion implantation with an inert gas such as argon to simulate damage caused by n-type implants, followed by high temperature capped anneal; the substrate q u a l i f i e s i f i t remains semi-insulating.  Other tests involve measurement of the electron  concentration p r o f i l e after ion implantation and annealing of s i l i c o n and checking that the doping p r o f i l e i s similar to that of a control sample. These tests aim at reproducibly obtaining high quality active layers with the following properties [79,15]: 1.  reproducible and well controlled c a r r i e r p r o f i l e s ,  2.  high undepleted  3.  high d r i f t mobility (> 4500 cm /v sec) which stays constant or  c a r r i e r concentration, 2  rises through the channel-substrate i n t e r f a c e , 4.  controlled drain currents and pinchoff voltages with minimal nonuniformities, and  5.  stable and high resistance substrates after high temperature  68  processing. Undoped LEC bulk grown GaAs substrates are preferred for fabrication over Bridgman or Cr-doped material because the l a t t e r tends to exhibit poor performance i n active layer properties such as lower a c t i v a t i o n and mobility, drain current and threshold voltage nonuniformity, and thermal associated with chromium i n the substrates  [72,74,77,79].  conversion  With LEC undoped  GaAs substrates, improvement of r e p r o d u c i b i l i t y of active layer properties compared to chromium doped LEC GaAs has been reported  [71] as uniformity from  ingot to ingot has been markedly improved and the problem of surface conversion  has been eliminated.  However, i t i s expected that undoped LEC  GaAs material from d i f f e r e n t sources should exhibit differences i n q u a l i t y and performance.  Also some suppliers may  change their growth procedures to  obtain semi-insulating wafers and to pass q u a l i f y i n g t e s t s . It i s the objective of this chapter to investigate undoped LEC GaAs substrates:  (1) from d i f f e r e n t suppliers; (2) for differences between low  pressure and high pressure eras from one supplier.  grown material; and  (3) from recent and  In addition, a substrate Is also analyzed  earlier which did  not pass the q u a l i f i c a t i o n tests of a device manufactuer, but did pass the screening test of the supplier.  The following parameters are sought to  charcterize GaAs substrates for this investigation: 1.  sheet resistance, H a l l mobility, a c t i v a t i o n ,  2.  doping p r o f i l e , undepleted c a r r i e r concentration, and zero gate bias depletion width,  3.  d r i f t mobility,  4.  deep levels i n MESFETs channel, and  69  5.  5.2  backgating  effect.  Description of the Diagnostic Test Pattern The test pattern which i s shown i n figure 5.1 was  Tarr [80] based on that reported by Immorlica [81].  developed by  N.G.  Occupying the centre of  the pattern i s a Van der Pauw cross used for measuring the n-implant sheet resistance, H a l l mobility, and undepleted  c a r r i e r concentration.  A similar  cross i s provided i n the top l e f t hand side to allow similar measurements for the heavily doped n -implant used for ohmic contacts. +  A Schottky diode on  the lower right hand corner Is used to measure implant p r o f i l e s . also four MESFETs with different dimensions, labelled T1-T4. fat FET with a gate length far greater than source-gate spacings; channel. DLTS.  and  There are  MESFET T3 i s a drain-gate  i t i s used to p r o f i l e the d r i f t mobility i n the ion implanted MESFET T4 i s used for investigating deep levels by channel current  F i n a l l y , MESFETs T l and T2 are used primarily to determine the drain  current and threshold voltage v a r i a t i o n s .  5.3  Diagnostic Pattern Fabrication Fabrication was  GaAs.  Two  carried out on five substrate s l i c e s of undoped LEC  of the s l i c e s B, and C from Sumitomo (high pressure LEC GaAs) and  L i t t o n (low pressure LEC GaAs) respectively were obtained from 2" wafers. The remaining  three s l i c e s were obtained from 3" wafers supplied by Cominco  (high pressure grown):  Substrate A-686 i s a recent wafer grown i n  1985,  substrate B-727 i s also a recent wafer which f a i l e d the screening tests of a device manufacturer, and f i n a l l y substrate A-184  i s from an e a r l i e r era grown  T1  (I0x500um)  T3 ( 100x200um)  T2  Schottky  (I0x200um)  diode  ( I00x4l0um) o  Fig.  5.1  The d i a g n o s t i c  test  pattern  71  in 1982.  A l l s l i c e s were fabricated i d e n t i c a l l y so that different substrate  effects can be observed.  Ten to twelve test patterns (each 5 mm x 5 mm)  fabricated on each s l i c e (20 mm x 15 mm)  are  to average the various  measurements. The f i r s t step i n f a b r i c a t i o n was to degrease for five minutes i n b o i l i n g trichloroethylene, acetone, and isopropanol.  This was followed with  four minutes cleaning i n a 1% Alconox solution (monosodium dihydrogen phosphate).  Afterwards the s l i c e s were rinsed for 15 seconds i n de-ionized  (DI) water.  The surface was then etched one micron by dipping i n a mixture  of ammonium hydroxide, hydrogen perioxide, DI water (5:2:240 by volume) f o r f i v e minutes.  After r i n s i n g the s l i c e s for 15 seconds i n DI water, the  s l i c e s were bathed for two minutes i n b o i l i n g isopropanol.  At this stage  (figure 5.2a), the s l i c e s were a l l ready for processing. In the next f a b r i c a t i o n stage, r e g i s t r a t i o n marks were opened i n the slices,  Photoresist (Shipley AZ1450J) was spun to a uniform thickness of 1.5  microns, baked for 30 minutes at 65°C, and exposed to UV l i g h t through the appropriate mask for 1.5 minutes.  The r e g i s t r a t i o n marks were then etched  1000A with the ammonium hydroxide solution used above for 30 seconds 5.2b).  (figure  With the photoresist removed by b o i l i n g acetone, the s l i c e s were  s i m i l a r l y patterned using an n-implant mask.  Windows were opened through the  photoresist to allow ion implantation d i r e c t l y into the GaAs surface (figure 5.2c).  The samples were then a l l ion implanted with  2.2xl0 /cm 12  2  at 100 keV.  2 8  S i using a dose of  Afterwards, the photoresist was removed by dipping  the s l i c e s i n acetone; the stubborn remainder was removed by oxygen plasma i n the Plasmtherm system.  Preparing the samples for high temperature anneal  72  SI GaAs  (A)  Wafer pre-clean  '/// SI GaAs  (B)  Registration mark etch  SI GaAs  (C)  F i g . 5.2  Opening windows for ion-implantation  Fabrication sequence for the diagnostic test pattern  N-CHANNEL SI GaAs  (D)  / APR  Encapsulation and annealing  PR /  / j  K-CHANNEL  j  SI GaAs  (E)  Opening windows for gold-germanium contacts  (F)  Evaporation of gold germanium  Ar/ j  j  N-CHANNEL SI GaAs  (G)  L i f t o f f of photo-resist, and alloying  ' / / /// j  '///// N-CHANNEL SI GaAs  (H)  evaporation of aluminium.  F i g . 5.2 cont'd  |  75  consisted of degreasing the s l i c e s , laying down a 900A to lOOOA f i l m of PECVD s i l i c o n n i t r i d e on both surfaces of the wafer (figure 5.2d) a Mini Brute s i l i c a tube furnace at 825°C for 25 minutes. the top s i l i c o n n i t r i d e f i l m was system.  The n -implant +  and annealing i n After the anneal,  removed by freon plasma i n the Plasmatherm  was here foregone  to simplify the processing steps.  In the next step (figure 5.2e), the s l i c e s were degreased and patterned with the ohmic contacts mask. to a thickness of 2000A (figure 5.2f). acetone to get metal l i f t o f f  Au+Ge (88%Au+12%Ge) was This was  (figure 5.2g)  435°C i n the Mini Brute furnace.  evaporated  followed with b o i l i n g i n  and alloying for two minutes at  In the f i n a l step (figure 5.2h), the s l i c e s  were patterned with the Schottky gate metal mask, and 2000A of aluminum was evaporated  into the s l i c e s and then followed by l i f t o f f to form Schottky  gate  contacts.  5.4  Measurements on the Diagnostic Test Pattern A l l the measurements carried out here were non-destructive and meant  to give information on the properties of the ion implanted active layers.  and  annealed  A useful tool that f a c i l i t a t e d a number of measurements i s  the HP 4145A Semiconductor Parameter Analyzer.  Measurements of MESFETs  c h a r a c t e r i s t i c s were programmed into the i n t e r n a l computer.  In this manner,  measurement of I , , or drain current at zero gate voltage was obtained from ass I  DS  vs. V  GS  .  Measurement of the threshold voltage was accomplished  by  measuring the gate voltage at which the drain current was roughly 5 ua. Measurement of the transconductance  was obtained by p l o t t i n g the drain  current versus gate voltage and determining the slope at each point.  76  Measurement of the sheet resistance was made using the central Van der Pauw cross of figure 5.1 with the technique i n [82].  A current (1 ma) was  passed between two adjacent terminals such as A and B using an HP 6186A DC current source, while the voltage between the other adjacent terminals C and D was measured by a sensitive (Fluke 8050) voltmeter.  The active layer sheet  resistance, Rg, was obtained by solving:  R  s  ( V ^ )  = (*/ln2)  The H a l l mobility of the active layer was measured by using the same Van der Pauw cross structure.  The sample was placed i n a miniature probe holder and  placed i n a magnet (Alpha S c i e n t i f i c Laboratories) such that a magnetic f i e l d , B, (0-.2 Tesla) was applied normally to the sample.  A constant  current (100 ua) was applied between two opposite terminals, such as A and C, while the voltage was monitored at the remaining opposite terminals B and D. The average H a l l mobility was obtained by solving:  U  H = < BD S V  /R  B  I  AC  )  The undepleted c a r r i e r concentration  was then calculated from the sheet  resistance and H a l l mobility:  N  uc "  * HV  (1/C  U  The doping p r o f i l e was obtained by using the Schottky diode i n figure  77  5.1 and performing gate capacitance versus reverse bias voltage measurement and calculating the electron concentration n(x) versus depth x (e.g. [83]):  n(x) = (C /qeA ) (dV/dC) 3  2  where e i s the permittivity of GaAs, A i s the area of the diode, and C i s the gate capacitance.  This capacitance was measured by a HP 4275A  Multi-Frequency LCR Meter which i s interfaced to a HP 9812 computer, and the doping was p r o f i l e d by two software routines, HFCVN and NWALLN, supplied by HP. The d r i f t mobility p r o f i l e was measured using the fat FET (T3) following the method of Pucel and Krumm [84].  With the FET biased i n the  l i n e a r mode such that i t i s well below saturation (V  = 50 mV), the  Do  transconductance, dlpg/dV^g, was recorded by the HP 4145A Semiconductor Parameter Analyzer, the gate capacitance vesus reverse bias voltage was recorded by the HP 4275 LCR Meter, and with the doping p r o f i l e obtained above, the d r i f t mobility u(x) was given by:  u(x) = (L/C V  D S  ) (dI /dV )  where L i s the gate length.  D S  G S  For the p a r t i c u l a r FET geometry used, the  channel resistance was much greater than the contact resistances associated with the drain and source, and those factors were thus ignored i n the mobility measurement. The backgating measurements were accomplished using the HP 4145A  78  Semiconductor Parametric Analyzer.  MESFET T l was used as the active device,  and the adjacent pad A of the Van der Pauw cross (500 as the sidegate electrode.  um separation) was  used  The Parameter Analyzer was programmed to plot the  drain current with both the gate and source grounded versus the backgating voltage as i t was swept from +20  V to -30  V.  The data were stored and  replotted on the HP 9816 computer so that the drain current was normalized to I, with the backgating electrode disconnected, dss The l a s t measurement was  the deep levels i n the MESFET channels.  That  was performed using the channel current DLTS technique described i n the l a s t Chapter.  5.5  Results of Active Layer Evaluation Typical ^ " V p g  c h a r a c t e r i s t i c s of the four MESFETs i n each test  pattern are shown i n figure 5.3.  ^gg  *-  s n o t  t n e  same In the four  t r a n s i s t o r s because of the d i f f e r e n t gate lengths and widths i n each device. The linear region of the c h a r a c t e r i s t i c s does not have a steep slope which i s a consequence of not using an n -implant +  contact resistances.  to reduce the source and drain  The drain current at saturation i s almost constant with  increasing drain voltage which i s desirable i n MESFETs.  Because of the l i g h t  doping of the channel, no breakdown i n the drain current occurs for drain voltages below 10 v o l t s .  Table 5.1  presents results on the average drain  current and threshold voltage and their scatter for MESFET T l (L = 10 um, W = 500 pm).  The averaging was done over 10 to 12 devices which are spaced  h o r i z o n t a l l y and v e r t i c a l l y by 5 mm,  and so the scatter r e f l e c t s  (as opposed to microscopic) inhomogeneity  i n the s l i c e s .  macroscopic  The table also  10  Fig. in  5.3  the  Typical diagnostic  I test  - V  79 (mA)  characteristics  pattern  of  MESFETs  80  Table 5.1  Comparison of the active ion implanted layers parameters of f i v e GaAs samples.  Parameter  A-686  A-727  I. (Tl) dss '  9.25 ma  7.82 ma  11.21 ma  9.58 ma  7.73 ma  Scatter (I,, ) dss  1.25 ma  0.61 ma  1.46 ma  1.00 ma  0.94 ma  v  Vth ( T l ) Scatter (Vth) Rs Scatter (Rs) U  H  N uc  -2.00 V 170 mV  -1.71 V 66 mV  A-184  -2.21 V 130 mV  -1.74 V 94 mV  -1.50 V 90 mV  1584  1672  1370  1282  1553  125  76  82  85  132  4542  4693  4530  4751  4683  8.7E11  8.0E11  1.0E12  1.0E12  8.6E11  1107 A  1215 A  949 A  1065 A  W  0  1186 A  W  l  2478 A  2389 A  2700 A  2501 A  2383 A  N max  1.32E17  1.22E17  1.26E16  1.36E17  1.12E17  Activation  66.2 %  61.5 %  63.0 %  68.4 %  56.1 %  81  shows the average sheet resistance (R^) and i t s scatter, H a l l mobility (U ), S  undepleted c a r r i e r concentration  H  (N^,), zero gate bias depletion width ( Q)» W  the doping p r o f i l e depth at a doping l e v e l of 10 concentration N  16  (Wj), the peak c a r r i e r  , and a c t i v a t i o n of the 5 samples.  max'  r  l a s t four entries i n table 5.1 were obtained f i v e samples determined by C-V  The information of the  from the doping p r o f i l e s of the  carrier profiling.  The doping p r o f i l e s of the  f i v e substrates and the d r i f t m o b i l i t i e s are shown i n figures 5.4(a-e). as-implanted p r o f i l e was and  the standard  Ds, of 2.2xl0  12  calculated knowing that the implant  deviation AR^ cm ;  The  and a dose,  n(x) i s (e.g. [4]):  -2  AR  )  2  -2—4  EXP{  —  1/2  (2it)  depth R^ i s 850A  i s 442A for an energy of 100 keV,  (x—R n(x) =  The  2(AR  P  P  )  (5.1)  2  t h e o r e t i c a l peak c a r r i e r concentration i s the factor multiplying the  exponential  i n equation  (5.1).  The measured peak c a r r i e r concentration  C-V measurements) can then be divided by that obtained p r o f i l e to obtain a c t i v a t i o n i n table 5.1. the other hand, was  estimated  (from  for the as-implanted  The calculated doping p r o f i l e , on  by including the e f f e c t s of the time, t, of the  anneal and also be taking into account the d i f f u s i o n c o e f f i c i e n t , D, of s i l i c o n i n GaAs (Yamazaki et a l . [85]).  The e f f e c t i v e straggle i s increased  by d i f f u s i o n at high temperatures and becomes [85,86]:  f  AR' = ((AR ) P P v  9  1  + 2 D t)  Fig. 5 . 4  As-implanted, calculated, and measured c a r r i e r density  and d r i f t mobility p r o f i l e s  profiles  toooo  l.E+18  7  <  s  I.E+17  u  \  •7 7  c o t. «• c • c o u  IOOO "Z « « >  .7  l.E+16  < fi U  too *  h  •  I.E+15  0  ' l  I  I. 11  .1  '  •  '  1  • \ •  .2 Depth  _i  .3  .4  1  1  1  I,  0  .5  (micron)  (b) A-727 (Cominco)  F i g . 5.4 cont'd oo  C e n c a n t r t t t o n (cm"—3)  <78  Concantratton  (cm--3)  Concantrstton  Mobility  98  (cn<"—3)  (cm"2/vsec)  87  where t i s 1500 replaces AR  sec and D = 3 x l 0  cm /sec.  - l b  2  This e f f e c t i v e straggle  i n equation (5.1) and the r e s u l t i n g calculated p r o f i l e i s  P  generally f l a t t e r than the as-implanted p r o f i l e . Examination of the parameters i n table 5.1 and the doping p r o f i l e s reveals wide variations between the substrates.  Concentrating  first  on  Cominco's material, i t i s seen that their most recent wafer A-727 has  the  least scatter i n the threshold voltage, drain current and sheet resistance among a l l the samples. current measured was (figure 5.4b)  This makes i t desirable.  The fact that the drain  one of the lowest i s explained by the doping p r o f i l e  which shows that the electron density as a function of depth i s  the closest to the calculated doping p r o f i l e and therefore the channel i s narrower.  An i n t e r e s t i n g feature of this sample i s the fact that the dip i n  the peak c a r r i e r concentration,  N m a x  »  was  not accompanied with a long  d i f f u s i o n t a i l as compared to other samples from the same vendor.  This  may  be caused by substantial compensation of s i l i c o n i n the channel. Nevertheless,  the d r i f t mobility of this substrate can be seen i n figure  to be r i s i n g towards the i n t e r f a c e , reaching semi-insulating substrate.  5100  5.4b  cm /v sec near the 2  On the other hand, comparison of Cominco's  samples from d i f f e r e n t eras, A-686 (1985) and A-184  (1982), both of which  were q u a l i f i e d for f a b r i c a t i o n , show differences with respect to the drain current magnitude and the threshold voltage which are evident by examining table 5.1.  The differences can be explained by comparing the doping p r o f i l e s  of the samples i n figures 5.4a  and 5.4c  where i t can be seen that  d i f f u s i o n has taken place for sample A-184  extensive  making i t s channel the widest, and  88  as a consequence, the drain current and threshold voltage of A-184 highest of a l l the f i v e samples.  i s the  Unlike A-727, there i s substantially higher  scattering of the threshold voltage, drain current, and sheet resistance i n both A-686 and A-727.  The d r i f t mobility p r o f i l e for A-686 can be seen i n  figure 5 . 4 a to be r i s i n g to a value fo 6200 cm /v sec towards the interface, 2  while for A-184  the d r i f t mobility shown i n figure 5 . 4 c  cm /v sec) towards the i n t e r f a c e . 2  (5000  i s constant  The better mobility, better a c t i v a t i o n ,  and smaller d i f f u s i o n t a i l of the recent sample, A-686 shows that the vendor has changed the growth conditions to improve his material.  A-727 which i s  rather d i f f e r e n t from A-686 though they were both grown at close periods of time indicate that one or more growth parameters were not adequately controlled. Sample B from Sumitomo showed s u b s t a n t i a l l y d i f f e r e n t c h a r c t e r i s t i c s . Compared to Cominco's recent material (A-686) and  i t had  similar drain currents,  s i m i l a r l y controlled d i f f u s i o n t a i l s i n the doping p r o f i l e .  high a c t i v a t i o n i s obtained concentration.  However,  as indicated by the better peak c a r r i e r  Also, s u b s t a n t i a l l y less depletion width under the gate i s  observed (949A compared to 1186A  for A - 6 8 6 ) .  current and of the threshold voltage was  The scatter i n the drain  better controlled, perhaps as a  result of a lower d i s l o c a t i o n density i n this 2" wafer than Cominco's 3 " wafers.  However, the d r i f t mobility of this sample (figure 5 . 4 d )  constant  ( 4 3 0 0 cm /v sec) toward the i n t e r f a c e , which was 2  was  far lower than any  of Cominco's material. Sample C from L i t t o n had the lowest percentage a c t i v a t i o n , drain current, and threshold voltage i n comparison to Cominco's and  Sumitomo's high  89  pressure grown substrates.  The scatter of the threshold voltage and drain  current, however, was confined to reasonably good values similar to sample B. The depletion width under the gate and the d i f f u s i o n of the c a r r i e r s were adequately controlled as i n A-727.  However, as a consequence of lower  a c t i v a t i o n , the threshold voltage was lower than A-727.  The d r i f t mobility  p r o f i l e shown i n figure 5.4e reaches a value of 4200 cm /v sec which i s 2  the lowest amongst the five samples.  5.6  Results on Deep Levels The MESFETs used for this test were made e s s e n t i a l l y following process  III described i n the previous chapter i . e . direct Implantation into GaAs and annealing under PECVD s i l i c o n n i t r i d e cap. Another refinement was now introduced i n that capping was done also on the back side so as to prevent As loss on this surface.  It was found i n the previous chapter that only a  single l e v e l , S l , was present i n the MESFET channels prepared by process I I I . In addition, i t was found using OTCS that this trap was present i n the starting material as EL12, and hence was not process-induced. In this experiment,  a l l processing steps are i d e n t i c a l and hence deep  levels other than Sl present i n the f i v e GaAs MESFET channels may be concluded to be substrate-induced.  Results of channel current DLTS spectra  on MESFET T4 (L = 50 um, W = 425 um) for the f i v e samples from three vendors are shown i n figures 5.5a to 5.5e. shown i n figure 5.6.  Arrhenius plots of the traps obtained are  Tables 5.2 and 5.3 provide the DLTS data and  concentration of the traps.  Examination of the DLTS spectra of the five  substrates reveal a number of substrate-induced defects.  Focussing f i r s t on  SI  1  200  i 250  i 300  i 400  •  350  0  T K  -  Fig.  (a) A-686  5.5  Channel c u r r e n t  DLTS s p e c t r a  s u b s t r a t e s (Rate Window = 49.7msec)  (Cominco)  f o r MESFETs f a b r i c a t e d  on  five  S2  S3 (b) A-727 (Cominco) Fig. 5.5 cont'd  S2  200  300  250  S3  T°K  ( c ) A-184  Fig.  (Cominco)  5.5 c o n t ' d  -2  < 3  S1 L_  200  300  250  T°K  1  (d) B (Sumitomo)  Fig. 5.5 cont'd  S4  (e) C  Fig.  (Litton)  5.5  cont'd  EL6 / THIS  HL6 /  /  MARTIN  4 1000/T g. 5.6  Signature  line plots  of  the c h a n n e l  c u r r e n t DLTS  data  96  Table 5.2  DLTS data on the traps found by channel current DLTS.  Trap Level  Activation Energy  Capture Cross Section  Sl  0.74 eV  2.1X10-  S2  0.52 eV  3.62xl0  S3  0.87 eV  5xlO  S4  0.69 eV  2.3* 1 0  - l i +  cm  13  2  cm  - 1 6  2  2  cm  2  electron  EL12  electron Cr ?  electron hole trap  S5  Table 5.3  Identity  hole trap  cm - 1 2  Type  Concentration of the traps found by channel current DLTS. concentration of traps (cm ) -3  Substrate Type  A-686  S2  Sl  8.7xl0  S3  1.98* 1 0  A-184  1.89x10*  C  S5  11+  A-727  B  S4  14  4  1.90* 1 0  2.13* 1 0  1 5  5.32xl0  1 3  1.7xl0  14  2.17xl0  llt  li+  97  Cominco's material, the DLTS spectrum of sample A-686 reveal that there are two traps one of which i s Sl (EL12) at a r e l a t i v e l y high concentration (8.7E14cm ). -3  The second trap i s substrate-induced and occurs at a high  temperature (T > 400 K) beyond the range of the experimental  setup,  and  therefore information about the a c t i v a t i o n energy, capture cross section and possible i d e n t i f i c a t i o n of the peak could not be obtained.  However, i t can  be seen that the concentration of that l e v e l Is high and i n addition, at that temperature, i t was  observed that there was  substantial lagging of the r i s e  time of the drain current i n response to changes i n the gate voltage.  The  above traps are expected to be i n the channel region and not at the interface since the d r i f t mobility was high toward the interface with the semi-insulating substrate. A rather d i f f e r e n t spectrum was 5.5b.  Three substrate-induced  traps.  observed for sample A-727 i n figure  defects were found, two of which were hole  The l e v e l Sl was not found but instead, another electron trap, S2,  occurs i n the v i c i n i t y with much smaller capture cross section and closer to the conduction band as seen i n table 5.2.  The main feature of the spectrum  i s the dominant hole trap S3 with an a c t i v a t i o n energy of 0.87  eV.  This  could be due to an impurity, possibly chromium, and occurred at a r e l a t i v e l y high concentration (2.13E15 c m ) . -3  Another hole trap S6 was  much smaller concentration (1.9E14 cm ) -3  found with a  but could not be i d e n t i f i e d since  the peak was  too broad for i t s c h a r a c t e r i s t i c temperature to be  obtained  accurately.  It i s possible that the limited d i f f u s i o n of the ion implanted  s i l i c o n found i n this sample i n comparison to other samples from this vendor was  due to the high concentration of the hole trap S3 which acts as an  98  acceptor and compensates donors i n the channel.  The hole traps appearing i n  this sample, but which were not observed i n A-686 although both substrates were recent indicates possible contamination  during growth.  The DLTS spectrum of sample A-184, the substrate which was grown three years e a r l i e r displayed similar traps to A-727.  Two  traps were found, S2 and  S3, the second of which showed smaller concentration (5.32E13 c m ) . -3  These  findings indicate again that vendor A has changed some of the growth parameters over the three year period, as the DLTS spectra of A-686 and are e n t i r e l y d i f f e r e n t .  A-184  While he succeeded i n reducing the impurities of his  undoped substrate material (evidenced by the absence of hole traps i n A-686), the control of the growth environment was  apparently inadvertently lost  during the growth of his recent substrate A-727. Sample B of Sumitomo displayed a DLTS spectrum similar to the material investigated i n the previous chapter for process I I I . with a small concentration (1.9E14 cm ) -3  were found.  The l e v e l SI was  and no substrate induced  found  defects  Sample C of L i t t o n did not show the l e v e l SI, but another  electron l e v e l appeared i n the v i c i n i t y , S4, at a small concentration, (1.90E14 c m ) , which was -3  5.7  Results on Backgating  not present i n the starting material.  Backgating i s the phenomenon where the drain current of a MESFET i s  modified by the application of a bias voltage to a nearby electrode separated from the active device by the semi-insulating substrate.  This phenomenon  occurs when the channel interface with the bulk i s modulated i n thickness as a result of backgating bias with the semi-insulating separating layer acting  99  as a d i e l e c t r i c [87].  The severity of the backgating  effect i s dictated  by the separation of the nearby devices, thermal s t a b i l i t y of the substrate, the degree of i s o l a t i o n between devices, and the material properties of the semi-insulating substrate. backgating  Lee et a l . [88] and Miers et a l . [76] found a  voltage threshold which coincided with a trap f i l l e d l i m i t  where c a r r i e r s injected from the backgating substrate.  voltage f i l l the traps i n the  Beyond the threshold, substrate conduction  between devices.  voltage  causes cross-talk  However, agreement between the backgating  threshold and  the  trap f i l l e d l i m i t voltage i s not conclusive i n the l i t e r a t u r e as the results of Blum and Fleshner  [89], and Tang [36] found l i t t l e or no threshold for  capless annealed and s i l i c o n dioxide cap annealed devices respectively; both suggest p-type surface conversion caused by the outdiffusion of EL2 as a probable cause of surface conduction  giving r i s e to backgating.  Ogawa and  Kamiya [90] studied both HB (chromium compensated) and undoped LEC  substrates  and found gradual reduction i n drain current as soon as backgating potential is applied for HB substrates; a threshold was  however found i n undoped LEC  GaAs. In this study, backgating  (sidegating) due to bias on a contact 500  away from an active device, T l , was from d i f f e r e n t vendors. I.  um  investigated for the undoped LEC GaAs  Results of normalized  ) as a function of sidegating bias from +20  drain current (with respect to V to -30 V for the 5 sub-  Q S S  strate materials are shown i n figure 5.7.  As a l l processing steps are the  same, expected variations i n the sidegating behaviour are attributed to material differences.  It can be seen from figure 5.7  A-727, A-686, and sample B were affected by backgating  that three substrates, bias at +5 V, with  F i g . 5.7 voltage  Comparison of normalized drain current versus backgating for five GaAs samples  g o  101  sample A-727 showing considerable backgating effect as the drain current reduce to half at fabrication.  of -30 V; this makes i t unqualified for active device  It i s l i k e l y that the dominant hole trap S3 found i n A-727  which behaves as an acceptor could form a p-type layer on the surface i n addition to the outdiffusion of EL2 reasoned by [89,36] and therefore enhancing  substrate conduction.  On the other hand, Cominco's e a r l i e r sample,  A-184, was affected d i f f e r e n t l y by backgating, and the threshold of backgating i s found to be -5 V, which agrees with Lee et a l . [88]. The low pressure grown sample C, appears i n this experiment  to have the best  backgating c h a r a c t e r i s t i c s , the backgating voltage threshold for this sample i s -16 V, which makes i t a t t r a c t i v e for high density f a b r i c a t i o n .  This study  shows that the backgating effect i s very much material dependent which can explain the disagreement  i n the experimental findings of backgating i n the  literature.  5.8  Discussion of the Results Comparison of various undoped LEC GaAs material has shown that the  e l e c t r i c a l c h a r a c t e r i s t i c s of ion implanted active layers, such as, a c t i v a t i o n e f f i c i e n c y , mobility, doping p r o f i l e control, and uniformity i s a function of the starting material. One of the main differences i n the active layer c h a r a c t e r i s t i c s of the f i v e substrates studied here was shown to be the c a r r i e r concentration p r o f i l e s .  Deviations from the calculated doping  p r o f i l e s occur as a result of variations i n the depletion width under the gate, the doping e f f i c i e n c y , and the d i f f u s i o n t a i l s . under the gate i s [91]:  The depletion width  102  2 e V W  0  where V  <l(N_. +  bi  u  /  2  N) T  i s the b u i l t - i n potential (0.8 V for GaAs), N  i s the doping  bi concentration and p e r m i t t i v i t y of GaAs.  i s the t o t a l concentration of traps, and e i s the Changes i n the depletion width can occur as a result  of variations i n doping e f f i c i e n c y and residual defects just under the surface.  Doping e f f i c i e n c y i s the r a t i o of the net donor concentration from  the implanted  s i l i c o n dose.  The net donor concentration i n undoped GaAs i s  the amount of the s i l i c o n which i s e l e c t r i c a l l y active plus the number of shallow donors N , minus the amount of both shallow and deep acceptors (N N^ ). a  , S3.  SG  Deep donors do not affect a c t i v a t i o n since they are e l e c t r i c a l l y  neutral i n the undepleted  channel [71]. The extent of d i f f u s i o n t a i l s are  affected by [92] the annealing temperature, stresses caused by the annealing cap, implant dose, and stoichiometry of the substrate.  With a l l parameters  the same, different extents of dopant d i f f u s i o n i n the five substrates examined were caused by stoichiometry differences affected by the varying concentration of impurities, defects, and  vacancies.  It has been reported that inhomogeneity i n the doping p r o f i l e s , which i n turn produces variations i n threshold voltages and drain currents, may caused by the dislocations i n the substrates.  be  For example, Nanishi et a l .  [93] reported that high d i s l o c a t i o n density increases the drain current and reduces the threshold voltage i n undoped LEC GaAs.  I s h i i et a l . [94]  focussed on the effect of d i s l o c a t i o n networks on the active layer parameters  103  and found that the threshold voltage scatter was  correlated with d i s l o c a t i o n  c e l l networks and not with d i s l o c a t i o n density.  In the central part of the  d i s l o c a t i o n network the drain current was voltage increased.  decreased whereas the threshold  More recently, however, Winston et a l . [95] found no  c o r r e l a t i o n between threshold voltage and the active layer v i c i n i t y to the nearest d i s l o c a t i o n for both conventional LEC GaAs and indium alloyed GaAs substrates.  They reported however more uniform  threshold voltages for lower  d i s l o c a t i o n density In-alloyed GaAs than the higher d i s l o c a t i o n density  LEC  GaAs. The extent of d i f f u s i o n of the Implanted species, the pinch-off voltages, and threshold voltages were calculated from the measured capacitance-voltage  p r o f i l i n g to determine the extent of variations In the  substrates investigated. both N  The e f f e c t i v e straggle, AR'^,  was  calculated from  aud the d i f f u s i o n depths at a doping concentration of 1 0 , 16  W^,  which were tabulated i n table 5.1 and solved for i n the following equation:  10  16  = N max  Exp(  2(AR"  The value of the corresponding  )  2  d i f f u s i o n c o e f f i c i e n t , D', was  then calculated  from the e f f e c t i v e straggle:  AR"  P  = (AR V  2  P  + 2 D't)  The pinchoff voltage was  1 / 2  calculated by integrating the charges under the gate  104  that had to be depleted numerically [91]:  CO  V  P  = M £  n(x)'xdx 0  where n(x)' i s the Gaussian p r o f i l e f i t t e d to the capacitance-voltage p r o f i l e obtained for each substrate.  F i n a l l y , the threshold voltage  (C-V) was  calculated by subtracting the b u i l t - i n potential from the pinchoff voltage. The results are given i n table 5.4 where the calculated pinchoff voltage and threshold voltages of the calculated and as-implanted given.  p r o f i l e s are also  The calculated threshold voltages can be seen to approximately  match  those experimentally derived i n table 5.1 with the exception of sample B where the experimental  threshold voltage was  lower.  This indicates that the  C-V p r o f i l e when integrated over the channel length gives more charges i n the depletion region than there actually are. a degree of n-type surface conversion.  This discrepancy must be caused by  For the other samples, the s l i g h t  difference i n threshold voltage i s due to variations i n the depletion width at zero gate voltage under the gate as indicated i n table  5.1.  From the c i r c u i t design stand-point, control of the threshold voltage i s required for the Schottky Diode F i e l d Effect Logic (SDFL) should be within ±200 mV. [71].  This allows thickness variations only i n the order of 80A-100A  This means for the samples studied that the measured straggle has to  be within that thickness v a r i a t i o n from the design or control sample. A l l the samples investigated here had a threshold voltage scatter within the required l i m i t for the SDFL c i r c u i t .  For LSI c i r c u i t s , however, considerably  105  Table 5.4  Comparison of the calculated values of e f f e c t i v e straggle (ARp), d i f f u s i o n c o e f f i c i e n t (D'), pinchoff voltage ( V ) , and threshold voltage (V ^) of f i v e GaAs samples. p  t  Profile  AR" p A  N max cm  D' cm sec  -3  2  -1  V p volts  V.. tn volts  w  10.6xl0  - 1 5  -2.91  -2.11  1.22xl0  17  9.24xl0  - 1 5  -2.58  -1.78  822  1.26xl0  17  16xl0  - 1 5  -3.18  -2.38  B  723  1.36xl0  17  10.9xl0  - 1 5  -3.03  -2.23  C  699  1.12xl0  17  9.72X10  -15  -2.39  -1.59  LSS  442  2.00xl0  17  -2.61  -1.81  Calculated  534  1.64X10  -2.63  -1.83  A-686  717  1.32xl0  A-727  688  A-184  1  0  3xio-l  5  106  more stringent demands are placed on the threshold voltage so that standard deviation must remain within ±50 mV  [71].  This requires better substrate  q u a l i t y and r e p r o d u c i b i l i t y than presently available.  5.9  Summary Undoped LEC GaAs was  investigated for s u i t a b i l i t y of IC applications.  The following results were obtained: 1.  Comparison of the low pressure and high pressure growth materials  showed that while the active layer properties of the low pressure grown GaAs was  poorer i n mobility and activation compared to the high pressure material,  i t nevertheless had good homogeneity, low deep l e v e l concentrations, and excellent backgating 2.  characteristics.  Comparison of the high pressure grown GaAs from different  suppliers showed that there are differences i n the material which resulted i n differences i n doping p r o f i l e s , m o b i l i t i e s , deep l e v e l s , backgating c h a r a c t e r i s t i c s , and surface conversion. 3.  Comparison of the substrates grown at different times from one  supplier revealed that the vendor had changed the 'recipe' over the time period examined as the latest material showed worse backgating c h a r a c t e r i s t i c s , lower d i f f u s i o n , and e n t i r e l y different  substrate-induced  deep l e v e l s . 4.  Examination of the substrate which was  rejected by a device  manufacturer revealed that while i t showed better controlled doping  profiles  and homogeneity, the sample had low e l e c t r i c a l a c t i v a t i o n , high concentration of undesirable deep l e v e l s , and substantial backgating.  107  CHAPTER 6  CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK  In the work reported i n this thesis a wide range of diagnostic tools including c a r r i e r concentration and d r i f t mobility p r o f i l i n g i n MESFETs, backgating, and deep l e v e l spectroscopic techniques were used to characterize commerically available undoped LEC GaAs.  The following observations  can be  made: 1.  Investigation of various GaAs substrates by OTCS revealed  eight traps, P1-P8, were present with P2 being a negative peak.  that  The r e l a t i v e  concentration of traps i n high and low pressure grown GaAs were found to be different.  The OTCS technique was found to be sensitive to GaAs surface  treatment, for example, some peaks were attenuated surface etch, whereas the amplitude of the negative surface grinding. type of electrodes.  i n amplitude following peak was increased  after  The OTCS spectra were affected by the sample geometry and For future work, i t i s suggested that the amplitudes of  the eight traps found here should be obtained as a function of position i n a GaAs substrate with a scanning OTCS system now under construction i n our laboratory.  The results of this study can then be correlated with the  d i s l o c a t i o n density d i s t r i b u t i o n . 2.  Investigation of deep levels after s i l i c o n ion implantation by  channel current DLTS revealed that process-induced defects appear i n MESFETs furnace annealed with s i l i c o n dioxide encapsulant.  Furnace annealing with  PECVD s i l i c o n n i t r i d e cap, however, did not cause process-induced defects.  108  For future work i t i s suggested that deep levels i n MESFETs annealed with and without cap using rapid thermal annealing  (RTA) should be investigated.  The  r e s u l t s can shed l i g h t into the role of heating and cooling rates of the two annealing  processes on defect  3.  generation.  Investigation of MESFETs fabricated i d e n t i c a l l y on various LEC  undoped GaAs revealed that some of them had defects which were not present i n the s t a r t i n g material and may therefore be concluded to be It i s believed that stoichiometry  substrate-induced.  differences i n various substrates play a  role i n inducing defects a f t e r ion implantation and annealing.  For future  study i t i s suggested that surface analysis by Secondary Ion Mass Spectroscopy (SIMS) for example should be carried out i n various to investigate the r e l a t i o n between stoichiometry and  substrates  substrate-induced  defects. 4.  It was concluded i n chapter 5 that backgating i s dependent on the  type of GaAs material used.  One of the samples which showed substantial  backgating had a dominant hole trap which could have played a r o l e .  Other  samples had d i f f e r e n t deep l e v e l compositions and showed d i f f e r e n t extents of backgating severity.  To investigate whether backgating i s influenced by  traps, i t i s suggested for future work that the technique of channel current DLTS be modified  to investigate deep levels at the interface of the channel  and the semi-insulating substrate. constant  The modification  requires that a  negative bias be applied to the gate of a MESFET so that the channel  i s nearly pinched o f f while e l e c t r i c a l pulses are applied to the backgating electrode.  The sampled region w i l l thus include both sides of the channel  substrate i n t e r f a c e .  The results of deep l e v e l spectra should c l a r i f y the  influence of traps on backgating.  110 REFERENCES [1]  R.D. Fairman and J.R. Oliver, "Growth and characterization of semi-insulating GaAs for use i n ion-implantation", Semi-Insulating III-V Materials, G. Rees editor, Shiva publishing, 83 (1980).  [2]  J.V. Dilorenzo and D.D. Artech House Inc., Ma.  [3]  R.E. Williams, Gallium Arsenide Processing Techniques, Artech House Inc., Ma. 1984.  [4]  S.K. Ghandi, VLSI Fabrication P r i n c i p l e s , John Wiley & Sons, 1983.  [5]  E.M. Swiggard, S.H. Lee, and F.W. Batchelder, "GaAs synthesized i n P y r o l y t i c Boron Nitride (PBN)", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 33b, 23 (1976).  [6]  Y. Nanishi, S. Ishida, and S. Miyazawa, "Characterization of SI GaAs substrates for GaAs ICs", Review of the E l e c t r i c a l Communication Laboratories 33(1), 136 (1985).  [7]  J.B. Mullin, R.J. Heritage, C.H. Holliday, and B.W. Straughan, "Liquid encapsulation c r y s t a l p u l l i n g at high pressures", J . Crystal Growth 3(4), 281 (1968).  [8]  L.B. Ta, R.N. Thomas, G.W. Eldridge, and H.M. Hobgood, "Reproducibility and uniformity considerations i n LEC growth of undoped, semi-insulating GaAs for large-area direct implantation technology", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 65, 31, (1982).  [9]  R.L. Henry and E.M. Swiggard, "LEC Growth of InP and GaAs using PBN Crucibles", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 33b, 28 (1976).  Khandelwal, GaAs Fet Principles and Technology, 1982.  N.Y.  [10]  L.B. Ta, H.M. Hobgood, A. Rohatgi, and R.N. Thomas, "Effects of stoichiometry on thermal s t a b i l i t y of undoped SI GaAs", J . Appl. Phys. 53(8), 5771 (1981).  [11]  R.N. Thomas, H.M. Hobgood, D.L. Barrett, and G.W. Eldridge, "Large diameter, undoped semi-insulating GaAs for high mobility direct ion-implanted fet technology", Semi-insulating III-V Materials, G. Rees e d i t o r , Shiva publishing, 76 (1980).  [12]  K. Tada, S. Murai, S. Akai, and T. Suzuuki, "Growth and characterization of d i s l o c a t i o n free GaAs mixed crystals for IC substrate", GaAs IC Symposium, Boston, Ma. 49 (1984).  Ill  [13]  A.M. Ruber, N.T. Llngh, M. Valladon, J.L. Debrun, G.M. Martin, A. Mitonneau, and A. Mircea, "Direct evidence for the nonassignment to oxygen of the main electron trap i n GaAs", J . Appl. Phys., 50(6), 4022 (1979).  [14]  J . Lagowski, J.M. Parsey, M. Kaminska, K. Wada, and H. Gatos, "On the behaviour of the major deep l e v e l (EL2) i n GaAs", Proc. 2nd Int. Conf. on SI III-V materials (Evian, France), Edited by S. Makram-Ebeid and B. Tuck, 99 (1982).  [15]  A..A. Immorlica J r . , D.R. Chen, D.R. Decker, and R.D. Fairman, "The effect of materials properties on the RF performance of GaAs f e t s " , GaAs and Related Compounds, Inst. Phys. Conf. Serv. 56, 423 (1980).  [16]  D.E. Holmes, R.T. Chen, K.R. E l l i o t , and C.G. Kirkpatrick, "Stoichiometry-controlled compensation i n l i q u i d encapsulated Czochralski GaAs", Appl. Phys. Lett., 40(1), 46 (1982).  [17]  T. Sato, K. Terashima, S. Ogawa, M. Nakajima, T. Fukuda, and K. Ishida, "Effect of e l e c t r i c a l uniformity of s i implanted undoped, semi-insulating GaAs", GaAs IC Symposium, Boston, Ma. 53 (1984).  [18]  D.E. Holmes, K.R. E l l i o t , R.T. Chen, and C.G. Kirkpatrick, "Stoichiometry related centres i n LEC GaAs", Proc. 2nd Int. Conf. on SI III-V materials (Evian, France), Edited by S. Makram-ebeid and B. Tuck, 19 (1982).  [19]  H. Emori, T. Kikuta, T. Inada, T. Obokata, and T. Fukuda, "Effect of water content on B 0 encapsulant on semi-insulating LEC GaAs c r y s t a l s " , Japn. J . Appl. Phys., 24(5), L291 (1985). 2  3  [20]  P.B. Klein, P.E.R. Nordquist, and P.G. Siebenman, "Thermal conversion of GaAs", J . Appl. Phys. 51(9), 4861 (1980).  [21]  T. Fukuda, K. Terashim and H. Nakajima, "In s i t u p u r i f i c a t i o n growth of undoped semi-Insulating GaAs single c r y s t a l s " , GaAs and Related Compounds, Inst. Phys. Conf. Ser. 65, 23 (1980).  [22]  W.M. Duncan, G.H. Westphal, and J.B. Sherer, "A direct comparison of LEC GaAs growing using low and high pressure techniques", Electron. Lett., 24(6), 199 (1983).  [23]  T. Shimada, T. Obokata, and T. Fukuda, "Growth and r e s i s t i v i t y c h a r a c t e r i s t i c s of undoped semi-insulating GaAs crystals with low d i s l o c a t i o n density", Japn. J . Appl. Phys., 23(7), L441 (1984).  [24]  T. Shimada, K. Terashima, H. Nakajima, and T. Fukuda, "Growth of low and homogeneous d i s l o c a t i o n density GaAs crystals by improved LEC growth technique", Japn. J . Appl. Phys., 23(1) L23 (1984).  {  112 [25]  J . Osaka, H. Kohda, T. Kubayashi, and K. Hoshikawa, "Homogeneity of v e r t i c a l magnetic f i e l d applied LEC GaAs c r y s t a l s " , Japn. J . Appl. Phys. 23(4), L195 (1984).  [26]  K. Terashima, T. Katsumata, F. Orito, and T. Fukuda, "Vertical magnetic f i e l d applied LEC apparatus for large diameter GaAs single c r y s t a l growth", Japn. J . Appl. Phys., 23(5), L302 (1984).  [27]  J.K. Rhee and P.K. Battacharya, "Photo-induced current transient current spectroscopy of semi-insulating InP:Fe and InP:Cr", J . Appl. Phys., 53(6) 4247 (1982).  [28]  C. Hurtes, M. Boulou, A. Mitonneau, and D. Bois, "Deep Level Spectroscopy i n high r e s i s t i v i t y materials", Appl. Phys. Lett. 32 (12, 821 (1978).  [29]  R.D. Fairman, F.J. Morin, and J.R. Oliver, "The influence of semi-insulating substrates on the e l e c t r i c a l properties of high purity GaAs buffer layers grown by vapor-phase epitaxy", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 45, 134 (1978).  [30]  G.M. Martin and D. Bois, "A new technique for the spectroscopy of deep levels i n insulating materials: Application to the study of semi-insulating GaAs", Semiconductor Characterization Techniques, P.A. Barnes ed., Electrochem. Soc. Proc. 78-3, 32 (1978).  [31]  G.L. M i l l e r , D.V. Lang, and L.C. Kimerling, "Capacitance transient spectroscopy", Ann. Rev. Mater. S c i . , 377 (1977).  [32]  B. Deveaud and B. Tolouse, "Observation of very deep levels by o p t i c a l DLTS", Semi-Insulating III-V Materials, G. Rees editor, Shiva publishing, 241 (1980).  [33]  R.D. Fairman, R.T. Chen, J.R. Oliver and D.R. Chen, "Growth of high purity semi-insulating bulk GaAs for integrated-circuit applications", IEEE Trans. Electron Devices, 28(2), 135 (1981).  [34]  J.R. Oliver, R.D. Fairman and R.T. Chen, "Undoped semi-insulating LEC GaAs: A model and a mechanism", Electron. Lett., 17(22), 839 (1981).  [35]  K.S. Lowe, "Ion-implanted GaAs MESFET technology", M.A.Sc. Thesis, U.B.C., 50 (August 1983).  [36]  W.C. Tang, "Semi-insulating GaAs-deep trapping l e v e l s , dislocations, and backgating", M.A.Sc. Thesis, U.B.C., (December 1984).  [37]  T. Itoh and H. Yanai, "Long term d r i f t of GaAs MESFET c h a r a c t e r i s t i c s and i t s dependence on substrate with buffer layer", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 45, 326 (1978).  113 J.P. Z i e l i n g e r , B. Pohoryles, J.C. Balland, J.G. Gross, and A. Coret, "Investigation of deep levels i n Pbl by photo-induced current transient spectroscopy", J . Appl. Phys. 57(2), 293 (1985). G.M. Maren and S. Makram-Ebeid, "Manifestation of deep levels point defects i n GaAs", Physica 116B, 371 (1983). R.I. Gloriozora, "Electron states of l o c a l centers i n n-type GaAs-O", Sov. Phys. Semicond., 14(8), 876 (1980). J.K. Rhee, P.K. Bhattacharya and R.Y. Koyama, "Deep levels i n Si-implanted and thermally annealed semi-insulating GaAs:Cr", J . Appl. Phys. 53(4), 3311 (1982). U. Kaufmann and J . Schneider, Advances i n Electronics and Electron Physics, V o l . 58, 81 (1982). D.E. Holmes and R.T. Chen, "Contour maps of EL2 deep l e v e l i n LEC GaAs", J . Appl. Phys., 55(10), 3588 (1984). Y. Nanishi, S. Ishida, and S. Miyazawa, "Correlation between d i s l o c a t i o n d i s t r i b u t i o n and FET performances observed i n low Cr doped LEC GaAs", J . Appl. Phys., 22(1) L54 (1983). T.W. Hickmott, "Temperature dependence of FET properties for Cr-doped and LEC semi-insulating GaAs substrates", IEEE Trans. Electron Devices, 27(6), 1037 (1980). 0. Wada, S. Yanagisawa, and H. Takanaski, "Evaluation of deep levels i n semiconductors using f i e l d effect transconductance", Japn. J . Appl. Phys., 14(1), 157 (1975). A. Zylbersztejn, "The effect of deep levels on GaAs MESFETs", Physica 117B & 118B, 44 (1983). A.S. Grove, Physics and Technology of Semiconductor Devices, John Wiley and Sons, Inc., New York 1967. M. Ogawa, T. Kamiya, and H. Yanai, "Appearance of a negative peak i n the PITS spectrum from GaAs LEC semi-insulating c r y s t a l s " , GaAs and Related Compounds, Inst. Phys. Conf. Serv. 63, 571 (1981). L. Young, W.C. Tang, S. Dindo, and K. Lowe, "Optical transient current spectroscopy i n semi-insulating LEC GaAs", To be published. G.M. Martin, A. Mitonneau, and A. MIrcea, "Electron Traps i n bulk and e p i t a x i a l GaAs c r y s t a l s " , Electron. Lett., 13(7), 191 (1977). D.V. Lang and I.C. Kimerling, "Lattice defects i n semiconductors", Inst. Phys. Conf. Ser. 23, 581 (1974).  114 [53]  C. Hurtes, L. Hollan and M. Boulou, "Impurity characterization of h i g h - r e s i s t i v i t y VPE layers for FET devices", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 45, 342 (1978).  [54]  S. Asai, S. Ishioka, H. Kurono, S. Takahashi and H. Kodra, "Effects of deep centers on microwave frequency c h a r a c t e r i s t i c s of GaAs Schottky barrier gate f e t " , Supplement to J . of Japan Society of Appl. Phys., V o l . 42, 71 (1973).  [55]  N. Yokoyama, A. Shibatomi, S. Ohkawa, M. Fukuta and H. Ishikawa, " E l e c t r i c a l properties of the interface between an n-GaAs e p i t a x i a l layer and a Cr-doped substrate", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 33b, 202 (1976).  [56]  T. Itoh and H. Yanai, "Interface e f f e c t s on drain i n s t a b i l i t y i n GaAs METFETs with buffer layer", Supplement 19-1, 351 (1979).  [57]  T. Itoh and H. Yanai, " S t a b i l i t y i n performance and I n t e r f a c i a l problems i n GaAs MESFETs", 27(6), 1037 (1980).  [58]  Y.M. Young and G.L. Pearson, "Deep trapping effects at the GaAs-GaAs:Cr interface i n GaAs FET structures", 49(6), 3248 (1978).  [59]  A. Zylberstein, G. Bert and G. N u z i l l a t , "Hole traps and their e f f e c t s i n GaAs MESFETs", GaAs and Related Compounds, Inst. Phys. Con. Ser. 45, 315 (1978).  [60]  G.N. Maracas, "DLTS analysis of GaAs MESFETs and effects of deep l e v e l s on device performance", Ph.D. Thesis, Cornell University (January 1982).  [61]  L.A. C h r i s t e l and J.F. Gibbons, "Stoichiometric disturbances i n ion-implanted compound seraicondcutors", J . Appl. Phys. 52, 5050 (1981).  [62]  T. Onuma, T. Hirao and T. Sugawa, "Study of encapsulents for annealing Si-implanted GaAs", J . Electrochemical S o c , 129(4), 837 (1982).  [63]  U. Kaufmann and J . Schneider, Physics, Vol. 58, 81 (1982).  [64]  S. Sriram and M.B. Das, "Characterization of electron traps i n ion-implanted GaAs MESFETs on undoped and Cr-doped LEC semi-insulating substrates", IEEE Trans, on Electron Dev., 30(6), 586 (1983).  [65]  S. Sriram, B. Kim, P.K. Gosh and M.B. Das, "Determination of deep l e v e l impurities and their e f f e c t s on the small signal and LF noise properties of ion-implanted GaAs MESFETs", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 63, 215 (1981).  Advances i n Electronics and Electron  115 [66]  P.K. Battacharya and J.K. Rhee, "Some properties of semi-insulating and Si-implanted GaAs", J . Electrochem. Soc. 131(5), 1152 (1984).  [67]  T.R. J e r v i s , D.W. Woodward, and L.F. Eastman, "Effects o f ion-implantation on deep levels i n GaAs", Electron. Lett., 15(20), 619 (1979).  [68]  R.T. Blunt, R. Sweda, and I.R. Sanders, "Recoil P r o f i l e s produced by ion-implantation through d i e l e c t r i c layers", Vacuum, 34(1), 281 (1984).  [69]  B.M. Welch, Y.D. Shen, R. Zucca, R.C. Eden, and S.I. Lang, LSI processing technology for planar GaAs integrated c i r c u i t s " , IEEE Trans. Electron Devices 27(6), 1116 (1980).  [70]  J.A. Higgins, R.L. Kovas, F.H. Eisen, and D.R. Chen, "Low noise GaAs fet's prepared by ion-implantation", IEEE Trans. Electron Devices, 25(6), 587 (1978).  [71]  C.G. Kirkpatrik, R.T. Chen, D.E. Holmes, P.M. Asbeck, K.R. E l l i o t , R.D. Fairman, and. J.R. Oliver, "LEC GaAs for integrated c i r c u i t s applications", Semiconductors and Semimetals, R.K. Willardson and A.C. Beer editors, Vol. 20, 159 (1984).  [72]  C.A. Stolte, "Ion implantation and materials for GaAs integrated c i r c u i t s " , Semiconductors and Semimetals, R.K. Willardson and A.C. editors, Vol. 20, 89 (1984).  Beer  [73]  C.A. S t o l t e , "The influence of substrate properties on the e l e c t r i c a l characterization of ion-implanted GaAs", Semi-insulating III-V Materials, G. Rees editor, Shiva publishing, 93 (1980).  [74]  Y. Nanishi, H. Yamazaki, T. Mizutani, and S. Miyazawa, "Characterization of LEC grown SI GaAs for integrated c i r c u i t s applications", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 63, 7 (1981).  [75]  Y. I s h i i , S. Miyazawa, and S. Ishida, "Threshold voltage scattering of GaAs MESFETs fabricated on LEC grown semi-insulating substrates", IEEE Trans, on Electron Devices, 31(6), 800 (1984).  [76]  T.H. Miers, W.M. Paulson, and M.S. B i r r i t t e l l a , "The influence of material parameters on backgating i n GaAs integrated c i r c u i t s " , GaAs and Related Compounds, Inst. Phys. Conf. Ser. 65, 339 (1982).  [77]  G.M. Martin, "Key e l e c t r i c a l properties i n semi-insulating materials; the methods to determine them i n GaAs", Semi-insulating III-V Materials, G. Rees editor, Shiva publishing, 13 (1980).  116 E.M. Swiggard, "Present and projected status of GaAs materials technology", IEEE GaAs IC Symposium, 26 (1983). R.N. Thomas, H.M. Hobgood, G.W. Eldridge, D.L. Barrett, T.T. Braggins, L.B. Ta, and S.K. Wang, "High purity LEC growth and direct implantation of GaAs for monolithic microwave c i r c u i t s " , Semiconductors and Semimetals, R.K. Willardson and A.C. Beer, editors, V o l . 20, 1 (1984). N.G. Tarr and L. Young, Second annual report for B r i t i s h Science Council, Grant #51 (RC-5), 4 (1983).  Columbia  A.A. Immorlica, D.R. Becker, and W.A. H i l l , "A diagnostic pattern f o r GaAs FET material development and process monitoring", IEEE Trans, on Electron Devices, 27(12), 2285 (1980). L.J. Van der Pauw, "A method for measuring s p e c i f i c r e s i s t i v i t y and H a l l effect of discs of arbitrary shape", P h i l . Res. Rep. 13(1), 1 (1958). J.P. Donnelly, "Ion implantation i n GaAs", GaAs and Related Compounds, Inst. Phys. Conf. Ser. 33a, 237 (1976). R.A. Pucel and C.F. Krumm, "Simple method for measuring d r i f t mobility p r o f i l e s i n thin semiconductor films", Elecronic Letters, 12(10), 240 (1976). H. Yamazaki, T. Honda, and Y. I s h i i , " S i Ion implantation for GaAs IC f a b r i c a t i o n " , Rev. of Elec. Comm. Lab., 33(1), 130 (1985). S.K. Dhiman and K.L. Wang, "Process modelling of n-type doping i n GaAs", Solid State Science and Technology, 131(2), 2957 (1984). W.C. Tang, K.S. Lowe, I.A. Motaleb, and L. Young, "Backgating i n i o n implanted GaAs MESFETs", To be published. C P . Lee, S.J. Lee, and B.M. Welch, "Carrier i n j e c t i o n and backgating effect i n GaAs MESFETs", IEEE Elec. Dev. Lett. 3(4), 97 (1982). A.S. Blum and L.D. Flesner, "Use of a surrounding p-type ring to decrease backgating biasing i n GaAs MESFETs", IEEE Trans, on Electron Devices, 6(2), 97 (1985). M. Ogawa and T. Kamiya, "Correlation between the backgating effect of a GaAs MESFET and the compensation mechanism of a semi-insulating substrate", IEEE Trans, on Electron Devices, 32(3), 571 (1985). S.M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, N.Y. 1981.  117  [92]  J . Kasahara, and N. Watanabe, "Redistribution of implanted impurities in semi-insulating GaAs", Proc. 2nd Int. Conf. on SI III-V materials (Evian, France), Edited by S. Makram-Ebeid and B. Tuck, 238 (1982).  [93]  Y. Nanaishi, S. Ishida, T. Honda, H. Yamazaki, and S.Miyazawa, "Inhomogeneous GaAs fet threshold voltage related to d i s l o c a t i o n d i s t r i b u t i o n " , Japan J . Appl. Phys., 21(6), L335 (1982).  [94]  Y. I s h i i , S. Miyazawa, and S. Ishida, "Threshold voltage scattering of GaAs MESFETs fabricated on LEC-grown semi-insulating substrates", IEEE Trans, on Electron Devices, 31(6), 800 (1984).  [95]  H.V. Winston, A.T. Hunter, H.M. Olsen, R.P. Bryan, and R.E. Lee, "Substrate effects on the threshold voltage of GaAs FETs", Appl. Phys. Lett., 45(4), 447 (1984).  

Cite

Citation Scheme:

    

Usage Statistics

Country Views Downloads
United States 14 0
Japan 6 0
China 3 1
France 2 0
Mexico 1 0
Russia 1 0
Ukraine 1 0
Canada 1 0
City Views Downloads
Ashburn 6 0
Tokyo 6 0
Unknown 6 12
Shenzhen 2 1
Plano 1 0
Saint Petersburg 1 0
Sunnyvale 1 0
Atlanta 1 0
Toronto 1 0
Boulder 1 0
Wilmington 1 0
Beijing 1 0
University Park 1 0

{[{ mDataHeader[type] }]} {[{ month[type] }]} {[{ tData[type] }]}
Download Stats

Share

Embed

Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                        
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:
http://iiif.library.ubc.ca/presentation/dsp.831.1-0096234/manifest

Comment

Related Items