UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

The design of CMOS colour palette integrated circuit Mielcarski, Robert James 1983

Your browser doesn't seem to have a PDF viewer, please download the PDF to view this item.

Item Metadata

Download

Media
831-UBC_1983_A7 M53.pdf [ 11.99MB ]
Metadata
JSON: 831-1.0095834.json
JSON-LD: 831-1.0095834-ld.json
RDF/XML (Pretty): 831-1.0095834-rdf.xml
RDF/JSON: 831-1.0095834-rdf.json
Turtle: 831-1.0095834-turtle.txt
N-Triples: 831-1.0095834-rdf-ntriples.txt
Original Record: 831-1.0095834-source.json
Full Text
831-1.0095834-fulltext.txt
Citation
831-1.0095834.ris

Full Text

DESIGN  OF  A CMOS COLOUR P A L E T T E  INTEGRATED  CIRCUIT  By ROBERT J A M E S B.A.Sc,  The  A THESIS  University  SUBMITTED  THE  MIELCARSKI  of B r i t i s h  IN PARTIAL FULFILLMENT  R E Q U I R E M E N T S FOR MASTER OF  Columbia,  THE  APPLIED  DEGREE  OF  SCIENCE  in THE  FACULTY  OF  GRADUATE  ELECTRICAL  We  accept to  THE  this  thesis  OF  October (c)  ENGINEERING  the required  UNIVERSITY  Robert  STUDIES  as  conforming  standard  BRITISH  COLUMBIA  1983  James M i e l c a r s k i ,  1983  1981 OF  In p r e s e n t i n g  this thesis in p a r t i a l  f u l f i l m e n t of  requirements f o r an advanced degree at the  the  University  o f B r i t i s h Columbia, I agree t h a t the L i b r a r y s h a l l make it  f r e e l y a v a i l a b l e f o r reference  and  study.  I  further  agree t h a t p e r m i s s i o n f o r e x t e n s i v e copying of t h i s t h e s i s f o r s c h o l a r l y purposes may  be  department or by h i s o r her  granted by  the head o f  representatives.  my  It i s  understood t h a t c o p y i n g or p u b l i c a t i o n of t h i s t h e s i s f o r f i n a n c i a l gain  s h a l l not  be  allowed without my  permission.  Department of  £c€CTK\CA<-.  The U n i v e r s i t y o f B r i t i s h 2075 Wesbrook P l a c e Vancouver, Canada V6T 1W5 Date  7Q ^  j@ -  OCT  £T\)61 N € € ^ \ A ) k  Columbia  written  ABSTRACT  This testing  t h e s i s i s concerned  colour  puter  design  aided  complete  rules,  CAD  graphics  colour  display  details  integrated  (CAD) a r e d i s c u s s e d  system  The  simulation palette  palette  and e l e c t r i c a l  described.  thesis  the design,  of an o x i d e - i s o l a t e d c o m p l e m e n t a r y  (ISO-CMOS)  a  with  me t a 1-o x i d e - s i 1 i c o n  circuit.  Concepts  and t h e t o o l s  a r e d e t a i l e d . The f a b r i c a t i o n parameters palette  systems  the design  results,  f a b r i c a t i o n , and  and  o f t h e ISO-CMOS  function  and  are explained.  i n com-  required f o r steps,  design  technology  are  i t sapplications i n  The  remainder  of the  philosophy,  the design  procedure, the  the testing  performed  on  circuit.  i i  the  colour  T A B L E OF  Title  CONTENTS  Page  i  Abstract Table  of Contents  List  of Tables  List  of F i g u r e s  i  i  ix  1: I n t r o d u c t i o n  1  Project  2: R e v i e w  Design  VLSI  Tools  The  Mead  . . .  and T o o l s  4  6 6  Management  10  Circuits  14 17  a n d Conway  Revolution  and J u s t i f i c a t i o n  Chip  1  Overview  of Custom  CAD  Custom  Concepts  Complexity  Classes  3: S e l e c t i o n  Overview  O b j e c t i v e s and A c c o m p l i s h m e n t s  o f IC D e s i g n  IC  Chapter  i  v i i  Microelectronics  Chapter  i  v\  Acknowledgment Chapter  i  27  of a  35  Project  Background  Information  35  The  Palette  Function  36  Applications  37  Colour  Colour  Palette  The  Colour  The  Current  Colour  Palette MPR  Palette  Market  Colour  Potential  Palette  Specifications i i i  Implementation  37 39 40  Chapter  A: The ISO-CMOS An  Chapter  Chapter  Technology  Overview  Fabrication  ISO-CMOS  Design  5: D e s i g n  43 and P a r a m e t r i c Data  Constraints  . . 50 . 52  T o o l s , Procedures, and P h i l o s o p h y MPR CMOS D e s i g n  The  Design  Procedure  62  The  Design  Philosophy  66  6: The C o l o u r  Palette  (CDS)  59  Design  Development  Dual  System  59  The  Module  68  Synopsis  Partitions  and D i v i s i o n  , . 68 of Labour  ... . 69  P o r t Memory  Pipeline Digital Input  72  Register to Analog  84 Converter  88  Pad  Process  92  Monitor  94  Simulation  94  Global  95  Routing  7: R e s u l t s First  Chapter  o f CMOS  ISO-CMOS  The  Chapter  43  96 Iteration  Results  96  Second  Iteration  Enhancements  102  Second  Iteration  Results  104  8: C o n c l u s i o n s  1  Bibliography  1  2  114  iv  Appendices  121  A.  S c h e m a t i c s and B l o c k D i a g r a m s o f t h e M i c r o t e l P a c i f i c Research L t d . Discrete Component Colour Palette Implementation  B.  Colour Palette  C.  GTE  ISO-CMOS P r o c e s s  D.  The  CDS  E.  Top  Level  Layout Cell  Specifications Sequence  Language Source  v  Listings  . . 121  126 138 156 163  LIST  OF T A B L E S  I.  ISO-CMOS  Capacitance  Data  52  II.  ISO-CMOS  R e s i s t i v i t y Data  52  III.  ISO-CMOS  Simplified  IV.  Memory  Control  V. .  Memory  Cell  VI.  Pipeline  Register  VII.  Critical  Path  VIII.  Chip  Design  and Data  Rules  Signals  Bus L o a d i n g  #1 M e m o r y T e s t  77 81  Bus L o a d i n g  Simulation  53  Results  Summary  vi  85 95 107  LIST  OF  FIGURES  1.  Number  of Components  Versus  Time Levels  per Integrated  of C i r c u i t  Circuit  2.  The F o u r  3.  The T h r e e  4.  Programmable  5.  CAD S y s t e m  6.  Example  of Caltech  7.  Caltech  Intermediate  8.  Colour  9.  Examples  10.  CMOS  11.  Example  12.  ISO-CMOS  13. 14.  Layout o f an I n v e r t e r with CDS L a y o u t P r o g r a m E x a m p l e  15.  Stick  16.  Colour  17.  Traditional  18.  Memory  Bus S t r u c t u r e  78  19.  Memory  Cell  Logic  Schematic  80  20.  Memory  Cell  Stick  Diagram  82  21.  Memory  Cell  Layout  22.  Pipeline Register  Logic  Schematic  85  23.  Pipeline  Stick  Diagram  86  24.  Pipeline Register  25.  Dynamic  Major  Design  Logic  Abstraction  2  Activities  8  Array  16  Overview  Palette  Inverter  18 Intermediate Form  Block  of True  Form  30  Relationships  Diagram  Complementary  CMOS  CMOS  Circuits  Circuit  46 51  2 Enable  Example Cell  Static  Register  44 45  F a b r i c a t i o n Sequence  Palette  31 41  Characteristics  o f a Dynamic  Diagram  6  Signals  54 61 65  Hierarchy CMOS Memory  71 Cell  75  83  Layout  87  DAC L a y o u t  90  vii  26.  Static  DAC  27.  Input  28.  Process  29.  The  30.  Static  31.  Process  Monitor  32.  Dynamic  DAC  Test  33.  Dynamic  DAC  Output  with  34.  Dynamic  DAC  Output  at  35.  The  36.  Second  Pad  Layout Layout  Monitor  First  92 Layout  Iteration  First  Second  91  93  Chip  Iteration  Test  Inverter  Circuit  Characteristics  Circuit  Iteration  Iteration  96  Test  97 98 99  Static  1 MHz Chip  Inputs  100 100 105  Circuit  viii  106  ACKNOWLEDGMENT I  would  Lawrence,  s p e c i a l note  f o r providing  grated  circuit  without thank  I  Professor  would  Paul  my  Research  necessary  Thiel,  I would  Young's  t o thank  like  f o rtheir  like  Cheng,  forhis contributions  palette  to  on t h e  like  Council  the tools  project.  In particular  Pejskar,  Mel  Phillips,  the B r i t i s h  Ltd., the Columbia  L t d . , and M i c r o t e l  my s t u d i e s  to integrated  to thank  Pacific  Research  circuit  and s u p p o r t .  design  made i t  funds f o r and  S c i e n c e s and  f o r awarding  like  Industry  fellowship  and provided  the Natural  o f Canada  ix  This  British  Telephone  t o t h e B.C. E l e c t r o n i c s  but not l e a s t I would patience  i n providing  Electronics  i n Microelectronics.  facilities.  Research  Mike  at M i c r o t e l  Schmiing.  Anatek  contributions  also  to the people  generosity  Snyder,  Electronics  cation  infinite  inte-  also  Warren  worthwhile visits  her  on  I would  f o r me t o c o n t i n u e  Last  courses  encouragement.  the colour  several  neering  industry  written  of Technology,  Fellowship  would  with  Young  been  gratitude  t o thank  Glenayre  I  Professor  dialogue  several  Peter  n o t have  and e s p e c i a l l y Gerhard  Company,  possible  counsel.  Young,  would  L t d . f o rt h e i r  Institute  Graduate  thesis  Gordon  deepest  Columbia  Ltd.  to attend  This  to implement  like  wise  Lawrence  project.  extend  Pacific  fortheir  fororchestrating  design.  palette  my s u p e r v i s o r s ,  t h e means  my c o l l e a g u e ,  colour  I  t o thank  a n d G. S c h r a c k  deserves and  like  me a  t o thank Heather  fabri-  Engi-  scholarship. Sharkey f o r  CHAPTER  1:  INTRODUCTION  Microelectronics  Overview  Microelectronics achievements. power,  The  Industrial  microelectronics  Microelectronics [WEBER the  80, JONES  bipolar  tories. poor  i s one  overcome  as  technology  device  was  and h i g h  i n h e r e n t low power  Texas  Instruments  then  went  on t o d e v e l o p  oscillator). shown  that every  The  by F i g u r e  Gordon  circuit  E. M o o r e ,  invented, transistors  Today,  Hewlett  that  reservations  and b e c a u s e  transis-  circuit  rapidly  director  of research at  Packard  Kilby  after  has succeeded  semiconductor  1  circuit the  of  necessary He  (a s i m p l e  accelerated  then  years  i t s  of the  a semiconductor.  integrated  per integrated  of  rapidly  I n 1958 J a c k  from  Labora-  were  the p r e d i c t i o n  36  invented  a l l of the components be made  history  because  supports  only  power.  at Bell  curve  was  on a s i n g l e  working  of s o p h i s t i c a t i o n  1. T h i s  physical  intellectual  skepticism  These  improved  the number of components year.  with  the f i r s t  level  who  met  could  man's  and S h o c k l e y  and s m a l l s i z e .  realized  an e l e c t r o n i c  Brattain,  cost.  the technology  technological  has had an e x h i l a r a t i n g  i n 1947 w h i l e  tor's  for  great  Revolution leveraged  82]. Bardeen,  reliability  man's  h a s l e v e r a g e d man's  transistor  The new  of  as  i n 1 9 6 4 by Fairchild,  would  double  transistor  i n integrating  was  450,000  s u b s t r a t e [CANEPA 8 3 ] .  Figure  An "a  on a n d w i t h i n  because  low  connected  circuits  steps  have  therefore per unit  elements  [G L A S E R 7 7 ] a s fabricated i n  are several  low cost  important  IC's p a t t e r n e d over  ratio  f a b r i c a t i o n . Although  many  wafers.  2  Each  steps are  wafer  i n turn  on i t . The f a b r i c a t i o n  thousands  cost.  systems.  per function  t o f a b r i c a t e an I C , t h e s e  t o many s i l i c o n  distributed  defined  Circuit  use of IC's i n e l e c t r o n i c  of t h e i r  are required  identical  There  an e x t r e m e l y  nature  simultaneously  many  circuit  a substrate".  of the batch  expensive applied  ( I C ) has been  f o r the widespread  Integrated  are  circuit  of inseparably  reasons  has  Number o f Components p e r I n t e g r a t e d V e r s u s T i m e [NOYCE 7 7 ]  integrated  group  place  1.  o f IC's r e s u l t i n g  costs in a  The  cost  per  function  rate  unprecedented  cost  per  was  b i t of  down  memory l i t t l e  to  is  only  about  reasonably  are  yield  [NOYCE 0.005  (percentage  identical  consume  less  the  reduced  required  are  other  that  which  100,000 t r a n s i s t o r s ,  lems  associated  able  for  with  designing  resistors,  and  simple  but  capacitors. a r i s e s not rather  from  the  cooling  because  integrated  from the  The  circuit  of  complex  costs.  number  IC's  that  per-  floor  Labor  be  IC.  space,  costs  are  Finally  of  large  solder  to  scale  inte-  contain  more  to the  components are  in designing  complexity  vast  number of  of  probavail-  identical  transistors,  the  3  b a t c h ) can  shifted  IC.  difficulty  provided  assemble.  the  of  reduced.  These i n c l u d e  The  IC  components  usually defined  s u c h an  bit  simple  fans.  the  manufacturer  per  cost  a  1 97 7 i t  per  support  to  e m p h a s i s has  i n a VLSI c i r c u i t .  therefore  components,  the  designing a  the  f a b r i c a t e very  are  cost  by  to f a b r i c a t e a  system  f a c t o r s are  to  and  fabricate a  at  example,  than a simple  components  reliability  possible  (VLSI) c i r c u i t s ,  used  fewer  defect-prone  i t is  cents  costs  reducing  there  For  the  discrete  because  than  cuits  than  s u p p l i e s , and  Now  those  to  power  and  IC  also reduce  power  system  It  required  f u n c t i o n , thereby  the  Today  cents.  racks,  improve  joints  and  goods.  a b o u t 0.4  77].  steps  those  circuits  space  same  mounting  to  continually declined  of d e f e c t - f r e e IC's  h i g h . The  Integrated  grated  was  more to f a b r i c a t e a c o m p l e x  kept  IC's  has  manufactured  m e m o r y i n 1973 cents  the  form  other  0.1  that  IC  by  ratio  the  to  wires,  VLSI  cir-  individual  components  used.  One nents  of the key d e s i g n  on a V L S I  increases  faster  problems taining done  circuit  and  design  continue  computer-aided  a VLSI  problems  that  t h e b e s t way t o a c c o m p l i s h circuit. some  specification, could has  be  many  I t was  design,  i s  The  targeted  Telidon  system.  become  acquainted  nately  we  tools  (CAD) t o o l s  to solve  [FEUER 8 3 ] . VLSI has  advanced  design  as  new  ideas  this  emerge  i n  The with  second  The  final  so t h a t testing,  chosen  was  In  Pacific this  semiconductor  to work  with  o b j e c t i v e of t h i s  IC s i m u l a t i o n and t e s t i n g  circuit c y c l e of  implementation  a colour  o b j e c t i v e of  4  decided  a  the f u l l and  circuitry.  Microtel  a current  familiar  I t was  d e s i r a b l e to choose  fabrication,  f o r the  t o become  w o u l d be t o d e s i g n a n a c t u a l  application  circuit  was  and c o n c e p t s .  clearly  had t h e o p p o r t u n i t y  with  i s being  project  a p p l i c a t i o n s i n video  circuit  familiar  design  practical  observed.  technology.  research  only  o b j e c t i v e of t h i s  computer-aided  had  main-  Accomplishments  with  that  Much  and  design.  first  integrated  [SEQUIN 8 1 ] . Other  of a design  circuit.  to advance  O b j e c t i v e s and  The  the correctness  on  of i n t e r c o n n e c t i o n s  of devices  b e t t e r computer-aided  and o t h e r  w i l l  i s i n t e r c o n n e c t i n g t h e compo-  the number  the number  documentation  Project  because  include proving  to develop  these  than  problems  palette  particular Research project  the popular  p r o j e c t was  the Ltd.  was  technology.  problems.  which  to  Fortu-  ISO-CMOS to  become  We type  succeeded  integrated  results minor  show  design  prototype cuits  implement the  chip  The  microns  (DAC) was  has  been  ules cause  Several  test  to f a c i l i t a t e  o u t t o be w e l l  redesigned contains  i n size.  estimate  dynamic  errors.  the f a b r i c a t i o n  from  into about  Critical  designed used  and  i t sfull 6000  paths  and  operate  on  included  test  by  required  to  and i n c l u d e d  on  simultaneously.  5  circuit  16  full  r e s u l t s show  to locate  a  cir-  process.  the chip  problems  the  effort  designed  digital  The  on  These  size colour  to the palette  a l lc i r c u i t appear  to  converter  i n addition  which  6398  simulated  to analog  that  on  colour  i s 4070 x  were  however  chip  the  b i t configuration.  the c i r c u i t  on  of a few  included  t r a n s i s t o r s and  static  are f u n c t i o n a l . Processing of our i n a b i l i t y  12  test  process.  the prototype  on t h e p r o t o t y p e .  fabricated  were  proto-  and  the exception  the extra was  palette  fabricated  the debugging worth  p e r f o r m a n c e . A new  DAC  was  circuits  monitor  knowledge gained  circuit  circuit  i t i s functional with  for evaluating  was  a 4 by 4 b i t c o l o u r  The  them. A p r o c e s s  Using palette  circuit.  that  chip  turned  i n designing  mod-  t o be t h e  a l l modules  CHAPTER  IC  Design  One and  2: REVIEW OF  circuit levels  TOOLS  Overview  of the key d i f f e r e n c e s  the design  involves  I C D E S I G N CONCEPTS AND  a  of  greater  design  number  electrical of  and  abstraction  physical  FUNCTIONAL  integrated  systems  circuit  c a n be v i e w e d a s a n  of c i r c u i t  electrical,  other  between  circuit  i s that  representations.  iterative  (Figure  mapping  IC  between  2): f u n c t i o n a l ,  [NEWTON 8 1 ] .  A+B=C  5v ELECTRICAL  PHYSICAL  C 2.  The  Four Levels  6  of C i r c u i t  design  Integrated  LOGICAL  Figure  design  Abstraction  four  logical,  The  functional  specifies  consumption.  often  used  and  at  stage  subdivision  level  result  that  level  information.  to experiment  with  expresses  symbols  of the c i r c u i t  tors,  and w i r e s .  may a l s o  physical  implements  components:  transistors,  with  force  level  such  cause  level  performance.  the e l e c t r i c a l  of layout, often  archi-  often  becomes needs  level  level i n  resistors,  capaci-  h a s t o be m o d i f i e d  devices.  these  Excessive  the geometric  components.  to  of  level.  mask  data  The u n p l e a s a n t  i t may p r o v e  func-  loading  two-dimensional  For example,  7  may be t h e  the l o g i c a l  o f t h e way t h a t  as t h e r e s t r i c t i v e  problems.  further  design. For  lines  a r e v i s i o n at the l o g i c a l  contains  clear  F o r e x a m p l e , NOR-NOR l o g i c i s  because MOS  abstrac-  boundaries.  expresses  are implemented  The  of  defined at  an e f f i c i e n t  representation  t h a n NAND-NAND l o g i c  transistors  Suppression  or other  of communication  of module  The l o g i c a l  the c i r c u i t  to achieve  number  choice  terms  faster  and  language i s  each of the modules  of logic  or r e o r g a n i z a t i o n  of a poor  improve  size,  different  the functional representation  The e l e c t r i c a l  IC's,  or high  i n terms  example, an e x c e s s i v e  ties  box d i a g r a m  the functional  as speed,  such as r e g i s t e r t r a n s f e r n o t a t i o n . I t o f t e n  this  tions  such  algorithms.  functional level  tion  t h e IC's a r c h i t e c t u r e and  properties  the designer  The l o g i c a l the  A black  to present  permits  tectures  displays  i t sm a c r o s c o p i c  power  detail  level  that reali-  nature  of  impossible  to  route  design  an i n t e r c o n n e c t i o n  c l e a r l y tends  There level  t o be a n i t e r a t i v e  are three  major  of abstraction:  [LATTIN  81].  Figure  as s p e c i f i e d  design  at higher  process.  activities  synthesis,  evaluation,  3 s h o w s how t h e s e  l e v e l s . IC  activities  required and  at each  validation  interact.  ELECTRICAL SCHEMATIC  SYNTHESIS  VALIDATION  MASK LAYOUT  Figure  Synthesis a  description  task the  because physical  whereas  3.  The T h r e e  i s t h e mapping a t the next  Major  level.  Synthesis  a t one l e v e l  tends  description 8  For example,  t o be g r a p h i c a l  tends  into  i s a non-trivial  differing descriptions.  level description  the functional  Activities  of a description  lower  of the widely  Design  t o be t e x t u a l .  i n nature  Evaluation cations level, no  and for  constraints example,  geometric  does  not  determines  design  description  can  is  transformation. the  All ologies the  first  of  they the  level  as  the  the  masks. A  tion  the  masks.  there  are  loading  of  the the  are  and  by  of  particular  logical  use  description.  can  i n each can  their  and  be  of  be  synthesis description  techniques in  correctly.  the  electrical  design or  a  method-  fitted  levels  of  distinguished  by  tools  four  into  (or  absence  of  activities.  of  circuits the  was  were  logic  with  involved  ( p l a s t i c ) which the  physical  descriptions  methodologies  use,  circuit  level  the  capacitive  inverse  activities  and  integrated  produce of  three  Evaluation  physical  rubylith  of  proposed  Techniques  bread-boarding the  been  perform  computers.  higher  variety  have  that  v e r i f y i n g that  the  descriptions  The  of  against  scenario  them) t h a t  process  compare  that  specifi-  performance.  l o g i c and  rich  At  the  i n v e r i f y i n g that and  given  description. the  violations  the  meets  particular level.  is interested  thought  For  description  example,  of  above  the  be  the  degrade  implements  Validation  of  rule  excessively  Validation  extract  one  i f the  was  discrete drawing then  painstaking  designed usually  aid  of  performed  by  components. Synthesis  of  the  circuit  photographically  v i s u a l check  9  without  shapes  onto  reduced  constituted  to  valida-  Computers by  the  early  were  first  1970's  to  integrated  lated.  The  of  physical level  the  next  used  application  of  simulate  circuits  CAD  [AVENIER  was  83].  a r e ) h a n d d r a w n on m y l a r p l a s t i c base. I n t e r a c t i v e g r a p h i c s When c o m p l e t e , graphics Calma  data-base.  GDS  machines  I as  (with  until  later  ating  the  DRC  was  a  were  look  chapter.  VLSI  Complexity  Management  Design  a  requires  efficient  Locating  an  correcting making  and  exploitation  error i t can  the  An  at  this  VLSI  be  used  circuit  tool  can  be  difficult very  of  a  will  take  fabrication.  VLSI  of  and  regularity  be  from as  for  evalu-  prevalent. and  circuit  CAD  system later  man-years team  cost  in  and  members.  complexity,  therefore  and  non-existent  presented  the  the  validation  (ERC)  the  the  drafting  become  design of  hierarchy.  10  layout.  such  complete  because of  design  the  (DRC)  several  because  expensive  data-  were  checkers  c o o r d i n a t i o n between is  into a  computerized  t o o l s to  overview  still  systems,  checkers  simu-  synthesis  masks  with  but  often  edit  the  assist  rule  each  to  simulators)  next  (and  digitized  CAD  rule  being  i n the  were  produces  to  of  electric  validation.  more d e t a i l e d  of  Tools  1970's. D e s i g n  by  then  then  exception  followed for  and  also  assist  essentially  above.  layout  to  generation  were  the  i n the  mask  extractors and  system,  were  Designs  generator  First  described  evaluation  The  a pattern  can  discrete circuits  of  requires  and mask the  A  regularity  number  of  circuit  devices  [LATTIN  logic  arrays  There  are  82].  factor drawn 79].  (PLA)  specify and OR  a few  plexity of  of  unique  when  one  iAPX  432  the  and  of  the  a  chip  ten  must  been  design  increase cope  with  to  to  on  of  The  be  because  by  any  by  regularity. [FAIRBAIRN  software  need  inputs,  the  of  the  only  AND  and  the  the  com-  number  becomes as  for  outputs,  the  reducing  such  i f  Software  designer  clear  the  circuits  ability levels  conquer  the  from  of a  to  Intel such  as  view  and  abstraction" circuit  same t i m e  whole.  hierarchy  into  maintaining  Much has  been  writ-  design  [TRIMBERGER  81,  reduces  design  be-  a  library  achieving  amount  of  detail  time  is  reduced  11  high  earlier  and  at  assembled  given  programmable  regularity  "the  hierarchical  the  the  regularity  The  various  divide  probability  on  79].  as  reconstruct  devices  programming  with  while  the  R e g u l a r i t y reduces  81]  at  of  defined.  testing  defined  is  can  at  for  [INTEL  E x p l o i t a t i o n of  cells.  with  number of  emphasis  data-base  idea  circuit  the  80].  [LATTIN  advantages  83].  the  defined  new  manageable modules  the  NIESSEN  should  has  The  79].  ratio  and  state-of-the-art circuits  information  on  cause  a  [LANG  b i t map  8080 m i c r o p r o c e s s o r  82].  enough  The  of  generated well  facilitates  microprocessor  manipulate  smaller  a  of  are  s u c h as  [GLASSER  and  compares  Hierarchy  [JENNE  PLA  elements.  Intel  cells  provide  circuits  be  the  (ROM)  advantages often  as  number  memory of  i s commonplace  parameters  minterms, planes  examples  between  defined  total  only  s t r u c t u r e s can  PLA's  been  the  important  interconnections generating  to  Read  are  several  Regular  has  a  of  time  previously  correct  that and  the  design designer  because  the  library  cells  encourages the  are presumably  localized  "spaghetti  design once tions  i t need  Hierarchical only  communication  layouts"  should increase  a lower  level  archical result  a r e , however, design. Working  printed  c i r c u i t board  Some  workers  never  Several  There  of  VLSI  time  several from  be no w o r s e  are very  boundary  strong  level  languages  mance  with  was  such  the least  poor.  more  a  [SEQUIN  area  system  but  the  a  good  imposed  on a  components.  to  have 81].  data-base  are pointed out.  software engineering the  history  e x p e n s i v e and t h e h a r d therefore  to e x t r a c t  wrote  t h e maximum  i n low perfor-  efficiency  and hardware  unstructured 12  may  because  [SOUKUP  relating  amount o f memory. P r o g r a m m e r  powerful  hier-  design  83]. Consider  Programmers  became c h e a p e r  with  Given  than that  CAD  was  because  of modules  of h i e r a r c h i c a l  conditions  as a s s e m b l e r  a p r i o r i t y . As memory  improved,  chip  a n a l o g i e s between  c o m p l e x i t y management  performance  problems  s t a n d a r d TTL  implementation problems  and module  [WHITNEY 8 1 ] .  to the a p p l i c a t i o n .  such  viola-  stored.  and i n c r e a s e d  proponents  example,  data-base  library  (PCB) d e s i g n u s i n g that  For  i t i s used  a fixed  avoiding  f o r design rule  potential  s o f t w a r e . I n t h e b e g i n n i n g memory  ware  not  checked  design  hierarchical  tools.  m u s t be  to implement  serious  management  and  suggest  CAD  module  r e s t r i c t i o n may  attempted  o f some  each  thus  In theory,  i n a smaller  are not customized this  cells,  result  performance  library  Hierarchical  between  module has been  of each  free.  the past.  the speed  d e s i g n may  i n poorer  modules  of  n o t be r e c h e c k e d  one i n s t a n c e  There  error  was  performance  languages  such  as  Fortran  became  prevalent,  very  large  ware  reliability  ing  and c o m p l e x fell  and m o d i f y i n g  sought and  supporting  Now  languages  consider  functions  ly a  could  Fabrication  improved priori  (no h i e r a r c h y )  yield  t h e maximum and d e v i c e  hierarchical  verification  design,  a r e now  the structured  as a s o l u t i o n . Note however  contains  t h e same  basic  circuit,  instructions  fundamental  components  just  has changed  the  13  reliability  memory.  beginning  that  only  a  customized  performance  in a  have  Designer  very  issues.  complexity.  Regular  circuit  were p r e s e n t  first  great-  a n a l o g y , has  a VLSI  still  since  given  p r o d u c t i v i t y and  strong  that  that  i t d i d when  except  and  meant  density  as t h e c o m p u t e r  that  Structured  and h i g h l y  programming  proposed  basic  were  on a s i n g l e c h i p . As a r e s u l t  r e s u l t i n g i n VLSI c i r c u i t s .  circuit  integrated  density  maintain-  programming  management. In the  device  be i n t e g r a t e d  and  soft-  concepts  C, a n d A d a .  of performance  and poor  r e g u l a r i t y ) to achieve area.  software  such as P a s c a l ,  t o be f l a t  in  t h e boon i n s t r u c t u r e d  VLSI complexity  few  tended  New  to write  e f f i c i e n c y and  of the d i f f i c u l t y  programs.  a t the expense  fabrication yields  designs  possible  p r o d u c t i v i t y of the programmer  low  chip  large  became  Programmer  o f f because  such  improves  the program  (poor  programs.  and t h e r e s u l t has been  software of  and i t then  on t h e  executes invented.  the  been s t i l l first same  Nothing  Classes  o f Custom  Within are  three  dard be  the framework  classes  cells,  the  with  same  A  that  (PLA),  storage  logic  Gate a r r a y s slice  [NEWTON  by  customizing  Gate  array  cause masks. fastest at  provided  on s p e c i f i c  a r e gate arrays  logic  such  arrays,  (SLA),  method  the logic  be  a r e used on  an  array  of  The common  programmable only  logic  memories  o f names  (ULA),  types  such  arrays  and i n t e g r a t e d 82].  14  A  gate  function i s determined  i n volume  metal.  and s t o c k p i l e d beup u n t i l  the least  the f i n a l  expensive  p a r t s . Gate a r r a y  and t h e r e f o r e a v o i d  injec-  with p e r i o d i c spaces or  i s standard  custom  (ROM).  and a r e a v a i l a b l e i n  81, TRIMBERGER  provide  arrays  as m a s t e r  l a y e r ( o r two) of i n t e r c o n n e c t i o n  sequence  of  masks.  or gates  c a n be p r o d u c e d  gate  as  by  a s CMOS, b i p o l a r ,  of obtaining level  and  function i s determined  f o r w i r i n g . The c i r c u i t  the fabrication As a r e s u l t  stan-  c l a s s of c i r c u i t s can  defined  and read  arrays  81, ROFFELSEN  the f i n a l  blanks  arrays,  classes of c i r c u i t s  c a n be  a r r a y i san a r r a y of t r a n s i s t o r s channels  Each  a r e known by a v a r i e t y  technologies  logic  programmable  there  a p p l i c a t i o n s . I t should  l o c a t i o n s whose  or uncommitted  several tion  array  the geometry arrays  earlier,  circuit.  i n fixed  programmable  presented  o f CAD t o o l s a n d m e t h o d o l o g i e s ,  often a l l three  programmable  customizing  circuits.  suited to c e r t a i n  integrated  components  circuits:  custom  a variety  c l a s s i s best  emphasized  o f IC d e s i g n  of custom  and f u l l y  designed  each  Circuits  users  and  design  the n e c e s s i t y of under-  standing permits  the f a b r i c a t i o n successful  the i n t e r c o n n e c t i o n  of  gate  utilize some second  i s a  Programmable  as  "glue  other  67,  circuitry"  circuit  shown  i n Figure  first  array  product plane require As  no  stated  tically  to  distributed  the  vantages  include  logic array  disadvantage  i t i s rare has a l s o  to  been  standardization  state  The  arrays  and  second  and t h e i r  array  speed  PLA's  structure often  function. the  The  required  i s called  t h e OR  f o r output.  and d e n s i t y  c a n be  used  o f t r a n s i s t o r s as  i t forms  products  mapping  f o r c o n t r o l of  of products and  of  a r e most  machines  two  of  means  circuit  7 9 ] . PLA's  plane  chapter  a  regular  a sum  sum  arrays  poor  (SLA) a r e a  design  except  PLA's  beginning  f o r layout  PLA's  a r e good.  generated  automa-  [LANG 7 9 ] .  throughout  of  just  i n this  t h e PLA  ization  is  routing  software  programmable  similar  the desired  earlier  by  t h e AND  the inputs.  internal  Structured to  4, a n d p e r f o r m s  from  i t forms  COOK  a  A PLA c o n t a i n s  i s called  terms  onto  or as f i n i t e  blocks.  main  a v a i l a b l e . There  (PLA) p r o v i d e  functions 75,  tools  because  of  structure  [SCHOFIELD 8 1 ] .  arrays  FLEISHER  8 1 ] . The  the lack  arrays  logic  boolean  [WEINBERGER  about  regular  routing  density  of the gates  of gate  and  [WERNER  circuit  expressed  sources  irregular  masks  low  100 p e r c e n t  concern  The h i g h l y  use of placement  of  arrays  process.  [PATIL  that  gates density  79, SMITH  storage  the array. and  elements  Advantages higher  and a l a c k  t o u s e t h e SLA. I n t e l 15  relatively  new  8 2 ] . The  better  functionality.  uses  SLA i s  ( f l i p - f l o p s ) are  include  of design  approach  aids.  utilDisad-  Industry  an SLA on t h e i A P X  432  computer  favorable  [BAYLISS  results  81]  [GOATES  and  Boeing  has  done  an  evaluation  with  82].  OR plane  A N D plane >  VDD VDD  ( K M  'iH -* -1  •iH -* -1  £ 1 "«4 2,' |f - Phase 2 Phase 1 -  z-,  Figure  The design  design  o f PC  of  4.  Programmable  IC's w i t h  a l i b r a r y of standard  from  many  his  effort  provide gate the  of  the  Is good  arrays.  and  arrays  layout  spent  fabrication  are achieved  the  however  the  cell  details.  16  i s provided  The  modules.  fully  must  achieved  of  customby  design  i n one  and  because be  of  cells  approach  cycle  l i b r a r i e s and pitch  majority  Standard  custom  savings  f i x the c e l l  to the  therefore i s divorced  i n the design  fabrication  Some s y s t e m s  designer  a l l of the masks  are not p o s s i b l e . Standard  greatly.  The  i n t e r c o n n e c t i n g the  modules  therefore  circuits.  between  Array  c e l l s i s analogous  f u n c t i o n s and  and  compromise  Savings  predesigned  ized  vary  a  standard  b o a r d s w i t h TTL  with  Logic  z,  gate tools  dimension  only  whereas  others  f i x both  confined  to predefined  complete  wiring  design  i s that  library  with  One  to achieve  several  choices  disadvantage  density  implementations  i s that a standard  cell  library  requires  a  cell large  function. For may  locations.  require Another  c a n be v e r y  are widely  has  standard  of s i t u a t i o n s  output  cells  the designer  of each  and  Standard  i s sometimes  with  one  input  to purchase.  cell  times  of the problems  routing i n a variety of  Wiring  and o t h e r  good  multiple cell  efficient  sive  channels  freedom.  example,  dimensions.  used  by  expen-  industry  [HAYDAMACK 8 1 ] .  Fully  custom  and  the talents  and  high  cost  approach  ware  language  CAD  fully  The a d v a n t a g e s  Fully  volume  profitable. custom  by t h e d e s i g n  of course  custom  circuits  Referring design  are high  design that  back  rules  density  are the high  i s u s u a l l y the  c a n make  the i n -  to the e a r l i e r  i s equivalent  to  soft-  assembly  programming.  Tools  An A  f o r high  density  only  The d i s a d v a n t a g e s  and debugging.  taken  analogy,  i s constrained  of the designer.  performance.  of design  creased  design  overview  of a complete  d i s c u s s i o n of each  therefore  tool  CAD s y s t e m  i n detail  i s a  i s shown i n F i g u r e thesis  t h e f u n c t i o n s and f e a t u r e s of t h e t o o l s  summari zed.  17  5.  unto  itself,  will  only  be  FUNCTIONAL  < SPEC —^  PHYSICAL  ELECTRICAL  LOGICAL  siliconN compiler )~  <  Interactive\_ graphics J  ^-  ]_/" functional V . \,f logic "V tfelectrical V_ ^/algorithmic ^"l simulator p "^simulator ^simulator J~ ^\ layout J  digitizer ^—5  K  placement & \\ routing )'  jf design rule y checker  <  electric rule/ checker  circuit A/ (extractor  <  >r  testability\_ analysis J  Figure  5.  CAD  System 18  Overview  VCHIP  Common  tools  design  include  ithmic  layout  silicon  compiler.  ed  on  layout  masks), this  digitizers,  of  the  tools  physical  the  use  placement  Synthesis  however,  at  synthesis  graphics  and  have  level  silicon  the  editors,  routing  is a  recent  and  the  concentrat-  representation  compiler  of  algor-  tools,  traditionally  of  stage  ( i . e . the  exception  to  rule.  directly  from  method  entry,  reason  than  there  cannot  be  reserved  an  for are  up  for  for editing  on  suppliers ranging  enter  the  coordinates  hand-drawing compared used  to  of  [NEWTON  there  work  s t a t i o n s and  the  designers  data  are  also  seem  masks.  Although  graphics  data  AVENIER  83].  more  IC  designers  the  stations  therefore  The  Interactive graphics  they to  81,  usually  entry.  masks a f t e r  vertices  interactive  that  bulk  the  of  have been e n t e r e d  prefer  doing  their  is  via a  initial  paper.  such from  approaches symbolic,  is  graphics  Many  to  commonly  this  Interactive  to  e d i t o r s are  Applicon,  $50,000  and  designer  graphics  as  to  Avera,  $450,000  i n t e r a c t i v e  standard  cells.  layout  systems  Geometric  lating  used  enlarged  s t i l l  tied  digitizer. layouts  are  is primitive  i t is  main  The  for  interactive  programs,  Digitizers  this  available  is  provided  geometric  shapes  with such  available  Calma  [WERNER  graphics  are a  19  Mentor 83].  layout  essentially  variety as  and  MOVE  of and  from  The are  a variety with  ROTATE.  prices  three  main  geometric,  drawing  commands  of  for  machines. manipu-  Often  more  powerful some  o p e r a t i o n s such  axis  systems  are provided  require  validation information  Symbolic superfluous symbolic  i s usually  detail  no  the geometric  from  the designer  functional  [BLACK  layout  electrical  by  81].  layout but the use of  "Sticks"  i s a  i n the design of  of displayed d e t a i l  of the c i r c u i t  per-  a t one t i m e  and  therefore  yields  Structural  a n d b e h a v i o r a l i n f o r m a t i o n c a n be made i n h e r e n t t o t h e  symbols tasks.  which Most  relative only  perspective of the c i r c u i t .  therefore simplifies  symbolic  grid.  layout  Fixed  at specific  possible  a better overall  or  t h e mask  was u s e d  The e c o n o m y  t o see more  about  f o r e v a l u a t i o n and  the designer  and one w h i c h  circuit.  tools  also generate  i s hidden  approach,  palette  a cell  data.  r e p r e s e n t a t i o n s f o r components  colour  mits  with  processing  layout systems  common s y m b o l i c the  post  there  entered  to stretch  [HEWLETT-PACKARD 8 1 ] . G e o m e t r i c  complex  because  as t h e a b i l i t y  design  grid rule  more  flexible  then  run to minimize  grid  t h e e v a l u a t i o n and  systems systems  permit  points which violations.  placement  on e i t h e r placement  are chosen  Relative  of symbols  the area  operate  grid  violating  a fixed  or  of symbols  t o e l i m i n a t e any systems  and a c o m p a c t i o n  without  validation  permit  a  program i s  any d e s i g n  rules  [NEWTON 8 1 B ] .  Standard ability which design  cell  to place  layout  systems  a n d move a r o u n d  a r e t r e a t e d as b l a c k cells  checking  using  f o rdesign  provide  previously designed  boxes. A very  a geometric violations  or symbolic the c e l l 20  the designer  with the circuits  common a p p r o a c h layout  system.  i s fabricated  i sto After  and c h a r a c -  terized.  The  c e l l  can  then  be  archived  for  use  by  other  des i g n e r s .  Algorithmic require  the  language include  designer  [LANG  the  examples  will  inherent  to  be  repeats  and  a  main  data  elegant  A simple can  i s that  between  the  can  aids  and  and  placement  are  building  blocks  i t s syntax of  for  use  by  designer  of  regular  large  i s the  be  embedded  text  editor  can  be  used  hardware  output.  is  p l o t and  parameterized this  the  thus  steps  low  can  for  arrays  that  system  used  and  structures  i n a loop  advantage  to  algorith-  the  arbitrarily  cost in  for  The  any  input  need  for  eliminated.  The  difficult input  nodes r a t h e r  to  see  the  text. Liberal than  absolute  problem.  algorithms  are  a c t i v e l y researched  problem  used  The  be  AHF  commands  was  control  i t i s sometimes  routing  of  advantage  parameters  output  alleviate  on  and  programming  implementations  the  systems.  a  and  available  changing  plotter  Placement  circuit  for  with  language  main  by  c o m m e n t s and  coordinates  The  The  i n t e r a c t i v e graphics  correlation  layout  later.  are  PLAP,  details  ROM's s i n c e  disadvantage  of  more  the  LAP,  Examples  algorithmic  PLA's and  layout  standard  usage  83].  and  of  as  layout  as  language.  expensive  a l l  the  a p r i m i t i v e c e l l . Another  algorithmic  available  presented  such  HEUFT  An  palette  makes  created  82,  PLA.  language  such  of  and  the  structures  and  express  that  This  be  to  is  80].  can  programs  CHENG  colour  layout  [HON  79,  W I R E , BOX,  design  mic  layout  involves subject 21  [PREAS  finding to  some  extremely 79,  optimal  spacing  and  valuable  SOUKUP  locations  81]. for  interconnect  constraints. length The  of  the  first  second  A  typical  is  is  modifications  When  to  to  there  are  that  vertical  is  only  of  the  and  a  fixed  number  BURSTEIN  of  computation  employed.  Specialized  gested  speed  be  the  silicon  as  lers  geometric level  82A].  software  dimensional dimensional  and  routing  step  process.  two  placement  i t by  and  the  making  local  span  of  generate  and  a l l levels  over  the  Proponents  and  assembly  compilers.  of  point  language  trivial  integrated 22  tracks  routing are  has  i n CAD  of  been  the  and  at  sug-  that  promises ideal  representation  as  to  are  often  s u c c e s s f u l . The  data  feel  achieve  83].  feasibility  Opponents  therefore  complexity  mask  and  separate  i s to  hardware  [HONG  i f i t is  the  to  heuristics  concept  the  assumed  horizontal  Placement  processing  tool  confined  minimum  solution  route  interconnects,  common g o a l  hence  i s a new  for  are  The  to  It is usually  a f u n c t i o n a l d e s c r i p t i o n of  controversy  layout  a  and  routing  would  automatically  [WERNER  total  necessary  blocks.  tracks.  parallel  design  input  considerable  on  i t is  83].  vertical  compiler  ultimate  accepting then  the  compiler  a  "good"  available  with  intensive  up  the  is  improve  layers  interconnections  silicon  i n i t i a l  h o r i z o n t a l segments  all  to  an  complete  two  [YOSHIMURA 82,  The  Placement  between c i r c u i t  and  minimize  81].  layers  to  to  iteratively  [GOTO  interconnections  very  find  placement  that  is  interconnections.  step  step  goal  the  circuit  output. of  that  compared  silicon  circuits.  success software to  They  and  There  analogies the  by  the argue  is  compibetween of  high  is  one  multithat  a  useful  silicon  intelligence mented,  be  problem.  however,  usually 81,  compiler  produce  SHIVA  83].  viewed  The  as  The  a  fabrication  as  simulators, therefore  the cal.  that  In  sentation ential well at  the  buted slow exact  the  state  but  the  that  University  because  employ  and  imple-  architectures 81,  and  THOMAS  earlier  can  compiler.  every  time  possible  means  Evaluation tools electric  rule  of  such  checkers  of  s i m u l a t o r s are  in: functional,  perform  of  of  logical,  simulators  a  less  simulation  operate set  of  the  or  run  detailed  faster  are  by  electriand  analysis.  techniques  the  each  node  electrical nonlinear  circuit.  [VLADIMIRESCU  California  heavy  the  coupled  describe  simulator of  at  at  2000 i n s t a l l a t i o n s . of  characterized  Two  available  81].  solve  circuit  over  been  turn-around  is correct.  higher-level  reviews  equations  to  lengthy to  have  artificial  discussed  silicon  checkers,  operate  simulators  and  known  design  they  HACHTEL  Circuit  his  classes  memory  comprehensive 83,  designer  main  that  less  [RUEHLI  sometimes  the  [TRIMBERGER  generator  simplified  rule  specific  designs  PLA  solve  compilers  to  optimal  to  essential.  general  consume  limited  the  design  three  domain  and  have  silicon  automated  requires  guaranteeing  The  than  cost  of  are  are  successful  high  first  Several  they  less  would  Circuit  computation for  each 23  and  It  is  was  has  reprediffer-  the  to  been  solve  increment.  most  developed distri-  s i m u l a t o r s tend  required  time  of  ordinary  SPICE  80].  Berkeley  level  to  for  SPICE,  be the for  example,  running  /timepoint run  on an I B M 3 7 0 / 1 6 8  [NEWTON 8 1 B ] ,  on c i r c u i t s  accuracy the  used  dependent  batch  containing  of a simulator  parameters  turn  preting  t h e most  interesting  than  i s strongly  One m u s t  to note  that  i t c a n be u s e d  a n d may v a r y  from  models.  are i n  from  when  Although  one  inter-  SPICE i s  domain  are usually  industrial  The  the f a b r i c a t i o n  i n the public  modifications  i n an  nodes.  These p a r a m e t e r s  someone  CAD p r o g r a m  rarely  on t h e a c c u r a c y o f  be c o n s e r v a t i v e  the device  refined  ms/device/c1ock  a few hundred  models.  unless  4  are therefore  dependent  therefore  results  i s supporting  probably  more  i n the device  simulation  facility  simulations  on t h e f a b r i c a t i o n f a c i l i t y  to the next.  before  Circuit  requires  setting  i t  i s  required  [DWIVEDI  82,  HEWLETT-PACKARD 8 0 ] .  Logic fixed  simulators  number o f node s t a t e s  impedance, be  three  where  and u n d e f i n e d .  orders  based  devices take  this  whose  fact  tion  account  most  communication  s i m u l a t o r s can  logic  logic  gate  and t h e newer  logic  abstract  are described  language  a  l o g i c - z e r o , high  circuit  79].E a r l y  only  simulators model.  MOS  simulators  [BRYANT 8 1 ] .  simulators  i s of course  global  over  [NEWTON  are bidirectional into  functions  behavioral  The s p e e d u p  on t h e u n i d i r e c t i o n a l b o o l e a n  however  by p e r m i t t i n g  such as l o g i c - o n e ,  of magnitude  Functional  or  s i m p l i f y the analysis  [HEPLER useful  the c i r c u i t  into  modules  description  language  81]. Functional  simula-  by a h a r d w a r e 7 9 , RAETH  i n the early  and a l g o r i t h m s  verified. 24  used  stages  of design  i n the c i r c u i t  when  must  be  The the  complexity  performance  reduce array  the  technique  is  combine  circuit feedback timing, well  i s the  and  solution can  of  mixed  functional  be  t a b l e s can  device  types  of  analysis  be  f o r areas  of  tempo-  avoided. A very [NEWTON 7 8 ] .  areas of  prom-  The  one  the  idea  package:  t i m i n g or  with  to  Specialized  Simulation  critical  for  improving  exploited  simulators into  t h a t have  analysis  be  models.  employed. can  on  less  strong  critical  circuit  that  are  understood.  rule  description tions.  The  example, have bloat and  of  checkers  the  masks  designer two  been  wires  intended  a m a s k by another  between  an  improve  and  accept  output  still  with  insufficient  to  decide  connect.  A  amount e q u a l  on  a  must  the  violations  the  (DRC)  l a y e r . T h e n by  polygons  encroachment  two  to the  mask  81].  caused  of  clearance DRC  spacing  one  a d i s t a n c e . H i e r a r c h y i n the of  the  25  same  rule  the may  or  AND  can  can  can  For  may  not  is  to  between  operations  easily  techniques  circuit  viola-  error.  required  that are  cell  geometric  algorithm  boolean  polygons  the  design  o f DRC's. P o l y g o n s  comparison  checking  what  Several  too great  repetitive  of  layers  to a v o i d  avoid  input  list  performing  [TUCKER  performance  as  typical  windowed  to  much w o r k  mode s i m u l a t o r  for areas logic  of  a circuit  a l l three  loops,  Design  to  areas  analysis  motivated  s i m u l a t o r s . Lookup  hardware  inactive  ising to  V L S I has  repetitive  processing  rarily  it  of  of  be  detect are  used  sorted  separated be  [WHITNEY  and by  exploited 81].  Electric  rule  checkers  electrical  violations  terminated  wires,  can  as  which  also  for  Validation greatest  level  extractor  accepts  electrical tion  can  or  logical  then  be  evaluation  stage  design  is  loop  evaluation  of  thus  was  the  In  the  faults  complexity  and  that  closed by  and  which  the  another  possible  observation  of  widths  sure  to  appear  after  the  specific general  to  the  testing  and  how  probe  a  this he  26  provide  the  A  circuit  outputs  This  used  descrip-  during  the  compared.  The  that  [TUCKER  facet  almost  the 81].  of  valida-  and  deduce  operation.  to  an  Today's  impossible. diagnose A  A  faults  review  of  into  two  techniques  are  83].  and  Examples  ERC  and  iteration.  techniques  chip  the  circuit  plans  first  structured.  particular problem.  to  [WILLIAMS  testability hoc  available  expectations  important  make  that  is available  is  possibility  i t s internal  of  ad  data  results any  designer's  is  line  incorrect  then  circuit.  the  un-  and  correct.  mask  avoids  aware  categories:  is  simulator  design  gates,  extractors  design  same  common  81].  into  acutely  for  data  the  the  of  floating  are  [CORBIN  geometric  be  Design  variety  ground,  which  a  must  testability  as  and  circuit  designer are  a  d e s c r i p t i o n of  i t was  small  and  as  the  analysis  past from  such  the  biased  Testability tion.  fed  such  power  clocks  input  for  additional information  confidence as  masks  mismatches  tools of  If  are  type  look  between  ratios.  buses  check  the  shorts  pull-up/pull-down such  in  (ERC)  The do  are ad  not  include  divided hoc  attempt  to  partitioning  solve the  the chip  into  modules  points of  for  be  individually tested,  (see  f o r example  i n t e r n a l buses  for  stimulating  signal  ad to  hoc the  method  circuit  is  and  [CANEPA the  signature then  providing  83]),  circuit  if  the  making  modules.  analysis  checks  and  test  which  use  Another  applies  compressed  a  response  correct.  Structured testability that  can  shift the  can  probes  popular  is  that  problem.  halt  out  the  circuit  logic  techniques  the  The  the  rather  problem  than  the  state  machine.  common  fault  is  to  a  detect  and  software  [CANEPA  The  Mead  Conway  The however, Conway  advances  are  when  one  had  design  on was  occurred  unpublished.  In  for  is  to  shift  reduced  to  faults  extra  a  of  [MERCER  vector  82].  By  assumes  board  or  halting  combinatorial  debugging  80].  general circuitry  known  [TSUI  device  on  add  more  debugging  approach  "stuck-at"  the  in  analysis  incorporating  a  that  and  then  Finally self  dynamic the  most  adds  cir-  some  test  of  the  circuitry  83].  Revolution  connotations  have  circuit  IC's  then  Another  a l l such  complex  solve  intractability  single  new  and  is  to  approach  and  state  finite  cuitry  usual  circuit  current  attempt  of  the  considers IC  in the  the  design  for  many  word  impact  i t is years  industry f a l l  revolution  of  an a  and 1 978 27  that apt  black  distasteful,  Carver  Mead  description. magic  therefore Lynn  are  were  Conway  art  and  Integrated  because  proprietary of  Lynn  Xerox  most and PARC  offered  a VLSI  course  resulted  student course  text  The sities based  book  results  being  have  What removed  by  design  have  a variety  A more  The of  c o r r e c t l y . The  o f Mead  a n d Conway's  complete  then  d i d Mead  o u t many  of t h i s  history i s  rules,  they (MPC),  83]. A  wide  available  and i n t i m i d a t i o n  introduced Caltech  a simplified  courses Canadian  Centre  VLSI  which  (VLSIIC) of  short  Several  new  Design,  and  13 r e c e n t  start-up  [SZIROM 8 3 ] .  actually from  do?  Mead  IC d e s i g n  and  by  p r o c e s s . A t t h e same topics  the s i l i c o n  transistor  28  univer-  courses  selection  Design,  f r u i t f u l  methodology.  8 2 ] , Many  to industry.  Intermediate MOS  60  design  design  are at least  and Conway  the design  over  Implementation  IC s e r v i c e s  potentially  VLSI  are offering  up. T h e r e  custom  a r e now  offer  Computer-Aided  sprung  the mystery  chip  a r e now  There  [FAIRBAIRN  the VLSI [GALE  IEEE  offering  specifically  design  79].  8 0 ] . The p u b l i c a t i o n  that  text  U.B.C.,  University  and f o r m a l i z i n g  pointed  containing  version  [MEAD  amazing.  and Conway  including  Integration  design  been  including  on V L S I  companies  [CONWAY  3 functioned  a revolution.  coordinated  Queen's  journals  chip  at least  Systems"  a t M.I.T.  [CONWAY 8 1 ] .  on t h e Mead  project  NMOS  i n t h e U.S. a n d E u r o p e  courses  ing  course  was a p r e - p u b l i s h e d  to VLSI  universities,  at  of which  i n 1979 s t a r t e d  available  are  design  i n a custom  designs  "Introduction book  system  simplifytime  of research.  foundry,  Form model,  (CIF), and a  Conway  the  they More  multi-  simplified structured  A  silicon  foundry  grated  circuit  from  [JANSEN afford  81]. the  dollars)  with  have  signer  does  place  led  foundry  now  cost  about  minimum the  representing reduced. GTE  i n P h o e n i x and  in  quantities  of  as  should  cost  and  dollars.  MPC's prior  distribution  costs  projects  a minimum  that  and to  de-  fabricabloats  the  are  at  or  commonleast  lots  38  of  10-  foundries  re-  dollars.  designers  this  the  or  specialize  minimum of  that  This in  has  inter-  [COHEN  82].  By  expenditure  can  be  thesis  was  fabricated  approximately  42  dollars  each  is a  amortizing  mask  10,000.  foundry 10  foundry  most  100,000  and  part  silicon  Minimum  however,  brokers  the  million  polarity,  There  cannot  15  analogous  of  foundries  multi-project chip  example,  designs  dollars,  silicon  designed  ideal  party  that  mask m a k i n g  film.  expenditure  silicon  chip  by  making  10,000  users  (approx.  [WERNER 8 2 B ] ,  several designers  The  The  is entirely  inte-  independent  i n t e r f a c e so  m a r k s , mask  operating  of  An  with  photographic  yearly  formation  between  concerned  concept  an  equipment  standardized be  f a b r i c a t e s an  those  capability.  fiducial  foundries  facing  then  as  of  a  to  such  to  processing  wafers  quire  have  by  provides  fabrication  and  that  supplied  foundry  circuit  a clean  The  silicon 20  of  custom  details  shrinks.  cost  not  facility  a design  silicon  high  should  tion  The  is a  can  (MPC)  over be  to when  require  placed run  wafers  and  return  University). 29  on  to to  [HON  80].  a 5000 m i c r o n  costs  someone  fabrication, the  of  several designs  10,000 d o l l a r do  method  each  look  (hence  square  designer  coordinate after the  If, for  and  only  chip 1000  pack  the  packaging  and  VLSIIC  at  Queen's  Caltech language  Intermediate  designer  (including CIF  cells  which  applied and  and foundry  as  define  supports  c a n be l a t e r  therefore  c a n be  called  Finally,  read  are indeed  mask  with text  graphics  circuits  i n t e r f a c e format  i n Figure  hierarchy  to i t . CIF i s i n p l a i n  computers.  shown  U.B.C.) a n d f o u n d r i e s  CIF a l s o  of i n t e g r a t e d  t o be a s t a n d a r d  primitives include  polygon.  (CIF)i s a low-level  f o r s p e c i f y i n g the geometry  8 0 ] . CIF was d e s i g n e d the  Form  7.  Most  using  l a y e r , draw  appropriate  format,  CIF i s independent  by  schools  and  draw  one t o d e f i n e transformations  as shown  and understood  between  CIF. Typical  wire,  by p e r m i t t i n g  [HON  i n Figure  both  of f a b r i c a t i o n  people  6, and  processes.  D S 2 ; 9 P a d B l a n k ; ( d e f i n e s y m b o l #2 w i t h n a m e P a d B l a n k ) (4 i t e m s ) ; ( b o u n d i n g b o x 0,0 t o 2 6 5 0 0 , - 2 6 5 0 0 ) ; L NM; B L 2 6 5 0 0 W 2 0 0 0 C 1 3 2 5 0 , - 1 0 0 0 ; (Vdd l i n e ) ; L NM; B L 2 0 5 0 0 W 2 0 0 0 C 1 3 2 5 0 , - 2 5 5 0 0 ; (ground l i n e ) ; L NM; B L 1 3 5 0 0 W 1 3 5 0 0 C 1 3 2 5 0 , - 1 3 2 5 0 ; ( m e t a l p a d ) ; L NG; B L 1 1 5 0 0 W 1 1 5 0 0 C 1 3 2 5 0 , - 1 3 2 5 0 ; ( o v e r g l a s s window) DF; (end d e f i n i t i o n ) DS 1 1 ; 9 P a d S a m p l e ; ( e x a m p l e i n p u t p a d ) c 6 R o, 1 T 0 , - 1 0 6 0 0 0 ; c 7 R o, 1 T 0 , - 7 9 5 0 0 ; c 5 R o, 1 T 0 , - 5 3 0 0 0 ; c 2 R o, 1 T 0 , - 2 6 5 0 0 ; L NM ; B L 7 7 7 5 0 W 2 0 0 0 C 3 8 8 7 5 , - 1 0 5 0 0 0 ; B L 10250 W 2000 C 24875, - 6 0 5 0 0 ; B L 2000 W 49500 C 2 5 5 0 0 , - 2 4 7 5 0 ; B L 28750 W 2000 C 38875, -1000; B L 14250 W 2000 C 3 1 6 2 5 , -102000; B L 2000 W 97000 C 31000, - 5 1 5 0 0 ; c 9 R o, -1 T 7 7 7 5 0 , - 5 3 0 0 0 ; C 8 R o, -1 T 7 7 7 5 0 , - 2 6 5 0 0 ; B L 2000 W 11250 C 37750, - 9 7 3 7 5 ; B L 6500 W 2000 C 4 0 0 0 0 , -92750; C 4 R o, -1 T 7 7 7 5 0 , - 7 9 5 0 0 ; C 10 E. 0 1 T 7 7 7 5 0 , - 7 9 5 0 0 ; B L 2000 W 103000 C 52250, -51500;  Figure  6.  Example  of Caltech  30  Intermediate  Form  [HON 8 0 ]  Designer  r  Standard Cells  Place & Route  Design Svqcm  Design Svstem  Design System  1  Interactive Graphical  Artwork I anguage  I a> out  eg  Design  Design  Data Base  Data Rase  Ocsicn System Text Fditor  t  LAP  Design Data Rase  C I F Output  C I T Output  O F Output  Check Plot  Fabrication  Fabrication  Mann PC  F-Bcam  Design Rule Check  Fxposurc  I Reticles  I  Fsnosure  T  t  r  Wafers  Wafers  J Fabricator  Figure  7.  Caltech  Intermediate 31  Form  Relationships  [HON  80]  Simplified and  design  Conway d e s i g n  fied  by  minimum  of geometric  normally  tend  ing  to squeeze  tight  facility  patterns  t o be q u i t e every  tolerances  that  they  are hard  violations. change  as  redesign third  The s e c o n d  be r e q u i r e d  problem  problem  i s that  masks.  particularly  Design  i f the designer  cases,  each  Under  requir-  to check f o r  case  rules  and t h e r e f o r e  complete  of the improvements.  rules  are very  C o n w a y b e l i e v e t h a t t h e d e s i g n r u l e s s h o u l d be r e l a x e d a n d be  silicon  gate  NMOS. I n a d d i t i o n ,  such  a l l rules  quantity  a fundamental  parameter  i n any f a b r i c a t i o n  feature  and they  made  quantity.  Lambda  based  e x a m p l e , i f one w i s h e s then  a 2 lambda  the  event  that  the  other.  fabrication they  should  spacing each w i r e  Since  Mead  lambda  design  to guarantee  process  that  rules  and a r e r e l a x e d  reasonably  a r e based to avoid  load of a that  of  this  sense.  For  do n o t c r o s s separation i n  1 lambda e r r o r  transportable 32  logical  to ensure  Mead  i s the minimum  two w i r e s  t h e maximum  noted  t o one h a l f  make  m u s t be p r o v i d e d moves  be i n t e r m s  and Conway  equal  rules  the s i m p l i f i e d  processes be  lambda.  as d e p l e t i o n  should  dimensionless  size  called  process  facility.  on  and  fabrication  fabrication  dependent  A  individual  on a g e n e r i c  of each  a  tend to  the  based  characteristics  special  advantage  case  or  with complex design rules i s  improves,  special  to  rules  out of the l a y o u t .  special  i s that  to take  are speci-  extensions,  and i t i s d i f f i c u l t  problem  the technology  may  on a n d b e t w e e n  a r e many  to learn  rules  separations,  possible micron  a d e s i g n r u l e . The f i r s t  o f t h e Mead  and c o n s t r a i n the design  complex,  there  cornerstone  [LYON 8 1 ] . D e s i g n  ( o r maximum) w i d t h s ,  overlaps  such  are another  philosophy  the f a b r i c a t i o n  certain  wishes  rules  on a  towards generic  special  between  cases  foundries.  Finally, resubmit course  as g e o m e t r i e s the o r i g i n a l  scale for  fabrication  mitted  unchanged  1.65 m i c r o n s  will  It  tists is  Mead  transistor enough  transistor  sion  that  layer.  through  [ELMASRY 8 3 ] .  the majority  a device  designing  o f work  by c o m p u t e r  model  o f t h e MOS  physics  background  wire  equals  voltage  current  crosses  the d i f f u -  t h e charge  f o r an e l e c t r o n t o t r a v e l  to the drain.  A simple  expression  induced  charge  and u s i n g i salso  thechannel i s found  from the  f o r the transit  time i s  l e n g t h a n d t h e e l e c t r o n v e l o c i t y . The  by t r e a t i n g  the definition presented  induced  d i v i d e d by t h e t r a n s i t  required  from  scien-  for this  vo1tage-contro11ed  the device  by  i n t e g r a t e d c i r c u i t s . The  a polysilicon  by t h e a p p l i e d g a t e  f o r CMOS  time  derived  model  when  technology  a simplified  as a  =  specified f o r  One o f t h e r e a s o n s  lacking  i s described  Current  or average  source  tor  people  i s formed  the channel  time  gave  that  presented  resub-  lambda  specified  has been p e r f o r m e d  information to begin  switch  in  which  were o r i g i n a l l y  engineers.  a n d Conway  indeed  submitted  however,  r e c e n t l y been  t o note  and n o t e l e c t r i c a l  do  pads  o f as y e t unknown m a g n i t u d e .  82J and f o r b i p o l a r  on V L S I d e s i g n  rules  I t c a n now be  = 2.0 m i c r o n s ,  rules  have  i s interesting  that  MOS  lambda  rules  8 2 , GRISWOLD  universities  simplified  This of  as bonding  p a l e t t e was o r i g i n a l l y  require a redesign  NMOS b u t s i m i l a r  to simply  specified.  f e a t u r e s such  shows t h a t  simplified  be a b l e  a new l a m b d a  l a m b d a = 2.5 m i c r o n s .  with  a n d Conway's  [SNYDER  with  The c o l o u r  with  one s h o u l d  b e c a u s e some  Experience  to a degree.  Mead  design  has l i m i t a t i o n s  do n o t s c a l e .  decrease  t h e gate  of capacitance.  i n t h e Mead 33  as a s i m p l e A second  a n d Conway  capaci-  MOS  book  device  by C a r l o  Sequin. as  This  a fluid  fluid  tal  model  and p o t e n t i a l  can  Mead  and Conway  time  unit  of  make c r u d e  refer  the  time.  design  have  which  the  as " t h e f u n d a m e n -  system".  A l l delays  expressed  as m u l t i p l e s  required for a  transistor  Using  been  methodology  this  twice  simple  performance  hierarchy  and  tran-  i t s size  idea  without  have  been  Mead and Conway  feel  hierarchically  decomposed  transfer promote  nonoverlapping dynamic  part  discussed  one  can  elaborate  into  that  The  actually  attack  earlier  by  finite  circuitry  difficulty  works  34  the the  exploitaproblems  8 1 ] . H i e r a r c h y and  combinations  controlled  scheme.  for introducing a  i n this  processing systems  the use of dynamic  clock  to  [TRIMBERGER  that d i g i t a l  paths,  touted  i s essentially  regularity  regularity  already  widely  which  with complex designs  plex  c a n be  of the c i r c u i t  associated  also  time  integrated  of a another  the t r a n s i t  and Conway  structured  They  charge  tools.  Mead  register  by d e s c r i b i n g  or w e l l s i n t o  to the t r a n s i t  entire  the gate  estimates  simulation  of  as d e p r e s s i o n s  time. For example, the time  to charge  two t i m e s  tion  to i n t u i t i o n  the i n t e g r a t e d c i r c u i t  of t h e t r a n s i t sistor  more  accumulate.  throughout  is  appeals  of  should  be  register-to-  state with  chapter.  machines.  a two  i n designing  i s , however, not  a  phase com-  addressed.  CHAPTER  3:  S E L E C T I O N AND  Background  In  keeping  with  circuit  electronics  read-only  to  memory  aperture  our  we  firms.  suggested  thetic  OF  A  CUSTOM C H I P  PROJECT  Information  integrated  were  JUSTIFICATION  desire  to  solicited  Several us.  radar  advice  a  and  included  in a rail  processing  a  car  novel  yet  impetus  i n t e r e s t i n g and  These  f o r use  design  from  promising  low  power  useful  projects  programmable  l o c a t i o n system,  element,  and  local  a colour  a  syn-  palette  circuit.  Our gested  decision by  to  Microtel  several  factors.  foundry.  Second,  function  has  therefore tation  but  palette and than while a  a  other  to  the  yet  with  Research  MPR  of  this  cannot  be  82],  Third,  circuitry  which  targeted  digital for  our  purpose  graphics  MPR  circuit  do  35  the a  to  a  truly  has  to  system,  colour  palette  chip,  combines  i t s novelty.  important  colour  and  implemen-  integrated  the  by  silicon  single  palette  sug-  a  know of a h y b r i d  adds  Telidon  systems.  influenced  f o r a more i n t e r e s t i n g  and  that  was access  onto  colour  makes  project  knowledge  considered the  palette  (MPR)  o f f e r us  integrated  circuit,  the  colour Ltd.  could  best been  the  i t i s a n o v e l p r o j e c t . We  purely  general  Pacific First,  not  [INTECH  analog  proceed  colour digital design Finally,  palette  is  applications  in  The  Colour  Palette  Given mix  an  only  the  three  Infinite  a  finite  colour  primary  number of number  palette  monitor  Function  serves  replaces  the  hues,  three each  the  DAC's. D a t a  presented one  of  the  bits  in  which  equals  In  select  The  from  2**(3*n)  one  into  i t to  array  of  Is  DAC.  to  that  room  for  that  a  a  colour  registers  be  a power colour  of  hues. 36  port  (DAC). the  their  The  monitor  resultant  pattern  that  is  through  processor.  Pixel  data  other  which  selects  port  drive  of  i t s data into  three  Typically n one  of  the  2 and  palette  array.  is normally  permits  log  m  is  n  each  unique  one  For  the  equals  4096 any  is  equal-  r e s o l u t i o n , then  a v a i l a b l e at  in  into  register field  colours.  m c o l o u r s , each of w h i c h can  dual  registers  divided  are  of  bit  the  specify  of  the  and  If each  2**(3*n)  colours  number  different  can  electronic  are  one  the  the  r e g i s t e r can  of  then,  the  by  system  causes  to  colour  determined  f o r each  each  i s chosen  summary  each  DAC's h a v e n b i t s  specify  the  m  one  number  except  palette  connected  c o n t r o l l e r to  i f the  case  m,  reasons 16.  can  is  graphics  register in  w i d e , and  colours.  a  CRT  bit fields,  register 4  the  by  colour  is written  r e g i s t e r s and  DAC's. E a c h width  therefore  ports by  a  I n t e n s i t y of  input  the  of  DAC  Is  of  An  digital-to-analog converters  hue  one  time.  artist  canvas.  combined to  one  function  and  The  an  p a l e t t e has  similar  array  guns.  any  palette  his  a  register  colour  however, at  components  of  his  colours  main  output  on  of  The  analog  colours  time  obvious equal  to  bits  to  be c h o s e n f r o m a p o o l  of  Colour  Palette  We its  Applications  have e x p l a i n e d  utility?  Assume  the  that  quality  monitor  in  of  i t s pixels.  at  once,  each  colours high The  colours number  are of  colour cally  bits  alter  operation. video  A new graphical  provides  a  pixel  b i t map  a  colour  National  Telidon  Standards  a  is  high  at  the  display a l l  attribute bits. amount  of  solution in  the to  to  same log  time,  In  and  updating  memory. that a l l and  the  m.  colour  palette  one  palette  the  striking a  a  can  is  dramatiinto  animation  register  is  a t t r i b u t e s of  in  a  each  sequick pixel  rewritten.  Potential  important  system  has  w r i t i n g d i f f e r e n t words  w o u l d h a v e t o be  information  12  a complex image  simply  has  standard  and  for  the  exchange  r e c e n t l y e m e r g e d . The  Presentation-Level-Protocol Canadian  not  able  excessive  a p p l i c a t i o n of  P a l e t t e Market  and  an  i s reduced  because  be  require  r e g i s t e r s . Rapid  possible  to  compromise  Given  system  what  d i s p l a y i n g 4096 d i f f e r e n t hues  be  a v a i l a b l e but each  graphics  wanted  can  animation.  Without  of  would  this  important  palette  are  Colour  I f one  pixel  p a l e t t e f u n c t i o n , but  colour  i t s a p p e a r a n c e by  colour  i n the  for  graphics  quences  The  each  s t i l l  a  i s capable  palette  Another  the  that  r e s o l u t i o n system colour  colour  has  Institute  Syntax  (NAPLPS)  been  standardized  ( A N S I ) and 37  the  of  North  evolved by  the  Canadian  text  and  American from  the  American Standards  Association  (CSA)  NAPLPS  play  will  encouraging 83]. to  This  i n turn  by  of  Mode  will  8 3 ] . Many  important  role  people  i n the near  of i n f o r m a t i o n - b a s e d  make  feel  Telidon-like  that  future  products  systems  more  by  [LAX  palatable  public.  rich  colour.  and p o w e r f u l  NAPLPS  the i n t e n s i t i e s  1 and 2 however  features  supports  three  of i t sthree  make u s e o f a c o l o u r  animation  programmed  CBEMA  0 i s the most p r i m i t i v e i n t h a t  specifying  vanced  very  o f t h e many  treatment modes.  a  82,  the production  the general  One  [CSA  by p r o v i d i n g  is  different  a colour  primary  i s selected Modes  supports  c a l l e d BLINK t h a t  the colour  i t s  colour  colours.  p a l e t t e . NAPLPS  a command  to p e r i o d i c a l l y change  o f NAPLPS  palette  ad-  c a n be  register  contents.  Jim review  Fleming, of NAPLPS  specialized 83].  He  time of  NAPLPS  modes  inexpensive  they  of  was  drawback  hardware  on t o s a y , " T h i s designed,  special  would  single chip  of  NAPLPS,  o f modes  that  was  determined  [FLEMING  known a t t h e that  that  c a n be  achieved  be i n c l u d e d " .  This  strongly  implies  colour  palette  when  i n the consumer  Telidon  market.  38  would  have  like  i n a  1 and 2 i s the  i s required  drawback  b u t i t was  states  effects  potential, particularly  NAPLPS, a p p e a r  the authors  a major  palette  goes  the i n c r e d i b l e  these  ket  that  colour  further  that  one  because using that  tremendous  systems,  a  mar-  fueled  by  The  Current  MPR  Microtel colour  and  system  can  in  a be  cm  printed  s ys  integrated  It  considerable  writes CRT  to the  the  the  amount  address  desired  A.  a  discrete  system.  how  colour  occupies  space,  and  obtain  an  component  Schematics  i t fits  This  colour  the  required single uses  contents  port  dual  palette period  into  for  the  palette  costs  about  estimate  contains  palette  9  37  of  cm  by  dollars  the  i s part  the  overall  approximately  We  the  update  the  circuitry of  into  the  the  of a  labor larger  pixel  to  will  array  later  and  the  the  is  associated  microprocessor,  palette  through  register  bit  palette.  see  therefore  map  and  the pre-  Multiplexing  formed  that  which  r e g i s t e r s , and  video  is  with  our  from  is  standard  implementation  eliminates  the  need  for  circuitry.  the  to  increasing  processor  r e g i s t e r updates of  CRT  each  registers  addition  between  the  buses  cycles  the  memory.  port  multiplexing  In  of  because  of  colours  c o n t r o l l e r , which  sents  the  because  has  tem.  multiplexing  to  board  d i f f i c u l t  for assembly  A  ing  showing  circuits,  circuit  is  Ltd.  Telidon  in Appendix  10  costs  current  found  14  parts.  Research  diagram  least  for  its  Implementation  block  at  of  Palette  Pacific  palette  circuit  Colour  monitor. palette  controller  Our  the  and to  circuit  the  occur  CRT  complexity, controller  during  implementation  registers  at  operation. 39  any  time  the  forces  vertical  permits and  multiplex-  the  a l l  blanking processor  asynchronously  to  The  advantages  numerous. count,  It  would  printed  being  chip  As  in  by  i n Figure  are  timing  Appendix  the  B  12  capable  of  generating  provided  and  help  the  the  MPR  reduce  also  cost.  colour  large  cost.  design  improve  the  issue  p a l e t t e has  part  In  parts  MPR's  multiplexing  are  Telidon  the  protect  It could  by  palette circuit  assembly  also  would  A  from  system  discussed  strong  market  itself.  important  time  required final  desired  wide. for  [SCHMIING  side  CRT  and  address  be  contains  buses and  and  the  summarized  signal  here.  definitions  are  16  control  processor. More  de-  available  82].  the  important  nsec. This pixel  is  the  DAC  settling  for  the  analog equals  from  the  CRT  at  time,  which  nsec.  40  i s the  voltages  output 50  number  means t h a t the  data  analog  and  palette  controller  will  appropriate  value,  colour  Separate  the  specifications  accepting  Also  the  specifications  video  the  8  bits  c y c l e t i m e w h i c h i s 180  its  area,  single chip  product  each  important  On  palette  a  reduce  probably  demonstrated  a  shown  circuitry  tailed  would  colour  Palette Specifications  registers,  The  as  as  board  a competitor.  Finally,  potential  Colour  i t  by  performance earlier.  significantly  colour  copied  a single chip  circuit  enough volumes single  of  to  reach  a  pixel  clock  p a l e t t e must controller rate  of  5.56  is defined  within  1/2  LSB  as  be and MHz. the  from  A0-A3  CS' ,A4,A5 E,R/W  processor data hns D0-D4  control signal gen.  processor address decoder  pixel clock  Vref  data buffer  16 x 4 d u a l p o r t RAM  pipeline register  DAC  16 x 4 d u a l p o r t RAM  pipeline register  16 x 4 d u a l p o r t RAM  pipeline register  data buffer  data buffer  video address decoder  X~ P0-P3 p i x e l data  Figure  8.  Colour  Palette 41  Block  Diagram  *  DAC  DAC  red  green  blue  On write  the processor  cycle  time  side  which  i s 500 n s e c .  registers  m u s t be c a p a b l e  MHz.  data  Read  rising for  processor  20 n s e c  Critical higher  must  clock  clock  prior  timing  be  of being  valid  no  and  occurs this  This read  later  edge. W r i t e  to the f a l l i n g  clearly  rate  the important  means t h a t  than  design.  42  and  the palette  150 n s e c  i s valid  of  i s taken  after  at worst  the processor  on t h e v i d e o  fact  i s the read  o r w r i t t e n a t a r a t e of 2  data  edge  number  side into  the case  clock.  because of the account  i n the  CHAPTER 4: THE ISO-CMOS  An  Overview  o f CMOS  Complementary tinguished  from  m e t a l - o x i d e - s i l i c o n (CMOS) t e c h n o l o g y  other  and  n channel  was  i n h e r e n t l y slow  not  justify  circuits  TECHNOLOGY  MOS  devices.  technologies  by t h e p r e s e n c e  of both  F o r many y e a r s  i t was t h o u g h t  that  and w a s t e f u l  i t s extra processing  that  required  became  a self-fulfilling  research  effort  was s p e n t  Two m a i n  a s nMOS d e n s i t i e s  became  a problem. nMOS  CMOS.  Subsequent  almost  as dense.  gate  The  traditional  for  every  technologies  h a s made  CMOS  circuit  device path  consumes  device very  i son i t s c o m p l e m e n t  between  over  since  43  MOS  interest  (nMOS) i n CMOS.  dissipation  complexity  of the high  CMOS  uses  or exceeded as f a s t  that of  a s nMOS a n d  o f a com-  of freedom.  one p c h a n n e l  i n Figure  static  This  power  power  i so f f and there  Vdd and V s s .  81].  the m a j o r i t y of  an e x t r a degree  as shown little  [POSA  nMOS. T h e p r e s e n c e  approach  CMOS  f o r the few  n channel  approached  thedesigner  CMOS d e s i g n  n channel  prophecy  the processing  research  except  properties  increased excessive  Second,  gives  complexity  p  and t h e r e f o r e d i d  l e d t o a renewed  CMOS h a s m a n y a d v a n t a g e s plementary  area  on i m p r o v i n g  factors  First,  performance  of chip  i t s special  viewpoint  technologies.  i s dis-  9. T h i s because  i s thus  device type  of  when one  never  a DC  Figure  CMOS  9.  circuits  transitions  because  capacitances, switching Figure  Examples  cycle  active  because  energy  when c u r r e n t  10. H i g h s p e e d  Complementary  however  and because  as an e q u i v a l e n t savings  do  of True  dissipate  This  during  logic  t o charge and discharge  there  brief  i s a  can flow  f o r a complex i sespecially 44  time  during  the  f r o m Vdd t o V s s as shown i n  nMOS c i r c u i t . I n g e n e r a l  a t a l ltimes.  power  Circuits  i srequired  CMOS c i r c u i t s d i s s i p a t e  i t i srare  CMOS  about  as much  power  CMOS r e s u l t s  i n a power  c i r c u i t t o be  completely  true  f o r memory  circuits.  Vout  Figure  One the  decrease  i n effective  devices.  dynamic  circuitry  precharging  glitches  buses  before  often  to deal  called  chip  i n which  In dynamic  used  of  To a l l e v i a t e  stabilized  approach  CMOS I n v e r t e r  of the disadvantages  channel  for  10.  this  one must  45  by  many  devices  [POSA  wait  until  Four  problem, suggested  circuits  designers  p  use  sparingly  8 1 ] . To  avoid  a l l inputs  phase  i s  the extra  a r e used  11)  the gate.  has been  caused  problem  the g l i t c h  logic  complementary  density  (see Figure  activating  domino  true  p channel  circuits  with  Characteristics  clocks  however,  a  have are new  [KRAMBECK 8 2 ] .  vdd  (AB)+CtD  Figure  Another fall  times  pull-down desires small  neither since  Example  important  o f a Dynamic  a d v a n t a g e o f CMOS  CMOS  transistor a large  trade  pull-up  o f fr i s e  ratioed  for rapid time  CMOS  rather  With  resistance  resistance  i s optimal.  a switch  sizes.  for  does  than  logic,  for rapid pull-up. fall  time  not suffer  a resistor  output.  46  Circuit  i s that  o f a g a t e do n o t d e p e n d o n t h e r a t i o  pull-up  therefore  11.  t h e r i s e and  o f i t sp u l l - u p t o such  a s nMOS, o n e  pull-down,  and a  The d e s i g n e r with  from  i s used  the result this  must that  tradeo f f  to pull-up the  CMOS i s m o r e i m m u n e fully  from  hand,  i s determined  pull-down  and t y p i c a l l y  a n nMOS t r a n s i s t o r at pulling  V d d . An nMOS d e v i c e  the  greater  source  than  can only  a similar  reason  low  high.  nodes  one  obtains  be p u l l e d  By c o n n e c t i n g and d r i v i n g  a very  efficient  a transmission  gate.  of  the design  offs  trade  the decrease  and p  has been  CMOS  through  devices,  such  New  technologies  CMOS fined  CMOS  lapsing  reduce  or low-voltage  Thus  o f Vdd.  For  suited to pulling In parallel  reverse  with  polarities  gates  reduce  many  switches.  disadvantage  As s t a t e d  earlier the  of i s o l a t i n g  this  circuitry t h e n and  rings, also wasted  area  wasted through  [MITEL 8 1 ] .  can s u f f e r from  of high  voltage.  the use of dynamic  E a r l y methods  i s no  The m a i n  a s n+ a n d p+ g u a r d  isolation  circuits  as a s t a t e  t o nMOS o n l y  i n functional density. improved  voltage  i su s u a l l y r e f e r r e d to  i t s disadvantages.  channel  use of oxide  that  transmission  devices.  the  with  i ti s  a l o w node  one t h r e s h o l d  gates  switch  switch,  than  i t s source  arebetter  their  on t h e o t h e r  0.3 v o l t s .  i t s gate  a n nMOS t r a n s i s t o r  p channel  area.  to ground  above  to within  fewer  chip  reaches  o f f when  inherent  CMOS i s n o t w i t h o u t  density  turn  one t h r e s h o l d  as  is  node  swing  of i t s pull-up to  i sa bidirectional  a high  will  output,  ratio  only  pMOS t r a n s i s t o r s  a pMOS t r a n s i s t o r  nMOS  by t h e r e s i s t a n c e  transistors  more e f f i c i e n t  longer  t h a n nMOS b e c a u s e s i g n a l s  Vdd t o V s s . A l o w l e v e l  Although  to  to noise  excess  condition 47  latch-up  current  which  has been de-  accompanied  [ESTREICH 82].  by a  A CMOS  col-  circuit  has  numerous  following forward gains  biased,  sourcing  (SOS),  designer  be  than gate  must  become  be c a p a b l e  up. L a t c h - u p power  to reduce  help  i susually  the latch-up  minority  as s i l i c o n  which  carrier  on  reduce  sapphire  the parasi-  are also available  and these  will  of  up. S e v e r a l  for reducing  such  latch-up  must  during  techniques  must  than  capacitance down h a r d e r  There  be d r i v e n . S i n c e  greater.  nMOS. T h i s  i s offset than  Given  nMOS  important  type,  to  the  be d i s c u s s e d i n  higher  because  t h e p type  fact  input  both  devices  one w o u l d  capaci-  a p and an n  theinput  i s n o t t h e case  by t h e a b i l i t y  are often  capacitance  expect  because  CMOS t o  the extra  o f CMOS t o p u l l - u p a n d p u l l -  [KRAMBECK 8 2 ] .  design  o f CMOS t e c h n o l o g i e s rules  were  distinguishing  t h e gate  layers,  have  devices  this  a r ea wide v a r i e t y  most  connection  circuits  nMOS c o u n t e r p a r t s  that s i m p l i f i e d  substrate  CMOS  as l a r g e as t h en type  slower  Their  Several  reducing  their  be 3 t i m e s  reason  isolation  complementary  made t w i c e can  for  given the  section.  True  channel  doping  n+ a n d p+ l a y e r s  gain.  junctions  latch  areavailable  dielectric  can conduct  supply  as occurs  These i n c l u d e gold  transistor  tances  that  o f t h e n-p-n and p-n-p t r a n s i s t o r  to maintain  techniques  and b u r i e d  later  paths  and t h e power  by a t r a n s i e n t s u c h  lifetimes,  a  unity,  enough c u r r e n t  tendency.  IC  the product  exceed  processing  tic  p-n-p-n  c o n d i t i o n s . The e m i t t e r - b a s e  must  caused  SCR l i k e  first  prepared  i s one  f o r nMOS.  features arethe starting  m a t e r i a l , t h e number  and t h e n and p channel 48  which  and type  isolation  of i n t e r -  method.  If  one s t a r t s  created type  to form  substrate.  merits  the  is  out that  technology  should  CMOS  that  they  side  steps  doped  both  devices,  CMOS  [GULETT  be t a i l o r e d Another  with  the issue  to optimize  substrate  helps  on-sapphire substrate tances  [KINOSHITA  and e l i m i n a t e s  Early advanced  CMOS  cost  results  layers  for  two  polysilicon  transis-  and t h e r e f o r e  line  type.  results  Twin  n and p w e l l s 80].  Twin  approach  t u b CMOS  i n lightly t u b CMOS i s  devices  of s i l i c o n  a n d t h e n+  called on an  siliconinsulating  i n low parasitic  capaci-  The m a i n d i s a d v a n t a g e s  used  metal  use p o l y s i l i c o n aligned  o f CMOS  gates  gates.  sources  A  while  t h e more  polysilicon  and d r a i n s  which  gate  reduces  [GLASER 7 7 ] .  interconnect  use a s i n g l e metal [LONDON  layers i s high  capacitors  channel  well  and l o w y i e l d .  CMOS t e c h n o l o g i e s  con  of n  o n a n nMOS f a b r i c a t i o n  A final  latch-up.  i n self  capacitances  Some  This  technologies  technologies  parasitic  requires  81].  the relative  CMOS  t h e n and p channel  layer  a p  of n w e l l  [PARRILLO  a thin  for  o p t i m i z a t i o n , as i s n  t h e same s u b s t r a t e  latch-up.  (SOS) grows  are i t s high  process  reduce  of n  performance,  by c r e a t i n g b o t h  both  over  p o t e n t i a l advantage  e p i o n a n n+ s u b s t r a t e  claimed  versa  Proponents  to their  c a n be p r o c e s s e d  start  debate 81].  higher  t h e n a p w e l l m u s t be  and v i c e  percentage  of their  [CHWANG 8 1 ] .  thewafers  substrate  i sconsiderable  a greater  because  since  SOS  There  a r e used  well  an n type  the n channel  of p and n w e l l  CMOS p o i n t tors  with  i n a design. 49  83].  which  and two p o l y s i l i -  Capacitance  between the  c a n be a n a d v a n t a g e  The s e c o n d  layer  of  I f one  polysilicon  is  sometimes  memory  made  arrays  technologies  that  require  Thicker  and t h e r e f o r e  Double  resistive high  f o ra p p l i c a t i o n s  density  use a s i n g l e p o l y s i l i c o n  interconnect. layers  highly  metal  they  processes  applications  oxide  do n o t f o r m  metal  high  value  for  the metal capacitors.  for high  better  as  CMOS  layers  to isolate  suited  i s a  Other  and two metal  i srequired  may be b e t t e r  because  pull-ups.  such  performance  conductor  than  polys i l i c o n .  The ogies As  final  major  distinguishing feature  i s t h e method  stated  earlier,  [MITEL 81] w h i l e  used  to isolate  t h e newer  others  technology  technol-  t h e n and p channel  devices.  and  with  we h a d t h e o p p o r t u n i t y  oxide  showing sion  one m e t a l isolation.  i s shown  masks  used. Rather l e t them  procedures  i n Figure  than speak  t o work  with  polysilicon  [SIMMONS  a series 82].  i fthe second  e x p l a i n each diagram f o rthemselves.  i s GTE's gate  pro-  of diagrams  process  polysilicon  In detail  An I n t r o d u c t i o n  [GLASER 7 7 ] .  50  83],  A condensed  12. ISO-CMOS i s a n 8 mask  required  i savailable  [SMITH  l e v e l s of interconnect,  C contains  t h e f a b r i c a t i o n sequence  additional  to  and two p o l y s i l i c o n Appendix  isolation  Data  ISO-CMOS. ISO-CMOS i s a 5 m i c r o n , p w e l l , cess,  use oxide  u s e n + a n d p+ g u a r d r i n g s  ISO-CMOS F a b r i c a t i o n a n d P a r a m e t r i c  The  CMOS  technologies  between  I have  verwith  layer i s decided  to fabrication  DEFINE ACTIVE  The diagrams (right) show the process stages for Mitel's ISO-CMOS process. This process uses a total of 8 masks. P-type transistors are formed directly in the N-type substrate which will be biassed to the most positive voltage used (VDD) N-type transistors are formed in P-type wells formed by inverting the N-type substrate with a high concentration of P-type dopant. The P-well will be biassed to the most negative supply voltage (Vss)- The process has self-aligning gates, as the polysilicon gate can be used to mask the source/ drain diffusion areas. Interconnect between the transistors is primarily with metal. However, the polysilicon is used as a second interconnection medium, greatly facilitating interconnect design. Isolation to prevent the formation of spurious transistors in the field-oxide region is achieved by using a very thick, recessed oxide. The 5-micron design rules coupled with oxideisolation and self-aligning gates gives the process major speed and packing-density advantages over metal-gate CMOS. While maintaining similar power dissipation characteristics to metal-gate CMOS, packing densities approach those of NMOS in similar geometries and speeds are comparable with low-power-Schottky technology.  nwm  • - -*JN4-  WEZBEZq*—wi-  ll SUISTAATE  DEFINE P - W E U DIFFUSIONS RESIST  IMPLANT M K U  worn F I E L D  OXIDE  P-WELL  6 R 0 W DATE OXIDE OEPOSIT P O L T S I U C O N DEFINE POLTSIUCON M E M  POLTSIUCON  ETCH POLYSILICON DEFINE N-TYPE DIFFUSION A R E A S  N DIFFUSION DEFINE P-TYPE DIFFUSION A R E A S  t DIFFUSION DEPOSIT OXIDE DEFINE CONTACT WINDOWS  ETCH CONTACT DEPOSIT DEFINE  WINDOWS  METAL  ALUMINUM  METAL  3 ETCH  METAL  DEPOSIT S C R A T C H PROTECTION  N SUBSTRATE  Figure  12.  ISO-CMOS F a b r i c a t i o n 51  Sequence  [MITEL 81]  Detailed tics  ISO-CMOS  process  were not a v a i l a b l e  Tables  parameters  t o u s . The d a t a  we h a v e  characteris-  i s presented i n  I andI I .  Note:  l a m b d a = 2.5  Component n p  I.  1.5 2.1 1.3 1.2 2.6  ISO-CMOS  Component  Table  ISO-CMOS D e s i g n  Design avoiding  I I .  x x x x x  pF/lambda**2  10**-4 10**-3 10**-3 10**-4 10**-3  Capacitance  |  n poly p poly n active p active metal  microns  Capacitance  | +  poly wire junction junction metal poly gate  Table  Resistivity  Data  ohms/square  25 50 12 100 0.023  ISO-CMOS R e s i s t i v i t y  Data  Constraints  constraints  latch-up,  tion.  Table  them  graphically  enable  and d e v i c e  include the design  fan-out  III lists  limitations,  the design  with  rules  the layout  signals. 52  rules,  techniques f o r  and m o b i l i t y  and F i g u r e  13  o f an i n v e r t e r  compensa-  demonstrates that  has two  Notes:  - a l l dimensions a r e i n lambdas - x means no r u l e  Minimum  Act i v e Polyl Poly2 Metal Cut  | Active | + + 2 1  Spacing  Polyl  X X  X X  X X  X  2  2  2  | Active | + + X  1.6 X X  |  |  |  2  Minimum |  N+  I  I-*  Overlap |  Poly2  Metal  0  -.6  X  2  Overlap | + |  N+ A c t i v e t o P+ A c t i v e N+ A c t i v e t o P+ A c t i v e P w e l l t o P+ Pwell to Pwell  1.4  Minimum = 7 = 3 3 8  |  1 1 1.6 1  Metal  |  2  of A c t i v e  P+  Cut  Rules  Poly2  |  |  +  0 0 0  Miscellaneous  I I I .  |  X X X  2  2 2 2 2 2  +  |  Cut  Rules  X X X  Polyl  | +  2 2  +  +  Table  Metal X X X  Minimum W i d t h | Active  | +  2  Polyl  microns)  Rules  Poly2  1 2  Minimum  Act i v e Polyl Poly2 Metal  | +  ( = 2.5  | + |  |  Cut  |  2  by:  Pwell | + 2 |  Spacing  Rules  (different substrates) (same p o t e n t i a l and s u b s t r a t e ) (different substrates) (different potentials)  ISO-CMOS S i m p l i f i e d 53  Design  Rules  [SNYDER  82]  •  •  Po 1 y2  Metal  Cut  •  •  Pp 1 u s  Np  •  1 us  Polyl  Pwe  11  Ret i ve  Figure  13.  • L a y o u t o f an I n v e r t e r w i t h [SNYDER 8 2 ] 54  • 2 Enable  Signals  As  Table  therefore tion  I I I shows  easy  to l e a r n  are the r u l e s  transistors. difficult  and  design  remember.  concerning  Fortunately  rules are integers The  are  three  CMOS c i r c u i t s along  there  are  only  design  guidelines  [ESTREICH 8 2 ] . F i r s t ,  potential latch-up  paths  must  s t r a p . Any  a metal  i n j e c t e d charge  the low r e s i s t a n c e t o Vdd  with  n+  path.  The  contacts.  suggested  nebulous.  of  n  type  these  more  put i n a contact;  isn't  current  shunted  do  in  which  This  can  contact  to  ground  should  similarly  occupy  valuable  many c o n t a c t s  r u l e of thumb  i f there  latch-up  to use i s  s t a t e s : i f there i s  space,  consider  making  [GRISWOLD 8 2 ] ,  A  second  design  parasitic  This  One  be  Contacts  often  the  of  and  t o V s s v i a a p+  n substrate  t h e d e c i s i o n on how  some  p  complica-  be m i n i m i z e d .  will  space and t h e r e f o r e  space,  few  the l a t e r a l  and  tied  a  of  f o r avoiding  by w i r i n g a l l o f t h e p w e l l s  be  slight  the separation  be a c h i e v e d  through  only  and a r e  rules.  There  flows  most  reduces  guideline for avoiding  latch-up  i s to  r e s i s t a n c e s of the p w e l l and s u b s t r a t e the voltage  the p a r a s i t i c makes  devices  drop  across  f o r a given  i t harder  to turn  regions.  the emitter-base level  junctions  of i n j e c t e d  the devices  current  and  thus  for  reducing  the p a r a s i t i c  r e s i s t a n c e s i s t o p l a c e a s m u c h p+ a n d  n+  diffusion  i n the p w e l l  and  is  possible  substrate  [LIPMAN 8 2 ] .  55  o n . One  reduce  regions  technique  r e s p e c t i v e l y as  A  third  prudent tween  placement  the p w e l l  to h e l p  collect  junctions the  design  We  p+ a n d nMOS s o u r c e  82, SMITH  to follow  as p o s s i b l e  memory c e l l ,  Spacing bebe m i n i m i z e d  the parasitic  emitter-base  contacts  the latch-up  the spacing  should  be  prevention  the colour  f o r example, contains  suggests  should  83]. S i m i l a r l y ,  throughout  latch-up  emitters.  contacts  c a r r i e r s near  n+ a n d pMOS d r a i n  tried  closely  f o ravoiding  of potential p a r a s i t i c  minority  [LIPMAN  substrate  guideline  four  between  minimized.  guidelines  palette  n+ c o n t a c t s  design.  as The  and f i v e  p+  contacts .  Fan-out Consider output  l i m i t a t i o n s are another  a large  capacitive  s i g n a l of a minimum  of  sourcing  and s i n k i n g  we  connect  i td i r e c t l y  bus that  a relatively  be e x c e s s i v e  system  performance.  A better  enough  larger  to optimally  drive  clear  there  It model  i s easy that  In  other  is  2.718 t i m e s  be some  t o show u s i n g  the optimal  amount  Mead  fan-out  the overall the signal i s large  stage  however  intuitively  factor.  simplified  timing  i s e (= 2 . 7 1 8 ) [ M E A D 8 0 ] .  drive  a s i t s own g a t e  and d i s -  device  buffer  a n d Conway's  factor  should  56  to charge  the f i n a l  capable  of current. I f  I t i s therefore  optimal  fan-out  words, each b u f f e r as l a r g e  delay.  with the  i sonly  i s to buffer  t h e bus. Each  an a d d i t i o n a l gate should  until  constraint.  be d r i v e n  a n d may d e g r a d e  approach  devices  introduces that  small  to t h e bus t h e time  t h e bus w i l l  successively  must  design  s i z e d g a t e . The g a t e  charge  with  important  a capacitive load capacitance.  One  that  problem  with  using  often not  the optimal  very  large  a l l paths  optimal mance  fan-out  which  reduces  i na circuit  fan-out unless  ratio  factor  i s that the f i n a l  the c i r c u i t  arec r i t i c a l  may n o t i m p r o v e  something  i s done  density.  buffer i s  Futhermore,  and t h e r e f o r e u s i n g the  the overall  to reduce  system  perfor-  the c r i t i c a l  path  delays.  The and  most  efficient  performance  their  delays  circuit  with  more  tive  design  used a near palette.  approach  favorable fan-outs  constraints that  ratio  S i m u l a t i o n was u s e d  Mobility discussed.  critical  approximately that  discharge  twice  and by t r y i n g  This  area  reduce  different  an i m p o r t a n t f o r a very  role at conserva-  f o r performance and  of 3 or 4 throughout  to check  the delay  i s the f i n a l  devices that  f o ra given a node  and then  area  thecolour  on s e v e r a l o f t h e  paths.  compensation  N channel  of c i r c u i t  paths  we o p t e d  sacrificed  optimal fan-out  palette  vices.  i n terms  c o n f i g u r a t i o n s . Simulation can play  s t a g e . Due t o t i m e  means  approach  i sto locate thec r i t i c a l  this  colour  design  have  a carrier  of p channel  size,  twice  constraint mobility  devices  n channel  approximately  i s one r e a s o n  design  devices  as f a s t  for the prominence  t o be  that i s  [SZE 69].  This  can charge  as p c h a n n e l o f nMOS o v e r  or de-  pMOS  technologies.  It  i s desirable that  approximately CMOS  equal  by m a k i n g  the rise  i n digital  the p channel  and f a l l  circuits.  This  devices  twice  57  times  of gates  be  c a n be a c h i e v e d i n as wide  as t h e n  channel to  d e v i c e s . There  nMOS w i d t h  process ratio margin  parameter  [KANG  as wide  advantages  o f 2. A s s u m i n g fluctuations  of 2 optimizes  conservative twice  ratio  are other  both  a fan-out  i t has been  the propagation  81]. For these approach  to maintaining  reasons,  to design,  as i t sn channel  we  counterpart  58  o f 3 and w o r s t shown delay  that  every  a  case width  and t h e noise  and i n keeping  made  a pMOS  with our  p channel  on t h e c o l o u r  device palette.  CHAPTER  5: D E S I G N  The  CMOS D e s i g n  MPR  The  colour  Pacific  to  package  t h e same  82].  code  CDS  written  a  inputs  plotter  plotted screen eight  uses  level  lower  the compiler one  and outputs  such  and white  check  f o r coloured hardcopy. plots  This  a l l  permits  without  and g r e a t l y  reduces  a f i l e  59  The  layouts  the standard  and t h e a b i l i t y t o  applied  t o i t .The  by t h e c o m p i l e r t o layers  to either plot,  c a n be  t h e HP98x6  o r t o t h e HP7820  The p l o t t e r  also  has a  of the top h i e r -  of the c e l l s  on t h e  to see the top l e v e l  theplot  the p l o t t i n g  computers.  containingthe  o f mask  boxes  [CHENG Packard  cell  provides  the designer  cluttering  top  more  of the features  the bounding  belongs  and the p l o t t e r .  generated  directed  8 2 ] . CDS  desk  a s BOX, WIRE,  c a n be  algorithmic  of Hewlett  or  transformations  Microtel  79] a n d PLAP  HP98x6  Any c o m b i n a t i o n  and only  interconnections  lines  the  i s an  [SNYDER  T h e CDS l a n g u a g e  black  that  level.  2000  t h e CIF code  cells.  (CDS) w h i c h  containing  suitable  pen p l o t t e r  detail,  file  and the output  archical next  with  option  out with  based  modules:  l a y o u t commands  f o r a quick  f i l t e r  laid  as LAP [LANG  on t h e 68000  a  the desired  PHILOSOPHY  Snyder  approximately  C I F code.  program  System  by Warren  I n t h e CDS l a n g u a g e  cell  was  of programs  and runs  algorithmic  plot  written  class  corresponding  call  chip  CMOS D e s i g n  has two m a i n  compiler  AND  System  CDS c o n t a i n s  BASIC  PROCEDURES,  palette  Research  layout  TOOLS,  time.  with  unnecessary  CDS an  example  CDS a  has s e v e r a l CDS  language  unique  layout  and u s e f u l  program  specification.  meaningful  label  and Appendix  The DEFN  t o a node  within  can  t h e n be r e t r i e v e d b y a c a l l i n g  the  lower  it  was  called  nates, does is  level  cell  they  written.  computing  cell  are automatically expect.  immediate  permits  must  the coordinates  required  particularly  at higher  l e v e l s when  on  and t h e d i s p l a y  when be  very  much  from  the interconnection  on  the plot.  design  rule  hierarchical a  leaf  cell  violations. i s that level.  a t each  chies.  We  palette  must One  nodes  This  level,  made v e r y  difficulty  Drawing  means  which  liberal  that  s t i l l that  to carry  u s e o f node  when cells,  i s displayed  a wire that  t o be  of the  to the  the  con-  connected  be on g u a r d f o r  arises  a node  execute  c a n become t e d i o u s  60  two  when  a v a i l a b l e to the next  one must  layout.  program  because  guarantees  of course  are only  to the top l e v e l  quence  command  nature,  remove a l l u n c e r -  made, and does n o t j u s t a p p e a r  The d e s i g n e r  D E F N a n d LOCN  process.  coordi-  careful  information  tainty  has been  t o i t when  to interconnect  s i z e s . The DEFN a n d LOCN c o m m a n d s  nection  coordinates  by i t s  r e s o l u t i o n i s reduced  b y a LOCN  give  the layout  cell  returned  one t o  t o t h e node  larger  coordinates  full  applied  layout,  therefore  shows  t h e LOCN c o m m a n d . I f  applied  feedback  14 the  The n o d e  with  Algorithmic  visual  The d e s i g n e r  the plots  command a cell.  Figure  D contains  had any t r a n s f o r m a t i o n s  as one w o u l d  not give  features.  through  using higher from  a LOCN-DEFN s e -  i n complex h i e r a r -  definitions  i n the colour  ! This example demonstrates ! f e a t u r e s o f CDS. The c o d e ! t h e t o p most p a l e t t e c e l l  some o f t h e m o r e p o w e r f u l s h o w n was e x t r a c t e d f r o m definition,  i  ! P l a c e t h e x - d e c o d e r b e n e a t h t h e memory ! Place("bigxdcod",168,-81,Xdecod)  array  I  ! D i m e n s i o n d a t a bus c o o r d i n a t e arrays ; DIM R d p x ( 4 ) , R d p y ( 4 ) ! red nibble DIM G d p x ( 4 ) , G d p y ( 4 ) ! green n i b b l e DIM B d p x ( 4 ) , B d p x ( 4 ) ! blue n i b b l e  !  ! Get x - d e c o d e r node c o o r d i n a t e s ! FOR 1=0 TO 3 Locn(Xdecod,"rdp"&VAL$(I),Rdpx(I+l),Rdpy(I+l )) Locn(Xdecod,"gdp"&VAL$(I),Gdpx(I+l),Gdpy(I+l)) Locn(Xdecod,"bdp"&VAL$(I),Bdpx(I+l),Bdpy(I+l)) NEXT I ! Get m i s c e l l a n e o u s  node  coordinates  Locn(Xdecod, " x s i g l e f t " , X s i g x , X s i g y ) Locn(Xdecod,"btmleft",Btmlef tx,Btmlefty) Locn(Xdecod,"toprght",Toprghtx,Toprghty) !  Check  forcell  placement  error  IF  B t m l e f t y <> R d p y ( l ) THEN BEEP PRINT "node e r r o r " END I F !  Connect  t h e Vss bus t o t h e x - d e c o d e r  Pitch=l68 Btrightx=Btmleftx+(Pitch*6) j Layer(Metal) Wire(12,Btmleftx-2,Btmlefty-10) X(Btrightx+2) j FOR 1=0 TO 6 Wire(4,Btmleftx+(Pitch*I),Btmlefty) Dy(-lO) NEXT I j ! etc....  Figure  14.  CDS L a y o u t 61  Program  Example  Another turns can  feature  the bounding  be u s e d  cell. a  nice  This  well  box c o o r d i n a t e s  t o make a n I n t e l l i g e n t i s especially  defined  Since  subscripted  We  also  made  important  print  self  ware. slow  One  problem  compared,  problem  are by  The  by  i s that  Design  Our system logic  hand  i s not at  corner.  features  can  the colour when  useful become  that  BASIC  very  loops.  print  information  out  at the  obvious  when  by i t s  hard-  disk  system  capacity  project.  one c o n s i d e r s  are caused  and p l o t t i n g  t o t h e PLAP  palette  FOR-NEXT  compared.  compilation  floppy  within  by h a v i n g  often  and  f o rexample,  n o t so s e r i o u s a desk  Errors  disadvantages  i s the limited  exceeded  left  operations  p a i r s and other  are studied  CDS h a s s e v e r a l  of the c e l l  i n BASIC a l l of BASIC'S  documenting  compilation. outs  coordinates  d e c i s i o n on where t o p l a c e t h e  as i t s l o w e r  and math  coordinate  of each  These  which r e -  p r o g r a m . F o r e x a m p l e , we m a d e e x t e n s i v e u s e  arrays cells  of a c e l l .  i f the o r i g i n  such  CDS i s e m b e d d e d  of  these  true  location  be u s e d i n t h e l a y o u t  end  o f CDS i s t h e B B O X c o m m a n d  i s relatively  a t UBC.  which  Perhaps  was  these  Another almost  drawbacks  the independence  provided  top computer.  Procedure  design  procedure  specification, design,  loading  consisted  module  of eight  partitioning,  analysis  62  distinct  floor  and s i m u l a t i o n ,  steps:  plan  design,  stick  diagram  layout, sion  mask  layout,  o f IC d e s i g n  module  place  level  at  layout,  the  logical  level  The  signal  A  &  block  module plexity  be  and  system  design  Logic  layout  design  were  are d i s t i n c t  and  shown  plan  design  then  placing  into  by  involved them  such  electrical are at the  the  synthesis,  Schmiing  as  a  using  foundation  Telidon  was  system.  relatively  architecture. are  easy  A l l module  well  defined.  A  8.  estimating that  G.  t h e MPR  i n Figure  diagram  c h a r a c t e r i s t i c s and  interconnections  earlier  takes  manually.  palette  modules  palette  course  entry  by  82]. Timing  at the  Stick  a l l of  developed  constrained  colour  of  performed  colour  the system  was  were  discus-  place  are at the  Virtually  was  [SCHMIING  take  and data  2  specification,  representation.  steps  the clean  diagram  Floor  Mask  component  B)  Partitioning  boundaries  the Chapter  that  plan  of  specification  discrete  of  floor  evaluation  definitions  because  note  of r e p r e s e n t a t i o n .  and  (Appendices  Using  a n a l y s i s , and s i m u l a t i o n  system  MPR  we  level  of r e p r e s e n t a t i o n .  validation,  the  and  entry.  of r e p r e s e n t a t i o n .  loading  physical  the  data  as a b a s i s  partitioning,  functional  level  and  of  each  the i n t e r c o n n e c t i o n  com-  and c h i p  area  w e r e m i n i m i z e d . The  modules were  laid  out because  the  floor  size  plan  the s i z e estimates  evolved often  as  had t o  updated.  Logic gates,  and  design was  one  involved  implementing  o f t h e most  each  module  i n t e r e s t i n g stages 63  with  of the  boolean design.  Several to  configurations  minimize  was  the  necessary  The  number  to  sizes  tain  a  process  of  required  good  to  sized  A l l gate  the  i n the  chip  were  large  The the  enough  next  logic  line  [MEAD 8 0 ] .  ing with  mask  design  whether and  Figure  diagram.  with  and  or  impossible through  routing  on  the  SPICE to  to  and be  the  It  stage.  determine still an  the  main-  iterative therefore  r e v i s i o n s to  multiples  of  attempt  of  a  many  minimum  analysis  will  be  critical  paths  on  determine  i f the  drivers  timing specifications.  was  layer  shows a s t i c k  to draw  are  diagram very the  Because  also of  diagrams  with  colour  corresponding  for  experimentburdened  clearly  indicate  i n terms  quickly  their  from  i s not  is efficient  They  64  can  shapes  unique  its  designer  layout  design.  a  convenient  proposed  stick  with  diagrams  mask  i s assigned  because  complexity.  stick  represent  Stick diagrams  many r e v i s i o n s of  this  to  loading  Several  Stick diagrams  schemes.  at  required  details.  interconnection  an  w e r e i n t e r r e l a t e d and  design  mask  in  performance.  fan-outs  s p e c i f i e d as  the  topologies  a  the  was  tended  gate often  S t i c k diagrams  rule not  gates  with  the  each 15  This  chapter.  meet  of  diagrams.  segments  logic  to  stage  optimal  details  were s i m u l a t e d  increase  analysis  were  next  module  loading  the  sizes  each  constraints  achieve  of  i n v e r t e r . More  presented  and  density.  many  for  fan-out  a c h a n g e I n t h e s i z e o f one others.  tried  gates  the  circuit  because  of  consider  objective  gate  were  point  convenience  before  of out we  finalizing  area any went the  Counter C e l l L=load T=toggle L and T a r e m u t u a l l y  exclusive  1*  V  L'*T' Dout  Din T  D T'  tr  Vdd  Vdd  Din  Dout  Vss  Vss T»  L'  L' Figure  Mask geometry  layout on g r i d  difficult  to and  cells  be r e p e t i t i v e l y compaction  interactive  often  a small  as s m a l l  a  paper  because  accommodate the  was  15.  Stick  tedious from  the stick  such  layout  of  mask  diagrams. Revisions  were  layout  was s p e n t  as i n t h e memory  tool. 65  we m o s t  drawing  h a d t o be r e d r a w n  particularly  o f c e l l s was w h e r e  graphics  the  Much e f f o r t  as p o s s i b l e ,  Example  process  the entire  change.  used  Diagram  trying  f o r those array.  wished  t o make  that  The  to  were  editing  f o r some f o r m o f  The for  final  the  grid  because with  one  a textual computer  The  plots  layouts  and  The  Design  We  and  sizes.  to  a  At  an  programs  e r r o r prone  for  was  then  process  violations.  with  I f an  shape  entered  compilation  for correspondence  and  the  into  plotting.  hand  e r r o r was  drawn  found  the  recompiled.  conservative with  (DAC).  of  circuits  are  not  be  time  we  will  to  processing  All  circuits  an  n channel way  see,  are  with  We  and  The  felt  static  reduce  to  not  feel  colour  yield  that  would  design of and  ensure  reduces  a the  design  dynamic  sense  memory  size  digital  static  was  palette's large  cell a  driver  major  con-  size  may  have  gate  there  problems.  CMOS, t h a t  high  felt  without  transmission  p channel 66  i s , f o r every  d e v i c e . We  performance  n and  the  A l l circuits  prototype  this  used  bidirectional  both  the  disadvantage  a p channel the  that  because The  of  Precharging  the  true  philosophy.  larger.  did  to keep  circuitry.  constructed  we  design  exception  success  the As  the  complexity.  could  contributed  best  be  program  e d i t e d and  static  circuit  the  straint.  namic  be  CDS editor  rule  converter  amplifiers  the  to  The  visual  probability  that  can  CDS  Philosophy  analog  both  a  checked  had  completely  timing is  with  adhered  greater  involved writing  layouts. This  for design  program  entry,  language.  were  CDS  to  paper  data  must a c c u r a t e l y d e s c r i b e a c o m p l e x g e o m e t r i c  the  are  step,  devices  that  going  gates to  this  improve  was  to  were  is  dyalso  their  switching  characteristics.  chip  because  many  transistors  true  CMOS  This  means  and  cussed delay out  o f two r e a s o n s .  requires that  gate  curve  of 3  resulted  for  The included instead runs  good  and most  of every  twice  as  each  gate.  Second,  signal  t o be  present. buses  the complements.  fan-out  t o 3 o r 4. A s w a s  i s e  (=2.718),  i t s minimum  design  of the f i n a l  obvious,  larger  f o r the complement  restricted  near  in a  being  however the  and t h e r e f o r e a f a n -  compromise.  drivers  dis-  The  quite  low  fan-out  large.  V s s t o t h e p - w e l l s , and Vdd t o t h e n s u b s t r a t e  used.  As was d i s c u s s e d  earlier  this  i s a  technique  latch-up.  usual  methods  keeping  f o r improving  the dimensions  of p o l y s i l i c o n  of metal  coupled  i s a  from  liberally  were  results  to implement  generate  flat  design  i s required  the optimal  i n many  reducing  that  is fairly  Contacts were  area  fan-outs  to 4  First  the complement  extra  earlier  CMOS  are required  f o rthe drivers  All  True  over  where  ever  polysilicon  crosstalk.  67  performance  t o a minimum possible. which  We  were  used.  and u s i n g also  can cause  avoided  These metal long  capacitively  CHAPTER  The  6:  THE  COLOUR P A L E T T E  Development  We least  Synopsis  a n t i c i p a t e d that  three  tions.  It  circuits  design is  r e q u i r e d . We  feel  and  is  The  first  Research student our was  by  16  contained cell in  the  was  one  with  test  bility  the  of  DAC.  cell  size  excellent  to  iterations  designed  and  the  errors the  as  for the  new  no  while  at  specificaintegrated that  means  were  abnormal  4  the  each chip  and  therefore  scaled  68  bit  microns. colour  This  palette  s i z e p a l e t t e has down,  the  s i z e p a l e t t e , and  that  i t would  therefore  each  experience  provided  upward  was  test circuit  results will  area  for  several be  an  compati-  f a b r i c a t e d and  however,  12  prototype  enough a d d i t i o n a l c h i p  worked,  chapter.  3750  maintaining  prototype  test  4  full  a separate  circuit  Detailed  Multiple  full  had  Pacific  1982.  by  the  Microtel  October  prototype  m o d u l e s . We  a i d s . The  detected.  a  the  still  the  3 7 5 0 by  loading  p a l e t t e . The  of  to  implement  handle  circuit  on  DAC's.) A l t h o u g h  vehicle  majority  next  the  on  i s by  of  included  required  to  debugging  were  require  iterations  during  Course  t o i n c l u d e a p r o c e s s m o n i t o r and module  design  (Recall that  three  designed full  of  constrained  area  every  was  was  w e r e t o be  size  with  bits  three  meet  literature  number  ISO-CMOS D e s i g n  sufficient  prototype  for  i t would  would  rather optimistic.  projects  circuit  that  palette chip  before  rare  the  iteration  Ltd.  colour  iterations  disclose  probably  the  extremely  to  DESIGN  each  tested layout  presented  in  Microtel er  Pacific  fabrication  design  began  run at  on A p r i l  problems  detected  the  size  full  1983  Test  The  colour  of  tests.  tion  has been  suspicions  Module  we  modules.  They  register,  memory  decoder, contains palette  turn array  resubmitted  control a  i s almost the scaled  has i t s  own  i s identical  pipeline  palette  register.  deal  of  status  into  on May  13,  t o us on J u l y  8,  chapter.  and c o r r e c t  during  i s that  any  the  second  second  itera-  f o r f a b r i c a t i o n because  diagram  nicely  of Figure  decomposes  to analog data  4 b i t wide  as i s each colour  into  buffer,  r e g u l a r i t y . Each This  8 on p a g e  justifies  The 4  y decoders, colour  each  x  palette of the to  first  4 b i t slice i n  b i t i n t h e memory  b i t i n the b i d i r e c t i o n a l  69  distinct  b i t slice  Each  41  pipeline  our d e c i s i o n  prototype.  palette  8  converter,  pads.  r e g u l a r i t y . F o r example,  The  the design  Labor  a n d t h e I/O  identical. down  to c o r r e c t the  i n the next  bidirectional  circuitry,  great  iteration  completed  detected  anoth-  problems.  a r e : the d i g i t a l array,  was  unchanged  to the block  the colour  was  and r e t u r n e d  project  us  the second  and t o expand  problems  The c u r r e n t  to o f f e r  r e f i n e the design  P a r t i t i o n s and D i v i s i o n of  see that  design  will  small  back  so  1983. Our o b j e c t i v e  of processing  Referring  enough  and  be p r e s e n t e d  iteration  iteration  of  charge  fabricated  will  the presumably  chip  5,  kind  p a l e t t e . The d e s i g n  was  results  third  no  was  i n the prototype  and the c h i p  1983.  Research  i s therefore  an  b u f f e r and excellent  candidate exploit 16.  the  cell  definition  program. Each  link  represents  a  CALL  by  cell.  of  colour  great.  logic  i t i s  the  node  prototype  on  or  in  therefore  one's  t o work  was  rule  own with  large  almost  was  Cheng  and  more  easier  to  for than  to  spot  else's  fortune  o f UBC  palette.  that  i n someone my  colour  the p o t e n t i a l  It i s invariably  It  Gordon  and  to  facilitated  colour  a necessity  violation  work.  size  CDS  cell  the e n t i r e  greatly  to the f u l l  the p r o j e c t .  design  design  i n our  the higher  represents  structured  palette project  work  first  cation,  module  efforts  by  and  little  from  us  analysis,  Schmiing,  i s actually  modules  were  after  stick  modules.  block  and  and  have  already  work  have  the  Gerhard  Schmiing  system  specifi-  namely plan  The been  design  system  were  joint  specification  discussed.  to the block  placement  diagram  of the modules  The  floor  of F i g u r e  deviated  8  very  diagram.  divided  between  the remaining  diagrams,  Frequent  floor  myself.  inherent  relative  this  looked  of the d e s i g n ,  partitioning,  41. The  The  stages  partitioning  design  page  three  Cheng,  module  plan  own  indeed  MPR.  The  of  highest  highly  I t was  error  opportunity  on  The  c h i p . Our  designer  of  did  a  The  than  We  represents  expansion  one  approach.  tree  palette  error  design  i n the  lower  the  hierarchical  i t s h i e r a r c h y as i s shown by t h e t r e e s t r u c t u r e i n F i g u r e  E a c h node  layout  a  for a  mask  stages layout,  interaction 70  Cheng  was  and  myself,  of design and of  data  and  each  (logic,  loading  entry)  f o r our  course  required  to  colour palette  protected i n p u t pads  y decoders I  /  Q  p  a  d  i g  s  0  0  x decoder  output pad  input pad  decoder cell  buffer decoder cell  control signal generator  read/write control  signal buffers  buffer  memory.pipeline r e g i s t e r , s t a t i c and dynamic DACs  buffer C E l l  memory array  pipeline register and DAC's  12 b i t row pipeline register  2 bits input drivers  I  tap switch  decoder  n channel half  input drivers  p channel half  Figure  16.  Colour  Palette 71  Cell  Hierarchy  ensure the  that  the modules  interconnections  (width) match each  and  those  bus  would  would  of  o f t h e memory work.  Cheng's  module  buffers,  contributions  were  t h e memory  pad, and  dynamic ly  DAC  DAC  input  Schmiing,  pad  and  responsible for  between  testing focus  butions to  was  by  Port  The other  Schmiing,  joint  effort  the d i s c u s s i o n  maintain  Dual  a  routing.  Cheng  and  o f MPR  iteration  static  DAC  and m y s e l f . pad  Cheng,  and  between  on my  own  Schmiing  used  was  generator.  My  be  tri-state  iteration  a  myself.  effort  Cheng  was  responsible was  Second  a  I  however where  joint  iteration  and m y s e l f .  discussed  dynamic  protected  MPR.  testing  a  slight-  a joint  I was  contributions,  will  the  used by  paths.  Schmiing  checking  t h e same  also  iteration  in  had to  and m o d i f i e d  which We  the p i t c h  register,  supplied  the c r i t i c a l First  signal  that  decoders,  For the f i r s t  Snyder  output  for simulating  t h e x and y  pipeline  monitor.  a new  Cheng,  were  and  buffer  cooperated  the c o n t r o l  The s e c o n d  buffered  the global  effort  to  with  also  array,  by W a r r e n  was u s e d .  i n parallel  between  and  the process  designed  by m y s e l f  We  contributions  data  For example  the b i d i r e c t i o n a l  array.  bidirectional  input  c o r r e c t l y together  be e f f i c i e n t .  locations  other's  operate  intend contri-  necessary  cohesion.  Memory  memory  modules  array  dominates  are dependent  the colour  on t h e memory 72  palette array's  circuit. A l l size  and c o n -  figuration the f i r s t cations our  module  most  processor  memory.  means  separate tration  data  cessing  that  scan  and  Dual  to note  i s that  controller  (CRTC)  but only  t h e memory  must  discuss  between  The p r o b a b i l i t y  a maximum will  t h e CPU  of both  write  the  n o t be  will  ported  i f we a r e  cell  MPR  to have  a n d C R T C . No and  arbi-  t h e CRTC  simultaneously  ac-  i t happen the t i m i n g i s  be d i s r u p t e d  noticed  to the  the discrete  cycle  devices  the  asynchronously  t h e memory  f o r t h e CPU  o f two p i x e l s  therefore  on  both  can write  be d u a l  used  requires  buses  can  t h e CPU  circuitry  porting  and c o n t r o l  a n d CRTC r e a d  by  f o r one  the user.  video  Simultaneous  c y c l e s on t h e same n i b b l e s h o u l d h a v e no  effect  output.  traditional  i s shown  decoded  array.  connected to  through progress  6 transistor  i n Figure  to enable  memory  coded  specification  t h e same n i b b l e i s l o w b u t s h o u l d  such  cell  the s p e c i f i -  and then  array,  that  i s performed  cycle.  A  review  therefore  designs  the m u l t i p l e x i n g  implementation.  on  first  was  s t a t i c memory  t h e CRT  t h e memory  This  avoid  CPU  The memory  designed, I w i l l  important  (CPU) a n d  from  read  t o be  data buses.  implementation.  The  to  and  and t r a d i t i o n a l  own  read  of c o n t r o l  one  When  the array then  17. A  i t s word  which  coupled  subset  of the word  to the data select  cross  and hence  i s true,  b u s . The r e m a i n i n g of  the  data  a r e t o be o p e r a t e d  the desired  b i t state 73  CMOS  of the address  lines  line  static  lines  one row  t h e memory  address  lines  running  on  are  In the  latch  lines  on. I f a w r i t e  i s placed  memory  Is  are de-  vertically cycle  the data  i si n bus by  a  driver  cross  that  i s sufficiently  coupled  then  a high  bit  state.  can  be  impedance  kept  we  as t h e t r a n s i s t o r  approach  t o make  line.  Extremely  simultaneous state.  far  t h e most  careful  application,  only  ensure first  that  or second  achieve  a  cell  Our most  the d e s i g n  critical  [PULFREY  We  i s  para-  and r e q u i r e  83]. Also,  many  82]. Another  problem  with  memory  transistors would  be  cell  dual  required  to  this ported  and a n o t h e r  applications  word  prevent  d i s r u p t i n g the  small  size  i s by  c o n s i d e r a t i o n and t h e r e f o r e one that  hand,  come  and met were  circuit.  74  with  the s m a l l  r e q u i r e s a memory  important  worked  sense  circuitry  memory  design  iteration.  working  t h e memory  b y t h e CPU a n d CRTC f r o m  on t h e o t h e r  the c i r c u i t  the  dynamic  2  complications  12 b y 16 b i t s .  to determine  internally  design  For t r a d i t i o n a l  the design  of  progress  fluctuations  i s that  the 6 t r a n s i s t o r  the addition  important  voltage  are very  simulation  i s i n  of the  i f a sophisticated  approach  [OCHII  cycle  i s that  small  employ  b i t accesses  bit  Our  designs  i s that  require  accepts  and  to avoid  would  design  sizes  the state  i s used  particularly  of t h i s  tried  read  amplifier  of d e t e c t i n g  static  to force  If a  of t h i s  small,  optimization  externally which  sense  disadvantage  such  careful  very  capable  The  meters  to comply.  The a d v a n t a g e  amplifier used.  latch  large  design  size.  array of  constraint  was t o  the s p e c i f i c a t i o n s  on t h e  willing  to s a c r i f i c e  area to  Vdd  The control  Figure  17.  first  step  and d a t a  lines  which  rows,  each  lected data for CRTC  buses. input does  because  are decoded  on  the data  signal  Yv  memory  cell  (video  y  to place  must  i s then  was  presents  t o a c o l o u r . When place  their  important  states  i t sdata  points  to note  and x d e c o d i n g  can t h e r e f o r e o n t h e CRTC 75  4  be  data  the  address  1 of the a row  16  i s se-  on t h e CRTC  the p i p e l i n e  o u t one row a t a t i m e .  select)  Cell  to determine  to select  latched into  t o t h e memory  i s read  design  the palette  corresponds  t o t h e DAC's. T h e not w r i t e  CMOS Memory  r e q u i r e d . The CRTC  o f i t s 12 b i t s The d a t a  Static  i n t h e memory  signals  of which  each  Traditional  register  are that  the  i s not required A single  used bus.  control  to f o r c e the  The  CPU,  memory  a nibble  select read the  the other at a  the s p e c i f i c  read  data  generated  clock  from  (E) goes  a n d R/W  false, buffer  delays  required that  the from  processor  The  CPU  that  when  valid  B) c a l l e d f o r nsec  read  signals  10 n s e c  bus  after  the  signal  (R)  (A4-A5)  after  capacitance  The  CPU  the data  write into  cycle  was  10  t h e memory.  therefore  goes  nsec  requires  i s the negative  signal  E  and the  f o rthe a d d i t i o n a l  i t i s latched  ( E ) . The w r i t e  i s a  * A  the data  for latching  to  as f o l l o w s :  f o r only  the s p e c i f i c a t i o n .  clock  the o f f chip  = C S ' * R/W  hold the data  be v a l i d  available  bus f o r 20-50  signals  are true  feel  will  t o meet  the data  signal  we  i f the operation  (Appendix  false.  to the  required  CS = c h i p s e l e c t R/W = p r o c e s s o r r e a d / w r i t e A = decoded p r o c e s s o r address  signals  however  and w r i t e s  are therefore  on t h e d a t a  the o f f chip  where  CS  Signals  reads  specifications  R  The  both  n i b b l e and t o s p e c i f y  t o be h e l d  enable  hand,  time.  o r a w r i t e . T h e MPR  processor was  on  The  edge of generated  as f o l l o w s :  W = C S ' * R/W'  * A  * E  where E = processor enable clock and t h e o t h e r s i g n a l s a r e d e f i n e d above  Note  that  ments. control  We  t h e CPU r e a d therefore  signals.  The  and w r i t e  had  two  first  signals  choices  approach  76  are not simply  f o r implementing was  provide  the c e l l  complet h e CPU with  x  and  y  signals  read  or  write.  select  a  signal  lines.  cell  row  would  double  to  select  The  in  be  column  selects.  was  much  easier  to  and  write  the  same  control  and  data  that  the  because  discussed number  our  of  signals  Name  The  next  structure. angles select metal read  to  step  The the  signals. and  and  IV.  which write  read row The to  the  and  supply  separate lines and  a  signal  read  and  were  false  write  second  specify  and  because  lines. in  the  Table  control  complementary  could  the  read  approaches  IV  lists  array.  signals  the  because i t  both  memory  write  lines  approach  to  are  the  Notice  required  circuitry.  Function  Control  write  in  was  lines  lines  problem  lines  to  d i f f e r e n c e s between  true  design  select  place  signal  p r o c e s s o r (CPU) data v i d e o (CRTC) d a t a v i d e o row select p r o c e s s o r row select processor read processor write  Memory  in  to  read  control  | +  Dp Dv Yv' Yp' R' W'  Yv Yp R W  the  above,  use  was  the  a l l the  d e c i s i o n to  Table  chose  required  of  third  write  the  accommodate  complements of  and  thus  We  a  provide  read  and  as  require  and  the  disabled  and  approach  array  both  signals  cell  second  the  If  the  then  and  Data  to  decide  must  because was  to  polysilicon.  i n metal  because  77  of  Signals  decide  the  the  course  they  We  on  memory  run  double which  decided write  at  as to  to  bus  right column  place place  timing  is  in the  more  WW  Vdd R'  R  Figure  Vss Dp Dv Dv  18.  Memory 78  R  Dp  Bus  Vdd R' W  W'  Structure  Dp  Dv  Vss  c r i t i c a l of  W  than  i s used  sion  is  Vdd  be must  and  must  that  the  ing  the  Vss  bus.  and  to  metal  run  we  left  two  This  is  out  and  laid place  and  bits  in  of  the  fact  how  The  mum  The  sized  inverters the  data  bit  via  the  CRTC  onto  the  schematic on  gates. Q2  and  buses the  Dv  each  Q6  with  cycle bus.  for  gate  Note  feedback  read  form  t r a n s l a t i o n s to  number  therefore  decision the  because  y  edge  dimen-  the  columns  delay.  Power  therefore  forced  array.  The  data  i t meant  upon. N o t i c e bits  also  a fanout loop is  nibble we  buses  that  can  they  was the  row.  the  form  the  the  3.  turned  the  cell  is  i t s size  sized  reflectcentral  CDS  bits rotate  times  row  and note  Two  was  shown  in  are  in  terms  about  large  Inverters  3  enough  Q 4 and  Q5  with called  gate  on  drives  by the  Yv  and  CPU  read  Figure  of  mini-  and  that  to  drive  store  transmission  during 79  the  18  array.  a l l fanouts  of  by  three  R,  Also  array.  called  memory  been  W",  nibble's  the  Finally  W,  formed  a nibble using then  Figure  nibble.  be  about  and  that  each  generated  through  Similarly,  of  nibble  indicates  that  have  Q6  array  configurations  to form  nibble  with  19.  bus  each  of  16  logic  the  negative  propagation  through  decided  reflected  command.  the  previous  adjacent  t r a n s l a t i o n s to  The  the  and  is fortunate  finally  bits  i s , the  metal.  suitable times  dimension  different  two  That  Furthermore,  minimize  in  between  right  data.  which  many  one  timing.  vertically  placed  shared  the  were  i t s x  in  tried  are  than  vertically  We  R'  the  be  be  select  latch  metal  to  also  shows  row  in  Vss  run  could  to  larger  should buses  the  Q3.  During  the  cycle  one  data Q2  is  turned that  on  by  t h e CPU  (Yp * R) w h i c h and  CRTC  read  cycles  out  any p r o b l e m s .  the  Q3  feedback  loop  i s broken.  drives  t h e new  data  into  new a  data  glitch  was  During  drives  i s latched  by  t h e CPU  QA  Q3.  o n Dv i f Y v g o e s  discussed  earlier  the data can occur  write  cycle  Ql i s turned  a n d Q5. W h e n  Note true  onto  that  and i s n o t a  Q2  i s turned  on b y  goes  a CPU w r i t e  Cell  problem.  80  Logic  false  c y c l e but  (Yp * W)'  Memory  which  i s the p o s s i b i l i t y  Q3  19.  with-  o f f and  ( Y p * W)  (Yp * R)  Figure  bus. Note  simultaneously  ( Y p * W)  there  during  t h e Dp  Schematic  the of this  The Much  effort  bridges the  stated  pays  exit  the  note  mal is  maxim  i n both  The  Given  drivers quite  have  nately  i n Figure  size  been  i n Table  we  i n t h e row  effect  our memory  at the s t i c k  stage.  The  21. Note  l i b e r a l l y  that  figures  on s e v e r a l of a f u l l y  to by  gate  were  decode  static,  bus  440  Dv Dp W' W R' R Yp' Yp Yv' Yv  16  Table  V.  m u l t i p l y by t h e o f b i t s p e r row  Memory 81  loading  Cell  Bus  Loading  on  and the data opti-  loading  i s one o f t h e  CMOS d e s i g n .  loads)  to  latch-up  to design  This  <- -+  21 <- -+ 11 110 I 4 <- -+  can  microns.  and i s not r e q u i r e d  | L o a d i n g (# o f m i n i m u m g a t e + 0 <- -+ 3 1 6 1 — m u l t i p l y by t h e 6 number o f rows I 36 1  enter  continuity.  avoid  pandable . Bus  bits  the c e l l  c i r c u i t r y . The  true  stage  f o r two  a l l buses  loads  used  of the buses.  i s small  diagram  the c a p a c i t i v e  of minimum  confirmed  and Vdd c o n t a c t s  i s 244  calculated  We  so t h a t  maintain  20.  polysilicon  layout  used  bit cell  These  of  cross.  or l a t i t u d e  and column  array  number  to the p wells  i n terms V.  i s shown i n F i g u r e  must  and s t i l l  o f t h e two  the layout  the  spent  the layout  longitude  cell  lines  time  Vss contacts  significant  deleterious  that  directions  bus i n t h e a r r a y  presented  two m e t a l  i s shown  substrate  each  when  minimizing  o f f during  that  problems.  f o r t h e memory  spent  on t h e same  repeated  Also  is  was  t h e memory  and be  diagram  required  often  always of  stick  Fortu-  t o be  ex-  Figure  20.  Memory 82  Cell  Stick  Diagram  Figure  21.  Memory 83  Cell  Layout  Pipeline  Register  The  pipeline  function cycle  of  matic.  Again,  is  control  Ql  the  when  Pclk  rising  gates.  Note  that  Q4  the  Inverters register  of  and  through  t o Q3  while  i n the second  stage  on  t h e DAC  Ql and  new  Data  i s  stored  i s true.  i s valid  i s  their passed  i n the  the negative  input  as a  to d r i v e the with  data  Pclk  sche-  loading  Q2  i s latched  The  f u l l  i t ssize  enough  stage.  the  timing  logic  minimal  i s large  with  for a  B contains  represents  i s false  that  i s valid  gate  Pclk.  guaranteeing  register  each  first  edge  i s passed  bus  structure  array.  signals  a l lof  straight  Data Pclk  shown  the  the power of  the p i p e l i n e  and power and  Pclk'  stick  wires.  bridges.  i n Figure  of  flow flow  diagram  transmission  diffusion  polysilicon  size  output  Appendix  fanout.  form  pipeline register  that  by  DAC  stage  the p i p e l i n e r e g i s t e r  on  sized  optimal  latched  memory  The  shows  two  first i n the  This  edge  of  f o r an  data Pclk  entire  cycle.  The the  to  stage  thereby Pclk  loop  i n the  then  the  (Pclk).  the number  near  feedback  stage  a  t o t h e Dv b u s a n d t h a t  with  through  22  of minimum  presented  i s  that  clock  and F i g u r e  multiple  first  ensuring  of the p i x e l  diagrams  DAC's  register  A plot  data  the p i p e l i n e  rails  i s dictated on m e t a l  h o r i z o n t a l l y on I s shown  requires  coming  only  register  cell 84  t h e memory  i s 229  by  216  23.  two  Note  i n two metal-  layout i s  of the r e g i s t e r  from  and t h e  formed  of the p i p e l i n e r e g i s t e r pitch  by  polysilicon.  i n Figure  are cleanly  layout  24. T h e h o r i z o n t a l  and  vertically  gates  The  register  i s fixed  array.  The  microns.  The  capacitive  loading  gate  and i s p r e s e n t e d  loads  Bus  on e a c h  | Loading +  6  Pclk Pclk' Dv  Table  Figure  b u s was  6 3  VI.  22.  calculated  i n Table  i n terms  VI.  (# o f m i n i m u m  gate  loads)  <--+ <  |-- m u l t i p l y by t h e n u m b e r 1o f b i t s p e r row  Pipeline  Pipeline  Register  Register 85  Bus  Logic  Loading  Schematic  of  minimum  Figure  23.  Pipeline  Register 86  Stick  Diagram  r*i  DAC  •  •  • •  _,_T  CD  •  •  -B-  • •  n  •  •  Dv  Figure  24.  Pipeline 87  Register  Layout  • •  Digital  to Analog  The  MPR  specification  resolution, within of  operate  50 n s e c ,  ways  ladder  network, or  The  Another  current approach and  a  and  counter  When  the counter circuit  approach voltages. switch. [POST  DAC  used  Snyder  i s used  formed  with  precharge  placed  the  R-2R  are  then  a  allowed  [GUY  voltage. counter-  8 2 ] . The  input  LSB  input  to  analog  increase.  the sample  voltage.  to generate be  selected  resistor  dividers  implemented results  the input  decoder  with will  along  iteration  i s shown ladder  and  Another  a l l possible by an are  pMOS, show,  array rather  with  analog possible  sixteen The  diffusion  equally  analog  A clock  ground  than  the dynamic 88  25. A  designed  CMOS  since  signal the  to conserve  precharge  signal  spaced  switches  and one o f t h e s i x t e e n  decoder. to  p r o t o t y p e was  i n Figure  i t s length.  nMOS t r a n s i s t o r s ,  on by  the  and  the r e s i s t o r  wide  i s turned  on t h e f i r s t a t MPR  as  switches  test  network  of  which  of  variety  the analog  the analog  v o l t a g e can then  configurations  called  [MACK  then  1/2  are a  generator,  the d i g i t a l  divider  +-  the d i g i t a l  to form  and  to freeze  There  4 bits  83].  analog  es  on  circuit  to zero  within  currents  ramp  hold  equals  resistor  The d e s i r e d  Warren  wire  a  analog  to have  approach,  weighted  be u s e d  and  are reset  Various  The by  an  value  common  depending  can then  i s triggered  uses  One  to  reference.  binary  sample  settle  1 volt  DAC.  uses  f o r t h e DAC  MHz,  to ground sum  ramp  hold  a  called  5.5  generates  shunted  comparator,  at  and use a  to implement  summed 82].  Converter  are  switch-  i s used decoder  area.  to was  As t h e  caused  some  noise  on t h e a n a l o g  process high  uniformity  impedance  ladder. to  voltage  reference  noise  shift  the output  A ette  new  DAC  rather  dynamic  resistor to Vss.  parallel  success.  This  any other  sufficient present  ter  s o we  gates  negative from  to reduce the  and t o p e r m i t  iteration  area.  was  was  us t o  its  pal-  with  with  however, a  pull-up  i t s gate  with  a true  tied CMOS  characteristics.  chip  because  DAC  connected i n  our p r o b a b i l i t y  complexity  t h e memory  the 3 pairs  but d i d  array  pitch  o f DAC's. T h e new  additional loading to increase  were  to maximize  the routing  89  time,  replaced  transistor  colour  implemented i n  This  was a l s o r e p l a c e d  iteration  problems  d i d n o t have  to save  DAC a n d t h e s t a t i c  increased  significant  DAC. T h e  was d o n e  circuitry  p channel  switch  to accommodate  not  pad. This  circuitry  to improve  on t h e s e c o n d  sized  i s 334 b y 5 5 0 m i c r o n s .  26. T h e d e c o d e r  CMOS, a g a i n  the dynamic  the resistor  o f 28 m i n i m u m  f o r the second  i n Figure  by a l o n g  gate  a  i f required.  designed  precharge  from  on  with  d i v i d e r was d i s c o n n e c t e d  by t h e d i g i t a l  T h e nMOS a n a l o g  Both  present  than  formed  transmission  of  was  and i s shown  nMOS,  i t s own  voltage  be t e r m i n a t e d  was made t o t h e MPR  on t h e v o l t a g e  caused  must  load  and i t s s i z e  modification  o f t h e DAC d e p e n d s  any c u r r e n t  an i n p u t  register  Vss bus and g i v e n  output  the  minor  node  shunting  T h e DAC p r e s e n t s  One  The a c c u r a c y  and t h e output  to avoid  the p i p e l i n e  the  output.  sizes.  was  DAC d i d  to the p i p e l i n e  the d r i v e r  not  regis-  O0<" J  *  11  ft  lot  !•  -n  1°  If •:  •  •:  11  •:  z:a\.  i  1  =!•  H •1  H  . I;  •  •:  !•  . I;;] .. i:  1° 1  lot  :]•[  •:  Z\D\  l°l=  Z\D\  [• [•  ;] .  1°  I;  )  1° 1°  I;1 .  !•  i: ]  .  !•  [•  Z\D\  •1=  ^  j  1  If  }  ]  ].  i  [•  A  f"1  ....  3  j  •  i  I•  1  i  f  i•  r  [[  J  •i • |  > - - I* \«(8  »w\  Figure  \Y\3  25.  Dynamic 90  •|  [•  •1  11  •| :]•[•  •1  ^•|D|  •1  n  ^•|n| •1 ^•|D|  •  [1 •1  •1 1 •1  T =!•(•! •1  -\°\  !•  : ••  (n* ^•|n| •1 [• i ^•|n| o| n  1  1  ].  •1  (•  j  }  [; 1 .  !•  [•  •:  I;1 .  z\n\n\  11  •1  *  ^•|D|  •  •:  !•  1  n  i  •  •1  •| *—  [n  1° •1  •1  ^•|D|  DAC  Layout  P •1  vss\  VQJ¥  t«rv\  inj  Figure  M«Te.<-  iwH  26.  Static 91  DAC  Layout  Input  Pad  A  simple  was  designed  can  be  used  unbuffered and  to  input  i s shown  disable  the  pad  with  in Figure  a  CMOS  27.  The  transmission  signals  en  and  pad.  Vdd  •  • •••••  • • • •  • •••••  • • • •  •  Vss  en  in  Figure  27.  Input 92  en  Pad  Layout  gate en'  Figure  28.  Process 93  Monitor  Layout  Process  A  Monitor  process  iteration device cess  monitor  prototype.  tained  a 21 s t a g e  inverter,  gate. mation sion  ring  I t was h o p e d  gates  process  would  monitor  with  a buffered  speed,  provide  i s shown  and t h a t  device  measure  output,  would  pro-  monitor  a n d a n nMOS  oscillator  to  the f a b r i c a t i o n  The p r o c e s s  t r a n s m i s s i o n gate, the ring  on t h e f i r s t  t o be a b l e  that  problems.  oscillator  that  on t h e p r o c e s s  was  and t o c o n f i r m  any gross  a pMOS  f o ri n c l u s i o n  The o b j e c t i v e  characteristics  d i dn o t have  CMOS  was d e s i g n e d  characteristics.  a large  transmission  provide  the inverter  con-  and  infor-  transmis-  A plot  ofthe  i n F i g u r e 28.  Simulat ion  A paths [CHENG  SPICE was  performed  83]. A  simulated 50  s i m u l a t i o n on s e v e r a l o f t h e c o l o u r  percent  test  to verify t o be  equivalent  chains  sults  that  our  show  design  and t h e r e s u l t s circuit t h e model  a r e summarized a  hand  of inverters  A l l  with  should  capacitive  be a s u f f i c i e n t  a l l of the design  94  circuits  were were  critical  i n Table VII  calculated  and a l l r e s u l t s  conservative.  the there  t o meet  with  palette  delay  was  increased  by  reduced  to  loading.  The r e -  s a f e t y margin i n  specifications.  Critical Path  Simulated Delay nsec  +  Yv' Yp' R' W  Table V I I .  Global  how  cells:  t h e CDS  connects 12  57 72 120 87  Critical  120 150 150 150  Path  Simulation  Results  Routing  Appendix level  Specification  +  E  pldac,  CDS  was  used  3 of the dynamic  Finally,  components  register. palette  to form  source  listings  to i n t e r c o n n e c t  Mempldac pulls  the colour  connects  together  palette  a t t h e end o f e a c h  show  the modules.  Pldac  c h i p . Note  compilation.  95  pldac  a l lof  note  top  listings  DAC's a n d 3 o f t h e s t a t i c  D E F N a n d L O C N , a n d BBOX c o m m a n d s . A l s o printed  of the three  mempldac, and p a l e t t e . These  language  b i t pipeline  array.  contains  how  DAC's  to the  to the  memory  the  remaining  the heavy  use of  diagnostics are  CHAPTER  First  7:  RESULTS  Iteration  Figure the  29 s h o w s  seven  test  periphery.  They  generator pipeline  Results  cell  a the f i r s t  circuits  register  cell  decoder  cell  (xdctest),  decoder  cell  (ydctst).  far  t o o many  given  3  that  are, clockwise (xsigtst),  pads  are from  situated  bidirectional  two  b i t memory  Because  each  bonded with  on  the  the top l e f t ,  (testpl), process  t o be  packages,  iteration prototype  buffer  of the t e s t  29.  The F i r s t 96  were  portions  bonded.  Figure  Iteration  (bdbtest),  (memtst),  We  Chip  signal  (proctest),  circuitry  i n one p a c k a g e . different  cell  Note  prototype  control  monitor cell  chip.  of  x  and a y  there are therefore the  chip  + 5  V  + 5,  Jl  0£ 3D - t >  JL  - o -  7 " a l T g . X\N  T3.fi  Tl.?,  N/C T3-OM2. lO  .Ik  T3.D\J\  £5!  Ti.55. Tl. AM  W/C N /C  70 2*  N/c. I T  T2.MOOT 8  T3.7V  . J  22. 3M  35  .  .  T3.M6S. +5  Jh.T 3 . T ? Jl  T3.W  25 23 36  Figure  30.  Static  T 2 . VSS  First 97  Iteration  Test  Circuit  7HC0M  The  circuit  process  monitor  Static  tests  gates,  and  the  to see  i n Figure i f any  confirmed  the  measured  shown  that  inverter  inverter  were  reason  we  could  careful  review  of  the  the  microscope  there  i s excess  cause  the device  devices the  n  on and  working  not  design  revealed  loading to  was  and  make as no  first  used  channel  correctly.  the  were  Figure  ring  oscillator  as  careful  errors.  a  One gain  work.  the  oscillate.  5.oJ  volts  Process  Monitor 98  A  inspection  VOltS  31.  shows  f o r some  Vout  Figure  alive.  31  possibility around  the  transmission  Unfortunately  well  insufficient  to t e s t  the c i r c u i t p  characteristics.  unknown  under  30  Inverter Characteristics  is  that  loop  to  Tests was  included  counter cycle  and the  analog  the  used  to  noise  DAC  test  that  supplies could  as  1/2 to  a  i t s  on  in  states. of  is coupled  to  reduce  the  their  to  34 the  analog  the on  33  n  which  A  were  4 used  shows  shows  32.  Dynamic 99  DAC  Test  Note was that  output. and  to the  clock  It  digital  channel  analog  resistance.  ^  Figure  bit  inputs.  a 1 MHz  Figure  through  Also  32,  binary  Next  DAC  chip.  Figure  static  noise  isolated.  dynamic  Figure  response.  this  the  separate  good l i n e a r i t y .  reduce  enlarged  a  shown  dynamic  be  on  function  LSB  should be  as  a l l of  DAC's  than  Schmiing  circuit  shows very  the  G.  buffers,  voltage  device  by  test  through  greater  switches  a  several  decided  power  performed  as  output  that  was  were  Circuit  VOUT  Loo  Vout mV  2_oo  Figure  33.  >  A  Dynamic  -  Figure  J  s  34.  *  ^  DAC  .  •  Output  "*""*  Dynamic  DAC  100  with  Static  Inputs  vf^y?77^»tj!!7M#vT^  Output  at  1  MHz  Static showed were  that  not  32  final  palette.  was  The  used  CPU  were  were  stage A  on e a c h  s e t up  o f t h e memory  detected.  backwards  a probe  with  on  resulted  to cut the output to test  the  o f t h e CPU i n p u t  that the  the input data  bus c o u l d  array  powered  write  "l"'s into  rule  up  violation  accesses  noise  could  i t . Another  indicated,  decoder  Despite  there  analog  aging.  Values  written  analog  output  voltages.  o f 13 MHz  showed  that  not tied  layout  static  problems  were  connected  The remedy thereby  was t o  making i t  problem  was  to Vss. This  fully  a n d i t was was  which  a  that meant  on and t h e r e f o r e  s t i l l  metal  i n  Finally,  significant  possible  to metal  resulted  locations.  problems  into  settled  the t e s t  t h e memory  I t was  and s t i l l  t h e DAC  lines  states.  to  design  unreliable  as  the  c o u p l i n g of  prior  digital  output.  a l l of these  excess  was  i n Figure  t o V s s . F o r t u n a t e l y t h e memory  problem  memory  the proto-  shown  pads  circuit.  turned  i n t h e "0" s t a t e  i n the y  t o t h e DAC  n o t be  circuits  to permit  cycle. Another  p a d was  test  a l l of t h e i r  output  pad power  n o t be p u l l e d  o f odd numbered  DAC t e s t s  t h e CPU  t h e CPU r e a d  pads  through  modules  performance.  to that  DIP s w i t c h e s  i n a short  impossible p-well  inputs  test  was t o t e s t  array. Several immediate  V s s and Vdd  which  circuit  These  dynamic  procedure  counter  t h e CRTC  were  correct.  of p r e d i c t i n g  i n the test  to c y c l e  of the remaining  functionally  similar  inputs  loading  use  they  performed  capable, however,  The type  tests  were  possible  obtain  3 nsec  were  encour-  confirmed  by t h e  to run the c i r c u i t  a reasonable  i n about 101  results  output.  with  a  Tests  i n also  15 p f l o a d .  To  summarize  strated  that  Second  its  the  by  enlargements  to  lier, the  a  new  chip, the  two  from  given chip. first tional sion.  us  pad  in  making  paths some a  second  increased  met.  demon-  and  that  A l l  problems  iteration  in  the  chip.  be  not  to  make  modules. and  in  minimize module  was  path  had  As  array  course  required  there  f o r the to  the  compatible  in parallel  with  bus  DAC's  DAC's was  more  the  i n -  output was  in  bonding  the  because  the  included  shown  the  modules  to  for  placements  were  tidied  lengths  decreased  102  in  separated  area  error.  were  the  attention  not  and  on  detected  sizes  were  Insufficient  y  ear-  six  difficulty  and  discussed  decrease  and  x  to  significant  violations  Power  used  the  any  was  being  rule  as  upward  included  attempt  were  module  reduced  have  memory  such  to  design  an  of  designed  supply  results  and  the  circuitry  corrected.  each  there  routing  The  pads to  for  test  because  Signal  the  designed  power  input  placement  Iteration and  were  supply  circuits  did  resulted  analog  digital  Test  resulted of  the  were  we  colour.  Protected to  was  support  was  This  each  we  individual  DAC  iteration  the  the  modules  the  DAC.  and  noise.  to  for  first  creased  the  static  dynamic  cycle on  prototype  functional  configuration. This  iteration  modifications  were  read  correct  bit  a l l of  first  CRTC  to  iteration  modules  iteration  16  Since  the  first  Refinements  second  12  decoders.  the  trivial  Iteration  final  from  for  were  For  the  a l l circuit  specification detected  then,  be  their  the  up  funcincluwhich chances  The is  4070  than  by  new  used  CAD  to  These such  were  Ltd.  A  a  we  This  chip  therefore  large  and  plotter of  array  Versatek  connected f i l e  plot  devices  required  running  on  a  the use of  on  at module  to the y  of the e n t i r e  750 the  was chip.  Interfaces  decoders.  to P a c i f i c  and  larger  VAX  sections  checking  our data  6000  is significantly  c r i t i c a l  for error  took  approximately  in size.  plots  t h e memory  check  has  section  invaluable  where  chip  iteration  blow-up  where  a final  microns  tools.  give  as  iteration  6398  the f i r s t  two  as  second  Also,  Microcircuits chip  was  gener-  ated.  Another was  important  the c r e a t i o n  found  that  when  of  documentation  such  that  references the  end  header name,  person  has  the c e l l node  this  size  names,  I t i s hoped  works  on  future  the  cell  must  be  pass  name,  and  revision  history.  that  cell  103  documentation.  t h e same  project  circuit  with  we  made  many  the  An  performance will  palette  at file  designer's refer-  enhancement  and  simulation  assist at  is  external  external  obvious  We  stan-  design  a standard  coordinates,  the c o l o u r  iteration  c o r r e c t l y assembled  our documentation  i t e r a t i o n s of  second  function,  box  be  cell  files  bounding  would  the  Integrated  multiple  a f i r s t  on  on  and  documentation  data.  As  of  work  necessity.  a l l of the f i l e s  detailed  made  form  designers  is a  of the p r o j e c t . that  ences, to  and  a standard  several  dard  each  enhancement  MPR.  whomever  Second  Iteration  We shows 36  received  eight  a photograph  shows  address,  the  counter.  Cursory different  The  cycled  and c o u l d  the majority  were  randomly  that  would  VIII  occur  access  that Chip  that  the cause  design  i n t h e same  of  DIP s w i t c h e s .  Video  #1,  the  have  chips  and 6 had  a l l three l i f e  was  were  the array that  of the d e f e c t s  would  a  had  short  control  colour  guns  and the m a j o r i t y  also  on  was  each  of  present  on  demonstrated  working,  defects  and i n c l u d e d  bits  change  only  the state  extremely expect  state  of other  t h e memory  one w o u l d  104  would  7, a n d 8 h a d  3, 4,  cells  results  of  a 4 b i t  at twice  we  f o r example,  to affect  existed  with  the eight  2,  results  bits  the test  locations  data,  chips.  o f memory  state,  error  Processor  problems.  rendering  on c h i p  seemed  Figure  operated  numbers  two  35  and  so t h a t  each  s c a t t e r e d throughout  summarizes  Determining memory  Tests  not change  Table  a  video  non-uniform  while  and b i t s  generator  on t h e s e  that  once,  was  1 a n d 5 e x h i b i t e d some  chips.  layout  the chip.  clock  address  individual  1983. F i g u r e  a l l possible values  bus p r o b l e m s  of  8,  chip  s e t up w i t h  register  concentrated  problem  test  n o t be t e s t e d . C h i p s  or address Chips  to  revealed  on J u l y  iteration  through  of observing  tests  inoperative.  chips  were  characteristics.  circuitry  tests  lines  of the video  chance  circuits  used  The p i p e l i n e  frequency better  circuit  were  bonded  of the second  and c o n t r o l  addresses  of  Results  bits.  i n chip  #1.  difficult.  If  the errors  to  the three  columns  of  F i g u r e 35.  The Second I t e r a t i o n Chip 105  I -4 c . j  "25  24  30 li-  *3S  ml  36  '3  j  1  \o\<.  x  ^ §  ra. 20  -  3^ DiJ.  -Ch — i  - — — —  .Do  s  ^  ft  Figure  36.  Second  Iteration 106  Test  Circuit  -  £•1 K j>  nibbles, not  since  the case  Memory Location  they  a r e exact  a s no l o g i c a l  | j  Gun 15 A4 = 0 A 5 = l  +-  bit  bit  duplicates  pattern  of e r r o r s  Gun A4 = l  | | +.  was  other.  This  obvious.  17 A5=0  Gun A4=0  19 A5=0  bad  bad  ok  ok  ok  ok  ok  ok  ok  ok  ok  bad  ok  ok  ok  ok  ok  ok  ok  2 bad  bit  ok  ok  4 = 0  ok  ok  ok  bit  3 = 0  ok  bad  bit  3 = 0  ok  ok  ok  ok  ok  ok  ok  ok  bits  0 once  only  ok  bits  0 once  only  ok  bad  bits  0 once  only  bad  VIII.  Chip  wa s  -+-  3 bad  bad  Table  of each  #1 Memory T e s t  107  affects  Summary  others  it 5  Chip chip to  #1.  With  confirm  data  written  one  The  the  design  The  plots  to  by  our  we  did  inconsistent back  results  than  written  data  to  read  what  we  expected.  had  no  correlation  hand  DAC's  on  the  global  routing.  to  Read  appears  to  with  bits.  a  It  the  the  bit  i t appeared  the  defective  down  to  often  to  bus  back  to  the  drivers  had  if  the  bit  Armed  the  to  therefore with  the 108  were  the  possible  state  high be  pull-down  to  of  stuck the  the  state  just  channel  unable  memory  explain  the  prior high,  defective  hypothesis n  demon-  apparent  accessing  c o r r e c t l y . Our with  to  plots.  the  to  the  was  appeared  prior  of  of  excess,  was  sixteen  previous bus  use  the  as  cause  that  the  from  in  dynamic  removes  hypothesis  data  i t  problems  and  one  noticed on  the  routed  the  by  correctly of  is  made  caused  iteration  inadvertently  which  Filtering  than  promising  low  function  bits  ground.  was  part  each  more  was  DAC  switch  works  depended  defective  data  be  second  information  generate  #1.  up  in  c r i t i c a l ,  specifically,  More  line  was  chip  come  power closed  DAC  the  dynamic  error  static  on  the  The  bus.  output  to  analog  bit  i f  confirmed  line  defective  whereas  bus  was  clock  ability  between  accessing  their  other  error  new  there  interaction  data  the  sometimes the  While  a  do  voltages  defects  contained  resulting normally  obviously  strated  to  on  dynamic  Fortunately  of  // 5  more  possible  memory  inoperative.  output  i t was  polysilicon  diffusion.  filter  even  data.  crosses  and  #1  the  chip  Only  DACs  chip  that  from  chip.  demonstrated  was halves  pull  hypothesis  that of  the  data  we  went  '1  back  and r e v i e w e d  could  be  sults  from  To  explained. chip  locations.  the  lowest  and  a bright  explained.  were  Next, light  immediately  we  into  was  shone  to accessing correctly  a high  to t h e i r  enough  on  correct  charge  when t h e b i t s  carriers  with  a  e a c h of displayed  was  the chip.  state.  used  a l l memory  t h e l i d on t h e c h i p  reverted  high  written  therefore  displayed  generated  hypothesis  low p r i o r  and the o u t p u t s  i tto f l o a t  then  returned  correctly  pull-down from  were  we  under  was  a  defects  included  scratches  foreign  material,  we  where  suspected  When zero  removed  T h e known the l i g h t s t a t e . The  on t h e d a t a  defective  bus  pull-downs  on  Since a  knew  o f t h e memory from  the chip  no d e s i g n  cell  tests  were  we  thought  error  was  f a b r i c a t i o n problem.  and  the area  i n question  no  was  visible,  however,  problem  were  obvious  gouges  elsewhere  broken on  metal  and i m p r o p e r l y  109  stripped  workthe  chips  scruti-  many  other  on t h e c h i p s .  These  lines,  the surface,  and  appar-  The  microscope  partially  and  plots  that  occurring.  we  Unfortunately  defects  sections  pin-pointed  the p l o t s  fabrication  to our layout  those  problem  placed  nized.  deep  zeroes  voltage.  incomprehensible re-  our pull-down  t h e bus s t a t e  o f f the b i t s  eliminating  ent  neatly  problems  accessed.  We  ing  t o see i f any of the  the p r e v i o u s l y  very  incandescent  apparently  were  by  bits  analog  turned  of  First,  made  bits  to cause  were  results  substantiate  This  defective  defective  Some  effect.  the  light  #5  further  photodiode  was  our test  short  circuits,  abnormal  contacts,  photoresist.  Many wafer  apparently  and b o n d i n g  procedures.  a new  wafer.  at  them  of  these  Before  problems  probable  The  second  I feel  less  decreases  that  because  came  thought  obvious  surface  during  the  requested  and  from  a  i t wise  problems.  defects  differto  look  Every  of the  of too l a r g e  feel  that  were  problems  been  resubmitted  fine  tuning  one  this  a chip  the chip  chip  There  one  nature  exist,  there  i tmust while  i s a combination size  increases.  and t o o s m a l l  probable  since  a test  approach. the  that  results A  o f t h e two. Y i e l d therefore  be  sample.  i s the that has  there  therefore  to see i f any of the  our  the performance  fabri-  observations.  Our d e s i g n  forfabrication  the  possible, i s  with  I t may  explanation  fabrication.  110  obvious  the i n c o n s i s t e n t  our microscope  mod-  be a m a r g i -  design  are problems  each  contained  however,  to chip  explain  that  a r e two  conservative  It i s likely t o meet  may  chip  explanation,  by  the chip  unchanged  disappear.  no  might  the most  with  however  i s that  This  as  demonstrated  from  possibility  rapidly  we  error  substantiated  obvious  then,  of our very  possibility  i s surely  require  that  simultaneously.  a design  of the chip.  problems  introduced  therefore  we  f o r any  correctly,  are not c o n s i s t e n t  not  We  chips  the results  First,  violation.  case  We  chips  serious  a l l functioned  nal  a  exhibited  summarize  that  third  these  were  above.  explanations.  and  bonding  functioned  cation  16 u n b o n d e d  the microscope  chips  To module  s e t of  under  described  ules  the problems  slicing  received ent  of  design  will  specifications  s t i l l but a t  least the  we  areas  may that  obtain  consistent  require  results  improvements.  Ill  from  which  we  can  locate  CHAPTER  8:  This  CONCLUSIONS  thesis  Integrated detailed design cess  that  resulted second  strate  test on  i n a scaled  down  resulted  i n a full  converters.  6000  at Microtel  devices Pacific  novel  results  were  disclosed.  rectly, evidence  albeit  resubmitted  The  pro-  first  and t h e  colour  the l a r g e s t  colour  on t h e same array  with  subthree  palette  chip  de-  stage  p a l e t t e . The  memory  size  was  circuitry,  circuitry  reported  A l lc i r c u i t  however,  con-  designed  that  each  of  112  modules  were  design  iteration.  the modules  to  and as  errors  were  iteration  functioned  such  our  functional  Second  on t h e same c h i p .  to f a b r i c a t i o n problems forfabrication.  i n the l i t e r a t u r e ,  several  f o r the second  not simultaneously  points  fabrication  palette,  test  static  aided  discussed.  colour  The f u l l  circuits  iteration,  showed  port  a  Research L t d .  many  results  size  a n d was  Unlike  and c o r r e c t e d  new  stages.  with  and as such  on c o m p u t e r  the colour  and a n a l o g  to analog  also  i n two  contributions.  of study  emphasis  was  prototype  of a dual  useful  a relatively  tested  digital  of  field  with  circuit,  and c o n s i s t s  detected  been  i s a new  a standard,  and  about  variety  ISO-CMOS,  fabricated,  the f i r s t  test  a  of the t o p i c  integrated  combines  digital  date  design  i s becoming  stage  palette  made  warranted.  novel  signed,  tains  circuit  overview  was  A  has  Most  corof the  the chip  has  In  addition  concepts design has  a  to  i n computer  methodology, very  strong  being aided the  market  an  excellent  design,  colour  such  palette  potential.  113  vehicle as  has  a  for testing  regular  many  new  structured  applications  and  BIBLIOGRAPHY  A v e n i e r , J e a n P i e r r e , " D i g i t i z i n g , L a y o u t , R u l e C h e c k i n g - The E v e r y d a y Tasks o f C h i p D e s i g n e r s " , P r o c . o f IEEE, v o l . 71, n o . 1, p p . 4 9 - 5 6 , J a n . 1 9 8 3 . B a y l i s s , J o h n A . , J . A. D e e t z , C. K. N g , S. A. O g i l v i e , C. B. P e t e r s o n , a n d D. K. W i l d e , " T h e I n t e r f a c e P r o c e s s o r f o r t h e I n t e l V L S I 432 3 2 - b i t C o m p u t e r " , I E E E J o u r n a l o f S o l i d S t a t e C i r c u i t s , v o l . S C - 1 6 , n o . 5, p p . 5 2 2 - 5 3 0 , Oct. 1981. B l a c k , K y l e M. a n d P. K e n t H a r d a g e , " A d v a n c e d S y m b o l i c Artwork P r e p a r a t i o n (ASAP)", H e w l e t t - P a c k a r d Journal, vol.32, n o . 6, p p . 8-10, June 1981. B r y a n t , R a n d a l E., "MOSSIM: A S w i t c h - L e v e l S i m u l a t o r f o r MOS LSI", 18th Design Automation C o n f e r e n c e , pp. 786-790, 1981. B u r s t e i n , M i c h a e l and R i c h a r d P e l a v i n , " H i e r a r c h i c a l R o u t e r " , I n t e g r a t i o n , v o l . 1, n o . 0, p p . 2 1 - 3 8 , Canepa, Mark, Ed Weber, a n d H a r l a n D e s i g n i n g a 3 2 - b i t CPU C h i p " , pp. 20-24, J a n . / F e b . 1983. CBEMA  Channel March 1983.  T a l l e y , "VLSI i n Focus: V L S I D e s i g n , v o l . I V , n o . 1,  (Computer and B u s i n e s s Equipment M a n u f a c t u r e r s A s s o c i a t i o n ) , " D r a f t P r o p o s e d NAPLPS S t a n d a r d D o c u m e n t # B S R X 3 . 1 1 0 - 1 9 8 X " , X3 S e c r e t a r i a t , CBEMA, 311 F i r s t S t . , NW, W a s h i n g t o n DC, 2 0 0 0 1 , 1 9 8 3 .  C h e n g , G o r d o n , "UBC L A P S y s t e m U s e r ' s M a n u a l " , D e p t . o f E l e c t r i c a l Engineering, Univ. of B r i t i s h Columbia, March 1982. Cheng, Gordon, "SPICE S i m u l a t i o n o f S e l e c t e d C r i t i c a l Path Delays f o rthe C o l o r P a l e t t e " , Dept. of E l e c t r i c a l E n g i n e e r i n g , U n i v . o f B r i t i s h C o l u m b i a , May 1 9 8 3 . C h w a n g , R o n a l d , a n d K e n Y u , "C-HMOS - A n N W e l l B u l k CMOS T e c h n o l o g y f o r V L S I " , V L S I D e s i g n , v o l . 2, n o . 4, p p . 4 2 - 4 7 , F o u r t h Q u a r t e r 1981. C o h e n , D a n n y a n d V a n c e Ty r e e , " Q u a l i t y C o n t r o l f r o m t h e S i l i c o n B r o k e r ' s P e r s p e c t i v e " , V L S I D e s i g n , v o l . 3, n o . 4, pp. 24-30, J u l y / A u g . 1982. C o n w a y , L y n n , " T h e MPC A d v e n t u r e s " , Center, 1981.  Xerox  C o n w a y , L y n n , " T h e M I T '78 V L S I S y s t e m Systems A r e a , Xerox P A R C , 1979.  114  Palo  Design  Alto  Research  Course", L S I  Cook,  P. W., S. E . S c h u s t e r , J . T. P a r r i s h , V. D i l o n a r d o , a n d D. R. F r e e d m a n , "1 um MOSFET V L S I T e c h n o l o g y : P a r t I I I Logic C i r c u i t Design Methodology and Applications", I E E E T r a n s , o n E l e c t r o n D e v i c e s , v o l . E D - 2 6 , n o . 4, pp. 3 3 3 - 3 4 6 , A p r i l 1979.  C o r b i n , L . V., " C u s t o m V L S I E l e c t r i c a l R u l e C h e c k i n g i n Intelligent T e r m i n a l " , 18th IEEE D e s i g n Automation C o n f e r e n c e , pp. 696-701, 1981. CSA  an  (Canadian Standards A s s o c i a t i o n ) , " P r e l i m i n a r y Standard T500-1982 V i d e o t e x / T e l e t e x t P r e s e n t a t i o n L e v e l Protocol Syntax (North American PLPS)", August 1982.  Dwivedi, Kamalesh, IC CAD, Mitel  "A R e p o r t on MOS Model Changes Corporation, April 1982.  in  SPICE2F",  E l m a s r y , M. I . , " S t i c k - L a y o u t N o t a t i o n f o r B i p o l a r VLSI", V L S I D e s i g n , v o l . 4, n o . 2, p p . 6 5 - 6 9 , M a r . / A p r . 1983. E s t r e i c h , D o n a l d B. a n d R o b e r t W. D u t t o n , " M o d e l i n g Latch-Up i n CMOS I n t e g r a t e d C i r c u i t s " , I E E E T r a n s , on CAD o f I C ' s a n d S y s t e m s , v o l . CAD-1, n o . 4, p p . 1 5 7 - 1 6 2 , O c t . 1982. F a i r b a i r n , D o u g l a s G., "VLSI: D e s i g n e r s " , C o m p u t e r , pp  A New Frontier for 87-96, J a n . 1982.  F e u e r , M i c h a e l , " V L S I D e s i g n A u t o m a t i o n : An P r o c . o f t h e I E E E , v o l . 71, n o . 1, p p .  Systems  Introduction", 5-9, J a n . 1983.  F l e i s h e r , H. a n d L . I . M a i s s e l , "An I n t r o d u c t i o n t o L o g i c " , IBM J o u r n a l o f R e s . D e v e l o p . , v o l . 19, March 1975.  Array pp. 98-109,  F l e m i n g , J i m a n d W i l l i a m F r e z z a , " N A P L P S : A New Standard f o r T e x t a n d G r a p h i c s " , B y t e , P a r t 1: v o l . 8, n o . 2, p p . 2 0 3 - 2 5 4 , F e b . 1 9 8 3 ; P a r t 2: v o l . 8, n o . 3, p p . 152-186, Mar. 1983; P a r t 3: v o l . 8, n o . 4, p p . 1 9 0 - 2 0 6 , A p r i l 1983; P a r t 4: v o l . 8, n o . 5, p p . 2 7 2 - 2 8 4 , May 1983. Gale,  Dan, "VLSI i n Canada", VLSI Implementation Q u e e n ' s U n i v e r s i t y , v o l . 1, n o . 1, p p . 1-4,  Centre, April 1983.  G l a s e r , A r t h u r B. a n d G e r a l d E . S u b a k - S h a r p e , " I n t e g r a t e d C i r c u i t E n g i n e e r i n g " , Addison-Wesley, p p . 2, 1977. G l a s s e r , L a n c e A. a n d P a u l P e n f i e l d , "An I n t e r a c t i v e PLA G e n e r a t o r a s a n A r c h e t y p e f o r a New VLSI Design Methodology", I E E E I n t . C o n f . on C i r c u i t s a n d C o m p u t e r s , 1980. G o a t e s , G. B., T. R. H a r r i s , R. E . O e t t e l , a n d H. M. W a l d r o n I I I , " S t o r a g e / L o g i c A r r a y D e s i g n : Reducing Theory to P r a c t i c e " , V L S I D e s i g n , v o l . 3, n o . 4, p p . 5 6 - 6 2 , J u l y / A u g . 1982.  115  Goto,  S a t o s h i "An E f f i c i e n t A l g o r i t h m f o r t h e T w o - D i m e n s i o n a l Placement Problem i n E l e c t r i c a l C i r c u i t Layout", I E E E T r a n s , on C i r c u i t s a n d S y s t e m s , v o l . C A S - 2 8 , n o . 1, p p . 1 2 - 1 8 , J a n . 1 9 8 1 .  Griswold, VLSI  Tom, " P o r t a b l e D e s i g n R u l e s f o r B u l k CMOS", D e s i g n , v o l . 3, n o . 5, p p . 6 2 - 6 7 , S e p . / O c t . 1 9 8 2 .  G u l e t t , M i c h a e l R., " T h e CMOS n o . 4, p p . 5 0 - 5 2 , F o u r t h Guy,  C o n t r o v e r s y " , VLSI Q u a r t e r 1981.  Design,  v o l . 2,  Thomas S., L i n d a M. T r y t h a l l , a n d A r t h u r J . B r o d e r s e n , "A S i x t e e n - B i t M o n o l i t h i c B i p o l a r DAC", I E E E J o u r n a l o f S o l i d S t a t e C i r c u i t s , v o l . S C - 1 7 , n o . 6, p p . 1 1 2 7 - 1 1 3 2 , Dec. 1982.  H a c h t e l , G a r y D. a n d A. S a n g i o v a n n i - V i n c e n t e l l i , "A S u r v e y o f T h i r d - G e n e r a t i o n S i m u l a t i o n Techniques", Proc. of IEEE, v o l . 69, n o . 10, p p . 1 2 6 4 - 1 2 8 0 , O c t . 1 9 8 1 . H a y d a m a c k , W. J . a n d D. J . G r i f f i n , " V L S I and T o o l s " , H e w l e t t - P a c k a r d J o u r n a l , pp. 5-12, June 1981.  Design Strategies v o l . 3 2 , n o . 6,  H e p l e r , E d w a r d L e e , "A F u n c t i o n a l S i m u l a t i o n S y s t e m f o r MSI and L S I S y s t e m s " , Ph.D. T h e s i s , D r e x e l U n i v . , J u n e 1 9 7 9 . H e u f t , R i c k , " A l b e r t a H i g h - L e v e l L a n g u a g e - AHF", V L S I v o l . 1, n o . 1, p p . 1 0 - 1 3 , A p r i l 1 9 8 3 .  i n Canada,  Hewlett-Packard, Oct. 1980.  "HPSPICE  DA320.3c,  Hewlett-Packard, June 1981.  "DRAW  User's  User's  Manual",  Manual",  Design  Design  Aids,  Aids,  DA180.1d,  Hon,  R o b e r t W. a n d C a r l o H. S e q u i n , "A G u i d e t o L S I Implementation", Xerox P a l o A l t o R e s e a r c h C e n t e r , 1980.  Hong,  Se J u n e a n d R a v i N a i r , T o o l s f o r VLSI P h y s i c a l n o . 1, p p . 5 7 - 6 5 , J a n .  "Wire-Routing Machines - New D e s i g n " , P r o c . o f IEEE, v o l . 71, 1983.  I n t e c h , " H y b r i d T r i p l e 4 B i t C o l o r Mapped V i d e o Preliminary Specifications", Microcircuits I n t e c h I n c . , p p . 1-6, 1 9 8 2 . Intel,  "MCS-80/85  Family  User's  Manual",  DAC (RGB DAC 4 T ) Division,  p p . 4-1, O c t .  1979.  J a n s e n , W. D. a n d D. G. F a i r b a i r n , " T h e S i l i c o n Foundry: C o n c e p t s a n d R e a l i t y " , L a m b d a , v o l . 2, n o . 1, p p . 1 6 - 2 6 , F i r s t Q u a r t e r 1981.  116  J e n n e , D a v i d C. a n d D a v i d A. Stamm, " M a n a g i n g V L S I Complexity: A U s e r ' s P e r s p e c t i v e " , V L S I D e s i g n , v o l . 3, n o . 2, pp. 14-20, M a r c h / A p r i l 1982. Jones, Morton E., "Semiconductors: The Key t o C o m p u t a t i o n a l P l e n t y " , P r o c . o f I E E E , v o l . 70, n o . 12, p p . 1380-1409, Dec. 1982. Kang,  S u n g Mo, "A D e s i g n o f CMOS P o l y c e l l s f o r L S I C i r c u i t s " , I E E E T r a n s , on C i r c u i t s a n d S y s t e m s , v o l . C A S - 2 8 , n o . 8, pp. 838-843, A u g u s t 1981.  K i n o s h i t a , G. a n d M. B e g u w a l a , "SOS - A C a n d i d a t e f o r V L S I " , L a m b d a , v o l . 2, n o . 2, p p . 7 0 - 7 3 , S e c o n d Q u a r t e r 1 9 8 1 . K r a m b e c k , R. H., C h a r l e s M. L e e , a n d H u n g - F a i S t e p h e n Law, " H i g h - S p e e d C o m p a c t C i r c u i t s w i t h CMOS", I E E E J o u r n a l o f S o l i d S t a t e C i r c u i t s , v o l . S C - 1 7 , n o . 3, p p . 6 1 4 - 6 1 8 , June 1982. Lang,  D., " L A P U s e r ' s M a n u a l " , S i l i c o n S t r u c t u r e s SSP F i l e #3356, C a l t e c h , D e c . 1 9 7 9 .  Project,  L a t t i n , W i l l i a m W., " V L S I D e s i g n M e t h o d o l o g y : T h e P r o b l e m s o f t h e 80's f o r M i c r o p r o c e s s o r D e s i g n s " , F i r s t C a l t e c h C o n f e r e n c e on V L S I , J a n u a r y 1 9 7 9 . L a t t i n , W. W., J . A . B a y l i s s , D. L . B u d d e , J . R. R a t t n e r , W. S. R i c h a r d s o n , "A M e t h o d o l o g y f o r V L S I C h i p D e s i g n " , L a m b d a , v o l . 2, n o . 2, p p . 3 4 - 4 4 , 2nd q u a r t e r 1 9 8 1 . Lax,  L e o a n d M a r k O l s e n , "NAPLPS S t a n d a r d G r a p h i c s a n d t h e Microcomputer", B y t e , v o l . 8, n o . 7, p p . 8 2 - 9 2 , J u l y 1 9 8 3 .  L i p m a n , J i m , " L a t c h u p P r e v e n t i o n i n B u l k P - W e l l CMOS C i r c u i t s " , V L S I D e s i g n , v o l . 3, n o . 3, p p . 3 0 - 3 0 , M a y / J u n e 1 9 8 2 . L o n d o n , A r n i e , " T w o - L a y e r M e t a l CMOS v s . T w o - L a y e r P o l y CMOS", V L S I D e s i g n , v o l . 4, n o . 2, p p . 6 2 - 6 3 , M a r . / A p r . 1 9 8 3 . Lyon,  R i c h a r d F., " S i m p l i f i e d Design Rules f o rVLSI L a y o u t s " , L a m b d a , v o l . 2, n o . 1, p p . 5 4 - 5 9 , F i r s t Q u a r t e r 1 9 8 1 .  Mack,  W i l l i a m D., M a r k H o r o w i t z , a n d R o b e r t A . B l a u s c h i l d , "A 14 B i t D u a l - R a m p DAC f o r D i g i t a l - A u d i o Systems", I E E E J o u r n a l o f S o l i d S t a t e C i r c u i t s , v o l . S C - 1 7 , n o . 6, pp. 1118-1126, D e c . 1982.  Mead,  C a r v e r a n d L y n n Conway, Addison-Wesley, 1980.  " I n t r o d u c t i o n t o VLSI  Systems",  M e r c e r , M e l v i n Ray, " D i g i t a l D e s i g n f o r T e s t a b i l i t y and C o n c u r r e n t F a u l t D e t e c t i o n i n L S I and VLSI D e v i c e s " , Ph.D. T h e s i s , U n i v . o f Texas a t A u s t i n , August 1980.  117  Mitel, "An I n t r o d u c t i o n t o ISO-CMOS T e c h n o l o g y " , A p p l i c a t i o n N o t e MSAN-104, O c t . 1 9 8 1 .  Mitel  Corp.,  Newton, A r t h u r R i c h a r d , "The S i m u l a t i o n o f L a r g e S c a l e I n t e g r a t e d C i r c u i t s " , Ph.D. T h e s i s , U n i v . o f C a l i f o r n i a a t B e r k e l e y , J u l y 1978. Newton, A r t h u r R i c h a r d , " T e c h n i q u e s f o r t h e S i m u l a t i o n of L a r g e S c a l e I n t e g r a t e d C i r c u i t s " , I E E E T r a n s , on C i r c u i t s a n d S y s t e m s , v o l . C A S - 2 6 , n o . 9, p p . 7 4 1 - 7 4 9 , S e p t . 1 9 7 9 . Newton, A r t h u r R i c h a r d , " C o m p u t e r - A i d e d D e s i g n o f VLSI Circuits", P r o c . o f I E E E , v o l . 6 9 , n o . 10, p p . 1 1 8 9 - 1 1 9 9 , O c t . 1 9 8 1 . N e w t o n , A r t h u r R i c h a r d , D o n a l d 0. P e d e r s o n , A. S a n g i o v a n n i V i n c e n t e l l i , a n d C. S e q u i n , " D e s i g n A i d s f o r V L S I : T h e B e r k e l e y P e r s p e c t i v e " , I E E E T r a n s , on C i r c u i t s a n d S y s t e m s , v o l . C A S - 2 8 , n o . 7, p p . 6 6 6 - 6 8 0 , J u l y 1 9 8 1 . N i e s s e n , C , " H i e r a r c h i c a l D e s i g n M e t h o d o l o g i e s and T o o l s f o r V L S I C h i p s " , P r o c . o f I E E E , v o l . 7 1 , n o . 1, p p . 6 6 - 7 5 , Jan. 1983. Noy c e , R o b e r t N., " M i c r o e l e c t r o n i c s " , S c i e n t i f i c v o l . 2 3 7 , n o . 3, p p . 6 3 - 6 9 , S e p t . 1 9 7 7 .  American,  O c h i i , K., K. H a s h i m o t o , H. Y a s u d a , M. M a s u d a , T. K o n d o , H. N o z a w a , a n d S. K o h y a m a , "An U l t r a l o w P o w e r 8K x 8 - B i t F u l l CMOS RAM w i t h S i x - T r a n s i s t o r C e l l " , I E E E J o u r n a l o f S o l i d S t a t e C i r c u i t s , v o l . S C - 1 7 , n o . 5, p p . 7 9 8 - 8 0 3 , Oct. 1982. P a r r i l l o , L . C , R. S. P a y n e , R. E . D a v i s , G. W. R e u t l i n g e r , a n d R. L . F i e l d , " T w i n - T u b CMOS - A T e c h n o l o g y f o r V L S I C i r c u i t s " , IEEE I n t . E l e c t r o n D e v i c e s M e e t i n g , pp. 752-755, 1980. P a t i l , S. S. a n d T. A. W e l c h , "A P r o g r a m m a b l e L o g i c Approach f o r V L S I " , I E E E T r a n s , o n C o m p u t e r s , v o l . C - 2 8 , n o . 9, pp. 594-601, S e p t . 1979. Posa,  J o h n G., "C-MOS I n s p i r e s t h e B e s t C h i p s Y e t f o r C o m p u t e r , Consumer, and Communication A p p l i c a t i o n s " , Electronics, v o l . 5 4 , n o . 2 0 , p p . 1 0 3 - 1 0 5 , O c t . 6, 1 9 8 1 .  Post,  H a n s - U l r i c h a n d K a r l S c h o p p e , "A 14 B i t M o n o t o n i c NMOS D/A C o n v e r t e r " , I E E E J o u r n a l o f S o l i d State C i r c u i t s , v o l . S C - 1 8 , n o . 3, p p . 2 9 7 - 3 0 1 , J u n e 1 9 8 3 .  P r e a s , B r y a n Thomas, " P l a c e m e n t and R o u t i n g A l g o r i t h m s f o r H i e r a r c h i c a l I n t e g r a t e d C i r c u i t L a y o u t " , Ph.D. T h e s i s , S t a n f o r d U n i v . , August 1979.  118  P u l f r e y , D a v i d L . , "An E x p a n d a b l e , F u l l y A s y n c h r o n o u s CMOS S t a t i c RAM f o r t h e MPR C e l l L i b r a r y " , M i c r o t e l Pacific R e s e a r c h L t d . , J u n e 9, 1 9 8 3 . R a e t h , P e t e r G., J o h n M. A c k e n , G a r y B. L a m o n t , a n d J o h n M. B o r k y , " F u n c t i o n a l M o d e l l i n g f o r L o g i c S i m u l a t i o n " , 18th IEEE D e s i g n Automation C o n f e r e n c e , 1981. R o f f e l s e n , L a r r y , "Gate A r r a y s : A U s e r ' s P e r s p e c t i v e " , Lambda, v o l . 2, n o . 1, p p . 3 2 - 3 6 , F i r s t Q u a r t e r 1 9 8 1 . R u e h l i , A l b e r t E . a n d G a r y S. D i t l o w , " C i r c u i t L o g i c S i m u l a t i o n , and Design V e r i f i c a t i o n P r o c . o f I E E E , v o l . 7 1 , n o . 1, p p . 3 4 - 4 8 ,  Analysis, f o r VLSI", J a n . 1983.  S c h m i i n g , G e r h a r d , "Hardware F u n c t i o n a l S p e c i f i c a t i o n f o r C o l o r P a l e t t e Integrated C i r c u i t " , M i c r o t e l P a c i f i c Research L t d . , August 1982. S c h o f i e l d , D a r r y l a n d D. F a i r b a i r n , " S t u m b l i n g B l o c k s t o G a t e A r r a y A c c e p t a n c e " , L a m b d a , v o l . 2, n o . 2, p p . 1 6 - 1 7 , Second Q u a r t e r 1981. S e q u i n , C a r l o H., " M a n a g i n g V L S I C o m p l e x i t y : An O u t l o o k " , P r o c . o f I E E E , v o l . 7 1 , n o . 1, p p . 1 4 9 - 1 6 6 , J a n . 1 9 8 3 . Sequin,  C a r l o H., " V L S I  Design",  Hellman  A s s o c i a t e s , 1981.  S h i v a , S a j j a n G., " A u t o m a t e d H a r d w a r e S y n t h e s i s " , P r o c . o f I E E E , v o l . 7 1 , n o . 1, p p . 7 6 - 8 7 , J a n . S i m m o n s , A . , "ISO-CMOS J a n . 14, 1 9 8 2 .  Process  Sequence",  GTE  1983.  Ltd.,  S m i t h , D a v i d , " N o r t h e r n T e l e c o m E l e c t r o n i c s 4um CMOS P r o c e s s "CM0S1B" D e s i g n I n f o r m a t i o n a n d G u i d e l i n e s " , Semiconductor C o m p o n e n t s G r o u p , N o r t h e r n T e l e c o m L t d . , May 1 9 8 3 . S m i t h , K. F., T. M. C a r t e r , a n d C. E . H u n t , " S t r u c t u r e d L o g i c Design of Integrated C i r c u i t s Using the Storage/Logic A r r a y ( S L A ) , IEEE T r a n s , on E l e c t r o n D e v i c e s , v o l . ED-29, n o . 4, p p . 7 6 5 - 7 7 6 , A p r i l 1 9 8 2 . S n y d e r , W a r r e n , "CMOS D e s i g n R e s e a r c h L t d . , 1982.  System",  Microtel  Soukup, J i r i , " C i r c u i t L a y o u t " , P r o c . pp. 1281-1304, O c t . 1981.  o f IEEE,  Sze,  Devices",  S. M., " P h y s i c s Sons, 1969.  of Semiconductor  Pacific  v o l . 6 9 , n o . 10,  John  Wiley and  S z i r o m , S t e v e , "Custom/Semicustorn IC I n d u s t r y B u s i n e s s U p d a t e " , V L S I D e s i g n , v o l . 4, n o . 1, p p . 3 0 - 3 4 , J a n . / F e b . 1 9 8 3 .  119  T h o m a s , D o n a l d E . , "The A u t o m a t e d S y n t h e s i s o f D i g i t a l Systems", P r o c . o f I E E E , v o l . 6 9 , n o . 10, p p . 1 2 0 0 - 1 2 1 1 , O c t . 1981. Trimberger, Stephen, v o l . 19, n o . 6,  "Automating Chip Layout", pp. 38-45, June 1982.  IEEE  Spectrum,  T r i m b e r g e r , S t e p h e n , J a m e s A. R o w s o n , C h a r l e s R. L a n g , and J o h n P. G r a y , "A S t r u c t u r e d D e s i g n M e t h o d o l o g y and A s s o c i a t e d S o f t w a r e T o o l s " , I E E E T r a n s , on C i r c u i t s and S y s t e m s , v o l . C A S - 2 8 , n o . 7, p p . 6 1 8 - 6 3 4 , J u l y 1981. Tsui,  F r a n k F., " I n - S i t u T e s t a b i l i t y D e s i g n ( I S T D ) - A New Approach f o r T e s t i n g High-Speed LSI/VLSI Logic", Proc. I E E E , v o l . 70, n o . 1 , p p . 5 9 - 7 8 , J a n . 1982.  of  T u c k e r , M i c h a e l G. a n d W i l l i a m J . H a y d a m a c k , " V L S I D e s i g n and A r t w o r k V e r i f i c a t i o n " , H e w l e t t - P a c k a r d J o u r n a l , v o l . n o . 6, p p . 2 5 - 2 8 , J u n e 1981.  32,  V l a d i m i r e s c u , A n d r e i and S a l l y L i u , "The S i m u l a t i o n o f MOS I n t e g r a t e d C i r c u i t s U s i n g SPICE2", E l e c t r o n i c s Research L a b o r a t o r y , C o l l e g e of E n g i n e e r i n g , U n i v . of B e r k e l e y , Feb. 1980. Weber, Samuel, Ed., " F i f t y E l e c t r o n i c s , v o l . 53,  Years of Achievement: A History", n o . 9, c h a p t e r 5, A p r . 17, 1980.  Weinberger, A r n o l d , " L a r g e S c a l e I n t e g r a t i o n o f MOS Complex L o g i c : A Layout Method", IEEE J o u r n a l of S o l i d - S t a t e C i r c u i t s , v o l . S C - 2 , n o . 4, p p . 1 8 2 - 1 9 0 , D e c . 1967. W e r n e r , J e r r y , " R e c e n t P r o g r e s s i n CAD S y s t e m s f o r I C L a y o u t " , V L S I D e s i g n , v o l . 4, n o . 3, p p . 4 8 - 5 9 , M a y / J u n e 1983. W e r n e r , J e r r y , "The S i l i c o n C o m p i l e r : P a n a c e a , W i s h f u l T h i n k i n g , o r O l d H a t ? " , V L S I D e s i g n , v o l . 3, n o . 5, pp. 46-52, S e p t . / O c t . 1982. W e r n e r , J e r r y , "A S u r v e y o f S i l i c o n F o u n d r i e s " , V L S I v o l . 3, n o . 4, p p . 4 2 - 4 9 , J u l y / A u g . 1982. Werner, J e r r y , "Software f o r Gate-Array A i d i n g Whom", V L S I D e s i g n , v o l . 2, Fourth Quarter 1981. W h i t n e y , T e l l e , "A H i e r a r c h i c a l L a m b d a , v o l . 2, n o . 1, p p . W i l l i a m s , Thomas Testability pp. 98-112,  Design,  D e s i g n : Who i s Really n o . 4, p p . 2 2 - 3 2 ,  Design-Rule Checking 40-43, F i r s t Q u a r t e r  Algorithm", 1981.  W. a n d K e n n e t h P. P a r k e r , " D e s i g n f o r - A S u r v e y " , P r o c . o f I E E E , v o l . 71, no. Jan. 1983.  1,  Yoshimura, T a k e s h i a n d E r n e s t S. K u h , " E f f i c i e n t A l g o r i t h m s f o r C h a n n e l R o u t i n g " , I E E E T r a n s , on C o m p u t e r A i d e d D e s i g n , v o l . CAD-1, n o . 1, p p . 2 5 - 3 5 , J a n . 1982. 120  APPENDIX  A  S c h e m a t i c s and B l o c k Diagrams of t h e M i c r o t e l P a c i f i c Research L t d . D i s c r e t e Component C o l o u r P a l e t t e Implementation  121  c  124  APPENDIX Colour  Palette  126  B  Specificati  MICROTEL P A C I F I C RESEARCH  HARDWARE FUNCTIONAL S P E C I F I C A T I O N FOR COLOR PALETTE INTEGRATED  P r e p a r e d by G.  Schmiing  A u g u s t 17,  1982  127  CIRCUIT  CONTENTS  1.  GENERAL DESCRIPTION 1.1 C o l o r P a l e t t e P i n D e s c r i p t i o n  2 2  2.  PIN DESCRIPTION 2.1 PROCESSOR INTERFACE 2.1.1 Data Bus (D0-D3) 2.1.2 Enable (E) 2.1.3 C h i p S e l e c t (CS) 2.1.4 Address Bus (AO-A5) 2.1.5 Read/Write (R/W) 2.2 VIDEO INTERFACE 2.2.1 P i x e l Data (P0-P3) 2.2.2 P i x e l C l o c k (PC) 2.2.3 D i s p l a y Enable (DE) 2.2.4 V i d e o Output (V0-V2) 2.2.5 Reference V o l t a g e ( V r e f ) . . 2.2.6 C o l o r P a l e t t e Memory O r g a n i z a t i o n  3 3 3 3 3 3 3 4 4 4 4 4 4 5  •  3.  VIDEO TIMING 3.1 VIDEO TIMING CHARACTERISTICS.  6 6  4.  PROCESSOR TIMING 4 . 1 PROCESSOR TIMING CHARACTERISTICS  7 7  5.  BLOCK DIAGRAM  8  128  - 2 1.  GENERAL DESCRIPTION  The C o l o r P a l e t t e b a s i c a l l y c o n s i s t s o f a n u l t i p o r t e d register a r r a y whose outputs d i r e c t l y d r i v e t h r e e v i d e o DAC's. The p r o c e s s o r * independent o f the v i d e o a c c e s s , has f u l l r e a d , w r i t e c a p a b i l i t y o f the i n t e r n a l r e g i s t e r s . The r e g i s t e r a r r a y appears as 16 c o l o r v a l u e s a t 12 b i t s per value t o the v i d e o i n t e r f a c e , and as 64 words a t 4 b i t s per word t o the h o s t p r o c e s s o r . See f i g . 1 Memory O r g a n i z a t i o n . C o l o r t r a n s l a t i o n i s performed by the 4 b i t p i x e l data (POPS) , a d d r e s s i n g one o f the 16 r e g i s t e r s i n the lookup t a b l e . The c o l o r v a l u e s t o r e d i n t h a t r e g i s t e r d r i v e s the t h r e e v i d e o DAC's, which produce an analog v i d e o s i g n a l p r o p o r t i o n a l t o the d i g i t a l v a l u e . T h i s v i d e o s i g n a l i s used t o d r i v e the RED, GREEN, BLUE i n p u t s o f a c o l o r monitor. As a r e s u l t the V i d e o C o n t r o l l e r c o l o r s o u t o f a r e p e r t o i r e o f 4096. 1.1  can  now  display  any  16  Color P a l e t t e P i n D e s c r i p t i o n  +5V  Ao-As Processor Interface  VDD  D0-D3  VO  ->  CS  VI  ->  E  V2  R/W P0-P3 Display Memory Interface  Vref  ->  Pclk  ->  DE  Vss  GND  129  <  Ref. Voltage  Video Output  - 3 2.  PIN DESCRIPTION  2.1  PROCESSOR INTERFACE  The P r o c e s s o r i n t e r f a c e s t o the C o l o r P a l e t t e v i a a b i d i r e c tional d a t a bus (D0-D3) u s i n g (A0-A5),CS,E and ,R/W f o r c o n t r o l s signals. 2.1.1  Data Bus (D0-D3)  The b i d i r e c t i o n a l data l i n e s (D0-D3) a l l o w d a t a t r a n s f e r s between the C o l o r P a l e t t e r e g i s t e r and the p r o c e s s o r . Data bus d r i v e r s a r e h i g h impedance u n t i l a read c y c l e . 2.1.2  Enable  (E)  The Enable s i g n a l i s a h i g h impedance, TTL compatible i n p u t which c l o c k s data t o and from the C o l o r P a l e t t e . The high t o low t r a n s i t i o n i s the a c t i v e edge. 2.1.3  C h i p S e l e c t (CS)  The CS s i g n a l i s a h i g h impedance, TTL compatible input which selects the C o l o r P a l e t t e , when low, t o read o r w r i t e t o the i n t e r n a l r e g i s t e r f i l e . 2.1.4  Address Bus (AO-A5)  The Address Bus s i g n a l s (A0-A5) are h i g h impedance, TTL compatible i n p u t s which s e l e c t s one o f the 4 8 r e g i s t e r s t o be w r i t t e n o r read. Data t r a n s f e r s a r e then performed under the cont r o l o f CS, E , R/W s i g n a l s . 2.1.5  Read/Write  (R/W)  The R/W s i g n a l i s a h i g h impedance, TTL compatible input which determines whether the i n t e r n a l r e g i s t e r s a r e w r i t t e n or read. A w r i t e i s d e f i n e d as a low l e v e l .  130  - 4 2.2  VIDEO INTERFACE  The V i d e o i n t e r f a c e V i d e o C o n t r o l l e r , and LOOKUP t a b l e t o a 12 b i t c o n v e r t e d by t h r e e v i d e o BLUE). 2.2.1  P i x e l Data  accepts p i x e l data (P0-P3) from the translates the data through the C o l o r c o l o r v a l u e . T h i s 12 b i t c o l o r v a l u e i s DAC's t o the analog s i g n a l s (RED, GREEN,  (P0-P3)  The P i x e l Data s i g n a l s (P0-P3) a r e h i g h impedance, TTL c o m p a t i b l e i n p u t s which a c t as address i n p u t s t o the c o l o r look.up table. 2.2.2  P i x e l Clock  (PC)  The PC c l o c k s i g n a l i s a h i g h impedance, TTL compatible i n p u t which l o a d s the c o l o r p i p e l i n e r e g i s t e r a f t e r the access time of the lookup t a b l e . The low to high transition i s the a c t i v e edge. 2.2.3  D i s p l a y Enable  (DE)  The DE s i g n a l i s a h i g h impedance, TTL compatible which d i s a b l e s the v i d e o output by c l e a r i n g the p i p e l i n e t e r . T h i s i n p u t i s a c t i v e low. 2.2.4  V i d e o Output  (V0-V2)  The t h r e e v i d e o outputs are analog the t h r e e v i d e o DAC's. i n p u t s o f a c o l o r 2.2.5  input regis-  signals monitor.  generated  by  Reference V o l t a g e (Vref)  T h i s i n p u t a p p l i e s a user s u p p l i e d v o l t a g e r e f e r e n c e t o the r e s i s t i v e d i v i d e c h a i n o f the d i g i t a l t o analog c o n v e r t e r .  131  -. 5 2.2.6  Color Palette Memory Organization  PROCESSOR ACCESS  7 0  •  DATA BUS 3 ****  0  RED  1  GREEN  2  BLUE  3  *  4  RED  5  GREEN  6  BLUE  7  *  60  RED  61  GREEN  62  BLUE  63  *  VIDEO ACCESS •  COLOR WORD 1  COLOR WORD 2  COLOR WORD 16  132  - 6 3.  VIDEO TIMING  |< PIXEL CLK  Tp  /—*v 7V_J^ j<—  MEMORY DATA  V  PIPELINE REGISTER  VIDEO OUTPUT  I<— Ts  \  /  /  Tp Tad Ta Th Ts  A Ta — > I  VIDEO TIMING  A  A  -\Z7-  V  7  —>I  SYMBOL  r  I < — Tad  MEMORY ADDRESS  3.1  >|  V  \  /  V  /  CHARACTERISTICS  MAX  CHARACTERISTIC P i x e l c l o c k c y c l e time Address a f t e r Pclk R e g i s t e r access time C o l o r data h o l d time DAC s e t t l i n g t i m e +- 1/2 L S B  Resolution Output r e s i s t a n c e Output V o l t a g e  180 20 20 20 50  WIN  nsec nsec nsec nsec nsec  20 n s e c  4 bits 1 * • 0 - 4 volts o  133  n  m  roax  - 7 4.  PROCESSOR TIMING  |< E CLK  Tcyc  •v  ADDRESS  { 7  CS  ->|  , / |  n < -  A  7  Tcs DATA  /"  ->|~1  A  Tddr->|  T  h  /-  U  -> I I<<" Thw Jf  !<-  h  -v—:7.  ->I|<-  Tdsw  PROCESSOR TIMING CHARACTERISTICS  SYMBOL Tcyc Tas Tah Tcs Tch Tddr Trh Tdsw Thw  a  Tl<- ^  WRITE DATA  4.1  T  /  1  READ  l  \  \ Tas  R/W,  >  MIN  CHARACTERISTIC  500 40 10 40 10  E c y c l e time Address setup time b e f o r e E Address h o l d time R/W, CS s e t u p t i m e b e f o r e E R/W, CS h o l d t i m e Read d a t a d e l a y t i m e Read d a t a h o l d t i m e Write data setup time W r i t e data h o l d time  0  20 50 60  134  nsec nsec nsec nsec nsec nsec nsec nsec nsec  MAX  150 n s e c 50 nsec 20 nsec  BLOCK DIAGRAM  APPENDIX GTE  ISO-CMOS  C  Process  J  138  Sequence  ISO - CMOS  139  Oxldr  140  A. Simons January 14, 1982  141  A. Simons January 14, 1982  Nitride  Photo Rosltt  Nltrldo Nltrld*  llll A (  X O » I N  |  •PHIIM  !mp!anK O x i d e  Nltox MltrS*«  Hltrld* Hltox  144  Mltox  Nltoz  Field Oxld*  Nltrld*  145  Nltrld*  Nltrld*  1A6  Gsto Oxld* Polysilicon  rely  148  B8K OS  foiy  Photo  149  Resist  ' 150  •k 05 P  152  Poly  Milk  07  Motal  Motal  Poly  M«t«l  Mask 08 Bond Pada  Poly  Matal  155  APPENDIX The  CDS  D  Layout Language from "CMOS D e s i g n S y s t e m 1982" M i c r o t e l P a c i f i c Research L t d . by Warren Snyder  156  CDS Layout  Language  A c e l l i n CDS i s d e f i n e d v i a s t a t e m e n t s i n the CDS l a y o u t language as opposed t o b e i n g c r e a t e d v i a a g r a p h i c s e d i t o r . T h i s a l l o w s a d e s i g n e r to p a r a m e t e r i z e h i s d e s i g n s , such as d y n a m i c a l l y v a r i a b l e c e l l s i z e s to s u i t v a r y i n g load c o n d i t i o n s . I t a l s o a l l o w s f o r easy c r e a t i o n of s t r u c t u r e s by the system i t s e l f , g i v e n j u s t a few s i m p l e v a l u e s . The best example of t h i s i n a u t o m a t i c s y n t h e s i s of P L A ' s .ROMS, and c o n t r o l u n i t s f o r m i c r o p r o c e s s o r s . The CDS system c u r r e n t l y has an a u t o m a t i c PLA g e n e r a t o r from t r u t h t a b l e s (see Appendix 2 ) . Statements a r e e i t h e r SYSTEM commands such as , FOR,NEXT,END,and a s s i g n m e n t s , XOR l a y o u t p r i m i t i v e s such as W i r e , P o l y g o n , D e f c . A l l t e x t i s e n t e r e d i n lowercase and i f the keyword i s a system command i t w i l l be a l l c a p i t a l i z e d (by the EDITor) e l s e o n l y the f i r s t c h a r a c t e r w i l l b e . Only one statement per l i n e i s a l l o w e d . example Defc("test") X1=1G Layer(Active) Polyaon(O.O) Xty(Xl.iO) Xy(0.10) Endc END  ! g i v e s name to c e i l [assignment to a v a r i a b l e [primitive specifying layering. I p o l y a o n w i t h s t a r t i n g p o i n t at 0 , 0 ."continues t o p o i n t s ( X I . 0 ) ( X 1 , 1 0 ) { c o n t i n u e s to p o i n t ( 0 , 1 0 ) =>box I c l o s e s d e f i n t i o n of c e l l ! l a s t l i n e of every f i l e  The example shows t h a t p r i m i t i v e s such as Polygon (and Wire) a r e u s u a l l y c o n t i n u e d on a new l i n e w i t h c o n t i n u a t i o n p r i m i t i v e s ( X t y ) . One can c o n t i n u e a p o l y g o n (or w i r e ) i n d e f i n i t e l y u n t i l the next p r i m i t i v e i s s t a t e d . A complete d e s c r i p t i o n of a l l commands i s g i v e n i n Appendix 1. The l i s t i n g s at t h i s m a n u a l ' s end b e s t i l l u s t r a t e the n a t u r e of the CDS l a y o u t l a n g u a g e . A l l c o o r d i n a t e s g i v e n as arguments to p r i m i t i v e commands a r e t r a n s l a t e d by the system r e l a t i v e to an o r i g i n d e t e r m i n e d by the two v a r i a b l e s X b a s e . Y b a s e . The a c t u a l c o o r d i n a t e i s d e t e r m i n e d by a d d i n g Xbase t o every x v a l u e and Ybase t o e v e r y y ' v a l u e . T h i s a l l o w s s e t t i n g up l o c a l o r i g i n s w i t h i n c e l l s . These v a r i a b l e s a r e r e s e t t o 0 by every Defc p r i m i t i v e .  157  Cell  9  Placement  To u s e a c e l l t h a t h a s b e e n p r e v i o u s l y d e f i n e d o n e u s e s the ' P l a c e " c o m m a n d . T h e c e l l w h o s e name i s g i v e n a s a r g u m e n t to ' P l a c e ' c a n b e o p t i o n a l l y f i r s t m i r r o r e d OR r o t a t e d a b o u t its axes then t r a n s l a t e d to a g i v e n l o c a t i o n w i t h i n the c u r r e n t d e f i n i t i o n . R o t a t i o n s c u r r e n t l y a r e l i m i t e d to 0 , 9 0 , 1 8 0 . XOR 270 d e g r e e s a b o u t t h e o r i g i n ( 0 , 0 ) . M i r r o r i n g i s a b o u t the y-axis ' m x ' (x v a l u e s a r e n e g a t e d ) XOR about t h e - x - a x i s 'my' (y va1ues negated). The i n t e r f a c e b e t w e e n c e l l s c a n be i m p l i c i t i n c a s e s where two c e l l s a r e i n t e n d e d t o b u t a g a i n s t e a c h o t h e r o r e x p l i c i t v i a ' N o d e s ' . A 'Node' i s a p o i n t d e f i n e d w i t h i n a c e l l which o t h e r c e l l s c a n i n t e r c o n n e c t t o , a n d a r e l a b e l e d by the d e s i g n e r w i t h names ( n e e d n o t b e u n i q u e o u t s i d e o f t h e cell). T o i n t e r c o n n e c t a n y two n o d e s o n e u s e s t h e ' L o c n ' command to o b t a i n the c u r r e n t c o o r d i n a t e s of the d e s i r e d nodes and v i a a ' W i r e ' command r o u t e a c o n d u c t o r b e t w e e n t h e m . T h e l o c a t i o n o f a n o d e i s o b t a i n e d f r o m i t s name a n d o w n e r c e l l , f r e e i n g the d e s i g n e r from remembering c o o r d i n a t e s . Three p r i m i t i v e contact c e l l s e x i s t for s p e c i f y i n g metal to active, metal to p o l y , or metal to p o l y to a c t i v e c o n t a c t s (BC butting contact) Jma.mp. be r e s p e c t i v e l y . T h e i r use i s o p t i o n a l b u t c a n s i m p l i f y most d e s i g n s (remember to c o m p i l e " L i b " i f you w i s h to use t h e m ) . The o r i e n t a t i o n o f the p o l y - a c t i v e i n a BC i s s p e c i f i e d v i a f o u r d i r e c t i o n s ; b e = E a s t , b n = N o r t h , bw=West, bs=South. The d i r e c t i o n i s a l o n g a v e c t o r from a c t i v e to p o l y .  158  APPENDIX 1  CDS PRIMITVES x i . y i s p e c i f y arguments t o p r i m i t i v e s and may be e x p r e s s i o n s . Arguments w i t h i n ( ) denote o p t i o n a l coordinates p a i r s . be,bn,bw,bs =>be(x1,y1. ( x 2 , y 2 , x 3 , y 3 , x 4 . y 4 , x 5 , yE», x S . yG)) - B u t t i n g c o n t a c t s formed by Ma-Mp c o n t a c t p a i r s . O r i g i n s a t c e n t e r of Ma c o n t a c t . E a s t , N o r t h , W e s t , S o u t h l o c a t i o n s f o r Mp. box  bbox  cut  >box(xl.y1,x2,y2) R e c t a n g l e w i t h lower l e f t a t x 1 , y 1 and upper r i g h t a t x 2 , y 2 (on c u r r e n t l a y e r ) . >bbox("test",x1.yt,x2.y2) I n t e r f a c e w i t h d a t a - b a s e t o f i n d the bounding box of a p r e v i o u s l y c o m p i l e d c e l l . R e t u r n s c o o r d i n a t e s of c e l l ' s r e c t a n g u l a r o u t l i n e . x 1 , y t . x 2 , y 2 must be v a r i a b l e names. >cut(x1,yJ.(x2.y2.x3,y3.x4.y4.x5,y5.x6,y6)) S e t s c u r r e n t l a y e r t o ' C u t ' i f not a l r e a d y and p l a c e s 2x2 s q u a r e s c e n t e r e d a t the given coordinates.  defc = >defc<"test") S t a r t s a new c e l l d e f i n i t i o n and names t h a t c e l l . R e s e t s xbase and ybase to 0 . The c u r r e n t l a y e r i s u n d e f i n e d . def n  =>defn("in1",x1,y1) D e f i n e s a node w i t h i n a c e l l . The name and p o i n t a r e p a i r e d t o g e t h e r .  dx = >dx(x1 ) - C o n t i n u a t i o n path increment. (x,y)<=(x,y)+(dx.O)  159  11  dy =>dy(y1) - Continuation path increment. (x,y)<=(x.y)+(0.dy) dxy  =>dxy(x1.y1) - Continuation path increment, (x.y)<=(x,y)+(dx.dy) end  - Very last line of a design f i l e . endc  - Terminates a cell definition. layer = > 1 ayer(Act ive) - Sets the current layer, which remains valid t i l l modified. locn ->locn(eel 1*,"node".x.y) - Returns the coordinates of a node in the cell, given by the cell*, as i t appears after a l l transformations. The cell* is set via the Place command which defined the cells location. =>ma(x1,y1,{x2.y2.x3,y3,x4,y4,xS,y5.xS.y6)) - Places metal-active contacts centered at the given coordinates. in f-'  =>mp(x1,y1,{x2.y2.x3.y3,x4,y4.x5.y5,x6.yb}) - Places metal-poly contacts centered at the given coordinates.  pla =>pla("bitfile",x,y) - see appendix 3  160  12  place  = >place( " e e l 1 ( . o p t i o n s ) " . x . y . (ce 11 *») ) - C e l l s are placed with t h e i r o r i g i n s at x.y with o p t i o n a l t r a n s f o r m a t i o n s ; mx XOR my f o r m i r r o r i n c about y a x i s . x a x i s r e s p e c t i v e l y ; r 9 0 . r 1 8 0 . XOR r270 f o r r o t a t i o n s about t h e i r o r i g i n s . An o p t i o n a l v a r i a b l e can be used to r e c o r d the c e l l s p l a c e number f o r use i n l o c n commands, eg. p l a c e ( " t e s t . m x . r 9 0 " , 1 0 . 1 0 , t e s t )  polygon =>polygon(x1,y1,(x2.y2,x3.y3,x4.y4.x5,y5.x6,y6>) - S t a r t s a new p o l y g o n a t x 1 . y 1 on c u r r e n t l a y e r . O p t i o n a l v e r t i c e s can be s p e c i f i e d i n same command or p a t h c o n t i n u a t i o n commands can f o l l o w . The p o l y g o n a u t o m a t i c a l l y c l o s e s up on i t s e l f so the f i r s t v e r t e x need not be repeated. wire  ->wire((width),x1.y1,(x2.y2,x3,y3.x4.y4,x5,y5,x6,yG)) S t a r t s a w i r e of d e f a u l t w i d t h 2 a t x 1 , y 1 . The p a t h of a w i r e i s a l o n g i t s c e n t e r l i n e and s t a r t s and ends f l u s h w i t h i t s end p o i n t s . Any p a t h c o n t i n u a t i o n command can be u s e d . >x(x1 ) Continues a path.  x tv  xy  ix.y)<=(x1,y)  >>:ty(x1 . { y l . x 2 . y 2 , x 3 , y 3 . x 4 , y 4 , x 5 . y 5 , x 6 , y6) ) C o n t i n u e s a p a t h w i t h o r t h o g i n a l bends. P e r f o r m s s u c c e s s i v e x ( x i ) y(yi+1> commands P r o d u c e s a j o g i n x , then y , then x e t c . . >xy(x1,y1,{x2,y2.x3.y3,x4,y4,x5,y5,x6.y6>) Continues a path along given c o o r d i n a t e s , (x.y)< = (xi , y i ) = y(y1 ) - Continues a path.  (x.yX-(x.yl)  161  APPENDIX 2  13  AUTOMATIC PLA GENERATION A Programmable L o g i c A r r a y may be s y n t h e s i z e d from a t r u t h t a b l e v i a the ' P l a ' command. To do so one must f i r s t c r e a t e a f i l e of the t r u t h t a b l e . C r e a t e a d e s i g n f i l e under some name ( e g . " t r u t h t a b l e " ) i n t o which the terms of the b o o l e a n l o g i c can be p u t . To see how t h i s i s done f o l l o w through w i t h t h i s example. !.3,2.5 !001 10 !101 01 ! 110 11 !x 11 00 ! 111 01  ! ! ! ! ! !  * variables,results,minterms term 1 term 2 term 3 term 4 term 5  Each l i n e must b e g i n w i t h a ' ! ' f o l l o w e d by d a t a . The f i r s l i n e s p e c i f i e s the s i z e of the PLA. Each s u c c e s s i v e l i n e r e p r e s e n t s the terms of the t r u t h t a b l e . Input c o n d i t i o n s f o l l o w e d by o u t p u t s . An ' x ' s p e c i f i e s t h a t the i n p u t v a r i a b l e i s i g n o r e d . N o t e ! an ' x ' can not o c c u r i n an output column. There must a s i n g l e space between the i n p u t and output s e c t i o n w i t h comments a l l o w e d anywhere a f t e r the o u t p u t s . Once a f i l e has been c r e a t e d i t can be used as i n . DefcCplal")  l o t h e r s t a t e m e n t s can be !used f o r custom a d d i t i o n s .  Pla("pla1table".x,y) Endc The p l a g e n e r a t o r i s a system macro t h a t expands a t r u t h t a b l e i n t o l a y o u t commands w i t h i n a c e l l d e f i n i t i o n . For each i n p u t ' i ' t h e r e w i l l be d e f i n e d an a s s o c i a t e d ' n o d e ' " i n " s u b ' i ' ( " i n 1 " , " i n 2 " e t c . ) . L i k e w i s e f o r a l l output! ("out 1 " , " o u t 2 " , e t c . ) . T h i s a l l o w s easy i n t e r f a c i n g to P L A s .  162  APPENDIX Top  Level  Cell  E  Source  163  Listings  Filename:  pidac  Desianer:  R. M i e l c a r s k i  Date: 3-May-83  Comments: 3 of S n y d e r ' s DACs c o n n e c t e d i n p a r a l l e l w i t h 3 of S c h m i i n g s D A C s to the 12 b i t p i p e l i n e reg C e l l name: p l d a c -function  . see above comment  - t e l l s called  .  -nodes defined  . lettp  Pipein.dcel1.dacbuf. pvs  (0.2)*lett pipel i n e rea c l l . r i g h t p (1008,2) - r i g h t p i p e l i n e rea c l l .  leftp/  (0.82)  . n a h t p / (1008,82) . dacvddl ( - 3 1 . 7 , 9 7 ) = l e f t end of vdd bus . dacvddr ( 1 0 4 9 . 8 . 9 7 ) = r i g h t end of vdd bus ; dacvssl (-31.7,494) = l e f t end of v s s bus . dacvssr (1049.8.494) r i a n t end of v s s bus . v r e f l l 1-31.7,508) = l e f t end of S n y d e r ' s v o l t a a e r e f e r e n c e bus . v r e f l r (1049.8,508) = r i g h t end of S n y d e r ' s v o l t a a e r e f e r n c e bus . vref21 (-31.7,522) l e f t end of S c h m i i n g ' s v o l t a g e r e f e r e n c e bus . vref2r (1043.8,522) = r i g h t end of S c h m i i n g s v o l t a g e r e f e r e n c e bus . c l k l (-31.7.531) = l e f t end of c l o c k bus . c l k r (1049.8.531) r i g h t end of c l o c k bus . o u t l . . . out6 = o u t p u t s - b o u n d i n g box Revision History: 570 580 590 600  pipeline  register  .(-36.1.-1.4,1049.8.534) (date/name/mod)  and the 6 dacs 164  610 620 6"-*0 6bU 660 670 680 630 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 860 870 880 i  C  910 S20 930 940 950 960 970 980 990 !000 1010 1020 1030 1040 1050 1060 1070 1080 1090 1100 1110 1120 1130 1140 I 0 1 io0 1170 1180 1190 1200  |  DIM DIM DIM DIM DIM DIM DIM DIM DIM DIM DIM DIM DIM DIM  Ploutx(12) Plouty(l2) vrefx(6) Vre*y(6) 0utx(6) Outy(6) Dacvssx(6) Dacvssy(6) Dacvss2x(3) ! S c h m i i n g ' s dac r e q u i r e s Dacvss2y(3' ! a second v s s Clkx(3) ! S n y d e r ' s dac r e q u i r e s Clky(3> ! a clock Dacvddx(6) Dacvddy(6)  •*+•  Defc("pldac") j P l a c e t " p i p e I n " , 0 , 0 . P i p e In) i FOR 1=1 TO 12 L o c n ( P i p e l n . " p l o u t " a V A L S ( I ) . P l o u t x ( I ) . P l o u t y (I) NEXT I i Locn( P i p e I n . " let" t p " .Let tpx , L e f tpy ) Defn( "let" tp",Let" t p x . L e f tpy) j Locn(Pipeln,"riohtp".Riahtpx.Rightpy) Def n l " r i a h t p " . R i a h t p x . R i g h t p y ) i LocnJPipein."lettp/".X.Y) Defn( iettp/",X.Y) » Locn(Pipeln."riahtp/".X,Y) Defnt"rightp/",X,Y) , ,  Get bounding box i n f o so we can f i g u r e out where t o p l a c e the dacs i  Bbox("dceli".Dcellx1.Dcellyl.Dcellx2.Dcelly2) Bbox("dacbuf".Dacbufx1.Dacbufyl,Dacbufx2.Dacbufy2)  i  the bottom of the dacs must not go below Y0  Y0=Plouty(1)+6+12*4+(3*6)+4 ! We a l l o w 10 lambda space between dacs P i tch=(Dee11x2-Dce11x1)•<Dacbufx2-Dacbuf x1) +12*10) F i n d t h e l e f t edge X0 s u c h t h a t the 6 dacs are n i c e l y centered X0=(Rightpx+Leftpx)/2-(Pitch*3)/2+5 165  1210 1220  Xr=X0+3*Pitch !  1. ] 1250 1260 1270 1280 1290 1300 1310 1320 1330 1340 13S0 1360 1370 1380 1390 1400 1410  ! !vdd bus ! LayeHMetal) Wire(12,X0,Plouty(1>+12> X(Xr) D e f n ( " d a c v d d 1 " . X O , P l o u t y ( 1 ) + 12) Defn("dacvddr".Xr,Plouty(1)+12) ! J connect p i p e l i n e r e a i s t e r to vdd bus ! Plpitch-168 ! FOR 1=0 TO 5 Wire(4.Plpitch/2+I*Plpitch.Plouty<1)-3) Y(Plouty(1)+12) NEXT I !  1430 1440 1450 1460 1470 1480 1 1 1^ J 1510  ! ! p l a c e the d a c ' s above the p i p e l i n e ! r e g i s t e r and connect ! DIM D c e l K 3 ) . D a c b u f ( 3 ) ! FOR 1=1 TO 3  1530 1540 1550 1560 1570 I580 1590 1600 1610 1620 1630 1640 1650 1660 1670 1680 1690 1 700 1710 1720 1730 1 0 T j 1760 1770 1780 1790 1800 7/,  ! r i a h t edae  !  ! p l a c e S n y d e r ' s dac  "  Y=Y0-Dcelly1 X=X0+(I-1)*Pitch-Dcelix1 ! Place("dcell",X.Y.DcellCl)) ! ! get a l l the dac c o o r d i n a t e s f o r ! f u t u r e use ! Locn(Dcell(I),"vref",VrefxC1*2-1),Vrefy(1*2-1)) Locn(Dcell(I),"vss",Dacvssx(I*2-1),Dacvssy(1*2-1)) Locn (Dcel 1 ( 1 ) , " e l k " , C l k x ( I ) , C l k y ( I ) ) Locn(DcelKI),"vdd".Dacvddx(1*2-1>,Dacvddy(1*2-1)) Locn(Dcell(I),"out",0utx(I*2-1).0uty(I*2-1)) ! ! p l a c e S c h m i i n q ' s dac ! Y-YO-Dacbufyl X = X + ( D c e l l x 2 - D c e l l x ' i ) + 10-Dacbufx1 ! Place("dacbuf".X,Y.Dacbuf(I)) ! ! get a l l the dac c o o r d i n a t e s f o r ! f u t u r e use ! Locn(Dacbuf(I),"vref".Vrefx(1*2),vrefy(1*2)) Locn(Dacbuf(I)."vss1",Dacvssx(1*2),Dacvssy(1*2)) Locn(Dacbuf(I),"vdd",Dacvddx(1*2),Dacvddy(1*2)) L o c n ( D a c b u f ( I ) , " v o u t \ 0 u166 tx (1*2),0uty(I*2))  1810 1820 l "" 0  L o c M D a c b u t ( I ) , " v s s 2 " ,Dacvss2x < I) ,Dacvss2y I D )  :,  is^n 1860 1870 1880 18S0 1900 1910 1920 1930 1 9 AO !950 1 960 1970 1 980 1 990 2000 201 0 2020 2030 2040 2050 2060 207 0 2080 f 0 2 . uO 21 10 21 20 2130 2140 2150 2160 2170 2180 2190 2200 2210 2220 2230 2240 2250 2260 2270 2280 2290 2300 2310 2320 2330  .  6  2360 2370 2380 2390 2400  connect  the data  lines  FOR J=1 TO 4 K = ( I - 1 )*4 + J Mp(Pioutx(K).Plouty(K)+2) h - P l o u t y ( K ) + 2 2 + ( J - 1 >*6 Mp(Ploutx(K).H)  i  Layer(Poly!) r e ( P l o u t x ( K ) . P l o u t y (t<) +2 ) Y(H) i L o c n ( D e e 1 1 ( I ) , " in"&vALS< J-1 ) .X,Y) Layer(Meta1) W i r e ' P l o u t x ' K ) .H) X(K> Y( Y ) i  l l o c n ( D a c b u t ( I ) . " i n " A v A L S ( J ) .X. Y) Layer(Metal) Wire(Ploutx(K),H)  X(Xi  Mp(X,H) Layer(Polv1) Wire(X.H) Y( V ) i  NEXT J i ! c o n n e c t t h e vdd bus t o t h e dacs i Layer(Meta1) W i r e ( 8 , D a c v d d x ( I * 2 - 1 ) . Dacvddy ( 1 * 2 - 1 ) ) Y(Plouty(1)+l2) Wire(8.Dacvddx(I*2).Dacvddy<1*2)> Y(Piouty(1)+12) NEXT I  b u s s e s above t h e dac I F 0 u t y ( 2 ) > 0 u t y ( 1 ) THEN Top=0uty(2) ELSE Top=0uty(1) END I F  VS<  Layer(Metal) Wire(12.X0.Top+12) X(0utx(1)-3) Wire(12.0utx(6)+3,Top+12)  167  2410 2420 2 ' ~1 2 J 2450 2460 2470 2480 2490 2600 2510 2520 2530 2540 2550 2560 2570 2580 2590 2600 2610 2620 2630 2640 2650 2660 2670 2680 2 ) 27u0 2710 2720 2730 2740 2750 2760 2770 2780 2790 2800 2810 2820 2830 2840 2850 2860 2870 2880 2890 2900 2910 2920 2930 2 '1 2'. J 2960 2970 2980 2990 3000 r  X(Xr) Def n ( " d a c v s s 1 " . X O . T o p + 1 2 ) Defn("dacvssr".Xr,Top+12) !  FOR 1=1 TO 5 Wire(12,0utx(I)+3.Top+12) X(Outx(I+1)-3) NEXT I ! Layer(Active) FOR 1=1 TO 6 Wire(12,0utx(I)-7.Top+12) X(0utx(I)+7) Ma(0utx(I)-5,Top+8) Ma(0utx(I)-5.Top+12) Ma(0utx(I)-5.Top+16) Ma(0utx(I)+5,Top+8) Ma(Outx(I)+5.Top+12) Ma(0utx(I)+5.Top+16) NEXT I ! * + *•*++*•**•*•**#*******•**•**•*•*** ! ! v r e f ! and v r e f 2 ! Layer(Metal) Wire(12,X0,Top+26) -X(Outx(1)-3) Wire(12.0utx(6)+3,Top+26) X(Xr) Defn("vref11".X0.TOP+26) Defn("vref1r",Xr,Top+26) ! Layer(Metal) Ware(12,X0,Top+40) X(0utx(1)-3) Wire(12,0utx(6)+3.Top+40) X(Xr) Defn("vref21X0,TOP+40) Defn("vref2r".Xr,Top+40) ! FOR 1=1 TO 5 Wire(12.0utx(I)+3,Top+26) X(Outx(I+1)-3) ! Uire(12.Outx(I)+3,Top+40) X(Outx(I+1)-3) NEXT I ! Layer(Active) FOR 1=1 TO 6 Wire(12,0utx(I)-7,Top+26) X(Outx(I)+7) Ma(0utx(I)-5,Top+22) Ma(0utx(I)-5,Top+26) Ma(0utx(I)-5,Top+30) Ma(0utx(I)+5,Top+22) Ma(0utx(I)+5,Top+26) Ma(0utx(I)+5,Top+30) ! 168 1  3010 3020  1 o  3050 3060 3070 3080 3090 3100 3110 3120 3130 3140 31 E>0 316G 3170 3130 3190 3200 3210 3220 3230 3240 3250 3260 3270 3?80 ' 0 3ouO  3310 3320 3330 3340 3350 3360 3370 3380 3390 3400 3410 3420 3430 3440 3450 3460 3470 3430 3490 3500 3510 3520 3530 ? 40 R /  • ,0 3560 3570 3530 3590 3600  Wire(12,0utx(I)-7,Top+40) XlOutx(I)+7) Ma(Outx(I)-5,TOP+36) Ma(0utxU)-5,Top+40) Ma(0utx(I)-5,Top+44) Ma(Outx(I)+5,Top+36) Ma(0utx(I)+5.Top+40) Ma(0utx<I)+5,Top+44) NEXT I  elk Layer(Poly1 ) Wire(2.X0,Top+49> X(Xr ) D e f n ( " e l k 1".X0,Top+49) De*n("clkr".Xr,Top+49)  connect the dacs to the busses FOR 1=1 TO 3 ! e l k used by S n y d e r ' s dac L a y e r ( P o l y 1) Wire(2,Clkx(I),Clky(I)) Y(Top+49) ! v s s 2 used by S c h m i i n g ' s dac L a y e r ( M e t a 1) Wire(8,Dacvss2x(I).Dacvss2y(I)) Y(Top+12) vrefl  to S n y d e r ' s dac  Layer(Act ive) W i r e < 4 . V r e f x f 1 * 2 - 1 > . V r e f y ( 1 * 2 - 1 )) Y(Top+26) Ma(Vrefxt1*2-1),Top+22) Ma<vrefx<1*2-1),Top+26) Ma(Vretx(1*2-1),Top+30) I Layer(Nplus) Box(Vrefx(I*2-1)-3.5,Vrefy(1*2-1)-3.5.Vrefx(1*2-1)+3.5.Top+30+ ! v r e f 2 to S c h m i i n g ' s dac Layer(Active) Wire(4,Vrefx(I*2),Vrefy(I*2)) Y(Top+40) Ma(Vrefx(I*2),Top+36) Ma(vrefx(I*2),Top+40) Ma(Vrefx(I*2),Top+44) Li a y e r ( N p l u s ) 169  3610 3620 3^0 c J 36b0 3660 3670 3680 3690 3700 3710 3720 3730 3740 3750 3760 3770 3780 3790 3800 3810 3820 3830 3840 3850 3860 3870 3880 3' 1 3.-d 3910 3920 3930 3940 3950 3960 3970 3980 3990 4000 4010 4020 4030 4040 4050 4060 4070 4080 4090 4100 4110 4120 4130 41*0 t ) 4lb0 4170 4180 4190 4200  Box(vrefx(I*2)-3.S,vrefy(I*2)-3.5.vrefx(I*2)+3.5,Top+44+3.5) NEXT I ! FOR 1=1 TO 6 ! ! vss ! LayeHMetal) Wire(8,Dacvssx(I).Dacvssy(I) ) Y(Top+12) ! ! output ! Layer(Metal) Wire(2,0utx(I) .Outyd) ) Y(Top+52) Def n ("out "AVALS <.1). Outx < I ) . Top+52.) ! Layer(Nplus) Box(0utx(I)-5-3.5,Top+8-3.5,0utx(I)+5+3.5.Top+44+3.5) NEXT I ! ! ***+******************************•**** ! i Extend the p u e l l r e g i o n ! around the a c t i v e bus jumpers ! FOR 1=1 TO 3 !  '  ! P l a c e the p u e l l around S n y d e r ' s dac ! and t i e to v s s ! Layer(Puell) Box(vrefx(I*2-1)-4.vrefy(1*2-1)-4,Outx(1*2-1)+5+4.Top+44+4) ! X=(Outx(1*2-1)-5+vrefx(1*2-1))/2 Y0=0uty(1*2-1)+10 ! Layer(Metal) Wire(4,X,Top+12) Y(Y0) ! Cnt = INT((Top+12-Y0)/10) FOR J=1 TO Cnt Place("pvs",X,Y0+2+(J-1)*10) NEXT J ! ! P l a c e the p u e l l around S c h m i i n g ' s ! dac and t i e to v s s ! Layer(Puell) Box(Outx(1*2)-5-4,Vrefy(1*2)-4,Vrefx(1*2)+4,Top+44+4) ! X=(Outx(1*2)+5+Vrefx(1*2))/2 Place("pvs".X,Top+12) ! NEXT I !  Endc END  170  20  !  2°  ! F i l e n a m e : mempldac  50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280  ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! i ! ! ! ! ! ! ! ! ! ! !  3uU  310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 470 480 490 500 510 520 530 F '' ^ L 560 570 580 590 600  D e s i g n e r : R. M i e l c a r s k i  Date: 4-May-83  Comments: The p i p e l i n e and DACs a r e c o n n e c t e d to the memory a r r a y . C e l l name: mempldac -function  . see above comment  -cells called  .  pldac,array  -nodes defined  .  dacvddl,dacvddr, dacvssl,dacvssr. vref11,vref1r. vref21,vref2r. clki.clkr, leftp.riohtp. leftp/,rightp/. vss1 . . . vss7 dpi . . . dp12 dv1 . . . dv12 r1 . . . r6 r/1 . . . r/6 vddl . . . vdd6 u1 . . . LIB u/1 . . . ui/6 yp1 . . . yp16 yp/1 . . . yp/16 yv1 . . . yv16 yv/1 . . . yv/16 o m i t t e d because of c o m p i l e r overflow.  - b o u n d i n g box . Revision History:  . (-36.1,0,1049.8.2070) (date/name/mod)  i  ! memory, p i p e l i n e , and dac ! Defc("mempldac") ! Place*"pldac",0,1536,Pldac) Place( array,r270".0,1536,Mem) ! ! C a r r y DAC nodes through to the ! next l e v e l ! DIM 0utx<6^ DIM 0 u t y ( 6 ) ! , ,  1 7 2  610 620 6 > b 660 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 860 870 880 f b^o 910 920 930 940 950 960 970 980 990 1000 1010 1020 1030 1040 1050 1060 1070 1080 1090 1100 1110 1120 1130 1 40 ( 0 1160 1170 1180 1190 1200 or  !  1  FOR 1=1 TO 6 Locn(Pldac."out"AVALS(I),0utx(I).Outy(I)) Defn("out"6VAL$(I),0utx(I),0uty(I) ) NEXT I ! Locn(Pldac,"dacvddl".Dacvddlx.Dacvddly) Defn("dacvddl",Dacvddlx.Dacvddly) ! Locn(Pldac."dacvddr",Dacvddrx,Dacvddry) Defn("dacvddr",Dacvddrx.Dacvddry) ! Locn(Pldac,"dacvssl".Dacvsslx,Dacvssly) Def n ( ' d a c v s s l " , D a c v s s l x . D a c v s s l y ) ! Locn(Pldac,"dacvssr",Dacvssrx,Dacvssry) Def n ( " d a c v s s r " , D a c v s s r x , D a c v s s r y ) ! Locn(Pldac."vrefl1".Vrefllx,Vreflly) Defn("vrefl1",Vrefllx.Vref1ly) ! Locn(Pldac,"vreflr",Vreflrx.Vreflry) Defn("vreflr".Vreflrx.Vreflry) ! Locn(Pldac."vref21".Vref2ix,Vref21y) Defnl"vref21",Vref21x.Vref21y) ! Locn(Pldac,"vref2r".Vref2rx,Vref2ry) Defn("vref2r",Vref2rx,Vref2ry) ! Locn(Pldac,"clkr .Clklx.Clkly) Defn("clkl",Clkl>:.Clkly) ! Locn(Pldac,"elkr",Clkrx,Cikry) Defn("clkr",Clkrx,Clkry) ! ! C a r r y the p i p e l i n e r e g i s t e r nodes ! through to the next l e v e l ! Locn(Pldac,"leftp".Leftpx,Leftpy) Defn("leftp",Leftpx,Leftpy) ! Locn(Pldac."riahtp".Riahtpx,Rightpy) Defn("riahtp",Riahtpx,Rightpy) ! Locn(Pldac."leftp/".Leftpnx.Leftpny) Defn("leftp/",Leftpnx,Leftpny) ! Locn(Pldac,"rightp/",Rightpnx,Rightpny) Defn("rightp/",Riahtpnx.Riahtpny) ! ! C a r r y memory a r r a y nodes through ! to the next l e v e l ! DIM V s s x ( 7 ) DIM V s s y ( 7 ) DIM D p x M 2 ) DIM Dpy(12) DIM Dvx(12) 173 DIM Dvy(12) DIM Rx(6) ,  1210 1220 1230 • 0 UDO 1260 1270 1280 1290 1300 1310 1320 1330 1340 1350 1360 1370 1380 1390 MOO 1410 1420 1430 1440 1450 1460 1470 1480 '90 I  ,  JO  1510 1520 1530 1540 1550 1560 1570 1580 1590 1600 1610 1620 1630 1640 1650 1660 1670 1680 1690 1700 1710 1720 1730 1740 ( ".0 I I 60 1770 1780 1790 1800  DIM Ry(6) DIM Rnx(6) DIM Rny(6) DIM Vddx(6> DIM Vddy(6) DIM Wx(6) DIM Wy(6) DIM Wnx(6) DIM Wny(6) DIM Ypx(16) DIM Ypy(16) DIM Ypnx(16) DIM Ypny(16) DIM Yvx(16) DIM Yvy(16) DIM Y v n x ( l 6 ) DIM Yvny(16) ! FOR 1=1 TO 7 Locn(Mem,"vss"AVALS(I) . V s s x ( I ) , V s s y ( I ) ) Defn( " v s s " AVALS (I) , V s s x d ) . 0 ) NEXT I ! FOR 1=1 TO 12 Locn(Mem."dp"AVALS(I),Dpx(I),Dpy(I)) Defn("dp"AVAL$(D.Dpx(I),0) Locn(Mem."dv"AVAL$(I),Dvx(I).Dvy(I)) Defn("dv"AVALS(I),Dvx(I),0) NEXT I !  FOR 1=1 TO 6 Locn(Mem,"r"AVALS<I>,Rx<I),Ry(I)) D e f n r r " A V A L S ( I ) , R x ( I > ,0) Locn(Menu " r / " A V A L S ( I ) , R n x ( I ) . R n y ( I ) ) Defn( " r / " A V A L S ( D , R n x ( D , 0 ) Locn(Mem."vdd"AVALS(I).Vddx(I).Vddy(I)) Defn("vdd"AVALS(I),Vddx(I).0) Locn(Mem,"id"AVALS(I). Wx ( I ) , Wy ( I ) ) Defn("u"AVALS(I),Wx(I),0) Locn(Mem,"w/"AVALS(I),Wnx(I),Wny(I)) De f n ( " w / " A V A L S ( I ) , W n x ( I ) , 0 ) NEXT I ! Xmax=Vssx(7) ! FOR 1=1 TO 16 ! Locn(Mem,"yp"AVAL$(I),Ypx(I),Ypy(I)) Defn("yp"AVALS(17-1),0.Ypy(I)) ! Locn(Mem,"yp/"AVALS(I),Ypnx(I),Ypny(I)) Defn("yp/"AVAL$(17-1),0.Ypny(I)) ! Locn(Mem,"yv"AVAL$(I),Yvx(I),Yvy(I)) Defn("yv"AVAL$(17-I),Xmax,Yvy(D) ! Locn(Mem,"yv/"AVALS(I),Yvnx <I),Yvny(I)) ! yv/ cannot be def noded because too ! many nodes bombs the c o m p i l e r . ! 1 7 4  1810 1820 1830 1 ? 1oo0 1860 1870 1880 1890 1900 1910 1920 1930 1940 1950 1960 1970 1980 1990 2000 2010 2020 2030 2040 2050 2060 2070 2080 2 °0 2 0 2110 2120 2130 2140 2150 2160 2170 2180 2190 2200 2210 2220 2230 2240 2250 2260 2270 2280 2290 2300 2310 2320 2330 2340 7 0 LoO 2370 2380 2390 2400 (  r  NEXT I Endc ! ! PRINT "*******•*•*•*•***•*'' Bbox("mempldac",X1.Y1.X2,Y2) PRINT "mempldac bounding b o x = " , X I , Y 1 . X 2 . Y 2 PRINT PRINT " d a c v d d l x , y = " . D a c v d d l x , D a c v d d l y PRINT "dacvddr x ,y = " , D a c v d d r x , D a c v d d r y PRINT "*•****•*****#*+*" PRINT " d a c v s s l x , y = " . D a c v s s l x , D a c v s s l y PRINT " d a c v s s r x , y = " , D a c v s s r x , D a c v s s r y PRINT •***••#*****•***••*" PRINT "out x=" PRINT 0 u t x ( O PRINT " y=" PRINT Outy(*> PRINT ''**-*-*****•**•***•*•*" PRINT " v r e f l 1 x , y = " , v r e f 1 l x . V r e f 1 l y PRINT " v r e f l r x . y = " , V r e f 1 r x , V r e f 1 r y PRINT " v r e f 2 1 x , y = " . V r e f 2 1 x , V r e f 2 1 y PRINT " v r e f 2 r x . y = " , V r e f 2 r x , V r e f 2 r y PRINT PRINT " c l k l x , y = " . C l k l x , C l k l y PRINT " c l k r x . y = " , C l k r x , C l k r y PRINT "**•*•*********•*•**•*•+*" PRINT " l e f t p x , y = " , L e f t p x . L e f t p y PRINT "*****+*•****•***•*+•**" PRINT " l e f t p / x , y = " . L e f t p n x , L e f t p n y PRINT "***•**•*-•****+****-*-*" PRINT " r i g h t p x , y = " , R i g h t p x , R i g h t p y PRINT "*******•**•*********" PRINT " r i g h t p / x , y = " . R i g h t p n x , R i g h t p n y PRINT "***•*•**-**#*+*****•*•*" PRINT " v s s x=" PRINT Vssx(*) PRINT " y= " PRINT Vssy(*) PRINT * ' * ' PRINT "vdd x=" PRINT Vddx(*) PRINT " y=" PRINT Vddy(*) PRINT "a*-********-***-*-**-***'' PRINT "dp x=" PRINT Dpx(*) PRINT " y=" PRINT D y ( * ) PRINT *******************" PRINT "dv x=" PRINT Dvx(*) PRINT " y=" PRINT Dvy(*) PRINT "•*****•****•****+*****" PRINT "r x = " PRINT Rx(*) PRINT " y=" PRINT Ry(*) PRINT "****************-****" 175 P  u  2410 2420 2/-°0  i  J  2450 2460 2470 2480 2490 2500 2510 2520 2530 2540 2550 2560 2570 2580 2590 2600 2610 2620 2630 2640 2650 2660 2670 2680 2 0 2«u0 2710 2720 2730 2740  PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT PRINT END  "r/ x = " Rnx(*) =» Rny(*) y  "w x=" Wx(*) " y=" Wy(*> "w/ x = " Wnx(*> " y=" Wny(*) "yp :< = " Ypx(*)  "  v"  Ypy(*)  "•*•***-*•****•* •***-*+•**•*****"  "yp/ x = " Ypnx(*) y=" Ypny(*) "yv x=",Xmax " y=" Yvy(*)  "*+***-***-***********•****  "yv/  x«'\Xma>: y=" Yvny (*•)  176  mempldac has been c o m p i l e d ^--•oldac bounding box=  -36.1  dacvddl x . y = dacvddr x,y=  -31.7 1049.8  1633 1633  d a c v s s l x,y= dacvssr x,y=  -31.7 1049.8  2030 2030  0  1049.S  out x = 73.8  232.3  434.3  S92.8  794.8  953.3  2070  2070  2070  2070  2070  2070  v/refll vreflr vref2i vref2r  x.y= x,y= x.y= x.y*  c l k l x,y= c l k r x.y=  -31.7 1049.8 -31.7 1049.8  -31.7 1049.8  l e f t p x.y=  0  2070  2044 2044 2058 2058  2067 2067 1538  l e f t p / x,y=  0  1618  r i g h t p x.y=  1008  1538  r^htp/ x . y  1008  1618  x=  v S S  0  168  336  504  672  840  1008  1536  1536  1536  1536  1536  1536  1536  252  420  588  756  924  1536 lV 157 683 825 1536 * 1536 1536 1536 -*•*•**-*+*•*****-**-«•***-*-  1536 325 987 1536 1536  1536 179 851 1536 1536  1536 347  1536 493  661  515.  1536  1536  1536  1536  & ~ 678  162 834  330 1002  174 846  342  498  666  1536 1536  1536 1536  1536 1536  1536  1536  1536  241  431  577  767  913  1536  1536  1536  1536  1536  vdd x = 84 1536  d  d  X  1536 636  1  r  95~ 1536  177  510  1536  r /  x=  246  426  582  762  918  1536  1536  1536  1536  1536  258  414  594  750  930  1536  1536  1536  1536  1536  73  263  409  599  745  935  1536  1536  1536  1536  1536  1536  o  o o  o o  SO  36  '  ^78 1536  u/ x =  yp x =  n o  1493 725  c  o  o  n  1397 629  1301  533  1205 437  0 0  0 0  0 0  1508 740  644  1412  yp/ x =  y  o  x= y=  o o  u r 82 >  1109  9!7  34<  1013 245  149  5;  0 0  0  0  0  C  0  0  0 0  1316 548  1220 452  1124 356  1028 260  932 164  8?8 bb  1250 482  1154 386  1058 290  962 194  866 98  ,'70 2  1274 506  1178 410  1082 314  986 218  890 122  1008  1442 674  1346 578  yv/ x=  1008  1466 698  1370 602  178  2  794 L.  Oi-rVfc  o o + l  cVtd  i  r»oV-r f  179  Filename:  palette  Designer:  R. M i e l c a r s H G. Cheng  Date: 4-May-83  Comments: Top l e v e l c e l l t h a t p u l l s t o g e t h e r a l l components of the c o l o u r p a l e t t e and c o n n e c t s the I/O p a d s . C e l l name: p a l e t t e -function  . see above comments  -cells  called  . mempldac.bigxdcod, iopad.neuypgen. newyvgen,newctr1. inpad,logo.  -nodes  defined  .  -bounding Revision  box  History  none  . (-353.-389,1275,2170) (date/name/mod) * * * * * * *  HM***4*********-+#  C o l o u r p a i e t t e c h i p c o n t a i n i n g the d a c s , the p i p e l i n e r e g i s t e r , the memory a r r a y , the x and y d e c o d e r s , the c o n t r o l c i r c u i t r y , and the I/O p a d s .  Defc("palette")  P l a c e the d a c s , p i p e l i n e r e g i s t e r memory a r r a y .  and  Placet"mempidac",0.0.Mem) ! DAC nodes  5*0  (  bbu 570 580 590 600  DIM 0 u t x ( 6 ) DIM 0 u t y ( 6 ) DIM C t r l x l ( 8 ) , C t r l y 1 ( 8 ) DIM C t r l x 4 ( 8 ) , C t r l y 4 ( 8 ) i  FOR 1=1 TO 6 Locn(Mem,"out"&vAL$(D,0utx(I),0uty(I)) NEXT I !  180  610 620 630 6 6bu 660 670 680 630 700 710 720 730 740 760 760 770 780 790 800 310 820 830 840 360 860 870 880 P' " S\  910 920 930 940 960 960 970 980 990 1000 1010 1020 1030 1040 1050 1060 1070 1080 1090 1100 1110 1120 1130 1140 ( 0 1 IOO 1170 1180 1190 1200  Locn(Mem, " d a c v d d l " . D a c v d d l x . D a c v d d l y ) Locn(Mem,"dacvddr",Dacvddrx,Dacvddry) Locn(Mem,"dacvssl",Dacvsslx,Dacvssly) Locn ( M e m , " d a c v s s r " , D a c v s s r x , D a c v s s r y ) Locn(Mem,"vref11",Vref1lx,Vref1ly) Locn(Mem,"vref1r",Vref1rx,Vref1ry) Locn(Mem."vref21".Vref21x,Vref2ly) Locn(Mem,"vref2r",Vref2rx,Vref2ry) Locn(Mem."clkl",Clklx,Clkly) Locn(Mem."clkr".Clkrx.Clkry) Pipeline register  nodes  Locn(Mem."leftp",Leftpx,Leftpy) I Locn(Mem,"riahtp",Riqhtpx,Rightpy) i Locn(Mem." l e f t p / " . L e f t p n x , L e f t p n y ) i Locn(Mem,"r i g h t p / " , R i g h t p n x , R i g h t p n y ) **********  P l a c e the x - d e c o d e r Placet"biaxdcod",168,-81,Xdecod) ! DIM R d p x ( 4 ) , R d p y ( 4 ) DIM G d p x ( 4 ) , G d p y ( 4 ) DIM B d p x ( 4 ) , B d p y ( 4 ) i FOR 1=0 TO 3 Locn(Xdecod,"rdp"<iVALS(I),Rdpx(I + 1 ),Rdpy(I + 1 ) ) L o c n ( X d e c o d . a d p " & V A L $ ( I ) , G d p x d + 1 ) , G d p y ( I + 1 )) Locn(Xdecod."bdp"&VALS(I),Bdpx(I+1),Bdpy(I+1)) NEXT I ! Locn(Xdecod,"xsiglef t",Xsigx,Xsiay) Locn(Xdecod,"btmleft".Btmleftx,Btmlefty) Locn(Xdecod,"toprght".Toprghtx,Toprghty) ,,  Check i f f i l e updated  correctly  IF B t m l e f t y O R d p y d ) THEN BEEP PRINT "node e r r o r " END IF  ************************************ Vss bus  1 8 1  1210 1220 1"'~-tG ; j 1250 1260 1270 1280 1290 1300 1310 1320 1330 1340 1350 1 -.60 1370 1380 1330 1400 1410 1420 1430 1440 1450 1460 1470 1480 I "0 L.O 1510 1520 1530 1540 1550 1560 1570 1580 1530 1600 1610 1620 1630 1640 1650 1660 1670 1680 1690 1700 1710 1720 1730 ( 0 1/60 1770 1730 1790 1800  ! Pitch=168 B t r i g h t x = B t m l e f tx + ( P i t c h + 6 ) ! Layer(Metal) Wiref12,Btmleftx-2.Btmiefty-10) X(Btnahtx+2) ! ! Connect Vss bus to the xdecoder ! FOR 1=0 TO 6 Wire(4,Btmleftx+(Pitch*I),Btmlefty ) Dy(-10) NEXT I ! '  i  '  ! P r o c e s s o r d a t a busses ! Dili Datay(4) ! FOR 1=1 TO 4 ! Datay(I>=Btmlefty-20-(I-1)*6 ! ! H o r i z o n t a l metal busses ! LayerlMetal) W i r e ( 2 , B t m l e f t x - 2 , D a t a y (I)> X(Btrightx+2) ! ! P o l y jumpers over the Vss bus ! Layer(Polyl) ! Mp(Rdpx(I),Rdpy(I),Rdpx(I>,Datay(I)) Wire(2.Rdpx(I),Rdpy(I)) Y(Datay(I>> ! Mp(Gdpx(I).Gdpy(I).Gdpx11),Datay(I)) Wire(2,Gdpx(I).Gdpy(I)) Y(Datayd)) ! Mp(Bdpx(D,Bdpy(I),Bdpx(D,Datay(I)) Wire(2.Bdpx(I) .Bdpyd)) Y(Datay(D) ! NEXT I ! ******************************************** 1  i  ! i n p u t e n a b l e busses !  ! ! enable / ! ! Note t h a t the l e n a t h of the i/o ! pads i s 800 !  182  1810 1820  y U  -r, J  1850 1860 1870 1880 1890 1900 1910 1920 1930 1940 1950 1960 1970 1930 1990 2000 2010 2020 2030 2040 2050 2060 2070 2080 3 3 2 1 UO  2110 2120 2130 2140 2150 2160 2170 2180 2190 2200 2210 2220 2230 2240 2250 2260 2270 2280 2290 2300 2310 2320 2330 -0 2,0 2360 2370 2380 2390 2400 T  Ennleftx=Btrightx+2-800 Ennlefty=Datay(4)-6 j Layer(Meta1) W i r e ( 2 , E n n l e f t x . E n n l e f ty > X(Btrightx+2) enable E n l e f t x = E n n l e f tx Enlefty=Ennlefty-6 j Layer(Meta1) Wire(2,Enleftx,Enlefty) X(Btrightx+2>  P l a c e the p r o c e s s o r I/O  pads  Iovssy=Enlefty-10 Iovddy=Iovssy-11 3 I  Place("iopad,my".Enleftx,Iovssy,Iopad) Connect the e n , e n / , i n and out/ s i g n a l s to t h e i r r e s p e c t i v e busses FOR 1=1 TO 4 enable Locn(Iopad,"en"&vAL$(I).X,Y) Mp(X.tnlefty ) Layer(Polyl) Wire(2.X,Y) Y(Enlefty) j ! enable / i Locn(Iopad,"en/'*dVAL£(I) ,X,Y) Mp(X,Ennlefty) Layer(Poly1) Wire(2,X,Y) Y(Ennlefty) input Locn(Iopad,"i n"&VAL$(I),X.Y) Mp(X,Datay(I)) Layer(Polyl) Wire(2,X,Y) Y(DatayCI)) output Locn(Io ad,"out/"&VAL$(I).X,Y) Mp(X.Datay(I)) Layer(Polyl) Wire(2,X,Y) 183 P  2410 2420 2-0 2 .0 2450 2460 2470 2480 2490 2500 2510 2520 2530 2540 2550 2560 2570 2530 2590 2600 2610 2620 2630 2640 2650 2660 2670 2680 0 2/u0 2710 2720 2730 2740  Y(Datayd)) ! NEXT I ! *******•*•****•******•*+*•******•******+* ! ! P l a c e the p r o c e s s o r y decoder ! ! Placet"neuypqen".-129,0.Ypgen) ! DIM A i n p x ( 4 ) . A i n p y ( 4 ) ! FOR 1=1 TO 4 Locn(Ypaen."ain"&vAL$(I),Ainpx(I).Ainpy(I)) NEXT I ! Locn(Ypgen."vdd".Ypvddx,Ypvddy) Locn(Ypaen,"vss".Ypvssx,Ypvssy) ! ! Connect VSS to newypqen ! Layer(Metal) Wire(4,Ypvssx.Ypvssy) X(Btmleftx) ! ! Connect Vdd to newypqen ! Layer (Metal) Wire(4,Ypvddx.Ypvddy) Y(Dacvddly) Wire(12.Dacvddix.Dacvddiy) X(Y vddx-2) !  2760 2770 2780 2790 2800 2810 2820 2830 2840 2850 2860 2870 2880 2890 2900 2910 2920 2930 ?~'<0 I -.0 2960 2970 2980 2990 3000  ! ! P l a c e the v i d e o y decoder ! ! Placet"newyvgen",1017.0,Yvgen) ! DIM A i n v x ( 4 ) , A i n v y ( 4 ) ! FOR 1=1 TO 4 Locn( Yvaen, " a i n " & V A L $ ( I > . A i n v x d ) , A i n v y ( I ) ) NEXT I ! Locn(Yvqen,"vdd",Yvvddx,Yvvddy) Locn(Yvaen."vss",Yvvssx,Yvvssy) ! ! Connect VSS to newyvgen ! Layer(Metal) Wire(4,Yvvssx,Yvvssy) X(Toprghtx) ! ! Connect Vdd t o newyvgen ! 184 Layer(Metal) Wire(4,Yvvddx,Yvvddy)  1  P  3010 3020 3 '»0 n  2  Y(Dacvddry) Wire(12,Dacvddrx,Dacvddry) X(Yvvddx+2)  J  3050 3060 3070 3080 3090 3100 3110 3120 3130 3140 3150 3160 3170 3180 3190 3200 3210 3220 3230 3240 3250 3260 3270 3280  5  0  3^oO 3310 3320 3330 3350 3360 3370 3380 3390 3400 3410 3420 3430 3440 3450 3460 3470 3480 3490 3500 3510 3520 3530 3 «0 c/  i o  3560 3570 3580 3590 3600  P l a c e the c o n t r o l s i g n a l  generator  The top r i g h t hand c o r n e r o f ' n e u c t r i ' i s l o c a t e d a t ( 1 1 7 . 3 7 ) r e l a t i v e to i t s origin. We a l l o u an x - s p a c i n g o f 40 from the l e f t hand edge of the x - d e c o d e r to r o u t e the p o l y b u s s e s . We a l l o u a 5 lambda s p a c i n g from the bottom of the y - d e c o d e r . Neuctrlx=0-40-117 Netjctr l y = Y p v s s y - 5 - 3 7 Place("neu)ctrr\NeuJctrlx.Neuctrly.Ctrl) i Locn(Ctrl. 'ctrlvdd",Ctrlvddx,Ctrlvddy) L o c n ( C t r l , ' c t r 1 v s s " , C t r 1 vss>:,Ctr 1 vssy ) L o c n ( C t r l . "cs",Csx,Csy) L o c m C t r i , ' r w " , Rux. Rwy) Locn(Ctrl, 'e",Ex,Ey) Locn(Ctr1, 'a4".A4x.A4y) Locn(Ctrl, 'a5\A5x,A5y) L o c n ( C t r l , 'busbttn" .Busbtmx .Busbtmy ) Locn(Ctrl. 'ctrlrat",Ctrlrgtx,Ctrlraty) Locn(Ctr1, ' t r i " . T r i x , T n y ) Locn(Ctrl, 'triouf'.Trioutx.Triouty) Locn(Ctr1. t r ioutb",Tr ioutbx,Tr ioutby) 1  *************************************  Connect c o n t r o l bus t o x decoder Wsep=4 Layer(Polyl) FOR 1=1 TO 8 Locn(Ctrl,"xdcbus"&vAL$(I),X1.Y1> X1=X1 Y1=Y1 X2=X1+(9-I)*Wsep Y2=Y1 X3=X2 Y3=Xsigy+(I-1)*(Wsep+1) X4=Xsiax Y4 = Y3 Wire(2,X1.Y1) X(X2) Y(Y3) X(X4) CtrlxKI)=X1 Ctrlyl(I)-YI 185  3610 3620 3690 2 3 3bb0 3660 3670 3680 3690 3700 3710 3720 3730 3740 3750 3760 3770 3780 3790 3300 3810 3820 3830 3840 3850 3860 3870 3880 3f ~'0 1 .0 3910 3920 3930 3940 3950 3960 3970 3980 3990 4000 4010 4020 4030 4040 4050 4060 4070 4080 4090 4100 4110 4120 4130 4140 < 0 4ib0 4170 4180 4190 4200  Ctrlx2(I)=X2 Ctrly2(I)=Y2 Ctrlx3(I)=X3 Ctrly3(I)=Y3 Ctrlx4(I)=X4 Ctrly4(I)=Y4 NEXT I •***#4#************************  Connect the i n p u t pad e n a b l e and enable/ s i a n a l s en/ Layer(Meta1) Wire(2.Trioutbx.Trioutby) XlBtmleftx) YCEnnlefty) X(Ennleftx) en Layer(Meta1) Wire(2.Trioutx,Triouty) XlBtmleftx+4) Y(Enlefty) - XtEnleftx)  Connect pouter and ground t o the control c i r c u i t r y (neuctrl) Vss Layer(Metal) Wi r e ( 4 , C t r 1 v s s x , C t r 1 v s s y ) Y(Ctrlvssy-4) X(Btcr.lef tx+9) Y ( I o v s s y ) ! Vss r a i l of i / o pads X(Enleftx) Vdd Layer(Meta1) Wire(4,Ctrlvddx.Ctrlvddy) Y(Ctrlvssy-4-6) X(Btmleftx+9+6) Y(Iovddy) X(Enleftx) ************************************ P l a c e and r o u t e the p r o t e c t e d pads ue r e q u i r e 17 DIM I n a d ( 1 7 ) DIM P a d o u t x ( 1 7 ) ! i n p u t pads DIM P a d o u t y ( 1 7 ) 186 P  input  snq S S A , pueu, m S i y  £81  j i  i i  (9)X}nope )x (OjA^nopPcDA d7+0t+ PP* A)X (^ud4M6Ty'xud;q6Ty'2)aaTM lAT |)jaAe-i i /d a ; n o y j i ( (S) + P d)X ((5)*+ P d)A (0t+xppAA (rfd:m6Ty xd:m5Ty'3)e.iTM ( l A j c - d ) jaAe-| i d a;noy \ i A=do}ssrt (  d  x  A  (  0 c  x  e  n o  n o  e  A ) X  4  I  008(7 O6ZI7  1X3N  08 Zl7 0ZZ«7 09/17 0 > 0i?Lt7 0SZ«7 Q3ZI7 OlZfr 00ZI7 06917 089<7 0Z9I7 09917 0S9«7 ot79t7 08917 039»7 019* 009^ O6SI7  ((l7+I)^+nc.ped* ()7+I) + P d , , + . . ' ( i 7 + I ) P I) l ( ( i 7 + I ) P e r A X ' , . 0 Z 3 P T „ )ao«?Id H3+Tdpej*( i-D+OA-A 3 01 1=1 HOJ i qo^Tdped*2-AjppA3BQ-0A i /d p u e d j a ^ s j o a a a u T j a d i j j  OZSfr 09Sfr OSS* OfrS* OSS* 02S* 0 1 S *  !  ° "f  :<  n o  e  d u  4  n o  e d u  ,  J k  u : j o  B d u  I  i 1X3N  T)x;nope x ((I)^+nopBd) (l7)xa ( (I)AAUTy(l)XAu y 3)aaT ( tAT°d) jeAe-] ( ( I ) A + nop*d"» a j x ; n o D 8 d * ; n o ( j j p e d u j juoo~| ( (I ) p e d u i - 1 • x „ 0 Z 3 P T ) 3 3 B i d u,o}Tdped*( t - I ) + 0A = A 17 01 1=1 iiOJ i u o i T d p e d - 2 / ( (3)AAUTy (e)AAUTfc))=0A ( (  d )  A  k  T  l ( ,  i (  M  4  J ,  B d u  I I  +  s^nduT  jepooep A oapTA  O8SI7  P  08i7i7 OZI7I7 09** OS** 0*** 0£*7*7 Q2** 0 Lt7*7 00** 06£«7 088* 0ZS* 09817  i  0S£*  J  0*£* 0££*  i  i  + s j i o s n a + 8 + ( 1 )XAury=X i a p i s pueq } q 6 T j au,} S u o f e s p e j j i *****^**********************^*******j i s n q ssft $o a i ^ u e o 03. j apou ^ndur UIOJ + a o u e ^ s r p i £t=;s>>osng OOl-Ma+Tdpej i  OI8I7  00817 06317 08217 0Z2* 092* 0S2I7 C * Q ^t7 022i7 01217 0  4810 4820 £ ^0 r,  L  .  0  4850 4860 4870 4880 4890 4900 4910 4920 4930 4940 4950 4960 4970 4980 4990 5000 5010 5020 5030 5040 5050 5060 5070 5080 n rj  Layer(Metal) Wire(12,Btrightx+2,Iovssy) X(X) Y(Vsstop) Jumper to j o i n the i o p a d v s s bus w i t h the x decoder v s s bus Layer(Meta1) Wire(12,Btriahtx+2,Btmlef ty-10) Dx(10) Y(Iovssy)  Vss pad Layer(Meta1) Box(X-6,Iovssy+6-50.X-6+50,Iovssy+6)  R i g h t hand vdd bus Layer(Metal) Wire(12.Btrightx+2.Iovddy) X(X+113) ! d i s t a n c e between v s s Y(Dacvddry) ! and vdd of pads i s 113 X(Dacvddrx)  §.o6  5110 5120 5130 5140 5150 5160 5170 5180 5190 5200 5210 5220 5230 5240 5250 5260 5270 5280 5290 5300 5310 5320 5330 $ 0 5360 5370 5380 5390 5400  Vdd pad Layer(Meta 1) Box(X+113+6-50,Dacvddry+6-50.X+113+6,Dacvddry+6) ********************************* dac v o l t a g e r e f e r e n c e pads Layer(Metal) Wire(12,Vref2rx.Vref2ry) X(X+113+6-50) Box(X+113+6-50,Vref2ry-25,X+113+6,Vref2ry+25) I L a y e r ( M e t a 1) Wire(12,Vref1rx,Vref1ry) X(X) Y(Vref2ry-Padpitch) X(X+113+6-50) Box(X+113+6-50,Vref2ry-Padpitch-25,X+113+6.Vref2ry-Padpitch+25) ********************************** P l a c e the logo i n the gap between the dac v o l t a g e r e f e r e n c e pad and the dacvdd r a i l . X0=X+113 Xh=X0-Dacvddrx Y0=Dacvddry Yh=Vref2ry-Padpitch-Y0 !  188  i.D  3 O  a CN > O  cri o  _i  «— . —  X  o o o o  o  -*->  »  o  OJ  o  • «—  >  o ai o •  *—  o Oi o  _J  »  r  _J . _ l •t- 1 C\J C\J  0)  o = —  o  + +  —. —. •—  >  X  o o Oi Oi o O  _J _J 1 1 C\J CN >  X  o o ai oi o o  _i —i -—•  o  +  w  + 1 CMCM \  \  -C XT  X >1 + i—>  X  o  >-  .a CQ — X > II  II  —I in  xi c  X  X) 0 )  CO XI • — i  • (1) O <-.  >. -t-'  .—1  >-  OJ  «  X r  0;  o •T)  +->  -  Oi  O Oi  o  •—1 = •—  * +  OJ  •—1  • Q_  o  .—I  ro 01  a.'  o  c  *  X ro  Q_  o  +->  o  a> o  X  .  4 —  -  »  Lfl  ro  +  » X  (- CO +  x  3 —•  C  = o -  x O  3 0j 2  CQ  X  X) II  01  <-*-  o  CQ 1  W  CM 1 X  II X  +  X  C ro  o o  X)  -C X  4-  1  -t->  CLX  c c  ro  o  C3  •  —••  x: o  o  >.  X  II  o  •—i  II  or  1—1 o  «i  o >—1  X  >  X «-i LD ro - + a. x i + ro — —  a  .. >_ _ .•  + o >-  c  a> —  o c  II  X  LJ  CM  —1  o  O'l  0"!  • z? ~Z. —• -  +  *—•  i_ r^- r-- r-J— ~ w w  —  +  J  Oi 3  o  - X X  >  •-> 3  3  •-H  ro  +  >II a  «—  •— ^  X ro  ro O I—1 —i 0 >- Q 11—  Li_  —  a  a t  LO  •— CO  —i  ax C ro —« a =  "—  +->  U.0~i —  O'l 01 OJ a ro o u tO) Q. O'l Oi  3  -  o  >  •—«  oo  ax  o  +  —  X 3 ro O  01  —< X I  a  ro •  —. — •  -Cl CO  4->  +•  (-.  (-4  c ro co aj o a * r—1 a in  a c  3  4»  ai Oi  — + tX) I—I  3  01  ' 1  1X1 a: ' o C UD  ro  —•  c  — CD  +  ro —H  (-4  X)  XI  0J  3  o o o  X • ro ro ro CM a a a  w ^ OJ 0> X >- X v  >  ro - i - -_l 1 2  v  >>CG CO l_Ti — — <r x >. —( • -(-•  X  Qj\— X X  -—  ITJ  ro Oi +J 3  O  a:  X  3  3  'X — x 3  oi<r x x x 21 • ro ro ro —P— c\i a a. a. —• •— 0> 0) X >  (-  ro —•  .. _j  ^  >-  X  o  > c n a*j cn  «sr w w « ^ a: x > x —1 . + J 4 - > -t^  -t-j  •^m o o o  -.^  ^  rc x  3  3  3  ro  •*-> <T O  ai  XI  -t-> 3  o or  0><r X X  X  • ro ro ro —( - t 'C—M—O' -—Q' -^ —a' OJ OJ  X  > fr« ro -»H ••J3  >-  X  O OJO OJ -<->  >  X  OJUJ  X  OJ  x  —< QJ -*•» rrj - 3 +J x O  z:  • ro oj a  3  O  cc  0)  > f-  ro -* - J 3  co cn  .O O O O O CD O CD O O CD O O O O O O CD O O O O O ~J O O O O O o o C3 ~ ' o o o o o o C3 o o o o o o CD o o o o CD o c^.. o o o <r> •> r - C\) CO <T U"" uD r~- CO CTi CD » — CsJ CO <T |_H i X r - CO <T> O CM CO 'jD N o — CM o _fi ix) r^. co cn o « — CM co <r LP LO OJ cn o » - o j co <r u"i X> r^- CO r^r^r^r^r^r^r^r^r-coori'DDCOCOODCOOOCOOOCncncncna jicncncno <T>T N <r <r <r -o" ->r u~i u"i u i LT> U~I LTI U"I U"I U"I UI UJ >X >XI IX> t x LO CO UD U"i Ll~l U"l U l L f l U~l U* U"i U^ U") u^ u"i LT) LP LO u l U " ) L ( * I LD LTl — J \S\ LH u"i un L LTi L P U"i LTl U"l Li") Ufl U l L P L O U~l L O LTI U l L f l LTl U'l U") L f l L O LTl U*l LO U l U"l U"l iXl LTl U ) LTI L f l U") U"I U"l  6010 6020 6030 6 0 6.^0 6060 6070 6080 6090 6100 6110 6120 6130 6140 6150 6160 6170 6180 6190 6200 6210 6220 6230 6240 6250 6260 6270 6280 6?90 0 0 6310 6320 6330 6340 6350 6360 6370 6380 6390 6400 6410 6420 6430 6440 6460 6460 6470 6480 6490 6500 6510 6520 6530 6540  r-o  6570 6580 6590 6600  Y(PadoutyMO)) X<Padoutx(10)) Route rw Layer(Metal) Wire(2,Ru>x,Rwy) X(Padoutx(11)+19) Y(Padouty(11)) X(Padoutx(11)) Route c s Layer(Meta1) Wire(2.Csx.Csy) X(Padoutx(12)+23) Y(Padouty(12)) X(Padoutx(12)) Route p r o c e s s o r y decoder  inputs  Layer(Metal) FOR 1=1 TO 4 Mp(Ainpx(I)-2,Ainpy(I)) Wire(2,Ainpx(I)-2,Ainpy(I)) Dx(-5-(4-I)*4) Y(Padouty(I+12)) X ( P a d o u t x d + 12) ) NEXT I  dac c l o c k i n p u t j Y = Dacv/ssly-2*Padpitch Place("inpad r90".X,Y.Inpad(17)) Locn(Inpad(17)."out",Padoutx(17),Padouty(17) ) f  Layer(Poly1 ) Wire(2.Clklx,Clkly) X(Padoutx(17)+7) Y(Padouty(17)) X(Padoutx(17))  L e f t hand Vss bus Layer(Meta1) Wire(12,X,Iovddy) Y(vsstop) Vss pad L a y e r ( M e t a 1) Box(X+6-50,Vsstop-50,X+6.Vsstop) Box(X+6-50,Iovssy+6-50.X+6,Iovssy+6) *******+*************************** 190  6610 6620 66 6  '-to : >  6bt>0 6660 6670 6680 6690 6700 6710 6720 6730 6740 6750 6760 6770 6780 6790 6800 6810 6820 6830 6840 6350 6860 6870 6880 f ' l  (L .0  6910 6920 6930 6940 6950 6960 6970 6980 6990 7000 7010 7020 7030 7040 7050 7060 7070 7080 7090 7100 7110 7120 7130 7140 1 0 7 ibO 7170 7180 7190 7200  ! Lef t hand vdd bus i Layer(Meta1) Wire(12,X-113,Iovddy) Y( Y) Wire(12.X-113,Dacvddly) X(Dacvddlx) i  Vdd pad ( T h i s i s not r e a l l y needed because t h e vdd bus e x t e n d s over t o to r i g h t hand s i d e ) Layer(Meta1) Box(X-113-6,Dacvddly+6-50,X-113-6+50.Dacvddly+6) i dac v s s pad Layer(Metal) Wi r e ( 1 2 , D a c v s s l x , D a c v s s l y ) X(X-113-6+50) Box(X-113-6,Dacvssly-25,X-113-6+50,Dacvssly+25 i ! connect v s s t o the c l k i n p u t pad i Wire(12,X.Dacvssly) Y(Dacvssly-Padpitch) i P l a c e and r o u t e the dac o u t p u t pads ! Layer(Metal) FOR 1-1 TO 6 Wire(2,0utx(D,0uty(I)) Y(Outy(I)+50) Box(Ou t x ( I ) - 2 5 . O u t y ( I ) + 5 0 , O u t x ( I ) + 2 5 . O u t y ( I ) + 5 0 + 5 0 ) NEXT I j ! * - * * - * + * * # - *  - i t - * * * - * * * * * - * * * - *  *  *  *  *  *  *  *  *  *  *  *  *  *  *  Endc PRINT "*****'**********" Bbox("palette",XI.Y1,X2,Y2) PRINT " p a l e t t e bounding b o x = " , X 1 , Y 1 , X 2 , Y 2 PRINT "*******-******•*•" PRINT " d a c v d d l x , y = " , D a c v d d l x , D a c v d d l y PRINT "dacvddr x,y=",Dacvddrx,Dacvddry PRINT "******•******#•»" PRINT " d a c v s s l x , y = ' \ D a c v s s l x , D a c v s s l y PRINT " d a c v s s r x , y = " , D a c v s s r x , D a c v s s r y PRINT "*•***•**•******•*•*•*" PRINT " o u t x=" PRINT Outx(*) PRINT " y=" PRINT Outy(*> PRINT "***************" PRINT " v r e f l l x,y=",Vref1lx,Vref1ly PRINT " v r e f l r x , y = " , V r e f 1 r x , V r e f 1 r y 191  7210 7220 7230 7 D 7^0 7260 7270 7280 7290 7300 7310 7320 7330 7340 7350 7360 7370 7380 7390 7400 7410 7420 7430 7440 7450 7460 7470 7480 7'^0 7 . ,0 7510 7520 7530 7540 7550 7560 7570 7580 7590 7600 7610 7620 7630 7640 7650 7660 7670 7680 7690 7700 7710 7720 7730 7740 7 0 7/DO 7770 7780 7790 7800  PRINT " v r e f 2 1 x , y = " , V r e f 2 1 x . V r e f 2 1 y PRINT v r e f 2 r x , y = " , V r e f 2 r x . V r e f 2 r y PRINT "********•*-*****-**" PRINT " c l l c l x , y = \ C l k l x , C l k l y PRINT " c l k r x ,y = " , C l k r x . C l k ry PRINT "**•********-*•*******" PRINT " l e f t p x , y = " . L e f t p x . L e f t p y PRINT "*******•**+•****•*•**•*'' PRINT " l e f t p / x , y = " , L e f t p n x , L e f t p n y PRINT "******•*****•#•*•**" PRINT " r i g h t p x ,y = ' \ R i g h t p x , R i g h t p y PRINT "*****************•*" PRINT " r i g h t p / x , y = " . R i g h t p n x , R i g h t p n y PRINT "**#*+**+•***•**•*****" PRINT " r d p x=".Rdpx(*) PRINT " y=",Rdpy(*) PRINT " PRINT "gdp x=".Gdpx<*) PRINT " y = '\Gdpy(*) PRINT "+**+*****#**+•*•*-***•*•*•*" PRINT "bdp x=",Bdpx<*) PRINT " y=",Bdpy(*) PRINT PRINT " a i n v x = " . A i n v x ( * ) PRINT " y= \Ainvy(*) PRINT "***********************" PRINT " a i n p x = " . A i n p x ( * ) PRINT. " y=",Ainpy(*) PRINT "**********************-*'' PRINT " c s x . y = " , C s x , C s y PRINT " r u x ,y = \ R w x ,Ruy PRINT "e x , y = " , E x . E y PRINT "a4 x , y = " . A 4 x , A 4 y PRINT " a 5 x , y = " , A 5 x . A 5 y PRINT ''^fr*******************-*' PRINT " b t m l e f t ( v s s ) x , y = " , B t m l e f t x , B t m l e f t y PRINT "***************#*******" PRINT " x s i g l e f t x , y = " , X s i g x , X s i g y PRINT "*****+****•++*+*******+•*" PRINT " c t r l r g t x , y = " , C t r l r g t x , C t r l r g t y PRINT "***¥•***•* + *•**•***** + *•**:*¥:" PRINT " i o v d d r x,y=",Btrightx,Iovddy PRINT " i o v d d l x , y = " , E n l e f t x , I o v d d y PRINT " i o v s s l x,y=",Enleftx,Iovssy PRINT " l o v s s r x,y=".Btrightx,Iovssy PRINT "*********************#*" PRINT " c t r l v s s x , y = " , C t r l v s s x , C t r l v s s y PRINT " c t r l v d d x , y = " , C t r l v d d x , C t r l v d d y PRINT "**********************-**" PRINT "padout x = , P a d o u t x ( * ) PRINT " y=\Padouty<0 PRINT "*******************•**•***" ! FOR 1=1 TO 8 ! PRINT " c t r l l ( " A V A L S ( I ) , " ) x.y=",Ctrlx1(I),Ctrly1(I) ! PRINT ' c t r l 2 ( " A V A L $ ( I ) . " ) x,y=",Ctrlx2(I),Ctrly2(I) ! PRINT c t r l 3 ( " A V A L $ ( I ) , " ) x,y='\Ctrlx3(I),Ctrly3(I) ! PRINT " c t r 1 4 ( " A V A L S ( I ) , " ) x , y = " , C t r l x 4 ( I ) , C t r l y 4 ( I ) ! PRINT " " ! NEXT I 192 ! PRINT M  1  u  H  7810 ! 7820 PRINTER IS 1 7°°0 ! 1 0 END  193  V6T  1*21*2*S8*S£11-  8001 012 012 8001  2-  181-  0  =A*X  = A«x  £62 S£U  Z61 621Z61 S£U  101 621-  SZ21  = ' S =**x * = ® A  X  B B  =A x mi =A'x so 4  * * * * * -<• •* * •* * •* * f * -«• * * * *  LOl S£ t i  S  -A  621-  =x  S  =  S£l I  =  dute  A  x  A  Te  U  131£83  131628  L31158  181Z66  -* = pq  131Z*£  181-  £617  131SIS  131l^gg  =  =x dp6  181IL  131 ZSi  1316Zt  131S2£  =A =x  0Z02 8**6Z  688-  x d  A  Y  = A»X /d^qSiJ  8191  800!  8£Sl  8001  = A»x  d}L|6Tl  8191  0  =A«x  /d+ja[  8S02 8S02 **02 **02  0Z12  ( S S A ) ^ajuj + q  SSI-  0 =A'x d+^a[  3*6*01  Z902 Z902  £*£S6  ^jeTBTSX  SSI-  8£Sl  0Z02  })  SSISSISSI-  82£•7629612910£l£62 621-  JSSAOT TSSAOT |ppAOT jppAOT  = A'X  0«7-  OSl-  = A'X = A*X = A'X = A*X  0Z02 8*265  -MI  X  H I  3 3  I^-fdJA  =A'X  =A'x  T2i  =A*X  ^J8JA  =A  \[  4  X  e j A  * 4 * 4-*-**-*•#•*-«••*-«•  0Z02  0Z02  0Z02 =A  £•282  £**£*  0£02 0£02  8*6*01 Z* l£  ££91 ££91  8*6*01 Z' IP.£•  £S£-  A  Z* 1 6 -  8*61701 Z* l£3 ' 6*0 I Z* t£-  =*  =xoq  8*£Z  = x \ no #•**•*****•****•*••>• =A*x jssAoep =A*X  TSSAOep  =A =A  ipp^ ;> yppAoep  X X  ouTpunoq  3-443 j e d  ctrlvss  x,y =  r'rivdd  X i y  =  padout x= 1144 -222 -222 -222 -222 y- -1 -204 -104 S96 1880 ****************  -84 -149  -377 -377  1144 -222  1144 -222  1144 -222  199 96  299 196  99 -4 r****+--M-  195  1144 -222  1144 -222  -222  1383 296  1483 396  -304 496  -222  c  3  )  196  

Cite

Citation Scheme:

        

Citations by CSL (citeproc-js)

Usage Statistics

Share

Embed

Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                        
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:
http://iiif.library.ubc.ca/presentation/dsp.831.1-0095834/manifest

Comment

Related Items