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Design of a tunable CML-based differential ring oscillator with short start-up and switching transiets Mollah, A.K.M. Kamruzzaman 2004

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Design of a Tunable CML-based Differential Ring Oscillator with Short Start-Up and Switching Transients by A. K.M. Kamruzzaman Mollah B. Eng., McGill University, 2002 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF T H E REQUIREMENTS FOR T HE D E G R E E OF MASTER OF APPLIED SC IENCE in THE FACULTY OF G R A D U A T E STUDIES (Department of Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH COLUMBIA December 2004 © A.K.M. Kamruzzaman Mollah, 2004 Abstract In this work, an improved Current-Mode-Logic-based (CML) ring oscillator is designed for use in an on-chip Vernier-based Time-to-Digital Converter (TDC) that could be used to measure timing specifications of high-speed signals, such as period and jitter, in the picoseconds range. The oscillator is designed with two tuning mechanisms to achieve coarse and fine tuning resolutions. The period of the oscillator can either be tuned from 0.5% to 10% or from 0.05% to 2.5% of the oscillator zero-resolution period (550 MHz) during coarse and fine resolutions of operation, respectively. A detailed study and characterization of the impact of the oscillator period variations when it is switched ON (start-up transient) and when the oscillator period is switched from one resolution to another (switching transient) on a Vernier oscillator-based TDC time interval is presented. The impact of oscillator period deviations in steady state and externally introduced random noise on the TDC performance is also shown analytically. A metric to characterize the effects of these transients and jitter on the time interval measurement is derived to benchmark the performance of the ring oscillator. This metric can be used to evaluate performance of any oscillators for its stability. Simulation results from the optimized ring oscillator show that the effects of the start-up transient become negligible after four clock cycles and that of the effects of switching transient become negligible instantaneously. Simulation also shows that the oscillator can achieve a stable steady state period, down to less than 0.5fs, which is the simulator precision. In reality, the oscillator will contain some random jitter due to external noise. This kind of jitter can be eliminated through averaging. ii Simulations also show that the oscillator could be fine tuned to a resolution of under one picosecond. A Vernier oscillator-based TDC using the modified oscillator was designed and simulated with input timing noise to demonstrate the stability of the ring oscillator and its robustness in TDC applications. Results show that two of these oscillators could be used in such a TDC design to measure timings in the range of picoseconds with the maximum error bound by the fine resolution of the oscillator. iii Table of Contents Abstract • ii Table of Contents iv List of Tables vii List of Figures viii Acknowledgements xii Dedication xiv Chapter 1 Introduction 1 1.1 Overview and Motivations 1 1.2 Thesis Organization 5 Chapter 2 Time-to-Digital Converter (TDC) Background 7 2.1 Different TDC Architectures 7 2.1.1 Counter-based TDC 7 2.1.2 Delay Chain 8 2.1.3 Vernier Delay Method 11 2.1.4 Ramp and ADC Method 13 2.1.5 Vernier Oscillator-based TDC 13 Chapter 3 Impact of Oscillator Non-idealities on TDC Design 18 3.1 Sources of Error 18 3.2 Impact of Oscillator Transients 20 3.3 Impact of Variations in T A and T B 24 3.4 Error due to Quantization 28 3.5 Stability Metric 29 Chapter 4 CML Differential Ring Oscillator Design 35 4.1 Introduction 35 4.2 Ring Oscillator Theory 35 4.2 CML Background 39 iv 4.3 Overall Ring Oscillator Architecture 42 4.4 CML Buffer and AND Gate 44 4.4.1 Pull-Down Network 46 4.4.2 Current Source 47 4.4.3 Output Voltage Swing 47 4.4.4 Pull-Up Resistors 48 4.5 Tuning Mechanism 52 4.5.1 Delay Elements-based Resolution Mechanism 53 4.5.2 Current Steering-based Resolution Mechanism 57 Chapter 5 Results and Analysis 61 5. 1 Methodology 61 5.2 Oscillators without Tuning 62 5.2.1 Original Oscillator Performance 62 5.2.2 Modified Oscillator Performance 67 5.3 Oscillators with Coarse and Fine Resolutions 69 5.3.1 Original Oscillator Performance 69 5.3.2 Modified Oscillator Performance 71 Chapter 6 Vernier Oscillator-based TDC Design 79 6.1 Goal 79 6.2 TDC Overview 79 6.2.1 Trf Generator • 80 6.2.1 Double Oscillator 80 6.2.2 Counter 80 6.2.3 Resolution Controller 81 6.2.4 Coincidence Detector 81 6.3 TDC Calibration 82 6.4 TDC Results and Analysis 83 6.4.1 Original Oscillator with 5 0 0 < Td < 600ps 84 6.4.2 Modified Oscillator with 500ps <Td < 600ps 91 6.5 Summary and Comparison of Results 95 Chapter 7 Conclusions 97 7.1 Summary of Contributions 97 7.2 Future Work 98 References 100 V Appendix A 105 A.l Original Oscillator with 500ps <Td < 600ps 106 A.2 Modified Oscillator with 500ps < Td < 600ps 108 A.3 Modified Oscillator with 250ps <Td< 350ps 110 A.4 Resolution Adjusting Blocks 112 A.5 Oscillator Schematic 113 vi List of Tables Table 4.1: Coarse Tuning 57 Table 4.2: Fine Tuning 60 Table 6. 1: Summary of Tj results as measured from TDC with the original oscillator... 89 Table 6. 2: Summary of Tj results as measured from TDC with the modified oscillator 93 Table 6. 3: Summary and comparison of the results of a test 7^  95 vii List of Figures Figure 1.1: Time interval to be measured using TDC 2 Figure 2.1: Using a counter to quantize a time interval 8 Figure 2.2: Using a delay chain to quantize a time interval 9 Figure 2.3: Using differential delay chains to quantize a time interval 11 Figure 2.4: Double oscillator based single resolution Vernier TDC showing z'th edges in oscillators A and B drawing closer after each cycle 13 Figure 2.5: Double oscillator based double resolution Vernier TDC showing z'th edges in oscillators A and B drawing closer after each cycle [ 1 ] 15 Figure 3.1: Illustration of period calculation in an ideal oscillator...; 18 Figure 3.2: Illustration of start-up transient and period jitter of an oscillator 21 Figure 3.3: Impact of oscillator start-up and switching transient on TDC measurement. 22 Figure 3.4: Zoomed-in plot of Fig. 3.2 showing the period variations of region 2 25 Figure 3.5: Illustration of period jitter 26 Figure 3.6: Illustration of Stable Period 30 Figure 3.7: Illustration of PeriodQualityWindow definition 31 Figure 4.1: Single-ended ring oscillator structure 36 Figure 4.2: Small signal single-ended equivalent for the ring of Fig. 4.1 36 Figure 4.3: Double-ended ring oscillator structure 37 Figure 4.4: Concept of a basic CML gate 40 Figure 4.5: Overall ring oscillator architecture 43 Figure 4.6: CML Buffer architecture 44 Figure 4.7: CML AND gate architecture 45 viii Figure 4.8: CML Buffer simulation results showing the input and output characteristic. 49 Figure 4.9: CML AND gate simulation results showing input and output characteristic. 50 Figure 4.10: Overall oscillator output before applying any coarse or fine resolution 51 Figure 4.11: (a) Voltage controlled NMOS load-based delay element (b) A simple model for the delay element in (a) 53 Figure 4.12: (a) NMOS load-based delay element (b) A simple model for the delay element in (a) 54 Figure 4.13: (a) Capacitive load-based delay element (b) A simple model for the delay element in (a) 55 Figure 4.14: (a) An alternative capacitive load-based delay element (b) A simple model for the delay element in (a) 56 Figure 4.15: Current steering-based resolution adjustment block 58 Figure 5.1: Oscillator debug and design flowchart 61 Figure 5.2: PeriodQuality plot of the initial oscillator circuit 62 Figure 5.3: Illustration of start-up transient 63 Figure 5.4: Bias voltages, VIB2, VIB12, and VIBO to the CML gates at the time of oscillator start-up : 65 Figure 5.5: Oscillator output 66 Figure 5.6: Bias voltage of a single buffer at the time of oscillator start-up 67 Figure 5.7: PeriodQuality plots from two different oscillator configurations 68 Figure 5.9: Illustrations of (a) start-up transient and (b) switching transient in Fig. 5.8.. 71 Figure 5.10: Plot oi PeriodQuality with NMOS load-based delay element for tuning.... 72 ) IX Figure 5.11: Plot of PeriodQuality'with parallel-plate capacitor load-based delay element for tuning 73 Figure 5.12: Delay element-based resolution adjustment block 75 Figure 5.13: Plot of PeriodQuality of modified oscillator with NMOS load-based delay element and with PMOS discharging transistors 77 Figure 5.14: Plot of PeriodQuality of modified oscillator with parallel-plate capacitor load-based delay element and with PMOS discharging transistors 78 Figure 6.2: Input Gaussian test time interval with a mean of Td and a of 2ps 85 Figure 6.3: (a) Measured Td versus test Tj measured from TDC (b) Corresponding error in the measured mean output Td from the TDC 86 Figure 6.4: Number of coarse and fine measurement cycles 87 Figure 6.5: Plot of period difference versus total measurement cycles from the TDC using the original oscillator for a (a) Td of 800ps and (b) Td of 515ps 90 Figure 6.6: (a) Input Gaussian test Td (b) Corresponding measured output r^from the TDC 91 Figure 6.7: (a) Measured Td versus test Td measured from TDC (b) Corresponding error in the measured mean output Td from the TDC 93 Figure 6.8: Period difference versus total measurement using the modified oscillator for a 7^of515ps .-.94 Figure A. l : Measured output Td histograms from the TDC using the original oscillator corresponding to an input Td with histogram as shown in (a) 106 Figure AAcont: Measured output Td histograms from the TDC using the original oscillator corresponding to an input Td with histogram as shown in (a) 107 Figure A.2: Measured output Tj histograms from the TDC using the modified oscillator corresponding to an input Td with histogram as shown in (a) 108 Figure A.lcont: Measured output Td histograms from the TDC using the modified oscillator corresponding to an input Td with histogram as shown in (a) 109 Figure A.3: Measured output Td histograms from the TDC using the modified oscillator corresponding to an input Td with histogram as shown in (a) 110 Figure A.3cont: Measured output Tj histograms from the TDC using the modified oscillator corresponding to an input Td with histogram as shown in (a) I l l Figure A.4: Current steering-based resolution adjustment block 112 Figure A5: Delay element based on (a) NMOS load (b) Capacitive load , 112 Figure A.6: Oscillator schematic 113 xi Acknowledgements This work spanned just over two years during which many people have, directly or indirectly, contributed to my life and research work. Among them, some were there for the academic support and advice and some were there for moral support. This part of my work allows me an opportunity to express my thanks and gratitude, to them. First of all, I would like to thank my supervisor, Prof. Andre Ivanov, without whose guidance and advice, this work would not have been possible. From the very start of the program, he made sure that he assigns a project that I have interests in and throughout the project he has been there to inspire and motivate me. It made research easier, less stressful and more fun. Next, I would like to thank Sassan Tabatabaei for many of his valuable insights towards this project. His original ideas were seeds that grew to become this thesis. I would like to express my sincere thanks to James Cicalo, Roberto Rosales and Andy Kuo from the System-On-Chip Test lab for the advice and great conversations that we have shared. James' and Roberto's help and valuable comments throughout the work, from circuit designs to making sense of the results obtained, have benefited my work tremendously. Their contributions towards this work are immense. The researchers at the System-On-Chip laboratory have also had a big impact during the course of this work. The social interactions and outings helped take off the stress and pressure that is always present during the course of graduate research work. Most importantly, I would like to thank my late dad for instilling in me a strong sense for higher education, my mom for her constant encouragement and advice of xii patience, my brother, Shopon Mollah, for guiding and motivating me throughout my academic life, and my sisters, Sahana and Shamim for their constant support. Without the guidance, support and help of God Almighty and then my family and friends, I would not have been able to complete this work. xiii Dedication To my loving family xiv Chapter 1 Introduction 1.1 Overview and Motivations With the continual shrinking of device sizes, more and more circuits are integrated on a single die, making System-On- -Chip designs a reality today. At the same time, the advent of SoC presents new challenges. The integration of third party circuit blocks required in implementing a SoC calls for means to diagnose, characterize and test each block accurately. Circuits such as Phase-Locked-Loops (PLLs), Delay-Locked-Loops (DLLs), and high-speed I/O modules are becoming increasingly prominent in SoC platforms. For such circuits, timing measurements and specifications, e.g., jitter and skew in the range of a few picoseconds are common nowadays [1], [2], [3], [4] and [5]. Measuring the timing of such circuits is becoming increasingly critical. Techniques for measuring digital circuit timing specifications including jitter, frequency, skew, timing variations, and delay are comprised into two main categories: amplitude sampling and time domain analysis, [1] and [2]. In amplitude sampling techniques, the signal under test is sampled at a high resolution and the collected samples are analyzed in the time domain or in the frequency domain to extract jitter or phase information respectively. The well-known eye-diagram method [6] uses an oscilloscope to estimate the signal threshold crossings from the collected voltage samples to measure the timing of the signal under test. High-speed ADCs have also been used to estimate jitter using indirect sampling methods [7]. I 1 Frequency domain analysis provides information about a signal's phase or frequency modulation components that relate to the signal timing [8]. In time domain analysis techniques, only signal threshold crossings are detected and used to estimate timing characteristics. One of the time domain analysis measurement approaches is the Time-to-Digital-Converter (TDC). There are many different kinds of TDC architectures that have been discussed previously [7], [9], [10], [11], [10], [13], [14], [15], [16], [17], [18] and [19]. Amongst these, one of the TDCs is based on Vernier oscillators [9]. In this type of TDC, the oscillators play the most important role since the difference in the period of two oscillators is used to quantize a time interval. Time interval to be measured Figure 1.1: Time interval to be measured using TDC For example, in Fig. 1.1, the time interval to be.measured is shown as the time difference between the rising edges of START and STOP events or signals. As mentioned earlier, one of the timing specification to be measured in circuits such as PLLs, DLLs or 2 high peed I/O modules using Vernier oscillator-based TDC is the rms jitter. RMS jitter is defined as follows [1]: where M is the total number of measurement samples, Td(i) is the time interval to be measured for i = 1, M and Td is the average of all the Td(i). In such a test, the total number of measurements, M, for a single time interval could range from 1000 to 10,000 [9]. This means that in a Vernier oscillator-based TDC technique, the two oscillators have to be started and stopped M times for a complete measurement. As such, the behavior of an oscillator when it is started and stopped becomes very important and plays a vital role in the performance of the TDC. As will be shown in Chapter 3, an oscillator will have period variations when it is started that must be left to settle before pursuing with the measurements. Thus reducing period transients of the oscillators reduces the measurement time for each time interval and so the overall test time. The period jitter in the ring oscillator also plays a vital role in the performance of the Vernier oscillator-based TDC. As will be explained in detail in Chapter 2, a TDC can measure a time interval using two approaches: single-shot resolution technique and double resolution technique. In a double resolution the two oscillators are started with a relatively big period difference and at some point of time, the period difference is switched to a finer resolution. As such, the transient behavior of the oscillators when their resolution is switched also plays an important role in the TDC performance, which will be shown in (1) 3 Chapter 3. In this project, an improved CML-based ring oscillator that has a short start-up and switching transients, and a very stable steady state period is described This project was motivated by the challenges and shortcomings encountered in a previous TDC design by Vector 12, Corp. in the year of 2003. Amongst the problems found in the TDC were inaccurate calibration results, long measurement times and inaccurate time interval measurements. The goal of this research project was to systematically identify design problems, characterize them and improve the design to f make such a TDC feasible. Since the core of the TDC design is based on two ring oscillators, the first target was to identify the behavior of oscillator non-idealities and study the impact of these non-idealities on the TDC performance. To that end, a new metric called "PeriodQuality " is developed that is used to benchmark the performance of the oscillator stability over a window of time. This metric can be extended to characterize period stability of any oscillator and can also be used to estimate maximum errors induced in TDC measurements due to intrinsic jitter. Equipped with this metric, the shortcomings of the previous oscillator could be identified and an improved oscillator was designed. The major problems identified were the large period variations when the oscillator is started (start-up transient) and when it is switched from one resolution to the other (switching transient) and the smaller but continuous period variations due to accumulation of intrinsic jitter. These problems are discussed in Chapter 5. Also shown in Chapter 5 is a new way of switching the oscillator from one resolution to the other to reduce the effects of switching transient. A system level simulation of an entire Vernier oscillator-based TDC that uses the modified oscillator was also performed. The results show that the total time required for an accurate time interval measurement is greatly 4 reduced with the modified design. Results predict that a measurement can be completed within ten clock cycles. The accuracy of the measurement is also increased, with the error bound by the quantization error defined by the fine period resolution of the oscillator. 1.2 Thesis Organization This thesis is organized as follows: Chapter 2 presents some background on different types of TDCs. Emphasis is put on Vernier oscillator based TDCs to show their advantages over other TDC architectures. Chapter 3 discusses the study and characterization of the impact of various ring oscillator non-idealities when such an oscillator is used in a Vernier oscillator-based TDC. Specifically, the impact on the TDC measurement time and accuracy due to start-up and switching transients, period jitter and quantization error are presented. The chapter concludes with a proposal of a unified quality metric that could be used to benchmark a ring oscillator that is used in a TDC. Chapter 4 discusses the overall ring oscillator design. This chapter briefly discusses the rationales for using the ring architecture in the oscillator and also explains the reasons and advantages of using Current-Mode-Logic (CML) for implementing the different gates that constitute up the oscillator. Basic components of the oscillator architecture such as the buffer, AND gate and tuning mechanism blocks are also explained. These blocks are designed and simulated using CMOS 0.18pm technology. Chapter 5 presents the methodology of the design procedure and the analysis of the results obtained from the oscillator. In Chapter 6, designs and results from Chapters 4 and 5 are used to implement a Vernier oscillator-based TDC. The control logics were implemented using VerilogA/SpectreHDL behavioral models. This demonstrates the impact of the oscillator 5 design on the TDC measurement accuracy and time. Finally, Chapter 7 provides a summary of this work and potential future work related to this project. 6 Chapter 2 Time-to-Digital Converter (TDC) Background 2.1 Different TDC Architectures A TDC measures a time interval Td and quantizes it to produce a digital number. There are several ways of implementing a TDC. The following sections briefly describe different TDC architectures and their capabilities. 2.1.1 Counter-based TDC A classic method of measuring a time interval Td is to use a counter [19]. The counter is started at the beginning of the time interval to be measured and stopped at the end of the interval. The resulting number in the counter is proportional to Td. The resolution of this method is the period of the clock that is running the counter. This technique is often used for frequency measurement but cannot provide high resolution for measuring short time intervals. With today's chips running at high frequencies, in the order of GHz, the resolution of the timing measurement parameters is becoming smaller and smaller in the range of picoseconds. For example, using such a counter based TDC to measure a time interval of lOps would require a clock running at a frequency of 100GHz! This can be explained with the help of Fig. 2.1. 7 A B I I r i i M 7r • Counter 1 i Clock • ! ' ^clock ' Figure 2.1: Using a counter to quantize a time interval In the figure, Td signifies a time interval to be quantized between event A and B. The minimum count using a counter-based TDC to complete the measurement is one. As such, the minimum period, Tciock, of the clock running the counter has to be equal to Td. For a Td of 1 Ops, this means the counter clock should have a frequency of = = \00GHz Tclock 10/w 2.1.2 Delay Chain In the delay chain technique, a time difference, Td, between the start and stop events is quantized by a chain of delay elements. The delay elements are implemented using gate delays. In [17], a TDC based on the use of delay chain is presented. Fig. 2.2 shows conceptually how the delay chain method works. Chain of Delay Elements START• STOP DE3>-D1 ^ 7 " o 7; D2 Recording flip-flops 0 D D ro DN V 0 0 7; 0 o To Period and Jitter Measurement Figure 2.2: Using a delay chain to quantize a time interval As shown in Fig. 2.2, the circuit contains a chain of delay elements. As the START signal rising edge travels through the delay elements, their outputs are set HIGH. When the rising edge of the STOP signal arrives at the CLK input of the flip-flops, only the ones with a HIGH logic value on their D-inputs will have their outputs set HIGH. The final settings of the flip-flops correspond to a snap shot of the outputs of the delay chain at the time of the STOP rising edge. Therefore, the number of flip-flops, which have their outputs, set to HIGH indicates the number of delay elements that the START edge traveled through before the STOP edge arrived. Let this number of delay elements be N. Therefore, T = T —T 1d  1STOP  1 START ^) ^Td=NxTA+Tc where TA is the delay of each delay element and 7c is a constant offset that consists of a delay due to the set-up time of the flip flops and any difference in delay in the signal paths of START and STOP to the chain of delay elements or gates and the flip-flops that are recoding the delays. The resolution in this type of technique is one gate delay, which is insufficient for timing measurements, such as jitter estimation, in the order of picoseconds. For example, the typical gate delay in 0.18um CMOS technology is 50ps. Therefore, this technique is not useful for measuring timing in the order of ten picoseconds. Moreover, the calibration of the delay elements to a known delay, TA, for this technique requires the use of DLLs, which require good matching between all the delay elements in both the DLL and the delay chain [17]. This is difficult to achieve considering process variations. Also, as the time interval, Tj, to be measured becomes longer, more elements have to be added to the delay chains making it more difficult to match the delays in the chain. In addition, the routing delays have to be accounted for as well. 10 2.1.3 Vernier Delay Method The Vernier delay technique uses the difference in delays between two delay elements to quantize a time interval Td. In [18], the authors describe a differential delay technique using two delay chains. Fig. 2.3 shows the concept behind this idea. START STOP r T i k To time interval and Jitter Measurement Time interval to be measured Figure 2.3: Using differential delay chains to quantize a time interval 11 One of the delay chains is composed of buffers each with a delay of lb, and the other chain is composed of latches each with a delay of rj. A delay cell is composed of two delay elements, a latch Lt having a delay of T\ between its input D and output Qh and a non-inverting buffer Bt having a delay of < IY The START signal, signifying the start of the interval, is connected to the input Di of the first latch L; and the STOP signal, signifying the end of the time interval to be measured, is connected to the input B; of the first buffer. The latch Lt in the START chain samples the data at the input D, at the rising edge of the signal from the output of the buffer Bt. Since the output from Bt is delayed from the signal at the input A , the output Qi will be a HIGH. Since r"b < ri, the output signals from the buffers, B,, slowly approaches the input D, of the latches. At some some value i = A7, the output from the buffer Bt is ahead of the signal at the input of latch Lt and the latch £, samples a LOW logic level. The minimum resolution of this technique is the difference between the delays of the two delay elements of the delay chains: Hence the time interval between the START and STOP edges are calculated according to: Although this technique provides a better resolution, the matching requirements for the delay elements make implementing it impractical [9]. (3) Td=NxTA -Td=Nx(T,-Tb) (4) 12 ( 2.1.4 Ramp and ADC Method This technique generates a voltage ramp, for example by charging a capacitor from a current source, for a period of time determined by a start and a stop event [7]. The final voltage on the capacitor is proportional to the time difference between the start and stop events. This method often requires implementing a high resolution ADC to digitize the voltage on the capacitor and as such it is difficult to implement. 2.1.5 Vernier Oscillator-based TDC The Vernier oscillator-based technique uses two oscillators, OscA and OscB, and their difference in periods, T&, to quantize a time interval Tj [9]. Fig. 2.4 shows the principle of its operation. F i g u r e 2.4: Double oscillator based single resolution V e r n i e r T D C showing rth edges in oscillators A and B drawing closer after each cycle 13 The time interval to be measured is the time difference between the rising edges of the START and STOP signals. OscA and OscB start oscillating on the rising edges of the START and STOP edges, respectively. A counter that is connected to OscB starts counting on the rising edge of STOP signal. Typically the two oscillators' periods differ by 2% to 10% [1]. Asuming Td is larger than TA, as time progresses, the z'th rising edges of the oscillators move closer and closer by TA in each successive cycle until they coincide at some value of i = N. This event is called the coincidence event and at this time, both the oscillators stop. At this point of time, the value of the counter is preserved and the counter stops counting. The value N in the counter indicates the value of the time interval Td. The resolution of this technique is determined by the period difference of the two oscillators TA. Since the measurements are based upon the coincidence at the edges of the two oscillators, the output of the oscillators function together as a Vernier scale. This is where the name Vernier-oscillator based TDC came. The following equation shows the relationship of Td with N and TA: TH=NxT (5) =>Nx(TA-TB) where Td is the time interval between the START and STOP edges, N is the number of OscB cycles needed for coincidence to occur and TA and TB are the periods of OscA and OscB, respectively. This method of measuring a time interval with only one resolution, TA, is called single-shot TDC measurement. 14 The measurement time is given by: TMEAS=NxTB (6) To have better accuracy in the measurement of Td and reduce the measurement time, a double resolution method is used. Fig. 2.5 shows the principle of its operation. I f Resolution • i Figure 2.5: Double oscillator based double resolution Vernier TDC showing fth edges in oscillators/I and B drawing closer after each cycle [1] In the double resolution method, the two oscillators periods initially differ by 2% to 10%. This represents the coarse resolution of operation. Some time before coincidence occurs, one of the two oscillators' period switches such that the difference in their periods is between 0.1% and 0.5%. This represents the fine resolution of operation of the TDC. In this case, OscB is connected to two counters: coarse counter that counts the number of OscB cycles (Nc) from STOP event to the point of switching from coarse resolution to 15 fine resolution and fine counter that counts the number of OscB cycles (iv» from switching to fine resolution to the point of coincidence. At the end of each measurement, the TDC generates two digital numbers, Nc and NF- The new equation to calculate Td then becomes [1]: Td=(NcxTAC) + (NFxTAF) (7) where Td is the time interval between the START and STOP edges, Nc is the number of OscB cycles during, coarse resolution operation, NF is the number of OscB cycles during fine resolution operation, and T&c and TAF are the difference in the periods of OscA and OscB during coarse and fine resolutions respectively. The resolution in this case is the difference in periods of oscillators OscA and OscB during fine resolution of operation, TAF-The amount of time required for a measurement to complete depends upon the value of Td. Let TMEAS be the measurement time needed for a time interval Td. The total number of OscB cycles required to perform the measurement would then be equal to N = Nc + NF. Therefore, the required measurement time is calculated as follows [1]: TMEAS=(Nc+NF)xTB (8) Comparing equations (6) and (8), we see that with double resolution technique (coarse and fine resolutions), we can have a large period difference at the beginning of the measurement and then switch to a smaller resolution, such that Nc + NF in Eq.(8) is 16 smaller than TV in Eq. (6), thereby greatly reducing the measurement time as compared to using only a single fine resolution technique (fine resolution only). Moreover, a ring oscillator accumulates noise due to jitter accumulation. The "accumulative jitter" increases with measurement intervals. The longer the oscillator is allowed to run, the higher is the accumulation of noise into the measurement [31]. Hence, speeding up the measurement time improves the accuracy of the measurement by reducing the accumulated noise from the ring oscillator. The Vernier oscillator method of implementing a TDC is very interesting since a resolution ideal for picosecond timing or picosecond jitter measurement can be achieved with a good oscillator design [19]. The smaller the difference in the period of the two oscillators, the higher is the resolution of the TDC. A Vernier TDC based on ring b oscillators provides fast measurement time and easy integration with other on-chip components. The reasons for using a ring oscillator for this work will be explained in more detail in Chapter 4. Chapter 3 discusses the impact of oscillator non-idealities in the design of Vernier oscillator-based TDC. 17 Chapter 3 Impact of Oscillator Non-idealities on T D C Design 3.1 Sources of Error The oscillators in a Vernier-oscillator based TDC play an important role in terms of the TDC's functionality and robustness. As mentioned earlier, with a high resolution oscillator design, timing measurements in the order of picoseconds is possible. However, an oscillator suffers from many non-idealities that can have destructive effects on its performance. Let us consider the output voltage of an oscillator at any time, t, to be Vout(t). Let us also consider the time instant of the nth positive rising edge (transition from VLOW to VHIGH in Fig. 3.1) of Vout(t) as tn. The nth period of the oscillator output is then defined as T„ = t„+i- tn. This is illustrated in Fig. 3.1. V out A " t Figure 3.1: Illustration of period calculation in an ideal oscillator 18 For an ideal oscillator, the nth period, Tn, is independent of n. But in reality, the period varies with n as a result of noise and non-idealities in the oscillator circuit. This results in a deviation in the oscillator period given by: ATn=Tn-T (9) where ATn is the deviation of the nth period, Tn, from the mean period T . The quantity ATn is an indication of jitter. This period deviation, ATn, at the start of oscillation is large and is manifested as the start-up transient. This is discussed in detail in section 3.2. As the time progresses, the deviation becomes progressively smaller and is within a certain range of values from the mean value. This is known as period jitter, which is contributed by oscillator intrinsic jitter and external random noise. This is shown in region 2 of Fig. 3.2 and will be discussed in detail in section 3.3. The effect of this random period jitter is not as destructive since it can be removed by averaging. However, the intrinsic jitter is accumulative in nature [31] and as such has to be compensated for. For the Vernier oscillator-based TDC, the start-up and or switching (when the resolution of the oscillator is changed) transients and the period jitter dictate the accuracy, linearity and the measurement time of the time interval Td to be measured. In equations (5) and (7), it was assumed that the oscillators were ideal and ignored the noise/jitter and non-idealities in the TDC. However, there are error terms that have to be accounted for. The errors arise mainly due to: 19 • Transients of the oscillator during start-up and also during switching from coarse to fine resolution • Variations in the two oscillators' periods, TA and TB, in the form of ring oscillator period jitter • Error due to quantization The next few subsections will discuss the impacts that the above errors have on the functionality of the TDC. Equations will be derived to quantify the effects of the errors due to each term. A unified metric will be defined that would qualify the degrading effects of these errors. This unified metric will be used as a specification or benchmark in the design of an improved ring oscillator and would cover for all the causes of the degrading effects mentioned above. 3.2 Impact of Oscillator Transients When an oscillator is started, it takes time for all the circuit elements to reach their steady state, and this is manifested as variations of the oscillator's period. Fig. 3.2 illustrates transient behavior when an oscillator is started. 20 Period vs Edge Q. 96 95 94 93 92 Region 2: Oscillator jitter Region 1: Oscillator transient 50 100 250 300 350 Figure 3.2: Illustration of start-up transient and per iod jitter of an oscillator 150 200 Edge Number This figure shows a plot of period value versus edge number of a 10MHz signal from a function generator. Approximately 350 cycles of the output waveform were captured after triggering the function generator. As shown in the Fig. 3.2, the plot can be divided into two distinct regions. The first region shows the effect of the period transient during start-up. In region 1, the period varies randomly from about 93ns to Wins from its steady-state value of 100ns. The transient is present for approximately 70 clock cycles before dying out. Region 2 illustrates the variations in the oscillator's period during steady state as jitter that will be explained in more detail in the next section. Fig. 3.3 shows how the transient in region 1 impact the measurement of Td in our TDC. 21 50_ CL Region #2 I I *J Region #1 I Coarse Resolution Point of switching from -Coarse to Fine resolution Fine Resolution • Region #4 I W Region #3 I 10 15 20 25 30 35 40 Measurement Cycles Figure 3.3: Impact of oscillator start-up and switching transient on T D C measurement A plot that is used to qualify a time interval measurement performed by a Vernier oscillator TDC method is that as shown in Fig. 3.3. This plot illustrates the period difference, (Ta-Tbj, of two oscillators in the y-axis, versus the measurement cycles of one of the oscillators in the x-axis. As explained in Chapter 2, a Vernier oscillator-based TDC uses the difference in the periods of two oscillators (TA - TB) to quantize a time interval Td. In a typical double resolution time interval measurement, the two oscillators are first started with a larger period difference (TAC - TBC) representing the coarse resolution of operation and then switched to a smaller period difference (TAF - TBF) representing the fine resolution. When oscillators A and B are started, there will be transient on the periods of both the oscillator outputs. These individual transients on each of the 22 oscillators' period will translate into a transient in the difference in the periods, (TA - TB), of the oscillators as shown in Fig. 3.3 during the first 10 measurement cycles. A similar transient is observed when the period difference between the two oscillators is switched from a coarse to a fine resolution. Thus the difference in the oscillator periods, (TA - TB), is no longer constant for the entire duration of either the coarse or the fine resolution of operation. Equation (7) is valid as long as (TA - TB) is constant. However, as we have just shown in figure 3.2, there is always a transient whenever an oscillator is started and this transient introduces a transient on (TA - TB) as shown in Fig. 3.3. To do a time interval measurement or a jitter measurement with good accuracy and with reduced errors due to random noise, the same measurement is repeated multiple times (approximately 1000 to 10000 times) and the random noise is reduced through averaging [19]. As shown in Fig. 3.3, if the coarse or fine measurement is always completed outside the transient regions of 1 and 3 respectively, the error due to the transient behavior of (TA - TB) shows up as a constant offset term for any time interval measurement. Eq. (10) is a modification of equation (7) incorporating the constant offset term: Td=(NcxTAC) + (NFxTAF) + ^OFFSET  V (10) where TOFFSET is the constant offset error term. This offset can be cancelled with multiple measurements done during TDC calibration prior to a time interval measurement. However, if either the coarse or fine measurement stops inside the transient regions of 1 and 3, the errors due to the transients are no longer constant. Therefore, repeated 23 measurements of the same time interval will contain non-linear error terms in the measurement equation. This error will be different for repeated measurements of the same Td. This shows that to minimize the error in our measurement when using an oscillator with a large start-up transient, we have to wait long enough for the transient to die out so that the measurement is completed in the non-transient region of Fig. 3.3. This amounts to a longer measurement time. As will be explained shortly, a longer measurement time means a higher number of clock cycles to complete a measurement, which will cause more accumulation of noise or jitter in the measurement result. The impact of accumulated noise or jitter will be explained in the next section. To summarize, the effect of oscillator start-up and switching transients is such that it introduces non-linearity in the measurement result. 3.3 Impact of Variations in TA and TB The plot of Fig. 3.4 below shows the zoomed-in version of region 2 in Fig. 3.2. It shows the variations in an oscillator period in the steady state. The period variations are random in this region and independent from the previous or subsequent cycles. The variations are also small (0.5ns peak-to-peak) as compared to those of region 1. 24 Period vs Edge 100.3 100.2 _ 100.1 1 100 a. 99.9 99.8 99 7 100 150 200 250 300 Edge Number Figure 3.4: Zoomed-in plot of Fig. 3.2 showing the period variations of region 2 The variations in Fig. 3.4 are due to the oscillator intrinsic jitter and/or any external noise. A ring oscillator in general accumulates jitter over successive cycles [31]. The longer the measurement time, the greater is the jitter accumulation. This is known as accumulated jitter. As shown in the Fig. 3.5 (a) below, an ideal oscillator has an output whose period, T , is constant for all cycles. 25 Ideal Oscillator Output (a) r I rp I I 1 I Real Oscillator Output jf+A7;! f + Ar2 j f+Ar3 — • ! T + AT I PeriodJitter, CUMULATIVE = ATl+AT2+ATi + ATn (b) Figure 3.5: Illustration of period jitter However, in reality, as explained earlier, the output of an oscillator will have a period that varies with deviation, AT„, that is independent from the deviation of previous or subsequent cycles, and this is shown in subplot (b) of Fig. 3.5. The total or cumulative period jitter on the signal is then given by: PeriodJitterCUMULATIVE - AT, + AT2 + AT3 + ATn ^ ^ As such, when using ring oscillators in the Vernier oscillator-based TDC, the output signals from OscA and OscB include some jitter. Thus the ith instantaneous period, 7}^ taking into account the period jitter of an oscillator, can then be expressed as: 26 T -T+AT (12) where T is the average or mean period in the steady state and AT(J) is the rth period jitter. Similarly, we can express the z'th instantaneous periods of oscillators A and B as TA(Q = TA + A TA(I) and Tg(i) = TB + A TB(I) respectively. In a measurement sample, the TDC stops after N cycles of OscA and OscB. Assuming the jitter in each cycle is independent of the jitter in any other cycle, the effect of jitter or variations in TA or TB on the Td measurement can be expressed as: T(L=(NcxTAC) + (NFxTAF) + ^OFFSET TD={Ncx{TAC-TBC)}+{NFx(TAF-TBF)} + TOFFSET = {Ncx(TAC-TBC)}+{NFX(TAF-TBF)}+TOFFSET (13) + Z \ ATAC(i) ~  ATBC(» J+Z \ A T A F U ) ~  ATBFU) ) ;=i j=\ j where TAC and TBC are the periods of oscillators A and B respectively during coarse resolution, TAF and TBF are the periods of oscillators A and B respectively during fine resolution, TAC and TBC are the average periods of oscillators A and B respectively during coarse resolution, TAF and TBF are the average or mean periods of oscillators A and B respectively during fine resolution, ATAC(I) and ATBC a) are the period jitter during coarse resolution in cycle (i) of oscillators A and B respectively, ATAF(J) a n d ATBF(J) are the period jitter during fine resolution in cycle (j) of oscillators A and B respectively, and 27 TOFFSET is the constant error term due to the transients of both the coarse and fine resolution. Therefore, the measurement error due to jitter in the oscillators is: TerrorJlller = E(Ar<C(,, - ATBC(i))^{ATAFU) -ATBF(j)) (14) From the above equation, it is seen that as the number of clock cycles (Nc and 7V>) for a measurement increases, so does the error due to period jitter that accumulates over the number of cycles. If this jitter is due to random noise sources, then it could be averaged out from multiple measurements. However, if it is oscillator intrinsic jitter, then the jitter accumulates with time. This growth in the accumulation of jitter occurs because any uncertainty in the transitions in the previous clock cycle affects the subsequent transitions and its effects persist indefinitely [31]. For this reason, it is important that the measurement time be reduced and that the oscillators have very low period jitter. 3.4 Error due to Quantization An additional error called "Quantization Error" occurs during coincidence detection. The coincidence does not always occur when the edges are exactly aligned. The coincidence detector is implemented using a D flip-flop that samples OscB as its D-input and OscA as the elk input. OscB thus has to be HIGH before OscA by an amount equal to the set-up time of the flip-flop for the D flip-flop to sample logic HIGH marking the coincidence event. Assuming the set-up time for this D-Flip-Flop is constant for multiple Td measurements, this set-up time can be removed through calibration. Depending on the difference of the two oscillator edges one clock cycle before the 28 coincidence event, the error due to quantization will vary. In double resolution TDC measurement, the quantization error, TQ, is bound by the fine resolution, T^F- The range of TQ is given by [9]: o<r e <7^' (15) So, the final equation to calculate Td incorporating all the error terms is given by: (16) Td = (NC x T A C ) + (NF xTAF) + T0FFSET + TQ Td = {Ncx{TAC-TBC)}+{NFx{TAF-TBF)} + TOFFSET +TQ = K x fcc ~ TBC )}+ {NF x (TAF - TBF )}+ TOFFSET + TQ i=\ 7=1 3.5 Stability Metric A stability quality metric called "PeriodQuality" is defined such that it can be used to benchmark the performance of an oscillator against the degrading effects of start-up and switching transients, and period jitter. The following definitions will help to understand the metric. Stable Period: "Stable Period" is defined as the oscillator steady-state period that, for practical purposes, is calculated by taking the average of the oscillator periods from the 41s' to the 80th clock cycles from the start of oscillation. The average is taken starting from the 41st cycle in order to avoid including any transients. As explained earlier, when 29 an oscillator is started, the variation in the period of oscillation is significant in the first few cycles. In our ring oscillator design, the variation becomes insignificant after the 20 cycle and so it is safe to assume that the period reaches steady state after the 40th cycle. A stable value of the period is obtained by taking the average from the 41s' to 80th cycle. Fig. 3.6 shows a plot of normalized period versus edge of the ring oscillator designed. It is seen that the period becomes very stable after approximately 20 edges or clock cycles. 1.01 1.008 1 1.006 -D_ T3 <L> N m 1 004-E | | | | ; i | 0 20 40 60 80 100 Edge Figure 3.6: Illustration of Stable Period PeriodQuality Window: A window that spans 10 clock cycles, as shown in Fig. 3.7. A PeriodQuality Window with a value of one (#1) means a window spanning from clock edge #0 to edge #10 incorporating 10 periods of the clock; a PeriodQualityWindow 30 with a value two (#2) means a window spanning from clock edge #1 to edge #11 and so on. PeriodQualityWindow #1 PeriodQualityWindow #2 PeriodQualityWindow #3 X 2 3 4 5 6 7 8 9 10 11 12 Figure 3.7: Illustration of PeriodQualityWindow definition PeriodQuality: Metric for quantifying the cumulative variation of the oscillator period over a PeriodQualityWindow, beginning from its "Stable Period\ Mathematically, PeriodQuality of the Nth. PeriodQualityWindow is expressed as follows: N+9 _ where N = PeriodQualityWindow number, Th) is the ith period of the clock and T is the "Stable Period'' of the clock. In other words, PeriodQuality is a measure of the 31 cumulative period variations or cycle jitter of an oscillator over a 70-clock cycle window. From Eq. (17), it is seen that one has to wait at least N+9 clock cycles to compute or measure PeriodQuality of a PeriodQuality'Window with a value of N. This means that the PeriodQuality measurement is a non-causal process where one has to wait for certain clock cycles (N+9) in order to compute a measurement result. For high-speed signals, the time intervals to be measured are very short. Using a double resolution TDC, these short time intervals can be measured with fewer clock cycles. However, as shown in Fig. 3.3, if the oscillator transients are long and not compensated for, a short time interval measurement with a small number of clock cycles would cause the measurement to be completed in the transient region. This introduces error in the measurement. In order to reduce the error, one way to complete a short time interval measurement is to ensure that coincidence occurs outside of the transient regions, shown in Fig. 3.3. This requires the TDC to run the two oscillators with a very fine or small period difference such that by the time the oscillators coincide, the transients of the oscillators would have died down or become negligible. As explained in [9], for timing measurements, a single time interval is measured 1000 to 10,000 times to average out random noise and also to estimate rms jitter. A long test time for a single measurement would dramatically increase the overall measurement time. For a short time interval measurement to complete with a fast test/measurement time, the transients need to be very short so that the coincidence occurs outside the transient regions. In order to be able to complete a measurement quickly and with good accuracy, one has to ensure that the transient during the coarse resolution of operation die down before the TDC switches from coarse to fine resolution and also that the transient at the point of switching dies 32 down before the coincidence event signifying the end of the measurement. To speed up picoseconds time interval measurements, one would ideally like to complete a measurement within 20 clock cycles, 10 clock cycles in the coarse resolution and 10 clock cycles in the fine resolution. This means that the start-up transient of an oscillator has to settle down to an acceptable steady state in less than 10 clock cycles. It also requires the oscillator switching transient to die down and settle to an acceptable steady-state in less than 10 clock cycles after the oscillator is switched from coarse to fine resolution. As the number of measurement cycles increases, so does the error due to period jitter. The error in TDC measurements due to jitter for Nc cycles of coarse and NF cycles of fine measurements is given by Eq. (14). The goal of this project is to complete a time interval measurement in 20 clock cycles with Nc = 10 and Nf = 10. The target is to design an oscillator such that the maximum cumulative jitter over ten cycles is within +/-2ps. That is, the PeriodQuality of a single oscillator be within +/-2ps for all values of the oscillator PeriodQuality Window. A Vernier oscillator-based TDC uses the period difference of two oscillators to quantize a time interval. Assuming the worst-case performance, each of the oscillators would then have a cumulative error of +/-2ps in its period calculation for a 70-cycle window. Therefore the maximum worst-case cumulative error of (TA-TB) would be +/-4ps for Nc = 10 in coarse region and another +/-4ps for Np = 10 in fine region of operation. This would introduce a maximum worst-case error of +/-8ps in any time interval measurement due to oscillator period jitter for a measurement that takes a total of twenty clock cycles to complete. This figure can be extended to find the maximum error in any time interval measurement that takes a different total number 33 of measurement cycles to complete. The cumulative error results obtained from the oscillator are presented in Chapter 5 where they are discussed in detail. 34 Chapter 4 C M L Differential Ring Oscillator Design 4.1 Introduction Due to its ease of integration and agile frequency tunability, ring oscillators are used for the Vernier oscillator-based TDC design. The oscillators were designed using Current Mode Logic (CML). The CML logic style was chosen for many of its advantageous properties. The oscillator is implemented in fully differential mode. The next few sections will discuss some background theory of ring oscillators, a brief background on CML logic style and the rationales of using it in the design, the overall oscillator architecture, and detailed explanations of each of the component blocks of the ring oscillator architecture and its tuning mechanisms. 4.2 Ring Oscillator Theory In general, ring oscillators consists of multiple delay cells that are connected in cascade and in a closed loop. This configuration has to satisfy the Barkhausen's oscillation criteria with certain phase shift and gain [32]. The criteria states that: the steady oscillation in a ring oscillator requires a total phase shift of 360° around the closed loop at a frequency where the small-signal gain is equal to 0 dB or 1. Fig. 4.1 below shows the basic structure of a ring oscillator. 35 Figure 4.1: Single-ended r i n g oscillator structure The corresponding small-signal model of the architecture, modeled as a transconductance, Gm, and RC circuit, is shown in Fig. 4.2 [31]. Figure 4.2: Smal l signal single-ended equivalent for the r i n g of F i g . 4.1 The frequency of operation of the above ring oscillator is given by: 1 2xN xzA (18) 36 where JV is the number of stages or delay cells in the ring structure and id is the delay through each delay cell. From the above equation, it can be seen that the frequency of the oscillator can be controlled in two ways: changing the number of stages or delay cells and through changing the delay through the delay cells. There is a limit up to which 7Y can be reduced. For small N, due to insufficient gain and phase shift, the Barkhausen's oscillation criteria is not met and as such the design ceases to sustain steady oscillation [31]. For single-ended architecture, placing an odd number of inverters or inverting amplifiers in a feedback-loop realizes a ring oscillator. With fully differential architectures, an even number of inverters can be used and the inversion required around the loop is achieved by cross-connecting the outputs of one of the inverters. This is shown in Fig. 4.3 below. v F i g u r e 4.3: Double-ended r ing oscillator structure In Fig. 4.3, the non-bubble input/output represents a true node while a bubble represents the complement of a true node. Also, shown in Fig. 4.3 is the positive output of buffer 4 that is connected in a feedback loop to the negative input of buffer 1 and the 37 negative output of buffer 4 that is connected to the positive input of buffer 1 to realize the signal inversion. Ring oscillators are crucial building blocks that are used in many integrated circuits such as clock recovery, on chip clocks and frequency synthesizers. The performance of a ring oscillator, however, is prone to noise. This in turn limits the performance of the system in which they are used. The on chip oscillators suffer from intrinsic device noise as well as from interference that is coupled onto the power supply lines and into the substrate from the digital switching of blocks on the same chip. In general, noise sources can be categorized into two broad types: (1) random signals such as device, thermal, shot and flicker noise that are stochastic in nature and (2) deterministic signals such as supply variations and substrate coupling, electromagnetic or direct coupling of power lines [33]. These noise and interference manifest themselves as timing jitter at the output of the oscillators. Depending on the applications, the contribution of each of these noise sources to jitter varies. The contribution of device noise to jitter is typically much less than that due to power supply and substrate noise [34]. However, in our intended application, that of a Vernier oscillator-based TDC, we explained in Chapter 3 that the intrinsic random period jitter plays a significant role in the final measurement results. Both single-ended and differential ring architectures are used depending on specific applications. Single-ended ring oscillators have better performance in terms of phase noise [31]. However, the differential implementation has some advantages over the single-ended counterpart. First, differential ring oscillators have high common mode rejection characteristics that decrease the sensitivity of the ring oscillator to the common 38 mode noise and the power supply and substrate distortions. Secondly, differential architectures can operate at higher frequency or speed than single-ended architectures. For these reasons, a differential topology is preferred in ICs with a large amount of digital circuitry because of the lower sensitivity to power and substrate noise, as well as lower noise injection into other circuits on the same chip. 4.2 CML Background The rapid growth of portable electronic devices caused development of integrated circuits (ICs) with high integration density, low power, high speed and low cost. Most of these requirements can be achieved by improving the process technology such as shrinking the device size for high speed and high density ICs. However, low power and other features such as noise immunity require new circuit design techniques. Also the advent of system on chip means that more and more ICs are designed where mixed-signal, analog as well as digital, blocks are present on the same die. The digital blocks on the same die as analog blocks can cause massive switching noise and to prevent such a hostile environment to the analog blocks, a new logic style has to be used. Current Mode Logic (CML) implemented in MOS technology shows promise in both reducing power consumption and providing analog friendly environment [20]. It is becoming one of the most widely used logic styles for high-speed digital circuits. This type of logic style was first implemented using bipolar transistor but the CMOS implementations became attractive as the technology advanced and the feature size started to scale down! Its high-speed switching and reduced voltage swing makes it a high performance logic style to be used in different circuit implementations [20]. The following presents a general idea of 39 how the CML logic style that we implemented works. This will give a good understanding on the issues involved in designing circuits with CML gates. The ideal CML gate is presented in Fig. 4.4 [20] below. It consists of three main parts: the pull up resistors, the pull down network and the current source. V D D GND Figure 4.4: Concept of a basic C M L gate As shown in Fig. 4.4, the gate is fully differential with the true and complement of all logic inputs to be presented at the gate and output taken differentially. The principle of operation of any CML gates is based on the current steering. The current IBIAS produced by the current source is steered by the pull down network into one of the branches of the 4 0 gate through one of the pull-up resistors depending on the voltages at the inputs. Thus the value of the input controls the current flow through the two branches. The amount of current passing through the branch that is ON, controls the delay of the gate during discharge from a logic "1" to logic "0" (1 —> 0 transition). On the other hand, the load resistor controls the charging of the output nodes from a logic "0" to logic "1" (0 --> 1 transition). The resistor that is connected to the current source through the pull down network will have the entire current IBIAS from the current source and a voltage drop equal to AV = / x R and so the output at the node OUT will take the value equal to VDD - AV. The other resistor will have zero current flowing through it and so the output OUTBAR connected to it will be pulled up to VDD- S O the outputs will take either the value of VDD or VDD - A V. The output voltage swing, A V, is dependent on the value of IBIAS and one of the pull up resistors R, and is in the order of few hundred millivolts. This small output swing has an advantage of reducing cross talks between adjacent signals as well as makes the gate to switch faster. The almost near constant current consumption reduces the switching noise and power supply variations. This is because if the current is constant, there is negligible dl/dt effect and so the CML gates are more suited for mixed-signals environments to reduce interference between the digital and analog blocks on the same chip than gates using CMOS logic style. The differential nature of the CML gates makes it very robust against power supply noise due to its common mode rejection. The NMOS transistors only implementation of the gate also means that circuits with CML logics are faster than circuits implemented with other logic families [20], [21], [22], [23] and [24]. There are a few disadvantages of the CML gates. CML gates dissipate static power, which is independent of its operating frequency. The constant current source at 41 the bottom of the gate that is biasing the gate causes it to dissipate a constant static power given by ( As such, compared to CMOS circuits, CML circuits consume more power at lower frequencies than their CMOS counterparts. However, at higher frequencies, the dynamic power in CMOS circuits become much more than the power consumed by CML based circuits. Therefore, CML logic is suitable and advantageous for circuits running at high frequencies and preferred for high frequency applications in order to reduce the overhead of its static biasing power consumption. The large load resistors in CML gates require special fabrication techniques to implement them in a reasonable area. This in turn increases the cost and area to implement a chip. Also, the chip would require a voltage reference to control the current source of each gate leading to larger chip area [20], [22] and [23]. 4.3 Overall Ring Oscillator Architecture Fig. 4.5 below shows the overall oscillator architecture under consideration. The initial circuit was obtained from VI2 Corp. Later on in this work, as will be discussed in Chapter 5, some modifications were done to the architecture to improve the performance of the oscillator according to our specifications. 42 RESET TRIG To Coarse adjustment controller 4= 4= . J z x _ L r d L,— Coarse resolution adjustment blocks -OSC OUT Figure 4.S: Overall ring oscillator architecture All the gates are implemented using differential CML logic. The oscillator consists of nine buffers and two AND gates. The first leftmost AND gate acts as a RESET switch for the oscillator. When the output of this gate is HIGH, the oscillator starts oscillating when TRIG is HIGH In TDC application, the TRIG signal is either the START or STOP signal corresponding to the start and stop of the time interval to be measured. As mentioned earlier, because of its ease of integration with other components on-chip and wide tuning capability, ring oscillators are used in Vernier oscillator-based TDC. The gates of this oscillator were designed using current mode logic (CML). This choice was due to CML logic's inherent characteristic of reduced power consumption at high frequency and its analog friendly nature. The core of the oscillator is analog in nature but the application (TDC) of these oscillators consists of other digital blocks and so it is important that the analog circuitry not be affected by the digital switching. The near constant current 43 consumption by the biasing circuitry of each CML gates reduces the affect of switching noise by digital circuitries and noise due to power supply variations. The differential architecture was chosen because of its inherent nature of common mode rejection. There are two sets of tuning mechanisms for this ring oscillator. Coarse resolution is achieved through a controlled capacitive coupling technique of the oscillator nodes. Fine-tuning is achieved through changing the bias current to the different gates that make up the oscillator. The next few sub-sections discuss the various component blocks and the tuning mechanism of the oscillator architecture. 4.4 CML Buffer and AND Gate V D D V D D I r> IB[> VBNO M1 M2 C_J_ Cj -O o -O OB M3 Xz Xz u Xz G N D Figure 4.6: C M L Buffer architecture 44 Fig. 4.6 illustrates the CML buffer used in our design. As in a typical CML block, the buffer consists of three main parts: a pull-up network, a pull down network and a current source. In Fig. 4.6, resistors R make up the pull-up network, transistors Ml and M2 realize the pull-down network and M3 acts as the current source. The gate voltage VBN of M3 controls the amount of bias current produced by M3. The true and compliment differential inputs, I and IB, are asserted at the gates of Ml and M2 respectively and the differential outputs, O and OB, are taken from the drains of M2 and Ml across the output capacitors C respectively. Figure 4.7: C M L AND gate architecture 45 Fig. 4.7 shows a 2-input differential AND gate implemented using CML logic [9]. Once a buffer is implemented, other types of gates are easy to implement due to the similarity in gate topologies as can be seen by comparing the two gates in Fig. 4.6 and 4.7. To simulate the functionality of our oscillator, all the component blocks were integrated. The simulation was performed in CMOS 0.18pm technology using the Cadence Spectre simulator. The subsequent sub-sections discuss the methodology and rationales behind choosing the parameters for the different components of the ring oscillator. 4.4.1 Pull-Down Network As mentioned earlier, the pull-down networks of the buffer and the AND gate are implemented with standard NMOS differential pairs controlled by inputs I and IB, A and AB, B and BB for the buffer and AND gate, respectively. The goal of the differential pair transistors is to switch current from one side to the other. For fast current switching, a large W/L ratio for these transistors is preferred since large W/L ratio decreases the ON resistance of the switching transistors. Hence, the lengths, L, of these two current steering switches are kept to the minimum (180nm) for fast switching and the widths, W, were chosen to be large. However, a very large W will introduce a significant capacitance and so increase the gate delay. A width of 8um is used. 46 4.4.2 Current Source The current source is an NMOS device, with a fixed gate voltage, VBN. A single NMOS device was chosen for area efficiency. The transistor has to be kept in the saturation region of operation for the device to behave as a current source. The value of VBN sets the gate-source voltage of the transistor and determines the amount of current flowing in the current source and hence determines the power and speed of the circuit. Whereas a smaller size is good in terms of area, a non-minimum length device is desirable for high output impedance, which is a required characteristic for a current source. The NMOS current source devices used in this project were set to W=15jum and L=ljum. In order to have gates with larger drive strengths, the width of the current source transistor must be increased. To achieve double the drive strength, the width is doubled, to triple the drive strength, the width is increased three times and so on. To keep the same output voltage swing as the drive strength is scaled, the values of the load resistors are reduced accordingly. The methodology of choosing the values of R will be explained in section 4.4.4. 4.4.3 Output Voltage Swing For high-speed circuits, it is desirable to reduce the voltage swing at the output as much as possible to reduce the propagation delay of the gate. Eq. (20) models the propagation delay of a CML gate: DCML KRCCC AVxC bias (20) 47 where DCML is the delay through the CML gate, A V is the voltage change across the load resistor R of each CML gate, C is the output capacitance, and i&/as is the biasing current. Eq. (20) shows that the propagation delay of a CML gate is proportional to the output voltage swing of the gate. In practice, the value of the voltage swing is limited by a reasonable noise safety margin. For this reason, a differential voltage swing of 500m V is used for the proposed circuits. 4.4.4 Pull-Up Resistors The values of the load resistors R were chosen according to the desired voltage drop (A V) across the load resistors and the amount of current passing through them. The following equation shows how this value is achieved: AV=IxR AV (21) R = Now, I is set by the current through the NMOS current source and is ideally given by: u C W ^ = Y X Y X ( ^ ^ ) 2 ( 2 2 ) In this work, I was calculated to be ~70uA. This gives a resistance value of ~7.5KOhms corresponding to a voltage swing of 500mV. Fig. 4.8 and 4.9 show the simulated input and output characteristics of the CML buffer and AND gates respectively. In Fig. 4.8, a square-wave of period 4ns is applied to the differential input I and IB of the buffer. From the graph, we see that the differential 48 outputs, O and OB, are also a square waves with a period of 4ns, thus following the input to the buffer. Fig. 4.9 shows the input output characteristic of the AND gate in the configuration used in this work. In this work, the AND gates are used as switched buffers. As shown in Fig. 4.9, when one of the AND gate inputs, B, is logic HIGH, the positive differential output, O, follows the input A. Here a logic HIGH = 1.8V and logic LOW = 1.3 V. Transient Response 1.8 1.5 1.2 1.8 1.5 1.2 2.0 1.6 1.2 2.0 1.6 1.2 / A o : /B /0 • : /OB -1.0n 3.0n 7.0n 11n time ( s ) 15n 19n Figure 4.9: CML AND gate simulation results showing input and output characteristic 50 > 2.00 v* / O S C - S 1 : O P P 1.70 1.40 > ' 1.30 • 1.90 J 1.60 1.30 1.90 > 1.60 1.30 1,90 * : 1.60 /clkp i ; /clkn 0.0 Transient Response 10n r - 1 n n r~ r U Uu U 20n time ( s ) Figure 4.10: Overall oscillator output before applying any coarse or fine resolution 30n The overall oscillator output once all the blocks of the oscillator are integrated is shown in Fig. 4.10. The plot shows the oscillator output with no coarse or fine-tuning applied. The topmost plot in Fig. 4.10 shows the waveform of the positive differential RESET signal, Oscstopp. Trigp is the positive differential trigger signal of the oscillator. When both Oscstopp and Trigp are equal to logic HIGH, the oscillator starts oscillating. The 51 positive and negative differential outputs from the oscillator are shown as clkp and clkn respectively. 4.5 Tuning Mechanism The oscillation period is controlled by two sets of resolutions - coarse and fine. During the first part of the double-resolution TDC measurement, the oscillators are run with a longer period difference (coarse resolution) and when the edges of the two oscillator outputs are close to within a certain amount, the measurement switches to a shorter period difference (fine resolution). These coarse and fine resolutions can be achieved by two methods. The first method uses delay elements with control voltages [9] at a few nodes in the oscillator. The delay elements provide either a shorter delay or a longer delay depending upon the value of their control signals. The second method uses a current steering circuit to change the resolution by changing the bias current to the CML gates in the ring oscillator. A resolution controller digitally controls the amount of current through eight digitally programmable taps [9]. With the coarse and fine adjustment steps known, a resolution control block in the TDC use a binary search algorithm to select which of the delay elements and control taps to turn ON during the coarse and fine resolution stages of the measurement, given the desired resolution, TA [19]. 52 4.5.1 Delay Elements-based Resolution Mechanism Controllable delay elements can take many various forms [19]. Each delay element can be implemented such that it introduces a controllable delay in the circuit. The controllable delay is implemented to provide different delays by choosing appropriate sizes for the components used in the delay elements. Simulations were performed using four different delay element architectures as shown in Fig. 4.11, 4.12, 4.13 and 4.14. Each delay element basically consists of a switch and a load. Turning on the switch adds the load onto the output of the ring oscillator gate to which it is connected. In designing the delay elements, it is important that the implementation area is kept to a minimum. It is also desirable that the delay introduced is insensitive to the control voltage at the switch otherwise any noise in the control voltage would result in added jitter at the oscillator output. CTRL L> A B O O IT 3H CTRL L> (a) (b) Figure 4.11: (a) Voltage controlled NMOS load-based delay element (b) A simple model for the delay element in (a) 53 Figure 4.11 (a) shows a delay element that consists of NMOS loads. Mp and M N are the switching transistors load corresponding to positive and negative nodes of the differential oscillator node A and B to which the delay element will be connected. Figure 4.11 (b) is the corresponding simple model of the NMOS load. This delay structure is not very robust because the capacitive loading is a strong function of the control voltage CTRL [9]-CTRL O (a) (b) Figure 4.12: (a) NMOS load-based delay element (b) A simple model for the delay element in (a) Figure 4.12 (a) shows a different delay structure. It consists of two NMOS gate capacitors, M L P and M L N , as the load for the positive and negative differential nodes A and B, and two switching transistors, Msp and M S N - Connecting the sources and drains of the two NMOS load transistors makes the load transistors behave like capacitors. Fig. 4.12 (b) shows the corresponding model of (a). Here, only one branch corresponding to the positive differential node A will be explained. Similar explanations are valid for the branch corresponding to the negative differential node B because of circuit symmetry. In Fig. 4.12 (b): 54 CI p — Cgate-source(L) C'gate-drain(L) C2p = Cgate-body (L) C3p — CsourCe-body(L) Cdrain-body(L) Cdrain-body(S) Cdrain-gate(S). The superscript in the bracket identifies the capacitance of the load (L) or switch (S). In this architecture, when Msp is ON, the impedance of C3p is given by [9]: 7 = 2nfC3, »R SP (23) The switch resistance, Rsp, of the transistor is a few kilohms when it is ON and so the impedance, ZCip, of C3p will be much greater than Rsp. As such, if C3p varies due to variations in the control voltage, CTRL, it does not affect the total loading that is provided by Clp and C2p which form the load Q . CTRLL> (a) C T R L D-A O B o PL C1N-Q \RSPS JCIP J 5R I^ 11 H lc2« C1. (b) Figure 4.13: (a) Capacitive load-based delay element (b) A simple model for the delay element in (a) 55 In Fig. 4.13 (a), two capacitors, CLP and CLN, are used as loads with switching transistors, M S P and M S N - hi this type of structure, the parasitic capacitances of the switching transistor load the oscillator when the transistor is witched ON. This can be seen from the equivalent simple model of the delay element. The switch resistance Rsp of the transistor is a few kilohms when it is ON and as such the parasitic capacitances Clp and C2p directly load the node of the oscillator. And since the parasitic capacitances are function of the control voltage [9], the delay is strongly a function of the control voltage. As a general rule of thumb, any switch connected directly to an oscillator node would have these sensitive characteristics. As such, this architecture is not preferred. CTRL L > (a) CTRLD-A O B o -l-C, L N (b) Figure 4.14: (a) An alternative capacitive load-based delay element (b) A simple model for the delay element in (a) Fig. 4.14 is similar to Fig. 4.13 except that the load capacitors are connected to the differential nodes, A and B, of the oscillator. In the equivalent model, shown in Fig. 4.14 (b), the parasitic capacitances that are lumped into Clp of the switching transistor, Msp, are in parallel with the switch resistance Rsp and is given by: 56 Clp Cdrain-body(S) Cdrain-gale(S). The explanations are similar to those for the delay structure in Fig. 4.12. The structures in Fig. 4.14 and 4.12 are the preferred ones since the delay is significantly insensitive to the control voltage [9] in both the cases. In Chapter 5, results of the oscillator performance using these two structures will be shown. Table 4.1 shows the different resolutions that could be achieved using the delay elements. These resolutions could be varied with different sizing of the components in the delay elements. These values changed in the modified ring oscillator. A "1" signifies logic HIGH (1.8V) and a "0" signifies a logic LOW (0V). T A B L E 4.1: C O A R S E T U N I N G Control Switches IrsO Crs! Crs2 Resolution (ps) I.I 0 0 0 1 0 0 8.5 1 1 0 20 1 0 1 90 1 1 1 144 4.5.2 Current Steering-based Resolution Mechanism Variations in period can also be achieved by changing the bias current to the CML gates through changing the voltage at node VBN in Fig. 4.6 and 4.7 for the buffer and AND gates respectively. Changing the biasing of the CML gates changes the propagation delay of each of the gates and hence the overall period of the oscillator. From Eq. (20), we can see that we can vary the delay of each gate in the overall architecture by controlling/changing the biasing current, ij,/as, hence changing the period/frequency of the 57 oscillator. The schematic in Fig. 4.15 illustrates how the change in the bias current of CML gates is achieved [9]. tap3 L>-tap2 L> Current Source II 2s 5 5 5 5 S To VBN tapl L> tapO L> Z^> V B N M1 M6 M7 M8 I' M2 B M3 M9 I' M4 D I" M5 £ fe ^ % • 1% i % vss Figure 4.15: Current steering-based resolution adjustment block The circuit of Fig. 4.15 is a current-steering circuit. The circuit consists of five branches A, B, C, D, and E. Except for branch A, the remaining four branches are each made up of two NMOS transistors. M2 and M6, M3 and M7, M4 and M8, and M5 and M9 make the branches B, C, D and E respectively. Transistor M l in branch A sets up the biasing for the rest of the circuit. This transistor is the heart of this circuit. The gate of this transistor, M l , is connected to its drain thereby forcing it to operate in saturation mode. The gates of transistors M l , M2, M3, M4 and M5 are all connected with each other and so are the sources. As such, transistors M2, M3, M4 and M5 all have the same 58 gate-source voltage, Vcs, as M l . Therefore, when these transistors are operating in saturation, each of these transistors form a current mirror with Ml and their drain current Ii is given by the following equation: (WIL)i (24) I REF (W/L) where IREF is the drain current of Ml and 7, is the drain current of branch i (i = B, C, D or E) and Wand. L are the widths and lengths of the transistors M l , M2 M3 , M4 or M5. Eq. (24) neglects the channel-length modulation, which is valid for large L. Therefore, we can see that the output current, through each of the branches can be controlled through a simple W/L ratio. Transistors M6, M7, M8 and M9 act as switches for the branches B, C, D and E. The input control signals tapO, tap I, tap2 and tap3 "at the gates of M6, M7, M8 and M9 act as the control taps for this circuit. Depending on which of the control taps is logic HIGH, that branch will be on and will sink in drain current according to Eq. (24). This will cause the overall current through node VBN to change and hence the voltage at VBN will change. The voltage at VBN is used to bias some of the CML gates. Thus any change in the voltage at node VBN changes the IBIAS of the CML gates to which it is connected. The change in IBIAS of the CML gate causes a corresponding change in its propagation delay and hence the period of the ring oscillator. The node VBN is set by the output from a current source [9]. The current source has three outputs, VIBO, VIB1 and VIB2, through which it sets the voltage at node VBN. There are two control blocks such as the one shown in Fig. 4.15 that are used for changing the resolution of the oscillator. The Low-Biasctrl and High-Biasctrl are the two 59 tuning control blocks that are built using the circuit in Fig. 4.15. The two control blocks are exactly the same except for the transistor sizes. The different transistor sizing allows each of the branch of the current steering circuit to sink in different amounts of current and hence vary the voltage that bias some of the gates (buffers and AND gates) in the ring oscillator. This, in turn, gives different delays for each gate, and hence different periods for the ring oscillator. The sizes of the transistors in High-Biasctrl are larger than that in Low-Biasctrl block for achieving larger period differences. With the two blocks, there are a total of eight control taps and thus 2A8 = 256 possible frequencies to which this ring oscillator could be tuned to. With these TAPS, a period resolution of less than one picosecond is achieved. Table 5.2 shows some of the tuning that was achieved through the circuit. T \m r 4.2. TINT T I M N G Control Switches Low-Biasctrl vlli»h-M"asctiT' ' Ki-Miluiion ps TapO lap/ Iap2 l'tip.1 Tap4 I'ap5 lap ft Tap 7 1 0 0 0 0 0 u 0 0.75 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 2.75 0 0 0 1 0 0 0 0 6 • 0 0 0 0 1 0 0 0 3.3 0 0 0 0 0 1 0 0 8 0 0 0 0 0 0 1 0 20 0 0 0 0 0 0 0 1 44 60 Chapter 5 Results and Analysis 5. 1 Methodology As explained earlier in Chapter 1, the goal of this research project was to modify a proposed circuit [9] according to the specifications set in Chapter 3, and make it suitable for picoseconds TDC measurements. Fig. 5.1 shows the flowchart of how the design was optimized to perform according to our benchmark of less than +/2ps PeriodQuality at. start-up, during steady-state and during switching between coarse and fine resolutions. This chapter presents and discusses the results of this process. (1) Run Oscillator (2)1 Plot PeriodQuality Graph (3) NO Modify Design (4). Y E S Run Oscillator with "coarse" and "fine" tuning Figure 5.1: Oscillator debug and design flowchart 61 5.2 Oscillators without Tuning As indicated by tasks 1, 2 and 3 in Fig. 5.1, the first objective in the design procedure was to determine if meets the defined PeriodQuality metric without any tuning. 5.2.1 Original Oscillator Performance With no coarse or fine tuning, the only error terms that are of concerns are that due to the oscillator start-up transient and period deviations in steady state. Fig. 5.2 shows the plot of PeriodQuality as obtained from the original circuit without any tuning. Lower Limit _i i i i i i 0 50 100 150 200 250 300 Peri odQuali tyWi ndow Figure 5.2: PeriodQuality plot of the initial oscillator circuit 62 In Fig. 5.2, the targeted upper and lower bound of +2ps and -2ps are shown by the two horizontal lines. It is seen that the PeriodQuality has a relatively large start-up transient and it is also observed that at steady state, the period is not constant and decreases continuously. As shown in Chapter 3, the effect of steady state period variations, after the start-up transient, causes error in the TDC measurements (Eq. 14). But with the oscillator characteristic as shown in Fig. 5.2, the period never stabilizes and so a TDC based on this oscillator will give inaccurate results. Fig. 5.3 shows a zoomed in view of Fig. 5.2 to emphasize the start-up transient. It can be seen that the PeriodQuality is outside of the +/-2ps bound approximately during the first 12 cycles signifying a start-up transient of 12 cycles. Start- UpTransient settles here CL 5 -upper limit 0 0 0 0 0 0 0 lower limit -5 0 5 10 15 PeriodQualityWindow 20 F i g u r e 5.3: Il lustration of start-up transient 63 As will be shown next, this start-up transient is caused by the gates of the ring oscillator having varying propagation delays when the oscillator is started. Eq. (20) shows the dependency of the delay through a CML gate to the tail biasing current, IBIAS-In the ring oscillator, the tail biasing currents of the buffers and AND gates are controlled by the voltages at node VBN (Figs. 4.6 and 4.7) which in turn are derived from the three output nodes, VBO, VB1 and VB2, of a current source [9] (Fig. A.4). As shown in Fig. 5.4, all the output nodes of the current source, VIB2, VIB1 and VIBO have transients when the oscillator is started. These cause a corresponding change in IBIAS and hence transient in the gate delay leading to the oscillator start-up transient. In Figs. 5.4 (a), (b) and (c), it can be seen that the voltage transients die away after about 25ns - 30ns. The duration of the start-up transient in terms of clock cycles is, from Fig. 5.3, 12 clock cycles, with each clock cycle equal to 1.767ns, as shown in Fig. 5.5. This gives a transient length of (12x1.767ns) ~ 21ns, which as expected, is in close proximity of the transient duration of 25ns - 30ns observed in Fig. 5.4. 64 Transient Response 591.4m " i B 2 591.2m l 610.6m 610.5m 610.4m 610.3m 610.8m,° : <™B0 0.00 (a) Transient Response 40.0n 6i3.0n time ( s ) (b) Transient Response 40.0n 60.0n if me ( s ) (c) Figure 5.4: Bias voltages, VIB2, VIB12, and VIBO to the C M L gates at the time of oscillator start-up 65 T r a n s i e n t R e s p o n s e »: /cikn 113n Figure 5.5: Oscillator output The amount of loading of the voltage nodes, VIB2, VIB1 and VIBO affects the duration of the start-up transient. The loading can increase with the number and size of CML gates connected to these output nodes, VIBO, VIB1, and VIB2, of the current source in Fig. A.4. Fig. 5.6 illustrates this point. In Fig. 5.6, only a single buffer of drive strength xl is connected to output, VIBO, of the current source as compared to Fig. 5.4 (c) where four CML gates were connected to the same node. The rest of the gates were connected to the other two output nodes, VIB1, and VIB2, of the current source. This introduces a relatively smaller load on the output, VBO, of the current source. The result in Fig. 5.6 shows that the output voltage reaches steady-state faster than that in Figs. 5.4 (c). 66 Transient Response 609.9m t i . . ._^. , -_ . . . . - J ,. , • 1 , i , , 1 I L_I_J._ , , 1 I L _ l : , i , I : 1_J_, 1 l - J — l — l 1 1 0.00 • 20.0n 40.0n 60.0n 80.0n 100n time ( s ) Figure 5.6: Bias voltage of a single buffer at the time of oscillator start-up 5.2.2 Modified Oscillator Performance Proper sizing of each of the gates in the oscillator minimized the effect of loading the current source. Fig. 5.7 shows the start-up characteristics of two modified oscillator with different gate sizing. These oscillators were run without any tuning. Oscillators with other configurations were also run with different sizing of the gates. However, the two configurations in Fig. 5.7 show the best results according to the PeriodQuality behavior. 67 The following gives the configurations of the gates used in each of the two cases shown in Fig. 5.7 (a) and (b): (a) All the gates are of xl drive strength. (b) All the gates are of x2 drive strength The drive strength of each gate is defined as the amount of bias current, IBIAS, that the current source provides. In this design, the drive strength of a gate with an IBIAS of ~70uA is defined as xl. From Fig. 5.7 (a) and (b), it can be seen that (a) has better performance in terms of start-up transient and period deviations in steady state. The start-up transient settles down to within the upper and lower limits of +/-2ps after only two clock cycles and the period deviations in steady state after the start-up transient is significantly reduced after about 25 clock cycles. The configuration in Fig. 5.7 (b) has a long start-up transient of 16 clock cycles. 68 The architecture in 5.7 (a) was chosen for its short start-up transient and low steady state period deviations. This is because of the minimum size gates that were used in Fig. 5.7 (a) and thus reducing the load on the output of the current source that provides biasing voltages to the tail current of the CML gates. 5.3 Oscillators with Coarse and Fine Resolutions Now that a design is chosen that shows performance in accordance to the specification without any tuning, the next step was to investigate its transient behavior when both coarse and fine resolutions are applied. 5.3.1 Original Oscillator Performance Fig. 5.8 shows the PeriodQuality plot of the original oscillator with both coarse and fine tuning applied, as would be used in a real TDC application. In Fig. 5.8, the oscillator RESET signal is enabled and preset to coarse resolution at event A, and the oscillations are triggered at event B. The coarse resolution is achieved through a combination of controlled delay elements (Fig. A.5) and taps switching of the current steering circuit in Fig. A.4. At event C, the resolution of the oscillator is switched from f coarse to fine. At event D, bringing the RESET signal to low stops the oscillation. From Fig. 5.8, it is seen that the oscillator PeriodQuality suffers a large variation at start-up, then settles down to a smaller value within the upper and lower limits of +/-2ps, has another large variation at event C when the resolution is switched from coarse to fine, and then settles again to a smaller value. It is noted that in Fig. 5.8, the PeriodQuality starts from a negative value as compared to starting from a positive value shown in Fig. 5.7. 69 A B • C D RESET TRIG rr>ApsF T ~ T X - T -Point of switching from coarse to fine resolution 150 100 ^ 50 <y •o 0 o n ft -50 -100 1 1 < > ) ;) ^ ^ ^ ^ Upper Limit t f o D 1 ' 1 Lower Limit J i : LJ i i _ 0 50 100 150 200 P eri odQual ityWindow Figure 5.8: PeriodQuality plot of the original oscillator with coarse and fine tnnino 70 Fig. 5.9 is a zoomed in view of Fig. 5.8 to emphasize the transients at the start-up and switching regions. Fig. 5.9 (a) and (b) illustrate clearly that the oscillator suffers from a start-up transient of 12 clock cycles and a switching transient of 14 cycles, respectively. Upper Limit Lower Limit Stari-Up transient settles after 12 cycles 10 15 PeriodQualityWindow 20 106 108 110 112 114 PeriodQualityWindow 118 (a) (b) Figure 5.9: Illustrations of (a) start-up transient and (b) switching transient in F i g . 5.8 5.3.2 Modified Oscillator Performance I The start-up and switching transients are due to introducing additional controllable delays to the oscillator nodes and loading the output of the current source (Fig. A.4) that bias the CML gates during the coarse and fine resolutions. The delay elements were modified such that more weight is put on the delay elements to achieve a coarse resolution. This allows for reduced current variation through the CML gates and hence improves the transient behavior of the oscillator. As mentioned in section 4.5.1 of Chapter 4, both the NMOS load-based delay elements and the parallel-plate capacitor 71 load-based delay elements can be used for the tuning mechanism that uses controllable delay elements (Fig. A.5). Figs. 5.10 and 5.10 shows the performance of the modified oscillator using either NMOS load-based or parallel-plate capacitor load-based delay elements in the tuning mechanism. A B D RESET TRIG COARSE FINE 25 20 15 to CL § 10 o T 3 O OJ Q. 5 Point of switching from coarse to fine resolution 0 50 100 150 200 PeriodGualityWindow Figure 5.10: Plot of PeriodQuality with NMOS load-based delay element for tuning 72 c D RESET TRIG COARSE FINE Figure 5.11: Plot of PeriodQuality with parallel-plate capacitor load-based delay element for tuning 73 It can be seen that the start-up transient in both Figs. 5.10 and 5.11 ends after the 4th cycle. However, at the time the operation of the oscillator is switched from coarse to fine resolution at event C, the PeriodQuality does not satisfy the upper and lower limits, producing a large switching transient. Compared to the 14 clock cycles long switching transient in Fig. 5.9, it is seen that the switching transients in Fig. 5.10 and 5.11 are longer with 45 and 30 clock cycles respectively. However, the effect of the transients in Fig. 5.10 and 5.11 is smaller because the transients have lower PeriodQuality value than that in Fig. 5.8. The reason for this transient can be explained with the circuits in Fig. A.5 (Appendix A). The delay elements shown in Fig. A.5 are very much similar. In Fig. A.5 (a), the NMOS transistors act as loads for the delay element whereas in Fig. A.5 (b), the capacitors act as loads for the delay element. The following explanations are with regard to the circuit in Fig. A.5 (a), but can be equally applied to the circuit in Fig. A.5 (b). The delay element in Fig. A.5 (a) consists of two capacitors, CLP and CLN, two NMOS switching transistors MSP and MSN (digital switches) and the control signal CTRL. In Fig. A. 5 (a), A and B are the two differential nodes of the oscillator to which the delay element is connected. B symmetry, the circuit with node B is exactly the same as the circuit connected to node A. The control signal CTRL is connected to the gates of M$p and MSN- When the input CTRL is high, both M$p and MSN are ON pulling down the drains of the two transistors to ground, hence connecting the bottom plates of the capacitors to the ground. As such, turning on MSP and MSN adds the capacitances of CLP and CLN to the capacitive load of the two input nodes A and B. This introduces an additional RC delay at the differential nodes, A and B, of the ring oscillator. This RC delay also causes the 74 period of the ring oscillator to change. Depending on how many of these blocks are connected to the differential nodes of the oscillator, the period can be varied more or less. To turn the tuning OFF, the control signal CTRL at the gates of the NMOS transistors are set to logic LOW. This makes the load capacitors CLp and CLN float because these capacitors are now in series with large impedances (transistors MSP and MSN are in high impedance mode when turned off). With the NMOS transistors MSP and MSN suddenly turned off, some of the charges that were stored on the bottom plate of the capacitors have no place to go and are trapped. These charges, if not properly discharged, cause the oscillator to have a varying oscillation period for a number of cycles. The period variations due to this trapped charges manifest as part of the switching transient as can be seen in Figs. 5.10 and 5.11 at event C. The trapped charges have to be discharged in some t way. The modified delay element of Fig. 5.12 is used to get rid of the trapped charges. A B Figure 5.12: Delay element-based resolution adjustment block 75 In the modified delay element of Fig. 5.12, two PMOS transistors, M3 and M4, are added in parallel with the two loading capacitors. M3 and M4 discharge the plates of the capacitors when the control signal, CTRL, is set to logic LOW. Figs 5.13 and 5.14 show the PeriodQuality plots after adding the two discharging transistors to all the delay elements. In Figs. 5.13 and 5.14, it is seen that adding the PMOS transistors immediately makes the PeriodQuality be within the upper and lower bounds of +/-2ps. It is also seen that the PeriodQuality is within the benchmark of +/-2ps starting from the fifth PeriodQualityWindow meaning that the start-up transient of the oscillator dies down according to the +/-2ps definition after the fourth clock edge. This means that using the modified oscillator in a TDC measurement, it is possible to switch admeasurement from coarse to fine resolution after five clock cycles with reduced error due to non-linearity in the measurement. With the switching transient within the +/-2ps immediately after switching, a measurement can be completed from the first cycle of the fine resolution of operation. Results in Chapter 6 will show this to be true. This will be demonstrated in Chapter 6. Therefore, from the results obtained from Fig. 5.13 and 5.14, it can be concluded that using the modified ring oscillator, with either parallel plate capacitor-based load or NMOS-based load delay elements as one of the tuning mechanisms, one can design a robust Vernier oscillator-based TDC for fast and accurate time interval measurements. 76 A B D RESET TRIG COARSE FINE 25 20 ^ 15 |T § 10 O O Q_ 5 The 5th PeriodQualityWindowj is within +/- 2ps Point of switching from coarse to fine resolution 0 50 100 150 PeriodQualityWindow 200 Figure 5.13: Plot of PeriodQuality of modified oscillator with NMOS load-based delay element and with PMOS discharging transistors 77 A B C D RESET , : : TRIG COARSE F I N E 25 -5 50 100 150 PeriodQualityWindow 200 F i g u r e 5.14: Plot of PeriodQuality of modified oscillator with parallel-plate capacitor load-based delay element and with P M O S discharging transistors 78 Chapter 6 Vernier Oscillator-based TDC Design 6.1 Goal To assess the performance of the improved oscillator in a TDC system, a complete system-level Vernier oscillator-based TDC simulation was performed. All the control blocks were implemented using VerilogA/SpectreHDL behavioral models in Cadence. The control blocks include coarse and fine counters, a resolution adjustment block that controls the coarse and fine resolution of operation of the TDC, and a coincidence detector that detects the coincidence event of the two clock edges from oscillators A and B. The functionality of these behavioral models was verified individually before integrating them at the system level. This chapter briefly presents the behavior of each of the blocks and an analysis of the results obtained from the TDC. 6.2 TDC Overview Fig. 6.1 shows the entire TDC implemented using the original and modified oscillators and associated control blocks. Trigger Oscillator A Fine/ . Coarse h Delay Element Control Fine/ Coarse CLKA To Delay1 Elements" Resolution Adjustment Controller Trigger Reset Oscillator B CLKB " A T Td Generator Coincidence Detector Coarse Counter Fine Counter Figure 6.1: Overall TDC architecture 79 As shown in Fig. 6.1, a basic Vernier oscillator based TDC consists of two oscillators (one of which has a variable period), two counters, a resolution adjustment controller and a coincidence detector. 6.2.1 Td Generator The Td generator generates the START and STOP signals corresponding to the start and end of a time interval to be measured. The generated Td values are programmable. 6.2.1 Double Oscillator During a time interval measurement, Oscillator A is triggered by the rising edge of the START signal and Oscillator B is triggered by the rising edge of the STOP signal. The START and STOP signals could be the time interval between two consecutive rising edges of the signal under test. Oscillator A is slower than Oscillator B, meaning that the period of Oscillator A is larger than that of Oscillator B. As shown in Fig. 6.1, the period of Oscillator A is varied to achieve the coarse and fine resolutions. 6.2.2 Counter The two counters record the measurement counts during coarse and fine resolution of operation. Both these counters are clocked by the output from Oscillator B. The coarse counter records the count from the STOP event to the point of switching from coarse to fine resolution. The fine counter records the count from the point of switching from coarse to fine resolution to the coincidence event. 80 6.2.3 Resolution Controller The resolution adjustment controller switches the resolution of one of the oscillators from coarse to fine when the difference between the rising edges of the two oscillators approaches a certain programmable threshold, TSWitChing. In Fig. 6.1, the controller switches the resolution of Oscillator A from a coarse to a fine resolution. Both the coarse and fine resolutions are programmable. The coarse and fine resolutions are achieved using controllable delay elements and the current steering circuits. The delay elements and the taps of the current steering circuits are controlled using control signals that may be supplied as a vector in the form of ao,ai,a2...an [9]. Setting a bit in the vector to HIGH or "1" means turning on its corresponding delay elements and tap switches corresponding to that vector. The resolution adjustment controller can choose different coarse and fine adjustment steps. A binary search algorithm may be used to select the vectors for the desired resolution [9]. 6.2.4 Coincidence Detector The coincidence detector detects the end of a measurement when the rising edge of the faster clock precedes the rising edge of the slower clock by at least a time equal to the setup time of the coincidence flip-flop. The coincidence detector was simulated using a behavioral flip-flop with zero set-up time. In this project, at the start of a measurement, the rising edge of the slower Oscillator A leads the rising edge of the faster Oscillator B. As time progresses, the time difference between the z'fh edges of the rising edges of the two oscillators becomes smaller and smaller until for some value of i, the rising edge of the faster Oscillator B precedes the corresponding rising edge of 81 Oscillator A. At this point, the coincidence detector records this event and sends out an end of measurement signal that resets both oscillators. 6.3 TDC Calibration The TDC needs to be calibrated prior to any time interval measurement. Eq. (10) is the defining equation for the operation of the TDC and is reproduced here [9]: In order to measure a time interval "TD" with a certain coarse and fine resolutions, the TDC needs to be calibrated for the three unknowns: TAQ TAF and TOFFSET- Each measurement generates two numbers, Nc and 7v>, from the coarse and fine counters respectively. To estimate the three unknowns, the TDC measures three different time intervals, T^ s, with the same coarse and fine resolution settings to produce three equations with the three unknowns of interest [19]. Td=(NcxTAC) + (NFxTAF) + Tc OFFSET (7v r c l xr A C )+(/v T n xr A F )+7; 0 (/vC 2xrA C)+(7v f 2xrA F)+r £ (/v C 3x7;A C) + (/vT F3xrA F)+r 0 OFFSET OFFSET OFFSET Td (/) 2Td...(ii) 3Td...(iii) Let a = N F 2 - N t F\ CI b = 2 c = C l CI 82 Solving equations i, ii, and iii and using a, b and c, the three unknown parameters of interest can be found as follows: b — a (25) (27) (26) This method is known as the three-point calibration technique [19]. In hardware, the known Tjs are generated using a low-jitter reference clock. With TAc, TAF and TOFFSET known, simulations were run for different Td values. The following equation is used to obtain the measured Td'. 6.4 TDC Results and Analysis The following subsections compare and discuss the results obtained from measuring test TdS using the original and modified oscillators in the system-level TDC of Fig. 6.1 to demonstrate their performance. Detailed results and plots are appended in Appendix A. Td =(NcxTAC) + (NFxT&F) + Ti OFFSET (28) 83 6.4.1 Original Oscillator with 500ps < Td < 600ps The target of the TDC was to measure timings of high-speed signals in the GHz range. A Td of 500ps amounts to measuring the period of a 2 GHz signal. Different values of TdS, ranging from 500ps to 600ps in increments of Wps were measured using simulations of the TDC. A coarse resolution, TAc, of 40ps and a fine resolution, TAF, of 3ps were used for all the simulations. A corresponding TOFFSET of -2ps was used. The resolution switches from coarse to fine when the difference between the two edges of the oscillators differs by 150ps or less. It has to be noted that since the period of the initial oscillator never stabilizes, the calibration method described in section 6.2.5 will give faulty results. Also, for the calibration to work, three different Tjs, each a multiple of the other, have to be tested for prior to any time interval measurement. Since the initial oscillator has large start-up and switching transients, large Tj& have to be used to remove the error due to the transients. The three parameters, T&c, TAp and TOFFSET, were determined from measuring a single Td of 800ps, with switching of the oscillator resolution from coarse to fine when the difference between the two edges of the oscillators differ by 250ps or less. This will allow the measurement to have enough cycles in the coarse and fine resolution regions and remove error due to the start-up and switching transients. However, errors due to long-term period deviations cannot be eliminated with the original oscillator. One complete measurement cycle consists of averaging several thousand consecutive Td measurements. Since in reality, the time interval, Td, to be measured may suffer from fluctuations due to random noise and it may vary from one measurement to 84 the other. Therefore, it is important to reproduce this behavior in the simulations. Any random noise can be modeled as a Gaussian variable. A set of Td values were generated such as they follow a Gaussian distribution with +/-2ps rms noise (a = 2ps). For example, for a Td of 500ps, the input simulated is that as shown in Fig. 6.2. It is a Gaussian distribution with a mean of 500ps and a standard deviation, a, of 2ps. The input was simulated with a noise distribution from -3a to 3a (-6ps to 6ps) to cover almost all the noise. This means that the input test Td range that was simulated is Td+/-3a. For a Td of 500ps, this means sweeping the input Td from (500-6)=494ps to (500+6)=506ps and measuring each of these Td values several times with a frequency weight in proportion to the values shown in the y-axis of Fig. 6.2. In Fig. 6.2, the y-axis shows the probability of occurrence of a Td with respect to the other 7^ s. Fig. A. l in the Appendix shows the distribution of the resulting output Td distribution from the TDC for input Td with a distribution as shown in Fig. 6.2 for 500ps ^Td> 600ps in increments of Wps. 0.25 - I 0 0.2 - r — 1 u e « i 1 u 3 0.15 -u o «*« I 1 © >> 0.1 -1 . . I 0.05 -SLN Q I I I | | I | I | | I I I - 3 a - 2 a - a T d a 2 a 3 a Test Td (ps) Figure 6.2: Input Gaussian test time interval with a mean of J r fand a of 2ps 85 Fig. 6.3 (a) plots the mean of the measured output Td versus their corresponding input Td. The corresponding error plot is shown in Fig. 6.3 (b). (a) (b) Figure 6.3: (a) Measured Td versus test Ta measured from TDC (b) Corresponding error in the measured mean output Td from the TDC Fig. 6.3 (a) shows that the output 7^ s from the TDC behaves non-linearly with respect to the input TdS. As will be explained next, this non-linearity is due to the transient of the original oscillator during switching from coarse to fine resolution of operation. The behavior of the graph in Fig 6.3 (a) can be explained with help of Figs. 5.9 and 6.4. Fig. 5.9 shows that the original oscillator has a start-up transient of 12 cycles and a switching transient of 14 cycles. A Td measurement that completes with an Nc of less than 12 cycles and or an JV> of less than 14 cycles would obviously fall within either of the transient regions and therefore, should show non-linear behavior in the output Td 86 according to the PeriodQuality metric. Fig. 6.4 shows the number of coarse cycles, Nc, and number of fine cycles, 7V>, to complete a test Td versus the input test Td. Fig 6.4 also shows the "Start-Up Limit" and "Switching Limit" lines. These lines corresponds to Nc=\2 and NF= 14. These two lines imply that a Td measurement that completes with an Nc value below the "Start-Up Limit" line and/or an JV> value below the "Switching Limit" line would show error due to non-linearity in the output Td due to start-up and/or switching transients respectively. From Fig. 6.4, it is observed that all the measurements complete with an Nc value, which is always equal to or greater than the "Start-Up Limit", and with an JV> value, which is always less than the "Switching Limit". This implies that all the Td measurements will show error due to switching transient. 2 0 494 504 514 524 534 544 554 564 574 584 594 604 Test Td (ps) Figure 6.4: Number of coarse and fine measurement cycles 87 From Fig. 6.4, it is seen that the test set for Td =500ps (Td swept from 494ps to 506ps) completes its measurement with Nc between 12 and 13 cycles and Np between 6 and 7 cycles. Since Nc is equal to or greater than the "Start-Up Limit" (12), the non-linearity error will be only due to switching transient. The smaller the value of Nc and Np, the larger is the error due to the transients. In Fig. 6.4, as Td increases, the Nc value does not change by much, with Nc having a minimum value of 12. However, Np is larger for the test set corresponding to Td of 500ps (6 and 7) and so suffers from a smaller error of 2.3969ps (Table 6.1). As Td is increased from 500ps to 51 Ops, Np decreases from 7 to 4 and the error increases from 2.3969ps to 23.6593ps, but then as Td increases from 51 Ops to 530ps, Np increases from 4 to 6 and so the error decreases from 23.6593ps to 8.7995ps with increasing Np. For a Td of 540ps, Np is back to 7 cycles, same as for Td of 500ps, and it is seen that the error for a Td of 54Ops is the same as the error for a Td of 500ps. This trend is shown Fig. 6.3 (b). The trend of Fig. 6.3 (a) and (b) for TdS greater than 54Ops can be explained in a similar manner. Table 6.1 shows the TdS that were measured, the corresponding output mean values, and the errors from the measurements. 88 TABLE 6 .1: SUMMARY OF TD RESULTS AS MEASURED FROM T D C WITH THE ORIGINAL OSCILLATOR KM 1,1 Mean I ,i (Measured) llrror (ps) (ps) (ps) 500 502.3969 2.3969 510 533.6593 23.6593 520 536.3282 16.3282 530 538.7995 8.7995 540 542.3969 2.3969 550 573.6593 23.6593 560 575.7995 15.7995 570 578.2005 8.2005 580 581.8683 1.8683 590 613.6593 23.6593 600 615.7995 15.7995 The period stability of both oscillators, A and B, can also be tracked by plotting c the instantaneous period difference, Ta-Tb versus total measurement cycle. Fig 6.5 (a) and (b) plot the difference in the period, Ta-Tb, versus the measurement cycles for a test Td using the original oscillator. Ideally, this plot should show two constant lines outside the regions of start-up and switching transients. Fig. 6.5 (a) is obtained from measuring a Td of 800ps as part of the calibration to determine TAc, TAp and TOFFSET- Fig. 6.5 (a) illustrates that the oscillator period has some jitter even after the start-up transient dies down after 12 cycles. 89 ! Measurement Cycles Measurement Cycles (a) (b) Figure 6.5: Plot of period difference versus total measurement cycles from the TDC using the original oscillator for a (a) Td of 800ps and (b) Td of 515ps Fig. 6.5(a) also shows that one has to wait approximately another 14 clock cycles after switching from coarse to fine resolution to reduce the effect of switching transient. Fig. 6.5 (a) shows the limitation of the old oscillator where a measurement takes at least a minimum of 36 clock cycles to complete to avoid any non-linear error due to the transients. As mentioned earlier, a time interval needs to be measured 1000-10,000 times to remove effects of random noise. This amounts to a long test time. Fig. 6.5 (b) shows a similar plot to Fig. 6.5 (a) with a Td of 550ps. It shows completion of the measurement before the switching transient dies down. It demonstrates that if the measurement is not given a long enough time to complete in the oscillators' steady-state region, the error is large (23.6593ps) and the error shows up as a non-linear error. This oscillator cannot be used to perform time interval measurements with good accuracy or fast test time. 90 The results from the other test Tjs (500ps to 600ps in increments of Wps) are shown in Appendix A. l . Fig. A. l (b) - (1) show the histograms of the output T^s corresponding to an input with the histogram as shown in Fig. A. l (a). From Fig. A. l (b) - (1), it is seen that the output histograms are spaced far apart from the input mean Td. 6.4.2 Modified Oscillator with 500 ps < Td < 600ps Different values of 7>s, ranging from 500ps to 600ps in increments of Wps were measured using simulations of the TDC with the modified oscillator. A coarse resolution, TAc, of 38.5/75 and a fine resolution, TAF, of 3.1ps were used for all the simulations. A corresponding TOFFSET of -OAps was obtained. The resolution switches from coarse to fine when the difference between the two edges of the oscillators differs by 50ps or less. Figure 6.6 (b) shows the distribution of the resulting output TdS from the TDC for the input TdS as in figure 6.6(a) corresponding to an input Td of mean 550ps. Test Td (ps) (a) 0.6 -. o 0.5 -fl w H § 0.4 • <S 0.3 • o >^  £ 0.2 cd JO O 0.1 -0 -Td550ps 544.3 547.4 550.5 553.6 554.9 Measured Td (ps) (b) F i g u r e 6.6: (a) Input Gauss ian test Td (b) C o r r e s p o n d i n g measured output J r f f r o m the T D C 91 It can be seen from Fig 6.6 (b) that the Tjs are binned to certain values only. The size of separation of the output bins is set by the fine resolution, TAF- The input test Tjs over 13 bins, that are separated by one picosecond from one another, are binned into only five output bins that are 3.1ps apart. This is as expected since the TAp used in the measurement is 3. lps and so all the input 7^ s will fall into the five different output bins, depending on where the coincidence happens. The height of the output bins or the probability of occurrence of the output bins are also larger compared to the input bins because TdS from 13 bins are quantized into five output bins only. It is also seen from Fig. 6.6 (b) that most of the output Tjs are concentrated around the 550.5ps bins implying that the mean of the output Td will be somewhere close to the input Td of 550ps. Fig. 6.7 (a) and (b) plot the mean of the measured Td versus the input test TdS and the error in the measured Td versus the input test 7js, respectively. Fig. 6.7 (a) shows that the plot of the mean of the measured output Inversus test Td from the TDC is very close to a straight line implying a linear relationship of the input Td to the output measured Td. This is in sharp contrast to the non-linear relationship of the input Td to the output measured Td in Fig. 6.3 (a), when the TDC uses the original oscillator. Fig. 6.7 (b) shows that the peak-to-peak error is smaller than the fine period resolution, TAp, of 3. lps. The maximum difference between two bins in the output histogram is set by TAf. As such, the maximum error is bound by the binning quantization error. With a smaller fine resolution, the binning quantization error could be reduced even further. Table 6.1 summarizes the results obtained in Fig. 6.7 (a) and (b). Histogram results for the rest of the Td s are shown in Appendix A.2. 92 620 -i Figure 6.7: (a) Measured TD versus test TD measured from TDC (b) Corresponding error in the measured mean output TD from the TDC Table 6.2 shows the sets of T^s that were measured, the corresponding output mean values, and the errors from the measurements using the modified oscillator. TABLE 6 .2: SUMMARY OF TD RESULTS AS MEASURED FROM T D C WITH THE MODIFIED OSCILLATOR 1 est 1 ,i Mean T,i (Measured) (ps) (ps) Error (ps) 500 501.5433 -1.5433 510 510.1276 -0.1276 520 519.504 0.496 530 529.2026 0.7974 540 541.4576 -1.4576 550 550.5153 -0.5153 560 559.2746 -0.7254 570 570.8026 -0.8026 580 579.7272 -0.2728 590 589.509 0.491 600 599.1974 0.8026 93 Fig 6.8 shows the plot of the difference in the period, Ta-Tb, versus the measurement cycles for a test Td of 515ps. 40 35 30 CO &> £ 20 CO E-i 15 10 5 0 0 5 10 15 20 Measurement C y c 1 e s Figure 6.8: Period difference versus total measurement using the modified oscillator for a rrfof515ps Comparing Fig. 6.8 to that of Fig. 6.5 (b), it is seen that coarse measurement and fine measurement cycles using the modified oscillator have insignificant transients. Fig. 6.8 shows that a TDC based on the modified oscillator can complete a time interval measurement with less than five clock cycles of coarse and less than five clock cycles of fine resolutions. Since the measurement would be completed outside any transient regions, the only sources of errors in the measurement would be a constant offset (for the very short transient at the start of coarse resolution), period deviations in the steady state and binning quantization error. From Fig. 5.14, it is seen that the PeriodQuality is around zero meaning that the effect of period deviations in the steady state is very minimal. The dominating error in this design is the binning quantization error as shown in Fig. 6.7(b). 94 However, the environment under which the TDC was simulated was noise-free. In reality, external noises could introduce some errors in the TDC measurement. Even though averaging could also minimize this error when due to random noise, it would not take care of any other non-random/interference patterns. Characterizing for external noise and simulating the circuit under noise conditions would be an interesting topic for future work and will be discussed in Chapter 7. The results from the other test 7^ s (500ps to 600ps in increments of Wps) are . shown in Appendix A.2. A second test case with a shorter set of 7^ s, from 250ps to 350ps, was also simulated. Appendix A.3 provides detailed plots for these results. Fig. A.2 (b) - (1) and Fig. A.3 (b) - (1) show the histograms of the output Tds corresponding to an input with the histogram as shown in Fig. A.2 (a) and Fig. A.3 (a) respectively. The results show that the outputs are binned around the input mean Td and as such, the errors in the measured output T^ s are small. 6.5 Summary and Comparison of Results Table 6.3 shows the comparison of the two oscillators. For a fair comparison, a test Td of 515ps is chosen because it takes equal number of Nc and Np to complete the measurement. TABLE 6.3: SUMMARY AND COMPARISON OF THE RESULTS OF A TEST TD Oscillator 1 Test T d 1 I^omst (ps) (ps) T\l IM (ps) l n i i s n (ps) \ ] i M 1 Measured T d 1 n o r (ps) Original 515 40 3.0 -2 13 4 534 -19 Modified 515 38.5 3.1 -0.4 13 4 513.3 1.7 95 Fig. 6.8 and Table 6.3 show that the TDC takes 77 cycles to measure a Td of 515ps with both the original and the modified oscillators. However, the absolute error using the original oscillator is larger (19ps) as compared to that using the modified structure (1.7ps). The error in Td measurements using the original oscillator is non-linear whereas that using the modified oscillator is always within TAF- The non-linear error due to the transients of the original oscillator makes it unsuitable to be used in TDC for fast measurements. By increasing T&c and TAF of the modified oscillator, the same Td measurement as shown in Table 6.3 can be completed in less number of cycles. However, this would cause the maximum error due to quantization to increase. 9 6 Chapter 7 Conclusions 7.1 Summary of Contributions This dissertation presented the problem of start-up and switching transients in a ring oscillator and their impact on Vernier oscillator-based TDC measurements. It also showed analytically, (Eq. (14)), the impact of oscillator period deviations in steady state and externally introduced random noise on the TDC performance. A PeriodQuality metric to characterize the effects of these transients and steady-state period variations, and noise on the time interval measurement is derived to benchmark the performance of the ring oscillator. This metric can be used to evaluate performance of any oscillators for its stability. This work also described an improved CML-based ring oscillator (modified from a given circuit from VI2 Corp.) that has short start-up and switching transients as well as a very stable steady state period suitable for use in TDC application. Simulation results from the improved ring oscillator show that the effects of the start-up transient become negligible after four clock cycles and that of the effects of switching transient become negligible within the bounds, set by the PeriodQuality metric, instantaneously. Simulations also show that the oscillator can achieve a stable steady state period, down to less than 0.5fs, which is the simulator's precision. A Vernier oscillator-based TDC system was designed with two ring oscillators and behavioral control blocks to demonstrate the stability of the modified oscillator. This 97 TDC system was simulated to measure a range of time intervals, with input timing noise, using both the original and the modified oscillator for detailed comparison. Results for the modified oscillator simulations show that the error due to the start-up and switching transients is negligible. Results also show that two of these oscillators could be used in such a TDC design to measure timings in the range of picoseconds with the maximum error bound by the fine resolution of the oscillator. 7.2 Future Work This work attempted to study the impact of the non-idealities of a ring oscillator on a Vernier oscillator-based TDC design and to improve the design such that time interval measurement is performed with reduced time and increased accuracy. It also enabled time interval measurements in the order of picoseconds, which would enable timing specification measurements such as jitter of high-speed signals running in the gigahertz range. The first goal of any future work would be to fully characterize the tuning mechanisms of the oscillator to have predictable resolutions steps. A detailed analysis of the effects of external and device noise on the performance of the oscillator, as well as design issues to compensate for these noises should be an interesting topic for future work. For a truly robust design, more modeling of noise and noise immunity in the oscillator is necessary. The next logical extension to the work would be to implement the oscillator on silicon to verify physically its functionality. Another main area for future work is to implement a calibration circuit on silicon that could be used to experimentally verify the functionality of the oscillator, such as 98 measuring the period of the oscillator to identify any transients in the oscillator period during the start-up and switching operations. The calibration circuit would be a practical application of the "PeriodQuality " tool that could be used to characterize the transients of the oscillator in this work. This circuit could also be used as a debugger to verify the resolution steps of the oscillator. Finally, a niche jitter generator circuit could be implemented by exploring the versatility of the current steering circuit using a current source. Jitter generation circuits are used to test timing circuits, such as PLLs, for their jitter tolerance and jitter transfer characteristics. As described previously in Chapter 4, one of the period resolution adjusting mechanisms consists of using two current steering circuits together with a current source circuit. These circuits can vary the biasing voltage of the different gates in the ring oscillator with 28 = 256 different possible resolutions. By proper characterization and control of these circuits, a precise amount of jitter could be generated using the oscillator. For example, being able to change and control the oscillator period every cycle with high-resolution amounts to producing a predictable amount of jitter on the oscillator output. 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Berroth, " 5 GHz Voltage-Controlled Ring Oscillator using Source Capacitively-Coupled Current Amplifier", IEEE Silicon Monolithic Integrated Circuits in RF Systems, pp. 45-48, April, 2003. [30] A. Rezayee, K. Martin, "A Coupled Two-Stage Ring Oscillator", Proceedings of the 44th IEEE Midwest Symposium of Circuit and Systems (MWSCAS), vol. 2, pp. 878-881, August 14-17 2001. [31] A. Hajimiri, T. H. Lee, "Low Noise Oscillators", Kluwer Academic Publishers, MA, USA, 1999. 103 [32] D. P. Bautista, M. L. Aranda, "A Low Noise and High Speed CMOS Voltage-Controlled Ring Oscillator", Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)," vol. 4, pp. IV-752 - 5, 23-26 May 2004. [33] N. Barton, D. Ozis, T. Fiez, K. Mayaram, "Analysis of Jitter in Ring Oscillator due to Deterministic Noise", IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, pp. 393-396, May 26-29, 2002. [34] F. Herzel, B. Razavi, "A Study of Oscillator Jitter due to Supply and Substrate Noise", IEEE Transactions on Circuits and Systems II, vol. 46, pp. 56-62, January 1999. [35] A. Hajimiri, T. Lee, "A General Theory of Phase Noise in Electrical Oscillators", IEEE Journal of Solid State Circuits, vol. 33, pp. 179-194, February 1998. [36] J. A. McNeill, "Jitter in Ring Oscillators", IEEE Journal of Solid State Circuits, vol. 32, pp. 870-879, June 1997. 104 Appendix A The following plots and tables show the results from detailed TDC analysis that was performed to demonstrate the stability of the modified oscillator and compared with results from similar analysis done using the original oscillator. 105 A.l Original Oscillator with 500ps <Td< eoops 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Test T d (ps) (a) Td510ps | | | H B lllliliii Measured T d (ps) (c) Measured T d (ps) (b) 534 Measured Td (ps) (d) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Td530ps HSfl 537 540 Measured T d (ps) (e) Figure A.l: Measured output Td histograms from the T D C using the original oscillator corresponding to an input Td with histogram as shown in (a) 106 Td550ps I B ^^^^^ 543 574 Measured T d (ps) .(g) 1 0.9 -0.8 -0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Td560ps IJBillll llliillllil lllllilllillll • • • H i llllllillllllii iBllllilj •H illS(l|l 574 577 Measured T d (ps) (h) 577 580 Measured Td (ps) (i) 0.8 0.7 0.6 0.3 0.2 0.1 0 Td580ps IBi liiiiills 111 Illllllil 580 583 614 Measured Td (ps) (j) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Td590ps Silllililil BB|BHM HEMP liillliilliil 583 614 Measured Td (ps) (k) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Td600ps M H I | | 1 IBMl 614 617 Measured Td (ps) (I) Figure AAcont: M e a s u r e d output Td histograms f r o m the T D C using the or ig inal oscillator corresponding to an input Td with histogram as shown in (a) 107 A.2 Modified Oscillator with 500ps <Td< 600ps 0.6 0.5 0.4 0.3 0.2 0.1 0 (a) TdS 1 Ops IIP I i m 1 mm mm — r=i 505.8 508.9 512 513.3 515.1 516.4 Measured Td (ps) (C) 525.7 528.8 531.9 Measured Td (ps) (e) 499.6 502.7 Measured Td (ps) (b) 505.8 513.3 515.1 516.4 519.5 522.6 525.7 Measured Td(ps) (d) 535 538.1 541.2 544.3 547.4 Measured Td (ps) (f) F i g u r e A . 2 : M e a s u r e d output Td histograms f r o m the T D C using the modif ied oscillator corresponding to an input Td with histogram as shown in (a) ) 108 0.6 0.6 Td550ps 544.3 547.4 550.5 553.6 Measured Td (ps) (g) 554.9 564.2 567.3 570.4 573.5 Measured Td (ps) (i) 576.6 a o. Td560ps 554.9 558 561.1 564.2 Measured Td (ps) (h) 567.3 573.5 576.6 579.7 582.i Measured Td (ps) G) 582.8 585.9 589 592.1 593.4 Measured Td(ps) (k) 596.5 596.5 599.6 602.7 Measured Td (ps) (I) Figure A.2cont: Measured output Td histograms from the TDC using the modified oscillator corresponding to an input Td with histogram as shown in (a) 109 A.3 Modified Oscillator with 250ps <Td< 350ps 2 5 6 . 2 2 5 9 . 3 262 .4 2 6 5 . 5 268 .6 Measured T d (ps) (c) 276.1 2 7 9 . 2 2 8 2 . 3 Measured T d (ps) (e) 285 .4 o 2 4 6 . 9 2 5 0 253 .1 2 5 6 . 2 2 5 9 . 3 Measured T d (ps) (b) 2 6 5 . 5 2 6 8 . 6 2 7 1 . 7 2 7 3 Measured T d (ps) (d) 2 8 5 . 4 2 8 8 . 5 2 9 1 . 6 2 9 4 . 7 Measured T d (ps) (f) F i g u r e A . 3 : M e a s u r e d output Td histograms f r o m the T D C using the modified oscillator corresponding to an input Td with histogram as shown in (a) 110 0.8 0.8 0.7 -0.6 • 0.5 -0.4 • 0.3 -0.2 • 0.1 -0 -Td300ps 294.7 297.8 300.9 304 Measured Td (ps) (g) 0.8 0.7 H 0.6 0.5 -| 0.4 0.3 0.2 0.1 0 Td320ps 314.6 317.7 320.8 323.9 Measured Td (ps) (i) 307.1 327 333.2 336.3 339.4 342.5 345.6 Measured Td (ps) (k) 348.7 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Td310ps 304 307.1 310.2 311.5 314.6 Measured T d (ps) (h) 317.7 323.9 327 330.1 333.2 Measured T d (ps) G) 345.6 348.7 351.8 350 353.1 Measured T d (ps) (I) 356.2 F i g u r e A.3cont: M e a s u r e d output Td histograms f r o m the TDC using the modif ied oscillator corresponding to an input 7 d with histogram as shown in (a) 111 A.4 Resolution Adjusting Blocks tap3 L> tap2 L> tapl L> Current Source tapO t > II 3 5 s S 5 * To VBN * Z^ > V B N r> M1 M6 ' M7 M8 M9t M2 B M3 M4 M5 E vss < 7 F i g u r e A . 4 : C u r r e n t steering-based resolution adjustment block B CTRL r> M, 'SP M, 'SN I | CTRL D4 I I (a) (b) F i g u r e A 5 : Delay element based on (a) N M O S load (b) Capaci t ive load 112 A. 5 Oscillator Schematic =€ -J 17= 1 1 i tr-i-rf Buffer Delay Elements, Delay Element Control Block WBO war VIB2 CML Tail Current Control Blocks J \ AND Gate Figure A .6: Oscillator schematic 113 

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