UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

The China Labour Code: its major issues and improvement Li, Jianyong 1996

Your browser doesn't seem to have a PDF viewer, please download the PDF to view this item.

Item Metadata

Download

Media
831-ubc_1996-0618.pdf [ 3.86MB ]
Metadata
JSON: 831-1.0077425.json
JSON-LD: 831-1.0077425-ld.json
RDF/XML (Pretty): 831-1.0077425-rdf.xml
RDF/JSON: 831-1.0077425-rdf.json
Turtle: 831-1.0077425-turtle.txt
N-Triples: 831-1.0077425-rdf-ntriples.txt
Original Record: 831-1.0077425-source.json
Full Text
831-1.0077425-fulltext.txt
Citation
831-1.0077425.ris

Full Text

DESIGN, ANALYSIS, AND IMPLEMENTATION OF A DSP-BASED MODEM FOR CODE-PHASE-SHIFT KEYING by  ROBERT G. L I N K Ph.D.(Physics), The University of British Columbia,  1989  A THESIS DRAFT SUBMITTED IN PARTIAL F U L F I L L M E N T OF T H E REQUIREMENTS FOR T H E D E G R E E OF MASTER OF APPLIED SCIENCE in T H E FACULTY OF GRADUATE STUDIES DEPARTMENT OF E L E C T R I C A L ENGINEERING  We accept this thesis as conforming to the required standard  THE UNIVERSITY OF BRITISH COLUMBIA © Robert G. Link, October 1996  In  presenting this  degree at the  thesis in  University of  partial  fulfilment  of  the  requirements  British Columbia, I agree that the  for  an advanced  Library shall make it  freely available for reference and study. I further agree that permission for extensive copying of  this thesis for scholarly purposes may be granted by the  department  or  by  his  or  her  representatives.  It  is  understood  that  head of copying  my or  publication of this thesis for financial gain shall not be allowed without my written permission.  Department of  E^g^W.C a  l  \ l A O I v> 0 0  ti • ..... ^ . . . The University of British Columbia Vancouver, Canada  Date  DE-6 (2/88)  P e l  vs  N  mi  ••'  A A -U  Abstract This thesis presents the design, analysis, and implementation of a radio-frequency modem which employs the Code-Phase-Shift Keying (CPSK) method of Direct-Sequence Spread-Spectrum (DS-SS) signaling. A correlation receiver is designed for a DSP based implementation. The received R F signal is brought to a digitally represented base-band signal by product demodulation at the nominal RF frequency, followed by low-pass filtering and dual-channel 8 bit sampling at 2 MSPS. Base-band signal processing is done on a quad TT TMS320C40 general purpose DSP. The SS spreading factor is user selectable from a range of 7 to 127; with corresponding data rates in the range 100 to 9.4 KBPS. The herein designed tracking and acquisition algorithms are adapted from those of conventional DS-SS systems; while the carrier-phase tracking problem is solved by a new method hereby called Phase-Invariant-Reception (PIR). Extensive bit-error-rate (BER) measurements have been made in Additive White Gaussian Noise (AWGN) and in the presence of single tone interference. A l l measured B E R vs SNR or B E R vs JSR curves are compared to those of an ideal optimal receiver. The implementation loss, with respect to the optimal receiver, for single-channel data flow in A W G N is approximately 1.8 dB in power efficiency when the stationary receiver and transmitter use local oscillators of the same nominal frequency. The additional B E R power efficiency loss as a function of the difference in frequency of the latter two oscillators, is obtained exactly analytically and is confirmed experimentally. The main contributions to the suboptimal B E R performance are due to approximating the optimal correlator with an analog filter plus digital correlator, to tracking the timing slippage, and to using PIR instead of optimal coherent reception.  The performance of  the analog filter/digital correlator combination is obtained approximately analytically, and found to be independent of the signal-to-noise ratio. The B E R degradation incurred by the tracking is derived analytically and found to be negligible for the timing error induced by the typical present day T T L clock oscillators, unless the SNR is very high. The theoretical B E R performance of PIR is obtained exactly analytically, and found to approach that of coherent reception as the SNR increases. In addition, measured data for the mean time-to-acquire and the mean time-to-loselock in A W G N is presented; along with an outline on how these curves could be obtained analytically, and their implications for packet transmission. ii  Table of Contents Abstract  ii  List of Figures  . . vi  List of Tables  viii  Acknowledgments  ix  Chapter 1  1  Section 1  Section 2 Chapter 2 Section 1  Section 2 Chapter 3  Introduction Spread-Spectrum Communications: Motivation and Applications  1  Objective and Outline of This Thesis  2  Introduction to DS-SS and CPSK  4  Standard Direct-Sequence Spread-Spectrum with Binary-Phase-Shift Keying  4  Code-Phase-Shift Keying DS-BPSK-SS  7  The Modem Implementation on a DSP Platform  11  Section 1  General Architecture and Implementation  11  Section 2  The C40 Based IF Transmitter  12  Section 3  The IF Receiver  13  Section 4  The Digital Demodulator  14  Section 5  The Tracking and Acquisition Algorithms .  16  Section 6  DSP On Board Results  19  Section 7  Experimental Setup  21  Steady-State Performance of the Coherent Receiver  23  Section 1  Approximating The Optimal Correlator  23  Section 2  BER Performance In The Presence of Timing Slippage . . . . 28  Section 3  Experimental BER in AWGN Performance with Carrier-Wave Synchronization Imposed Externally 33  Chapter 4  iii  Chapter 5  Solving the Carrier-Wave Synchronization Problem by PIR for CPSK .  35  Section 1  Phase-Invariant Reception  35  Section 2  BER For Real Data over the Complex Channel with AWGN — Theoretical Analysis and Experimental Results  38  Section 3  BER Performance of PIR for Time Varying Phase  .42  Section 4  BER For Complex Data Flow with AWGN  Chapter 6  45  The BER Performance of CPSK in the Presence of Single-Tone Interference  48  Section 1  Theoretical Analysis for Coherent Reception  Section 2  Theoretical Analysis and Experimental Results for PIR . . . . 50  Chapter 7  ...48  Tracking and Acquisition in AWGN  53  Section 1  Mean Time to Acquire  53  Section 2  Mean Time to Lose Lock  55  Chapter 8  Conclusions  .58  Bibliography  60  Appendix A  Maximal Length PN Sequence Generation  61  Appendix B  IF Transmitter Modules  63  Section 1  Digital Communication Port Interface  63  Section 2  Level Shifter and Amplifier  64  Section 3  BPSK Modulator and Bandpass Filter  65  IF Receiver Modules  68  Appendix C Section 1  BPSK Demodulator and Low Pass Filter .  Section 2  Analog/Digital Converter  69  Section 3  ADC Converter Control  70  Section 4  FIFO Memory Banks  71  Section 5  FIFO/TMS320C40 Communication Port  73  iv  . 68  Appendix D  DSP Code Listings  75  Section 1  Master Receiver  75  Section 2  Pair of Complex Correlators . . . .  81  Section 3  Tracking Correlators  84  Section 4  Transmitter Code  87  Section 5  Application Configuration  90  V  List of Figures Figure 1  Conventional DS-BPSK-SS System  4  Figure 2  CPSK Transmitter  7  Figure 3  Synchronized CPSK Receiver  8  Figure 4  Probability of Symbol Error vs. SNR for CPSK with Coherent Reception in AWGN  9  Figure 5  Wireless Spread-Spectrum Modem Block Diagram  12  Figure 6  C40 Based IF Transmitter Block Diagram  13  Figure 7  IF Receiver Block Diagram  14  Figure 8  Digital Demodulator Block Diagram  15  Figure 9  Timing Decision Algorithm in Acquisition Mode .  18  Figure 10  Timing Decision Algorithm for Tracking  Figure 11  Experimental Setup for Measuring BER in AWGN  21  Figure 12  Analog Correlator  23  Figure 13  Analog Filter with Digital Correlator  23  Figure 14  LPF Response To a Square Pulse Chip  25  Figure 15  Signal-to-Noise Ratio for a Sampled Low-Pass Filtered Chip  . . 19  as a Function of LPF Cut-off Frequency  28  Figure 16  Two-State Markov Chain  29  Figure 17  Signal Space for Tracking Performance Calculation  31  Figure 18  BER Performance in AWGN with Tracking  33  Figure 19  Bit Error Rate vs Signal-to-Noise Ratio for M=2 and M=4 CPSK with Carrier-Wave Synchronization Imposed Externally . . . . 34  Figure 20  Quadrature CPSK Transmitter  Figure 21  Quadrature Demodulation followed by Complex Correlation . 36  Figure 22  BER vs. Signal to Noise Ratio for PIR with Real Data over Complex Channel, Word Length 1  Figure 23  . 42  Output SNR As a Function of Rx and Tx LO Frequency Difference 8 = df/f  Figure 24  . 35  45  c  Symbol Error Rate vs Signal-to-Noise Ratio for Complex Word Length 1 Data in AWGN  vi  47  Figure 25  Theoretical and Experimental BER versus JSR at SNR=12.0 dB with 8u = 0.1w  c  Figure 26  ••••  •  5  2  Mean Time-to-Acquire Measured in Data Symbol Durations vs SNR for G=63  55  Figure 27  Markov Chain for Tracking Loss Calculation  56  Figure 28  Mean Time-to-Lose-Lock Measured in Number of Data Symbols vs. SNR  .57  Figure 29  Three-Stage Maximal Generator  61  Figure 30  l-Sequence Autocorrelation Function  62  Figure 31  Communication Port Interface (one channel)  64  Figure 32  Level Shifter and Amplifier  65  Figure 33  BPSK Modulator and Filter .  Figure 34  BPSK Demodulator and Low Pass Filter  69  Figure 35  Dual Channel 8-Bit ADC . .  70  Figure 36  ADC Converter Control  71  Figure 37  FIFO Memory Banks .  72  Figure 38  FIFO/TMS320C40 Communication Port  74  v i i  . . . . . . . . 67  List of Tables Table 1  Maximum sampling rates and the corresponding data rates . 20  Table 2  Decision Variables for Phase-Invariant Decoding  viii  37  Acknowledgments I wish to thank my research supervisor Dr. Victor C M . Leung for the direction he gave me, and for the leadership that he gave to the W L A N project, of which this work forms part. I thank the professors from whom I have learned about the theory of modern day telecommunication systems — these are Prof.  Samir Kallel, Prof.  Takis Mathiopoulos,  and Prof. Victor C M . Leung. I also thank Professor Robert W . Donaldson for advice on my program and for having me on two earlier research projects, before letting me go to the W L A N project. A very special thanks go to our scientific engineer Hansen Wang for designing a portion of the modem hardware, for doing the P C B layout, for assistance with the modem testing, and for very valuable help in general. Thanks also go to Amiee Chan for assisting Hansen and I with the R F portion of the hardware design and construction. This work was supported by the Science Council of British Columbia through a Technology B . C . Grant.  ix  Chapter 1 Introduction 1.1 Spread-Spectrum Communications: Motivation and Applications A spread spectrum communication system is denned to be one for which the transmitted signal occupies a bandwidth much larger than the minimum bandwidth necessary to send the information [1]. Every information signal modulates a spreading signal, called the code signal, which is independent of the data. At the receiver, recovery of the original signal is accomplished by despreading; whereby the received spread signal is correlated with a synchronized replica of the spreading signal. The signal thus recovered is then processed by the usual techniques for communication signal reception. The techniques for spreading are direct sequencing, frequency hopping, time hopping, and hybrids of these. The use of spread-spectrum techniques originated in the development, by the military, of communication systems highly immune to intentional interference by a jammer. The idea is that if many orthogonal signal coordinates are available to a communication link, and if only a small subset of these coordinates are used at any one time, a jammer who cannot determine the signal subset currently in use would be severely handicapped. Because the error performance of the system is a function of the received signal to noise ratio, against infinite power gaussian noise, increasing the bandwidth does not improve performance. However, when the noise comes from a jammer with fixed finite power, and with uncertainty as to where in the signal space the transmission is presently located, the error performance is significantly improved. The energy density of a spread signal can be made very low because the signal power is on average spread uniformly over the enlarged number of signalling coordinates. This makes the signal very difficult to detect; and in fact, to anyone who does not posses a synchronized replica of the spreading signal, the spread signal will appear to be random noise. These properties of high interference rejection and low probability of interception have been exploited to give rise to the multiple access technique called code-division multiple access (CDMA) wherein each user of the communication channel employs a unique spreading signal to locate herself in the common transmission band. In fact, the method has become the basis for the development of new cellular radio systems for personal communications  l  networks. The spreading signal is based on a pseudorandom sequence called a key. Each radio uses its own unique key for receiving transmissions, and each radio can transmit waveforms with the key corresponding to some other radio. The different keys correspond to sequences designed to have low cross-correlation and low autocorrelation properties. The low cross-correlation of two different keys insures that a receiver locked on to a signal will experience relatively little interference from any other signal of the same channel based on a different key. Similarly, the low autocorrelation of a key will mitigate multipath effects, because a signal due to a multipath component which arrives with a delay with respect to the signal to which the receiver is synchronized, will be strongly attenuated. Direct sequencing is discussed in detail in the next chapter. In the frequency hopping technique^ the spreading is done by changing the carrier frequency of the transmitted signal, at a rate called the hop rate, according to the code sequence. With the time hopping technique, the code sequence is used to key the transmitter on and off.  1.2 Objective and Outline of This Thesis The objective of this thesis is to present the design, analysis, and implementation of a new radio-frequency (RF) direct-sequence spread-spectrum (DS-SS) modem which can enhance both the power efficiency and the bandwidth efficiency of the present day conventional DSSS systems. It uses a technique called Code-Phase-Shift Keying (CPSK), which is first proposed in [2]. The presentation is organized as follows: In Chapter 2 an introduction is given to the code-phase-shift keying method of direct-sequence spread-spectrum signaling. The remaining chapters describe work by the author which constitutes original contribution. Chapter 3 documents both the design and the implementation on a digital signal processing (DSP) platform, of the modem. A correlation receiver is designed, and the problem of synchronizing the receiver to the baseband signal is solved. The synchronization to the bit intervals is achieved by an acquisition scheme which is a generalization of the simplest acquisition scheme for conventional DS-SS. A timing recovery algorithm to maintain the bit interval synchronization, called tracking, has been realized in a hardware efficient manner by a novel design. Optimal correlating has been approximated by a combination of analogfilteringand digital correlating; and in Chapter 4, an analysis of the signal-to-noise ratio (SNR) degradation 2  incurred by this approximation has been estimated analytically. This chapter also contains theoretical analysis of the bit-error-rate (BER) in additive white gaussian noise (AWGN) performance of the herein designed signal tracking scheme.  The implementation loss  associated with the tracking scheme has been analytically estimated and found to be negligible for BERs less than 1 0  - 6  for the timing slippages induced by typical TTL clock oscillators.  To close Chapter 4, measured BER performance in AWGN, of the receiver with the carrierwave synchronization imposed externally, is presented. These measurements were performed to test the design, and to obtain an experimental confirmation of the analytic performance estimate thus far. The synchronization to the phase of the carrier wave problem is solved by a new method which is hereby named Phase-Invariant-Reception (PIR). This is presented in Chapter 5 along with a theoretical performance analysis and experimental results for the BER in AWGN. The degree to which PIR approximates optimal reception has been obtained exactly analytically as a function of the frequency difference between the carrier-wave and the local oscillator (LO) of the receiver. Chapter 6 gives theoretical analysis and experimental results on system performance in the presence of single-tone interference. A numerical expression for the BER performance of the coherent CPSK receiver has been obtained in AWGN and single tone interference. This is compared to the measured performance of the CPSK receiver employing phase-invariant reception. All claims to receiver performance have been verified, to within experimental uncertainty, by the bit error rate measurements. Chapter 7 presents experimental results on the acquisition and tracking performance of the receiver, and outlines the mathematical problems which need to be solved in order to predict these results theoretically. Mean time-to-acquire and mean time-to-lose-lock in AWGN data is reported, along with the implications for transmission data packet format. Chapter 8finisheswith the conclusions and discussion of future development.  3  Chapter 2 Introduction to DS-SS and CPSK 2.1 Standard Direct-Sequence Spread-Spectrum with Binary-Phase-Shift Keying At the modulator of a generic direct-sequence system, the information signal, of data rate Rd, is multiplied by a code signal with symbol rate R , called the code chip rate. The ratio c  G = Rc/Rd is equal to the factor by which the signal transmission bandwidth is spread. It is usually much greater than unity, and is called the processing gain. Since multiplication in the time domain transforms to convolution in the frequency domain, provided the information signal is relatively narrow-band, the product signal will have approximately the bandwidth of the spreading signal. At the demodulator, the received signal is multiplied by a synchronized replica of the code signal; thus collapsing the desired signal to its original bandwidth, while spreading any undesired signal in the same way that the transmitter spread the desired signal originally. The signal is subsequently passed through a bandpass filter, whose passband corresponds to the spectrum of the information signal, resulting in a high rejection of the interfering signal. The difference in output and input signal-to-noise ratios, in dBs, for a narrow band interferer is equal to the processing gain in dB. To see this in detail, refer to Figure 1 and consider the following analysis for the conventional coherent DS-BPSK-SS system. More details can be found in [3].  j(t) + ri(t)  d(t)  Hg)—Hg> p(t)  PN generator  s(t)  6  P(t)  PN generator  V2i;cosatt transmitter  JJ>  J()dt  4>  ^coscM channel  receiver  Figure 1 Conventional DS-BPSK-SS System  4  ddeecvisc iioen  The information sequence to be sent over the channel is represented by an antipodal pulse stream, d(t), where a pulse value of +1 represents a 0 bit, a pulse value of —1 represents a 1 bit, and the bit duration is T . This information signal is spread by multiplication with b  the antipodal chip stream p(t), with chip duration T = T /G. c  b  p(t) represents a periodic  pseudorandom sequence called a pseudonoise (PN) sequence; the generation of which is discussed in Appendix A. It is required that p(t) be synchronized with d(t), so that each bit period accommodates precisely G chips. Finally, the spread signal modulates the carrier, to produce the transmitted signal: s(t) = V2Pd(t)p(t) cos u t;  (2.1)  0  where P = E /T b  bit, and u  0  b  is the transmitter power, E is the energy of the signal representing one b  is the carrier frequency in radians.  With the receiver exactly synchronized to the bit interval, and to the carrier phase, the delay for the communication link can be taken to be zero, and the simplified block diagram, omitting the synchronization modules, of the system is as in Figure 1. We wish to consider the error performance of the idealized receiver for a channel which adds noise and interference to the transmitted signal. The channel output is r(t) = s(t)+j(t)  + n(t);  (2.2)  where j(t) is narrow-band interference, centered at the carrier, of total average power  J, av  and n(t) is additive white gaussian noise of power spectral density N . Denoting the spread 0  signal bandwidth as W, the value of the power spectral density of an equivalent wide-band interference is J  0  =  J /W. av  The received signal is despread, by correlating against p(i), and demodulated by correlating against \/2/T cos u . Thus, after every T seconds, the BPSK detector outputs b  0  b  r = dy/F + J + N; b  (2.3)  where d (= ± 1 ) is the data bit for the T second interval, and the interference and noise b  components are respectively: J=  ]/Y l b  "P{t)j(t)™su tdt 0  5  (2.4)  • N=J—  V <b  Jo  p(t)n(t) cosu tdt.  (2.5)  0  The white noise has zero mean and variance E[N } — N /2; while the interference has zero 2  0  mean, and in the limit of zero bandwidth, variance E[J ] = J /2. 2  0  The BPSK decision rule is to choose d — +1 if r > 0, and choose d = — 1 if r < 0. Assuming that d = ± 1 are transmitted with equal probability, one may take, without loss of generality, d = — 1; to compute the probability of bit error P . e  P = Pr{r > 0|d= - 1 } = P r { J + N > ^/F } e  b  (2.6)  With the statistics of the interference gaussian arid independent of the thermal noise statistics, the bit error probability is given by  * = Hv i5z) /  i  :  (2  7)  where erfc is the complementary error function. Therefore; as previously mentioned, the spreading does not improve the error rate performance of Coherent BPSK in white noise. However, the effects of the narrow-band interferer are reduced by a factor equal to the processing gain. To implement Forward Error Correction (FEC) encoding in conventional DS-SS, the data stream isfirstencoded to a higher rate symbol stream by block or by convolutional encoding; which is then transmitted by the same transmitter as in Figure 1. The receiver structure for coherent reception is also the same except that the integration is now over the symbol period; and the resulting stream of decision variables is used by a more general decision device to form an estimate of the original data stream. To increase the data rate without increasing the required transmission bandwidth, while maintaining the high interference rejection capability, one can use M-ary modulation, in which a signaling alphabet of M different code sequences is used to transmit alphabet symbols representing multiple bit sequences. One such method, which offers the performance advantages of conventional Af-ary DS-SS systems; but also many implementation advantages over other M-ary DS-SS systems, is the CPSK method described in the next section.  6  2.2 Code-Phase-Shift Keying DS-BPSK-SS In the CPSK method, each of the M = 2 , where the word length k is the number of bits k  per symbol, signaling waveforms is obtained by a different phase shift (an integer number of chips) of a single PN maximal length code sequence p(t). It's autocorrelation function is R(r) = ^  PiiTcMi  + r)T ) = {  G  »=o  '  *  -1,  c  ^  T  =  °' ' ^ G  otherwise.  """  (2-8)  ;  The transmitter, shown in Figure 2, groups the data into k-bit data symbols of duration T . Each of these are represented by an integer ra, 0 < m < M — 1, which is used to select 3  the signaling waveform p (t) = p(t — m T ); which is the phase shift by m = m(G+l) m  c  c  c  jM  chips of the non-shifted PN sequence p(t). The final up-conversion for transmission at carrier frequency u  results in transmitter output  0  s(t) = where P = E /T s  s  V2Pp (t)cosuj t; m  (2.9)  0  is the transmitter power, and E is the energy of the signal representing s  a symbol (a PN sequence).  d(t)  k  Serial to Parallel  /  /  Sequence  fc  S(t)  m  * Selector  M Bank of PN Sequences  VP COSCOJ  Figure 2 CPSK Transmitter For now, assume synchronization, so that the CPSK correlation receiver for coherent reception is as in Figure 3. The received signal, r(t) = s(t) +j(t) + n(t), is fed to a bank of M correlators, one for each alphabet member PN sequence p (t). m  When the m-th symbol  is sent, the output of the m—th correlator, after every symbol period, is m  r  —  \J E -\- J a  m  7  -f-  A^ j m  (2.10)  while the output of the other correlators, r{ for i ^ m, are r,- = -^y/£U  + Ji + Ni.  (2-11)  The noise and interference terms are (Vi | 0 < i < M — 1):  Ji -  J  (2.12)  Pi(t)j(t) cosu tdt 0  Ni = J — / \ +s Jo  pi(t)n(t) cos Lo t dt.  (2.13)  0  T_8  ()dt  P(t) 0  decision device and Mtok decode  ff()« T s  r(t)  kto 1 parallel to serial  d  © 2/XCOSC0fct  l  T_8 f  |()dt  Figure 3 Synchronized CPSK Receiver The decision device decides in favor of the symbol corresponding to the correlator with the largest output. When the interference is a single tone jammer at the carrier wave frequency, j(t) = Acos(u t + <f>), 0  (2.14)  the terms J, are equal for all i, and therefore do not affect the decision. Thus, the effects of a carrier-wave jammer are completely mitigated by CPSK signaling! When the single-tone interference is not precisely at the carrier-wave frequency, the decision is affected, and the noise performance of the receiver is degraded (but still much better than for conventional DS-SS). The analysis of this more complicated situation is left for Chapter 6.  The white noise terms are independent, zero-mean, gaussian random variables with variances E[Nf] = N /2; and therefore, when the spreading factor is much greater than 0  unity, G »  1, the probability of symbol error in AWGN, P , is precisely that for coherent e  reception of M orthogonal signals [4]: r+OO  P {M,E /N ) e  a  0  = l-  /  f{a-^E~ )[ s  J—oo  rot  \  f(8)dp) \J—oo J  (M-l)  da;  (2.15)  where (2.16)  E /N s  0  (dB)  Figure 4 Probability of Symbol Error vs. SNR for CPSK with Coherent Reception in AWGN 9  Figure 4 shows a plot of the probability of symbol error as a function of symbol signalto-noise ratio (SNR = E /N ) s  0  for several values of M.  Using the fact that an Af-ary  symbol represents k = log M bits, and that the energy of a bit is Ef, = E /k; the symbol 2  s  error probability as a function of symbol SNR can be converted to a bit error probability as a function of bit SNR. The BER (equal to the bit error probability), at a given bit signal-to-noise ratio decreases with increasing word length k. The power efficiency of a communication system operating at a certain BER is defined as the SNR required to attain the specified BER. The power efficiency of optimal coherent M-ary signaling for word length 1 is 3 dB poorer, for word length 2 is slightly poorer, and for word length 3 is better than that of coherent BPSK (at any BER). At word length 6, M-ary signaling outperforms BPSK by 3.5 dB at a BER of 10 . In other words, at word length 6, in thermal noise, CPSK outperforms -5  conventional DS-SS by 3.5 dB. The system discussed thus far is an idealization whose performance represents the upper limit which an implementation could realize. Synchronization of the receiver to the phase of the carrier wave, and to the time of the bit and chip intervals has been assumed for coherent reception. Hereafter, a set of synchronization modules are designed, and optimal correlators are approximated, to realize a complete receiver which approximates optimal coherent reception.  10  Chapter 3 The Modem Implementation on a DSP Platform 3.1 General Architecture and Implementation The development is aimed towards the construction of a wireless, high processing gain, high data throughput modem which transmits at radio frequency in an ISM band. (ISM bands are the industrial, scientific and medical bands in the gigahertz range over which unlicensed spread spectrum systems are employed.) See Figure 5 for the high level block diagram illustrating the general architecture. The signal processing unique to CPSK is done at the digital stage, which is implemented oh a general purpose DSP. To test this system, we have developed a prototype which operates at IF (chosen to be 140 MHz) thus allowing the performance to be evaluated by measurements taken with an RF channel simulator inserted into the IF link. An eventual RF modem could be built and on-air tested by integrating the present system with IF/RF up/down converters and RF transceivers. The general purpose DSP used is the QPC/C40B, built by Loughborough Sound Images, which is comprised of four T l TIM-40 modules, each of which hosts a Tl TMS320C40 and 96 kilowords of SRAM [5]. Of the four C40s; three are dedicated to the receiver, and one is dedicated to the transmitter. An optimizing C compiler along with a substantial run-time library has been purchased from 3L Software of Edinburgh [6]. However, the TMS320C40 C compiler does not produce satisfactory code for many of the time critical operations; as it does not seem to be aware of all'of the hardware — in particular, the circular addressing modes of the C40. Therefore, it was found necessary to code many of the software modules direcdy in TMS assembler. The code listings, (either in C40 C or assembler, depending on the module), are given in Appendix D.  11  RF/IF Converter & AGC  L„*-> Receive t Transmit  Quadrature Demod., LPF & ADC  Despread, Decode, Track, Acquire  t  t  IF LO  Data out  PN code  i  IF/RF Converter & Amplifier  QPSK Modulator  IF  Encode, Spread  Data in  digital  Figure 5 Wireless Spread-Spectrum Modem Block Diagram  3.2 The C40 Based IF Transmitter The digital modulator implementing the code-phase-shift keying, direct-sequence spreadspectrum signaling technique, as described in the previous chapter, uses a C40 to produce an asynchronous chip stream from the data file to be transmitted. During the transmission, the software is responsible for maintaining the C40 output communication port FIFO nonempty; while an interface reads from the C40 fifo and clocks the data into a level-shifter (converts TTL to bipolar) and amplifier. The resulting chip stream is then BPSK modulated onto the IF carrier by Mini-Circuits MIQY-140M quadrature modulator. This is followed by a bandpass LC filter (in-house constructed by the author due to the unavailability of an off-the-shelf unit) to remove the signal replicas produced at harmonics of the carrier by the modulator. See Figure 6 for the block diagram of the C40 based IF transmitter. The indicated modules are built on a PCB copperboard, and connected to the C40 by a high density, 0.025" pitch ribbon cable. A description and a circuit schematic for each of these modules is given in Appendix B . . ,  12  TMS'C40  1 chan Comm Port Q chan Interface  1 chan  ^—  Q chan  Level Shifter  &  Amplifier  1 chan BPSK Modulator and Q chan Bandpass Filter  RF  Figure 6 C40 Based IF Transmitter Block Diagram  3.3 The IF Receiver The incoming IF signal is product demodulated and low-pass filtered so as to recover the baseband signal. The BPSK product demodulation is done with Mini-Circuits MIQY-140D quadrature demodulator. The ensuing low-pass filter not only removes the second and higher harmonics of the IF signal resulting from the product operation; but has a bandwidth chosen low enough to maximize the output signal-to-noise ratio of the BPSK signal demodulator. This is discussed in detail in the next chapter. The baseband signal is sampled at twice the chipping rate (or four time the chipping rate with a two-sample preaccumulation) by a dual-channel 8-bit ADC. The samples are synchronously written to a bank of four FIFO memories, and asynchronously read from the FIFOs and written to the DSP by four FIFO/TMS320C40 communication ports. As explained more fully in the next section, for each channel of data (I or Q), the tracking algorithm requires the same channel of data delayed by one data symbol — resulting in a total of four data streams to be processed by the digital demodulator. Figure 7 shows the high-level block diagram of the IF receiver. It was prototyped by the author and built on a full size PC AT printed circuit board as documented in [7]. Each of the modules indicated in Figure 7 is described in detail, with circuit schematics, in Appendix C.  13  Reset and Go/Stop Control  C40 Comm Port 5 Reset  RF Signal  BPSK Signal Demodulator  C40 Comm Port 1  Port Arb. chan data  C40Comm Port 2 .  Data Read Control  Control  Q chan data  1  1 chan baseband • - • Q chan baseband  - — •  8 bit 1 channel A/D Converter  —  FIFO/TMS320C40 Communication Ports ( 4 )  Data  A/D Encode Signal  Local Oscillator •  ^  A/D Converter Control  TTL Clock Oscillator  Voltaqe Offset Control  •  8 bit Q channel ^  FIFO Memory (4 banks)  C40 Comm Port 3  J l cchan h l data Q chan data  C40 Comm Port 4  Figure 7 IF Receiver Block Diagram  3.4 The Digital Demodulator There are two primary methods of implementing a despreader for the standard DS/SS system: the code-matched filter and the serial correlator-accumulator technique. This is also the case in the CPSK signaling scheme, wherein the receiver employs a bank of correlators or matched filters — one for each of the possible phase shifts. In the code-matched filter technique, the entire reference PN sequence and each of its phase shifts corresponding to a data symbol are stored in separate length G registers; while the incoming signal samples are stored in another length G shift register. As the incoming signal moves chip by chip down the signal register, it will give a large positive correlation with one signal register when it contains a data symbol. In this method, no separate sequence acquisition is required, as the signal is acquired during the first complete symbol received. However, implementing this algorithm in software results in a prohibitively slow receiver because the cross-correlation between the signal sequence and each phase shifted PN sequence is computed once per chip. With a serial correlator-accumulator, one has an entire symbol period in which to compute the required cross correlations; and therefore we choose this technique, as it is appropriate for a DSP based implementation. 14  Figure 8 shows a block diagram of the digital receiver. The term m-correlator means a correlator which correlates against the PN sequence, p (t), m  representing the m-th data  symbol.  correlator slide  early m-correlator  timing decision device  late m-correlator J f sampled base-band signal  I m-correlator output  m  O-correlator  symbol decision device  1 -correlator  (M-l)-correlator  m  decode symbol  data out  [D~| = 1 symbol delay  Figure 8 Digital Demodulator Block Diagram Each correlator must process at the sampling rate (two times the chipping rate, R ); c  whereas the symbol decision device must process at the correlators output rate (the data symbol rate times the number of symbols).  With a fixed amount of processing power  available for correlation at a given PN sequence length, the maximum chipping rate which the system can handle is inversely proportional to the number of data symbols (the number of correlators); whereas the data rate is proportional to the symbol word length, k, times the chipping rate. Because the number of data symbols is 2 , the data rate, Rd, is given by k  R = d  K; ¥  (3-1)  for some constant K. Thus, the maximum data rate is obtained for word lengths 1 and 2. 15  Based on thisfiniteprocessing power performance consideration, we choose to implement the word length 1 and word length 2 versions on the DSP. By adding more processing power, one could maintain the chipping rate constant as one increases the data symbol alphabet length. This would give a data rate proportional to the word length. This could be done by adding more processors to the DSP, or by implementing the correlators in hardware, and using the DSP for processing the correlator bank output. The latter approach is taken in [8]; where a RAKE receiver for conventional DS-SS is designed. The three processors dedicated to the digital demodulator share the tasks indicated in Figure 8 as follows: Processor A implements the symbol decision device, the timing decision device, and the symbol decoder. Processor B implements the bank of punctual correlators. Processor D implements the early and late pair of correlators required for tracking. (Processor C is dedicated to transmission). The one symbol delay required for the input sample stream to the early/late correlator pair is implemented in hardware by a FIFO on the IF receiver. Processor A is the master processor which controls the two slave processors implementing correlators. It reads from, and configures the correlators; reading and updating the configuration at the data symbol rate.  3.5 The Tracking and Acquisition Algorithms The system is designed for packet transmission. After initialization, the receiver enters it's acquisition mode, to perform the initial PN code synchronization, and remains in this mode indefinitely until it successfully acquires a signal. It then enters it's tracking mode; during which it continually fine adjusts the symbol interval synchronization, and decodes and stores the incoming data. It remains in this mode until it loses lock — either because of excessive noise or because the signal transmission has ended. It then passes the data, stored in the DSP's on board memory, to the host computer. The program may then be restarted. Each data packet must have a preamble, of sufficient length (discussed later), consisting of a string of the zeroth data symbol. This is followed by a special data sequence to flag the end of the preamble and the beginning of the original data. The data is also terminated by the special sequence. The data passed to the host by the modem will consist of the portion of the preamble remaining after the receiver achieved acquisition, the encapsulated data packet, and perhaps several bits decoded from noise before the receiver lost lock. It is left to the host to extract the encapsulated data packet.  16  In the acquisition mode, the data symbol correlators are precessed by a shift of two samples, (one chip) between every trial symbol read. With reference to Figure 8, the symbol decision device chooses the correlator with the largest output and passes that output to the timing device, the timing device outputs the two-sample correlator precession, and the symbol decode is not invoked. The early/late pair of correlators compute a one sample early and a one sample late (called slides) version of the correlation (with precessed correlator) corresponding to the symbol which gave the largest correlation on the trial precession. When a data symbol correlator output crosses afirstthreshold, the timing device compares the early and late correlator outputs with the on-time correlator output, and the maximum of the three is checked against a second higher threshold. If it is crossed, the timing device adjusts the precessed (shifted) correlators according to the one sample slide adjustment and on the next trial symbol read, checks if the largest correlation crosses a third threshold. If the acquisition is confirmed, it switches to tracking mode; if the acquisition is not confirmed, it stays in acquisition mode — increments the precession and repeats the tests. In this way, the signal can be acquired in the presence of a timing error less than or equal to the maximum timing error that the tracking module can handle. See Figure 9 for the timing decision device's algorithm for acquisition. The CPSK signaling method is well suited to this acquisition scheme because all M data symbol correlators contribute to the search on every trial. Therefore, to precess through an entire PN sequence length G; takes only G/M trials. In other words, the acquisition time for the CPSK scheme is cut down from the standard acquisition time for conventional DS-SS by a factor of M.  17  W read correlators  punctual crosses threshold 1  choose max of early, late, punctual  yes  no no  precess correlators  max crosses threshold2  yes ^  adjust tracking  1  read correlators  max crosses threshold2  no  1 choose max of early, late, punctual  n  yes enter tracking mode  Figure 9 Timing Decision Algorithm in Acquisition Mode In tracking mode (refer to Figure 8), the symbol decision device chooses the correlator with the largest output and passes the symbol to the symbol decoder. This symbol also determines which shift of the PN sequence the early/late pair of correlators use for correlating against the one symbol delayed stream. If the early or the late correlator give a larger output than the punctual correlator, and the timing decision device has its flag raised for tracking adjustment in the corresponding direction, all the correlators are precessed by the plus one or minus one sample slide. If the flag was not up, it gets raised. If the punctual correlator gave the largest output, the flag is lowered. In other words, the correlators must indicate that the tracking must be adjusted in a particular direction twice in a row before the tracking adjustment is made. See Figure 10 for the timing device's tracking algorithm. It follows a similar algorithm to check for tracking loss..  18  The timing decision device checks for loss of lock by raising a flag if the maximum of the punctual, early, or late correlator output falls below a threshold. If the flag was already up, the tracking is declared to be lost. If the maximum of the punctual, early, or late correlator exceeds the threshold, the flag is lowered. That is, the maximum of the punctual, early, or late correlator outputs must fall below the threshold on two consecutive data symbols before the tracking is declared to be lost — at which point the reception is aborted, and the stored data is then passed to the host.  read correlators)-  early or late corr > punctual ? no 1 lower tflag  raise tflag yes adjust tracking  Figure 10 Timing Decision Algorithm for Tracking  3.6 DSP On Board Results Before inserting the IF link, the DSP software was tested on-board by having the digital transmitter communicate directly with the digital receiver. Besides providing a test of the software functionality, this allows determination of the maximum sampling rate which the receiver can handle. Also, timing error can be simulated in real time by adding or deleting samples from the transmitted data stream. The receiver acquires and decodes the otherwise noiseless transmission successfully for a timing slippage as high as 1 sample for every 4 data bits. Because there are 2G samples per data bit, this translates to a maximum timing slippage of 12.5/G percent.  19  Table 1 shows the maximum sampling rates in MSPS and the corresponding data rate in KBPS for spreading factors of G = 2 — 1, and word lengths 1 and 2, for single channel l  and complex channel processing.  k=l, single chan.  k=2, single chan  k=l, I+Q chan.  reg len 1 len G  MSPS  KBPS  MSPS  KBPS  MSPS  KBPS  3  7  1.45  104  0.80  114  0.70  100  4  15  1.96  65.3  1.02  68.0  0.92  61.3  5  31  2.33  37.6  1.16  37.4  1.06  34.2  6  63  2.57  20.4  1.24  19.7  1.15  18.3  7  127  2.70  10.6  1.28  10.1  1.19  9.4  8  255  2.77  5.4  1.30  5.1  1.22  4.8  9  511  2.81  2.7  1.32  2.6  1.24  2.4  10  1023  2.83  1.4  1.32  1.3  1.24  1.2  shift  PN seq  Table 1 Maximum sampling rates and the corresponding data rates The maximum chipping rate is determined by the speed at which the receiver DSP modules can process. For word lengths of 1 or 2, and with G larger than the threshold value of 63, the inner kernel of the code implementing a correlator is the bottleneck. For G smaller than the threshold value, the bottleneck becomes the "intelligent" process which accepts the correlator outputs. We have not determined how much this threshold value of the spreading factor increases for word lengths higher than 2.  20  3.7 Experimental Setup  Host PC 486DX4/100 i r  Marconi 2022D Signal Generator  Marconi 2031 Signal Generator  DSP QPC/C40B  IF  IF  transmitter  receiver  H-P 8656B Signal Generator  KAY 437A Attenuator  Wandel & Goltermannl White Noise Genertor (6 KHz - 25 MHz)  Mini-Circuits MCL SBL-1 Mixer  Mini-Circuits ZSC-2-1 Summer/Splitter  Mini-Circuits ZHL-2-8 Amp. (28 dB)  Figure 11 Experimental Setup for Measuring BER in AWGN The DSP is a full-sized PC AT card residing in a 16 bit expansion slot of the host 486 PC. It communicates with the IF transmitter and the IF receiver via the C40's 8-bit high speed parallel communication ports.  21  The Marconi 2022D signal generator provides the 140 MHz LO for the IF transmitter; while the Marconi 2031 signal generator provides the 140 MHz LO for the IF receiver. It should be stressed that the IF transmitter and the IF receiver are each driven by their own TTL clock oscillator as well; rendering them independent. The IF transmitter produces a 2.9 dBm double-sideband-suppressed-carrier signal centered at 140 MHz, which is further attenuated by 30 to 50 dB, by the KAY 437A step attenuator. This signal is summed with the AWGN by Mini-Circuit's two-way, 0 degrees, ZSC-2-1 Summer/Splitter. The AWGN is produced at baseband by the Wandel & Goltermann White Noise Generator; and is mixed up to the frequency range of the data transmission by Mini-Circuit's MCL SBL-1 frequency mixer, whose LO is provided by the Hewlett-Packard 8656B signal generator. The total signal (data plus noise), is brought back up in strength by 28 dB at the IF receiver front-end. The signal-to-noise power measurements were made at the IF receiver front-end with the Tektronix 497P Spectrum Analyser. The BER measurements were made by having the transmitter send a simple pattern of data bits (therefore, essentially random pattern of chips) and having the receiver operate like a BER analyser. It triggers on the first non-zero symbol, and counts the times that the decoded symbol stream does not match the pattern.  22  Chapter 4 Steady-State Performance of the Coherent Receiver 4.1 Approximating The Optimal Correlator In the DSP based implementation of the CPSK receiver, the baseband signal is sampled at twice the chipping rate, and the 2G samples representing a data symbol are correlated by an add and accumulate operation. Thus the integration in Figure 3 is approximated by a summation, and the optimal correlator is roughly approximated. To improve the approximation, we low-passfilterthe baseband signal, y(t), before sampling it; and therefore, approximate the ideal analog correlator of Figure 12 by the combination of analogfilterand digital correlator in Figure 13.  y(t)  ]()dt J  p(t) m  m  Figure 12 Analog Correlator  y(t)  „ LPF  ^  sample  Z  •  1  2G 0  1=0  1  p(t.) Figure 13 Analog Filter with Digital Correlator The resolution of the tracking scheme is one sampling interval, so that the position in the chipping interval of the pair of samples for one chip is a random variable. The purpose of this chapter is to show how the cut-off frequency of the low-pass filter (which filters the chips) can be chosen so as to maximize the output signal-to-noise ratio of the digital correlator for a PN sequence of chips.  23  The output signal-to-noise ratio of afilteror correlator, S N R , at time T, is defined as 0  the ratio of the instantaneous power of the output signal, -r (T), to the average power in 0  output noise n (t): 0  \ro(T)\ ' 2  SNR =  1  0  y  .  (4.1)  A matchedfilteror correlator, optimizes this ratio to the value for coherent reception: SNR , 0  o;)<  IE = ^ .  (4.2)  We take the low-passfilterof Figure 13 to befirstorder RC; thus, with transfer function given by  W  = i + 7 W  )  (  4  '  3  )  where the 3-dB bandwidth of the filter, f , is given by c  >« = ds?-  -  (4 4)  We, require the output SNR of the digital correlator for the reception of 2G samples of the LPF output correlated against the PN sequence, p (£,•), which takes values ± 1 . Start by m  calculating the output noise power M . 0  '  The ith sample of the low-pass filtered noise is +oo h(r)n(t - T)<1T;  n,:  (4.5)  l  / •00  where h(r) is the impulse response of the LPF. Since the noise output is Yli=o Pm(U)ni, the average output noise power, obtained by taking the expectation of the noise output squared, is 2G  •  2G  K = ^2^2pm{ti)pm(t )E[n n }. i=0 j-0 J  Using (4.5), the expectation E[n(ti)n(tj)]  i  (4.6)  :J  = \N 8(ti - tj), and the fact that h(r) is the 0  fourier transform of H(f); leads to E[n \ inj  = |w / e- ^-*l.  (4.7)  2  0  c  Since the cutoff frequency, f , is the same order of magnitude as T c  _ 1 c  , and for i ^  j,  \tj — U\ > T /2, the terms for which i = j are dominant. Furthermore, most of the terms c  24  in the sum (4.6) cancel for i ^ j; therefore, the sum (4.6) is approximately given by the sum of the i = j terms: Af = 0  irGN f  (4.8)  0 c  To calculate the output signal power of thefilter/correlator,we first need the sampled response of the LPF to a square pulse chip of duration T and amplitude A, as shown c  in Figure 14. The time origin is indicated by the circle, and the two sampling instances are indicated by the crosses. Let r be the time, as measured from the origin, of the first sampling instance. The second sampling instance occurs at time r + T /2. c  Let St be the  time interval from the rising edge of the square pulse to the time origin. The tracking scheme (next chapter) keeps the sampling times synchronized to the chip intervals, to within 1 sampling interval, by maintaining maximum signal power. Therefore r takes a random value uniformly distributed in the interval [0,^T ]. C  +A  V  5 t /  /  T  -A Figure 14 LPF Response To a Square Pulse Chip St is determined by demanding that the well-known exponential solution to the first order RC circuit go from —A to 0 in time St: 0 = -A + 2A(l-e- ^ y, s  Rc  (4.9)  which solves, using (4.4), for St to In 2 St = ^ - r . 2TT/  25  C  , (4.10)  The sampled response, S (T) of the LPF to the chip, is the sum of the LPF output at C  the two sampling times: W ) "  \A(c - - -l)c-^, 6  forr€[Jr -ft,ir ];  6  C  where 6 is defined to be b = irf T . c  c  ( 4  c  "  U )  To obtain an approximate expression for r (T), the  c  0  response of the correlator to a synchronized (to within a sampling interval) PN sequence, we make use of (4.11) along with some of the general properties of maximal length PN sequences. We will assume that the LPF response to chips which are preceded by a chip of the same polarity is ±A.  In other words, that the LPF output essentially reaches the  voltage of the input when the input is held constant for longer than a chip duration. Once the LPF cut-off frequency is found, it can be checked that this assumption is consistent with the solution. One quarter of the chips of a maximal length PN sequence (of length G) are included in run lengths of 1; and there are G/4 runs of length greater than 1. Therefore, since 3G/4 chips are members of a run length greater than 1, and G / 4 chips begin such a run length, there are G/2 chips preceded by a chip of the same polarity; and therefore the sampled signal strength of G/2 chips is approximately ±2A. The Gj\ chips that immediately follow a greater than length 1 run length have the signal strength magnitude depicted in Figure 15 and given exactly by (4.11). The G/4 chips that immediately follow a run length of 1 have a signal strength magnitude approximately given by (4.11). Therefore, since multiplication by the synchronized PN sequence gives all the samples positive polarity, the output of the digital correlator is approximately r (T) = 0  ±G(s (T)  2A).  +  C  (4.12)  It remains to average the output SNR of equation (4.1) over the random variable r. From (4.2) it follows immediately that 2A T =- ^ A 2  S  SNR  0>opt  (4.13)  So that with (4.12) and (4.8) substituted into (4.1), we have the ratio of the average output signal-to-noise ratio of the digital correlator, S N R , to the output signal-to-noise ratio of an 0  ideal analog correlator, S N R  0)0;)  i: SNR  SNR  0  _ (i(2'+ (r)))  2  ge  2b  0 ) 0 p t  26  [  •  1  where the indicated average is with respect to r, and S (T) is given by (4.11) with A set C  to unity. The average of S (T) with respect to r is C  ^ and the average of  ( i . - )  2  +  ^  ;  ( 4  ,  5 )  with respect to r is  SI(.T)  4 = 4 ( l - -f^j + 1 ( l O e l  + 14e-  26  3ft  - e~* - 4 ) . b  (4.16)  Substitution pf these last 2 equations into (4.14) yields the ratio of SNR's as a function of b = 7r/ r for the received data symbol. c  c  The optimization of (4.14) with respect to b is not well defined because the signal strength A was assigned to one half of the chips, when really these strengths should be subject to the optimization as well. Instead we optimize, with respect to b, the ratio of the average output SNR of the LPF due to the chip of Figure 14 to the output SNR of a filter matched to the chip. This ratio is given by: S N R ^ h f r SNR  0 j m a  =  (S (T)) C  <  _  ^  2b  and is plotted in Figure 15. Optimizing the ratio (4.17) with respect to b yields an optimal value for the chip of b = 2,28;.  (4.18)  which, when substituted into (4.14) for the symbol, yields S  N  SNR  R  o  0 j 0  pi  0.63 = - 2 . 0 dB.  •  (4.19)  The optimal value of b, as given_by (4.18), corresponds to the first order RC LPF cut-off frequency f  = 0.73T" .. 1  c  The extremely complicated complete optimization problem has here been simplified to something tractable by the approximations made above.  Thus both the optimum value  of the LPF cut-off frequency, and the performance degradation of - 2 . 0 dB incurred by approximating the matched filter by the LPF followed by the digital correlator, should only be viewed as reasonable estimates. Experimentation with the hardware of the implementation 27  has lead us to the approximate optimal value of f = 0.5T" for which we have found an 1  c  SNR degradation of only 0.8 ± 0.4 dB. By doubling the sampling rate and performing a two-sample preaccumulation, we find an SNR degradation of only 0.45 ± 0.4 dB.  SNR., SNRo,,  1.5  2  2.5  3  3.5  4  rcfcT  c  Figure 15 Signal-to-Noise Ratio for a Sampled Low-Pass Filtered Chip as a Function of L P F Cut-off Frequency  4.2 BER Performance In The Presence of Timing Slippage In this chapter, we evaluate the B E R in A W G N performance degradation for coherent reception, due to the fact that the receiver is not always exactly on track, even to within the one sample timing resolution. Recall from chapter 3 that at every data symbol interval, the output signal strength of the correlator corresponding to the data symbol being received is compared to the output signal strength of the corresponding correlator synchronized to the signal delayed by one sampling interval, and to the output signal strength of the corresponding correlator synchronized to the signal advanced by one sampling interval. If the delayed or advanced correlator has a higher output than the oh-time correlator, the sample stream is shifted with respect to the on-time correlator appropriately. Let So denote the state in which the receiver is synchronized to within the one sample resolution; S\ denote the state in which the receiver synchronization is off by one sample; and S2 denote the state in which the receiver synchronization is off by more than one sample. 28  The receiver tests for state S2 by checking if the signal strengths of the on-time, delayed, and advanced correlators all fall below a threshold. If it tests positive for state S2, the receiver leaves its tracking and data decoding mode and returns to the state in which it is searching for a new transmission. When the receiver is in state 5*2, the probability of exiting the tracking/data decoding mode is very high, so that the probability of state S2 is very low; and we approximate the problem by assuming that the probability of state .92 is zero. We have checked this approximation, in the absence of timing slippage, by including state £2 in the analysis, and have obtained the same result as that of the following calculation. Therefore, we approximate the receiver when it is in tracking/data decoding mode by the two-state Markov chain depicted in Figure 16. The solution for the two-state chain state  Figure 16 Two-State Markov Chain probabilities, Po, Pi, as functions of the state-transition probabilities P^j, can be obtained from the detailed balance equations PoPo,i = PiPi,o1  Po 1 +  Pl =  ,  ^0,1/^1,0  (4.20)  1. .  1 + /V0//V1  Let BERo and B E R i denote the bit-error rates when the receiver is in state So and Si, respectively. Then the average bit-error rate is given by B E R = BERnPo + B E R i P i .  (4.2T  We take the word length 1 case, so that B E R Q is the ideal B E R given by (2.15) for the M=  2 case:  . ' . . BER,  = P« = l e r f c  29  U  §  -  (4.22)  The correlator output is down by a factor of approximately 3 dB when the receiver is 1/2 chip off-track; therefore B E R i is given by the expression for BERo with 6 dB less SNR. It remains to determine the state-transition probabilities. The transition probability from state So to state S\, Po,i> has two components. One is due to the A W G N which can cause the output signal strength in either the early or the late correlator to be greater than that of the on-time correlator, even though the receiver is actually on track. The other is due to a drift of the chip time interval of the transmitted stream relative to the sampling times of the receiver. The latter, for stationary transmitter and receiver, is due to a frequency difference of the transmitter's and receiver's T T L clock oscillator. Let N^/  2  denote the number of data bits received in the mean time, t j , that it A  2  takes the receiver's clock to drift by one sampling interval relative to the transmitter's clock. The component of Po,i due to the clock drift is equal to l/N-y^. Let A denote the percent frequency difference between the two clock oscillators: A = 1/r ~ ft  (4.23)  fr  where f and ft are the receiver and transmitter clock frequencies, respectively. Then T  1  (4.24)  2GA  To determine the component of Po,i due to the A W G N , we need the probability, po,i, that the output, ro, of the on-time correlator corresponding to the received data symbol is less than the output, r\/ , 2  of the corresponding correlator which is displaced by 1/2 a  chipping interval (one sampling interval) from the received data symbol. To obtain this probability, it is convenient to consider the embedding G-dimensional vector signal space with the orthonormal basis consisting of the normalized maximal length P N sequence and it's G — 1 code-phase-shifted versions. Let so, 5*1/2,  a n  d -si denote the on-time, 1/2 chip  displaced, and 1 chip displaced signals, respectively. Since all the vector signals have length  30  y/E~ , s • .si = 0, and sb • J*j/ s  0  ' ^1/2  = 2  the signal space in the  =  SQ,SI  plane is  as in Figure 17.  rotate  and  |  translate  ?1  °1/2  VEs/2  So  ^E,/2  Figure 17 Signal Space for Tracking Performance Calculation For coherent reception, Figure 17 makes it clear that given that 5*0 is sent, the probability that the vector received is closer to .s*i/ is 2  (4.25) The way that the state-transition probability Po,i is related to po,i is dependent on the tracking algorithm. Recall that there are two components: P , i = 2 ( , i ) + (/Vi/2 2  0  P o  (4.26)  In the term due to the A W G N , the square is taken because the test for tracking in a particular direction must pass twice in a row on consecutive data bits before the tracking adjustment is made; and the factor of 2 is due to the fact that a tracking error can be made in either direction. Given that we are in state S\, to return to state So, the output of the correlator synchronized to the signal (an early or late correlator) must exceed the output of the correlator which is half a chip displaced (the correlator which is the on-time correlator when the receiver is on track). The probability of this occurring is 1 — po,i; and it must occur twice in a row before the tracker acts, therefore = (1 31  P0,l) •  (4-27)  Equations (5.1) through (5.8) give the complete solution to the problem of determining the B E R in A W G N with timing error. Figure 18 shows a plot of the B E R as a function of the SNR for single-channel, word length 1, coherent reception with a particular choice of parameters. The ideal bit error rate is given by (5.3) and is plotted for comparison. With tracking in the presence of zero timing slippage there is a B E R degradation corresponding to 0.35 dB at low SNRs up to about 13 dB, that increases to .5 dB at an SNR of 16 dB. With finite timing slippage, the performance depends on the spreading factor. The curve for the G = 63 P N sequence is shown for the case of timing slippage A = 5 x 10~ , and for the 6  case of a timing slippage of A = 5 x 1 0 , which is typical between a pair of TTL clock - 7  oscillators. Over the relevant SNR range for data transmission, and the above spreading factor, it is not until.the B E R of 6 x 10~ for A = 5 x 10~ , and the B E R of 2 x 1 0 6  6  - 7  for A = 5 x 10~ , that the timing slippage induces a performance degradation of 1 dB. At 7  low SNR, the performance degradation, although practically negligible, is due entirely to the tracking errors caused by the noise. At high SNR the performance degradation is due almost entirely to the timing slippage.  32  E /N s  (dB)  0  Figure 18 B E R Performance in A W G N with Tracking  4.3 Experimental B E R in A W G N Performance with Carrier-Wave Synchronization Imposed Externally The experimental results reported in this chapter were obtained by making a two-way, zero-degree split of the 140MHz Marconi 2031 signal generator output to provide the IF receiver and IF transmitter with the same LO. In addition to providing a test of the acquisition, tracking, and decoding algorithms, the reason for doing this is that it provides the B E R performance limit for the present system upgraded to solve the carrier-wave synchronization problem (which we do in the next chapter). The approximation to optimal coherent reception thus far is quantified, allowing us to identify the additional performance degradation from optimal incurred by our solution to the carrier-wave synchronization problem. We have carefully checked that the B E R performance of the word length 1, and word length 2, CPSK transmissions does not depend on the spreading factor G. Each point on the graph of Figure 19 represents the results of 25 measurements; 5 measurements at each  33  of the 5 spreading factors G = 7,15,31, 63,127. For comparison, the B E R versus SNR curves for theoretical; optimal reception of M-ary signals for M = 2, and M = 4 are given on the same graph. In the B E R range from 10~ to 5 x 10~ the implementation loss is 0.8 dB; of which we 3  5  identify 0.35 dB as due to the effect of noise on tracking, and 0.45 dB as due to approximating the optimal correlator. As the BER's decrease from 5 x 10~ to 10~ the loss increases by 5  7  another 0.2 dB; which we ascribe to a combination of intrinsic receiver noise and timing slippage. The experimental uncertainty on the SNR is approximately ±0.4 dB overall. The increments between the experimental SNR values have negligible experimental uncertainty. In other words, the shape of the experimental curves have very little uncertainty; but their horizontal placement is uncertain by 0.4 dB.  10^  F  '  •j 0" I 9.0 8  f""  •  1  10.0  '  '  1  •  I  11.0  '.  —.  '  1  I  . 12.0  '  1  .  J  13.0  :  1  .  1  I  .14.0  .  I  15.0  E_s/N_o (dB) Figure 19 Bit Error Rate vs Signal-to-Noise Ratio for M=2 and M=4 CPSK with Carrier-Wave Synchronization Imposed Externally  34  3  '  1  _.  I  16.0  Chapter 5 Solving the Carrier-Wave Synchronization Problem by PIR for CPSK 5.1 Phase-Invariant Reception Phase-Invariant Reception is a technique for demodulating a complex baseband data stream which does not require an estimate of the degree to which the I and Q channels have been rotated into one-another by the down-conversion from RF. It requires that the phase angle between the received complex RF signal and the local oscillator of the receiver be fairly constant over the duration of a data symbol. We first assume it to be exactly constant, and in a later section quantify the SNR degradation when it varies with time.  d(t)  d(t)  Serial to Parallel  K //  ^  Sequence Selector M Bank of PN Sequences  Serial to Parallel  Serial to Parallel  k  VP coscoJ  Sequence Selector  /  IP) VPsincOot  Figure 20 Quadrature CPSK Transmitter  35  s(t)  ©  <2fT. C0SC0 t o  rm.l .  T_s.  f  J()d»  ) r(t)  ' i1  m r  J()dl  m,Q  ^sincc^t  Figure 21 Quadrature Demodulation followed by Complex Correlation Quadrature RF transmission for CPSK is realized with the transmitter of Figure 20; which is basically two copies, in quadrature, of the transmitter in Figure 2. The corresponding receiver is as in Figure 3, except that the RF demodulation produces a complex signal (with I and Q components) which is fed to a bank of correlators, each of which having two identical arms. Figure 21 shows the complex signal resulting from quadrature RF demodulation, and the ensuing complex correlator. The signal received at the demodulator now has both I and Q components: s(t)  where pj and q P  = V2P (t)  cos(u t  Pl  0  + 0) + V2Pp (t) Q  sin(w i + 0); 0  (5.1)  are the PN sequences representing the I and Q channel data symbols  respectively, and P is the power of the transmission dedicated to a single channel. 0 is the phase angle difference between the carrier and the local oscillator of the receiver. The I and Q channel outputs of the quadrature demodulator, neglecting the double frequency components which get filtered off anyway, are obtained by multiplication by i / 2 / T s cos Lo t, and ^/2/T 0  s  smu> t, respectively: 0  Pl(t) cos 6 + pq(t)  /(*)  Q(t) --  T,  -P!(t)  sin 0 + p (t) Q  36  sin 0);  cos 0).  ;s.2)  Then the complex output, f  m  cation by p (t),  = ( r / , r g ) , of the m'th correlator is formed by multiplimj  m j  followed integration over the symbol period:  m  rr m  m,Q  r  =  "El  (c ,i cos 0 + c Q sin 6); m  G  m>  (-c j  sin 0 + c Q cos 9);  m  G  (5.3)  m>  where c / (C Q) is the correlation between the m'th P N sequence and the PN sequencem>  TOJ  which represents the I (Q) channel data symbol. For. the synchronized system, c / equals m>  G or —1, depending on whether the I channel carries the m'th data symbol or not, (and similarly for c g ) . m  For the time being, consider the word length 1 case, and form the following two quantities which are invariant with respect to the phase rotation 0: h = ^ W , / + 4 Q - K / + r; )); i 0  (  5  4  )  g = - n y n . Q + Q,Q lJr  r  2h is the magnitude squared of the 0 correlator minus the magnitude squared of the 1 correlator; while g is the dot product of the 0 correlator with the rotation by 90 degrees of the 1 correlator. It is easy to check that when the (I,Q) dibit is received in the absence of interference and noise, that the invariants take the values shown in the Table 2. Therefore, d,Q)  g  h  h-g  (0,0)  0  +k  +k  +k  (0,1)  -k  0  +k  -k  (1,0)  +k  0  -k  +k  (1,1)  o  -k  -k  -k  .  g+h  Table 2 Decision Variables for Phase-Invariant Decoding g —h and g+h are the appropriate decision variables for the I and Q channel bits, respectively. For higher word lengths, one way of generalizing this scheme would be to first choose the two correlator outputs of the largest squared magnitude, and then apply the described scheme to decide on the I and Q channel data symbols. For single-channel (real) data transmission, the,same data symbol would be sent over the l a n d Q channel, and the decision variable  37  would simply be h. In this case, the generalization to higher word lengths is immediate: the decision variables are the magnitudes squared of the complex correlator outputs. The local oscillator of the receiver's IF to baseband demodulator runs freely at its nominal frequency LO . With the conventional direct-sequence spread-spectrum demodulator with a 0  free local oscillator, it is necessary to track the phase error because the decision variable for the two data symbols is based on the output of one complex correlator. The two data symbols (corresponding to bit 0 or bit 1) are 180 degree shifts in the I-Q plane of one another. PIR is possible for the CPSK method because different data symbols correspond to different complex correlators. In the next two sections we derive the BER performance of this technique in A W G N . To show that the decision variables continue to be independent of the phase rotation, it is convenient to represent the noise by the narrow-band representation: n(t) = n/(£) cos(cu t + 9) — nq(t) sin(o> £ + 9). 0  (5-5)  0  The I and Q channel quadrature demodulator outputs become 1  \  .  sin 9:  This form makes it evident that if the decision variables are independent of 9 in the absence of noise (which they are), then they are independent of 9 in the presence of noise as well.  5.2 BER For Real Data over the Complex Channel with AWGN — Theoretical Analysis and Experimental Results By real data over the complex channel, we mean quadrature transmission with the same data symbol in each channel. We will first calculate the.BER in A W G N for the M = 2 case. From this we will obtain a bound on the SER (data symbol error rate) for arbitrary M by means of the union bound for probability. Recall that for Phase-Invariant Reception, the decision variables are the magnitudes of the complex correlators.  38  In the last section it was shown that for PIR, that the phase angle 9 can be taken to be zero; so that for spreading factor, G, much greater than unity, the reception of the zeroth symbol results in the correlator output: r ,i = y/E~ + N 0  a  Q>I  + N ,Q  ro,Q = \fE~  s  n,i =  ^  0  N  ltI  ri,Q = N ] 1>Q  where E  = Ep/2, and the noise components are:  s  J  Ni = h  pi(t)ri(t) cos io tdt 0  2  i,Q =  N  (5.1  Pi{t)n{t)smuj tdt. 0  ±b Jo  These are independent gaussian random variables with zero mean and deviation a = N /.2. 2  0  For equally likely transmission of a zero or a one, the probability of error is equal to the probability of error conditioned on the reception of a zero: P (2,E /N ) c  b  =  o  Pv{\r \<\r,\} 0  /|f, i-|fbi ( « ) « « ;  where | r | = ^ ' o , ; + o,Q' 1^1 r  y/ \,i  =  r  0  i,Q>  +  r  a  n  f\fi\-\r \  d  0  i s  t h e  probability density  function for | n | — |rb|By going to polar coordinates: r%,i = |r*i| cos 9i, (5-10) i'i,Q = \ri\sin 9 ] l  the square-law transformation for random variables, which gives the probability density for \n\ in terms of the probability density for / | f l ( ) = f Jo ' / ' ' i ( I 0, a  a  is obtained: a c o s J  '  a s i n  *)^'  for a > 0; . for a < 0.  Since the probability density functions for ri are:  (5.12) .M(«i,a ) = 4 r " e  (  c  v  2  39  M  /  A  r  °;  the probability densities for  are:  1  rl-K  /|.|(a) = 4r  •  /  f  e-« -v^) +(- ^-^) )/^^ acose  2  i  2  tt  ;  (5.13)  The general result for the. difference of two independent random variables, in the present notation, is r+oo  /|*H?o|(«)= /  Jo  /|f,|(«  +  (5-14)  ^ ) / | f b | ( ^ ) ^ -  The probability of error is given by (5.13) substituted into ,(5.14), substituted into (5.9). The resulting triple integral can be reduced to the following single integral: -2E /N b  P (2,E /N )= i  b  0  0  ^  /  d6[l  (5.15)  We have evaluated this integral numerically with Maple V, and plotted the BER (= P ) t  has a function of the SNR (E /-N ). b  0  The theoretical curve is shown in Figure 22. For  comparison, the curve for coherent reception (the best performance theoretically possible) of two orthogonal signals is given on the same graph. At zero frequency difference, (df = 0), between the carrier wave and the local oscillator of the receiver; at a BER of 1 0 , -3  PIR is 1.1 dB less efficient than coherent reception; at a BER of 1 0 , PIR is 0.5 dB less -8  efficient than coherent reception. In the limit of infinite SNR, the BER performance in noise of PIR approaches that of coherent reception. The reason that PIR does not do as well as coherent reception, is that the PIR decision variables are quadratics of the decision variables for coherent reception. The measured curve for df = 0 is shown as well; exhibiting an implementation loss, with respect to theoretical PIR, of 0.8 dB at the BER of 1 0 , and a loss of 1.1 dB at the BER -3  of 1 0 . The total implementation loss with respect to coherent reception is approximately -6  constant at 1.8 dB for any BER. The BER measurements were obtained by the experimental setup described in chapter 3.  Each point represents 20 measurements, all taken with a  spreading factor of 63.  40  In the next section, the performance degradation of a function of df is obtained analytically. Figure 22 also shows the experimental curve at the value of df found to give a signal-to-noise degradation of 1 d B . The union bound gives an upper limit for the B E R , in A W G N , of M-ary orthogonal signaling in terms of the B E R for the M — 2 case. The symbol error rate, P , when all M e  signals are equally likely to be sent is  P (M, E /N ) e  s  0  < (M — 1)P (2, E /N ). £  s  0  ,  (5.16)  In the case of coherent reception, the union bound upper limit becomes equality to within a percent for SERs lower than 1 0 . - 4  Also, in this S E R range, the S E R vs. S N R curves (see  Figure 4) become practically straight lines (on the linear-log plot). Therefore, for this range of SERs, the power efficiency loss of PIR relative to coherent reception is no greater than the relative loss in the word length 1 case.  41  10"  1  10" I 8.0 9  •  "  9.0  -•  i  10.0  .  i  ,  11.0  i  ,  12.0 E_b/N_o  i  13.0  ,  i  14.0  .  i  15.0  ,  I 16.0  (dB)  Figure 22 B E R vs. Signal to Noise Ratio for PIR with Real Data over Complex Channel, Word Length 1  5 . 3 BER Performance of PIR for Time Varying Phase In this section we examine the effective loss in signal-to-noise ratio as a function of the difference in frequency between the carrier-wave and the local oscillator of the receiver for real data transmission. The quadrature demodulator output is given by (5.2), except that now 9 is a function of time. Let duj denote the difference in angular frequency between the carrier-wave and  42  the local oscillator of the demodulator. With 6 — dut, the I and Q channel outputs of the quadrature demodulator are: I(t) = ——p (t)(cos divt + sin divt) m  ' ^ •' • Q(t) = ——p (t)(cos duit — sin dut;) ,  (5-17)  m  J- s  where p (t) is the symbol being received. m  Let 8 denote the percentage of the chipping frequency by which the carrier-wave and local oscillator differ in frequency: du =  oto  c  2TT8  = -pfr-  .•  (5.18)  J- c  Then, provided that we have PN code alignment, with the integral of the correlator approximated by a sum over chipping times, the output of the mth correlator due to the information-bearing part of the incoming signal is: I'm,I  =  Q  (cos(27ri<5) + sin(27ric?))  S  (  r ,Q m  8  '  1  9  )  = —^r- ^ ( c o s ( 2 7 r i < 5 ) - sm(2ir i8)).  Therefore, the magnitude squared of the mth correlator (equal to the effective bit energy) is r m, 2  ,l + r ,Q = E k(G,8); 2  m  l  (5.20)  where C7-1  G-l  KG, s) = — E co<2<* 2  J  i=0 j-0  (5-21)  •  k(G,8) is the ratio of the signal-to-noise ratio that the decision device uses, S N R , to 0  the signal-to-noise ratio of the signal at the receiver front end, SNR. *«™ = H .  (5-22)  Figure 23 shows a plot of k (in dB) as a function of 8 for the case G = 63. The curve shows that the output S N R is down from the received S N R by 1 dB at the value of delta equal to 4 x 1 0 . We have confirmed this using fslove of Maple V . At a chipping rate of 0.5 M H z - 3  (the rate supported by the implementation), this corresponds to a frequency difference of 43  df=0.0021 MHz. We have also measured the B E R at this frequency difference between the stationary transmitter's L O and stationary receiver's LO. The experimental curve is shown in Figure 22 of the previous section. To within experimental uncertainty, the B E R degradation is indeed 1 dB. The frequency difference corresponding to a 1 dB degradation is 15 ppm. Commercial oscillators are available at 140 M H z that are accurate to within 15 ppm. For example, the Raltron V C O H F series 6700. The degradation of the SNR with increasing 6 here presented is not unique to PhaseInvariant Reception. Other systems we have found [9] which demodulate the carrier with a local oscillator at the nominal carrier frequency (ie. not a phase-locked loop), estimate the phase rotation 0, and rotate the complex demodulator output so as to remove the phase rotation from the decision variables. However, all such systems which only update the phase rotation estimate at the data rate, and not at the chipping rate, (these include the implementations [9] and [10]), suffer precisely the effective SNR loss herein calculated.  44  0  -11 SNR SNR  0  (dB)  I—i—i—i—i—i—i—i—i—i—i—'—'—i—i—i—i—'—'—i—i—'—'—iii.'—i—i—i—i—i—i—i—•—i—i—i—•—i-  0  1  2  3 ^  4  5  6  7  (x1E-3)  Figure 23 Output SNR As a Function of Rx and Tx L O Frequency Difference 8 = df/f  c  5.4 BER For Complex Data Flow with AWGN As of this writing, we have not obtained an analytical expression for the BER in A W G N for PIR with independent I and Q channel data streams. Thus we rely on the experimental curve, and compare it to the theoretical curve for coherent reception for the case in which each channel carries one of two possible orthogonal signals. We refer to the data encoding for this scenario as complex word length 1 encoding. First we outline the as of yet to be solved problem for the theoretical BER. Suppose the dibit (0,0) is transmitted. Referring to the decoding table of figure (23), one sees that it is correctly decoded iff g — h < 0 and g + h > 0; that is iff — h < g < +h. The probability, P , of this occurring is c  P = / c  Ja=0  da /  d/?/ (a)/ (/3|h = a); h  Jp=-a  45  g  (5.23)  where /h(a) is the pdf for h, and / (/?|h" = a) is the pdf for g conditioned on h. h and g  g are given by (5.4). One approach to deriving the conditional pdf for g is to transform to polar coordinates, (5.10), as was done to obtain the square-law transformation (5.11). The random variable  = |n|-\A* +  g conditioned on h becomes g\h=  a  l "^! 7  2  sm  ($o —  Derivation of a pdf for  this function requires finding the inverse of the function f(r) = ir\/a + r — a problem we 2  have not yet solved. However, we do have the measured, BER vs. SNR curve from which to evaluate the noise performance. The theoretical performance upper limit for quadrature transmission of two independent data streams, each of which carries orthogonal symbols from an alphabet of length 2, is given by coherent reception. In this case, the I-channel decision is independent of the Q-chanhel decision. The probability of a correct decision in one channel is 1 — P ; with P given e  e  by (4.22). The probability of a correct decision for a symbol representing an (I,Q) dibit is (1 — P ) . Therefore, the symbol error rate is 2  e  SER = 1 - (1 - I',) . 1  -(5.24)  Figure 24 shows the experimental SER has function of the SNR for PIR of complex data flow in A W G N ; and the theoretical SER for coherent reception from the same transmission. To achieve an SER of 1 0  - 3  requires 3.0 dB more signal power for experimental PIR than  for theoretical coherent reception. At an SER of 10~ , the loss is 3.4 dB. Provided that the 6  implementation loss with respect to theoretical PIR is the same as the implementation loss for real data flow over the complex channel (Figure 22), we deduce that PIR is approximately 2.2 dB less power efficient than coherent reception for quadrature data transmission. Over the same SER range, for real data flow over the complex channel, PIR is approximately 0.9 dB less efficient than coherent reception (see Section 7.2). With coherent reception, going from single-channel to dual-channel transmission entails doubling the data rate and doubling the transmission power and achieving the same BER. With PIR, doubling the data rate by going to complex data flow at a. constant B E R requires approximately another 1.3 dB of transmitter power in addition to the 3 dB required when using coherent reception for quadrature data transmission.  46  10"  1  10"  2  10"  3  10"  4  10  -5  10"  6  lO'  7  lCoherent Reception Theoretical  10" 10"  Phase Invariant Reception Experimental  11.0  12.0  13.0  14.0  15.0  16.0  E_s/N_o  17.0  18.0  19.0  (dB)  Figure 24 Symbol Error Rate vs Signal-to-Noise Ratio for Complex Word Length 1 Data in A W G N  47  20.0  21.0  Chapter 6 The BER Performance of CPSK in the Presence of Single-Tone Interference 6.1 Theoretical Analysis for Coherent Reception In [2], a general expression for the probability of error in A W G N and single tone interference is derived. This provided the basis for simulations of the performance for specific choices of spreading sequence, word length and jammer parameters. Unfortunately, the P N sequence length there chosen for the simulations is longer than can be accommodated by the hardware of the receiver that we have implemented. To allow a quantitative comparison between theory and experiment, in this section we. derive a numerical expression for the word length 1, P N sequence length 63 case. Consider a single-tone jammer of angular frequency to = LO + SUJ, with power Pj, at 0  phase angle <j> with respect to the information signal: j{t) = y/2Pjcos{ut  + <f,):  (6.1)  %  For convenience, the amount by which the angular frequency of the jammer differs from that of the signal carrier is written as a percentage of the angular chipping frequency: SUJ = guj =  (6.2)  c  J-c  SUJ will be chosen low enough so that the time integral of (2.12) for the interference terms of the receiver decision variables is well approximated by a summation over chipping times. Then (2.12) for the received interference, upon substitution of (8.1) for the interference, becomes: J =\jE~ju(g,<j),m);  (6.3)  m  where we have defined G-l u(g, <f>,m) = — 1  J  and Ej = PjT  s  p (iT ) m  c  COS(2TTgi  + <f>),  i=0  to be the power of the jammer integrated over a symbol period.  In the word length 1 case, the probability of bit error in A W G N is:  48  (6.4)  Because the interference terms are additive constants to the decision variables, it is clear that the probability of error conditioned on cf>, conditioned on the reception of a 0 bit, is given by <f>, 0). — u(g, <f), 1)); and therefore, with  P with A/EJ replaced by y/Ei + \fEj(u(g\ c  replaced by VSNR(1 + V JSR(u(^, <f>, 0) - u(g,<f>,l))); where SNR = E /N /  b  to noise ratio, and JSR = Ej/E  0  y/Ei/N  0  is the signal  is the jammer to signal ratio.  b  The function u can be written (next paragraph) as u(g, </>, rn) = J(Q, rn).cos <f>,  (6-6)  so that the probability of error conditioned on <f>, for equally likely transmission of 0 or 1, is P^] =  i-(erfc(-^/^  + e r f c ^ V S M ( l + v^SR(7(^l)-7(e,0))cos^)^; /  where the first and second terms are due to the probability of bit error conditioned on the reception of a 0 or 1 respectively. The average bit error rate is \* P [<f>]d<f>. ^ J<t>=o  BER =  -  e  (6.8)  To obtain the function 7 , write (6.4) as u(g, (j>, rn) — c(g, m) cos <f> — d(g, m) sin </>;  (6-9)  with 1 c(g,m) =— l  G _ 1  ' • ^2p (iT )cos(2ngi), m  c  i=o G-1  d{g, m)  Pm(iT ) sin(2vr^); i=0 and redefine (j> by an additive constant to obtain (6.6) with j(g,m) =  (6.10)  c  c (g, rn) + d (g, rn). 2  (6.11^  2  It is easily shown that G_1  1 / l{Q,m) = - i ^ c {l)cos(2ir l)\ G \/=l-G m  V  e  /2  ;  (6.12)  /  where c (l) is the aperiodic autocorrelation of the PN code sequence p (i) m  m  . 49  = p(i — m).  We have written a C program which evaluates 7 , and find that for a maximal length P N sequence with G = 63 and with g = 0.1 that 7(0:1,0) = 0.143  7(0.1,1) = 0.048.  (6.13)  Figure 25 of the next section shows a plot of the B E R versus JSR at an SNR equal to 12:0 dB, as given by (6.8). There we also give a set of measured points, for the same parameter values, for comparison.  6.2 Theoretical Analysis and Experimental Results for PIR In this section we derive an analytic expression for the B E R as a function of ISR arid SNR with phase-invariant reception, for the same spreading and coding parameters (G = 63, k = 1) as the previous section. The intensity of computation prohibits a numerical evaluation of the resulting expression; so we rely on the measured curve to evaluate the performance. With real word length 1 data flow over the complex channel in "the "presence of the single-tone interference as described by (6.1) and (6.2), the m'th correlator output, r , has m  both I and Q channel interference components:  J ,l  = VEju(Q,<f>,m),  m  (6.14)  -VEjv(g,<J),m);  Jm,Q =  where the functions u and v are defined by:  u(g, (f>, m)  l  ^  1  = —  p (iT ) m  c  COS(2TTgi + <j>),  i=0  1  v(g,  m) =  G  _  (6.15)  1  —i=0E  Pm(iT ) c  s'mfa'gi +  </>);  with parameters g and (j> as defined in the previous section. We showed there that u can be written as per (6.6). v admits a similar representation:  u(g, <j), m)  = 7(0,  m) cos <f>,  v(g, <j), m)  = 7(0,  m) sin <f>\  with 7 given by (6.12).  50  _  (6.16)  The probability density functions for the decision variables \ fi \ are obtained by the squarelaw transformation (5.11). Conditioned on jammer phase angle <j>, and on the reception of the symbol representing a 0 bit, these are: f2r  IT N  J  0  (6.17)  8 = 0  r-2-K  j  (p.) = 1  7^(( -^Ejyi  /  e  cos0) + (cvsin6i+A/E77i sine/.)  acosS  2  KN J 0  •  0  where 7; = i(g,i).  With these, the probability of error, conditioned on <f>, and on the  reception of a zero, is as given by (5.9) and (5.14): rOO  /  Jo  rOO  /  Jo  fm(a + B)f .\(8)dadB.  (6.18)  lf  The probability of error conditioned on the reception of a one, P (4>\1), is given by (6.18) C  and (6.17) with 70 and 71 interchanged. Then, for equally likely reception of a zero or a one, the probability of error is Pe =  ^J^-(Pe(<f>\0)  +  PeW))d<f>..  (6.19)  This quintuple integral is too heavy to evaluate numerically to any useful degree of accuracy in any reasonable amount of time. Figure 25 shows the measured curve corresponding to (6.19) at an SNR of 12 dB. The corresponding curve, derived in the previous section, for theoretical coherent reception is shown for comparison. The B E R (theoretical optimal or experimental PIR) at JSR = —10 dB is only about 10 percent higher than in the absence of a jammer (JSR = —oo dB). The implementation loss at 12 dB SNR of PIR with respect to coherent reception, is approximately 1.8 dB; meaning that the experimental curve at a 1.8 dB higher SNR than that of the exhibited curve, roughly coincides with the theoretical curve shown. From the graph, it is evident that it is not until the jammer strength reaches the signal strength (JSR = 0 dB) that the B E R starts to degrade significantly. As for coherent reception, at SUJ = 0 the jammer does not contribute to the B E R because the decision variables are all contributed to equally. At SUJ = oo, the jammer does not contribute either because of the low-pass filtering performed to form the decision variables. The most pessimistic value of g is dependent on the PN sequence used, but is near the value chosen (g = 0.1) for any maximal length PN sequence. 51  1E-1  1E-2  BER 1E-3  Experimental PIR  i  1  1E-4 Theoretical Optimal  0  4  12  JSR (dB) Figure 25 Theoretical and Experimental B E R versus JSR at SNR=12.0 dB with  52  6u> = 0.1UJ  C  Chapter 7 Tracking and Acquisition in AWGN In this chapter, we outline the analysis required to analytically predict the mean timeto-acquire and the mean time-to-lose-16ck, in additive white gaussian noise, that the CPSK receiver achieves. The experimental curves of these quantities as functions of the signalto-noise ratio are presented. They determine the minimum length of preamble, and the maximum length of body that should be used for packet transmission.  7.1 Mean Time to Acquire Refer to Figure 9 of chapter 3 for the PN code acquisition algorithm. For M-ary CPSK the length, measured in number of chips, of an elementary code-phase shift, m , is e  », = ^ i .  (7.1)  The acquisition algorithm uses M data correlators, spaced by m chips, to search for lock e  by one chip increments. At the end of a data symbol period, if the data correlator with the maximum output has an output which crosses threshold!,  the maximum of it and the output of the corresponding  early and late correlators is compared to threshold^.  Let P \ denote the probability of s  exceeding these two thresholds (or passing stage 1) given that the code is in fact aligned to within 1/2 chip. If stage 1 is not passed, the data correlators are precessed for the next attempt to pass stage 1. If stage 1 is passed, the output of the correlator which was largest in stage 1 is checked again on another data read, along.with it's early and late counterparts. If the maximum of these three exceeds threshold?,, the signal is declared to be acquired. Let P  s2  denote the probability of passing stage 2, given rough (to within 1/2 chip) code alignment. Let rii denote the average number of attempts required to pass stage i when the code is aligned to within 1/2 chip. Then . ' ni = ——  for  i  = 1,2.  (7-2)  Since the probability of passing stage 2 is independent of the probability of passing stage 1, the average number of attempts required to pass both stages is n\n . 2  Provided that the  thresholds are set such that the probability of false acquisition is negligible, attempts to pass stage 1, given that the code is aligned to within 1/2 chip, occur at m data symbol intervals. e  '• 53  Each failed attempt to pass stage 1, with code alignment to within 1/2 chip, costs m data e  symbol periods; while the subsequent attempt to pass stage 2 costs 1 data symbol.period. Then since 1/2 chip code alignment first occurs, on average, after ( m + l ) / 2 data symbols, e  the mean time to acquire, measured in number of data symbols is given by • A — ( n i n — 1 )m + n H 2  e  2  ^—.  (7.3)  In the absence of noise, this reduces to •  A  = ^ ± l + l.  ldeal  '  '  (7.4)  The pdf for the output magnitude of the punctual complex correlator is given by the first of (5.13) for exact code alignment; and given by the same equation with ^/E~ replaced by s  \/E7/2 for 1/2 chip-off code alignment. Obtaining  P i however, requires the joint pdf of s  the latter two — something which we have not yet been able to obtain. To derive the mean time-to-acquire when the probability of false acquisition is non-negligible, one must go to a Markov chain analysis, similar to that in [11]. Let the acquisition thresholds be written as fractions of the complex correlator magnitude for the noiseless reception of the corresponding data symbol: thresholdi  Then with c\ = 1/16,  = Ci\fW .  (7.5)  s  c = C3 = 1/4, and G = 63, we have found the mean time-to2  acquire as a function of signal-to-noise ratio, as shown in Figure 26, for the experimental arrangement described in chapter 3. Each data point represents 20 measurements. The error bars represent one standard deviation due to the noise induced variance. A false acquisition was observed less than 1 out of 100 trials during these measurements. However, not enough measurements were made to collect meaningful false acquisition statistics. Note that the ideal mean time-to-acquire reaches the value A i  given by (7.4) at an  ldea  SNR of 13 dB. At SNRs greater than or equal to his value, a data packet with a preamble length of hdeal — ((G +  l)/-^0  + 1  w  m  be blocked with negligible probability. Assuming  that the time-to-acquire is approximately gaussian, a preamble length, l , which will result in n  a blocking probability which is upper bounded by the probability of a normalized gaussian process falling n standard deviations outside of its mean is given by l = A + no- - A n  ideal  54  + kdeai\  (7.6)-  where A and a are to be read from the graph of Figure 26.  100.0  80.0  60.0  40.0  A  (number of data symbols)  20.0  o.o  10.0  11.0  12.0  E_b/N_o  (dB)  13.0  14.0  15.0  Figure 26 Mean Time-to-Acquire Measured in Data Symbol Durations vs SNR for G=63  7.2 Mean Time to Lose Lock The mean time-to-lose-lock can be analysed by means of Markov chain theory. Let s\ be the state for which the tracking loss flag is down; .32 be the state for which the tracking loss flag is raised; and 53 be the state representing a loss of lock. Let p denote the probability that the maximum of the outputs of the punctual, early, and late correlator corresponding to the received data symbol is below ihreshohU.  Then the receiver makes one state transition per  data symbol period in the Markov chain shown in Figure 27 with state transition probabilities Pl,l  =  ^2,1 =  Pi,2 = ^2,3 = P ,  ^3,3  55  =  1.  Figure 27 Markov Chain for Tracking Loss Calculation The states si and S2 are the transient states, and state S3 is an absorbing state. By the theory of finite Markov chains [12], the mean number of times,  n;(.Sj),  that the process which  started in transient state .s; is in a transient state SJ, is given by {•n -( )} = ( / - Q ) - ; 1  1  Bi  '  (7.7)  where Q = {Pij} is the transition probability matrix for the transient states, and / is the identity matrix. For the case at hand, since we start in state .si, the mean time-to-lose-lock is given by '  TL = n (s ) l  1  + n,(s ) 2  = ^  -  .  (7.8)  As in the previous section, computation of p requires the joint pdf of the magnitudes of a complex correlator and its 1/2 chip displaced counterparts. Furthermore, it also depends on the symbol error probability, and on the degree to which the receiver is actually on track. To take into account the latter, the states need another set of quantum numbers corresponding to whether the receiver is on, 1 sample off, 2 samples off, or greater than 2 samples off track. Taking into account timing slippage, would also require specifying the direction of the off-track states. With the tracking loss threshold c = 1/16, as defined by (7.5), and a spreading factor 4  of G = 63, we have found the mean time-to-lose-lock as a function of signal-to-noise ratio by experiment. It is only independent of the spreading factor for zero timing slippage. Each data point of the graph shown in Figure 28 represents 10 measurements.  Since the error  bars represent 1 standard deviation, provided that the process is approximately gaussian, the  56  maximum packet body length for nonblocked complete reception with na confidence can be read from the graph.  10 p 10  TL  •  ,——  ,  •  ,  .  ,  •  ,  .  10  7  (number of data symbols) 10  6  10  5  9.5  10.0  10.5  11.0  11.5  12.0  E_b/N_o (dB) Figure 28 Mean Time-to-Lose-Lock Measured in Number of Data Symbols vs. SNR  57  12.5  Chapter 8 Conclusions The design and implementation of a correlation receiver for CPSK has been presented. This involved solving the spreading code and carrier-wave synchronization problems. The steady state behaviour of the receiver has been investigated exhaustively in A W G N and singletone interference; and the previous theoretical BER performance claims by the inventors of CPSK have been experimentally verfied. Beyond this, the present author has found the following. When sampling at twice the chipping rate, applying a first order R C filter of 3-dB bandwidth equal to 1/2 the chipping rate, to the baseband signal before sampling, optimizes the SNR of the correlated signal to a value which is within 1 dB of the output SNR of an ideal matched filter. This result is not specific to CPSK — in the DS-SS literature, the L P F bandwidth is as here (for example, in [13]); but we have not been able to find a publication of the SNR optimization calculation. The author's herein described tracking algorithm has been found to be very satisfactory. For coherent reception, we have found by theoretical analysis, that in A W G N with a timing slippage typical of a TTL oscillator, that the signal is kept on track well enough to incurr a B E R performance degradation of less than 0.4 dB for SNRs less than about 14 dB. The hereby invented Phase-Invariant-Reception method for CPSK for solving the carrierwave synchronization problem eliminates the need for a phase-lock loop, or for a phase estimation DSP filter, by forming receiver decision variables that do not depend on the phase difference between the carrier-wave and the receiver's L O . This method is well suited for DSP because of the minimal amount of post-correlation processing that it requires. For single-channel data transmission and zero frequency difference between the carrier and the receiver LO, at a B E R of 10~ , PIR is 1.1 dB less .power efficient than coherent reception; 3  at a B E R of 10~ this loss of power efficiency goes down to 0.5 dB. This loss increases 8  independently of the SNR as a function of the frequency difference according to the graph shown in Figure 23. For a 140 M H z carrier, commercial oscillators exist with frequency tolerances that would keep this additional degradation within 1 dB. The degradation due to non-zero frequency difference could be minimized by the addition of a frequency lock loop. The remaining implementation loss with respect to coherent reception can not be recovered.  58  This loss should serve as a bench mark for DSP filters which remove the phase rotation so as to allow coherent reception. More work needs to be done on the dynamic aspects of CPSK reception. The acquisition algorithm presented is very simple and reasonably fast.  The threshold values to use in  A W G N were experimentally determined by lowering them from some high nominal value (thus shortening the acquisition time) until the probability of false acquisition started to become non-negligible. The resulting threshold values need to be fine tuned, either by more experimentation or by finding reasonably exact analytic expressions for the acquisition time and for the probability of false acquisition. This would allow tradeoff considerations between preamble length and acquisition failure rate under different SNR and JSR values to be analysed. The algorithm for checking for loss of lock should be improved from the present 2 state algorithm to a 3 (or higher) state algorithm so as to improve the time to lose lock. Such an algorithm would make the loss of lock more immune to bit errors. Again either by more experimentation, or by solving the theoretical problems described in chapter 9, the best algorithm should be determined and its thresholds optimized. After this, a higher level performance evaluation which optimizes data throughput with respect to packet length needs to be done so that the modem can be used effectively in a computer network.  59  Bibliography [I] Robert C. Dixon. Spread Spectrum Systems with Commercial  Applications.  Wiley-  Interscience, 1994. [2] Aries Y.C. Wong. Analysis of techniques to enhance the performance of direct sequence spread spectrum signaling for wireless data communications. Master's thesis, University of British Columbia, 1995. [3] M.K. Simon. Spread Spectrum Communications,  Vols. 1,2,3.  Computer Science Press,  1985. [4] J.M. Wozencraft and I.M. Jacobs. Principles of Communication Engineering. John Wiley & Sons, 1965. [5] Spectrum Signal Processing Inc. Quad C40 Processor Board User's Guide, June 1993. [6] Texas Instruments. TMS320C4x User's Guide, 1993. [7]  3L Ltd. Parallel  C User Guide,  1994.  [8] Chris Bowick. RF Circuit Design. Indianapolis, Ind. : H.W. Sams, 1982. [9] Hansen Wang. Spread Spectrum Modem IF Receiver, Technical Manual, Board Revision 1.0, June 1995. [10]K. Beeler and H. Kaufmann. Time integrating correlator for real-time processing of spread-spectrum signals. Proc. Custom Integral Circ. Conf, May 1990. [II] Unisys. PA-100 Spread Spectrum Demodulator, Technical Data Sheet and User's Guide, June 1993. [12] Stanford Telecom. STEL-2000A, Processor,  Digital,  Fast Acquisition,  Spread Spectrum Burst  1994.  [13]V.C.M. Leung and R.W. Donaldson. Confidence estimtes for acquisition times and holdin times for pn-ssma synchronizer employing envelope correlation. IEEE Trans. Comm., COM-26, Jan. 1982. [14]J.G. Kemeny and J.L. Snell. Finite Markov Chains. D. Van Nostrand Company, Inc., 1960. [15]A.L. Welti and B. Bobrovsky. On optimal age structure for direct sequence spread spectrum pn-code tracking. IEEE Trans. Comm., 42(2/3/4), 1994. 60  Appendix A Maximal Length PN Sequence Generation The Maximal Length Pseudo-Noise Sequences are the longest codes that can be generated by a shift register of a given number of stages /. Their length is (Al)  G = 2' - 1 .  Figure 29 shows the 3-stage shift register with the appropriate linear feedback connections, for generating the G = 7 PN sequence; while Figure 30 shows the autocorrelation function, as given by (2.8) for the /-sequence. In the implementation, the non-shifted PN sequence is, chosen to be the one generated by initializing all the stages of the generating register with 1. The PN sequence is software generated and written to the DSP's memory during system initialization.  2  1  3  Code Output Figure 29 Three-Stage Maximal Generator  61  -1 chip  +1 chip  Figure 30 1-Sequence Autocorrelation Function  62  Appendix B IF Transmitter Modules Each section of this appendix discusses and gives a schematic of a module of the IF transmitter shown in Figure 6.  B.1 Digital Communication Port Interface The digital interface reads from the C40 communication port via four control signals: /CPvEQ, /CACK, /CSRTB, /CRDY. Of these, /CREQ and /CACK are for determining ownership of the data bus; and for unidirectional data flow, these can simply be tied high, provided that the C40 communication port used defaults to an output port at system reset. A sending C40 activates /CSTRB to indicate that it has placed a data byte on the data bus; while a receiving C40 activates /CRDY to indicate that it has received a data byte. The IF transmitter's digital interface (call it Tx) mimics the C40 communication port protocol in such a manner that the data flows according to the interfaces' 4 MHz clock. This is achieved with a Dflip-flopwhich controls both the /CSTRB /CRDY handshaking and the clock signal for a following D flip-flop which reads the data line. See Figure 31 for the digital interface circuit schematic. The logic elements are implemented by the FAST logic family; and the propagation delays and C40 response times are such that the circuit is guaranteed to function with a clock rate of up to 5.25 MHz. With a 4 MHz clock, the available, software controlled, chipping rates are divisions by 2 of 4 Mbps. Because the C40 communication port is very high-speed, signal quality is very important. The value for the serial impedance matching resistor (39£7) was determined by experimentally minimizing the ringing of the output /CRDY signal. The 10 kfi pullup resistors are used to avoid unintended triggering after reset. Figure 32 shows the circuit appropriate for a single channel system. In actuality, both I and Q channels are present. Because thefirst/CSTRB for the two channels is only asserted by the C40 at the same time to within some uncertainty, it is possible for the two channels to be skewed by one Tx clock period. To avoid this and ensure that the two channels are synchronized, the RESET signal of the I-channel controlflip-flopis routed to RESET of the Q-channel controlflip-flop,and vice-versa.  63  Vcc  CLR  DATA  D  SN74F125  Q  SN74F74  H>  DATA OUT  SN74F125  Vcc  1_ ~~^—L  /CSTRB > I^SN74F1?5  D  I^SM7<1F SN74F04  Q  PRE  — T I  Vcc  SN74F74 CLK >-  X •<3 PRE  Vcc  /CREQ Vcc  Vcc  /CRDY < 39 O  SN74F125  ^  10K  /CACK >  SN74F04  Figure 31 Communication Port Interface (one channel)  B.2 Level Shifter and Amplifier The level shifter/amplifier converts the TTL logic valued data stream to a bipolar data stream appropriate for BPSK modulation. The circuit uses the high frequency operational amplifier AD963Tto implement a difference amplifier in which one input is the TTL signal, and the other input is a constant voltage signal held at a point midway between TTL high and TTL low. The constant voltage signal is obtained by a 20 kf) voltage divider inserted between ground and the +5 volt supply, followed by a unity-gain buffer implemented by the operational amplifier LM741. The buffer holds the voltage divider output, V f, constant re  (up to a small jitter which is then taken out by a capacitor between ground and the buffer output) in spite of the large changes in the current drawn by the difference amplifier. Two Zener diodes are used to clip off the overshoot and the undershoot of the TTL input signal, Vin, to the difference amplifier. See Figure 32 for the circuit schematic. The output voltage of the difference amplifier is given by 1 + R /Ri 2  V  o  u  t  -  R2  v  1 + Rz/Rt  64  V  V  i  n  i?/  r e /  '  (Bl)  The resistors R2 and i?4 are both chosen to be 150S7 ± 10%, while the variable resistors i?i and i?3 are adjusted so as to make R2/R1 =  RA/RZ  Vout = A(V  = A. Then the output voltage is given by (52)  - V ).  m  ref  Vcc Vcc  .1 u F  3.3 uF  1 uF  R2  A/V  20K  Vcc 3.3 u F .1 u F  .1 u F  -Vcc Vcc Vout  TTL input  26'N4733A 5.1 V  Vin  ^JT~1 T1N4619 3.0 V /  GND  3.3 u F  -Vcc  Figure 32 Level Shifter and Amplifier  B.3 BPSK Modulator and Bandpass Filter The quadrature BPSK modulator performs double-sideband suppressed-carrier modulation with an RF carrier of frequency 140 MHz in both I and Q channels. It is implemented by Mini-Circuits MIQY-140M, whose characteristics are as follows: — input and output impedance of 50 ohms — operating LO frequency and power: 140 MHz at 10 dBm — maximum I and Q current: 40 mA (2 V peak-to-peak) — bandwidth: 10 MHz — conversion loss: 6 dB —- carrier suppression: 30 dB  65  The RF modulator output is bandpassfilteredto remove the image spectra at frequencies harmonic to 140 MHz. See Figure 33 for the modulator plusfiltercircuit schematic. Thefilterconsists of two identical cascaded stages whose circuit elements are determined by the formulae:  L  . _  V2RQ  C  G  ^ 2 - Wi  _  1  lolLg  .  .  where R = 50f2 is the characteristic impedance of the filter input and output, u> is the 0  0  angular frequency band-center, and u>2 — u>\ is the angular frequency 3-dB bandwidth. With a band-center of 140 MHz and a bandwidth of 134 MHz, these are: L  s  = MnH  C  = 34pF  L  s  =  IbpF  =  39nH.  (£4) C  p  p  The inductors where wound with 20 AWG tinned copper wire according to the following formula for an air-core, single-layer solenoid: L = Fn d; 2  '  (£5)  where n is the number of turns, d is the diameter of the coil, and F is a constant that depends on the ratio of the length to the diameter of the coil. The extremely small values for the inductances make the circuit element parameter values hard to control — as the lumped parameter model is barely appropriate. The actual constructedfilterended up with a bandwidth of approximately 100 MHz about a band-center of 120 MHz. The 20 MHz band about the desired 140 MHz has a passband ripple of less than 1 dB about zero attenuation, so the filter is satisfactory.  66  I chan > Q chan >  MIQY-140M  A  LO  RF  Ls Cs  Lp  RF out  Ls Cs  Cp  Lp  >  i  i  •'mj^-  Figure 33 B P S K Modulator and Filter  67  Cp  Appendix C IF Receiver Modules Each section of this appendix discusses and gives a schematic of a module of the IF receiver shown in Figure 7.  C.1 BPSK Demodulator and Low Pass Filter A 3 dB pad improves the impedance matching between the BNC connector for the incoming IF signal and the QPSK demodulator, which is implemented by Mini-Circuits MIQY-140D, and is of the following specifications: — input and output impedance of 50 ohms — operating LO frequency and power: 140 MHz at 10 dBm — maximum RF input power: 50 mW (1.6 V peak-to-peak) — bandwidth: 10 MHz — conversion loss: 5.6 dB — maximum output current: 40 mA The active low pass filter and amplifier has an overall gain of 28 dB equally distributed over 2 stages, each of which is implemented with Analog Device's high frequency AD843TN op amp in the basic inverting configuration. One of the stages implements thefirstorder low-pass filter by a parallel RC feedback. The values of R and C were chosen so as to give the filter the 3-dB cut-off frequency of 0.25 MHz, as called for in Chapter 4. The voltage offset adjustment, implemented with the LM741CN op amp, is necessary to shift the bipolar baseband signal to be centered about 1 volt, because that is the middle of the ADC range. The circuit includes a trim pot to precisely adjust the offset.  68  O.luF  0.1 uF  —»—  -a—  J6.8UF TANT  I channel I  3> LO input > RF input >  I—Ur  I & Q Demodulator  a  I analog m  ^>^AD843JI  4  O.luF  —K—  6.8uF TANT  8.66 H 8.66 R VW-i-WV 1  940 pF  MIQY-140D  -Vcc  6.8UF TANT  •  Low Pass Filter and Amplifier  3 dB pad  Vcc  O.luF  O.luF  HI—  6.8UF TANT|  681R  681R  6.8UF TANT  AAA.  1  940 pF  Q channel  I  1  Q analog  A D M ! I 1  O.luF  0.1UF  I 6.8UF TANT -Vcc  J^AD843Jl  ' *  —K6.8UF TANT • ^ Vcc  Voltage Offset Adjustment  i—ixi/v  74^0^^i  Figure 34 BPSK Demodulator and Low Pass Filter  C.2 Analog/Digital Converter The I and Q signals are sampled on the rising edge of the ENCODE signal by Analog Devices AD9058JD Dual-Channel 8-Bit, 50 MSPS Flash ADC. It has an encode propagation time delay of 12 ns, and an input aperture time of 0.8 ns. It provides a +2 volt reference output, Vint, which is used by the voltage offset adjustment of the previous section to bring the LPF output signal into the center of the 0 to 2 volt analog input range of the AD9058JD.  69  Pull-down resistors are on the TTL output lines to approximately equalize the TTL high/low rise and fall times. The two Octal D Latches (SN74F373) latch the ADC output data.  Octal D Latch  AD9058JD  DI.O DM  Vint «-  'DI.2 DI.3 >DU  ENCODE >-  DI.5 >DI.6 DI.7  [ENCODE A  I analog >-  DQ.O DQ.) DQ2 DQ.3  Q analog >-  DQ.4  DQ5 DQ.e DQ.7  GG GG GNNGGGNNG D N N N [ >DDDI  1 Octal D Latch  Figure 35 Dual Channel 8-Bit ADC  C.3 ADC Converter Control The ADC Converter Control module takes as input the TTL clock oscillator, the QPC/C40 global reset, and one data line from a C40 communication port; and produces as output the ENCODE control signal for the ADC, and the write control signals, /WEN and WCLK, for writing ADC output to the bank of FIFO memory.  The serial connection of two  buffers (SN74F04N) provides a simple communication interface with the C40 providing the GO/STOP signal, clocked in by the D-flip-flop SN74F74N, for enabling/disabling the ADC conversion and FIFO writing. Each of the two J K flip-flops (SN74F109) perform a  70  division by two of their respective clock inputs. Thus, the FIFO write clock, WCLK, is driven at half the clock rate; while the FIFO write enable, /WEN, and the ADC encode control, ENCODE, signals are driven at one quarter of the receiver TTL clock oscillator rate.  CLK>Vcc  Vcc  2  ^101  .SN74F109  /CSTRB>-  ,. PRE  Vcc SN74F04N  L  n  .  ^2  •pOLK  >IOK  L_  5P  &CLK /CRDYf-  Vcc _  Vcc  CLR SN74F04N  — GND  1  T J_  /WEN ^ENCODE  SN74F109  — GND _, Vcc  /RS >-  -> WCLK SN74F08N  CDO>-  PRE D Q — GND  pax.Qp  T  SN74F74N  Vcc  Figure 36 ADC Converter Control  C.4 FIFO Memory Banks Each FIFO of the memory bank is TI's SN74ACT722X1L-25RJ. They are 2048 9-bit bytes of SRAM deep, with a 25 ns read or write access time. Either end of the FIFO can be operated in synchronous or in asynchronous mode. The write control signals, WCLK and /WEN, issued from the ADC conversion module, operate the input side of the FIFO in synchronous mode; while the read control signals, RCLK and /REN, issued from the FIFO/TMS320C40 communication port, operate the output side of the FIFO in asynchronous mode. The FIFO activates the full flag, /FF, when the FIFO is full, indicating that the writes are blocked; and activates the emptyflag,/EF, when the FIFO is empty, indicating that the reads are blocked. /EF is used by the FIFO/TMS320C40 communication as a control signal.  71  /FF is not used at present; but a future iteration of the receiver could use the full flag indicate a system error — for normal operation, /FF should never be activated.  -<RCLK1 -</REN1 ->/EF1 DI.O> DI.1 > Dl.2> DI.3J Dl.4>  CDI.O CDI.1 CDI.2 CDI.3 CDI.4 CDI.S CDI.6 CDI.7  DI.55 DI.6J DI.7J  SN74ACT722X1L /RS  -<RCLK2  WCLK /WEN  -</REN2  DQ.O DQ.1 DQ.2 DQ.3 DQ.4 DQ.5 D0.6 DQ.7  CDQ.O CDQ.1 CDQ.2 CDQ.3 CDQ.4 CDQ.5 CDQ.6 CDQ.7 SN74ACT722X1L  -< RCLK3 -</REN3 ->/EF3 CDI.O CDI.1 CDI.2 CDI.3 CDI.4  SB!:I cDi.7 SN74ACT722X1L -<RCLK4 WOK  -</REN4  MEN1 TV£NS/L0  -)/EF4 CDQ.O CDQ.1 CDQ.2 CDQ.3 CDQ.4 CDQ.5  888:1 SN74ACT722X1L ±GND  Figure 37 FIFO Memory Banks  72  C.5 FIFO/TMS320C40 Communication Port Of all the receiver hardware, the FJFO/C40 communication port was the most challenging to design.  This is because the C40 communication port is very high speed, and its  communication protocol is rather particular; so that setup time requirements are stringent and signal quality is very important in order to avoid byte slippage. The C40 communication port transfers words in an asynchronous transmission of 4 bytes, followed by a word synchronizer delay. The port we have designed transfers bytes synchronously, and does not exercise an extra delay after every fourth byte. The resulting port speed is one half of that possible between two C40s. The communication port has been extensively tested, and found to be reliable when driven by a clock of frequency up to 32 MHz. However, due to the C40 response time, and the propagation delays of the input and output buffers (SN74F125), we have found that the communication rate in bytes per second changes from clock frequency divided by 2 with a 16 MHz (or slower) clock, to clock frequency divided by 4 with a 20 MHz (or faster) clock. Therefore, we use a 16 MHz clock for a port speed of 8 MB PS. The communication port schematic does not show the token forcer which is necessary to give the IF receiver ownership of the data bus. We have it implemented according to the schematic given in the Tl TMS320C40 Data Book.  73  IRS >CLK >—  •o-  I ->  /REN  /EF >RCLK « -  /CRDY>-  SN74F08N  SN74F74N  T _vw27R  Figure 38 FIFO/TMS320C40 Communication Port  74  -»  /CSTRB  Appendix D DSP Code Listings D.1 Master Receiver * Master r e c e i v e r f o r word l e n g t h 1, q u a d r a t u r e d a t a f l o w w i t h Phase* I n v a r i a n t r e c e p t i o n f o r a f i l e sent over the IF l i n k . * Hosted on p r o c e s s o r A. R e c e i v e s from a p a i r o f complex c o r r e l a t o r s * on p r o c e s s o r B, and an e a r l y and a l a t e c o r r e l a t o r on p r o c e s s o r D. * The t a s k reads from f i l e d a t a c ( c o n t a i n s zeroes and ones) and p a s s e s * i t t o p r o c e s s o r B which r e l a y s i t t o the t r a n s m i t t e r on p r o c e s s o r C. * The d a t a which the r e c e i v e r p r o c e s s e s i s w r i t t e n to f i l e r e _ d a t a c . * The amount o f s p r e a d i n g i s determined by a u s e r s u p p l i e d PN g e n e r a t o r * s h i f t r e g i s t e r length. * The f u n c t i o n a l i t y i n c l u d e s a c q u i s i t i o n which uses a two sample s t e p * s i z e . Once the code i s a c q u i r e d , the program t r a c k s , decodes, and * w r i t e s to a b u f f e r . */ i i n c l u d e <chan.h> t i n c l u d e <stdio.h> # i n c l u d e <math.h> /* f o r pow * / #include <stdlib.h> /* f o r c a l l o c * / # i n c l u d e <compt4 0.h> /* f o r out_word * / e x t e r n reed() ; /* f o r r e a d i n g from c o r r e l a t o r s */ f l o a t ciO=0 /* ciO h o l d s 0 I c o r r e l a t o r output */ f l o a t cqO=0 /* cqO h o l d s 0 Q c o r r e l a t o r output */ float cil=0 /* c i l h o l d s 1 I c o r r e l a t o r output */ f l o a t cql=0 /* c q l h o l d s 1 Q c o r r e l a t o r output */ f l o a t die=0 /* d i e h o l d s e I c o r r e l a t o r output */ f l o a t dqe=0 /* dqe h o l d s e Q c o r r e l a t o r output */ f l o a t dil=0 /* d i l h o l d s 1_ I c o r r e l a t o r output */ f l o a t dql = 0 /* d q l h o l d s 1 Q c o r r e l a t o r output */ m a i n ( i n t argc, char * a r g v [ ] , char *envp[), CHAN * i n _ p o r t s [ ] , i n t i n s , CHAN * o u t _ p o r t s [ ] , i n t outs) { f l o a t c0=0; /* 0 c o r r e l a t o r magnitude squared * / f l o a t c l = 0; /* 1 c o r r e l a t o r magnitude squared * / f l o a t de=0; /* e a r l y c o r r e l a t o r mag squared */ f l o a t dl=0; /* l a t e c o r r e l a t o r mag squared */ f l o a t g; /* 0 c o r r . dot r o t a t e d 1 c o r r . */ f l o a t h; squared 1 */ /* mag.squared 0 minus mag int M,N; /* PN s h i f t r e g l e n g t h , PN l e n g t h * / float thresholdl; /* to d e t e c t w i t h i n 1/2 c h i p */ f l o a t threshold2; /* to d e t e c t e x a c t c o r r e l a t i o n */ f l o a t threshold?; /* f o r acq conferm */ f l o a t threshold4; /* to d e t e c t t r a c k i n g l o s s */ i n t ESHIFT; /* l e n g t h o f elementary phase s h i f t */ i n t acq=0; /* acq=0 means not a c q u i r e d * / int tflag=l; /* f o r t r a c k e r */ int tlflag=0; /* f o r t r a c k e r */ f l o a t max=0,maxd=0; /* max c o r r . output, max d e l a y e d */ i n t j=0; /* f o r t r a c k e r */ f l o a t temp; /* f o r t r a c k i n g l o s s , t e s t */ i n t shift=0,shft=0; /* s h i f t s f o r acq. and t r a c k i n g */ i n t s h i f t d = 0 , shftd=0; /* d e l a y e d s h i f t s */.  75  int slide; /* t r a c k i n g adjustment */ i n t sld=0; /* s l i d e adjustment */ int slided; /* d e l a y e d s l i d e */ i n t i=0; /* sample c o u n t e r */ int flag=-l; /* f o r f l a g g i n g c o r r e l a t o r s */ int flagc; /* flagc=0 means m a l l o c f o r c o r r s OK */ int flagg; /* flagg=0 means m a l l o c f o r gen OK */ int *bufi,*bufq; /* p o i n t e r s t o b u f f e r e d d a t a */ int valuei,valueq; /* f o r r e a d i n g d a t a */ i n t datacount=0; • /* i n p u t datacount */ FILE * o u t f i l e , * i n f i l e ; /* f o r d a t a i o */ i n f i l e = f o p e n ( " d a t a c " , "r " ) ; /* s t a r t by c o u n t i n g d a t a */ w h i l e ( f s c a n f ( i n f i l e , " % d %d",&valuei,&valueq)==2) datacount=datacount+2; fclose(infile); p r i n t f ( " T h e number o f b i t s t o t r a n s m i t i s %d \n",datacount);. p r i n t f ( " I n p u t PN s h i f t r e g i s t e r l e n g t h (max=10): " ) ; scanf("%i",&M); /* r e a d M */ chan_out_word(M,out_ports[0]); /* send M t o the c o r r e l a t o r s */ chan_out_word(M,out_ports[1]) ; /* send M t o d e l a y e d c o r r e l a t o r s */ N=pow(2,M)-1; t h r e s h o l d l = (2*N)/(16*16); t h r e s h o l d 2 = (2*N)/16; threshold3 = threshold2; threshold4 = t h r e s h o l d l ; ESHIFT=N-1; slide=2*N-l; slided=2*N-l; chan_in_word(&flagc,in_ports[0]) ; /* c o n f i r m a t i o n from c o r r e l a t o r s */ i f ( f l a g c ) { p r i n t f ( " I n s u f f i c i e n t space f o r c o r r e l a t o r s \ n " ) ; e x i t ( 1 ) ; ) chan_out_word(datacount,out p o r t s [ 0 ] ) ; /* send t o c o r r . * / b u f i = ( i n t *) c a l l o c ( d a t a c o u n t / 2 + 1,1); /* a l l o c a t e and z e r o s t o r a g e */ b u f q = ( i n t *) c a l l o c ( d a t a c o u n t / 2 + 1 , 1 ) ; /* a l l o c a t e and z e r o s t o r a g e */ i f ( b u f q == NULL ) •"{ p r i n t f ( " T h e r e q u i r e d r e c s t o r a g e space i s n o t a v a i l a b l e \n") exit(1) ; }  chan_in_word(&flagg,in_ports[0]); /* c o n f i r m a t i o n from g e n e r a t o r */ i f ( f l a g g ) { p r i n t f ( " I n s u f f i c i e n t space f o r g e n e r a t o r \ n " ) ; e x i t ( 1 ) ; } i n f i l e = fopen("datac","r"); /* pass d a t a t o c o r r */ w h i l e ( f s c a n f ( i n f i l e , " % d %d",&valuei,&valueq)==2) { chan_out_word(valuei,out_ports[0]); chan_out_word(valueq,out_ports[ 0 ] ) ; } /* chan_out_word(flag,out_ports[0]); /* chan_out_word(flag,out_ports[0]); fclose(infile); /* chan_in_word(&flag,in_ports[0]); /* chan_in_word(&flag,in_ports[1]); c h a n _ o u t _ w o r d ( f l a g , o u t _ p o r t s [ 0 ] ) ; /* /* chan_out_word(flag,out_ports[1]); /* Send c o n t r o l s i g n a l s t o IF board V asm ( " . data asm("o_addr: .word 00100092H a s m ( " f i f o s p : .word 0F4F4F4F4H asm("frst: .word 0F5F5F5F5H asm("gostop: .word 0F7F7F7F7H asm("rst: .word 00000000H  f l a g end o f f i l e */ w i t h 2 - l ' s */ wait f o r c o r r e l a t o r s ready */' wait f o r d e l a y e d c o r r e l a t o r s */ f l a g ready t o c o r r e l a t o r */ f l a g d e l a y e d c o r r e l a t o r */  76  asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm{" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" asm(" for {  .text push ARO push AR1 push AR2 push AR3 ldpk @o_addr Ida @o_addr, ARO ldpk @fifosp • I d a @ f i f o s p , AR1 ldpk @ f r s t I d a @ f r s t , AR2 ldpk Ogostop I d a ©gostop, AR3 s t i AR1,*AR0 nop nop nop nop nop s t i AR2,*AR0 nop nop nop nop nop s t i AR3, *AR0 pop AR3 pop AR2 pop AR1 pop ARO  .  (i=0;i<=datacount;i++) if {  (acq==0)  /* a c q u i s i t i o n mode */  /* s h i f t c o r r e l a t o r s */ out_word(shift,0); out_word(slide,0); /* s h i f t d e l a y e d c o r r e l a t o r s */ out_word(shiftd,3) ; o u t _ w o r d ( s l i d e d , 3) ; slided = slide; /* increment s h i f t by 2 samples */ s h i f t = (shift+2)%(2*N) /* t e s t f o r a c q u i s i t i o n */ i f (maxd>thresholdl) { sld=0; (de>maxd)?(maxd=de,sld=-l):(maxd=maxd); /* a d j u s t by 1 samp */ (dl>maxd)?(maxd=dl,sld=+l):(maxd=maxd); i f (maxd>threshold2) /* t e s t a d j u s t e d a c q u i s i t i o n */ {  acq=l;shift=(2*N+shft-sld)%(2*N);j=2; } }  maxd=max; p r i n t f ( " % e %e %e %e %d %d %d\n", cO, c l , de ,dl., s l i d e , s h i f t, j ) ; */ shft=shiftd; reed(); • . /* r e a d c o r r e l a t o r s */ cO = c i O * c i O + cqO*cqO; /* form magnitudes squared */ cl = c i l * c i l + cql*cql; de = .die*die + dqe*dqe; dl = d i l * d i l + dql*dql;  77  (cO>=cl)?(max=c0,shiftd=(2*N+shift-2)%(2*N)): /* f i n d max and */ (max=cl,shiftd=(ESHIFT+shift-2)%(2*N)); /* a d j u s t s h i f t */ } e l s e i f (acq==l)  /* a c q u i s i t i o n  c o n f i r m a t i o n */  {  out_word(shift,0); o u t _ w o r d ( s l i d e , 0) ; o u t _ w o r d ( s h i f t d , 3) ; o u t _ w o r d ( s l i d e d , 3) ; if {  (j==0) sld=0; (de>maxd)?(maxd=de,sld=-l):(maxd=maxd); (dl>maxd)?(maxd=dl,sld=+l):(maxd=maxd); i f (maxd>threshold3) /* a c q c o n f i r m e d */ acq=2;slide=2*N-shift+sld-1;shftd=0;j=4; lse  /* go back t o a c q mode */  acq=0;shift=(shift+2)%(2*N) }  j=j-i; maxd=cO; p r i n t f ( " % e %e %e %e %d %d % d \ n " , c O , c l , d e , d l , s l i d e , s h i f t , j ) ; shft=shiftd; reed(); cO = c i O * c i O + cqO*cqO; cl = c i l * c i l + cql*cql; de = d i e * d i e + dqe*dqe; dl = d i l * d i l + dql*dql;  */  (cO>=cl)?(max=cO,shiftd=(2*N+shift-2)%(2*N)): (max=cl,shiftd=(ESHIFT+shift-2)%(2*N)); } e l s e i f (acq == 2)  /* t r a c k i n g / d e c o d i n g  mode */  C out_word(0,0); /* w r i t e s h i f t t o (0,1) p a i r */ out_word(slide, 0 ) /* w r i t e s l i d e t o (0,1) p a i r */ out_word(shftd,3) /* w r i t e s h i f t t o ( e , l ) p a i r */ out_word(slide,3) /* w r i t e s l i d e t o ( e , l ) p a i r */ slide=2*N-l; ' i f (j<=0) /* p r e v i o u s t r a c k i n g a d j done */ { (de>dl) ? ( s l d = - l , temp=de) : (sld=+l, temp=dl) '; i f (maxd<temp) /* t e s t i f t r a c k i n g a d j needed */ { /* i f t r a c k e r f l a g up, a d j u s t */ i f ( t f l a g ) {j=4; s l i d e = 2 * N - l + s l d ; tflag=0;} else tflag=l; /* e l s e r a i s e f l a g */ }  e l s e {temp=maxd; tflag=0;} i f - (temp<threshold4)  /* lower t r a c k e r f l a g */ /* t e s t f o r t r a c k i n g l o s s */  {  if {  (tlflag)  /* i f f l a g i s up, e x i t */  printf("tracking loss \n"); break;  78  } else  tlflag=l;  /* r a i s e t r a c k i n g  l o s s f l a g */  }  else tlflag=0; /* lower t r a c k i n g l o s s f l a g */ } j=j-i; maxd=max; /* form d e c i s i o n v a r i a b l e s */ g = cqO*cil-ciO*cql; 'h = (cO-cl)12; /* decode and b u f f e r I and Q */ i f (g-h<=0) /* channel d a t a */ { i f (g+h>=0) {*(bufi+i)=0; *(bufq+i)=0;} else {*(bufi+i)=0; *(bufq+i)=1;} }  else { i f (g+h>=0).{*(bufi+i)=1; *(bufq+i)=0;} else {* ( b u f i + i ) =1; * (bufq+i) =1'; } }  p r i n t f ( " % e %e %e %e %e %e \n",cO,cl,de,dl,g+h,g-h); */ reed(); /* r e a d c o r r e l a t o r s */ cO = c i 0 * c i 0 + cq0*cq0; /* form magnitudes squared */ cl = c i l * c i l + cql*cql; de = d i e * d i e + dqe*dqe; dl = d i l * d i l + dql*dql; (c0>=cl)?(max=cO,shftd=0) : (max=cl,shftd=ESHIFT) '; /* end o f w h i l e l o o p */ /* r e s e t IF b o a r d */ asm ( " push ARO asm ( " push AR1 asm( " l d p k @o_addr asm ( " Ida @o_addr, ARO asm ( " l d p k @rst asm ( " Ida @rst, AR1 asm ( " s t i AR1,*AR0 asm( " pop AR1 asm( " pop ARO o u t f i l e == fopen("re_datac","w") /* decode s h i f t s and w r i t e t o f i l e */ f o r (i=0;i<datacount/2+l;i++) { v a l u e i = *(bufi+i),• valueq = *(bufq+i); f p r i n t f ( o u t f i l e , " % d %d ", v a l u e i , v a l u e q ) ; }  fclose(outfile); }  '/* end o f main */  79  assembler r o u t i n e f o r r e a d i n g . v e r s i o n 40 .text .globl _reed .globl _ c i 0 . g l o b l _cq0 .globl _ c i l .globl _ c q l .globl _ d i e . g l o b l _dqe .globl _ d i l .globl _ d q l reed: ldpk @il_addr Ida @il_addr,AR0 l d p k @i2_addr Ida @i2_addr,ARl l d f *AR0,R1 l d p k ©_ci0 s t f Rl,@_ci0 l d f *AR0,R1 l d p k 0_cq0 s t f Rl,@_cq0 l d f *AR0,R1 ldpk @_cil stf Rl,@_cil l d f *AR0,R1 l d p k @_cql s t f Rl,@_cql l d f *AR1,R1 l d p k @_die s t f Rl,@_die l d f *AR1,R1 l d p k @_dqe s t f Rl,@_dqe l d f *AR1,R1 l d p k @_dil stf Rl,@_dil l d f *AR1,R1 l d p k @_dql s t f Rl,@_dql rets . data l_addr: 2_addr: . end  .word .word  correlators  I chan 0 c o r r e l a t o r i n p u t Q chan 0 c o r r e l a t o r i n p u t I chan 1 c o r r e l a t o r i n p u t Q chan 1 c o r r e l a t o r i n p u t d e l a y e d I chan e a r l y c o r r e l a t o d e l a y e d Q chan e a r l y c o r r e l a t o d e l a y e d I chan l a t e c o r r e l a t o r d e l a y e d Q chan l a t e c o r r e l a t o r  ; c o r r e l a t o r i n p u t p o r t addr ; d e l a y e d c o r r e l a t o r i n p u t addr ,; r e a d from c o r r e l a t o r ; write to global  variable  ; r e a d from d e l a y e d ; write to global  00100041H 00100071H  variable  comm p o r t 0 i n p u t comm p o r t 3 i n p u t  80  correlator  fifo fifo  D.2 Pair of Complex Correlators  We s e t up a p a i r o f complex c o r r e l a t o r s t o l o o k f o r t h e 0 o r t h e 1 r e p r e s e n t e d by s h i f t e d o r n o n - s h i f t e d PN sequence produced by gen.c and c o r r e l a t e w i t h c o r r ( ) c o n t a i n e d i n f i l e cor.asm. C o r r ( ) a l s o r e a d s a s h i f t and a s l i d e from r e c . c . T h e r e . a r e 2 samples p e r c h i p . T h e s h i f t r e g i s t e r l e n g t h i s r e a d from r e c . c and determines the PN sequence. B e f o r e r e c e i v i n g , c o r r r e l a y s d a t a f i l e t o be t r a n s m i t t e d from r e c t o gen. */  #include <chan.h> /* f o r pow */ #include <math.h> /* f o r m a l l o c */ #include < s t d l i b . h > /* c o r r e l a t o r w r i t t e n i n assembler */ extern v o i d c o r r ( v o i d ) ; /* PN sequence l e n g t h */ i n t N; /* PN gen s h i f t r e g l e n g t h */ i n t M; i n t s t a g e [ ] = {1,1,1,1,1,1,1,1,1, 1};/* s h i f t r e g i s t e r f o r PN g e n e r a t o r */ i n t connect[10][10]={{1,0,0,0,0,0,0,0,0,0}, {1,1,0,0,0,0,0,0,0,0} {1,0,1,0,0,0,0,0,0,0} {1,0,0,1,0,0,0,0,0,0} {1,0,0,1,0,0,0,0,0,0} {1,0,0,0,0,1,0,0,0,0} {1,0,0,0,0,0,1,0,0,0} {1,0,0,0,1,1,1, 0,0,0} {1,0,0,0,0,1,0, 0,0,0} {1,0,0,0,0,0,0, 1,0,0}} /* c o n n e c t i o n v e c t o r s */ i n t *pn0, * p n l ; /* p o i n t e r s t o t h e PN sequences v o i d p n _ g e n ( i n t *pn0, i n t * p n l ) ; /* t h e PN's g e n e r a t i n g func */ m a i n ( i n t a r g c , char a r g v [ ] , char * envp[] , CHAN * i n _ p o r t s [ ] i n t i n s , CHAN * o u t _ p o r t s [ ] i n t outs) {  int flag; i n t datacount; i n t valuei=0; i n t valueq=0; i n t *p0; int * p l ; chan_in_word(&M,in_ports[0]); chan_out_word(M,out_ports[0]);  /* f o r p r o c e s s o r s y n c h r o n i z a t i o n /* f o r d a t a r e l a y */ /* f o r d a t a r e l a y */ /* p o i n t e r s t o a l l o c a t e d space */ /* r e a d M from r e c */ I* pass M t o g e n e r a t o r */  N = pow(2,M)-l; pO = ( i n t *) malloc(4*N+2) ; /* a l l o c a t e f o r a l i g n e d p o i n t e r */ p i = ( i n t *) malloc(4*N+2); i f (pl==NULL) c h a n _ o u t _ w o r d ( l , o u t _ p o r t s [ 1 ] ) ; e l s e c h a n _ o u t _ w o r d ( 0 , o u t _ p o r t s [ 1 ] ) ; /* i n d i c a t e t o r e c m a l l o c r e s u l t * A pnO = ( i n t * ) ( ( ( ( u n s i g n e d i n t ) p 0 » (M+l) )+1) « (M+l) ) ;' /* a l i g n e d */ pnl = (int *)((((unsigned int)pl»(M+l))+1)«(M+l)); /* p o i n t e r s */ c h a n _ i n _ w o r d ( & d a t a c o u n t , i n _ p o r t s [ 0 ] ) ; /* r e l a y d a t a count */ chan_out_word(datacount,out ports[0]); chan_in_word(&flag,in_ports[1]); /* r e a d from gen */ chan_out_word(flag,out_ports[1]); /* i n d i c a t e t o r e c e i v e r */  81  w h i l e ( v a l u e i != -1 ) { chan_in_word(&valuei,in ports[0]) chan_in_word(&valueq,in_ports[0]) chan_out_word(valuei,*out_ports [ 0] chan_out_word(valueq,out_ports[0] } pn_gen(pnO,pnl); chan_out_word(flag,out_ports[1]); chan_in_word(&flag,in_ports[0]); chan_out_word(flag,out_ports[0]); corr(); } v o i d p n _ g e n ( i n t *PN0, i n t *PN1) { i n t i , j , temp; f o r (j=0; j<N ; j++)  '/* r e l a y d a t a t o g e n e r a t o r */  /* i n i t i a l i z e PN's */ /* i n d i c a t e r e a d i n e s s t o r e c */ / * w a i t f o r r e c e i v e t o be ready */ /* f l a g gen t o i n d i c a t e ready */ /* c a l l c o r r e l a t o r f u n c t i o n */' /* PN sequence g e n e r a t o r  *I  .{  temp=0; *(PN0+2*j) = 1 - 2 * s t a g e [ 0 ] ; I* c o n v e r t (0,1) t o (1,-1) */ " *(PN0+2*j+l) = 1 - 2 * s t a g e [ 0 ] ; /* and double up t h e e n t r i e s */ *(PNl+((2*j+((2*N)+2)/2)%(2*N))) = *(PN0+2*j); /* s h i f t e d PN s e q */ ) =*(PN0+2*j); *(PNl+((2*j+l+((2*N)+2)/2)%(2*N)) f o r (i=0; i < M; i++) { temp = t e m p " ( s t a g e [ i ] ' c o n n e c t [ M - l ] [ i ] : i f (i<M-l) s t a g e [ i ] = s t a g e [ i + 1 ] ; } stage[M-l]=temp; }  assembler  r o u t i n e t o implement a p a i r o f r e a l - t i m e c o r r e l a t o r s  . v e r s i o n 40 . text .globl _corr . g l o b l _pn0 .globl _pnl . g l o b l _N ; setup l d p k @i_addr Ida @i_addr, ARO l d p k @q_addr Ida @q_addr, AR1 l d p k @is_addr Ida @is_addr, AR2 ldpk @o_addr Ida @o_addr, AR3 l d p k @_pn0 Ida @_pn0, AR4 l d p k ©_pnl Ida @_pnl, AR5 l d p k @_N Ida @_N, BK mpyi 2,BK l d p k ©center  correlator  ; ARO h o l d s I d a t a i n p u t p o r t addr ; AR1 h o l d s Q d a t a i n p u t p o r t addr ;' s h i f t / s l i d e i n p u t p o r t addr ; AR3 h o l d s output p o r t addr ; AR4 addresses AR5 N i for two  0 PN sequence  addresses 1 PN sequence s PN s e q l e n g t h c i r c u l a r a d d r e s s i n g mode samples p e r c h i p  82  delay: top:  ldi  ©center,R6  ; ADC o f f s e t  subi rptb ldi ldi  1,BK,RC delay *AR0,R8 *AR1,R8  ; r e a d o f f 2N samples,  Ida AR4,AR6 Ida AR5,AR7 l d i *AR2,IR1 nop *AR6++(IR1)% nop *AR7++(IR1)% l d i *AR2,IR0 l d i IRO, RC l d i 0,R10 l d i 0,R2 rptbd f i n l d i 0,R3 l d i 0,R4 l d i 0,R5  AR6 indexs 0 PN s e q AR7 indexs 1 PN s e q read' s h i f t i n t o IR1 shift correlators  lbuO lbuO subi subi mpyi mpyi addi addi mpyi mpyi addi addi mpyi mpyi addi addi  load zeroth byte load zeroth byte s u b t r a c t ADC o f f s e t  *AR0,RO *ARl,Rl' R6,R0 R6,R1 • RO,*AR6 ,R8 Rl,*AR6++5!>, R9 R8,R2 R9,R3 RO,*AR7 ,R8 Rl,*AR7++%,R9 R8,R4 R9,R5 R0,R0 R1,R1 RO,RIO R1,R10  f l o a t R2,R0 f l o a t R3,R1 f l o a t R4,R8 ' f l o a t R5,R9 f l o a t R10,R11 bz p r o t e c t r s q r f R11,R10 mpyf R10/R0 mpyf R10,R1 mpyf R10,R8 mpyf R10,R9 s t f RO,*AR3 brd top s t f R1,*AR3 s t f R8,*AR3 s t f R9,*AR3 p r o t e c t : l d f 0,R11 s t f Rll,*AR3 brd top s t f Rll,*AR3 s t f Rll,*AR3  create delay  read s l i d e r e p e a t s l i d e + 1 times RIO h o l d s sum o f I sample R2 h o l d s 0 I sum  squares  R3 h o l d s 0 Q sum R4 h o l d s 1 I sum R5 h o l d s 1 Q sum  I chan m u l t i p l y f o r 0 c o r r e l a t o r Q chan m u l t i p l y f o r 0 c o r r e l a t o r accumulate I chan 0 c o r r e l a t i o n accumulate Q chan 0 c o r r e l a t i o n mult and accumulate for 1 correlator  I Q I Q  chan chan chan chan  sample sample sum o f sum o f  square square squares squares  R l l h o l d s sum o f squares p r o t e c t a g a i n s t zero d i v i s i o n RIO h o l d s r e c i p r o c a l s q r t n o r m a l i z e d 0 I c o r r e l a t o r output n o r m a l i z e d 0 Q c o r r e l a t o r output n o r m a l i z e d ! I c o r r e l a t o r output n o r m a l i z e d 1 Q c o r r e l a t o r output  output c o r r e l a t o r  output  83  zeroes  results  s t f R11,*AR3 .data i_addr: .word 00100061H q_addr: .word 00100081H i s _ a d d r : .word 00100071H o_addr: .word 00100072H center: .word 0000007EH . end  comm p o r t coram p o r t comm p o r t comm p o r t ADC o f f s e t  2 input f i f o 4 input f i f o 3 input f i f o 3 output f i f o (127)  D.3 Tracking Correlators /*  We s e t up a p a i r o f c o r r e l a t o r s t o l o o k f o r t h e 0 o r t h e 1 r e p r e s e n t e d by s h i f t e d o r n o n - s h i f t e d PN sequence produced by gen.c and c o r r e l a t e w i t h c o r r ( ) c o n t a i n e d i n f i l e cor.asm. C o r r ( ) a l s o reads a s h i f t and a s l i d e from r e c . c . There a r e 2 samples p e r c h i p . The s h i f t r e g i s t e r l e n g t h i s r e a d from r e c . c and determines the PN sequence. */  # i n c l u d e <chan.h> /* f o r pow */ #include <math.h> /* f o r m a l l o c */ #include <stdlib.h> c o r r e l a t o r w r i t t e n i n assembler extern v o i d c o r r ( v o i d ) ; PN sequence l e n g t h */ i n t N; PN gen s h i f t r e g l e n g t h */ i n t M; i n t connect[10][10]={{1,0,0,0,0,0,0,0,0,0} {1,1,0,0,0,0,0,0,0,0}, {1,0,1,0,0,0,0,0,0,0}, {1,0,0,1,0,0,0,0,0,0}, {1,0,0,1,0,0,0,0,0,0}, {1,0,0,0,0,1,0,0,0,0}, {1,0,0,0,0,0,1,0,0,0}, {1,0,0,0,1,1,1,0,0,0}, {1,0,0,0,0,1,0,0,0,0}, {1,0,0,0,0,0,0,1,0,0}}; /* c o n n e c t i o n v e c t o r s */ i n t s t a g e [ ] = {1,1,1,1,1,1,1,1,1,1}; /* s h i f t r e g f o r PN g e n e r a t o r */ i n t *pn0, * p n l ; I* p o i n t e r s t o t h e PN sequences v o i d p n _ g e n ( i n t *pn0, i n t * p n l ) ; I* the PN's g e n e r a t i n g func */_ m a i n ( i n t argc, char * a r g v [ ] , char *envp[], CHAN * i n _ p o r t s [ ] , . i n t i n s , CHAN * o u t _ p o r t s [ ] , i n t outs) { int flag; I* f o r p r o c e s s o r s y n c h r o n i z a t i o n * i n t *p0; /" p o i n t e r t o a l l o c a t e d space */ int *pl; chan_in_word(&M,in_ports[0]); /* r e a d M from r e c */ N = pow(2,M)-l; pO = ( i n t *) malloc(4*N+2); /* a l l o c a t e f o r a l i g n e d p o i n t e r */ p i = ( i n t *) malloc(4*N+2); pnO = ( i n t * ) ( ( ( ( u n s i g n e d i n t ) p 0 » ( M + l ) ) + 1 ) « ( M + l ) ) ; /* a l i g n e d */ p n l = ( i n t * ) ( ( ( ( u n s i g n e d i n t ) p l » ( M + l ) ) + 1 ) « ( M + l ) ) ; /* p o i n t e r s */ pn_gen(pnO,pnl); / i n i t i a l i z e PN's */ chan_out_word(flag,out_ports[1]); /* i n d i c a t e r e a d i n e s s t o r e c */ chan_in_word(&flag,in_ports[0]); / w a i t f o r r e c e i v e t o be ready */ chan_out_word(flag,out_ports[0]); I* f l a g gen t o i n d i c a t e r e a d y */ corr(.); /" c a l l c o r r e l a t o r f u n c t i o n */ i  i  84  }  v o i d p n _ g e n ( i n t *PN0, i n t *PN1) /* generate { i n t i , j , temp; f o r (j=0; j<N ; j++) { temp=0; *(PN0+((2*N-l+2*j)%(2*N))) = 1 - 2*stage[0] *(PN0+((2*N+2*j)%(2*N))) = 1 - 2*stage[0] *(PNl+((2*N+l+2*j)%(2*N))) = 1 - 2*stage[0] *(.PNl+( (2*N+2+2*j)%(2*N) ) ) = 1 - 2*stage[0] f o r (i=0; i < M; i++) { temp = t e m p " ( s t a g e [ i ] ' c o n n e c t [ M - l ] [ i ] ) ; i f (i<M-l) s t a g e [ i ] = s t a g e [ i + 1 ] ; }  PN sequence */  /* e a r l y c o r r e l a t o r */ /* l a t e c o r r e l a t o r  */  .  stage[M-l]=temp; }  assembler  r o u t i n e t o implement a p a i r o f r e a l - t i m e c o r r e l a t o r s  . v e r s i o n 40 .text .globl _corr . g l o b l _pn0 .globl _pnl . g l o b l _N . setup l d p k @i_addr Ida @i_addr, ARO l d p k @q addr Ida @q_addr, AR1 l d p k @is_addr Ida @is_addr, AR2 l d p k @o_addr Ida @o_addr, AR3 l d p k @_pn0 Ida @_pn0, AR4 l d p k @_pnl Ida @_pnl, AR5 l d p k @_N Ida @_N BK mpyi 2,BK l d p k ©center l d i ©center,R6 (  correlator  ARO h o l d s I d a t a i n p u t p o r t addr AR1 'holds Q d a t a i n p u t p o r t addr shift/slide  i n p u t p o r t addr  AR3 h o l d s o u t p u t p o r t addr AR4 addresses  e a r l y PN sequence  AR5 addresses l a t e PN sequence N i s PN s e q l e n g t h f o r c i r c u l a r a d d r e s s i n g mode two samples p e r c h i p ADC  offset  top: Ida AR4,AR6 Ida AR5,AR7 l d i *AR2,IR1 nop *AR6++(IR1)% nop *AR7++(IR1)% l d i *AR2,IR0 l d i IRO, RC l d i 0,R10 l d i 0,R2 rptbd f i n  AR6 indexes e a r l y PN s e q AR7 indexes l a t e PN s e q r e a d s h i f t i n t o IR1 shift correlators read s l i d e r e p e a t s l i d e + 1 times RIO h o l d s sum o f I sample R2 h o l d s e a r l y I sum  85  squares  l d i 0, R3 l d i 0, R4 l d i 0,R5 lbuO *AR0,RO lbuO *AR1, R l s u b i R6,R0 s u b i R6,R1 mpyi R0,*AR6 ,R8 mpyi R1,*AR6++%,R9 a d d i R8, R2 a d d i R9,R3 mpyi RO,*AR7 , R8 mpyi R1,*AR7++%,R9 a d d i R8,R4 a d d i R9,R5 mpyi RO , RO mpyi R1,R1 • a d d i R0,R10 a d d i R1.R10 f l o a t R2,R0 f l o a t R3,R1 f l o a t R4,R8 f l o a t R5,R9 f l o a t RIO,Rll bz p r o t e c t r s q r f Rll,RIO mpyf R10,R0 mpyf R10,R1 mpyf RIO, R8 mpyf R10,R9 s t f R0,*AR3 brd top s t f R1,*AR3 s t f R8,*AR3 s t f R9,*AR3 p r o t e c t : l d f 0,R11 s t f Rll,*AR3 brd top s t f Rll,*AR3 s t f R11,*AR3 s t f Rll,*AR3 .data i_addr: q_addr: is_addr: o_addr: center:  .word .word .word .word .word . end  00100061H 00100091H 00100041H 00100042H 0000007EH  R3 h o l d s e a r l y Q sum R4 h o l d s l a t e I sum R5 h o l d s l a t e Q sum load zeroth byte load zeroth byte s u b t r a c t ADC o f f s e t I chan mult f o r e a r l y c o r r e l a t o r Q chan mult f o r e a r l y c o r r e l a t o r accumulate I chan e a r l y c o r r accumulate Q chan l a t e c o r r m u l t i p l y and accumulate for l a t e c o r r e l a t o r  I Q I Q  chan chan chan chan  sample sample sum o f sum o f  square square' squares squares  R l l h o l d s sum o f squares p r o t e c t against zero d i v i s i o n RIO h o l d s r e c i p r o c a l s q r t n o r m a l i z e d 0 I c o r r e l a t o r output n o r m a l i z e d 0 Q c o r r e l a t o r output n o r m a l i z e d 1 I c o r r e l a t o r output n o r m a l i z e d 1 Q c o r r e l a t o r output  output c o r r e l a t o r r e s u l t s .  output  zeroes  comm p o r t 2 i n p u t f i f o comm p o r t 5 i n p u t f i f o comm p o r t 0 i n p u t f i f o comm p o r t 0 output f i f o ADC o f f s e t (127)  86  D.4 Transmitter Code  T r a n s m i t t e r code f o r word l e n g t h 1, q u a d r a t u r e d a t a t r a n s m i s s i o n over t h e I F l i n k . We r e a d from f i l e d a t a , copy the d a t a t o the on-board memory, and then t r a n s m i t a stream o f independent I and Q channel d a t a , w i t h t h e assembler f u n c t i o n t r a n ( ) , which i s t h e f a s t e s t p o s s i b l e t r a n s m i t t e r . T h i s t a s k goes on p r o c e s s o r C. */  # i n c l u d e <chan.h> # i n c l u d e <math.h> /* f o r pow */ #include <stdlib.h> /* f o r m a l l o c */ i n t N; /* l e n g t h o f t h e PN sequence */ i n t M; /* number o f PN g e n e r a t o r s t a g e s int len; /* N, used by t r a n s ( ) */ i n t s t a g e [ ] = {1,1,1,1,1,1,1,1,1,1}; /* s h i f t r e g f o r PN g e n e r a t o r */ i n t connect[10][10]={{1,0,0,0,0,0,0,0,0,0} {1,1,0,0,0,0,0,0,0,0}, {1,0,1,0,0,0,0,0,0,0}, {1,0,0,1,0,0,0,0,0,0}, {1,0,0,1,0,0,0,0,0,0}, {1,0,0,0,,0,1,0,0,0,0}, {1,0,0,0,, 0 1,0,0,0}, {1,0,0,0, 1,0,0,0}, {1,0,0,0, 0,0,0,0}, {1,0 , 0„ 0, 0,1,0,0}}; /* c o n n e c t i o n v e c t o r s */ i n t *pni; /* p o i n t e r t o I chan PN s e q */ i n t *pnq; /* p o i n t e r t o Q chan PN s e q */ int *bufi; /* p o i n t e r t o I chan i n p u t d a t a */ i n t *bufq; /* p o i n t e r t o Q chan i n p u t d a t a */ i n t count; /* d a t a count minus one */ v o i d p n _ g e n ( i n t * p n i , i n t *pnq) extern v o i d t r a n s ( ) ; /* f u n c t i o n w r i t t e n i n assembler */ m a i n ( i n t a r g c , char * a r g v [ ] , char * e n v p [ ] , CHAN * i n _ p o r t s [ ] , i n t i n s , CHAN * o u t _ p o r t s [ ] , i n t outs { int flag; /* f o r p r o c e s s o r s y n c h r o n i z a t i o n */ i n t valuei=0; /* f o r d a t a i n p u t */ i n t valueq=0; i n t i=0; /* a d a t a i n d e x */ i n t ESHIFT; int *pi; /* t o a l l o c a t e space */ i n t *pq; i n t datacount; chan_in_word(&M,in_ports[0]  )  /* r e a d M from c o r r e l a t o r '*/  87  N = pow(2,M)-1; l e n = N; ESHIFT = ( N - l ) / 2 ; f l e n g t h o f elem code s h i f t */ pi = (int *)malloc(2*len); f allocate for aligned pointer pq = ( i n t * ) m a l l o c ( 2 * l e n ) ; pni = (int *)((((unsigned int)pi»(M))+1)«(M)); /* a l i g n e d */ pnq = ( i n t * ) ( ( ( ( u n s i g n e d int)pq>>(M))+1)<<(M)); /* p o i n t e r s */ chan_in_word(&datacount,in_ports[0]); '/*' r e a d d a t a count */ count = datacount/2-1; bufi = calloc(datacount/2,1); /* a l l o c s t o r a g e f o r i n p u t d a t a bufq = calloc(datacount/2,1); i f (buf q==NULL) chan_out_word (1, out_ports.[ 0 ] ) ; e l s e chan_out_word(0,out_ports[0]); , while { (valuei!=-l)&&(valueq!=-l) ) /* r e a d and s t o r e d a t a /* d a t a t e r m i n a t e d by a { chan_in_word(lvaluei,in ports[0]) ; M b u f i + i ) = v a l u e i * E S H I F T •; I* s t o r e the s h i f t s */ chan_in_word(&valueq,in_ports[0]); *(bufq+i) = valueq*ESHIFT ; i + +; } pn_gen(pni,pnq) ;  /* i n i t i a l i z e  chan_in_word(&flag,in\_ports[0]); chan_in_word(&flag,in_ports[1]); trans(); while(1);  /* wait  ) v o i d pn_gen(int {  *PNI, i n t *PNQ)  PN's  */  f o r c o r r s t o be ready  /* t r a n s m i t  */  */  /* PN sequence g e n e r a t o r  */  •  i n t i , j , temp; i n t value; for  (j=0; j<N  ; j++)  {•  value = -l*stage[0]; *(PNI+j) = v a l u e ; *(PNQ+j) = v a l u e ;  /* c o n v e r t 1 t o a l l ones word */ /* s t o r e I chan PN sequence */ /* s t o r e Q chan PN sequence */  temp=0; f o r (i=0; i < M; i++) { temp = t e m p " ( s t a g e [ i ] ' c o n n e c t [ M - l ] [ i ] ) ; i f (i<M-l) s t a g e [ i ] = s t a g e [ i + 1 ] ; } stage[M-l]=temp;  assembler r o u t i n e f o r r e a l - t i m e  transmission  88  . v e r s i o n 40 .text .globl _trans .globl _ b u f i .globl _bufq .globl _ p n i . g l o b l _pnq .globl _ l e n . g l o b l _count  points, to I points to Q points to I points to Q PN sequence d a t a count  chan d a t a b u f f e r chan d a t a b u f f e r chan PN sequence chan PN sequence length  trans: push AR3 push AR4 push AR5 push AR6 push AR7 push R4 push R5 push R6 pushf R6 push R7 pushf R7 push R8  lpl:  lp2 :  l d p k @_len • l d i @_len,BK ldpk @ p n i l d i @_pni,R8 l d p k @_pnq l d i @_pnq,R9 l d p k @i_addr Ida @i_addr,AR2 l d p k @q_addr Ida @q_addr,AR3 l d p k @_bufi Ida @_bufi,AR4 l d p k @_bufq Ida @_bufq,AR5 l d p k @_count Ida @_count,AR6 l d i R8,AR0 l d i R9,AR1 s u b i 1,BK,RC l d i *AR4++,IR0 rptbd lp2 l d i *AR5++,IR1 nop *AR0++(IR0)% nop *AR1++(IR1)% l d i *AR0++%,R3 l d i *AR1++%,R5 s t i R3,*AR2 s t i R5,*AR3 s t i R3,*AR2 s t i R5,*AR3  ; f o r c i r c u l a r addressing ; R8 addresses p n i ; R9 addresses pnq ; I chan output p o r t ; Q chan output p o r t ; AR4 h o l d s I channel  data b u f f e r  ; AR5 h o l d s I channel  data b u f f e r  AR6 h o l d s d a t a count minus one s e t ARO t o p n i s t a r t addr s e t AR1 t o pnq s t a r t addr f o r r e p e a t mode r e a d I chan s h i f t i n t o IRO r e a d Q chan s h i f t i n t o IR1 s h i f t p n i index according to I data s h i f t pnq i n d e x a c c o r d i n g t o Q d a t a s t a r t of repeat block I/Q chan c h i p s i n R3/R5 w r i t e c h i p s t o output p o r t s repeat w r i t e f o r h a l f transmission  89  speed  db A R 6 , l p l pop R8 popf R7 pop R7 popf R6 pop R6 pop R5 pop R4 pop AR7 pop AR6 pop AR5 pop AR4 pop AR3 rets . data i_addr: q_addr:  .word .word  00100052H 00100062H  comm p o r t 0 output comm p o r t 1 output  . end  D.5 Application Configuration ! Hardware c o n f i g u r a t i o n processor root p r o c e s s o r second processor t h i r d processor fourth w i r e ? r o o t [ 0 ] second[3] w i r e ? second[0] t h i r d [ 3 ] wire ? third[0] fourth[3] wire ? fourth!0] root[3] ! Software c o n f i g u r a t i o n t a s k rec4 ins=2 outs=2 t a s k c o r r 4 ins=2 outs=2 t a s k c o r r d 4 i n s = l outs=2 t a s k gen4 ins=2 o u t s = l 0PT=C0DE p l a c e rec4 r o o t p l a c e c o r r 4 second p l a c e gen4 t h i r d p l a c e corrd4 f o u r t h connect ? r e c 4 [ 0 ] c o r r 4 [ 0 ] connect ? r e c 4 [ l ] c o r r d 4 [ 0 ] connect ? c o r r 4 [ 0 ] gen4[0] connect ? c o r r d 4 [ 0 ] gen4[1] connect ? c o r r 4 [ l ] rec4[0] connect ? gen4[0] c o r r 4 [ l ] connect ? c o r r d 4 [ l ] r e c 4 [ l ]  90  fifo fifo  

Cite

Citation Scheme:

        

Citations by CSL (citeproc-js)

Usage Statistics

Share

Embed

Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                        
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:
http://iiif.library.ubc.ca/presentation/dsp.831.1-0077425/manifest

Comment

Related Items