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UBC Theses and Dissertations

The China Labour Code: its major issues and improvement 1996

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DESIGN, ANALYSIS, AND IMPLEMENTATION OF A DSP-BASED MODEM FOR CODE-PHASE-SHIFT KEYING by ROBERT G. LINK Ph.D.(Physics), The University of British Columbia, 1989 A THESIS DRAFT SUBMITTED IN PARTIAL FULFILLMENT OF T H E REQUIREMENTS FOR T H E DEGREE OF MASTER OF APPLIED SCIENCE in T H E FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA © Robert G. Link, October 1996 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of E ^ g ^ W . C a l \ l A O I v > 0 0 A A ti • ..... ^ . . . N ••' -U The University of British Columbia Vancouver, Canada P e l vs mi Date DE-6 (2/88) Abstract This thesis presents the design, analysis, and implementation of a radio-frequency modem which employs the Code-Phase-Shift Keying (CPSK) method of Direct-Sequence Spread-Spectrum (DS-SS) signaling. A correlation receiver is designed for a DSP based implementation. The received RF signal is brought to a digitally represented base-band signal by product demodulation at the nominal RF frequency, followed by low-pass filtering and dual-channel 8 bit sampling at 2 MSPS. Base-band signal processing is done on a quad TT TMS320C40 general purpose DSP. The SS spreading factor is user selectable from a range of 7 to 127; with corresponding data rates in the range 100 to 9.4 KBPS. The herein designed tracking and acquisition algorithms are adapted from those of conventional DS-SS systems; while the carrier-phase tracking problem is solved by a new method hereby called Phase-Invariant-Reception (PIR). Extensive bit-error-rate (BER) measurements have been made in Additive White Gauss- ian Noise (AWGN) and in the presence of single tone interference. A l l measured BER vs SNR or BER vs JSR curves are compared to those of an ideal optimal receiver. The imple- mentation loss, with respect to the optimal receiver, for single-channel data flow in A W G N is approximately 1.8 dB in power efficiency when the stationary receiver and transmitter use local oscillators of the same nominal frequency. The additional BER power efficiency loss as a function of the difference in frequency of the latter two oscillators, is obtained exactly analytically and is confirmed experimentally. The main contributions to the suboptimal BER performance are due to approximating the optimal correlator with an analog filter plus digital correlator, to tracking the timing slippage, and to using PIR instead of optimal coherent reception. The performance of the analog filter/digital correlator combination is obtained approximately analytically, and found to be independent of the signal-to-noise ratio. The BER degradation incurred by the tracking is derived analytically and found to be negligible for the timing error induced by the typical present day TTL clock oscillators, unless the SNR is very high. The theoretical BER performance of PIR is obtained exactly analytically, and found to approach that of coherent reception as the SNR increases. In addition, measured data for the mean time-to-acquire and the mean time-to-lose- lock in A W G N is presented; along with an outline on how these curves could be obtained analytically, and their implications for packet transmission. ii Table of Contents Abstract ii List of Figures . . vi List of Tables viii Acknowledgments ix Chapter 1 Introduction 1 Section 1 Spread-Spectrum Communications: Motivation and Applications 1 Section 2 Objective and Outline of This Thesis 2 Chapter 2 Introduction to DS-SS and CPSK 4 Section 1 Standard Direct-Sequence Spread-Spectrum with Binary-Phase-Shift Keying 4 Section 2 Code-Phase-Shift Keying DS-BPSK-SS 7 Chapter 3 The Modem Implementation on a DSP Platform 11 Section 1 General Architecture and Implementation 11 Section 2 The C40 Based IF Transmitter 12 Section 3 The IF Receiver 13 Section 4 The Digital Demodulator 14 Section 5 The Tracking and Acquisition Algorithms . 16 Section 6 DSP On Board Results 19 Section 7 Experimental Setup 21 Chapter 4 Steady-State Performance of the Coherent Receiver 23 Section 1 Approximating The Optimal Correlator 23 Section 2 BER Performance In The Presence of Timing Slippage . . . . 28 Section 3 Experimental BER in AWGN Performance with Carrier-Wave Synchronization Imposed Externally 33 iii Chapter 5 Solving the Carrier-Wave Synchronization Problem by PIR for CPSK . 35 Section 1 Phase-Invariant Reception 35 Section 2 BER For Real Data over the Complex Channel with AWGN — Theoretical Analysis and Experimental Results 38 Section 3 BER Performance of PIR for Time Varying Phase .42 Section 4 BER For Complex Data Flow with AWGN 45 Chapter 6 The BER Performance of CPSK in the Presence of Single-Tone Interference 48 Section 1 Theoretical Analysis for Coherent Reception . . . 48 Section 2 Theoretical Analysis and Experimental Results for PIR . . . . 50 Chapter 7 Tracking and Acquisition in AWGN 53 Section 1 Mean Time to Acquire 53 Section 2 Mean Time to Lose Lock 55 Chapter 8 Conclusions .58 Bibliography 60 Appendix A Maximal Length PN Sequence Generation 61 Appendix B IF Transmitter Modules 63 Section 1 Digital Communication Port Interface 63 Section 2 Level Shifter and Amplifier 64 Section 3 BPSK Modulator and Bandpass Filter 65 Appendix C IF Receiver Modules 68 Section 1 BPSK Demodulator and Low Pass Filter . . 68 Section 2 Analog/Digital Converter 69 Section 3 ADC Converter Control 70 Section 4 FIFO Memory Banks 71 Section 5 FIFO/TMS320C40 Communication Port 73 iv Appendix D DSP Code Listings 75 Section 1 Master Receiver 75 Section 2 Pair of Complex Correlators . . . . 81 Section 3 Tracking Correlators 84 Section 4 Transmitter Code 87 Section 5 Application Configuration 90 V List of Figures Figure 1 Conventional DS-BPSK-SS System 4 Figure 2 CPSK Transmitter 7 Figure 3 Synchronized CPSK Receiver 8 Figure 4 Probability of Symbol Error vs. SNR for CPSK with Coherent Reception in AWGN 9 Figure 5 Wireless Spread-Spectrum Modem Block Diagram 12 Figure 6 C40 Based IF Transmitter Block Diagram 13 Figure 7 IF Receiver Block Diagram 14 Figure 8 Digital Demodulator Block Diagram 15 Figure 9 Timing Decision Algorithm in Acquisition Mode . 18 Figure 10 Timing Decision Algorithm for Tracking . . 19 Figure 11 Experimental Setup for Measuring BER in AWGN 21 Figure 12 Analog Correlator 23 Figure 13 Analog Filter with Digital Correlator 23 Figure 14 LPF Response To a Square Pulse Chip 25 Figure 15 Signal-to-Noise Ratio for a Sampled Low-Pass Filtered Chip as a Function of LPF Cut-off Frequency 28 Figure 16 Two-State Markov Chain 29 Figure 17 Signal Space for Tracking Performance Calculation 31 Figure 18 BER Performance in AWGN with Tracking 33 Figure 19 Bit Error Rate vs Signal-to-Noise Ratio for M=2 and M=4 CPSK with Carrier-Wave Synchronization Imposed Externally . . . . 34 Figure 20 Quadrature CPSK Transmitter . 35 Figure 21 Quadrature Demodulation followed by Complex Correlation . 36 Figure 22 BER vs. Signal to Noise Ratio for PIR with Real Data over Complex Channel, Word Length 1 . 42 Figure 23 Output SNR As a Function of Rx and Tx LO Frequency Difference 8 = df/f c 45 Figure 24 Symbol Error Rate vs Signal-to-Noise Ratio for Complex Word Length 1 Data in AWGN 47 vi Figure 25 Theoretical and Experimental BER versus JSR at SNR=12.0 dB with 8u = 0.1wc • • • • • 5 2 Figure 26 Mean Time-to-Acquire Measured in Data Symbol Durations vs SNR for G=63 55 Figure 27 Markov Chain for Tracking Loss Calculation 56 Figure 28 Mean Time-to-Lose-Lock Measured in Number of Data Symbols vs. SNR .57 Figure 29 Three-Stage Maximal Generator 61 Figure 30 l-Sequence Autocorrelation Function 62 Figure 31 Communication Port Interface (one channel) 64 Figure 32 Level Shifter and Amplifier 65 Figure 33 BPSK Modulator and Filter . . . . . . . . . 67 Figure 34 BPSK Demodulator and Low Pass Filter 69 Figure 35 Dual Channel 8-Bit ADC . . 70 Figure 36 ADC Converter Control 71 Figure 37 FIFO Memory Banks . 72 Figure 38 FIFO/TMS320C40 Communication Port 74 v i i List of Tables Table 1 Maximum sampling rates and the corresponding data rates . 20 Table 2 Decision Variables for Phase-Invariant Decoding 37 viii Acknowledgments I wish to thank my research supervisor Dr. Victor C M . Leung for the direction he gave me, and for the leadership that he gave to the W L A N project, of which this work forms part. I thank the professors from whom I have learned about the theory of modern day telecommunication systems — these are Prof. Samir Kallel, Prof. Takis Mathiopoulos, and Prof. Victor C M . Leung. I also thank Professor Robert W . Donaldson for advice on my program and for having me on two earlier research projects, before letting me go to the W L A N project. A very special thanks go to our scientific engineer Hansen Wang for designing a portion of the modem hardware, for doing the P C B layout, for assistance with the modem testing, and for very valuable help in general. Thanks also go to Amiee Chan for assisting Hansen and I with the R F portion of the hardware design and construction. This work was supported by the Science Council of British Columbia through a Tech- nology B . C . Grant. ix Chapter 1 Introduction 1.1 Spread-Spectrum Communications: Motivation and Applications A spread spectrum communication system is denned to be one for which the transmitted signal occupies a bandwidth much larger than the minimum bandwidth necessary to send the information [1]. Every information signal modulates a spreading signal, called the code signal, which is independent of the data. At the receiver, recovery of the original signal is accomplished by despreading; whereby the received spread signal is correlated with a synchronized replica of the spreading signal. The signal thus recovered is then processed by the usual techniques for communication signal reception. The techniques for spreading are direct sequencing, frequency hopping, time hopping, and hybrids of these. The use of spread-spectrum techniques originated in the development, by the military, of communication systems highly immune to intentional interference by a jammer. The idea is that if many orthogonal signal coordinates are available to a communication link, and if only a small subset of these coordinates are used at any one time, a jammer who cannot determine the signal subset currently in use would be severely handicapped. Because the error performance of the system is a function of the received signal to noise ratio, against infinite power gaussian noise, increasing the bandwidth does not improve performance. However, when the noise comes from a jammer with fixed finite power, and with uncertainty as to where in the signal space the transmission is presently located, the error performance is significantly improved. The energy density of a spread signal can be made very low because the signal power is on average spread uniformly over the enlarged number of signalling coordinates. This makes the signal very difficult to detect; and in fact, to anyone who does not posses a synchronized replica of the spreading signal, the spread signal will appear to be random noise. These properties of high interference rejection and low probability of interception have been exploited to give rise to the multiple access technique called code-division multiple access (CDMA) wherein each user of the communication channel employs a unique spreading signal to locate herself in the common transmission band. In fact, the method has become the basis for the development of new cellular radio systems for personal communications l networks. The spreading signal is based on a pseudorandom sequence called a key. Each radio uses its own unique key for receiving transmissions, and each radio can transmit waveforms with the key corresponding to some other radio. The different keys correspond to sequences designed to have low cross-correlation and low autocorrelation properties. The low cross-correlation of two different keys insures that a receiver locked on to a signal will experience relatively little interference from any other signal of the same channel based on a different key. Similarly, the low autocorrelation of a key will mitigate multipath effects, because a signal due to a multipath component which arrives with a delay with respect to the signal to which the receiver is synchronized, will be strongly attenuated. Direct sequencing is discussed in detail in the next chapter. In the frequency hopping techniquê  the spreading is done by changing the carrier frequency of the transmitted signal, at a rate called the hop rate, according to the code sequence. With the time hopping technique, the code sequence is used to key the transmitter on and off. 1.2 Objective and Outline of This Thesis The objective of this thesis is to present the design, analysis, and implementation of a new radio-frequency (RF) direct-sequence spread-spectrum (DS-SS) modem which can enhance both the power efficiency and the bandwidth efficiency of the present day conventional DS- SS systems. It uses a technique called Code-Phase-Shift Keying (CPSK), which is first proposed in [2]. The presentation is organized as follows: In Chapter 2 an introduction is given to the code-phase-shift keying method of direct-sequence spread-spectrum signaling. The remaining chapters describe work by the author which constitutes original contribution. Chapter 3 documents both the design and the implementation on a digital signal pro- cessing (DSP) platform, of the modem. A correlation receiver is designed, and the problem of synchronizing the receiver to the baseband signal is solved. The synchronization to the bit intervals is achieved by an acquisition scheme which is a generalization of the simplest acquisition scheme for conventional DS-SS. A timing recovery algorithm to maintain the bit interval synchronization, called tracking, has been realized in a hardware efficient manner by a novel design. Optimal correlating has been approximated by a combination of analog filtering and digital correlating; and in Chapter 4, an analysis of the signal-to-noise ratio (SNR) degradation 2 incurred by this approximation has been estimated analytically. This chapter also contains theoretical analysis of the bit-error-rate (BER) in additive white gaussian noise (AWGN) performance of the herein designed signal tracking scheme. The implementation loss associated with the tracking scheme has been analytically estimated and found to be negligible for BERs less than 1 0 - 6 for the timing slippages induced by typical TTL clock oscillators. To close Chapter 4, measured BER performance in AWGN, of the receiver with the carrier- wave synchronization imposed externally, is presented. These measurements were performed to test the design, and to obtain an experimental confirmation of the analytic performance estimate thus far. The synchronization to the phase of the carrier wave problem is solved by a new method which is hereby named Phase-Invariant-Reception (PIR). This is presented in Chapter 5 along with a theoretical performance analysis and experimental results for the BER in AWGN. The degree to which PIR approximates optimal reception has been obtained exactly analytically as a function of the frequency difference between the carrier-wave and the local oscillator (LO) of the receiver. Chapter 6 gives theoretical analysis and experimental results on system performance in the presence of single-tone interference. A numerical expression for the BER performance of the coherent CPSK receiver has been obtained in AWGN and single tone interference. This is compared to the measured performance of the CPSK receiver employing phase-invariant reception. All claims to receiver performance have been verified, to within experimental uncertainty, by the bit error rate measurements. Chapter 7 presents experimental results on the acquisition and tracking performance of the receiver, and outlines the mathematical problems which need to be solved in order to predict these results theoretically. Mean time-to-acquire and mean time-to-lose-lock in AWGN data is reported, along with the implications for transmission data packet format. Chapter 8 finishes with the conclusions and discussion of future development. 3 Chapter 2 Introduction to DS-SS and CPSK 2.1 Standard Direct-Sequence Spread-Spectrum with Binary-Phase-Shift Keying At the modulator of a generic direct-sequence system, the information signal, of data rate Rd, is multiplied by a code signal with symbol rate Rc, called the code chip rate. The ratio G = Rc/Rd is equal to the factor by which the signal transmission bandwidth is spread. It is usually much greater than unity, and is called the processing gain. Since multiplication in the time domain transforms to convolution in the frequency domain, provided the information signal is relatively narrow-band, the product signal will have approximately the bandwidth of the spreading signal. At the demodulator, the received signal is multiplied by a synchronized replica of the code signal; thus collapsing the desired signal to its original bandwidth, while spreading any undesired signal in the same way that the transmitter spread the desired signal originally. The signal is subsequently passed through a bandpass filter, whose passband corresponds to the spectrum of the information signal, resulting in a high rejection of the interfering signal. The difference in output and input signal-to-noise ratios, in dBs, for a narrow band interferer is equal to the processing gain in dB. To see this in detail, refer to Figure 1 and consider the following analysis for the conventional coherent DS-BPSK-SS system. More details can be found in [3]. j(t) + ri(t) d(t) Hg)—Hg> s(t) p(t) PN generator 6 V2i;cosatt transmitter 4 > channel JJ> J()dt decision device ^coscM P(t) PN generator receiver Figure 1 Conventional DS-BPSK-SS System 4 The information sequence to be sent over the channel is represented by an antipodal pulse stream, d(t), where a pulse value of +1 represents a 0 bit, a pulse value of —1 represents a 1 bit, and the bit duration is Tb. This information signal is spread by multiplication with the antipodal chip stream p(t), with chip duration Tc = Tb/G. p(t) represents a periodic pseudorandom sequence called a pseudonoise (PN) sequence; the generation of which is discussed in Appendix A. It is required that p(t) be synchronized with d(t), so that each bit period accommodates precisely G chips. Finally, the spread signal modulates the carrier, to produce the transmitted signal: s(t) = V2Pd(t)p(t) cos u0t; (2.1) where P = Eb/Tb is the transmitter power, Eb is the energy of the signal representing one bit, and u0 is the carrier frequency in radians. With the receiver exactly synchronized to the bit interval, and to the carrier phase, the delay for the communication link can be taken to be zero, and the simplified block diagram, omitting the synchronization modules, of the system is as in Figure 1. We wish to consider the error performance of the idealized receiver for a channel which adds noise and interference to the transmitted signal. The channel output is r(t) = s(t)+j(t) + n(t); (2.2) where j(t) is narrow-band interference, centered at the carrier, of total average power Jav, and n(t) is additive white gaussian noise of power spectral density N0. Denoting the spread signal bandwidth as W, the value of the power spectral density of an equivalent wide-band interference is J0 = Jav/W. The received signal is despread, by correlating against p(i), and demodulated by corre- lating against \/2/Tb cos u0. Thus, after every Tb seconds, the BPSK detector outputs r = dy/Fb + J + N; (2.3) where d (= ±1) is the data bit for the Tb second interval, and the interference and noise components are respectively: J= ]/Ybl "P{t)j(t)™su0tdt (2.4) 5 • N=J— p(t)n(t) cosu0tdt. (2.5) V <b Jo The white noise has zero mean and variance E[N2} — N0/2; while the interference has zero mean, and in the limit of zero bandwidth, variance E[J2] = J0/2. The BPSK decision rule is to choose d — +1 if r > 0, and choose d = — 1 if r < 0. Assuming that d = ± 1 are transmitted with equal probability, one may take, without loss of generality, d = — 1; to compute the probability of bit error Pe. Pe = Pr{r > 0|d= -1} = P r { J + N > ^/Fb} (2.6) With the statistics of the interference gaussian arid independent of the thermal noise statistics, the bit error probability is given by * = Hv /i5z) i (2:7) where erfc is the complementary error function. Therefore; as previously mentioned, the spreading does not improve the error rate performance of Coherent BPSK in white noise. However, the effects of the narrow-band interferer are reduced by a factor equal to the processing gain. To implement Forward Error Correction (FEC) encoding in conventional DS-SS, the data stream is first encoded to a higher rate symbol stream by block or by convolutional encoding; which is then transmitted by the same transmitter as in Figure 1. The receiver structure for coherent reception is also the same except that the integration is now over the symbol period; and the resulting stream of decision variables is used by a more general decision device to form an estimate of the original data stream. To increase the data rate without increasing the required transmission bandwidth, while maintaining the high interference rejection capability, one can use M-ary modulation, in which a signaling alphabet of M different code sequences is used to transmit alphabet symbols representing multiple bit sequences. One such method, which offers the performance advantages of conventional Af-ary DS-SS systems; but also many implementation advantages over other M-ary DS-SS systems, is the CPSK method described in the next section. 6 2.2 Code-Phase-Shift Keying DS-BPSK-SS In the CPSK method, each of the M = 2k, where the word length k is the number of bits per symbol, signaling waveforms is obtained by a different phase shift (an integer number of chips) of a single PN maximal length code sequence p(t). It's autocorrelation function is R(r) = ^ PiiTcMi + r)Tc) = { G ' * T = °' G ' ^ """; »=o ^ -1, otherwise. (2-8) The transmitter, shown in Figure 2, groups the data into k-bit data symbols of duration T3. Each of these are represented by an integer ra, 0 < m < M — 1, which is used to select the signaling waveform pm(t) = p(t — mcTc); which is the phase shift by m c = m(G+l) jM chips of the non-shifted PN sequence p(t). The final up-conversion for transmission at carrier frequency u0 results in transmitter output (2.9) s(t) = V2Ppm(t)cosuj0t; where P = Es/Ts is the transmitter power, and Es is the energy of the signal representing a symbol (a PN sequence). d(t) Serial to Parallel k / fc Sequence Selector / * M Bank of PN Sequences m S(t) V P C O S C O J Figure 2 CPSK Transmitter For now, assume synchronization, so that the CPSK correlation receiver for coherent reception is as in Figure 3. The received signal, r(t) = s(t) +j(t) + n(t), is fed to a bank of M correlators, one for each alphabet member PN sequence pm(t). When the m-th symbol is sent, the output of the m—th correlator, after every symbol period, is rm — \J Ea -\- Jm -f- A^m j (2.10) 7 while the output of the other correlators, r{ for i ^ m, are r,- = -^y/£U + Ji + Ni. The noise and interference terms are (Vi | 0 < i < M — 1): Ji - J Pi(t)j(t) cosu0tdt Ni = J — / pi(t)n(t) cos Lo0t dt. \ +s Jo (2-11) (2.12) (2.13) r(t) © l2/XCOSC0fct P0(t) T_8 ()dt fT-s f()« fT_8 |()dt decision device and Mtok decode kto 1 parallel to serial d Figure 3 Synchronized CPSK Receiver The decision device decides in favor of the symbol corresponding to the correlator with the largest output. When the interference is a single tone jammer at the carrier wave frequency, j(t) = Acos(u0t + <f>), (2.14) the terms J, are equal for all i, and therefore do not affect the decision. Thus, the effects of a carrier-wave jammer are completely mitigated by CPSK signaling! When the single-tone interference is not precisely at the carrier-wave frequency, the decision is affected, and the noise performance of the receiver is degraded (but still much better than for conventional DS-SS). The analysis of this more complicated situation is left for Chapter 6. The white noise terms are independent, zero-mean, gaussian random variables with variances E[Nf] = N0/2; and therefore, when the spreading factor is much greater than unity, G » 1, the probability of symbol error in AWGN, Pe, is precisely that for coherent reception of M orthogonal signals [4]: r+OO / rot \ (M- l ) Pe{M,Ea/N0) = l- f{a-^E~s)[ f(8)dp) da; (2.15) J—oo \J—oo J where (2.16) E s /N 0 (dB) Figure 4 Probability of Symbol Error vs. SNR for CPSK with Coherent Reception in AWGN 9 Figure 4 shows a plot of the probability of symbol error as a function of symbol signal- to-noise ratio (SNR = Es/N0) for several values of M. Using the fact that an Af-ary symbol represents k = log 2 M bits, and that the energy of a bit is Ef, = Es/k; the symbol error probability as a function of symbol SNR can be converted to a bit error probability as a function of bit SNR. The BER (equal to the bit error probability), at a given bit signal-to-noise ratio decreases with increasing word length k. The power efficiency of a communication system operating at a certain BER is defined as the SNR required to attain the specified BER. The power efficiency of optimal coherent M-ary signaling for word length 1 is 3 dB poorer, for word length 2 is slightly poorer, and for word length 3 is better than that of coherent BPSK (at any BER). At word length 6, M-ary signaling outperforms BPSK by 3.5 dB at a BER of 10 - 5. In other words, at word length 6, in thermal noise, CPSK outperforms conventional DS-SS by 3.5 dB. The system discussed thus far is an idealization whose performance represents the upper limit which an implementation could realize. Synchronization of the receiver to the phase of the carrier wave, and to the time of the bit and chip intervals has been assumed for coherent reception. Hereafter, a set of synchronization modules are designed, and optimal correlators are approximated, to realize a complete receiver which approximates optimal coherent reception. 10 Chapter 3 The Modem Implementation on a DSP Platform 3.1 General Architecture and Implementation The development is aimed towards the construction of a wireless, high processing gain, high data throughput modem which transmits at radio frequency in an ISM band. (ISM bands are the industrial, scientific and medical bands in the gigahertz range over which unlicensed spread spectrum systems are employed.) See Figure 5 for the high level block diagram illustrating the general architecture. The signal processing unique to CPSK is done at the digital stage, which is implemented oh a general purpose DSP. To test this system, we have developed a prototype which operates at IF (chosen to be 140 MHz) thus allowing the performance to be evaluated by measurements taken with an RF channel simulator inserted into the IF link. An eventual RF modem could be built and on-air tested by integrating the present system with IF/RF up/down converters and RF transceivers. The general purpose DSP used is the QPC/C40B, built by Loughborough Sound Images, which is comprised of four T l TIM-40 modules, each of which hosts a Tl TMS320C40 and 96 kilowords of SRAM [5]. Of the four C40s; three are dedicated to the receiver, and one is dedicated to the transmitter. An optimizing C compiler along with a substantial run-time library has been purchased from 3L Software of Edinburgh [6]. However, the TMS320C40 C compiler does not produce satisfactory code for many of the time critical operations; as it does not seem to be aware of all'of the hardware — in particular, the circular addressing modes of the C40. Therefore, it was found necessary to code many of the software modules direcdy in TMS assembler. The code listings, (either in C40 C or assembler, depending on the module), are given in Appendix D. 11 RF/IF Converter & AGC L„*-> Receive t Transmit IF/RF Converter & Amplifier Quadrature Despread, Demod., Decode, LPF & Track, ADC Acquire t t IF LO PN code i QPSK Encode, Modulator Spread IF digital Data out Data in Figure 5 Wireless Spread-Spectrum Modem Block Diagram 3.2 The C40 Based IF Transmitter The digital modulator implementing the code-phase-shift keying, direct-sequence spread- spectrum signaling technique, as described in the previous chapter, uses a C40 to produce an asynchronous chip stream from the data file to be transmitted. During the transmission, the software is responsible for maintaining the C40 output communication port FIFO non- empty; while an interface reads from the C40 fifo and clocks the data into a level-shifter (converts TTL to bipolar) and amplifier. The resulting chip stream is then BPSK modulated onto the IF carrier by Mini-Circuits MIQY-140M quadrature modulator. This is followed by a bandpass LC filter (in-house constructed by the author due to the unavailability of an off-the-shelf unit) to remove the signal replicas produced at harmonics of the carrier by the modulator. See Figure 6 for the block diagram of the C40 based IF transmitter. The indicated modules are built on a PCB copperboard, and connected to the C40 by a high density, 0.025" pitch ribbon cable. A description and a circuit schematic for each of these modules is given in Appendix B.. , 12 TMS'C40 1 chan Comm 1 chan Level 1 chan BPSK Modulator Port Interface ^ — Shifter Q chan Q chan & Amplifier Q chan and Bandpass Filter RF Figure 6 C40 Based IF Transmitter Block Diagram 3.3 The IF Receiver The incoming IF signal is product demodulated and low-pass filtered so as to recover the baseband signal. The BPSK product demodulation is done with Mini-Circuits MIQY-140D quadrature demodulator. The ensuing low-pass filter not only removes the second and higher harmonics of the IF signal resulting from the product operation; but has a bandwidth chosen low enough to maximize the output signal-to-noise ratio of the BPSK signal demodulator. This is discussed in detail in the next chapter. The baseband signal is sampled at twice the chipping rate (or four time the chipping rate with a two-sample preaccumulation) by a dual-channel 8-bit ADC. The samples are synchronously written to a bank of four FIFO memories, and asynchronously read from the FIFOs and written to the DSP by four FIFO/TMS320C40 communication ports. As explained more fully in the next section, for each channel of data (I or Q), the tracking algorithm requires the same channel of data delayed by one data symbol — resulting in a total of four data streams to be processed by the digital demodulator. Figure 7 shows the high-level block diagram of the IF receiver. It was prototyped by the author and built on a full size PC AT printed circuit board as documented in [7]. Each of the modules indicated in Figure 7 is described in detail, with circuit schematics, in Appendix C. 13 Reset and Go/Stop Control TTL Clock Oscillator C40 Comm Port 5 Reset ^ FIFO/TMS320C40 Communication Ports (4) A/D Converter Control A/D Encode Signal Data Control 1 Port Arb. Data Read Control Local Oscillator BPSK Signal Demodulator 1 chan baseband • - • A/D Converter 8 bit 1 channel FIFO Memory • RF Signal Q chan baseband • 8 bit Q channel ̂ — Voltaqe (4 banks) Offset Control chan data C40 Comm Port 1 C40Comm Port 2 . Q chan data - — • Q chan data J l c h l C40 Comm Port 3 chan data C40 Comm Port 4 Figure 7 IF Receiver Block Diagram 3.4 The Digital Demodulator There are two primary methods of implementing a despreader for the standard DS/SS system: the code-matched filter and the serial correlator-accumulator technique. This is also the case in the CPSK signaling scheme, wherein the receiver employs a bank of correlators or matched filters — one for each of the possible phase shifts. In the code-matched filter technique, the entire reference PN sequence and each of its phase shifts corresponding to a data symbol are stored in separate length G registers; while the incoming signal samples are stored in another length G shift register. As the incoming signal moves chip by chip down the signal register, it will give a large positive correlation with one signal register when it contains a data symbol. In this method, no separate sequence acquisition is required, as the signal is acquired during the first complete symbol received. However, implementing this algorithm in software results in a prohibitively slow receiver because the cross-correlation between the signal sequence and each phase shifted PN sequence is computed once per chip. With a serial correlator-accumulator, one has an entire symbol period in which to compute the required cross correlations; and therefore we choose this technique, as it is appropriate for a DSP based implementation. 14 Figure 8 shows a block diagram of the digital receiver. The term m-correlator means a correlator which correlates against the PN sequence, pm(t), representing the m-th data symbol. sampled base-band signal f O-correlator 1 -correlator (M-l)-correlator correlator slide early m-correlator late m-correlator J I m timing decision device m-correlator output symbol decision m decode data out device symbol [D~| = 1 symbol delay Figure 8 Digital Demodulator Block Diagram Each correlator must process at the sampling rate (two times the chipping rate, Rc); whereas the symbol decision device must process at the correlators output rate (the data symbol rate times the number of symbols). With a fixed amount of processing power available for correlation at a given PN sequence length, the maximum chipping rate which the system can handle is inversely proportional to the number of data symbols (the number of correlators); whereas the data rate is proportional to the symbol word length, k, times the chipping rate. Because the number of data symbols is 2k, the data rate, Rd, is given by Rd = K¥; (3-1) for some constant K. Thus, the maximum data rate is obtained for word lengths 1 and 2. 15 Based on this finite processing power performance consideration, we choose to implement the word length 1 and word length 2 versions on the DSP. By adding more processing power, one could maintain the chipping rate constant as one increases the data symbol alphabet length. This would give a data rate proportional to the word length. This could be done by adding more processors to the DSP, or by implementing the correlators in hardware, and using the DSP for processing the correlator bank output. The latter approach is taken in [8]; where a RAKE receiver for conventional DS-SS is designed. The three processors dedicated to the digital demodulator share the tasks indicated in Figure 8 as follows: Processor A implements the symbol decision device, the timing decision device, and the symbol decoder. Processor B implements the bank of punctual correlators. Processor D implements the early and late pair of correlators required for tracking. (Processor C is dedicated to transmission). The one symbol delay required for the input sample stream to the early/late correlator pair is implemented in hardware by a FIFO on the IF receiver. Processor A is the master processor which controls the two slave processors implementing correlators. It reads from, and configures the correlators; reading and updating the configuration at the data symbol rate. 3.5 The Tracking and Acquisition Algorithms The system is designed for packet transmission. After initialization, the receiver enters it's acquisition mode, to perform the initial PN code synchronization, and remains in this mode indefinitely until it successfully acquires a signal. It then enters it's tracking mode; during which it continually fine adjusts the symbol interval synchronization, and decodes and stores the incoming data. It remains in this mode until it loses lock — either because of excessive noise or because the signal transmission has ended. It then passes the data, stored in the DSP's on board memory, to the host computer. The program may then be restarted. Each data packet must have a preamble, of sufficient length (discussed later), consisting of a string of the zeroth data symbol. This is followed by a special data sequence to flag the end of the preamble and the beginning of the original data. The data is also terminated by the special sequence. The data passed to the host by the modem will consist of the portion of the preamble remaining after the receiver achieved acquisition, the encapsulated data packet, and perhaps several bits decoded from noise before the receiver lost lock. It is left to the host to extract the encapsulated data packet. 16 In the acquisition mode, the data symbol correlators are precessed by a shift of two samples, (one chip) between every trial symbol read. With reference to Figure 8, the symbol decision device chooses the correlator with the largest output and passes that output to the timing device, the timing device outputs the two-sample correlator precession, and the symbol decode is not invoked. The early/late pair of correlators compute a one sample early and a one sample late (called slides) version of the correlation (with precessed correlator) corresponding to the symbol which gave the largest correlation on the trial precession. When a data symbol correlator output crosses a first threshold, the timing device compares the early and late correlator outputs with the on-time correlator output, and the maximum of the three is checked against a second higher threshold. If it is crossed, the timing device adjusts the precessed (shifted) correlators according to the one sample slide adjustment and on the next trial symbol read, checks if the largest correlation crosses a third threshold. If the acquisition is confirmed, it switches to tracking mode; if the acquisition is not confirmed, it stays in acquisition mode — increments the precession and repeats the tests. In this way, the signal can be acquired in the presence of a timing error less than or equal to the maximum timing error that the tracking module can handle. See Figure 9 for the timing decision device's algorithm for acquisition. The CPSK signaling method is well suited to this acquisition scheme because all M data symbol correlators contribute to the search on every trial. Therefore, to precess through an entire PN sequence length G; takes only G/M trials. In other words, the acquisition time for the CPSK scheme is cut down from the standard acquisition time for conventional DS-SS by a factor of M. 17 W read correlators punctual crosses threshold 1 no yes choose max of early, late, punctual precess correlators no no max crosses threshold2 yes adjust tracking ^ 1 read correlators max crosses threshold2 n yes 1 choose max of early, late, punctual enter tracking mode Figure 9 Timing Decision Algorithm in Acquisition Mode In tracking mode (refer to Figure 8), the symbol decision device chooses the correlator with the largest output and passes the symbol to the symbol decoder. This symbol also determines which shift of the PN sequence the early/late pair of correlators use for correlating against the one symbol delayed stream. If the early or the late correlator give a larger output than the punctual correlator, and the timing decision device has its flag raised for tracking adjustment in the corresponding direction, all the correlators are precessed by the plus one or minus one sample slide. If the flag was not up, it gets raised. If the punctual correlator gave the largest output, the flag is lowered. In other words, the correlators must indicate that the tracking must be adjusted in a particular direction twice in a row before the tracking adjustment is made. See Figure 10 for the timing device's tracking algorithm. It follows a similar algorithm to check for tracking loss.. 18 The timing decision device checks for loss of lock by raising a flag if the maximum of the punctual, early, or late correlator output falls below a threshold. If the flag was already up, the tracking is declared to be lost. If the maximum of the punctual, early, or late correlator exceeds the threshold, the flag is lowered. That is, the maximum of the punctual, early, or late correlator outputs must fall below the threshold on two consecutive data symbols before the tracking is declared to be lost — at which point the reception is aborted, and the stored data is then passed to the host. read correlators)- early or late corr > punctual ? raise tflag 1 no yes lower tflag adjust tracking Figure 10 Timing Decision Algorithm for Tracking 3.6 DSP On Board Results Before inserting the IF link, the DSP software was tested on-board by having the digital transmitter communicate directly with the digital receiver. Besides providing a test of the software functionality, this allows determination of the maximum sampling rate which the receiver can handle. Also, timing error can be simulated in real time by adding or deleting samples from the transmitted data stream. The receiver acquires and decodes the otherwise noiseless transmission successfully for a timing slippage as high as 1 sample for every 4 data bits. Because there are 2G samples per data bit, this translates to a maximum timing slippage of 12.5/G percent. 19 Table 1 shows the maximum sampling rates in MSPS and the corresponding data rate in KBPS for spreading factors of G = 2l — 1, and word lengths 1 and 2, for single channel and complex channel processing. shift reg len 1 PN seq len G k=l, single chan. k=2, single chan k=l, I+Q chan. MSPS KBPS MSPS KBPS MSPS KBPS 3 7 1.45 104 0.80 114 0.70 100 4 15 1.96 65.3 1.02 68.0 0.92 61.3 5 31 2.33 37.6 1.16 37.4 1.06 34.2 6 63 2.57 20.4 1.24 19.7 1.15 18.3 7 127 2.70 10.6 1.28 10.1 1.19 9.4 8 255 2.77 5.4 1.30 5.1 1.22 4.8 9 511 2.81 2.7 1.32 2.6 1.24 2.4 10 1023 2.83 1.4 1.32 1.3 1.24 1.2 Table 1 Maximum sampling rates and the corresponding data rates The maximum chipping rate is determined by the speed at which the receiver DSP modules can process. For word lengths of 1 or 2, and with G larger than the threshold value of 63, the inner kernel of the code implementing a correlator is the bottleneck. For G smaller than the threshold value, the bottleneck becomes the "intelligent" process which accepts the correlator outputs. We have not determined how much this threshold value of the spreading factor increases for word lengths higher than 2. 20 3.7 Experimental Setup Marconi 2022D Signal Generator Host PC 486DX4/100 i r DSP QPC/C40B Marconi 2031 Signal Generator IF transmitter IF receiver KAY 437A Attenuator H-P 8656B Signal Generator Wandel & Goltermannl White Noise Genertor (6 KHz - 25 MHz) Mini-Circuits ZSC-2-1 Summer/Splitter Mini-Circuits MCL SBL-1 Mixer Mini-Circuits ZHL-2-8 Amp. (28 dB) Figure 11 Experimental Setup for Measuring BER in AWGN The DSP is a full-sized PC AT card residing in a 16 bit expansion slot of the host 486 PC. It communicates with the IF transmitter and the IF receiver via the C40's 8-bit high speed parallel communication ports. 21 The Marconi 2022D signal generator provides the 140 MHz LO for the IF transmitter; while the Marconi 2031 signal generator provides the 140 MHz LO for the IF receiver. It should be stressed that the IF transmitter and the IF receiver are each driven by their own TTL clock oscillator as well; rendering them independent. The IF transmitter produces a 2.9 dBm double-sideband-suppressed-carrier signal cen- tered at 140 MHz, which is further attenuated by 30 to 50 dB, by the KAY 437A step attenuator. This signal is summed with the AWGN by Mini-Circuit's two-way, 0 degrees, ZSC-2-1 Summer/Splitter. The AWGN is produced at baseband by the Wandel & Goltermann White Noise Gen- erator; and is mixed up to the frequency range of the data transmission by Mini-Circuit's MCL SBL-1 frequency mixer, whose LO is provided by the Hewlett-Packard 8656B signal generator. The total signal (data plus noise), is brought back up in strength by 28 dB at the IF receiver front-end. The signal-to-noise power measurements were made at the IF receiver front-end with the Tektronix 497P Spectrum Analyser. The BER measurements were made by having the transmitter send a simple pattern of data bits (therefore, essentially random pattern of chips) and having the receiver operate like a BER analyser. It triggers on the first non-zero symbol, and counts the times that the decoded symbol stream does not match the pattern. 22 Chapter 4 Steady-State Performance of the Coherent Receiver 4.1 Approximating The Optimal Correlator In the DSP based implementation of the CPSK receiver, the baseband signal is sampled at twice the chipping rate, and the 2G samples representing a data symbol are correlated by an add and accumulate operation. Thus the integration in Figure 3 is approximated by a summation, and the optimal correlator is roughly approximated. To improve the approximation, we low-pass filter the baseband signal, y(t), before sampling it; and therefore, approximate the ideal analog correlator of Figure 12 by the combination of analog filter and digital correlator in Figure 13. y(t) J pm m (t) ]()dt Figure 12 Analog Correlator y(t) „ LPF sample • ^ 1 Z 2 G 0 1 1=0 p(t.) Figure 13 Analog Filter with Digital Correlator The resolution of the tracking scheme is one sampling interval, so that the position in the chipping interval of the pair of samples for one chip is a random variable. The purpose of this chapter is to show how the cut-off frequency of the low-pass filter (which filters the chips) can be chosen so as to maximize the output signal-to-noise ratio of the digital correlator for a PN sequence of chips. 23 The output signal-to-noise ratio of a filter or correlator, SNR 0 , at time T, is defined as the ratio of the instantaneous power of the output signal, -r0(T), to the average power in output noise n0(t): \ro(T)\2' S N R 0 = 1 y . (4.1) A matched filter or correlator, optimizes this ratio to the value for coherent reception: IE SNR 0 , o ; ) < = ^ . (4.2) We take the low-pass filter of Figure 13 to be first order RC; thus, with transfer function given by W ) = i + 7 W ( 4 ' 3 ) where the 3-dB bandwidth of the filter, fc, is given by >« = ds?- (4-4) We, require the output SNR of the digital correlator for the reception of 2G samples of the LPF output correlated against the PN sequence, p m (£,•), which takes values ± 1 . Start by calculating the output noise power M0. ' The ith sample of the low-pass filtered noise is / +oo h(r)n(tl - T)<1T; (4.5) •00 where h(r) is the impulse response of the LPF. Since the noise output is Yli=o Pm(U)ni, the average output noise power, obtained by taking the expectation of the noise output squared, is 2G 2G • K = ^2^2pm{ti)pm(tJ)E[nin:J}. (4.6) i=0 j-0 Using (4.5), the expectation E[n(ti)n(tj)] = \N08(ti - tj), and the fact that h(r) is the fourier transform of H(f); leads to E[ninj\ = | w 0 / c e - 2 ^ - * l . (4.7) Since the cutoff frequency, fc, is the same order of magnitude as T c _ 1 , and for i ^ j, \tj — U\ > Tc/2, the terms for which i = j are dominant. Furthermore, most of the terms n,: 24 in the sum (4.6) cancel for i ^ j; therefore, the sum (4.6) is approximately given by the sum of the i = j terms: Af0 = irGN0fc (4.8) To calculate the output signal power of the filter/correlator, we first need the sampled response of the LPF to a square pulse chip of duration Tc and amplitude A, as shown in Figure 14. The time origin is indicated by the circle, and the two sampling instances are indicated by the crosses. Let r be the time, as measured from the origin, of the first sampling instance. The second sampling instance occurs at time r + Tc/2. Let St be the time interval from the rising edge of the square pulse to the time origin. The tracking scheme (next chapter) keeps the sampling times synchronized to the chip intervals, to within 1 sampling interval, by maintaining maximum signal power. Therefore r takes a random value uniformly distributed in the interval [0,^TC]. +A - A 5 t / V / T Figure 14 LPF Response To a Square Pulse Chip St is determined by demanding that the well-known exponential solution to the first order RC circuit go from —A to 0 in time St: 0 = -A + 2A(l-e-s^Rcy, (4.9) which solves, using (4.4), for St to In 2 , St = ^ - r . (4.10) 2TT/C 25 The sampled response, SC(T) of the LPF to the chip, is the sum of the LPF output at the two sampling times: W ) " \ A ( c 6 - C - 6 - l ) c - ^ , f o r r € [ J r c - f t , i r c ] ; ( 4 " U ) where 6 is defined to be b = irfcTc. To obtain an approximate expression for r0(T), the response of the correlator to a synchronized (to within a sampling interval) PN sequence, we make use of (4.11) along with some of the general properties of maximal length PN sequences. We will assume that the LPF response to chips which are preceded by a chip of the same polarity is ±A. In other words, that the LPF output essentially reaches the voltage of the input when the input is held constant for longer than a chip duration. Once the LPF cut-off frequency is found, it can be checked that this assumption is consistent with the solution. One quarter of the chips of a maximal length PN sequence (of length G) are included in run lengths of 1; and there are G/4 runs of length greater than 1. Therefore, since 3G/4 chips are members of a run length greater than 1, and G/4 chips begin such a run length, there are G/2 chips preceded by a chip of the same polarity; and therefore the sampled signal strength of G/2 chips is approximately ±2A. The Gj\ chips that immediately follow a greater than length 1 run length have the signal strength magnitude depicted in Figure 15 and given exactly by (4.11). The G/4 chips that immediately follow a run length of 1 have a signal strength magnitude approximately given by (4.11). Therefore, since multiplication by the synchronized PN sequence gives all the samples positive polarity, the output of the digital correlator is approximately r0(T) = ±G(sC(T) + 2A). (4.12) It remains to average the output SNR of equation (4.1) over the random variable r. From (4.2) it follows immediately that 2A2TS So that with (4.12) and (4.8) substituted into (4.1), we have the ratio of the average output SNR0>opt = - ^ A (4.13) signal-to-noise ratio of the digital correlator, S N R 0 , to the output signal-to-noise ratio of an ideal analog correlator, S N R 0 ) 0 ; ) i : SNR 0 _ (i(2'+ g e(r))) 2 S N R 0 ) 0 p t 2b [ • 1 26 where the indicated average is with respect to r, and SC(T) is given by (4.11) with A set to unity. The average of SC(T) with respect to r is ^ 2 ( i . - ) + ^ ; ( 4 , 5 ) and the average of SI(.T) with respect to r is 4 = 4 ( l - l-f^j + 1 ( l O e - 2 6 + 14e- 3 f t - e~*b - 4 ) . (4.16) Substitution pf these last 2 equations into (4.14) yields the ratio of SNR's as a function of b = 7r/ cr c for the received data symbol. The optimization of (4.14) with respect to b is not well defined because the signal strength A was assigned to one half of the chips, when really these strengths should be subject to the optimization as well. Instead we optimize, with respect to b, the ratio of the average output SNR of the LPF due to the chip of Figure 14 to the output SNR of a filter matched to the chip. This ratio is given by: S N R ^ h f r = (SC(T)) _ ^ S N R 0 j m a < 2b and is plotted in Figure 15. Optimizing the ratio (4.17) with respect to b yields an optimal value for the chip of b = 2,28;. (4.18) which, when substituted into (4.14) for the symbol, yields S N R o 0.63 = -2.0 dB. • (4.19) S N R 0 j 0 p i The optimal value of b, as given_by (4.18), corresponds to the first order RC LPF cut-off frequency fc = 0.73T"1.. The extremely complicated complete optimization problem has here been simplified to something tractable by the approximations made above. Thus both the optimum value of the LPF cut-off frequency, and the performance degradation of -2.0 dB incurred by approximating the matched filter by the LPF followed by the digital correlator, should only be viewed as reasonable estimates. Experimentation with the hardware of the implementation 27 has lead us to the approximate optimal value of fc = 0.5T" 1 for which we have found an SNR degradation of only 0.8 ± 0.4 dB. By doubling the sampling rate and performing a two-sample preaccumulation, we find an SNR degradation of only 0.45 ± 0.4 dB. SNR., SNRo,, 1.5 2 2.5 3 3.5 4 rcfcTc Figure 15 Signal-to-Noise Ratio for a Sampled Low-Pass Filtered Chip as a Function of LPF Cut-off Frequency 4.2 BER Performance In The Presence of Timing Slippage In this chapter, we evaluate the BER in AWGN performance degradation for coherent reception, due to the fact that the receiver is not always exactly on track, even to within the one sample timing resolution. Recall from chapter 3 that at every data symbol interval, the output signal strength of the correlator corresponding to the data symbol being received is compared to the output signal strength of the corresponding correlator synchronized to the signal delayed by one sampling interval, and to the output signal strength of the corresponding correlator synchronized to the signal advanced by one sampling interval. If the delayed or advanced correlator has a higher output than the oh-time correlator, the sample stream is shifted with respect to the on-time correlator appropriately. Let So denote the state in which the receiver is synchronized to within the one sample resolution; S\ denote the state in which the receiver synchronization is off by one sample; and S2 denote the state in which the receiver synchronization is off by more than one sample. 28 The receiver tests for state S2 by checking if the signal strengths of the on-time, delayed, and advanced correlators all fall below a threshold. If it tests positive for state S2, the receiver leaves its tracking and data decoding mode and returns to the state in which it is searching for a new transmission. When the receiver is in state 5*2, the probability of exiting the tracking/data decoding mode is very high, so that the probability of state S2 is very low; and we approximate the problem by assuming that the probability of state .92 is zero. We have checked this approximation, in the absence of timing slippage, by including state £2 in the analysis, and have obtained the same result as that of the following calculation. Therefore, we approximate the receiver when it is in tracking/data decoding mode by the two-state Markov chain depicted in Figure 16. The solution for the two-state chain state Figure 16 Two-State Markov Chain probabilities, Po, Pi, as functions of the state-transition probabilities P^j, can be obtained from the detailed balance equations PoPo,i = PiPi,o- , 1 Po Pl = 1 + ^0 ,1 /^1 ,0 1. . (4.20) 1 + /V0//V1 Let BERo and B E R i denote the bit-error rates when the receiver is in state So and Si, respectively. Then the average bit-error rate is given by B E R = BERnPo + B E R i P i . (4.2T We take the word length 1 case, so that BERQ is the ideal BER given by (2.15) for the M= 2 case: . ' . . B E R , = P« = lerfc U § - (4.22) 29 The correlator output is down by a factor of approximately 3 dB when the receiver is 1/2 chip off-track; therefore B E R i is given by the expression for BERo with 6 dB less SNR. It remains to determine the state-transition probabilities. The transition probability from state So to state S\, Po,i> has two components. One is due to the AWGN which can cause the output signal strength in either the early or the late correlator to be greater than that of the on-time correlator, even though the receiver is actually on track. The other is due to a drift of the chip time interval of the transmitted stream relative to the sampling times of the receiver. The latter, for stationary transmitter and receiver, is due to a frequency difference of the transmitter's and receiver's TTL clock oscillator. Let N^/2 denote the number of data bits received in the mean time, tAj2, that it takes the receiver's clock to drift by one sampling interval relative to the transmitter's clock. The component of Po,i due to the clock drift is equal to l/N-y^. Let A denote the percent frequency difference between the two clock oscillators: where fT and ft are the receiver and transmitter clock frequencies, respectively. Then To determine the component of Po,i due to the AWGN, we need the probability, po,i, that the output, ro, of the on-time correlator corresponding to the received data symbol is less than the output, r\/2, of the corresponding correlator which is displaced by 1/2 a chipping interval (one sampling interval) from the received data symbol. To obtain this probability, it is convenient to consider the embedding G-dimensional vector signal space with the orthonormal basis consisting of the normalized maximal length PN sequence and it's G — 1 code-phase-shifted versions. Let so, 5*1/2, a n d -si denote the on-time, 1/2 chip displaced, and 1 chip displaced signals, respectively. Since all the vector signals have length A = 1/r ~ ft fr (4.23) 1 (4.24) 2GA 30 y/E~s, s0 • .si = 0, and sb • J*j/2 = ' ^1/2 = the signal space in the SQ,SI plane is as in Figure 17. r o t a t e a n d | t r a n s l a t e ?1 °1/2 So VEs/2 ^E,/2 Figure 17 Signal Space for Tracking Performance Calculation For coherent reception, Figure 17 makes it clear that given that 5*0 is sent, the probability that the vector received is closer to .s*i/2 is (4.25) The way that the state-transition probability Po,i is related to po,i is dependent on the tracking algorithm. Recall that there are two components: P 0 , i = 2 ( P o , i ) 2 + (/Vi/2 (4.26) In the term due to the AWGN, the square is taken because the test for tracking in a particular direction must pass twice in a row on consecutive data bits before the tracking adjustment is made; and the factor of 2 is due to the fact that a tracking error can be made in either direction. Given that we are in state S\, to return to state So, the output of the correlator synchronized to the signal (an early or late correlator) must exceed the output of the correlator which is half a chip displaced (the correlator which is the on-time correlator when the receiver is on track). The probability of this occurring is 1 — po,i; and it must occur twice in a row before the tracker acts, therefore = (1 P0,l) • (4-27) 31 Equations (5.1) through (5.8) give the complete solution to the problem of determining the BER in A W G N with timing error. Figure 18 shows a plot of the BER as a function of the SNR for single-channel, word length 1, coherent reception with a particular choice of parameters. The ideal bit error rate is given by (5.3) and is plotted for comparison. With tracking in the presence of zero timing slippage there is a BER degradation corresponding to 0.35 dB at low SNRs up to about 13 dB, that increases to .5 dB at an SNR of 16 dB. With finite timing slippage, the performance depends on the spreading factor. The curve for the G = 63 PN sequence is shown for the case of timing slippage A = 5 x 10~ 6, and for the case of a timing slippage of A = 5 x 1 0 - 7 , which is typical between a pair of TTL clock oscillators. Over the relevant SNR range for data transmission, and the above spreading factor, it is not until.the BER of 6 x 10~6 for A = 5 x 10~ 6, and the BER of 2 x 1 0 - 7 for A = 5 x 10~ 7, that the timing slippage induces a performance degradation of 1 dB. At low SNR, the performance degradation, although practically negligible, is due entirely to the tracking errors caused by the noise. At high SNR the performance degradation is due almost entirely to the timing slippage. 32 E s / N 0 (dB) Figure 18 BER Performance in AWGN with Tracking 4.3 Experimental BER in A W G N Performance with Carrier-Wave Synchronization Imposed Externally The experimental results reported in this chapter were obtained by making a two-way, zero-degree split of the 140MHz Marconi 2031 signal generator output to provide the IF receiver and IF transmitter with the same LO. In addition to providing a test of the acquisition, tracking, and decoding algorithms, the reason for doing this is that it provides the BER performance limit for the present system upgraded to solve the carrier-wave synchronization problem (which we do in the next chapter). The approximation to optimal coherent reception thus far is quantified, allowing us to identify the additional performance degradation from optimal incurred by our solution to the carrier-wave synchronization problem. We have carefully checked that the BER performance of the word length 1, and word length 2, CPSK transmissions does not depend on the spreading factor G. Each point on the graph of Figure 19 represents the results of 25 measurements; 5 measurements at each 33 of the 5 spreading factors G = 7,15,31, 63,127. For comparison, the BER versus SNR curves for theoretical; optimal reception of M-ary signals for M = 2, and M = 4 are given on the same graph. In the BER range from 10~3 to 5 x 10~5 the implementation loss is 0.8 dB; of which we identify 0.35 dB as due to the effect of noise on tracking, and 0.45 dB as due to approximating the optimal correlator. As the BER's decrease from 5 x 10~5 to 10~7 the loss increases by another 0.2 dB; which we ascribe to a combination of intrinsic receiver noise and timing slippage. The experimental uncertainty on the SNR is approximately ±0.4 dB overall. The increments between the experimental SNR values have negligible experimental uncertainty. In other words, the shape of the experimental curves have very little uncertainty; but their horizontal placement is uncertain by 0.4 dB. 10^ F ' f"" ' 1 ' 1 ' 1 ' 1 1 1 ' 3 •j 0"8 I • 1 • I '. —. I . J : . I . I _. I 9.0 10.0 11.0 . 12.0 13.0 .14.0 15.0 16.0 E_s/N_o (dB) Figure 19 Bit Error Rate vs Signal-to-Noise Ratio for M=2 and M=4 CPSK with Carrier-Wave Synchronization Imposed Externally 34 Chapter 5 Solving the Carrier-Wave Synchronization Problem by PIR for CPSK 5.1 Phase-Invariant Reception Phase-Invariant Reception is a technique for demodulating a complex baseband data stream which does not require an estimate of the degree to which the I and Q channels have been rotated into one-another by the down-conversion from RF. It requires that the phase angle between the received complex RF signal and the local oscillator of the receiver be fairly constant over the duration of a data symbol. We first assume it to be exactly constant, and in a later section quantify the SNR degradation when it varies with time. d(t) d(t) Serial to Parallel IP) Serial to Parallel K / Sequence Selector / ^ M Bank of PN Sequences Serial to Parallel k Sequence Selector / VP coscoJ s(t) VPsincOot Figure 20 Quadrature CPSK Transmitter 35 © <2fT. C0SC0ot r(t) ^sincc^t m fT_s. J()d» r . m.l ' i ) 1 J()dl rm,Q Figure 21 Quadrature Demodulation followed by Complex Correlation Quadrature RF transmission for CPSK is realized with the transmitter of Figure 20; which is basically two copies, in quadrature, of the transmitter in Figure 2. The corresponding receiver is as in Figure 3, except that the RF demodulation produces a complex signal (with I and Q components) which is fed to a bank of correlators, each of which having two identical arms. Figure 21 shows the complex signal resulting from quadrature RF demodulation, and the ensuing complex correlator. The signal received at the demodulator now has both I and Q components: s(t) = V2PPl(t) cos(u0t + 0) + V2PpQ(t) sin(w 0i + 0); (5.1) where pj and Pq are the PN sequences representing the I and Q channel data symbols respectively, and P is the power of the transmission dedicated to a single channel. 0 is the phase angle difference between the carrier and the local oscillator of the receiver. The I and Q channel outputs of the quadrature demodulator, neglecting the double frequency components which get filtered off anyway, are obtained by multiplication by i /2/Ts cos Lo0t, and ^/2/Ts smu>0t, respectively: /(*) Q(t) -- T, Pl(t) cos 6 + pq(t) sin 0); -P!(t) sin 0 + pQ(t) cos 0). ;s.2) 36 Then the complex output, fm = ( r m j / , r m j g ) , of the m'th correlator is formed by multipli- cation by pm(t), followed integration over the symbol period: "El rmr = rm,Q G (cm,i cos 0 + c m > Q sin 6); G (-cmj sin 0 + c m > Q cos 9); (5.3) where c m > / (CT O JQ) is the correlation between the m'th PN sequence and the PN sequence- which represents the I (Q) channel data symbol. For. the synchronized system, c m > / equals G or —1, depending on whether the I channel carries the m'th data symbol or not, (and similarly for c m g ) . For the time being, consider the word length 1 case, and form the following two quantities which are invariant with respect to the phase rotation 0: h = ^ W , / + 4 Q - K / + r ; i 0 ) ) ; ( 5 4 ) g = - n y n . Q + rQ,QrlJ- 2h is the magnitude squared of the 0 correlator minus the magnitude squared of the 1 correlator; while g is the dot product of the 0 correlator with the rotation by 90 degrees of the 1 correlator. It is easy to check that when the (I,Q) dibit is received in the absence of interference and noise, that the invariants take the values shown in the Table 2. Therefore, d,Q) g h h-g . g+h (0,0) 0 +k +k +k (0,1) -k 0 +k -k (1,0) +k 0 -k +k (1,1) o -k -k -k Table 2 Decision Variables for Phase-Invariant Decoding g —h and g+h are the appropriate decision variables for the I and Q channel bits, respectively. For higher word lengths, one way of generalizing this scheme would be to first choose the two correlator outputs of the largest squared magnitude, and then apply the described scheme to decide on the I and Q channel data symbols. For single-channel (real) data transmission, the,same data symbol would be sent over the l a n d Q channel, and the decision variable 37 would simply be h. In this case, the generalization to higher word lengths is immediate: the decision variables are the magnitudes squared of the complex correlator outputs. The local oscillator of the receiver's IF to baseband demodulator runs freely at its nominal frequency LO0. With the conventional direct-sequence spread-spectrum demodulator with a free local oscillator, it is necessary to track the phase error because the decision variable for the two data symbols is based on the output of one complex correlator. The two data symbols (corresponding to bit 0 or bit 1) are 180 degree shifts in the I-Q plane of one another. PIR is possible for the CPSK method because different data symbols correspond to different complex correlators. In the next two sections we derive the BER performance of this technique in AWGN. To show that the decision variables continue to be independent of the phase rotation, it is convenient to represent the noise by the narrow-band representation: n(t) = n/(£) cos(cu0t + 9) — nq(t) sin(o>0£ + 9). (5-5) The I and Q channel quadrature demodulator outputs become 1 \ . sin 9: This form makes it evident that if the decision variables are independent of 9 in the absence of noise (which they are), then they are independent of 9 in the presence of noise as well. 5.2 BER For Real Data over the Complex Channel with AWGN — Theoretical Analysis and Experimental Results By real data over the complex channel, we mean quadrature transmission with the same data symbol in each channel. We will first calculate the.BER in AWGN for the M = 2 case. From this we will obtain a bound on the SER (data symbol error rate) for arbitrary M by means of the union bound for probability. Recall that for Phase-Invariant Reception, the decision variables are the magnitudes of the complex correlators. 38 In the last section it was shown that for PIR, that the phase angle 9 can be taken to be zero; so that for spreading factor, G, much greater than unity, the reception of the zeroth symbol results in the correlator output: r0,i = y/E~a + NQ>I ro,Q = \fE~s + N0,Q ^ n,i = NltI ri,Q = N1>Q] where Es = Ep/2, and the noise components are: Nhi = J pi(t)ri(t) cos io0tdt 2 (5.1 Ni,Q = Pi{t)n{t)smuj0tdt. ±b Jo These are independent gaussian random variables with zero mean and deviation a2 = N0/.2. For equally likely transmission of a zero or a one, the probability of error is equal to the probability of error conditioned on the reception of a zero: Pc(2,Eb/No) = Pv{\r0\<\r,\} /|f, i-|fbi ( « ) « « ; where | r 0 | = ^ ' o , ; + ro,Q' 1̂ 1 = y/r\,i + ri,Q> a n d f\fi\-\r0\ i s t h e probability density function for | n | — |rb|- By going to polar coordinates: r%,i = |r*i| cos 9i, (5-10) i'i,Q = \ri\sin 9l] the square-law transformation for random variables, which gives the probability density for \n\ in terms of the probability density for is obtained: / | f l ( a ) = f Jo ' a / ' ' i ( a c o s J ' a s i n * ) ^ ' for a > 0; . I 0, for a < 0. Since the probability density functions for ri are: . M ( « i , a 2 ) = 4 r e " ( c v M / A r ° ; (5.12) 39 the probability densities for are: 1 rl-K • /|f.|(a) = 4r / tte-«acose-v^)2+(-i^-^)2)/^^; (5.13) The general result for the. difference of two independent random variables, in the present notation, is r+oo / | * H ? o | ( « ) = / / | f , | ( « + ^ ) / | f b | ( ^ ) ^ - (5-14) J o The probability of error is given by (5.13) substituted into ,(5.14), substituted into (5.9). The resulting triple integral can be reduced to the following single integral: -2Eb/N0 Pi(2,Eb/N0)= ^ / d6[l (5.15) We have evaluated this integral numerically with Maple V, and plotted the BER (= Pt) has a function of the SNR (Eb/-N0). The theoretical curve is shown in Figure 22. For comparison, the curve for coherent reception (the best performance theoretically possible) of two orthogonal signals is given on the same graph. At zero frequency difference, (df = 0), between the carrier wave and the local oscillator of the receiver; at a BER of 10 - 3 , PIR is 1.1 dB less efficient than coherent reception; at a BER of 10 - 8 , PIR is 0.5 dB less efficient than coherent reception. In the limit of infinite SNR, the BER performance in noise of PIR approaches that of coherent reception. The reason that PIR does not do as well as coherent reception, is that the PIR decision variables are quadratics of the decision variables for coherent reception. The measured curve for df = 0 is shown as well; exhibiting an implementation loss, with respect to theoretical PIR, of 0.8 dB at the BER of 10 - 3 , and a loss of 1.1 dB at the BER of 10 - 6 . The total implementation loss with respect to coherent reception is approximately constant at 1.8 dB for any BER. The BER measurements were obtained by the experimental setup described in chapter 3. Each point represents 20 measurements, all taken with a spreading factor of 63. 40 In the next section, the performance degradation of a function of df is obtained ana- lytically. Figure 22 also shows the experimental curve at the value of df found to give a signal-to-noise degradation of 1 dB. The union bound gives an upper limit for the B E R , in A W G N , of M-ary orthogonal signaling in terms of the B E R for the M — 2 case. The symbol error rate, Pe, when all M signals are equally likely to be sent is Pe(M, Es/N0) < (M — 1)P£(2, Es/N0). , (5.16) In the case of coherent reception, the union bound upper limit becomes equality to within a percent for SERs lower than 1 0 - 4 . Also, in this S E R range, the S E R vs. S N R curves (see Figure 4) become practically straight lines (on the linear-log plot). Therefore, for this range of SERs, the power efficiency loss of PIR relative to coherent reception is no greater than the relative loss in the word length 1 case. 41 10"1 10"9 I • " -• i . i , i , i , i . i , I 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 E_b/N_o (dB) Figure 22 BER vs. Signal to Noise Ratio for PIR with Real Data over Complex Channel, Word Length 1 5 . 3 BER Performance of PIR for Time Varying Phase In this section we examine the effective loss in signal-to-noise ratio as a function of the difference in frequency between the carrier-wave and the local oscillator of the receiver for real data transmission. The quadrature demodulator output is given by (5.2), except that now 9 is a function of time. Let duj denote the difference in angular frequency between the carrier-wave and 4 2 the local oscillator of the demodulator. With 6 — dut, the I and Q channel outputs of the quadrature demodulator are: I(t) = ——pm(t)(cos divt + sin divt) ' ^ • ' • (5-17) Q(t) = ——pm(t)(cos duit — sin dut;) , J- s where pm(t) is the symbol being received. Let 8 denote the percentage of the chipping frequency by which the carrier-wave and local oscillator differ in frequency: 2TT8 . • du = otoc = -pfr- (5.18) J- c Then, provided that we have PN code alignment, with the integral of the correlator ap- proximated by a sum over chipping times, the output of the mth correlator due to the information-bearing part of the incoming signal is: I'm,I = Q S (cos(27ri<5) + sin(27ric?)) ( 8 ' 1 9 ) rm,Q = —^r- ^(cos(27ri<5) - sm(2ir i8)). Therefore, the magnitude squared of the mth correlator (equal to the effective bit energy) is ,l + r2m,Q = Elk(G,8); (5.20) where C7-1 G - l KG, s) = —2 E co<2<* - (5-21) J i=0 j-0 • k(G,8) is the ratio of the signal-to-noise ratio that the decision device uses, SNR 0 , to the signal-to-noise ratio of the signal at the receiver front end, SNR. *«™ = H . (5-22) Figure 23 shows a plot of k (in dB) as a function of 8 for the case G = 63. The curve shows that the output S N R is down from the received S N R by 1 dB at the value of delta equal to 4 x 1 0 - 3 . We have confirmed this using fslove of Maple V. At a chipping rate of 0.5 MHz (the rate supported by the implementation), this corresponds to a frequency difference of r2 m, 4 3 df=0.0021 MHz. We have also measured the BER at this frequency difference between the stationary transmitter's LO and stationary receiver's LO. The experimental curve is shown in Figure 22 of the previous section. To within experimental uncertainty, the BER degradation is indeed 1 dB. The frequency difference corresponding to a 1 dB degradation is 15 ppm. Commercial oscillators are available at 140 MHz that are accurate to within 15 ppm. For example, the Raltron VCOHF series 6700. The degradation of the SNR with increasing 6 here presented is not unique to Phase- Invariant Reception. Other systems we have found [9] which demodulate the carrier with a local oscillator at the nominal carrier frequency (ie. not a phase-locked loop), estimate the phase rotation 0, and rotate the complex demodulator output so as to remove the phase rotation from the decision variables. However, all such systems which only update the phase rotation estimate at the data rate, and not at the chipping rate, (these include the implementations [9] and [10]), suffer precisely the effective SNR loss herein calculated. 44 0 -11 S N R 0 SNR (dB) I— i— i— i—i— i— i—i—i— i—i—'—'— i—i— i—i—'—'— i— i—'—'— i i i . '— i—i— i— i— i—i—i—•— i— i—i—•— i - 0 1 2 3 ^ 4 5 6 7 (x1E-3) Figure 23 Output SNR As a Function of Rx and Tx LO Frequency Difference 8 = df/f c 5.4 BER For Complex Data Flow with AWGN As of this writing, we have not obtained an analytical expression for the BER in A W G N for PIR with independent I and Q channel data streams. Thus we rely on the experimental curve, and compare it to the theoretical curve for coherent reception for the case in which each channel carries one of two possible orthogonal signals. We refer to the data encoding for this scenario as complex word length 1 encoding. First we outline the as of yet to be solved problem for the theoretical BER. Suppose the dibit (0,0) is transmitted. Referring to the decoding table of figure (23), one sees that it is correctly decoded iff g — h < 0 and g + h > 0; that is iff — h < g < +h. The probability, Pc, of this occurring is Pc = / da / d/?/ h(a)/ g(/3|h = a); (5.23) Ja=0 Jp=-a 45 where /h(a) is the pdf for h, and / g(/?|h" = a) is the pdf for g conditioned on h. h and g are given by (5.4). One approach to deriving the conditional pdf for g is to transform to polar coordinates, (5.10), as was done to obtain the square-law transformation (5.11). The random variable g conditioned on h becomes g\h=a = |n|-\A* + l 7 " ^ ! 2 s m ($o — Derivation of a pdf for this function requires finding the inverse of the function f(r) = ir\/a + r2 — a problem we have not yet solved. However, we do have the measured, BER vs. SNR curve from which to evaluate the noise performance. The theoretical performance upper limit for quadrature transmission of two independent data streams, each of which carries orthogonal symbols from an alphabet of length 2, is given by coherent reception. In this case, the I-channel decision is independent of the Q-chanhel decision. The probability of a correct decision in one channel is 1 — Pe; with P e given by (4.22). The probability of a correct decision for a symbol representing an (I,Q) dibit is (1 — Pe)2. Therefore, the symbol error rate is SER = 1 - (1 - I',)1. -(5.24) Figure 24 shows the experimental SER has function of the SNR for PIR of complex data flow in AWGN; and the theoretical SER for coherent reception from the same transmission. To achieve an SER of 1 0 - 3 requires 3.0 dB more signal power for experimental PIR than for theoretical coherent reception. At an SER of 10~ 6, the loss is 3.4 dB. Provided that the implementation loss with respect to theoretical PIR is the same as the implementation loss for real data flow over the complex channel (Figure 22), we deduce that PIR is approximately 2.2 dB less power efficient than coherent reception for quadrature data transmission. Over the same SER range, for real data flow over the complex channel, PIR is approximately 0.9 dB less efficient than coherent reception (see Section 7.2). With coherent reception, going from single-channel to dual-channel transmission entails doubling the data rate and doubling the transmission power and achieving the same BER. With PIR, doubling the data rate by going to complex data flow at a. constant BER requires approximately another 1.3 dB of transmitter power in addition to the 3 dB required when using coherent reception for quadrature data transmission. 46 10"1 10"2 10"3 10"4 10-5 10"6 lO' 7 l- 10" 10" Coherent Reception Theoretical Phase Invariant Reception Experimental 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 E_s/N_o (dB) Figure 24 Symbol Error Rate vs Signal-to-Noise Ratio for Complex Word Length 1 Data in AWGN 47 Chapter 6 The BER Performance of CPSK in the Presence of Single-Tone Interference 6.1 Theoretical Analysis for Coherent Reception In [2], a general expression for the probability of error in AWGN and single tone interference is derived. This provided the basis for simulations of the performance for specific choices of spreading sequence, word length and jammer parameters. Unfortunately, the PN sequence length there chosen for the simulations is longer than can be accommodated by the hardware of the receiver that we have implemented. To allow a quantitative comparison between theory and experiment, in this section we. derive a numerical expression for the word length 1, PN sequence length 63 case. Consider a single-tone jammer of angular frequency to = LO0 + SUJ, with power Pj, at phase angle <j> with respect to the information signal: j{t) = y/2Pjcos{ut + <f,): % (6.1) For convenience, the amount by which the angular frequency of the jammer differs from that of the signal carrier is written as a percentage of the angular chipping frequency: SUJ = gujc = (6.2) J-c SUJ will be chosen low enough so that the time integral of (2.12) for the interference terms of the receiver decision variables is well approximated by a summation over chipping times. Then (2.12) for the received interference, upon substitution of (8.1) for the interference, becomes: Jm=\jE~ju(g,<j),m); (6.3) where we have defined 1 G - l u(g, <f>,m) = — pm(iTc) COS(2TTgi + <f>), (6.4) J i=0 and Ej = PjTs to be the power of the jammer integrated over a symbol period. In the word length 1 case, the probability of bit error in A W G N is: 48 Because the interference terms are additive constants to the decision variables, it is clear that the probability of error conditioned on cf>, conditioned on the reception of a 0 bit, is given by Pc with A / E J replaced by y/Ei + \fEj(u(g\ <f>, 0). — u(g, <f), 1)); and therefore, with y/Ei/N0 replaced by VSNR(1 + V /JSR(u(^, <f>, 0) - u(g,<f>,l))); where SNR = Eb/N0 is the signal to noise ratio, and JSR = Ej/Eb is the jammer to signal ratio. The function u can be written (next paragraph) as u(g, </>, rn) = J(Q, rn).cos <f>, (6-6) so that the probability of error conditioned on <f>, for equally likely transmission of 0 or 1, is P^] = i - ( e r f c ( - ^ / ^ + e r f c ^ V / S M ( l + v ^ S R ( 7 ( ^ l ) - 7 ( e , 0 ) ) c o s ^ ) ^ ; where the first and second terms are due to the probability of bit error conditioned on the reception of a 0 or 1 respectively. The average bit error rate is B E R = \* Pe[<f>]d<f>. - (6.8) ^ J<t>=o To obtain the function 7, write (6.4) as u(g, (j>, rn) — c(g, m) cos <f> — d(g, m) sin </>; (6-9) with 1 G _ 1 ' • c(g,m) =— ^2pm(iTc)cos(2ngi), i=o l G-1 d{g, m) Pm(iTc) sin(2vr^); (6.10) i=0 and redefine (j> by an additive constant to obtain (6.6) with j(g,m) = c2(g, rn) + d2(g, rn). (6.11^ It is easily shown that 1 /  G_1 V/2 l{Q,m) = - i ^ cm{l)cos(2irel)\ ; (6.12) \ /=l-G / G where cm(l) is the aperiodic autocorrelation of the PN code sequence pm(i) = p(i — m). . 49 We have written a C program which evaluates 7 , and find that for a maximal length PN sequence with G = 63 and with g = 0.1 that 7(0:1,0) = 0.143 7(0.1,1) = 0.048. (6.13) Figure 25 of the next section shows a plot of the BER versus JSR at an SNR equal to 12:0 dB, as given by (6.8). There we also give a set of measured points, for the same parameter values, for comparison. 6.2 Theoretical Analysis and Experimental Results for PIR In this section we derive an analytic expression for the BER as a function of ISR arid SNR with phase-invariant reception, for the same spreading and coding parameters (G = 63, k = 1) as the previous section. The intensity of computation prohibits a numerical evaluation of the resulting expression; so we rely on the measured curve to evaluate the performance. With real word length 1 data flow over the complex channel in "the "presence of the single-tone interference as described by (6.1) and (6.2), the m'th correlator output, rm, has both I and Q channel interference components: (6.14) Jm,l = VEju(Q,<f>,m), Jm,Q = -VEjv(g,<J),m); where the functions u and v are defined by: l ^ 1 u(g, (f>, m) = — pm(iTc) COS(2TTgi + <j>), i=0 1 G _ 1 v(g, m) = — E Pm(iTc) s'mfa'gi + </>); (6.15) i=0 with parameters g and (j> as defined in the previous section. We showed there that u can be written as per (6.6). v admits a similar representation: u(g, <j), m) = 7 (0 , m) cos <f>, _ (6.16) v(g, <j), m) = 7 (0 , m) sin <f>\ with 7 given by (6.12). 50 The probability density functions for the decision variables \ fi \ are obtained by the square- law transformation (5.11). Conditioned on jammer phase angle <j>, and on the reception of the symbol representing a 0 bit, these are: f2r IT N0 J 8 = 0 r-2-K j (p.) = / e7^((acosS-^Ejyi cos0)2 + (cvsin6i+A/E77i sine/.) 1 KN0 J0 • (6.17) where 7; = i(g,i). With these, the probability of error, conditioned on <f>, and on the reception of a zero, is as given by (5.9) and (5.14): rOO rOO / / fm(a + B)flf.\(8)dadB. (6.18) Jo Jo The probability of error conditioned on the reception of a one, PC(4>\1), is given by (6.18) and (6.17) with 70 and 71 interchanged. Then, for equally likely reception of a zero or a one, the probability of error is Pe = ^J^-(Pe(<f>\0) + PeW))d<f>.. (6.19) This quintuple integral is too heavy to evaluate numerically to any useful degree of accuracy in any reasonable amount of time. Figure 25 shows the measured curve corresponding to (6.19) at an SNR of 12 dB. The corresponding curve, derived in the previous section, for theoretical coherent reception is shown for comparison. The BER (theoretical optimal or experimental PIR) at JSR = —10 dB is only about 10 percent higher than in the absence of a jammer (JSR = —oo dB). The implementation loss at 12 dB SNR of PIR with respect to coherent reception, is approximately 1.8 dB; meaning that the experimental curve at a 1.8 dB higher SNR than that of the exhibited curve, roughly coincides with the theoretical curve shown. From the graph, it is evident that it is not until the jammer strength reaches the signal strength (JSR = 0 dB) that the BER starts to degrade significantly. As for coherent reception, at SUJ = 0 the jammer does not contribute to the BER because the decision variables are all contributed to equally. At SUJ = oo, the jammer does not contribute either because of the low-pass filtering performed to form the decision variables. The most pessimistic value of g is dependent on the PN sequence used, but is near the value chosen (g = 0.1) for any maximal length PN sequence. 51 1E-1 1E-2 BER 1E-3 1E-4 Experimental PIR i 1 Theoretical Optimal 0 4 JSR (dB) 12 Figure 25 Theoretical and Experimental BER versus JSR at SNR=12.0 dB with 6u> = 0.1UJC 52 Chapter 7 Tracking and Acquisition in AWGN In this chapter, we outline the analysis required to analytically predict the mean time- to-acquire and the mean time-to-lose-16ck, in additive white gaussian noise, that the CPSK receiver achieves. The experimental curves of these quantities as functions of the signal- to-noise ratio are presented. They determine the minimum length of preamble, and the maximum length of body that should be used for packet transmission. 7.1 Mean Time to Acquire Refer to Figure 9 of chapter 3 for the PN code acquisition algorithm. For M-ary CPSK the length, measured in number of chips, of an elementary code-phase shift, m e , is », = ̂ i . (7.1) The acquisition algorithm uses M data correlators, spaced by me chips, to search for lock by one chip increments. At the end of a data symbol period, if the data correlator with the maximum output has an output which crosses threshold!, the maximum of it and the output of the corresponding early and late correlators is compared to threshold^. Let Ps\ denote the probability of exceeding these two thresholds (or passing stage 1) given that the code is in fact aligned to within 1/2 chip. If stage 1 is not passed, the data correlators are precessed for the next attempt to pass stage 1. If stage 1 is passed, the output of the correlator which was largest in stage 1 is checked again on another data read, along.with it's early and late counterparts. If the maximum of these three exceeds threshold?,, the signal is declared to be acquired. Let Ps2 denote the probability of passing stage 2, given rough (to within 1/2 chip) code alignment. Let rii denote the average number of attempts required to pass stage i when the code is aligned to within 1/2 chip. Then . ' ni = —— for i = 1,2. (7-2) Since the probability of passing stage 2 is independent of the probability of passing stage 1, the average number of attempts required to pass both stages is n\n2. Provided that the thresholds are set such that the probability of false acquisition is negligible, attempts to pass stage 1, given that the code is aligned to within 1/2 chip, occur at me data symbol intervals. '• 53 Each failed attempt to pass stage 1, with code alignment to within 1/2 chip, costs m e data symbol periods; while the subsequent attempt to pass stage 2 costs 1 data symbol.period. Then since 1/2 chip code alignment first occurs, on average, after (m e + l ) /2 data symbols, the mean time to acquire, measured in number of data symbols is given by • A — (n in 2 — 1 )me + n 2 H ^ — . (7.3) In the absence of noise, this reduces to • Aldeal = ^ ± l + l. ' ' (7.4) The pdf for the output magnitude of the punctual complex correlator is given by the first of (5.13) for exact code alignment; and given by the same equation with ^/E~s replaced by \/E7/2 for 1/2 chip-off code alignment. Obtaining Psi however, requires the joint pdf of the latter two — something which we have not yet been able to obtain. To derive the mean time-to-acquire when the probability of false acquisition is non-negligible, one must go to a Markov chain analysis, similar to that in [11]. Let the acquisition thresholds be written as fractions of the complex correlator magnitude for the noiseless reception of the corresponding data symbol: thresholdi = Ci\fWs. (7.5) Then with c\ = 1/16, c 2 = C3 = 1/4, and G = 63, we have found the mean time-to- acquire as a function of signal-to-noise ratio, as shown in Figure 26, for the experimental arrangement described in chapter 3. Each data point represents 20 measurements. The error bars represent one standard deviation due to the noise induced variance. A false acquisition was observed less than 1 out of 100 trials during these measurements. However, not enough measurements were made to collect meaningful false acquisition statistics. Note that the ideal mean time-to-acquire reaches the value Aldeai given by (7.4) at an SNR of 13 dB. At SNRs greater than or equal to his value, a data packet with a preamble length of hdeal — ((G + l ) / - ^ 0 + 1 w m be blocked with negligible probability. Assuming that the time-to-acquire is approximately gaussian, a preamble length, ln, which will result in a blocking probability which is upper bounded by the probability of a normalized gaussian process falling n standard deviations outside of its mean is given by ln = A + no- - Aideal + kdeai\ (7.6)- 54 where A and a are to be read from the graph of Figure 26. 100.0 80.0 60.0 A 40.0 (number of data symbols) 20.0 o.o 10.0 11.0 12.0 13.0 14.0 15.0 E_b/N_o (dB) Figure 26 Mean Time-to-Acquire Measured in Data Symbol Durations vs SNR for G=63 7.2 Mean Time to Lose Lock The mean time-to-lose-lock can be analysed by means of Markov chain theory. Let s\ be the state for which the tracking loss flag is down; .32 be the state for which the tracking loss flag is raised; and 53 be the state representing a loss of lock. Let p denote the probability that the maximum of the outputs of the punctual, early, and late correlator corresponding to the received data symbol is below ihreshohU. Then the receiver makes one state transition per data symbol period in the Markov chain shown in Figure 27 with state transition probabilities Pl,l = ^2,1 = Pi,2 = ^2,3 = P, ^3,3 = 1. 55 Figure 27 Markov Chain for Tracking Loss Calculation The states si and S2 are the transient states, and state S3 is an absorbing state. By the theory of finite Markov chains [12], the mean number of times, n ; ( .S j ) , that the process which started in transient state .s; is in a transient state SJ, is given by {•n1-(Bi)} = ( / - Q ) - 1 ; ' (7.7) where Q = {Pij} is the transition probability matrix for the transient states, and / is the identity matrix. For the case at hand, since we start in state .si, the mean time-to-lose-lock is given by ' TL = nl(s1) + n,(s2) = ^ - . (7.8) As in the previous section, computation of p requires the joint pdf of the magnitudes of a complex correlator and its 1/2 chip displaced counterparts. Furthermore, it also depends on the symbol error probability, and on the degree to which the receiver is actually on track. To take into account the latter, the states need another set of quantum numbers corresponding to whether the receiver is on, 1 sample off, 2 samples off, or greater than 2 samples off track. Taking into account timing slippage, would also require specifying the direction of the off-track states. With the tracking loss threshold c 4 = 1/16, as defined by (7.5), and a spreading factor of G = 63, we have found the mean time-to-lose-lock as a function of signal-to-noise ratio by experiment. It is only independent of the spreading factor for zero timing slippage. Each data point of the graph shown in Figure 28 represents 10 measurements. Since the error bars represent 1 standard deviation, provided that the process is approximately gaussian, the 56 maximum packet body length for nonblocked complete reception with na confidence can be read from the graph. 1010 p • , — — , • , . , • , . TL 107 (number of data symbols) 106 105 9.5 10.0 10.5 11.0 11.5 E_b/N_o (dB) 12.0 12.5 Figure 28 Mean Time-to-Lose-Lock Measured in Number of Data Symbols vs. SNR 57 Chapter 8 Conclusions The design and implementation of a correlation receiver for CPSK has been presented. This involved solving the spreading code and carrier-wave synchronization problems. The steady state behaviour of the receiver has been investigated exhaustively in A W G N and single- tone interference; and the previous theoretical BER performance claims by the inventors of CPSK have been experimentally verfied. Beyond this, the present author has found the following. When sampling at twice the chipping rate, applying a first order RC filter of 3-dB bandwidth equal to 1/2 the chipping rate, to the baseband signal before sampling, optimizes the SNR of the correlated signal to a value which is within 1 dB of the output SNR of an ideal matched filter. This result is not specific to CPSK — in the DS-SS literature, the LPF bandwidth is as here (for example, in [13]); but we have not been able to find a publication of the SNR optimization calculation. The author's herein described tracking algorithm has been found to be very satisfactory. For coherent reception, we have found by theoretical analysis, that in AWGN with a timing slippage typical of a TTL oscillator, that the signal is kept on track well enough to incurr a BER performance degradation of less than 0.4 dB for SNRs less than about 14 dB. The hereby invented Phase-Invariant-Reception method for CPSK for solving the carrier- wave synchronization problem eliminates the need for a phase-lock loop, or for a phase estimation DSP filter, by forming receiver decision variables that do not depend on the phase difference between the carrier-wave and the receiver's LO. This method is well suited for DSP because of the minimal amount of post-correlation processing that it requires. For single-channel data transmission and zero frequency difference between the carrier and the receiver LO, at a BER of 10~ 3, PIR is 1.1 dB less .power efficient than coherent reception; at a BER of 10~8 this loss of power efficiency goes down to 0.5 dB. This loss increases independently of the SNR as a function of the frequency difference according to the graph shown in Figure 23. For a 140 MHz carrier, commercial oscillators exist with frequency tolerances that would keep this additional degradation within 1 dB. The degradation due to non-zero frequency difference could be minimized by the addition of a frequency lock loop. The remaining implementation loss with respect to coherent reception can not be recovered. 58 This loss should serve as a bench mark for DSP filters which remove the phase rotation so as to allow coherent reception. More work needs to be done on the dynamic aspects of CPSK reception. The acquisition algorithm presented is very simple and reasonably fast. The threshold values to use in AWGN were experimentally determined by lowering them from some high nominal value (thus shortening the acquisition time) until the probability of false acquisition started to become non-negligible. The resulting threshold values need to be fine tuned, either by more experimentation or by finding reasonably exact analytic expressions for the acquisition time and for the probability of false acquisition. This would allow tradeoff considerations between preamble length and acquisition failure rate under different SNR and JSR values to be analysed. The algorithm for checking for loss of lock should be improved from the present 2 state algorithm to a 3 (or higher) state algorithm so as to improve the time to lose lock. Such an algorithm would make the loss of lock more immune to bit errors. Again either by more experimentation, or by solving the theoretical problems described in chapter 9, the best algorithm should be determined and its thresholds optimized. After this, a higher level performance evaluation which optimizes data throughput with respect to packet length needs to be done so that the modem can be used effectively in a computer network. 59 Bibliography [I] Robert C. Dixon. Spread Spectrum Systems with Commercial Applications. Wiley- Interscience, 1994. [2] Aries Y.C. Wong. Analysis of techniques to enhance the performance of direct sequence spread spectrum signaling for wireless data communications. Master's thesis, University of British Columbia, 1995. [3] M.K. Simon. Spread Spectrum Communications, Vols. 1,2,3. Computer Science Press, 1985. [4] J.M. Wozencraft and I.M. Jacobs. Principles of Communication Engineering. John Wiley & Sons, 1965. [5] Spectrum Signal Processing Inc. Quad C40 Processor Board User's Guide, June 1993. [6] Texas Instruments. TMS320C4x User's Guide, 1993. [7] 3L Ltd. Parallel C User Guide, 1994. [8] Chris Bowick. RF Circuit Design. Indianapolis, Ind. : H.W. Sams, 1982. [9] Hansen Wang. Spread Spectrum Modem IF Receiver, Technical Manual, Board Revision 1.0, June 1995. [10]K. Beeler and H. Kaufmann. Time integrating correlator for real-time processing of spread-spectrum signals. Proc. Custom Integral Circ. Conf, May 1990. [II] Unisys. PA-100 Spread Spectrum Demodulator, Technical Data Sheet and User's Guide, June 1993. [12] Stanford Telecom. STEL-2000A, Digital, Fast Acquisition, Spread Spectrum Burst Processor, 1994. [13]V.C.M. Leung and R.W. Donaldson. Confidence estimtes for acquisition times and hold- in times for pn-ssma synchronizer employing envelope correlation. IEEE Trans. Comm., COM-26, Jan. 1982. [14]J.G. Kemeny and J.L. Snell. Finite Markov Chains. D. Van Nostrand Company, Inc., 1960. [15]A.L. Welti and B. Bobrovsky. On optimal age structure for direct sequence spread spectrum pn-code tracking. IEEE Trans. Comm., 42(2/3/4), 1994. 60 Appendix A Maximal Length PN Sequence Generation The Maximal Length Pseudo-Noise Sequences are the longest codes that can be generated by a shift register of a given number of stages /. Their length is Figure 29 shows the 3-stage shift register with the appropriate linear feedback connec- tions, for generating the G = 7 PN sequence; while Figure 30 shows the autocorrelation function, as given by (2.8) for the /-sequence. In the implementation, the non-shifted PN sequence is, chosen to be the one generated by initializing all the stages of the generating register with 1. The PN sequence is software generated and written to the DSP's memory during system initialization. G = 2' - 1 . (Al) 1 2 3 Code Output Figure 29 Three-Stage Maximal Generator 61 -1 chip +1 chip Figure 30 1-Sequence Autocorrelation Function 62 Appendix B IF Transmitter Modules Each section of this appendix discusses and gives a schematic of a module of the IF transmitter shown in Figure 6. B.1 Digital Communication Port Interface The digital interface reads from the C40 communication port via four control signals: /CPvEQ, /CACK, /CSRTB, /CRDY. Of these, /CREQ and /CACK are for determining ownership of the data bus; and for unidirectional data flow, these can simply be tied high, provided that the C40 communication port used defaults to an output port at system reset. A sending C40 activates /CSTRB to indicate that it has placed a data byte on the data bus; while a receiving C40 activates /CRDY to indicate that it has received a data byte. The IF transmitter's digital interface (call it Tx) mimics the C40 communication port protocol in such a manner that the data flows according to the interfaces' 4 MHz clock. This is achieved with a D flip-flop which controls both the /CSTRB /CRDY handshaking and the clock signal for a following D flip-flop which reads the data line. See Figure 31 for the digital interface circuit schematic. The logic elements are implemented by the FAST logic family; and the propagation delays and C40 response times are such that the circuit is guaranteed to function with a clock rate of up to 5.25 MHz. With a 4 MHz clock, the available, software controlled, chipping rates are divisions by 2 of 4 Mbps. Because the C40 communication port is very high-speed, signal quality is very important. The value for the serial impedance matching resistor (39£7) was determined by experimentally minimizing the ringing of the output /CRDY signal. The 10 kfi pullup resistors are used to avoid unintended triggering after reset. Figure 32 shows the circuit appropriate for a single channel system. In actuality, both I and Q channels are present. Because the first /CSTRB for the two channels is only asserted by the C40 at the same time to within some uncertainty, it is possible for the two channels to be skewed by one Tx clock period. To avoid this and ensure that the two channels are synchronized, the RESET signal of the I-channel control flip-flop is routed to RESET of the Q-channel control flip-flop, and vice-versa. 63 DATA SN74F125 /CSTRB > Vcc I^SN74F1? 5 I^SM7<1F SN74 04 CLK >- 1_ ~ ~ ^ — L — T D Q I Vcc SN74F74 P R E Vcc /CRDY <- 39 O SN74F125 •<3 X Vcc Vcc C L R D Q SN74F74 P R E H> DATA OUT SN74F125 /CREQ SN74F04 /CACK > Vcc ^ 10K Figure 31 Communication Port Interface (one channel) B.2 Level Shifter and Amplifier The level shifter/amplifier converts the TTL logic valued data stream to a bipolar data stream appropriate for BPSK modulation. The circuit uses the high frequency operational amplifier AD963Tto implement a difference amplifier in which one input is the TTL signal, and the other input is a constant voltage signal held at a point midway between TTL high and TTL low. The constant voltage signal is obtained by a 20 kf) voltage divider inserted between ground and the +5 volt supply, followed by a unity-gain buffer implemented by the operational amplifier LM741. The buffer holds the voltage divider output, Vref, constant (up to a small jitter which is then taken out by a capacitor between ground and the buffer output) in spite of the large changes in the current drawn by the difference amplifier. Two Zener diodes are used to clip off the overshoot and the undershoot of the TTL input signal, Vin, to the difference amplifier. See Figure 32 for the circuit schematic. The output voltage of the difference amplifier is given by 1 + R2/Riv R2V V o u t - 1 + Rz/Rt V i n i ? / r e / ' (Bl) 64 The resistors R2 and i?4 are both chosen to be 150S7 ± 10%, while the variable resistors i?i and i?3 are adjusted so as to make R2/R1 = RA/RZ = A. Then the output voltage is given by Vout = A(Vm - Vref). ( 5 2 ) Vcc Vcc 20K 1 uF .1 uF 3.3 uF .1 uF - V c c Vcc .1 uF TTL input 26' N4733A 5.1 V Vin ^ T 1 N 4 6 1 9 3.0 V /J ~1 A/V R2 Vcc 3.3 uF G N D 3.3 uF - V c c Vout Figure 32 Level Shifter and Amplifier B.3 BPSK Modulator and Bandpass Filter The quadrature BPSK modulator performs double-sideband suppressed-carrier modula- tion with an RF carrier of frequency 140 MHz in both I and Q channels. It is implemented by Mini-Circuits MIQY-140M, whose characteristics are as follows: — input and output impedance of 50 ohms — operating LO frequency and power: 140 MHz at 10 dBm — maximum I and Q current: 40 mA (2 V peak-to-peak) — bandwidth: 10 MHz — conversion loss: 6 dB —- carrier suppression: 30 dB 65 The RF modulator output is bandpass filtered to remove the image spectra at frequencies harmonic to 140 MHz. See Figure 33 for the modulator plus filter circuit schematic. The filter consists of two identical cascaded stages whose circuit elements are determined by the formulae: L . _ V2RQ C G _ 1 ^ 2 - W i lolLg . . where R0 = 50f2 is the characteristic impedance of the filter input and output, u>0 is the angular frequency band-center, and u>2 — u>\ is the angular frequency 3-dB bandwidth. With a band-center of 140 MHz and a bandwidth of 134 MHz, these are: Ls = MnH Cs = IbpF ( £ 4 ) Cp = 34pF Lp = 39nH. The inductors where wound with 20 AWG tinned copper wire according to the following formula for an air-core, single-layer solenoid: L = Fn2d; ' (£5) where n is the number of turns, d is the diameter of the coil, and F is a constant that depends on the ratio of the length to the diameter of the coil. The extremely small values for the inductances make the circuit element parameter values hard to control — as the lumped parameter model is barely appropriate. The actual constructed filter ended up with a bandwidth of approximately 100 MHz about a band-center of 120 MHz. The 20 MHz band about the desired 140 MHz has a passband ripple of less than 1 dB about zero attenuation, so the filter is satisfactory. 66 I chan > Q chan > MIQY-140M RF Ls Cs Ls Cs RF out > A LO Lp Cp Lp i i •'mĵ - Cp Figure 33 BPSK Modulator and Filter 67 Appendix C IF Receiver Modules Each section of this appendix discusses and gives a schematic of a module of the IF receiver shown in Figure 7. C.1 BPSK Demodulator and Low Pass Filter A 3 dB pad improves the impedance matching between the BNC connector for the incoming IF signal and the QPSK demodulator, which is implemented by Mini-Circuits MIQY-140D, and is of the following specifications: — input and output impedance of 50 ohms — operating LO frequency and power: 140 MHz at 10 dBm — maximum RF input power: 50 mW (1.6 V peak-to-peak) — bandwidth: 10 MHz — conversion loss: 5.6 dB — maximum output current: 40 mA The active low pass filter and amplifier has an overall gain of 28 dB equally distributed over 2 stages, each of which is implemented with Analog Device's high frequency AD843TN op amp in the basic inverting configuration. One of the stages implements the first order low-pass filter by a parallel RC feedback. The values of R and C were chosen so as to give the filter the 3-dB cut-off frequency of 0.25 MHz, as called for in Chapter 4. The voltage offset adjustment, implemented with the LM741CN op amp, is necessary to shift the bipolar baseband signal to be centered about 1 volt, because that is the middle of the ADC range. The circuit includes a trim pot to precisely adjust the offset. 68 I channel O.luF -a— LO input > I & Q Demodulator RF input 8.66 H 8.66 R > VW-i-WV 1 3 dB pad MIQY-140D 3 > I—Ur a m 4 0.1 uF —»— J6.8UF TANT O.luF —K— 6.8uF TANT - V c c • Low Pass Filter and Amplifier V c c I 940 pF ^ > ^ A D 8 4 3 J I 6.8UF TANT O.luF HI— 6.8UF TANT Q channel 681R I A D M ! O.luF 6.8UF TANT| 1 1 O.luF I 6.8UF TANT - V c c ' * Voltage Offset Adjustment 681R AAA. 1 940 pF I J ^ A D 8 4 3 J l 0.1UF —K- 6.8UF TANT • ^ V c c i—ixi/v 7 4 ^ 0 ^ ^ i I analog Q analog Figure 34 BPSK Demodulator and Low Pass Filter C.2 Analog/Digital Converter The I and Q signals are sampled on the rising edge of the ENCODE signal by Analog Devices AD9058JD Dual-Channel 8-Bit, 50 MSPS Flash ADC. It has an encode propagation time delay of 12 ns, and an input aperture time of 0.8 ns. It provides a +2 volt reference output, Vint, which is used by the voltage offset adjustment of the previous section to bring the LPF output signal into the center of the 0 to 2 volt analog input range of the AD9058JD. 69 Pull-down resistors are on the TTL output lines to approximately equalize the TTL high/low rise and fall times. The two Octal D Latches (SN74F373) latch the ADC output data. Vint «- ENCODE >- I analog >- Q analog >- AD9058JD [ENCODE A GG GG G N N G G G N N G D N N N [ >DDDI 1 Octal D Latch Octal D Latch DI.O D M 'DI.2 DI.3 > D U DI.5 >DI.6 DI.7 DQ.O DQ.) D Q 2 DQ.3 DQ . 4 DQ5 DQ.e DQ.7 Figure 35 Dual Channel 8-Bit ADC C.3 ADC Converter Control The ADC Converter Control module takes as input the TTL clock oscillator, the QPC/C40 global reset, and one data line from a C40 communication port; and produces as output the ENCODE control signal for the ADC, and the write control signals, /WEN and WCLK, for writing ADC output to the bank of FIFO memory. The serial connection of two buffers (SN74F04N) provides a simple communication interface with the C40 providing the GO/STOP signal, clocked in by the D-flip-flop SN74F74N, for enabling/disabling the ADC conversion and FIFO writing. Each of the two JK flip-flops (SN74F109) perform a 70 division by two of their respective clock inputs. Thus, the FIFO write clock, WCLK, is driven at half the clock rate; while the FIFO write enable, /WEN, and the ADC encode control, ENCODE, signals are driven at one quarter of the receiver TTL clock oscillator rate. C L K > - /CSTRB>- /CRDYf - /RS >- CDO>- Vcc 1̂01 Vcc SN74F04N SN74F04N Vcc 2 .SN74F109 ,. PRE &CLK CLR — GND PRE D Q pax.Qp T Vcc SN74F08N — GND SN74F74N Vcc Vcc _ L n . >IOK ^ 2 L _ •pOLK 5P 1 T — GND J_ _ , Vcc SN74F109 /WEN ^ E N C O D E -> WCLK Figure 36 ADC Converter Control C.4 FIFO Memory Banks Each FIFO of the memory bank is TI's SN74ACT722X1L-25RJ. They are 2048 9-bit bytes of SRAM deep, with a 25 ns read or write access time. Either end of the FIFO can be operated in synchronous or in asynchronous mode. The write control signals, WCLK and /WEN, issued from the ADC conversion module, operate the input side of the FIFO in synchronous mode; while the read control signals, RCLK and /REN, issued from the FIFO/TMS320C40 communication port, operate the output side of the FIFO in asynchronous mode. The FIFO activates the full flag, /FF, when the FIFO is full, indicating that the writes are blocked; and activates the empty flag, /EF, when the FIFO is empty, indicating that the reads are blocked. /EF is used by the FIFO/TMS320C40 communication as a control signal. 71 /FF is not used at present; but a future iteration of the receiver could use the full flag indicate a system error — for normal operation, /FF should never be activated. DI.O> DI.1 > Dl.2> DI.3J Dl.4> DI.55 DI.6J DI.7J / R S WCLK /WEN DQ.O DQ.1 DQ.2 DQ.3 DQ.4 DQ.5 D0.6 DQ.7 SN74ACT722X1L SN74ACT722X1L SN74ACT722X1L WOK MEN1 TV£NS/L0 SN74ACT722X1L -<RCLK1 -</REN1 ->/EF1 CDI.O CDI.1 CDI.2 CDI.3 CDI.4 CDI.S CDI.6 CDI.7 -<RCLK2 -</REN2 CDQ.O CDQ.1 CDQ.2 CDQ.3 CDQ.4 CDQ.5 CDQ.6 CDQ.7 -< RCLK3 -</REN3 ->/EF3 CDI.O CDI.1 CDI.2 CDI.3 CDI.4 SB!:I cDi.7 -<RCLK4 -</REN4 -)/EF4 CDQ.O CDQ.1 CDQ.2 CDQ.3 CDQ.4 CDQ.5 888:1 ±GND Figure 37 FIFO Memory Banks 72 C.5 FIFO/TMS320C40 Communication Port Of all the receiver hardware, the FJFO/C40 communication port was the most challenging to design. This is because the C40 communication port is very high speed, and its communication protocol is rather particular; so that setup time requirements are stringent and signal quality is very important in order to avoid byte slippage. The C40 communication port transfers words in an asynchronous transmission of 4 bytes, followed by a word synchronizer delay. The port we have designed transfers bytes synchronously, and does not exercise an extra delay after every fourth byte. The resulting port speed is one half of that possible between two C40s. The communication port has been extensively tested, and found to be reliable when driven by a clock of frequency up to 32 MHz. However, due to the C40 response time, and the propagation delays of the input and output buffers (SN74F125), we have found that the communication rate in bytes per second changes from clock frequency divided by 2 with a 16 MHz (or slower) clock, to clock frequency divided by 4 with a 20 MHz (or faster) clock. Therefore, we use a 16 MHz clock for a port speed of 8 MB PS. The communication port schematic does not show the token forcer which is necessary to give the IF receiver ownership of the data bus. We have it implemented according to the schematic given in the Tl TMS320C40 Data Book. 73 IRS >- CLK >— •o- /EF >- RCLK « - /CRDY>- I SN74F08N SN74F74N T _vw- 2 7 R - > / R E N - » /CSTRB Figure 38 FIFO/TMS320C40 Communication Port 74 Appendix D DSP Code Listings D.1 Master Receiver * Master r e c e i v e r for word length 1, quadrature data flow with Phase- * Invariant reception f o r a f i l e sent over the IF l i n k . * Hosted on processor A. Receives from a p a i r of complex c o r r e l a t o r s * on processor B, and an e a r l y and a l a t e c o r r e l a t o r on processor D. * The task reads from f i l e datac (contains zeroes and ones) and passes * i t to processor B which relays i t to the transmitter on processor C. * The data which the r e c e i v e r processes i s written to f i l e re_datac. * The amount of spreading i s determined by a user supplied PN generator * s h i f t r e g i s t e r length. * The f u n c t i o n a l i t y includes a c q u i s i t i o n which uses a two sample step * s i z e . Once the code i s acquired, the program tracks, decodes, and * writes to a b u f f e r . */ i i n c l u d e <chan.h> tinclud e <stdio.h> #include <math.h> /* for pow * / #include <stdlib.h> /* for c a l l o c * / #include <compt4 0.h> /* for out_word * / extern reed() ; /* for reading from c o r r e l a t o r s */ f l o a t ciO=0 /* ciO holds 0 I c o r r e l a t o r output */ f l o a t cqO=0 /* cqO holds 0 Q c o r r e l a t o r output */ f l o a t cil=0 /* c i l holds 1 I c o r r e l a t o r output */ f l o a t cql=0 /* c q l holds 1 Q c o r r e l a t o r output */ f l o a t die=0 /* die holds e I c o r r e l a t o r output */ f l o a t dqe=0 /* dqe holds e Q c o r r e l a t o r output */ f l o a t dil=0 /* d i l holds 1_ I c o r r e l a t o r output */ f l o a t dql = 0 /* dql holds 1 Q c o r r e l a t o r output */ main(int argc, char *argv[], char *envp[), CHAN * i n _ p o r t s [ ] , i n t ins, CHAN *out_ports[], i n t outs) { f l o a t c0=0; /* 0 c o r r e l a t o r magnitude squared * / f l o a t c l = 0; /* 1 c o r r e l a t o r magnitude squared * / f l o a t de=0; /* e a r l y c o r r e l a t o r mag squared */ f l o a t dl=0; /* l a t e c o r r e l a t o r mag squared */ f l o a t g; /* 0 corr. dot rotated 1 c o r r . */ f l o a t h; /* mag.squared 0 minus mag squared 1 */ i n t M,N; /* PN s h i f t reg length, PN length * / f l o a t t h r e s h o l d l ; /* to detect within 1/2 chip */ f l o a t threshold2; /* to detect exact c o r r e l a t i o n */ f l o a t threshold?; /* f o r acq conferm */ f l o a t threshold4; /* to detect tracking loss */ i n t ESHIFT; /* length of elementary phase s h i f t */ i n t acq=0; /* acq=0 means not acquired*/ i n t t f l a g = l ; /* for tracker */ i n t tlflag=0; /* for tracker */ f l o a t max=0,maxd=0; /* max corr. output, max delayed */ i n t j=0; /* for tracker */ f l o a t temp; /* f o r tracking l o s s , t e s t */ i n t shift=0,shft=0; /* s h i f t s f o r acq. and tracking */ i n t shiftd=0, shftd=0; /* delayed s h i f t s */. 75 i n t s l i d e ; i n t sld=0; i n t s l i d e d ; i n t i=0; i n t f l a g = - l ; i n t f l a g c ; i n t flagg; i n t *bufi,*bufq; i n t valuei,valueq; i n t datacount=0; • FILE * o u t f i l e , * i n f i l e ; i n f i l e = fopen("datac", "r " ) ; while ( f s c a n f ( i n f i l e , " % d %d",&valuei,&valueq)==2) datacount=datacount+2; f c l o s e ( i n f i l e ) ; p r i n t f ( " T h e number of b i t s to transmit i s %d \n",datacount);. p r i n t f ( " I n p u t PN s h i f t r e g i s t e r length (max=10): " ) ; /* tracking adjustment */ /* s l i d e adjustment */ /* delayed s l i d e */ /* sample counter */ /* for flagging c o r r e l a t o r s */ /* flagc=0 means malloc f o r corrs OK */ /* flagg=0 means malloc f o r gen OK */ /* pointers to buffered data */ /* for reading data */ /* input datacount */ /* for data i o */ /* s t a r t by counting data */ scanf("%i",&M); chan_out_word(M,out_ports[0]); chan_out_word(M,out_ports[1]) ; N=pow(2,M)-1; thr e s h o l d l = (2*N)/(16*16); threshold2 = (2*N)/16; threshold3 = threshold2; threshold4 = th r e s h o l d l ; /* read M */ /* send M to the c o r r e l a t o r s */ /* send M to delayed c o r r e l a t o r s */ send to corr.*/ a l l o c a t e and zero storage */ a l l o c a t e and zero storage */ \n") ESHIFT=N-1; slide=2*N-l; slided=2*N-l; chan_in_word(&flagc,in_ports[0]) ; /* confirmation from c o r r e l a t o r s */ i f (flagc) { p r i n t f ( " I n s u f f i c i e n t space f o r c o r r e l a t o r s \ n " ) ; e x i t ( 1 ) ; ) chan_out_word(datacount,out p o r t s [ 0 ] ) ; /* b u f i = ( i n t *) calloc(datacount/2 + 1,1); /* bufq = ( i n t *) calloc(datacount/2+1,1); /* i f ( bufq == NULL ) •"{ pr i n t f ( " T h e required rec storage space i s not a v a i l a b l e exit(1) ; } chan_in_word(&flagg,in_ports[0]); /* confirmation from generator */ i f (flagg) { p r i n t f ( " I n s u f f i c i e n t space f o r generator\n");exit(1);} i n f i l e = fopen("datac","r"); /* pass data to corr */ while ( f s c a n f ( i n f i l e , " % d %d",&valuei,&valueq)==2) { chan_out_word(valuei,out_ports[0]); chan_out_word(valueq,out_ports[ 0 ] ) ; } chan_out_word(flag,out_ports[0]); chan_out_word(flag,out_ports[0]); f c l o s e ( i n f i l e ) ; chan_in_word(&flag,in_ports[0]); chan_in_word(&flag,in_ports[1]); chan_out_word(flag,out_ports[ 0 ] ) ; chan_out_word(flag,out_ports[1]); /* Send control signals to IF board /* f l a g end of f i l e */ /* with 2 - l ' s */ /* wait f or c o r r e l a t o r s ready */' /* wait f or delayed c o r r e l a t o r s */ /* f l a g ready to c o r r e l a t o r */ /* f l a g delayed c o r r e l a t o r */ V asm ( " . data asm("o_addr: .word 00100092H asm("fifosp: .word 0F4F4F4F4H asm("frst: .word 0F5F5F5F5H asm("gostop: .word 0F7F7F7F7H asm("rst: .word 00000000H 76 asm(" .text asm(" push ARO asm(" push AR1 asm(" push AR2 asm(" push AR3 asm(" ldpk @o_addr asm(" Ida @o_addr, ARO asm(" ldpk @fifosp • asm(" Ida @fifosp, AR1 asm(" ldpk @frst asm(" Ida @frst, AR2 asm(" ldpk Ogostop asm(" Ida ©gostop, AR3 asm(" s t i AR1,*AR0 asm(" nop asm(" nop asm{" nop asm(" nop asm(" nop asm(" s t i AR2,*AR0 asm(" nop asm(" nop asm(" nop asm(" . nop asm(" nop asm(" s t i AR3, *AR0 asm(" pop AR3 asm(" pop AR2 asm(" pop AR1 asm(" pop ARO for (i=0;i<=datacount;i++) { i f (acq==0) { out_word(shift,0); out_word(slide,0); out_word(shiftd,3) ; out_word(slided, 3) ; s l i d e d = s l i d e ; s h i f t = (shift+2)%(2*N) i f (maxd>thresholdl) { /* a c q u i s i t i o n mode */ /* s h i f t c o r r e l a t o r s */ /* s h i f t delayed c o r r e l a t o r s */ /* increment s h i f t by 2 samples */ /* t e s t f o r a c q u i s i t i o n */ sld=0; (de>maxd)?(maxd=de,sld=-l):(maxd=maxd); /* adjust by 1 samp */ (dl>maxd)?(maxd=dl,sld=+l):(maxd=maxd); i f (maxd>threshold2) /* t e s t adjusted a c q u i s i t i o n */ { acq=l;shift=(2*N+shft-sld)%(2*N);j=2; } } maxd=max; p r i n t f ( " % e %e %e %e %d %d %d\n", cO, c l , de ,dl., s l i d e , s h i f t, j ) ; */ shft = s h i f t d ; reed(); • . /* read c o r r e l a t o r s */ cO = ciO*ciO + cqO*cqO; /* form magnitudes squared */ c l = c i l * c i l + c q l * c q l ; de = .die*die + dqe*dqe; d l = d i l * d i l + dql*dql; 77 (cO>=cl)?(max=c0,shiftd=(2*N+shift-2)%(2*N)): /* f i n d max and */ (max=cl,shiftd=(ESHIFT+shift-2)%(2*N)); /* adjust s h i f t */ } else i f (acq==l) /* a c q u i s i t i o n confirmation */ { out_word(shift,0); out_word(slide, 0) ; out_word(shiftd, 3) ; out_word(slided, 3) ; i f (j==0) { sld=0; (de>maxd)?(maxd=de,sld=-l):(maxd=maxd); (dl>maxd)?(maxd=dl,sld=+l):(maxd=maxd); i f (maxd>threshold3) /* acq confirmed */ acq=2;slide=2*N-shift+sld-1;shftd=0;j=4; l s e /* go back to acq mode */ acq=0;shift=(shift+2)%(2*N) } j = j - i ; maxd=cO; p r i n t f ( " % e %e %e %e %d %d % d \ n " , c O , c l , d e , d l , s l i d e , s h i f t , j ) ; */ shft= s h i f t d ; reed(); cO = ciO*ciO + cqO*cqO; c l = c i l * c i l + c q l * c q l ; de = die* d i e + dqe*dqe; d l = d i l * d i l + dql*dql; (cO>=cl)?(max=cO,shiftd=(2*N+shift-2)%(2*N)): (max=cl,shiftd=(ESHIFT+shift-2)%(2*N)); } else i f (acq == 2) /* tracking/decoding mode */ C /* write s h i f t to (0,1) p a i r */ /* write s l i d e to (0,1) p a i r */ /* write s h i f t to (e,l) p a i r */ /* write s l i d e to (e,l) p a i r */ /* previous tracking adj done */ out_word(0,0); out_word(slide, 0 ) out_word(shftd,3) out_word(slide,3) slide=2*N-l; ' i f (j<=0) { (de>dl) ? (sld=-l, temp=de) : (sld=+l, temp=dl) '; i f (maxd<temp) /* te s t i f tracking adj needed */ { /* i f tracker f l a g up, adjust */ i f (tflag) {j=4; slide=2*N-l+sld; tflag=0;} else t f l a g = l ; /* else r a i s e f l a g */ } else {temp=maxd; tflag=0;} if - (temp<threshold4) { i f ( t l f l a g ) { /* lower tracker f l a g */ /* test f or tracking l o s s */ /* i f f l a g i s up, e x i t */ p r i n t f ( " t r a c k i n g loss \n"); break; 78 } else t l f l a g = l ; } else tlflag=0; /* r a i s e tracking loss f l a g */ /* lower tracking loss f l a g */ /* form de c i s i o n v a r i a b l e s */ /* decode and buffer I and Q */ /* channel data */ } j = j - i ; maxd=max; g = c q O * c i l - c i O * c q l ; 'h = (cO-cl)12; i f (g-h<=0) { i f (g+h>=0) {*(bufi+i)=0; *(bufq+i)=0;} else {*(bufi+i)=0; *(bufq+i)=1;} } else { i f (g+h>=0).{*(bufi+i)=1; *(bufq+i)=0;} else {* (bufi + i ) =1; * (bufq+i) =1'; } } p r i n t f ( " % e %e %e %e %e %e \n",cO,cl,de,dl,g+h,g-h); */ reed(); /* read c o r r e l a t o r s */ cO = c i 0 * c i 0 + cq0*cq0; /* form magnitudes squared */ c l = c i l * c i l + c q l * c q l ; de = die* d i e + dqe*dqe; d l = d i l * d i l + dql*dql; (c0>=cl)?(max=cO,shftd=0) : (max=cl,shftd=ESHIFT) '; /* reset IF board */ asm ( " push ARO asm ( " push AR1 asm( " ldpk @o_addr asm ( " Ida @o_addr, ARO asm ( " ldpk @rst asm ( " Ida @rst, AR1 asm ( " s t i AR1,*AR0 asm( " pop AR1 asm( " pop ARO o u t f i l e = = fopen("re_datac","w") /* end of while loop */ /* decode s h i f t s and write to f i l e */ for (i=0;i<datacount/2+l;i++) { v a l u e i = *(bufi+i),• valueq = *(bufq+i); f p r i n t f ( o u t f i l e , " % d %d ", valuei,valueq); } f c l o s e ( o u t f i l e ) ; } '/* end of main */ 79 assembler routine f or reading c o r r e l a t o r s .version 40 .text .globl _reed .globl _ c i 0 .globl _cq0 .globl _ c i l .globl _ c q l .globl _ d ie .globl _dqe .globl _ d i l .globl _dql reed: ldpk @il_addr Ida @il_addr,AR0 ldpk @i2_addr Ida @i2_addr,ARl l d f *AR0,R1 ldpk ©_ci0 s t f Rl,@_ci0 l d f *AR0,R1 ldpk 0_cq0 s t f Rl,@_cq0 l d f *AR0,R1 ldpk @_cil s t f R l ,@_cil l d f *AR0,R1 ldpk @_cql s t f Rl,@_cql l d f *AR1,R1 ldpk @_die s t f Rl,@_die l d f *AR1,R1 ldpk @_dqe s t f Rl,@_dqe l d f *AR1,R1 ldpk @_dil s t f Rl,@_dil l d f *AR1,R1 ldpk @_dql s t f Rl,@_dql rets I chan 0 c o r r e l a t o r input Q chan 0 c o r r e l a t o r input I chan 1 c o r r e l a t o r input Q chan 1 c o r r e l a t o r input delayed I chan e a r l y c o r r e l a t o delayed Q chan e a r l y c o r r e l a t o delayed I chan l a t e c o r r e l a t o r delayed Q chan l a t e c o r r e l a t o r ; c o r r e l a t o r input port addr ; delayed c o r r e l a t o r input addr ,; read from c o r r e l a t o r ; write to global v a r i a b l e ; read from delayed c o r r e l a t o r ; write to global v a r i a b l e . data l_addr: 2_addr: . end .word .word 00100041H 00100071H comm port 0 input f i f o comm port 3 input f i f o 80 D.2 Pair of Complex Correlators We set up a p a i r of complex c o r r e l a t o r s to look f o r the 0 or the 1 represented by s h i f t e d or non-shifted PN sequence produced by gen.c and c o r r e l a t e with corr() contained i n f i l e cor.asm. Corr() also reads a s h i f t and a s l i d e from rec.c. There.are 2 samples per chip. T h e s h i f t r e g i s t e r length i s read from rec.c and determines the PN sequence. Before r e c e i v i n g , corr relays data f i l e to be transmitted from rec to gen. */ #include <chan.h> #include <math.h> #include <stdlib.h> extern v o i d c o r r ( v o i d ) ; i n t N; i n t M; i n t stage[] = {1,1,1,1,1,1,1,1,1, i n t connect[10][10]={{1,0,0,0,0,0,0,0,0,0}, {1,1,0,0,0,0,0,0,0,0} {1,0,1,0,0,0,0,0,0,0} {1,0,0,1,0,0,0,0,0,0} {1,0,0,1,0,0,0,0,0,0} {1,0,0,0,0,1,0,0,0,0} {1,0,0,0,0,0,1,0,0,0} /* f o r pow */ /* f o r malloc */ /* c o r r e l a t o r written i n assembler */ /* PN sequence length */ /* PN gen s h i f t reg length */ 1};/* s h i f t r e g i s t e r f or PN generator */ {1,0,0,0,1,1,1, {1,0,0,0,0,1,0, {1,0,0,0,0,0,0, i n t *pn0, *pnl; v o i d pn_gen(int *pn0, main(int argc, char CHAN *in_ports[] { 0,0,0} 0,0,0} 1,0,0}} i n t *pnl); argv[] , char * envp[] , i n t i ns, CHAN *out_ports[] /* connection vectors */ /* pointers to the PN sequences /* the PN's generating func */ i n t outs) i n t f l a g ; /* i n t datacount; - /* i n t valuei=0; /* i n t valueq=0; i n t *p0; i n t * p l ; chan_in_word(&M,in_ports[0]); /* chan_out_word(M,out_ports[0]); I* for processor synchronization for data r e l a y */ for data r e l a y */ /* pointers to a l l o c a t e d space */ read M from rec */ pass M to generator */ N = pow(2,M)-l; pO = (int *) malloc(4*N+2) ; /* a l l o c a t e f or aligned pointer */ p i = (int *) malloc(4*N+2); i f (pl==NULL) chan_out_word(l,out_ports[1]) ; else chan_out_word(0,out_ports[1]); /* i n d i c a t e to rec malloc r e s u l t * A pnO = (int *)((((unsigned int) p 0 » (M+l) )+1) « (M+l) ) ;' /* aligned */ pnl = (int *)((((unsigned int)pl»(M+l))+1)«(M+l)); /* pointers */ chan_in_word(&datacount,in_ports[0]); /* r e l a y data count */ chan_out_word(datacount,out p o r t s [ 0 ] ) ; chan_in_word(&flag,in_ports[1]); /* read from gen */ chan_out_word(flag,out_ports[1]); /* i n d i c a t e to re c e i v e r */ 81 while ( v a l u e i != -1 ) { chan_in_word(&valuei,in ports[0]) chan_in_word(&valueq,in_ports[0]) chan_out_word(valuei,*out_ports [ 0] chan_out_word(valueq,out_ports[0] } pn_gen(pnO,pnl); chan_out_word(flag,out_ports[1]); chan_in_word(&flag,in_ports[0]); chan_out_word(flag,out_ports[0]); c o r r ( ) ; } void pn_gen(int *PN0, i n t *PN1) { i n t i , j , temp; for (j=0; j<N ; j++) .{ temp=0; *(PN0+2*j) = 1 - 2*stage[0]; " *(PN0+2*j+l) = 1 - 2*stage[0]; *(PNl+((2*j+((2*N)+2)/2)%(2*N))) *(PNl+((2*j+l+((2*N)+2)/2)%(2*N)) for (i=0; i < M; i++) { temp = temp"(stage[i]'connect[M-l] i f (i<M-l) stage[i]=stage[i+1]; } stage[M-l]=temp; } '/* r e l a y data to generator */ /* i n i t i a l i z e PN's */ /* i n d i c a t e readiness to rec */ / * w a i t f o r receive to be ready */ /* f l a g gen to in d i c a t e ready */ /* c a l l c o r r e l a t o r function */' /* PN sequence generator * I I* convert (0,1) to (1,-1) */ /* and double up the entries */ = *(PN0+2*j); /* s h i f t e d PN seq */ ) =*(PN0+2*j); [i] : assembler routine to implement a p a i r of real-time c o r r e l a t o r s .version 40 . text .globl _ c o r r .globl _pn0 .globl _pnl .globl _N ldpk @i_addr Ida @i_addr, ARO ldpk @q_addr Ida @q_addr, AR1 ldpk @is_addr Ida @is_addr, AR2 ldpk @o_addr Ida @o_addr, AR3 ldpk @_pn0 Ida @_pn0, AR4 ldpk ©_pnl Ida @_pnl, AR5 ldpk @_N Ida @_N, BK mpyi 2,BK ldpk ©center ; setup c o r r e l a t o r ; ARO holds I data input port addr ; AR1 holds Q data input port addr ;' s h i f t / s l i d e input port addr ; AR3 holds output port addr ; AR4 addresses 0 PN sequence AR5 addresses 1 PN sequence N i s PN seq length fo r c i r c u l a r addressing mode two samples per chip 82 delay: top: l d i ©center,R6 subi 1,BK,RC rptb delay l d i *AR0,R8 l d i *AR1,R8 Ida AR4,AR6 Ida AR5,AR7 l d i *AR2,IR1 nop *AR6++(IR1)% nop *AR7++(IR1)% l d i *AR2,IR0 l d i IRO, RC l d i 0,R10 l d i 0,R2 rptbd f i n l d i 0,R3 l d i 0,R4 l d i 0,R5 ; ADC o f f s e t ; read o f f 2N samples, create delay AR6 indexs 0 PN seq AR7 indexs 1 PN seq read' s h i f t i n t o IR1 s h i f t c o r r e l a t o r s read s l i d e repeat slide+1 times RIO holds sum of I sample squares R2 holds 0 I sum R3 holds 0 Q sum R4 holds 1 I sum R5 holds 1 Q sum lbuO *AR0,RO load zeroth byte lbuO *ARl,Rl' load zeroth byte subi R6,R0 subtract ADC o f f s e t subi R6,R1 • mpyi RO,*AR6 ,R8 I chan m u l t i p l y f o r 0 c o r r e l a t o r mpyi Rl,*AR6++5 !>, R9 Q chan m u l t i p l y f o r 0 c o r r e l a t o r addi R8,R2 accumulate I chan 0 c o r r e l a t i o n addi R9,R3 accumulate Q chan 0 c o r r e l a t i o n mpyi RO,*AR7 ,R8 mult and accumulate mpyi Rl,*AR7++%,R9 for 1 c o r r e l a t o r addi R8,R4 addi R9,R5 mpyi R0,R0 I chan sample square mpyi R1,R1 Q chan sample square addi RO,RIO I chan sum of squares addi R1,R10 Q chan sum of squares protect: f l o a t R2,R0 f l o a t R3,R1 f l o a t R4,R8 ' f l o a t R5,R9 f l o a t R10,R11 bz protect r s q r f R11,R10 mpyf R10/R0 mpyf R10,R1 mpyf R10,R8 mpyf R10,R9 s t f RO,*AR3 brd top s t f R1,*AR3 s t f R8,*AR3 s t f R9,*AR3 l d f 0,R11 s t f Rll,*AR3 brd top s t f Rll,*AR3 s t f Rll,*AR3 R l l holds sum of squares protect against zero d i v i s i o n RIO holds r e c i p r o c a l sqrt normalized 0 I c o r r e l a t o r output normalized 0 Q c o r r e l a t o r output n o r m a l i z e d ! I c o r r e l a t o r output normalized 1 Q c o r r e l a t o r output output c o r r e l a t o r r e s u l t s output zeroes 83 s t f R11,*AR3 .data i_addr: .word 00100061H q_addr: .word 00100081H is_addr: .word 00100071H o_addr: .word 00100072H center: .word 0000007EH . end comm port 2 input f i f o coram port 4 input f i f o comm port 3 input f i f o comm port 3 output f i f o ADC o f f s e t (127) D.3 Tracking Correlators /* We set up a p a i r of c o r r e l a t o r s to look f o r the 0 or the 1 represented by s h i f t e d or non-shifted PN sequence produced by gen.c and c o r r e l a t e with corr() contained i n f i l e cor.asm. Corr() also reads a s h i f t and a s l i d e from rec.c. There are 2 samples per chip. The s h i f t r e g i s t e r length i s read from rec.c and determines the PN sequence. /* f o r pow */ /* f o r malloc */ co r r e l a t o r written i n assembler PN sequence length */ PN gen s h i f t reg length */ */ #include <chan.h> #include <math.h> #include <stdlib.h> extern v o i d c o r r ( v o i d ) ; i n t N; i n t M; i n t connect[10][10]={{1,0,0,0,0,0,0,0,0,0} {1,1,0,0,0,0,0,0,0,0}, {1,0,1,0,0,0,0,0,0,0}, {1,0,0,1,0,0,0,0,0,0}, {1,0,0,1,0,0,0,0,0,0}, {1,0,0,0,0,1,0,0,0,0}, {1,0,0,0,0,0,1,0,0,0}, {1,0,0,0,1,1,1,0,0,0}, {1,0,0,0,0,1,0,0,0,0}, {1,0,0,0,0,0,0,1,0,0}}; i n t stage[] = {1,1,1,1,1,1,1,1,1,1}; /* s h i f t reg f o r PN generator */ i n t *pn0, *pnl; I* v o i d pn_gen(int *pn0, i n t *pnl); I* main(int argc, char *argv[], char *envp[], CHAN *in_ports[],. i n t ins, CHAN *out_ports[], i n t outs) { /* connection vectors */ pointers to the PN sequences the PN's generating func */_ i n t f l a g ; I* i n t *p0; /" i n t * p l ; chan_in_word(&M,in_ports[0]); /* N = pow(2,M)-l; pO = (int *) malloc(4*N+2); /* p i = (int *) malloc(4*N+2); pnO = (int *)((((unsigned int)p0»(M+l))+1)«(M+l)); /* aligned */ pnl = (int *)((((unsigned int)pl»(M+l))+1)«(M+l)); /* pointers */ for processor synchronization * pointer to a l l o c a t e d space */ read M from rec */ a l l o c a t e f or aligned pointer */ pn_gen(pnO,pnl); / i chan_out_word(flag,out_ports[1]); /* chan_in_word(&flag,in_ports[0]); / i chan_out_word(flag,out_ports[0]); I* corr(.); /" i n i t i a l i z e PN's */ ind i c a t e readiness to rec */ wait f o r receive to be ready */ f l a g gen to in d i c a t e ready */ c a l l c o r r e l a t o r function */ 84 } v o i d pn_gen(int *PN0, i n t *PN1) { i n t i , j , temp; for (j=0; j<N ; j++) { temp=0; *(PN0+((2*N-l+2*j)%(2*N))) = 1 - 2*stage[0] *(PN0+((2*N+2*j)%(2*N))) = 1 - 2*stage[0] *(PNl+((2*N+l+2*j)%(2*N))) = 1 - 2*stage[0] *(.PNl+( (2*N+2+2*j)%(2*N) ) ) = 1 - 2*stage[0] for (i=0; i < M; i++) { temp = temp"(stage[i]'connect[M-l][i]); i f (i<M-l) stage[i]=stage[i+1]; } . stage[M-l]=temp; } /* generate PN sequence */ /* e a r l y c o r r e l a t o r */ /* l a t e c o r r e l a t o r */ assembler routine to implement a p a i r of real-time c o r r e l a t o r s .version 40 .text .globl _ c o r r .globl _pn0 .globl _pnl .globl _N . top: ldpk @i_addr Ida @i_addr, ARO ldpk @q addr Ida @q_addr, AR1 ldpk @is_addr Ida @is_addr, AR2 ldpk @o_addr Ida @o_addr, AR3 ldpk @_pn0 Ida @_pn0, AR4 ldpk @_pnl Ida @_pnl, AR5 ldpk @_N Ida @_N( BK mpyi 2,BK ldpk ©center l d i ©center,R6 Ida AR4,AR6 Ida AR5,AR7 l d i *AR2,IR1 nop *AR6++(IR1)% nop *AR7++(IR1)% l d i *AR2,IR0 l d i IRO, RC l d i 0,R10 l d i 0,R2 rptbd f i n setup c o r r e l a t o r ARO holds I data input port addr AR1 'holds Q data input port addr s h i f t / s l i d e input port addr AR3 holds output port addr AR4 addresses e a r l y PN sequence AR5 addresses l a t e PN sequence N i s PN seq length for c i r c u l a r addressing mode two samples per chip ADC o f f s e t AR6 indexes e a r l y PN seq AR7 indexes l a t e PN seq read s h i f t i n t o IR1 s h i f t c o r r e l a t o r s read s l i d e repeat slide+1 times RIO holds sum of I sample squares R2 holds e a r l y I sum 85 l d i 0, R3 R3 holds e a r l y Q sum l d i 0, R4 R4 holds l a t e I sum l d i 0,R5 R5 holds l a t e Q sum lbuO *AR0,RO load zeroth byte lbuO *AR1, Rl load zeroth byte subi R6,R0 subtract ADC o f f s e t subi R6,R1 mpyi R0,*AR6 ,R8 I chan mult f o r e a r l y c o r r e l a t o r mpyi R1,*AR6++%,R9 Q chan mult f o r e a r l y c o r r e l a t o r addi R8, R2 accumulate I chan e a r l y corr addi R9,R3 accumulate Q chan l a t e corr mpyi RO,*AR7 , R8 mul t i p l y and accumulate mpyi R1,*AR7++%,R9 for l a t e c o r r e l a t o r addi R8,R4 addi R9,R5 mpyi RO , RO I chan sample square mpyi R1,R1 • Q chan sample square' addi R0,R10 I chan sum of squares addi R1.R10 Q chan sum of squares protect: i_addr: q_addr: is_addr: o_addr: center: f l o a t R2,R0 f l o a t R3,R1 f l o a t R4,R8 f l o a t R5,R9 f l o a t RIO,Rll bz protect r s q r f Rll,RIO mpyf R10,R0 mpyf R10,R1 mpyf RIO, R8 mpyf R10,R9 s t f R0,*AR3 brd top s t f R1,*AR3 s t f R8,*AR3 s t f R9,*AR3 l d f 0,R11 s t f Rll,*AR3 brd top s t f Rll,*AR3 s t f R11,*AR3 s t f Rll,*AR3 .data .word 00100061H .word 00100091H .word 00100041H .word 00100042H .word 0000007EH . end R l l holds sum of squares protect against zero d i v i s i o n RIO holds r e c i p r o c a l sqrt normalized 0 I c o r r e l a t o r output normalized 0 Q c o r r e l a t o r output normalized 1 I c o r r e l a t o r output normalized 1 Q c o r r e l a t o r output output c o r r e l a t o r results. output zeroes comm port 2 input f i f o comm port 5 input f i f o comm port 0 input f i f o comm port 0 output f i f o ADC o f f s e t (127) 86 D.4 Transmitter Code Transmitter code for word length 1, quadrature data transmission over the IF l i n k . We read from f i l e data, copy the data to the on-board memory, and then transmit a stream of independent I and Q channel data, with the assembler function t r a n ( ) , which i s the f a s t e s t p o s s i b l e transmitter. This task goes on processor C. */ #include <chan.h> #include <math.h> /* #include <stdlib.h> /* i n t N; /* i n t M; /* i n t len; /* i n t stage[] = {1,1,1,1,1,1,1,1,1,1}; /* i n t connect[10][10]={{1,0,0,0,0,0,0,0,0,0} {1,1,0,0,0,0,0,0,0,0}, {1,0,1,0,0,0,0,0,0,0}, {1,0,0,1,0,0,0,0,0,0}, {1,0,0,1,0,0,0,0,0,0}, ,0,1,0,0,0,0}, , 0 for pow */ for malloc */ length of the PN sequence */ number of PN generator stages N, used by trans() */ s h i f t reg f o r PN generator */ {1,0,0,0, {1,0,0,0, {1,0,0,0, {1,0,0,0, , 0„ 0, 1,0,0,0}, 1,0,0,0}, 0,0,0,0}, 0,1,0,0}}; {1,0 i n t *pni; i n t *pnq; i n t * b u f i ; i n t *bufq; i n t count; v o i d pn_gen(int *pni, i n t *pnq) extern v o i d t r a n s ( ) ; main(int argc, char CHAN * i n _ p o r t s [ ] , /* connection vectors */ /* pointer to I chan PN seq */ /* pointer to Q chan PN seq */ /* pointer to I chan input data */ /* pointer to Q chan input data */ /* data count minus one */ /* function written i n assembler */ *argv[], char *envp[], i n t i ns, CHAN *out_ports[], i n t outs { i n t f l a g ; i n t valuei=0; i n t valueq=0; i n t i=0; i n t ESHIFT; i n t * p i ; i n t *pq; i n t datacount; chan_in_word(&M,in_ports[0] ) /* for processor synchronization */ /* for data input */ /* a data index */ /* to a l l o c a t e space */ /* read M from c o r r e l a t o r '*/ 87 length of elem code s h i f t */ a l l o c a t e for aligned pointer N = pow(2,M)-1; len = N; ESHIFT = (N-l)/2; f p i = (int *)malloc(2*len); f pq = (int *)malloc(2*len); pni = (int *)((((unsigned int)pi»(M))+1)«(M)); /* aligned */ pnq = (int *)((((unsigned int)pq>>(M))+1)<<(M)); /* pointers */ chan_in_word(&datacount,in_ports[0]); '/*' read data count */ count = datacount/2-1; b u f i = calloc(datacount/2,1); /* a l l o c storage f o r input data bufq = calloc(datacount/2,1); i f (buf q==NULL) chan_out_word (1, out_ports.[ 0 ] ) ; else chan_out_word(0,out_ports[0]); , while { (valuei!=-l)&&(valueq!=-l) ) { chan_in_word(lvaluei,in ports[0]) ; Mbufi+i) = valuei*ESHIFT •; I* chan_in_word(&valueq,in_ports[0]); *(bufq+i) = valueq*ESHIFT ; i + +; } /* read and store data /* data terminated by a store the s h i f t s */ pn_gen(pni,pnq) ; /* i n i t i a l i z e PN's */ chan_in_word(&flag,in\_ports[0]); /* wait for corrs to be ready */ chan_in_word(&flag,in_ports[1]); t r a n s ( ) ; /* transmit */ while(1); ) v o i d pn_gen(int *PNI, i n t *PNQ) { • i n t i , j , temp; i n t value; /* PN sequence generator */ fo r (j=0; j<N ; j++) {• value = - l * s t a g e [ 0 ] ; *(PNI+j) = value; *(PNQ+j) = value; /* convert 1 to a l l ones word */ /* store I chan PN sequence */ /* store Q chan PN sequence */ temp=0; for (i=0; i < M; i++) { temp = temp"(stage[i]'connect[M-l][i]); i f (i<M-l) stage[i]=stage[i+1]; } stage[M-l]=temp; assembler routine f o r real-time transmission 88 trans: l p l : lp2 : .version 40 .text .globl _trans .globl _ b u f i .globl _bufq .globl _pni .globl _pnq .globl _ l e n .globl _count push AR3 push AR4 push AR5 push AR6 push AR7 push R4 push R5 push R6 pushf R6 push R7 pushf R7 push R8 ldpk @_len • l d i @_len,BK ldpk @ pni l d i @_pni,R8 ldpk @_pnq l d i @_pnq,R9 ldpk @i_addr Ida @i_addr,AR2 ldpk @q_addr Ida @q_addr,AR3 ldpk @_bufi Ida @_bufi,AR4 ldpk @_bufq Ida @_bufq,AR5 ldpk @_count Ida @_count,AR6 l d i R8,AR0 l d i R9,AR1 subi 1,BK,RC l d i *AR4++,IR0 rptbd lp2 l d i *AR5++,IR1 nop *AR0++(IR0)% nop *AR1++(IR1)% l d i *AR0++%,R3 l d i *AR1++%,R5 s t i R3,*AR2 s t i R5,*AR3 s t i R3,*AR2 s t i R5,*AR3 points, to I points to Q points to I points to Q PN sequence length data count chan data b u f f e r chan data b u f f e r chan PN sequence chan PN sequence ; f o r c i r c u l a r addressing ; R8 addresses pni ; R9 addresses pnq ; I chan output port ; Q chan output port ; AR4 holds I channel data b u f f e r ; AR5 holds I channel data b u f f e r AR6 holds data count minus one set ARO to pni s t a r t addr set AR1 to pnq s t a r t addr fo r repeat mode read I chan s h i f t i n t o IRO read Q chan s h i f t i n t o IR1 s h i f t pni index according to I data s h i f t pnq index according to Q data s t a r t of repeat block I/Q chan chips i n R3/R5 write chips to output ports repeat write for h a l f speed transmission 89 i_addr: q_addr: db AR6,lpl pop R8 popf R7 pop R7 popf R6 pop R6 pop R5 pop R4 pop AR7 pop AR6 pop AR5 pop AR4 pop AR3 rets . data .word 00100052H .word 00100062H . end comm port 0 output f i f o comm port 1 output f i f o D.5 Application Configuration ! Hardware configuration processor root processor second processor t h i r d processor fourth wire ? root[0] second[3] wire ? second[0] third[3] wire ? third[0] fourth[3] wire ? fourth!0] root[3] ! Software configuration task rec4 ins=2 outs=2 task corr4 ins=2 outs=2 task corrd4 ins=l outs=2 task gen4 ins=2 outs=l 0PT=C0DE place rec4 root place corr4 second place gen4 t h i r d place corrd4 fourth connect ? rec4[0] corr4[0] connect ? rec4[l] corrd4[0] connect ? corr4[0] gen4[0] connect ? corrd4[0] gen4[1] connect ? co r r 4 [ l ] rec4[0] connect ? gen4[0] c o r r 4 [ l ] connect ? corrd4[l] rec4[l] 90

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