GALLIUM ARSENIDE INTEGRATED CIRCUIT MODELING, LAYOUT AND FABRICATION by WILLIAM C. RUTHERFORD A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA MAY 1987 © WILLIAM C. RUTHERFORD, 1987 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date Ju^e /fl, 1971 DE-6(3/81) ABSTRACT The object of the work described in this thesis was to develop GaAs integrated circuit modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold circuits. A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance of inverted common drain logic (ICDL) digital integrated circuits compared to other circuit configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width capability of 25 ps with 5 ps rise and fall time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough isolation and minimum sampling switch off isolation of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 urn gate length process approaches the suggested performance guidelines. A mask layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate i i structure produces a sub 0.5 Mm gate length. Ac knowledgement Our work on the integrated sampling amplifier block was supported by the Defense Research Establishment Ottawa. I thank my supervisor, Dr. L. Young, for his guidance and for suggesting many of the ideas in this work. Mr. Salam Dindo is to be thanked for his advice concerning layout topology and process optimization. Mr. David Michelson is to be thanked for his discussions of microwave circuit considerations. Mr. Bruce Beggs is to be thanked for his collaboration in developing fine line lithography techniques. Mr. Peter Townsley is to be thanked for his effort in getting the first two runs of selective implant devices working. Mrs. Mary Mager is to be thanked for instructing Bruce Beggs and myself on the intricacies of SEM photography. Mr. Martin Lord is to be thanked for his effort to get discrete MESFET test fixtures built by Microtel Pacific Research Ltd. Mr. Hiroshi Kato is to be thanked for his work on the RSAG process. i v Table of Contents ABSTRACT . ii Acknowledgement v List of Tables viiList of Figures ix Symbol Definitions xii List of Acronyms xv1. Introduction 1 1.1 Integrated Sampling Amplifier Overview 1 2. Process Definition, Parameter Extraction and Mask Layout 14 2.0.1 Process Parameters 12.1 Process Definition 15 2.1.1 Process Listing 6 3. Schottky Diode Parameter Extraction and Layout 30 4. MESFET Parameter Extraction and Layout 34 4.1 Alignment Limitations 34.1.1 Interlayer Alignment Marks 35 4.2 RSAG and Selective Implant Process Parameter Differences 37 4.2.1 Source and Drain Resistance 37 4.2.2 Gate Phase Shift 39 4.3 MESFET Capacitance 41 4.4 MESFET 1 Mm Slice Parameters 42 5. Switch Considerations and Layout 51 5.1 The Sampling Cycle 54 5.2 Guard and Sampling Gate Biasing Considerations 6 5.3 Hold Capacitance Considerations 56 v 6. Amplifier Layout 59 7. ISAB Design and Layouts 66 7.1 Configurations7.2 I SAB Simulation Results 68 8. Process Monitors and Measured Results 87 8.1 Isolation Monitors 88.2 TLMs 88.3 Power MESFET 88 8.4 TiW Sheet Resistance 88.5 Three Amplifier Oscillator 89 8.6 Peaking Inductor ...88.7 Selective Implant Fabrication Run Results 91 8.7.1 Isolation 98.7.2 Doping and Mobility Profiles 92 8.7.3 SI MESFET Characteristics 94 9. Conclusion 96 REFERENCES 7 10. Appendix A -ICDL Simulations 102 10.1 Digital Integrated Circuit Simulation Overview 1010.2 ICDL Basic Circuits 105 10.3 Buffer Circuit 107 10.4 Inverter 110 10.5 Buffered Inverter 115 10.6 OR Gate 1110.7 AND Gate10.8 Results and their SPICE Simulation 116 REFERENCES FOR APPENDIX A ....119 vi 11. Appendix B -Layouts 121 12. Appendix C -GASFET Subroutine 123 13. Appendix D -Simulation Source Listings 129 vii List of Tables Table Description Page 1.1 Overall mask pattern die locations.... 12 2.1 Process Parameters 14 2.2 Process Plates 5 4.1 Thin film resistivity 40 5.1 MESFET parameters for sampling switches 58 viii List of Figures Figure Description Page 1.1 Integrated Sampling Amplifier Block configuration 3 1.2 Triple Gate Switch Cross Sections 5 1.3 Overall layout pattern 7 2.1 Nonbevelled PR edge profile, no chlorobenzene soak 17 2.2 Bevelled profile with chlorobenzene... 19 2.3 N" implant profile 20 2.4 SEM photograph of alignment 21 2.5 SEM photograph of 1/Ltm gate before liftoff 22 2.6 SEM photograph of Ijim gate after liftoff 23 2.7 Cross Section of MIM 25 2.8 MESFET Gate Cross Sections.. 28 3.1 Schottky diode cross sections 30 4.1 Alignment marks 36 4.2 Cross section of MESFETs 38 4.3 MESFET circuit model 42 4.4 a) 7r-Gate Layout 43 4.4 b) 7r-Gate Magnified 4 4.5 RSAG 0.5Mm characteristics 45 4.6 RSAG lAim characteristics 46 ix 4.7 SI characteristics 47 5.1 a) Triple Gate Switch Layout 51 5.1 b) Magnified Triple Gate Switch 52 5.2 Triple Gate Switch Slice Equivalent Circuit 53 5.3 Triple Gate Switch Distributed Model..53 5.4 Single Gate Distributed Simulation.... 55 6.1 Amplifier Equivalent Circuit 59 6.2 Amplifier Layout 60 6.3 Amplifier Open Loop DC Characteristic.61 6.4 AORT3_9012 Open Loop Transient 61 6.5 90mn RSAG1_2 Amplifier DC Character i st ics 62 6.6 90/im RSAG1_2 Amplifier Step Response..62 6.7 90MITI RSAG2_2 Amplifier DC Characteristics 63 6.8 90mri RSAG2_2 Amplifier Step Response..63 6.9 90/im SI1_2 Amplifier DC Characteristics 64 6.10 90MITI S11_2 Amplifier Step Response.... 64 7.1 SI and RSAG I SAB layout ...66 7.2 MIM ISAB layout 67 7.3 RSAG1_2 Single Gate ISAB Tracking 69 7.4 RSAG1_2 Dual Gate ISAB Tracking 69 7.5 RSAG1_2 Triple Gate ISAB Tracking 70 7.6 RSAG1_2 Single Gate Time Constant 70 7.7 RSAG1_2 Dual Gate Time Constant 71 x 7.8 RSAG1_2 Triple Gate Time Constant 71 7.9 Pad Pulse Distortion 72 7.10 Single Gate Feedthrough 73 7.11 Dual Gate Feedthrough 73 7.12 Triple Gate Feedthrough ..74 7.13 Guard Gate Source and Drain Voltages..76 7.14 Guard Gate Current 77 7.15 RI16R912T3 150ps Tracking, 0.6 V Bias.79 7.16 RI16R912T3 150ps Tracking, 0.4 V Bias.80 7.17 RI16R912T3 75ps Tracking 81 7.18 RI16R912T3 25ps Tracking 82 7.19 RI36R912T3 300ps Tracking 83 7.20 RI26R912T3 50ps Tracking 84 8.1 Power MESFET Gate Strip Layout 88 8.2 TiW Stepped Resistor Layout 89 8.3 Test Oscillator OFRT3_9013 90 8.4 Amplifier Peaking Inductor 90 8.5 Isolation monitor chip 8. 91 8.6 Isolation monitor chip 5 ...92 8.7 SI doping profile 93 8.8 SI mobility profile..... 93 8.9 SF_236_1_4 *~gate I-V characteristics.94 xi Symbol Definitions Symbol Units Description 5I Mm mask intra layer skew *L Mm mask inter layer skew «A Mm mask alignment skew 5 LA Mm lateral alloy movement e F/cm free space permittivity GaAs F/cm permittivity of GaAs, taken as 12. 9e cm2/V-s Hall mobility cmJ/V-s electron low field drift mobility cm2/V-s electron drift mobility P 0/cm specific resistivity Pen fi/Mm2 contact specific resistance, C1 = N + GaAs to AuGe, C2 = AuGe to TiW. ARp standard deviation of the implant r ps channel transit time = L/v^r VS cm/s saturated electron drift velocity ="nEs *Bn V Schottky barrier height on n-GaAs ©G rad/Mm gate phase shift fi A/V2 MESFET model current gain factor X v- • channel length modulation parameter a hyperbolic tangent function parameter Es V/cm velocity saturation field =vs/vn L Mm channel length xi i t Mm apparent channel thickness A Mm effective uniform profile channel thickness LQ Mm metallurgical gate length Lgap Mm effective MESFET source or drain to gate gap or diode Schottky metal to ohmic gap. Z Mm gate width dimension CGD fF/Mm gate to drain capacitance CQg fF/Mm gate to source capacitance CDS fF/Mm drain to source capacitance Cgc fF/Mm space charge capacitance RpS fl/Mm Schottky diode parasitic series resistance RG ft gate series resistance Rg fl source series resistance RD fl drain series resistance Rsi ft/n LEC GaAs semi-insulating sheet resistivity RgH ft drain to source shunt resistance gm mA/V 9IDS/3VGS IDg mk/nm drain to source current ^SS mA/Mm saturated drain to source current at stated VQS and VDS xi i i V-,- V internal gate to source voltage VGg V external gate to source voltage V^g V internal drain to source voltage VDg V external drain to source voltage V^g V substrate bias voltage fT Hz cutoff frequency = 1/(27rr) V (positive) built-in voltage at the gate Vp V pinchoff voltage =q/eGaAs/^N(x)xdx VT V threshold voltage VT=Vp+Vbi WQ Mm zero gate bias depletion width Wi Mm the doping profile depth at a doping level of 10'6 n diode ideality factor N(x) ions/cm3 activated ion implanted doping profile Na ions/cm3 effective p-doping substrate concentrat ion ND ions/cm3 effective uniform profile channel doping density Nmax ions/cm3 peak value of doping profile q C electron charge n e/cm3 free electron concentration n^ e/cm3 intrinsic free electron concentration NQ s/cm3 effective density of states in conduction band xiv NT s/cm3 total concentration of traps Q1 ions/cm2 total N" dose Q_2 ions/cm2 total N+ dose Qa ions/cm available dose =/oN(x)dx keV N" implant energy $2 keV N + implant energy RpQ cm projected range of the implantation Rp cm effective projected range Rp0-ARp xv List of Acronyms Acronym Meaning BFL buffered FET logic CAD computer aided design EBL electron beam lithography ID interdigitated MBE molecular beam epitaxy MESFET metal semiconductor field effect transistor MIM metal insulator metal PR positive photoresist RD refractory diode RIE reactive ion etch RSAG refractory self aligned gate ISAB integrated sampling amplifier block SD selective implant diode SEM scanning electron microscope SI selective implant SPICE simulation program with integrated circuit emphasis TD two implant diode, SD on N+ xvi 1. INTRODUCTION The purpose of this work was to investigate the design, simulation and fabrication of GaAs devices and in particular of a GaAs sample and hold device. The work was sponsored by the Defense Research Establishment Ottawa. 1.1 INTEGRATED SAMPLING AMPLIFIER OVERVIEW One of the target applications for integrated GaAs sample and holds is a microwave acquisition system or digital radio frequency memory(DRFM)[1.1]. This involves sampling a microwave frequency signal on an input delay line at regular distributed points. Ideally the entire unit would be constructed on a single chip, complete with microstrip delay line, pulse generator, controller circuits, and analog to digital conversion. The primary purpose of the simulation, layout and fabrication is to investigate and optimize, as far as possible within the confines of the available process parameters, the performance of the integrated sampling amplifier (ISAB). The most important aspects of the ISAB are a low input time constant, ideally less than 25ps, combined with minimal strobe "blow-by". In previous published work Saul[1.2] demonstrated a MESFET switch ring approach with greater than 40dB of "OFF" isolation and an acquisition time of 2ns suggesting operation up to 250MHz. Sample pulse "blow-by" or feedthrough was minimized by careful chip and circuit layout 1 2 to minimize capacitive coupling. Sample strobe feedthrough ranged from a worst case of about 80mV to an average of about 20 to 30 mV on a 2.5V signal corresponding to about 40dB of strobe isolation from the sampled signal. A 1/zm SI triple gate MESFET switch ISAB with a 65ps input time constant was built and tested to 500 Megasamples per second, using a 36MHz sine-wave input by G.S. Barta and A.G. Rode[1.3]. Isolation in the "OFF" state was about 40dB with a MHz band input. Sample strobe blow-by was -35mV on a 300 mV signal, corresponding to 18.6dB of strobe isolation. The test equipment was considered inadequate for the full capability of the device. If the MIM capacitor was omitted an input time constant of about 33ps would result, close to the desired specification. However absence of the MIM capacitor would likely result in a reduction of strobe isolation below the already marginal specification. Work at U.B.C. by Durtler attempted to extend the results of Barta and Rode using a single and dual gate switch configurationf1.4]. The ISAB configuration, shown in figure 1.1, consists of either a single, dual or triple gate sampling switch followed by a MIM or interdigitated hold capacitor and an amplifier. Due to the low acquisition time, switch configuration variations are designed to investigate the relative merit of MESFET "guard gates" (BSG1 and BSG2 in Fig. 1.1) in suppressing sampling strobe feedthrough to the signal path. 3 The amplifier is, in its open loop form, essentially a BFL inverter, shown with the ICDL modeling section of Appendix A. Feedback is achieved by adding another MESFET(BFB) with source and drain, in parallel with the input MESFET as shown in Fig. 1.1. The amplifier was developed to enable cascading and is treated extensively by D.P. Hornbuckle, R.L. Van Tuyl and D.B. Estreich [1.5,1.6,1.7,1.8]. The MESFET integrated sampling switch and amplifier built and tested by G. S. Barta and A. G. Rode[1.3], was fabricated in SI process technology, with the Nminus channel implant through a 100nm silox film yielding Vp=-1.5 V or VT*-0.8 V. The lithographic resolution was ^um lines and Ijxm gaps for the triple gate structure resulting in an "ON" Fig. 1.1 Integrated Sampling Amplifier Block configuration. 4 resistance of 120S2 at Vgs=0 V for a 100Mm width, or 12000ft/Mm. The base RC input time constant calculated from this is 36ps as compared to the 65ps input time constant arrived at with 90% sampling efficiency with a 150ps strobe. If the system is considered as a simple RC network with a switch input step height and the capacitor initially at Vh0 such that 5V=Vi-Vh0 then Vh(t)=Vi-6Ve"t/r and 90% of 6V is lost in t=2.3r. This would imply an input time constant of 83ps for the switch, as compared to the measured 65ps. However the MESFET I^g is not linear with V^g and the strobe can be driven to 0.5* V providing more node charging current. The amplifier output stage diode stack employs diodes fabricated using gate metal on N* GaAs, reducing the series resistance(RpS) per unit width of the forward biased stack diodes. A 150fF MIM capacitor was formed by using 100 nm of sputtered silicon nitride over an AuGe base plate resulting in a total of about 300fF sample node capacitance and a droop rate of 4 mV/ns. The use of external capacitors induces excessive ringing due to lead inductance[1.2]. The amplifier had a measured 3dB bandwidth of 1.1GHz with unity gain feedback and a measured system slew rate of 800 V/MS. The aim of the present project was to extend the work of Barta and Rode by modeling and implementing an ISAB in refractory self aligned gate(RSAG) technology using lithographic resolution of 1/im line and 2um gaps as shown in figure 1.2. As the RSAG process is a t-gate technology the 5 SI I urn line lum gap RSAG lum line 2um gap 3- —•t= RSAG 0.2um line 0.2um gap Nplus TiW AuGe Schottky Fig. 1.2 Triple Gate Switch Cross Sections. resulting submicrometer gate will exhibit a reduced CgS which should reduce the displaced charge during strobe operation and increase the strobe isolation to over 20dB. The input time constant should be reduced by decreasing the "ON" resistance per Mm with the self aligned intergate Nplus implant. Considering the triple gate structures of figure 1.2 four series parasitic resistance regions will have a sheet resistance reduction of about 5 times which should reduce "ON" resistance by 15 to 20% compared to Barta and Rode. Thus the same width switch RSAG version of the SI triple gate ISAB should have a 55ps input time constant with about 25dB of strobe isolation. Strobe isolation could then be sacrificed by reducing the node capacitance to bring the input time constant into the 25ps range. This implies that 6 operation up to 20GHz would be possible with the triple gate configuration. Dual and single gate configurations would have lower input time constants, which is the main priority of the work. The RSAG process has been demonstrated for digital integrated circuitsC1.9,1.10,1.11 ] of short gate widthdOmn) and gate length down to less than 0.1um using electron beam lithography (EBL). Devices with 0.5/um gate length are obtainable with 300nm optical lithography capable of 1um linewidthst1.4]. Considering the 0.2wm EBL triple gate of figure 1.2, "ON" resistance would be reduced by about ten times and CgS about 5 times compared to the other RSAG cross section. This implies that operation up to several hundred GHz would be possible with good strobe isolation. As the RSAG TiW or tungsten silicide gate metalization is more resistive than SI gate metalizations RSAG switch gates should be driven at one or more t-junctions, similar to power MESFETs. In order to fabricate RSAG MESFET ISABs with low Rps Schottky diodes for the amplifier output stage and MIM capacitors, eight mask layers were necessary. Interdigitated hold capacitors were used in the ISAB layouts as an alternative to the MIM type and if successful will result in the elimination of one mask layer and an increase in yield, which would be significant for the single chip acquisition system. Only the refractory and Schottky metalizations are shown in figure 1.3 for clarity. 7 Lithographic plate process related layout variations are designed to enable fabrication of high performance working devices, with manufacturable tolerances. As such SI layouts with ~\nm gate lengths and 2, 3, or 4nm source and drain to gate gaps are combined with six RSAG layouts with 1 or 2Mm gate mask lengths and 2, 3, or 4 /zm source and drain A mSm m II * 61 8- • BS SI A • A A C-. 8% afi" a&" 8% • • A A D- SI 8ft • • A A P mmm e- 8% eft da *i eft £ £ £ A Fan H eft eft ela £ £ A G-s 8G> eft eft £ H§ -H * 9fr e& 8% da e& eft • JJL a 1 A 8- 8ft r+::+ j + + 4- M • • V • J A e- 8ft eft II K A 9- SB* 8- 6- M « « 6! 81 1 • L A B • A" •I >••» fill va •'• • =. 1 1 2 3 4 5 6 7 8 9 10 Fig. 1.3 Overall layout pattern. 8 to gate gaps, for a total of nine basic MESFET variations. It was necessary to leave approximately 300MITI channels between the device die to enable nondestructive separation with a narrow blade saw, assuming a cutting channel of about 100 Mm and a chipping width of about 40Mm [1.12]. This requirement served to motivate compaction of the device pad frame in order to maximize the number of ISAB units in the lithographically optimal inner 60% of the overall pattern[1.13]. A modified pad frame may be necessary later in the discrete phase of the project to enable automatic probing. Conversely the one chip acquisition system would have minimal pad requirements enabling circuit compaction within the limits of the transmission line geometries. The first mask layer is used to control an alignment etch in the surface about 2Mm deep to provide a reference for all subsequent layers. The second layer provides holes through which to implant the active regions for MESFET channel characteristics (N~). The third layer provides a pattern for the t-gate top for the RSAG process, protecting regions of TiW from removal. The fourth layer provides an implant mask for the N+ regions. The fifth mask is for ohmic contact to the N+ regions and production of MIM bottoms and inductors over nonactivated substrate. The sixth layer is a positive overlay mask protecting the MIM insulator Si3N4 dielectric from etching, (which could be eliminated). The seventh mask is for SI Schottky metalization providing a high quality 9 interface for N* diodes and MESFET gates. This metalization serves a dual purpose as the MIM capacitor top plate. The eighth mask defines openings which are to be gold plated to a few Mm for airbridge bodies and bonding pad thickening. The N~ mask can be used with negative photo resist for implant isolation if necessary. The overall pattern outer dimensions are approximately 8.8mm high by 9.2mm across. Test patterns for process calibration and device characterization are around the outer edge of the pattern. The devices are listed in table 1.1 with alphanumeric grid reference to figure 1.3. The trailing grid reference characters(L,R,T,B) refer to the left, right, top and bottom of the addressed cell. Loc Item Description/Code A 1 diagnostic amplifier AORT2_9024 A 2 diagnostic amplifier AORR2_9024 A 3LT RD diagnostic diode 5Mm Lg A 3LB RD diagnostic diode 10Mm Lg A 3R RD diagnostic diode 3Mm Lg A 4 amplifier AFRT3_9024 A 5 amplifier AFRT3_9023 A 6 amplifier AFRT3_9022 A 7 switch R2_40_1_A 8 switch R3_60_1_3 A 9L switch RO0_1_2 A 9R L C calibration inductor test B 1 diagnostic amplifier AORT3_9024 B 2 diagnostic amplifier AORR3_9024 B 3LT TD diagnostic diode 5Mm Lg B 3LB TD diagnostic diode 10^m Lg B 3R TD diagnostic diode 3Mm Lg B 4 amplifier AFRT3_9014 B 5 amplifier AFRT4_901B 6 amplifier AFRR3_9012 B 7 switch R3_60_1_B 8 100Mm test FET SF_100_1_3 B 9L 100Mm test FET SF 100 1 4 10 B 9R 100Mm test FET RF_100_2_4 B 10 fat FET RSAG normal C 1 inductor large center C 2 switch R2 60 2 2 C 3 ISAB RM16R924T3 C 4 amplifier AFRT3 9013 C 5 amplifier AFRT4 9013 C 6 amplifier AFRR3~9013 C 7 ISAB RM16R922T3 C 8 100Mm test FET SF 100 1 2 C 9L 100**m test FET RF 100~1 4 C 9R 100t*m test FET RF~100~2_3 C 10 fat FET RSAG no Nplus D 1 inductor small center D 2 switch R3 60 2 4 D 3 ISAB RMT6R923T3 D 4 amplifier - AFRT3 9012 D 5 amplifier AFRR2~6012 D 6 amplifier AFRR2~6013 D 7 alignment mark D 8 100Mm test FET RF 100 1 2 D 9L 100Mm test FET RF 100~1 3 D 9R 100Mm test FET RF_100~2~2 D 10 fat FET SI on Nplus E 1 stepped resistor TiW 3 step E 2 switch R1 60 2 2 E 3 ISAB RM16R914T3 E 4 ISAB RM16R913T3 E 5 ISAB SI3S912T3 E 6 ISAB SI2S912T3 E 7 ISAB SI1S912T3 B 8 '-gate FET RF 236 1 4 E 9L ff-gate FET SF 236 1 2 E 9R "•-gate FET RF_236_2_4 E 10 fat FET SI normal F 1 stepped resistor TiW 3 step F 2 switch R3 60 1 4 F 3 ISAB RI16R913T4 F 4 ISAB RI16R912T3 F 5 ISAB RI34R612T3 F 6 ISAB RI36R912T3 F 7 ISAB RI36R913T3 F 8 ff-gate FET RF 236 1 3 F 9L ff-gate FET SF 236~1~3 F 9R "•-gate FET RF~236~2_3 F 10 fat FET SI~on both G 1L isolation monitor lateral 10Mm by 150mi gap G 1R isolation monitor vertical G 2 switch R2 60 1 2 G 3 ISAB RI16R913T3 G 4 ISAB RI16R912R3 G 5 ISAB RI26R912T3 G 6 ISAB RI26R913T3 G 7 ISAB SI1S913T3 G 8 ff-gate FET RF 236 1 2 G 9L "•-gate FET SF 236~1~4 G 9R "•-gate FET RF 236~2 4 11 G 10 isolation monitor lateral H 1 fat FET RSAG normal H 2 switch R3 40 1 2 H 3 ISAB RI26R922T3 H 4 ISAB RM16R912T3 H 5 ISAB SI3S913T3 H 6 ISAB SI2S913T3 H 7 ISAB SI1S914T3 H 8 dual gate FET RMPR 1 2 H 9L dual gate FET SMPR 1 2 H 9R dual gate FET RMPR~2~2 H 10 isolation monitor vertical I 1 fat FET RSAG no Nplus I 2 switch R1 60 1 2 I 3 ISAB RI16R924T3 I 4 alignment mark I 5 ISAB RI16R914T4 I 6 3 amp oscillator OFRT39013 I 7 power FET dfet-500Mm I 8 dual gate FET RMPR 1 3 I 9L dual gate FET SMPR 1 3 I 9R dual gate FET RMPR~2_3 I 10 meander AuGe J 1 fat FET SI on Nplus J 2 switch R1 60 1 3 J 3 ISAB RI16R923T3 J 4 ISAB RI16R922T3 J 5 ISAB RI16R914T3 J 6 modulator M26R912T3 J 7L dual gate switch rm2 40 1 2 J 7R dual gate switch rm2 40 1~3 J 8 dual gate FET RMPR 1~4~ J 9L dual gate FET SMPR~1 4 J 9R dual gate FET RMPR_2_4 J 10 meander SI gate metal K 1 Fat FET SI on Nminus K 2 switch R1 60 2 3 K 3 switch R3~60 2 2 K 4 switch R1 60 2 4 K 5 switch R1 60 1 4 K 6 switch R2 60~1~4 K 7 switch R2 60 1~3 K 8 switch R2~60~2~4 K 9L switch R2 60 2 3 K 9R switch R3_60_2~3 L 1 fat FET SI on both L 2T SD diagnostic diode 5 Mm Ls L 2B SD diagnostic diode 3 Men Ls L 3 SD diagnostic diode 10Mm Ls L 4 airbridge test AuGe under bridge L 5T transmission line on Nminus L 5B transmission line on both L 6 diagnostic amplifier AORT4 9024 L 7 diagnostic amplifier AORR4_9024 L 8T MIM capacitor area 5 by 100*411 L 8B MIM capacitor area 6 by 60Mm 12 L 9T Interdigitated capacitor MIM capacitor transmission line 14 half pairs 200^m long L 9B L 10 area 50,000Mm' on Nplus Table 1.1 Overall mask pattern die locations Device codes, for the most part, serve the dual purpose of CAD data base file name and unit description. The switch identification code begins with the process type, 'R' for RSAG and 'S' for SI, followed by the number of gates, the gate width over the active region, the mask gate length and the source/drain to gate gap in Mm. The ir-gate FET code begins with the process type followed by 'F', the gate width over the active region, mask gate length and source/drain to gate gap. The dual gate FET code begins with the process type followed by the logo "MPR" of the target test facility, Microtel Pacific Research, then mask gate length and source/drain to gate gap. For the amplifiers the first two characters identify configuration as open loop 'AO' or feedback 'AF' followed by the MESFET process type. The next two characters are the diode process type, 'T' for SI gate metal on Nplus, and the number of diodes in the stack. The first two of the last four digits indicate the output stage MESFET width, followed by the mask gate length and source/drain to gate gap. The ISAB code starts with the switch process type followed by the hold capacitor type, 'M' for MIM and 'I' for interdigitated, the number of gates in the switch, a single digit representation of the switch gate width(ie. 6 for 13 60um), the amplifier MESFET process type, a single digit representation of the output stage widthde. 9 for 90mn), then source/drain to gate and intergate gap for both the switch and amplifier, and finally the diode process type and number of diodes in the stack. 2. PROCESS DEFINITION, PARAMETER EXTRACTION AND MASK LAYOUT Process parameters required for layout were estimated from previous work, then adjusted by calculation for current process requirements. 2.0.1 PROCESS PARAMETERS Table 2.1 represents averaged data from Dindo[2.1] at U.B.C. and Sadler[2.2] at Cornell University, concerning Si ion implanted processing of LEC GaAs. Parameter Value Source Rsi 3-io« «/• [2.1] Qi 2.2 '10'' ions/cmJ [2.1] •i 100 keV [2.1] Rsht1 1542 «/• [2.1] vT -1.97 V [2.1] VP 2.67 V [2.1] RP1 85 nm [2.1] ARP1 44.2 nm [2.1 ] W0 114 nm [2.1] W1 244 nm [2.1] Nmax1 1.27-10" [2.1] Q2 2-10" ions/cm' [2.2] *2 150 keV [2.2] Rsht2 320 [2.2] Rp2 110 nm [2.2] ARp2 96 nm [2.2] Nmax2 5.2-10" [2.2] Nplus to AuGe Pc1 65 tt/«nJ [2.2] AuGe to TiW Pc2 78 n/Mnl [2.2] Table 2.1 Process Parameters 14 15 2.1 PROCESS DEFINITION Plate definitions used for fabrication (Table 2.2) are a consequence of ISAB features and the process steps to build them. The plates can be used with discretion to include or omit device features for a given process run. Plate Name 1N Align 2N Nminus 3N TiW 4N Nplus 5N AuGe 6P Dielectric 7N Schottky 8N ' Airbridge Description Align Etch pattern for subsequent layers. The Nminus implant is the same for all FBTs and Diodes active region. Defines t-gate and all TiW not etched. Defines the Nplus implant window allowing selective FET fabrication. Defines ohmic contacts and MIM capacitor bottoms. Si3Ng capacitor dielectric is etched back to PR islands. Schottky SI FET, TD diode metal, MIM tops and airbridge footing. Airbridge body, connector run and bonding pad thickening. Table 2.2 Process Plates The plates are designated by their plate name in the following process listing. The letter "N" or "P" following the plate number corresponds to positive or negative in terms of relation of the residual photoresist on the wafer, using positive photoresist, to the enclosed layer on the CAD station screen. "N" refers to no positive photoresist(PR) left in the enclosed area and ."P" refers to PR remaining in the enclosed area, being developed away elsewhere. 16 2.1.1 PROCESS LISTING The process allows production of both SI and RSAG devices concurrently, specifically allowing the use of low resistance two implant (TD) type diodes for RSAG amplifiers. As process results will be optimized for a given subprocess individual ISAB units were constructed from components of the same type with the notable exception of the diode stack. The RSAG process should be optimized with respect to ion implantation, TiW thickness, and plasma or reactive ion etch parameters, as a result of the 1 and 0.5Mm mask gate lengths, only one may be made optimal on a given wafer run. These fabrication parameters should be optimized for switch transient characteristics as the main priority as long as this is consistent with amplifier operation and process yield. Bevelling was found to be necessary on test pieces for reducing photoresist edge bead height. If the bevelling is omitted increased mask to surface gap results in loss of line width control and rectangular edge profile as seen in figure 2.1. Process steps 30 to 57 are similar to those developed for MMIC manufacturing^.3,2.4]. Problems with implant activation uniformity and dislocations due to handling are expected[2.5,2.6]. Step Description 1 Wafer bevelling(test pieces only) and surface layer removal: Fig. 2.1 Nonbevelled PR edge profile, no chlorobenzene soak. -deposit silicon nitride or Al over new wafer -scribe and break wafer as desired -spin on photoresist at low rpm -mount pieces to be bevelled with beeswax on glass slide or aluminum bevelling fixture for quarters -bevel wafer edges using 1.0**m alumina polishing compound on polisher, heating beeswax on hot plate to rotate 18 -remove PR, beeswax and alumina in boiling acetone -use hot acetone then trichloroethylene followed by Microstrip to remove residue, then rinse in DI water -remove protective layer with HF -1% Alconox solution -DI water rinse -First etch solution: 5:NH4OH 2:H202 240:DI -DI water rinse -Buffered HF -10% NH4OH -DI water rinse -Nitrogen blow dry 2 Photoresist deposition for alignment etch -Photoresist thickness: 1.5Wn 3 Photoresist pattern exposure for alignment etch -Plate: Align -Mask to PR method: vacuum contact 4 Photoresist develop for alignment etch -Developer type MF-316 -Spray application -DI water rinse 5 Alignment etch of GaAs surface -Etch solution: 5:NH4OH 2:H202 240:DI 6 Photoresist removal -Boiling acetone -Boiling isopropanol 7 Photoresist deposition for Nminus implant -Photoresist thickness: 1.5Mm 8 Photoresist pattern exposure for Nminus implant -Plate: Nminus -Mask to PR method: depends on work piece 9 Photoresist develop for Nminus implant -Developer type: MF-316 -Spray application -DI water rinse 10 Nminus Implant -Species: Si2^ -Energy: *^ keV -Dose: Qi ions/cm' -Wafer tilt: 11° -Wafer rotation: 22° Fig. 2.2 Bevelled profile with chlorobenzene 11 Photoresist removal -Hot Microstrip *TO Shipley Ltd. -Boiling acetone -Boiling isopropanol 12 Light cleaning etch -Etch solution: 1:NH4OH 1:H202 240:DI -DI water rinse -Buffered HF -10% NH4OH -DI water rinse -Nitrogen blow dry 13 Refractory metal deposition -Method: rf sputter, Ar atmosphere, TiW -Pressure 33 mTorr -RSAG thickness optimization hf 14 Refractory metal surface cleaning -Buffered HF -DI water rinse -Nitrogen blow dry 15 Photoresist deposition for t-gate mask -Photoresist thickness: 1.5Wn -Critical: prebake to remove water traces. -Spin on -Softbake 16 Photoresist pattern exposure for t-gate -Plate: TiW -Mask to PR method: vacuum contact Nminus Implant vs. Depth 20 min. annoal. 60* acflv* D*pth (nm) a implanted + annaated © activated g. 2.3 Nminus implant profile Fig. 2.4 SEM photograph of alignment 17 Photoresist develop for t-gate -Chlorobenzene soak -Developer type: MF-312 -Immersion -DI water rinse 18 T-gate top metal deposition -Deposition method: slow evaporation 19 Photoresist removal and t-gate liftoff -Boiling acetone -Boiling isopropanol 20 Refractory metal undercut etch -Etch method: plasma or RIE -Plasma composition: CF4 -RSAG etch optimization t, Afp, Ajr 21 Photoresist deposition for Nplus implant -Photoresist thickness: 1.5MB 22 Fig. 2.5 SEM photograph of 1/um sampling gate before liftoff 22 Photoresist pattern exposure for Nplus implant -Plate: Nplus -Mask to PR method: vacuum contact 23 Photoresist develop for Nplus implant -Developer type: MF-316 -Spray application -DI water rinse 24 Nplus implant -Species: Si2^ -Optimization for LG = 1 **m -Energy: *22 keV -Dose: Fig. 2.6 SEM Photograph of 1jim gate after liftoff. Q22 ions/cm* -Wafer tilt: 11° -Wafer rotation: 22° -Optimization for LG • 0.5^m -Energy: *21 fceV -Dose: Q21 ions/cm' -Wafer tilt: 11° -Wafer rotation: 22° 25 Photoresist removal -Hot Microstrip Shipley Ltd. -Boiling acetone -Boiling isopropanol 26 T-gate top removal 24 -Wet etch solution: HC1 -DI water rinse -Nitrogen blow dry 27 Silicon nitride blanket deposition -Plasma preclean using: NH3 -Plasma composition: He:500 seem SiH4:550 seem, NH3:37.6 seem 28 Implant anneal -furnace: 30 min. 800° C 29 Silicon nitride removal -Wet etch solution: HF -DI water rinse -Nitrogen blow dry 30 Photoresist deposition for AuGe -Photoresist thickness: 1Mm 31 Photoresist pattern exposure for AuGe -Plate: AuGe -Mask to PR method: vacuum contact 32 Photoresist develop for AuGe -Chlorobenzene soak -Developer type MF-312 -Immersion -DI water rinse 33 AuGe deposition -Deposition method: evaporation 34 Photoresist removal and AuGe liftoff -Boiling acetone -Boiling isopropanol 35 Alloy AuGe to Nplus GaAs -Optimization: furnace or rapid thermal alloy 36 Test process monitors enabled at this stage Isolation leakage TiW step resistor AuGe ohmic meander Transmission lines RSAG test MBSFBTs RD test diodes 37 Deposition of MIM capacitor dielectric: Si3N4 -Plasma preclean using: NHj -Deposition method: plasma -Plasma composition: He:500 seem SiH4:550 seem NH3:37.6 seem 38 Photoresist deposition 813X4 etch -Photoresist thickness: 1.5wn -Spin on -Softbake 39 Photoresist pattern exposure for MIM dielectric -Plate: Dielectric -Mask to PR method: vacuum contact 40 Photoresist develop for MIM dielectric -Developer type: MF-316 -Spray application -DI water rinse 41 Dielectric Etch to PR islands -Etch Solution 20% HF -Buffered HF -DI water rinse 42 Photoresist removal and liftoff -Boiling acetone -Boiling isopropanol 43 Photoresist deposition for Schottky metalization -Photoresist thickness: 1^m -Spin on -Softbake 44 Photoresist pattern exposure Fig. 2.7 Cross Section of MIM 26 -Plate: Schottky -Mask to PR method: vacuum contact 45 Photoresist develop for Schottky metalization -Developer type: MF-312 -Immersion -DI water rinse 46 Schottky metalization deposition -Deposition method: slow evaporation 47 Photoresist removal and metalization liftoff -Boiling acetone -Boiling isopropanol 48 Photoresist deposition for airbridge footing -Photoresist thickness: 1.5Mm 49 Photoresist pattern exposure for airbridge footing -Plate: Schottky -Mask to PR method: standard contact -Exposure wavelength: -Exposure 50 Photoresist develop for airbridge footing -Developer type: MF-316 -Spray application -DI water rinse 51 Deposition of airbridge footing and plate conduction metal -Method: rf sputter, Ar atmosphere, Au 3 nm 52 Photoresist deposition for airbridge body -Photoresist thickness: 1.5wn 53 Photoresist pattern exposure for airbridge body -Plate: Airbridge -Mask to PR method: standard contact 54 Photoresist develop for airbridge body -Developer type MF-316 -Spray application -DI water rinse 55 Gold plate airbridge body -electrodes on exposed edge Au -plate to few Mm -DI water rinse 56 Photoresist removal and plating metalization liftoff -Boiling acetone -Boiling isopropanol 27 57 Wafer/Slice completed With respect to step 20, plasma etching has a vertical to lateral etch rate vv-):v^1 of about 15:1 whereas RIE is 18:1. Referring to figure 2.8 MESFET high frequency performance improvement could be achieved by gate width resistance reduction and capacitance per unit width reduction by maximizing the TiW cross section available for conduction and minimizing the Schottky contact length. As the t-top should remain firmly in place for subsequent operations dft, the final dimension of the TiW top, should be maximized with respect to df^, the final dimension of the TiW bottom. The t-top, initially hfc^ thick and dt^ wide should have Rp+3ARp=ht£ thickness and kdfD=dt£, where k is in the order of 2, after etching to prevent 99% of the implant from reaching the channel[2.2]. Assuming the t-top material vv2:v^2 ratio is the same as TiW and the etch rates of significantly less magnitude the approximate maximum TiW thickness (hj) can be calculated for the two mask line widths and both etch processes. Taking as bias B=(dti-dt£)/2 - dft and the degree of anisotropy Aj = 1 -VQ_ ^/Vv -| as Af=1-B/2hj after Mogab[2.7] then dft=dm-(1-Af)2hf when etched to completion, where dm is the mask gate width and at completion ) 28 SI12 RSAG1 2 RSAG2_2 EM Nminus • Nplus TiW AuGe Schottky. Fig. 2.8 MESFET Gate Cross Sections. dfj3=dm. If etching continues until the base is tedm, or less, as required for RSAG dftc«dft-&dm=tedm-(1-Af)2hf where dftc is the critical TiW top width left to support the t-top through subsequent operations. Choosing dftc as 0.9dfbc, where df^^djj, corresponds to the Schottky contact width, for maximum t-top support, limits TiW thickness to hf*0.025dm/[(1-Af)]. Neglecting t-top etching hf = 0.025dmvvi/vi -j or about 0.45itm for RIE and 0.37itm for plasma etching of a 1itm dm t-top. For dm=2Mm a maximum 0.75um of TiW can be used with the plasma etch and 0.9um 29 with RIE. Over etching produces a shorter gate length at the risk of losing the t-tops. 3. SCHOTTKY DIODE PARAMETER EXTRACTION AND LAYOUT The amplifier output stage diode stack requires diodes which provide voltage level shifting with reasonable transient performance, compact size and reliable fabrication. Comparing the TD and RD structures of figure o) TO Type [ . . ' [ 'semi-insulating GaAs III] Nminus ; mW TiW B Sdniffcy • Nplus mi AuGe; : : : : : b) RD Type :::::::: Fig. 3.1 Schottky diode cross sections. a) TD Schottky gate metal on Nplus+Nminus b) RD RSAG process 30 31 3.1, where the "dot grid" is 1/im for the cross sections and 10jum for the amplifier stack top views, the TD type diode used by Barta and Rode[1.2] is more compact but at the expense of increased capacitance when compared to the RD type. In the forward biased mode of the amplifier stack the depletion width W diminishes as the applied voltage approaches V^. The major transport process is due to majority carriers tunneling from the GaAs under the depletion region over the potential barrier into the metal[3.1]. Thermionic emission theory is adequate for high mobility semiconductors and results in equation 3-1, [3.1]. Is = SA**T2exp(-q0B/kT) [3-1] For GaAs the Richardson constant changes from low to high field conditions at Es as the effective electron mass changes due to scattering into the upper valley of the conduction band. The high field condition sets in at about 3kV/cm, which in consideration of the depletion width at zero bias for the N" implant of table 2.1 holds for applied voltages above about 0.03. As such the value of A** is taken as 144 A/cm2/K2 [3.1]. The Schottky diode barrier transit time(TT) for SPICE is approximated as W0/2i>s, where i>s=MnEs and Es is taken as 3200 V/cm and Mn is adjusted for doping level. 32 The parasitic series resistance (RpS) per unit width of the diode determines the total width required for the amplifier diode stack, neglecting substrate shunt resistance. As can be seen from the cross sections in figure 3.1 RpS=Rc+R^+Rs, where Rc is the contact resistance, R^ is due to the gap and Rs is the average resistance under the depletion region. Rs is calculated after Kellner, Enders, Ristaw and Kniepkamp[3.2] via equation 3-2. Rs~3^Rsht [3-2] Where Rsht *-s taken as the sheet resistance of the implant under the Schottky metal. R^ is taken as the sheet resistance between the ohmic and Schottky barrier contacts. Rc is calculated after Berger[3.3] for a *\nm strip as Rc=i/[RCV(RSS) ] where Rcv is pc ^(contact area) and Rss is Rsht2(length)/(width). The total series resistance due to the RpS per unit width for the diode type is divided by the area factor taken as width included in the amplifier diode specifications in Appendix B. A default value for the Schottky to ohmic metal spacing of 4jum is used for both diode types. Velocity saturation is achieved in the gap at approximately 1.2 V across the gap, or 2 V across the diode, or about 1.7 V for a 3Mm gap. Both are adequate however the 4Mm gap being more reliable with respect to process yield[3.4]. Only the diode stack number 33 and width is changed to match the diode stack to amplifier circuit requirements. Diodes were model characterized per unit width for standard gaps of 3 and 4 Mm and Schottky metal length of 3 Mm from alignment and capacitance considerat ions. SPICE model Schottky diode trailing numbers are Lgap. SPICE input deck format specifies RS as RpS in the following diode models. .MODEL RD4 D(IS=0.31E—12, RS=3206, N=1.18, TT=0.45PS, + CJO=3.85E-15, VJ=0.72, EG=1.42, BV=8, IBV=1E~3) .MODEL TD4 D(IS=0.31E-12, RS=1744, N=1.1, TT=0.59PS, + CJO=8.02E-15, VJ=0.72, EG=1.42, BV=8, IBV=1E~3) The cutoff frequency ( f c= 1/( 27rRpsC j) ) is about 8.8 and 11.1 GHz for the TD and RD types, respectively, with a bias of 0 V. Equation 3-3 gives the diode I-V characteristic with the effect of RpS. V = IRps + (nkT/q)ln(l/ls + 1) [3-3] Using data in Table 2.1 and referring to Figure 3.1 the parameters for a iMm wide diode slice were constructed for the two types and used for amplifier stack layout calculations in section 6. Ideality factor n is taken as 1.18 for RSAG and 1.1 for SI. Schottky interface problems were assumed negligible for the layout calculations however can be determined from the FAT FETs and accounted for later in simulations[3.5]. 4. MESFET PARAMETER EXTRACTION AND LAYOUT The major limitations to MESFET fabrication using mask contact optical lithography are minimum linewidth and worst case alignment. 4.1 ALIGNMENT LIMITATIONS Factors that dominate layout are interlayer alignment skew and minimum linewidth and line to gap ratio of mask lithography provided by the plate manufacturer. The line width limit of the current mask is 1/xm and the line to gap ratio was fixed at 1:2 for mask production cost, fabrication and alignment reasons. If the mask set has a tolerance of 8j (±0.1«xm) [4.1] lateral position within and ±0.4/xm (6L) between layers and the alignment can be manually made to ±0.5Mm (6A) under optimal conditions[4.2], a minimum spacing of $j+SL+SA must be allotted to avoid contact. A further margin must be allowed for lateral movement during alloying (8LA) with the total error times a safety factor (S) to account for the optimistic alignment assumption, as it is a time consuming manual operation and some misalignment may occur during the vacuum transfer phase of the exposure operation. S(6I+8L+ 6A+ 6LA) = MINIMUM SEPARATION [4-1] Taking 6LA as 0.3/um and S as 1.5 gives about 2(im minimum separation between layers, or more conservatively 2.6/xm with 34 35 S as 2. Minimum separation within a layer can be reduced by the compounding effect of interlayer mask skew and lateral spreading resulting in a minimum separation of less than "Idem. However previous experience at U.B.C. has shown that a 1iim intergate gap on a multiple gate RSAG MESFET causes liftoff problems in step 19 of section 2.1.1, asymmetric plasma undercutting in step 20[4.3] and is highly demanding of the current plate manufacturing process[4.1]. 4.1.1 INTERLAYER ALIGNMENT MARKS To maximize alignment accuracy a set of alignment marks shown in figure 4.1 were developed. As the mask aligner is capable of lateral movement at a magnification of 160X corresponding to a mask to wafer gap of 20xtm, then an alignment checking operation with the mask and wafer at a 3 Mm gap or under vacuum assisted direct contact, three levels of alignment mark are necessary. The first mark must allow the operator to align wafer to mask orientation easily, for which a simple stacked structure will suffice(corner brackets in fig. 4.1). The second mark should allow maximum alignment accuracy at 160X magnification at which the smallest visible feature is 1.5Mm in a field of approximately 200 by 200Mm. The proposed 0.5Mm alignment accuracy of the process can only be obtained under these conditions by taking advantage of the symmetry detection capability of the operator by balancing light and dark 36 Fig. 4.1 Alignment Marks fields[4.2] of greater than 1.5/im. As such 3 and 4Mm were taken as a 2nd level gaps. The third level mark should be able to take advantage of the 320X objective capability of detecting a 0.75Mm minimum feature[4.2] to check the second mark alignment under direct contact through a 1 to 2Mm photoresist layer with a depth of field of 3Mm and a frame of less than 100mn.The inner cross has a 1 or 2Mm gap to compensate the possible interference due to the photoresist, resulting in the multiple patterns for each layer. In order to accommodate the demands of aligning to the original alignment etch, thus to avoid any error t accumulation between layers, and check metal to metal alignment, separate alignment marks were used, including metal overlays of previous metal depositions. The fact that with positive photoresist the exposed area through the clear portion of the mask is subsequently developed away means that to obtain the light field symmetry for second level alignment the clear area must surround the periphery of the etch line by 4Mm. Third level alignment can be accomplished by a internal etch periphery with a dark mask field 1/xm inside it. 4.2 RSAG AND SELECTIVE IMPLANT PROCESS PARAMETER DIFFERENCES As is apparent from figure 4.2, RSAG devices made with the same level of lithography as SI devices should have superior performance due to reduced gate length and source/drain parasitic resistance. Equally apparent though is the fact that RSAG process gate resistance is much higher leading to a loss of some of the gained benefit with respect to the SI process. 4.2.1 SOURCE AND DRAIN RESISTANCE Source and drain resistances are minimized to minimize the channel transit time(T) and increase IDs at a given VDg. Referring to Fig. 4.2 it can be seen that Rs and RD have several series contributions. The 38 Fig. 4.2 Cross Section of MESFETs trailing model numbers(ie. RSAG1_2) correspond to mask LG and Lgap. The gap resistance RSgap or RDgap is calculated by using the applicable Rgheet tin163 t^e number of squares in the gap, allowing for lateral diffusion during anneal in the RSAG case. This does not allow for alignment variations. Ohmic contact resistance is calculated after Berger[3.3]. For the purposes of compaction and layout regularity for a large number of circuit variations a 39 standard contact length of 20iim was selected, however some layouts are adjusted slightly. 4.2.2 GATE PHASE SHIFT A "well designed FET", with respect to gate series resistance, has gate metal evaporation onto thick double layer photoresist for lithographic accuracy with reliable liftoff of unwanted metal from a thick deposition[2.4]. Typical layers are 300 nm of TiW topped by 0.7 (tn Au producing a "mushroom gate" profile. The thick gold layer is necessary to decrease Rg per unit width at high frequency, minimizing gain degradation due to transmission line and skin effects[4.4-4.8]. The current gain of a MESFET depends on a uniform voltage acting along the channeKz axis). If a phase shift of the control signal occurs along the width of the gate, the source to drain flow of electrons through the channel varies with Z. This effect is a result of phase shift due to the transmission line character of the gate. A second metal layer for the TiW RSAG gate has been attempted by Sadler[2.2] to make up for the discrepancy apparent in table 4.1, leaving Al, Ni, Au, and Pt t-gate tops in place during annealing. The result was "drastic interdiffusion and alloying ... between the top metal and the GaAs". With this in mind we considered post anneal processing as the only viable refractory gate 40 stripe resistance reduction strategy. Metal Bulk Thin Film Estimate Units Al Au Ti W Ti0.3w0.7 2.56 2.44 41.00 5.60 16.22 5.12 4.88 82.00 11.20 74.61* jifl-cm MO-cm MO-cm Mfl-cm Mfi-cm Table 4.1 Thin film resistivity.(* from [2.2]) A post anneal gate gold plating process was conjectured. An extra fabrication step would be added where a temporary interconnect web would provide plating current to the gates. This would cause electrolytic plating action at exposed areas, but would require precisely aligned mask windows to prevent unwanted plating. After plating the PR would be removed and a circuit shielding mask used to etch the plating current distribution grid. The main problem with this plan is plating mask alignment and minimum line width. Alignment skew of 1.6/im is expected, and the mask minimum line width of 1um is inadequate for 0.5/xm RSAG gate lengths. It has been demonstrated by Wolf[4.3] that the effect of gate metalization resistance is proportional to b?, where b is the gate width. As such the design philosophy of this project has been to maximize TiW thickness and the gate width with respect to the maximum 41 frequency or pulse response required of the MESFET. Separate considerations are included for the switch of section 5 and the amplifier of section 6. 4.3 MESFET CAPACITANCE Capacitance due to the depletion layer(CGg and CGD varies with the specific two dimensional geometry of the depletion region, which is dependent on VGg and VDg. CDg is considered to be relatively independent of the depletion region and as such is treated as a constant. The SPICE 2[4.4] MESFET model proposed by Curtice[4.5] and realized by Sussman-Fort[4.6] models CGg as variable and treats CGD as constant. Several other models have been published some of which are included in the references[4.7-4.11]. In the course of modeling ICDL and other logics(partial inclusion in appendix A) with the SPICE 2 MESFET model Abdel-Moteleb, Rutherford and Young[4.17] included a variable CGD for some of the simulation runs. The MESFET circuit model with an added shunt resistor, due to substrate conduction, appears in figure 4.3. A more accurate capacitance model has been proposed by Golid, Hauser and Blakey[4.13] of which the CGD portion has been included in a version of SPICE 2 (re: appendix B). 42 GATE RG CGS RS fFl I | CGD SOURCE• CDS II RSHUNT RD DRAIN MESFET CIRCUIT MODEL UITH SHUNT RESISTOR Fig. 4.3 MESFET circuit model 4.4 MESFET 1<xM SLICE PARAMETERS From the process definition and parameter estimation procedures nine MESFET SPICE models are maintained for circuit evaluation. Figure 4.4 a) represents a typical industry standard MESFET configuration which is used as a process benchmark for comparison of our variations to each other and MESFETs currently being produced by several manufacturers. Figure 4.4 b) has a 1um dot grid superimposed on the magnified layout of the gate connect, as compared to the 100Mm dot grid of figure 4.4 a). DC characteristics are accumulated from the 100/zm test MESFET or 236 w-gate array of figure 1.2 with the use of a semiconductor parameter analyzer. 43 Fig. 4.4 a) 7r-Gate Layout The simulated I-V characteristics are displayed for 100iim widths in figures 4.5 to 4.7 for the nine variations. In the SPICE models below all width dependent constants are per nm. SPICE GGSO and CGD are calculated at VGS and VDS = 0 V from the normal space charge equation 4-2. Comparing the measured results of Van Tuyl and Liechti[4.14] 44 Fig. 4.4 b) ff-Gate Magnified CSc is approximately equal to CGS until the MESFET is biased near VQC*=0.5 V where the measured CGg is about 0.68CSG. From symmetry CGD is equal to CGS under these conditions. The SPICE simulation then proceeds to modify the initial values according to equations 4-3[4.5] and 4-4[4.13]. Csc=LZ[q£N(x) /2(VBI - VGS - VFCH)]* [4-2] cGs(vgs)s= CGS0/[1-VGS/VBI]* [4-3] cGD<vgs'Vds>= CGD0/£ T-^GDlVgs-Vds^^GD^G5 3 (1-XGD2vgs) [4-4] 45 RSAG1_4 TEST MESFET Fig 4.5 RSAG 0.5Mm I-V characteri sties RSAG2_2 TEST MESFET 2.4 la RSAG2_3 TEST MESFET RSAG2_4 TEST MESFET 4.6 RSAG lMm I-V characteristics SI1_3 TEST MESFET SI1_4 TEST MESFET Fig. 4.7 SI 1um I-V characteristics 48 The constants for equation 4-4 are listed in Appendix C as part of the GASFET subroutine source code. Ids is empirically fitted with equation [4-5] after Curtice[4.5]. Ids=/5(Vgs+VT)i • (1+XVds)tanh(oVds) [4-5] Where X is the channel length modulation factor and a is the hyperbolic tangent function parameter, o is used to fit the linear region and X the slope of the saturation region. The transconductance parameter /J=Ip/Vp* and VT are generally determined by plotting /IJJS VS« VGS anc* accounting for Rg and RD. If devices are not available j8 can be approximated theoretically after Chen and Shur[4.15]. 0=[2eGaAsusw3/[A(vP+3EmL1)] [4_6] where A=[2eGaAsVp]/[qQa] [4-7] and L1=L-2^sinh-,{[TKd(Vds-Vis)]/[2AEs]} [4-8] and the voltage drop across the channel at saturation is: Vis= [EsL(Vgs-VT)]/[EsL+Vgs-VT] [4-9] Kd is approximately 1 for self aligned gates and Kd=AV/(Vds-Vis) for SI gates where AV is the "voltage drop across part of the high field domain under the gate". When 49 VGS = VBI the maximum VIS = (ESLVPQ/(ESL+VPQ) and increase in I^g due to channel shortening is negligible for vcls>v"is + 2 volts at this point, /? can be considered independent [4. 10 ] of VDS >> Vis+2 at VGS=VBI. QA is taken as the implant activation times the N~ dose for the purposes of initial approximation. The following models are the result of layout and process calculations. .MODEL RSAG1_2 GASFET(VTO=-2, VBI=1.23, RG=4.97, ALPHA=2.3, + BETA=3.1E-5, LAMBDA=0.055, CGS0=0.595FF, CGD=0.595FF, + CDS=0.0791FF, IS=2.07E-15, RD=1170, RS=1170, + TAU=0.71PS) .MODEL RSAG1_3 GASFET(VTO=-2, VBI=1.23, RG=4.97, ALPHA=2.3, + BETA=3.1E-5, LAMBDA=0.055, CGS0=0.595FF, CGD=0.595FF, + CDS=0.0738FF, IS=2.07E-15, RD=1490, RS=1490, + TAU=0.71PS) .MODEL RSAG1_4 GASFET(VTO=-2, VBI=1.23, RG=4.97, ALPHA=2.3, + BETA=3.1E-5, LAMBDA=0.055, CGS0 = 0.595FF, CGD=0.595FF, + CDS=0.0714FF, IS=2.07E-15, RD=1810, RS=1810, + TAU=0.71PS) .MODEL RSAG2_2 GASFET(VTO=~2, VBI=1.23, RG=1.49, ALPHA=2.3, + BETA=2.61E-5, LAMBDA=0.055, CGS0=1.19FF, CGD=1.19FF, + CDS=0.096FF, IS=4.13E-15, RD=1555, RS=1555, TAU=2.86PS) .MODEL RSAG2_3 GASFET(VTO=~2, VBI=1.23, RG=1.49, ALPHA=2.3, + BETA=2.61E-5, LAMBDA=0.055, CGS0=1.19FF, CGD=1.19FF, + CDS=0.0947FF, IS=4.13E-15, RD=1875, RS=1875, TAU=2.86PS) .MODEL RSAG2_4 GASFET(VTO=-2, VBI=1.23, RG=1.49, ALPHA=2.3, + BETA=2.61E~5, LAMBDA=0.055, CGS0=1.19FF, CGD=1.19FF, + CDS=0.0791FF, IS=4.13E~15, RD=2195, RS=2195, TAU=2.86PS) .MODEL SI1_2 GASFET(VTO=-2, VBI=1.23, RG=0.13, ALPHA=2.3, + BETA=2.61E~5, LAMBDA=0.055, CGS0=1.19FF, CGD=1.19FF, + CDS=0.096FF, IS=4.13E-15, RD=3228, RS=3228, TAU=2.86PS) .MODEL SI1_3 GASFET(VTO=-2, VBI=1.23, RG=0.13, ALPHA=2.3, + BETA=2.61E-5, LAMBDA=0.055, CGS0=1.19FF, CGD=1.19FF, + CDS=0.0847FF, IS=4.13E-15, RD=4770, RS=4770, TAU=2.86PS) .MODEL SI1_4 GASFET(VTO=-2, VBI=1.23, RG=0.13, ALPHA=2.3, + BETA=2.61E"5, LAMBDA=0.055, CGS0=1.19FF, CGD=1.19FF, + CDS=0.0791FF, IS=4.13E-15, RD=6312, RS=6312, 50 + TAU=2.86PS) Vfai is taken as 0.5 V + 0Bn after Curtice[4.5] allowing for a voltage drop across r^ in the conduction channel under the gate. The transit time under the gate TAU is used in the model to include the delayed effect of a change in VgS on Ijjg. In the Curtice[4.5] model it is a constant. TAU is taken at V^s - 1 V, using a conservative average low field mobility of 3500 cm2/V-s, across the effective channel length. This value is then modified during program execution in a prototype SPICE version by dividing TAU by V^g+k, where k is to prevent division by zero, to produce an effective transit time. 5. SWITCH CONSIDERATIONS AND LAYOUT Figure 5.1 a) is the layout for a triple gate RSAG1_2 switch with a 100/zin dot grid and figure 5.1 b) is a magnified view of the gate region. Assuming the existence of a ground plane a distance d under the metalization, circuit Fig. 5.1 a) Triple Gate Switch Layout 51 52 Fig. 5.1 b) Magnified Triple Gate Switch parasitics can be calculated after Van Tuyl, Liechti, Lee and Gowen[5.1]. Switch sampling performance involves the combined effect of pulse edge propagation and reflection in the gate and channel reaction. In a pulse modulated short channel MESFET transient behavior can be simulated by a two dimensional mesh model in fractions of a picosecond such as performed by Faricelli, Fig. 5.3 Triple Gate Switch Distributed Model 54 Frey and Krusius[5.2] with respect to digital logic. 5.1 THE SAMPLING CYCLE In a sampling cycle the switch is initially held at or below pinchoff by the sampling pulse transmission line bias. The rising edge of the pulse ramps from VT to Vj^-AV, where AV is to prevent forward conduction, in tr. The voltage ramp propagates down the gate transmission line and reflects off the unterminated end. In the channel the positive gate pulse causes fields to withdraw from the active layer, drawing majority carriers from the source and drain towards the gate, increasing CGS and CGD. The transverse field profile due to VDS in combination with the altering depletion boundary accelerates mobile charge in the channel from source to drain moving charge from or to the hold node depending on the magnitude of vhold vs- vin-After 25ps the down ramp propagates down and reflects from the unterminated gate end causing fields to penetrate the active layer. The majority carriers move down the potential gradient to the source and drain, decreasing CGS and CGD and reversing the source current of the previous state. The rapid displacement of charge from the channel to the source and drain areas likely causes most of the observed voltage change which is referred to as "sample strobe blow-by" by Barta and Rode[1.2]. Ideally the magnitude of the "strobe feedthrough" to the output of the sample and hold would be negligible. The bandwidth of the amplifier should be maximized for minimization of the number of ISAB units[1.1]. Thus the strobe feedthrough should be minimized at the switch. RSAG1_2 Pulse Gate End -0-2 Fig. 5.4 Single Gate Distributed Simulation } 5.2 GUARD AND SAMPLING GATE BIASING CONSIDERATIONS 56 The operation of the switch with respect to sample and hold is such that, when the switch is on, VDg tends to zero while bringing the hold capacitance to a potential near the source potential. When the switch is off the source is free to follow excursions which do not inadvertently bias the switch on with the charged hold capacitance supplying a voltage to the amplifier input MESFET. The hold charge leakage paths include MIM or ID capacitor leakage, switch shunt leakage, amplifier input leakage and substrate shunt leakage. The amplifier input bias should be such that the output bias is very close so as to enable cascade operation for several stages. Amplifier input bias is in the order of 0.3VT, varying with the specific amplifier component characteristics. Amplifier gain and output swing limit the input swing such that V^oia should vary by about 200mV about the symmetry bias point. The guard gate bias should be such that charging current is maximized without causing gate forward conduction, about 500 mV above the most negative input signal excursion. 5.3 HOLD CAPACITANCE CONSIDERATIONS The optimum magnitude of the hold capacitance is determined by the rate of charging for the aperture available. The guideline aperture is the highest priority aspect of the design. Amplifier input capacitance is mainly CgS of the input MESFET plus a small parasitic contribution and as such 57 is a function of VgS. Reduction of potential distortion can be accomplished by increasing the ratio of fixed capacitance to variable capacitance. Fixed capacitance is from two sources, parasitic or layout dependent and MIM or interdigitated structures. The estimated node capacitance for the Barta and Rode ISAB is 0.3pF of which half is MIM and the other a combination of parasitic and depletion layer. The amplifier input width is 50mn implying CgGg of about 60fF combined with the node side guard gate width of 100/im amounting to CSrjo~12OfF, with the node at zero volts. Parasitic capacitance originates with the layout separations, substrate thickness and dielectric constant. If the ISAB is mounted on a sheet of conducting epoxy at ground potential the surface metalizations form a MIM capacitor. Substrate thickness is about 450mn leading to an approximate capacitance per unit area of eGaAs/d=*25, 700f F/cm2. For a 100Mm2 pad this amounts to about 2.6fF. This would increase for a thinned substrate design incorporating the entire DRFM acquisition unit including microstrip delay line. The rate of charging for a single gate switch at VDS is determined by switch characteristics and VGS. A multiple gate switch has a lower charging rate due to the added guard channels in series. Barta and Rode[1.2] claim that in a three gate switch "the outside gates serve a shielding function by minimizing the effects of sample strobe blow-by reflected back into the input source and coupled onto the output signal." 58 Comparative lumped element modeling of this configuration with equivalent input time constant single and dual gate configurations is shown in section 7 simulations. The switch slice parameters are accumulated in table 5.1. Figure 5.2 is the equivalent circuit of a triple gate switch slice connected to the amplifier input FET with a fixed capacitance(Cf). The distributed model of the switch incorporates the switch as a set of n slice elements connected to simulate the layout of figure 5.1 as demonstrated in figure 5.3 for n=3. Notts ICSrTT ID CS50 11) Rc (2) Rs (3) RH (4) TMJ (5) RSAG if OhM onus ones usee 1 6ate to Source Caoacitance it Vgs=0 V 61 1 1 2 0.59. 144.2 1169.7 705.5 0.71 Contact Resistance S 1 1 2 0.59 0.0 705.5 705.5 0.71 62 1 : 2 0.59 IM.: 705.5 1169.7 0.71 3 Source resistance SI 1 2 2 1.17 144.2 1555.2 1091.0 2.86 S i 2 2 1.17 0.0 1091.C 1091.0 2.86 4 Drain resistance 62 1 2 2 1.17 144.2 1091.0 1555.2 2.86 J CTTtiuv. uiannei Langin/Miuf align veigtiiy TiiAu Selective laciint NESFETJ 31 1 1 2 1.17 144.2 3226.2 1542.0 2.36 S 1 ! 1.17 0.0 1542.0 1542.0 2.86 S2 1 1 2 1.17 144.2 1542.0 3228.2 2.B6 Mtl R1.261 RI 2S R 1.252 R2.2S1 R2.2S R2.2S2 S1.261 S1.2S S1.262 UNITS 0.5 0.5 0.5 1 1 1 1 1 1 ut S/D Sao 2 2 2 2 2 2 2 2 2 ue VTO .? -2 -2 -2 -2 -2 -2 -2 V VB! 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 V RE 4.97 4.97 4.97 1.49 1.49 1.49 0.13 0.128 0.128 onus ALPHA 2.J 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 SETA 3.055M5 3.055EK.3 3.055E-05 2.615E-05 2.615E-05 2.615E-05 2.6I5E-05 2.615E-05 2.615E-05 A/V-2 'JWDA 0.055 0.055 0.055 0.055 0.055 0.055 0.055 0.055 0.055 CSSO 0.586 0.586 •}.586 1.173 1.173 1.173 1.190 1.190 < 1.190 fF CSD 0.566 0.5B6 0.536 1.173 1.173 1.173 1.190 1.190 1.190 fF CDS 0.0791 0.0736 0.0714 0.096 0.0847 0.0791 0.096 0.0B47 0.0791 fF IS 2.07E-O5 2.V7E-05 2.07E-O5 4.13E-05 4.13E-05 4.13E-05 4.13E-05 4.13E-05 4.13E-05 A RS 1169.7 705.3 705.5 1555.2 1091.0 1091.0 3228.2 1542.0 1542.0 ohn RD 705.5 705.5 1169.7 1091.0 1091.0 1555.2 1542.0 1542.0 3228.2 ohm m 0.71 0.7: 0.71 . 2.86 2.86 2.86 2.86 2.96 2.86 os Table 5.1 MESFET Parameters for sampling switches. 6. AMPLIFIER LAYOUT The amplifier equivalent circuit of figure 6.1 is realized with the layout of figure 6.2. The relative feedback MESFET width was taken as 25% of BPU after Van Tuyl [2.4] giving about 3dB gain. In the layout BPU is the MESFET most affected by gate metalization resistance, as it is not driven at both ends. For the SPICE transient simulations RQ is taken as 1/3 the end to end metalization resistance after Wolf[4.3] for an end driven gate and 1/2 of that for both ends driven. •*|rBPu BLPU rt y »> y »e u u GNO VSS Fig. 6.1 Amplifier Equivalent Circuit. 59 60 Fig. 6.2 Amplifier Layout The -3dB frequency of the amplifier is determined by pole interaction treated by Hornbuckle and Van Tuyl[1.7], Step response settling time is a more suitable performance measure for sampling. The input step of the simulations is a 0.1ps transition carried out about the amplifier symmetry bias point. The step amplitude is chosen to reflect the maximum excursions of the hold node with respect to keeping the amplifier output linear. AORT3_9012 DC Characteristics 3 -. 4 3 2 O -1 •2 I i 1 1 1 i—i 1 i i 1 1 -1.2 -1 -0.8 -0.6 -0.4 -0.2 O vm (v) . 6.3 Amplifier Open Loop DC Characteristics A0RT3_9012 Transient Fig. 6.4 AORT3_9012 Open Loop Transient AFRT3_9012 DC Characteristics VH (V) 6.5 90tim RSAG1_2 Amplifier DC Characteristics AFRT3_9012 Transient 2.3 > 0.5 -0.5 4 S (Tbn« 10E-10) Tim* (*) g. 6.6 90/xm RSAG1_2 Amplifier Step Response 63 AFRT3_9022 DC Characteristics Fig. 6.7 90<xm RSAG2_2 Amplifier DC Characteristics Fig. 6.8 90Mm RSAG2_2 Amplifier Step Response 64 AFST3_9012 DC Characteristics -1.2 -1 -0.8 -0.6 -0.4 -OJ 0 Vh (V) Fig. 6.9 90iim S11_2 Amplifier DC Characteristics AFST3_9012 Transient 3.3 _ 1.5 -> 1 -0.5 -O -• -1-3 -i—i—i—i—i—r—i—i—i—i—i—i—I—i—i—i—r—i—i—i— 0 0.2 0.4. 0.6 0.8 1 1.2 1.4 1.6 1.8 2 (TVnw 10E-9) Hm« (•) Fig. 6.10 90mn SI1_2 Amplifier Step Response 65 The Schottky diode stack number and width were chosen to maintain about a 1 V per diode voltage drop for a given supply voltage difference, scaled with VT, and total RpS to balance the output and input voltages. As the input voltage swing is biased near the center of the input MESFET operating characteristic the output voltage must coincide to give cascade capability. The amplifier transient and DC characteristics are shown in figures 6.4 through 6.10 for the tightest lithographic tolerances of the three major performance groups. The fastest settling time is less than 200ps for RSAG1_2 technology. Amplifier variations were generated for 30 to 120ixm maximum MESFET width range, with 2, 3 and 4 diode stacks of both RD and TD type for the nine MESFET parameter sets. The role of the amplifier in this project was to demonstrate minimum settling time for the DRFM application, while providing a suitable adjunct for the switch. Variable hold capacitance increases with input width, output drive decreases with width and phase shift degradation of transient performance increases with width. The 67iim input width has a Campin of about 20fF for RSAG1_N and 40fF for the other processes at the required input bias. The combination of guard gate capacitance with Camp^n results in the approximate minimum capacitance for input time constant calculations for dual and triple gate switches. 7. ISAB DESIGN AND LAYOUTS 7.1 CONFIGURATIONS The possible configurations include single, dual and triple gate switches of various widths in each of the nine MESFET variations, combined with an amplifier in the same or other process variation. A representative group of 28 ISAB configurations were included on the mask with a subset of 21 separate switches and 12 amplifiers(re: Fig. 1.3). Seven SI process ISABs are included without separated components, as on chip priority was given to RSAG units in terms of research interest. The SI units encompass 140um center tap single, dual and triple gate switches in both 2 Fig. 7.1 SI and RSAG ISAB layout 66 67 s Iterate**} m a- P Fig. 7.2 MIM ISAB layout and 3/xm source/drain gap variations with 90um amplifiers in the same variation plus one single gate 4*xm gap ISAB. The ISAB layout on the left of figure 7.1 is the triple gate 2/im gap version, of which a full page layout is included in appendix B. The minimum input time constant for a given switch is obtained by eliminating all fixed hold capacitance, as seen in equation 7-1. chold = cfixed+campin+cguard+cswitch+cparasitic guai [7-1] 68 The switch contribution is a combination of CDs and CGD assuming the hold node is the switch drain side. As guard gates are added the resulting decrease of node charging current makes interdigitated capacitors a more attractive process option due to the process yield considerations of MIM shorts. 7.2 ISAB SIMULATION RESULTS Taking the theoretically derived SPICE model parameters from table 4.1 a representative selection of large signal simulations were performed. These include simulations of expected pulse and transient conditions indicative of intrinsic performance with ideal input conditions. The overall performance of actual devices will depend on actual inputs and associated parasitics as well as the intrinsic performance highlighted here. The SPICE MESFET model version used has fixed CQD with a value the same as CGSQ. More accurate capacitance modeling can be done at the expense of increased simulation time. Circuit parameters for the SPICE source listings for the simulations are in appendix D. Figures 7.3 to 7.5 show the simulated open switch tracking of the three tightest tolerance RSAG ISABs with a 1GHz sine wave input. As the number of guard gates are increased fixed node capacitance is decreased to compensate, however as can be seen in figures 7.3 to 7.5 significant hold node attenuation and phase shift occurs. Fig. 7.3 RSAG1_2 Single Gate ISAB Tracking Fig. 7.4 RSAG1_2 Dual Gate ISAB Tracking 70 RI36R912T3 Tracking -OJ -| Fig. 7.5 RSAG1_2 Triple Gate ISAB Tracking RI16R912T3 Time Constant T 1—1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I OJ 0.4 O.S 0.8 1 1.2 1.4 1.8 1.8 (Hmm 10C-10) Tim* (•) W •*•*> input — Fig. 7.6 RSAG1_2 Single Gate Time Constant RI26R912T3 Time Constant i—r-i—i i i—i—i—i—i—i—i—• i i 0.2 0.4 0.6 0.S 1 1.2 1-4 1.6 (1)nt« 10C-10) Tim* (•) -7^- W atop input Fig. 7.7 RSAG1_2 Dual Gate Time Constant RI36R912T3 Time Constant -0.33-1 -0.85 A—i—i—r—i—i—i—i—r—i—i—r—T—I—i—i—i—i—i—i— 0 CJ. 0.4 0.6 03 1 1.2 1.4 1.6 13 2 (Tim** 10E-10) Tim* (•) RT atop kiput -j- Mold nod* Fig. 7.8 RSAG1_2 Triple Gate Time Constant 72 Figures 7.6 to 7.8 use the same circuit model as figures 7.3 to 7.5 with a 0.1ps step input of the same magnitude. The input time constant increases with the number of gates from about 40ps for 90% sampling efficiency with a single gate switch to about 52ps and 71ps for dual and triple gate switches. Figure 7.9 shows the simulated distortion of an ideal 50S2 transmission line pulse on the gate pad due to a single gold bond wire and variable capacitance of the gate. Figures 7.10 through 7.12 show the effect of guard gates on pulse feedthrough at both the RF input side and hold node side. The hold node voltage changes to a more negative value on switch closure due to channel majority carrier distribution across capacitances. Initially the single gate switch of Pulse Distortion Tim* (•} -j— Transmission In* —g- Cat* pad Fig. 7.9 Pad Pulse Distortion 73 RI16R912T3 Feedthrough (Hm« IOC-11) v _ 1km (•) CotoPulM -j,- UT Pod Hold nod* Fig. 7.10 Single Gate Feedthrough RI26R912T3 Feedthrough 0.4 Fig. 7.11 Dual Gate Feedthrough 74 RI36R912T3 Feedthrough > -3 0 4 Cote "ukM -j- Hotd nod* Fig. 7.12 Triple Gate Feedthrough figure 7.10 is open with source and drain at the same potential as the 152fF fixed capacitor. When the switch ramps closed in 5ps both source and drain receive an injection of majority carrier causing a negative voltage swing. The lack of availability of neutralizing charge for the hold node produces a stored negative offset of about 0.4V inversely proportional to the node capacitance. The RF input side is neutralized returning to its original potential in about 20ps. On switch opening majority carriers are pulled into the channel leaving a temporary lack at source and drain, increasing voltage. The resultant transient decays in approximately the same time as for switch closure, about 20ps. 75 The dual gate switch of figure 7.11 has a single guard gate on the hold node side with a 39fF fixed capacitor. The hold node stored negative offset of figure 7.11 is reduced in the presence of the guard gate to about one half the single gate magnitude of figure 7.10. The post switch opening transient is about 100mV larger requiring a longer settling time. The guard gate CGS0 is about 36fF, and VGS is 0.3 V at the amplifier symmetry point giving a CGS of about 41fF from equation 4-3. Thus the combined distributed capacitance for the initial phase of the dual gate simulation is about 116fF+Csw^tch+<-ampin as compared to 152fF+Csw^tcj1+Campin for the single gate. As charge is transfered to the hold node during the switch down ramp guard gate CGS increases responding to the change in potential to about 47fF. The displaced charge can be considered to be held on two nodes, the switch guard gate node and the hold node separated by the guard gate channel. The approximate simulated capacitance of the switch guard gate node is Csw£tch+c-GSguard ano- that of the hold node campin+cfixed+cGDguard- The charge holding ability of the various capacitances is directly proportional to the voltage across the capacitance. When the strobe down ramp levels off the switch gate is at -2.9V such that about -2.1V is across cswitch* cGSguard and cGDguard have about +0-5 volts across them and Cfixe(j and Camp^n are about +0.8 V. The distributed capacitance of the two nodes thus holds less charge than the single node of the single switch ISAB. The "blow-by" 76 displacement charge is the same however, thus some of the channel charge is being neutralized by another source of carriers. The most obvious path for these carriers is from the bias supply through the guard gate Schottky diode. Figure 7.13 shows the voltage at the guard node between the switch and the guard gate for a dual gate switch, with the same transient conditions as figure 7.11. The guard node voltage drops suddenly in response to electrons being injected from the switch. The voltage from gate to source of the guard gate reaches about 0.9 V, causing electrons to tunnel through the Schottky barrier. Figure 7.14 shows the guard gate current increase in the positive going pulse, corresponding to the strobe down ramp. The negative going current pulse is mainly due to capacitive coupling, and as RI26R912T3 Guard Gate Source and Drain 0.3 -, 1 0.2-I (TbriM 10E-11) Tim* (•) ^ guard nod* ^ hold nod* Fig. 7.13 Guard Gate Source and Drain Voltages 77 RI26R912T3 Guard Gate Current (TWIM tOE-11) Tlm» (•) Fig. 7.14 Guard Gate Current such is missing the conduction effect. The triple gate switch of figure 7.12 exhibits a reduced RF pad transient due to its guard gate and a larger hold node swing than either the single or dual gate switch. The reason for the increased hold node swing is reduced hold node capacitance in an attempt to improve the input time constant. The hold node capacitance is thus mainly composed of guard gate and amplifier input depletion capacitance which varies with hold node voltage. Unfortunately the triple gate switch is both slower in terms of input time constant and as a result of minimal fixed capacitance at the hold node not as good in terms of hold node feedthrough. While the single gate switch is predictably the fastest in terms of input time constant the dual gate exhibits about 78 one half the feedthrough, at the amplifier input bias voltage, with a 30% time constant increase. Figures 7.15 to 7.20 show sampled tracking conditions similar to those of Barta and Rode[1.3] using a 36MHz sine wave input, however the strobe pulses are at 1 rather than 2ns intervals as suggested by the research sponsor. The strobe pulse rise time is taken as 20% of the strobe "ON" width for all the simulations. Figure 7.15 shows sampled tracking if the RF pad input bias is at the same level as the unsampled tracking of figure 7.3. Due to the stored negative offset at the hold node after switch closure the amplifier input is biased about 200mV below its symmetry transfer point. This can be corrected by changing the bias of the RF pad input by 200mV as seen in figure 7.16 resulting in a symmetrical amplifier output. Figure 7.18 shows that the single gate ISAB still tracks when operated below the 90% sampling efficiency aperture. The simulation resolution of figure 7.18 is 50ps and as such some of the hold node detail is lost. It should be noted that the amplifier acts as a low pass filter with respect to hold node transients and as such their output magnitude can be limited with minimal sample and hold signal degradation by choosing the amplifier frequency response appropriately. Figure 7.19 shows triple gate tracking with 300ps pulses. Signal divergence problems were encountered, where hold node voltage would consistently rise when using 79 Fig. 7.15 RI16R912T3 150ps Tracking, 0.6 V Bias Fig. 7.16 RI16R912T3 150ps Tracking, 0.4 V Bias Fig. 7.17 RI16R912T3 75ps Tracking 82 I I I I I I I I I III A Fig. 7.18 RI16R912T3 25ps Tracking 83 Fig. 7.19 RI36R912T3 300ps Tracking Fig. 7.20 RI26R912T3 50ps Tracking 85 narrower pulses. Figure 7.20 shows dual gate tracking at 50ps, close to the 90% sampling efficiency input time constant. Both figures 7.19 and 7.20 exhibit feedthrough compression on the negative swing of the input sine wave and a spreading effect on the positive going half cycle. This effect is not seen on the single gate tracking simulations of figures 7.16 to 7.18. The probable cause is hold node side guard gate bias with respect to the hold node voltage. The guard gate voltage is fixed such that any depletion region variation or gate conduction is caused by changing source or drain potentials. The depletion region capacitance will decrease as the source/drain potentials increase and vice versa. The amount of charge is being expelled from the switch by the action of the strobe is relatively constant. Greater capacitance is available at the hold node with more negative guard gate source/drain voltages thus the stored negative offset is less, however only slight change would be due to this as the capacitance change is only a few fF. The neutralizing charge injected by the hold side guard gate will depend on the initial bias of the hold node as this will determine the position of the negative transient on the voltage axis of figure 7.13. The more negative the peak the greater the amount of neutralizing charge passing through the guard gate Schottky diode under forward biased conditions. Thus feedthrough is less with lower hold node voltage. 86 The amplifier bandwidth is instrumental in determining the peak feedthrough voltage. Comparison of devices should thus be done on the basis of similar amplifier bandwidth. The amplifier bandwidth of Barta and Rode[1.3] is in the order of 1GHz whereas the RSAG1_2 amplifier bandwidth is in the order of 3GHz. The simulations were done with fixed CQD at CGgQ which is a reasonable approximation for VQD near 0 V and low VDS. More accurate capacitance simulation would be very unlikely to reduce the 200 to 800mV feedthrough transients of the simulations an order of magnitude to compare directly with the experimental 35mV feedthrough of Barta and Rode. The discrepancy would seem to be with the pulse parameters of the experimental setup compared to ideal pulses combined with transient response of the amplifier and measuring system compared to the simulated version. 8. PROCESS MONITORS AND MEASURED RESULTS The early verification of device characteristics enhances fabrication troubleshooting. Test probes can be used, as soon as AuGe ohmics are present, to verify implant activation and ideality factor. At the same time MESFET DC characteristics and metal sheet resistance can be checked. 8.1 ISOLATION MONITORS The isolation monitors (at coordinates G 1L, G 1R ,G 10, H 10 in figure 1.3) are ohmic pads on combined Nminus and Nplus implants separated by a gap to test the nonactivated substrate for retention of the semi-insulating sheet resistance of about 3-10*O/n in both crystal directions with respect to the major flat. Should this isolation be less for some reason it is possible to incorporate an isolation implant[8.1]. 8.2 TLMS The three transmission lines (L 5T, L 5B, L 10) measure the contact resistance of the AuGe ohmic pads to the three possible implant combinations for calibration of process anneal characteristics. The pad gaps are measured by SEM and the data analyzed by use of the transmission line model[8.2] for accurate results. 87 88 8.3 POWER MESFET The gate of an open drain power MESFET should be driven with the last amplifier output. A power MESFET requires airbridges for the interdigitated gate architecture. This architecture could be expanded to a dual gate configuration for output sampling to a time domain multiplexed transmission line. A single gate version power MESFET has been included on the mask for fabrication evaluation. [8.3]. 8.4 TIW SHEET RESISTANCE The stepped resistor pattern used to determine TiW sheet resistance is shown in figure 8.2. The actual segment widths can be measured by SEM and the resistivity calculated after [2.2]. Fig. 8.1 Power MESFET Gate Strip Layout 89 Fig. 8.2 TiW Stepped Resistor Layout \ 8.5 THREE AMPLIFIER OSCILLATOR Airbridges were used to construct a three amplifier ring oscillator to verify simulation. The RSAG1_3 MESFET was used as a base unit to increase the probability of all three amplifiers working. 8.6 PEAKING INDUCTOR The amplifier frequency response can be improved by adding a pole with a peaking inductor in series between the input and output stages.[1.8] r Fig. 8.4 Amplifier Peaking Inductor 91 8.7 SELECTIVE IMPLANT FABRICATION RUN RESULTS 8.7.1 ISOLATION The isolation monitors are two 150*im square pads on Nplus GaAs separated by a 15/um gap of SI GaAs. Figure 8.5 shows the current and resistance plots for a low voltage scan of the monitor on test chip 8. Considering the positive voltage side a diode characteristic appears with a series resistance in the order of 15k£2 implying a sheet resistance of 150kJ2/n. Figure 8.6 from chip 5 shows about 5MJJ series resistance corresponding to about 50MR/n of isolation which is an improvement over chip 8 however does not match the expected semi-insulating value of 300MJ2/n. Switch "OFF" isolation and hold mode I R (UA) (n ) 145.9 MARKER (- .6000V 1 . i . -2.B65UA . 209E+03 ) 232.0 E+03 14.59 /div .0000 23. 15 /div .4476 -2.000 0 .4000/div 2.000 V ( V) Fig. 8.5 Isolation monitor chip 8 92 MARKER {- .BOOOV .-7.517nA . 1Q6E+Q6 ) V .4000/div ( V) Fig. 8.6 Isolation monitor chip 5 leakage are the two most critical performance aspects of isolation. 8.7.2 DOPING AND MOBILITY PROFILES Using the fat FET at grid position K-1 of figure 1.3 on test chip 8 the doping and mobility profiles of figures 8.7 and 8.8 are obtained. The Nminus implant for this run was a dose of 3•1012 ions/cm2 at 125keV. The peak depth is about 103nm with an activated dose of 2.6-10<|2 ions/cm2 or about 87%. This is higher than the design simulation calculation assumption of 60% activation representing a 45% increase for the SI process, however annealing is performed at a lower temperature for the RSAG process which may result in Fig. 8.7 SI doping profile. 3831 tn \ > \ (M < £ u L L 3112 F-r 2334 P r 1556 p F ~1 H J j j -i M 778. 1 h § t t a t--779.1 .2 .3 DEPTH (MICRONS) .5 Fig. 8.8 SI mobility profile. 94 lower activation. Mobility is close to the assumed value of 3500 cm2/V-s. 8.7.3 SI MESFET CHARACTERISTICS The measured I-V characteristics of figures 8.9 and 8.10 are 236um width ir-gate MESFETs for which industry specifications are available. Three versions of this device are present on each chip, corresponding to source/drain gaps of 2, 3 and 4um. The published device IO (mA) CURSOR 31.13 3.113 /div .0001 .0000 3.2000V , 31.10mA . / I 1 fy r YDS .3500/div ( V) 3.500 GRA3 1/GRAD ••• Xintercept' Yintercept! LINE1 12.BE-03 78.3E+00 12.0E-03 : -154E-06 • i LINE2. 15.9E-06; 52 . 9E-rQ3, -1.95E+03 , 31.0E-03 \ Fig. 8.9 SF_236_1_4 7r-gate I-V characteristics, VT^-2.7V, lDSS"30mA 95 ID (RIA) 71.70 MARKER 7.168 /div .0228 .0000 VDS ,3000/div ( V) 3.000 Fig. 8.10 SF_236__1_2 jr-gate I-V characteristics, VT=*-3.7V, IDSSa'70mA specifications of manufacturers have a VT and IQSS tolerance typically ranging from -4 to -2V and 30 to 70mA respectively. The measured characteristics of our SI devices are in this range. 9. CONCLUSION Sample and hold cycles, with ideal switch strobe pulses, indicate a single gate 0.5/im MESFET switch integrated sampling amplifier block will have the best input time constant, and likely be the only unit, at this level of lithography, capable of successful operation with 25ps pulses. The mechanisms by which MESFET switch guard gates affect sample and hold switch operation have been demonstrated by simulation. Strobe pulse feedthrough is reduced by momentary forward conduction of the guard gate, allowing displaced carriers to tunnel out of the switch channel. The number of carriers involved in the tunneling action is guard gate bias and signal level sensitive causing some distortion of the output signal. The input time constant increases, due to the extra guard channels in series, is in the order of 30 to 40% when using a reduction of hold node capacitance. The applicability of the GaAs RSAG process to sample and hold switch design has been verified by a multiple gate slice simulation, indicating in the order of 5ps gate center tap to gate end delay for a 30Mm width t-gate. 96 REFERENCES 1.1 L. J. Conway and S. L. Bouchard, "The Sampling Amplifier", DREO REPORT NO. 863, (1982). 1.2 P.H. Saul, "A GaAs MESFET Sample and Hold Switch," IEEE JSSC, Vol. SC-15, No. 3, 282-285, (1980) 1.3 G. S. Barta and A. G. Rode, "GaAs Sample and Hold IC using a 3-Gate MESFET Switch," IEEE GaAs IC Symposium, 29-32, (1982). 1.4 W. G. Durtler, "The Design, Simulation and Fabrication of a Gallium Arsenide Monolithic Sample and Hold Circuit," M.A.Sc. Thesis, University of British Columbia, (1986). 1.5 R. L. Van Tuyl, "A Monolithic Integrated 4-GHz Amplifier," IEEE ISSC Conference, 72-73, (1978). 1.6 D. Hornbuckle, "GaAs IC Direct Coupled Amplifiers," IEEE MTT Symposium Digest, 387-389, (1980). 1.7 R. L. Van Tuyl, D. Hornbuckle, and D. B. Estreich, "Computer Modeling of Monolithic GaAs IC's," IEEE MTT Symposium Digest, (1980). 1.8 D. P. Hornbuckle and R. L. Van Tuyl, "Monolithic GaAs Direct-Coupled Amplifiers," IEEE Trans. ED, ED-28, 175-182, (1981). 1.9 K. Yamasaki, K. Asai and K. Kurumada, "N* Self-Aligned MESFET for GaAs LSI," Proc. 14th Conf. Solid-State Devices, (Tokyo, Japan), 201-202, (1982). 1.10 H.M. Levy, R.E. Lee and R.A. Sadler, "A Submicron Self-Aligned GaAs MESFET Technology for Digital Integrated Circuits," IEEE Trans. ED, ED-29, 1687, (1982). 1.11 R. Kiehl, P. Flahive, S. Wemple and H. Cox, "Direct-Coupled GaAs Ring Oscillator with Self Aligned Gates," IEEE ED Lett., Vol. EDL-3, No. 11, 325, (1982). 1.12 Microtel Pacific Research verbal communication. 1. 13 Precision Photomask Inc. verbal communication. 2.1 S. Dindo, "GaAs Material Investigation for Integrated 97 98 Circuits Fabrication," M.A.Sc. Thesis, University of British Columbia, (1985). 2.2 R. A. Saddler, "Fabrication and Performance of Submicron GaAs MESFET Digital Circuits by Self Aligned Ion Implantation," Ph.D. Thesis, Cornell University, (1984). 2.3 R. L. Van Tuyl, V. Kumar, D. C. D'Avanzo, T. W. Taylor, V.E. Peterson, D. P. Hornbuckle, R. A. Fisher, D. B. Estreich, "A Manufacturing Process for Analog and Digital Gallium Arsenide Integrated Circuits," IEEE Trans. MTT, MTT-30, 935-941, (1982). 2.4 T. Andrade, "Manufacturing Technology for GaAs Monolithic Microwave Integrated Circuits," Solid State Technology, (1985). 2.5 A.W. Livingstone, P.A. Leigh, N. Mclntyre, I.P. Hall, J.A. Bowie and P.J. Smith, "Ion Implantation of GaAs Integrated Circuits," Solid-State Electronics, Vol. 26, No. 1, 19-24, (1983) 2.6 H. Hartnagel and B.L. Weiss, "Dislocations in GaAs Produced by Device Fabrication," Solid-State Electronics, Vol. 17, 799-803, (1974) 2.7 CJ. Mogab, "VLSI Technology: Chapter 8," edited by S.M. Sze, McGraw Hill, (1983). 3.1 S.M. Sze, "Physics of Semiconductor Devices," Second Edition, John Wiley & Sons, 254, (1981) 3.2 W. Kellner, N. Enders, D. Ristaw, and H. Kniepkamp, "Solid-State Electronics, Vol. 23, 9, (1980). 3.3 H.H. Berger, "Models for Contacts to Planar Devices," Solid-State Electronics, Vol. 15, 145-158, (1972). 3.4 P. Townsley Process Engineer, U.B.C. Electrical Engineering Solid-State Lab, verbal communication. 3.5 P.K. Vasudev, B.L. Mattes, E. Pietras and R.H. Bube, "Excess Capacitance and Non-Ideal Schottky Barriers on GaAs," Solid-State Electronics, Vol. 19, 557-559, (1976) 4.1 Precision Photomask Inc. verbal communication. 4.2 Karl Suss mask aligner manual. 4.3 W. Durtler, P. Townsley and L. Young, "High Speed Gallium Arsenide Switches," Progress Report to 31 May 1985 submitted to DREO. 4.4 P. Wolf, "Microwave Properties of Schottky-Barrier 99 Field-Effect Transistors," IBM Journal Res. & Dev., Vol. 14, 125-141, (1970). 4.5 P.H. Ladbrooke, "Some Effects of Wave Propagation in the Gate of a Microwave MESFET," Electronics Letters, Vol. 14, No. 1, 21-22, (1978) 4.6 Y. Wang and M. Bahrami, "Distributed Effect in GaAs MESFET," Solid-State Electronics, Vol. 22, 1005-1009, (1979) 4.7 R.L. Kuvas, "Equivalent Circuit Model of FET Including Distributed Gate Effects, IEEE Trans. ED, ED-27, No. 6, 1193-1195, (1980) 4.8 W. Heinrich and H.L. Hartnagel, "Wave Propagation on MESFET Electrodes and Its Influence on Transistor Gain," IEEE MTT, MTT-35, No. 1, 1-8, (1987). 4.9 L. W. Nagel, "SPICE 2: A computer program to simulate semiconductor circuits," Electronics Research Lab, Col. Eng., University of California, Berkeley, Memo. ERL-M520 (1975). 4.10 W.R. Curtice, "A MESFET Model for Use in the Design of GaAs Integrated Circuits," IEEE Trans. MTT, MTT-28, No. 5, 448 (1980). 4.11 S.E. Sussman-Fort, S. Narasimhan and K. Mayaram, "A Complete GaAs MESFET Computer Model for SPICE," IEEE Trans. MTT, MTT-32, No. 4, 471 (1984). 4.12 W.R. Curtice and Yong-Hoon Yun, "A Temperature Model for the GaAs MESFET," IEEE Trans. ED, ED-28, No. 8, 954, (1981). 4.13 W.R. Curtice and R.L. Camisa, "Self-Consistent GaAs FET Models for Amplifier Design and Device Diagnostics,"IEEE Trans. MTT, MTT-32, No. 12, 1573 (1984). 4.14 W.R. Curtice and M. Ettenberg, "A Nonlinear GaAs FET Model for Use in the Design of Output Circuits for Power Amplifiers," IEEE Trans. MTT, MTT-33, No. 12, 1383 (1985). 4.15 Philip L. Hower and N. George Bechtel, "Current Saturation and Small-Signal Characteristics of GaAs Field-Effect Transistors," IEEE Trans. ED, ED-20, No. 3, 100 (1973) . 4.16 S.E. Sussman-Fort, J.C. Hantgan and F.L. Huang, "A SPICE Model for Enhancement and Depletion Mode GaAs FETs," IEEE MTT, MTT-34, No. 11, 1115-1119, (1986). 4.17 I.M. Abdel-Motaleb, W.C. Rutherford and L. Young, "GaAs Inverted Common Drain Logic(ICDL) and Its Performance Compared with Other GaAs Logic Families," to be published Solid-State Electronics, (1987). 4. 18 J. Michael Golio, John R. Hauser, and Peter A. Blakey, "A Large-Signal GaAs MESFET Model Implemented on SPICE," IEEE Circuits and Devices Magazine, 21-30, Sept. (1985). 4.19 R.L. Van Tuyl and C.A. Liechti "High-Speed Integrated Logic with GaAs MESFET's," IEEE JSSC, Vol. 9, No. 5, (1974) . 4.20 Tzu-Hung Chen and Michael S. Shur, "Analytical Models of Ion-Implanted GaAs FET's," IEEE Trans. ED, ED-32, No. 1, 18-28, (1985) 4.21 S. Chaudhuri and D.C. Look, "Effect of the Velocity-Field Peak on I-V Characteristics of GaAs FETs," Solid-State Electronics, Vol. 26, No. 8, 811-814, (1983) 5.1 J.V. Faricelli, J. Frey and J.P. Krusius,"Physical Basis of Short Channel MESFET Operation II: Transient Behavior," IEEE Trans. ED, ED-29, No. 3, 377-388, (1982) 5.2 F.A. Buot, "Effects of Velocity Overshoot on Performance of GaAs Devices, with Design Information," Solid-State Electronics, Vol. 26, No. 7, 617-632, (1983) 6.1 D. B. Estreich, "A Monolithic Wide-Band GaAs IC Amplifier," IEEE JSSC, SC-17, 1166-1173, (1982). 8.1 D.C. D'Avanzo, "Proton Isolation for GaAs MESFETs," IEEE Trans. MTT, Vol. MTT-30, No. 7, (1982). 8.2 H.H. Berger, "Models for Contacts to Planar Devices," Solid-State Electronics, Vol. 15, 145-158, (1972) 8.3 C. A. Liechti, "Performance of Dual-Gate GaAs MESFET's as Gain-Controlled Low-Noise Amplifiers and High-Speed Modulators," IEEE Trans. MTT, MTT-23, No. 6, (1975). 101 8.4 Y. Ikawa, W.E. Eisenstadt and R.W. Dutton, "Modeling of High-Speed, Large-Signal Transistor Switching Transients from s-Parameter Measurements," IEEE JSSC, SC-17, No. 2, (1982). 10. APPENDIX A -ICDL SIMULATIONS 10.1 DIGITAL INTEGRATED CIRCUIT SIMULATION OVERVIEW Inverted common drain logic (ICDL), was modeled comparatively to other GaAs MESFET logics. ICDL is a new logic circuit configuration developed by Abdel-Motaleb[4.17] in which the logic functions are realized using the pullup rather than the pulldowm transistors which are normally used. Depletion ("normally on") transistors are employed. The basic switching modes and the advantages and problems are discussed. Simulations were done using both the JFET and the Sussman-Fort MESFET models in SPICE. Experimental results were first simulated using parametric data obtained from measurements. In order to attempt to compare performance with some well established logic approaches, these were simulated using the same parametric data for all the logics. Depletion transistors (which conduct for Vgg = 0) were used in the first GaAs logic circuits because of the problems of fabricating enhancement type devices with sufficiently controlled threshold voltages and low enough series resistances (Rs and RD). In the BFL (buffered FET logic) approach, logic functions are achieved, as shown in Fig. 10.1(a), using combinations of pulldown depletion transistors. This is the same, for example, as in silicon MOSFET DCFL (direct coupled FET logic) which uses enhancement devices (which are OFF for VQS = 0), except that 102 103 A Fig. 10.1 GaAs MESFET logic. a) BFL (buffered FET logic) [1] -i-b) SDFL (Schottky diode FET logic)[2] c) DCFL (direct coupled FET logic)[3] the output must be level-shifted before presentation to the next stage, since a negative gate voltage (with respect to the source) is required to turn off the depletion pulldown transistors. The level shifting is achieved using Schottky diodes. In SDFL (Schottky diode FET logic, Fig. 10.1(b)) the inputs are combined using diodes. Eventually, it is commonly believed, VLSI using GaAs will be achieved by using enhancement pulldown devices [3] 1 104 and DCFL (Fig. 10.1(c)). The required threshold voltage and low series resistances may be obtained using a self-aligned gate technology [4-8] (once the ion implantation and activation process is better controlled) or else some form of etched recessed gate [9], For the present we restrict ourselves, however, to depletion type transistors to form the logic and consider what advantages (or otherwise) may be obtained by, so to speak, turning the logic upside down by using the pullup transistors to form the logic with pulldown transistors acting as loads. The idea of doing this seems an obvious one, but there is surprisingly little previous consideration of it in the literature. Of what we could find, the most significant was the work of Nuzillat et al. [8,9]. 105 10.2 ICDL BASIC CIRCUITS The basic gates for ICDL [10] are assembled in Fig. 10.2 and are first briefly listed before discussion in later sections. The first (Fig. 10.2(a) is a non-inverting buffer. This buffer was proposed previously by Hartgring et al. [11] for use in connection with dynamic silicon MESFET logic. An inverter is needed and requires a second power supply Vss for level shifting between stages. The inverter considered, Fig. 10.2(b), differs from the SDFL inverter, Fig. 10.1(c), in using an ion implanted, non-velocity saturating, resistor in place of diodes for level shifting. The buffered form of the inverter, with high input impedance, is actually the version most needed, and this is shown in Fig. 10.2(c). The AND gate is in Fig. 10.2(d) and the OR gate in Fig. 10.2(e), with possible complex gate configurations in Fig. 10.2(f) and (g). A similar inverted OR gate was previously listed by Nuzillat et al. in connection with their quasi-normally-off logic. Our logic gate differs by not having a diode between the pullup transistors and the pulldown load and also by using a transistor instead of a resistive load. Also Nuzillat et al. were specifically studying quasi-normally-off devices with small threshold voltages (either positive or negative) whereas we are considering depletion transistors. With this constraint Nuzillat et al. were able to require only one positive supply. In ICDL a supply rail is necessary to accommodate medium to large negative threshold voltages. ICDL differs from the SDFL Fig. 10.2 ICDL configurations: a)buffer, b)inverter, c)buffered inverter, d) AND, e)OR. f)F = H-F2 = (K+W) • (C+D) g)F = (A+B)•(C+D) 107 configuration not only in the use of a resistor as voltage translator, but in the use of the inverted logic as input buffer. Similarly ICDL differs from the BFL configuration by removing the voltage translation mechanism from the output path. 10.3 BUFFER CIRCUIT Load line plots for the buffer are given in Fig. 10.3(a) to show how the logic levels are obtained. The IDs vs VDS characteristics are here plotted for constant a) b) Fig. 10.3 Inverted buffer loadline with VDD=3V, VSS=0V, VQD=0 and -2.5 V for the switching transistor corresponding to a high and low logic input, with measured vs. model JFET and MESFET characteristics in (b) for (M-|) and (J-|) in (a). a) MESFET Model (Mi,), JFET Model (J^ where VT • -1.37 V and MESFET Model (M,) where VT = -0.5 V b) Comparison of the JFET(J) and MESFET(M) models vs. experimental(•) data: ID vs. VDS for VGS » -0.5 and O.O V 108 VDg instead of the usual constant VGg needed for conventional FET logic. Using the common approximation for IDS below saturation IDs = 2/}( (VGS - VT)VDS - VDS2/2) we can USE VGS = VDS + VGD t0 o°tain tne form we need IDS = 2^((VGD - VT) VDS + VDS2/2). Here IDS > 0 if VGD - Vm + VDS/2 > 0. Above saturation, instead of the usual *DS = ^(VGS " VT^2 we obtain IDS = 0(VDS + VQD - VT)2. For a high input (ie small VGD) VDS for the switching transistor is small so that the output is high. For a low input (VGD large and negative) VDg is large so that the output is low. The load line plotted on these drain current characteristics for constant VGD is the pulldown depletion transistor characteristic for its VGS = 0. In Fig. 10.3(a) the JFET SPICE model [12] (which employs the above approximate characteristics) has been used and, also, an improved model due to Sussman-Fort et al. [13] following criticisms and proposed improvement of the JFET model by Curtice [14]. The chief differences are the use of a better representation of IDg in the triode region as shown in Fig. 10.3(b) and the introduction of a gate transit time delay. The difference in representation of IDg shows up in Fig. 10.3(a) but is more important in considering transients. From Fig. 10.3(a) it is apparent that with a larger magnitude VT the supply voltage needs to be larger to get good VT = -1.37 (M^), Vt = -0.5 (M2) '> separation of the logic levels. This appears again in Fig. 10.4(a) and (b) which shows the simulated transfer 109 Fig. 10.4 Buffer transfer. a) MESFET(M) vs. JFET(J): VDD = -0.5 (M2, J2) b) MESFET(M) vs. JFET(J): VT characteristic (Vout vs V^n) for different VT and supply voltages VDD using both JFET and MESFET models. A computer simulation of the voltage transfer characteristics of the buffer, using the JFET and MESFET models, is shown in Fig. 10.4(a) and (b).The MESFET model is employed for simulation in Fig. 10.4(c) and (d). In Fig. 10.4(a) and (b) the switching and load transistors are identical. The voltage gain dVQut/dV^n for a single stage is close to 1 over a certain range for a choice of supply voltage scaled with device parameters (Fig. 10.4(b)). The simulation of several stages shown in Fig. 5(c) and (d) shows that the logic high and low levels saturate at about = 3 V, VT = -1.37 (M1f JT), VT - "1.37, Vjjjj - 7 V 110 BUFFER STAGE NUMBER BUFFER STAGE c) d) Fig. 10.4 c) Logic levels as a function of sequential stages where: VDD - 3, d) Logic levels as a function of sequential buffer stages where: VDD = 7, VT = -1.37 (M-j), VT = -0.5 (M2) VDD ~ IVTI ANO- AT IVTI respectively. 10.4 INVERTER The transistors for pullup and pulldown in the buffer will show process variations. Also as shown in Fig. 10.4(b) and (d) for a threshold voltage of a certain magnitude a sufficient supply voltage is needed to get well distinguished logic levels. Hence the logic levels may be lost after a few stages under certain adverse conditions. This indicated that an inverter with voltage gain greater than unity is required to regenerate the original values of the logic levels. 111 The proposed inverter, shown in Fig. 10.2(b), consists of a level shifter stage and an output stage which acts like a conventional ratioed logic inverter. The use of a resistor in place of the diodes, for example as used in the SDFL inverter, was chosen because it appeared to be easier to fabricate, since the diodes are required to be small and very accurate due to the need for reproducible current voltage characteristics. The resistance of the ion implanted resistor can be varied by varying the dose rather than the dimensions (which requires a different mask set). If small diodes of exact area are used to obtain strain on the photolithography. If, instead, a series combination of larger diodes is used (as in BFL, for example) then more space and power are consumed. When replacing the diode stack with a resistor the I-V curves must coincide for the critical switching region quiescent condition to give the same DC transfer characteristics. The resistor is chosen by plotting resistance versus output voltage for a resistor input voltage in the center of the logic swing as shown in Fig. 10.5. When the input and output voltages are equal at the logic midpoint a symmetrical transfer characteristic is obtained. For the case in Fig. 10.5(a) and (b) this occurs at approximately 2.5 and 0.63 kohm respectively. Using the criterion of equal current for a given voltage drop at the logic midpoint for the diode stack and resistor, the diode stack diode number and area can be 1 12 1Kohm/R IKohm/R a) b) Fig. 10.5 Inverter output voltage vs. reciprocal of the voltage translator resistor value with fixed input voltage at (vOH ~ VOL*/2 + vOL' where vOH s 3 v and vOL " °-2 v-a) VT • -0.5 V, VDD - 3 V, Vss = -2 V b) VT * -1.37 V, VDD = 3 V, Vss = -2 V determined once average diode process constants are known. For the case in Fig. 10.5(a) the voltage drop across the resistor is 1.6 V and the current 0.64 mA. If the diode process is fixed only the number of diodes, the area, and the supply voltages can be changed. Assuming the same supply rails, and average diode process constants from reference [7], a two diode stack would be necessary to provide the voltage drop, which if equal in area would consume 1 nm2 per diode, for a symmetrical transfer characteristic. The I-V characteristics of the resistor and diode stack are shown in Fig. 10.6. In the low input logic state the inverter with diodes dissipates about 85% less power and in the high input logic state, (assuming the inverter input peaks at 2 volts) 113 Fig. 10.6 I-V plots for translator resistor and diode stack. dissipates about the same amount of power. However, if the inverter input rises to the supply rail, 3 volts, the diode circuit dissipates about five times more power than the resistor circuit. The difference in dynamic behavior thereafter depends on the diode stack non-linearity. The simulated relative dynamic performance for the case under consideration is shown in Fig. 10.7. The diode stack circuit is predictably faster in the high to low transition, due to the diode stack current nonlinearity, but approximately equivalent to the resistor circuit in the low to high transition, where the depletion load must remove the accumulated charge. Thus, although the resistor circuit is slower on the down transition, it is delay symmetric making it a less complex timing design problem for large interactive systems, and it poses a less critical power consumption problem for logic 114 Fig. 10.7 Pulse response of buffer and inverter. a) Buffer :VDD = 5 V with one buffer load. b) Inverter, R = 629 0, VDD = 3 V, Vss = -2 V, with one buffer load. c) Inverter comparison, diode stack vs. resistor version, VT = -0.5V, no load. high inputs. 115 10.5 BUFFERED INVERTER The ICDL inverter turns out to give a rather low fan-in and fan-out, similar to the case with SDFL, a large current must be driven into the next stage. This problem can be overcome if the buffer circuit or appropriate logic block is added as shown in Fig. 10.2(c). The sizing of the buffer transistors must account for the DC load, power dissipation, and dynamic considerations with respect to the inverter. 10.6 OR GATE The operation of the OR logic follows from the discussion of the buffer with degraded dynamic performance due to the added capacitance. 10.7 AND GATE The positive logic AND as shown in Fig. 10.2(d) suffers from a severe limitation not present for MISFET circuits. For logic high inputs forward current will flow through the Schottky diode gates of the input transistors when gate source voltage exceeds about 0.7V. The four possible input logic combination gate currents as a function of input voltage are shown in Fig. 10.8. The width of T-| is taken as twice the width of T2 and four times the width of T3 to maintain a reasonable output swing for the voltage combinations that are acceptable before gate forward conduction sets in. The problem can be circumvented by using gates of the form of Fig. 10.2(g), instead. These are ) 116 a) b) Fig. 10.8 Schottky diode gate current of transistors at inputs A and B of AND gate of Fig. (2) (d) as a result of fixed logic level on A with input voltage on B swept. a) A high (VQH = 3 V) B swept from 0 to 3 V. b) A low (VQL • 0.2 V) B swept from 0 to 3 V. combinations of the logic OR of Fig. 10.2(e). In summary, if a limited (0.5 V) logic swing is used, gates such as shown in Fig. 10.2(d) and (f) could be used. This would give lower power dissipation compared to Fig. 10.2(g), but probably at the expense of speed and reliability. 10.8 RESULTS AND THEIR SPICE SIMULATION The measured parameters used for SPICE simulation for 117 experiment results matching are in Table 10.1. Parameter 2um FET Group 1 Group 2 Group 3 Rs o RD SI VT 0(A/V») 68 180 -1.37 2.8- 10"3 100 100 -2.5 200 200 -1.0 400 400 -0.5 or 0 4.4- 10~4 7-10"4 1 0r -3 1.4-10 3 5 100 100 5 5 5 5 5 Table 10.1: Measured and Simulation MESFET parametric data. Simulation data adjusted from [20-23]. In Group 3 logic approaches designed for VT = 0 or -0.5 V are considered, thus two values of fi were used as listed, respectively. Capacitance and fi tor the measured data is total whereas for the parametric data it is per unit length. As shown in Fig. 10.2(b) experimental characteristics were well fitted by the MESFET model both in the saturation and linear regions. The MESFET model successfully fits the whole DC characteristic better than the JFET model. The measured and simulated DC characteristics of the buffer circuit and the inverter are shown in Fig. 10.4(b). Experimental results confirm the feasibility projected by the simulations. The small deviation between simulated and measured transfer characteristic for the buffer corresponds to the variation in the IQS ~ VDS characteristics of the transistors from the simulation values. Simulated dynamic responses for the buffer and the inverter are given in Fig. 10.6. These were obtained neglecting parasitics due to interconnections. The justification for this is that these would depend on details 118 of layout and we are seeking the basic or intrinsic behavior of the circuit. The MESFET model simulated experimental buffer, using VDD = 5 V, gave an average time delay of 105 ps for unity fanout with power dissipation (input held at the logic midpoint) of 18.7 mW, and power delay product of 1.96 pJ. The inverter gave an average delay of 550 ps using a buffer circuit as load with 22.2 mW dissipation and a power delay product of 12.2 pJ per gate. REFERENCES 1. R. Van Tuyl and C. Liechti, IEEE JSSC, SC-9, No. 5, 269 (1974) . 2. R. Eden, B. Welch, and R. Zucca, IEEE JSSC, SC-13, No. 4, 619 (1978). 3. H. Ishakawa, H. Kusakawa, K. Suyama and M. Fukuta, Int. Solid-State Circuits Conf., Dig. Tech. Papers, 200 (1977). 4. R.A. Sadler and L.F. Eastman, IEEE Electron Dev. Lett., EDL-4, No. 7, 215 (1983). 5. R.E. Lee, H.M. Levy and D.S. Matthews, IEEE GaAs IC Symposium, 177 (1982). 6. K. Yamasaki, K. Asai and K. Kurumada, Japanese J. Appl. Phys., 22, Supplement 22-1, 381 (1983). 7. R. A. Saddler, "Fabrication and Performance of Submicron GaAs MESFET Digital Circuits by Self Aligned Ion Implantation," Ph.D. Thesis, Cornell University, (1984). 8. R. Pengelly, Microwave Field-Effect Transistors-Theory Design and Applications, Research Studies Press, Chichester (1982). 9. G. Nuzillat, F. Damay-Kavala, G. Bert and C. Arnodo, IEE Proc, 127, Pt. I, No. 5, 287 ( 1980). 10. G. Nuzillat, G. Bert, T.P. Ngu and M. Gloanec, IEEE Trans. Electron Dev., ED-27, No. 6, 1102 (1980). 11. I. M. Abdel-Motaleb, "GaAs MESFETS and Their Applications in Digital Logic and Digital to Analog Conversion", Ph.D. Thesis, University of British Columbia, (1985). 12. CD. Hartgring, B.A. Rosario and J.M. Pickett, IEEE JSSC, SC-16, NO. 5, 578 (1981). 13. L. W. Nagel, "SPICE 2: A computer program to simulate semiconductor circuits," Electronics Research Lab, Col. Eng., University of California, Berkeley, Memo. ERL-M520 (1975) . 14. S.E. Sussman-Fort, S. Narasimhan and K. Mayaram, "A Complete GaAs MESFET Computer Model for SPICE," IEEE Trans. MTT, MTT-32, No. 4, 471 (1984). 15. W.R. Curtice, "A MESFET Model for Use in the Design of 119 120 GaAs Integrated Circuits," IEEE Trans. MTT, MTT-28, No. 5, 448 (1980). 16. A. Livingstone and D. Welbourn, Proc. of the 14th Conf. on Solid State Devices, Tokyo, 393 (1982). 17. A. Livingstone, and P. Mellor, IEEE Proc, 127, Pt. I, No. 5, 297 (1980). 18. M. Namordi and W. White, GaAs IC Symposium, 21 (1982). 19. A. Barna, and C. Liechti, IEEE JSSC, SC-14, No. 4, 708 (1979) 20. M. Helix, S. Jamison, S. Hanka, R. Vidano, P. Ng, and C. Chao, GaAs IC Symposium, 108 (1982). 21. S. Katsu, S. Nambu, S. Shimano and G. Kano, IEEE Electron Dev. Lett., EDL-3, No. 8, 197 (1982) 22. T. Onuma, A. Tamura, T. Uenoyama, H. Tsujii, K. Nishii and H. Yagita, IEEE Electron Dev. Lett., EDL-4, No. 11, 409 (1983). 23. K. Yamasaki, K. Asai, K. Kuramada, IEEE Trans. Electron Dev., ED-29, NO. 11, 1772 (1982) 11. APPENDIX B -LAYOUTS SI3S913T3 ISAB 121 RI26R912T3 ISAB 12. APPENDIX C -GASFET SUBROUTINE SUBROUTINE GASFET IMPLICIT REAL*8 (A-H.O-Z) C C THIS ROUTINE PROCESSES GaAs HESFETS FOR DC AND C TRANSIENT ANALYSES. C BASED ON THE MODEL OF WALTER R. CURTICE C IEEE TRANS ON MICROWAVE THEORY AND TECHNIQUES C VOL MTT-28 NO. 5 MAY 1980 C COMMON /TABINF/IELMNT,ISBCKT,NSBCKT.IUNSAT,NUNSAT,ITEMPS,NUMTEM, 1 ISENS,NSENS,IFOUR,NFOUR,IFIELD,ICODE,IDELIM.ICOLUM.INSIZE. 2 JUNODE.LSBKPT,NUMBKP,IORDER.JMNODE,IUR,IUC,ILC,ILR,NUMOFF,ISR, 3 NMOFFC.ISEQ.ISEQ1.NEQN.NODEVS.NDIAG,ISWAP,IEQUA.MACINS.LVNIM1, 4 LX0,LVN,LYNL,LYU,LYL,LX1,LX2,LX3,LX4,LX5,LX6,LX7,LD0,LD1.LTD, 5 IMYNL,IMVN,LCVN,NSNOD,NSMAT.NSVAL,ICNOD,ICMAT»ICVAL, 6 LOUTPT,LPOL,LZER,IRSWPF,IRSWPR,ICSWPF,ICSWPR,IRPT,JCPT, 7 IROWNO,JCOLNO,NTTBR,NTTAR,LVNTMP COMMON /CIRDAT/LOCATE(50),JELCNT(50 >.NUNODS,NCNODS,NUMNOD,NSTOP, 1 NUT,NLT,NXTRM,NDIST,NTLIN,IBR,NUMVS COMMON /STATUS/OMEGA.TIME,DELTA,DELOLD(7).AGO).VT.XNI,EGFET, 1 XMU,MODE,MODEDC,ICALC,INITF,METHOD,IORD,MAXORD,NONCON,ITERNO. 2 ITEMNO.NOSOLV.MODAC,IPIV,IVMFLG.IPOSTP,ISCRCH,IOFILE COMMON /KNSTNT/TWOPI,XLOG2,XLOG10,ROOT2,RAD,BOLTZ,CHARGE,CTOK, 1 GMINtRELTOL,ABSTOL,VNTOL,TRTOL,CHGTOL,EPSO,EPSSIL,EPSOX. 2 PIVTOL.PIVREL COMMON /BLANK/ VAXUE(200000) INTEGER NODPLC<64) COMPLEX • 16 CVALUE(32) EQUIVALENCE (VALUE<1>,NODPLC(1).CVALUE(1)) C C DIMENSION VGSO(1),VGDO(1),CGO<1>,CDO(1),CGDO(1),GMO(1),GDSO(1). 1 GGSO(1),GGDO(1),QGS(1),CQGS(1),QGD(1),CQGD(1). 2 QDS(1).CQDS(1).QTT<1),CQTT(1> EQUIVALENCE (VGSO(1>.VALUE( 1>>.(VGDO(1>.VALUE( 2)), 1 (CGO <D.VALUE( 3)),(CDO (1).VALDE( 4>), 2 (CGDOO),VALUE( 5)),(GMO ( 1),VALUE( 6)), 3 <GDSO<1).VALUE( 7)),(GGSO(1),VALUE< 8>), 4 (GGDOO). VALUE < 9)).<QGS ( 1) ,VALUE( 10) > . 5 (CQGS(D.VALUE(11)).<QGD ( 1 > ,VALUE( 12)), 6 (CQGD(1),VALUE(13)),<QDS (1>,VALUE(14)>, 7 (CQDS(1).VALUE(15)),(QTT (1),VALUE<16)), 8 (CQTT(1),VALUE(17)) C C LOC=LOCATE(16) 10 IF (LOC.EQ.0) RETURN LOCV=NODPLC < LOC+1) NODE 1=NODPLC(LOC+2) NODE2=NODPLC(LOC+ 3) NODE 3=NODPLC(LOC+ 4) NODE 4=NODPLC < LOC+5 > NODE5=NODPLC<LOC+6) NODE6=NODPLC< LOC+25) LOCM=NODPLC(LOC+7) IOFF=NODPLC(LOC+ 8) TYPE=NODPLC(LOCM+2) LOCM=NODPLC < LOCM+1) LOCT=NODPLC(LOC+19 > C C DC MODEL PARAMETERS C 123 WlDTH-VALUE{LOCV+1) VT0»VALUE<L0CM+1> VBI•VALUE<LOCM+2) C GATE PARASITIC CONDUCTANCE: GGPR GGPR"VALUE(LOCM+3 >'WIDTH ALPHA=VALUE(LOCM+4 > BETA-VALUE(LOCM* 5)•WIDTH XLAMB-VALUE < LOCM+6) CSAT-VALUE(LOCM*10)»WIDTH C DRAIN PARASITIC CONDUCTANCE: GDPR GDPR -VALUE (LOCM+11) »WI DTH C SOURCE PARASITIC CONDUCTANCE: GSPR GSPR-VALUE(LOCM+12)»WIDTH TAU-VALUE(LOCM+13) VCRIT-VALUE < LOCM+14 > C C INITIALIZATION C ICHECK=1 GO TO (100.20,30,50,60,70), INITF 20 IF(MODE.NE.1.OR.HODEDC.NE.2.OR.NOSOLV.EQ.0) GO TO 25 VDS=TYPE«VALUE<LOCV+2) VGS-TYPE•VALUE(LOCV+ 3) VGD°VGS-VDS GO TO 300 25 IF(IOFF.NE.O) GO TO 40 VGS--1.0D0 VGD--1.0D0 GO TO 300 30 IF (IOFF.EQ.0) GO TO 100 40 VGS-O.ODO VGD-O.ODO GO TO 300 50 VGS=VGSO<LXO+LOCT) VGD-VGDO(LXO+LOCT) GO TO 300 60 VGS=VGSO(LX1+LOCT> VGD-VGDO(LX1+LOCT) GO TO 300 70 XFACT-DELTA/DELOLD<2) VGSO< LXO+LOCT)»VGSO< LX1+LOCT) VGS=(1.0D0+XFACT>*VGSO(LX1+LOCT>-XFACT»VGSO<LX2+LOCT) VGDO(LX0+LOCT)=VGDO< LX1+LOCT) VGD-(1.0D0+XFACT)•VGDO(LX1+LOCT)-XFACT*VGDO<LX2+LOCT) CGO< LXO+LOCT >-CGO(LX1+LOCT) CDO(LX0+LOCT)=CDO(LX1+LOCT) CGDO(LX0+LOCT)«CGDO(LX1+LOCT) GMO(LX 0+LOCT >-GMO < LX1+LOCT) GDSO(LX0+LOCT)=GDSO< LX1+LOCT) GGSO(LXO+LOCT > =GGSO(LX1+LOCT) GGDO(LX0+LOCT)»GGDO(LX1+LOCT) GO TO 110 C C COMPUTE NEW NONLINEAR BRANCH VOLTAGES C 100 VGS-TYPE*(VALUE(LVNIM1+ NODE6 >-VALUE(LVNIM1+NODE 5)) VGD-TYPE*(VALUE(LVNIM1+NODE6)-VALUE(LVNIM1+NODE4 >) 110 DELVGS=VGS-VGSO(LX0+LOCT) DELVGD-VGD-VGDO< LX0+LOCT > DELVDS-DELVGS-DELVGD CGHAT=CGO(LX0+LOCT)•GGDO(LX0+LOCT>»DELVGD+GGSO<LX0+LOCT>»DELVGS CDHAT=CDO(LX0+LOCT)+GMO(LXO+LOCT)*DELVGS+GDSO< LXO+LOCT)»DELVDS 1 -GGDO<LXO+LOCT)«DELVGD C BYPASS IF SOLUTION HAS NOT CHANGED C IF (INITF.EQ.6) GO TO 200 TOLoRELTOL»DMAX1< DABS(VGS),DABS(VGSO(LX0+LOCT)> > +VNTOL IF <DABS<DELVGS).GE.TOL) GO TO 200 TOL=RELTOL*DMAX1(DABS(VGD),DABS(VGDO<LXO+LOCT))>+VNTOL IF <DABS(DELVGD).GE•TOL) GO TO 200 TOL=RELTOL*DMAX1(DABS(CGHAT) ,DABS<CGO<LX0+LOCT>) >+ABSTOL IF (DABS(CGHAT-CGO(LX0+LOCT)).GE.TOL) GO TO 200 TOL«RELTOL*DMAX1< DABS(CDHAT),DABS(CDO(LXO+LOCT)))+ABSTOL IF (DABS(CDHAT-CDO(LXO+LOCT)).GE.TOL) GO TO 200 VGS«VGSO(LXO+LOCT> VGD«VGDO(LXO+LOCT) VDS=VGS-VGD CG=CGO(LX0+LOCT) CD«CDO(LXO+LOCT) CGD=CGDO(LXO+LOCT) GM=GMO<LXO+LOCT) GDS»GDSO<LXO+LOCT) GGS«GGSO<LXO+LOCT> GGD=GGDO<LXO+LOCT) GO TO 900 C C LIMIT NONLINEAR BRANCH VOLTAGES C 200 ICHK1-1 CALL PNJLIM<VGS,VGSO(LX0+LOCT).VT.VCRIT,ICHECK) CALL PNJLIM< VGD,VGDO(LXO+LOCT),VT,VCRIT,ICHK1> IF <ICHK1.EQ.O ICHECK«1 CALL FETLIM(VGS,VGSO(LXO+LOCT),VTO) CALL FETLIM(VGD,VGDO(LX0+LOCT),VTO) C C DETERMINE DC CURRENT AND DERIVATIVES C 300 VDS=VGS-VGD IF(VGS.GT.-5.0D0*VT) THEN EVGS=DEXP<VGS/VT) GGS=CSAT*EVGS/VT+GMIN CG=CSAT*(EVGS-1.ODO)+GMIN*VGS ELSE GGS=-CSAT/VGS+GMIN CG'GGS*VGS END IF C IF(VGD.GT.-5.0D0*VT) THEN C EVGD=DEXP(VGD/VT) C GGD=CSAT*EVGD/VT+GMIN C CGDsCSAT*(EVGD-1.0D0)+GMIN*VGD C ELSE C GGD=-CSAT/VGD+GMIN C CGD=GGD*VGD C END IF GGDoGMIN CGD=0.0D0 CG=CG+CGD C C COMPUTE DRAIN CURRENT AND DERIVITIVES C IF(VDS.GE.O) THEN C NORMAL MODE VGST»VGS-VTO IF<VGST.LE.O) THEN C C CUT-OFF SUBTHRESHOLD EFFECTS NOT INCLUDED CDRAINoO.ODO GM-O.ODO GDS =O.ODO ELSE C LINEAR AND SATURATION REGION BETAP=BETA»{1.0D0+XLAMB*VDS) TWOB=BETAP+BETAP CDRAIN=BETAP*VGST*VGST*DTANH(ALPHA*VDS> GM=TWOB*VGST*DTANH(ALPHA*VDS > GDS=XLAMB* BETA*VGST* VGST * DTANH(ALPHA*VDS) + 1 (BETAP«VGST»VGST*ALPHA*<1.0D0-2 <DTANH(ALPHA*VDS)*DTANH(ALPHA*VDS)))) END IF ELSE C INVERSE MODE VGDT=VGD-VTO IF(VGDT.LE.O) THEN C CUT-OFF CDRAIN-0.0D0 GM-0.0D0 GDS-O.ODO ELSE C LINEAR AND SATURATION REGION BETAP-BETA*(1.0D0-XLAMB*VDS) TWOB»BETAP+BETAP C CDRAIN«BETAP*VGDT*VGDT*DTANH(ALPHA»VDS) GM=-TWOB*VGDT* DTANH(ALPHA*VDS) GDS=-XLAMB*BETA*VGDT*VGDT*DTANH(ALPHA*VDS)• 1 (BETAP*VGDT*VGDT*ALPHA*(1.0D0-2 (DTANH(ALPHA*VDS)*DTANH(ALPHA* VDS)))) END IF END IF C C C COMPUTE EQUIVALENT DRAIN CURRENT SOURCE C CD=CDRAIN-CGD IF (MODE • NE• 1 ) GO TO 500 IF ((MODEDC.EQ.2).AND.(NOSOLV.NE.O)) GO TO 500 IF (INITF.EQ.4) GO TO 500 GO TO 700 C C CHARGE STORAGE ELEMENTS C 500 CZGS=VALUE<LOCM+7)»WIDTH CZGD=VALUE(LOCM+ 8)«WIDTH CZDS=VALUE(LOCM+9)*WIDTH TW0P=VB1+VBI C C IF VGS APPROACHES VBI NON ZERO CAPGS GOES TO INFINITY C VBI IS SCHOTTKY BARRIER JCT. PLUS 0.5V DUE TO DROP C IN CONDUCTION CHANNEL UNDER GATE C SARG=DSQRT(1.ODO-VGS/VBI) QGS(LXO+LOCT)*TWOP*CZGS* (1. ODO-SARG) CAPGS-CZGS/SARG QGD(LXO+LOCT)=CZGD»VGD C C GATE DRAIN CAPACITANCE HAS BEEN MODIFIED C TO THAT BELOW. C VDS AND VGS INCORPORATED FOR AC AND TRANSIENT ANALYSIS C ADAPTED FROM THE PAPER BY GOLIO ET AL. C IEEE CIRCUITS AND DEVICES MAGAZINE SEPTEMBER 1985 P 21. C VBI ASSUMED TO BE PHIG + CHANNEL DROP<0.5) 127 c CAPGD= (CZGD*(1.0D0-6.OD-1»VGS))/<(1.ODO-<1.23DO»VGS-VDS)/ 1 (1.23D0*(VBI-5.0D-1)))»6.6D-O QDS(LXO+LOCT)=CZDS*VDS CAPDS=CZDS C C QTT IS CHARGE TRANSPORTED UNDER GATE IN TIME TAU C QTT(LXO+LOCT > «TAU*CDRAIN CAPTT=TAU»GM C C STORE SMALL-SIGNAL PARAMETERS C 560 ir <(MODE.EQ.1).AND.(MODEDC.EQ.2).AND.(NOSOLV.NE.O>) GO TO 700 IF (INITF.NE.4) GO TO 600 VALUE(LXO+LOCT+9 >-CAPGS VALUE(LX0+LOCT+11>-CAPGD VALUE < LX0+LOCT+13)=CAPDS VALUE < LX0+LOCT+15)"CAPTT GO TO 1000 C C TRANSIENT ANALYSIS C 600 IF (INITF.NE.5) GO TO 610 QGS(LX1+LOCT > =QGS(LXO+LOCT > QGD < LX1+LOCT)*QGD(LXO+LOCT) QDS < LX1+LOCT)«QDS(LXO+LOCT) QTT(LX1+LOCT >-QTT(LXO+LOCT) 610 CALL INTGR8(GEQ,CEQ,CAPGS,LOCT+9) GGS'GGS+GEQ CG=CG+CQGS(LXO+LOCT) CALL INTGR 8(GEQ,CEQ,CAPGD,LOCT+11) GGD*GGD+GEQ CG-CG+CQGD(LXO+LOCT) CD»CD-CQGD<LXO+LOCT) CGDaCGD+CQGD(LXO+LOCT) CALL INTGR8(GEQ,CEQ,CAPDS,LOCT+13) GDSeGDS+GEQ CD=CD+CQDS(LXO+LOCT) CALL INTGR 8(GEQTT, CEQ,CAPTT,LOCT+15) GM=GM-GEQTT CD-CD-CQTT(LXO+LOCT) IF (INITF.NE.5) GO TO 700 CQGS(LX1+LOCT)«CQGS(LXO+LOCT) CQGD(LX1+LOCT)=CQGD(LXO+LOCT) CQDS(LX1+LOCT)=CQDS(LXO+LOCT) CQTT(LX1+LOCT)«CQTT(LXO+LOCT) C C CHECK CONVERGENCE C 700 IF (INITF.NE.3) GO TO 710 IF (IOFF.EQ.0) GO TO 710 GO TO 750 710 IF (ICHECK.EQ.1) GO TO 720 TOL«RELTOL*DMAX1(DABS(CGHAT),DABS(CG))+ABSTOL IF <DABS(CGHAT-CG).GE.TOL) GO TO 720 TOL=RELTOL»DMAX1(DABS(CDHAT).DABS(CD))+ABSTOL IF (DABS(CDHAT-CD).LE.TOL) GO TO 750 720 NONCON=NONCON+1 750 VGSO(LXO+LOCT)=VGS VGDO(LXO+LOCT>«VGD CGO<LXO+LOCT)=CG CDO(LXO+LOCT)"CD CGDO(LXO+LOCT)=CGD 128 GMO(LXO+LOCT>-GM GDSO(LX0+LOCT)»GDS GGSO(LXO+LOCT)-GGS GGDO(LXO+LOCT>-GGD LOAD CURRENT VECTOR 900 CEQGD-TYPE* < CGD-GGD*VGD) CEQGS=TYPE*((CG-CGD)-GGS«VGS) CDREQ-TYPB*((CD+CGD)-GDS*VDS-GM*VGS) VALUE < LVN+NODE6 >"VALUE < LVN+NODE6)-CEQGS-CEQGD VALUE(LVN+NODE4 >-VALUE(LVN+NODE4)-CDREQ+CEQGD VALUE(LVH+NODE5)-VALUE(LVN+NODE5)+CDREQ+CEQGS LOAD Y MATRIX LOCY-LVN+NODPLC(LOC+20 VALUE < LOCY)"VALUE < LOCY LOCY-LVN+NODPLC(LOC+21 VALUE(LOCY)-VALUE(LOCY LOCY-LVN+NODPLC< LOC+22 VALUE < LOCY)-VALUE(LOCY LOCY-LVN+NODPLC(LOC+23 VALUE(LOCY)-VALUE(LOCY LOCY-LVN+NODPLC(LOC+2 4 VALUE(LOCY >-VALUE(LOCY LOCY-LVN+NODPLC(LOC+26 VALUE(LOCY >-VALUE(LOCY LOCY-LVN+NODPLC(LOC+9) VALUE(LOCY >-VALUE < LOCY LOCY-LVN+NODPLC(LOC+10 VALUE(LOCY >-VALUE(LOCY LOCY-LVN+NODPLC(LOC+11 VALUE(LOCY >-VALUE(LOCY LOCY-LVN+NODPLC(LOC+12 VALUE< LOCY)-VALUE(LOCY LOCY-LVN+NODPLC(LOC+13 VALUE(LOCY >-VALUE(LOCY LOCY-LVN+NODPLC(LOC+14 VALUE(LOCY)-VALUE(LOCY LOCY-LVN+NODPLC< LOC+15 VALUE < LOCY >-VALUE(LOCY LOCY-LVN+NODPLC(LOC+16 VALUE(LOCY)-VALUE(LOCY LOCY-LVN+NODPLC(LOC+17 VALUE(LOCY)-VALUE(LOCY LOCY-LVN+NODPLC < LOC+18 VALUE(LOCY)-VALUE(LOCY LOCY-LVN+NODPLC(LOC+2 7 VALUE < LOCY >-VALUE< LOCY LOCY-LVN+NODPLC(LOC+2 8 VALUE(LOCY)-VALUE(LOCY 1000 LOC=NODPLC<LOC) GO TO 10 END •GDPR +GGD+GGS+GGPR •GSPR +GDPR +GDS +GGD +GSPR+GDS+GM+GGS +GGPR •GDPR -GGD -GGS -GSPR -GDPR +GM-GGD -GDS-GM -GGS-GM -GSPR -CDS -GGPR -GGPR 13. APPENDIX D -SIMULATION SOURCE LISTINGS PROCESS TEST 100 um MESFET CHARACTERIZATION •Cycle Controls .OPTIONS ITL4-1000 ITL5»0 LIMPTS=2000 NOPAGE NOMOD * •Listing Options .WIDTH OOT=80 • •Active Elements •Bn ND NG NS GFETn (width in urn) B1 1 2 0 SI12 100 B2 3 4 0 SI12 100 B3 5 6 0 S112 100 B4 7 8 0 SH2 100 B5 9 10 0 S112 100 * •Active Element Models •model is for 1 urn slice of MESFET which is multiplied by length •factor in device definition * .MODEL S112 GASFET(VTO'-2, VBI-1.23, RC0.13, ALPHA-2.3, BETA=2.61E-5 + LAMBDA»0.055, CGS0-1.19FF, CGD=1.19FF, CDS=0.096FF, IS=4.13E-15, • RD-3228, RS-3228, TAU-2.86PS) • •Independent Sources VDS 11 0 VDS 1 11 1 DC 0 VGS1 2 0 DC -1.5 VDS2 11 3 DC 0 VGS2 4 0 DC -1 VDS3 11 5 DC 0 VGS3 6 0 DC -0.5 VDS4 11 7 DC 0 VGS 4 8 0 DC 0 VDS5 11 9 DC 0 VGS5 10 0 DC 0.5 • •DC Analysis Parameters .DC VDS 0 3 0.025 • •Output Parameters .PRINT DC I(VDS1> I(VDS2) I(VDS3) I(VDS4) l(VDS5) • END ISAB RI36R912T3 Strobe Pulse Distortion • •Cycle Controls and Listing Options .OPTIONS ITL4=1000 ITL5=0 LIMPTS=2000 NOPAGE NOMOD .WIDTH OHT=80 * •••••••••••••ISAB Circuit******* • BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 1 1 20 0 V5 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components 129 CFIXED 11 0 9FF CSPAD 25 0 10FF CRFPAD 23 0 20FF CGPAD 24 0 2OFF LSIN 15 25 0.16NH LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RSIN 5 15 50 RRFIN 3 13 50 RGIN 4 14 50 • «»**»****«End ISAB Circuit******* •Amplifier Subcircuit • .SOBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66_ D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-+ LAMBDA-0.055. CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF. IS-2.07E-15, • RD-1170, RS-1170. TAO-0.71PS) .MODEL R12G1 GASFET<VTO=-2, VBI-1.23, RG-4.97, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET<VTO--2, VBI-1.23, RG-4.97, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAO-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Strobe Pulse Distortion due to Parasitics » VSIN 5 0 POLSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS) VRFB 3 0 -0.6 VGGB 4 0 -0.3 .TRAN 0. 1PS 50PS .PRINT TRAN V(5) V(25> . END ISAB RI36R912T3 Time Constant Determination * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • ******«»*»*«*XSAB Circuit******* * BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SOBCKT AMP 3 5 12 BIN 4 3 0 RSA612 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 • ENDS AMP « •Active Element Models • MODEL RSAG12 GASFET(VTO«- 2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF. CDS-0.0791FF. IS-2.07E-15. + RD-1170, RS-1170. TAU-0.71PS) •MODEL R12G1 GASFET(VTO-- 2, VBI-1.23. RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF. CDS»0.0791FF, IS-2.07E-15. + RD-705, RS-1170, TAU-0.71PS) •MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83. ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF. CDS-0.0791FF, IS-2.07E-15. • RD-705. RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA=3.1E-5 + LAMBDA-0.055, CGS0-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705. TAU-0.71PS) • .MODEL TD4 D<IS=.312E-12, RS-1745, N-1.1. TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8. IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Input Time Constant Determination * VSGB 25 0 -0.3 VGGB 24 0 -0.3 VRFIN 23 0 -0.6 PWL(0PS -.8 0.1PS -.4 100PS -0.4 100.IPS -0.8 200PS -0. .TRAN 2PS 200PS .PRINT TRAN V(6) V(20) . END ISAB RI36R912T3 Pulse Feedthrough at vbias • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 * •*•*••••••*••ISAB Circuit******* • BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF CRFPAD 23 0 2OFF CGPAD 24 0 2OFF LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RRFIN 3 13 50 RGIN 4 14 50 • «********«End ISAB Circuit******* •Amplifier Subcircuit » .SOBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF. CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170. TAU-0.71PS) .MODEL R12G1 GASFET(VTO«-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-1170, TAO-0.71PS) .MODEL R12S GASFET(VTO«-2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-705, TAO-0.71PS) .MODEL R12G2 GASFET(VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Pulse Feedthrough at vbias • VSIN 25 0 POLSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS) VGGB 4 0 -0.3 VRFB 3 0 -0.6 .TRAN 0.1PS 50PS .PRINT TRAN V<26) V(23) V(20) . END ISAB RI36R912T3 Off Isolation at 10GHz * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 « ••••«***««*t*ISAB Circuit******* 133 BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF * t*****»***End ISAB Circuit******* •Amplifier Subcircuit * .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 •ENDS AMP * •Active Element Models • MODEL RSAG12 GASFET(VTO--2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3. BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-705, TAU-0.71PS) « .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Off Isolation with 10 GHz Sine RF Input * RSHUNT 23 20 15M VRFIN 23 0 SIN<-0.6 0.2 10GHZ) VSGB 25 0 -2.9 VGGB 24 0 -0.3 .TRAN 2PS 100PS .PRINT TRAN V<23) V(20) V(21) .END ISAB RI36R912T3 Open Switch Tracking • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 * «»**«********ISAB Circuit******* BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • ZAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF * ••••••••••gnd ISAB Circuit******* •Amplifier Subcircuit * .SOBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0=0.595FF, CGD=0.595FF. CDS-0.0791FF, IS-2.07E-15. + RD-1170, RS-1170. TAU-0.71PS) .MODEL R12G1 GASFET( VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-O.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF. IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • Sine wave Tracking Open Switch * VRFIN 23 0 SIN(-0.6 0.2 1GH2) VSGB 25 0 -0.3 VGGB 24 0 -0.3 .TRAN 10PS INS .PRINT TRAN V<23) V(20) V(21) .END ISAB RI36R912T3 Tracking at 2.3Tau Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 « •••••••••••••ISAB Circuit******* BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V2 7 8 0 V3 9 10 0 Vt 11 20 0 V5 25 26 0 • ZAHP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit * .SOBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 T04 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0-0.S95FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) « .MODEL TD4 D( IS- '• 312E-12 , RS-1745, N-1.1, TT-.59PS, CJO-8. 02E-15, • VJ-0.72, EG-1.42, BV-8, IBV«1E-3> • •Independent Sources VDD 2 0 4.E VSS 10-3 * •Sine Have Tracking at Sampling Aperture 2.3Tau * VRFIN 23 0 SIN("0.6 0.2 1GHZ) VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 57.5PS 100PS) VGGB 24 0 -0.3 .TRAN 1PS INS .PRINT TRAN V(26) V(23) V(20) V(21) • END ISAB RI36R912T3 Tracking at Tau Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* * BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SOBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 • ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1-42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Sine wave Tracking at Sampling Aperture Tau * VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSIN 26 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS 100PS) VGGB 4 0 -0.3 .TRAN 1PS 1NS .PRINT TRAN V(26) V{23) V<20) V(21) .END ISAB RI26R912T3 Time Constant Determination * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* * BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF • •*«*******End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 • ENDS AMP • •Active Element Models .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA=0.055, CGSO-0.595FF, CGD=0.595FF, CDS-0.0791FF, IS-2.07E-15. + RD=705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 •» LAMBDA-0.055, CGS0=0. 595FF, CGD-0.595FF, CDS-0.079 IFF, IS-2. 07E-1 5, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG«0.83, ALPHA"2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0=0.595FF, CGD=0.595FF. CDS-0.0791FF. IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) « .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Input Time Constant Determination • VSGB 25 0 -0.3 VGGB 24 0 -0.3 VRFIN 23 0 -0.6 PWL(0PS -.8 0.1PS -.4 100PS -0.4 100.1PS -0.8 200PS -0. .TRAN 2PS 2OOPS .PRINT TRAN V(6) V<20> .END ISAB RI26R912T3 Pulse Feedthrough * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • «***««««*«**«iSAB Circuit******* • BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP 1 138 •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • •SOBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 01 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA=0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG«0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83. ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at vbias * VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS> VGGB 24 0 -0.3 VRFB 23 0 -0.6 .TRAN 0.1PS 50PS .PRINT TRAN V(26> V(23> V(20) . END ISAB RI26R912T3 Off Isolation • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* • BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 12 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP * •Active Element Models .MODEL R12S GASFET<VTO«-2, VBI=1.23, RG=0.83, ALPHA=2.3, BETA«3.1E-5 + LAMBDA=0.055, CGS0=0.595FF, CGD=0.595FF, CDS*0.079 IFF, IS«2.07E-15, + RD=705, RS=1170. TAU-0.71PS) .MODEL R12G2 GASFET(VTO=-2, VBI«1.23, RG»0.83, ALPHA=2.3, BETA=3.1E-5 + LAMBDA=0.055, CGS0=0.595FF, CGD«0.595FF, CDS=0.0791FF, IS=2.07E-15, • RD=1170, RS=705, TAU=0.71PS) .MODEL RSAG12 GASFET(VT0=-2, VBI=1.23, RG=0.83, ALPHA»2.3, BETA=3.1E"5 • LAMBDA«0.055, CGSO=0.595FF, CGD=0.59SFF, CDS=0.0791FF, IS=2.07E-15, + RD=1170, RS*1170^ TAU*0.71PS) • .MODEL TD4 D<IS».312E-12, RS-1745, N=1.1, TT=.59PS, CJO«8.02E-15, • VJ-0.72. EG'1.42, BV«»8, IBV«1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Ott Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 10M VRFIN 23 0 SIN(-0.6 0.2 10GHZ) VSGB 25 0 -2.9 VGGB 24 0 -0.3 .TRAN 2PS 100PS •PRINT TRAM V(23> V<20> V<21> • END ISAB RI26R912T3 Open Switch Tracking • •Cycle Controls and Listing Options •OPTIONS ITL4-1000 ITL5=0 LIMPTS«2000 NOPAGE NOMOD .WIDTH OUT=80 • •••**********ISAB Circuit******* * BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF * ••••••••••End ISAB Circuit******* •Amplifier Subcircuit * .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 140 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF. CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.07.91 FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS> .MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, + RD-1170, RS-1170, TAO-0.71PS) • .MODEL TD4 D<IS-.312E-12 , RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10-3 • Sine wave Tracking Open Switch * VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSGB 25 0 -0.3 VGGB 24 0 -0.3 .TRAN 10PS 1NS .PRINT TRAN V(23) V(20) V(21) .END ISAB RI26R912T3 Tracking with 2.3Tau Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OOT-80 • •••••••••••••ISAB Circuit******* • BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 Vt 23 6 O V3 9 10 0 V4 11 20 0 VS 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF « ••••••••••End ISAB Circuit******* •Amplifier Subcircuit « .SDBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP •Active Element Models • MODEL R12S GASFET(VT0--2, VBI-1.23, RG=0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15. • RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET (VTO- - 2 , VBI = 1.23, RG«0.83, ALPHA-2.3, BETA-3. 1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170. RS-1170, TAU-0.71PS> • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1. TT-.59PS. CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8. IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture 2.3Tau • VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSIN 25 0 POLSE<-2.9 -.3 5PS 5PS 5PS 57.5PS 100PS) VGGB 24 0 -0.3 .TRAN IPS INS .PRINT TRAN V<26) V(23) V(20) V(21) • .END ISAB RI26R912T3 Tracking with Tau Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 * •••••••••»***ISAB Circuit»»»»»»» • BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 V1 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF * ••••••••••End ISAB Circuit******* •Amplifier Subcircuit * . SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP * •Active Element Models .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAO-0.71PS) .MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, * RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) « •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine Nave Tracking at Sampling Aperture Tau • VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 25PS 100PS) VGGB 4 0 -0.3 .TRAN 1PS INS .PRINT TRAN V(25) V<23> V(20> V<21> .END ISAB RH6R912T3 Time Constant Determination • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD •WIDTH OUT-80 • •••••••••••••ISAB Circuit******* • BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP * •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170. RS-1170, TAU-0.71PS) * .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS. CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10-3 * •Input Time Constant Determination VSGB 25 0 -0.3 VRFIN 23 0 -0.6 PWUOPS -.8 0. IPS -.4 100PS -0.4 100. 1PS -0.8 200PS -0. .TRAN 2PS 200PS .PRINT TRAN V(6) V<20> .END ISAB RH6R912T3 Pulse Feedthrough • •Cycle Controls and Listing Options .OPTIONS ITL4=1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT«80 • ••••«******«*ISAB Circuit******* * BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF CRFPAD 23 0 20FF CGPAD 24 0 2OFF LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RRFIN 3 13 50 RGIN 4 14 50 • ••••••««**End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP * •Active Element Models .MODEL RSAG12 GASFET(VTO=-2, VBI=1.23, RG=0.83, ALPHA«2.3, BETA«3.1E"5 + LAMBDA=0.055, CGS0=0.595FF, CGD-0.595FF, CDS=0.0791FF, IS»2.07E-15, • RD=1170, RS=M70, TAU=0.71PS) * .MODEL TD4 D< IS=.312E-12, RS=1745, N=1.1, TT=.59PS, CJO=8.02E-15, + VJ=0.72, EG=1.42, BV=8, IBV=1E-3) * •Independent Sources VDD 2 0 4.5 VSS 10-3 * •Pulse Feedthrough at Vbias * VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 25PS 200PS) VRFB 3 0 -0.6 .TRAN 0. IPS 50PS .PRINT TRAN V<26) V<23) V<20) . END ISAB RI16R912T3 Off Isolation * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* • BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 12 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF * ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models • MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-+ LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, + RD-1170, RS-1170, TAU=0.71PS> • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Off Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 5M VRFIN 23 0 SIN<-0.6 0.2 10GHZ) VSGB 25 0-2.9 .TRAN 2PS 100PS .PRINT TRAN V(23> V(20) V(21) .END ISAB RI16R912T3 Open Switch Tracking * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* « BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF 145 •••*******End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 02 7 8 TD4 66 D3 8 5 T04 66 BPD 5 1 1 RSAG12 90 •ENDS AMP • •Active Element Models • MODEL RSAG12 GASFET<VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170. RS-1170. TAU-0.71PS) * •MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • Sine wave Tracking Open Switch • VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSGB 25 0 -0.3 .TRAN 10PS INS .PRINT TRAN V<23) V<20) V(21> .END ISAB RI16R912T3 Tracking with 2.3Tau Aperture • •Cycle Controls and Listing Options •OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •«««*»******»ISAB Circuit******* * BSS 11 26 6 RSAG12 60 V1 23 6 0 V4 11 20 0 V5 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF * •*«******«End ISAB Circuit******* •Amplifier Subcircuit * .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 S3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models -MODEL RSAG12 GASFET(VTO=-2, VBI-1.23, RG=0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF. IS-2.07E-15. + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8. IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Sine wave Tracking at Sampling Aperture 2.3Tau * VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSIN 25 0 POLSE<-2.9 -.3 5PS 5PS 5PS 53PS 100PS) .TRAN 1PS 1NS .PRINT TRAN V(26) V<23) V(20> V<21> . END ISAB RI16R912T3 Tracking with Tau Aperture * •Cycle Controls and Listing Options -OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* • BSS 11 26 6 RSAG12 60 VI 23 ( 0 V4 11 20 0 V5 25 26 0 • SAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) * .MODEL TD4 D(IS-.312E-12. RS-1745, N-1.1, TT-.59PS, CJO-8-02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture Tau • VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 23PS 100PS) 147 .TRAN IPS 1NS .PRINT TRAN V(26> V(23> V<20) V(21> .END ISAB RI16R922T3 Time Constant Determination • •Cycle Controls and Listing Options •OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 * «**»»*«******ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF * *****«*«»*End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 D1 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP • •Active Element Models .MODEL RSAG22 GASFET(VTO--2, VBI-1.23, RG-0.5, ALPHA-2.3, BETA-2.61E-5 + LAMBDA-0.055, CGS0-1.19FF, CGD-1.19FF, CDS-0.096FF, IS-4.13E-15, + RD-1555, RS-1555, TAU-2.86PS) * .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Input Time Constant Determination * VSGB 25 0 -0.35 VRFIN 23 0 -0.65 PWL(0PS -.8 0.1PS -.4 100PS -0.4 100.1PS -0.8 200PS -0.8) .TRAN 2PS 200PS .PRINT TRAN V(6> V(20) .END ISAB RH6R922T3 Pulse Feedthrough * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •**»**»**««**ISAB Circuit******* • BSS 11 26 6 RSAG22 60 V1 23 6 0 V4 11 20 0 V5 25 26 0 XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF CRFPAD 23 0 20FF CGPAD 24 0 2OFF LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RRFIN 3 13 50 RGIN 4 14 50 • •o********End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 DI 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 . ENDS AMP • •Active Element Models .MODEL RSAG22 GASFET(VTO--2, VBI-1.23, RG-0.5, ALPHA-2.3, BETA-2.61E-5 + LAMBDA-0.055, CGS0-1.19FF, CGD-1.19FF, CDS-0.096FF, IS-4.13E-15, • RD-1555, RS-1555, TAU-2.86PS) • .MODEL TD4 D(IS-.312E-12, RS-174S, N-1.1, TT-.59PS, CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at Vbias • VSIN 25 0 PULSE<-2.95 -.35 5PS 5PS 5PS 25PS 200PS) VRFB 3 0 -0.65 .TRAN 0.IPS 50PS .PRINT TRAN V<26> V(23> V(20> . END ISAB RI16R922T3 Off Isolation » •Cycle Controls and Listing Options -OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 * •••••••••••••ISAB Circuit******* * BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 VS 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF * ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 Dl 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 •ENDS AMP • •Active Element Models .MODEL RSAG22 GASFET(VTO=-2, VBI=1.23, RG=0.5, ALPHA-2.3, BETA=2.61E-5 + LAMBDA=0.055, CGS0=1.19FF, CGD=1.19FF, CDS=0.096FF, IS=4.13E-15, + RD*1555, RS=1555, TAU=2.86PS) • .MODEL TD4 D( IS-.312E-12, RS=1745. N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG=1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Off Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 10M VRFIN 23 0 SIN("0.65 0.2 10GHZ) VSGB 25 0 -2.95 .TRAN 2PS 100PS .PRINT TRAN V(23) V(20> V(21) . END ISAB RH6R922T3 Open Switch Tracking • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 « •••••••••••••ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI 23 6 0 Vi 11 20 0 V5 25 26 0 • XAMP1 20 21 12 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF * ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • -SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 D1 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP * •Active Element Models .MODEL RSAG22 GASFET<VTO=-2, VBI=1.23, RG-0.5, ALPHA=2.3, BETA=2.61E"5 + LAMBDA=0.055, CGS0=1-19FF, CGD-1-19FF, CDS=0.096FF, IS=4.13E-15, + RD=1555, RS=1555, TAU=2.86PS) 150 •MODEL TD4 D<IS=.312E-12. RS=1745, N=1.1, TT*.59PS, GJO=8.02E-15. + VJ=0.72, EG«1.42, BV=8, IBV«1E-3) « •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * Sine wave Tracking Open Switch • VRFIN 23 0 SIN(-0.65 0.2 1GHZ) VSGB 25 0 -0.35 .TRAN 10PS 1NS .PRINT TRAN V<23) V(20) V(21> • END ISAB RH6R922T3 Tracking with 2.3Tau Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4«1000 ITL5=0 LIMPTS=2000 NOPAGE NOMOD .WIDTH OUT=80 • •••••••••••••ISAB Circuit******* * BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF * ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 D1 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP * •Active Element Models .MODEL RSAG22 GASFET(VTO=-2, VBI=1.23, RG=0.83, ALPHA=2.3, BETA=3.1E"5 + LAMBDA=0.055, CGS0=0.595FF, CGD=0.595FF, CDS=0.0791FF, IS=2.07E-15, + RD=1170, RS=1170, TAU=0.71PS) • .MODEL TD4 D(IS=.312E-12, RS=1745, N=1.1, TT=.59PS, CJO=8.02E-15, + VJ»0.72, EG=1.42, BV=8. IBV=1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Sine Wave Tracking at Sampling Aperture 2.3Tau * VRFIN 23 0 SIN(-0.65 0.2 1GHZ) VSIN 25 0 PULSE(-2.95 -.35 5PS 5PS 5PS 53PS 100PS) .TRAN IPS INS .PRINT TRAN V(25) V(23) V<20> V(21> • END 151 ISAB RI16R922T3 Tracking with Tau Aperture » •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS=2000 NOPAGE NOMOD .WIDTH OUT-80 • •***********«ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF • ******«**»End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 DI 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP * •Active Element Models .MODEL RSAG22 GASFET(VTO«-2, VBI-1.23, RG-0.25, ALPHA-2.3, BETA-2.61E-5 + LAMBDA-0.055, CGS0-1.19FF, CGD-1.19FF, CDS-0.096FF, IS-4.13E-15, + RD-1555, RS-1555, TAU-2.86PS) • .MODEL TD4 D< IS-.312E"12, RS-1745, N-1.1. TT-.59PS, CJO-8.02E-16, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture Tau « VRFIN 23 0 SIN(-0.65 0.2 1GHZ) VSIN 25 0 PULSE(-2.95 -.35 5PS 5PS 5PS 23PS 100PS) .TRAN 1PS 1NS .PRINT TRAN V(26) V(23) V(20) V<21) . END ISAB RI36R912T3 Pulse Feedthrough at vbias * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • ••••*********ISAB Circuit******* * BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 60 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF IC--0.6 CRFPAD 23 0 2OFF CGPAD 24 0 20FF LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RRFIN 3 13 50 RGIN 4 14 50 • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP « •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23. RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055. CGSO-0.S95FF, CGD-0.S95FF, CDS-0.0791FF. IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170. RS-705, TAU-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3> • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at vbias • VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 25PS 200PS> VGGB 4 0 -0.6 VRFB 3 0 -0.6 .TRAN 0.25PS 50PS UIC .PRINT TRAN V(26> V(23) V(20> • END ISAB RI36R912T3 Off Isolation at 10GHz * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* • BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 60 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 * ZAHP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dt 6 7 TD4 66 D2 7 B TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 •ENDS AMP • •Active Element Models •MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705. RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-O.595FF. CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D(IS-.312E"12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Off Isolation with 10 GHz Sine RF Input * RSHUNT 23 20 0.5E8 VRFIN 23 0 SlN(-0.6 0.2 10GHZ) VSGB 25 0 -2.9 VGGB 24 0 -0.3 .TRAN 2PS 100PS .PRINT TRAN V(23> V(20) V(21) .END ISAB RI36R912T3 Open Switch Tracking • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 * •••*••••*••»*ISAB Circuit******* « BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 60 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 VS 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF • •*««**«***End ISAB Circuit******* •Amplifier Subcircuit « .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI=1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055. CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, •RD-1170, RS-705, TAU-0.71PS) * .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Sine Have Tracking Open Switch • VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSGB 25 0 -0.3 VGGB 24 0 -0.3 .TRAN 10PS INS .PRINT TRAN V<23> V(20> V(21) .END ISAB RI36R912T3 Tracking at 100PS Aperture * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 * ***«**«****«*ISAB Circuit******* « BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 60 VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF IC--0.6 • ••••••••••End ISAB Circuit*»»»»»» •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TO4 66 BPD 5 1 i RSAG12 90 .ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.59SFF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705. RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, • RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine Have Tracking at Sampling Aperture • VRFIN 23 0 SIN<-0.6 0.2 250MEG> VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 100PS 410PS) VGGB 24 0 -0.3 .TRAN 10PS 4NS UIC .PRINT TRAN V<26) V<23) V<20) V<21> .END ISAB RI36R912T3 Tracking at 25PS Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •**••••••**••ISAB Circuit******* * BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 60 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 9FF IC--0.6 « ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 •ENDS AMP • •Active Element Models • MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF. CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO«-2, VBI-1.23, RG-0.83. ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF. IS-2.07E-15. • RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8. IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture Tau • VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS HOPS) VGGB 24 0 -0.3 .TRAN 2.5PS INS UIC .PRINT TRAN V(26) V(23) V(20> V<21> .END ISAB RI26R912T3 Pulse Feedthrough * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* « BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 60 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF IC--0.6 CRFPAD 23 0 20FF LRFIN 13 23 0.16NH RRFIN 3 13 50 • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL R12S GAS FET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, • RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.IE-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-S + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, • RD-1170, RS-1170, TAU-0.71PS) * .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Pulse Feedthrough at Vbias * VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS) VGGB 24 0 -0.3 VRFB 3 0 -0.6 .TRAN 0.25PS 50PS UIC .PRINT TRAN V<26) V(23) V{20) . END ISAB RI26R912T3 Off Isolation * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 * •••«»»*******ISAB Circuit******* • BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 60 VI 23 6 0 V3 9 10 0 V4 11 20 0 VS 25 26 0 » XAMP1 20 21 12 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 110 39FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SOBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL R12S GASFET<VTO«-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055. CGSO-0.595FF. CGD-0.595FF. CDS-0.0791FF. IS-2.07E-15. + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-S • LAMBDA-0.055, CGSO-0.595Fr, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12. RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV=1E-3> * •Independent Sources VDD 2 0 4.5 VSS 10-3 * •Off Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 0.4E8 VRFIN 23 0 SlN<-0.6 0.2 10GHZ) VSGB 25 0 -2.9 VGGB 24 0 -0.3 .TRAN 2PS 100PS .PRINT TRAN V(23> V{20) V(21) . END ISAB RI26R912T3 Tracking with 100PS Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* * BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 60 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP 1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF IC--0.6 • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit 159 .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 01 6 7 TD4 66 02 7 8 TD4 66 03 8 5 T04 66 BPD 5 1 1 RSAG12 90 •ENDS AMP • •Active Element Models •MODEL R12S GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3. BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU=0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15. + RD-1170, RS-1170, TAU-0.71PS) * •MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS. CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8. IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture 2.3Tau • VRFIN 23 0 SIN(-0.6 0.2 250MEG) VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 100PS 410PS) VGGB 24 0-0.3 .THAN 10PS 4NS UIC .PRINT TRAN V(26> V<23) V(20) V(21) • .END ISAB RI26R912T3 Tracking with 25PS Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • »•••*••*»••»•ISAB Circuit******* * BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 60 V1 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 39FF IC--0.6 • (.•••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL R12S GASFET(VTO--2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF. IS-2.07E-15, + RD-705, RS-1170, TAO-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO—2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-1170. TAO-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS. CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture • VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSIN 25 0 PULSE<-2.9 -.3 5PS SPS SPS 25PS 11 OPS) VGGB 24 0 -0.3 .TRAN 2.5PS INS .PRINT TRAN V(25) V(23) V(20) V<21) . END ISAB RI16R912T3 Pulse Feedthrough • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* • BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 1 1 20 0 V5 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF IC--0.6 CRFPAD 23 0 20FF LRFIN 13 23 0.16NH RRFIN 3 13 50 • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models • MODEL RSAG12 GASFET(VT0--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF. CGD-0.595FF, CDS-0.0?91FF. IS-2.07E-15. + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at vbias • VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS> VRFB 3 0 -0.6 .TRAN 0.25PS 50PS UIC .PRINT TRAN V(26) V{23) V(20) . END ISAB RH6R912T3 Off Isolation • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD • WIDTH OUT-80 * •••••••••••••ISAB Circuit******* • BSS 11 26 6 RSAG12 60 VI 23 6 0 Vt 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit * .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10-3 * •Off Isolation with 10 GHz Sine RF Input ) 162 RSHUNT 23 20 .25E8 VRFIN 23 0 SIN(-0.6 0.2 10GHZ) VSGB 25 0 -2.9 .TRAN 2PS 100PS .PRINT TRAN V<23) V<20) V(21) • END ISAB RI16R912T3 Tracking with 100PS Aperture * •Cycle Controls and Listing Options •OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD •WIDTH OUT-80 • •*«***«****«*ISAB Circuit******* * BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • ZAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF IC--0.6 • ***t*»****End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 . ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3. BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) * .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8. IBV-1E-3) » •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Sine wave Tracking at Sampling Aperture * VRFIN 23 0 SIN(-0.6 0.2 250MEG) VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 100PS 410PS) .TRAN 2.5PS 1NS UIC .PRINT TRAN V(26> V(23) V(20) V(21> .END ISAB RI16R912T3 Tracking with 25PS Aperture « •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •••••••••••••ISAB Circuit******* BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 152FF IC--0.6 • ••••••••••End ISAB Circuit»»«»«»» •Amplifier Subcircuit * • SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP * •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1B-5 • LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-1170, TAU-0.71PS) * .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture • VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSIN 25 0 PULSE(-2.9 -.3 5PS SPS 5PS 25PS 110PS) .TRAN 2.5PS 1NS UIC .PRINT TRAN V(26) V(23> V<20) V(21> .END ISAB RI16R922T3 Pulse Feedthrough • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • •*•••**•••••*ISAB Circuit******* • BSS 11266 RSAG22 60 V1 23 6 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF IC--0.65 CRFPAD 23 0 20FF LRFIN 13 23 0.16NH RRFIN 3 13 50 • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit •SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 Dl 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP • •Active Element Models • MODEL RSAG22 GASFET<VTO--2, VBI-1.23. RG-0.5. ALPHA-2.3, BETA-2.61E-+ LAMBDA-0.055, CGS0-1.19FF, CGD-I.19FF. CDS-0.096FF, IS-4.13E-15. + RD-1555, RS-1555, TAU-2.86PS) • • MODEL TD4 D(IS-. 312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10 -3 • •Pulse Feedthrough at Vbias • VSIN 25 0 PULSE<-2.95 -.35 5PS 5PS 5PS 25PS 200PS) VRFB 3 0 -0.65 .TRAN 0.25PS 50PS UIC .PRINT TRAN V<26) V(23) V(20) .END ISAB RI16R922T3 Off Isolation • •Cycle Controls and Listing Options •OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD •WIDTH OUT-80 • •••••••••••••ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 * ZAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit * •SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 Dl 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 •ENDS AMP * •Active Element Models •MODEL RSAG22 GASFET(VTO--2, VBI-1.23, RG-0.5, ALPHA-2.3, BETA-2.61E-+ LAMBDA-0.055, CGS0-1.19FF, CGD-1.19FF, CDS-0.096FF, IS-4.13E-15, + RD-1555, RS-1555, TAU-2.86PS) 165 •MODEL TD4 D<IS-•312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-B, IBV-1E-3) » •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Off Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 0.5E8 VRFIN 23 0 SIN(-0.65 0.2 10GHZ) VSGB 25 0 -2.95 .TRAN 2PS 100PS .PRINT TRAN V(23) V<20) V(21> . END ISAB RH6R922T3 Tracking with 100PS Aperture * •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5«0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • ****»***»***»ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0 • ZAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIZED 11 0 74FF IC--0.65 • •«********End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 D1 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP • •Active Element Models .MODEL RSAG22 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture 2.3Tau * VRFIN 23 0 SIN(-0.65 0.2 250MEG) VSIN 25 0 PULSE(-2.95 -.35 5PS 5PS 5PS 100PS 410PS) .TRAN 10PS 4NS UIC .PRINT TRAN V(25) V(23) V<20) V(21) .END ISAB RI16R922T3 Tracking with 25PS Aperture • •Cycle Controls and Listing Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH ODT=80 • •••••••••••••ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 VS 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB Circuit Passive and Parasitic Components CFIXED 11 0 74FF IC--0.65 • ••••••••••End ISAB Circuit******* •Amplifier Subcircuit • _ .SUBCKT AMP 3 5 12 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 DI 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP • •Active Element Models .MODEL RSAG22 GASFET<VTO-- 2, VBI-1.23, RG-0.25, ALPHA-2.3. BETA-2.61E-5 • LAMBDA-0.055, CGS0-1.19FF. CGD-1.19FF, CDS-0.096FF. IS-4.13E-15, + RD-1555, RS-1555, TAU-2.86PS) * .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-1S, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture Tau * VRFIN 23 0 SIN(-0.65 0.2 1GH2) VSIN 25 0 PULSE(-2.95 -.35 5PS 5PS 5PS 25PS HOPS) .TRAN 2.5PS 1NS UIC .PRINT TRAN V(26) V(23) V(20) V<21) .END
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Gallium arsenide integrated circuit modeling, layout and fabrication Rutherford, William C. 1987
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Title | Gallium arsenide integrated circuit modeling, layout and fabrication |
Creator |
Rutherford, William C. |
Publisher | University of British Columbia |
Date | 1987 |
Date Issued | 2010-07-21T18:11:58Z |
Description | The object of the work described in this thesis was to develop GaAs integrated circuit modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold circuits. A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance of inverted common drain logic (ICDL) digital integrated circuits compared to other circuit configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width capability of 25 ps with 5 ps rise and fall time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough isolation and minimum sampling switch off isolation of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 µm gate length process approaches the suggested performance guidelines. A mask layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate structure produces a sub 0.5 µm gate length. |
Subject |
Metal semiconductor field-effect transistors Gallium arsenide semiconductors |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Collection |
Retrospective Theses and Dissertations, 1919-2007 |
Series | UBC Retrospective Theses Digitization Project |
Date Available | 2010-07-21 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0065552 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Campus |
UBCV |
Scholarly Level | Graduate |
URI | http://hdl.handle.net/2429/26733 |
Aggregated Source Repository | DSpace |
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