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UBC Theses and Dissertations

Gallium arsenide integrated circuit modeling, layout and fabrication Rutherford, William C. 1987

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GALLIUM ARSENIDE  INTEGRATED  C I R C U I T MODELING, LAYOUT AND  FABRICATION  by  W I L L I A M C. RUTHERFORD A T H E S I S SUBMITTED I N P A R T I A L FULFILMENT THE REQUIREMENTS FOR THE DEGREE OF MASTER OF A P P L I E D SCIENCE  in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF E L E C T R I C A L  ENGINEERING  We a c c e p t t h i s t h e s i s a s c o n f o r m i n g to the required  standard  THE UNIVERSITY OF B R I T I S H COLUMBIA MAY ©  1987  WILLIAM C. RUTHERFORD, 1987  OF  In  presenting  degree  at  this  the  thesis in  University of  partial  fulfilment  of  British Columbia, I agree  freely available for reference and study. I further copying  of  department  this or  publication of  thesis for by  his  or  her  The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3  DE-6(3/81)  that the  for  an advanced  Library shall make  it  It  is  granted  by the  understood  that  head of copying  my or  this thesis for financial gain shall not be allowed without my written  Department  J u ^ e  representatives.  requirements  agree that permission for extensive  scholarly purposes may be  permission.  Date  the  /fl,  1971  ABSTRACT  The object of the work described in this thesis was to develop GaAs integrated c i r c u i t modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold c i r c u i t s . A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance  of inverted common drain  logic (ICDL) d i g i t a l integrated c i r c u i t s compared to other c i r c u i t configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width c a p a b i l i t y of 25 ps with 5 ps rise and f a l l time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough i s o l a t i o n and minimum sampling switch off i s o l a t i o n of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 urn gate length process approaches the suggested performance  guidelines. A mask  layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate i i  structure produces a sub 0.5 Mm gate length.  Ac knowledgement  Our work on the integrated sampling amplifier block was supported by the Defense Research Establishment Ottawa. I thank my supervisor, Dr. L . Young, for his guidance and for suggesting many of the ideas in this work. Mr. Salam Dindo i s to be thanked for his advice concerning layout topology and process optimization. Mr. David Michelson i s to be thanked for his discussions of microwave c i r c u i t considerations. Mr. Bruce Beggs i s to be thanked for his collaboration in developing fine l i n e lithography techniques. Mr. Peter Townsley i s to be thanked for his e f f o r t in getting the f i r s t two runs of selective implant devices working. Mrs. Mary Mager i s to be thanked for instructing Bruce Beggs and myself on the i n t r i c a c i e s of SEM photography. Mr. Martin Lord i s to be thanked for his e f f o r t to get discrete MESFET test fixtures b u i l t by Microtel P a c i f i c Research Ltd. Mr. Hiroshi Kato i s to be thanked for his work on the RSAG process.  iv  Table of Contents ABSTRACT  .  i i  Acknowledgement  iv  L i s t of Tables  viii  L i s t of Figures  ix  Symbol Definitions  xii  L i s t of Acronyms 1.  2.  xvi  Introduction  1  1.1  1  Integrated Sampling Amplifier Overview  Process D e f i n i t i o n , Parameter Extraction and Mask Layout  2.1  14  2.0.1 Process Parameters  14  Process D e f i n i t i o n  15  2.1.1 Process L i s t i n g  16  3.  Schottky Diode Parameter Extraction and Layout  30  4.  MESFET Parameter Extraction and Layout  34  4.1  Alignment Limitations  34  4.1.1 Interlayer Alignment Marks  35  RSAG and Selective Implant Process Parameter Differences  37  4.2.1 Source and Drain Resistance  37  4.2.2 Gate Phase Shift  39  4.3  MESFET Capacitance  41  4.4  MESFET 1 Mm S l i c e Parameters  4.2  5.  42  Switch Considerations and Layout  51  5.1  The Sampling Cycle  54  5.2  Guard and Sampling Gate Biasing Considerations  56  5.3  Hold Capacitance Considerations  56  v  6.  Amplifier Layout  59  7.  ISAB Design and Layouts  66  7.1  Configurations  66  7.2  I SAB Simulation Results  68  8.  9.  Process Monitors and Measured Results  87  8.1  Isolation Monitors  87  8.2  TLMs  87  8.3  Power MESFET  88  8.4  TiW Sheet Resistance  88  8.5  Three Amplifier O s c i l l a t o r  89  8.6  Peaking  8.7  Selective Implant Fabrication Run Results  91  8.7.1  Isolation  91  8.7.2  Doping and Mobility P r o f i l e s  92  8.7.3  SI MESFET C h a r a c t e r i s t i c s  94  Inductor  ...89  Conclusion  96  REFERENCES 10.  97  Appendix A -ICDL Simulations  102  10.1 D i g i t a l Integrated C i r c u i t Simulation  10.2  Overview  102  ICDL Basic C i r c u i t s  105  10.3 Buffer C i r c u i t  107  10.4  110  Inverter  10.5 Buffered Inverter  115  10.6 OR Gate  115  10.7 AND  115  Gate  10.8 Results and their SPICE Simulation REFERENCES FOR APPENDIX A  116 ....119  vi  11.  Appendix  B -Layouts  121  12.  Appendix  C -GASFET S u b r o u t i n e  123  13.  Appendix  D  129  -Simulation  Source L i s t i n g s  vii  L i s t of Tables  Table  Description  Page  1.1  Overall mask pattern die locations.... 12  2.1  Process Parameters  14  2.2  Process Plates  15  4.1  Thin film r e s i s t i v i t y  40  5.1  MESFET parameters switches  for sampling 58  viii  L i s t of Figures  Figure  1.1  Description  Page  Integrated Sampling Amplifier Block configuration  3  1.2  T r i p l e Gate Switch Cross Sections  5  1.3  Overall layout pattern  7  2.1  Nonbevelled PR edge p r o f i l e , no chlorobenzene soak  17  2.2  Bevelled p r o f i l e with chlorobenzene... 19  2.3  N" implant p r o f i l e  20  2.4  SEM photograph of alignment  21  2.5  SEM photograph of 1/Ltm gate before liftoff  2.6  22  SEM photograph of Ijim gate after liftoff  23  2.7  Cross Section of MIM  25  2.8  MESFET Gate Cross Sections..  28  3.1  Schottky diode cross sections  30  4.1  Alignment marks  36  4.2  Cross section of MESFETs  38  4.3  MESFET c i r c u i t model  42  4.4  a)  7r-Gate Layout  43  4.4  b) 7r-Gate Magnified  44  4.5  RSAG 0.5Mm c h a r a c t e r i s t i c s  45  4.6  RSAG lAim c h a r a c t e r i s t i c s  46  ix  4.7  SI c h a r a c t e r i s t i c s  47  5.1  a) T r i p l e G a t e S w i t c h L a y o u t  51  5.1  b) M a g n i f i e d  52  5.2  T r i p l e Gate S w i t c h S l i c e  T r i p l e Gate S w i t c h Equivalent  Circuit  53  5.3  T r i p l e Gate S w i t c h D i s t r i b u t e d  5.4  Single  6.1  Amplifier  Equivalent  6.2  Amplifier  Layout  6.3  Amplifier  Open L o o p DC  6.4  AORT3_9012 Open Loop T r a n s i e n t  6.5  90mn RSAG1_2 A m p l i f i e r  Gate D i s t r i b u t e d  Model..53  S i m u l a t i o n . . . . 55  Circuit  59 60  Characteristic.61 61  DC  Character ist i c s  62  6.6  90/im RSAG1_2 A m p l i f i e r  Step  6.7  90MITI RSAG2_2 A m p l i f i e r  DC  Response..62  Characteristics  63  6.8  90mri RSAG2_2 A m p l i f i e r  6.9  90/im S I 1 _ 2 A m p l i f i e r  Step  Response..63  DC  Characteristics  64  6.10  90MITI S11_2 A m p l i f i e r  S t e p R e s p o n s e . . . . 64  7.1  SI and RSAG I SAB l a y o u t  7.2  MIM ISAB  7.3  RSAG1_2 S i n g l e  7.4  RSAG1_2 D u a l G a t e  7.5  RSAG1_2 T r i p l e G a t e ISAB T r a c k i n g  70  7.6  RSAG1_2 S i n g l e  70  7.7  RSAG1_2 D u a l G a t e Time C o n s t a n t  ...66  layout  67 G a t e ISAB T r a c k i n g ISAB T r a c k i n g  G a t e Time  x  Constant  69 69  71  7.8  RSAG1_2 T r i p l e Gate Time Constant  71  7.9  Pad Pulse Distortion  72  7.10  Single Gate Feedthrough  73  7.11  Dual Gate Feedthrough  73  7.12  T r i p l e Gate Feedthrough  7.13  Guard Gate Source and Drain Voltages..76  7.14  Guard Gate Current  7.15  RI16R912T3 150ps Tracking, 0.6 V Bias.79  7.16  RI16R912T3 150ps Tracking, 0.4 V Bias.80  7.17  RI16R912T3 75ps Tracking  81  7.18  RI16R912T3 25ps Tracking  82  7.19  RI36R912T3 300ps Tracking  83  7.20  RI26R912T3 50ps Tracking  84  8.1  Power MESFET Gate Strip Layout  88  8.2  TiW Stepped Resistor Layout  89  8.3  Test O s c i l l a t o r OFRT3_9013  90  8.4  Amplifier Peaking Inductor  90  8.5  Isolation monitor chip 8.  91  8.6  Isolation monitor chip 5  8.7  SI doping p r o f i l e  93  8.8  SI mobility p r o f i l e . . . . .  93  8.9  S F  _  2 3 6  _ _ 1  4  ..74  77  ...92  *~gate I-V characteristics.94  xi  Symbol Definitions Symbol  Units  I  Mm  mask intra layer skew  *L  Mm  mask inter layer skew  Mm  mask alignment skew  5 LA  Mm  l a t e r a l a l l o y movement  e  F/cm  free space permittivity  GaAs  F/cm  permittivity of GaAs, taken as 12. 9e  5  «A  Description  cm /V-s Hall mobility 2  cm /V-s electron low f i e l d d r i f t mobility J  cm /V-s electron d r i f t mobility 2  0/cm  P Pen  fi/Mm  specific contact  2  resistivity s p e c i f i c resistance, C1 = N +  GaAs to AuGe, C2 = AuGe to TiW. AR  standard deviation of the implant  p  r  ps  S  cm/s  *Bn  V  ©G  rad/Mm  V  fi X  channel t r a n s i t time =  r  saturated electron d r i f t v e l o c i t y ="n s E  Schottky barrier height on n-GaAs  A/V  2  v- •  gate phase s h i f t MESFET model current gain factor channel length modulation hyperbolic  a E  L/v^  s  V/cm  L  Mm  tangent function  v e l o c i t y saturation f i e l d channel  parameter  length xi i  parameter =v /v s  n  t  Mm  apparent  channel  A  Mm  effective  thickness  uniform  profile  channel  thickness LQ  Mm  metallurgical  Lg p  Mm  effective  a  gap  gate  MESFET  or diode  length  source  Schottky  or drain  metal  t o gate  t o ohmic  gap. Z  Mm  gate  width  GD  fF/Mm  gate  to drain  CQg  fF/Mm  gate  to source  DS  fF/Mm  drain  to source  Cgc  fF/Mm  space  charge  C  C  Rp  S  fl/Mm  Schottky  dimension capacitance capacitance capacitance  capacitance  diode  parasitic  series  resistance R  ft  gate  Rg  fl  source  R  fl  drain  G  D  R i s  ft/n  series  resistance  series series  L E C GaAs  resistance resistance  semi-insulating  sheet  resistivity Rg g  H  m  I g D  ^SS  ft mA/V  drain 9 I  D  S  to source  / 3 V  G  resistance  S  mk/nm  drain  mA/Mm  saturated stated  shunt  to source  VQ  drain S  and V  xi i i  current to source D  S  current  at  V-,-  V  i n t e r n a l gate t o source v o l t a g e  V g  V  e x t e r n a l gate to source v o l t a g e  V^g  V  i n t e r n a l d r a i n t o source v o l t a g e  V g D  V  e x t e r n a l d r a i n t o source v o l t a g e  V^g  V  substrate bias voltage  f  Hz  cutoff  V  ( p o s i t i v e ) b u i l t - i n v o l t a g e a t the gate  G  T  frequency = 1/(27rr)  V  p  V  pinchoff voltage =q/e  V  T  V  threshold voltage V =V +V  WQ  Mm  zero gate b i a s d e p l e t i o n  Wi  Mm  the doping p r o f i l e depth a t a doping  T  l e v e l of n  10'  GaAs  /^N(x)xdx  p  bi  width  6  diode i d e a l i t y  factor  N(x)  ions/cm  3  a c t i v a t e d i o n implanted doping  N  ions/cm  3  e f f e c t i v e p-doping s u b s t r a t e  a  profile  concentrat ion N  D  ions/cm  3  e f f e c t i v e uniform p r o f i l e channel doping density  N  max  ions/cm  q  C  n  e/cm  n^  e/cm  NQ  s/cm  3  peak value of doping electron  profile  charge  3  free electron concentration  3  intrinsic  3  free electron concentration  e f f e c t i v e d e n s i t y of s t a t e s i n conduction band  xiv  N  T  s/cm  Q  ions/cm  2  1  t o t a l N" dose  Q_2  ions/cm  2  total N  Q  t o t a l concentration of traps  3  a  ions/cm  +  dose  available dose =/oN(x)dx  keV  N" implant energy  $2  keV  N  RpQ  cm  projected range of the implantation  Rp  cm  effective  +  implant energy  projected range R -AR p0  xv  p  L i s t of Acronyms  Acronym  Meaning  BFL  buffered FET logic  CAD  computer aided design  EBL  electron beam lithography  ID  interdigitated  MBE  molecular beam epitaxy  MESFET  metal semiconductor f i e l d effect transistor  MIM  metal insulator metal  PR  positive photoresist  RD  refractory diode  RIE  reactive ion etch  RSAG  refractory self aligned gate  ISAB  integrated sampling amplifier block  SD  selective implant diode  SEM  scanning electron microscope  SI  selective implant  SPICE  simulation program with integrated c i r c u i t emphasis  TD  two implant diode, SD on N  xvi  +  1. INTRODUCTION The purpose of this work was  to investigate the design,  simulation and fabrication of GaAs devices and in particular of a GaAs sample and hold device. The work was  sponsored by  the Defense Research Establishment Ottawa.  1.1 INTEGRATED SAMPLING AMPLIFIER OVERVIEW One of the target applications for integrated GaAs sample and holds i s a microwave a c q u i s i t i o n system or d i g i t a l radio frequency memory(DRFM)[1.1]. This involves sampling a microwave frequency  signal on an input delay l i n e at regular  distributed points. Ideally the entire unit would be constructed on a single chip, complete with microstrip delay l i n e , pulse generator, c o n t r o l l e r c i r c u i t s , and analog to d i g i t a l conversion. The primary purpose of the simulation, layout and fabrication i s to investigate and optimize, as far as possible within the confines of the available process parameters, the performance of the integrated sampling amplifier (ISAB). The most important  aspects of the ISAB are  a low input time constant, i d e a l l y less than 25ps, combined with minimal strobe "blow-by". In previous published work Saul[1.2] demonstrated a MESFET switch ring approach with greater than 40dB of i s o l a t i o n and an acquisition time of 2ns  "OFF"  suggesting  operation up to 250MHz. Sample pulse "blow-by" or feedthrough  was minimized by c a r e f u l chip and c i r c u i t layout 1  2 to minimize  c a p a c i t i v e c o u p l i n g . Sample s t r o b e  feedthrough  r a n g e d f r o m a w o r s t c a s e o f a b o u t 80mV t o a n a v e r a g e o f a b o u t 20 t o 30 mV on a 2.5V s i g n a l c o r r e s p o n d i n g 40dB o f s t r o b e  isolation  A 1/zm S I t r i p l e input time per  constant  from t h e sampled  t o about  signal.  g a t e MESFET s w i t c h ISAB w i t h a 65ps was b u i l t a n d t e s t e d t o 500 M e g a s a m p l e s  s e c o n d , u s i n g a 36MHz s i n e - w a v e i n p u t by G.S. B a r t a a n d  A.G. R o d e [ 1 . 3 ] . I s o l a t i o n  i n t h e "OFF" s t a t e was a b o u t 40dB  w i t h a MHz b a n d i n p u t . S a m p l e s t r o b e b l o w - b y was -35mV on a 300  mV s i g n a l , c o r r e s p o n d i n g  The  t e s t e q u i p m e n t was c o n s i d e r e d  capability an  t o 18.6dB o f s t r o b e inadequate  isolation.  f o r the f u l l  o f t h e d e v i c e . I f t h e MIM c a p a c i t o r was  input time  constant  omitted  o f about 33ps would r e s u l t , c l o s e t o  t h e d e s i r e d s p e c i f i c a t i o n . However a b s e n c e o f t h e MIM c a p a c i t o r would l i k e l y  result  i n a reduction of strobe  i s o l a t i o n below t h e a l r e a d y m a r g i n a l  specification.  Work a t U.B.C. by D u r t l e r a t t e m p t e d t o e x t e n d t h e r e s u l t s o f B a r t a a n d Rode u s i n g a s i n g l e a n d d u a l  gate  switch configurationf1.4]. The  I S A B c o n f i g u r a t i o n , shown i n f i g u r e  of e i t h e r  a single, dual or t r i p l e  gate  1.1, c o n s i s t s  sampling  switch  f o l l o w e d by a MIM o r i n t e r d i g i t a t e d h o l d c a p a c i t o r a n d an a m p l i f i e r . Due t o t h e l o w a c q u i s i t i o n  time,  c o n f i g u r a t i o n v a r i a t i o n s are designed  to i n v e s t i g a t e the  r e l a t i v e m e r i t o f MESFET " g u a r d g a t e s " Fig.  1.1) i n s u p p r e s s i n g  signal  path.  sampling  switch  (BSG1 a n d BSG2 i n  strobe feedthrough  to the  3 The a m p l i f i e r BFL  inverter,  i s , i n i t s open l o o p form, e s s e n t i a l l y  shown w i t h t h e ICDL m o d e l i n g  A p p e n d i x A. F e e d b a c k i s a c h i e v e d by a d d i n g MESFET(BFB) w i t h s o u r c e and d r a i n ,  s e c t i o n of another  in parallel  with the  i n p u t MESFET a s shown i n F i g . 1.1. The a m p l i f i e r developed  a  was  t o e n a b l e c a s c a d i n g a n d i s t r e a t e d e x t e n s i v e l y by  D.P. H o r n b u c k l e , R.L. V a n T u y l a n d D.B.  Estreich  [1.5,1.6,1.7,1.8]. The MESFET i n t e g r a t e d s a m p l i n g s w i t c h a n d a m p l i f i e r b u i l t a n d t e s t e d by G. S. B a r t a a n d A. G. R o d e [ 1 . 3 ] , fabricated  was  i n SI p r o c e s s t e c h n o l o g y , w i t h t h e Nminus c h a n n e l  i m p l a n t t h r o u g h a 100nm s i l o x V * - 0 . 8 V. The l i t h o g r a p h i c T  f i l m y i e l d i n g V =-1.5 V o r p  r e s o l u t i o n was ^um l i n e s a n d Ijxm  gaps f o r t h e t r i p l e gate s t r u c t u r e r e s u l t i n g  i n an  Fig.  configuration.  1.1 I n t e g r a t e d S a m p l i n g  Amplifier  Block  "ON"  4 resistance of 120S2 at V =0 V for a 100Mm width, or gs  12000ft/Mm. The base RC input time constant calculated from this i s 36ps as compared to the 65ps input time constant arrived at with 90% sampling e f f i c i e n c y with a 150ps strobe. If the system i s considered as a simple RC network with a switch input step height V  h 0  such that 5V=V -V i  and the capacitor i n i t i a l l y at then V (t)=V -6Ve" / t  h0  h  r  i  and 90% of 6V  is lost in t=2.3r. This would imply an input time constant of 83ps for the switch, as compared to the measured 65ps. However the MESFET I^g i s not linear with V^g and the strobe can be driven to 0.5*  V providing more node charging  current. The amplifier output stage diode stack employs diodes fabricated using gate metal on N* GaAs, reducing the series resistance(Rp ) per unit width of the forward biased stack S  diodes. A 150fF MIM  capacitor was  formed by using 100 nm of  sputtered s i l i c o n n i t r i d e over an AuGe base plate resulting in a t o t a l of about 300fF sample node capacitance and a droop rate of 4 mV/ns.  The use of external capacitors  induces excessive ringing due to lead inductance[1.2]. The amplifier had a measured 3dB bandwidth of 1.1GHz with unity gain feedback and a measured system slew rate of 800 The aim of the present project was  V/MS.  to extend the work  of Barta and Rode by modeling and implementing an ISAB in refractory self aligned gate(RSAG) technology  using  lithographic resolution of 1/im l i n e and 2um gaps as shown in figure 1.2. As the RSAG process i s a t-gate technology  the  5  SI I urn line lum gap  RSAG lum line 2um gap 3-  —•t=  RSAG 0.2um line 0.2um gap  TiW Nplus  Fig.  1.2  Schottky  AuGe  T r i p l e Gate Switch Cross S e c t i o n s .  r e s u l t i n g submicrometer gate w i l l e x h i b i t a reduced  Cg  S  which s h o u l d reduce the d i s p l a c e d charge d u r i n g s t r o b e o p e r a t i o n and The  i n c r e a s e the strobe i s o l a t i o n to over  input time c o n s t a n t  should be reduced  by d e c r e a s i n g  the  r e s i s t a n c e per Mm with the s e l f a l i g n e d i n t e r g a t e Nplus  "ON"  implant. C o n s i d e r i n g the t r i p l e gate s t r u c t u r e s of 1.2  20dB.  four s e r i e s p a r a s i t i c  sheet  r e s i s t a n c e r e g i o n s w i l l have a  r e s i s t a n c e r e d u c t i o n of about 5 times which should  reduce "ON"  r e s i s t a n c e by  Rode. Thus the same width triple  figure  15 to 20% compared to B a r t a  and  switch RSAG v e r s i o n of the SI  gate ISAB s h o u l d have a 55ps input time c o n s t a n t  about 25dB of s t r o b e i s o l a t i o n . Strobe  with  i s o l a t i o n c o u l d then  be s a c r i f i c e d by r e d u c i n g the node c a p a c i t a n c e to b r i n g the input time constant  i n t o the 25ps range. T h i s i m p l i e s that  6 operation  up  t o 20GHz w o u l d be p o s s i b l e w i t h t h e t r i p l e  c o n f i g u r a t i o n . D u a l and  s i n g l e gate c o n f i g u r a t i o n s would  have lower input time c o n s t a n t s , of the  w h i c h i s the main  RSAG p r o c e s s  has  been d e m o n s t r a t e d f o r  digital  i n t e g r a t e d circuitsC1.9,1.10,1.11 ] of short gate g a t e l e n g t h down t o l e s s t h a n 0.1um  obtainable  w i t h 300nm o p t i c a l  linewidthst1.4]. Considering 1.2,  t i m e s and  Cg  "ON"  the  0.2wm EBL  implies that operation  t h e RSAG TiW  i s more r e s i s t i v e gates should  l i t h o g r a p h y capable  r e s i s t a n c e w o u l d be  w o u l d be p o s s i b l e As  are of  r e d u c e d by a b o u t  up  w i t h good s t r o b e or tungsten  t h a n SI  of ten  RSAG  cross  to s e v e r a l hundred isolation.  silicide  gate m e t a l i z a t i o n  g a t e m e t a l i z a t i o n s RSAG  be d r i v e n a t one  1um  t r i p l e gate  about 5 t i m e s compared t o the o t h e r  S  section. This GHz  widthdOmn)  u s i n g e l e c t r o n beam  l i t h o g r a p h y ( E B L ) . D e v i c e s w i t h 0.5/um g a t e l e n g t h  figure  priority  work.  The  and  gate  switch  o r more t - j u n c t i o n s , s i m i l a r  t o power MESFETs. In order Schottky  t o f a b r i c a t e RSAG MESFET I S A B s w i t h low  diodes  f o r the a m p l i f i e r output stage  and  R  p s  MIM  c a p a c i t o r s , e i g h t mask l a y e r s w e r e n e c e s s a r y . I n t e r d i g i t a t e d h o l d c a p a c i t o r s were u s e d i n t h e a l t e r n a t i v e t o t h e MIM  type  the  mask l a y e r and  e l i m i n a t i o n o f one  w h i c h w o u l d be  significant  and  ISAB l a y o u t s a s  shown i n f i g u r e 1.3  for  i f successful w i l l  f o r the  s y s t e m . O n l y t h e r e f r a c t o r y and clarity.  an  an  increase  result in  yield,  single chip acquisition  Schottky  in  metalizations  are  7  Lithographic plate process related layout v a r i a t i o n s are designed t o enable f a b r i c a t i o n of high working devices, with manufacturable layouts with drain or  performance  t o l e r a n c e s . As such SI  ~\nm g a t e l e n g t h s a n d 2 , 3 , o r 4nm s o u r c e a n d  t o g a t e g a p s a r e c o m b i n e d w i t h s i x RSAG l a y o u t s w i t h 1  2Mm g a t e mask l e n g t h s a n d 2, 3 , o r 4 /zm s o u r c e a n d d r a i n  *  II A mSm m SI BS C-. 8% D - SI 8ft  61 8- • A • A A afi" a&" 8% • • A A • • A A  P mmm e- 8%  eft da * i eft £ £ Fan H eft eft ela £ eft G-s 8G> eft £ H * 9fr e& 8% da e& eft •  1 A 8- 8ft  J  A K A  L A 1  e-  8ft 9- SB* B •  eft  2 3  4  Fig.  4-  +::+ j + +  r  •I  5  6  •  1.3 O v e r a l l l a y o u t  « «  va •'•  7  A  £  A  H§ JJL  8  pattern.  a  •  M  II  8- 6- M A" >••» fill  £  V  •  6! 81 1 ••  =. 1 9 10  8 to gate gaps, for a t o t a l of nine basic MESFET variations. It was necessary to leave approximately  300MITI  channels  between the device die to enable nondestructive separation with a narrow blade saw, assuming a cutting channel of about 100  Mm  and a chipping width of about  requirement  40Mm  This  [1.12].  served to motivate compaction of the device pad  frame in order to maximize the number of ISAB units in the l i t h o g r a p h i c a l l y optimal inner 60% of the overall pattern[1.13]. A modified pad frame may be necessary in the discrete phase of the project to enable  later  automatic  probing. Conversely the one chip acquisition system would have minimal pad requirements  enabling c i r c u i t compaction  within the l i m i t s of the transmission line  geometries.  The f i r s t mask layer i s used to control an alignment etch in the surface about 2Mm deep to provide a reference for  a l l subsequent layers. The second layer provides holes  through which to implant the active regions for MESFET channel c h a r a c t e r i s t i c s (N~). The third layer provides a pattern for the t-gate top for the RSAG process, protecting regions of TiW from removal. The fourth layer provides an implant mask for the N  +  regions.  The f i f t h mask i s for ohmic contact to the N  +  regions  and production of MIM bottoms and inductors over nonactivated substrate. The sixth layer i s a positive overlay mask protecting the MIM insulator Si3N  4  dielectric  from etching, (which could be eliminated). The seventh mask is for SI Schottky metalization providing a high quality  9 interface for N* diodes and MESFET gates. This metalization serves a dual purpose as the MIM capacitor top plate. The eighth mask defines openings which are to be gold plated to a few Mm for airbridge bodies and bonding pad thickening. The N~ mask can be used with negative photo r e s i s t for implant i s o l a t i o n i f necessary. The overall pattern outer dimensions are approximately 8.8mm high by 9.2mm across. Test patterns for process c a l i b r a t i o n and device characterization are around the outer edge of the pattern. The devices are l i s t e d in table 1.1 with alphanumeric  grid reference to figure 1.3. The t r a i l i n g  grid reference characters(L,R,T,B) top and bottom of the addressed  refer to the l e f t ,  cell.  Loc  Item  Description/Code  A A A A A A A A A A A A B B B B  1 2 3LT 3LB 3R 4 5 6 7 8 9L 9R 1 2 3LT 3LB  diagnostic a m p l i f i e r diagnostic a m p l i f i e r RD diagnostic diode RD diagnostic diode RD diagnostic diode amplifier amplifier amplifier switch switch switch L C calibration diagnostic a m p l i f i e r diagnostic a m p l i f i e r TD diagnostic diode TD diagnostic diode  AORT2_9024 AORR2_9024 5Mm Lg 10Mm Lg 3 M m Lg AFRT3_9024 AFRT3_9023 AFRT3_9022 R2_40_1_2 R3_60_1_3 0 1 2  B B B B B B B  3R 4  TD diagnostic diode amplifier amplifier amplifier switch 100Mm test FET 100Mm test FET  5  6 7 8 9L  O__  R  inductor test AORT3_9024 AORR3_9024 5Mm Lg 10^m Lg 3Mm Lg AFRT3_9014 AFRT4_9014  AFRR3_9012 R3_60_1_2 SF_100_1_3 S F 100 1 4  right,  10 B 9R B 10 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9L C 9R C 10 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9L D 9R D 10 E 1 E 2 E 3 E 4 E 5 E 6 E 7 B 8 E 9L E 9R E 10 F 1 F 2 F 3 F 4 F 5 F 6 F 7 F 8 F 9L F 9R F 10 G 1L G 1R G 2 G 3 G 4 G 5 G 6 G 7 G 8 G 9L G 9R  100Mm t e s t F E T f a t FET inductor switch ISAB amplifier amplifier amplifier ISAB 1 0 0 M m t e s t FET 100**m t e s t F E T 100t*m t e s t F E T f a t FET inductor switch ISAB amplifier amplifier amplifier a l i g n m e n t mark 1 0 0 M m t e s t FET 100Mm t e s t F E T 1 0 0 M m t e s t FET f a t FET stepped r e s i s t o r switch ISAB ISAB ISAB ISAB ISAB '-gate FET -gate FET "•-gate F E T f a t FET stepped r e s i s t o r switch ISAB ISAB ISAB ISAB ISAB ff-gate FET ff-gate FET "•-gate F E T f a t FET i s o l a t i o n monitor i s o l a t i o n monitor switch ISAB ISAB ISAB ISAB ISAB -gate FET "•-gate FET "•-gate F E T ff  ff  RF_100_2_4 RSAG normal large center R2 60 2 2 RM16R924T3 AFRT3 9013 AFRT4 9013 AFRR3~9013 RM16R922T3 SF 100 1 2 RF 1 0 0 ~ 1 4 RF~100~2_3  RSAG no N p l u s small center R3 60 2 4 RMT6R923T3 AFRT3 9012 AFRR2~6012 AFRR2~6013 RF 1 0 0 1 2 RF 100~1 3 RF_100~2~2  SI on N p l u s TiW 3 s t e p R1 60 2 2 RM16R914T3 RM16R913T3 SI3S912T3 SI2S912T3 SI1S912T3 RF 236 1 4 SF 236 1 2 RF_236_2_4 SI n o r m a l TiW 3 s t e p R3 60 1 4 RI16R913T4 RI16R912T3 RI34R612T3 RI36R912T3 RI36R913T3 RF 236 1 3 SF 236~1~3 RF~236~2_3 SI~on b o t h l a t e r a l 10Mm by 150mi gap vertical R2 60 1 2 RI16R913T3 RI16R912R3 RI26R912T3 RI26R913T3 SI1S913T3 RF 236 1 2 SF 236~1~4 RF 236~2 4  11  G H H H H H H H H H H H I I I I I I I I I I I  i s o l a t i o n monitor f a t FET switch ISAB ISAB ISAB ISAB ISAB d u a l gate FET dual gate FET d u a l gate FET i s o l a t i o n monitor f a t FET switch ISAB a l i g n m e n t mark ISAB 3 amp o s c i l l a t o r power FET d u a l g a t e FET d u a l gate FET dual gate FET meander f a t FET switch ISAB ISAB ISAB modulator dual gate s w i t c h dual gate s w i t c h d u a l gate FET d u a l g a t e FET d u a l gate FET meander F a t FET switch switch switch switch switch switch switch switch switch f a t FET SD d i a g n o s t i c d i o d e  lateral RSAG n o r m a l R3 40 1 2 RI26R922T3 RM16R912T3 SI3S913T3 SI2S913T3 SI1S914T3 RMPR 1 2 SMPR 1 2 RMPR~2~2 vertical RSAG no N p l u s R1 60 1 2 RI16R924T3  SD d i a g n o s t i c d i o d e  3 Men L  L 3  SD d i a g n o s t i c d i o d e  10Mm L  L L L L L L L  airbridge test transmission line transmission l i n e diagnostic amplifier diagnostic amplifier MIM c a p a c i t o r MIM c a p a c i t o r  AuGe under b r i d g e on Nminus on b o t h AORT4 9024 AORR4_9024 a r e a 5 by 100*411 a r e a 6 by 60Mm  J  J J J J J  J J J J J  10 1 2 3 4 5 6 7 8 9L 9R 10 1 2 3 4 5 6 7 8 9L 9R 10 1 2 3 4 5 6 7L 7R 8 9L 9R 10 1 2 3 4 5 6 7 8 9L 9R  J K K K K K K K K K K L 1 L 2T L 2B 4 5T 5B 6 7 8T 8B  RI16R914T4  OFRT39013 dfet-500Mm RMPR 1 3 SMPR 1 3 RMPR~2_3 AuGe SI on N p l u s R1 60 1 3 RI16R923T3 RI16R922T3 RI16R914T3 M26R912T3  rm2 40 1 2 rm2 40 1~3  R M P R 1~4~  SMPR~1 4 RMPR_2_4 SI g a t e m e t a l SI on Nminus R1 60 2 3 R3~60 2 2 R1 60 2 4 R1 60 1 4 R2 60~1~4 R2 60 1~3 R2~60~2~4 R2 60 2 3 R3_60_2~3 SI on b o t h 5 Mm L s  s  s  12  L  9 T  Interdigitated capacitor MIM c a p a c i t o r transmission l i n e  L 9B L 10  14 h a l f p a i r s  200^m l o n g  a r e a 50,000Mm' on N p l u s  Table 1.1 O v e r a l l mask p a t t e r n d i e l o c a t i o n s  Device codes, f o r the most p a r t , serve the d u a l purpose of CAD data base f i l e name and u n i t The type,  description.  switch i d e n t i f i c a t i o n code begins w i t h the p r o c e s s  'R' f o r RSAG and 'S' f o r S I , f o l l o w e d by the number of  g a t e s , the gate width over the a c t i v e r e g i o n , the mask gate l e n g t h and the s o u r c e / d r a i n t o gate gap i n Mm. The ir-gate FET code begins with the p r o c e s s type f o l l o w e d by 'F', the gate width over the a c t i v e r e g i o n , mask gate l e n g t h and s o u r c e / d r a i n t o gate gap. The d u a l gate FET code begins with the p r o c e s s type f o l l o w e d by the logo "MPR" of the t a r g e t test  facility,  M i c r o t e l P a c i f i c Research, then mask gate  l e n g t h and s o u r c e / d r a i n t o gate gap. For  the a m p l i f i e r s the f i r s t two c h a r a c t e r s i d e n t i f y  c o n f i g u r a t i o n as open l o o p 'AO' or feedback  'AF' f o l l o w e d by  the MESFET process type. The next two c h a r a c t e r s a r e the diode p r o c e s s type, 'T' f o r SI gate metal on Nplus, and the number of diodes i n the s t a c k . The f i r s t two of the l a s t four d i g i t s  i n d i c a t e the output stage MESFET width, f o l l o w e d  by the mask gate l e n g t h and s o u r c e / d r a i n t o gate gap. The  ISAB code s t a r t s with the s w i t c h p r o c e s s type  f o l l o w e d by the h o l d c a p a c i t o r type, 'M' f o r MIM and ' I '  for  i n t e r d i g i t a t e d , the number of gates i n the s w i t c h , a s i n g l e digit  r e p r e s e n t a t i o n of the s w i t c h gate w i d t h ( i e . 6 f o r  13 60um), t h e a m p l i f i e r MESFET p r o c e s s t y p e , a s i n g l e representation  of t h e output stage w i d t h d e .  digit  9 f o r 90mn),  t h e n s o u r c e / d r a i n t o g a t e and i n t e r g a t e gap f o r b o t h t h e s w i t c h and a m p l i f i e r , and f i n a l l y number o f d i o d e s i n t h e s t a c k .  t h e d i o d e p r o c e s s t y p e and  2. PROCESS D E F I N I T I O N , PARAMETER EXTRACTION AND MASK LAYOUT Process from  p a r a m e t e r s r e q u i r e d f o r l a y o u t were  p r e v i o u s work, then a d j u s t e d by c a l c u l a t i o n  process  2.0.1  PROCESS PARAMETERS 2.1 r e p r e s e n t s a v e r a g e d  data  a t U.B.C. a n d S a d l e r [ 2 . 2 ] a t C o r n e l l concerning  Dindo[2.1]  University,  Source  Value  3-io« « / •  si  2.2 '10''  Qi •i sht1  v  from  S i i o n i m p l a n t e d p r o c e s s i n g o f LEC GaAs.  Parameter  R  for current  requirements.  Table  R  estimated  T  [2.1] ions/cm  J  [2.1]  100 keV  [2.1]  1542 « / •  [2.1]  -1.97  [2.1]  V  V  P  2.67 V  [2.1]  R  P1  85 nm  [2.1]  A R  44.2  P1  [2.1 ]  nm  114  nm  [2.1]  1  244  nm  [2.1]  max1  1.27-10"  [2.1]  Q2  2-10"  [2.2]  *2  150 keV  [2.2]  sht2 R A  320  [2.2]  110 nm  [2.2]  96 nm  [2.2]  max2 N p l u s t o AuGe P  5.2-10"  [2.2]  65 tt/«n  [2.2]  W  0  W  N  R  p 2  R p 2  N  AuGe t o TiW P  c 2  ions/cm'  J  c 1  78  n/Mn  T a b l e 2.1 P r o c e s s  14  [2.2]  l  Parameters  15 2.1  PROCESS D E F I N I T I O N  P l a t e d e f i n i t i o n s used f o r f a b r i c a t i o n c o n s e q u e n c e o f ISAB f e a t u r e s a n d t h e m . The  ( T a b l e 2.2)  the process  are  steps to  a build  p l a t e s c a n be u s e d w i t h d i s c r e t i o n t o i n c l u d e o r  omit d e v i c e f e a t u r e s f o r a g i v e n p r o c e s s  run.  Plate  Name  Description  1N  Align  2N  Nminus  3N  TiW  4N  Nplus  5N  AuGe  6P  Dielectric  7N  Schottky  A l i g n E t c h p a t t e r n f o r subsequent layers. The Nminus i m p l a n t i s t h e same f o r a l l FBTs and D i o d e s a c t i v e r e g i o n . D e f i n e s t - g a t e and a l l TiW not etched. D e f i n e s t h e N p l u s i m p l a n t window a l l o w i n g s e l e c t i v e FET fabrication. D e f i n e s ohmic c o n t a c t s and MIM c a p a c i t o r bottoms. Si3Ng c a p a c i t o r d i e l e c t r i c i s e t c h e d back t o PR i s l a n d s . S c h o t t k y SI FET, TD d i o d e m e t a l , MIM t o p s and a i r b r i d g e f o o t i n g . A i r b r i d g e body, c o n n e c t o r run and b o n d i n g pad t h i c k e n i n g .  8N  ' Airbridge  Table  The  2.2  Process P l a t e s  p l a t e s a r e d e s i g n a t e d by  following process  listing.  The  t h e p l a t e number c o r r e s p o n d s terms of r e l a t i o n  t h e i r p l a t e name i n t h e  letter  "N"  o r "P"  following  to p o s i t i v e or n e g a t i v e i n  o f t h e r e s i d u a l p h o t o r e s i s t on  the  wafer,  u s i n g p o s i t i v e p h o t o r e s i s t , t o t h e e n c l o s e d l a y e r on t h e station left  s c r e e n . "N"  CAD  r e f e r s t o no p o s i t i v e p h o t o r e s i s t ( P R )  i n t h e e n c l o s e d a r e a and ."P"  the enclosed area, being developed  r e f e r s t o PR away  remaining  elsewhere.  in  16 2.1.1  PROCESS LISTING The process allows production of both SI and RSAG  devices concurrently, s p e c i f i c a l l y allowing the use of low resistance two implant  (TD) type diodes for RSAG  a m p l i f i e r s . As process results w i l l be optimized for a given subprocess i n d i v i d u a l ISAB units were constructed from components of the same type with the notable exception of the diode  stack.  The RSAG process should be optimized with respect to ion implantation, TiW thickness, and plasma or reactive 0.5Mm  ion etch parameters, as a result of the 1 and  mask gate lengths, only one may be made optimal on  a given wafer run. These f a b r i c a t i o n parameters should be optimized for switch transient c h a r a c t e r i s t i c s as the main p r i o r i t y as long as t h i s i s consistent with amplifier operation and process y i e l d . Bevelling was found to be necessary  on test pieces  for reducing photoresist edge bead height. If the bevelling i s omitted increased mask to surface gap results in loss of l i n e width control and rectangular edge p r o f i l e as seen in figure 2.1. Process  steps 30 to 57 are similar to those  developed for MMIC manufacturing^.3,2.4]. Problems with implant activation uniformity and d i s l o c a t i o n s due to handling are expected[2.5,2.6].  Step 1  Description Wafer b e v e l l i n g ( t e s t removal:  Fig.  pieces  o n l y ) and s u r f a c e  2.1 N o n b e v e l l e d PR e d g e p r o f i l e , c h l o r o b e n z e n e soak.  layer  no  - d e p o s i t s i l i c o n n i t r i d e o r A l o v e r new w a f e r - s c r i b e and break wafer a s d e s i r e d - s p i n on p h o t o r e s i s t a t l o w rpm - m o u n t p i e c e s t o be b e v e l l e d w i t h b e e s w a x on g l a s s s l i d e o r aluminum b e v e l l i n g f i x t u r e f o r quarters - b e v e l w a f e r e d g e s u s i n g 1.0**m a l u m i n a p o l i s h i n g c o m p o u n d o n p o l i s h e r , h e a t i n g b e e s w a x on h o t plate to rotate  18  -remove PR, beeswax a n d a l u m i n a i n b o i l i n g acetone -use h o t a c e t o n e t h e n t r i c h l o r o e t h y l e n e f o l l o w e d by M i c r o s t r i p t o remove r e s i d u e , t h e n r i n s e i n DI w a t e r -remove p r o t e c t i v e l a y e r w i t h HF - 1 % Alconox s o l u t i o n -DI w a t e r r i n s e - F i r s t e t c h s o l u t i o n : 5:NH OH 2 : H 0 240:DI -DI w a t e r r i n s e - B u f f e r e d HF - 1 0 % NH OH -DI w a t e r r i n s e - N i t r o g e n blow d r y 4  2  2  4  2  P h o t o r e s i s t d e p o s i t i o n f o r alignment - P h o t o r e s i s t t h i c k n e s s : 1.5Wn  3  P h o t o r e s i s t p a t t e r n exposure f o r alignment -Plate: Align -Mask t o PR method: vacuum c o n t a c t  4  P h o t o r e s i s t develop f o r alignment - D e v e l o p e r t y p e MF-316 -Spray a p p l i c a t i o n -DI water r i n s e  5  A l i g n m e n t e t c h o f GaAs s u r f a c e - E t c h s o l u t i o n : 5:NH OH 2 : H 0 4  2  2  etch  etch  etch  240:DI  6  P h o t o r e s i s t removal - B o i l i n g acetone -Boiling isopropanol  7  P h o t o r e s i s t d e p o s i t i o n f o r Nminus - P h o t o r e s i s t t h i c k n e s s : 1.5Mm  8  P h o t o r e s i s t p a t t e r n e x p o s u r e f o r Nminus i m p l a n t - P l a t e : Nminus -Mask t o PR method: depends on work p i e c e  9  P h o t o r e s i s t d e v e l o p f o r Nminus - D e v e l o p e r t y p e : MF-316 -Spray a p p l i c a t i o n -DI water r i n s e  10  Nminus Implant -Species: S i ^ - E n e r g y : *^ keV -Dose: Q i i o n s / c m ' -Wafer t i l t : 11° -Wafer r o t a t i o n : 22° 2  implant  implant  Fig.  2.2  11  B e v e l l e d p r o f i l e with  chlorobenzene  P h o t o r e s i s t removal -Hot M i c r o s t r i p * S h i p l e y L t d . - B o i l i n g acetone - B o i l i n g isopropanol T O  12  Light cleaning etch - E t c h s o l u t i o n : 1:NH OH 1 : H 0 -DI water r i n s e - B u f f e r e d HF - 1 0 % NH OH 4  4  2  2  240:DI  -DI water r i n s e - N i t r o g e n blow d r y 13  R e f r a c t o r y metal d e p o s i t i o n -Method: r f s p u t t e r , A r a t m o s p h e r e , TiW - P r e s s u r e 33 mTorr -RSAG t h i c k n e s s o p t i m i z a t i o n h f  14  Refractory metal surface - B u f f e r e d HF -DI w a t e r r i n s e - N i t r o g e n blow d r y  cleaning  15  P h o t o r e s i s t d e p o s i t i o n f o r t - g a t e mask - P h o t o r e s i s t t h i c k n e s s : 1.5Wn - C r i t i c a l : p r e b a k e t o remove w a t e r t r a c e s . - S p i n on -Softbake  16  P h o t o r e s i s t p a t t e r n exposure f o r t-gate - P l a t e : TiW -Mask t o PR method: vacuum c o n t a c t  Nminus Implant vs. Depth 20 min. annoal. 6 0 * acflv*  a  implanted  +  g. 2.3 Nminus implant  D*pth (nm) annaated  profile  ©  activated  Fig.  2.4  SEM photograph of alignment  17  P h o t o r e s i s t develop f o r t-gate - C h l o r o b e n z e n e soak - D e v e l o p e r t y p e : MF-312 -Immersion -DI water r i n s e  18  T-gate t o p metal d e p o s i t i o n - D e p o s i t i o n method: slow e v a p o r a t i o n  19  P h o t o r e s i s t r e m o v a l and t - g a t e - B o i l i n g acetone - B o i l i n g isopropanol  20  R e f r a c t o r y metal undercut etch - E t c h method: plasma o r R I E -Plasma c o m p o s i t i o n : C F -RSAG e t c h o p t i m i z a t i o n t , A p , A j  liftoff  4  f  21  P h o t o r e s i s t d e p o s i t i o n f o r Nplus - P h o t o r e s i s t t h i c k n e s s : 1.5MB  r  implant  22  F i g . 2.5 SEM photograph of 1/um sampling gate before l i f t o f f 22  P h o t o r e s i s t p a t t e r n exposure f o r Nplus implant - P l a t e : Nplus -Mask t o PR method: vacuum c o n t a c t  23  P h o t o r e s i s t develop f o r Nplus implant - D e v e l o p e r t y p e : MF-316 -Spray a p p l i c a t i o n -DI water r i n s e  24  Nplus implant -Species: S i ^ -Optimization f o r L -Energy: * 2 -Dose: 2  k  2  e  V  G  = 1 **m  F i g . 2.6 SEM Photograph of 1jim gate a f t e r l i f t o f f . Q22 ions/cm* -Wafer t i l t : 11° -Wafer r o t a t i o n : 22° -Optimization f o r L • -Energy: * fceV -Dose: Q21 i o n s / c m ' -Wafer t i l t : 11° -Wafer r o t a t i o n : 22° G  0.5^m  2 1  25  P h o t o r e s i s t removal -Hot M i c r o s t r i p Shipley L t d . - B o i l i n g acetone - B o i l i n g isopropanol  26  T-gate t o p removal  24 -Wet e t c h s o l u t i o n : HC1 -DI water r i n s e - N i t r o g e n blow d r y 27  S i l i c o n n i t r i d e blanket deposition - P l a s m a p r e c l e a n u s i n g : NH3 -Plasma c o m p o s i t i o n : He:500 seem S i H : 5 5 0 seem, NH :37.6 seem 4  3  28  Implant anneal - f u r n a c e : 30 m i n .  800° C  29  S i l i c o n n i t r i d e removal -Wet e t c h s o l u t i o n : HF -DI water r i n s e - N i t r o g e n blow d r y  30  P h o t o r e s i s t d e p o s i t i o n f o r AuGe - P h o t o r e s i s t t h i c k n e s s : 1Mm  31  P h o t o r e s i s t p a t t e r n e x p o s u r e f o r AuGe - P l a t e : AuGe -Mask t o PR method: vacuum c o n t a c t  32  P h o t o r e s i s t d e v e l o p f o r AuGe - C h l o r o b e n z e n e soak - D e v e l o p e r t y p e MF-312 -Immersion -DI water r i n s e  33  AuGe d e p o s i t i o n - D e p o s i t i o n method: e v a p o r a t i o n  34  P h o t o r e s i s t r e m o v a l and AuGe - B o i l i n g acetone - B o i l i n g isopropanol  35  A l l o y AuGe t o N p l u s GaAs - O p t i m i z a t i o n : furnace or r a p i d thermal  liftoff  36  Test process monitors enabled I s o l a t i o n leakage TiW s t e p r e s i s t o r AuGe ohmic meander Transmission l i n e s RSAG t e s t MBSFBTs RD t e s t d i o d e s  37  D e p o s i t i o n o f MIM c a p a c i t o r d i e l e c t r i c : - P l a s m a p r e c l e a n u s i n g : NHj - D e p o s i t i o n method: p l a s m a -Plasma c o m p o s i t i o n : He:500 seem SiH :550 seem NH :37.6 seem 4  3  at this  alloy  stage  Si3N  4  Fig.  38  P h o t o r e s i s t d e p o s i t i o n 813X4 e t c h - P h o t o r e s i s t t h i c k n e s s : 1.5wn - S p i n on -Softbake  39  P h o t o r e s i s t p a t t e r n e x p o s u r e f o r MIM d i e l e c t r i c -Plate: Dielectric -Mask t o PR method: vacuum c o n t a c t  40  P h o t o r e s i s t d e v e l o p f o r MIM - D e v e l o p e r t y p e : MF-316 -Spray a p p l i c a t i o n -DI w a t e r r i n s e  41  D i e l e c t r i c E t c h t o PR i s l a n d s - E t c h S o l u t i o n 20% HF - B u f f e r e d HF -DI w a t e r r i n s e  42  P h o t o r e s i s t r e m o v a l and - B o i l i n g acetone - B o i l i n g isopropanol  43  Photoresist deposition f o r Schottky metalization - P h o t o r e s i s t t h i c k n e s s : 1^m - S p i n on -Softbake  44  Photoresist pattern  dielectric  liftoff  exposure  2.7 Cross Section of MIM  26 - P l a t e : Schottky -Mask t o PR method: vacuum  contact  45  P h o t o r e s i s t develop f o r Schottky - D e v e l o p e r t y p e : MF-312 -Immersion -DI water r i n s e  metalization  46  Schottky metalization deposition - D e p o s i t i o n method: slow e v a p o r a t i o n  47  P h o t o r e s i s t removal and m e t a l i z a t i o n - B o i l i n g acetone -Boiling isopropanol  liftoff  48  Photoresist deposition for airbridge -Photoresist thickness: 1.5Mm  footing  49  P h o t o r e s i s t p a t t e r n exposure f o r a i r b r i d g e - P l a t e : Schottky -Mask t o PR method: s t a n d a r d contact -Exposure wavelength: -Exposure  50  P h o t o r e s i s t develop f o r a i r b r i d g e - D e v e l o p e r t y p e : MF-316 -Spray a p p l i c a t i o n -DI water r i n s e  51  D e p o s i t i o n o f a i r b r i d g e f o o t i n g and p l a t e c o n d u c t i o n metal -Method: r f s p u t t e r , Ar a t m o s p h e r e , Au 3 nm  52  P h o t o r e s i s t d e p o s i t i o n f o r a i r b r i d g e body - P h o t o r e s i s t t h i c k n e s s : 1.5wn  53  P h o t o r e s i s t p a t t e r n e x p o s u r e f o r a i r b r i d g e body -Plate: Airbridge -Mask t o PR method: s t a n d a r d contact  54  P h o t o r e s i s t d e v e l o p f o r a i r b r i d g e body - D e v e l o p e r t y p e MF-316 -Spray a p p l i c a t i o n -DI water r i n s e  55  G o l d p l a t e a i r b r i d g e body - e l e c t r o d e s on exposed edge Au - p l a t e t o few Mm -DI water r i n s e  56  P h o t o r e s i s t removal and p l a t i n g m e t a l i z a t i o n liftoff - B o i l i n g acetone -Boiling isopropanol  footing  footing  27  57  Wafer/Slice  completed  With respect to step 20, plasma etching has a v e r t i c a l to l a t e r a l etch rate v - :v^ v  )  of about 15:1 whereas RIE  1  is 18:1. Referring to figure 2.8 MESFET high frequency performance improvement could be achieved by gate width resistance reduction and capacitance per unit width reduction by maximizing  the TiW cross section available  for conduction and minimizing the Schottky contact length. As the t-top should remain firmly in place for subsequent operations d f , the f i n a l dimension of the t  TiW top, should be maximized with respect to df^, the f i n a l dimension of the TiW bottom. The t-top, i n i t i a l l y h ^ thick and d ^ wide should fc  t  have Rp+3ARp=h £ thickness and kdf =d £, where k i s in t  D  t  the order of 2, after etching to prevent 99% of the implant from reaching the channel[2.2]. Assuming the t-top material 2:v^2 ratio i s the same as TiW and the v  v  etch rates of s i g n i f i c a n t l y l e s s magnitude the approximate maximum TiW thickness (hj) can be calculated for the two mask l i n e widths and both etch processes. Taking as bias B=(d i-d £)/2 - d f and the degree t  t  t  of anisotropy Aj = 1 -VQ_ ^/V -| as Af=1-B/2hj after v  Mogab[2.7] then d = d - ( 1 - A ) 2 h ft  completion, where d completion  m  m  f  f  when etched to  i s the mask gate width and at  )  28  SI12 RSAG1  2  RSAG2_2  TiW A u G e  EM Nminus •  Nplus  Fig. dfj =d . 3  m  Schottky.  2.8 MESFET Gate Cross  I f etching continues  Sections.  u n t i l the base i s ted , or m  l e s s , as r e q u i r e d f o r RSAG d f « d f - & d = t e d - ( 1 - A ) 2 h tc  where d f  i s the c r i t i c a l  t c  t c  limits  c  m  f  f  t o support  df^^djj,  c o n t a c t width, f o r maximum  TiW t h i c k n e s s t o  h *0.025d /[(1-A )]. Neglecting f  m  operations.  as 0 . 9 d f b , where  corresponds t o the Schottky t - t o p support,  m  TiW t o p width l e f t  the t - t o p through subsequent Choosing d f  t  f  t-top etching  hf = 0 . 0 2 5 d v i / v i -j or about 0.45itm f o r RIE and 0.37itm f o r m  v  plasma e t c h i n g of a 1itm d  m  t - t o p . F o r d =2Mm a maximum m  0.75um of TiW can be used with the plasma e t c h and 0.9um  29  with the  RIE. risk  Over e t c h i n g of l o s i n g  the  produces t-tops.  a shorter  gate  length  at  3. SCHOTTKY DIODE PARAMETER EXTRACTION AND LAYOUT The a m p l i f i e r o u t p u t s t a g e d i o d e s t a c k r e q u i r e s which p r o v i d e v o l t a g e l e v e l  diodes  s h i f t i n g with reasonable  t r a n s i e n t p e r f o r m a n c e , compact s i z e and r e l i a b l e f a b r i c a t i o n . C o m p a r i n g t h e TD a n d RD s t r u c t u r e s o f f i g u r e  o) TO Type  [ . . ' [ 'semi-insulating GaAs III]  Nminus ;  mW  TiW  •  Nplus  mi  AuGe;  : : : : : b) RD Type  Fig.  B  Sdniffcy  ::::::::  3.1 S c h o t t k y d i o d e c r o s s s e c t i o n s .  a ) TD S c h o t t k y g a t e m e t a l on N p l u s + N m i n u s b) RD RSAG p r o c e s s  30  31  3.1,  where t h e  10jum f o r t h e used  by  and  i s 1/im  grid"  amplifier  Barta  expense of  "dot  stack  Rode[1.2]  f o r the  cross  top views,  t h e TD  i s more compact  increased capacitance  sections type  but  when compared  at  and  diode the  to the  RD  type. In  the  depletion  forward  width  W diminishes  approaches V ^ . majority  voltages as  144  Richardson  is  s  as  results  b a n d . The  high  to  the  into  the  i s adequate  for  3-1,  in equation  high  [3.1].  [3-1]  effective the  field  implant 0.03.  above a b o u t  diode 0  M  As  of  from  low  condition sets  of  the  in at  about  d e p l e t i o n width  t a b l e 2.1  such  high  e l e c t r o n mass  upper v a l l e y  the  to  the  holds  value  at  for applied  o f A**  is  taken  [3.1].  2  Schottky  and  changes  i n c o n s i d e r a t i o n of  f o r the N "  2  the into  barrier  a p p r o x i m a t e d as W /2i> ,  3 2 0 0 V/cm  barrier  theory  constant  to s c a t t e r i n g  A/cm /K  The  i s due  t h e GaAs under  potential  and  the  applied voltage  transport process  emission  stack  B  3kV/cm, w h i c h bias  the  amplifier  2  c o n d i t i o n s at E  conduction  the  = SA**T exp(-q0 /kT)  s  c h a n g e s due  zero  the  Thermionic  GaAs t h e  field  as  t u n n e l i n g from  semiconductors  I  For  major  r e g i o n over  metal[3.1]. mobility  The  carriers  depletion  b i a s e d mode of  n  s  where  i s adjusted  transit i> =M E s  n  f o r doping  time(TT) s  and  E  level.  s  f o r SPICE i s taken  as  32  The the  parasitic  diode  series  determines  amplifier  diode  resistance.  A s c a n be s e e n  due  t o t h e gap and R  c  depletion Ristaw  s  region. R  i sthe contact  i s the average  s  i scalculated  s  sections i n figure resistance,  R^ i s  r e s i s t a n c e under t h e  after  Kellner,  Enders,  between  i scalculated  c  C V  (R  as t h e sheet  s  the Schottky  R =i/[R  [3-2]  *- t a k e n  resistance  R  the cross  R  s  c  c  from  shunt  s~3^ sht  Where R h t  R  required f o r the  a n d K n i e p k a m p [ 3 . 2 ] v i a e q u a t i o n 3-2.  R  under  width  stack, neglecting substrate  Rp =R +R^+R , where R  width of  S  the total  3.1  S  resistance (Rp )per unit  S S  metal.  R^ i s t a k e n  t h e ohmic  after  ) ] where R  r e s i s t a n c e of the implant  and Schottky  Berger[3.3] c v  as t h e sheet barrier  contacts.  f o r a *\nm s t r i p a s  i s p ^ ( c o n t a c t area)  and R  c  i s  s s  sht2(length)/(width). The  width as  total  series  f o rthe diode  width  Appendix  type  or are  by t h e a r e a diode  f o rthe Schottky  f o r both  diode  per unit factor  taken  specifications in  adequate  the diode, however  t o process  t o ohmic m e t a l  types. Velocity  i n t h e gap a t approximately  2 V across  respect  S  B.  4jum i s u s e d  achieved  i sdivided  included i n the amplifier  A default value of  r e s i s t a n c e due t o t h e R p  or about  saturation i s  1.2 V a c r o s s  the gap,  1.7 V f o r a 3Mm g a p . B o t h  t h e 4Mm g a p b e i n g  yield[3.4].  spacing  Only  more  reliable  the diode  stack  with number  33 and width i s changed to match the diode stack to amplifier c i r c u i t requirements. Diodes were model characterized per unit width for standard gaps of 3 and 4 Mm and Schottky metal length of 3 Mm from alignment and capacitance considerat ions. SPICE model Schottky diode t r a i l i n g numbers are Lg p. a  SPICE input deck format specifies RS as Rp  S  in the following  diode models. .MODEL RD4 D(IS=0.31E—12, RS=3206, N=1.18, TT=0.45PS, + CJO=3.85E-15, VJ=0.72, EG=1.42, BV=8, IBV=1E~3) .MODEL TD4 D(IS=0.31E-12, RS=1744, N=1.1, TT=0.59PS, + CJO=8.02E-15, VJ=0.72, EG=1.42, BV=8, IBV=1E~3)  The cutoff frequency ( f= 1/( 27rR C j) ) i s about 8.8 c  ps  and 11.1 GHz for the TD and RD types, respectively, with a bias of 0 V. Equation 3-3 gives the diode I-V characteristic with the effect of Rp . S  V = IR  p s  + (nkT/q)ln(l/l  s  + 1)  [3-3]  Using data in Table 2.1 and referring to Figure 3.1 the parameters  for a iMm wide diode s l i c e were constructed for  the two types and used for amplifier stack layout calculations in section 6. Ideality factor n i s taken as 1.18 for RSAG and 1.1 for SI. Schottky interface problems were assumed negligible for the layout calculations however can be determined  from the FAT FETs and accounted for later  in simulations[3.5].  4. MESFET PARAMETER EXTRACTION AND The m a j o r l i m i t a t i o n s contact case  optical  LAYOUT  t o MESFET f a b r i c a t i o n  using  mask  l i t h o g r a p h y a r e minimum l i n e w i d t h a n d w o r s t  alignment.  4.1 ALIGNMENT L I M I T A T I O N S Factors and  t h a t dominate l a y o u t a r e i n t e r l a y e r alignment  minimum l i n e w i d t h a n d l i n e  lithography provided width  limit  t o gap r a t i o  alignment If  line  i s 1/xm a n d t h e l i n e t o g a p  r a t i o was f i x e d a t 1:2 f o r mask p r o d u c t i o n and  o f mask  by t h e p l a t e m a n u f a c t u r e r . The  o f t h e c u r r e n t mask  skew  cost,  fabrication  reasons.  t h e mask s e t h a s a t o l e r a n c e o f 8 j (±0.1«xm) [ 4 . 1 ]  l a t e r a l p o s i t i o n w i t h i n a n d ±0.4/xm  ( 6 ) between l a y e r s and L  t h e a l i g n m e n t c a n be m a n u a l l y made t o ±0.5Mm ( 6 ) u n d e r A  optimal be  c o n d i t i o n s [ 4 . 2 ] , a minimum s p a c i n g  allotted  allowed total  to avoid contact.  f o r l a t e r a l movement  of $ j + S  during  alloying  a n d some m i s a l i g n m e n t may o c c u r  vacuum t r a n s f e r p h a s e o f t h e e x p o s u r e  S(6 +8 +  Taking  6  6+  6  L A  )  must  f o r the consuming during the  operation.  = MINIMUM SEPARATION  [4-1]  I  L  L A  a s 0.3/um a n d S a s 1.5 g i v e s a b o u t 2(im minimum  separation  A  A  (8LA) w i t h t h e  alignment assumption, as i t i s a time  manual o p e r a t i o n  S  A f u r t h e r m a r g i n must be  e r r o r t i m e s a s a f e t y f a c t o r (S) t o a c c o u n t  optimistic  + L  b e t w e e n l a y e r s , o r more c o n s e r v a t i v e l y 2.6/xm w i t h 34  35  S a s 2.  Minimum s e p a r a t i o n w i t h i n a l a y e r c a n be r e d u c e d  the compounding e f f e c t spreading  resulting  o f i n t e r l a y e r mask  i n a minimum  skew a n d  by  lateral  s e p a r a t i o n of l e s s  than  "Idem. However p r e v i o u s e x p e r i e n c e a t U.B.C. h a s shown t h a t a 1iim i n t e r g a t e g a p on a m u l t i p l e g a t e RSAG MESFET liftoff  p r o b l e m s i n s t e p 19 o f s e c t i o n 2 . 1 . 1 ,  causes  asymmetric  plasma u n d e r c u t t i n g i n s t e p 20[4.3] and i s h i g h l y demanding process[4.1].  of the c u r r e n t p l a t e manufacturing  4.1.1  INTERLAYER ALIGNMENT MARKS To m a x i m i z e a l i g n m e n t  m a r k s shown i n f i g u r e 4.1 aligner  i s capable  of  o f l a t e r a l movement  t h e n an a l i g n m e n t  20xtm,  a s e t of  were d e v e l o p e d .  o f 160X c o r r e s p o n d i n g  magnification gap  accuracy  a t a 3 Mm  t h e mask a n d w a f e r  alignment  A s t h e mask  at a  t o a mask  t o wafer  checking operation with  g a p o r u n d e r vacuum  a s s i s t e d d i r e c t c o n t a c t , three l e v e l s of alignment are necessary. align  wafer  The f i r s t  t o mask  mark must a l l o w t h e o p e r a t o r t o  orientation  simple stacked s t r u c t u r e w i l l fig.  4.1).  easily,  f o r which a  suffice(corner  brackets i n  The s e c o n d mark s h o u l d a l l o w maximum  alignment  accuracy  smallest v i s i b l e approximately accuracy  mark  200  a t 160X m a g n i f i c a t i o n a t w h i c h t h e  f e a t u r e i s 1.5Mm i n a f i e l d o f by  200Mm.  of the process  The p r o p o s e d  0.5Mm  alignment  c a n o n l y be o b t a i n e d u n d e r  these  c o n d i t i o n s by t a k i n g a d v a n t a g e o f t h e s y m m e t r y d e t e c t i o n capability  o f t h e o p e r a t o r by b a l a n c i n g l i g h t  and  dark  36  F i g . 4.1 Alignment Marks f i e l d s [ 4 . 2 ] of greater than 1.5/im. As such 3 and 4Mm were taken as a 2nd l e v e l gaps. The t h i r d l e v e l mark should be able to take advantage of the 320X objective c a p a b i l i t y of detecting a  0.75Mm  minimum feature[4.2] to check the second mark  alignment under d i r e c t contact  through a 1 to 2Mm  photoresist layer with a depth of f i e l d of 3Mm and a frame of less than 100mn.The inner cross has a 1 or 2Mm gap to compensate the possible interference due to the photoresist, r e s u l t i n g i n the multiple patterns layer.  for each  In order the  t o a c c o m m o d a t e t h e demands o f a l i g n i n g t o  o r i g i n a l alignment etch,  thus t o avoid  any e r r o r t  a c c u m u l a t i o n between l a y e r s , and check m e t a l t o m e t a l a l i g n m e n t , s e p a r a t e a l i g n m e n t marks were u s e d , metal overlays  of previous  metal depositions.  that with positive photoresist  The f a c t  t h e exposed area  t h e c l e a r p o r t i o n o f t h e mask i s s u b s e q u e n t l y away means t h a t t o o b t a i n  including  the l i g h t  field  through  developed  symmetry f o r  s e c o n d l e v e l a l i g n m e n t t h e c l e a r a r e a must s u r r o u n d t h e periphery can  of the e t c h  l i n e by 4Mm. T h i r d l e v e l  alignment  be a c c o m p l i s h e d by a i n t e r n a l e t c h p e r i p h e r y  d a r k mask f i e l d  with a  1/xm i n s i d e i t .  4.2 RSAG AND S E L E C T I V E IMPLANT PROCESS PARAMETER DIFFERENCES As  i s a p p a r e n t f r o m f i g u r e 4.2, RSAG d e v i c e s  same l e v e l  of lithography  a s SI d e v i c e s  should  p e r f o r m a n c e due t o r e d u c e d g a t e l e n g t h and parasitic  have  superior  source/drain  r e s i s t a n c e . E q u a l l y apparent though i s t h e f a c t  t h a t RSAG p r o c e s s g a t e r e s i s t a n c e a  made w i t h t h e  i s much h i g h e r  l o s s o f some o f t h e g a i n e d b e n e f i t w i t h  respect  leading to t o t h e SI  process.  4.2.1  SOURCE AND DRAIN RESISTANCE S o u r c e and d r a i n  resistances are minimized to  minimize the channel t r a n s i t a given R  s  and R  V g. Referring D  D  time(T)  and i n c r e a s e  t o F i g . 4.2 i t c a n be s e e n  h a v e s e v e r a l s e r i e s c o n t r i b u t i o n s . The  I s D  that  a  t  38  F i g . 4.2 Cross Section of MESFETs t r a i l i n g model numbers(ie. RSAG1_2) correspond  to mask  L  is  G  and L  g a p  . The gap resistance R  S g a p  or R  D g a p  calculated by using the applicable Rgheet t i n  1 6 3  t^e  number of squares in the gap, allowing for l a t e r a l d i f f u s i o n during anneal  in the RSAG case. This does not  allow for alignment v a r i a t i o n s . Ohmic contact resistance i s calculated after Berger[3.3]. For the purposes of compaction and layout r e g u l a r i t y for a large number of c i r c u i t v a r i a t i o n s a  39 s t a n d a r d c o n t a c t l e n g t h o f 20iim was s e l e c t e d , h o w e v e r some l a y o u t s a r e a d j u s t e d  4.2.2  slightly.  GATE PHASE S H I F T A "well designed  FET", w i t h r e s p e c t t o g a t e  r e s i s t a n c e , has gate metal  e v a p o r a t i o n onto  layer photoresist f o r lithographic accuracy reliable  liftoff  o f unwanted m e t a l  from a  d e p o s i t i o n [ 2 . 4 ] . T y p i c a l l a y e r s a r e 300 by 0.7 (tn Au p r o d u c i n g thick gold layer  series  thick with  thick  nm o f TiW  a "mushroom g a t e " p r o f i l e .  i s necessary  double  t o decrease  topped The  Rg p e r u n i t  width at high frequency, minimizing gain degradation t o t r a n s m i s s i o n l i n e and s k i n  due  effects[4.4-4.8].  The c u r r e n t g a i n o f a MESFET d e p e n d s on a u n i f o r m voltage acting along the channeKz a x i s ) . shift  I f a phase  of t h e c o n t r o l s i g n a l occurs a l o n g t h e w i d t h of  the gate, the source the channel  to drain flow of electrons  v a r i e s w i t h Z. T h i s e f f e c t  through  i s a r e s u l t of  p h a s e s h i f t due t o t h e t r a n s m i s s i o n l i n e c h a r a c t e r o f the  gate. A second metal  attempted apparent tops  layer  by S a d l e r [ 2 . 2 ] i n t a b l e 4.1,  f o r t h e TiW RSAG g a t e h a s b e e n t o make up f o r t h e d i s c r e p a n c y  l e a v i n g A l , N i , Au, and P t t - g a t e  i n p l a c e d u r i n g a n n e a l i n g . The r e s u l t was  i n t e r d i f f u s i o n and a l l o y i n g and  t h e GaAs". W i t h  anneal  this  "drastic  ... b e t w e e n t h e t o p m e t a l  i n m i n d we c o n s i d e r e d  p r o c e s s i n g as t h e o n l y v i a b l e  refractory  post gate  40 stripe  resistance reduction strategy.  Metal  Bulk  Thin F i l m Estimate  Units  Al Au Ti W  2.56 2.44 41.00 5.60 16.22  5.12 4.88 82.00 11.20 74.61*  jifl-cm MO-cm MO-cm Mfl-cm Mfi-cm  T i  0.3 0.7 w  Table  4.1 T h i n  A post  anneal  film  gate  resistivity.(*  gold p l a t i n g process  c o n j e c t u r e d . An e x t r a f a b r i c a t i o n where a t e m p o r a r y  from  [2.2])  was  s t e p w o u l d be a d d e d  i n t e r c o n n e c t web w o u l d p r o v i d e  c u r r e n t t o the gates. T h i s would cause  plating  electrolytic  p l a t i n g a c t i o n a t exposed a r e a s , but would r e q u i r e p r e c i s e l y a l i g n e d mask w i n d o w s t o p r e v e n t plating. After plating circuit  unwanted  t h e PR w o u l d be r e m o v e d a n d a  s h i e l d i n g mask u s e d t o e t c h t h e p l a t i n g  distribution The  grid.  main problem w i t h t h i s p l a n  alignment  current  a n d minimum l i n e  1.6/im i s e x p e c t e d , 1um i s i n a d e q u a t e  i s p l a t i n g mask  width. Alignment  skew o f  a n d t h e mask minimum l i n e w i d t h o f f o r 0.5/xm RSAG g a t e  lengths.  I t h a s been d e m o n s t r a t e d by W o l f [ 4 . 3 ] t h a t t h e effect  of gate m e t a l i z a t i o n r e s i s t a n c e i sp r o p o r t i o n a l  t o b ? , where b i s t h e g a t e philosophy  w i d t h . As s u c h t h e d e s i g n  o f t h i s p r o j e c t h a s been t o m a x i m i z e TiW  t h i c k n e s s and t h e gate  width with respect  t o t h e maximum  41  frequency or pulse response required of the MESFET. Separate considerations are included for the switch of section 5 and the amplifier of section 6.  4.3 MESFET CAPACITANCE Capacitance due to the depletion layer(C g and C G  G D  varies  with the specific two dimensional geometry of the depletion region, which i s dependent on V g and V g. C g i s considered G  D  D  to be r e l a t i v e l y independent of the depletion region and as such i s treated as a constant. The SPICE 2[4.4] MESFET model proposed by Curtice[4.5] and realized by Sussman-Fort[4.6] models C g as variable and treats C G  G D  as constant. Several  other models have been published some of which are included in the references[4.7-4.11]. In the course of modeling ICDL and other l o g i c s ( p a r t i a l inclusion in appendix A) with the SPICE 2 MESFET model Abdel-Moteleb,  Rutherford and  Young[4.17] included a variable C  for some of the  G D  simulation runs. The MESFET c i r c u i t model with an added shunt  resistor,  due to substrate conduction, appears in figure 4.3. A more accurate capacitance model has been proposed by Golid, Hauser and Blakey[4.13] of which the C  G D  portion has been  included in a version of SPICE 2 (re: appendix B).  42  GATE RG  CGS RS  fFl I  |  SOURCE•  CGD RD DRAIN  CDS  II RSHUNT  MESFET CIRCUIT MODEL UITH SHUNT RESISTOR  Fig. 4.3 MESFET c i r c u i t model 4.4 MESFET 1<xM SLICE PARAMETERS From the process d e f i n i t i o n and parameter estimation procedures nine MESFET SPICE models are maintained for c i r c u i t evaluation. Figure 4.4 a) represents a t y p i c a l industry standard MESFET configuration which i s used as a process benchmark for comparison of our v a r i a t i o n s to each other and MESFETs currently being produced by several manufacturers. Figure 4.4 b) has a 1um dot g r i d superimposed on the magnified layout of the gate connect, as compared to the  100Mm dot grid of figure 4.4 a ) . DC c h a r a c t e r i s t i c s are  accumulated from the 100/zm test MESFET or 236 w-gate array of  figure 1.2 with the use of a semiconductor parameter  analyzer.  43  Fig. The  s i m u l a t e d I-V c h a r a c t e r i s t i c s a r e d i s p l a y e d f o r  100iim w i d t h s i n f i g u r e s In  a) 7r-Gate L a y o u t  4.4  t h e SPICE models  a r e p e r nm.  4.5  t o 4.7  f o r the nine  below a l l w i d t h dependent  S P I C E GGSO a n d CGD  are calculated  constants  at V  = 0 V f r o m t h e n o r m a l s p a c e c h a r g e e q u a t i o n 4-2. the measured  variations.  G S  and  V  Comparing  r e s u l t s o f Van T u y l a n d L i e c h t i [ 4 . 1 4 ]  D S  44  F i g . 4.4 C c  b)  ff-Gate  i s approximately equal t o C  S  Magnified until  G S  t h e MESFET i s b i a s e d  n e a r V Q C * = 0 . 5 V where t h e m e a s u r e d C g i s a b o u t 0 . 6 8 C . G  From  S G  s y m m e t r y CGD i s e q u a l t o CGS u n d e r t h e s e c o n d i t i o n s . The SPICE s i m u l a t i o n then proceeds  t o modify  a c c o r d i n g t o e q u a t i o n s 4-3[4.5] and  C =LZ[q N(x) s c  c  c  £  Gs( gs v  ) s =  / 2 ( V  B  I  CGS0/[1-V  - V  G S  /V  G  B I  S  - V  F  C  H  the i n i t i a l  values  4-4[4.13].  ) ] *  [4-2]  [4-3]  ]*  GD< gs' ds>= v  V  C D0/£ T - ^ G D l V g s - V d s ^ ^ G D ^ G G  5  3 (1-X D2 gs v  G  )  [4-4]  45  RSAG1_4 TEST MESFET  Fig  4.5  RSAG  0.5Mm I-V c h a r a c t e r i s t i e s  RSAG2_2 TEST MESFET  2.4  la  RSAG2_3 TEST MESFET  RSAG2_4 TEST MESFET  4.6 RSAG l M m I-V c h a r a c t e r i s t i c s  SI1_3  TEST MESFET  SI1_4  TEST MESFET  F i g . 4.7 SI 1um I-V c h a r a c t e r i s t i c s  48 The c o n s t a n t s f o r e q u a t i o n 4-4 a r e l i s t e d  i n Appendix  p a r t o f t h e GASFET s u b r o u t i n e s o u r c e c o d e . empirically  f i t t e d w i t h equation [4-5] a f t e r  I =/5(V +V ) d s  g s  i  T  d s  h y p e r b o l i c tangent  Curtice[4.5].  f a c t o r and a i s t h e  o i s used  t o f i t the  r e g i o n and X t h e s l o p e of t h e s a t u r a t i o n r e g i o n .  Rg a n d R .  approximated  by p l o t t i n g  /J=Ip/V * a n d V p  /IJJS  V  S  «  V  GS  a n c  T  are  * accounting  I f d e v i c e s a r e n o t a v a i l a b l e j8 c a n be  D  2 e  is  [4-5]  f u n c t i o n parameter,  g e n e r a l l y determined  0=[  s  d s  The t r a n s c o n d u c t a n c e p a r a m e t e r  for  d  •(1+XV )tanh(oV )  Where X i s t h e c h a n n e l l e n g t h m o d u l a t i o n  linear  I  C as  t h e o r e t i c a l l y a f t e r Chen a n d S h u r [ 4 . 1 5 ] .  GaAs s 3/[ ( P u  w  where A = [ 2 e  A  G a A s  v  + 3 E  m 1 L  ) ]  [  V ]/[qQ ] p  4  and  L =L- ^sinh- {[TK (V  and  the voltage drop across the channel at s a t u r a t i o n i s :  V  i s  K  d  2  ,  =  d  [E L(V s  g s  s  i s approximately  K =AV/(V -V ) d  d s  d s  -V )]/[E L+V T  i s  6  ]  [4-7]  a  1  _  -V  g s  i s  )]/[2AE ]} s  -V ] T  [4-8]  [4-9]  1 f o r s e l f a l i g n e d gates and  f o r S I g a t e s w h e r e AV i s t h e " v o l t a g e d r o p  a c r o s s p a r t o f t h e h i g h f i e l d d o m a i n u n d e r t h e g a t e " . When  49  V  G  = V  S  B  I  the maximum  V  I  =  S  ( E  S  L V  P  Q / ( E  S  L + V  P  Q )  and increase  in I ^ g due to channel shortening i s negligible for c l v  > v s  "is  + 2  volts at this point, /? can be considered independent [ 4 . 10 ] of  V  D  S  >>  V  i s  +2  at  V  G  S  = V  B  I  .  Q  A  i s taken as the implant  activation times the N~ dose for the purposes of i n i t i a l approximation. The following models are the result of layout and process calculations.  .MODEL RSAG1_2 G A S F E T ( V T O = 2 , V B I = 1 . 2 3 , RG=4.97, A L P H A = 2 . 3 , + B E T A = 3 . 1 E - 5 , LAMBDA=0.055, C G S 0 = 0 . 5 9 5 F F , C G D = 0 . 5 9 5 F F , + C D S = 0 . 0 7 9 1 F F , I S = 2 . 0 7 E - 1 5 , RD=1170, R S = 1 1 7 0 , + TAU=0.71PS) -  .MODEL RSAG1_3 G A S F E T ( V T O = - 2 , V B I = 1 . 2 3 , RG=4.97, A L P H A = 2 . 3 , + B E T A = 3 . 1 E - 5 , LAMBDA=0.055, C G S 0 = 0 . 5 9 5 F F , C G D = 0 . 5 9 5 F F , + C D S = 0 . 0 7 3 8 F F , I S = 2 . 0 7 E - 1 5 , RD=1490, R S = 1 4 9 0 , + TAU=0.71PS) .MODEL RSAG1_4 G A S F E T ( V T O = 2 , V B I = 1 . 2 3 , RG=4.97, A L P H A = 2 . 3 , + B E T A = 3 . 1 E - 5 , LAMBDA=0.055, CGS0 = 0 . 5 9 5 F F , C G D = 0 . 5 9 5 F F , + C D S = 0 . 0 7 1 4 F F , I S = 2 . 0 7 E - 1 5 , RD=1810, R S = 1 8 1 0 , + TAU=0.71PS) -  .MODEL RSAG2_2 G A S F E T ( V T O = ~ 2 , V B I = 1 . 2 3 , RG=1.49, A L P H A = 2 . 3 , + B E T A = 2 . 6 1 E - 5 , LAMBDA=0.055, C G S 0 = 1 . 1 9 F F , CGD=1.19FF, + C D S = 0 . 0 9 6 F F , I S = 4 . 1 3 E - 1 5 , RD=1555, R S = 1 5 5 5 , TAU=2.86PS) .MODEL RSAG2_3 G A S F E T ( V T O = ~ 2 , V B I = 1 . 2 3 , RG=1.49, A L P H A = 2 . 3 , + B E T A = 2 . 6 1 E - 5 , LAMBDA=0.055, C G S 0 = 1 . 1 9 F F , CGD=1.19FF, + C D S = 0 . 0 9 4 7 F F , I S = 4 . 1 3 E - 1 5 , RD=1875, R S = 1 8 7 5 , T A U = 2 . 8 6 P S ) .MODEL RSAG2_4 G A S F E T ( V T O = 2 , V B I = 1 . 2 3 , RG=1.49, A L P H A = 2 . 3 , + B E T A = 2 . 6 1 E ~ 5 , LAMBDA=0.055, C G S 0 = 1 . 1 9 F F , CGD=1.19FF, + CDS=0.0791FF, I S = 4 . 1 3 E ~ 1 5 , RD=2195, R S = 2 1 9 5 , T A U = 2 . 8 6 P S ) -  .MODEL S I 1 _ 2 G A S F E T ( V T O = - 2 , V B I = 1 . 2 3 , RG=0.13, A L P H A = 2 . 3 , + B E T A = 2 . 6 1 E ~ 5 , LAMBDA=0.055, C G S 0 = 1 . 1 9 F F , CGD=1.19FF, + C D S = 0 . 0 9 6 F F , I S = 4 . 1 3 E - 1 5 , RD=3228, R S = 3 2 2 8 , T A U = 2 . 8 6 P S ) .MODEL S I 1 _ 3 G A S F E T ( V T O = - 2 , V B I = 1 . 2 3 , RG=0.13, A L P H A = 2 . 3 , + B E T A = 2 . 6 1 E - 5 , LAMBDA=0.055, C G S 0 = 1 . 1 9 F F , CGD=1.19FF, + CDS=0.0847FF, I S = 4 . 1 3 E - 1 5 , RD=4770, RS=4770, T A U = 2 . 8 6 P S ) .MODEL S I 1 _ 4 G A S F E T ( V T O = - 2 , V B I = 1 . 2 3 , RG=0.13, A L P H A = 2 . 3 , + B E T A = 2 . 6 1 E " 5 , LAMBDA=0.055, C G S 0 = 1 . 1 9 F F , CGD=1.19FF, + C D S = 0 . 0 7 9 1 F F , I S = 4 . 1 3 E - 1 5 , RD=6312, R S = 6 3 1 2 ,  50  +  TAU=2.86PS)  V i  i s taken  f a  as 0 . 5 V + 0  B  n  after  Curtice[4.5] allowing  for a voltage drop across r ^ i n t h e conduction the  channel  under  gate. The  t r a n s i t t i m e u n d e r t h e g a t e TAU i s u s e d i n t h e  model t o i n c l u d e t h e d e l a y e d e f f e c t  o f a change i n V g on S  I j j g . I n t h e C u r t i c e [ 4 . 5 ] m o d e l i t i s a c o n s t a n t . TAU i s taken a t V^ mobility  s  - 1 V, u s i n g a c o n s e r v a t i v e a v e r a g e l o w f i e l d  of 3500 cm /V-s, a c r o s s t h e e f f e c t i v e 2  length. This value  i sthen m o d i f i e d d u r i n g program  i n a p r o t o t y p e S P I C E v e r s i o n by d i v i d i n g k i st o prevent transit  time.  channel execution  TAU by V^g+k, w h e r e  d i v i s i o n by z e r o , t o p r o d u c e a n e f f e c t i v e  5. SWITCH CONSIDERATIONS AND Figure  5.1 a ) i s t h e l a y o u t  LAYOUT  fora triple  g a t e RSAG1_2  s w i t c h w i t h a 100/zin d o t g r i d a n d f i g u r e 5.1 b) i s a magnified  view of t h e gate r e g i o n . Assuming t h e e x i s t e n c e of  a ground plane  Fig.  a d i s t a n c e d under t h e m e t a l i z a t i o n , c i r c u i t  5.1 a ) T r i p l e G a t e S w i t c h  51  Layout  52  Fig.  5.1 b) M a g n i f i e d T r i p l e G a t e  Switch  p a r a s i t i c s c a n be c a l c u l a t e d a f t e r Van T u y l , L i e c h t i , L e e and  Gowen[5.1]. Switch sampling  effect and  performance i n v o l v e s t h e combined  o f p u l s e edge p r o p a g a t i o n a n d r e f l e c t i o n  channel  i n the gate  reaction.  In a pulse modulated short channel  MESFET  transient  b e h a v i o r c a n be s i m u l a t e d by a t w o d i m e n s i o n a l mesh model i n f r a c t i o n s of a picosecond  such as performed  by  Faricelli,  F i g . 5.3 T r i p l e Gate Switch Distributed Model  54 F r e y and K r u s i u s [ 5 . 2 ] w i t h r e s p e c t t o d i g i t a l  5.1  THE  logic.  SAMPLING CYCLE  In a sampling c y c l e the s w i t c h i s i n i t i a l l y  h e l d at or  p i n c h o f f by t h e s a m p l i n g p u l s e t r a n s m i s s i o n l i n e b i a s . rising  edge o f t h e p u l s e ramps f r o m V  propagates  r  . The  reflects off  end.  In the channel the p o s i t i v e gate p u l s e causes withdraw  and C .  The  G D  transverse f i e l d  the gate, i n c r e a s i n g  p r o f i l e due  to V  mobile charge  v  v s  -  v  After  C  G S  accelerates  i n the channel from source t o d r a i n  f r o m o r t o t h e h o l d node d e p e n d i n g  hold  to  in  D S  c o m b i n a t i o n w i t h the a l t e r i n g d e p l e t i o n boundary  o f  fields  from the a c t i v e l a y e r , drawing m a j o r i t y c a r r i e r s  from t h e s o u r c e and d r a i n towards  charge  AV  v o l t a g e ramp  down t h e g a t e t r a n s m i s s i o n l i n e a n d  the unterminated  The  t o V j ^ - A V , where  T  i s to prevent forward conduction, i n t  below  moving  on t h e m a g n i t u d e  i n -  25ps t h e down ramp p r o p a g a t e s down a n d  reflects  f r o m t h e u n t e r m i n a t e d g a t e end c a u s i n g f i e l d s t o p e n e t r a t e the a c t i v e potential and C  G D  l a y e r . The  g r a d i e n t t o t h e s o u r c e and d r a i n , d e c r e a s i n g  and  s t a t e . The  m a j o r i t y c a r r i e r s move down t h e C  G S  r e v e r s i n g the s o u r c e c u r r e n t of the p r e v i o u s r a p i d displacement of charge  t h e s o u r c e and d r a i n a r e a s l i k e l y o b s e r v e d v o l t a g e change which s t r o b e b l o w - b y " by B a r t a and  from the c h a n n e l  c a u s e s most o f  i s r e f e r r e d t o as Rode[1.2].  the "sample  to  Ideally  t h e magnitude o f t h e " s t r o b e f e e d t h r o u g h " t o  t h e o u t p u t o f t h e s a m p l e a n d h o l d w o u l d be n e g l i g i b l e . The bandwidth of t h e a m p l i f i e r minimization strobe  s h o u l d be m a x i m i z e d f o r  o f t h e number o f ISAB u n i t s [ 1 . 1 ] .  Thus t h e  f e e d t h r o u g h s h o u l d be m i n i m i z e d a t t h e s w i t c h .  RSAG1_2 Pulse Gate End -0-2  Fig.  5.4  S i n g l e Gate D i s t r i b u t e d  Simulation  }  56  5.2 GUARD AND SAMPLING GATE B I A S I N G CONSIDERATIONS The  operation  of the switch w i t h respect  t o sample and h o l d  i s s u c h t h a t , when t h e s w i t c h  i s on, V g tends t o zero  bringing the hold capacitance  t o a p o t e n t i a l near t h e source  D  p o t e n t i a l . When t h e s w i t c h i s o f f t h e s o u r c e follow excursions  The  supplying a voltage to  i n p u t MESFET. The h o l d c h a r g e l e a k a g e  i n c l u d e MIM o r ID c a p a c i t o r l e a k a g e , amplifier  i s free to  w h i c h do n o t i n a d v e r t e n t l y b i a s t h e s w i t c h  on w i t h t h e c h a r g e d h o l d c a p a c i t a n c e the a m p l i f i e r  while  input leakage amplifier  s w i t c h shunt  and s u b s t r a t e shunt  input bias should  paths leakage,  leakage.  be s u c h t h a t t h e o u t p u t  b i a s i s v e r y c l o s e so as t o enable cascade o p e r a t i o n f o r several  stages. A m p l i f i e r input b i a s i s i n the order of  0.3V , v a r y i n g w i t h t h e s p e c i f i c T  amplifier  component  c h a r a c t e r i s t i c s . A m p l i f i e r g a i n and output swing l i m i t t h e input swing such t h a t the  V^oia  should  vary  by a b o u t 200mV a b o u t  s y m m e t r y b i a s p o i n t . The g u a r d g a t e b i a s s h o u l d  that charging forward  current  conduction,  input s i g n a l  i s maximized without  causing  a b o u t 500 mV a b o v e t h e most  be s u c h gate  negative  excursion.  5.3 HOLD CAPACITANCE CONSIDERATIONS The by  optimum magnitude o f t h e h o l d c a p a c i t a n c e the rate of charging  guideline aperture design.  f o r the aperture  i s the highest  a v a i l a b l e . The  priority  A m p l i f i e r input capacitance  i n p u t MESFET p l u s a s m a l l p a r a s i t i c  i s determined  aspect  i s mainly  Cg  of the S  of the  c o n t r i b u t i o n and as such  57 is a function of V g . Reduction of potential distortion can S  be accomplished  by increasing the ratio of fixed capacitance  to variable capacitance. Fixed capacitance i s from two sources, p a r a s i t i c or layout dependent and MIM or interdigitated structures. The estimated node capacitance for the Barta and Rode ISAB i s 0.3pF of which half i s MIM and the other a combination  of p a r a s i t i c and depletion  layer. The amplifier input width i s 50mn implying Cg g of G  about 60fF combined with the node side guard gate width of 100/im amounting to C rjo~ OfF, with the node at zero v o l t s . 12  S  Parasitic capacitance originates with the layout separations, substrate thickness and d i e l e c t r i c constant. If the ISAB i s mounted on a sheet of conducting epoxy at ground potential the surface metalizations form a MIM capacitor. Substrate thickness i s about 450mn leading to an approximate capacitance per unit area of e 100Mm  2  /d=*25, 700f F/cm . For a 2  GaAs  pad this amounts to about 2.6fF. This would increase  for a thinned substrate design incorporating the entire DRFM acquisition unit including microstrip delay l i n e . The rate of charging for a single gate switch at V determined  D S  is  by switch c h a r a c t e r i s t i c s and V . A multiple G S  gate switch has a lower charging rate due to the added guard channels in series. Barta and Rode[1.2] claim that in a three gate switch "the outside gates serve a shielding function by minimizing the effects of sample strobe blow-by reflected back into the input source and coupled onto the output  signal."  58 Comparative lumped element modeling of this configuration with equivalent input time constant single and dual gate configurations i s shown i n section 7 simulations. The switch s l i c e parameters are accumulated in table 5.1. Figure 5.2 i s the equivalent c i r c u i t of a t r i p l e gate switch s l i c e connected to the amplifier input FET with a fixed capacitance(Cf). The distributed model of the switch incorporates the switch as a set of n s l i c e elements connected to simulate the layout of figure 5.1 as demonstrated in figure 5.3 for n=3.  Notts ICSrTT ID RSAG  CS50 11) if  61 1 1 2 S 1 1 2 62 1 : 2 SI 1 2 2 S i 2 2 62 1 2 2  0.59. 0.59 0.59 1.17 1.17 1.17  TiiAu Selective laciint 31  S S2  1 1 2 1 ! 1 1 2  Mtl S/D Sao  1.17 1.17 1.17 R1.261 0.5 2  VTO  .?  VB!  1.23 4.97 2.J 3.055M5 0.055 0.586 0.566 0.0791 2.07E-O5 1169.7 705.5 0.71  RE ALPHA SETA 'JWDA  CSSO CSD CDS IS RS RD m  Rc (2) OhM 144.2 0.0 IM.:  144.2 0.0 144.2  Rs (3) onus  RH (4) ones  1169.7 705.5 705.5 1555.2 1091.C 1091.0  TMJ (5) usee  705.5 705.5 1169.7 1091.0 1091.0 1555.2  1 6ate to Source Caoacitance i t Vgs=0 V  0.71 0.71 0.71 2.86 2.86 2.86  Contact Resistance 3 Source resistance 4 Drain resistance J C T T t i u v . uiannei Langin/Miuf align  veigtiiy  NESFETJ  144.2 0.0 144.2 RI 2S 0.5 2  1.23 4.97 2.3 3.055EK.3 0.055 0.586 0.5B6 0.0736 2.V7E-05 705.3 705.5 0.7:  3226.2 1542.0 1542.0 R 1.252 0.5  1542.0 1542.0 3228.2 R2.2S1  2.36 2.86 2.B6 R2.2S  R2.2S2  S1.261  S1.262  S1.2S  2  1 2  1 2  1 2  1 2  1 2  -2 1.23 4.97 2.3 3.055E-05 0.055 •}.586 0.536 0.0714 2.07E-O5 705.5 1169.7 0.71  -2 1.23 1.49 2.3 2.615E-05 0.055 1.173 1.173 0.096 4.13E-05 1555.2 1091.0 . 2.86  -2 1.23 1.49 2.3 2.615E-05 0.055 1.173 1.173 0.0847 4.13E-05 1091.0 1091.0 2.86  -2 1.23 1.49 2.3 2.615E-05 0.055 1.173 1.173 0.0791 4.13E-05 1091.0 1555.2 2.86  -2 1.23 0.13 2.3 2.6I5E-05 0.055 1.190 1.190 0.096 4.13E-05 3228.2 1542.0 2.86  -2 1.23 0.128 2.3 2.615E-05 0.055 1.190 1.190 0.0B47 4.13E-05 1542.0 1542.0 2.96  Table 5.1 MESFET Parameters for sampling  1 2  UNITS ut ue  -2 V 1.23 V 0.128 onus 2.3 2.615E-05 A/V-2 0.055 < 1.190 fF 1.190 fF 0.0791 fF 4.13E-05 A 1542.0 ohn 3228.2 ohm 2.86 os  switches.  6. A M P L I F I E R LAYOUT The  amplifier equivalent  realized with feedback  the layout  circuit  o f f i g u r e 6.2. The r e l a t i v e  MESFET w i d t h was t a k e n a s 2 5 % o f BPU a f t e r Van T u y l  [ 2 . 4 ] g i v i n g a b o u t 3dB g a i n .  In the layout  most a f f e c t e d by g a t e m e t a l i z a t i o n driven  o f f i g u r e 6.1 i s  BPU i s t h e MESFET  r e s i s t a n c e , as i t i s not  a t b o t h ends. F o r t h e SPICE t r a n s i e n t s i m u l a t i o n s R Q  i s t a k e n a s 1/3 t h e e n d t o e n d m e t a l i z a t i o n Wolf[4.3] ends  f o r an e n d d r i v e n  resistance  g a t e a n d 1/2 o f t h a t  driven.  •*|rBPu  BLPU  y »>  rt  y »e  u Fig.  u  GNO  VSS  6.1 A m p l i f i e r E q u i v a l e n t  59  Circuit.  after  f o r both  60  F i g . 6.2 Amplifier Layout The -3dB frequency of the amplifier i s determined by pole interaction treated by Hornbuckle and Van Tuyl[1.7], Step response s e t t l i n g time i s a more suitable  performance  measure for sampling. The input step of the simulations i s a 0.1ps t r a n s i t i o n c a r r i e d out about the amplifier symmetry bias point. The step amplitude i s chosen to r e f l e c t the maximum excursions of the hold node with respect to keeping the amplifier output l i n e a r .  AORT3_9012 DC Characteristics 3 -.  4 3  2  O  -1  •2 I -1.2  i  1  1  1  -0.8  -1  i—i -0.6  1  i  -0.4  i  1  -0.2  1  O  vm (v)  . 6.3 A m p l i f i e r  Open L o o p DC  Characteristics  A0RT3_9012 Transient  Fig.  6.4 AORT3_9012 Open L o o p T r a n s i e n t  AFRT3_9012 DC Characteristics  VH (V)  6.5 90tim RSAG1_2 Amplifier DC C h a r a c t e r i s t i c s  AFRT3_9012 Transient 2.3  >  0.5  -0.5  4 S ( T b n « 1 0 E 1 0 ) T m i * (*)  g. 6.6 90/xm RSAG1_2 Amplifier Step Response  63  AFRT3_9022 DC Characteristics  Fig.  6.7 90<xm RSAG2_2 A m p l i f i e r DC C h a r a c t e r i s t i c s  Fig.  6.8 90Mm RSAG2_2 A m p l i f i e r  Step Response  64  AFST3_9012 DC  -1.2  Fig.  6.9  -1  -0.8  90iim S11_2  Characteristics  -0.6 Vh (V)  -0.4  -OJ  0  Amplifier DC C h a r a c t e r i s t i c s  AFST3_9012 T r a n s i e n t 3.3 _  15. >  10.5 O -•  -1-3 -i—i—i—i—i—r—i—i—i—i—i—i—I—i—i—i—r—i—i—i— 0 0.2 0.4. 0.6 0.8 1 12. 14. 16. 18. 2 T (V n w 1 0 E 9 ) Hm« (•)  Fig.  6.10  90mn SI1_2  Amplifier Step Response  65 The  Schottky  to maintain supply  diode  s t a c k number a n d w i d t h  about a 1 V per  diode  were chosen  voltage drop f o r a given  voltage d i f f e r e n c e , scaled with V , and t o t a l R p  balance  T  the output  and i n p u t v o l t a g e s . As the  swing i s b i a s e d near the center o f the operating characteristic give cascade The  the output  input  S  to  voltage  i n p u t MESFET  v o l t a g e must c o i n c i d e t o  capability.  a m p l i f i e r t r a n s i e n t and  shown i n f i g u r e s 6.4 t h r o u g h  DC c h a r a c t e r i s t i c s  6.10 f o r t h e  are  tightest  l i t h o g r a p h i c t o l e r a n c e s o f the t h r e e major performance g r o u p s . The f a s t e s t s e t t l i n g RSAG1_2  time  i s l e s s than  200ps f o r  technology.  A m p l i f i e r v a r i a t i o n s were g e n e r a t e d  f o r 30 t o 120ixm  maximum MESFET w i d t h  r a n g e , w i t h 2, 3 a n d 4 d i o d e  both  f o r t h e n i n e MESFET p a r a m e t e r s e t s . The  RD a n d TD t y p e  stacks of  r o l e o f t h e a m p l i f i e r i n t h i s p r o j e c t was t o d e m o n s t r a t e minimum s e t t l i n g  time  f o r t h e DRFM a p p l i c a t i o n , w h i l e  providing a s u i t a b l e adjunct capacitance  f o r the  switch. Variable hold  increases w i t h input width, output  drive  d e c r e a s e s w i t h w i d t h a n d phase s h i f t d e g r a d a t i o n o f t r a n s i e n t p e r f o r m a n c e i n c r e a s e s w i t h w i d t h . The 67iim i n p u t w i d t h has  a C  a  m  p  i  n  the other processes combination  o f about 20fF  f o r RSAG1_N a n d 4 0 f F  a t the r e q u i r e d i n p u t b i a s . The  of guard gate capacitance  t h e a p p r o x i m a t e minimum c a p a c i t a n c e calculations  for  with C  a m  p^  n  f o r input time  for dual and t r i p l e gate  switches.  results i n constant  7. I S A B DESIGN AND LAYOUTS  7.1 CONFIGURATIONS The p o s s i b l e c o n f i g u r a t i o n s i n c l u d e s i n g l e , d u a l a n d t r i p l e gate  switches  of v a r i o u s widths  i n each of t h e nine  v a r i a t i o n s , combined w i t h an a m p l i f i e r process  MESFET  i n t h e same o r o t h e r  v a r i a t i o n . A r e p r e s e n t a t i v e g r o u p o f 28 I S A B  c o n f i g u r a t i o n s were i n c l u d e d on t h e mask w i t h a s u b s e t separate  s w i t c h e s a n d 12 a m p l i f i e r s ( r e : F i g .  Seven SI p r o c e s s  terms of r e s e a r c h center  separated  was g i v e n t o RSAG u n i t s i n  i n t e r e s t . The S I u n i t s e n c o m p a s s  t a p s i n g l e , d u a l and t r i p l e  Fig.  1.3).  ISABs a r e i n c l u d e d w i t h o u t  c o m p o n e n t s , a s on c h i p p r i o r i t y  gate  7.1 S I a n d RSAG I S A B  66  o f 21  switches  layout  140um  i n both  2  67  P  m  s Iterate**}  a-  Fig.  7.2 MIM ISAB  layout  and  3/xm s o u r c e / d r a i n  g a p v a r i a t i o n s w i t h 90um a m p l i f i e r s i n  the  same v a r i a t i o n p l u s one s i n g l e g a t e 4*xm g a p I S A B . The  ISAB l a y o u t on t h e l e f t gap  version,  appendix  page l a y o u t  minimum i n p u t t i m e c o n s t a n t  obtained  c  of which a f u l l  g a t e 2/im  i s included i n  B.  The  in  o f f i g u r e 7.1 i s t h e t r i p l e  by e l i m i n a t i n g  f o r a given  switch i s  a l l fixed hold capacitance,  as seen  e q u a t i o n 7-1.  hold  =  c  fixed  + c  ampin  + c  g uguai ard  + c  switch  + c  parasitic  [7-1]  68 The s w i t c h c o n t r i b u t i o n i s a c o m b i n a t i o n o f C s  a  D  n  d  a s s u m i n g t h e h o l d node i s t h e s w i t c h d r a i n s i d e . A s g a t e s a r e a d d e d t h e r e s u l t i n g d e c r e a s e o f node  C  G D  guard  charging  c u r r e n t makes i n t e r d i g i t a t e d c a p a c i t o r s a more a t t r a c t i v e process  o p t i o n due t o t h e p r o c e s s  MIM  shorts.  7.2  I S A B SIMULATION RESULTS  Taking  the t h e o r e t i c a l l y derived  y i e l d c o n s i d e r a t i o n s of  SPICE model p a r a m e t e r s  from  t a b l e 4.1 a r e p r e s e n t a t i v e s e l e c t i o n o f l a r g e s i g n a l s i m u l a t i o n s were p e r f o r m e d . T h e s e i n c l u d e s i m u l a t i o n s o f e x p e c t e d p u l s e and t r a n s i e n t c o n d i t i o n s i n d i c a t i v e of intrinsic  performance w i t h  ideal  i n p u t c o n d i t i o n s . The  o v e r a l l performance of a c t u a l devices  will  d e p e n d on a c t u a l  i n p u t s and a s s o c i a t e d p a r a s i t i c s as w e l l as t h e  intrinsic  p e r f o r m a n c e h i g h l i g h t e d h e r e . The S P I C E MESFET m o d e l v e r s i o n used has f i x e d C Q accurate increased  D  with a value  capacitance  Figures  S  Q . More  C i r c u i t p a r a m e t e r s f o r t h e SPICE  f o r the s i m u l a t i o n s are i n appendix  7.3 t o 7.5  t r a c k i n g of the three 1GHz  G  m o d e l i n g c a n be done a t t h e e x p e n s e o f  s i m u l a t i o n time.  source l i s t i n g s  t h e same a s C  show t h e s i m u l a t e d  open  D.  switch  t i g h t e s t t o l e r a n c e RSAG I S A B s w i t h a  s i n e wave i n p u t . As t h e number o f g u a r d g a t e s a r e  increased  f i x e d node c a p a c i t a n c e  i s decreased t o compensate,  h o w e v e r a s c a n be s e e n i n f i g u r e s 7.3 t o 7.5 h o l d node a t t e n u a t i o n a n d p h a s e s h i f t  occurs.  significant  F i g . 7.3  F i g . 7.4  RSAG1_2  RSAG1_2  Single Gate ISAB Tracking  Dual Gate ISAB Tracking  70  RI36R912T3 Tracking -OJ -|  F i g . 7.5 RSAG1_2 T r i p l e G a t e I S A B  Tracking  RI16R912T3 Time Constant  T  OJ  Fig.  1 1 1 1 1 0.8 1 1.2 (Hmm 10C-10) T m i * (•) W• * • * > input —  1—1  0.4  1  1  O.S  1  1  1  1.4  1  1  1.8  1  1  1.8  I  7.6 RSAG1_2 S i n g l e G a t e Time C o n s t a n t  RI26R912T3 Time Constant  i—r-i—i  0.2  i  i—i—i—i—i—i—i—•  7.7  0.6  i  0.S 1 12 . 1-4 (1)nt« 1 0 C 1 0 ) T m i * (•) -7^- W a t o p input  Fig.  0.4  RSAG1_2  i  16 .  Dual Gate Time Constant  RI36R912T3 Time Constant 0 3 .3 1  -0.85 A—i—i—r—i—i—i—i—r—i—i—r—T—I—i—i—i—i—i—i— 0  Fig.  7.8  CJ.  0.4  0.6  03 1 1.2 14 . 1.6 13 ( T m i * * 1 0 E 1 0 ) T m i * (•) RT a t o p k i p u t -j- M o d l n o d *  RSAG1_2  2  T r i p l e Gate Time Constant  72 Figures figures  7.6 t o 7.8 u s e t h e same c i r c u i t m o d e l a s  7.3 t o 7.5 w i t h a 0.1ps s t e p  m a g n i t u d e . The i n p u t t i m e c o n s t a n t  i n p u t o f t h e same  i n c r e a s e s w i t h t h e number  of g a t e s from about 40ps f o r 90% s a m p l i n g single  Figure  switches. 7.9 shows t h e s i m u l a t e d d i s t o r t i o n  50S2 t r a n s m i s s i o n  line pulse  g o l d bond w i r e a n d v a r i a b l e  o f an i d e a l  on t h e g a t e p a d due t o a  single  capacitance  Figures  t h r o u g h 7.12 show t h e e f f e c t  feedthrough The  of the gate.  o f g u a r d g a t e s on p u l s e  a t b o t h t h e RF i n p u t s i d e a n d h o l d node  h o l d node v o l t a g e c h a n g e s t o a more n e g a t i v e  s w i t c h c l o s u r e due t o c h a n n e l across  with a  g a t e s w i t c h t o a b o u t 52ps a n d 7 1 p s f o r d u a l a n d  t r i p l e gate  7.10  efficiency  capacitances.  Initially  majority carrier the single  Tim* (•}  Fig.  7.9 P a d P u l s e  v a l u e on distribution  gate switch of  Pulse Distortion  -j— Transmission I n *  side.  —g- Cat* pad  Distortion  73  RI16R912T3 Feedthrough  v  (Hm«  IOC-11)  1km (•)  _  C o t o P u M l  -j,- UT Pod  H o d l n o d *  F i g . 7.10 Single Gate Feedthrough  RI26R912T3 Feedthrough 0.4  F i g . 7.11 Dual Gate Feedthrough  74  RI36R912T3 F e e d t h r o u g h  >  -3 0  4 C o t e "ukM  Fig. figure  -j-  H o t d n o d *  7.12 T r i p l e G a t e F e e d t h r o u g h  7.10 i s open w i t h  s o u r c e a n d d r a i n a t t h e same  p o t e n t i a l a s t h e 1 5 2 f F f i x e d c a p a c i t o r . When t h e s w i t c h ramps c l o s e d  i n 5ps b o t h s o u r c e a n d d r a i n r e c e i v e an  i n j e c t i o n of majority c a r r i e r causing s w i n g . The l a c k o f a v a i l a b i l i t y the  a negative  voltage  of n e u t r a l i z i n g charge f o r  h o l d node p r o d u c e s a s t o r e d n e g a t i v e  o f f s e t of about  0.4V i n v e r s e l y p r o p o r t i o n a l t o t h e node c a p a c i t a n c e . input  side  potential are  The RF  i sneutralized returning to i t s original i n a b o u t 2 0 p s . On s w i t c h o p e n i n g m a j o r i t y  carriers  p u l l e d i n t o t h e channel l e a v i n g a temporary l a c k a t  s o u r c e a n d d r a i n , i n c r e a s i n g v o l t a g e . The r e s u l t a n t t r a n s i e n t decays i n approximately s w i t c h c l o s u r e , about  20ps.  t h e same t i m e a s f o r  75  The  d u a l gate s w i t c h of  g a t e on  t h e h o l d node s i d e w i t h a 3 9 f F  h o l d node s t o r e d n e g a t i v e in  f i g u r e 7.11  o f f s e t of  settling 0.3 41fF  t i m e . The  half  post  from equation  simulation  i s about  152fF+C  s w  ^  t c  j +C 1  a m  pi  4-3.  i s about 36fF,  G S 0  Thus t h e c o m b i n e d  initial +  + <  s i n g l e gate.  t r a n s f e r e d t o t h e h o l d node d u r i n g guard gate C potential  increases responding  G S  + c  fixed  + c  GDguard-  various capacitances across  them a n d  GSguard Cfi  capacitance  x e (  a n d  j and  of t h e  s i n g l e node o f t h e  switch guard  the guard gate of the  t h a t of t h e h o l d  When t h e  c  guard node of  C  a m  two  p^  n  h  a  v  the voltage  s t r o b e down ramp l e v e l s  s u c h t h a t a b o u t -2.1V  GDguard  gate  channel.  switch  charge holding a b i l i t y  T h e  s w i t c h g a t e i s a t -2.9V c  -  be  i s d i r e c t l y p r o p o r t i o n a l to the  the c a p a c i t a n c e .  switch*  by  capacitance a n o  to  t o the change i n  nodes, the  +c  about  s w i t c h down ramp  two  sw  e  a  is  charge i s  t o be h e l d on  g a t e node i s C £ t c h - G S g u a r d ampin  As  d i s p l a c e d c h a r g e can  approximate simulated  G S  gate  The  t h e h o l d node s e p a r a t e d  V  of  G S  to about 47fF.  considered node a n d  the  and  compared  a s  s w  f o r the  longer  distributed  phase of the d u a l  116fF C ^tch -ampin n  the  switch  V a t t h e a m p l i f i e r symmetry p o i n t g i v i n g a C  f o r the  c  The  The  i s reduced  100mV l a r g e r r e q u i r i n g a  guard gate C  capacitance  the  fixed capacitor.  t h e p r e s e n c e o f t h e g u a r d g a t e t o a b o u t one  opening t r a n s i e n t i s about  c  a s i n g l e guard  f i g u r e 7.11  s i n g l e g a t e m a g n i t u d e o f f i g u r e 7.10.  The  has  b  o  u  t  + 0  -  5  a r e a b o u t +0.8  nodes t h u s h o l d s  v  V.  o  l  t  s  The  is a  across  cross  distributed  l e s s charge than  s i n g l e s w i t c h I S A B . The  off  "blow-by"  the  76 displacement charge channel charge  i s t h e same h o w e v e r , t h u s some o f t h e  i s b e i n g n e u t r a l i z e d by a n o t h e r  source of  c a r r i e r s . The most o b v i o u s p a t h f o r t h e s e c a r r i e r s  i s from  the b i a s supply through the guard gate Schottky diode. F i g u r e 7.13 shows t h e v o l t a g e a t t h e g u a r d node b e t w e e n t h e s w i t c h and t h e g u a r d gate f o r a d u a l g a t e s w i t c h , w i t h t h e same t r a n s i e n t c o n d i t i o n s a s f i g u r e 7 . 1 1 . The g u a r d v o l t a g e drops injected  suddenly  i n response  to electrons  node  being  f r o m t h e s w i t c h . The v o l t a g e f r o m g a t e t o s o u r c e o f  the guard gate reaches about  0.9 V, c a u s i n g e l e c t r o n s t o  t u n n e l t h r o u g h t h e S c h o t t k y b a r r i e r . F i g u r e 7.14 shows t h e guard gate current i n c r e a s e i n the p o s i t i v e going p u l s e , c o r r e s p o n d i n g t o t h e s t r o b e down ramp. The n e g a t i v e g o i n g c u r r e n t p u l s e i s m a i n l y due t o c a p a c i t i v e c o u p l i n g , a n d a s  RI26R912T3 G u a r d Gate S o u r c e a n d D r a i n 1  0.3 -,  0.2-I  (TbriM 10E-11) ^  Fig.  guard nod*  Tim*  (•)  ^  7.13 G u a r d G a t e S o u r c e  hold nod*  and D r a i n V o l t a g e s  77  RI26R912T3 Guard Gate Current  tOE-11) Tlm» (•)  (TWIM  Fig.  7.14 Guard Gate Current  such i s missing the conduction e f f e c t . The t r i p l e gate switch of figure 7.12 exhibits a reduced RF pad transient due to i t s guard gate and a larger hold node swing than either the single or dual gate switch. The reason for the increased hold node swing i s reduced hold node capacitance in an attempt to improve the input time constant. The hold node capacitance i s thus mainly composed of guard gate and amplifier input depletion capacitance which varies with hold node voltage. Unfortunately the t r i p l e gate switch i s both slower in terms of input time constant and as a result of minimal fixed capacitance at the hold node not as good in terms of hold node  feedthrough.  While the single gate switch i s predictably the fastest in terms of input time constant the dual gate exhibits about  78 one  h a l f the  feedthrough, at the a m p l i f i e r input  v o l t a g e , w i t h a 30% Figures similar  7.15  time constant  t o 7.20  2ns  i n t e r v a l s as  strobe pulse width  strobe  pad  input bias  input  i s biased  t r a n s f e r p o i n t . T h i s can  research 20%  pad  resulting  i n a symmetrical  Figure  7.15  Due  than The  strobe  "ON"  shows s a m p l e d same l e v e l  to the  as  stored  i n p u t by  7.18  aperture.  The  200mV a s  amplifier  shows t h a t t h e  sampling  t o h o l d node t r a n s i e n t s and  as  efficiency  is lost.  i s 50ps It  should  pass f i l t e r  such t h e i r  l i m i t e d w i t h m i n i m a l s a m p l e and  by c h o o s i n g  still  f i g u r e 7.18  n o t e d t h a t t h e a m p l i f i e r a c t s a s a low  degradation  7.16  s i n g l e g a t e ISAB 90%  bias  output.  s i m u l a t i o n r e s o l u t i o n of  be  changing the  seen i n f i g u r e  s u c h some o f t h e h o l d node d e t a i l  magnitude can  the  a b o u t 200mV b e l o w i t s s y m m e t r y  t r a c k s when o p e r a t e d b e l o w t h e  respect  sponsor.  i s at the  f i g u r e 7.3.  1 rather  of the  be c o r r e c t e d by  o f t h e RF  be  the  are at  o f f s e t a t t h e h o l d node a f t e r s w i t c h c l o s u r e  amplifier  as  pulses  simulations. Figure  the unsampled t r a c k i n g of  and  R o d e [ 1 . 3 ] u s i n g a 36MHz s i n e  r i s e time i s t a k e n as  i f t h e RF  negative  and  s u g g e s t e d by  f o r a l l the  tracking  increase.  show s a m p l e d t r a c k i n g c o n d i t i o n s  t o t h o s e of B a r t a  wave i n p u t , h o w e v e r t h e  bias  output hold  the a m p l i f i e r frequency  with  signal  response  appropriately. Figure pulses.  7.19  shows t r i p l e  Signal divergence  h o l d node v o l t a g e  gate t r a c k i n g with  300ps  p r o b l e m s were e n c o u n t e r e d , where  w o u l d c o n s i s t e n t l y r i s e when  using  79  Fig.  7.15  RI16R912T3  150ps T r a c k i n g ,  0.6 V  Bias  F i g . 7.16 RI16R912T3 150ps Tracking, 0.4 V Bias  F i g . 7.17 RI16R912T3 75ps Tracking  82  I  I  I  I  I  I  I  I  A  Fig.  7.18  RI16R912T3  25ps T r a c k i n g  I  I I I  83  Fig.  7.19  RI36R912T3  300ps  Tracking  Fig.  7.20  RI26R912T3  50ps T r a c k i n g  85 narrower pulses. Figure  7.20  shows d u a l g a t e t r a c k i n g a t  5 0 p s , c l o s e t o t h e 90% s a m p l i n g constant.  a spreading  of  effect  on t h e p o s i t i v e g o i n g  feedthrough  half cycle. This  i s n o t s e e n on t h e s i n g l e g a t e t r a c k i n g s i m u l a t i o n s  s i d e guard gate b i a s with respect The g u a r d g a t e v o l t a g e  i s fixed  cause i s h o l d  t o t h e h o l d node  decrease as the source/drain  s w i t c h by t h e a c t i o n o f t h e s t r o b e  e x p e l l e d from the  i s relatively  guard gate source/drain  negative  offset  voltages  i s l e s s , however o n l y  due t o t h i s a s t h e c a p a c i t a n c e  thus the stored  c h a n g e i s o n l y a few f F . The s i d e guard  gate  b i a s o f t h e h o l d node a s  this  will  d e p e n d on t h e i n i t i a l  will  determine the p o s i t i o n of the negative  t r a n s i e n t on t h e  v o l t a g e a x i s o f f i g u r e 7.13. The more n e g a t i v e  diode  c o n d i t i o n s . Thus f e e d t h r o u g h voltage.  t h e peak t h e  t h e amount o f n e u t r a l i z i n g c h a r g e p a s s i n g  guard gate Schottky  more  s l i g h t c h a n g e w o u l d be  n e u t r a l i z i n g c h a r g e i n j e c t e d by t h e h o l d  the  constant.  i s a v a i l a b l e a t t h e h o l d node w i t h  negative  greater  capacitance  p o t e n t i a l s i n c r e a s e and  v i c e v e r s a . The amount o f c h a r g e i s b e i n g  capacitance  voltage.  i s c a u s e d by c h a n g i n g  o r d r a i n p o t e n t i a l s . The d e p l e t i o n r e g i o n  Greater  node  such t h a t any d e p l e t i o n  r e g i o n v a r i a t i o n or gate conduction  will  time  s w i n g o f t h e i n p u t s i n e wave a n d  f i g u r e s 7.16 t o 7.18. The p r o b a b l e  source  input  B o t h f i g u r e s 7.19 a n d 7.20 e x h i b i t  c o m p r e s s i o n on t h e n e g a t i v e  effect  efficiency  under forward  through  biased  i s l e s s w i t h lower  hold  node  86 The amplifier bandwidth i s instrumental in determining the peak feedthrough voltage. Comparison of devices should thus be done on the basis of similar amplifier bandwidth. The amplifier bandwidth of Barta and Rode[1.3] i s in the order of 1GHz whereas the RSAG1_2 amplifier bandwidth i s in the order of 3GHz. The simulations were done with fixed C Q at C g Q which D  is a reasonable approximation  G  for V Q near 0 V and low V D  D S  .  More accurate capacitance simulation would be very unlikely to reduce the 200 to 800mV feedthrough transients of the simulations an order of magnitude to compare d i r e c t l y with the experimental 35mV feedthrough of Barta and Rode. The discrepancy would seem to be with the pulse parameters of the experimental setup compared to ideal pulses combined with transient response of the amplifier and measuring system compared to the simulated version.  8. The  PROCESS MONITORS AND  early verification  enhances f a b r i c a t i o n used,  and  characteristics  t r o u b l e s h o o t i n g . Test probes can  ideality  c h a r a c t e r i s t i c s and  ISOLATION MONITORS  The  i s o l a t i o n monitors in figure  1.3)  sheet  r e s i s t a n c e c a n be  (at coordinates G  implant  1L, G  1R  by a gap  to test  the  DC  checked.  ,G  a r e o h m i c p a d s on c o m b i n e d N m i n u s  implants separated  substrate  be  f a c t o r . A t t h e same t i m e MESFET  metal  8.1  Nplus  of d e v i c e  a s s o o n a s AuGe o h m i c s a r e p r e s e n t , t o v e r i f y  activation  10  MEASURED RESULTS  10,  H  and  nonactivated  f o r r e t e n t i o n of the s e m i - i n s u l a t i n g sheet  r e s i s t a n c e of about 3-10*O/n i n both c r y s t a l d i r e c t i o n s r e s p e c t t o the major f l a t . some r e a s o n  Should  this  isolation  i t i s p o s s i b l e t o i n c o r p o r a t e an  be  less  with for  isolation  implant[8.1].  8.2  TLMS  The  three transmission l i n e s  contact  L 5B,  L  10) m e a s u r e  r e s i s t a n c e o f t h e AuGe o h m i c p a d s t o t h e  possible anneal  ( L 5T,  implant combinations  characteristics.  t h e d a t a a n a l y z e d by for accurate  use  The  for calibration  pad  of  results.  87  three process  g a p s a r e m e a s u r e d by  of the t r a n s m i s s i o n l i n e  the  SEM  and  model[8.2]  88 8.3 POWER MESFET The gate of an open drain power MESFET should be driven with the l a s t amplifier output. A power MESFET  requires  airbridges for the i n t e r d i g i t a t e d gate architecture. This architecture could be expanded to a dual gate configuration for output sampling to a time domain transmission  multiplexed  l i n e . A single gate version power MESFET has  been included on the mask for f a b r i c a t i o n evaluation.  [8.3].  8.4 TIW SHEET RESISTANCE The stepped r e s i s t o r pattern used to determine TiW sheet resistance i s shown i n figure 8.2. The actual segment widths can be measured by SEM and the r e s i s t i v i t y calculated a f t e r [2.2].  F i g . 8.1 Power MESFET Gate S t r i p Layout  89  F i g . 8.2 TiW Stepped Resistor Layout \  8.5 THREE AMPLIFIER OSCILLATOR Airbridges were used to construct a three amplifier ring o s c i l l a t o r to v e r i f y simulation. The RSAG1_3 MESFET was used as a base unit to increase the probability of a l l three amplifiers working. 8.6 PEAKING INDUCTOR The amplifier frequency response can be improved by adding a pole with a peaking inductor in series between the input and output stages.[1.8]  r  F i g . 8.4  A m p l i f i e r Peaking  Inductor  91  8.7 SELECTIVE IMPLANT FABRICATION RUN RESULTS  8.7.1  ISOLATION The  i s o l a t i o n monitors are two 150*im square pads on  Nplus GaAs separated  by a 15/um gap of SI GaAs. Figure  8.5 shows the current and resistance plots for a low voltage scan of the monitor on test chip 8. Considering the p o s i t i v e voltage side a diode c h a r a c t e r i s t i c appears with a series resistance i n the order of 15k£2 implying a sheet resistance of 150kJ2/n. Figure 8.6 from chip 5 shows about 5MJJ series resistance corresponding to about 50MR/n of i s o l a t i o n which i s an improvement over chip 8 however does not match the expected semi-insulating value of 300MJ2/n. Switch "OFF" i s o l a t i o n and hold mode I  R (UA)  145.9  MARKER (- .6000V . -2.B65UA . 209E+03 ) .  1  i  (n ) 232.0 E+03  14.59 /div  23. 15 /div  .0000  .4476  -2.000  V  0 .4000/div  ( V)  2.000  F i g . 8.5 I s o l a t i o n monitor chip 8  92  MARKER {-  .BOOOV . - 7 . 5 1 7 n A  V  Fig. leakage  .  1Q6E+Q6 )  .4000/div  ( V)  8.6 I s o l a t i o n m o n i t o r  a r e t h e two most c r i t i c a l  chip 5  performance aspects of  isolation.  8.7.2 DOPING AND MOBILITY P R O F I L E S Using  t h e f a t FET a t g r i d p o s i t i o n K-1 o f f i g u r e  1.3 on t e s t c h i p 8 t h e d o p i n g  and m o b i l i t y  p r o f i l e s of  f i g u r e s 8.7 a n d 8.8 a r e o b t a i n e d . The N m i n u s i m p l a n t f o r t h i s r u n was a d o s e o f 3 • 1 0 peak d e p t h  i s about  2.6-10<|2 i o n s / c m design  2  1 2  a t 125keV. The  o r about 87%. T h i s i s h i g h e r  than t h e  assumption o f 60%  r e p r e s e n t i n g a 4 5 % i n c r e a s e f o r t h e SI  p r o c e s s , however a n n e a l i n g temperature  2  103nm w i t h a n a c t i v a t e d d o s e o f  simulation calculation  activation  ions/cm  i s performed a t a  f o r t h e RSAG p r o c e s s  lower  w h i c h may r e s u l t i n  Fig.  8.7 S I d o p i n g  profile.  3831  ~1  L  H  L 3112  J j j  Fr  tn \ > \  2334  (M <  £ u  1556  -i  P r p  F M  778. 1  §  h  t t  a t-779.1 .2 DEPTH  Fig.  .5  .3 (MICRONS)  8.8 S I m o b i l i t y  profile.  94 lower a c t i v a t i o n . Mobility  i s close to the assumed value  of 3500 cm /V-s. 2  8.7.3  SI MESFET CHARACTERISTICS The measured I-V c h a r a c t e r i s t i c s of figures 8.9  8.10  and  are 236um width ir-gate MESFETs for which industry  s p e c i f i c a t i o n s are a v a i l a b l e . Three versions of t h i s device are present on each chip, corresponding source/drain gaps of 2, 3 and 4um.  IO  The published device  3.2000V , 31.10mA . (mA)  /  CURSOR  31.13  3.113 /div  r LINE1 LINE2.  I  1  fy  .0001 .0000  Fig.  to  3.500 .3500/div ( V) 1/GRAD Xintercept' Yintercept! • i 78.3E+00 12.0E-03 : -154E-06  YDS  GRA3  •••  12.BE-03 15.9E-06  ;  52 . 9E-rQ3, - 1 . 9 5 E + 0 3 ,  31.0E-03 \  8.9 SF_236_1_4 7r-gate I-V c h a r a c t e r i s t i c s , V ^-2.7V,  lDSS"  T  3 0 m A  95  ID  (RIA)  MARKER  71.70  7.168 /div  .0228 .0000  VDS  ,3000/div  3.000  ( V)  F i g . 8.10 SF_236__1_2 j r - g a t e I - V c h a r a c t e r i s t i c s , DSS ' I  a  V =*-3.7V, T  7 0 m A  specifications  of manufacturers have a V  T  and  I Q S S  t o l e r a n c e t y p i c a l l y ranging from -4 to -2V and 30 t o 70mA r e s p e c t i v e l y . SI  The measured c h a r a c t e r i s t i c s  d e v i c e s a r e i n t h i s range.  of our  9 . CONCLUSION Sample and h o l d c y c l e s , pulses,  with ideal switch  i n d i c a t e a s i n g l e g a t e 0.5/im MESFET  integrated  sampling a m p l i f i e r  time c o n s t a n t , lithography,  and l i k e l y  c a p a b l e of  block w i l l  strobe  switch  have t h e b e s t  be t h e o n l y u n i t ,  at  successful operation  this  input  level  of  w i t h 25ps  pulses. The m e c h a n i s m s by w h i c h MESFET s w i t c h g u a r d g a t e s affect  s a m p l e and h o l d s w i t c h o p e r a t i o n h a v e been  d e m o n s t r a t e d by s i m u l a t i o n . r e d u c e d by momentary  Strobe pulse feedthrough  f o r w a r d c o n d u c t i o n of  allowing displaced carriers channel. action  The number o f  tunnel  carriers  out  the guard of  the  i n v o l v e d in the  gate,  switch tunneling  i s g u a r d g a t e b i a s and s i g n a l l e v e l s e n s i t i v e c a u s i n g  some d i s t o r t i o n constant series, of  to  is  of  the output  s i g n a l . The i n p u t  i n c r e a s e s , due t o t h e e x t r a is  i n the o r d e r  of  time  guard c h a n n e l s  30 t o 40% when u s i n g a  in  reduction  h o l d node c a p a c i t a n c e . The a p p l i c a b i l i t y  of  t h e GaAs RSAG p r o c e s s t o  a n d h o l d s w i t c h d e s i g n h a s been v e r i f i e d slice  simulation,  indicating  t a p t o g a t e end d e l a y f o r  by a m u l t i p l e  in the order  a 30Mm w i d t h  96  sample  of  5ps g a t e  t-gate.  gate center  REFERENCES 1.1  L. J . Conway a n d S. L. B o u c h a r d , A m p l i f i e r " , DREO REPORT NO. 8 6 3 ,  1.2  P.H. S a u l , "A GaAs MESFET S a m p l e a n d H o l d S w i t c h , " I E E E J S S C , V o l . S C - 1 5 , No. 3, 2 8 2 - 2 8 5 , (1980)  1.3  G. S. B a r t a a n d A. G. R o d e , "GaAs S a m p l e a n d H o l d IC u s i n g a 3-Gate MESFET S w i t c h , " I E E E GaAs I C S y m p o s i u m , 29-32, (1982).  1.4  W. G. D u r t l e r , "The D e s i g n , S i m u l a t i o n a n d F a b r i c a t i o n o f a G a l l i u m A r s e n i d e M o n o l i t h i c Sample a n d H o l d C i r c u i t , " M.A.Sc. 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C u r t i c e a n d Yong-Hoon Y u n , "A T e m p e r a t u r e M o d e l f o r t h e GaAs MESFET," I E E E T r a n s . ED, ED-28, No. 8, 9 5 4 , (1981). W.R. C u r t i c e a n d R.L. C a m i s a , " S e l f - C o n s i s t e n t GaAs FET Models f o r A m p l i f i e r D e s i g n and D e v i c e D i a g n o s t i c s , " I E E E T r a n s . MTT, MTT-32, No. 12, 1573 ( 1 9 8 4 ) . W.R. C u r t i c e a n d M. E t t e n b e r g , "A N o n l i n e a r GaAs FET M o d e l f o r Use i n t h e D e s i g n o f O u t p u t C i r c u i t s f o r Power A m p l i f i e r s , " I E E E T r a n s . MTT, MTT-33, No. 12, 1383 (1985). P h i l i p L. Hower a n d N. G e o r g e B e c h t e l , " C u r r e n t S a t u r a t i o n a n d S m a l l - S i g n a l C h a r a c t e r i s t i c s o f GaAs F i e l d - E f f e c t T r a n s i s t o r s , " I E E E T r a n s . ED, ED-20, No. 3,  100 (1973) . 4.16  S.E. S u s s m a n - F o r t , J . C . H a n t g a n a n d F . L . H u a n g , "A S P I C E M o d e l f o r Enhancement a n d D e p l e t i o n Mode GaAs F E T s , " I E E E MTT, MTT-34, No. 1 1 , 1115-1119, ( 1 9 8 6 ) .  4.17 I.M. A b d e l - M o t a l e b , W.C. R u t h e r f o r d a n d L. Y o u n g , "GaAs I n v e r t e d Common D r a i n L o g i c ( I C D L ) a n d I t s P e r f o r m a n c e C o m p a r e d w i t h O t h e r GaAs L o g i c F a m i l i e s , " t o be p u b l i s h e d S o l i d - S t a t e E l e c t r o n i c s , (1987). 4. 18  4.19  4.20  J . M i c h a e l G o l i o , J o h n R. H a u s e r , a n d P e t e r A. B l a k e y , "A L a r g e - S i g n a l GaAs MESFET M o d e l I m p l e m e n t e d on S P I C E , " IEEE C i r c u i t s and D e v i c e s M a g a z i n e , 21-30, S e p t . (1985). R.L. V a n T u y l a n d C.A. L i e c h t i " H i g h - S p e e d I n t e g r a t e d L o g i c w i t h GaAs MESFET's," I E E E J S S C , V o l . 9, No. 5, (1974) . T z u - H u n g Chen a n d M i c h a e l S. S h u r , " A n a l y t i c a l M o d e l s o f I o n - I m p l a n t e d GaAs F E T ' s , " I E E E T r a n s . ED, ED-32, No. 1, 18-28, ( 1 9 8 5 )  4.21 S. C h a u d h u r i a n d D.C. L o o k , " E f f e c t o f t h e V e l o c i t y - F i e l d Peak on I - V C h a r a c t e r i s t i c s o f GaAs F E T s , " S o l i d - S t a t e E l e c t r o n i c s , V o l . 2 6 , No. 8, 8 1 1 - 8 1 4 , (1983) 5.1 J . V . F a r i c e l l i , J . F r e y a n d J . P . K r u s i u s , " P h y s i c a l B a s i s o f S h o r t C h a n n e l MESFET O p e r a t i o n I I : T r a n s i e n t B e h a v i o r , " I E E E T r a n s . ED, ED-29, No. 3, 3 7 7 - 3 8 8 , ( 1 9 8 2 ) 5.2 F.A. B u o t , " E f f e c t s o f V e l o c i t y O v e r s h o o t on P e r f o r m a n c e o f GaAs D e v i c e s , w i t h D e s i g n I n f o r m a t i o n , " S o l i d - S t a t e E l e c t r o n i c s , V o l . 2 6 , No. 7, 6 1 7 - 6 3 2 , ( 1 9 8 3 ) 6.1 D. B. E s t r e i c h , "A M o n o l i t h i c W i d e - B a n d GaAs I C A m p l i f i e r , " I E E E J S S C , SC-17, 1166-1173, ( 1 9 8 2 ) . 8.1 D.C. D ' A v a n z o , " P r o t o n I s o l a t i o n f o r GaAs MESFETs," I E E E T r a n s . MTT, V o l . MTT-30, No. 7, ( 1 9 8 2 ) . 8.2 H.H. B e r g e r , " M o d e l s f o r C o n t a c t s t o P l a n a r D e v i c e s , " S o l i d - S t a t e E l e c t r o n i c s , V o l . 15, 145-158, ( 1 9 7 2 ) 8.3 C. A. L i e c h t i , " P e r f o r m a n c e o f D u a l - G a t e GaAs MESFET's as G a i n - C o n t r o l l e d Low-Noise A m p l i f i e r s and High-Speed M o d u l a t o r s , " I E E E T r a n s . MTT, MTT-23, No. 6, ( 1 9 7 5 ) .  101 8.4  Y. I k a w a , W.E. E i s e n s t a d t a n d R.W. D u t t o n , " M o d e l i n g o f High-Speed, L a r g e - S i g n a l T r a n s i s t o r Switching T r a n s i e n t s f r o m s - P a r a m e t e r M e a s u r e m e n t s , " I E E E J S S C , SC-17, No. 2, (1982).  10. APPENDIX  A -ICDL SIMULATIONS  10.1 D I G I T A L INTEGRATED C I R C U I T SIMULATION I n v e r t e d common d r a i n l o g i c  (ICDL),  OVERVIEW  was m o d e l e d  comparatively  t o o t h e r GaAs MESFET l o g i c s .  logic circuit  c o n f i g u r a t i o n d e v e l o p e d by A b d e l - M o t a l e b [ 4 . 1 7 ]  in  which the l o g i c  functions are realized  r a t h e r than the pulldowm t r a n s i s t o r s used. D e p l e t i o n  ICDL i s a  using  the p u l l u p  which are  ( " n o r m a l l y on") t r a n s i s t o r s  new  normally  a r e employed.  The b a s i c s w i t c h i n g modes a n d t h e a d v a n t a g e s a n d p r o b l e m s are d i s c u s s e d .  Simulations  w e r e done u s i n g b o t h t h e J F E T a n d  t h e S u s s m a n - F o r t MESFET m o d e l s i n S P I C E . results  were f i r s t  simulated  from measurements. In order  Experimental  using parametric  established logic  these  t h e same p a r a m e t r i c  the  using  approaches, data  for a l l  logics. Depletion  transistors  used i n t h e f i r s t  (which  GaAs l o g i c  c o n d u c t f o r Vgg = 0) w e r e  circuits  because of the  problems of f a b r i c a t i n g  enhancement t y p e  sufficiently  threshold voltages  controlled  series  resistances (R  logic)  approach, l o g i c  Fig.  obtained  t o a t t e m p t t o compare  p e r f o r m a n c e w i t h some w e l l were s i m u l a t e d  data  10.1(a),  transistors.  s  devices  and low enough  a n d R ) . I n t h e B F L ( b u f f e r e d FET D  functions are achieved,  u s i n g c o m b i n a t i o n s of pulldown This  with  i s t h e same,  MOSFET DCFL ( d i r e c t  coupled  enhancement d e v i c e s  (which  a s shown i n  depletion  f o r example, as i n s i l i c o n  FET l o g i c ) a r e OFF 102  which  for V  Q S  uses  = 0 ) , except  that  103  A  Fig.  10.1 GaAs MESFET l o g i c .  a) B F L ( b u f f e r e d FET l o g i c ) [ 1 ] b) SDFL ( S c h o t t k y d i o d e FET l o g i c ) [ 2 ] c ) DCFL ( d i r e c t c o u p l e d FET l o g i c ) [ 3 ] the  o u t p u t must be l e v e l - s h i f t e d  next stage, the  since a negative  presentation to the  gate voltage  (with respect to  source) i s r e q u i r e d t o turn o f f the d e p l e t i o n pulldown  transistors. diodes.  The l e v e l s h i f t i n g i s a c h i e v e d  I n SDFL ( S c h o t t k y  i n p u t s a r e combined u s i n g  will  before  - i -  diode  using  Schottky  FET l o g i c , F i g . 1 0 . 1 ( b ) ) t h e  diodes.  Eventually,  i t i s commonly b e l i e v e d , V L S I u s i n g  be a c h i e v e d  by u s i n g  GaAs  enhancement p u l l d o w n d e v i c e s  [3]  1  104 and  DCFL ( F i g . 1 0 . 1 ( c ) ) .  low  s e r i e s r e s i s t a n c e s may be o b t a i n e d  gate technology activation  the  using  gate  self-aligned  [ 9 ] , F o r t h e p r e s e n t we  however, t o d e p l e t i o n  restrict  type t r a n s i s t o r s  t o form  what a d v a n t a g e s ( o r o t h e r w i s e ) may be  the pullup transistors  t o form t h e l o g i c w i t h  pulldown  a c t i n g a s l o a d s . The i d e a o f d o i n g t h i s seems a n  obvious one, but there consideration  [8,9].  a  b y , s o t o s p e a k , t u r n i n g t h e l o g i c u p s i d e down by  transistors  find,  using  p r o c e s s i s b e t t e r c o n t r o l l e d ) o r e l s e some f o r m  l o g i c and consider  obtained  t h r e s h o l d v o l t a g e and  [ 4 - 8 ] (once t h e i o n i m p l a n t a t i o n and  of e t c h e d r e c e s s e d ourselves,  The r e q u i r e d  i s surprisingly  little  previous  o f i t i n t h e l i t e r a t u r e . Of what we  could  t h e most s i g n i f i c a n t was t h e work o f N u z i l l a t e t a l .  105 10.2 ICDL BASIC CIRCUITS The b a s i c g a t e s f o r ICDL [ 1 0 ] a r e a s s e m b l e d are  first  briefly listed  s e c t i o n s . The f i r s t  before  i n F i g . 10.2 a n d  discussion i n later  ( F i g . 10.2(a) i s a n o n - i n v e r t i n g b u f f e r .  T h i s b u f f e r was p r o p o s e d p r e v i o u s l y by H a r t g r i n g e t a l . [ 1 1 ] for  use i n c o n n e c t i o n  inverter for  i s n e e d e d a n d r e q u i r e s a s e c o n d power s u p p l y  level  Fig.  w i t h d y n a m i c s i l i c o n MESFET l o g i c .  shifting  10.2(b),  b e t w e e n s t a g e s . The i n v e r t e r  differs  f r o m t h e SDFL  in  u s i n g an i o n i m p l a n t e d ,  in  p l a c e of diodes  the  inverter,  input  v e r s i o n most n e e d e d , a n d t h i s AND  F i g . 10.1(c),  s h i f t i n g . The b u f f e r e d  g a t e i s i n F i g . 1 0 . 2 ( d ) a n d t h e OR g a t e i n F i g .  (g).A similar  Nuzillat  gate d i f f e r s  the p u l l u p t r a n s i s t o r s using a transistor Nuzillat  (either  with their  by n o t h a v i n g  devices  negative  by  between  Also  voltages  w h e r e a s we a r e c o n s i d e r i n g  With t h i s  i s necessary  load.  studying  constraint Nuzillat  w e r e a b l e t o r e q u i r e o n l y one p o s i t i v e rail  a diode  with small threshold  or negative)  depletion transistors.  supply  10.2(f)  a n d t h e p u l l d o w n l o a d a n d a l s o by  e t a l . were s p e c i f i c a l l y  positive  10.2(e),  quasi-normally-off  instead of a r e s i s t i v e  quasi-normally-off  The  i n v e r t e d OR g a t e was p r e v i o u s l y l i s t e d  et a l . i n connection  l o g i c . Our l o g i c  the  i n F i g . 10.2(c).  w i t h p o s s i b l e complex gate c o n f i g u r a t i o n s i n F i g . and  resistor form of  impedance, i s a c t u a l l y i s shown  s s  considered,  non-velocity saturating,  for level  with high  inverter,  V  An  supply.  et a l .  I n ICDL a  t o accommodate medium t o l a r g e  t h r e s h o l d v o l t a g e s . ICDL d i f f e r s  f r o m t h e SDFL  F i g . 10.2 ICDL configurations: a)buffer, b)inverter, c)buffered inverter, d) AND, e)OR. f ) F = H-F2 = (K+W) • (C+D) g)F = (A+B)•(C+D)  107  c o n f i g u r a t i o n not only  i n the use of a r e s i s t o r as  t r a n s l a t o r , but i n t h e use of t h e i n v e r t e d l o g i c buffer. Similarly  ICDL d i f f e r s  voltage  as  input  f r o m t h e BFL c o n f i g u r a t i o n by  r e m o v i n g t h e v o l t a g e t r a n s l a t i o n mechanism  from the output  path.  10.3 BUFFER  CIRCUIT  Load l i n e p l o t s f o r the b u f f e r a r e given show how  the l o g i c  i n F i g . 10.3(a) t o  l e v e l s a r e o b t a i n e d . The I s  v  s  V  D  DS  c h a r a c t e r i s t i c s are here p l o t t e d f o r constant  a)  Fig.  b)  Inverted buffer loadline with V = 3 V , V = 0 V , and - 2 . 5 V f o r t h e s w i t c h i n g t r a n s i s t o r c o r r e s p o n d i n g t o a h i g h and low l o g i c i n p u t , w i t h measured v s . model JFET a n d MESFET c h a r a c t e r i s t i c s i n ( b ) f o r (M-|) a n d (J-|) i n ( a ) .  V Q  D  10.3  D  D  S  S  = 0  a ) MESFET M o d e l (Mi,), J F E T M o d e l ( J ^ where V • - 1 . 3 7 V a n d MESFET M o d e l (M,) where V = - 0 . 5 V b) C o m p a r i s o n o f t h e J F E T ( J ) a n d MESFET(M) m o d e l s v s . experimental(•) data: I vs. V for V » - 0 . 5 and O . O V T  T  D  D  S  G  S  108  V g  instead of the usual constant V g  D  conventional I  I V  FET l o g i c . Using the common approximation for  below saturation I s  = 2/}( ( V  D  D S  U S E  needed for  G  V  D S  G D  *DS  G S  =  D S  V  = 2^((V  G D  V  - V )  GD  - Vm + V  +  D S  V  high input  t a  + V  D S  i 2  D S  n  T  D S  - V  GD  V  2  w e  / 2 ) . Here I  obtain I  (ie small V )  V  G D  we  D S  D  can  D S  > 0 if  = 0(V  D S  + V  - V ) . 2  Q D  T  usual For a  for the switching t r a n s i s t o r  D S  large and negative) V g  low. The  /2)  form we need  t n e  i s small so that the output i s high. For a low (V  2 D S  / 2 > 0. Above saturation, instead of the  ^ ( G S " T^  =  V  T  o°  t 0  - V )V  GS  input  i s large so that the output i s  load l i n e plotted on these drain current  c h a r a c t e r i s t i c s for constant V  G D  i s the pulldown depletion  t r a n s i s t o r c h a r a c t e r i s t i c for i t s V the JFET SPICE model [12]  = 0.  G S  In F i g . 10.3(a)  (which employs the above  approximate c h a r a c t e r i s t i c s ) has been used and, improved model due to Sussman-Fort et a l . [13]  also, an following  c r i t i c i s m s and proposed improvement of the JFET model by Curtice [14].  The chief differences are the use of a better  representation  of I g D  in the triode region as shown in F i g .  10.3(b) and the introduction of a gate t r a n s i t time delay. The difference in representation  of I g shows up in F i g . D  10.3(a) but i s more important in considering transients. From F i g . 10.3(a) i t i s apparent that with a larger magnitude V good V  T  T  the supply voltage needs to be larger to get  = -1.37  (M^), V  t  = -0.5  (M ) 2  '> separation of the l o g i c l e v e l s . This appears again in F i g . 10.4(a) and  (b) which shows the simulated  transfer  109  Fig.  10.4 B u f f e r t r a n s f e r .  a) MESFET(M) v s . J F E T ( J ) : = -0.5 ( M , J )  V  b) MESFET(M) v s . J F E T ( J ) :  V  2  = 3 V, V  T  = -1.37 ( M  1 f  J T ) ,  V  T  2  characteristic voltages V  D D  D D  (V  o u t  - " 1 . 3 7 , Vjjjj - 7 V T  vs V^ ) f o rd i f f e r e n t V n  T  and supply  u s i n g b o t h J F E T a n d MESFET m o d e l s .  A computer s i m u l a t i o n of t h e v o l t a g e t r a n s f e r c h a r a c t e r i s t i c s of the b u f f e r , using  t h e J F E T a n d MESFET  m o d e l s , i s shown i n F i g . 1 0 . 4 ( a ) a n d ( b ) . T h e MESFET m o d e l i s employed f o r s i m u l a t i o n i n F i g . 10.4(c) and ( d ) . In F i g . 10.4(a) and (b) t h e s w i t c h i n g and l o a d t r a n s i s t o r s a r e identical.  The v o l t a g e  gain d V  Q u t  /dV^  n  f o r a s i n g l e stage i s  c l o s e t o 1 over a c e r t a i n range f o r a c h o i c e of supply voltage  scaled with device  parameters  s i m u l a t i o n of several stages  ( F i g . 10.4(b)).  The  shown i n F i g . 5 ( c ) a n d ( d )  shows t h a t t h e l o g i c h i g h a n d l o w l e v e l s s a t u r a t e a t a b o u t  110  BUFFER STAGE NUMBER  BUFFER STAGE  c)  d)  F i g . 10.4 c) L o g i c l e v e l s as a f u n c t i o n o f s e q u e n t i a l s t a g e s where: - 3, d) L o g i c l e v e l s a s a f u n c t i o n o f s e q u e n t i a l b u f f e r s t a g e s where: V = 7, V = -1.37 (M-j), V = -0.5 ( M ) D D  V  DD  ~  I  V  T I  T  A  N  O  -  A  T  T  I  V  T I  V  D D  2  respectively.  10.4 INVERTER The t r a n s i s t o r s f o r p u l l u p a n d p u l l d o w n  i n the buffer  will  show p r o c e s s v a r i a t i o n s . A l s o a s shown i n F i g . 1 0 . 4 ( b ) a n d (d)  for a threshold  sufficient  supply  voltage  voltage  distinguished logic  of a c e r t a i n magnitude a  i s needed t o g e t w e l l  l e v e l s . Hence t h e l o g i c  l e v e l s may be  l o s t a f t e r a few s t a g e s u n d e r c e r t a i n a d v e r s e This  i n d i c a t e d t h a t an i n v e r t e r w i t h v o l t a g e  than u n i t y the  logic  i s required levels.  conditions. gain  to regenerate the o r i g i n a l  greater values  of  111 The p r o p o s e d of a l e v e l  shifter  inverter,  shown i n F i g . 1 0 . 2 ( b ) ,  stage and an output  a conventional ratioed logic  stage which  acts  like  i n v e r t e r . The u s e o f a r e s i s t o r  i n p l a c e of t h e d i o d e s , f o r example as used i n v e r t e r , was c h o s e n b e c a u s e i t a p p e a r e d fabricate,  consists  i n t h e SDFL  t o be e a s i e r t o  s i n c e t h e d i o d e s a r e r e q u i r e d t o be s m a l l a n d  v e r y a c c u r a t e due t o t h e n e e d f o r r e p r o d u c i b l e c u r r e n t v o l t a g e c h a r a c t e r i s t i c s . The r e s i s t a n c e o f t h e i o n i m p l a n t e d resistor  c a n be v a r i e d by v a r y i n g t h e d o s e r a t h e r t h a n t h e  dimensions  ( w h i c h r e q u i r e s a d i f f e r e n t mask s e t ) . I f s m a l l  d i o d e s of exact a r e a a r e used  t o o b t a i n s t r a i n on t h e  photolithography. I f ,instead, a s e r i e s combination of larger diodes space  i s used  (as i n BFL, f o r example) then  more  a n d power a r e c o n s u m e d . When r e p l a c i n g t h e d i o d e  stack with a r e s i s t o r  c u r v e s must c o i n c i d e f o r t h e c r i t i c a l  t h e I-V  switching region  q u i e s c e n t c o n d i t i o n t o g i v e t h e same DC t r a n s f e r c h a r a c t e r i s t i c s . The r e s i s t o r  i s c h o s e n by p l o t t i n g  r e s i s t a n c e versus output v o l t a g e f o r a r e s i s t o r voltage 10.5.  i n the center of the l o g i c  input  s w i n g a s shown i n F i g .  When t h e i n p u t a n d o u t p u t v o l t a g e s a r e e q u a l a t t h e  l o g i c midpoint a symmetrical transfer c h a r a c t e r i s t i c i s o b t a i n e d . F o r t h e case  i n F i g . 10.5(a) and (b) t h i s  a t a p p r o x i m a t e l y 2.5 a n d 0.63 kohm Using the c r i t e r i o n  respectively.  of equal c u r r e n t f o r a given  v o l t a g e drop a t t h e l o g i c midpoint resistor,  occurs  f o r t h e diode s t a c k and  t h e d i o d e s t a c k d i o d e number a n d a r e a c a n be  1 12  1Kohm/R  IKohm/R  a)  b)  F i g . 10.5 I n v e r t e r o u t p u t v o l t a g e v s . r e c i p r o c a l o f t h e voltage t r a n s l a t o r r e s i s t o r value with f i x e d input voltage OH ~ VOL*/ OL' OH O L " °-  a  t  (v  a) V b) V  2  +  • -0.5 V, V * -1.37 V, V  T  v  w  D D  T  h  e  r  e  v  - 3 V, V = 3 V, V  s  s s  D D  s s  d e t e r m i n e d once average diode For  v  a  n  d  v  2  v  = -2 V = -2 V  process  constants  a r e known.  t h e c a s e i n F i g . 10.5(a) t h e v o l t a g e d r o p a c r o s s t h e  resistor process the  3  i s 1.6 V a n d t h e c u r r e n t  and average diode  process  f o r a symmetrical  characteristics  logic  i n area  transfer  dissipates state,  from  supply  reference  to provide the  w o u l d consume  1 nm  2  per  c h a r a c t e r i s t i c . The I-V  of t h e r e s i s t o r and diode  10.6. I n t h e l o w i n p u t l o g i c  diodes  constants  s t a c k w o u l d be n e c e s s a r y  voltage drop, which i f equal  Fig.  t h e a r e a , and  v o l t a g e s c a n be c h a n g e d . A s s u m i n g t h e same  [ 7 ] , a two d i o d e  diode,  I f the diode  i s f i x e d o n l y t h e number o f d i o d e s ,  supply  rails,  0.64 mA.  state  s t a c k a r e shown i n  the inverter  with  a b o u t 8 5 % l e s s power a n d i n t h e h i g h  (assuming the i n v e r t e r  input peaks a t 2  input volts)  113  Fig.  10.6  I-V p l o t s  d i s s i p a t e s about inverter circuit  for translator  resistor  t h e same amount o f p o w e r . H o w e v e r , i f t h e  input r i s e s to the supply r a i l , d i s s i p a t e s about  resistor The  and d i o d e s t a c k .  five  3 volts,  the  t i m e s more power t h a n  diode  the  circuit. difference  i n dynamic b e h a v i o r t h e r e a f t e r  on t h e d i o d e s t a c k n o n - l i n e a r i t y . The  depends  simulated relative  dynamic performance  f o r the case under c o n s i d e r a t i o n i s  shown i n F i g . 10.7.  The  faster  diode stack c i r c u i t  i n t h e h i g h t o l o w t r a n s i t i o n , due  current nonlinearity, resistor depletion  circuit  t o the diode  i n t h e low t o h i g h t r a n s i t i o n , where  a l t h o u g h the r e s i s t o r c i r c u i t  i s s l o w e r on  i t i s d e l a y symmetric  charge.  for large  interactive  poses  power c o n s u m p t i o n  the  Thus,  t h e down  making i t a l e s s  t i m i n g design problem a less c r i t i c a l  stack  but a p p r o x i m a t e l y e q u i v a l e n t t o t h e  l o a d must remove t h e a c c u m u l a t e d  transition,  i s predictably  complex  systems,  problem  and i t  for logic  114  Fig.  10.7  P u l s e response of b u f f e r and  inverter.  a) B u f f e r : V = 5 V w i t h one b u f f e r l o a d . b) I n v e r t e r , R = 629 0, V = 3 V, V = -2 V , w i t h one buffer load. c) I n v e r t e r comparison, diode stack v s . r e s i s t o r v e r s i o n , V = -0.5V, no l o a d . D  D  D  T  high  inputs.  D  s  s  115 10.5 The  BUFFERED INVERTER ICDL i n v e r t e r t u r n s o u t  fan-out,  similar  driven  if  the b u f f e r c i r c u i t  i n t o the next stage.  The  must a c c o u n t f o r t h e DC  logic  be  block  s i z i n g of the b u f f e r  t o the  The  as  and  dynamic  inverter.  o f t h e OR  logic  f o l l o w s from the d i s c u s s i o n of to  the  capacitance.  AND  GATE  positive  a severe  Schottky source  l o g i c AND  inputs forward  diode  voltage  are  The  of T  2  and  The  width  four times  before  p r o b l e m can  form of F i g . 10.2(g),  o f T-|  the width  output swing f o r the  s e t s i n . The  the  four p o s s i b l e  g a t e c u r r e n t s as a f u n c t i o n o f  combinations t h a t are acceptable  g a t e s of the  flow through  For  i n p u t t r a n s i s t o r s when g a t e  e x c e e d s a b o u t 0.7V.  a reasonable  conduction  f o r MISFET c i r c u i t s .  current w i l l  shown i n F i g . 10.8.  the w i d t h  maintain  shown i n F i g . 1 0 . 2 ( d ) s u f f e r s f r o m  g a t e s of the  l o g i c combination voltage  as  l i m i t a t i o n not present  logic high  twice  overcome  transistors  t h e b u f f e r w i t h d e g r a d e d d y n a m i c p e r f o r m a n c e due  10.7  must  GATE  operation  added  and  i s added  l o a d , power d i s s i p a t i o n ,  considerations with respect  The  T h i s problem can  or a p p r o p r i a t e  shown i n F i g . 1 0 . 2 ( c ) .  OR  fan-in  t o t h e c a s e w i t h SDFL, a l a r g e c u r r e n t  be  10.6  t o g i v e a r a t h e r low  be  input  input i s taken  o f T3  as  to  voltage  gate  forward  circumvented  i n s t e a d . These  by are  using  )  116  a)  b)  F i g . 10.8 S c h o t t k y d i o d e g a t e c u r r e n t o f t r a n s i s t o r s a t i n p u t s A a n d B o f AND g a t e o f F i g . (2) (d) a s a r e s u l t o f f i x e d l o g i c l e v e l on A w i t h i n p u t v o l t a g e on B s w e p t . a) A h i g h ( V b) A low ( V  Q L  Q H  = 3 V) B s w e p t f r o m 0 t o 3 V. • 0.2 V) B s w e p t f r o m 0 t o 3 V.  c o m b i n a t i o n s o f t h e l o g i c OR In  summary, i f a l i m i t e d  of F i g . 10.2(e). ( 0 . 5 V)  logic  swing  i s used,  g a t e s s u c h a s shown i n F i g . 1 0 . 2 ( d ) a n d  ( f ) c o u l d be  T h i s would  compared t o F i g .  g i v e l o w e r power d i s s i p a t i o n  1 0 . 2 ( g ) , but p r o b a b l y a t the expense of speed  and  reliability.  10.8 The  RESULTS AND  THEIR S P I C E SIMULATION  measured parameters  used  f o r SPICE s i m u l a t i o n f o r  used.  117 experiment  r e s u l t s matching  a r e i n Table 10.1.  Parameter  2um FET  Group 1  Group 2  Group 3  R o R SI V 0(A/V»)  68 180 -1.37 2.8- 1 0 "  100 100 -2.5 4.4- 1 0 ~  200 200 -1.0 7-10"  400 400 -0.5 o r 0  s  D  T  3  4  4  1.4-10-3 5 5 1  0  r  3  100 100 Table  5 5  5 5  1 0 . 1 : M e a s u r e d a n d S i m u l a t i o n MESFET p a r a m e t r i c d a t a . S i m u l a t i o n data a d j u s t e d from [20-23]. I n Group 3 l o g i c a p p r o a c h e s d e s i g n e d f o r V = 0 o r -0.5 V a r e c o n s i d e r e d , t h u s two v a l u e s o f fi w e r e u s e d a s l i s t e d , r e s p e c t i v e l y . C a p a c i t a n c e a n d fi t o r the measured d a t a i s t o t a l whereas f o r t h e parametric data i t i s per unit length. T  A s shown i n F i g . 1 0 . 2 ( b ) e x p e r i m e n t a l c h a r a c t e r i s t i c s well  fitted  linear  by t h e MESFET m o d e l b o t h  i n t h e s a t u r a t i o n and  r e g i o n s . The MESFET m o d e l s u c c e s s f u l l y  DC c h a r a c t e r i s t i c  b e t t e r than  were  fits  t h e whole  t h e JFET model.  The m e a s u r e d a n d s i m u l a t e d DC c h a r a c t e r i s t i c s o f t h e buffer circuit Experimental  a n d t h e i n v e r t e r a r e shown i n F i g .  results confirm the f e a s i b i l i t y  10.4(b).  p r o j e c t e d by  t h e s i m u l a t i o n s . The s m a l l d e v i a t i o n b e t w e e n s i m u l a t e d a n d measured t r a n s f e r c h a r a c t e r i s t i c to  the variation  transistors  f o r the b u f f e r  corresponds  i n the I Q S ~ DS c h a r a c t e r i s t i c s of the V  from t h e s i m u l a t i o n v a l u e s .  S i m u l a t e d dynamic responses  f o r the b u f f e r and t h e  i n v e r t e r a r e g i v e n i n F i g . 1 0 . 6 . T h e s e were  obtained  n e g l e c t i n g p a r a s i t i c s due t o i n t e r c o n n e c t i o n s . The justification  forthis  i s t h a t t h e s e w o u l d d e p e n d on d e t a i l s  118 o f l a y o u t a n d we a r e s e e k i n g  the b a s i c or i n t r i n s i c  o f t h e c i r c u i t . The MESFET m o d e l s i m u l a t e d buffer, using V ps the  D D  behavior  experimental  = 5 V, g a v e an a v e r a g e t i m e d e l a y o f 105  f o r u n i t y fanout l o g i c midpoint)  w i t h power d i s s i p a t i o n o f 18.7 mW,  (input held at  a n d power d e l a y p r o d u c t  of  1.96 p J . The i n v e r t e r g a v e an a v e r a g e d e l a y o f 550 p s u s i n g a buffer circuit  a s l o a d w i t h 22.2 mW  power d e l a y p r o d u c t  o f 12.2 p J p e r  d i s s i p a t i o n and a  gate.  REFERENCES 1.  R. Van T u y l a n d C. L i e c h t i , (1974) .  I E E E J S S C , S C - 9 , No.  5,  2.  R. E d e n , B. W e l c h , a n d R. 4, 619 ( 1 9 7 8 ) .  3.  H. I s h a k a w a , H. K u s a k a w a , K. Suyama a n d M. F u k u t a , I n t . S o l i d - S t a t e C i r c u i t s C o n f . , D i g . T e c h . P a p e r s , 200 (1977).  4.  R.A. S a d l e r a n d L . F . E a s t m a n , I E E E E l e c t r o n Dev. EDL-4, No. 7, 215 ( 1 9 8 3 ) .  5.  R.E. L e e , H.M. L e v y a n d D.S. Symposium, 177 ( 1 9 8 2 ) .  6.  K. Y a m a s a k i , K. A s a i a n d K. K u r u m a d a , J a p a n e s e J . A p p l . P h y s . , 2 2 , S u p p l e m e n t 2 2 - 1 , 381 ( 1 9 8 3 ) .  7.  R. A. S a d d l e r , " F a b r i c a t i o n a n d P e r f o r m a n c e o f S u b m i c r o n GaAs MESFET D i g i t a l C i r c u i t s by S e l f A l i g n e d I o n I m p l a n t a t i o n , " Ph.D. T h e s i s , C o r n e l l U n i v e r s i t y , ( 1 9 8 4 ) .  8.  R. P e n g e l l y , M i c r o w a v e F i e l d - E f f e c t T r a n s i s t o r s - T h e o r y D e s i g n and A p p l i c a t i o n s , R e s e a r c h S t u d i e s P r e s s , Chichester (1982).  9.  G. N u z i l l a t , F. D a m a y - K a v a l a , G. B e r t a n d C. A r n o d o , I E E P r o c , 127, P t . I , No. 5, 287 ( 1 9 8 0 ) .  Z u c c a , IEEE J S S C , SC-13,  269 No.  Lett.,  M a t t h e w s , I E E E GaAs I C  10. G. N u z i l l a t , G. B e r t , T.P. Ngu a n d M. G l o a n e c , I E E E T r a n s . E l e c t r o n Dev., ED-27, No. 6, 1102 ( 1 9 8 0 ) . 11. I . M. A b d e l - M o t a l e b , "GaAs MESFETS a n d T h e i r A p p l i c a t i o n s i n D i g i t a l L o g i c and D i g i t a l t o A n a l o g C o n v e r s i o n " , Ph.D. T h e s i s , U n i v e r s i t y o f B r i t i s h Columbia, (1985). 12. C D . H a r t g r i n g , B.A. R o s a r i o a n d J.M. J S S C , SC-16, NO. 5, 578 ( 1 9 8 1 ) .  Pickett,  IEEE  13. L. W. N a g e l , " S P I C E 2: A c o m p u t e r p r o g r a m t o s i m u l a t e semiconductor c i r c u i t s , " E l e c t r o n i c s Research Lab, C o l . E n g . , U n i v e r s i t y o f C a l i f o r n i a , B e r k e l e y , Memo. ERL-M520 (1975) . 14. S.E. S u s s m a n - F o r t , S. N a r a s i m h a n a n d K. Mayaram, "A C o m p l e t e GaAs MESFET C o m p u t e r M o d e l f o r S P I C E , " I E E E T r a n s . MTT, MTT-32, No. 4, 471 ( 1 9 8 4 ) . 15. W.R.  Curtice,  "A MESFET M o d e l f o r Use 119  i n t h e D e s i g n of  120 GaAs I n t e g r a t e d C i r c u i t s , " 5, 448 ( 1 9 8 0 ) .  I E E E T r a n s . MTT,  MTT-28, No.  16. A. L i v i n g s t o n e a n d D. W e l b o u r n , P r o c . o f t h e 1 4 t h C o n f . on S o l i d S t a t e D e v i c e s , T o k y o , 393 ( 1 9 8 2 ) . 17. A. L i v i n g s t o n e , a n d P. M e l l o r , No. 5, 297 ( 1 9 8 0 ) . 18. M.  N a m o r d i a n d W.  White,  19. A. B a r n a , a n d C. L i e c h t i , (1979)  IEEE P r o c ,  127, P t . I ,  GaAs I C S y m p o s i u m , 21  (1982).  I E E E J S S C , SC-14, No.  20. M. H e l i x , S. J a m i s o n , S. H a n k a , R. V i d a n o , C h a o , GaAs I C S y m p o s i u m , 108 ( 1 9 8 2 ) .  4,  708  P. Ng, a n d  C.  2 1 . S. K a t s u , S. Nambu, S. Shimano a n d G. K a n o , I E E E E l e c t r o n Dev. L e t t . , E D L - 3 , No. 8, 197 ( 1 9 8 2 ) 2 2 . T. Onuma, A. T a m u r a , T. Uenoyama, H. T s u j i i , K. N i s h i i a n d H. Y a g i t a , I E E E E l e c t r o n Dev. L e t t . , EDL-4, No. 11, 409 ( 1 9 8 3 ) . 23. K. Y a m a s a k i , K. A s a i , K. K u r a m a d a , Dev., ED-29, N O . 11, 1772 ( 1 9 8 2 )  IEEE T r a n s .  Electron  11. APPENDIX B -LAYOUTS  S I 3 S 9 1 3 T 3 ISAB 121  RI26R912T3  ISAB  12. APPENDIX C -GASFET SUBROUTINE SUBROUTINE GASFET IMPLICIT REAL*8 (A-H.O-Z) C C C C C C C  THIS ROUTINE PROCESSES GaAs HESFETS FOR DC AND TRANSIENT ANALYSES. BASED ON THE MODEL OF WALTER R. CURTICE IEEE TRANS ON MICROWAVE THEORY AND TECHNIQUES VOL MTT-28 NO. 5 MAY 1980 COMMON /TABINF/IELMNT,ISBCKT,NSBCKT.IUNSAT,NUNSAT,ITEMPS,NUMTEM, 1 ISENS,NSENS,IFOUR,NFOUR,IFIELD,ICODE,IDELIM.ICOLUM.INSIZE. 2 JUNODE.LSBKPT,NUMBKP,IORDER.JMNODE,IUR,IUC,ILC,ILR,NUMOFF,ISR, 3 NMOFFC.ISEQ.ISEQ1.NEQN.NODEVS.NDIAG,ISWAP,IEQUA.MACINS.LVNIM1, 4 LX0,LVN,LYNL,LYU,LYL,LX1,LX2,LX3,LX4,LX5,LX6,LX7,LD0,LD1.LTD, 5 IMYNL,IMVN,LCVN,NSNOD,NSMAT.NSVAL,ICNOD,ICMAT»ICVAL, 6 LOUTPT,LPOL,LZER,IRSWPF,IRSWPR,ICSWPF,ICSWPR,IRPT,JCPT, 7 IROWNO,JCOLNO,NTTBR,NTTAR,LVNTMP COMMON /CIRDAT/LOCATE(50),JELCNT(50 >.NUNODS,NCNODS,NUMNOD,NSTOP, 1 NUT,NLT,NXTRM,NDIST,NTLIN,IBR,NUMVS COMMON /STATUS/OMEGA.TIME,DELTA,DELOLD(7).AGO).VT.XNI,EGFET, 1 XMU,MODE,MODEDC,ICALC,INITF,METHOD,IORD,MAXORD,NONCON,ITERNO. 2 ITEMNO.NOSOLV.MODAC,IPIV,IVMFLG.IPOSTP,ISCRCH,IOFILE COMMON /KNSTNT/TWOPI,XLOG2,XLOG10,ROOT2,RAD,BOLTZ,CHARGE,CTOK, 1 GMINtRELTOL,ABSTOL,VNTOL,TRTOL,CHGTOL,EPSO,EPSSIL,EPSOX. 2 PIVTOL.PIVREL COMMON /BLANK/ VAXUE(200000) INTEGER NODPLC<64) COMPLEX • 16 CVALUE(32) EQUIVALENCE (VALUE<1>,NODPLC(1).CVALUE(1))  C C DIMENSION VGSO(1),VGDO(1),CGO<1>,CDO(1),CGDO(1),GMO(1),GDSO(1). 1 GGSO(1),GGDO(1),QGS(1),CQGS(1),QGD(1),CQGD(1). 2 QDS(1).CQDS(1).QTT<1),CQTT(1> EQUIVALENCE (VGSO(1>.VALUE( 1>>.(VGDO(1>.VALUE( 2)), 1 (CGO <D.VALUE( 3)),(CDO (1).VALDE( 4>), 2 (CGDOO),VALUE( 5)),(GMO ( 1),VALUE( 6 ) ) , 3 <GDSO<1).VALUE( 7)),(GGSO(1),VALUE< 8>), 4 (GGDOO). VALUE < 9)).<QGS ( 1) ,VALUE( 10) > . 5 (CQGS(D.VALUE(11)).<QGD ( 1 > ,VALUE( 12)), 6 (CQGD(1),VALUE(13)),<QDS (1>,VALUE(14)>, 7 (CQDS(1).VALUE(15)),(QTT (1),VALUE<16)), 8 (CQTT(1),VALUE(17)) C C LOC=LOCATE(16) 10 IF (LOC.EQ.0) RETURN LOCV=NODPLC < LOC+1) NODE 1=NODPLC(LOC+2) NODE2=NODPLC(LOC+ 3) NODE 3=NODPLC(LOC+ 4) NODE 4=NODPLC < LOC+5 > NODE5=NODPLC<LOC+6) NODE6=NODPLC< LOC+25) LOCM=NODPLC(LOC+7) IOFF=NODPLC(LOC+ 8) TYPE=NODPLC(LOCM+2) LOCM=NODPLC < LOCM+1) LOCT=NODPLC(LOC+19 > C C C  DC MODEL PARAMETERS  123  WlDTH-VALUE{LOCV+1) VT0»VALUE<L0CM+1> VBI•VALUE<LOCM+2) C  GATE  PARASITIC  CONDUCTANCE:  GGPR"VALUE(LOCM+3  GGPR  >'WIDTH  ALPHA=VALUE(LOCM+4 > BETA-VALUE(LOCM* 5)•WIDTH X L A M B - V A L U E < LOCM+6) CSAT-VALUE(LOCM*10)»WIDTH C  DRAIN  PARASITIC  CONDUCTANCE:  G D P R - V A L U E ( L O C M + 1 1 ) »WI C  SOURCE  PARASITIC  GDPR  DTH  CONDUCTANCE:  GSPR  GSPR-VALUE(LOCM+12)»WIDTH TAU-VALUE(LOCM+13) V C R I T - V A L U E < LOCM+14 > C C  INITIALIZATION  C ICHECK=1 GO 20  TO  ( 1 0 0 . 2 0 , 3 0 , 5 0 , 6 0 , 7 0 ) ,  INITF  I F ( M O D E . N E . 1 . O R . H O D E D C . N E . 2 . O R . N O S O L V . E Q . 0 )  GO  TO  25  VDS=TYPE«VALUE<LOCV+2) VGS-TYPE•VALUE(LOCV+  3)  VGD°VGS-VDS GO 25  TO  300  I F ( I O F F . N E . O )  GO  TO  40  V G S - - 1 . 0 D 0 V G D - - 1 . 0 D 0 GO  TO  30  IF  ( I O F F . E Q . 0 )  300  40  VGS-O.ODO  GO  TO  100  VGD-O.ODO GO 50  TO  300  VGS=VGSO<LXO+LOCT) VGD-VGDO(LXO+LOCT) GO  60  TO  300  VGS=VGSO(LX1+LOCT> VGD-VGDO(LX1+LOCT) GO  70  TO  300  XFACT-DELTA/DELOLD<2) VGSO< L X O + L O C T ) » V G S O <  LX1+LOCT)  VGS=(1.0D0+XFACT>*VGSO(LX1+LOCT>-XFACT»VGSO<LX2+LOCT) VGDO(LX0+LOCT)=VGDO<  LX1+LOCT)  VGD-(1.0D0+XFACT)•VGDO(LX1+LOCT)-XFACT*VGDO<LX2+LOCT) CGO< L X O + L O C T  >-CGO(LX1+LOCT)  CDO(LX0+LOCT)=CDO(LX1+LOCT) CGDO(LX0+LOCT)«CGDO(LX1+LOCT) G M O ( L X 0+LOCT >-GMO < L X 1 + L O C T ) GDSO(LX0+LOCT)=GDSO< GGSO(LXO+LOCT >  LX1+LOCT)  =GGSO(LX1+LOCT)  GGDO(LX0+LOCT)»GGDO(LX1+LOCT) GO  TO  110  C C  COMPUTE  NEW  NONLINEAR  BRANCH  VOLTAGES  C 100  V G S - T Y P E * ( V A L U E ( L V N I M 1 + NODE6 >-VALUE(LVNIM1+NODE VGD-TYPE*(VALUE(LVNIM1+NODE6)-VALUE(LVNIM1+NODE4  110  5)) >)  DELVGS=VGS-VGSO(LX0+LOCT) DELVGD-VGD-VGDO< LX0+LOCT > DELVDS-DELVGS-DELVGD  CGHAT=CGO(LX0+LOCT)•GGDO(LX0+LOCT>»DELVGD+GGSO<LX0+LOCT>»DELVGS  CDHAT=CDO(LX0+LOCT)+GMO(LXO+LOCT)*DELVGS+GDSO< 1  -GGDO<LXO+LOCT)«DELVGD  LXO+LOCT)»DELVDS  C C  BYPASS  I F SOLUTION HAS NOT CHANGED  IF (INITF.EQ.6) GO TO 200 TOLoRELTOL»DMAX1< DABS(VGS),DABS(VGSO(LX0+LOCT)> > +VNTOL IF <DABS<DELVGS).GE.TOL) GO TO 200 TOL=RELTOL*DMAX1(DABS(VGD),DABS(VGDO<LXO+LOCT))>+VNTOL IF <DABS(DELVGD).GE•TOL) GO TO 200 TOL=RELTOL*DMAX1(DABS(CGHAT) ,DABS<CGO<LX0+LOCT>) >+ABSTOL I F (DABS(CGHAT-CGO(LX0+LOCT)).GE.TOL) GO TO 200 TOL«RELTOL*DMAX1< DABS(CDHAT),DABS(CDO(LXO+LOCT)))+ABSTOL IF (DABS(CDHAT-CDO(LXO+LOCT)).GE.TOL) GO TO 200 VGS«VGSO(LXO+LOCT> VGD«VGDO(LXO+LOCT) VDS=VGS-VGD CG=CGO(LX0+LOCT) CD«CDO(LXO+LOCT) CGD=CGDO(LXO+LOCT) GM=GMO<LXO+LOCT) GDS»GDSO<LXO+LOCT) GGS«GGSO<LXO+LOCT> GGD=GGDO<LXO+LOCT) GO TO 900 C C C  LIMIT NONLINEAR BRANCH VOLTAGES 200 ICHK1-1 CALL PNJLIM<VGS,VGSO(LX0+LOCT).VT.VCRIT,ICHECK) CALL PNJLIM< VGD,VGDO(LXO+LOCT),VT,VCRIT,ICHK1> I F <ICHK1.EQ.O ICHECK«1 CALL FETLIM(VGS,VGSO(LXO+LOCT),VTO) CALL FETLIM(VGD,VGDO(LX0+LOCT),VTO)  C C C  C C C C C C C C  C C C C  C C  DETERMINE  DC CURRENT AND DERIVATIVES  300 VDS=VGS-VGD IF(VGS.GT.-5.0D0*VT) THEN EVGS=DEXP<VGS/VT) GGS=CSAT*EVGS/VT+GMIN CG=CSAT*(EVGS-1.ODO)+GMIN*VGS ELSE GGS=-CSAT/VGS+GMIN CG'GGS*VGS END I F IF(VGD.GT.-5.0D0*VT) THEN EVGD=DEXP(VGD/VT) GGD=CSAT*EVGD/VT+GMIN CGDsCSAT*(EVGD-1.0D0)+GMIN*VGD ELSE GGD=-CSAT/VGD+GMIN CGD=GGD*VGD END I F GGDoGMIN CGD=0.0D0 CG=CG+CGD COMPUTE DRAIN CURRENT AND DERIVITIVES IF(VDS.GE.O) THEN NORMAL MODE VGST»VGS-VTO IF<VGST.LE.O) THEN CUT-OFF SUBTHRESHOLD EFFECTS NOT  INCLUDED  C  CDRAINoO.ODO GM-O.ODO GDS =O.ODO ELSE LINEAR AND SATURATION REGION BETAP=BETA»{1.0D0+XLAMB*VDS) TWOB=BETAP+BETAP CDRAIN=BETAP*VGST*VGST*DTANH(ALPHA*VDS> GM=TWOB*VGST*DTANH(ALPHA*VDS > GDS=XLAMB* BETA*VGST* VGST * DTANH(ALPHA*VDS) + 1  C  C  C  ( B E T A P « V G S T » V G S T * A L P H A * < 1 . 0 D 0 -  2 <DTANH(ALPHA*VDS)*DTANH(ALPHA*VDS)))) END IF ELSE INVERSE MODE VGDT=VGD-VTO IF(VGDT.LE.O) THEN CUT-OFF CDRAIN-0.0D0 GM-0.0D0 GDS-O.ODO ELSE LINEAR AND SATURATION REGION BETAP-BETA*(1.0D0-XLAMB*VDS) TWOB»BETAP+BETAP  C CDRAIN«BETAP*VGDT*VGDT*DTANH(ALPHA»VDS) GM=-TWOB*VGDT* DTANH(ALPHA*VDS) GDS=-XLAMB*BETA*VGDT*VGDT*DTANH(ALPHA*VDS)• 1 (BETAP*VGDT*VGDT*ALPHA*(1.0D02 (DTANH(ALPHA*VDS)*DTANH(ALPHA* VDS)))) END IF E N D IF C C C C  COMPUTE EQUIVALENT DRAIN CURRENT SOURCE CD=CDRAIN-CGD IF (MODE • NE• 1 ) GO TO 500 IF ((MODEDC.EQ.2).AND.(NOSOLV.NE.O)) IF (INITF.EQ.4) GO TO 500 GO TO 700  C C C  GO TO 500  CHARGE STORAGE ELEMENTS 500 CZGS=VALUE<LOCM+7)»WIDTH CZGD=VALUE(LOCM+ 8)«WIDTH CZDS=VALUE(LOCM+9)*WIDTH TW0P=VB1+VBI  C C C C C  IF VGS APPROACHES VBI NON ZERO CAPGS GOES TO INFINITY VBI IS SCHOTTKY BARRIER JCT. PLUS 0.5V DUE TO DROP IN CONDUCTION CHANNEL UNDER GATE SARG=DSQRT(1.ODO-VGS/VBI) QGS(LXO+LOCT)*TWOP*CZGS* (1. ODO-SARG) CAPGS-CZGS/SARG QGD(LXO+LOCT)=CZGD»VGD  C C C C C C C  GATE DRAIN CAPACITANCE HAS BEEN MODIFIED TO THAT BELOW. VDS AND VGS INCORPORATED FOR AC AND TRANSIENT ANALYSIS ADAPTED FROM THE PAPER BY GOLIO ET AL. IEEE CIRCUITS AND DEVICES MAGAZINE SEPTEMBER 1985 P 21. VBI ASSUMED TO BE PHIG + CHANNEL DROP<0.5)  127  c  C C C  CAPGD= (CZGD*(1.0D0-6.OD-1»VGS))/<(1.ODO-<1.23DO»VGS-VDS)/ 1 (1.23D0*(VBI-5.0D-1)))»6.6D-O QDS(LXO+LOCT)=CZDS*VDS CAPDS=CZDS QTT IS CHARGE TRANSPORTED UNDER GATE IN TIME TAU QTT(LXO+LOCT > «TAU*CDRAIN CAPTT=TAU»GM  C C C  STORE SMALL-SIGNAL PARAMETERS 560  C C C  ir <(MODE.EQ.1).AND.(MODEDC.EQ.2).AND.(NOSOLV.NE.O>) GO TO 700 IF (INITF.NE.4) GO TO 600 VALUE(LXO+LOCT+9 >-CAPGS VALUE(LX0+LOCT+11>-CAPGD VALUE < LX0+LOCT+13)=CAPDS VALUE < LX0+LOCT+15)"CAPTT GO TO 1000  TRANSIENT ANALYSIS 600  IF (INITF.NE.5) GO TO 610 QGS(LX1+LOCT > =QGS(LXO+LOCT > QGD < LX1+LOCT)*QGD(LXO+LOCT) QDS < LX1+LOCT)«QDS(LXO+LOCT) QTT(LX1+LOCT >-QTT(LXO+LOCT) 610 CALL INTGR8(GEQ,CEQ,CAPGS,LOCT+9) GGS'GGS+GEQ CG=CG+CQGS(LXO+LOCT) CALL INTGR 8(GEQ,CEQ,CAPGD,LOCT+11) GGD*GGD+GEQ CG-CG+CQGD(LXO+LOCT) CD»CD-CQGD<LXO+LOCT) CGDaCGD+CQGD(LXO+LOCT) CALL INTGR8(GEQ,CEQ,CAPDS,LOCT+13) GDSeGDS+GEQ CD=CD+CQDS(LXO+LOCT) CALL INTGR 8(GEQTT, CEQ,CAPTT,LOCT+15) GM=GM-GEQTT CD-CD-CQTT(LXO+LOCT) IF (INITF.NE.5) GO TO 700 CQGS(LX1+LOCT)«CQGS(LXO+LOCT) CQGD(LX1+LOCT)=CQGD(LXO+LOCT) CQDS(LX1+LOCT)=CQDS(LXO+LOCT) CQTT(LX1+LOCT)«CQTT(LXO+LOCT) C C C  CHECK CONVERGENCE 700  IF (INITF.NE.3) GO TO 710 IF (IOFF.EQ.0) GO TO 710 GO TO 750 710 IF (ICHECK.EQ.1) GO TO 720 TOL«RELTOL*DMAX1(DABS(CGHAT),DABS(CG))+ABSTOL IF <DABS(CGHAT-CG).GE.TOL) GO TO 720 TOL=RELTOL»DMAX1(DABS(CDHAT).DABS(CD))+ABSTOL IF (DABS(CDHAT-CD).LE.TOL) GO TO 750 720 NONCON=NONCON+1 750 VGSO(LXO+LOCT)=VGS VGDO(LXO+LOCT>«VGD CGO<LXO+LOCT)=CG CDO(LXO+LOCT)"CD CGDO(LXO+LOCT)=CGD  128 GMO(LXO+LOCT>-GM GDSO(LX0+LOCT)»GDS GGSO(LXO+LOCT)-GGS GGDO(LXO+LOCT>-GGD LOAD CURRENT VECTOR 900 CEQGD-TYPE* < CGD-GGD*VGD) CEQGS=TYPE*((CG-CGD)-GGS«VGS) CDREQ-TYPB*((CD+CGD)-GDS*VDS-GM*VGS) VALUE < LVN+NODE6 >"VALUE < LVN+NODE6)-CEQGS-CEQGD VALUE(LVN+NODE4 >-VALUE(LVN+NODE4)-CDREQ+CEQGD VALUE(LVH+NODE5)-VALUE(LVN+NODE5)+CDREQ+CEQGS LOAD Y MATRIX LOCY-LVN+NODPLC(LOC+20 VALUE < LOCY)"VALUE < LOCY•GDPR LOCY-LVN+NODPLC(LOC+21 VALUE(LOCY)-VALUE(LOCY +GGD+GGS+GGPR LOCY-LVN+NODPLC< LOC+22 VALUE < LOCY)-VALUE(LOCY •GSPR LOCY-LVN+NODPLC(LOC+23 VALUE(LOCY)-VALUE(LOCY +GDPR +GDS +GGD LOCY-LVN+NODPLC(LOC+2 4 VALUE(LOCY >-VALUE(LOCY +GSPR+GDS+GM+GGS LOCY-LVN+NODPLC(LOC+26 VALUE(LOCY >-VALUE(LOCY +GGPR LOCY-LVN+NODPLC(LOC+9) VALUE(LOCY >-VALUE < LOCY •GDPR LOCY-LVN+NODPLC(LOC+10 VALUE(LOCY >-VALUE(LOCY -GGD LOCY-LVN+NODPLC(LOC+11 VALUE(LOCY >-VALUE(LOCY -GGS LOCY-LVN+NODPLC(LOC+12 VALUE< LOCY)-VALUE(LOCY -GSPR LOCY-LVN+NODPLC(LOC+13 VALUE(LOCY >-VALUE(LOCY -GDPR LOCY-LVN+NODPLC(LOC+14 VALUE(LOCY)-VALUE(LOCY +GM-GGD LOCY-LVN+NODPLC< LOC+15 VALUE < LOCY >-VALUE(LOCY -GDS-GM LOCY-LVN+NODPLC(LOC+16 VALUE(LOCY)-VALUE(LOCY -GGS-GM LOCY-LVN+NODPLC(LOC+17 VALUE(LOCY)-VALUE(LOCY -GSPR LOCY-LVN+NODPLC < LOC+18 VALUE(LOCY)-VALUE(LOCY -CDS LOCY-LVN+NODPLC(LOC+2 7 VALUE < LOCY >-VALUE< LOCY LOCY-LVN+NODPLC(LOC+2 8 -GGPR VALUE(LOCY)-VALUE(LOCY -GGPR 1000 LOC=NODPLC<LOC) GO TO 10 END  13.  APPENDIX D -SIMULATION SOURCE L I S T I N G S  PROCESS TEST 100 um MESFET CHARACTERIZATION •Cycle Controls .OPTIONS ITL4-1000 ITL5»0 LIMPTS=2000 NOPAGE NOMOD * • L i s t i n g Options .WIDTH OOT=80 • •Active Elements •Bn ND NG NS GFETn (width in urn) B1 1 2 0 SI12 100 B2 3 4 0 SI12 100 B3 5 6 0 S112 100 B4 7 8 0 S H 2 100 B5 9 10 0 S112 100  *  •Active Element Models •model is for 1 urn s l i c e of MESFET which i s m u l t i p l i e d by length •factor in device d e f i n i t i o n  * .MODEL S112 GASFET(VTO'-2, VBI-1.23, R C 0 . 1 3 , ALPHA-2.3, BETA=2.61E-5 + LAMBDA»0.055, CGS0-1.19FF, CGD=1.19FF, CDS=0.096FF, IS=4.13E-15, • RD-3228, RS-3228, TAU-2.86PS) • •Independent Sources VDS 11 0 VDS 1 11 1 DC 0 VGS1 2 0 DC -1.5 VDS2 11 3 DC 0 VGS2 4 0 DC -1 VDS3 11 5 DC 0 VGS3 6 0 DC -0.5 VDS4 11 7 DC 0 VGS 4 8 0 DC 0 VDS5 11 9 DC 0 VGS5 10 0 DC 0.5 • •DC Analysis Parameters .DC VDS 0 3 0.025  •  •Output Parameters .PRINT DC I(VDS1> I(VDS2) I(VDS3) I(VDS4) l(VDS5) • END ISAB RI36R912T3 Strobe Pulse Distortion • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4=1000 ITL5=0 LIMPTS=2000 NOPAGE NOMOD .WIDTH OHT=80  *  • • • • • • • • • • • • • I S A B Circuit*******  •  BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 1 1 20 0 V5 25 26 0  * XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components  129  CFIXED 11 0 9FF CSPAD 25 0 10FF CRFPAD 23 0 20FF CGPAD 24 0 2OFF LSIN 15 25 0.16NH LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RSIN 5 15 50 RRFIN 3 13 50 RGIN 4 14 50 • «»**»****«End ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit • .SOBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66_ D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models .MODEL RSAG12 GASFET(VTO--2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E+ LAMBDA-0.055. CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF. IS-2.07E-15, • RD-1170, RS-1170. TAO-0.71PS) .MODEL R12G1 GASFET<VTO=-2, VBI-1.23, RG-4.97, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET<VTO--2, VBI-1.23, RG-4.97, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAO-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Strobe Pulse Distortion due to P a r a s i t i c s » VSIN 5 0 POLSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS) VRFB 3 0 -0.6 VGGB 4 0 -0.3 .TRAN 0. 1PS 50PS .PRINT TRAN V(5) V(25> . END ISAB RI36R912T3 Time Constant Determination * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  ******«»*»*«*XSAB Circuit******* * BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2  VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c CFIXED 11 0 9FF  Components  • • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit • .SOBCKT AMP 3 5 1 2 BIN 4 3 0 RSA612 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 • ENDS AMP « •Active Element Models • MODEL RSAG12 GASFET(VTO«- 2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF. CDS-0.0791FF. IS-2.07E-15. + RD-1170, RS-1170. TAU-0.71PS) •MODEL R12G1 GASFET(VTO-- 2, VBI-1.23. RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF. CDS»0.0791FF, IS-2.07E-15. + RD-705, RS-1170, TAU-0.71PS) •MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83. ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF. CDS-0.0791FF, IS-2.07E-15. • RD-705. RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA=3.1E-5 + LAMBDA-0.055, CGS0-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705. TAU-0.71PS) • .MODEL TD4 D<IS=.312E-12, RS-1745, N-1.1. TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8. IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Input Time Constant Determination * VSGB 25 0 -0.3 VGGB 24 0 -0.3 VRFIN 23 0 -0.6 PWL(0PS -.8 0.1PS -.4 100PS -0.4 100.IPS -0.8 200PS -0. .TRAN 2PS 200PS .PRINT TRAN V(6) V(20) . END ISAB RI36R912T3 Pulse Feedthrough at vbias • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  *  • * • * • • • • • • * • • I S A B Circuit*******  • BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0  V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and Parasitic Components CFIXED 11 0 9FF CRFPAD 23 0 2OFF CGPAD 24 0 2OFF LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RRFIN 3 13 50 RGIN 4 14 50  •  «********«End ISAB Circuit******* •Amplifier Subcircuit » .SOBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  • •Active Element Models .MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF. CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170. TAU-0.71PS) .MODEL R12G1 GASFET(VTO«-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-1170, TAO-0.71PS) .MODEL R12S GASFET(VTO«-2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-705, TAO-0.71PS) .MODEL R12G2 GASFET(VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Pulse Feedthrough at vbias • VSIN 25 0 POLSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS) VGGB 4 0 -0.3 VRFB 3 0 -0.6 .TRAN 0.1PS 50PS .PRINT TRAN V<26) V(23) V(20) . END ISAB RI36R912T3 Off Isolation at 10GHz * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 « ••••«***««*t*ISAB  Circuit*******  133  BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 9FF  * t * * * * * » * * * E n d ISAB Circuit******* •Amplifier Subcircuit * .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 •ENDS AMP  * •Active Element Models • MODEL RSAG12 GASFET(VTO--2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3. BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-705, TAU-0.71PS) « .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent  Sources  VDD 2 0 4.5 VSS 1 0 -3 • •Off Isolation with 10 GHz Sine RF Input * RSHUNT 23 20 15M VRFIN 23 0 SIN<-0.6 0.2 10GHZ) VSGB 25 0 -2.9 VGGB 24 0 -0.3 .TRAN 2PS 100PS .PRINT TRAN V<23) V(20) V(21) .END ISAB RI36R912T3 Open Switch Tracking • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  *  «»**«********ISAB Circuit*******  BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  •  ZAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 9FF  *  • • • • • • • • • • g n d ISAB Circuit******* •Amplifier Subcircuit * .SOBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0=0.595FF, CGD=0.595FF. CDS-0.0791FF, IS-2.07E-15. + RD-1170, RS-1170. TAU-0.71PS) .MODEL R12G1 GASFET( VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-O.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF. IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • Sine wave Tracking Open Switch * VRFIN 23 0 SIN(-0.6 0.2 1GH2) VSGB 25 0 -0.3 VGGB 24 0 -0.3 .TRAN 10PS INS .PRINT TRAN V<23) V(20) V(21) .END ISAB RI36R912T3 Tracking at 2.3Tau Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 «  • • • • • • • • • • • • • I S A B Circuit*******  BSG1 7 24 6 R12G1 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V2 7 8 0 V3 9 10 0 Vt 11 20 0 V5 25 26 0  •  ZAHP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 9FF  • • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit * .SOBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 T04 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  • •Active Element Models .MODEL RSAG12 GASFET(VTO--2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0-0.S95FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) « .MODEL TD4 D( IS-'•312E-12 , RS-1745, N-1.1, TT-.59PS, CJO-8. 02E-15, • VJ-0.72, EG-1.42, BV-8, IBV«1E-3> • •Independent Sources VDD 2 0 4.E VSS 1 0 - 3 * •Sine Have Tracking at Sampling Aperture 2.3Tau * VRFIN 23 0 SIN("0.6 0.2 1GHZ) VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 57.5PS 100PS) VGGB 24 0 -0.3 .TRAN 1PS INS .PRINT TRAN V(26) V(23) V(20) V(21) • END ISAB RI36R912T3 Tracking at Tau Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  *  BSG1 7 24 6 R12G1  BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 9FF  •  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SOBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 • ENDS AMP • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS)  •  .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1-42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Sine wave Tracking at Sampling Aperture Tau * VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSIN 26 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS 100PS) VGGB 4 0 -0.3 .TRAN 1PS 1NS .PRINT TRAN V(26) V{23) V<20) V(21) .END ISAB RI26R912T3 Time Constant Determination * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  • • • • • • • • • • • • • • I S A B Circuit*******  * BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2  VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 * XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 39FF  • •*«*******End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 • ENDS AMP • •Active Element Models .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA=0.055, CGSO-0.595FF, CGD=0.595FF, CDS-0.0791FF, IS-2.07E-15. + RD=705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 •» LAMBDA-0.055, CGS0=0. 595FF, CGD-0.595FF, CDS-0.079 IFF, IS-2. 07E-1 5, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, R G « 0 . 8 3 , ALPHA"2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0=0.595FF, CGD=0.595FF. CDS-0.0791FF. IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) «  .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Input Time Constant Determination • VSGB 25 0 -0.3 VGGB 24 0 -0.3 VRFIN 23 0 -0.6 PWL(0PS -.8 0.1PS -.4 100PS -0.4 100.1PS -0.8 .TRAN 2PS 2OOPS .PRINT TRAN V(6) V<20> .END ISAB RI26R912T3 Pulse Feedthrough * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • «***««««*«**«iSAB Circuit******* • BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP  200PS -0.  1  138 •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 39FF •  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • •SOBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 01 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA=0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG«0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83. ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at vbias * VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS> VGGB 24 0 -0.3 VRFB 23 0 -0.6 .TRAN 0.1PS 50PS .PRINT TRAN V(26> V(23> V(20) . END ISAB RI26R912T3 Off Isolation • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 V I 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 39FF • • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit  .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  *  •Active Element Models .MODEL R12S GASFET<VTO«-2, VBI=1.23, RG=0.83, ALPHA=2.3, BETA«3.1E-5 + LAMBDA=0.055, CGS0=0.595FF, CGD=0.595FF, CDS*0.079 IFF, I S « 2 . 0 7 E - 1 5 , + RD=705, RS=1170. TAU-0.71PS) .MODEL R12G2 GASFET(VTO=-2, V B I « 1 . 2 3 , R G » 0 . 8 3 , ALPHA=2.3, BETA=3.1E-5 + LAMBDA=0.055, CGS0=0.595FF, CGD«0.595FF, CDS=0.0791FF, IS=2.07E-15, • RD=1170, RS=705, TAU=0.71PS) .MODEL RSAG12 GASFET(VT0=-2, VBI=1.23, RG=0.83, ALPHA»2.3, BETA=3.1E"5 • LAMBDA«0.055, CGSO=0.595FF, CGD=0.59SFF, CDS=0.0791FF, IS=2.07E-15, + RD=1170, RS*1170^ TAU*0.71PS)  •  .MODEL TD4 D < I S » . 3 1 2 E - 1 2 , RS-1745, N=1.1, TT=.59PS, • VJ-0.72. EG'1.42, BV«»8, IBV«1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Ott Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 10M VRFIN 23 0 SIN(-0.6 0.2 10GHZ) VSGB 25 0 -2.9 VGGB 24 0 -0.3 .TRAN 2PS 100PS •PRINT TRAM V(23> V<20> V<21> • END ISAB RI26R912T3 Open Switch Tracking • •Cycle Controls and L i s t i n g Options •OPTIONS ITL4-1000 ITL5=0 LIMPTS«2000 NOPAGE NOMOD .WIDTH OUT=80  •  •••**********ISAB Circuit******* * BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  *  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 39FF  * • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit * .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90  CJO«8.02E-15,  140 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF. CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.07.91 FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS> .MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, + RD-1170, RS-1170, TAO-0.71PS) • .MODEL TD4 D<IS-.312E-12 , RS-1745, N - 1 . 1 , TT-.59PS, CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 10-3 • Sine wave Tracking Open Switch * VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSGB 25 0 -0.3 VGGB 24 0 -0.3 .TRAN 10PS 1NS .PRINT TRAN V(23) V(20) V(21) .END ISAB RI26R912T3 Tracking with 2.3Tau Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OOT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 Vt 23 6 O V3 9 10 0 V4 11 20 0 VS 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 39FF «  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit « .SDBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •Active Element Models • MODEL R12S GASFET(VT0--2, VBI-1.23, RG=0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15. • RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET (VTO- - 2 , VBI = 1.23, R G « 0 . 8 3 , ALPHA-2.3, BETA-3. 1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170. RS-1170, TAU-0.71PS>  •  .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1. TT-.59PS. CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8. IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture 2.3Tau • VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSIN 25 0 POLSE<-2.9 -.3 5PS 5PS 5PS 57.5PS 100PS) VGGB 24 0 -0.3 .TRAN IPS INS .PRINT TRAN V<26) V(23) V(20) V(21) • .END ISAB RI26R912T3 Tracking with Tau Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  *  •••••••••»***ISAB Circuit»»»»»»» • BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 V1 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c CFIXED 11 0 39FF  Components  *  • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit * . SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  *  •Active Element Models .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5  + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAO-0.71PS) .MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, * RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3) «  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine Nave Tracking at Sampling Aperture Tau • VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 25PS 100PS) VGGB 4 0 -0.3 .TRAN 1PS INS .PRINT TRAN V(25) V<23> V(20> V<21> .END ISAB RH6R912T3 Time Constant Determination • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD •WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c CFIXED 11 0 152FF  Components  • • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  *  •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170. RS-1170, TAU-0.71PS) * .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS. CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 10-3 * •Input Time Constant Determination  VSGB 25 0 -0.3 VRFIN 23 0 -0.6 PWUOPS -.8 0. IPS -.4 100PS -0.4 100. 1PS -0.8 .TRAN 2PS 200PS .PRINT TRAN V(6) V<20> .END ISAB RH6R912T3 Pulse Feedthrough • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4=1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT«80  200PS -0.  •  • • • • « * * * * * * « * I S A B Circuit******* * BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c CFIXED 11 0 152FF CRFPAD 23 0 20FF CGPAD 24 0 2OFF LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RRFIN 3 13 50 RGIN 4 14 50  Components  •  • • • • • • « « * * E n d I S A B Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  *  •Active Element Models .MODEL RSAG12 GASFET(VTO=-2, VBI=1.23, RG=0.83, ALPHA«2.3, B E T A « 3 . 1 E " 5 + LAMBDA=0.055, CGS0=0.595FF, CGD-0.595FF, CDS=0.0791FF, I S » 2 . 0 7 E - 1 5 , • RD=1170, RS=M70, TAU=0.71PS) * .MODEL TD4 D< IS=.312E-12, RS=1745, N=1.1, TT=.59PS, CJO=8.02E-15, + VJ=0.72, EG=1.42, BV=8, IBV=1E-3)  *  •Independent Sources VDD 2 0 4.5 VSS 10-3 * •Pulse Feedthrough at Vbias * VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 25PS 200PS) VRFB 3 0 -0.6 .TRAN 0. IPS 50PS .PRINT TRAN V<26) V<23) V<20) . END ISAB RI16R912T3 Off Isolation * •Cycle Controls and L i s t i n g Options  .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  • BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 152FF  *  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models • MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E+ LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, + RD-1170, RS-1170, TAU=0.71PS> • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Off Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 5M VRFIN 23 0 SIN<-0.6 0.2 10GHZ) VSGB 25 0-2.9 .TRAN 2PS 100PS .PRINT TRAN V(23> V(20) V(21) .END ISAB RI16R912T3 Open Switch Tracking * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit******* «  BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 152FF  145 •••*******End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 02 7 8 TD4 66 D3 8 5 T04 66 BPD 5 1 1 RSAG12 90 •ENDS AMP  •  •Active Element Models • MODEL RSAG12 GASFET<VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170. RS-1170. TAU-0.71PS) * •MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  *  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • Sine wave Tracking Open Switch • VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSGB 25 0 -0.3 .TRAN 10PS INS .PRINT TRAN V<23) V<20) V(21> .END ISAB RI16R912T3 Tracking with 2.3Tau Aperture • •Cycle Controls and L i s t i n g Options •OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  •«««*»******»ISAB Circuit******* * BSS 11 26 6 RSAG12 60 V1 23 6 0 V4 11 20 0 V5 25 26 0  * XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 152FF  * •*«******«End ISAB Circuit******* •Amplifier Subcircuit * .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 S3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models  -MODEL RSAG12 GASFET(VTO=-2, VBI-1.23, RG=0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF. IS-2.07E-15. + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8. IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Sine wave Tracking at Sampling Aperture 2.3Tau * VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSIN 25 0 POLSE<-2.9 -.3 5PS 5PS 5PS 53PS 100PS) .TRAN 1PS 1NS .PRINT TRAN V(26) V<23) V(20> V<21> . END ISAB RI16R912T3 Tracking with Tau Aperture * •Cycle Controls and L i s t i n g Options -OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 11 26 6 RSAG12 60 VI 23 ( 0 V4 11 20 0 V5 25 26 0  •  SAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 152FF  • • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) * .MODEL TD4 D(IS-.312E-12. RS-1745, N-1.1, TT-.59PS, CJO-8-02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture Tau • VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 23PS 100PS)  147 .TRAN IPS 1NS .PRINT TRAN V(26> V(23> V<20) V(21> .END ISAB RI16R922T3 Time Constant Determination • •Cycle Controls and L i s t i n g Options •OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  *  «**»»*«******ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  *  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 74FF  *  *****«*«»*End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 D1 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP  •  •Active Element Models .MODEL RSAG22 GASFET(VTO--2, VBI-1.23, RG-0.5, ALPHA-2.3, BETA-2.61E-5 + LAMBDA-0.055, CGS0-1.19FF, CGD-1.19FF, CDS-0.096FF, IS-4.13E-15, + RD-1555, RS-1555, TAU-2.86PS) * .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Input Time Constant Determination * VSGB 25 0 -0.35 VRFIN 23 0 -0.65 PWL(0PS -.8 0.1PS -.4 100PS -0.4 100.1PS -0.8 .TRAN 2PS 200PS .PRINT TRAN V(6> V(20) .END ISAB RH6R922T3 Pulse Feedthrough * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  •**»**»**««**ISAB Circuit******* • BSS 11 26 6 RSAG22 60 V1 23 6 0 V4 11 20 0 V5 25 26 0  200PS  -0.8)  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 74FF CRFPAD 23 0 20FF CGPAD 24 0 2OFF LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RRFIN 3 13 50 RGIN 4 14 50  •  •o********End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 DI 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 . ENDS AMP  •  •Active Element Models .MODEL RSAG22 GASFET(VTO--2, VBI-1.23, RG-0.5, ALPHA-2.3, BETA-2.61E-5 + LAMBDA-0.055, CGS0-1.19FF, CGD-1.19FF, CDS-0.096FF, IS-4.13E-15, • RD-1555, RS-1555, TAU-2.86PS) • .MODEL TD4 D(IS-.312E-12, RS-174S, N-1.1, TT-.59PS, CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  *  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at Vbias • VSIN 25 0 PULSE<-2.95 -.35 5PS 5PS 5PS 25PS 200PS) VRFB 3 0 -0.65 .TRAN 0.IPS 50PS .PRINT TRAN V<26> V(23> V(20> . END ISAB RI16R922T3 Off Isolation » •Cycle Controls and L i s t i n g Options -OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 *  • • • • • • • • • • • • • I S A B Circuit*******  *  BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 VS 25 26 0  * XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 74FF  * • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2  BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 Dl 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 •ENDS AMP  • •Active Element Models .MODEL RSAG22 GASFET(VTO=-2, VBI=1.23, RG=0.5, ALPHA-2.3, BETA=2.61E-5 + LAMBDA=0.055, CGS0=1.19FF, CGD=1.19FF, CDS=0.096FF, IS=4.13E-15, + RD*1555, RS=1555, TAU=2.86PS) • .MODEL TD4 D( IS-.312E-12, RS=1745. N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG=1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Off Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 10M VRFIN 23 0 SIN("0.65 0.2 10GHZ) VSGB 25 0 -2.95 .TRAN 2PS 100PS .PRINT TRAN V(23) V(20> V(21) . END ISAB RH6R922T3 Open Switch Tracking • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 «  • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 11 26 6 RSAG22 60 VI 23 6 0 V i 11 20 0 V5 25 26 0  •  XAMP1 20 21  12  AMP  •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 74FF *  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • -SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 D1 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP  * •Active Element Models .MODEL RSAG22 GASFET<VTO=-2, VBI=1.23, RG-0.5, ALPHA=2.3, BETA=2.61E"5 + LAMBDA=0.055, CGS0=1-19FF, CGD-1-19FF, CDS=0.096FF, IS=4.13E-15, + RD=1555, RS=1555, TAU=2.86PS)  150  •MODEL TD4 D<IS=.312E-12. RS=1745, N=1.1, TT*.59PS, GJO=8.02E-15. + VJ=0.72, E G « 1 . 4 2 , BV=8, IBV«1E-3) « •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * Sine wave Tracking Open Switch • VRFIN 23 0 SIN(-0.65 0.2 1GHZ) VSGB 25 0 -0.35 .TRAN 10PS 1NS .PRINT TRAN V<23) V(20) V(21> • END ISAB RH6R922T3 Tracking with 2.3Tau Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4«1000 ITL5=0 LIMPTS=2000 NOPAGE NOMOD .WIDTH OUT=80  •  • • • • • • • • • • • • • I S A B Circuit*******  * BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  • XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c CFIXED 11 0 74FF  Components  *  • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 D1 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP  *  •Active Element Models .MODEL RSAG22 GASFET(VTO=-2, VBI=1.23, RG=0.83, ALPHA=2.3, BETA=3.1E"5 + LAMBDA=0.055, CGS0=0.595FF, CGD=0.595FF, CDS=0.0791FF, IS=2.07E-15, + RD=1170, RS=1170, TAU=0.71PS) • .MODEL TD4 D(IS=.312E-12, RS=1745, N=1.1, TT=.59PS, CJO=8.02E-15, + V J » 0 . 7 2 , EG=1.42, BV=8. IBV=1E-3)  *  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Sine Wave Tracking at Sampling Aperture 2.3Tau * VRFIN 23 0 SIN(-0.65 0.2 1GHZ) VSIN 25 0 PULSE(-2.95 -.35 5PS 5PS 5PS 53PS 100PS) .TRAN IPS INS .PRINT TRAN V(25) V(23) V<20> V(21> • END  151 ISAB RI16R922T3 Tracking with Tau Aperture » •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS=2000 NOPAGE NOMOD .WIDTH OUT-80  •  •***********«ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 74FF  •  ******«**»End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 DI 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP  *  •Active Element Models .MODEL RSAG22 GASFET(VTO«-2, VBI-1.23, RG-0.25, ALPHA-2.3, BETA-2.61E-5 + LAMBDA-0.055, CGS0-1.19FF, CGD-1.19FF, CDS-0.096FF, IS-4.13E-15, + RD-1555, RS-1555, TAU-2.86PS) • .MODEL TD4 D< IS-.312E"12, RS-1745, N-1.1. TT-.59PS, CJO-8.02E-16, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  *  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture Tau « VRFIN 23 0 SIN(-0.65 0.2 1GHZ) VSIN 25 0 PULSE(-2.95 -.35 5PS 5PS 5PS 23PS 100PS) .TRAN 1PS 1NS .PRINT TRAN V(26) V(23) V(20) V<21) . END ISAB RI36R912T3 Pulse Feedthrough at vbias * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  ••••*********ISAB Circuit******* * BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 60 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0  V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c CFIXED 11 0 9FF IC--0.6 CRFPAD 23 0 2OFF CGPAD 24 0 20FF LRFIN 13 23 0.16NH LGIN 14 24 0.16NH RRFIN 3 13 50 RGIN 4 14 50  Components  • • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP «  •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23. RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055. CGSO-0.S95FF, CGD-0.S95FF, CDS-0.0791FF. I S - 2 . 0 7 E - 1 5 , + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170. RS-705, TAU-0.71PS)  •  .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3>  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at vbias • VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 25PS 200PS> VGGB 4 0 -0.6 VRFB 3 0 -0.6 .TRAN 0.25PS 50PS UIC .PRINT TRAN V(26> V(23) V(20> • END ISAB RI36R912T3 Off Isolation at 10GHz * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  • • • • • • • • • • • • • • I S A B Circuit*******  • BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60  BSG2 11 24 10 R12G2 60 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  *  ZAHP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c CFIXED 11 0 9FF  Components  • • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dt 6 7 TD4 66 D2 7 B TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 •ENDS AMP  •  •Active Element Models •MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705. RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-O.595FF. CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D(IS-.312E"12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Off Isolation with 10 GHz Sine RF Input * RSHUNT 23 20 0.5E8 VRFIN 23 0 SlN(-0.6 0.2 10GHZ) VSGB 25 0 -2.9 VGGB 24 0 -0.3 .TRAN 2PS 100PS .PRINT TRAN V(23> V(20) V(21) .END ISAB RI36R912T3 Open Switch Tracking • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  * • • • * • • • • * • • » * I S A B Circuit******* « BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60  BSG2 11 24 10 R12G2 60 V1 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 VS 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 9FF  • •*««**«***End ISAB Circuit******* •Amplifier Subcircuit « .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI=1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055. CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, •RD-1170, RS-705, TAU-0.71PS) * .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Sine Have Tracking Open Switch • VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSGB 25 0 -0.3 VGGB 24 0 -0.3 .TRAN 10PS INS .PRINT TRAN V<23> V(20> V(21) .END ISAB RI36R912T3 Tracking at 100PS Aperture * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  *  * * * « * * « * * * * « * I S A B Circuit******* « BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 60  VI 23 6 0 V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c CFIXED 11 0 9FF IC--0.6  Components  • • • • • • • • • • • E n d ISAB C i r c u i t * » » » » » » •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TO4 66 BPD 5 1 i RSAG12 90 .ENDS AMP  •  •Active Element Models .MODEL RSAG12 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.59SFF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705. RS-705, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, • RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine Have Tracking at Sampling Aperture • VRFIN 23 0 SIN<-0.6 0.2 250MEG> VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 100PS 410PS) VGGB 24 0 -0.3 .TRAN 10PS 4NS UIC .PRINT TRAN V<26) V<23) V<20) V<21> .END ISAB RI36R912T3 Tracking at 25PS Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 • • * * • • • • • • * * • • I S A B Circuit*******  *  BSG1 7 24 6 R12G1 60 BSS 9 26 8 R12S 60 BSG2 11 24 10 R12G2 60 V1 23 6 0  V2 7 8 0 V3 9 10 0 V4 11 20 0 V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 9FF IC--0.6 «  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 •ENDS AMP  •  •Active Element Models • MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) .MODEL R12G1 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12S GASFET(VTO=-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF. CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-705, TAU-0.71PS) .MODEL R12G2 GASFET<VTO«-2, VBI-1.23, RG-0.83. ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF. IS-2.07E-15. • RD-1170, RS-705, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8. IBV-1E-3)  • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture Tau • VRFIN 23 0 SIN<-0.6 0.2 1GHZ) VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS HOPS) VGGB 24 0 -0.3 .TRAN 2.5PS INS UIC .PRINT TRAN V(26) V(23) V(20> V<21> .END ISAB RI26R912T3 Pulse Feedthrough * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit******* «  BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 60 VI 23 6 0 V3 9 10 0 V4 11 20 0  V5 25 26 0 • XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 39FF IC--0.6 CRFPAD 23 0 20FF LRFIN 13 23 0.16NH RRFIN 3 13 50  • • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  • •Active Element Models .MODEL R12S GAS FET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, • RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.IE-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-S + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15, • RD-1170, RS-1170, TAU-0.71PS) * .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 1 0 - 3 • •Pulse Feedthrough at Vbias * VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS) VGGB 24 0 -0.3 VRFB 3 0 -0.6 .TRAN 0.25PS 50PS UIC .PRINT TRAN V<26) V(23) V{20) . END ISAB RI26R912T3 Off Isolation * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  * • • • « » » * * * * * * * I S A B Circuit******* • BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 60 VI 23 6 0 V3 9 10 0 V4 11 20 0 VS 25 26 0 »  XAMP1 20 21 1 2 AMP  •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 110 39FF  •  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SOBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  • •Active Element Models .MODEL R12S GASFET<VTO«-2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU-0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055. CGSO-0.595FF. CGD-0.595FF. CDS-0.0791FF. IS-2.07E-15. + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-S • LAMBDA-0.055, CGSO-0.595Fr, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12. RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV=1E-3>  *  •Independent Sources VDD 2 0 4.5 VSS 10-3 * •Off Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 0.4E8 VRFIN 23 0 SlN<-0.6 0.2 10GHZ) VSGB 25 0 -2.9 VGGB 24 0 -0.3 .TRAN 2PS 100PS .PRINT TRAN V(23> V{20) V(21) . END ISAB RI26R912T3 Tracking with 100PS Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80 •  • • • • • • • • • • • • • I S A B Circuit*******  *  BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 60 VI 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  •  XAMP 1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 39FF IC--0.6  •  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit  159  .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 01 6 7 TD4 66 02 7 8 TD4 66 03 8 5 T04 66 BPD 5 1 1 RSAG12 90 •ENDS AMP  •  •Active Element Models •MODEL R12S GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3. BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-705, RS-1170, TAU=0.71PS) .MODEL R12G2 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.079IFF, IS-2.07E-15. + RD-1170, RS-1170, TAU-0.71PS) * •MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS. CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8. IBV-1E-3)  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture 2.3Tau • VRFIN 23 0 SIN(-0.6 0.2 250MEG) VSIN 25 0 PULSE<-2.9 -.3 5PS 5PS 5PS 100PS 410PS) VGGB 24 0-0.3 .THAN 10PS 4NS UIC .PRINT TRAN V(26> V<23) V(20) V(21) • .END ISAB RI26R912T3 Tracking with 25PS Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  • » • • • * • • * » • • » • I S A B Circuit******* * BSS 9 26 6 R12S 60 BSG2 11 24 10 R12G2 60 V1 23 6 0 V3 9 10 0 V4 11 20 0 V5 25 26 0  *  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 39FF IC--0.6  •  ( . • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45  BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models .MODEL R12S GASFET(VTO--2. VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF. IS-2.07E-15, + RD-705, RS-1170, TAO-0.71PS) .MODEL R12G2 GASFET<VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-705, TAU-0.71PS) .MODEL RSAG12 GASFET(VTO—2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-1170. TAO-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS. CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture • VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSIN 25 0 PULSE<-2.9 -.3 5PS SPS SPS 25PS 11 OPS) VGGB 24 0 -0.3 .TRAN 2.5PS INS .PRINT TRAN V(25) V(23) V(20) V<21) . END ISAB RI16R912T3 Pulse Feedthrough • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 1 1 20 0 V5 25 26 0  * XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 152FF IC--0.6 CRFPAD 23 0 20FF LRFIN 13 23 0.16NH RRFIN 3 13 50  • • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90  .ENDS AMP • •Active Element Models • MODEL RSAG12 GASFET(VT0--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 • LAMBDA-0.055, CGSO-0.595FF. CGD-0.595FF, CDS-0.0?91FF. IS-2.07E-15. + RD-1170, RS-1170, TAU-0.71PS)  •  .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  CJO-8.02E-15,  •  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at vbias • VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 25PS 200PS> VRFB 3 0 -0.6 .TRAN 0.25PS 50PS UIC .PRINT TRAN V(26) V{23) V(20) . END ISAB RH6R912T3 Off Isolation • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD • WIDTH OUT-80 * • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 11 26 6 RSAG12 60 VI 23 6 0 Vt 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 152FF  •  • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit * .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 D1 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  •  •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) • •Independent Sources VDD 2 0 4.5 VSS 10-3 * •Off Isolation with 10 GHz Sine RF Input  )  162  RSHUNT 23 20 .25E8 VRFIN 23 0 SIN(-0.6 0.2 10GHZ) VSGB 25 0 -2.9 .TRAN 2PS 100PS .PRINT TRAN V<23) V<20) V(21) • END ISAB RI16R912T3 Tracking with 100PS Aperture * •Cycle Controls and L i s t i n g Options •OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD •WIDTH OUT-80  •  •*«***«****«*ISAB Circuit******* * BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  •  ZAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 152FF IC--0.6  •  ***t*»****End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 DI 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 . ENDS AMP  • •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3. BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF. CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) * .MODEL TD4 D(IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15. + VJ-0.72, EG-1.42, BV-8. IBV-1E-3) »  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 * •Sine wave Tracking at Sampling Aperture * VRFIN 23 0 SIN(-0.6 0.2 250MEG) VSIN 25 0 PULSE(-2.9 -.3 5PS 5PS 5PS 100PS 410PS) .TRAN 2.5PS 1NS UIC .PRINT TRAN V(26> V(23) V(20) V(21> .END ISAB RI16R912T3 Tracking with 25PS Aperture « •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  BSS 11 26 6 RSAG12 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 152FF IC--0.6  • • • • • • • • • • • E n d ISAB C i r c u i t » » « » « » » •Amplifier Subcircuit * • SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 .ENDS AMP  *  •Active Element Models .MODEL RSAG12 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1B-5 • LAMBDA-0.055, CGS0-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, • RD-1170, RS-1170, TAU-0.71PS) * .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  *  •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture • VRFIN 23 0 SIN(-0.6 0.2 1GHZ) VSIN 25 0 PULSE(-2.9 -.3 5PS SPS 5PS 25PS 110PS) .TRAN 2.5PS 1NS UIC .PRINT TRAN V(26) V(23> V<20) V(21> .END ISAB RI16R922T3 Pulse Feedthrough • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  •  •*•••**•••••*ISAB Circuit******* • BSS 1 1 2 6 6 RSAG22 60 V1 23 6 0 V4 11 20 0 V5 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 74FF IC--0.65 CRFPAD 23 0 20FF LRFIN 13 23 0.16NH RRFIN 3 13 50  • • • • • • • • • • • E n d ISAB C i r c u i t * * * * * * * •Amplifier Subcircuit  •SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 Dl 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP  •  •Active Element Models • MODEL RSAG22 GASFET<VTO--2, VBI-1.23. RG-0.5. ALPHA-2.3, BETA-2.61E+ LAMBDA-0.055, CGS0-1.19FF, CGD-I.19FF. CDS-0.096FF, IS-4.13E-15. + RD-1555, RS-1555, TAU-2.86PS) • • MODEL TD4 D(IS-. 312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Pulse Feedthrough at Vbias • VSIN 25 0 PULSE<-2.95 -.35 5PS 5PS 5PS 25PS 200PS) VRFB 3 0 -0.65 .TRAN 0.25PS 50PS UIC .PRINT TRAN V<26) V(23) V(20) .END ISAB RI16R922T3 Off Isolation • •Cycle Controls and L i s t i n g Options •OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD •WIDTH OUT-80  •  • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 V5 25 26 0  *  ZAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 74FF  • • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit * •SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 Dl 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 •ENDS AMP  *  •Active Element Models •MODEL RSAG22 GASFET(VTO--2, VBI-1.23, RG-0.5, ALPHA-2.3, BETA-2.61E+ LAMBDA-0.055, CGS0-1.19FF, CGD-1.19FF, CDS-0.096FF, IS-4.13E-15, + RD-1555, RS-1555, TAU-2.86PS)  165  •MODEL TD4 D<IS-•312E-12, RS-1745, N-1.1, TT-.59PS, • VJ-0.72, EG-1.42, BV-B, IBV-1E-3) » •Independent Sources VDD 2 0 4.5 VSS 10-3 • •Off Isolation with 10 GHz Sine RF Input • RSHUNT 23 20 0.5E8 VRFIN 23 0 SIN(-0.65 0.2 10GHZ) VSGB 25 0 -2.95 .TRAN 2PS 100PS .PRINT TRAN V(23) V<20) V(21> . END ISAB RH6R922T3 Tracking with 100PS Aperture * •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5«0 LIMPTS-2000 NOPAGE NOMOD .WIDTH OUT-80  CJO-8.02E-15,  •  ****»***»***»ISAB Circuit******* • BSS 11 26 6 RSAG22 60 VI  23  6  0  V4 11 20 0 V5 25 26 0  •  ZAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIZED 11 0 74FF IC--0.65  • •«********End ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 D1 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP  •  •Active Element Models .MODEL RSAG22 GASFET(VTO--2, VBI-1.23, RG-0.83, ALPHA-2.3, BETA-3.1E-5 + LAMBDA-0.055, CGSO-0.595FF, CGD-0.595FF, CDS-0.0791FF, IS-2.07E-15, + RD-1170, RS-1170, TAU-0.71PS) • .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-15, • VJ-0.72, EG-1.42, BV-8, IBV-1E-3) * •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture 2.3Tau * VRFIN 23 0 SIN(-0.65 0.2 250MEG) VSIN 25 0 PULSE(-2.95 -.35 5PS 5PS 5PS 100PS 410PS) .TRAN 10PS 4NS UIC .PRINT TRAN V(25) V(23) V<20) V(21)  .END ISAB RI16R922T3 Tracking with 25PS Aperture • •Cycle Controls and L i s t i n g Options .OPTIONS ITL4-1000 ITL5-0 LIMPTS-2000 NOPAGE NOMOD .WIDTH ODT=80  •  • • • • • • • • • • • • • I S A B Circuit*******  •  BSS 11 26 6 RSAG22 60 VI 23 6 0 V4 11 20 0 VS 25 26 0  •  XAMP1 20 21 1 2 AMP •ISAB C i r c u i t Passive and P a r a s i t i c Components CFIXED 11 0 74FF IC--0.65  •  • • • • • • • • • • E n d ISAB Circuit******* •Amplifier Subcircuit • .SUBCKT AMP 3 5 1 2 BIN 4 3 0 RSAG22 67 BFB 4 5 0 RSAG22 23 BLPU 2 4 4 RSAG22 45 BPU 2 4 6 RSAG22 90 DI 6 7 TD4 40 D2 7 8 TD4 40 D3 8 5 TD4 40 BPD 5 1 1 RSAG22 90 .ENDS AMP  _  •  •Active Element Models .MODEL RSAG22 GASFET<VTO-- 2, VBI-1.23, RG-0.25, ALPHA-2.3. BETA-2.61E-5 • LAMBDA-0.055, CGS0-1.19FF. CGD-1.19FF, CDS-0.096FF. IS-4.13E-15, + RD-1555, RS-1555, TAU-2.86PS)  * .MODEL TD4 D<IS-.312E-12, RS-1745, N-1.1, TT-.59PS, CJO-8.02E-1S, + VJ-0.72, EG-1.42, BV-8, IBV-1E-3)  • •Independent Sources VDD 2 0 4.5 VSS 1 0 -3 • •Sine wave Tracking at Sampling Aperture Tau * VRFIN 23 0 SIN(-0.65 0.2 1GH2) VSIN 25 0 PULSE(-2.95 -.35 5PS 5PS 5PS 25PS HOPS) .TRAN 2.5PS 1NS UIC .PRINT TRAN V(26) V(23) V(20) V<21) .END  

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