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Display system for computer graphics Hamilton, Frank Robert 1974

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A DISPLAY SYSTEM FOR COMPUTER GRAPHICS by FRANK ROBERT HAMILTON B.A. Sc., Un i v e r s i t y of B r i t i s h Columbia, 1968 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER" OF APPLIED SCIENCE i n the Department of E l e c t r i c a l Engineering We accept t h i s t h e s i s as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA September, 1974 In p r e s e n t i n g t h i s t h e s i s i n p a r t i a l f u l f i l m e n t o f the r e q u i r e m e n t s f o r an advanced degree at the U n i v e r s i t y of B r i t i s h C olumbia, I agree t h a t the L i b r a r y s h a l l make i t f r e e l y a v a i l a b l e f o r r e f e r e n c e and s t u d y . I f u r t h e r agree t h a t p e r m i s s i o n f o r e x t e n s i v e c o p y i n g o f t h i s t h e s i s f o r s c h o l a r l y purposes may be g r a n t e d by the Head o f my Department o r by h i s r e p r e s e n t a t i v e s . I t i s u n d e r s t o o d t h a t c o p y i n g o r p u b l i c a t i o n o f t h i s t h e s i s f o r f i n a n c i a l g a i n s h a l l not be a l l o w e d w i t h o u t my w r i t t e n p e r m i s s i o n . Department o f The U n i v e r s i t y o f B r i t i s h Columbia Vancouver 8, Canada Date ABSTRACT A d i s p l a y system f o r computer graphics i s described i n t h i s t h e s i s . The requirements of the d i s p l a y system are defined, with the emphasis on use i n computer-aided network design. Several basic design a l t e r n a t i v e s are examined, and a basic approach i s chosen toward development of a prototype system. A d e t a i l e d d e s c r i p t i o n of the graphics d i s p l a y system a r c h i -tecture and operation i s provided. D e t a i l s r e l a t i n g to the implemen-t a t i o n of the prototype system are provided, and the performance of the system i s examined. i i TABLE OF CONTENTS Page LIST OF ILLUSTRATIONS v ACKNOWLEDGEMENT v i i 1. INTRODUCTION • • 1 1.1 Statement of the Problem 1 1.2 Scope of the Thesis ..vC....... 1 2. DESIGN OF THE GRAPHICS DISPLAY SYSTEM 2 2.1 Graphics Display System Requirements 2 2.2 Design Considerations 3 2.2.1 Basic Display System Ar c h i t e c t u r e 3 2.2.2 Analog Versus D i g i t a l Techniques 5 2.2.3 Display-Element Generation 5 2.2.3.1 Display Program Subroutines 5 2.2.3.2 Character Generation 6 2.2.3.3 Vector Generation 6 3. FUNCTIONAL ORGANIZATION OF THE GRAPHICS DISPLAY SYSTEM ... 8 3.1 Display System Overview 8 3.2 Display Instructions 11 3.2.1 Control Instructions 12 3.2.2 Transfer Instructions 12 3.2.3 Point Instructions 13 3.2.4 Graph-Point Instructions 14 3.'2.5 Character Instructions 14 3.2.6 Short-Vector Instructions 16 3.2.7 Long-Vector Instructions 16 i i i Page 3.3 Host Computer Interface 18 3.4 The Display Processor 24 3.4.1 The Immediate I n s t r u c t i o n Sequence 28 3.4.2 The Single-Word I n s t r u c t i o n Sequence 29 3.4.3 The Half-Word I n s t r u c t i o n Sequence 29 3.4.4 The Double-Word I n s t r u c t i o n Sequence 32 3.5 The Display Oscilloscope Interface 32 3.6 The System Clock 34 3.7 Display-Element Generators 36 3.7.1 The Point and Graph-Point Generator 36 3.7.2 The Character Generator 39 3.7.3 The Short-Vector Generator 44 3.-7.4 The Long-Vector Generator 47 4. IMPLEMENTATION OF THE GRAPHICS DISPLAY SYSTEM 51 4.1 A Modular Approach ' •••• 51 4.2 Purchased Components 51 4.3 The Logic Family '51 4.4 Construction Techniques 52 5. PERFORMANCE OF THE GRAPHICS DISPLAY SYSTEM 53 6. CONCLUSIONS ...... 56 APPENDIX 1 THE VECTOR GENERATION ALGORITHM 58 REFERENCES 60 i v LIST OF ILLUSTRATIONS Figure Page 3.1 System Block Diagram 9 3.2 Display I n s t r u c t i o n Formats 10 3.3 The ASCII Character Set 15 3.4 T y p i c a l Short Vectors 15 3.5 A Sample Long Vector 17 3.6 CPU Interface 19 3.7 CPU Interface Timing 23 3.8 Display Processor 25 3.9 The Immediate Sequence 27 3.10 The Single-Word Sequence 27 3.11 The Half-Word Sequence 30 3.12 The Double-Word Sequence 31 3.13 The Display Oscilloscope Interface 33 3.14 The System Clock 35 3.15 Clock Timing 35 3.16 The Point,and Graph-Point Generator 38 3.17 Point,and Graph-Point Timing 38 3.18 Beam P o s i t i o n i n g During Character Generation 40 3.19 The Character Generator 41 3.20 Character Timing 42 3.21 The Short-Vector Generator 45 3.22 Short-Vector Timing 46 3.23 The Long-Vector Generator 48 3.24 Long-Vector Timing 50 v LIST OF TABLES Table Page 3.1 Input-Output Transfer Instructions 21 5.1 Display System Performance 54 5.2 Graph Generation Performance 54 v i ACKNOWLEDGEMENT I am g r a t e f u l to the National Research Council of Canada f o r support received during the term of t h i s p r o j e c t . I would l i k e to thank Dr. A.D. Moore for h i s invaluable guidance while supervising t h i s project and Dr. M.R. Ito f o r reading t h i s t h e s i s and providing h e l p f u l suggestions. Special thanks go to Dr. J.S. MacDonald, Messrs. D. Heywood, S. Semrau, G. Austin and N. Thompson f o r the many u s e f u l ideas r e s u l t i n g from discussions. I wish to acknowledge the assistance provided by Mr. B. Nuttal who constructed the d i s p l a y system, and by my wife who typed t h i s t h e s i s . v i i 1. INTRODUCTION 1.1 Statement of the Problem Computer graphics has long been recognized as a des i r a b l e (perhaps e s s e n t i a l ) approach to information d i s p l a y i n c e r t a i n a p p l i -cations (1,2,3,4). In p a r t i c u l a r , the use of graphics d i s p l a y tech-niques i n i n t e r a c t i v e , computer-aided design has proven to be i n v a l -uable. (5) Computer graphics techniques have been u t i l i z e d on the PDP-9 i n s t a l l a t i o n at the U n i v e r s i t y of B r i t i s h Columbia Department of E l e c t r i c a l Engineering f o r several years. L i m i t a t i o n s on the e x i s t i n g graphics f a c i l i t y have been noted, the most important of which are the r e s t r i c t i v e central processing u n i t (CPU) overheads during the maintenance of a graphics d i s p l a y , and the excessive d i s p l a y generation ^ -I / r j . . - *_ _ _ i i i — r i A. i _ _j — -i - — i -i i \ -i * . ~ --"">- Kf- <^ VJ.«_ I.O J-OV. U U U U . i u (.H uu-O^J-C^ WOk.^.J.J.V^^U.Oj/C:/ , ._ i n " f l i c k e r i n g " d i s p l a y s . 1.2 Scope of the Thesis The t h e s i s w i l l describe the steps leading to the implemen-t a t i o n of a graphics d i s p l a y system f o r use at the U n i v e r s i t y of B r i t i s h Columbia Department of E l e c t r i c a l Engineering. Chapter 2 examines the requirements of such a system, and presents the basic design considerations pertinent to these requirements. Chapter 3 pro-vides the d e t a i l e d f u n c t i o n a l organization of the d i s p l a y system, and Chapter 4 describes the implementation d e t a i l s . System performance i s described i n Chapter 5, and conclusions presented i n Chapter 6. 2. DESIGN OF THE GRAPHICS DISPLAY SYSTEM 2.1 Graphics Display System Requirements P r i o r to the design of a graphics d i s p l a y system, some general requirements must be established. .To e s t a b l i s h these r e q u i r e -ments, a graphics f a c i l i t y f o r use i n computer-aided network design and analysis i s considered. Display system requirements f o r computer-aided network design and analysis include the c a p a b i l i t y of generating and a l t e r i n g schematic c i r c u i t diagrams i n a highly i n t e r a c t i v e fashion. The c a p a b i l i t y of d i s p l a y i n g the response of a network to various input s i g n a l s i s also required. I d e a l l y , i t i s d e s i r a b l e to be able to generate a continuously varying response (perhaps i l l u s t r a t i n g the e f f e c t of a continuous v a r i a t i o n i n a network parameter). C l e a r l y , the computer supervising the d i s p l a y system must be capable of more than the support of a s t a t i c d i s p l a y . Computer over-heads associated with the generation of the d i s p l a y must be minimized. The o s c i l l o s c o p e u t i l i z e d i n the graphics system must permit highly dynamic d i s p l a y s , eliminating the p o s s i b i l i t y of a storage o s c i l l o s c o p e . The o s c i l l o s c o p e should have a r e s o l u t i o n of at l e a s t 100 points to the inch, with a usable d i s p l a y area of 10 inches by 10 inches. At l e a s t 8 d i s t i n c t i n t e n s i t y l e v e l s should be provided. The system must be capable of generating a complex d i s p l a y with a r e f r e s h r a t e of at l e a s t 20 times each second. The graphics system should be simple to use. Generation of common d i s p l a y elements, including points, graphs, vectors, and characters should be simple from the user point of view. .3, . 2.2 Design Considerations 2.2.1 Basic Display System Architecture Consideration of possible forms of computer/display system i n t e r a c t i o n suggests several p o s s i b i l i t i e s f o r the basic d i s p l a y system a r c h i t e c t u r e . Choice of a basic a r c h i t e c t u r e is- made on the basis of complexity and the ef f e c t on host computer overheads. One possible form of computer/display system i n t e r a c t i o n i s exemplified by the e x i s t i n g PDP-9 f a c i l i t y . In t h i s case, a PDP-9 program must i n i t i a t e the d i s p l a y of each point v i a input-output trans f e r (IOT) i n s t r u c t i o n s , the main advantage of t h i s approach i s i t s s i m p l i c i t y ; the primary disadvantage i s the extensive CPU involvement i n di s p l a y generation and maintenance. Computer i n v o l v -ment could be lessened considerably by a d d i t i o n of hardware to generate common dis p l a y elements, such as characters and vectors. Certain types of displays s t i l l r equire considerable host computer involvement; f o r example, maintenance of an i r r e g u l a r graph contain-ing 1000 points (such as a network response to a step input) would f u l l y load most small computers i f a l l data i s passed v i a IOT i n s t r u c -t i o n s . A second form of computer/display system i n t e r a c t i o n i s v i a the d i r e c t memory access (DMA) f a c i l i t y a v a i l a b l e on most small com-puters (6,7). In t h i s case, data representing an e n t i r e d i s p l a y can be constructed by the host computer i n i t s main memory. In the simplest case, the memory resident d i s p l a y data (the "d i s p l a y program") could consist of sequential p a i r s of X and Y co-ordinate rvalues, and a beam unblanking i n d i c a t i o n . To generate a d i s p l a y , the host computer pro-vides the display system with the data table address and a word count v i a IOT i n s t r u c t i o n s . On r e c e i p t of a "GO" i n d i c a t i o n , the d i s p l a y system accesses sequential data words v i a the CMA f a c i l i t y and constructs the desired d i s p l a y . Following generation of the l a s t point, the di s p l a y system int e r r u p t s the host computer, and awaits f u r t h e r i n s t r u c -t i o n s . The e n t i r e process i s repeated as often as required to ensure a f l i c k e r - f r e e d i s p l a y . The decrease i n host computer overhead associated with t h i s type of d i s p l a y system can be i l l u s t r a t e d using the 1000 point graph example. T y p i c a l l y , each DMA access " s t e a l s " 1 microsecond from the a v a i l a b l e host CPU execution time; 1000 X-Y co-ordinate p a i r s would reduce a v a i l a b l e CPU time by 2 mi l l i s e c o n d s . Since at l e a s t 30 r e p e t i t i o n s per second are required to eliminate f l i c k e r , generation of the graph reduces host computer c a p a b i l i t i e s by approximately 6%. The DMA approach provides a s i g n i f i c a n t decrease i n computer overheads compared with the programmed I/O approach, but has the disadvantage of increasing the d i s p l a y system complexity. A t h i r d basic system a r c h i t e c t u r e would u t i l i z e a large storage system dedicated to the d i s p l a y system (6). With t h i s approach, the host CPU would t r a n s f e r a d i s p l a y program to the d i s p l a y system memory v i a either IOT i n s t r u c t i o n s or DMA. Subsequent d i s p l a y generation would be performed using the dedicated memory i n a fashion s i m i l a r to the DMA approach described above. With t h i s approach, host CPU involvement i s l i m i t e d to loading the d i s p l a y system memory. In the case of a s t a t i c d i s p l a y , host CPU overheads are n e g l i g i b l e . In the case of a hi g h l y dynamic di s p l a y , overheads are not s i g n i f i c a n t l y decreased from those asso-c i a t e d with the previously described a r c h i t e c t u r e s . A disadvantage of the t h i r d approach i s a considerable i n -crease i n complexity through a d d i t i o n of the large dedicated-memory system. The d i s p l a y system was implemented using the DMA approach, since t h i s basic a r c h i t e c t u r e provides a reasonable compromise between complexity and host CPU overheads. 2.2.2 Analog Versus D i g i t a l Techniques Analog d i s p l a y generation techniques (8) provide c e r t a i n advantages, p a r t i c u l a r l y i n the generation of vectors and characters; however, they have some major disadvantages compared to d i g i t a l techniques. These include: a) analog c i r c u i t s tend to d r i f t , n e c e s s i t a t i n g frequent adjustment, b) analog implementation i s generally more d i f f i c u l t , and time consuming. On the basis of these considerations, implementation using d i g i t a l techniques was adopted. 2.2.3 Display-Element Generation The DMA approach has severe l i m i t a t i o n s ' i f a l l d i s p l a y e l e -ments are generated as described f o r the 1000 point graph example. Both core requirements and CPU overheads are r e s t r i c t i v e i n the case of complex d i s p l a y s . The a d d i t i o n of hardware display-element generators e l i -minates these r e s t r i c t i o n s . A vector generator, f o r example, requires only 2 words of core storage and 2 DMA accesses i f the vector i s r e -presented by a delta-X and delta-Y co-ordinate p a i r . 2.2.3.1 Display Program Subroutines A subroutine c a p a b i l i t y provides a means of decreasing core requirements f o r most graphic d i s p l a y s . 6,' A s i n g l e - l e v e l subroutine c a p a b i l i t y requires s t o r i n g a s i n g l e d i s p l a y program address w i t h i n e i t h e r a d i s p l a y system r e g i s t e r , or a dedicated host CPU memory l o c a t i o n . A m u l t i p l e - l e v e l (nested) sub-routine c a p a b i l i t y requires unique storage f o r a number of d i s p l a y pro-gram addresses, hence a considerable increase i n hardware complexity over the s i n g l e - l e v e l case. . To minimize complexity a s i n g l e - l e v e l subroutine c a p a b i l i t y was included i n the d i s p l a y system. Since many complex d i s p l a y elements are generated by hardware (as described i n subsequent sections) the nested subroutine c a p a b i l i t y i s seldom desired f o r most,graphic:displays. 2.2.3.2 Character Generation A simple approach to character generation i s to generate each character v i a a corresponding subroutine. This approach decreases core requirements, but requires several DMA accesses during the generation of most characters. ' Recent i n t r o d u c t i o n of pre-programmed large capacity read-only-memories (ROM's) provides a more a t t r a c t i v e a l t e r n a t i v e . The ROM's provide a simple method of converting a 7-bit ASCII (American Standard Code for Information Interchange) code into 35 binary values used to generate the character i n a 5 by 7 dot-matrix format. A d e t a i l e d des-c r i p t i o n of the ROM-driven character generator i s provided i n Chapter 2. 2.2.3.3 Vector Generation Two common techniques are often used i n a d i g i t a l approach to vector generation. Both techniques produce only an approximation to a true vector. The f i r s t technique u t i l i z e s d i g i t a l , d i f f e r e n t i a l analyzers 7, (DDA's) to produce a very accurate approximation. The technique requires quite complex c i r c u i t s . A second method u t i l i z e s a binary r a t e m u l t i p l i e r (BRM) algorithm. The algorithm produces an adequate, but poorer approxima-t i o n ( i n some cases) than the DDA techniques, but implementation i s considerably l e s s complex. The BRM approach (described i n d e t a i l i n Chapter 3) was chosen on the basis of s i m p l i c i t y . 8, 3. FUNCTIONAL ORGANIZATION OF THE GRAPHICS DISPLAY SYSTEM 3.1 Display System Overview A s i m p l i f i e d block diagram of the graphics d i s p l a y system and the associated host computer i s provided i n Figure 3.1. The host computer i s a Data General Supernova, a f a s t t h i r d -generation mini-computer. The major components of the graphics d i s p l a y system include a set of i n t e r n a l storage r e g i s t e r s , three D/A converters, a set of display-element generators, and the d i s p l a y processor. General r e g i s t e r s provide temporary storage f o r data used i n the generation of a p a r t i c u l a r d i s p l a y element. Examples of t h e i r use include the storage of an ASCII code during character generation, or the storage of data used during vector generation. - ArMif-ional rpttisf-prs provide storage f o r X. Y and Z—axis co-ordinates. Associated D/A converters d i r e c t l y d r i v e the d i s p l a y o s c i l l o s c o p e , an Optimation CDO-6100. X and Y co-ordinate r e g i s t e r s are p a r a l l e l - l o a d i n g up/down counters, rather than simple l a t c h r e g i s t e r s . Generation of s p e c i f i c d i s p l a y elements, e i t h e r character, long vector, short vector, point or graph-point i s c o n t r o l l e d by a corresponding display-element generator. Each display-element gener-ator converts the data contained i n the general r e g i s t e r s to the c o n t r o l s i g n a l s (±X, ±Y, UNBLANK) required to generate a s p e c i f i c d i s p l a y element. A system clock provides basic timing s i g n a l s f o r d i s p l a y element generation. The heart of the graphics d i s p l a y system i s the d i s p l a y 9. HOST PROCESSOR & CORE STORAGE I/O BUS CPU INTERFACE DISPLAY PROCESSOR LOAD REGISTERS START FUNCTION Z REG. & D/A Y REG. & D/A FUNCTION COMPLETE 3 GENERAL REGISTERS DISPLAY CONTROL SIGNALS . e X REG. & D/A t BLANKING] CONTROL DISPLAY OSCILLOSCOPE SYSTEM CLOCK 3 3 "SI 3 3 CHAR-GEN. LONG-VECTOR GEN-SHORT-V L O l U J \ GEN. POINT GEN. GRAPH" POINT GEN-LuaJ -0 FIGURE 3.1 SYSTEM BLOCK DIAGRAM INSTRUCTION FORMAT MODE NUMBER MODE NAME CONTROL TRANSFER (JMP) (JSR) 1 o | i | 2 3 • h 1 6 |' 7 8 | 9 10 | l l 121 13 14 | 15 NXMD LP USER SC X PI INT 0 0 E X DISPLAY PROGRAM ADDRESS 0 1 E X DISPLAY PROGRAM ADDRESS 2 3 (RSR) POINT GRAPH-POINT CHARACTER SHORT VECTOR 1 1 E ^ ^ X " — PI NXMD B AX D CORD C2 , E Cl E B D2 N2 , E B Dl Nl E LONG VECTOR 1 1 0 B X S DY NXMD >< X DX FIGURE 3.2 DISPLAY INSTRUCTION FORMATS 11. processor. The d i s p l a y processor accesses host CPU memory l o c a t i o n s , d i r e c t s the tr a n s f e r of data to i n t e r n a l storage r e g i s t e r s , and supervises operation of the display-element generators. I n i t i a t i o n of the display process i s performed by the host CPU. Thereafter, the host CPU i s e s s e n t i a l l y free to perform any rel a t e d or t o t a l l y unrelated function. The d i s p l a y processor accesses i n s t r u c t i o n s and data from the host CPU memory. Each i n s t r u c t i o n i s interpreted by the d i s p l a y processor and any associated data i s routed to one or more i n t e r n a l r e g i s t e r s . Following r e g i s t e r loading, a " s t a r t f u n c t i o n " s i g n a l i s sent to the appropriate display-element generator. The display-element generator executes the required function and indicates completion by asserting a "function complete" s i g n a l . Occurrence of the "function complete" s i g n a l i n i t i a t e s the next i n s t r u c t i o n execution cycle. An e n t i r e o s c i l l o s c o p e d i s p l a y i s generated by accessing and executing a set of d i s p l a y i n s t r u c t i o n s . 3.2 Display Instructions A d i s p l a y program consists of a set of d i s p l a y i n s t r u c t i o n s d e f i n i n g a complete graphic dis p l a y . Each d i s p l a y i n s t r u c t i o n defines one or two elements of the t o t a l graphic d i s p l a y . Figure 3.2 provides a summary of the dis p l a y i n s t r u c t i o n set. Display i n s t r u c t i o n s are interpreted by the d i s p l a y pro-cessor according to the current: d i s p l a y processor mode. Display processor modes include c o n t r o l , t r a n s f e r , point, graph-point, charac-t e r , short vector and long vector. A f i e l d i n each d i s p l a y i n s t r u c -t i o n defines the d i s p l a y processor mode f o r i n t e r p r e t a t i o n of the next i n s t r u c t i o n . 12. In', one form of di s p l a y system operation, the d i s p l a y processor accesses sequential d i s p l a y i n s t r u c t i o n s d i r e c t l y from the host CPU memory. The f i r s t i n s t r u c t i o n accessed i s always interpreted i n c o n t r o l mode. 3.2.1 Control Instructions Control mode i n s t r u c t i o n s are used p r i m a r i l y to set up various display system r e g i s t e r s . The r e g i s t e r s , i n c l u d i n g i n t e n s i t y (INT), scale (SC) and "user", tend to remain constant over large segments of any d i s p l a y program. The i n t e n s i t y r e g i s t e r provides f o r eight l e v e l s of d i s p l a y o s c i l l o s c o p e i n t e n s i t y . The scale r e g i s t e r defines a scale f a c t o r , 1,2,4 or 8, applied i n graph-point, character and vector element gen-eration. A "user" r e g i s t e r i s maintained by the d i s p l a y system f o r the programmer's convenience. The r e g i s t e r can be read under program c o n t r o l , and can be used, f o r example, to i n d i c a t e the por t i o n of a disp l a y program being executed at the time of a l i g h t pen i n t e r r u p t . An i n t e r r u p t f i e l d , PI, o p t i o n a l l y generates a host CPU in t e r r u p t , and a l i g h t pen co n t r o l b i t , LP, i s provided to enable or disab l e l i g h t pen i n t e r r u p t s . The next mode f i e l d , NXMD, s p e c i f i e s the d i s p l a y processor mode for i n t e r p r e t a t i o n of the next sequential i n s t r u c t i o n . 3.2.2 Transfer Instructions Transfer i n s t r u c t i o n s allow m o d i f i c a t i o n of the d i s p l a y program counter without host CPU int e r v e n t i o n . Three types of tran s f e r i n s t r u c t i o n s are d i f f e r e n t i a t e d by the code i n i n s t r u c t i o n b i t s 0 and 1. A jump (JMP) i n s t r u c t i o n , code 0, sets the d i s p l a y program 13.. counter to the address s p e c i f i e d by the d i s p l a y program address f i e l d . Code 1 i d e n t i f i e s a subroutine jump i n s t r u c t i o n , JSR. On execution, the d i s p l a y program counter i s incremented, saved i n a subroutine r e g i s t e r , and a new value f o r the d i s p l a y program counter i s obtained from the d i s p l a y program address f i e l d . A return from subroutine (RSR) i n s t r u c t i o n , code 3, t r a n s f e r s the subroutine r e g i s t e r contents to the d i s p l a y program counter. An interrupt f i e l d , PI, permits the generation of a host CPU i n t e r r u p t . The "E" b i t i n each trans f e r i n s t r u c t i o n s p e c i f i e s the mode for execution of the next i n s t r u c t i o n . I f the "E" b i t i s set, the di s p l a y processor w i l l enter c o n t r o l mode. When the "E" b i t i s c l e a r , a mode change w i l l not occur. 3.2.3 Point Instructions Point i n s t r u c t i o n s are used to load the X and Y co-ordinate r e g i s t e r s with absolute values. Each point i n s t r u c t i o n modifies a s i n g l e co-ordinate r e g i s t e r , as s p e c i f i e d by the "AX" f i e l d . When AX contains zero, the X r e g i s t e r i s modified; otherwise, the Y r e g i s t e r i s modified. On point i n s t r u c t i o n execution, the absolute value contained i n the "CORD" f i e l d i s transferred to the s p e c i f i e d co-ordinate r e g i s t e r . A time delay i s generated to permit the o s c i l l o s c o p e beam to s e t t l e i n the new p o s i t i o n . The length of the time delay i s in d i c a t e d by the "D" f i e l d content. When D contains zero, a time delay appropriate to a one-inch beam d e f l e c t i o n i s generated. A one i n the D f i e l d r e s u l t s i n a time delay permitting a worst case beam d e f l e c t i o n (15 inches). On expiry of the time delay, the beam i s unblanked i f the "B" f i e l d contains one. The d i s p l a y processor i s placed i n the mode 14, s p e c i f i e d by the "NXMD" f i e l d , and the next sequential i n s t r u c t i o n i s executed. 3.2.4 Graph-Point Instructions Graph-point i n s t r u c t i o n s provide a simple mechanism f o r generating graphs on the d i s p l a y o s c i l l o s c o p e . Execution of a graph-point i n s t r u c t i o n i s almost i d e n t i c a l to the execution of a point i n s t r u c t i o n . The absolute value contained i n the "CORD" f i e l d i s transferred to the co-ordinate r e g i s t e r i n d i -cated by the "AX" f i e l d . At the same time, however, the other co-ordinate r e g i s t e r i s incremented by 1,2,4 or 8, as s p e c i f i e d by the current content of the scale r e g i s t e r . I n t e r p r e t a t i o n of a l l other graph-point i n s t r u c t i o n f i e l d s i s i d e n t i c a l to that of the point i n s t r u c t i o n . 3.2.5 Character Instructions Character i n s t r u c t i o n s are used to d i s p l a y alpha-numeric text on the d i s p l a y o s c i l l o s c o p e . Each i n s t r u c t i o n provides for the generation of up to two characters. Sixty-four d i s t i n c t characters can be generated, as i l l u s -trated i n Figure 3.3. A s p e c i f i c character i s indic a t e d by i t s corresponding ASCII code. The low-order eight b i t s of a character i n s t r u c t i o n s p e c i f y the f i r s t character to be generated. The character i n d i c a t e d by the ASCII code contained i n the C l f i e l d i s generated i n a 5 x 7 dot-matrix format. The s i z e of the dot-matrix i s determined by the content of the scale r e g i s t e r . When the "E" f i e l d contains a zero, the character spe-c i f i e d by the high-order eight b i t s i s generated. Sequential characters are generated from l e f t to r i g h t on ••• •••• ••• ••• ••••« ••••• ••• • • « • • • * • 9 • • * c •«••• ••»• • • • •«•• •••• • • • • • • • • * * • • • • • • • • • • • • *•« • • •••• • •••• • •••* oo i i u 03 04 as M o; met* wtaai n e m toe an too I M cot tot MO no scout • • • • • • • • • • • • • • • • « 9 « • • • • ••••« • • • • ••••• • • ••••• • • • • • •• 4 • • • • 11 tt u ij u u i* i ; K I N S ooi n i oatoto mi on OOMOO OOMOI sat tie oat tn •*•• •••• ••••• • • • • • • • • • a • • • • • • • • • • • • • • • • •••• • • ••»• ••• • • • • • • * • » • a • • • • • • •••••• • • • « • • • • • • • • • • • • • • • • •••• • ••• • • • to it n n M » 2S 77 its oas iiooot its fit oio oti oio too oto lei OIB no no tit 12 11 J4 as on sto I M tit on iao an ioi • • •••• •••*« • •  • ••• • • • * • • • • • • • • • • «l « «J M *i 41 m m too M I iot an ioa ait ion isa tea ici iao no Ml tSO 'Iflt Ml 10t 110 tit III IB) 100' 101 101 101 110 101 lit •*• * ••• •••• • ••••• ' ••••• • • • • • • ••>*• • • • • • • • * • • • • • • • • • • • • • • • • • • ••••• • • • • • * • • • ••• ••••• ••••«-< • • ••• • •a it i i i i M ts u ir itteoo iioMi ITO no noon 110100 neisi no no ttont *•• ••• • • • • • • • • • • • • • • • • • • • • • • • • • • m i n . m m in i n i n i n m m m m FIGURE 3.3 THF. ASCII CHARACTER SET N=0 D=6 N=3 D=l FIGURE 3.4 TYPICAL SHORT VECTORS 16. the d i s p l a y o s c i l l o s c o p e . The character d i s p l a y process continues u n t i l a non-zero "E" f i e l d i s encountered, r e s u l t i n g i n a t r a n s i t i o n to c o n t r o l mode. 3.2.6 Short-Vector Instructions Vectors l i m i t e d i n both s i z e and d i r e c t i o n are generated using short-vector i n s t r u c t i o n s . Each i n s t r u c t i o n defines up to two short vectors. A short vector i s defined by one of 8 d i r e c t i o n s as s p e c i f i e d i n the "D" f i e l d , and i t s length, (1 to 8 points) as indic a t e d by the "N" f i e l d content. Figure 3.4 i l l u s t r a t e s some of the po s s i b l e short vectors. The low-order 8 b i t s of a short-vector i n s t r u c t i o n s p e c i f i e s the f i r s t vector to be generated. A vector i s generated by d e f l e c t i n g the o s c i l l o s c o p e beam by equal increments i n the s p e c i f i e d d i r e c t i o n . A f t e r each increment, the beam i s unblanked i f the "B" f i e l d i s non-zero. The s i z e of each increment i s s p e c i f i e d by the content of the scale r e g i s t e r , and the number of increments as indic a t e d by the "N" f i e l d content. Successive half-words are processed i n short-vector mode u n t i l a non-zero "E" f i e l d i s encountered, causing a d i s p l a y processor t r a n s i t i o n to c o n t r o l mode. 3.2.7 Long-Vector Instructions Vectors l e s s constrained i n length and d i r e c t i o n than short vectors are generated using long-vector i n s t r u c t i o n s . A long-vector i n s t r u c t i o n c o n s i s t s of two 16-bit words. The DX and Dy f i e l d s s p e c i f y corresponding signed delta-X and delta-Y co-ordinate values. Each d e l t a co-ordinate value i s i n sign-magnitude format, where a non-zero value of "S" i n d i c a t e s a 17, FIGURE 3.5_ A SAMPLE LONG VECTOR 18. negative value. Long vectors are generated using a binary r a t e m u l t i p l i e r algorithm. Implementation of the algorithm (described i n Section 3.7.4) r e s u l t s i n a vector c o n s i s t i n g of a s e r i e s of points at approximately equal i n t e r v a l s . Since a d i g i t a l approach r e s t r i c t s points to a g r i d , most vectors are only approximations to a s t r a i g h t l i n e . A sample vector i s i l l u s t r a t e d i n Figure 3.5. DX and DY speci f y the number of points i n the vector. Point spacing i s determined by the content of the scale r e g i s t e r . The os c i l l o s c o p e beam i s unblanked at each vector point p o s i t i o n i f the "B" f i e l d i s non-zero. The contents of the "NXMD" f i e l d s p e c i f y the d i s p l a y processor mode f o r execution of the next i n s t r u c t i o n . 3.3 Host Computer Interface The i n t e r f a c e to the host computer, i l l u s t r a t e d i n block diagram form i n Figure 3.6, provides the i n t e r f a c e between the d i s p l a y processor and the host CPU. The CPU i n t e r f a c e consists of bus d r i v e r s and r e c e i v e r s , a buffer r e g i s t e r f o r output data, a four-channel input multiplexer and an i n t e r f a c e c o n t r o l u n i t . A l l data and c o n t r o l signals between the host CPU and the disp l a y system are provided by the I/O BUS. Each I/O BUS l i n e i s terminated by a simple r e s i s t i v e network matching the c h a r a c t e r i s t i c impedance of the l i n e . Signals from the host CPU are buffered by l i n e r e c e i v e r s , each a simple i n v e r t e r presenting a s i n g l e u n i t load to the I/O BUS. Signals to the host CPU are presented to the I/O BUS v i a open-collector bus d r i v e r s . B i d i r e c t i o n a l I/O BUS data l i n e s 19. I/O BUS BUS DRIVERS/ RCVRS V BUFFERED DATA OUT BUS (DAT BUS) f t IN BUS V INPUT MUX I/O CONTROL SIGNALS i ^ 1 OUTPUT BUFFER REG LOAD BUFFER CHAN 0 c c c CHAN 1 CHAN 2 CHAN 3 DPC X REG. Y REG. MISC .CHANNEL SELECT INTERFACE UNIT WDRQ LDWD INIT INTERRUPT LOAD REQUEST DPC LINES FIGURE-3.6 CPU INTERFACE 20.. are s p l i t into two u n i d i r e c t i o n a l buses, the IN BUS and the OUT BUS, by p a i r s of bus d r i v e r s and r e c e i v e r s . Data received from the host CPU i s temporarily stored i n the output buffer r e g i s t e r . Outputs from the sixteen simple latches form the buffered data out bus, DATBUS. The input multiplexer permits the switching of four 16-b i t channels of data to the INBUS. Supervision of a l l input/output t r a n s f e r s i s provided by the i n t e r f a c e c o n t r o l u n i t . The i n t e r f a c e c o n t r o l u n i t performs three major functions: the decoding and processing of d i s p l a y system IOT i n s t r u c t i o n s issued by the host CPU, the supervision of d i r e c t memory access fetches from host CPU memory and the a s s e r t i o n of a host CPU in t e r r u p t . Table 3.1 provides a summary of the IOT i n s t r u c t i o n s used f o r d i s p l a y system operation. Two device codes with mnemonics DCO and DC1 are used to sp e c i f y the d i s p l a y system. Four data-input IOT i n s t r u c t i o n s are used to read the four input multiplexer channels. The i n t e r f a c e c o n t r o l u n i t decodes the input IOT request and switches the appropriate multiplexer channel to the INBUS. The i n t e r f a c e c o n t r o l u n i t provides f o r two modes of oper-a t i o n during display generation. The f i r s t mode, DMA execution mode, provides f o r d i s p l a y generation with minimal host CPU program c o n t r o l . IOT i n s t r u c t i o n s are used to i n i t i a t e the d i s p l a y process, and d i s p l a y i n s t r u c t i o n s are fetched using the d i r e c t memory access f a c i l i t y . A second mode, IOT execution mode, provides f o r d i s p l a y generation under host CPU c o n t r o l . That i s , d i s p l a y i n s t r u c t i o n s are presented to the 21, IOT INSTRUCTION FUNCTION DIA AC,DCO INPUT CHANNEL -0 DATA DIB AC.DCl INPUT CHANNEL 1 DATA DIB AC.DCO INPUT CHANNEL 2 DATA DIC AC.DCO INPUT CHANNEL 3 DATA DOA AC,DCO LOAD DISPLAY PROGRAM COUNTER DOB AC,DCO OUTPUT DISPLAY DATA,EXECUTE DOC AC.DCO INIT.IOT EXECUTION MODE IOT INSTRUCTION MODIFIERS START (S) CLEAR (C) FUNCTION STANDARD MANUF. CONVENTION STANDARD MANUF. CONVENTION TABLE 3.1 INPUT--OUTPUT TRANSFER INSTRUCTIONS 22. d i s p l a y system v i a program IOT i n s t r u c t i o n s . P r i o r to d i s p l a y generation i n DMA execution mode, the address of the dis p l a y program must be output to the d i s p l a y processor. Execution of "DOA AC, DCO" by the host CPU r e s u l t s in. the d i s p l a y program address on the I/O BUS. The i n t e r f a c e c o n t r o l u n i t strobes the address into the output buffer r e g i s t e r and sends a s i g n a l , LOAD DPC, to the di s p l a y processor. Execution of an IOT i n s t r u c t i o n with the START modifier enables d i s p l a y system i n t e r r u p t s and d i r e c t memory accesses. On decoding an IOT i n s t r u c t i o n with the IOPLS modifier, the i n t e r f a c e c o n t r o l unit asserts the INIT l i n e , p l a c i n g the d i s p l a y processor i n co n t r o l mode. The s i g n a l WDRQ, requesting a d i s p l a y i n s t r u c t i o n , i s also generated and i n i t i a t e s the d i s p l a y generation process. The i n t e r f a c e c o n t r o l u n i t supervises the DMA fe t c h of a dis p l a y i n s t r u c t i o n . On re c e i p t of the s i g n a l WDRQ, a DMA fe t c h i s performed and the r e s u l t i n g data i s strobed into the output b u f f e r r e g i s t e r . The s i g n a l LDWD i s sent to the di s p l a y processor to i n d i -cate that a display i n s t r u c t i o n word i s a v a i l a b l e f o r processing. Figure 3.7 i l l u s t r a t e s the i n t e r a c t i o n between the host CPU and the i n t e r f a c e c o n t r o l u n i t during d i r e c t memory accesses. On r e c e i p t of the f i r s t WDRQ, a DMA request i s sent to the host CPU. When the host CPU i s able to honour the DMA request, the si g n a l ADDRESS IN i s sent to the i n t e r f a c e c o n t r o l u n i t ; the c o n t r o l unit responds by switching multiplexer channel 0, the d i s p l a y program counter, onto the I/O BUS. The host CPU accesses the indic a t e d memory address and outputs the contents on the I/O BUS, accompanied by the WDRQ ADDRESS IN DATA OUT , FETCH LDWD _ . 1st FETCH ; FIGURE 3.7, CPU INTERFACE TIMING to CO INSTRUCTION PROCESSING 2nd FETCH INSTRUCTION PROCESSING 3rd FETCH INSTRUCTION PROCESSING \ 24. s i g n a l DATA OUT. The data i s strobed into the output buffer r e g i s t e r , and the s i g n a l LDWD i s generated, i n d i c a t i n g completion of the DMA request. •To minimize the average time between WDRQ and LDWD, the in t e r f a c e c o n t r o l unit i n i t i a t e s another DMA cy c l e immediately a f t e r LDWD i s generated. In cases where d i s p l a y i n s t r u c t i o n processing i s a lengthy operation, the next d i s p l a y i n s t r u c t i o n i s a v a i l a b l e when WDRQ i s next asserted; hence LDWD i s immediately returned. In cases of short d i s p l a y i n s t r u c t i o n execution time, the DMA cycle i s i n progress when WDRQ i s asserted, and LDWD i s generated on completion of the cycle . The DMA scheme necessitates double-buffering of the data. The d i s p l a y processor must ensure that the d i s p l a y program counter i s updated and the output buffer r e g i s t e r i s f r e e f o r use s h o r t l y a f t e r LDWD i s generated. IOT execution mode i s i n i t i a t e d by the execution of a "DOC AC, DCO" i n s t r u c t i o n . Decoding by the i n t e r f a c e c o n t r o l u n i t r e s u l t s i n the a s s e r t i o n of INIT, placing the d i s p l a y processor i n c o n t r o l mode. Execution of "DOBS AC, DCO" places a d i s p l a y i n s t r u c t i o n on the I/O BUS. The di s p l a y i n s t r u c t i o n i s strobed into the output bu f f e r r e g i s t e r , d i s p l a y system i n t e r r u p t s are enabled, and the s i g n a l LDWD i s generated. The di s p l a y processor, on r e c e i p t of LDWD, processes the d i s p l a y i n s t r u c t i o n and asserts WDRQ on completion. On r e c e i p t of WDRQ, the i n t e r f a c e c o n t r o l unit requests a host CPU in t e r r u p t and awaits program inte r v e n t i o n . 3.4 The Display Processor The d i s p l a y processor, i l l u s t r a t e d i n block diagram form i n Figure 3.8, supervises the execution of a l l d i s p l a y i n s t r u c t i o n s . B U S T O I N P U T M U X 25. CN PS 3 o < o D I S P L A Y P R O G R A M C O U N T E R ( D P C ) TS: 3 M U X 3 I N T E R N A L R E G . 2 (IR2) I N T E R N A L R E G . 1 (IR1) M O D E R E G I S T E R ( M R ) 3 3 S U B R O U T I N E R E G I S T E R ( S R ) I N C R D P C c L O A D D P C 3 3 L O A D M O D E C L E A R M O D E T I M I N G G E N E R A T O R L O A D S R y IR2 B U S S E L E C T C H A N N E L - \ I R M S B U S y I R I S B U S S T A R T F U N C T I O N — F U N C T I O N C O M P L E T E W D R Q L D W D I N T E R R U P T R E Q U E S T L O A D R E G I S T E R S F I G U R E 3.8 D I S P L A Y P R O C E S S O R 2 6 , . Fundamental components of the d i s p l a y processor include: the d i s p l a y program counter and multiplexer, the subroutine r e g i s t e r , the mode r e g i s t e r and the timing generator. Two of the i n t e r n a l storage r e g i s t e r s , IR1 and IR2, are also shown i n Figure 3.8. The d i s p l a y program counter, DPC, i s a p a r a l l e l loading, 12-bit up-counter. The associated DPC multiplexer permits p a r a l l e l loading of the DPC from ei t h e r the output buffer r e g i s t e r (via the DAT BUS), or the subroutine r e g i s t e r . The DPC contains the current d i s p l a y program address during DMA execution mode. The subroutine r e g i s t e r i s a p a r a l l e l loading r e g i s t e r c o n s i s t i n g of 12 RS f l i p - f l o p s . The subroutine r e g i s t e r can r e t a i n a d i s p l a y program address during i n s t r u c t i o n execution. Internal r e g i s t e r 2, IR2, i s a 16-bit, p a r a l l e l loading r e g i s t e r constructed of RS f l i p - f l o p s . IR2 i s provided f o r the storage of data used i n display-element generation. Another i n t e r n a l r e g i s t e r , IR1, i s i d e n t i c a l to IR2. A multiplexer associated with IR1 allows the switching of ei t h e r the low-order or high-order 8 b i t s of IR1 to the IRM BUS. IR1 i s normally used f o r storage of the dis p l a y i n s t r u c t i o n during display-element generation. The mode r e g i s t e r i s a 3-bit f l i p - f l o p r e g i s t e r used to store the current mode code during i n s t r u c t i o n execution. The timing generator c o n s i s t s of mode decode c i r c u i t r y , monostable m u l t i v i b r a t o r s , and associated l o g i c used to generate the fundamental system timing s i g n a l s . Four d i s t i n c t timing sequences are generated during d i s -play i n s t r u c t i o n execution. An "immediate" sequence appli e s during 27, WDRQ LDWD TP1 TP2 FIGURE 3.9 THE IMMEDIATE SEQUENCE WDRQ LDWD TP1 TP2 START FUNCTION FUNCTION COMPLEXE FIGURE 3.10 THE SINGLE-WORD SEQUENCE 28. the execution of co n t r o l and transfe r i n s t r u c t i o n s . The " s i n g l e -word" sequence i s u t i l i z e d during the execution of point and graph-point i n s t r u c t i o n s . A t h i r d sequence, the "half-word" sequence, i s used during the execution of character and short-vector i n s t r u c t i o n s . The f i n a l sequence, the "double-word" sequence, i s app l i c a b l e during long-vector i n s t r u c t i o n execution. 3.4.1 The Immediate In s t r u c t i o n Sequence The immediate i n s t r u c t i o n sequence, i l l u s t r a t e d i n Figure 3.9, i s i n i t i a t e d on ass e r t i o n of WDRQ, a request f o r the next d i s p l a y i n s t r u c t i o n . Completion of the memory access i s denoted by LDWD. The leading edge of LDWD i s used to increment the DPC, and the t r a i l i n g edge t r i g g e r s a monostable m u l t i v i b r a t o r to produce timing pulse 1, TP1 TP1 i s used to transfer the dis p l a y i n s t r u c t i o n from the output b u f f e r r e g i s t e r (DAT BUS) to IR1. The t r a i l i n g edge of TP1 t r i g g e r s a second monostable m u l t i v i b r a t o r , producing timing pulse 2, TP2. TP2 i s used to generate WDRQ, i n i t i a t i n g the next timing sequence. On execution of a cont r o l i n s t r u c t i o n , the sc a l e , i n t e n s i t y and user r e g i s t e r s are loaded from the DAT BUS using TP1. I f s p e c i f i e d a program int e r r u p t i s also i n i t i a t e d by TP1. TP2 i s used to tr a n s f e r the mode (for execution of the next i n s t r u c t i o n ) from IR1 to the mode r e g i s t e r . LDWD i s used to transfe r the DPC to the subroutine r e g i s t e r during execution of a JSR tra n s f e r i n s t r u c t i o n . TP1 i s used to load the DPC with the new program address ( v i a the DAT BUS) on execution of both a JSR and a JMP transfe r i n s t r u c t i o n . On execution of an RSR transfer i n s t r u c t i o n , TP1 i s used to load the DPC from the subroutine r e g i s t e r . If the "E" f i e l d of the tr a n s f e r i n s t r u c t i o n s i s non-zero, 2 9 . TP2 i s used to cl e a r the mode r e g i s t e r , r e s t o r i n g the d i s p l a y processor to c o n t r o l mode. 3.4.2 The Single-Word I n s t r u c t i o n Sequence A single-word sequence i s i l l u s t r a t e d i n Figure 3.10. During a single-word sequence, LDWD, TP1 and TP2 are generated i n the same manner as i n an immediate sequence. LDWD i s used to increment the DPC, and TP1 i s used to strobe the d i s p l a y i n s t r u c t i o n i n t o IR1. The appropriate " s t a r t f u n c t i o n " l i n e i s asserted by TP2, and the d i s p l a y processor enters an i d l e s t a t e while a display-element generator performs i t s f u n c t i o n . On completion of the appropriate f u n c t i o n , the d i s p l a y element-generator asserts "function complete",and WDRQ i s generated. The mode r e g i s t e r i s modified, i f required, on the leading edge of "function complete". 3.4.3 The Half-Word I n s t r u c t i o n Sequence A half-word sequence, used f o r the generation of characters and short vectors, i s s i m i l a r to a single-word sequence. " S t a r t f u n c t i o n " , r e s u l t i n g from the i n i t i a l WDRQ, i n i t i a t e s the generation of the element defined by the low-order 8 b i t s of the d i s p l a y i n s t r u c -t i o n . Subsequent timing i s dependent upon the content of the d i s p l a y i n s t r u c t i o n "E" f i e l d . On completion of the function associated with the low-rorder 8 b i t s of the d i s p l a y i n s t r u c t i o n , " f u n c t i o n complete" i s asserted. If the "E" f i e l d (of the low-border half-word) contains zero, generation of another character or short vector i s i n d i c a t e d , and " s t a r t f u n c t i o n " i s immediately reasserted, as i l l u s t r a t e d i n Figure 3.11a. Following element generation associated with the high-order 8 b i t s of the d i s p l a y 30, a) CASE I - PROCESSING 2 CONSECUTIVE HALF WORDS b) CASE II - PROCESSING LOW ORDER HALF WORD ONLY FIGURE 3.11 THE HALF WORD-SEQUENCE 31 r 32, i n s t r u c t i o n , "function complete" i s again generated, r e s u l t i n g i n WDRQ, a request for a new di s p l a y i n s t r u c t i o n . If the "E" f i e l d (associated with e i t h e r half-word) i s non-zero, the mode r e g i s t e r i s cleared i n preparation f o r a c o n t r o l i n s t r u c t i o n , and WDRQ i s asserted. Figure 3.11b i l l u s t r a t e s the case where the "E" b i t of the low-order half-word of the d i s p l a y i n s t r u c t i o n i s non-zero. During a half-word sequence, the appropriate 8 b i t s of the di s p l a y i n s t r u c t i o n are switched onto the IRM bus for use by the di s p l a y generator. 3.4.4 The Double-Word I n s t r u c t i o n Sequence The f i r s t h a l f of a double-word sequence (Figure 3.12) i s i d e n t i c a l to an immediate sequence except that TP1 i s used to load the f i r s t word of a lone-vector i n s t r u c t i o n into-IR2. The second h a l f of a double-word sequence i s i d e n t i c a l to a singler-word sequence. 3.5 The Display Oscilloscope Interface The i n t e r f a c e to the d i s p l a y o s c i l l o s c o p e i s i l l u s t r a t e d i n block diagram form i n Figure 3.13. Major axis components include: X and Y up/down counters, and D/A converters. A scale r e g i s t e r , an i n t e n s i t y r e g i s t e r and D/A converter, and beam unblanking c i r c u i t r y complete the i n t e r f a c e . The X up/down counter i s a 10~bit, synchronous counter constructed from J-K f l i p - f l o p s . The counter can be p a r a l l e l loaded from the DAT BUS. A count d i r e c t i o n input i n d i c a t e s count up or count down, and a toggle l i n e i n i t i a t e s the counter s t a t e change. The counter can be incremented or decremented by 1,2,4 or 8 u n i t s f o r each toggle pulse, as s p e c i f i e d by the scale r e g i s t e r content. DAT BUS 33, i LOAD SCALE AND INTENSITY LOAD X -ts* TOGGLE X X COUNT -EH DIRECTION X UP/DOWN COUNTER SCALE REGIS-TER V LOAD Y TOGGLE Y Y COUNT DIRECTION S L A z Y UP/DOWN COUNTER LOAD X D BUFFERED X D/A LOAD Y D/A^ BUFFERED Y D/A INTEN-SITY REGIS-TER AMPLIFIER z D/A X-AXIS Y-AXIS Z-AXIS UNBLANK TO DISPLAY OSCILLOSCOPE FIGURE 3.13 THE DISPLAY OSCILLOSCOPE INTERFACE 34, The content of the X up/down counter i s tra n s f e r r e d to the 10-bit, buffered, X D/A converter which d i r e c t l y d r i v e s the X-axis of the d i s p l a y o s c i l l o s c o p e . The Y-axis up/down counter and associated D/A converter are i d e n t i c a l to the X-axis c i r c u i t r y . The i n t e n s i t y r e g i s t e r i s a 3-bit r e g i s t e r c o n s i s t i n g of simple latches. Signals from the i n t e n s i t y r e g i s t e r are input to a 3-bit D/A converter which d i r e c t l y drives the Z-axis of the di s p l a y o s c i l l o s c o p e . A simple two-r-stage t r a n s i s t o r a m p l i f i e r i s used to dr i v e the low impedance, beam unblanking input of the di s p l a y o s c i l l o s c o p e . When "UNBLANK" i s asserted, a point with co-ordinates s p e c i f i e d by the X and Y axis D/A buffers and i n t e n s i t y s p e c i f i e d by the i n t e n s i t y r e g i s t e r i s displayed. 3.6 The System Clock Fundamental timing s i g n a l s used i n the generation of a l l d i s p l a y elements are derived from the system clock. The clock frequency i s programmable, permitting the optimization of d i s p l a y element generation times. Figure 3.14 i s a simple block diagram of the system clock, which consists of two monostable m u l t i v i b r a t o r s , Ml and M2, and a r e s i s t o r switching network. The monostable m u l t i v i b r a t o r s are trigger e d by a r i s i n g edge applied to the "T" terminal, and can s u s t a i n a duty c y c l e near 100 percent. Duration of the monostable output i s determined by an RC network. The r e s i s t o r switching network permits the s e l e c t i o n of 16 d i s t i n c t pulse durations from Ml, as s p e c i f i e d by the TIMING SELECTION inputs. r TIMING 1 -SELECTION • RESISTOR SWITCHING NETWORK FIGURE 3.14 THE SYSTEM CLOCK ENABLE CLOCK C l C2 (a) - SINGLE CLOCK CYCLE ENABLE CLOCK 1 ci : _ J U U I C2 % I 1 1 | [ (b) - MULTIPLE CLOCK CYCLES FIGURE 3 .15 CLOCK TIMING 36. Figure 3.15 i l l u s t r a t e s t y p i c a l waveforms obtained from the system clock. A s i n g l e clock c y c l e w i l l r e s u l t from a b r i e f a s s e r t i o n of "ENABLE CLOCK", as i l l u s t r a t e d i n Figure 3.15a. The r i s i n g edge of "ENABLE CLOCK" tr i g g e r s Ml, producing the f i r s t clock phase, C l . M2 i s triggered on the f a l l i n g edge of C l , generating C2, the second clock phase. If "ENABLE CLOCK" remains asserted, m u l t i p l e clock cycles are generated, as shown i n Figure 3.15b. C2 i s fed back to r e - t r i g g e r Ml, providing a free-running clock as long as "ENABLE CLOCK" i s asserted. The r e s i s t o r switching network consists of 4 simple t r a n -s i s t o r switches providing 16 d i f f e r e n t RC time constants for Ml. The duration of C l ranges from 400 nanoseconds to 10 microseconds. The duration of C2 i s f i x e d at 400 nanoseconds. The two phases of the system clock are used i n a standard fashion by most display-element generators. Normally, a s i n g l e point within a d i s p l a y element i s generated during one complete clock c y c l e . During the f i r s t clock phase, a display-element generator modifies the X and Y d i s p l a y co-ordinates as required for a s p e c i f i c d i s p l a y point. The optimum time duration f o r C l can be selected by each element generator to provide the appropriate beam excursion and s e t t l i n g time. C2 i s normally used to unblank the CRT beam, d i s p l a y i n g the s i n g l e point. 3.7 Display-Element Generators 3.7.1 The Point and Graph-Point Generator Points and graph-point functions are performed by a s i n g l e display-element generator since most of the processing requirements 37,. are common to both. In each case, one d i s p l a y axis i s set to an absolute value, and i n the case of graph-point i n s t r u c t i o n s , the other d i s p l a y axis i s incremented. Figure 3.16 provides a simple block diagram of the point and graph-point generator, i n d i c a t i n g the si g n a l s used i n the generation process. Figure 3.17 i l l u s t r a t e s the fundamental timing waveforms during element generation. Element generation i s i n i t i a t e d when the d i s p l a y processor asserts e i t h e r "START POINT" or "START GRAPH-POINT". The s t a r t s i g n a l i s used to generate e i t h e r "LOAD X" or "LOAD Y" (according to the content of the "AX" i n s t r u c t i o n f i e l d ) , t r a n s f e r r i n g the absolute co-ordinate to the X or Y up/down counter v i a the DAT BUS. In the case of the graph-point i n s t r u c t i o n , the s t a r t s i g n a l i s used to generate a toggle s i g n a l , (TOGGLE Y or TOGGLE X) incrementing the appropriate co-ordinate axis counter. The s t a r t s i g n a l i s also used to i n i t i a t e one f u l l cycle of the two-phase clock by as s e r t i n g "ENABLE CLOCK". Phase 1 of the two-phase clock, C l , i s used to transf e r the contents of the X and Y up/down counters to t h e i r associated D/A buffer r e g i s t e r s . The duration of C l i s determined by the content of the "D" i n s t r u c t i o n f i e l d , providing f o r e i t h e r a t y p i c a l (1-inch), or worst case (15-inch) beam d e f l e c t i o n . When C l expires, the second clock phase, C2, i s generated. C2 i s o p t i o n a l l y used to unblank the d i s p l a y o s c i l l o s c o p e beam, according to the content of the "B" i n s t r u c t i o n f i e l d . C2 i s used to assert "FUNCTION COMPLETE", terminating the element generation process. 38, START POINT START. GRAPH-POINT ENABLE^LOCK - H c i C2 «asg • •—1 FUNCTION COMPLETE IR 1 BUS POINT & GRAPH-POINT GENERATOR f) COUNT DIRECTION -©•Y COUNT DIRECTION -©.TOGGLE X .^TOGGLE Y _^LOAD X jte.LOAD Y -^UNBLANK FIGURE 3.16 THE POINT AND GRAPH-POINT GENERATOR START ENABLE CLOCK C l C2 | FIGURE 3.17 POINT AND GRAPH-POINT TIMING 39, 3.7.2 The Character Generator Alphanumeric characters are constructed i n a 5 by 7 dot-matrix format by the character generator. Characters are generated using the X-axis and Y-minor a x i s D/A converters. Figure 3.18 i l l u s t r a t e s the beam p o s i t i o n i n g during character generation. A character i s generated i n 5 v e r t i c a l segments, with each segment produced by incrementing the Y-minor axis 6 times. The Y-minor axis co-ordinate,is then cleared and the X-axis counter incremented to p o s i t i o n the beam for the next v e r t i c a l segment. When the 5 v e r t i c a l segments are complete, an a d d i t i o n a l X-axis increment po s i t i o n s the beam i n readiness for the next character. Figure 3.19 provides a s i m p l i f i e d block diagram of the character generator. The diagram i l l u s t r a t e s the primary components of the character generator; these include the h o r i z o n t a l and v e r t i c a l counters, the character read-only-memory (ROM), Y-minor axis D/A converter, a s h i f t r e g i s t e r and the c o n t r o l u n i t . The h o r i z o n t a l counter i s a 3-bit, modulo-5 counter used to sequence through the 5 v e r t i c a l segments. The v e r t i c a l counter i s a 3-bit, modulo-7 counter which i s incremented through a l l states during the generation of each v e r t i c a l segment. The character read-only-memory i s a National Semiconductor Corporation s t a t i c MOS 3072-bit ROM used to convert a 6-bit ASCII character code to the required dot-matrix pattern. The r e s u l t of each ROM access determines which of the seven beam p o s i t i o n s are to be unblanked during the generation of a v e r t i c a l segment. The low-order b i t s of the ROM address are the 6^bit ASCII character code, and the high-order b i t s are the v e r t i c a l segment number, defined by the 40, FIGURE 3,18 BEAM POSITIONING DURING CHARACTER GENERATION 41, START CHARACTER ENABLE CLOCK «ss§— Cl C2 CHARACTER COMPLETE CHARACTER GENERATOR CONTROL UNIT CLEAR i TOGGLE VERTICAL COUNTER TOGGLE HORIZONTAL COUNTER 7\ ROM ADDRESS TOGGLE X B» LOAD X D/A UNBLANK LOAD D/A Y Y MINOR ,> MINOR REGIS- D/A TER Y MINOR -®»AXIS SHIFT REGISTER 7 v CHARACTER ROM IRM BUS FIGURE 3.19 THE CHARACTER GENERATOR START CHARACTER ENABLE CLOCK Cl C2 LOAD SHIFT REG. SERIAL DATA _ UNBLANK TOGGLE X VERTICAL COUNTER STATE 0 Y MINOR REGISTER STATE CHARACTER COMPLETE— -hi-1 _ 0 6 0 I 6 FIGURE 3.20 CHilRACTER TIMING 43, h o r i z o n t a l counter. A s h i f t r e g i s t e r i s used to hold ROM data during v e r t i c a l segment generation. Y-minor axis components include a 3-bit Y-minor r e g i s t e r and the associated Y-minor D/A converter. The character generator c o n t r o l u n i t provides the c o n t r o l signals required f o r character generation. Figure 3.20 i l l u s t r a t e s a portion of the timing waveforms during the generation of a s i n g l e character. "START CHAR" i s asserted by the d i s p l a y processor to i n i t i a t e character generation. The low-order 8 b i t s of IR1 are switched onto the IRM BUS; the h o r i z o n t a l and v e r t i c a l counters are cleared; and the two-phase clock i s enabled. The 7-bit ROM word s p e c i f i e d by the h o r i z o n t a l counter and the ASCII code i s p a r a l l e l - l o a d e d into the s h i f t r e g i s t e r by the f i r s t clock phase, C l . C l i s also used to strobe the v e r t i c a l counter into the Y-minor axis buffer r e g i s t e r and the X-axis up/down counter to the X-axis buffer r e g i s t e r . The r i s i n g edge of C2 i s used to increment the v e r t i c a l counter, and the d i s p l a y o s c i l l o s c o p e beam i s unblanked during the second clock phase. S h i f t r e g i s t e r data i s s h i f t e d on the f a l l i n g edge of C2. The remaining 6 points i n the f i r s t v e r t i c a l segment are generated i n a s i m i l a r fashion. Following the seventh point, the v e r -t i c a l counter overflows, r e s e t t i n g i t to zero and incrementing the h o r i z o n t a l counter. A new ROM word i s transferred to the s h i f t r e g i s t e r , the X-axis up/down counter i s incremented, and the gener-a t i o n of the next v e r t i c a l segment i s i n i t i a t e d . The process i s repeated u n t i l 5 v e r t i c a l segments have been generated, completing the character. An extra clock c y c l e i s allowed, 44, during which a n a d d i t i o n a l X-axis increment i s generated, the Y-minor r e g i s t e r i s cleared and "CHARACTER COMPLETE" i s asserted. 3.7.3 The Short-Vector Generator Short vectors, as described i n 3.2.6, are constructed by the short-vector generator. Short vectors are generated using the X and Y major axis D/A converters. Figure 3.21 provides a s i m p l i f i e d block diagram of the short-vector generator. Major components include: the length counter, the v e c t o r - d i r e c t i o n decoder, and the c o n t r o l u n i t . The length counter i s a 3-bit modulo-7 counter used to determine the length of a short vector. Vector d i r e c t i o n i s established by decoding the "D" f i e l d of the short-vector i n s t r u c t i o n . The v e c t o r - d i r e c t i o n decoder t r a n s l a t e s the "D" f i e l d into the required X and Y-axis up/down counter d i r e c t i o n s i g n a l s , and routes the master toggle s i g n a l (generated by the c o n t r o l unit) to the appropriate axis-counter. Control signals used during short-vector generation are derived from the c o n t r o l u n i t . Figure 3.22 i l l u s t r a t e s the fundamental waveforms associated with the generation of a s i n g l e short vector. Short-vector generation i s i n i t i a t e d when the d i s p l a y pro-cessor asserts "START SHORT VECTOR". The low-order 8 b i t s of IR1 are switched onto the IRM BUS, and the two-phase clock i s enabled. The f i r s t occurrence of C l i s used to load the length counter from the IRM BUS. The r i s i n g edge of C2 i s used to toggle the appropriate X and Y-axis up/down counters. The length counter i s incremented by the r i s i n g edge of C l , and the axis up/down counters are tra n s f e r r e d to the 45, S T A R T V E C T O R E N A B L E C L O C K C l C2 - H S H O R T _ V E C T O R C O M P C STE I R M B U S S H O R T - V E C T O R C O N T R O L U N I T L O A D T O G G L E O V E R -F L O W L E N G T H C O U N T E R TV-M A S T E R T O G G L E U N B L A N K V E C T O R D I R E C T I O N D E C O D E R X C O U N T D I R E C T I O N ^ T O G G L E X Y C O U N T D I R E C T I O N T O G G L E Y F I G U R E 3 . 2 1 T H E S H O R T - V E C T O R G E N E R A T O R START SHORT VECT ENABLE CLOCK_ C l C2 TOGGLE U/D CNTRS LOAD D/A BUFFERS UNBLANK COMPLETE LENGTH - •- • I I COUNTER . 1 . 4 . 1 5 | 6 | 7 | . 0 STATE FIGURE 3.22 SHORT-VECTOR TIMING 47, appropriate D/A buffer r e g i s t e r s . If the "B" b i t of the short-vector i n s t r u c t i o n i s set, the d i s p l a y o s c i l l o s c o p e beam i s unblanked during the second occurrence of C2, d i s p l a y i n g the f i r s t point i n the vector. The second occurrence of C2 i s also used to toggle the axis up/down counters, i n i t i a t i n g the generation of the second vector point. A d d i t i o n a l short-vector points are generated i n t h i s fashion u n t i l the length counter i s incremented to the zero s t a t e . The l a s t vector point i s displayed, completing a s i n g l e short vector. Assertion of "SHORT VECTOR COMPLETE" then restores c o n t r o l to the d i s p l a y processor. 3.7.4 The Long-Vector Generator Long vectors, capable of spanning the e n t i r e d i s p l a y o s c i l l o s c o p e screen, are constructed by the long-vector generator. Vector length and d i r e c t i o n are s p e c i f i e d by delta-X (DX) and delta-Y (DY) values i n sign-magnitude form. The long-vector generator provides an approximation to the vector by d i s p l a y i n g points at roughly equal i n t e r v a l s along the path of the true vector. Complete d e t a i l s of the vector generation algorithm are provided as Appendix 1. Figure 3.23 provides an overview of the long-vector gener-ator. The long-vector generator consists of the vector counter, an X and Y change detector and the c o n t r o l u n i t . The vector counter i s a 10-bit special-purpose up-counter used to e s t a b l i s h the length of a long vector. In order to s a t i s f y the vector generation algorithm, the s i z e of the vector counter need N only be N b i t s , where DX and DY are each l e s s than 2 . To minimize the time required to produce a s p e c i f i c vector, some vector-counter 48. S T A R T L O N G -V E C T O R ENABLE C L O C K C l C 2 L O N G . V E C T O R C O M P L E T E " L O N G - V E C T O R C O N T R O L U N I T IR1 V C T O G G L E M A S T E R T O G G L E V C O V F L O V E C T O R C O U N T E R ( V C ) IR2 © — E H 3 3 1 2 X C H A N G E D E T E C T O R ( X C D ) Y C H A N G E D E T E C T O R ( Y C D ) X C O U N T D I R E C T I O N T O G G L E X T O G G L E Y Y C O U N T " D I P S C T I O N F I G U R E 3 . 2 3 T H E L O N G - V E C T O R G E N E R A T O R 4 9 « b i t s are automatically disabled (according to the highest power of 2 contained i n the larger of DX or DY). The X and Y change detectors compare the vector-counter content to the values of DX and DY, r e s p e c t i v e l y , and modify the major axis up/down counters as required to produce the desired vector.. Control signals required f o r vector generation are provided by the con t r o l u n i t . Figure 3.24 i l l u s t r a t e s the timing s i g n a l s used i n the generation of a s p e c i f i c vector. In t h i s case, the vector corresponds to DX=7 and DY=4, as shown i n Figure 3.5. Vector generation i s i n i t i a t e d by the s i g n a l "START LONG-VECTOR", which r e s u l t s i n the enabling of the two-phase clock. The r i s i n g edge of C l toggles the vector counter, i n prepartion for d i s p l a y of the f i r s t vector point. C2 i s used to modify the X and Y-axis up/down counters through the sig n a l s TOGGLE X and TOGGLE Y (C2 i s blocked by the X and Y change detectors when an axis m o d i f i c a t i o n i s not required). The contents of the X and Y-axis up/down counters are transferred to the corresponding D/A converters on the next occurrence of C l . The d i s p l a y o s c i l l o s c o p e beam i s unblanked during the second occurrence of C2 and completes the di s p l a y of the f i r s t vector point. The remaining vector points are generated i n an i d e n t i c a l fashion u n t i l the vector counter overflows to zero. On completion of the l a s t vector point, "LONG VECTOR COMPLETE" i s asserted, r e s t o r i n g c o n t r o l to the d i s p l a y processor. 50. START | LONG VECTOR ENABLE CLOCK!  £2 . I I I I I I I I I I I I I I £2 I I __l I 1 I 1 1 1 I I l_ I TOGGLE VC 1 I I | I I I I I I J I I I VC STATE. 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 0 TOGGLE X j 1 | I I j I I I I I I I TOGGLE Y I. .1 II II I LOAD D/A'S |_J | \ | 1 UNBLANK | I » 1 | I | | 1 1 t I VC OVFLO  VECTOR COMPLETE FIGURE 3.24 LONG-VECTOR TIMING 51, 4. IMPLEMENTATION OF THE GRAPHICS DISPLAY SYSTEM 4.1 A Modular Approach The graphics display system was implemented i n a highly modular form for the following reasons: a) to simplify trouble-shooting (modularity permits the removal of some ci r c u i t boards without affecting the operation of others, providing a means for quickly isolating many faults) b) to permit the addition of special-purpose display-element generators. Circuitry associated with each display-element generator i s indepen-dent from a l l others, so addition of a new element generator i s r e l a -tively simple. The main restriction i s that any display-element generator must conform to one of the standard instruction sequences. 4.2 Purchased Components Where possible, standard "off-the-shelf" components were purchased for use i n the graphics display system. The major purchased components include: a) the display oscilloscope, b) the major axis - D/A converters, c) power-supplies and d) c i r c u i t board mounting panels. 4.3 The Logic Family The graphics display system was implemented using 7400 and 3000 series TTL integrated circuits.' These logic families provide several advantages, including the existence of a large number of func-tions in the product lines, low propagation delays, compatibility with 52, the host CPU and a v a i l a b i l i t y . 4.4 Construction Techniques The graphics d i s p l a y system was constructed using D i g i t a l Equipment Corporation H-series wire-wrap mounting panels. The H-series panels accommodate up to 32 c i r c u i t boards, with 72.conductor p o s i t i o n s for each board. C i r c u i t boards with up to 50 wire-wrap sockets f o r 14- or 16-pin integrated c i r c u i t s provided the basi s f o r construction of the di s p l a y system. Approximately 15 c i r c u i t boards were required f o r implementation of the special-purpose d i s p l a y system c i r c u i t r y . Wire-wrap techniques were generally u t i l i z e d f o r c i r c u i t interconnection. The primary advantage off e r e d by t h i s technique i s the a b i l i t y to quickly make changes to c i r c u i t s . 53, 5. PERFORMANCE OF THE GRAPHICS DISPLAY SYSTEM Table 5.1 provides a summary of observed element generation time and calculated host processor overhead. CPU overheads are based on DMA fetches from the Supernova processor. A l l times are approximate. Element generation times are based p r i m a r i l y on the s e t t l i n g and point d i s p l a y requirements of the d i s p l a y o s c i l l o s c o p e . Character, short-vector and long-vector elements require at l e a s t 1.6 microseconds per point (1.2 microseconds to allow o s c i l l o s c o p e s e t t l i n g , and 400 nanoseconds f or point d i s p l a y ) . The t o t a l " f l i c k e r - f r e e " capacity of the d i s p l a y system i s l a r g e l y dependent on the scale f a c t o r used during long and short vector generation; as the scale f a c t o r i s increased, the capacity i s also increased. The subjective appearance of d i s p l a y elements ( p a r t i -f a c t o r . The minimum scale f a c t o r provides f o r the generation of a long vector on a 0.01-inch g r i d . Since the o s c i l l o s c o p e spot diameter i s 0.02 inches, a vector generated using the minimum scale f a c t o r appears continuous and fair l y " s m o o t h " to the human eye. A vector generated using the maximum scale f a c t o r i s constructed on a .08-inch g r i d , and the eye i s very aware of the d i s c r e t e point make-up of the vector. F l i c k e r - f r e e capacity of the d i s p l a y system f o r graph gener-a t i o n i s dependent on both the scale f a c t o r and the programmable delay. Capacity and CPU overheads are summarized i n Table 5.2. Small characters are generated on a 0.02-inch g r i d using scale factor 2. At t h i s s c a le f a c t o r , characters are approximately GENERATION CPU TIME OVERHEAD ELEMENT (ysec) (ysec) POINT \ SHORT DELAY 5 1 GRAPH-POINTJ LONG.DELAY 15 1 CHARACTER 60 0.5 SHORT VECTOR 2 + 2N (1) 0.5 LONG VECTOR. 4 + 2N (1) 2 (1) N = NUMBER OF POINTS IN ELEMENT TABLE 5.1 DISPLAY SYSTEM PERFORMANCE PROGRAMMABLE SCALE APPROXIMATE APPROXIMATE DELAY FACTOR CAPACITY (1) CPU LOADING SHORT MINIMUM 10 20% SHORT MAXIMUM 80 20% LONG MINIMUM 3 6.5% LONG MAXIMUM 26 6.5% CAPACITY - The number of f u l l - s c r e e n (10") graph p l o t s which can be accommodated at a r e p e t i t i o n r a t e of 20 frames per second. TABLE 5.2 GRAPH GENERATION PERFORMANCE 55, 0.14-inch high by 0.1-inch wide, and 70 characters can be accommodated across the f u l l width of the screen. At scale f a c t o r 2, the d i s c r e t e point make-up of each character i s only detectable on close examination. 20 f u l l l i n e s of characters can be displayed without objectionable f l i c k e r (20 r e p e t i t i o n s per second^ at the expense of l e s s than 2% of host CPU capacity. Up to 5000 short vectors (containing an average of 4 points each) can be displayed without annoying f l i c k e r . Capacity i s inde-pendent of the scale f a c t o r employed. Host CPU loading at f u l l capa-c i t y i s approximately 5%. Long vectors can be generated at various rates ranging from 5 inches per m i l l i s e c o n d (minimum scale f a c t o r ) to 40 inches per m i l l i s e c o n d (maximum scale f a c t o r ) . At minimum scale f a c t o r , at l e a s t 25 ten-inch vectors can be generated without annoying f l i c k e r , at the expense of approximately 0.1% of host CPU capacity. The capacity and CPU loading are increased by a f a c t o r of 8 when the maximum sc a l e f a c t o r i s employed. T y p i c a l displays w i l l c o n s ist of a mixture of the various element types. T o t a l host CPU loading i s a function of the s p e c i f i c d i s p l a y , but w i l l normally not exceed 10%.of the Supernova capacity. 56, 6. CONCLUSIONS A computer-based display system was constructed to augment the existing PDP-9 f a c i l i t y . The limitations of the PDP-9 system were overcome through the use of a high bandwidth display oscilloscope,, and a more sophisticated display processor. By accessing and executing display instructions stored in host CPU memory, the display processor relieves much of the host CPU overhead associated with the maintenance of a graphics display. The a b i l i t y to generate complex display elements (for example, characters and vectors) from single-display instructions reduces host CPU display software requirements consi-derably. During the four years between construction of the display system and the writing of this thesis, d i g i t a l technology has advanced considerably. Examination of alternative solutions to display system implementation in light of the current technology i s appropriate. An obvious alternative solution to the problem i s to u t i l i z e the design of the graphics display system (essentially as outlined i n this thesis), but implement the design with state-of-the-art components. Extensive use of medium and large-scale integrated circuits would significantly reduce the size and complexity of the display system. Another alternative would take advantage of programmable read-only memories (PROM's) now available. This approach would require a new design, the heart of which would consist of a high-speed PROM-driven processor similar to those now used i n commercially-available "micro-programmable" mini-computers. This approach could be adopted for the display processor only, or i t could be extended to encompass 57, the functions performed by the display-element generators. The use of PROM rather than standard read-only-memory would f a c i l i t a t e a l t e r -ations during system implementation as w e l l as l a t e r additions or a l t e r a t i o n s to the d i s p l a y system. 58, APPENDIX 1 THE VECTOR GENERATION ALGORITHM This appendix provides a d e s c r i p t i o n of the binary ra t e . ; ; m u l t i p l i e r algorithm used i n long-vector generation. Consider an a r b i t r a r y vector between the o r i g i n and a point whose X and Y co-ordinates are DX and DY r e s p e c t i v e l y . I f the vector i s generated i n time T, then the equation for the X and Y components of the d i s p l a y o s c i l l o s c o p e beam as a function of time are simply X = DX(t/T) Y = DY(t/T) To produce an approximation to the desired vector, an algorithm i s required which w i l l provide, for example, DX equal increments of the X-axis co-ordinate value at approximately equal i n t e r v a l s over the time T. C r i T i H T r}c*-r T-i=>s:tr"i r>t-<=>H v a l i i o q rif T W a r i H T W T.7>i-f r - V i ^ a - p \\o -ropr-o— sented as: DX = X 2 2 2 + X 2 1 + X Q2 0, and DY = Y,,22 + Y 2 1 + Y Q2° where X^ and Y^ are binary c o e f f i c i e n t s . An algorithm f o r producing DX increments along the X a x i s , and DY increments along the Y axis 3 over 2 -1 time i n t e r v a l s i s i l l u s t r a t e d i n the following t a b l e . Time Action 9 -i 0 (INCREMENT CO-ORDINATE IF 2 2 2 SPECIFIED CO-EFFICIENTS ARE NON-ZERO) X-Axis Y-Axis 0 0 0 Don't increment Don't increment 0 0 1 X, Y. 0 1 0 Xf Y 2 0 1 1 X, Y , 1 0 0 X0 Y0 1 0 1 X" Y° 1 1 0 X^ Y^ 1 i i yr2 Y* In general terms, for values of DX and DY up to 2 -1, the algorithm can be stated as: a) locate the l e a s t s i g n i f i c a n t non-zero power of two, P, i n the current time, b) increment the X co-ordinate i f the c o e f f i c i e n t X„ _ i s N-P non-zero, c) increment the Y co-ordinate i f the c o e f f i c i e n t Y„ _ i s N-P non-zero. 60. REFERENCES 1. Prince, M.D., "Man-Computer Graphics f o r Computer-Aided Design", Proceedings of the IEEE, -Vol. 54, No. 12, pp. 1698 - 1708, December, 1966. 2. Mann, R.W., "The "CAD" Project", Mechanical Engineering, pp. 41-43, May, 1965. 3. Skinner, F.D., "Computer Graphics - Where Are We?", Datamation, V o l . 12, No. 5, pp. 28 - 31, May, 1966. 4. Coons, S.A., "Computer Graphics and Innovative Engineering Design", Datamation, Vol. 12, No. 5, pp. 32 - 34, May, 1966. 5. Scharf, J . , "Simplify Design with Computer Graphics", The E l e c t r o n i c  Engineer, pp. 67 - 71, December, 1968. 6. Myer, T.H., Sutherland, I.E., "On the Design of Display Systems", Coimnunicadons of the ACH, Vol. 11, No. 6, pp. 410 - 414, June, 1965. 7. English, W., "How to Use the Nova and the Supernova", Mass.: Data General Corporation, 1970. 8. Sherr, S., "Fundamentals of Display System Design", New York: John Wiley and Sons, Inc., pp. 280 - 306, 1970. 9. Arnstein, W., Mergler, H.W., Singer, B., " D i g i t a l Linear I n t e r p o l a t i o n and the Binary Rate M u l t i p l i e r " , Control Engineering, pp. 79 - 83, June, 1964. 

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