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UBC Theses and Dissertations

Display system for computer graphics Hamilton, Frank Robert 1974

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A DISPLAY SYSTEM FOR COMPUTER GRAPHICS  by  FRANK ROBERT HAMILTON  B.A. Sc., U n i v e r s i t y o f B r i t i s h  Columbia, 1968  A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF  MASTER" OF APPLIED SCIENCE  i n t h e Department  of  Electrical  We a c c e p t t h i s  Engineering  t h e s i s as conforming t o t h e  required  standard  THE UNIVERSITY OF BRITISH COLUMBIA  September, 1974  In p r e s e n t i n g an the  this  thesis  a d v a n c e d d e g r e e at Library  shall  I f u r t h e r agree for  scholarly  by  his  of  this  written  the  fulfilment of  University  of  make i t f r e e l y that permission  p u r p o s e s may  representatives.  be  available  for  for extensive  granted  gain  permission.  of  The U n i v e r s i t y o f B r i t i s h V a n c o u v e r 8, Canada  British  by  the  It i s understood  thesis for financial  Department  Date  in p a r t i a l  Columbia  shall  requirements  Columbia,  Head o f my  be  I agree  r e f e r e n c e and copying of  that  not  the  that  study.  this  thesis  Department  copying or  for  or  publication  allowed without  my  ABSTRACT  A d i s p l a y system f o r computer  graphics i s described i n t h i s  thesis.  The r e q u i r e m e n t s of the d i s p l a y system a r e d e f i n e d , w i t h t h e  emphasis  on use i n computer-aided network d e s i g n .  Several basic design  a l t e r n a t i v e s a r e examined,  and a b a s i c approach i s chosen toward  development  system.  of a p r o t o t y p e  A d e t a i l e d d e s c r i p t i o n of the g r a p h i c s d i s p l a y system t e c t u r e and o p e r a t i o n i s p r o v i d e d .  Details relating  archi-  to the implemen-  t a t i o n o f the p r o t o t y p e system a r e p r o v i d e d , and t h e performance o f the system i s examined.  ii  TABLE OF CONTENTS  Page  LIST OF ILLUSTRATIONS  v  ACKNOWLEDGEMENT 1.  2.  3.  v i i  INTRODUCTION  •  1.1  Statement o f t h e Problem  1.2  Scope o f t h e T h e s i s  •  1 1  ..vC.......  1  DESIGN OF THE GRAPHICS DISPLAY SYSTEM  2  2.1  Graphics Display  2  2.2  Design Considerations  System Requirements  3  2.2.1  Basic Display  System A r c h i t e c t u r e  2.2.2  Analog V e r s u s D i g i t a l T e c h n i q u e s  5  2.2.3  Display-Element Generation  5  2.2.3.1  D i s p l a y Program S u b r o u t i n e s  5  2.2.3.2  Character  6  2.2.3.3  Vector  Generation  Generation  3  6  FUNCTIONAL ORGANIZATION OF THE GRAPHICS DISPLAY SYSTEM ...  8  3.1  Display  System Overview  8  3.2  Display  Instructions  11  3.2.1  Control  Instructions  3.2.2  Transfer  3.2.3  Point  Instructions  13  3.2.4  Graph-Point I n s t r u c t i o n s  14  3.'2.5  Character  14  3.2.6  Short-Vector  3.2.7  Long-Vector I n s t r u c t i o n s  Instructions  Instructions Instructions  iii  12 12  16 16  Page  4.  3.3  Host Computer I n t e r f a c e  18  3.4  The D i s p l a y P r o c e s s o r  24  3.4.1  The Immediate I n s t r u c t i o n Sequence  28  3.4.2  The Single-Word  29  3.4.3  The Half-Word  3.4.4  The Double-Word I n s t r u c t i o n Sequence  I n s t r u c t i o n Sequence  I n s t r u c t i o n Sequence  29 32  3.5  The D i s p l a y O s c i l l o s c o p e I n t e r f a c e  32  3.6  The  34  3.7  Display-Element Generators  36  3.7.1  The P o i n t and Graph-Point G e n e r a t o r  36  3.7.2  The C h a r a c t e r Generator  39  3.7.3  The S h o r t - V e c t o r G e n e r a t o r  44  3.-7.4  The Long-Vector G e n e r a t o r  47  System C l o c k  IMPLEMENTATION OF THE GRAPHICS DISPLAY SYSTEM 4.1  A Modular Approach  4.2  Purchased  4.3  The L o g i c F a m i l y  4.4  C o n s t r u c t i o n Techniques  '  Components  5.  PERFORMANCE OF THE  6.  CONCLUSIONS  APPENDIX 1  51 ••••  51 51 '51 52  GRAPHICS DISPLAY SYSTEM  53 ......  THE VECTOR GENERATION ALGORITHM  REFERENCES  56 58 60  iv  LIST OF  ILLUSTRATIONS  Figure  Page  3.1  System B l o c k Diagram  9  3.2  D i s p l a y I n s t r u c t i o n Formats  10  3.3  The ASCII C h a r a c t e r Set  15  3.4  T y p i c a l Short V e c t o r s  15  3.5  A Sample Long V e c t o r  17  3.6  CPU  Interface  19  3.7  CPU  I n t e r f a c e Timing  23  3.8  Display Processor  25  3.9  The  27  Immediate Sequence  3.10  The Single-Word  Sequence  27  3.11  The Half-Word  3.12  The Double-Word Sequence  31  3.13  The D i s p l a y O s c i l l o s c o p e I n t e r f a c e  33  3.14  The  35  3.15  C l o c k Timing  35  3.16  The P o i n t , a n d Graph-Point G e n e r a t o r  38  3.17  P o i n t , a n d Graph-Point Timing  38  3.18  Beam P o s i t i o n i n g D u r i n g C h a r a c t e r G e n e r a t i o n  40  3.19  The C h a r a c t e r Generator  41  3.20  Character Timing  42  3.21  The  45  3.22  S h o r t - V e c t o r Timing  46  3.23  The Long-Vector  48  3.24  Long-Vector  Sequence  30  System C l o c k  Short-Vector Generator  Generator  Timing  50  v  LIST OF TABLES  Table  Page  3.1  Input-Output T r a n s f e r  Instructions  5.1  D i s p l a y System Performance  54  5.2  Graph G e n e r a t i o n  54  Performance  vi  21  ACKNOWLEDGEMENT  I am g r a t e f u l t o t h e N a t i o n a l R e s e a r c h C o u n c i l o f Canada f o r support r e c e i v e d d u r i n g I would  t h e term o f t h i s p r o j e c t .  l i k e t o thank Dr. A.D. Moore f o r h i s i n v a l u a b l e g u i d a n c e  w h i l e s u p e r v i s i n g t h i s p r o j e c t and Dr. M.R. I t o f o r r e a d i n g and p r o v i d i n g h e l p f u l  this thesis  suggestions.  S p e c i a l thanks go t o Dr. J.S. MacDonald, M e s s r s . D. Heywood, S. Semrau, G. A u s t i n and N. Thompson f o r t h e many u s e f u l i d e a s r e s u l t i n g from d i s c u s s i o n s . I w i s h t o acknowledge t h e a s s i s t a n c e p r o v i d e d who c o n s t r u c t e d  by Mr. B. N u t t a l  t h e d i s p l a y system, and by my w i f e who typed t h i s t h e s i s .  vii  1.  1.1  INTRODUCTION  Statement o f the Problem Computer g r a p h i c s has l o n g been r e c o g n i z e d  as a d e s i r a b l e  (perhaps e s s e n t i a l ) approach t o i n f o r m a t i o n d i s p l a y i n c e r t a i n cations niques  (1,2,3,4).  appli-  I n p a r t i c u l a r , t h e use o f g r a p h i c s d i s p l a y t e c h -  i n interactive,  computer-aided d e s i g n has proven t o be i n v a l -  u a b l e . (5) Computer g r a p h i c s t e c h n i q u e s  have been u t i l i z e d  on t h e PDP-9  i n s t a l l a t i o n a t t h e U n i v e r s i t y o f B r i t i s h Columbia Department o f E l e c t r i c a l Engineering  f o r several years.  g r a p h i c s f a c i l i t y have been noted,  L i m i t a t i o n s on t h e e x i s t i n g  t h e most important  the r e s t r i c t i v e c e n t r a l p r o c e s s i n g u n i t  o f which a r e  (CPU) overheads d u r i n g t h e  maintenance o f a g r a p h i c s d i s p l a y , and t h e e x c e s s i v e d i s p l a y g e n e r a t i o n ^ -I  j..  / r  --"">-  Kf-  -  *_ _  <^VJ.«_  _  i  I.O  i  J-OV.  i — r  i  A. i _  _j  U U U U . i u (.H  —  -i - —  uu-O^J-C^  i  -i  i  -i  \  WOk.^.J.J.V^^U.Oj/C:/  *  .  ,  in "flickering" displays. 1.2  Scope o f t h e T h e s i s The  t h e s i s w i l l d e s c r i b e t h e s t e p s l e a d i n g t o t h e implemen-  t a t i o n o f a g r a p h i c s d i s p l a y system f o r u s e a t t h e U n i v e r s i t y o f B r i t i s h Columbia Department o f E l e c t r i c a l E n g i n e e r i n g . examines t h e requirements  Chapter 2  o f such a system, and p r e s e n t s t h e b a s i c  design c o n s i d e r a t i o n s p e r t i n e n t to these requirements.  Chapter 3 p r o -  v i d e s t h e d e t a i l e d f u n c t i o n a l o r g a n i z a t i o n o f t h e d i s p l a y system, and Chapter 4 d e s c r i b e s t h e implementation  details.  System performance  i s d e s c r i b e d i n Chapter 5, and c o n c l u s i o n s p r e s e n t e d  i n Chapter 6.  ~  ._  2.  2.1  DESIGN OF THE  GRAPHICS DISPLAY SYSTEM  G r a p h i c s D i s p l a y System Requirements P r i o r to the d e s i g n of a g r a p h i c s d i s p l a y system, some  g e n e r a l requirements  must be e s t a b l i s h e d . .To e s t a b l i s h t h e s e r e q u i r e -  ments, a g r a p h i c s f a c i l i t y and  f o r use  i n computer-aided network d e s i g n  a n a l y s i s i s considered. D i s p l a y system requirements  d e s i g n and schematic  a n a l y s i s i n c l u d e the c a p a b i l i t y of g e n e r a t i n g and c i r c u i t diagrams i n a h i g h l y i n t e r a c t i v e f a s h i o n .  c a p a b i l i t y of d i s p l a y i n g signals i s also required. generate  f o r computer-aided network  the response  The  o f a network to v a r i o u s i n p u t  I d e a l l y , i t i s d e s i r a b l e to be a b l e to  a c o n t i n u o u s l y v a r y i n g response  e f f e c t of a continuous  altering  (perhaps  v a r i a t i o n i n a network  illustrating  the  parameter).  C l e a r l y , the computer s u p e r v i s i n g the d i s p l a y system must c a p a b l e of more than the support  of a s t a t i c d i s p l a y .  Computer  heads a s s o c i a t e d w i t h the g e n e r a t i o n of the d i s p l a y must be The  oscilloscope utilized  oscilloscope.  The  over-  minimized.  i n the g r a p h i c s system must  h i g h l y dynamic d i s p l a y s , e l i m i n a t i n g the p o s s i b i l i t y of a  permit  storage  o s c i l l o s c o p e s h o u l d have a r e s o l u t i o n of a t  least  100 p o i n t s to the i n c h , w i t h a u s a b l e d i s p l a y a r e a of 10 i n c h e s by inches.  At l e a s t 8 d i s t i n c t The  i n t e n s i t y l e v e l s s h o u l d be  10  provided.  system must be c a p a b l e of g e n e r a t i n g a complex d i s p l a y  w i t h a r e f r e s h r a t e of a t l e a s t 20 times The  be  each second.  g r a p h i c s system should be s i m p l e to use.  o f common d i s p l a y elements, i n c l u d i n g p o i n t s , graphs,  Generation v e c t o r s , and  c h a r a c t e r s should be simple from the u s e r p o i n t of view.  .3, . 2.2  Design  2.2.1  Considerations  B a s i c D i s p l a y System A r c h i t e c t u r e C o n s i d e r a t i o n o f p o s s i b l e forms o f c o m p u t e r / d i s p l a y  system  i n t e r a c t i o n suggests s e v e r a l p o s s i b i l i t i e s f o r t h e b a s i c d i s p l a y system architecture. complexity  Choice o f a b a s i c a r c h i t e c t u r e is- made on t h e b a s i s o f  and the e f f e c t on host One  computer overheads.  p o s s i b l e form o f c o m p u t e r / d i s p l a y  i s e x e m p l i f i e d by t h e e x i s t i n g PDP-9 f a c i l i t y .  system  interaction  In t h i s case,  a PDP-9  program must i n i t i a t e t h e d i s p l a y o f each p o i n t v i a i n p u t - o u t p u t transfer  (IOT) i n s t r u c t i o n s ,  is i t s simplicity;  t h e main advantage o f t h i s  approach  the p r i m a r y d i s a d v a n t a g e i s t h e e x t e n s i v e CPU  involvement i n d i s p l a y g e n e r a t i o n ment c o u l d be l e s s e n e d  and maintenance.  Computer i n v o l v -  c o n s i d e r a b l y by a d d i t i o n o f hardware t o  g e n e r a t e common d i s p l a y elements, such as c h a r a c t e r s and v e c t o r s . C e r t a i n types o f d i s p l a y s s t i l l  r e q u i r e c o n s i d e r a b l e host  computer  involvement; f o r example, maintenance o f an i r r e g u l a r graph c o n t a i n ing  1000 p o i n t s  (such as a network r e s p o n s e t o a s t e p i n p u t ) would  f u l l y l o a d most s m a l l computers i f a l l d a t a i s passed v i a IOT i n s t r u c tions. A second form o f c o m p u t e r / d i s p l a y the d i r e c t memory a c c e s s puters  (6,7).  (DMA) f a c i l i t y a v a i l a b l e on most s m a l l com-  I n t h i s c a s e , d a t a r e p r e s e n t i n g an e n t i r e d i s p l a y c a n  be c o n s t r u c t e d by t h e h o s t case,  system i n t e r a c t i o n i s v i a  computer i n i t s main memory.  t h e memory r e s i d e n t d i s p l a y d a t a  In the simplest  ( t h e " d i s p l a y program") c o u l d  c o n s i s t o f s e q u e n t i a l p a i r s o f X and Y c o - o r d i n a t e r v a l u e s , and a beam unblanking  indication.  To g e n e r a t e a d i s p l a y , t h e h o s t  v i d e s t h e d i s p l a y system w i t h via  IOT i n s t r u c t i o n s .  the d a t a  computer  pro-  t a b l e a d d r e s s and a word count  On r e c e i p t o f a "GO" i n d i c a t i o n , t h e d i s p l a y  system a c c e s s e s s e q u e n t i a l d a t a words v i a t h e CMA f a c i l i t y and c o n s t r u c t s the d e s i r e d d i s p l a y .  Following generation of the l a s t p o i n t , the  d i s p l a y system i n t e r r u p t s t h e host computer, tions.  and a w a i t s f u r t h e r  The e n t i r e p r o c e s s i s r e p e a t e d as o f t e n as r e q u i r e d  a flicker-free  instruc-  t o ensure  display.  The d e c r e a s e i n host computer  overhead a s s o c i a t e d w i t h t h i s  type o f d i s p l a y system can be i l l u s t r a t e d u s i n g t h e 1000 p o i n t example.  graph  T y p i c a l l y , each DMA a c c e s s " s t e a l s " 1 m i c r o s e c o n d from t h e  a v a i l a b l e h o s t CPU e x e c u t i o n time; 1000 X-Y c o - o r d i n a t e p a i r s reduce a v a i l a b l e CPU time by 2 m i l l i s e c o n d s .  S i n c e a t l e a s t 30  r e p e t i t i o n s p e r second a r e r e q u i r e d t o e l i m i n a t e f l i c k e r , of t h e graph r e d u c e s h o s t computer  would  generation  c a p a b i l i t i e s by a p p r o x i m a t e l y 6%.  The DMA approach p r o v i d e s a s i g n i f i c a n t d e c r e a s e i n computer overheads compared w i t h t h e programmed I/O approach, b u t has t h e d i s a d v a n t a g e o f i n c r e a s i n g t h e d i s p l a y system c o m p l e x i t y . A t h i r d b a s i c system a r c h i t e c t u r e would s t o r a g e system d e d i c a t e d t o t h e d i s p l a y system approach, the h o s t CPU would  u t i l i z e a large  (6).  t r a n s f e r a d i s p l a y program  system memory v i a e i t h e r IOT i n s t r u c t i o n s o r DMA. g e n e r a t i o n would  With  this  to the d i s p l a y  Subsequent  display  be performed u s i n g t h e d e d i c a t e d memory i n a f a s h i o n  s i m i l a r t o t h e DMA approach d e s c r i b e d  above.  W i t h t h i s approach, h o s t CPU i n v o l v e m e n t i s l i m i t e d t o l o a d i n g t h e d i s p l a y system memory.  I n the case o f a s t a t i c  display,  h o s t CPU overheads a r e n e g l i g i b l e .  I n the case o f a h i g h l y  dynamic  d i s p l a y , overheads a r e n o t s i g n i f i c a n t l y d e c r e a s e d from t h o s e a s s o ciated with the previously described  architectures.  A d i s a d v a n t a g e o f t h e t h i r d approach i s a c o n s i d e r a b l e i n c r e a s e i n c o m p l e x i t y through a d d i t i o n o f t h e l a r g e  dedicated-memory  system. The d i s p l a y system was  implemented u s i n g the DMA  since t h i s basic a r c h i t e c t u r e provides a reasonable complexity 2.2.2  and host CPU  Analog  approach,  compromise between  overheads.  Versus D i g i t a l  Techniques  Analog d i s p l a y g e n e r a t i o n t e c h n i q u e s  (8) p r o v i d e  certain  advantages, p a r t i c u l a r l y i n the g e n e r a t i o n of v e c t o r s and c h a r a c t e r s ; however, they have some major d i s a d v a n t a g e s techniques. a)  compared t o d i g i t a l  These i n c l u d e : a n a l o g c i r c u i t s tend to d r i f t , n e c e s s i t a t i n g f r e q u e n t adjustment,  b)  analog time  On  implementation  i s g e n e r a l l y more d i f f i c u l t ,  consuming.  the b a s i s of these c o n s i d e r a t i o n s , implementation  d i g i t a l t e c h n i q u e s was  adopted.  2.2.3  Generation  Display-Element The DMA  and  approach has  ments a r e generated  severe l i m i t a t i o n s ' i f  as d e s c r i b e d f o r the 1000  Both c o r e requirements  and  CPU  using  a l l display ele-  p o i n t graph example.  overheads a r e r e s t r i c t i v e i n the  case  of complex d i s p l a y s . The  a d d i t i o n of hardware d i s p l a y - e l e m e n t  minates t h e s e r e s t r i c t i o n s .  A vector generator,  o n l y 2 words of c o r e s t o r a g e and presented 2.2.3.1  by a d e l t a - X and D i s p l a y Program  2 DMA  accesses  delta-Y co-ordinate  generators  eli-  f o r example, r e q u i r e s i f the v e c t o r i s r e -  pair.  Subroutines  A s u b r o u t i n e c a p a b i l i t y p r o v i d e s a means o f d e c r e a s i n g requirements  f o r most g r a p h i c d i s p l a y s .  core  6,' A s i n g l e - l e v e l subroutine c a p a b i l i t y requires s t o r i n g a s i n g l e d i s p l a y program address w i t h i n e i t h e r a d i s p l a y system r e g i s t e r , o r a d e d i c a t e d h o s t CPU memory l o c a t i o n . r o u t i n e c a p a b i l i t y r e q u i r e s unique  A multiple-level  (nested)  s t o r a g e f o r a number o f d i s p l a y  gram a d d r e s s e s , hence a c o n s i d e r a b l e i n c r e a s e i n hardware over t h e s i n g l e - l e v e l . To minimize  pro-  complexity  case. complexity a s i n g l e - l e v e l subroutine  was i n c l u d e d i n t h e d i s p l a y system. a r e generated  sub-  by hardware  capability  S i n c e many complex d i s p l a y  elements  (as d e s c r i b e d i n subsequent s e c t i o n s ) t h e  n e s t e d s u b r o u t i n e c a p a b i l i t y i s seldom d e s i r e d f o r m o s t , g r a p h i c : d i s p l a y s . 2.2.3.2  Character  Generation  A s i m p l e approach t o c h a r a c t e r g e n e r a t i o n i s t o g e n e r a t e character v i a a corresponding subroutine. requirements,  but r e q u i r e s s e v e r a l DMA  T h i s approach d e c r e a s e s  each core  accesses during the generation  of most c h a r a c t e r s .  '  Recent i n t r o d u c t i o n o f pre-programmed l a r g e c a p a c i t y r e a d only-memories  (ROM's) p r o v i d e s a more a t t r a c t i v e a l t e r n a t i v e .  p r o v i d e a s i m p l e method o f c o n v e r t i n g a 7 - b i t ASCII (American Code f o r I n f o r m a t i o n Interchange) generate  The ROM's Standard  code i n t o 35 b i n a r y v a l u e s used t o  t h e c h a r a c t e r i n a 5 by 7 d o t - m a t r i x format.  A detailed  des-  c r i p t i o n o f the ROM-driven c h a r a c t e r g e n e r a t o r i s p r o v i d e d i n Chapter 2. 2.2.3.3  Vector  Generation  Two common t e c h n i q u e s a r e o f t e n used to v e c t o r g e n e r a t i o n .  in a digital  Both t e c h n i q u e s produce o n l y an  approach  approximation  to a t r u e v e c t o r . The  first  technique u t i l i z e s d i g i t a l , d i f f e r e n t i a l a n a l y z e r s  7, (DDA's) t o produce  a very accurate approximation.  The t e c h n i q u e r e q u i r e s  q u i t e complex c i r c u i t s . A second method u t i l i z e s a b i n a r y r a t e m u l t i p l i e r algorithm. tion  The a l g o r i t h m produces an adequate,  ( i n some c a s e s ) than the DDA  considerably less  complex.  The BRM  approach  chosen on the b a s i s of  but p o o r e r  (BRM) approxima-  t e c h n i q u e s , but i m p l e m e n t a t i o n i s  ( d e s c r i b e d i n d e t a i l i n Chapter 3)  simplicity.  was  8, 3.  3.1  FUNCTIONAL ORGANIZATION OF THE GRAPHICS DISPLAY SYSTEM  D i s p l a y System Overview A s i m p l i f i e d b l o c k diagram o f t h e g r a p h i c s d i s p l a y system  and  t h e a s s o c i a t e d host computer i s p r o v i d e d i n F i g u r e 3.1. The h o s t computer i s a Data G e n e r a l Supernova, a f a s t  third-  g e n e r a t i o n mini-computer. The major components o f t h e g r a p h i c s d i s p l a y system i n c l u d e a s e t o f i n t e r n a l s t o r a g e r e g i s t e r s , t h r e e D/A c o n v e r t e r s , a s e t o f display-element  g e n e r a t o r s , and the d i s p l a y p r o c e s s o r .  G e n e r a l r e g i s t e r s p r o v i d e temporary s t o r a g e f o r d a t a used i n the g e n e r a t i o n o f a p a r t i c u l a r d i s p l a y element. use  Examples o f t h e i r  i n c l u d e t h e s t o r a g e o f an ASCII code d u r i n g c h a r a c t e r g e n e r a t i o n ,  or the s t o r a g e o f data used d u r i n g v e c t o r g e n e r a t i o n . - ArMif-ional co-ordinates.  rpttisf-prs p r o v i d e s t o r a g e f o r X. Y and Z — a x i s  A s s o c i a t e d D/A c o n v e r t e r s d i r e c t l y d r i v e t h e d i s p l a y  o s c i l l o s c o p e , an O p t i m a t i o n  CDO-6100.  X and Y c o - o r d i n a t e r e g i s t e r s  a r e p a r a l l e l - l o a d i n g up/down c o u n t e r s , r a t h e r than s i m p l e  latch  registers. G e n e r a t i o n o f s p e c i f i c d i s p l a y elements, e i t h e r c h a r a c t e r , long v e c t o r , short vector, point or graph-point corresponding display-element  generator.  i s c o n t r o l l e d by a  Each d i s p l a y - e l e m e n t  gener-  ator converts the data contained i n the general r e g i s t e r s to the c o n t r o l signals  (±X, ±Y, UNBLANK) r e q u i r e d t o g e n e r a t e  a specific display  element. A system c l o c k p r o v i d e s b a s i c t i m i n g s i g n a l s f o r d i s p l a y element g e n e r a t i o n . The h e a r t o f t h e g r a p h i c s d i s p l a y system i s t h e d i s p l a y  9. HOST PROCESSOR & CORE STORAGE  SYSTEM CLOCK  I/O BUS LOAD REGISTERS CPU INTERFACE  START FUNCTION FUNCTION COMPLETE  DISPLAY PROCESSOR  3  GENERAL REGISTERS  3 3  LONGVECTOR GEN-  "SI  SHORT-  e  t Z REG. & D/A  Y REG. & D/A  X REG. & D/A  3  UJ\  POINT GEN.  BLANKING] CONTROL  3  DISPLAY OSCILLOSCOPE  FIGURE 3.1  V L O l  GEN.  DISPLAY CONTROL SIGNALS  .  CHARGEN.  SYSTEM BLOCK DIAGRAM  GRAPH" POINT GEN-  LuaJ  -0  MODE NUMBER  1  MODE NAME  3  o | i 2|  TRANSFER (JMP)  0  0  E  (JSR)  0  1  E  (RSR)  1  1  E  POINT GRAPH-POINT  •h 1  3  6 |'  LP  NXMD  CONTROL  2  INSTRUCTION FORMAT  X X  SHORT VECTOR  B  LONG VECTOR  1  NXMD  0  ^ ^ X " — AX  X  12113  14 | 15  INT  PI  X  PI  CORD  D  E  Dl  B  S  DY  X  DX  ><  FIGURE 3.2 DISPLAY INSTRUCTION FORMATS  E  Cl  E  N2 ,  B  |ll  DISPLAY PROGRAM ADDRESS  D2  1  10  DISPLAY PROGRAM ADDRESS  C2 ,  CHARACTER  8 | 9  SC  USER  B  NXMD  7  Nl  E  11. processor.  The d i s p l a y p r o c e s s o r a c c e s s e s h o s t CPU memory l o c a t i o n s ,  d i r e c t s t h e t r a n s f e r o f d a t a t o i n t e r n a l s t o r a g e r e g i s t e r s , and supervises  operation  of the display-element  generators.  I n i t i a t i o n o f t h e d i s p l a y p r o c e s s i s performed by the h o s t CPU.  Thereafter,  the h o s t CPU i s e s s e n t i a l l y f r e e t o p e r f o r m any  related or t o t a l l y unrelated The  d i s p l a y p r o c e s s o r a c c e s s e s i n s t r u c t i o n s and d a t a from  the host CPU memory.  Each i n s t r u c t i o n i s i n t e r p r e t e d by t h e d i s p l a y  p r o c e s s o r and any a s s o c i a t e d registers.  Following  and  d a t a i s r o u t e d t o one o r more i n t e r n a l  r e g i s t e r loading,  sent t o t h e a p p r o p r i a t e The  function.  display-element  i n d i c a t e s c o m p l e t i o n by a s s e r t i n g  next i n s t r u c t i o n e x e c u t i o n c y c l e . generated by a c c e s s i n g Display  generator.  a "function  complete" s i g n a l i n i t i a t e s t h e  An e n t i r e o s c i l l o s c o p e d i s p l a y i s  and e x e c u t i n g a s e t o f d i s p l a y i n s t r u c t i o n s .  Instructions  d e f i n i n g a complete g r a p h i c d i s p l a y .  Each d i s p l a y  o r two elements o f t h e t o t a l g r a p h i c d i s p l a y .  a summary o f t h e d i s p l a y Display  Figure  t e r , short vector  instruction.  3.2  provides  instruction set.  instructions are interpreted  p r o c e s s o r modes i n c l u d e  instructions  i n s t r u c t i o n defines  by t h e d i s p l a y  c e s s o r a c c o r d i n g t o t h e current: d i s p l a y p r o c e s s o r mode.  t i o n defines  function  complete" s i g n a l .  A d i s p l a y program c o n s i s t s o f a s e t o f d i s p l a y  one  signal i s  display-element generator executes the r e q u i r e d  Occurrence of the " f u n c t i o n  3.2  a "start function"  control, transfer, point,  and l o n g v e c t o r .  A field  pro-  Display  graph-point, charac-  i n each d i s p l a y  instruc-  t h e d i s p l a y p r o c e s s o r mode f o r i n t e r p r e t a t i o n o f t h e next  12. In', one form o f d i s p l a y accesses sequential memory.  display  system o p e r a t i o n , t h e d i s p l a y  processor  i n s t r u c t i o n s d i r e c t l y from t h e h o s t CPU  The f i r s t i n s t r u c t i o n a c c e s s e d i s always i n t e r p r e t e d  i n control  mode. 3.2.1  Control  Instructions  Control various display (INT), s c a l e  system r e g i s t e r s .  The r e g i s t e r s , i n c l u d i n g  intensity  i n t e n s i t y r e g i s t e r provides f o r eight intensity.  1,2,4 o r 8, a p p l i e d  The s c a l e r e g i s t e r d e f i n e s  l e v e l s of d i s p l a y a scale  factor,  i n g r a p h - p o i n t , c h a r a c t e r and v e c t o r element gen-  A " u s e r " r e g i s t e r i s m a i n t a i n e d by t h e d i s p l a y  the programmer's convenience.  system f o r  The r e g i s t e r can be read under program  c o n t r o l , and can be used, f o r example, t o i n d i c a t e t h e p o r t i o n d i s p l a y program b e i n g executed a t t h e time o f a l i g h t An  segments  program.  The  eration.  t o s e t up  (SC) and "user", tend t o remain c o n s t a n t over l a r g e  of any d i s p l a y  oscilloscope  mode i n s t r u c t i o n s a r e used p r i m a r i l y  interrupt f i e l d ,  of a  pen i n t e r r u p t .  P I , o p t i o n a l l y g e n e r a t e s a h o s t CPU  i n t e r r u p t , and a l i g h t pen c o n t r o l b i t , LP, i s p r o v i d e d t o e n a b l e o r disable  l i g h t pen i n t e r r u p t s . The  next mode f i e l d , NXMD, s p e c i f i e s t h e d i s p l a y  mode f o r i n t e r p r e t a t i o n o f t h e next s e q u e n t i a l 3.2.2  Transfer  processor  instruction.  Instructions  Transfer  instructions allow modification  program counter w i t h o u t h o s t CPU i n t e r v e n t i o n .  of the d i s p l a y  Three t y p e s o f  t r a n s f e r i n s t r u c t i o n s a r e d i f f e r e n t i a t e d by t h e code i n i n s t r u c t i o n b i t s 0 and 1. A jump (JMP) i n s t r u c t i o n , code 0, s e t s  the d i s p l a y  program  13.. counter  t o t h e address  s p e c i f i e d by t h e d i s p l a y program address  field.  Code 1 i d e n t i f i e s a s u b r o u t i n e jump i n s t r u c t i o n , JSR. On e x e c u t i o n , t h e d i s p l a y program counter  i s incremented,  saved  s u b r o u t i n e r e g i s t e r , and a new v a l u e f o r t h e d i s p l a y program i s o b t a i n e d from t h e d i s p l a y program address A r e t u r n from s u b r o u t i n e the s u b r o u t i n e r e g i s t e r interrupt  f i e l d , P I , permits The  for  contents  counter  field.  (RSR) i n s t r u c t i o n , code 3, t r a n s f e r s  t o t h e d i s p l a y program c o u n t e r .  An  t h e g e n e r a t i o n o f a host CPU i n t e r r u p t .  " E " b i t i n each t r a n s f e r  e x e c u t i o n o f t h e next  ina  i n s t r u c t i o n s p e c i f i e s t h e mode  instruction.  I f the "E" b i t i s s e t , the  d i s p l a y p r o c e s s o r w i l l e n t e r c o n t r o l mode.  When t h e " E " b i t i s c l e a r ,  a mode change w i l l n o t o c c u r . 3.2.3  Point Instructions P o i n t i n s t r u c t i o n s a r e used t o l o a d t h e X and Y c o - o r d i n a t e  r e g i s t e r s with absolute values. Each p o i n t i n s t r u c t i o n m o d i f i e s a s i n g l e c o - o r d i n a t e r e g i s t e r , as s p e c i f i e d by t h e "AX" f i e l d . i s modified; otherwise,  When AX c o n t a i n s z e r o , t h e X r e g i s t e r  the Y r e g i s t e r  i s modified.  On p o i n t i n s t r u c t i o n e x e c u t i o n , t h e a b s o l u t e v a l u e in  t h e "CORD" f i e l d  i s t r a n s f e r r e d to the s p e c i f i e d co-ordinate  A time d e l a y i s generated i n t h e new p o s i t i o n . "D" f i e l d  content.  contained  t o permit  register.  t h e o s c i l l o s c o p e beam t o s e t t l e  The l e n g t h o f t h e time d e l a y i s i n d i c a t e d by t h e When D c o n t a i n s z e r o , a time d e l a y a p p r o p r i a t e t o  a o n e - i n c h beam d e f l e c t i o n i s g e n e r a t e d .  A one i n t h e D f i e l d  i n a time d e l a y p e r m i t t i n g a worst case beam d e f l e c t i o n  results  (15 i n c h e s ) .  On e x p i r y o f t h e time d e l a y , t h e beam i s unblanked i f t h e "B"  field  c o n t a i n s one. The d i s p l a y p r o c e s s o r i s p l a c e d i n t h e mode  14, s p e c i f i e d by t h e "NXMD" f i e l d , is  and t h e next  sequential instruction  executed.  3.2.4  Graph-Point I n s t r u c t i o n s Graph-point  i n s t r u c t i o n s p r o v i d e a s i m p l e mechanism f o r  g e n e r a t i n g graphs on t h e d i s p l a y o s c i l l o s c o p e . Execution  of a g r a p h - p o i n t  i n s t r u c t i o n i s almost  to  the execution of a p o i n t i n s t r u c t i o n .  in  t h e "CORD" f i e l d  identical  The a b s o l u t e v a l u e  contained  i s t r a n s f e r r e d to the co-ordinate r e g i s t e r  c a t e d by t h e "AX" f i e l d .  indi-  A t t h e same time, however, t h e o t h e r c o -  o r d i n a t e r e g i s t e r i s incremented by 1,2,4 o r 8, as s p e c i f i e d by t h e c u r r e n t content  of the s c a l e r e g i s t e r .  I n t e r p r e t a t i o n o f a l l other graph-point i s i d e n t i c a l to that of the point 3.2.5  instruction  fields  instruction.  Character I n s t r u c t i o n s Character  i n s t r u c t i o n s a r e used t o d i s p l a y alpha-numeric  t e x t on t h e d i s p l a y o s c i l l o s c o p e .  Each i n s t r u c t i o n p r o v i d e s f o r t h e  g e n e r a t i o n o f up t o two c h a r a c t e r s . S i x t y - f o u r d i s t i n c t c h a r a c t e r s c a n be g e n e r a t e d , t r a t e d i n F i g u r e 3.3. corresponding The  A s p e c i f i c c h a r a c t e r i s i n d i c a t e d by i t s  ASCII code. low-order e i g h t b i t s o f a c h a r a c t e r i n s t r u c t i o n s p e c i f y  the f i r s t c h a r a c t e r to be generated. ASCII code c o n t a i n e d format.  as i l l u s -  i n the C l f i e l d  The s i z e o f t h e d o t - m a t r i x  scale register.  When t h e " E " f i e l d  c i f i e d by t h e h i g h - o r d e r  The c h a r a c t e r i s generated  i n d i c a t e d by t h e  i n a 5 x 7 dot-matrix  i s determined by t h e c o n t e n t  of the  contains a zero, the character  eight b i t s i s generated.  S e q u e n t i a l c h a r a c t e r s a r e generated  from l e f t  t o r i g h t on  spe-  •••  ••••  ••• •••  ••••« ••••• •••  • « ••»• • • • •• • * •«•• • ••••9 •• • *c• •«••• • •*•« •• •••••••• ••••• • ••• *••*••••• • • •••* •  oo met*  ii wtaai  •  •  4  •  u nem  • • • •  •  04 too I M  •  as cot tot  •  •  o; scout  M  MO no •  •  « 9 «  • •• • • • •• • •••••« ••••• • ••••• • • • •••  •  • •  03 toe an  • • • •  11  tt  u  ij  u  u  i*  i;  its oas  iiooot  its f i t  oio oti  oio too  oto lei  OIB no  12 on sto  11 I M tit  J4 on iao  as an ioi  • •  ••••  ioa ait  ion isa  tea ici  iao no  tit III  IB) 100'  101 101  101 110  ii noon  M 110100  KINS ooi n i oatoto mi on OOMOO n •*•• •••• ••••• ••OOMOI•a ••sat tie• •oat t• • • • ••• ••••»• • ••••• • •• •• •• ••• *•••• • •••• » •• a • • • •• •• •• •• • • • ••• • • ••to •it•••«•n• • •••• • • ••• • •• • n M » 2S 77  * «l  • m m  too M I  « iot a n  Ml tSO  'Iflt Ml  10t 110  •• • •••• •••*« • • • • •••*i • •• •41•• «J M  •*• • •* • •••• • ••••• '• • •• •••• • ••••* •••>*• • • • • ••••• • •• •• • • •*• • • ••• •• •••  •a itteoo  • •  ••••• ••••«-< it iioMi  ii ITO no  • *•• ••  ••  • •  • •  •  • m•i n  .mm  •  FIGURE 3.3  no tit  •  •  •  •  •  in i n  • •  ••• •  ts neisi  u no no  in in  m m  •• •  101 lit  ••••• •• • ir ttont  •••• •• • • m m  THF. ASCII CHARACTER SET  N=0  D=6  FIGURE 3.4  N=3 D=l  TYPICAL SHORT VECTORS  16. the d i s p l a y o s c i l l o s c o p e .  The c h a r a c t e r d i s p l a y p r o c e s s  u n t i l a non-zero " E " f i e l d  i s encountered, r e s u l t i n g i n a t r a n s i t i o n  to  continues  c o n t r o l mode.  3.2.6  Short-Vector Vectors  Instructions  limited  i n b o t h s i z e and d i r e c t i o n a r e generated  using short-vector i n s t r u c t i o n s .  Each i n s t r u c t i o n d e f i n e s up t o two  short vectors. A s h o r t v e c t o r i s d e f i n e d by one o f 8 d i r e c t i o n s as s p e c i f i e d i n t h e "D" f i e l d , "N" f i e l d  content.  and i t s l e n g t h ,  (1 t o 8 p o i n t s ) as i n d i c a t e d by t h e  F i g u r e 3.4 i l l u s t r a t e s  some o f t h e p o s s i b l e s h o r t  vectors. The low-order 8 b i t s o f a s h o r t - v e c t o r i n s t r u c t i o n the f i r s t v e c t o r t o be g e n e r a t e d . the o s c i l l o s c o p e beam by e q u a l  specifies  A v e c t o r i s g e n e r a t e d by d e f l e c t i n g  increments i n t h e s p e c i f i e d  direction.  A f t e r each increment, t h e beam i s unblanked i f t h e "B" f i e l d zero.  i s non-  The s i z e o f each increment i s s p e c i f i e d by t h e c o n t e n t  of the  s c a l e r e g i s t e r , and the number o f i n c r e m e n t s as i n d i c a t e d by t h e "N" field  content. Successive half-words are processed  u n t i l a non-zero " E " f i e l d  i n s h o r t - v e c t o r mode  i s encountered, c a u s i n g a d i s p l a y  processor  t r a n s i t i o n t o c o n t r o l mode. 3.2.7  Long-Vector I n s t r u c t i o n s Vectors  less constrained  i n l e n g t h and d i r e c t i o n than s h o r t  v e c t o r s a r e generated u s i n g l o n g - v e c t o r  instructions.  A  long-vector  i n s t r u c t i o n c o n s i s t s o f two 1 6 - b i t words. The DX and Dy f i e l d s s p e c i f y c o r r e s p o n d i n g and  delta-Y co-ordinate values.  signed  delta-X  Each d e l t a c o - o r d i n a t e v a l u e  is in  sign-magnitude format, where a non-zero v a l u e o f "S" i n d i c a t e s a  17,  FIGURE 3.5_ A SAMPLE LONG VECTOR  18. negative  value. Long v e c t o r s a r e generated u s i n g a b i n a r y r a t e m u l t i p l i e r  algorithm.  Implementation o f t h e a l g o r i t h m  ( d e s c r i b e d i n S e c t i o n 3.7.4)  r e s u l t s i n a v e c t o r c o n s i s t i n g of a s e r i e s o f p o i n t s a t equal  intervals.  approximately  S i n c e a d i g i t a l approach r e s t r i c t s p o i n t s t o a g r i d ,  most v e c t o r s a r e o n l y a p p r o x i m a t i o n s t o a s t r a i g h t A sample v e c t o r i s i l l u s t r a t e d  line.  i n F i g u r e 3.5.  DX and DY s p e c i f y t h e number o f p o i n t s i n t h e v e c t o r . spacing  i s determined by t h e content  of the s c a l e r e g i s t e r .  Point  The  o s c i l l o s c o p e beam i s unblanked a t each v e c t o r p o i n t p o s i t i o n i f t h e "B" field  i s non-zero. The  contents  mode f o r e x e c u t i o n 3.3  o f t h e "NXMD" f i e l d  o f the next  s p e c i f y the d i s p l a y  processor  instruction.  Host Computer I n t e r f a c e The  i n t e r f a c e t o t h e host  diagram form i n F i g u r e 3.6, p r o v i d e s processor  and t h e host The  computer, i l l u s t r a t e d  i n block  t h e i n t e r f a c e between t h e d i s p l a y  CPU.  CPU i n t e r f a c e c o n s i s t s o f bus d r i v e r s and r e c e i v e r s , a  buffer register  f o r output  data, a four-channel  i n p u t m u l t i p l e x e r and  an i n t e r f a c e c o n t r o l u n i t . A l l d a t a and c o n t r o l s i g n a l s between t h e h o s t d i s p l a y system a r e p r o v i d e d terminated  by the I/O BUS.  Each I/O BUS l i n e i s  by a s i m p l e r e s i s t i v e network matching t h e c h a r a c t e r i s t i c  impedance o f t h e l i n e .  S i g n a l s from t h e h o s t  l i n e r e c e i v e r s , each a s i m p l e to  CPU and t h e  t h e I/O BUS.  CPU a r e b u f f e r e d by  inverter presenting a s i n g l e u n i t load  S i g n a l s t o the h o s t  BUS v i a o p e n - c o l l e c t o r bus d r i v e r s .  CPU a r e p r e s e n t e d  t o t h e I/O  B i d i r e c t i o n a l I/O BUS d a t a  lines  19.  I/O BUS  BUS DRIVERS/ RCVRS  cc c  V  f t  INPUT MUX IN BUS  CHAN 0  DPC  CHAN 1  X REG.  CHAN 2  Y REG.  CHAN 3  MISC  .CHANNEL SELECT  I/O CONTROL SIGNALS  i  ^  INTERFACE  1  OUTPUT BUFFER REG  UNIT  LOAD BUFFER  V BUFFERED DATA OUT BUS (DAT BUS)  WDRQ  FIGURE-3.6  LDWD  CPU INTERFACE  INIT  INTERRUPT REQUEST LINES  LOAD DPC  20.. are s p l i t  i n t o two u n i d i r e c t i o n a l buses, t h e IN BUS and t h e OUT BUS,  by p a i r s o f bus d r i v e r s and r e c e i v e r s . Data r e c e i v e d from t h e h o s t CPU i s t e m p o r a r i l y s t o r e d i n the output b u f f e r r e g i s t e r .  Outputs from t h e s i x t e e n s i m p l e l a t c h e s  form t h e b u f f e r e d d a t a out bus, DATBUS. The bit  channels  input m u l t i p l e x e r permits  the switching of four 16-  o f d a t a to t h e INBUS.  S u p e r v i s i o n of a l l i n p u t / o u t p u t the i n t e r f a c e c o n t r o l u n i t . major f u n c t i o n s :  t r a n s f e r s i s p r o v i d e d by  The i n t e r f a c e c o n t r o l u n i t performs t h r e e  the decoding  and p r o c e s s i n g o f d i s p l a y system IOT  i n s t r u c t i o n s i s s u e d by t h e h o s t CPU, t h e s u p e r v i s i o n o f d i r e c t memory a c c e s s f e t c h e s from host CPU memory and t h e a s s e r t i o n o f a h o s t CPU interrupt. T a b l e 3.1 p r o v i d e s a summary o f t h e IOT i n s t r u c t i o n s used for  d i s p l a y system o p e r a t i o n .  Two d e v i c e codes w i t h mnemonics DCO  and DC1 a r e used t o s p e c i f y t h e d i s p l a y system. Four d a t a - i n p u t IOT i n s t r u c t i o n s a r e used t o r e a d t h e f o u r input m u l t i p l e x e r channels.  The i n t e r f a c e c o n t r o l u n i t decodes t h e  i n p u t IOT r e q u e s t and s w i t c h e s to  the appropriate m u l t i p l e x e r  channel  t h e INBUS. The  i n t e r f a c e c o n t r o l u n i t p r o v i d e s f o r two modes o f o p e r -  a t i o n during d i s p l a y generation.  The f i r s t mode, DMA e x e c u t i o n mode,  p r o v i d e s f o r d i s p l a y g e n e r a t i o n w i t h m i n i m a l h o s t CPU program c o n t r o l . IOT  i n s t r u c t i o n s a r e used t o i n i t i a t e  t h e d i s p l a y p r o c e s s , and d i s p l a y  i n s t r u c t i o n s a r e f e t c h e d u s i n g t h e d i r e c t memory a c c e s s f a c i l i t y .  A  second mode, IOT e x e c u t i o n mode, p r o v i d e s f o r d i s p l a y g e n e r a t i o n under h o s t CPU c o n t r o l .  That  i s , d i s p l a y i n s t r u c t i o n s a r e presented  to the  21, IOT INSTRUCTION  FUNCTION  DIA  AC,DCO  INPUT CHANNEL -0  DATA  DIB  AC.DCl  INPUT CHANNEL  1  DATA  DIB  AC.DCO  INPUT CHANNEL  2  DATA  DIC  AC.DCO  INPUT CHANNEL  3  DATA  DOA  AC,DCO  LOAD DISPLAY PROGRAM COUNTER  DOB  AC,DCO  OUTPUT DISPLAY DATA,EXECUTE  DOC  AC.DCO  INIT.IOT EXECUTION MODE  IOT INSTRUCTION MODIFIERS  FUNCTION  START (S)  STANDARD MANUF. CONVENTION  CLEAR (C)  STANDARD MANUF. CONVENTION  TABLE 3.1  INPUT--OUTPUT TRANSFER INSTRUCTIONS  22. d i s p l a y system v i a program IOT i n s t r u c t i o n s . P r i o r t o d i s p l a y g e n e r a t i o n i n DMA e x e c u t i o n mode, t h e address  o f t h e d i s p l a y program must be output  t o the d i s p l a y  E x e c u t i o n o f "DOA AC, DCO" by the h o s t CPU r e s u l t s i n . the program address the address  on the I/O BUS.  DPC, t o t h e d i s p l a y  display  The i n t e r f a c e c o n t r o l u n i t  i n t o the output b u f f e r  processor.  strobes  r e g i s t e r and sends a s i g n a l , LOAD  processor.  E x e c u t i o n o f an IOT i n s t r u c t i o n w i t h the START m o d i f i e r enables d i s p l a y system i n t e r r u p t s and d i r e c t memory a c c e s s e s . On decoding  an IOT i n s t r u c t i o n w i t h t h e IOPLS m o d i f i e r ,  the i n t e r f a c e c o n t r o l u n i t a s s e r t s processor  i n c o n t r o l mode.  t h e INIT l i n e , p l a c i n g  the d i s p l a y  The s i g n a l WDRQ, r e q u e s t i n g a d i s p l a y  i n s t r u c t i o n , i s a l s o generated  and i n i t i a t e s  the d i s p l a y  generation  process. The  i n t e r f a c e c o n t r o l u n i t s u p e r v i s e s t h e DMA f e t c h o f a  display instruction.  On r e c e i p t o f t h e s i g n a l WDRQ, a DMA f e t c h i s  performed and t h e r e s u l t i n g d a t a i s s t r o b e d i n t o the output register.  buffer  The s i g n a l LDWD i s sent t o t h e d i s p l a y p r o c e s s o r t o i n d i -  c a t e t h a t a d i s p l a y i n s t r u c t i o n word i s a v a i l a b l e f o r p r o c e s s i n g . F i g u r e 3.7 i l l u s t r a t e s t h e i n t e r a c t i o n between t h e h o s t CPU  and t h e i n t e r f a c e c o n t r o l u n i t d u r i n g d i r e c t memory a c c e s s e s . On r e c e i p t o f t h e f i r s t WDRQ, a DMA r e q u e s t  host CPU.  i s sent t o t h e  When t h e host CPU i s a b l e t o honour t h e DMA r e q u e s t , t h e  s i g n a l ADDRESS IN i s sent t o t h e i n t e r f a c e c o n t r o l u n i t ; t h e c o n t r o l u n i t responds by s w i t c h i n g m u l t i p l e x e r c h a n n e l c o u n t e r , onto t h e I/O BUS. address  and o u t p u t s  0, t h e d i s p l a y program  The h o s t CPU a c c e s s e s  t h e i n d i c a t e d memory  t h e c o n t e n t s on t h e I/O BUS, accompanied by t h e  WDRQ  ADDRESS IN  DATA OUT  ,  FETCH  LDWD  _  .  1st FETCH ;  INSTRUCTION PROCESSING  INSTRUCTION 2nd FETCH PROCESSING  3rd FETCH  INSTRUCTION PROCESSING  FIGURE 3.7, CPU INTERFACE TIMING  to CO \  24. s i g n a l DATA OUT. and  The d a t a i s s t r o b e d i n t o t h e output b u f f e r  register,  the s i g n a l LDWD i s generated, i n d i c a t i n g c o m p l e t i o n o f t h e DMA r e q u e s t . •To minimize  the average  interface control unit LDWD i s g e n e r a t e d .  time between WDRQ and LDWD, t h e  i n i t i a t e s another DMA c y c l e immediately  In cases where d i s p l a y  a l e n g t h y o p e r a t i o n , the next d i s p l a y  instruction processing i s  instruction i s available  WDRQ i s next a s s e r t e d ; hence LDWD i s immediately r e t u r n e d . short d i s p l a y  after  i n s t r u c t i o n e x e c u t i o n time, t h e DMA c y c l e  when  In cases o f  i s i n progress  when WDRQ i s a s s e r t e d , and LDWD i s g e n e r a t e d on c o m p l e t i o n o f t h e cycle. The DMA scheme n e c e s s i t a t e s The d i s p l a y p r o c e s s o r must ensure t h a t i s updated and the output b u f f e r  d o u b l e - b u f f e r i n g o f the data. the d i s p l a y  register  program c o u n t e r  i s f r e e f o r use s h o r t l y  a f t e r LDWD i s g e n e r a t e d . IOT e x e c u t i o n mode i s i n i t i a t e d AC, DCO" i n s t r u c t i o n . i n the a s s e r t i o n mode. I/O  Decoding by t h e i n t e r f a c e  o f INIT, p l a c i n g  the d i s p l a y  control unit  BUS.  The d i s p l a y  i s generated. the d i s p l a y  buffer  a r e e n a b l e d , and t h e s i g n a l LDWD  The d i s p l a y p r o c e s s o r , o n r e c e i p t o f LDWD, p r o c e s s e s  i n s t r u c t i o n and a s s e r t s  o f WDRQ, t h e i n t e r f a c e a w a i t s program  i n s t r u c t i o n on t h e  i n s t r u c t i o n i s strobed i n t o the output  system i n t e r r u p t s  results  processor i n control  E x e c u t i o n o f "DOBS AC, DCO" p l a c e s a d i s p l a y  register, display  3.4  by t h e e x e c u t i o n o f a "DOC  WDRQ on c o m p l e t i o n .  On r e c e i p t  c o n t r o l u n i t r e q u e s t s a h o s t CPU i n t e r r u p t and  intervention.  The D i s p l a y P r o c e s s o r The d i s p l a y  processor, i l l u s t r a t e d  i n b l o c k diagram form i n  F i g u r e 3.8, s u p e r v i s e s the e x e c u t i o n o f a l l d i s p l a y  instructions.  TO  25.  I N P U T M U X  B U S  3  D I S P L A Y P R O G R A M C O U N T E R  ( D P C )  TS:  3  M U X  c  I N C R  ( S R )  D P C  L O A D S R  L O A D  3  S U B R O U T I N E R E G I S T E R  D P C  I N T E R N A L  2 (IR2)  R E G .  y  IR2 B U S S E L E C T C H A N N E L  3 3  I N T E R N A L R E G .  1  (IR1)  L O A D  S  B U S  y  I R I  S  B U S  - \  I R M  M O D E  M O D E R E G I S T E R  CN  PS  3 o  C L E A R  (MR)  M O D E  < o  3  T I M I N G G E N E R A T O R  S T A R T —  F U N C T I O N  F U N C T I O N  C O M P L E T E  WDRQ L D W D I N T E R R U P T L O A D  F I G U R E  3.8  D I S P L A Y  P R O C E S S O R  R E Q U E S T  R E G I S T E R S  26,.  Fundamental components o f t h e d i s p l a y p r o c e s s o r program counter  include:  the d i s p l a y  and m u l t i p l e x e r , t h e s u b r o u t i n e r e g i s t e r ,  r e g i s t e r and t h e t i m i n g g e n e r a t o r .  Two o f t h e i n t e r n a l  t h e mode  storage  r e g i s t e r s , IR1 and IR2, a r e a l s o shown i n F i g u r e 3.8. The  d i s p l a y program c o u n t e r ,  1 2 - b i t up-counter.  DPC, i s a p a r a l l e l  The a s s o c i a t e d DPC m u l t i p l e x e r p e r m i t s  l o a d i n g o f t h e DPC from e i t h e r t h e output DAT BUS),  or the subroutine r e g i s t e r .  d i s p l a y program address The  buffer register  loading, parallel (via the  The DPC c o n t a i n s t h e c u r r e n t  d u r i n g DMA e x e c u t i o n mode.  subroutine r e g i s t e r  c o n s i s t i n g of 12 RS f l i p - f l o p s . a d i s p l a y program address  i s a p a r a l l e l loading  The s u b r o u t i n e r e g i s t e r can r e t a i n  during i n s t r u c t i o n  Internal register  register  execution.  2, IR2, i s a 1 6 - b i t , p a r a l l e l  r e g i s t e r c o n s t r u c t e d o f RS f l i p - f l o p s .  IR2 i s p r o v i d e d  s t o r a g e o f d a t a used i n d i s p l a y - e l e m e n t  generation.  loading  f o r the  Another i n t e r n a l r e g i s t e r , IR1, i s i d e n t i c a l t o IR2. A multiplexer associated with low-order or h i g h - o r d e r  IR1 a l l o w s t h e s w i t c h i n g o f e i t h e r t h e  8 b i t s o f IR1 t o t h e IRM BUS.  used f o r s t o r a g e o f t h e d i s p l a y i n s t r u c t i o n d u r i n g  IR1 i s n o r m a l l y  display-element  generation. The mode r e g i s t e r i s a 3 - b i t f l i p - f l o p r e g i s t e r used t o s t o r e t h e c u r r e n t mode code d u r i n g i n s t r u c t i o n The  timing generator  execution.  c o n s i s t s o f mode decode  circuitry,  monostable m u l t i v i b r a t o r s , and a s s o c i a t e d l o g i c used t o g e n e r a t e t h e fundamental system t i m i n g Four d i s t i n c t  signals.  t i m i n g sequences a r e generated  play i n s t r u c t i o n execution.  during  dis-  An "immediate" sequence a p p l i e s d u r i n g  27,  WDRQ  LDWD  TP1  TP2 FIGURE 3.9 THE IMMEDIATE SEQUENCE  WDRQ  LDWD  TP1  TP2 START FUNCTION FUNCTION COMPLEXE  FIGURE 3.10 THE SINGLE-WORD SEQUENCE  28. the e x e c u t i o n o f c o n t r o l and t r a n s f e r word" sequence i s u t i l i z e d point  instructions.  instructions.  The " s i n g l e -  during the execution of point  A t h i r d sequence, t h e " h a l f - w o r d " sequence, i s  used d u r i n g t h e e x e c u t i o n o f c h a r a c t e r and s h o r t - v e c t o r The  and g r a p h -  instructions.  f i n a l sequence, t h e "double-word" sequence, i s a p p l i c a b l e  during  long-vector i n s t r u c t i o n execution. 3.4.1  The Immediate I n s t r u c t i o n The  3.9,  immediate i n s t r u c t i o n sequence, i l l u s t r a t e d  i s initiated  instruction. leading  Sequence  on a s s e r t i o n  o f WDRQ, a r e q u e s t f o r t h e next  edge o f LDWD i s used t o increment t h e DPC, and t h e t r a i l i n g  i s used t o t r a n s f e r  register  the d i s p l a y  (DAT BUS) t o IR1.  t h e next t i m i n g  sequence.  u s e r r e g i s t e r s a r e loaded from t h e DAT BUS u s i n g TP1. i s also  buffer  p u l s e 2, TP2. TP2  execution of a control i n s t r u c t i o n , the scale,  a program i n t e r r u p t  p u l s e 1, TP1  edge o f TP1 t r i g g e r s a  producing timing  i s used t o g e n e r a t e WDRQ, i n i t i a t i n g On  t o produce t i m i n g  i n s t r u c t i o n from t h e output  The t r a i l i n g  second monostable m u l t i v i b r a t o r ,  and  display  Completion o f t h e memory a c c e s s i s denoted by LDWD. The  edge t r i g g e r s a monostable m u l t i v i b r a t o r TP1  i n Figure  i n i t i a t e d by TP1.  intensity I f specified  TP2 i s used t o t r a n s f e r  the mode ( f o r e x e c u t i o n o f t h e next i n s t r u c t i o n )  from IR1 t o t h e mode  register. LDWD i s used t o t r a n s f e r d u r i n g e x e c u t i o n o f a JSR t r a n s f e r  t h e DPC t o t h e s u b r o u t i n e r e g i s t e r instruction.  the DPC w i t h t h e new program address b o t h a JSR and a JMP t r a n s f e r transfer register.  ( v i a t h e DAT BUS) on e x e c u t i o n o f  instruction.  i n s t r u c t i o n , TP1 i s used t o l o a d I f the "E" f i e l d  TP1 i s used t o l o a d  On e x e c u t i o n o f an RSR t h e DPC from t h e s u b r o u t i n e  of the transfer  i n s t r u c t i o n s i s non-zero,  29. TP2 to  i s used t o c l e a r the mode r e g i s t e r , r e s t o r i n g the d i s p l a y p r o c e s s o r c o n t r o l mode.  3.4.2  The Single-Word I n s t r u c t i o n Sequence A single-word  During  a single-word  sequence i s i l l u s t r a t e d  The  and  d i s p l a y processor  LDWD i s used t o increment  i s a s s e r t e d by TP2,  and t h e  performs i t s f u n c t i o n . o f t h e a p p r o p r i a t e f u n c t i o n , the d i s p l a y  element-generator a s s e r t s " f u n c t i o n complete",and WDRQ i s The mode r e g i s t e r i s m o d i f i e d ,  3.4.3  i f r e q u i r e d , on the l e a d i n g edge o f  The Half-Word I n s t r u c t i o n Sequence sequence, used f o r the g e n e r a t i o n o f c h a r a c t e r s  short v e c t o r s , i s s i m i l a r to a single-word  sequence.  f u n c t i o n " , r e s u l t i n g from the i n i t i a l WDRQ, i n i t i a t e s t h e of  generated.  complete".  A half-word and  IR1.  e n t e r s an i d l e s t a t e w h i l e a d i s p l a y - e l e m e n t  On c o m p l e t i o n  "function  i n the  TP1 i s used t o s t r o b e the d i s p l a y i n s t r u c t i o n i n t o  appropriate "start function" l i n e  generator  3.10.  sequence, LDWD, TP1 and TP2 a r e generated  same manner a s i n an immediate sequence. the DPC,  i n Figure  "Start generation  the element d e f i n e d by t h e low-order 8 b i t s o f the d i s p l a y i n s t r u c -  tion.  Subsequent t i m i n g i s dependent upon the c o n t e n t  i n s t r u c t i o n "E" On  o f the d i s p l a y  field.  completion  of the f u n c t i o n a s s o c i a t e d w i t h t h e  low-rorder  8 b i t s o f the d i s p l a y i n s t r u c t i o n , " f u n c t i o n complete" i s a s s e r t e d . If  the "E" f i e l d  of  another  (of the low-border h a l f - w o r d ) c o n t a i n s z e r o ,  generation  c h a r a c t e r o r s h o r t v e c t o r i s i n d i c a t e d , and " s t a r t f u n c t i o n "  i s immediately  r e a s s e r t e d , as i l l u s t r a t e d  i n F i g u r e 3.11a.  element g e n e r a t i o n a s s o c i a t e d w i t h the h i g h - o r d e r  Following  8 b i t s o f the d i s p l a y  30,  a)  CASE I - PROCESSING 2 CONSECUTIVE HALF WORDS  b)  CASE I I - PROCESSING LOW ORDER HALF WORD ONLY  FIGURE 3.11  THE HALF WORD-SEQUENCE  31  r  32, i n s t r u c t i o n , " f u n c t i o n complete" i s a g a i n WDRQ, a request If  generated, r e s u l t i n g i n  f o r a new d i s p l a y i n s t r u c t i o n .  the "E" f i e l d  (associated with e i t h e r half-word) i s  non-zero, t h e mode r e g i s t e r i s c l e a r e d i n s t r u c t i o n , and WDRQ i s a s s e r t e d .  i n preparation  Figure  for a control  3.11b i l l u s t r a t e s  the c a s e  where the " E " b i t o f t h e low-order h a l f - w o r d o f t h e d i s p l a y i n s t r u c t i o n is  non-zero. D u r i n g a h a l f - w o r d sequence, t h e a p p r o p r i a t e  8 b i t s of the  d i s p l a y i n s t r u c t i o n a r e switched onto t h e IRM bus f o r u s e by the display 3.4.4  generator. The Double-Word I n s t r u c t i o n Sequence The  f i r s t h a l f o f a double-word sequence ( F i g u r e 3.12) i s  i d e n t i c a l t o an immediate sequence except t h a t TP1 i s used t o l o a d the f i r s t word o f a l o n e - v e c t o r  i n s t r u c t i o n into-IR2.  The second  h a l f o f a double-word sequence i s i d e n t i c a l t o a singler-word 3.5  The D i s p l a y O s c i l l o s c o p e The  sequence.  Interface  i n t e r f a c e t o the d i s p l a y o s c i l l o s c o p e i s i l l u s t r a t e d  i n b l o c k diagram form i n F i g u r e 3.13. X and Y up/down c o u n t e r s ,  Major a x i s components i n c l u d e :  and D/A c o n v e r t e r s .  i n t e n s i t y r e g i s t e r and D/A c o n v e r t e r ,  A s c a l e r e g i s t e r , an  and beam u n b l a n k i n g  circuitry  complete t h e i n t e r f a c e . The constructed  X up/down c o u n t e r i s a 1 0 ~ b i t , synchronous c o u n t e r  from J-K f l i p - f l o p s . The c o u n t e r can b e p a r a l l e l  from t h e DAT BUS.  A count d i r e c t i o n i n p u t  loaded  i n d i c a t e s count up o r count  down, and a t o g g l e l i n e i n i t i a t e s t h e c o u n t e r s t a t e change. The c o u n t e r can be incremented o r decremented b y 1,2,4 o r 8 u n i t s f o r each toggle pulse, as s p e c i f i e d by the s c a l e r e g i s t e r content.  33, DAT BUS  i LOAD SCALE AND INTENSITY  SLAz  X UP/DOWN COUNTER LOAD X  INTENSITY  SCALE REGISTER  V  REGISTER  LOAD Y  -ts*  TOGGLE X  TOGGLE Y  X COUNT DIRECTION-EH  Y COUNT DIRECTION  LOAD X D  Y UP/DOWN COUNTER  BUFFERED X D/A  X-AXIS  LOAD Y D/A^  AMPLIFIER  BUFFERED Y D/A  z D/A  Y-AXIS  Z-AXIS  TO DISPLAY OSCILLOSCOPE  FIGURE 3.13 THE DISPLAY OSCILLOSCOPE INTERFACE  UNBLANK  34, The  content o f t h e X up/down c o u n t e r i s t r a n s f e r r e d t o t h e  10-bit, buffered,  X D/A c o n v e r t e r  which d i r e c t l y d r i v e s  the X - a x i s o f  the d i s p l a y o s c i l l o s c o p e . The are  Y - a x i s up/down c o u n t e r and a s s o c i a t e d  i d e n t i c a l to the X-axis The  D/A  converter  circuitry.  i n t e n s i t y r e g i s t e r i s a 3-bit r e g i s t e r consisting of  simple l a t c h e s .  S i g n a l s from t h e i n t e n s i t y r e g i s t e r a r e i n p u t t o  a 3 - b i t D/A c o n v e r t e r  which d i r e c t l y d r i v e s  the Z-axis of the d i s p l a y  oscilloscope. A s i m p l e two-r-stage t r a n s i s t o r a m p l i f i e r i s used t o d r i v e the  low impedance, beam u n b l a n k i n g i n p u t When "UNBLANK" i s a s s e r t e d ,  of the d i s p l a y o s c i l l o s c o p e .  a point with  co-ordinates  s p e c i f i e d by t h e X and Y a x i s D/A b u f f e r s and i n t e n s i t y s p e c i f i e d by the 3.6  intensity register i s displayed. The System C l o c k Fundamental t i m i n g  d i s p l a y elements a r e d e r i v e d i s programmable, p e r m i t t i n g generation  s i g n a l s used i n t h e g e n e r a t i o n from t h e system c l o c k . the o p t i m i z a t i o n  of a l l  The c l o c k  of display  frequency  element  times. Figure  3.14 i s a s i m p l e b l o c k diagram o f t h e system  clock,  which c o n s i s t s o f two monostable m u l t i v i b r a t o r s , M l and M2, and a r e s i s t o r switching rising  network.  The monostable m u l t i v i b r a t o r s a r e t r i g g e r e d by a  edge a p p l i e d  near 100 p e r c e n t . an RC network.  t o t h e "T" t e r m i n a l ,  The r e s i s t o r s w i t c h i n g  inputs.  cycle  D u r a t i o n o f t h e monostable o u t p u t i s determined by  o f 16 d i s t i n c t p u l s e SELECTION  and can s u s t a i n a d u t y  durations  network p e r m i t s t h e s e l e c t i o n  from M l , as s p e c i f i e d by t h e TIMING  r  RESISTOR SWITCHING NETWORK  TIMING 1SELECTION •  FIGURE 3.14  THE SYSTEM CLOCK  ENABLE CLOCK  Cl  C2 (a) - SINGLE CLOCK CYCLE  ENABLE CLOCK  ci C2  : %  1  _ J  U  U  I1  1 |  I [  (b) - MULTIPLE CLOCK CYCLES  FIGURE 3 .15  CLOCK TIMING  36. F i g u r e 3.15 system c l o c k .  i l l u s t r a t e s t y p i c a l waveforms o b t a i n e d  from  A s i n g l e c l o c k c y c l e w i l l r e s u l t from a b r i e f  of "ENABLE CLOCK", as i l l u s t r a t e d  i n F i g u r e 3.15a.  "ENABLE CLOCK" t r i g g e r s Ml,  p r o d u c i n g the f i r s t  is  edge of C l , g e n e r a t i n g  t r i g g e r e d on the f a l l i n g  The  assertion  r i s i n g edge of  c l o c k phase, C l . C2,  the  M2  the second  clock  phase. If  "ENABLE CLOCK" remains a s s e r t e d , m u l t i p l e c l o c k  a r e g e n e r a t e d , as shown i n F i g u r e 3.15b. Ml,  providing a free-running  C2  cycles  i s f e d back to r e - t r i g g e r  c l o c k as l o n g as "ENABLE CLOCK" i s  asserted. The sistor  r e s i s t o r switching  network c o n s i s t s of 4 s i m p l e  s w i t c h e s p r o v i d i n g 16 d i f f e r e n t RC  time c o n s t a n t s  f o r Ml.  duration  of C l ranges from 400  nanoseconds to 10 m i c r o s e c o n d s .  duration  of C2  nanoseconds.  The  i s f i x e d a t 400 two  phases of the system c l o c k a r e used i n a  f a s h i o n by most d i s p l a y - e l e m e n t  generators.  w i t h i n a d i s p l a y element i s generated d u r i n g D u r i n g the f i r s t the X and point.  The  optimum time d u r a t i o n  element g e n e r a t o r t o p r o v i d e settling  time.  C2  as r e q u i r e d  one  The  standard  complete c l o c k c y c l e . generator  modifies  for a specific  f o r C l can be  the a p p r o p r i a t e  The  Normally, a s i n g l e p o i n t  c l o c k phase, a d i s p l a y - e l e m e n t  Y d i s p l a y co-ordinates  tran-  s e l e c t e d by  beam e x c u r s i o n  i s n o r m a l l y used to unblank the CRT  display each and  beam, d i s p l a y i n g  the s i n g l e p o i n t . 3.7 3.7.1  Display-Element Generators The  P o i n t and P o i n t s and  display-element  Graph-Point Generator g r a p h - p o i n t f u n c t i o n s a r e performed by a s i n g l e  g e n e r a t o r s i n c e most o f the p r o c e s s i n g  requirements  37,. a r e common t o both.  In each case, one d i s p l a y a x i s i s s e t t o an  a b s o l u t e v a l u e , and i n t h e case o f g r a p h - p o i n t  i n s t r u c t i o n s , the other  d i s p l a y a x i s i s incremented. F i g u r e 3.16 p r o v i d e s a s i m p l e b l o c k diagram o f t h e p o i n t and graph-point process.  g e n e r a t o r , i n d i c a t i n g t h e s i g n a l s used  i n the generation  F i g u r e 3.17 i l l u s t r a t e s t h e fundamental t i m i n g waveforms  d u r i n g element g e n e r a t i o n . Element g e n e r a t i o n i s i n i t i a t e d when t h e d i s p l a y a s s e r t s e i t h e r "START POINT" or "START GRAPH-POINT". i s used  to generate  processor  The s t a r t  signal  e i t h e r "LOAD X" o r "LOAD Y" ( a c c o r d i n g t o t h e  content o f t h e "AX" i n s t r u c t i o n f i e l d ) ,  t r a n s f e r r i n g the absolute co-  o r d i n a t e t o t h e X o r Y up/down counter v i a t h e DAT BUS.  I n the case  of t h e g r a p h - p o i n t  to generate  a toggle signal,  i n s t r u c t i o n , the s t a r t  (TOGGLE Y o r TOGGLE X) i n c r e m e n t i n g t h e a p p r o p r i a t e  co-ordinate a x i s counter. one  full  s i g n a l i s used  The s t a r t  s i g n a l i s a l s o used  to i n i t i a t e  c y c l e o f the two-phase c l o c k by a s s e r t i n g "ENABLE CLOCK". Phase 1 o f the two-phase c l o c k , C l , i s used  to t r a n s f e r the  c o n t e n t s o f t h e X and Y up/down c o u n t e r s t o t h e i r a s s o c i a t e d D/A buffer registers.  The d u r a t i o n o f C l i s determined  by t h e c o n t e n t  of t h e "D" i n s t r u c t i o n f i e l d , p r o v i d i n g f o r e i t h e r a t y p i c a l ( 1 - i n c h ) , or worst  case  (15-inch) beam d e f l e c t i o n .  When C l e x p i r e s , t h e second C2 i s o p t i o n a l l y used  c l o c k phase, C2, i s g e n e r a t e d .  to unblank t h e d i s p l a y o s c i l l o s c o p e beam,  a c c o r d i n g t o the content o f t h e "B" i n s t r u c t i o n f i e l d .  C2 i s used  t o a s s e r t "FUNCTION COMPLETE", t e r m i n a t i n g t h e element g e n e r a t i o n process.  38,  START POINT  COUNT DIRECTION  START. GRAPH-POINT ENABLE^LOCK  - H POINT & GRAPHPOINT GENERATOR  ci C2  -©•Y COUNT DIRECTION -©.TOGGLE X .^TOGGLE Y _^LOAD X jte.LOAD Y  «asg  •  •— 1  -^UNBLANK  FUNCTION COMPLETE  f)  IR 1 BUS FIGURE 3.16  THE POINT AND GRAPH-POINT GENERATOR  START  ENABLE CLOCK Cl  C2  |  FIGURE 3.17  POINT AND GRAPH-POINT TIMING  39, 3.7.2  The  Character  Generator  Alphanumeric c h a r a c t e r s a r e c o n s t r u c t e d format by the c h a r a c t e r Characters D/A  converters.  F i g u r e 3.18  and  incrementing  the X - a x i s  character generator.  f o r the next  counter  The  character. the  diagram i l l u s t r a t e s the p r i m a r y components these  i n c l u d e the h o r i z o n t a l and  vertical  the c h a r a c t e r read-only-memory (ROM), Y-minor a x i s  c o n v e r t e r , a s h i f t r e g i s t e r and The h o r i z o n t a l counter sequence through the 5 v e r t i c a l 3 - b i t , modulo-7 counter  Corporation  the c o n t r o l u n i t . i s a 3 - b i t , modulo-5 c o u n t e r segments.  The  vertical  used  counter  3072-bit  ROM  used to c o n v e r t  c h a r a c t e r code t o the r e q u i r e d d o t - m a t r i x  is a  pattern.  Semiconductor  a 6 - b i t ASCII The  result  of  a c c e s s d e t e r m i n e s which of the seven beam p o s i t i o n s a r e  be unblanked d u r i n g the g e n e r a t i o n of a v e r t i c a l o r d e r b i t s o f t h e ROM the h i g h - o r d e r  to  segment.  c h a r a c t e r read-only-memory i s a N a t i o n a l  s t a t i c MOS  D/A  which i s incremented through a l l s t a t e s d u r i n g  the g e n e r a t i o n o f each v e r t i c a l The  When  increment  p r o v i d e s a s i m p l i f i e d b l o c k diagram of  of the c h a r a c t e r g e n e r a t o r ;  each ROM  times.  segment.  segments a r e complete, an a d d i t i o n a l X - a x i s  p o s i t i o n s the beam i n r e a d i n e s s  segments,  the Y-minor a x i s 6  incremented to p o s i t i o n the beam f o r the next v e r t i c a l  counters,  Y-minor a x i s  A character i s generated i n 5 v e r t i c a l  Y-minor a x i s c o - o r d i n a t e , i s t h e n c l e a r e d and  F i g u r e 3.19  dot-matrix  i l l u s t r a t e s the beam p o s i t i o n i n g d u r i n g  w i t h each segment produced by  the 5 v e r t i c a l  7  generator.  a r e generated u s i n g the X - a x i s  character generation.  The  i n a 5 by  segment.  The  to  low-  address a r e t h e 6 ^ b i t ASCII c h a r a c t e r code,  b i t s a r e the v e r t i c a l  segment number, d e f i n e d by  and  the  40,  FIGURE 3,18  BEAM POSITIONING DURING CHARACTER GENERATION  41, TOGGLE X B»  START CHARACTER ENABLE CLOCK «ss§—  LOAD X D/A  Cl  CHARACTER GENERATOR CONTROL UNIT  C2 CHARACTER COMPLETE  UNBLANK  CLEAR  LOAD D/A  TOGGLE  i  Y MINOR REGISTER  VERTICAL COUNTER  ,>  Y MINOR D/A  TOGGLE  HORIZONTAL COUNTER  SHIFT REGISTER  7v  ROM ADDRESS  7\ IRM BUS  FIGURE 3.19  THE CHARACTER GENERATOR  CHARACTER ROM  Y MINOR -®»AXIS  START CHARACTER  -hi-  ENABLE CLOCK  Cl  C2 LOAD SHIFT REG. SERIAL DATA _  UNBLANK  TOGGLE X VERTICAL COUNTER STATE  0  0  Y MINOR REGISTER STATE  6  0  CHARACTER COMPLETE—  FIGURE 3.20  CHilRACTER TIMING  I  6  1_  43, horizontal  counter. A shift  r e g i s t e r i s used  t o h o l d ROM d a t a d u r i n g v e r t i c a l  segment g e n e r a t i o n . Y-minor a x i s components i n c l u d e a 3 - b i t Y-minor r e g i s t e r and the a s s o c i a t e d Y-minor D/A c o n v e r t e r . The c h a r a c t e r g e n e r a t o r c o n t r o l u n i t p r o v i d e s t h e c o n t r o l signals required f o r character generation.  F i g u r e 3.20 i l l u s t r a t e s a  p o r t i o n o f t h e t i m i n g waveforms d u r i n g t h e g e n e r a t i o n o f a s i n g l e character. "START CHAR" i s a s s e r t e d by t h e d i s p l a y p r o c e s s o r t o i n i t i a t e character generation.  The low-order  8 b i t s o f IR1 a r e s w i t c h e d  onto  the IRM BUS; t h e h o r i z o n t a l and v e r t i c a l c o u n t e r s a r e c l e a r e d ; and the two-phase c l o c k i s e n a b l e d .  The 7 - b i t ROM word s p e c i f i e d by t h e  h o r i z o n t a l c o u n t e r and t h e ASCII code i s p a r a l l e l - l o a d e d r e g i s t e r by t h e f i r s t  c l o c k phase, C l . C l i s a l s o used  into the s h i f t to strobe the  v e r t i c a l counter i n t o t h e Y-minor a x i s b u f f e r r e g i s t e r and t h e X - a x i s up/down counter t o t h e X - a x i s b u f f e r r e g i s t e r . i s used t o increment beam i s unblanked  The r i s i n g edge o f C2  t h e v e r t i c a l c o u n t e r , and t h e d i s p l a y  d u r i n g t h e second  c l o c k phase.  oscilloscope  Shift register  data  i s s h i f t e d on t h e f a l l i n g edge o f C2. The r e m a i n i n g generated tical  6 p o i n t s i n t h e f i r s t v e r t i c a l segment a r e  i n a similar fashion.  F o l l o w i n g the seventh p o i n t , the v e r -  counter o v e r f l o w s , r e s e t t i n g i t t o z e r o and i n c r e m e n t i n g t h e  h o r i z o n t a l counter.  A new ROM word i s t r a n s f e r r e d t o t h e s h i f t  r e g i s t e r , t h e X - a x i s up/down counter i s incremented,  and t h e gener-  a t i o n o f the next v e r t i c a l segment i s i n i t i a t e d . The p r o c e s s i s r e p e a t e d u n t i l 5 v e r t i c a l segments have been generated, completing the c h a r a c t e r .  An e x t r a c l o c k c y c l e i s a l l o w e d ,  44, d u r i n g which a n register 3.7.3  a d d i t i o n a l X-axis  i s c l e a r e d and "CHARACTER  The S h o r t - V e c t o r  increment i s g e n e r a t e d , t h e Y-minor COMPLETE" i s a s s e r t e d .  Generator  Short v e c t o r s , as d e s c r i b e d the s h o r t - v e c t o r g e n e r a t o r . X and Y major a x i s D/A  i n 3.2.6, a r e c o n s t r u c t e d by  Short v e c t o r s a r e g e n e r a t e d u s i n g t h e  converters.  F i g u r e 3.21 p r o v i d e s short-vector generator.  a simplified  b l o c k diagram o f t h e  Major components i n c l u d e : t h e l e n g t h  counter,  the v e c t o r - d i r e c t i o n decoder, and t h e c o n t r o l u n i t . The  l e n g t h counter  i s a 3 - b i t modulo-7 counter  used t o  determine the l e n g t h o f a s h o r t v e c t o r . Vector  d i r e c t i o n i s e s t a b l i s h e d by d e c o d i n g t h e "D" f i e l d o f  the s h o r t - v e c t o r i n s t r u c t i o n . the "D" f i e l d  The v e c t o r - d i r e c t i o n decoder t r a n s l a t e s  i n t o the r e q u i r e d X and Y - a x i s up/down counter  s i g n a l s , and r o u t e s  the master t o g g l e s i g n a l (generated  u n i t ) to the appropriate  direction  by t h e c o n t r o l  axis-counter.  C o n t r o l s i g n a l s used d u r i n g s h o r t - v e c t o r g e n e r a t i o n a r e d e r i v e d from t h e c o n t r o l u n i t .  F i g u r e 3.22 i l l u s t r a t e s t h e fundamental  waveforms a s s o c i a t e d w i t h t h e g e n e r a t i o n Short-vector  generation  first  vector.  i s i n i t i a t e d when t h e d i s p l a y p r o -  c e s s o r a s s e r t s "START SHORT VECTOR". switched  of a s i n g l e short  The low-order 8 b i t s o f IR1 a r e  onto the IRM BUS, and t h e two-phase c l o c k i s e n a b l e d .  occurrence  o f C l i s used t o l o a d t h e l e n g t h c o u n t e r  The  from t h e IRM  BUS. The  r i s i n g edge o f C2 i s used t o t o g g l e t h e a p p r o p r i a t e X and  Y - a x i s up/down c o u n t e r s . rising  The l e n g t h counter  i s incremented by t h e  edge o f C l , and t h e a x i s up/down c o u n t e r s  are t r a n s f e r r e d to the  45,  START V E C T O R  E N A B L E  C L O C K U N B L A N K  S H O R T - V E C T O R C O N T R O L  Cl  -H  U N I T  C2  S H O R T _ V E C T O R  COMPCSTE M A S T E R T O G G L E  L O A D  T O G G L E  OVERF L O W  L E N G T H C O U N T E R  TV-  X  C O U N T  D I R E C T I O N V E C T O R  ^ T O G G L E  X  D I R E C T I O N D E C O D E R  I R M  Y  B U S  C O U N T  D I R E C T I O N T O G G L E  F I G U R E  3 . 2 1  T H E  S H O R T - V E C T O R  G E N E R A T O R  Y  START SHORT VECT ENABLE CLOCK_  Cl  C2 TOGGLE U/D CNTRS LOAD D/A BUFFERS  UNBLANK  COMPLETE LENGTH COUNTER STATE  -  .1.4.1  •5  • |  FIGURE 3.22  I 6  |  7  I |  .0  SHORT-VECTOR TIMING  47, a p p r o p r i a t e D/A b u f f e r r e g i s t e r s .  I f t h e "B" b i t o f t h e s h o r t - v e c t o r  i n s t r u c t i o n i s s e t , t h e d i s p l a y o s c i l l o s c o p e beam i s unblanked  during  the second o c c u r r e n c e  o f C2, d i s p l a y i n g t h e f i r s t  The  o f C2 i s a l s o used t o t o g g l e t h e a x i s up/down  second o c c u r r e n c e  counters,  initiating  the generation  p o i n t i n the v e c t o r .  o f the second v e c t o r  point.  A d d i t i o n a l s h o r t - v e c t o r p o i n t s a r e generated i n t h i s fashion u n t i l The  the l e n g t h counter  i s incremented t o t h e z e r o s t a t e .  l a s t v e c t o r p o i n t i s d i s p l a y e d , completing  a s i n g l e short vector.  A s s e r t i o n o f "SHORT VECTOR COMPLETE" then r e s t o r e s c o n t r o l t o the d i s p l a y 3.7.4  processor.  The Long-Vector Generator Long v e c t o r s , c a p a b l e  o f spanning t h e e n t i r e d i s p l a y  o s c i l l o s c o p e screen, are constructed Vector and  delta-Y  generator  generator.  l e n g t h and d i r e c t i o n a r e s p e c i f i e d by d e l t a - X  (DY) v a l u e s  provides  points a t roughly  by t h e l o n g - v e c t o r  i n sign-magnitude form.  (DX)  The l o n g - v e c t o r  an a p p r o x i m a t i o n t o t h e v e c t o r by d i s p l a y i n g equal  i n t e r v a l s along  t h e path o f t h e t r u e v e c t o r .  Complete d e t a i l s o f t h e v e c t o r g e n e r a t i o n  a l g o r i t h m a r e p r o v i d e d as  Appendix 1. F i g u r e 3.23 p r o v i d e s an o v e r v i e w o f t h e l o n g - v e c t o r ator.  The l o n g - v e c t o r  generator  gener-  c o n s i s t s o f t h e v e c t o r c o u n t e r , an  X and Y change d e t e c t o r and t h e c o n t r o l u n i t . The  v e c t o r counter  i s a 10-bit special-purpose  used t o e s t a b l i s h the l e n g t h o f a l o n g v e c t o r . the v e c t o r g e n e r a t i o n a l g o r i t h m ,  In order  up-counter to s a t i s f y  the s i z e o f the v e c t o r counter  need  N o n l y be N b i t s , where DX and DY a r e each l e s s t h a n 2 . the time r e q u i r e d t o produce a s p e c i f i c v e c t o r , some  To m i n i m i z e  vector-counter  48.  S T A R T  LONG-  V E C T O R  ENABLE  C L O C K  Cl  L O N G - V E C T O R C O N T R O L  U N I T  C2  L O N G  M A S T E R  T O G G L E  .VECTOR  C O M P L E T E "  IR1  V C  V C  T O G G L E  O V F L O  12  ©—EH  3  X  C O U N T  D I R E C T I O N X  C H A N G E  D E T E C T O R  T O G G L E  X  T O G G L E  Y  ( X C D ) V E C T O R C O U N T E R ( V C )  3  Y  C H A N G E  D E T E C T O R ( Y C D )  IR2  F I G U R E  3 . 2 3  T H E  L O N G - V E C T O R  G E N E R A T O R  Y  C O U N T  " D I P S C T I O N  4  bits  9  «  a r e a u t o m a t i c a l l y d i s a b l e d ( a c c o r d i n g t o t h e h i g h e s t power o f 2  contained  i n t h e l a r g e r o f DX or DY). The X and Y change d e t e c t o r s compare the v e c t o r - c o u n t e r  content  t o t h e v a l u e s o f DX and DY, r e s p e c t i v e l y , and modify t h e major  a x i s up/down c o u n t e r s  as r e q u i r e d t o produce t h e d e s i r e d v e c t o r . .  Control signals required f o r vector generation by t h e c o n t r o l u n i t . in  F i g u r e 3.24 i l l u s t r a t e s  the g e n e r a t i o n o f a s p e c i f i c  vector.  are provided  t h e t i m i n g s i g n a l s used  In t h i s  case,  the v e c t o r  corresponds to DX=7 and DY=4, as shown i n F i g u r e 3.5. Vector  generation  i s initiated  by t h e s i g n a l "START LONG-  VECTOR", which r e s u l t s i n t h e e n a b l i n g o f t h e two-phase c l o c k . rising  edge o f C l t o g g l e s the v e c t o r c o u n t e r ,  The  i n prepartion for display  of the f i r s t v e c t o r p o i n t . C2 i s used t o modify t h e X and Y - a x i s up/down through t h e s i g n a l s TOGGLE X and TOGGLE Y (C2 i s b l o c k e d  counters by t h e X and  Y change d e t e c t o r s when an a x i s m o d i f i c a t i o n i s n o t r e q u i r e d ) . contents  o f the X and Y - a x i s up/down c o u n t e r s  corresponding  D/A c o n v e r t e r s  are t r a n s f e r r e d to the  on t h e next o c c u r r e n c e  of C l .  o s c i l l o s c o p e beam i s unblanked d u r i n g t h e second o c c u r r e n c e and  completes t h e d i s p l a y o f t h e f i r s t v e c t o r The  remaining  overflows  The d i s p l a y o f C2  point.  v e c t o r p o i n t s a r e generated i n an  f a s h i o n u n t i l t h e v e c t o r counter  The  to zero.  identical  On c o m p l e t i o n o f  the l a s t v e c t o r p o i n t , "LONG VECTOR COMPLETE" i s a s s e r t e d , r e s t o r i n g c o n t r o l t o the d i s p l a y p r o c e s s o r .  50.  START | LONG VECTOR ENABLE CLOCK!  £2  .  I  I I  £2 TOGGLE VC  1  VC STATE. 0 |  I I  I I  I I  I I  I I  I  I I __l I  1I  1 1  1I  I l_  I  I  I  I  I  I  I  1  I  |  TOGGLE X  j  TOGGLE Y  I. .1  1  |  2  I  |  |  I  3  I  |  I  j  4  I  |  I  I  II  LOAD D/A'S  |_J  UNBLANK  |  I  » 1  5  J  |  I  I  6  I  |  I  I  II  |  |  \  |  I  |  |  |  I  I 1  1  VC OVFLO  VECTOR COMPLETE  FIGURE 3.24  7  LONG-VECTOR TIMING  1  t  I  0  51, 4.  4.1  IMPLEMENTATION OF THE GRAPHICS DISPLAY SYSTEM  A Modular Approach The graphics display system was implemented i n a highly  modular form for the following reasons: a)  to simplify trouble-shooting (modularity permits the removal of some c i r c u i t boards without a f f e c t i n g the operation of others, providing a means f o r quickly i s o l a t i n g many f a u l t s )  b)  to permit the addition of special-purpose d i s p l a y element generators.  C i r c u i t r y associated with each display-element generator i s independent from a l l others, so addition of a new element generator i s r e l a t i v e l y simple.  The main r e s t r i c t i o n i s that any display-element  generator must conform to one of the standard i n s t r u c t i o n sequences. 4.2  Purchased Components Where possible, standard " o f f - t h e - s h e l f " components were  purchased f o r use i n the graphics display system.  The major purchased  components include:  4.3  a)  the display o s c i l l o s c o p e ,  b)  the major axis - D/A converters,  c)  power-supplies and  d)  c i r c u i t board mounting panels.  The Logic Family The graphics display system was implemented using 7400 and  3000 series TTL integrated c i r c u i t s . ' These l o g i c f a m i l i e s provide several advantages,  including the existence of a large number of func-  tions i n the product l i n e s , low propagation delays, compatibility with  52, the h o s t CPU and a v a i l a b i l i t y . 4.4  C o n s t r u c t i o n Techniques The  g r a p h i c s d i s p l a y system was c o n s t r u c t e d u s i n g  Equipment C o r p o r a t i o n H - s e r i e s wire-wrap mounting p a n e l s . panels for  Digital The H - s e r i e s  accommodate up t o 32 c i r c u i t b o a r d s , w i t h 72.conductor p o s i t i o n s  each b o a r d . Circuit  16-pin  boards w i t h up t o 50 wire-wrap s o c k e t s f o r 14- o r  integrated c i r c u i t s  d i s p l a y system. implementation  provided  Approximately  the b a s i s f o r c o n s t r u c t i o n o f the  15 c i r c u i t boards were r e q u i r e d f o r  o f t h e s p e c i a l - p u r p o s e d i s p l a y system  Wire-wrap t e c h n i q u e s interconnection.  The primary  circuitry.  were g e n e r a l l y u t i l i z e d  for circuit  advantage o f f e r e d by t h i s t e c h n i q u e i s  the a b i l i t y t o q u i c k l y make changes t o c i r c u i t s .  53, 5.  PERFORMANCE OF THE GRAPHICS DISPLAY SYSTEM  T a b l e 5.1 p r o v i d e s a summary o f observed c a l c u l a t e d host processor  overhead.  and  per p o i n t  A l l times  a r e approximate.  times a r e based p r i m a r i l y on t h e s e t t l i n g  p o i n t d i s p l a y requirements  s h o r t - v e c t o r and l o n g - v e c t o r  time and  CPU overheads a r e based on DMA  f e t c h e s from t h e Supernova p r o c e s s o r . Element g e n e r a t i o n  element g e n e r a t i o n  of the d i s p l a y o s c i l l o s c o p e .  Character,  elements r e q u i r e a t l e a s t 1.6 m i c r o s e c o n d s  (1.2 microseconds t o a l l o w o s c i l l o s c o p e s e t t l i n g , and 400  nanoseconds f o r p o i n t The  display).  t o t a l " f l i c k e r - f r e e " c a p a c i t y o f t h e d i s p l a y system i s  l a r g e l y dependent on t h e s c a l e f a c t o r used d u r i n g l o n g and s h o r t vector generation; also increased.  factor.  as t h e s c a l e f a c t o r i s i n c r e a s e d , t h e c a p a c i t y i s  The s u b j e c t i v e appearance o f d i s p l a y elements  The minimum s c a l e f a c t o r p r o v i d e s f o r t h e g e n e r a t i o n o f a  l o n g v e c t o r on a 0.01-inch g r i d . i s 0.02 i n c h e s , a v e c t o r generated appears continuous generated  (parti-  S i n c e t h e o s c i l l o s c o p e spot d i a m e t e r u s i n g t h e minimum s c a l e f a c t o r  and f a i r l y " s m o o t h " t o t h e human eye.  A vector  u s i n g t h e maximum s c a l e f a c t o r i s c o n s t r u c t e d on a  .08-inch  g r i d , and t h e eye i s v e r y aware o f the d i s c r e t e p o i n t make-up o f t h e vector. F l i c k e r - f r e e c a p a c i t y o f t h e d i s p l a y system f o r graph genera t i o n i s dependent on both t h e s c a l e f a c t o r and t h e programmable d e l a y . C a p a c i t y and CPU overheads a r e summarized Small c h a r a c t e r s a r e generated s c a l e f a c t o r 2.  i n T a b l e 5.2. on a 0.02-inch g r i d  using  At t h i s s c a l e f a c t o r , characters a r e approximately  GENERATION TIME (ysec)  ELEMENT  POINT \ GRAPH-POINTJ  5 15  1 1  CHARACTER  60  0.5  SHORT VECTOR  2 + 2N (1)  0.5  LONG VECTOR.  4 + 2N (1)  2  (1)  SHORT DELAY LONG.DELAY  CPU OVERHEAD (ysec)  N = NUMBER OF POINTS IN ELEMENT  TABLE 5.1  DISPLAY SYSTEM PERFORMANCE  PROGRAMMABLE DELAY  SCALE FACTOR  APPROXIMATE CAPACITY (1)  APPROXIMATE CPU LOADING  SHORT  MINIMUM  10  20%  SHORT  MAXIMUM  80  20%  LONG  MINIMUM  3  6.5%  LONG  MAXIMUM  26  6.5%  CAPACITY - The number o f f u l l - s c r e e n (10") graph p l o t s which can be accommodated a t a r e p e t i t i o n r a t e o f 20 frames p e r second.  TABLE 5.2  GRAPH GENERATION  PERFORMANCE  55, 0.14-inch h i g h by 0.1-inch wide, and across  70 c h a r a c t e r s  the f u l l w i d t h of the s c r e e n .  p o i n t make-up of each c h a r a c t e r  can be  At s c a l e f a c t o r 2,  i s only detectable  accommodated the d i s c r e t e  on c l o s e  examination.  20 f u l l  l i n e s of c h a r a c t e r s  can be d i s p l a y e d w i t h o u t  flicker  (20 r e p e t i t i o n s per  second^ a t the expense of l e s s t h a n 2%  host  CPU  t o 5000 s h o r t v e c t o r s  ( c o n t a i n i n g an average of 4  each) can be d i s p l a y e d w i t h o u t annoying f l i c k e r . pendent of the s c a l e f a c t o r employed. c i t y i s approximately Long v e c t o r s  at and  can be  is  inde-  loading at f u l l  generated a t v a r i o u s  (maximum s c a l e f a c t o r ) .  ten-inch vectors  rates ranging  (minimum s c a l e f a c t o r ) to 40  can be  capa-  l o a d i n g are increased  inches  from  per  At minimum s c a l e f a c t o r , at  generated w i t h o u t annoying f l i c k e r ,  the expense o f a p p r o x i m a t e l y 0.1% CPU  Host CPU  Capacity  points  5%.  per m i l l i s e c o n d  millisecond l e a s t 25  of  capacity. Up  5 inches  objectionable  of host  CPU  capacity.  The  capacity  by a f a c t o r o f 8 when the maximum s c a l e  f a c t o r i s employed. T y p i c a l d i s p l a y s w i l l c o n s i s t of a m i x t u r e of the element t y p e s .  T o t a l host  CPU  d i s p l a y , but w i l l n o r m a l l y n o t  loading  i s a f u n c t i o n o f the  various specific  exceed 10%.of the Supernova c a p a c i t y .  56, 6.  CONCLUSIONS  A computer-based display system was constructed the e x i s t i n g PDP-9 f a c i l i t y .  to augment  The l i m i t a t i o n s of the PDP-9 system  were overcome through the use of a high bandwidth display oscilloscope,, and a more sophisticated display processor.  By accessing  and executing  display instructions stored i n host CPU memory, the display processor r e l i e v e s much of the host CPU overhead associated with the maintenance of a graphics display.  The a b i l i t y to generate complex display  elements (for example, characters  and vectors) from s i n g l e - d i s p l a y  instructions reduces host CPU display software requirements c o n s i derably. During the four years between construction of the display system and the writing of t h i s t h e s i s , d i g i t a l technology has advanced considerably.  Examination of a l t e r n a t i v e solutions to display system  implementation i n l i g h t of the current technology i s appropriate.  An  obvious a l t e r n a t i v e solution to the problem i s to u t i l i z e the design of the graphics display system ( e s s e n t i a l l y as outlined i n t h i s t h e s i s ) , but implement the design with state-of-the-art components.  Extensive  use of medium and large-scale integrated c i r c u i t s would s i g n i f i c a n t l y reduce the s i z e and complexity of the display system. Another a l t e r n a t i v e would take advantage of programmable read-only memories (PROM's) now a v a i l a b l e .  This approach would require  a new design, the heart of which would consist of a high-speed PROMdriven processor s i m i l a r to those now used i n "micro-programmable" mini-computers.  commercially-available  This approach could be adopted  for the display processor only, or i t could be extended to encompass  57, the f u n c t i o n s performed  by the d i s p l a y - e l e m e n t g e n e r a t o r s .  The  of PROM r a t h e r than s t a n d a r d read-only-memory would f a c i l i t a t e a t i o n s d u r i n g system implementation a l t e r a t i o n s to the d i s p l a y  system.  use alter-  as w e l l as l a t e r a d d i t i o n s o r  58, APPENDIX 1  THE  VECTOR GENERATION ALGORITHM  T h i s appendix p r o v i d e s a d e s c r i p t i o n of the b i n a r y r a t e . ; ; m u l t i p l i e r a l g o r i t h m used i n l o n g - v e c t o r g e n e r a t i o n . C o n s i d e r an a r b i t r a r y v e c t o r between the o r i g i n and whose X and Y c o - o r d i n a t e s a r e DX i s generated  and DY  respectively.  a point  I f the v e c t o r  i n time T, then the e q u a t i o n f o r the X and Y components  of the d i s p l a y o s c i l l o s c o p e beam as a f u n c t i o n of time a r e  simply  X = DX(t/T) Y = DY(t/T) To produce an a p p r o x i m a t i o n  to the d e s i r e d v e c t o r , an a l g o r i t h m i s  r e q u i r e d which w i l l p r o v i d e , f o r example, DX X-axis co-ordinate value at approximately time  sented  T-i=>s:tr"i r>t-<=>H  2  2  and  v a l i i o q  rif  TW  DY = Y,,2  2  + X 2  1  increments  TW  T.7>i-f r - V i  ^a-p  \\o  -ropr-o—  + Y 2  1  0  + Y 2° Q  a l o n g the X a x i s , and DY  Time -i 2 2  0  0  0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 i i  An a l g o r i t h m f o r p r o d u c i n g  increments  3  0  ariH  Q  over 2 -1 time i n t e r v a l s i s i l l u s t r a t e d  0  the  + X 2 ,  where X^ and Y^ a r e b i n a r y c o e f f i c i e n t s .  2  e q u a l i n t e r v a l s over  the  as:  DX = X 2  9  of  T. C r i T i H T r}c*-r  DX  e q u a l increments  i n the f o l l o w i n g t a b l e .  Action (INCREMENT CO-ORDINATE IF SPECIFIED CO-EFFICIENTS ARE NON-ZERO) X-Axis Y-Axis Don't increment Don't increment X, Y. Xf Y2 X, Y, X  0  Y  X" X^  0  Y° Y^  yr  2  Y*  a l o n g the Y a x i s  In g e n e r a l terms, f o r v a l u e s of DX  and DY  up  to 2 -1,  the  a l g o r i t h m can be s t a t e d as: a)  l o c a t e the l e a s t i n the c u r r e n t  b)  increment  significant  non-zero power of two,  P,  time,  the X c o - o r d i n a t e i f the c o e f f i c i e n t  X„ _ i s N-P  the Y c o - o r d i n a t e i f the c o e f f i c i e n t  Y„ _ i s N-P  non-zero, c)  increment non-zero.  60. REFERENCES  1.  P r i n c e , M.D., Proceedings  "Man-Computer G r a p h i c s  f o r Computer-Aided  of the IEEE, -Vol. 54, No.  12,  pp.  1698  Design",  - 1708,  December,  1966. 2.  Mann, R.W., May,  3.  4.  "The  "CAD"  P r o j e c t " , Mechanical  S k i n n e r , F.D.,  "Computer G r a p h i c s - Where Are We?",  12, No.  28 - 31, May,  5, pp.  Coons, S.A.,  pp.  5, pp.  Myer, T.H.,  Sutherland,  E n g l i s h , W.,  S h e r r , S., W i l e y and  9.  Innovative Engineering  32 - 34, May,  67 - 71, December,  "How  I.E., "On  to Use  General Corporation, 8.  1966.  "Computer G r a p h i c s and  Coimnunicadons of the ACH, 7.  Datamation, V o l .  and  the D e s i g n  V o l . 11, No.  the Nova and  6,  of D i s p l a y Systems",  pp.  410  - 414,  1965.  Data  1970.  Sons, Inc., pp.  1964.  June,  the Supernova", Mass.:  280  M e r g l e r , H.W.,  - 306,  New  York:  John  1970.  S i n g e r , B.,  " D i g i t a l Linear Interpolation  the B i n a r y Rate M u l t i p l i e r " , C o n t r o l E n g i n e e r i n g , pp.  June,  Electronic  1968.  "Fundamentals of D i s p l a y System D e s i g n " ,  A r n s t e i n , W.,  Design",  1966.  S c h a r f , J . , " S i m p l i f y D e s i g n w i t h Computer G r a p h i c s " , The Engineer,  6.  41-43,  1965.  Datamation, V o l . 12, No. 5.  E n g i n e e r i n g , pp.  79 -  83,  

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