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On the design of wideband CMOS low-noise amplifiers Molavi, Reza 2005

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ON THE DESIGN OF WIDEBAND CMOS LOW-NOISE AMPLIFIERS by Reza Molavi B.A.Sc, Sharif University of Technology, 2003 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE i n The Faculty of Graduate Studies ^Electrical and Computer Engineering THE UNIVERSITY OF BRITISH COLUMBIA September 2005 © R e z a Molavi, 2005 ABSTRACT Integrated wideband low-noise amplifiers (LNAs) are used in communication applications in which either the signal bandwidth is large or multiple narrowband signals are processed simultaneously. An example of the former case is the recently popular ultra wideband (UWB) wireless technology that can be used for high-data-rate low-power short-range wireless communications. A multi-mode multi-standard wireless system is an example of the latter case. Providing large enough gain while introducing as little noise as possible over a wide frequency band is a challenging design task, in particular if the L N A is designed in CMOS. In this work, a methodology for designing wideband CMOS LNAs is presented. The core of the design is the inductively degenerated L N A which is a popular architecture in narrow-band applications due to its superior noise and input matching properties as well as low power consumption. Wideband performance of inductively degenerated L N A is explored both at the circuit and system level. Trade-offs among different design requirements and their impacts on circuit parameters is discussed in detail. To demonstrate the effectiveness of the design technique, two wideband LNAs are designed and simulated in a 0.18pm CMOS technology. The first L N A is intended for a multi-standard system with the frequency range of 1.4 to 2.5GHz. The frequency band of the second L N A is from 3 to 5GHz which covers the lower band of UWB technology. ii TABLE OF CONTENTS Abstract i i Table of Contents i i i List of Tables iv List of Figures v Acronyms vii Acknowledgements viii Chapter 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Research Goals 5 1.3 Thesis Outline 5 Chapter 2 BACKGROUND 7 2.1 Noise 8 2.2 Nonlinear Effects 16 • 2.3 Input Matching 20 2.4 S Parameters 24 2.5 Wideband L N A Topologies 26 Chapter 3 WIDEBAND L N A METHODOLOGY 38 3.1 Power gain and Impedance mismatch factor 39 3.2 Wideband noise and input matching 44 3.3 SNR-based Optimization Technique 52 3.4 Proposed Design Technique 58 3.5 Wideband Impedance Matching Networks 64 Chapter 4 SIMULATION RESULTS AND L A Y O U T ISSUES 70 4.1 Wideband L N A for multi-standard application in 1.5-2.5GHz 70 4.2 Wideband L N A for UWB application (3.2-5GHz) 74 Chapter 5 CONCLUSIONS A N D FUTURE WORK 80 5.1 Conclusions 80 5.2 Future Work 81 References 82 Appendix A Linear two port noise analysis 86 Appendix B Classic MOS device noise analysis 90 iii LIST OF TABLES Table 1 Wireless standards characteristics 3 Table 2 Summary of Performance 75 iv LIST OF FIGURES Figure 1.1 Block diagram of a simplified RF receiver 2 Figure 2.1 Thermal noise of a resistor 10 Figure 2.2 (a) Dominant sources of noise in a MOS - (b) Thevenin equivalent circuit ..12 Figure 2.3 Two-port network model of MOS device for noise calculations 14 Figure 2.4 NF calculations for a cascaded system 15 Figure 2.5 ldB compression point 17 Figure 2.6 (a) Signal spectrum of a nonlinear system (b) Graphical interpretation of IIP3 18 Figure 2.7 Different input matching topologies (a) resistive termination 21 Figure 2.8 Small signal model of an inductively degenerated L N A 23 Figure 2.9 S parameters definition of two-port networks 25 Figure 2.10 Two port model of a hunt-series amplifier 28 Figure 2.11 Common drain feedback L N A 29 Figure 2.12 Two-stage L N A for UWB applications 30 Figure 2.13 Two stage wideband L N A for UWB applications 31 Figure 2.14 Simplified block diagram of a shunt-feedback L N A 32 Figure 2.15 Schematic of thermal noise cancelling technique „ 33 Figure 2.16 Block diagram of balanced amplifier 35 Figure 2.17 Schematic of a basic distributed amplifier 36 Figure 3.1 Conceptual diagram of power transfer in an amplifier 39 Figure 3.2 Input mismatch factor with matching network 40 Figure 3.3 (a) Narrowband L N A (b) Wideband L N A 41 Figure 3.4 block diagram of a unilateral amplifier with port matching 43 Figure 3.5 Small signal model of an inductively degenerated L N A 44 Figure 3.6 Gain of L N A vs. Re{Z i n} and Re{Z o p t} for UWB applications in 3-5GHz....49 Figure 3.7 NF of L N A vs. Re{Z i n} and Re{Z o p t} for UWB applications in 3-5GHz 49 Figure 3.8 Gain of L N A vs. Re{Zop,j (co) for several values of Re{Zin} (Ls) 50 Figure 3.9 NF of L N A vs. Re{Zoptj (co) for several values ofRe{ZinJ (Ls) 50 Figure 3.10 Graphs of Re{Z;n} and Re{Z o p t} vs. frequency for UWB applications in 3-5GHz (W=75um) 51 Figure 3.12 SNR<,U, vs. Re{Z i n} and Re{Z o p t} for UWB applications in 3-5GHz 55 Figure 3.13 SNR of L N A vs. Re{Zo p,} (co) for several values of Re{Z i n} (L s) 56 Figure 3.14 Optimum value of Re{Zjn} (L s) for variations of N F e q 57 Figure 3.15 Contour plots of total power consumption 60 Figure 3.16 Transit frequency (ft) vs. overdrive voltage 61 Figure 3.17 Contour plots of equivalent noise resistance (R„) 62 Figure 3.18 (a) n matching network (b) T matching network 65 Figure 3.19 Contours of constant Q„ displayed in the smith chart 66 Figure 3.20 (a) n matching network (b) Equivalent circuit 67 Figure 3.21 Real parts of impedances Z,„ and Zeq over the UWB band 68 Figure 3.22 Imaginary parts (equivalent inductance) of impedances Z,„ and Zeq over the UWB band 69 Figure 4.1 Complete schematic of the multi-standard L N A 71 v Figure 4.2 Real part matching of Rin and Ropt for multi-standard L N A 72 Figure 4.3 Simulated S-parameters of the multi-standard L N A 73 Figure 4.4 Simulated NF and NFmin of the multi-standard L N A 73 Figure 4.5 Complete schematic of the UWB L N A 74 Figure 4.6 Layout of cascade amplifier for the UWB L N A 76 Figure 4.7 Nine-element equivalent model of spiral inductors 77 Figure 4.8 Simulated S-parameters of the UWB L N A (post-layout) 78 Figure 4.9 Simulated NF of the UWB L N A (post-layout) 79 Figure A . l (a) block diagram of noisy two-port network (b) Equivalent network with input and output noise current sources 86 Figure A.2 Input Referred equivalent noise model 87 Figure B.l (a) Noise sources of a MOS device b) Equivalent input referred model 90 vi ACRONYMS A D C Analog to Digital Converter ADS Advanced Design Systems CAD Computer Aided Design CMOS Complementary Metal Oxide Semiconductor C N M Classical Noise Matching D A Distributed Amplifier DAC Digital to Analog Converter DSM Deep Sub Micron DSP Digital Signal Processing GPS Global Positioning System GSM Global System for Mobile Communication IMF Impedance Mismatch Factor IMP Inter Modulation Product K C L Kirchhoff Current Law K V L Kirchhoff Voltage Law L N A Low Noise Amplifier LO Local Oscillator M C M Multi Chip Module M I M Metal Insulator Metal NF Noise Figure PCNO Power Constrained Noise Optimization PCSNIM Power Constrained Simultaneous Noise and Input Matching PCWSNIM Power Constrained Wideband Simultaneous Noise and Input Matching RF Radio Frequency SiP System in Package SNIM Simultaneous Noise and Input Matching SNR Signal to Noise Ratio UMTS Universal Mobile Telecommunication System UWB Ultra Wide band VCO Voltage Controlled Oscillator y s w R Voltage Standing Wave Ratio W L A N Wireless Local Area Network WPAN Wireless Personal Area Network vii ACKNOWLEDGEMENT There are many friends and colleagues that I would like to thank for their invaluable help and support during my years at UBC. First of all, I would like to thank my supervisor and friend, Dr. Shahriar Mirabbasi who gave me the opportunity to join his research group at UBC. His keen knowledge on the design of analog/RF integrated circuits was the key factor in the success of this research project. I am particularly grateful for the great advises, both technical and personal, that he gave me over these years. Also, I would like to thank Dr. Ivanov and Dr. Schober for reading my thesis and serving as my committee members. I am honoured to call myself part of SoC research group. Working with a group of brilliant researchers who were, undoubted fully, great motives throughout my research years, was a great privilege I benefited in SoC lab. I would like to express appreciations to all my friends at SoC particularly to Scott Chin, Howard Yang, Amit Kedia, Karim Allidina, Neda Nouri, Melody Chang, Samad Sheikhai, Pedram Sameni, Dipanjan Sengupta, Peter Hallschmid, Marwa Hamour,Behnoosh Rahmatian, Xiongfei Meng and Shirley Au. I also thank Roberto Rosales, Roozbeh Mehrabadi and Sandy Scott for their help and support in the SoC lab. I would like to extend my gratitude to all my friends and relatives in Canada and US with whom I shared great memories in the past two years, especially my uncles in Seattle, Farbod Abtin, Amirhossein Heydari, Amir Sadaghianizadeh and A l i Mashinchi. The last but the most, I would like to express my deepest appreciation to my wonderful parents and brother for their continuous love, inspiration and support. I could feel their supportive presence in every single moment of these two years even though they were physically miles away from me. Thank you from the bottom of my heart! This research was supported by NSERC and SiRF Technology Inc. viii This thesis is dedicated to: My father who is and will always be my best friend and teacher, My mother without whose unconditional support I would not be where I am today, My brother who is and will always be my most trustworthy friend, and My beautiful country, Iran. ix Chapter 1 - Introduction 1 CHAPTER 1 INTRODUCTION 1.1 Motivation Communication technology is moving toward a major milestone. The explosive growth of the wireless industry, global access to the internet, and the ever increasing demand for high speed data communication are spurring us toward rapid developments in communication technology. Wireless communication plays an essential role in this transformation to the next generation of communication systems. Cellular phones, pagers, wireless local area networks (WLAN), global positioning system (GPS) handhelds, and short-range data communication devices employing Bluetooth and ultra wideband (UWB) technologies are all examples of portable wireless communication devices. Nowadays, driven by the insatiable commercial demand for low-cost and low-power multi-standard portable devices, RT designers are urged to develop new methodologies that allow the design of such products. An irreplaceable component of any RF receiver is the front-end low-noise amplifier (LNA). As the first active building block in the receiver front-end, the L N A should provide considerable gain while minimizing the noise introduced to the system. Fig. 1.1 depicts the simplified structure of an RF receiver. The received signal is typically filtered, amplified by an L N A and translated to the base-band by mixing with a local-oscillator (LO). After being demodulated, the signal is applied to an analog-to-digital converter (ADC) which digitizes the analog signal. The digital signal is then processed in a digital signal processing unit (DSP). As Chapter 1 - Introduction 2 can be seen, the first step of signal amplification is done by the L N A . Therefore, the performance of L N A can greatly affect sensitivity and noise parameters of the overall receiver. Bandpass filter Demodulator ADC Figure 1.1 Block diagram of a simplified R F receiver Why Wideband? Recently, there has been a tremendous effort to develop wireless devices that integrate multiple applications (phone, video-game console, navigator, digital camera, web browser, etc.) on a single chip. A variety of standards exist for each of these applications. The plethora of standards include global system for mobile communication (GSM) and universal mobile telecommunication system (UMTS) for cellular telephony, IEEE802.Ha/b/g and HiperLAN2 for L A N access, Bluetooth for short-range communication, and GPS. A brief summary of these standards is provided in Table 1 [1][2][3]. The growing number of these wireless communication standards promotes the need for a multi-standard transceiver. The RF front-end of such a receiver has to cover a wide range of different carrier frequencies (see Table 1). To achieve this goal, wideband performance of the receiver front-end is desired. A variety of architectures have been proposed to fulfill this requirement. One approach is to use a parallel combination of several tuned narrowband LNAs. This solution, although straightforward, is power hungry and area Chapter 1 - Introduction 3 inefficient. Therefore, it is not particularly suitable for low-cost portable systems. Two other LNA architectures that can be used for multi-standard signal reception are concurrent LNA [4] and tuneable LNA [5]. The former technique is applicable when the frequency bands of desired standards are well separated, while the latter design approach is complicated if a wideband tuning-range is desired [6]. An alternative solution is to design a single wideband LNA covering the entire band of interest, which is the subject of this research. Wireless Carrier Channel Access Modulation Standard Frequency Spacing Scheme Technique uata Kate GSM 880-960MHz 200kHz TDMA/FDD GMSK 270.8kb/s PCS 1900 1.88-1.93GHz 200kHz TDMA GMSK 270.8kb/s GPS 1.575GHz 2MHz C/A code N/A BPSK/SS 50b/s IEEE 802.11a 5.15-5.85GHz 20MHz OFDM QPSK up to 54Mb/s IEEE 802.11b 2.4-2.48GHz 22MHz CDMA/DSSS QPSK up to UMb/s Bluetooth 2.4-2.48GHz 1MHz CDMA/FH GFSK IMb/s UWB 3.1-10.6GHz N/A OFDM QPSK up to 480Mb/s UMTS 1.92-2.17 GHz 5MHz CDMA QPSK 3.84Mb/s Table 1 Wireless standards characteristics Wideband LNAs also find application in the recently introduced UWB systems. Over the last few years, these systems, initially developed for wireless personal area network (WPAN) application, have received significant attention from industry, media and academia. Theoretically, UWB systems support data rates from HOMb/s at a distance of 10 meters to 480Mb/s at a distance of 2 meters, while consuming little power [7]. The allocated frequency band for the UWB system is 3.1-10.6GHz (low-frequency band: 3.1-5GHz; high frequency band: 6-10GHz). Therefore, the design of a wideband LNA covering the entire band of interest is of major concern in the development of a UWB receiver. Chapter 1 - Introduction 4 Other applications of wideband LNAs include analog cable (50-850MHz), satellite (950-2150MHz) and terrestrial digital (450-850MHz) video broadcasting [8]. Transceivers used in optical links with a high number of channels also need a wideband L N A at the front-end [9]. Why CMOS? Currently, most commercial RF transceivers are implemented as multi-chip modules (MCMs) or system in packages (SiPs), using various technologies [10]. Base-band and mixed-signal components (e.g., DAC, ADC, and DSP) are mainly implemented in complementary metal-oxide semiconductor (CMOS) technology, while RF and analog sections are typically implemented in silicon-germanium (SiGe) or gallium-arsenide (GaAs) technologies. High quality passive filters are mostly realized as discrete components. M C M and SiP approaches suffer from many shortcomings, such as large size, high power consumption, and high integration cost. The aforementioned problems account for the global trend toward a single technology that can support a commercially viable single chip RF transceiver. Historically, CMOS technology was not considered a good candidate for analog and RF applications. Relatively small transconductance, low drive capability, and poor quality of on-chip passive elements are among the several limitations of this technology. However, the incredible growth of the digital industry due to the continuous scaling in CMOS technology has motivated designers to develop analog and RF CMOS circuits that can be integrated along with the digital circuitry. This has led to the tremendous research and development in implementing single chip systems. Furthermore, the transit frequency ( / J ) of MOS devices has recently increased due to the evolution of CMOS into deep-sub-micron (DSM) technologies (/,'s exceeding 100GHz have Chapter 1 - Introduction 5 been recently reported [11]). This greatly improves the performance of integrated RF CMOS circuits. To summarize, despite the inferior performance of RF CMOS circuits compared to their SiGe and GaAs counterparts, the dominance of CMOS in the digital world, combined with the feasibility of integrating digital/RF/analog circuits on a single chip and the potential cost and power advantage of this integration, provide reasonable motives to adopt CMOS over other technologies. 1.2 R e s e a r c h G o a l s The objective of this thesis is to develop a wideband L N A design technique suitable for the inductively-degenerated L N A architecture. To accomplish this task, first a detailed analysis of this architecture is presented and the wideband performance of L N A is studied from both the circuit and the system level perspectives. Afterwards, the effect of different circuit parameters on the wideband performance of the L N A is discussed. Finally, the results of this research are used to develop a step-by-step design technique that satisfies the requirements of low noise, high gain, and the input matching over a wide frequency range. The proposed wideband design technique is used to successfully design and simulate two different wideband LNAs in a 0.18pm CMOS technology. The results of these simulations demonstrate the applicability of the proposed methodology to the design of wideband RF front-ends needed for many applications such as UWB and multi-standards transceivers. 1 .3 T h e s i s O u t l i n e This thesis is organized as follows: Chapter 2 reviews the fundamentals of the L N A design such as its noise figure and the input matching. Different L N A architectures, which are suitable for —J Chapter 1 - Introduction 6 wideband applications, and their corresponding advantages and disadvantages, are presented. This chapter emphasizes the need to develop a wideband L N A methodology. Chapter 3 suggests the use of an inductively degenerated topology as an appropriate candidate for the wideband L N A design. A detailed analysis of this topology and the underlying concept of the wideband noise and input matching are presented. Furthermore, the trade-off among different design issues such as noise, gain, input matching, and power consumption is addressed. Chapter 4 demonstrates the simulation results of two different CMOS LNAs designs using the proposed design technique. Issues related to the layout of high frequency CMOS L N A are also discussed. Finally, Chapter 5 presents concluding remarks and suggestions for future work. Chapter 2 - Background 7 CHAPTER 2 BACKGROUND In a receiver chain, L N A is usually the first active signal-processing block after the antenna. The amplitude of the received signal at the input of L N A may vary from few nV (less than -130dBm for GPS signals) to tens of mV (e.g., large interferers accompanying the signal). The L N A should be capable of amplifying all these signals without causing any significant distortion. Furthermore, the sensitivity1 of L N A determines the sensitivity of the overall receiver. This requires that very little noise from the L N A be introduced to the entire receiver [12]. Another major requirement of the L N A is to provide a large gain to suppress the noise of subsequent blocks. This issue will be discussed in detail shortly. LNAs are usually preceded and followed by passive filters for out-of-band rejections and channel selection. The transfer function of such filters is usually a function of their termination impedance. This imposes the requirement of certain input and output impedances, such as 50Q, on the L N A . On the other hand, as will be shown in the following sections, the amount of noise introduced by the L N A is also a function of source impedance. The optimum source impedance, which results in the minimum noise figure of the L N A , may not be equal to that required by the preceding stage, e.g., 50Q. This may result in an L N A having a good input matching and a poor noise figure or vice versa. ' The sensitivity of a receiver (or block) is defined as the minimum level of the input signal for which the receiver (or block) provides an acceptable signal quality. Chapter 2 - Background 8 The design of an L N A satisfying all these requirements in a wide bandwidth is even more challenging and needs a careful study of the different parameters affecting noise, gain, and linearity. To achieve this goal one needs to develop an accurate mathematical model for the L N A and find the analytical expressions for noise, gain, and linearity. 2.1 Noise In communication systems, any signal other than the desired signal is called noise and will reduce the sensitivity of the overall system. Different sources of noise with different noise generation mechanisms exist. The dominant sources of noise in integrated circuits are shot noise, flicker noise, and thermal noise. Shot noise is mainly caused by the hopping of electric charges over a potential barrier and is specific to nonlinear devices such as diodes and transistors. In MOS devices, which are the subject of this work, the only source of shot noise is the DC gate leakage current, and hence it is not considered a major problem [12]. This is in contrast to bipolar transistors in which base and collector shot noise may significantly degrade the performance of the overall receiver. Flicker noise, also known as pink noise, occurs due to the trapping of charges in the defects and impurities of the channel region in MOS devices [12]. As a general rule, larger MOS devices experience less flicker noise. The spectral density of this noise is given by: r K.S 2 i 1 - S m (7 1) fWLCj ( J where K is a device-specific constant, gm is the transconductance of the MOS device, / is the operating frequency, Cox is the gate-oxide capacitance per unit area, and W and L are the width and length of the MOS device, respectively. Chapter 2 - Background 9 As can be seen from (2.1), the amount of flicker noise is inversely proportional to the frequency of operation. Therefore, flicker noise can be a dominant noise source at very low frequencies. In LNAs where the frequency of the received signal is about several gigahertz, flicker noise does not play an important role and is usually ignored. It is worth mentioning that in other receiver stages such as mixers or voltage controlled oscillators (VCO) flicker noise can be a major problem. Thermal Noise Thermal noise is the noise caused by the agitation of carriers in a conductor, and its spectrum density is given by the following quantity known as available noise power [12]. PNA=kTAf . (2.2) where k is the Boltzman constant (~1.38 x 10 J/K), Tis the absolute temperature in Kelvins, and Af is the bandwidth of the noise measured in Hz. The value of this quantity for \Hz of noise bandwidth at room temperature (290AT) is -MAdBm and is often called the noise floor of the system. The noise floor is an important quantity in determining the sensitivity of the receiver [13]. The available noise power is the maximum power delivered to a load from a noise source. On the basis of this definition, the thermal noise of each passive or active element can be modelled with an equivalent voltage or current noise source. To demonstrate this equivalency, consider the network shown in Fig. 2.1 and the equivalent noise voltage source of the resistor Chapter 2 - Background 10 Figure 2.1 Thermal noise of a resistor PR=kTAf=i*xRi RI=R — ^' 1 R 4R (2.3) Therefore, the mean square noise voltage over a noisy resistor (en2) is 4kTRAf. As a reference point, the rms voltage noise of a 50Q resistor is equal to InV/yjHz Dominant sources of noise in MOS devices MOS devices act like a trans-conductance in the saturation region, and like a resistance in the triode region. So, one should expect a thermal noise associated with the carriers in the channel similar to the noise of carriers in a conductor. Van der Ziel in [14] has derived the expression for the drain current noise of MOS devices, also known as channel thermal noise: ind2=4kTrgd0Af (2.4) where gdo is the drain conductance for zero drain-source voltage and y is a technology-dependant parameter and has a value of around 2/3 for long-channel devices in saturation (in short channel devices y is larger and its value is between 2 and 3) [15]. Chapter 2 - Background 11 A careful examination of noise characteristics in a MOS device reveals that channel thermal noise does not fully take into account all the noise associated with a MOS device [16]. The extra noise can be modelled by introducing a frequency-dependant gate conductance: co2C (2.5) 5gdo and an equivalent gate current noise of: 7^ = 4kTSggAf (2.6) where S is the gate noise coefficient and is also a technology-dependant parameter. Its value is 4/3 for long channel devices and is augmented by a factor of 2 in short channel devices. Note that the gate current noise is partially correlated with the channel thermal noise and their correlation coefficient factor is given by: 4 (2.7) i 2i 2 where c is a complex number and its value is theoretically computed to be around -0.395J for long channel devices [14]. This value is higher for short channel MOS and an experimental value of —0.5j is usually assumed for noise calculations. The exact value of y and S depends on the technology and, unless provided by the foundry, is cumbersome to measure. However, it can be shown that the noise behaviour of an L N A depends on the ratio of these two numbers and not their exact value. Fortunately, this ratio is almost a constant (S/y~2) regardless of whether we use long channel or short channel devices. Hence, one can determine the characteristics of an L N A without knowing the exact values of these parameters. Chapter 2 - Background 12 Another source of noise in MOS devices that may contribute to the total noise of the L N A is the noise generated by the distributed resistance of poly-silicon gate [17]. The value of this resistance is given by: RJV_ 3n2L (2.8) where RA is the sheet resistivity of the gate terminal, n is the number of gate fingers in the layout of the device, and W and L are the width and the length of the MOS device, respectively. The value of this resistance (and the associated noise) can be decreased through the careful layout of transistor, and therefore be rendered insignificant in the noise calculations. Different sources of noise in a MOS device are shown in Fig. 2.2. e2. Rg RG R^s R_ ^RgMS R s g.NQS - £ W w — O — M A — i J (b) Figure2.2 (a) Dominant sources of noise in a MOS - (b) Thevenin equivalent circuit Another resistance associated with the gate of MOS devices, known as the non-quasi-static gate resistance (RG.NQS), is also reported in the literature [20][18][19]. In fact, RG,NQS is the equivalent series resistance of the Thevenin network representation of the conductance gg and noise current source i2ng discussed earlier (see Fig. 2.2b). R G ,NQS (2.9) Chapter 2 - Background 13 Noise Figure Noise figure (NF) is a measure of signal-to-noise ratio (SNR) degradation as the signal traverses the receiver front-end. Mathematically, NF is defined as the ratio of the input SNR to the output SNR of the system. SNRJN total output noise power NI = = (2.10) SNR0UT output noise power due to source NF may be defined for each block as well as the entire receiver. NFLNA, for instance, determines the inherent noise of the L N A , which is added to the signal through the amplification process. With the use of the classical two-port network theory, it can be shown that the NF of a noisy two-port network is given by (Appendix A): NF = NFMIN + ^ -[(Gs -Goptf +(BS -Bopl)2] (2.11) where NFMI„ is the minimum achievable NF, Bopt and Gopt are the optimum source susceptance and conductance corresponding to NFmj„, and RN is an equivalent noise resistance, which quantifies the sensitivity of NF to departure from optimum conditions. Note that NF is a function of source admittance seen from the input terminal of the two-port network. To achieve the NFMIN, an optimum admittance, namely Yopt, should be introduced to the network. The expressions for NFMI„ and Yopt can be derived for a MOS device by considering a two-port network model for the MOS device. In this model the gate-source terminal is the input port and the drain-source terminal is the output port. Figure 2.3 shows the small signal model of a MOS device (including all sources of noise), connected to the noise source i2s and the source admittance Ys=Gs+jBs. Chapter 2 - Background 14 Assuming that i2nd and i2ng are dominant sources of noise in MOS devices, the following expressions for NFmj„ and the noise parameters can be obtained: opt Figure 2.3 Two-port network model of MOS device for noise calculations rg dO (2.12) G„„, =aojCg ^-(\-\cf) opt (2.13) Bopt=-ccCgs(\-a\cl\-) gs (2.14) NF.„ :1 + 2 « ^ H ^ f ) V 5 cot (2.15) where a is the ratio of gm and gdo and is equal to one for long channel devices and decreases as devices shrink to smaller dimensions. It is evident from (2.15) that the minimum noise figure decreases with the increasing transit frequency (/J). This will be an advantage of using the CMOS process because, as mentioned in the previous chapter, CMOS scaling into D S M technologies increases the value of/J. Chapter 2 - Background 15 Direction of Signal Propagation Figure 2.4 cascade of several noisy blocks Noise f igure : System level considerat ions In a receiver path, as the signal propagates from the antenna to digital back-ends, different blocks may introduce noise to the signal. The overall NF of the receiver depends on the NF of each block as well as the gain of preceding stages. Intuitively, larger signals are less susceptible to noise, and this is why the large gain of one stage makes the noise of the following stage less important. Friis [20] shows that the overall NF of a cascaded system (such as the one shown in Fig. 2.4) is given by: NF„. =NF + i V F , NF. A j A ^ A 2 •+. (2.16) where NFt and At are the NF and available power gain2 of each stage, respectively. Assuming that Ai is a large value then NFi is the dominant term in (2.16). This accounts for the fact that the low noise of the L N A , i.e., low NFi, is of great importance in the receiver design. Note that NF2 is the NF of the second stage, which is usually a mixer. Mixers usually exhibit much higher NF than LNAs; therefore, it is essential that the gain of the L N A be large enough (high ^4/) to reduce the contribution of NF2 to NFtot. NFtot determines the sensitivity of the overall receiver. This relation is analytically given by: The available power gain is defined as the ratio the power available from the network to the power available from the source. Chapter 2 - Background 16 Sensitivity (dBm) = -\14dBm I Hz + \0log(BW ) + NFtot + \0\og(SNRoul) (2.17) where -174dBm/Hz is the available noise power from the antenna (the noise floor) and BWis the bandwidth of the desired signal, and the last term is the minimum acceptable SNR at the receiver output, which is a function of minimum required bit-error-rate (BER) at the output of the demodulator. As can be seen from (2.16) and (2.17), low NF of the L N A greatly improves the sensitivity of the overall receiver. 2 . 2 N o n l i n e a r E f f e c t s The dynamic range (DR) is usually defined as the ratio of the maximum input signal that the circuit can tolerate to the minimum input signal that provides adequate signal quality. The L N A should possess a large DR to guarantee that it remains linear when receiving weak signals in the presence of strong interferers. The upper limit of DR in low-frequency applications is usually defined as the maximum input power that the circuit can handle without going into saturation. However, in high-frequency applications, non-linear effects such as inter-modulation distortion or signal compression may be prominent and limit this upper bound There are many measures of linearity for high frequency circuits, but the most commonly used are the 1-db compression point (PMB) and third order intercept point (IP3) [13]. The input 1-dB compression point is usually defined as the amplitude of the input signal at which small-signal gain drops ldB below its nominal value (Fig. 2.5). Input signals above the compression point are usually clipped or saturated at the output; therefore, the compression point is considered an upper bound on the dynamic range of the L N A . Chapter 2 - Background 17 P out,ldB / 1 dB *- Pin(dBm) Figure 2.5 ldB compression point Another issue that may cause signal distortion is the multiplication of the input signal with its harmonics, generated due to the nonlinear nature of the realistic systems. This mixing (multiplication) will produce output terms known as inter-modulation products (IMP). For instance, if two adjacent sinusoids (also known as "two tones'") are applied to the input of a nonlinear system, the harmonics of these signals will produce many unwanted components at the output of the system. The frequency of some of these unwanted components may be very close to that of the desired signals and cause signal distortion, see Fig. 2.6 (a). To further illustrate the inter-modulation effect, consider a realistic system with the following input-output relation: Now assume the input is formed by two closely-spaced sinusoidal components of the same amplitude: y(t) = aix(t) + a2x2(t) + aix\t) + ... (2.18) x(t) = A (cos(a>/) + cos(<»/)) (2.19) Chapter 2 - Background 18 Then at the output of the system, the following terms exist in the vicinity of a>j and a>2: First-order terms: Third-order IMP terms: at a>x :yaX -(a{A +—aiA})cos(a)]t) 9 at o)2:ya2 = (alA +—aJAi)cos(a>2t) at 2ax -a)2:y: 3 a3A3 cos(2«, -co2)t at 2a>2 - a),: y 2 ^ - - a3A cos(2<y2 - OJx )t (2.20) (2.21) P„ u,(dBm) Adjacent channnels Nonlinear system Input spectrum <w( co 4 4 2ft),- cot Output spectrum I M product piiP3.in P i n (dBm) (a) (b) Figure 2.6 (a) Signal spectrum of a nonlinear system - (b) Graphical interpretation of IIP3 In typical systems, GC3 is usually a negative number and is much smaller than a/, so for small input signals the first-order terms, i.e., (2.20), are dominant at the output. However, as the amplitude of the input signals increases, first-order terms do not grow as fast as the IMP terms (the former increases linearly with the amplitude while the latter increases proportional to A 3 ) . The input level for which fundamental terms and IMP at the output have the same power is called third-order input intercept point (IIP3). Mathematically, this can be expressed as follows: Chapter 2 - Background 19 3a, (UP3)3 ax (IIP3) = — ^ '— => 2ZP3 =, «i 3 «3 (2.22; These calculations are based on the assumption that the terms (9/4a$As) are negligible in_yw/ and ym2 expressions. However, at the intercept point where the amplitude of signals are quite large, this assumption no longer holds and therefore the calculated value of IIP3 in (2.22) is just an extrapolation of the small input behaviour of the system. Nevertheless, in practical systems the effect of these terms, i.e. (9/4a$A ), is to increase the actual IIP3, and the calculated value of IIP3 may be used without any difficulty. This can also be verified from Fig. 2.6 (b) where the actual IIP3 is higher than the extrapolated one. Linearity: System level considerations The overall linearity of a receiver consisting of a cascade of several blocks depends on the gain as well as the linearity of each stage. This can analytically be shown by once again considering the chain of Fig 2.4 and expressing the input-output relation of the different stages in the chain. However, finding a closed-form expression for the linearity of overall system is rather difficult and requires some simplifying assumptions. The following expression gives an estimate of the worst-case IIP3 of the system in terms of the IIP3 of individual blocks in the chain [21]: 1 1 + a ^ + g a l + ^ A AL A1 A UPljtot IIP 3,i ™ UP 3,2 ^ //P3.3 where Anp3,i and a, are the IIP3 and gain of the /-th stage, respectively. A careful examination of (2.23) reveals that if each stage in a cascade has a gain greater than unity, then the nonlinearity of the following stage becomes more critical [21]. This means that the nonlinearity of the L N A , as the first building block, does not affect the overall nonlinearity as much as the nonlinearity of the Chapter 2 - Background 20 following stages, e.g., mixers, does. This expression also states that the high'gain of L N A degrades the overall linearity of the system. This is in contrast with the NF scenario in which the high gain of the L N A improves the overall NF. Despite the opposing behaviours of NF and linearity, designers typically try to maximize the gain of the L N A to achieve a better NF response. 2.3 Input Matching To deliver the maximum power from the antenna to the L N A , matching to the impedance of antenna, e.g., 50D., is required at the input port of the L N A . For wideband applications, this impedance matching should be obtained over a wide frequency range at the input port of the L N A and is usually a major challenge considering the noise and power consumption requirements. To quantify the degree of the impedance matching, it is customary to introduce the concept of voltage standing wave ratio (VSWR) [22]: i+|r| VSWR=—Li 2.24) i - r where F is the reflection coefficient and is defined as lz - Z _ r = z +z„ (2.25) In this expression, Z is the actual input impedance and Z 0 is the characteristic impedance of the source, which is usually equal to 50Q. Perfect matching (Z=Z0) results in F=0 (-oo dB) and equivalently VSWR=1. However, for practical purposes F<-l0dB is usually sufficient to meet the matching requirement. Chapter 2 - Background 21 J (a) (b) R rVNAA-(c) (d) Figure 2.7 Different input matching topologies (a) resistive termination 0>) 1/gm termination (c) shunt feedback (d) inductive degeneration There exist several architectures that generate the required 50Q impedance at the input port of the L N A . Some popular topologies are shown in Fig. 2.7. The simplest method to obtain matching over a wide range of frequencies is to use the resistive termination illustrated in Fig. 2.7 (a). However, this method suffers from a relatively high NF due to the thermal noise of resistive termination. Referring all noise sources to the input of the L N A and using the definition of NF, it is easy to show that: NF = -Total input referred noise input noise due to source only • = 2 + - n,MOS KTRAf (2.26) This is just a low-frequency limit for which the gate noise is totally ignored. The actual NF is much higher and gets even worse at higher frequencies. Another shortcoming of the resistive termination is that the input power is attenuated by the resistive divider before reaching the MOS device, and this will reduce the maximum power gain. Chapter 2 - Background 22 An alternative approach to achieve input matching is to use the source of a MOS device as the input termination, symbolically depicted in Fig. 2.7 (b). In common-gate architecture, the impedance looking into the source terminal of active device is l/gm. Therefore, proper bias and sizing of the L N A will result in l/gm=50 and satisfies the matching requirement. However, there still exists the problem of high NF with this architecture. The impedance matching at the input port yields the following lower bound on the NF of common gate L N A [12] This will force a lower limit of around 4.7dB (y/ci ~ 2) in short-channel devices, which is not an acceptable value for applications such as GPS receivers. Shunt feedback amplifier suggests yet another solution for achieving the required matching at the input port (see Fig. 2.7 (c)). This type of amplifier employs negative feedback to generate the 50Q impedance at the input port. This architecture still suffers from the thermal noise of the shunt resistor; however, the lower bound on NF is usually smaller than that of resistive and l/gm terminations. A modified version of this architecture that incorporates series feedback is widely used in the wideband L N A designs and will be addressed in section 2.5. To overcome the deleterious effect of real resistors on the NF of LNAs, designers suggest the use of inductively degenerated LNA to generate the required input impedance. Consider Fig. 2.8 where the small signal model of an inductively degenerated L N A is shown. Writing the K V L at the input port we obtain: NF>1 + ^ (2.27) a v in («) = iln (»)(/ (Lg +Ls)co-J (2.28) Chapter 2 - Background 23 Small Signal Model in in ^7 L 9 V gs Figure 2.8 Small signal model of an inductively degenerated LNA which yields Z,„{co) = = +J(Ls +Lg)co + cotLs (2.29) where a>t—gm/Cgs is the transit frequency of the MOS device. Evidently, the last term in (2.29) is a real impedance with the advantage that it does not have the thermal noise of a resistor. The value of source inductance needed to satisfy the input matching, i.e. <y,Z,=50Q, is usually very small (e.g., a few nH). This small inductance is usually realized using bond-wires with high-quality factors and hence negligible loss and noise. One immediate observation from (2.29) is that impedance matching is only achievable at a single frequency, more precisely, the resonance frequency of series inductors and gate-source capacitance: 1 6)0 = (2.30) Chapter 2 - Background 24 Due to the superior performance of L-deg L N A in terms of NF and power consumption, this architecture has found many applications in industry. In the last few years, several design techniques have been developed to satisfy the noise, gain, and power requirements of L-deg L N A for different applications. However, due to the narrowband nature of (2.29), none of these approaches are suitable for broadband applications. To summarize, the important requirements of an L N A are low NF, high gain, good input matching, and good linearity. With these goals in mind, we will now start our study of the existing wideband architectures. Before doing so, we will introduce the concept of S-parameters, which is a widely used concept in the context of high frequency amplifier design. 2.4 S Parameters Two-port networks are described in numerous ways. The most well-known description is to relate the four variables of input/output voltage/current by using a 2x2 matrix. Depending on which two of these four elements are selected as the independent variables, different matrices can be defined. Impedance (Z) matrix, admittance (Y) matrix, and hybrid (H) matrix are the most common matrices that define the two-port network voltage-current relation. In order to find the elements of these matrices, certain short and open-circuit tests must be performed on the network. However, these tests might not be possible at very high frequencies where open and short tests fail due to the existence of stray capacitances and inductances as well as transmission line effects. Chapter 2 - Background 25 z0 E E i2 vV\A E r1 Two Port Network E r2 Figure 2.9 S parameters definition of two-port networks The inability to perform short and open tests and the possibility of harming the circuit during these tests suggest the use of an alternative solution to characterize the network at high frequencies [23]. One popular solution is the introduction of the Scattering parameters (simply S parameters), which defines the four variables as the incident /reflected input/output voltage waves (or powers). The definition of S parameters exploits the fact that a transmission line terminated in its characteristic impedance does not reflect any power at its termination [12]. To show the usefulness of this property, consider the block diagram of a two-port network shown Fig. 2.9 where Zo is the impedance of the source and the load terminations and En and Eri are the magnitude of incident and reflected voltage waves, respectively. The S parameter coefficients are expressed as: The normalization to the square root of Zo makes the square of magnitude of at and bt equal to the incident and reflected power at both ports. bx =suai + si2a2 b2 — s2iaj +s22a2 (2.31) where (2.32) Chapter 2 - Background 26 Now, if we terminate port two in Zo , which sets a? equal to zero, and apply a power source to port one, we obtain the following relations: E „ ''21 i „ 2 = o En «. V2 la2=0 En (2.33) where su is called the input reflection coefficient and is a practical measure for the impedance matching at the input port of the L N A and S21 represents the forward gain of the amplifier. If, on the other hand, port 1 is terminated to Zo and power is sent from port 2: E. a2 la,=0 ^''2 a2 V 2 lfl,=o En (2.34) where S12 is the reverse transmission or gain of the network and S22 is called the output reflection coefficient of the network. Using these definitions, we can predict that a good amplifier should possess a large S21 to achieve high gain, small su and S22 to possess good input and output matching, and very small sn to ensure stability and reverse isolation. The typical values of S parameters for an L N A are su and S22<- 10dB, S21 >10dB, and si2<-40dB, which may vary according to the application. 2.5 Wideband LNA Topologies The major challenges of a wideband L N A design can be summarized in terms of S parameters and NF as follows: [24] • Forward gain degradation (decreases in S21) which necessitates some techniques to compensate the gain roll-off. • Frequency variations of su and S22-Chapter 2 - Background 27 • Increase in \sj2\ which will reduce the forward gain and increase the possibility of oscillation and instability. • NF degradation at high frequencies. To address these challenges in the design of a wideband L N A , several topologies and circuit techniques have been proposed in the literature. In This section, we will introduce briefly some of the popular wideband architectures and briefly discuss their advantages and disadvantages. Negative Feedback Wideband LNA The classical approach to satisfy the required impedance matching at the input of a wideband L N A is to employ negative feedback. This technique will provide a flat gain and a very small VSWR at the input and output ports, and also it reduces the sensitivity of the circuit to the MOS device parameters. However, as discussed in the analysis of shunt feedback amplifier, the feedback circuitry may increase the minimum NF and reduce the maximum achievable gain. Different topologies of negative feedback amplifier exist in the literature. One of the most popular variations of negative amplifier is the shunt-series amplifier, symbolically shown in Fig. 2.10 (as a two-port network). To achieve wideband input and output matching, one should design for zero sn and S22 after finding the S parameter expressions for this network. Solving for Su=S22=0, yields the following equation that relates the values of/?/ and R2 [24]: R 1 (2.35) 8 m Chapter 2 - Background 28 nAAA-n + Port 1 Port 2 Figure 2.10 Two port model of a hunt-series amplifier An appropriate choice of R; and R2 values will satisfy (2.35) and hence the input and output matching. It will also result in a flat in-band forward gain with no dependency on the MOS device parameters (see [24]). However, (2.35) is only valid in low frequencies where all parasitic effects may be ignored. In gigahertz applications parasitic capacitances and inductances become non-negligible and the power gain starts to roll-off. The input and output matching also degrades significantly in high frequencies. One implementation of a negative feedback amplifier is shown in Fig. 2.11. In this circuit [25] the input stage is a common source amplifier and the feedback stage is a common drain amplifier. A simple analysis of this circuit shows that gm,M2 of the common drain stage controls the input impedance, while gMiMi of the common source amplifier contributes to the gain and NF of the overall LNA. This is in contrast to the l/gm termination architecture where the gm of the input transistor is set by the input matching requirements and leaves no freedom for NF optimization. The main disadvantage of this architecture is the relatively high power consumption due to the addition of the feedback stage. Chapter 2 - Background 29 I 5 Figure 2.11 Common drain feedback L N A In another work, negative feedback is employed to realize a UWB L N A covering a 7GHz bandwidth ( 2 - 9 GHz) [26]. The schematic of this L N A is shown in Fig. 2.12. The input stage adopts a shunt-series feedback structure to satisfy the wideband input matching. The inverter configuration at the input is to increase the total trans-conductance (gmi+gm2), and hence the open-loop voltage gain for a fixed power consumption. The increase in the total trans-conductance also allows for a higher shunt resistor for a given 3dB bandwidth. This increase in the value of shunt resistance will lend itself to a lower total NF. Two degeneration inductances Lsi and LS2 are used to partially cancel the parasitic capacitances at the input of the L N A , which would otherwise devastate the impedance matching at high frequencies. The second stage is a simple cascode amplifier with a shunt-peaking load that provides the required gain of the entire L N A . Chapter 2 - Background 30 Figure 2.12 Two-stage L N A for U W B applications Negative feedback amplifiers may also be used as the second stage of wideband amplifiers. One example is the work in [27] that combines the benefits of l/gm termination with those of the negative feedback amplifier. Fig 2.13 depicts the schematic of this architecture. The input stage uses a common-gate amplifier to achieve 50Q impedance matching. However, this matching sets the value of gm,Mi, and another stage is required to provide sufficient gain over the entire band-width. This second stage is realized by employing M2 in a shunt-feedback configuration. One drawback of this feedback is that the degradation of forward gain at high frequencies causes a positive feedback through Rf, thus leading to oscillation at the output. To alleviate this problem, Lf is connected in series with the shunt resistor, Rf. This will reduce the feedback at high frequencies and also improve the gain flatness. Ldi and Lj2 are inductive loads to compensate the gain degradation at high frequencies. Chapter 2 - Background 31 -d1 V, biasl - M, ' bias2 ^ 2 ^ Figure 2.13 Two stage wideband LNA for UWB applications In [27], a UWB LNA is successfully designed and simulated using this two-stage architecture. The aforementioned trade-offs among power, bandwidth, and gain are a serious drawback of any feedback system. For illustration purposes, consider the conceptual schematic of a shunt feedback amplifier as shown in Fig 2.14. The input impedance is given by Zin(s)=Rs/(l +sRsCjn),where i?/and A are chosen in a way that Rf/(1+A)=RS. In order to achieve input matching at 10GHz, i.e., |r|<-10dB, the input capacitance (C,„) is limited to as low as 200fF [28]. This limits the width of the input transistor and hence the maximum gain of this stage. To overcome this problem, most of the feedback amplifiers must include a second stage to boost the gain. Two stages of gain directly translate into higher power consumption, which is not a desirable outcome. Chapter 2 - Background 32 V \ A A V, v. out Figure 2.14 Simplified block diagram of a shunt-feedback LNA Thermal-noise-cancelled Wideband L N A Feedback amplifiers, as discussed earlier, typically require two stages of amplification in order to provide sufficient gain and thus dissipate a large amount of power. Also note that the input impedance in a feedback amplifier is a function of the amplifier gain. However, this dependency is not straightforward, and the impedance matching is susceptible to the variations of the gain. To overcome these shortcomings, [29] suggests the use of a noise-cancelling feed-forward technique that decouples noise and input matching requirements. The conceptual schematic of this LNA is shown in Fig. 2.15. The noise current of the amplifier, Inj flows out of the MOS device and passes through R and Rs. Therefore, the instant noise voltages at nodes X and Y have the same polarity. Conversely, the signals at X and Y are of opposite polarities, simply due to the negative gain of the amplifier. This difference between the sign of signal and noise suggest the possibility of cancelling the noise while boosting the signal up. C h a p t e r 2 - B a c k g r o u n d 33 N o d e Y Figure 2.15 Schematic of thermal noise cancelling technique T o d o s o , a n o t h e r g a i n s tage i s i n s e r t e d b e t w e e n the first s tage a n d t h e o u t p u t . T h e v o l t a g e at n o d e Y ( s i g n a l p l u s n o i s e ) i s a d d e d w i t h the p r o p e r l y s c a l e d n e g a t i v e r e p l i c a o f t h e v o l t a g e at n o d e X (the b l o c k s h o w n b y -Av g e n e r a t e t h i s r e p l i c a ) [ 3 0 ] . B y the p r o p e r c h o i c e o f Av, the n o i s e c o n t r i b u t i o n o f t h e M O S d e v i c e b e c o m e s e q u a l to z e r o , a n d a l o w NF c a n b e o b t a i n e d o v e r a w i d e r a n g e o f f r e q u e n c y . T h e a n a l y s i s i n [30] d e r i v e s t h e a p p r o p r i a t e v a l u e o f Av i n t e r m s o f c i r c u i t e l e m e n t s R a n d Rs: (2.36) Chapter 2 - Background 34 It is also shown that, under these conditions, the noise contribution of different components is as follows: NFLNA = 1 + EFM0S + EFR + EFA FF = 0 EFR=^- (2.37) R R where the excess noise factor, EF, is used to quantify the contribution of different noise sources to the NFLNA- Also note that the impedance of the L N A equals l/gmi. Since the term gm! is not present in the NFLNA expressions, NF optimization and input matching can be done separately. The idea of noise cancellation can be extended to any type of amplifier that has 1) a stage of impedance matching, 2) an auxiliary amplifier for sensing the voltage across a real input source, and 3) a circuit to combine the output of two amplifiers to cancel out the noise of the impedance matching stage. Some implementations of this idea are proposed in the same paper. Despite all these benefits, the dominant pole at the input (node X) may limit the bandwidth at high frequencies. Furthermore, due to the existence of the parasitic capacitances, NF increases quadratically with the frequency. These effects, along with the high power consumption required by the two amplifiers, may limit the applications of this architecture. Balanced Amplifier A typical block diagram of a balanced amplifier is shown in Fig. 2.16 [24][31]. It consists of two amplifiers in parallel and two 3dB Lange or hybrid couplers. The basic operation is as follows: Chapter 2 - Background —i 35 90° Hybrid coupler Figure 2.16 Block diagram of balanced amplifier The input signal is split into two quadrature components (equal but with a 90° phase shift) by the input hybrid coupler. The two quadrature signals are then amplified using two identical LNAs. The output coupler combines the output signals of the two amplifiers by introducing an additional 90° phase shift, thus bringing them in phase again [25]. Denoting the S parameters of two amplifiers by S;JA and SyB, one can relate the S parameters of the entire amplifier to that of individual branches as follows: l s M | = ^ - V | 1^ 211 - 2 |^2/ +^21B j (2.38) : — _ 9 A j- c k • 121 - 2 12 U12 Irr I ^ I O ^ C ^ r 22|— "2~P22 22 The advantage of this architecture is that it possesses a very good matching at the input and output ports and continues to operate even if one of the amplifiers fails to function. However, this architecture suffers from the increased power consumption of two amplifiers, increased circuit size, and the bandwidth reduction caused by the couplers. Chapter 2 - Background 36 Drain Term. L_nnn_ RFC L/2 _nnpL Drain Line Gate Line _nrn_ L/2 L _nnn_ ^7 L L JTSTL jnnpL L L/2 _nnpL Load ^7 L/2 Gate Term. Figure 2.17 Schematic of a basic distributed amplifier Distributed Amplifier Distributed amplifiers (DA) (also known as travelling wave amplifiers) employ an architecture in which several active devices are connected in parallel [32]. A basic distributed amplifier is shown in Fig. 2.17. The output current of individual amplifiers combine in an additive fashion, and this dictates a relatively low gain for this architecture. The advantage of this architecture comes from the fact that the input capacitances of these amplifiers are distributed in an LC network which allows for the realization of amplifiers with large bandwidths. In fact, the series inductive elements and capacitances of MOS devices form an artificial transmission line, which allows the flow of the signal to the end of the gate line. The signal fed to the gate of the MOS device is transferred to the drain line through the trans-conductance (gm) of the device. If the phase velocity on the gate and drain lines are identical, then the signals at the output add in the forward direction as they arrive at the output. Many wideband LNAs in CMOS have been Chapter 2 - Background 37 realized using D A architectures [33][34]. However, the large power consumption of this architecture is a major drawback and makes it unsuitable for low-power portable systems. These architectures are the most well-known works in the literature of wideband L N A design. Although successfully implemented for some applications, there are still many issues that need to be addressed when it comes to the design of highly integrated LNAs. For instance, the large power consumption of most of these architectures is a major problem, which may eliminate the feasibility of their integration for low-power multi-standard applications. Moreover, a well-established methodology is needed to provide the general guidelines for the design of wideband and multi-standard LNAs. Chapter 3 - Wideband L N A Methodology 38 CHAPTER 3 WIDEBAND L N A METHODOLOGY As discussed in chapter two, the inductively degenerated L N A (L-deg L N A for short) satisfies the input matching requirement without introducing the additional noise attributed to a real resistor. In addition, compared to other architectures, L-deg LNAs consume less power and therefore are especially suitable for low-power applications. The design of L-deg L N A involves many trade-offs among gain, NF, power consumption, matching, and linearity. Several design techniques have been proposed to satisfy these requirements for different applications. The classical noise matching (CNM) technique [35], simultaneous noise and input matching (SNIM) technique [36], power constrained noise optimization (PCNO) technique [16], and power-constrained simultaneous noise and input matching (PCSNIM) technique [37][38] are among the many design procedures developed for this architecture. A l l these design techniques have been developed based on the assumption of narrowband input signal; i.e., the bandwidth of the input signal to be amplified is much smaller than the centre frequency. However, low power consumption and the low NF capabilities of L-deg LNAs have motivated us to develop a new methodology for broadband applications. To study the requirements of wideband noise and input matching and establish a well-defined design approach, a careful analysis of this architecture is presented in the following sections. Also, the principles of operation and the role of different parameters on the performance of the wideband L-deg L N A are discussed in detail. Chapter 3 - Wideband L N A Methodology 39 3 .1 Power gain and Impedance mismatch factor It is a well-known fact that the power delivered from a power source to a load reaches its maximum value if the source impedance is the complex conjugate of the load impedance. Consider the basic block diagram of an amplifier shown in Fig. 3.1. Figure 3.1 Conceptual diagram of power transfer in an amplifier The current and power delivered to the system, /,„ and Pin, are: V. P,. = Z.+Z, R, (3.1) " Z s + Z i n " 21 When Zi„ = Z* (Rm = Rs, Xin = -Xs) or, in terms of reflection coefficient rin = rs", the maximum available power, denoted by PA, is transferred to the load: P -P A 1 in p. =r 1 2 AR. (3.2) However, in general, when Z,„ ^  Zs , the input power to the system may be written as: Z„ +Z,„ R:» =• 4 ^ , i N2 _ Z . + Z , 2 -IMF 2 4 ^ PA IMFxP, (3.3) where IMF is the impedance mismatch factor (7MF)[39][40]. Chapter 3 - Wideband L N A Methodology 40 I M F = ^ z +Z, IMF< = - ^ ZT+Zh Z s a A A A r - f -Matching network Amplifier Reference plane A Reference plane B Figure 3.2 Input mismatch factor with matching network Recall from (2.24) that VSWR is a measure of the impedance matching at the input port of the L N A . IMF is another way of expressing the quality of matching and is related to VSWR through the following relation VSWR 1 + Vl -ZMF l-y/l-IMF (3.4) IMF also determines how much power is absorbed by the input port of the amplifier. For instance, i f IMF =1 then the power delivered to the system is equal to PA and the power gain reaches its maximum value. Now consider Fig. 3.2 where a lossless matching network is inserted between the source and the input port of an amplifier. In this figure Zj is the series impedance of the Thevenin equivalent of the circuit to the left of the amplifier. Note that IMF and IMF' represent the value of the impedance mismatch factor at the two reference planes of A and B, respectively. An analysis of this network, assuming lossless passive elements in the matching network, proves that IMF = IMF' [41]. This is an important observation because it shows that the choice of reference C h a p t e r 3 - W i d e b a n d L N A M e t h o d o l o g y 41 p l a n e h a s n o e f f e c t o n t h e v a l u e o f IMF, a n d h e n c e the p o w e r g a i n . S o , w e c a n c h o o s e a r e f e r e n c e p l a n e that b e s t su i t s o u r a p p l i c a t i o n , e . g . , s i m p l i f i e s the a n a l y s i s . Thevenin Equivalent Matching network (a) (b) Figure 3.3 (a) Narrowband LNA (b) Wideband LNA L e t u s n o w a p p l y t h e s e c o n c e p t s to a n L-deg L N A . C o n s i d e r F i g . 3.3 (a) w h i c h d e p i c t s the i n p u t p o r t o f a t y p i c a l n a r r o w b a n d L N A . T h e o v e r a l l t r a n s - c o n d u c t a n c e o f the a m p l i f i e r , u n d e r the m a t c h i n g r e q u i r e m e n t s , i s g i v e n b y : i i v '"out _ lout gs _ V • V V . m gs in 8n 1 (0, (3.5) w h e r e cotLs=Rs i s the i n p u t i m p e d a n c e at t h e r e s o n a n c e a n d cot=gm/Cgs i s the t rans i t f r e q u e n c y o f the a m p l i f i e r . T h e las t e x p r e s s i o n i m p l i e s that the t r a n s c o n d u c t a n c e o f t h e L N A , at t h e r e s o n a n c e , is i n d e p e n d e n t o f t h e M O S d e v i c e t r a n s c o n d u c t a n c e a n d its w i d t h . T h e r e f o r e , t h e o n l y w a y to b o o s t t h e g a i n o f a matched a m p l i f i e r i s to i n c r e a s e the t rans i t f r e q u e n c y o f the M O S d e v i c e . Chapter 3 - Wideband L N A Methodology 42 Now, consider Fig. 3.3 (b) which shows a wideband L N A and its wideband matching network. For our convenience we move the reference plane to the gate of the MOS device. Under wideband matching conditions, we have ZIN—Z*T over the entire range of frequency. If the matching network is lossless, the power conservation theorem states that: 1 V 2 \ V 2 PA=LLj- = L.Ll- (3.6) A 2 4Rs 2 4Rr Also note that, the current into the gate of the input transistor is given by iin=Vj/(RT+Rin). Using (3.6), the overall transconductance Gm can be written as: g = ^ = i ^ - . ^ = g . 1 . p - = — ( w m vs v g s v T v s *m Cgsco{Rin+RT)\Rs 2co4R~Ts where the last expression assumes Rm=Rr over the entire band of interest. This equation shows that Gm is inversely proportional to the frequency of operation. Therefore, i f one can compensate the 1/co term in Gm with an appropriate load at the output, constant gain will be obtained over the wide band of interest. This compensation can be accomplished by employing an inductive load at the output of the L N A . More discussion on how to design the output load will follow shortly. The foregoing discussion suggests that i f we achieve input matching at the gate of the MOS device, i.e., the new reference plane, then it is possible to achieve a constant gain over a wide frequency range. To achieve this goal and also maximize the power gain, IMF should be as close to one as possible over the entire band of interest. C h a p t e r 3 - W i d e b a n d L N A M e t h o d o l o g y 4 3 Reference Plane i—vAAA Input matching network Unilateral Amplifier (S12=0) Output matching network r o u t " S 2 2 Figure 3.4 block diagram of a unilateral amplifier with port matching T o i n c l u d e t h e e f f e c t o f IMF o n t h e p o w e r g a i n o f the L N A , c o n s i d e r F i g 3 .4 , w h i c h s h o w s a u n i l a t e r a l 1 a m p l i f i e r a n d i ts i n p u t a n d o u t p u t m a t c h i n g n e t w o r k s . It c a n b e s h o w n that t h e to ta l u n i l a t e r a l p o w e r g a i n ( f r o m s o u r c e to l o a d ) i s g i v e n b y [24] : i 5 ' 2 2 r i (3.8) w h e r e 5,y are t h e S p a r a m e t e r s o f t h e a m p l i f i e r a n d rs a n d Fi a re the s o u r c e a n d l o a d r e f l e c t i o n c o e f f i c i e n t s , r e s p e c t i v e l y . T h i s e q u a t i o n i s i n t e r m s o f r e f l e c t i o n c o e f f i c i e n t s a n d s h o u l d b e r e -e x p r e s s e d i n t e r m s o f i m p e d a n c e s to e x p l i c i t l y r e f l e c t the e f f e c t o f IMF. N o t e that the m a x i m u m p o w e r g a i n r e s u l t s w h e n b o t h t h e i n p u t a n d o u t p u t p o r t s a re m a t c h e d ( i .e . , rs -S*n a n d FL = S 22): max 2 T 2 1 | • 2 1 O,j 1 d22 (3.9) Unilateral amplifiers possess zero reverse power gain (Si2= 0) and are more flexible to design. There are several techniques to make an ordinary amplifier unilateral, one of which is the use of cascade architecture. In the following sections, we will further investigate the properties of this architecture. Chapter 3 - Wideband LNA Methodology 44 Reference Plane Figure 3.5 Small signal model of an inductively degenerated L N A Now, if there is an impedance mismatch at the input port of the LNA, the available power gain of the LNA can be written as the product of the maximal power and IMF: 4R.R,. „ (zin+zs)2 (3.10) IMF where Zin are Z$ are the input and source impedances at the reference plane shown in Fig. 3.4. This last expression incorporates the effect of input port on the gain of the LNA and is extensively used in the development of the proposed LNA design technique 3.2 Wideband noise and input matching2 The generic small-signal model of an inductively-degenerated CMOS LNA is shown in Fig. 3.5. This model is used to study the different parameters affecting the design and performance of LNA. 2 All the calculations and impedances in this section are based on the small signal model and the reference plane shown in Fig. 3.5 Chapter 3 - Wideband L N A Methodology 45 In this model / „d and / „ g are dominant sources of noise and their respective power densities are given in (2.4) and (2.6). Recall from chapter two that the NF of a two-port network is given by: NFLNA = NFmin +|H(G S -Goptf +(BS -Bopl)2] (3.11) This expression shows the dependency of NF on the admittance of the source seen from the gate of the transistor. To make this expression compatible with that of the gain formula in (3.10), it is convenient to re-express (3.11) in terms of source impedance rather than source admittance. The new expression for NFLNA is as follows: NFLNA = NFmin +—£*—[(Rt -Ropl?HXs -Xopl)2] (3.12) Rs \Zop, I where X o p t and R o p t are the optimum source reactance and the optimum source resistance, and \Zopt\2is the magnitude of the optimum impedance. Analytic expressions for Yopt(ox Zopt)3, NFmin, and Rn can directly be calculated by applying K V L / K C L to the circuit shown in Fig. 3.5. Calculations are tedious and are presented in Appendix B. The results of these calculations are summarized below: & m NF„:„ «1 + min 2 co 7 5 cot a Re{Z o p ,} = S(l-\c\2) 5y °P< ' 2 cvi i |2 \ c-„ ra 0(1- c ) /1 I I $ 2^^  aCgs[ J+(l + a\c\ — )2] (3.15) 3 Throughout this section we interchangeably use R e { Z o p t } for Ropt and Re{Z f a } for Ri„ Chapter 3 - Wideband LNA Methodology 46 lm{Zopt} = -coLs+-coC a2S(l- c ) 5y • + ( l + a | c | J ^ ) 2 (3.16) As it is evident from (3.13) and (3.14), the expressions for 7?„ and NFMIN are approximately equal to that of a MOS device without the degeneration inductance. This is due to the fact that a lossless inductor does not introduce additional noise to the circuit. Also, we need to find the input impedance at the gate of the transistor in order to calculate the power gain expression in (3.10). The input impedance at the gate plane, ignoring the losses of inductors, is given by Re{Z,,} = ^  = «,Z„ C 1 0)C (3.17) (3.18) Now that GLNA and NFLNA expressions are related to the design parameters of the LNA, we can study the requirement of simultaneous noise and input matching for the L-deg LNA. To obtain the wideband noise and input matching, the source impedance seen from the gate of the input transistor (Zs shown in Fig. 3 .5) should be the complex conjugate of the input impedance, Z,„ (to deliver the maximum power) and at the same time be equal to Zopt (to achieve NFmin). Thus the following four conditions should hold over the entire frequency band of interest: Re{Z^} = Re{Z,} I m { Z „ } = Im{Z1} Rfi{Zh} = Re{Z,} Im{Z,„} = -M z , } (3.19) Combining the above criteria, simultaneous noise and input matching are achieved when: Chapter 3 - Wideband L N A Methodology 47 opt (3.20) To satisfy this equation we should analyze the real and imaginary parts of the two impedances Z,„ and Zopt. As can be seen from (3.16), lm{Zopt} is of the form of -a)Ls+K/(coCgs) which is the negative of Im{Z,„}in (3.18), i f K=l. K=f(a, y, S) is a technology-dependant parameter, and its value approaches 1 as the MOS devices scale down to smaller dimensions (K&0.7 for 0.25um and K&O.S for 0.18um technology). Furthermore, at high frequencies, the inductive terms in both expressions become dominant and the effect of the capacitive terms in (3.16) and (3.18) fade away, further improving the matching [42]. On the other hand, the matching of Re{Zopl} and Re{Zin} in a wide frequency range is very challenging. This is due to the fact that the former is frequency-dependant while the latter is constant and bias-dependant (proportional to the cut-off frequency, cot). However, Re{Zin} is also a function of Ls and by the proper choice of this inductance we can optimize the circuit for wideband operation. Before proceeding, note that Re{Zopt} is in the form of m/(a>CgS), where m=f(a, y, 5) is again a technology-dependant parameter. The expression for Cgs of a MOS device in the saturation region is [43]: So once we choose the width of the input transistor based on the power budget and the NF requirements (to be discussed in section 3.4), Re{Zopt} is only a function of the frequency. The frequency range of the L N A (e.g., 3-5GHz for UWB applications) sets the valid range of Re{Zopt} over which the optimization should be carried out. To explain the details of this 3 OX (3.21) Chapter 3 - Wideband L N A Methodology 48 optimization, we rewrite GLNA and NFLNA equations when there is a mismatch among Re{Zopl}, Re{Zs}, and Re{Z,„}as follows:4 AR R n = — s — G (3 22) NFLNA =NFMIN + R" (Rs -Roptf (3.23) Rs \Zopt I where Rs is the real part of the source impedance and should be a compromise between Rin and Ropt. As it is evident from (3.22) and (3.23) GLNA and NFLNA are functions of Rin and Ropt.5 The idea behind this optimization is to find a value of Rin, i.e., Ls, for which we can satisfy both requirements of NF < NFMAX and G > GMIN where NFMAX and G„i„ are the maximum tolerable NF and the minimum acceptable G of the L N A . Note that the term Rs is present in both GLNA and NFLNA expressions. However, the design of the matching network that generates Rs, must be done after we satisfy the conditions for the wideband matching. Therefore, different assumptions about the value of Rs can be made at the early stages of the design. Since the value of Rs varies between Rin and Ropt, one pessimistic assumption is to assume Rs = Ropt for the GLNA expression and Rs=Rm for the NFLNA expression. Designing the L N A in this way guarantees that we will still meet the requirement of simultaneously high GLNA arid low NFLNA, even in the presence of some impedance mismatch at the input port. Using this assumption, the graphs of GLNA and NFLNA are plotted vs. Rin and Roph as shown in Figs. 3.6 and 3.7 4 These expressions assume Im{Z,}=Im{Zop,}= -Im{Z,„}. 5 This statement assumes that \Zopl\2= D Ropr2 where D is a constant. This assumption will be justified later in this chapter. Chapter 3 - Wideband L N A Methodology 4 9 Figure 3.6 NF of LNA vs. Re{Zin} and Re{Zopt} for UWB applications in 3-5GHz for input transistor width of 75pm Figure 3.7 Gain of LNA vs. Re{Zi„} and Re{Zopt} for UWB applications in 3-5GHz for input transistor width of 75pm Chapter 3 - Wideband LNA Methodology 50 18.5 18 17.5 ST 17 T O . c 'TO O 16.5 16 15.5 15 14.! Re(Z j n) = 60 ohms R e ( Z J = 78 ohms R e ( Z J = 96 ohms 60 70 80 R e ( Z o p t ) (ohms) 90 100 110 Figure 3.8 Gain of LNA vs. Re{Zopt} (co) for several values oiRe{Zm} (Ls) 2.8 2.6 2.4 2.2 S - 2 LL. z 1.8 1.6 1.4 1.2 1 0 — Re(Z i n) = 60 ohms « Re(Z i n) = 78 ohms ... R e ( Z J = 96 ohms 60 70 80 R e ( Z o p ( ) (ohms) 90 100 110 Figure 3.9 NF of LNA vs. Re{ZopJ (a>) for several values of Re{Zin} (Ls) Chapter 3 - Wideband LNA Methodology 51 In order to perform the optimization we should examine the vertical slices of both graphs of GLNA and NFLNA- Each of these slices correspond to a different value of LS (i.e., Re{Zin}). The graphs of NFLNA and GLNA for several values of LS are shown in Figs. 3.8 and 3.9. It can be seen that the best NFLNA and GLNA are obtained for Re{Zin}~ 78Q6. r To verify the results of our calculations, we also simulated the circuit using Agilent advanced design systems (ADS). The results of this simulation show an optimum value of around 75Q for Re{Zin} and are illustrated in Fig. 3.10. 100-E Re{Z. } r inJ Re{Zopt} i i i i i i i i i i i i i i i i i i i i in i i i i i i "i—i—i—i—i—r 2.5 3.0 " i — | — i — i — r 3.5 4.0 4.5 freq, GHz Figure 3.10 Graphs of Re{Zj„} and Re{Zo p t} vs. frequency for UWB applications in 3-5GHz (W=75pm) 6 Now we can justify our assumption in footnote 5: For the optimum value of the degeneration inductance we have Rm~Ropt(o), or in terms of circuit parameters co,Ls~m/ wCgs, where w varies over the frequency band of interest. On the other hand, Xopl(a>)=k/ a>Cgs- coLs. Note that 1) coLs «co,L5=m/ u>Cgs and 2) k and m are comparable values. Therefore wLs« kJ coCgs and we may write Xop,(w)~ kf coCgs. So, Xopl=nRop, where n=k/m and is a constant. Therefore | Z 0 p, | 2 =R o p , 2 + X o p t 2 = (1+n2) R o p t 2 = D . R o p t 2 where D is a constant. Chapter 3 - Wideband L N A Methodology 52 As Fig. 3.10 shows Re{Zin} is not quite a constant value and varies slightly over the band of interest. This is mainly due to the parasitic capacitances of MOS devices (e.g., Csb) which become non-negligible at very high frequencies. Therefore, calculations based on the simplified small-signal model of Fig. 3.5 give an estimate of the optimum values and are not exact. Consequently, advanced CAD tools with accurate models should be used to design the circuit for wideband performance. 3 . 3 S N R - b a s e d O p t i m i z a t i o n T e c h n i q u e So far our objective was to optimize the L N A over a wide bandwidth based on the assumption that the L N A is a stand-alone block with certain requirements (NFLNA<NFmax and GLNA>Gmin). However, in a more realistic scenario where the L N A is followed by the rest of the receive chain; a better approach is to include the effects of the following blocks and optimize the performance of the overall system rather than the L N A as a single block. Previous work in the design of L N A attempted to include the trade-off between the .minimum NF and maximum gain by introducing the concept of noise measure (NM) [44] and optimizing its value at the frequency range of operation: This formula is obtained by considering the definition of NF for a cascade of an infinite number of identical L N A stages, that is: NM = NF-l (3.24) 1-1/G NFtot=NF + NF-l NF-l + T~ G G + ... (3.25) Chapter 3 - Wideband L N A Methodology 53 where G is the available power gain of each L N A stage. Yet, this definition does not properly reflect the effect of following stages in a realistic RF front-end where L N A is usually followed by a mixer and not an identical L N A . Equivalent Block with NF eq Figure 3.11 Equivalent model of RF front end To include these effects, consider the system of Fig 3.11, in which L N A is taken out of the receiver chain and the rest of the system is treated as a single block with an equivalent NF, NFeq. The expression for the SNR at the output of the receiver is given by: SNR,. „„„ SNR,. NF, SNR, SNRnil = — NF +NF IG I V 1 LNA T J V - < eq ' VJLNA (3.26) where NFLNA and GLNA are the NF and available power gain of the L N A , respectively. In order to obtain the best SNR0Ut, this expression should be optimized using the equations for G L N A and N F L N A in (3.22) and (3.23). After this substituting we observe that SNRout is an explicit function of the source resistance, Rs. The value of Rs that maximizes the SNRout expression can be found by taking the first derivative of SNR0Ut with respect to Rs: dSNR„ dR, 0 (3.27) Chapter 3 - Wideband L N A Methodology 54 After some algebraic manipulations we have: R 4(NFN -1) Z„„, R3. + 1 6 G R 2INRNR2 v eq J opt in max in n < opt (3.28) \ 4{NFEQ-l)\ZOPL\2RIN +l6GMAXR2INRN As can be seen, the optimum source resistance (Rs,opt) is a function of input resistance, RIN, and the optimum resistance, ROPT. Also note that GMAX and RN expressions are provided in (3.9) and (3.13), respectively. A few interesting observation can be made from the RSI0PT expression in (3.28). First, assume that NFEQ is considerably high, i.e., NFEQ-^ co, then (3.28) reduces to Rs<opt ~ Rm- This result can be interpreted in the following way: when the noise of blocks following the L N A is very high, the dominant term in the denominator of (3.26) is the term NFEQIGLNA, and therefore GLNA should be very large to suppress the contribution of NFEQ. Therefore, in the trade-off between RIN and ROPT, Rs,opt should be equal to RIN to maximize the gain. As the second special case, assume that NFEQ is very small, i.e., NFEQ-^\, then we obtain RSI0PT ~ ROPT. This result is also intuitively satisfying, for NFLNA is now the dominant term in SNR0UT expression and hence RS should be equal to ROPT over the entire band to minimize NFLNA (maximize SNROUL). Another important situation occurs in narrow-band applications where it is possible to match ROPT and RIN at a certain frequency. Therefore we obtain RS=ROPT=RIN from (3.28), which is the same criteria used in classic narrowband design techniques. For narrowband applications this requirement can be satisfied by a proper choice of LS that guarantees RIN =ROPT at the frequency of operation. To complete the design, an appropriatematching network should then be inserted before the amplifier to produce RS=ROPT at the single frequency of operation. Chapter 3 - Wideband L N A Methodology 5 5 In wideband applications, we can use the expression in (3.26) to plot SNR0Ut vs. Re{Zin} and Re{Zopt} (Fig. 3.12) and then find an appropriate value of Re{Zin}_ which results in the best overall SNR0U, over the entire frequency band of interest. Figure 3.12 SNR™, vs. Re{Z i n} and Re{Z o p t} for UWB applications in 3 -5GHz (NF e q=20dB, W=75pm and G m a x =20dB) This last task can be accomplished by examining the vertical slices of SNR0Ut vs. Re{Zop,} (or frequency) and choose the one that results in the best overall SNR0Ut7 The Ls corresponding to this particular slice is the optimum value of the source degeneration inductance. Graphs of SNRout vs. Re{Zoplj for different values of Re{Zin} are shown in Fig. 3.13. One measure for the best overall SNR0U, is the average value of SNR0U, taken over the entire bandwidth. Chapter 3 - Wideband L N A Methodology 56 Re(Zin) = 60 ohms Re(ZJ = 78 ohms Re(ZJ = 96 ohms AA\ . 1 1 1 1 1 1 50 60 70 80 90 100 110 R e ( Z o p ( ) (ohms) Figure 3.13 SNR of LNA vs. Re{Zopt} (w) for several values of Re{Zin} (Ls) Thus far we have studied the effect ofNFeq variations on the value ofRs,opt. We observed that RS:0pt takes different values over the entire bandwidth to balance the effect of NFeq and NFLNA on the SNRout. Now, we should study how NFeq variations may affect the optimum value of Ls obtained from the graphs of Fig. 3.12 and Fig. 3.13. For this purpose SNR0Ut is plotted vs. Re{Zopt} and Re{Zin} for different values of NFeq and the optimum Ls, i.e., Ri„,opt is found for each of the SNR0U, plots (by examining different slices of SNRout for each of these plots). The graph of Fig. 3.14 depicts the variations of Ri„,opl vs. NFeq for our UWB example. As can be seen from this figure, for large variations of NFeq (from 0 to 40dB) Rin.op, varies in a very small range (from 79Q to 73Q.). This is an interesting observation because it reflects the fact that the optimum value of Rin is almost independent of NFeq variations. Also note that the Ri„,opt obtained in this analysis Chapter 3 - Wideband L N A Methodology 57 (73D. -79Q) is approximately equal to that of the standalone L N A analysis in the previous section (i?(„=75Q). 79 Figure 3.14 Optimum value of Re{Zj„} (Ls) for variations of NF e q To summarize, we can use either the stand-alone or the SNR-based design technique to find the optimum value of Ls (/?,„). After finding the appropriate value of we must design a matching network to produce the required RSy0pl over the entire band of interest; see (3.25). However, for most practical purposes, it may not be possible to design such a matching network that tracks the value of Rs,opt with the variations of the frequency. Therefore, we may alternatively match Rs to either Rin or Ropt, i.e., satisfying GLNA and NFLNA requirements for the stand-alone analysis. Chapter 3 - Wideband L N A Methodology 58 3.4 Proposed Design Technique Thus far, we have studied the requirements for wideband noise and input matching from both circuit and system level perspectives. Now we can develop a design technique based on the analysis we performed in the last section. The design parameters of L-deg L N A are the overdrive voltage of the input transistor, V o v , the width of the input transistor, W, and the source degeneration inductance, L s . By appropriately choosing these parameters, we should satisfy the requirements of low power consumption, low NF, and simultaneous noise and input matching at the input port. The conditions needed to satisfy the wideband noise and input matching is discussed in detail in Section 3.3. In this section, we study the NF and power requirements from a circuit-level perspective and find their corresponding expressions in terms of circuit parameters. Using the expression for the drain current of a MOS device the power dissipation of an L-deg L N A can be written as [ 12]: LL C W PD = VDDID = ^ j ( V S s ~ K)Wgs -Vt)\\LESJ] (3.29) where pin is the mobility of electrons, Esaf is the velocity saturated electric field, and Vt is the threshold voltage of transistor. After slight simplifications, (3.29) can be rewritten as: PD=VDDWLCoxosatEsat-^- (3.30) \ + p where vsat=ju„Esa/2 is the saturation velocity and p is called the normalized overdrive voltage and is given by: 8 Esat is the field strength at which the carrier velocity has dropped to half the value extrapolated from low-field mobilities. Chapter 3 - Wideband L N A Methodology 59 P = V -V gs t (3.31) As evident from (3.30), the total power consumption is a function of W and Vov. Fig. 3.15 shows the contour plot of power consumption in the design space of W and Vov. The requirement for certain power consumption for the L N A , e.g. lOmW, limits our design space to one portion of the W-Vov plane. Now, remember the equation of NFLNA from (3.9): NFLNA =NFmin + ^ [(GS -Goptf +(B,-Boptf] To achieve low values of NFLNA we should guarantee 1) N F M I N is a small value and 2) R N is as small as possible to suppress any deviations from optimum conditions, i.e., Y S = Y O P T . To satisfy these two conditions let us study the two expressions again: V5 <ot R , (3.32) (3.33) To minimize the NFmin in (3.32) transit frequency, cot, should be much higher than the operating frequency, co. Recall from chapter two that the expression for cot is gm/Cgs, where gm is the transconductance of the device and can easily be found by differentiating ID with respect to Vov: _ dID _ l + p/2 (1 + A) 2 W M„C0Xj-(Fgs-V,) ag dO (3.34) Chapter 3 - Wideband L N A Methodology 60 E 2 0 0 h 180 160 0 140 tn 1 1201 Q. ™ 1001 o § 80 60 40 \ \ \ \ \ % - V \ X X \ ^ \ \ \ X \ x;%>C \ \ \ \ \ \ \ < C s H ^. X \ % \ \ \ v . . . \ *" 3 Q(r) lV 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 V Q v (volts) Figure 3.15 Contour plots of total power consumption The substitution of Cgs and gm from (3.20) and (3.30) yields the following expression for the transit frequency: ~E2L+E V„. 12 co. g o m sat sat ov (LEsat+V0V) MnV0V ' C. 2L (3.35) Therefore, cot is only a function of Vov, and the graph of this dependency is shown in Fig. 3.17. Using this graph we can find a V0Vimin such that for Vov> Vovm„ we satisfy cot» co in the frequency range of operation, e.g. Fov>200mV is sufficient for UWB applications . Rn, as seen from (3.33), is a function of actual transconductance (gm) and zero drain-source voltage transconductance (gdo)- Note that the relation between gm and gdo is earlier defined in (3.34). Chapter 3 - Wideband L N A Methodology 61 80 V o v (volts) Figure 3.16 Transit frequency ( / J ) vs. overdrive voltage By substituting gm and gdo in (3.33), we find that Rn is also a function of width (W) and overdrive voltage (Vov). Fig 3.17 shows the contour curves of R„ vs. ^and Vov. For small values of Vov both the gm and gao increase linearly with Vov and hence, Rn decreases rapidly. As Vov further increases, the velocity saturation phenomenon occurs and gm becomes almost constant. However, gdo keeps increasing in a linear fashion, and this causes Rn to roll up after a certain value of Vov. Therefore, for a fixed device width, there exists an optimum Vov for which Rn is the minimum (Fig. 3.17). Now the steps of the proposed power constrained wideband simultaneous noise and input matching design technique, in short PCWSNIM, can be explained as follows: • The contours of power consumption and equivalent noise resistance (Rn) are plotted in the design space of W and Vov. Parameters W and Vov are chosen in a way that the pair (Vov, W) meets the power consumption requirement and minimizes the R„. Chapter 3 - Wideband L N A Methodology 62 • Once Vov and Wave chosen, Re{Zopt} is only a function of frequency; see (3.15). So, we can plot NF^A and GLNA V S . Re{Zin} and Re{Zopt} and find the optimum value of Re{Z;n}, and the corresponding LS, that achieves the best NFLNA and GLNA over the frequency range of interest. • A suitable matching network should be designed to satisfy the input matching over the entire band of interest. o u5 in TO "3 CL _C o T3 200 180 160 140 120 100 80I 39Q 67Q V v 39a — 53a " 67Q 810 .... 1,90. 53fi -gin ] 94Q iosn - mo. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 V o v (volts) Figure 3.17 Contour plots of equivalent noise resistance (R„) The last task should be accomplished using lossless passive elements (capacitors and inductors). A number of architectures can be used to generate the required wideband impedance matching network, some of which will be introduced in section 3.5. Chapter 3 - Wideband L N A Methodology 63 Additional considerations To complete the discussion, we now study the existing trade-offs among different requirements and how they may affect the proposed PCWSNIM design technique. Assume we decrease our power budget and want to study the feasibility of designing a ultra low-power wideband L N A . A low-power budget translates directly into small values of transistor width. This is because a low-power budget limits the location of the point (W,V0V) to a very small portion of W-Vov design space. Since the requirement of Vov> Vov>min from the previous section, the value of W has to decrease in proportion to the power budget. Recall from equation (3.15) that Re{Zopt}=m/coCgs and note that 1/Cgs acts as a multiplier in this expression and amplifies the variations of Re{Zopt} over a wide frequency range. Therefore, a small value of transistor width, i.e., small Cgs, results in large variations of Re{Zopt}. Since \Re{Zopt}-Re{Zi„}\ is a measure of simultaneous matching over the entire band, the large variations ofRe{Zopt} deteriorates the wideband noise and input matching. Furthermore, we know that Re{Zin} approximates Re{Zopt} to satisfy the simultaneous noise and input matching over the frequency band of interest. Therefore, large values of Re{Zopt} also require a large Re{Zin} to meet this requirement. However, recall from (3.7) that the overall transconductance and hence the overall gain is inversely proportional to Re{Zin}(Rin). Consequently, a small power budget may result in a severe reduction of the power gain which is not desirable. Considering the foregoing discussion, we can modify the proposed wideband L N A design technique as follows. Start the design with a limited power budget and find the appropriate values of Vov, W, and Ls. If the circuit fails to satisfy the noise and gain requirements Chapter 3 - Wideband L N A Methodology 64 over the entire bandwidth after the insertion of the matching network, return to step one, increase the power budget and repeat the subsequent steps. 3.5 W i d e b a n d I m p e d a n c e M a t c h i n g N e t w o r k s As pointed out in previous sections, to achieve the maximum power transfer and minimum NF, we need to insert a matching network before the input port of the transistor. There exist many techniques to design the matching network for narrowband applications. Most of these approaches rely on Smith chart as a graphical tool. Smith chart highly simplifies the complicated calculations needed for the synthesis of the matching network. Smith chart gives an initial solution to our problem and can be made more precise through the use of some advanced C A D tools. The applications of the abovementioned narrowband techniques can be extended to broadband amplifiers through the use of the so-called nodal quality factor, Q„, technique [24]. This technique is based on the observation that the total impedance at each node of matching network can be expressed either as an equivalent series impedance or parallel admittance. Therefore we can assign a quality factor to each node of circuit defined as the ratio of absolute value of reactance \XS\ to that of resistance Rs at that particular node: Q or equivalently Q For narrowband applications, there is an exact relation between the nodal quality factor and the bandwidth of the matching network. However, for broadband applications where the network configuration is usually more complicated, Q„ only gives an estimation of the network \BB (3.36) (3.37) Chapter 3 - Wideband L N A Methodology 65 bandwidth. As a rule of thumb, the maximum value of nodal quality factor is usually considered as the actual quality factor of the network. The three-element matching network is the simplest network that allows us to achieve impedance matching over a wide frequency range. Two variants of three element matching network are illustrated in Fig. 3.18. \J*2 jx, JX, jx, Z=R+jX Y=G+jB o=B-=E. ^n R G Z=R+jX Y=G+jB o=B.=E-^n R G (a) (b) Figure 3.18 (a) n matching network (b) T matching network Note that when we use these networks in our L N A design, Z/ represents the impedance seen at the gate of the input transistor looking into the transistor (denoted by Z,„ in the previous section) and jXjS and jBjS are the reactances and susceptances of the matching network elements, respectively. Since the nodal Q is considered as the quality factor of this filter, the bandwidth of input network becomes approximately: BW (3.38) Therefore, for broadband applications we should use networks with very low values of Q„. Fig.3.19 shows the contours of constant Q„ in the smith chart. Chapter 3 - Wideband L N A Methodology 66 Figure 3.19 Contours of constant Qn displayed in the smith chart The details of matching network design using smith chart are provided in [24]. Here, we introduce an alternative approach to the design of it matching network and study its broadband nature. Consider the schematic of Fig. 3.20 (a) where a % matching network is inserted between the source and the input of a MOS device. Fig. 3.20 (b) shows the high frequency model of the same circuit used for matching purposes. Recall from section 3.1, that IMF is the same for different reference planes, assuming the matching network is lossless. Therefore, we choose the reference plane to be in the middle of the network, as shown in Fig. 3.20 (b). The impedance looking to the left of the reference plane is given by: R R-"co2Cp%2H\-co2CpLj L,-C(o2L2+R2) , 2 , 2 . (3-39) L =• g l co'Cp%2+(\-co2CpLglY Chapter 3 - Wideband L N A Methodology 67 L91 L9 2 J T F L M. JTTTL V (a) V* 7 g2 s Lnnn-(b) Figure 3.20 (a) it matching network (b) Equivalent circuit To satisfy the matching at this reference plane the following, conditions should hold: R =R =mL, eq in t s L =-L. =-(L +L ,)+ 1 eq in V s z2J gs ' gs ® t L s (3.40) Req , as expressed in (3.39), is not a constant and varies with the frequency. However, there exists a maximum for Req expression at the frequency coj: co, l2Lgl-CpR/ 2CA>2 (3.41) In the vicinity of this maximum frequency, Req is almost constant. So, by proper choice of Lg and Cp we can set the maximum frequency,**)/, and the maximum resistance, Req,max, in a way that Req closely approximates Rin, i.e., cotLs in the frequency band of interest. On the other hand, the equivalent inductance, Leq, should also satisfy the requirement in (3.40) to guarantee wideband matching over the entire band. Leq, as described by (3.39), has a zero at the frequency given by: Chapter 3 - Wideband L N A Methodology 68 OJ2 -L.-CR2 "1 p s i c (3.42) Once the values Cp and Lgi are chosen to ensure Ri„=Req over the band of interest, a>2 will have a fixed value. Now, by proper choice of Lg2, we must attempt to satisfy (3.40). We have performed this analysis for a UWB L N A using Agilent ADS, and the following values for the passive elements are obtained: Zg/=1.68nH, Cp=540fFj and Lg2=5nH. The graphs of Req (Rin) and Leq(Lin) are shown in Figs 3.21 and 3.22. E 95-90-85 80H ! " - R : - I I I 11 I I I ) I II in tl. J> 55—|—i—i—i—i—|—i—i—i—i—|—i—i—i—i—|—i—i—i—i—|—i—i—i—i—j—i—i—i—r 2.5 3.0 3.5 4.0 4.5 5.0 5.5 freq, GHz Figure 3.21 Real parts of impedances Z,„ and Zeq over the UWB band Chapter 3 - Wideband L N A Methodology 69 3.5 4 .0 4 .5 f req, G H z Figure 3.22 Imaginary parts (equivalent inductance) of impedances Zin and Zeq over the UWB band Chapter 4 - Simulation Results and Layout Issues 70 CHAPTER 4 SIMULATION RESULTS AND LAYOUT ISSUES To demonstrate the applications of the proposed design technique, two wideband inductively degenerated LNAs are designed and simulated in a 0.18um CMOS technology. In this chapter we present the design stages of these two LNAs and the corresponding simulation results. The layout of the second L N A has also been drawn and has been sent for fabrication. Issues related to the layout of this L N A will be discussed in the last section. 4.1 Wideband LNA for multi-standard application in 1.5-2.5GHz The first L N A is intended for multi-standard applications in the frequency range of 1.5-2.6GHz. This choice of frequency band covers the bands of GPS (1.575GHz), UMTS (1.9GHz and 2.1GHz), Bluetooth (2.4-2.48GHz), and IEEE802.1 lb/g (2.4-2.48) standards. In the design of this LNA, cascode architecture is used to reduce the Miller 1 effect and improve the reverse isolation (s/2~0). Also, to eliminate the need for a balun2 a single-ended amplifier is preferred over its differential counterpart. Fig. 4.1 shows the complete schematic of this LNA. The width (130um) and over-drive bias of transistor Mj (220mV) are chosen to satisfy the power budget requirement and to achieve the minimum R„ and NFmin (first step of design technique). With this choice of parameters, the cascode core draws a small current of 6mA from a 1.5V power supply. Mi, M3 and RBI form a current mirror to provide the bias for the input 1 For a through study of Miller effect refer to [45] 2 RF balun transformers convert the single input of the antenna into a differential pair to be used by differential amplifiers Chapter 4 - Simulation Results and Layout Issues 71 transistor. The width of MS is chosen to be very small to minimize the power headroom of the bias circuitry (WM3=2.2\im). The resistor RB2 is chosen very large to reduce its noise contribution to the input of L N A [12]. To achieve the wideband noise and input matching Re{Zin} and Re{ZopJ are simulated in Agilent ADS. Fig. 4.2 shows the results of this simulation. An appropriate choice of the degeneration inductance (Zx=1.2nH) brings the two curves are very close two each other over the band of interest. Figure 4.1 Complete schematic of the multi-standard LNA Chapter 4 - Simulation Results and Layout Issues 72 3 0 0 E 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2 .4 2.6 2.8 3.0 freq, GHz Figure 4.2 Real part matching of Ri„ and Ropt for multi-standard LNA Also, a T matching network is designed to obtain the desired bandwidth. The values of passive elements in this network are L/=8nH, C/=700fF, and Z,2=28nH. This T matching network is intended to be off-chip. The output load of L N A is a shunt-peaking structure and is formed by an inductor (Zrf=3nH) in series with a resistor (7?<f=40Q). The inductive nature of this load compensates the gain roll-off of L N A at high frequencies. To avoid the use of an output buffer, which will result in extra power consumption and chip area, the shunt peaking structure also provides the 50Q matching at the output port. To achieve this goal, an extra capacitance, Q , is added in parallel with the gate-drain capacitance of M?. The value of this capacitance is chosen to satisfy |/]<-10dB at 2.6GHz. (Q=300fF). Figs. 4.3 and 4.4 depict the simulated performance of this L N A . Low values of Su (<-lOdB) in Fig. 4.3 are an indication of input matching over the entire bandwidth. Fig. 4.4 shows Chapter 4 - Simulation Results and Layout Issues 73 both NF and NFmjn on the same graph. As can be seen, NFmin is in close agreement with NF over the bandwidth of interest and satisfies the wideband low NF requirement. 20 -10-0--10 --20 --30--40-i | i p i | i | i | i | i | r 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 S(2,1) S(1,1) S(2,2) freq, G H z Figure 4.3 Simulated S-parameters of the multi-standard LNA ~! "j i | i | i | i | i | i | i | i | i — | — r 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 freq, GHz Figure 4.4 Simulated NF and NFmin of the multi-standard LNA Chapter 4 - Simulation Results and Layout Issues 74 4.2 Wideband LNA for UWB application (3.2-5GHz) The second L N A is designed to operate in the frequency range of 3.2-5GHz, which covers the lower frequency band of UWB systems. The schematic of this L N A is similar to the first LNA, except that the output matching is achieved by using a common drain amplifier. Fig. 4.5 shows the complete schematic of this L N A . Figure 4.5 Complete schematic of the U W B L N A The values of all elements at the input port are chosen based on the steps of the proposed design technique. The value of the parameters are as follows: WM!=160p.m, VOViMi=230mV, Ls=720pH, Lj=l. 7nH, L2=5nH, and Ci=300fF. These values of input network elements facilitate the on-chip implementation of the matching network. Shunt peaking load is used at the drain of the cascode transistor to enhance the bandwidth of the L N A . The value of Rd (41Q) is chosen as a compromise between the gain at low frequencies and the linearity. The inductance Z r f(4.1nH) also compensates the current gain roll-off at high frequencies. Chapter 4 - Simulation Results and Layout Issues 75 The output buffer is properly sized to produce the required 50Q. impedance at the output (^Mi =50pm). The inductor Li provides the DC path to the ground and is chosen large enough so that it does not deteriorate the impedance matching at high frequencies (Z-z.=4.5nH). The width of the cascode transistor is somewhat arbitrary and is usually chosen as a compromise between two competing factors of low noise and input matching [12]. For this LNA, the width of M 2 is chosen to be equal to the width of M i to simplify the layout and to improve the high frequency performance (refer to the layout considerations section). The entire L N A , including the buffer, draws 10mA from a 1.5V power supply. The current usage of the core amplifier is around 7.7mA. Table 2 summarized the performance results of the two LNA. Multi-standard L N A (external matching) UWB L N A (post-layout) |S2l|max 13.6dB 17.7dB NF m ax (in 3dB bandwidth) 0.8 dB 3.2dB IIP3 (worst case) -2.5 dBm -4.5dBm ldB CP (worst case) -13.2 dBm -15dBm Power 9.1 mW 11.6mW -3dB Bandwidth (|S2i|) 1-2.6 GHz 3.16-5.05GHz Bandwidth (|Su|<-10dB) 1.48-2.65 GHz 3.2-6GHz Bandwidth (|S22|<-10dB) >2.55 GHz 3-6GHz Table 2 Summary of Performance Layout Considerations The circuit of this UWB L N A is laid out in a 0.18pm CMOS technology with 6 metal layers using the Cadence Virtuoso layout tool. The careful layout of high frequency circuits is quite Chapter 4 - Simulation Results and Layout Issues 76 necessary to minimize the noise and loss contribution of parasitic elements. For this purpose, a large effort is made to reduce the effect of these parasitics wherever possible. Wide interconnects and a large number of vias are used all over the chip to reduce the parasitic resistances and improve the gain and NF. Two cascode transistors are interdigitated with the gate fingers connected at both ends. This will highly reduce the distributed gate resistance, Rg, and hence improve the NF. Also, the contact windows at the common node of the two transistors are eliminated to decrease the junction capacitance at the drain of Mi and improve the high-frequency performance [46]. Large number of substrate contacts surrounds the cascode architecture to reduce the substrate resistance, Rsub, and its contribution to the NF of L N A [47]. Fig. 4.6 illustrates the layout of the interdigitated transistors Ml and M2. Figure 4.6 Layout of cascade amplifier for the UWB L N A Chapter 4 - Simulation Results and Layout Issues 77 The capacitors are implemented using the metal-insulator-metal (MIM) option in 0.18pm technology with C T M and metal5 as the two plates. These capacitances possess high values of quality factor (Q>300) and are suitable for our high frequency applications. The inductors are all implemented as on-chip spiral inductors. To realize these inductors, thick metal-6 layer (the top-most layer) with the lowest resistivity is employed. However, the quality factor of these inductors is still very low and is about 5 to 10. A lumped RLC equivalent circuit is used to model these spiral inductors [48] and is employed for simulation purposes. Fig. 4.7 shows the 9-element RLC model provided by the foundry. C. Port 1 o -oxl Port 2 — O 'subl R C ox2 subl 'sub2 R sub2 <7 Figure 4.7 9-element equivalent model of spiral inductors This model is developed based on the S parameter fitting of the data obtained from the measurements of stand alone inductors. The information provided by the foundry is valid up to 6GHz, which is sufficient for our UWB L N A . Chapter 4 - Simulation Results and Layout Issues 78 Post-layout simulation results of UWB L N A The layout of this L N A is extracted using the Diva extraction tool from Cadence. A l l parasitic resistances are included in this extraction. Due to the inability of this tool to extract the inductors, all spiral inductors are substituted with their corresponding 9- element model available from foundry measurement. The following figures show the post-layout simulations of this L N A . As can be seen from Fig. 4.8 the 3 dB bandwidth of S21 covers the entire band from 3.1 to 4.8GHz and SI 1 and S22 are less than -lOdB over the entire band. Fig. 4.9 shows the NF and N F m j n on the same graph. The rapid degradation of NF at high frequency is mainly due to the parasitics of spiral inductors and the increase of NFm in at high frequencies. 20 r 15-10-5-0-m T3 -5" — S 21 s„ 1 1 • s °22 251 I 1 I I I I I 2.5 3 3.5 4 4.5 5 5.5 6 Frequency (GHz) Figure 4.8 Simulated S-parameters of the UWB LNA (post-layout) Chapter 4 Simulation Results and Layout Issues 79 Chapter 5 - Conclusions and Future Work 80 CHAPTER 5 CONCLUSIONS AND FUTURE WORK 5.1 Conclusions This thesis presents a wideband power constrained L N A design technique that satisfies simultaneous noise and input matching over a wide range of frequency. Several steps are taken to develop this new methodology. First, the existing wideband architectures are explored and their advantages and disadvantages are briefly discussed. As the result of this overview, the L-deg L N A is chosen as a suitable solution due to its superior performance in terms of NF and power consumption. Second, the wideband performance of L-deg L N A is explored from both the circuit and the system level perspectives. It has been shown that, under power dissipation constraint, the source degeneration inductance plays a significant role in the fulfillment of the simultaneous noise and input matching requirement. Finally, combining all the requirements of low-power consumption, low NF, and simultaneous noise and input matching, a step-by-step design technique is developed. The trade-offs among different requirements and the way they may affect the circuit parameters are also discussed in detail. Also, two LNAs are designed and simulated using the proposed design technique. The first L N A was intended for multi-standard application in the frequency range of (1.2-2.5GHz) and the second L N A was aimed for the lower band of UWB applications (3-5GHz). Both LNAs Chapter 5 - Conclusions and Future Work 81 are designed and simulated in a 0.18um CMOS technology and exhibit high gain as well as good NF and impedance matching, while consuming little power. 5.2 Future Work Large signal behaviour and the linearity performance of the L N A were not priories in the development of the proposed wideband design technique. The linearity of the broadband L N A requires further investigation to clarify the effects of the frequency variation on the linearity of the LNA. Also, a more careful analysis of the L-deg L N A should be carried out to reveal the design trade-offs when high linearity is a major requirement. As discussed in section 3.3, Rs,opt is a frequency-dependant value. However, the existing matching networks cannot track the value of RSi0pt as the frequency varies. Therefore, the best alternative, at present, is to design a wideband matching network that produces Rs=Rjn (i.e., a constant value) at the gate input reference plane. To surmount this shortcoming, one promising area of research is to study the different matching networks in more detail, and find ways to facilitate broadband matching to variable impedances. This will result in a more flexible L N A design that can be optimized for frequency-variant gain and NF requirements. Finally, developing software and C A D tools to automatically design a broadband L N A based on the proposed design technique is of great importance. This will highly simplify the design of integrated RF and mixed-signal circuits and systems. References 82 REFERENCES [1] M . Brandolini, P. Rossi, D. Manstretta, F. Svelto, "Toward multistandard mobile terminals -fully integrated receivers requirements and architectures'''' IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 3, Part 2, March 2005 pp. 1026- 1038. [2] R. R. Kishore, J. Wilson, M . Ismail, "A CMOS RF front-end for a multistandard WLAN receiver", IEEE Microwave and Wireless Components Letters, vol. 15, no. 5, May 2005, pp. 321 - 323. [3] F. Behbahani et al, "A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection", IEEE Journal of Solid-State Circuits, vol. 37, no. 12, Dec. 2002 pp. 1721 -1727. [4] H. Hashemi, A Hajimiri, "Concurrent Multiband Low-Noise Amplifiers-Theory, Design, and Applications," IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, January 2002, pp.288 - 301. [5] S. Andersson, P. Caputa, and C. Svensson, "A Tuned, Inductorless, Recursive Filter LNA in CMOS," Proceedings of the European Solid-State Circuits Conference, September 2002, pp. 351-354. [6] S. Andersson, C. Svenson, and O. Drugge, "Wideband LNA for a Multistandard Wireless Receiver in 0.18pm CMOS," Proceedings of the European Solid-State Circuits, September ' 2003, pp. 655-658. [7] S. w. Chung; S. Y . Lee; K. H. Park, "Wideband impedance matching of integrated antennas and CMOS low noise amplifiers for a multi-band UWB receiver" IEEE Conference on Radio and Wireless, 19-22 Sept. 2004, pp. 131 - 134. [8] F. Bruccoleri; E . A . M Klumperink;B. Nauta, "Wide-band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling", IEEE Journal of Solid-State Circuits, vol. 39, no. 2, Feb. 2004, pp. 275 - 282. [9] F. Ellinger, D. Barms, M . Schmatz, H. Jackel, "A Low Power DC-7.8 GHz BiCMOS LNA for UWB and Optical Communication", 2004 IEEE MTT-S International Microwave Symposium Digest, vol. 1,6-11 June 2004, pp. 13-16. [10] T. Tsang, The Design of Low-Voltage High Frequency Low Noise Amplifiers for Future Wireless Applications, M . Eng. dissertation, McGil l University, 2002. References 83 [11]H. S. Momose et al., "High Frequency AC Characteristics of 1.5nm Gate Oxide MOSFETs", Technical digest of 1996 IEEE international Electron device meeting, pp 105, Dec 1996. [12] T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2 n d Edition, , 2004, Cambridge Press. [13] B. Razavi, RF Microelectronics, 1st edition, 1998, Prentice Hall press. [14] A. van der Ziel, Noise in solid-state devices and circuits, 1986, John Willey and Sons. [15] Y . Tividis, Operation and Modelling of the MOS transistor, 2 n d Edition, June 2003, Oxford Press. [16] D.K. Shaeffer et al., "A 1.5V, 1.5GHz CMOS Low Noise Amplifier" IEEE Journal of Solid-State Circuits, vol. 32, pp. 745-758, May 1997. [17] D.K. Shaeffer, The Deisgn and Implementation of Low-Power CMOS Radio Receivers, Ph.D. dissertation, Stanford University, 1997. [18] J. Janssens, H. Steyaert, "MOS Noise Performance Under Impedance Matching Constraints", Electronics Letters, vol. 35,no. 15, July 1999,pp. 1278 - 1280. [19] J. Janssens, M . Steyaert, "Optimum MOS Power Matching by Exploiting Non-Quasistatic Effect", Electronics Letters, vol. 35, no. 8, April 1999, pp. 672 - 673. [20] H. T. Friis, "Noise figure of Radio Receivers," Proceedings of the institute of radio engineers, vol. 32, pp 419-422, 1944. [21] B. Mohammadi, A 5.8GHz CMOS Low Noise Amplifier for WLAN Applications, M.Sc. dissertation, University of Toronto, 2003. [22] Y . Tang, Design of an RF Wideband Low noise amplifier using 0.35um CMOS Technology, M.Sc. dissertation, University of Alberta, 2002. [23] R. Witte, Spectrum and Network Measurement, 2001, Noble Publication [24] R. Ludwig and P Bretchko, RF Circuit Design, 2000, Prentice Hall. [25] S. Andersson, C. Svenson, and O. Drugge, "Wideband LNA for a Multistandard Wireless Receiver in 0.18pm CMOS," Proceedings of the European Solid-State Circuits, September 2003, pp 655-658. [26] C.-W Kim, M.-S. Jung, S.-G. Lee, "Ultra-wideband CMOS low noise amplifier", Electronics Letters, vol. 41, no. 7, 31 March 2005, pp. 384 - 385. References 84 [27] S. Vishwakarma, J. Sungyong; J. Youngjoong; "Ultra Wideband CMOS Low Noise Amplifier With Active Input Matching", International Workshop on Ultra Wideband Systems, 2004. Joint with Conference on Ultrawideband Systems and Technologies. Joint UWBST & IWUWBS, 18-21 May 2004, pp. 415 - 419. [28] A. Bevilacqua, A. Niknejad, "An Ultra-Wideband CMOS LNA for 3.1 to 10.6 GHz Wireless Receivers", Digest of Technical papers of International Solid-State Circuits Conference, February 2004, pp. 382-383. [29] F. Bruccoleri, E .A .M. Klumperink, B. Nauta, "Wide-band CMOS low-noise amplifier exploiting thermal noise canceling", IEEE Journal of Solid-State Circuits, vol. 39, no. 2, Feb. 2004 pp. 275 - 282. [30] F. Bruccoleri, E .A .M. Klumperink, B. Nauta, "Noise cancelling in wideband CMOS LNAs", Digest of Technical Papers. ISSCC. 2002 IEEE International Solid-State Circuits Conference, vol.1, 3-7 Feb. 2002, pp. 406 - 407. [31] D. M . Pozar, Microwave Engineering, 2 n d Edition, 1998, John Willey & Sons. [32] H.-T. Ahn, D.J. Allstot, "0.5-8.5 GHz fully differential CMOS distributed amplifier", IEEE Journal of Solid-State Circuits, vol. 37, no. 8, Aug. 2002, pp. 985 - 993. [33]B.M. Ballweber, R. Gupta and D.J. Allstot, "A Fully Integrated 0.5 - 5.5 GHz CMOS Distributed Amplifier," IEEE Journal of Solid-State, vol. 35, Feb. 2000, pp. 231-239. [34]R.-C. Liu, K . -L . Deng and H. Wang, "A 0.6-22GHz Broadband CMOS Distributed Amplifier," , Dig. of Technical papers in RFIC Symp., 2003, pp. 103-106. [35] H. A . Haus et al., "Representation of Noise in Linear Two Ports," Proceeding of IRE, vol. 48, pp. 69-74, Jan 1960. [36] S. P. Voinigescu et al., "A Scalable High-Frequency Noise Model for Bipolar Transistors with Application to Optimal Transistor Sizing for Low-Noise Amplifier Deisgn," IEEE Journal of Solid-State Circuits, vol. 32, no. 9, pp. 1430-1439, Sept. 1997. [37] P. Andreani et al., "Noise optimization of an inductively degenerated CMOS low noise amplifier." IEEE Transactions on Circuits and Systems, vol. 48, no. 9, pp. 835-841, Sept 2001. [38] T. K. Nguyen et al., "CMOS low-noise amplifier design optimization techniques," IEEE Transactions on Microwave Theory and Technique, vol. 52, no. 5, pp 1433-1442, May 2004. References 85 [39] G. Gonzalez, "Microwave transistor amplifiers - analysis and design", 2 n Edition, 1997, Prentice Hall. [40] Documents for RF Circuit Designs (Focusing on using Advance Design System (ADS) Software) and High-Speed PCB Design http://pesona.mmu.edu.my/~wlkung/ADS/rf/lesson8a. [41] R. E. Colin, "Foundation for Microwave Engineering", 2 n d Edition, 1992, McGraw-Hill. [42] R. Molavi, S. Mirabbasi, and M . Hashemi, "A Wideband LNA Design Approach", Proceedings of the International Symposium on Circuits and Systems, May 2005, pp. 5107 -5110. [43] D. A . Hodges, R. Saleh, H. Jackson, "Analysis and Design of Digital Integrated Circuits", , 3 r d Edition, 2004, McGraw-hill. [44] H. Javan, "Noise measure for optimum broadband design," IEE Proceedings-Circuits, Devices, and Systems, vol. 138, no. 1, February 1991, pp. 1-4. [45] A. Sedra and K. C. Martin, Microelectronics Circuits, Fourth Edition, 1998, Oxford press. [46] B. Razavi, "Design of Analog CMOS Integrated Circuits", 1s t Edition, 2000, McGraw-Hill. [47] MIT RF open course website http://ocw.mit.edu/OcwWeb/Electrical-EngineeringandComputerScience/6976High-SpeedCommunicationCircuitsandSystemsSpring2003/LectureNotes/index. [48] CMOSP18 Design kit document provided by Canadian Microelectronic Corporation (CMC). Appendix A - Linear Two-port Network Noise Analysis 86 A P P E N D I X A L I N E A R T W O - P O R T N E T W O R K NOISE A N A L Y S I S In this Appendix, we present the theory of linear two port network noise analysis. The formulae obtained in this section are widely used throughout the thesis. Consider the noisy two port network shown in Fig. A. 1 a I, L I, L + V, Noisy two-port network + 1 v, Noise free two-port network up + (a) (b) Figure A. l (a) block diagram of noisy two-port network (b) Equivalent network with input and output noise current sources The total noise in the network can be represented by two independent noise sources at the input and outputs of the network. So, in admittance matrix representation we can write: (A.1) Rearranging the parameters, we can convert the admittance representation to the inverse hybrid representation: + — Jl. Y 1 2 2 . Jn2. Hl2 v2 + — J l . H2l H22 h (A.2) where all the noise sources are transformed to the input of network and are represented by voltage and current noise sources, V„ and /„: en = - ^ l n 2 a i l d ' „ = l « l - — ln2 1 21 1 21 (A3) Appendix A - Linear Two-port Network Noise Analysis 87 Using this simplification we arrive at the network model shown in Fig A.2, where the noisy admittance, Ys, and the corresponding parallel current noise are connected to the input of the network. ( t ) n Noiseless Two Port Network Figure A.2 Input Referred equivalent noise model The definition of NF is given by: total input referred noise power NF = • input referred noise power due to source (A.4) Assuming that the two-port network and the source noise are uncorrelated, then the following expression for the NF of the network can be written: NF = - (A.5) Note that (A.5) does not assume that the internal noise sources i„ and en are uncorrelated. To include this correlation, /„ can be expressed as the sum of two components: K = lu + lc (A.6) where /„ is uncorrelated with e„ and ic is the correlated with e„. Since ic is fully correlated with e„ we can introduce a correlation admittance Yc, which relates the two components: ic=Ycen (A.7) Appendix A - Linear Two-port Network Noise Analysis 88 Now, the NF expression in (A.5) can be simplified as follows: NF = - • 2 • = 1+-i2..+ +Ys)e„ (A.8) Each of the noise sources iu, is, and e„ can be represented by an equivalent resistance or conductance that generates the same noise: " AkTAf i2u G = " 4kTAf • 2 G. = s 4kTAf Therefore, (A.8) can be rewritten as: NF G, +Vr +Y2R„ 1 + Gu+[(Gc+Gs)2+(Bc+Bs)2]Rn (A.9) (A.10) (All) (A. 12) This last expression explicitly shows the dependence of NF on the conductance and susceptance of source, i.e. Gs and Bs. Hence, one can optimize NF by properly choosing these values. Taking the first derivative of (A. 12) with respect to Gs and Bs, we can find the optimum value of the source admittance and that of NFmin: s .opt ^-+G' R. D _ _ n s ,opt c NFm,=\ + 2R„ B^+G2C +GC R. (A. 13) (A. 14) Appendix A - Linear Two-port Network Noise Analysis 89 It is also possible to express NF in terms of NFmin and the optimum impedance: NF=NFmin +^[(GS -Goptf +(BS-Boptf] (A.15) The contours of constant NF in the Smith chart are circles that have their centres located along a line drawn from the origin to Yopt. Appendix B - Classic MOS Device Noise Analysis 90 A P P E N D I X B C L A S S I C M O S D E V I C E NOISE A N A L Y S I S In this appendix we apply the formulae obtained in Appendix A to a MOS device to find analytical expressions for Gopt, Bopt and NFmin in terms device parameters. Recall from chapter 2 that dominant sources of noise in a MOS device are the channel thermal noise, i2nd, and the gate induced current noise, i2ng with the power spectral densities given by: iJ=4kTygd0Af iJ=4kTSgAf (B.l) (B.2) where / „ g can be rewritten as the sum of two term, one correlated with i2nd and one totally uncorrelated: V = ' V +i„gc2=4kTSggAf(\-\c\ ) + 4kT8ggAf \c\ (B.3) where i2ngu is the uncorrelated portion, i2ngc is the correlated portion, and c is the correlation factor and is defined in chapter 2. In order to relate NF to the noise parameters of MOS device, we should find the internal noise sources en and /„ in terms of i2„d and i2ng. To do this, consider the MOS noise model in Fig. A . l a and its equivalent input-referred model in FigA.2 nd (a) (b) Figure B.l (a) Noise sources of a MOS device b) Equivalent input referred model Appendix B - Classic MOS Device Noise Analysis 91 Equating the input-referred noise in the two figures yields the following expressions for e„ and i„: 7 \ = i ^ = A k T ^ ( B A ) & m & m V (B.5) gm J To calculate Gopt and Bopt, we need to find Yc given by the expression ic=Ycen., see (A.7). A simple way to find Yc is to re-express (A. 7) in the following way: Yc=l-£f (B.6) After substituting (BA) and (B.5) in (B.6), and after some simple algebraic manipulation we obtain: Yc=jaCgs+gml-^k (B.7) 1 nd •2 xl/2 Multiplying both the numerator and denominator by (i n g ) and recalling the definition of correlation factor from (2.6) yields: Yc=jccCgs+gmc\^= (B.8) 1 nd Substituting the expressions for i „^and / «dfrom (B.l) and (B.2) we find that: where the last equality is written on the assumption that the correlation factor is a purely imaginary number, i.e. c--j\c\. Based on these calculations we can now find the expressions for noise conductances and resistance in terms of MOS noise parameters: Appendix B - Classic MOS Device Noise Analysis 92 e - rgd0 _ r n 4kT Af g \ a.g„ (B.10) G.. =• / 2 I ngu AkT6f5g(\-c') dco2Cj{\-c ) u 4kT Af 4kTAf Therefore we obtain: 4kTAf _g£_ 5g dO (B.U) Bt„=-Bc=-aCp<\-a)f\\-) (B.12) ^ m i n = i + 2 ^ j J | ^ + G j , i + ^ ^ ( i - k r ) (B.13) (B.U) and also for Zopt we have 7 = _ op' y 5 ( 1 - O . , , I , opt caC„ - + ( l + «|c| / - ) 5r The calculations for inductively degenerated L N A can be performed in the same way. The details of these calculations are provided in [38]. 

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