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Delay compensated fade prediction based CDMA closed loop power control Lee, Peter Ming Wong 2004

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DELAY COMPENSATED FADE PREDICTION BASED CDMA CLOSED LOOP POWER CONTROL by PETER MING WONG LEE B.A.Sc, The University of British Columbia, 2000 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA September 2004 © Peter Ming Wong Lee, 2004 THE UNIVERSITY OF BRITISH COLUMBIA FACULTY OF GRADUATE STUDIES Library Authorization In presenting this thesis in partial fulfillment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Name of Author (please prini 0^1 \o ( Jjco^ Date (dd/mm/yyyy) Title of Thesis: PeW^ C QAftAsckiA Y~CL\I^ Prt <[\cko/^ £PMA CUM, H Degree: Year: — Department of TpUcb>rc-ft.\ Compu.W' ^AtS/\tej^a The University of British Columbia ' \J 'A Vancouver, BC Canada grad.ubc.ca/forms/?formlD=THS page 1 of 1 last updated: 20-Jul-04 Abstract Power control is essential in Code Division Multiple Access (CDMA) systems in order to reduce the near-far effect, optimize,the system capacity, and combat the signal degradation due to fading. One problem with Closed Loop Power Control (CLPC) is the delay introduced by power measurement and round-trip delay in the power control loop. We study the impact of power control loop delays on Frame Error Rate (FER) performance under a range of channel conditions. A new CLPC algorithm with delay compensation and fade prediction is then proposed to mitigate the effects of loop delays on CLPC. Delay compensation can reduce power oscillation amplitude around the desired received power level and fade prediction can forecast an upcoming fade in order to mitigate its effect. The FER performance on the forward link of an Interim Standard - 2000 (IS-2000) CDMA system using the delay compensated fade prediction based CLPC algorithm is studied. Simulations with a detailed IS-2000 physical layer model and various Third Generation Partnership Project 2 (3GPP2) channel models are used to illustrate the performance gains of the proposed CLPC algorithm over the conventional CLPC algorithm. The performance of the proposed CLPC algorithm as a function of mobile speed, delay, and carrier frequency is analyzed. It is found that the proposed CLPC algorithm performs better than the conventional CLPC algorithm by about 1 dB for a range of mobile speeds of interest. The performance improvement obtainable by using the proposed CLPC algorithm can reduce the interference and result in an increase in the system capacity. Finally, the effect of power control bit (PCB) errors on the performance of the proposed CLPC algorithm is studied. Simulation results indicate that the proposed CLPC algorithm is still beneficial when the PCB error rate is 5%. ii Table of Contents Abstract ii Table of Contents iiList of Tables • v List of Figures vi List of Abbreviations xList of Symbols xiii Acknowledgments '. xv 1.0 Introduction 1 1.1 Motivation.... 2 1.2 Goals 5 1.3 Contributions1.4 Thesis Outline 6 2.0 Background... 7 2.1 Multipath Rayleigh Fading 8 2.2 Maximal Ratio Combining 9 2.3 Near-Far Problem 10 2.4 Power Control 1 2.4.1 Open Loop Power Control 12 2.4.2 Closed Loop Power Control2.4.3 Outer Loop Power Control 13 2.5 IS-2000 Closed Loop Power Control Procedure 15 3.0 Previous Work 20 iii 3.1 Delay Compensation. , -20 3.2 Fade Prediction 23 4.0 Simulation Model , 25 5.0 Delay Compensated Fade Prediction Based Closed Loop Power Control Algorithm 34 5.1 Power Oscillations 5 5.2 Fade Linearity 39 5.3 Proposed Closed Loop Power Control Algorithm 42 5.4 System Capacity 44 5.4.1 Multi-cell IS-2000 Forward Link Capacity 46 5.4.2 Multi-cell IS-2000 Reverse Link Capacity 47 6.0 Simulations 49 6.1 Numerical Results for 800 MHz Band 49 6.2 Numerical Results for 1.9 GHz Band 70 6.3 Numerical Results for 800 MHz Band with 5% PCB Error Rate 89 6.4 Discussion of Simulation Results 97.0 Conclusion 108 7.1 Contributions of the Thesis 107.2 Topics for Further Study 110 Bibliography 112 iv List of Tables Table 1 Reverse Power Control Subchannel Configurations 17 Table 2 BS Simulation Parameters 29 Table 3 Channel Simulator Configurations 30 Table 4 Channel Parameters and Target FER 1 Table 5 Additional Channel Parameters and Target FER 32 Table 6 Simulation Duration and Number of Fade Cycles 32 Table 7 MSE Comparisons of Fade Envelopes with No Prediction and with Linear Prediction 41 Table 8 Summary of 800 MHz Band Simulation Figures 51 Table 9 Summary of 1.9 GHz Band Simulation Figures 70 Table 10 Summary of 800 MHz Band with 5% PCB Error Rate Simulation Figures 89 Table 11 Impact of CLPC and Loop Delays on Et/Nt Required by the Conventional CLPC Algorithm to Achieve the Target FER at 870 MHz 99 Table 12 Impact of CLPC and Loop Delays on Eb/Nt Required by the Conventional CLPC Algorithm to Achieve the Target FER at 1.93 GHz 99 Table 13 Relative Performance Gain of Proposed CLPC Algorithm at 870 MHz.... 101 Table 14 Relative Performance Gain of Proposed CLPC Algorithm at 1.93 GHz ... 102 Table 15 Impact of 5% PCB Error Rate on Eb/Nt for the Conventional CLPC Algorithm to Achieve the Target FER at 870 MHz 105 Table 16 Relative Performance Gain of Proposed CLPC Algorithm at 870 MHz with 5% PCB Error 106 v List of Figures Figure 1 Sources of Delay in Power Control Loop 3 Figure 2 Examples of Power Control Loop Delays 4 Figure 3 Spectral Spreading and Despreading in IS-95 / IS-2000 8 Figure 4 Closed Loop Power Control and Outer Loop Power Control Flow Chart.... 14 Figure 5 Reverse Pilot Channel Showing the Power Control Subchannel Structure ..16 Figure 6 Reverse Power Control Subchannel 1Figure 7 CDMA System Timing 18 Figure 8 Received SIR when Power Control Commands are Delayed by Two Slots, (a) TDC Employed and (b) No TDC 22 Figure 9 Block Diagram of Multi-step SIR-based Power Control Method with Fade Prediction 24 Figure 10 Block Diagram of SPW IS-2000 Forward Link Model 25 Figure 11 Functional Set-up for Traffic Channel Tests in Fading Channel 28 Figure 12 Effects of Power Control Delay on Received Eb/Nt and BS Tx Gain in 1 path 3 km/hr Rayleigh Fading 37 Figure 13 Effects of Power Control Delayon Received Eb/Nt and BS Tx Gain in 1 path 30 km/hr Rayleigh Fading 38 Figure 14 Rayleigh Fading Envelopes for Different Channel Environments at 870 MHz 4Figure 15 Conventional CLPC Algorithm and Proposed CLPC Algorithm 43 Figure 16 Difference between Proposed(D) and Proposed(D+0.5) 50 Figure 17 Effects of PCG Delays on FER (1 path 3 km/hr Rayleigh Fading at 870 MHz) 52 vi Figure 18 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 3 km/hr Rayleigh Fading at 870 MHz) 53 Figure 19 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 3 km/hr Rayleigh Fading at 870 MHz) 54 Figure 20 Effects of PCG Delays on FER (1 path 30 km/hr Rayleigh Fading at 870 MHz) 55 Figure 21 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 30 km/hr Rayleigh Fading at 870 MHz) 56 Figure 22 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 30 km/hr Rayleigh Fading at 870 MHz) 57 Figure 23 Effects of PCG Delays on FER (3 path 100 km/hr Rayleigh Fading at 870 MHz) 58 Figure 24 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 100 km/hr Rayleigh Fading at 870 MHz) 59 Figure 25 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 100 km/hr Rayleigh Fading at 870 MHz) 60 Figure 26 Effects of PCG Delays on FER (1 path 50 km/hr Rayleigh Fading at 870 MHz) 61 Figure 27 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 50 km/hr Rayleigh Fading at 870 MHz) ..62 Figure 28 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 50 km/hr Rayleigh Fading at 870 MHz) 63 Figure 29 Effects of PCG Delays on FER (1 path 100 km/hr Rayleigh Fading at 870 MHz) 64 vii Figure 30 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (f path 100 km/hr Rayleigh Fading at 870 MHz): 65 Figure 31 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 100 km/hr Rayleigh Fading at 870 MHz) 66 Figure 32 Effects of PCG Delays on FER (3 path 30 km/hr Rayleigh Fading at 870 MHz) 67 Figure 33 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 30 km/hr Rayleigh Fading at 870 MHz) 68 Figure 34 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 30 km/hr Rayleigh Fading at 870 MHz) 69 Figure 35 Effects of PCG Delays on FER (1 path 3 km/hr Rayleigh Fading at 1.93 GHz) 71 Figure 36 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 3 km/hr Rayleigh Fading at 1.93 GHz) 72 Figure 37 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 3 km/hr Rayleigh Fading at 1.93 GHz) 73 Figure 38 Effects of PCG Delays on FER (1 path 30 km/hr Rayleigh Fading at 1.93 GHz) '. 74 Figure 39 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 30 km/hr Rayleigh Fading at 1.93 GHz) 75 Figure 40 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 30 km/hr Rayleigh Fading at 1.93 GHz) 76 Figure 41 Effects of PCG Delays on FER (3 path 100 km/hr Rayleigh Fading at 1.93 GHz) 77 viii Figure 42 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 100 km/hr Rayleigh Fading at 1.93 GHz) 78 Figure 43 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 100 km/hr Rayleigh Fading at 1.93 GHz) 79 Figure 44 Effects of PCG Delays on FER (1 path 50 km/hr Rayleigh Fading at 1.93 GHz) 80 Figure 45 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 50 km/hr Rayleigh Fading at 1.93 GHz) 81 Figure 46 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 50 km/hr Rayleigh Fading at 1.93 GHz) 82 Figure 47 Effects of PCG Delays on FER (1 path 100 km/hr Rayleigh Fading at 1.93 GHz) 8Figure 48 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 100 km/hr Rayleigh Fading at 1.93 GHz) 84 Figure 49 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 100 km/hr Rayleigh Fading at 1.93 GHz) 85 Figure 50 Effects of PCG Delays on FER (3 path 30 km/hr Rayleigh Fading at 1.93 GHz) 86 Figure 51 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 30 km/hr Rayleigh Fading at 1.93 GHz) 87 Figure 52 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 30 km/hr Rayleigh Fading at 1.93 GHz) 88 Figure 53 Effects of PCG Delays on FER (1 path 3 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 9ix Figure 54 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 3 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate).91 Figure 55 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 3 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate).92 Figure 56 Effects of PCG Delays on FER (1 path 30 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 93 Figure 57 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 30 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 94 Figure 58 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 30 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 95 Figure 59 Effects of PCG Delays on FER (3 path 100 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 96 Figure 60 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 100 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 97 Figure 61 Comparison of Conventional and Proposed Algorithms when Delay=73,PCG Slots (3 path 100 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 98 x List of Abbreviations 2G - Second Generation 3G - Third Generation 3GPP2 - Third Generation Partnership Project 2 AWGN - Additive White Gaussian Noise BER - Bit Error Rate BS - Base Station CDMA - Code Division Multiple Access CLPC - Closed Loop Power Control DSCDMA - Direct Sequence Code Division Multiple Access EIA - Electronic Industries Alliance ESN - Electronic Serial Number FER - Frame Error Rate GPS - Global Positioning System IS - Interim Standard MMSE - Minimum Mean Square Error MRC - Maximum Ratio Combining MS - Mobile Station MSE - Mean Square Error NIST - National Institute of Science and Technology OCNS - Orthogonal Channel Noise Simulator PCB - Power Control Bit PCG - Power Control Group PCS - Personal Communications Services xi PN - Pseudo Noise QoS - Quality of Service QPSK - Quadriphase-Shift Keying PvLS - Recursive Least Square SIR - Signal to Interference Ratio SPW - Signal Processing Worksystem TDC - Time Delay Compensation TIA - Telecommunications Industry Association xii List of Symbols a* - Complex conjugate of channel gain fj - Time in fraction of a slot at which a power control command is sent Br - MS receive frequency band Bt - MS transmit frequency band A - Power control step size 6 - MS transmit power fraction for traffic data Eb - Received energy per bit Ec - Received energy per PN chip et - Difference between SIR threshold and measured SIR at receiver i n - Background noise power due to spurious interference and thermal noise fl - Doppler frequency threshold ft - Relative received sector power at MS i y, - SIR measured at receiver i yt - Adjusted SIR measurement at receiver i I0 - Total power spectral density (signal and interference) at the MS antenna Ioc - Other cell interference power spectral density Ior - Total transmit power spectral density Ior - Total transmit power spectral density after channel simulator k - Number of correlators M - Number of users in one cell MS - Number of users in one sector - • xiii N0 - Noise power spectral density Nt - Noise power spectral density at MS antenna nc - Computation and signaling delay in slot units nr - Round trip delay in slot units nt - Total power control loop delay in slot units pi - Received signal power at receiver i R - Information bit rate r - Signal after MRC p - BS transmit power fraction for traffic data 5 - Received signal power si - Single bit power control command (up or down) sent by receiver i STi - Received signal power from home BS T - Slot duration TSIR - SIR threshold td - Power control command detection delay tm - Signal quality measurement delay t0 - Transmitter power output delay t - Signal propagation delay , ts - Power control signaling delay vn - Output of the n -th correlator at sampling time W - Total bandwidth wn - Weight of the n -th correlator xiv Acknowledgments I would like to thank my thesis supervisor, Dr. Cyril Leung, for his guidance and encouragement throughout the duration of this thesis work. His valuable suggestions and critical reviews were essential to the completion of this project. It gave me great pleasure to learn from him and work under his supervision. I would also like to thank Mr. Roozbeh Mehrabadi for helping me with the simulation tool and other people in the Communications Group for their support. Finally, I would like to thank my parents, Mr. Cheng-Jau Lee and Mrs. Jenny Lee, for their support and encouragement. They played an important role in the completion of this work. This work was supported in part by the Natural Sciences and Engineering Research Council of Canada under grant OGP0001731. xv 1.0 Introduction Over the past decade, wireless technology has undergone an enormous evolution. The rapid growth of the cellular telephone industry and the increasing demand for mobile multimedia services have necessitated an efficient cellular system. As a result, Direct Sequence Code Division Multiple Access (DSCDMA) has been proposed to meet the needs of the cellular industry. A popular Third Generation (3G) mobile communication standard based on DSCDMA technology is the Telecommunications Industry Association / Electronic Industries Alliance (TIA/EIA) Interim Standard - 2000 (IS-2000). IS-2000 is the successor of the Second Generation (2G) IS-95 standard and it is an evolutional step to provide next generation capacity, data rates, and services. TIA/EIA released the first version of IS-2000 in 1999, and has published several revisions in subsequent years. The wireless industry is enthusiastic about the commercialization of IS-2000 because it is a technology developed to accommodate the growing demand for higher data rates and increased system capacity. The incentive for using a DSCDMA communication system is its ability to reject interference from other users simultaneously attempting to transmit over the channel. Since a CDMA system is interference limited, system capacity is maximized when signals are transmitted at the minimum required power to satisfy the signal-to-interference ratio (SIR) requirement. Therefore, power control is a critical issue in CDMA systems, as efficient power control maintains the SIR and reduces a user's interference to other users in the system. 1 1.1 Motivation Closed Loop Power Control (CLPC) is commonly used to compensate for power fluctuations due to fast fading in a cellular multiple access environment. It is closed loop in that the process involves both the transmitter and the receiver. Given that CLPC is essential to reduce inter-user interference, much effort has been devoted to improving the CLPC algorithm. A better CLPC algorithm will not only help to maintain the SIR in a fading environment, but it can also increase the system capacity by mitigating the near-far problem. Therefore, it is highly desirable to make the CLPC algorithm as efficient as possible. Generally, a CLPC algorithm requires input data, i.e. power control command, periodically with a hard timing deadline, and adjusts the output power after a fixed amount of time relative to the received power control command. The power control command and output power can be treated as sampled values at the transmitter and receiver of the CLPC algorithm with a fixed sampling rate. A major problem that can hamper the performance of a CLPC algorithm is time delay. In practice, it takes some time, tm, to measure the signal quality (assuming signal quality is averaged over a certain period). After the signal quality is measured, there is a delay, ts, before the power control command is sent to the transmitter. Furthermore, there are propagation delays, t , when the power control command is sent to the transmitter, and when the adjusted power arrives at the receiver. The transmitter requires a time, td, to detect the power control command. In addition, there is a delay, t0, before the power control command is acted upon and applied in the transmitter output. Figure 1 shows the sources of delay in the power control loop. 2 Transmitter Receiver m - Measurement Delay s - Signaling Delay p - Propagation Delay d - Detection Delay 0 - Output Delay Figure 1 Sources of Delay in Power Control Loop In general, time is divided into slots by the CLPC algorithm and one power control command is sent at a fixed time in each slot. Let T be the slot duration (tm <T) and fi be a value between 0 and 1 that represents the time in fraction of a slot at which a power control command is sent. For instance, =0.5 means the power control command is sent in the middle of the slot. Assuming tm starts from the beginning of each slot. For the signal quality measured in slot i to be used to generate the power control command sent in slot i, tm+ ts must be less than /3T. Otherwise, the signal quality measured in slot i can only be used to generate a power control command in some future slot. Let nc be the delay in slot units in generating a power control command based on the most recent signal quality measurement. Then, nc =0,1,2.... (1.1) The round trip delay in the power control loop is the time interval between the transmission of the power control command and the arrival of the corresponding adjusted power at the receiver, i.e. t +ttl +ta+t . In most cases, the transmitter 3 output power is changed at a fixed time in each slot. Assuming the transmitter power is only changed at the beginning of a slot and let nr be the round trip delay in slot units. Then, n, = + J3 nr =1,2,3.... (1.2) Hence, the total delay, nt, in slot units in the power control loop is n, =nc+nr, n, =1,2,3. (1-3) Figure 2 shows two examples of power control loop delays in slot units. Let slot i be the current slot and a power control command is just sent to the transmitter in slot i. Figure 2(a) shows the case when n, =1 (nc = 0 ,nr = 1). It can be seen that the signal quality measured in slot i was used to generate the power control command sent in slot i. The power control command will be applied in the transmitter output at the beginning of slot I' + l. Figure 2(b) shows the case when nt - 3 (nc -\,nr = 2). It can be seen that the signal quality measured in slot i-1 was used to generate the power control command sent in slot i. The power control command will be applied in the transmitter output at the beginning of slot i + 2. 2t, +tt +t. V, h-4-H Slot i-1 Slot I Slot l+l I—H—H—H -000 N—H T > Sloti-2 Slot i-1 Sloti Sloti+1 Slot i+2 I i I I II III 0 0 0 0 0 H—H (a) n, =1 (nc = 0,nr =1) (b) n, =3 (nc =l,nr =2) Figure 2 Examples of Power Control Loop Delays 4 Since the channel condition is changing over time, a delay in the power control loop means that the power control commands may be outdated and do not reflect the latest channel condition. As a result, the performance of CLPC is degraded due to the loop delays. 1.2 Goals The IS-2000 standard has been widely adopted because of its superior features and CLPC is essential to the smooth operation of an IS-2000 system. Since loop delays can cause CLPC to be ineffective, the overall system performance can be improved if the effects of loop delays are reduced or compensated. The objectives in this thesis are to investigate the impact of power control loop delays on the overall system performance, improve the existing CLPC algorithm, and demonstrate the advantages of the improved CLPC algorithm. Computer simulations will be used to verify the performance gains of the improved CLPC algorithm and expressions will be provided to show how the improvements will result in an increased system capacity. 1.3 Contributions The main contributions of this thesis are: 1. The effects of power control loop delays on Quality of Service (QoS) in terms of Frame Error Rate (FER) in an IS-2000 system were studied. 2. A new CLPC algorithm based on delay compensation and fade prediction was proposed to mitigate the effects of loop delays. The new algorithm is applicable to IS-2000 compliant systems with no additional hardware requirements as well as to other power controlled CDMA systems. 5 3. The performance of the proposed CLPC algorithm was examined using simulations to confirm the benefits of using the proposed CLPC algorithm in different fading environments and with different loop delays. A complete IS-2000 forward link physical layer model that includes channel coding / decoding, interleaving / deinterleaving, and spectrum spreading / despreading was used to evaluate the overall FER performance. In this thesis, the focus is on the forward link CLPC since it is not used in IS-95 but has been introduced in IS-2000. 1.4 Thesis Outline The rest of this thesis is organized as follows. In Chapter 2, some of the fundamental concepts in CDMA systems are reviewed. This chapter also summarizes the standard CLPC algorithm used in IS-2000. Chapter 3 examines the state of the art in power control and previous works. In this chapter, the effects of power control loop delays are studied. In Chapter 4, the IS-2000 forward link system simulation model is presented, along with the test conditions specified in Third Generation Partnership Project 2 (3GPP2) C.S0011-A, Recommended Minimum Performance Standards for cdma2000 Spread Spectrum Mobile Stations. In Chapter 5, the use of delay compensation and fade prediction in IS-2000 CLPC algorithm is discussed and a new CLPC algorithm is proposed. Furthermore, the relationship between SIR and IS-2000 forward / reverse link system capacities are depicted. In Chapter 6, FER simulation results of the proposed CLPC algorithm are provided and compared against those of the conventional CLPC algorithm. Conclusions and future research suggestions are given in Chapter 7. 6 2.0 Background Spread spectrum has been used for a long time in military communications to combat intentional jamming and reduce the probability of intercept. More recently, spread spectrum has been employed in civilian applications, and has profoundly influenced the digital cellular industry. IS-2000 utilizes DSCDMA, which differs from the traditional system design objective of minimizing the utilization of channel bandwidth, to achieve a higher system capacity. In DSCDMA, a wideband code sequence that is independent of the data sequence is used to accomplish spectrum spreading. The information-bearing signal is multiplied by the wideband code to make the signal appear wideband and noise-like. Different users can occupy the same band at the same time and they are separated from each other via a set of codes. The transmitted signal, along with background noise, external interference (interference from unknown sources), and internal interference (interference from co-channel users), arrive at the receiver at the same time. The receiver sifts the desired signal out of the composite signal by correlating the composite signal with the original code. All the unwanted signals that do not match the original code will result in a low correlation when they are despread and are rejected by the receiver. Figure 3 shows the spreading and despreading of the data signal in an IS-95 / IS-2000 system. 7 Figure 3 Spectral Spreading and Despreading in IS-95 / IS-2000 (adapted from [1]) In addition to noise and interference, the transmitted signal may be subject to other propagation impairments. Multipath fading is often a major impediment to reliable communication. Another issue is the near-far problem caused by propagation loss and the geographical locations of the users. In IS-2000, power control is employed to mitigate multipath distortion and the near-far problem. A description of the CLPC procedure in IS-2000 is given at the end of this chapter. 2.1 Multipath Rayleigh Fading A signal can be reflected from various physical structures, such as buildings and walls, on its way to the receiver. Due to the reflections, the signal arrives at the receiver via a number of different paths. The different reflected signals arrive at slightly different times, with different amplitudes, and with different phases. These 8 reflected signals may add constructively or destructively to the original signal, resulting in multipath fading [2]. The envelope of a received signal for a moving mobile is often modeled by a Rayleigh distribution [3]. The performance of a communication system can be severely degraded by Rayleigh fading. Possible solutions to combat multipath Rayleigh fading are to increase transmit power or to use diversity techniques [4]. In IS-2000, with a pilot signal that provides timing reference, the signal arriving from different paths may be independently received to reduce the severity of the multipath fading. This multipath diversity is a form of time diversity in which the signals from different paths are combined to reduce the effect of fading and improve SIR. As long as the time separations between the signals are greater than one chip time, the signals can be resolved and can be combined to provide better signal quality [5]. In IS-2000, the chip rate is 1.2288 Mcps. Therefore, two signals can be separately combined using the technique discussed in the next section if they are at least 814 ns apart. 2.2 Maximal Ratio Combining A common technique that is used in CDMA systems to combat multipath fading is maximal ratio combining (MRC). With the aid of a pilot signal in IS-2000, the outputs from the correlators that have been synchronized to the signals from the multipaths are combined in an optimum manner. Let vn be the output of the n-th correlator at the sampling time. In MRC, the outputs are combined with some weights, wn, to give k (2.1) n=l 9 where r is the signal after MRC and k is the number of correlators. The weights are selected to emphasize the contributions of stronger signal components. The optimum combining law is [6]: r = J!,aX, (2-2) n=l where a* is the complex conjugate of the gain of path n . The advantage of this combining technique is that it avoids the loss of information about the received signal from the multipaths. By combining the signal energy from different paths, the multipath distortion is mitigated. This diversity combining receiver is also called a rake receiver. Note that the rake receiver improves signal quality by coherently combining the multipath signals. The earliest arrived signal is delayed until the end of the rake receiver combining window, which is the arrival time of the latest multipath signal used for MRC. The added delay can contribute to the delay in the CLPC algorithm. 2.3 Near-Far Problem The near-far effect, which is caused by propagation loss, distance between the base station (BS) and the mobile station (MS), and transmitter power, is a critical issue in CDMA systems. For example, MS's are geographically dispersed but transmit in the same frequency band, Bt, and receive in the same frequency band, Br. In the forward link (BS to MS direction), an MS close to a BS usually requires a lower received signal power than an MS which is far from the BS in order to achieve the same SIR. This is because inter cell interference is more severe at cell boundaries. In the reverse link (MS to BS direction), an MS transmitting near a BS can significantly degrade the performance of an MS which is far away from the BS if all 10 MS's transmit at the same power. This is because the BS receives a higher power signal from the closer MS, and this higher power signal can severely interfere with the distant MS. Without solving the near-far problem, CDMA would be ineffective in a wireless multiple access environment. In IS-2000, forward link and reverse link power control are employed to ensure that the desired signals received at the MS and BS all have the same strength. 2.4 Power Control IS-2000 employs forward link and reverse link power control in order to solve the near-far problem, achieve high capacity and meet SIR requirement. The objective of BS / MS power control is to produce a nominal signal power at the receiver regardless of the channel condition and MS's locations. From the system operator's point of view, it is highly desirable to maximize the capacity of the CDMA system, i.e. the number of simultaneous traffic channels that can be handled in a given bandwidth, while maintaining the QoS. If a transmitted signal arrives at the receiver with a received power that is too low, the FER will be too high to maintain high quality communications. On the other hand, if the received power is too high, the FER will satisfy requirements, but the interference introduced to other system users is increased. Power control provides a way to reduce average power by transmitting at high power levels only during fades and when interference is severe. The system capacity is maximized when the transmitted power is controlled so that signals arrive at the receiver with the minimum required SIR. For data services traffic, power control can lower the FER and reduce the number of packet retransmissions. Also, by reducing the reverse link average power, MS power consumption is reduced, thereby resulting in a longer handset operating time. 11 There are three types of power control that are employed in IS-2000: open loop power control, closed loop power control and outer loop power control [7]. The purpose of each power control type is described below. 2.4.1 Open Loop Power Control On the reverse link in an IS-2000 system, open loop power control is employed. Open loop power control refers to the process of adjusting the MS transmit power according to changes in the MS received power. The stronger the power received by the MS, the lower is the MS transmit power. Thus, the MS transmit power is made inversely proportional to the power received by the MS. After a traffic channel is set up, and as the MS moves around, the path loss and shadowing effect between the MS and the BS will change. As a result, the received power at the receiver will change, and the open loop power control will continue to monitor the received power and adjust the transmit power accordingly. The response time of the open loop power control is made slow intentionally to ignore small-scale fading [8]. In other words, open loop power control is used to compensate for slowly varying and shadowing effects where there is a correlation between the forward link and reverse link fades. However, since the forward and reverse links operate at different frequencies, the open loop power control is inadequate and too slow to compensate for fast fading. 2.4.2 Closed Loop Power Control The goal of closed loop power control is for the BS to instruct the MS, or the MS to instruct the BS, to change the transmit power in a rapid manner in order to combat fast fading. In IS-2000, the transmit and receive frequencies are separated, and the frequency separation generally exceeds the coherence bandwidth of the 12 channel [9]. Therefore, the fast fading processes on the forward and reverse channels are not highly correlated, and it is more appropriate to power control the forward link and reverse link separately. A one-bit power control signaling scheme is used for powering up or down the transmitter by a fixed amount, and the signaling bit is called the power control bit (PCB). The PCB is generated once every power control group (PCG), which is 1.25 ms in duration, by comparing the received SIR to an adjustable threshold. While the method for measuring SIR is not specified in IS-2000, it is usually obtained by averaging the traffic channel signal quality over a short duration in order to get an accurate SIR measurement. If the received SIR is larger than or equal to the threshold, a power down command is generated. Otherwise, a power up command is generated. The PCB is transmitted through the forward or reverse power control subchannel with specific timing requirements. The closed loop power control provides correction to the open loop power control. It is important that the latency in generating a PCB based on the received SIR and the signaling process be kept small so that the channel condition will not change significantly before the PCB is received and acted upon. However, delay is introduced when averaging the SIR over time, and this delay can degrade the power control performance. Hence, there is a tradeoff between obtaining a more accurate SIR measurement and shortening the power control delay. Furthermore, sending the PCB over the power control subchannel adds an additional delay to the process. 2.4.3 Outer Loop Power Control Outer loop power control is the process of adjusting the threshold value used in closed loop power control. Since the power control objective is to maintain an acceptable FER, and since in a cellular environment, there is no simple relationship between FER and SIR, the SIR threshold has to be dynamically adjusted to maintain 13 the desired FER. Increasing the threshold reduces FER, thereby, improving the QoS. Reducing the threshold tends to increase FER. The threshold is selected to ensure that enough power is received to satisfy the required FER for the call and it can be dynamically changed every frame. Closed loop power control and outer loop power control work together to ensure that the desired SIR is maintained and the required FER is met. Figure 4 shows the closed loop power control and outer loop power control flow chart. The received energy per bit to the effective noise power spectral density (Eb/Nl) is used as the figure of merit for the received SIR and SIR threshold. Set initial Eb/ N, threshold to satisfy FER requirement Send up command Increase Eb/N, threshold Figure 4 Closed Loop Power Control and Outer Loop Power Control Flow Chart 14 2.5 IS-2000 Closed Loop Power Control Procedure This section describes the forward link CLPC procedure in IS-2000 [10]. Forward link CLPC is newly introduced in IS-2000 and does not exist in IS-95. An IS-2000 BS can transmit up to three data channels (one fundamental channel and up to two supplemental channels) for a single user, together with a common pilot and some signaling channels for all users in a cell. The main purpose of the forward link CLPC algorithm is to maintain the forward link FER of the target channel at the desired level by adapting the BS transmit power. Recall that the outer power control loop estimates the SIR threshold value based on Eb/N, required to achieve the target FER on the forward traffic channel. The MS estimates the Eb/Nl using the received forward traffic channel and compares the estimated Eb/N, with the corresponding outer power control loop threshold to determine the value of the PCB to be sent to the BS on the reverse power control subchannel. The estimation is performed in 1.25 ms PCG interval and a PCB is generated every PCG resulting in a PCB rate of 800 bps. A '0' PCB corresponds to an up command, meaning an increase in transmit power and a '1' PCB corresponds to a down command, meaning a decrease in transmit power. The PCB is transmitted to the BS through the reverse power control subchannel in the reverse link. The PCBs are inserted in the reverse pilot channel by a multiplexer (MUX). Each 1.25 ms PCG on the reverse pilot channel contains 1536 chips for 1.2288 MHz chip rate. The MS transmits the reverse pilot signal in the first 1152 PN chips, and transmits the reverse power control subchannel in the following 384 PN chips in each PCG on the reverse pilot channel. Each of the 384 PN chips on the reverse power control subchannel is a repetition of the PCB generated by the MS. Figure 5 illustrates the reverse power control subchannel structure. 15 Pilot (all 'O'sJ Power Control Bit Reverse Pilot Channel Pilot PpWBI 1 1 Control -*\ 384 Chips 1 Power Control Group = 1536 Chips * Hi-Figure 5 Reverse Pilot Channel Showing the Power Control Subchannel Structure (adapted from [10]) In one 20 ms frame, there are 16 PCGs, and thus 16 PCBs. The PCGs within a 20 ms frame are numbered from 0 to 15. Figure 6 shows the reverse power control subchannel and the PCGs in a 20 ms frame. Power Control Group Number Reverse Pilot Channel One Frame (20ms) ^^^^^^+J 0 1 2 3 4 5 6 7 8 • 9 10 11 12 13 14 151 \uuwnunnww EDL Frame Boundary 1 Power Control Group (1.25 ms) Reverse Pilot Channel Reverse Power Control Subchannel Frame Boundary Figure 6 Reverse Power Control Subchannel (adapted from [10]) 16 The BS adjusts its mean output power level in response to each PCB received in order to reduce the effects of the fading fluctuation and interference in the forward link channel. The nominal change in mean output power per PCB is fixed and can be 1 dB, 0.5 dB or 0.25 dB depending on the BS's setting. The total change in the closed loop mean output power is the accumulation of the valid level changes. The forward fundamental channel and forward supplemental channel have to share the reverse power control subchannel. Thus, the reverse power control subchannel is further divided into primary reverse power control subchannel and secondary reverse power control subchannel. The reverse power control subchannel carries PCB on the primary channel for the fundamental channel and on the secondary channel for the supplemental channel. The fundamental channel and supplemental channel PCBs are multiplexed onto the reverse power control subchannel. This results in reduced effective PCB per second for each traffic channel. The forward link CLPC has different modes (FPCMODE) to control the PCB rate for the fundamental and supplemental channel. The reverse power control subchannel configurations are shown in Table 1. Table 1 Reverse Power Control Subchannel Configurations (adapted from [10]) Reverse Power Control Subchannel Allocations (Power Control Group Numbers 0-15) Primary Reverse Power Control Subchannel Secondary Reverse Power Control Subchannel FPC_MODE = '000' 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Not Supported FPC_MODE = 'OOP 0, 2, 4, 6, 8, 10, 12, 14 1, 3, 5, 7, 9, 11, 13, 15 FPC_MODE = '010' 1,5, 9, 13 0, 2, 3, 4, 6, 7, 8, 10, 11, 12, 14, 15 17 Note that all IS-2000 BS transmissions are referenced to a common CDMA system-wide time scale that uses the Global Positioning System (GPS) time. The system time at various points in the transmission and reception processes is the absolute time referenced at the BS transmit antenna offset by the one-way or two-way delay of the transmission. Figure 7 shows the relation of system time at different points in the CDMA system. The BS starts transmission for the i + 1th PCG before it has finished receiving the PCB on the reverse power control subchannel from the ith PCG. BSTx MSRx MSTx BSRx 1 PCG -M-One-Way One-Way Delay Delay Figure 7 CDMA System Timing The idea of reverse link CLPC is similar to the forward link CLPC. The reverse link CLPC controls the MS to transmit enough power to achieve the target FER for the target channel. The PCB is transmitted on the forward power control subchannel, which is inserted on the forward traffic channel by puncturing the symbols according to the MS's Electronic Serial Number (ESN) and the long Pseudo-18 Noise (PN) code sequence [10]. In other words, the PCB is pseudo randomly punctured in the forward traffic channel and the PCB starting position is determined by the long PN code sequence masked by the MS's ESN. 19 3.0 Previous Work CLPC plays an important role in CDMA cellular radio systems in reducing mutual interference and compensating for time varying propagation conditions. A CLPC algorithm in which the transmitter power is increased or decreased based on a comparison of the received SIR and a threshold is proposed in [11]. This algorithm is used in IS-95 and IS-2000. In this thesis, this algorithm is referred to as the conventional CLPC algorithm. Due to the increased interest in managing radio resources efficiently, CLPC has been an area which has attracted much extensive research attention in recent years. Many variations to the conventional CLPC algorithm have been proposed, for instance, using multiple code PCBs, employing centralized power control, and modified PCB signaling [12, 13, 14]. However, most of these CLPC algorithms are not directly applicable to IS-2000 compliant systems. On the other hand, some papers have proposed methods to improve the existing CLPC algorithm. In [15], it is stated that time delays hamper the power control performance in two different ways: 1. Internal dynamics of the power control loop. 2. Delayed reactions to changes in external disturbances. Schemes to compensate for delays and predict channel fades are possible methods to overcome the performance degradation. This section examines previous studies in these two areas. 3.1 Delay Compensation The ideal behavior of the CLPC algorithm in IS-2000 is that the received SIR oscillates up and down around the threshold every alternate PCG. However, in real 20 systems, CLPC is imperfect. One of the main problems in CLPC is time delay due to measuring and reporting. CLPC is based on feedback information which may be outdated. When the power control delay is large, the power control can become ineffective. It is noted in [16] that power control performance is degraded when subject to time delays in the algorithm. Power control delay can lead to an oscillatory behavior in received power and result in larger bounds on the deviations from the desired SIR [17]. In [18], an analysis of power control in WCDMA reveals that a distributed power control algorithm, which works well under ideal circumstances, may result in large power oscillation amplitude when subject to a small delay. Since the power control command signaling is standardized, the power control delays are known exactly. Time Delay Compensation (TDC) is proposed in [18] to reduce the effects of time delays caused by internal dynamics of the power control loop and hence mitigate the power oscillation amplitudes. Let y,.[«] be the SIR measured at receiver i and TSIR be the SIR threshold used in the CLPC. Then, e,[n] = Tm-yt[n-ne], (3.1) si[n] = sign(ej[n]). (3.2) nc is from equation (1.1) and [+1 if x>0 ^nW = l-i if x<o-The signal st [n] is sent to the transmitter using a single bit command (up or clown) for power control. Assuming the power control command is the only cause for a change in the received signal power and there is no external disturbance such as fading, we can write Pi [« + !] = Pi [«] + As,, [n - (nr -1)]. (3.3) 21 where p\ri\ is the received signal power at receiver i in dB, A is the power control step size in dB, and nr is the round trip delay before the power adjustment has arrived at the receiver. Now, in order to compensate for the delays of the power control loop, an adjustment is made to the measured SIR before it is used to generate a power control decision. In logarithmic scale, let ?,["] = r,in~nc] + A_^' s,[n - j], (3.4) where f,[n] takes into account the delayed power control commands. The new decision is based on y t[n] and s, [n] = sign(TSIR - f,[n]). (3.5) When there is no external disturbance such as fading, the merits of TDC are evident since the delays are cancelled in the loop. By employing TDC, the power control algorithm exhibits lower power oscillation amplitude, which is important from a network perspective (see [18] for the proof and analysis of TDC). With power control loop delays, the amplitude of the oscillations without TDC is larger than the one with TDC as seen in Figure 8. a) 1\ •ii-Figure 8 Received SIR when Power Control Commands are Delayed by Two Slots, (a) TDC Employed and (b) No TDC (adapted from [18]) 22 3.2 Fade Prediction In a mobile radio environment, the signal quality is significantly affected by fading. Since outdated measurements used in power control result in delayed reactions to changes in external disturbances, accurate prediction of the channel fade may improve the performance of the power control loop. This is because the transmitter power can be adjusted beforehand when an upcoming fade is predicted. Prediction methods using recursive least square (RLS) algorithm and minimum mean square error (MMSE) based polynomial have been proposed [19, 20]. While all the proposed prediction methods show improvements in fade tracking capability, another important factor that determines the applicability of a prediction algorithm is complexity. On the MS side, where processing power is limited, a simpler algorithm is especially important. The use of the slope of the received SIR to predict the Rayleigh fading envelope in a multi-step SIR-based power control algorithm is discussed in [21]. The main idea is to predict the variation of Rayleigh fading from the received SIR and to track it in time. In [21], the slope of the Rayleigh fading curve is assumed to be constant during the interval between adjacent local highest and local lowest points. Figure 9 shows a block diagram of the multi-step SIR-based fade prediction power control method. 23 Mobile Station Mean Received SIR Measurement SIR ^ ~f\ \ err Power Control Command . Decision Channel Power Control ] Command i Detector J i Base Station ! i i Figure 9 Block Diagram of Multi-step SIR-based Power Control Method with Fade Prediction (adapted from [21]) In [21], the signal outage probability, which is the probability of the received SIR being less that the SIR threshold is used to access the performance of the prediction method at 900MHz and vehicle speeds from 6 to 60 km/hr. From the simulation results, the fade prediction based power control method performs better than the method without fade prediction. The algorithm in [21] is a multi-step CLPC algorithm, meaning that a multi-bit power control command is used, and the transmitter changes its output power based on the multi-bit command times the power control step size. With some modifications, the prediction idea should be applicable to the single bit CLPC algorithm used in IS-2000. However, no such studies can be found in previous works. Also, as the Doppler rate decreases in lower frequency band and increases in higher frequency band, studies on linear fade prediction in different frequency bands, for instance, the commonly used 800 MHz and 1900 MHz bands for IS-2000, are desired. Transmitter Power Prediction cmd' p Adjustment Algorithm 24 4.0 Simulation Model Many simulation studies have been carried out on CLPC [12-21]. However, most of these simulations are based on simplified models which do not include coding and interleaving. When investigating the performance of IS-2000 CLPC algorithm in different fading environments, we need to take into account the effect of coding and interleaving. It is commonly accepted that CLPC is effective at low speeds and ineffective at high speeds [16]. When errors tend to occur in bursts, interleaving is the main process to mitigate fading. As specified in [22], the QoS metric used is the FER. In this thesis, simulation is done using the physical layer model in the IS-2000 library provided by Signal Processing Worksystem® (SPW™), a software platform commonly used for system design [23]. SPW's IS-2000 library was a joint effort of Cadence and the National Institute of Standards and Technology (NIST) to provide library support for the physical layer of IS-2000. Figure 10 shows the block diagram of the forward link simulation model. Traffic Data Decoded Traffic Data Channel Encoder/ Interleaver Channel Decoder/ Deinterleaver Modulator Demodulator Pilot, Sync, Paging, OCNS Transmitter Power Control Rake Receiver Channel Figure 10 Block Diagram of SPW IS-2000 Forward Link Model 25 The Traffic Data block generates random bits to simulate the user data on the forward fundamental channel. The Channel Encoder / Interleaver block and the Modulator block implement the IS-2000 forward fundamental channel structure, which includes the convolutional encoder, interleaver, spreader, QPSK modulator, etc. The Transmitter block adds the pilot channel, overhead signaling channels (sync channel and paging channel), and orthogonal channel noise simulator (OCNS) to the user traffic channel. The OCNS simulates the users on the other orthogonal channels of a forward CDMA channel. The Transmitter block also adjusts the transmitter power according to the accumulated power control commands. The Channel block contains a Rayleigh fading simulator and an Additive White Gaussian Noise (AWGN) generator. The flat Rayleigh fading channel is simulated using Jakes' model [3]. The Power Control block executes the CLPC algorithm and is the main focus of this thesis. It measures the received SIR and makes a PCB decision every PCG. The Rake Receiver block has 3 correlator elements and uses MRC to combine the received signals. The Demodulator block and the Channel Decoder / Deinterleaver block are inverses of the IS-2000 forward link process. The received user data is collected and FER is measured in the Decoded Traffic Data block. System performance is evaluated using the test conditions defined in 3GPP2 C.S0011-A [22]. The C.S0011-A specification details definitions, methods of measurement, and minimum performance characteristics for an IS-2000 MS. Test 3.4.7, Demodulation of Forward Traffic Channel in Multipath Fading Channel with Closed Loop Power Control (FPCMODE = '000'), in [22] is used to analyze the impact of loop delays on CLPC, and compare the performances of the conventional CLPC algorithm and other CLPC algorithms. 26 All simulations are performed for the forward fundamental traffic channel, with 20 ms frames and fixed data rate. With the SPW IS-2000 model, random data is transmitted from the BS to the MS. The MS measures the Eb/Nl of the received forward fundamental traffic channel, and compares it with the Eb/Nt threshold. The PCBs are transmitted from the MS to the BS, and the BS adjusts its transmitter power accordingly. The following assumptions are made in the simulation: 1. There is no line of sight path to the MS; therefore, a Rayleigh fading model is assumed. 2. The total transmitted power of the BS is assumed to be constant in each PCG. That is, the BS will not change the transmitter power in the middle of a PCG and the transmitter power is only adjusted at the beginning of a PCG according to the PCB. 3. The mobile speed is assumed to be constant during the simulation. 4. The propagation loss and long-term fading effects are fully compensated for by the open loop power control so that the propagation loss, long-term fading and open loop power control are omitted from the simulation. 5. The data rate is fixed at 9600 bps on the forward fundamental traffic channel with R=l/4 convolutional coding as in Radio Configuration 3 [10]. 6. The outer loop power control threshold is fixed during the simulation. 7. The MS starts measuring the SIR from the beginning of each PCG for 0.625 rris (half of a PCG), and the SIR mean during the first half of the PCG is used to generate a PCB. Perfect SIR measurement is assumed. Simulations were used to verify that change in FER was negligible for an estimation error to signal power ratio of-20 dB. 27 8. Background noise is assumed to be negligible and inter cell interference is assumed to be the dominant source of interference. Therefore, the figure of merit for SIR, Eb/N,, equals to the received energy per bit to the inter cell interference power spectral density. Figure 11 shows the functional block diagram of the set-up for the simulation model. Ior is the total transmit power spectral density of the forward CDMA channel A at the BS antenna. After the channel simulator, Ior becomes Ior, which is the received power spectral density of the forward CDMA channel as measured at the MS antenna. Then, an AWGN source is used to simulate interference from other cells. The power spectral density of the AWGN source as measured at the MS antenna, Ioc, is added to Ior, to give I0, which is the total received power spectral density, including signal and interference, as measured at the MS antenna. AWGN Genera tor Base Station l loc r Tx Ior ^ Channel. lor mA S lo Simulator 0 Rx (Mobile Statio'n| Under Test Rx/T: x Figure 11 Functional Set-up for Traffic Channel Tests in Fading Channel (adapted from [22]) The BS simulation parameters for the forward CDMA channel are shown in Table 2. The Pilot Ejl„ , Sync EjIor, Paging Ec/Ior, and Traffic EjIor are the 28 ratio of the average transmit energy per PN chip for the corresponding channels to the total transmit power spectral density. The paging channel data rate is the rate of the signaling data that is sent on the forward CDMA channel. As the Traffic Ec/lor changes according to the received PCB and it is not possible to allocate unlimited power for the traffic channel when the accumulated power control commands results in continuous power increase, an upper limit is set for the Traffic Ec jIor. The Traffic Ec IIgr will be clipped at the limit when the maximum Traffic Ec /Ior is reached and the MS asks for more power by sending an up command. FPC_MODE is the reverse power control subchannel configuration for sending PCB. The power control step size is the amount of power change in response to a PCB. Table 2 BS Simulation Parameters Parameter Value Pilot Ec/lor [dB] -7 Sync Ec/lor [dB] -16 Paging Ejlor [dB] -12 Paging Channel Data Rate [bps] 4800 Maximum Traffic Ejlor [dB] -3 FPC_MODE . '000' (800 bps Primary) Power Control Step Size [dB] 0.5 The equation below describes the relationship of the different channels and the transmit power of the BS [22]. Pilot Ec Sync Ec Paging E Traffic Ec OCNS Ec , fA „ - + — C- + L + ±L L + L = l (4.1) 29 In our simulations, two different multipath configurations are used to represent rural and urban fading environments. Table 3 specifies the channel simulator configurations. All paths are independently faded. Table 3 Channel Simulator Configurations Parameter 1 path fading 3 path fading Number of Paths 1 3 Path 2 Power (Relative to Path 1) [dB] N/A 0 Path 3 Power (Relative to Path 1) [dB] N/A -3 Delay from Path 1 to Input [us] 0 o Delay from Path 2 to Input [us] N/A 2 Delay from Path 3 to Input [us] N/A 14.5 According to the two multipath configurations, the ratio of the combined received traffic channel energy per bit to the effective noise power spectral density at the MS antenna, Traffic Eb/Nt , can be described by the following two equations where Traffic_Chip_Bh is the number of PN chips per traffic channel bit [22]: One-Path Case: Traffic ^x Traffic _Chip _Bit Traffic N, Three-Path Case: Traffic Eb Traffic Ec N. X Traffic _ Chip _Bitx 2x- • + -he 3 Ioc 4 E. 5 / 5 (4.2) (4.3) 30 As the Doppler frequency is a function of carrier frequency and mobile speed, a range of carrier frequencies and mobile speeds are selected for simulations. Two common IS-2000 frequency bands are the 800 MHz cellular band and the 1.9 GHz Personal Communications Services (PCS) band. Since the forward link traffic is simulated, two BS transmitting frequencies, 870 MHz and 1.93 GHz, from the cellular band and PCS band are chosen for simulations. The channel simulation configuration specifies the channel simulator configuration from Table 3 and the mobile speed to be used. Table 4 shows the simulation parameters for the channel model. These parameters are suggested in [22]. Table 4 Channel Parameters and Target FER Channel Simulation Configuration LI loc [dB] Ioc [dBm/ 1.23 MHz] Target FER 1 path 3 km/hr 6 -61 10% 1 path 30 km/hr 4 -59 1 % 3 path 100 km/hr 2 -57 1 % In addition to the settings specified in [22], more scenarios are selected for simulations. This is because the channel parameters from [22] are selected to ensure the MS meets minimum standard requirements. To study the CLPC algorithm performance, extended coverage is needed to show the effectiveness of CLPC at different mobile speeds and channel configurations. Table 5 shows the additional simulation parameters used for simulations. 31 Table 5 Additional Channel Parameters and Target FER Channel Simulation Configuration iji0c [dB] 70C [dBm/1.23 MHz] "Target FER 1 path 50 km/hr 4 -59 1 % 1 path 100 km/hr 4 -59 1 % 3 path 30 km/hr 2 -57 1 % In our simulations, 5000 frames are run when the targeted FER is set to 10% and 10000 frames when the targeted FER is set to 1%. This translates into a minimum of approximately 500 frame errors and 100 frame errors for 10% FER and 1% FER respectively. The simulation duration and number of fade cycles for various channel simulation configurations are shown in Table 6. Table 6 Simulation Duration and Number of Fade Cycles CDMA Vehicle Speed Doppler Number of 20 Number of Frequency [km/hr] Frequency ms Frames Fade Cycles in [MHz] [Hz] Simulation 870 3 2.4 5000 241.7 30 24.2 10000 4833.3 50 40.3 10000 8055.6 100 80.6 10000 16111.1 1930 3 5.4 5000 536.1 30 53.6 10000 10722.2 50 89.4 10000 17870.4 100 178.7 10000 35740.7 At the end of a simulation, a FER will be obtained, and the Traffic Eb/Nl measured in each PCG is averaged over the simulation duration to obtain a mean 32 Traffic Eb/Nl . For each test case, two simulations are run to obtain two (mean Traffic Eb/Nt, FER) sets. The two (mean Traffic Eb/Nl, FER) sets are plotted and joined by a straight line. The mean Traffic Eb/Nt needed to achieve the target FER is used for performance evaluation.-33 5.0 Delay Compensated Fade Prediction Based Closed Loop Power Control Algorithm In the conventional CLPC algorithm, power control can become ineffective if the loop delay is large or the fade rate is high. As seen in Chapter 3, delay compensation can eliminate the delays introduced by SIR measurement and round trip delay of the power control loop. However, changes in channel conditions which occur during the loop delay are not compensated for. One method for keeping track of channel fading is fade prediction. Since a PCB command is executed every PCG and the PCB could be delayed for several PCGs, fade prediction can be disturbed in the sense that changes in measured SIR are not only caused by fading, but also by PCB command executions. Consequently, PCB commands should be taken into consideration in order to predict the channel fade more accurately. The effect of PCB command execution on fade prediction is specially significant when the Doppler frequency is low because the SIR change as a result of PCB commands may be comparable to the change in fading envelope between SIR samples. In this chapter, it is first verified that loop delays in the conventional IS-2000 CLPC algorithm produces large power oscillation amplitudes as described in [18]. Then, the linearity of Rayleigh fading is studied to access the applicability of piecewise linear fade prediction for CLPC when the PCG interval is 1.25 ms. A new CLPC algorithm that combines the benefits of both delay compensation and fade prediction is proposed. 34 5.1 Power Oscillations First, we study the effects of loop delays in the conventional IS-2000 forward link CLPC algorithm using the SPW model described in Chapter 4. A PCB is generated every PCG and we assume that the BS transmitter power is constant in each PCG. The sources of delay in PCG slot units are given in equations (1.1), (1.2) and (1.3). Figure 12 shows the effects of three different loop delays on the received Eb/Nl and BS power gain adjustment in a 1 path 3 km/hr Rayleigh fading environment. Figure 12 (a) represents the minimum delay case in our model since the total delay, nt, cannot be less than 1. Each Eb/Nl sample is compared against the threshold to generate a PCB that is sent to the BS. If the Eb/N, is above the threshold, a "down" command is generated, and if the Eb/N, is below the threshold, an "up" command is generated. The BS Tx Gain is the transmitter gain which corresponds to the accumulation of the PCBs and the difference between two consecutive BS Tx Gain samples is the power control step size (i.e. 0.5 dB in our simulations). The difference between two consecutive Eb/Nt samples is the result of changes in the BS Tx Gain, the total noise power, and the channel fading gain. It can be seen that as the loop delay increases, so does the received SIR oscillation amplitude. When the total delay, is 1 PCG, the oscillation amplitude is about ±0.5 dB around the desired value. The oscillation amplitude-is approximately ±1 dB when there is a 2 PCG delay, and approximately ±1.5 dB when there is a 3 PCG delay. Simulation results show that when TDC is employed, the oscillation amplitudes in Figure 12(b) and (c) are reduced, and the received Eb/Nl and BS power gain adjustment with 2 PCG delay or 3 PCG delay are similar to those with 1 PCG delay 35 as shown in Figure 12(a). The simulation results indicate that TDC stabilizes the power control algorithm by reducing the power oscillation amplitude. When the Doppler frequency is low, the merit of TDC is clear. However, when the Doppler frequency increases and the change in channel gain between adjacent PCGs becomes larger, the change in SIR can be larger than what the power control step size can compensate for. In this case, large power oscillation amplitudes are often unavoidable. TDC is most effective when the change in channel gain is comparable to the power control step size. Figure 13 shows the effects of three different loop delays on the received Eb/Nt and BS power gain adjustment in a more rapidly changing channel environment, namely the 1 path 30 km/hr Rayleigh fading environment. We can see that the differences between consecutive samples in the first 40 faded Eb/Nl samples have a magnitude comparable to the power control step size, and TDC can reduce the oscillation amplitude. However, TDC cannot reduce the oscillation amplitudes when the change in fading envelope is large, as in samples 40 to 100 in Figure 13. 36 4r . . er >l . • • . . -6 I . • • • • 0 20 40 60 80 100 0 20 40 60 80 100 Sample Number Sample Number (a) 1 PCG Delay 0 20 40 60 80 100 O 20 40 60 80 100 Sample Number Sample Number (b) 2 PCG Delay (c) 3 PCG Delay Figure 12 Effects of Power Control Delay on Received Eb/N, and BS Tx Gain in 1 path 3 km/hr Rayleigh Fading 37 (a) 1 PCG Delay 0 20 40 60 80 100 Sample Number (b) 2 PCG Delay £ 0 8 0 20 40 60 BO 100 Sample Number (c) 3 PCG Delay ure 13 Effects of Power Control Delay on Received Eb/Nt and BS Tx Gain in path 30 km/hr Rayleigh Fading 38 5.2 Fade Linearity In [21], it is proposed that the slope of the fading curve can be used to predict future fades. In this section, the linearity of Rayleigh fading is studied. Figure 14 shows the Rayleigh fading envelopes for different channel environments at 870 MHz with a sample period of 1.25 ms. Future channel conditions can be predicted using linear extrapolation, i.e. x[n + a] - (x[n]-x[n-i])-a +x[n] . The most recent SIR sample and the preceding SIR sample in linear scale can be used to estimate the slope of the fading curve for predicting channel conditions. Ideally, the Eb/Nt measured in PCG i is used to generate a PCB that is sent in PCG i to control the power in PCG i + l. This happens when nt = 1. Without fade prediction and assuming the PCB is delayed by nt > 1 PCG (i.e. PCB generated using Eb/Nt measured in PCG i is executed in PCG i + nt), the Eb/Nt error is the difference between the Eb/Nt measured in PCG i delay compensated by the nt -1 previously sent PCBs, and the actual Eb/N, in PCG i + ra,-1 . Note that PCG i + n, -1 immediately precedes the PCG in which the currently generated PCB (i.e. in PCG i + nc) is executed. Using linear extrapolation to predict fade can improve the accuracy of the estimated Eb/N, . However, the predicted value may differ significantly from the actual value when the fading curve passes through local maxima and minima. Therefore, prediction performance will degrade when the number of local maxima and minima increases in a given time period. In a cellular environment with pedestrian and vehicular users, the advantage of using linear fade prediction can be significant when the user mobility is low or moderate. 39 0 10 20 30 40 50 60 70 BO 90 100 (a) One Path 3 km/hr Rayleigh Fading | RayteghFadrngErwclcpe || 0 10 20 30 40 50 60 70 SO 90 100 Sample Number (c) One Path 50 km/hr Rayleigh Fading Sample Number (b) One Path 30 km/hr Rayleigh Fading 10, 0 10 20 30 40 50 60 70 B0 90 100 Sample Number (d) One Path 100 km/hr Rayleigh Fading | — Raytefr Fadrq Envelope | ,51 • , • , , , , , 1 0 10 20 30 40 50 60 70 SO 90 100 Sample Number (e) Three Path 30 km/hr Rayleigh Fading (f) Three Path 100 km/hr Rayleigh Fading Figure 14 Rayleigh Fading Envelopes for Different Channel Environments at 870 MHz 40 Assuming changes in SIR are only caused by fading and ignoring PCB execution for the moment, we study how prediction can improve SIR estimation in the presence of loop delays. Table 7 shows the MSE between the fading envelope values at time n and n + a with and without the use of prediction. Table 7 MSE Comparisons of Fade Envelopes with No Prediction and with Linear Prediction No Prediction MSE: average value of (x[n] - x[n + a]f Linear Prediction MSE: average value of ((x[n] - x[n - !])• a + x[n] - x[n + a]f Channel Simulation Configuration a No Prediction MSE Linear Prediction MSE 1 path 3 km/hr 1 3.32e-4 8.37e-7 2 1.33e-3 4.13e-6 1 path 30 km/hr 1 3.50e-2 2.74e-3 2 1.37e-l 2.41e-2 1 path 50 km/hr 1 9.27e-2 1.94e-2 2 3.51e-l 1.64e-l 1 path 100 km/hr 1 3.46e-l 2.68e-l 2 1.12 1.90 3 path 30 km/hr 1 3.82e-3 4.07e-4 2 1.49e-2 3.49e-3 3 path 100 km/hr 1 3.80e-2 3.55e-2 2 1.16e-l 2.23e-l With linear prediction, the MSE is reduced at low and moderate speeds (less than or equal to 50km/hr), and is about the same or worse (depending on delay) at high speed. Recall that local maxima or minima degrade fade prediction accuracy. This explains why the MSE with prediction is larger at high mobile speeds. Note that Table 7 only shows how prediction can improve the MSE of the Eb/N, estimation when there are loop delays. Since there is no simple relationship between the received 41 Eb/Nt and FER, computer simulations will be used to show the FER performance improvements when fade prediction is used in the CLPC algorithm. 5.3 Proposed Closed Loop Power Control Algorithm Based on the available information from previous works and simulation results using the SPW IS-2000 model, a new CLPC algorithm using delay compensation and linear fade prediction is proposed. The proposed CLPC algorithm can be easily implemented in software for both the forward link and reverse link traffic channels. No modifications are required in the IS-2000 standard, the mobile terminal hardware, or the base station hardware. The only component in the cellular system that has to be changed is the firmware which generate the PCBs. This new CLPC algorithm is not only applicable to IS-2000, but can also be used in other power controlled CDMA systems employing a command-based, threshold comparing CLPC scheme. Figure 15 (a) shows the block diagram of the conventional CLPC algorithm. The MS measures the Eb/Nt and compares the measured value against a threshold value to make a decision on the PCB. The algorithm is simple and straightforward. Figure 15 (b) shows the block diagram of the proposed CLPC algorithm. The MS measures the Eb./N, in the same way as for the conventional CLPC algorithm. But the measured Eb/Nl is further processed to improve the accuracy of the estimated channel condition. The new prediction block performs delay compensation and linear fade prediction using past PCB decisions and Eb/Nt samples. For n, > 1, the proposed CLPC algorithm expressed in a linear scale is P,M = fo[n-nc]-fi[n-l-^ 42 Mobile Station Mean Received SIR Measurement SIR Desired Level Power Control Command Decision Transmitter Power Adjustment cmd * p Power Control Command Detector Base Station (a) Conventional CLPC Algorithm Mobile Station Desired Level Mean Received SIR Measurement Channel Transmitter Power Adjustment SIR . Prediction Algorithm err Power Control Command Decision cmd * p cmd Power Control Command Detector Base Station (b) Proposed CLPC Algorithm Figure 15 Conventional CLPC Algorithm and Proposed CLPC Algorithm 43 First, the second last measured SIR, ^[n-l-nj, is power adjusted using the PCB that was sent as s^n-n,] and executed in PCG n — nc. This power adjusted SIR is subtracted from the latest measured SIR, y \n- nc ], to give the slope of the fading envelope. Second, fading envelope is linearly extrapolated for nt -1 PCG slots. Finally, the extrapolated fade envelope is added to the latest measured SIR, and the "(-' 2>["-.n delay compensated PCBs, AJ=1 , are used to adjust the SIR estimation. f,[n], the SIR estimation with delay compensation and fade prediction, is then compared against the threshold to generate a PCB just like the conventional CLPC algorithm. Comparing Figure 15 (b) with Figure 9 in Chapter 3, we note that the two block diagrams differ in the locations of the prediction algorithms. In IS-2000, the BS does not know the power control threshold of the MS since the MS's outer loop power control algorithm maintains the threshold locally. Due to this reason, in order to use the improved SIR estimation with the threshold, the prediction block must reside in the MS. 5.4 System Capacity Capacity is defined as the number of simultaneous users which the system can support while the radio link conditions of all users still meet QoS requirements. In IS-2000, the QoS requirement is stated in terms of the FER. In a CDMA system, each user accessing the system is power controlled so that system resources can be shared equitably among users and capacity maximized. Due to the interference limited nature of CDMA networks, any reduction in interference translates directly into an increase in capacity [24]. For completeness, this section summarizes the relationship between CDMA capacity and SIR from [24, 25]. 44 In digital communications, Eb/N0 is often used as the radio link metric [4]. In [22], Eb/Nt refers to the Eb/Ng at the MS antenna. This quantity can be related to the SIR. We will start with a simplified SIR definition in a single cell environment, and then refine the equation according to the forward link and reverse link characteristics of IS-2000 in a multi-cell environment. We first consider a single cell CDMA system with M users, in which all the user signals are assumed to be perfectly power controlled and each is received with power S . Let J] be the background noise due to spurious interference as well as thermal noise. Then, a simplified SIR expression that ignores various performance factors (e.g. voice activity and sectorization gain) at any receiver is SIR =  —. (5.2) (M-l)S + n (M-\) + TJ/S This is so because the total interference power in the band is equal to the sum of powers from individual users and the background noise. To get Eb/Na , whose numerator is obtained by dividing the desired signal power by the information bit rate, R, and the denominator is obtained by dividing the noise (or interference) by the total bandwidth, W, equation (5.2) becomes E/N= = W/R (53) bl " ((M-l)S + 7])/W (M-l) + n/S The term W/R is generally referred to as the processing gain. Therefore, the capacity in terms of number of users supported is M=WJR_1 + 1 EJN0 S 45 Generally,n/S is small. As shown in equation (5.4), the capacity in terms of number of simultaneous users is approximately inversely proportional to Eb/N0 . Next, we show the capacity equations for IS-2000 forward link and reverse link. 5.4.1 Multi-cell IS-2000 Forward Link Capacity Sectorization is used in IS-2000 to improve capacity. Typically, three antennas per cell site, each having a 120° effective beam width, are used to reduce mutual interference. With three sectors, M = 3MS where M s is the number of users in each sector. In a multi-cell environment, more forward link power must be provided to users near the boundaries of cells because they receive more interference from other cell-site transmitters [25]. Suppose that MS i, communicating via the sector 1 antenna, receives power STI from the sector 1 BS, and MS i can receive a total of K signal powers from K different sector antennas. Therefore, the total power received K by MS i is ^ST and ST for j #1 are interference powers. For MS i to select the sector 1 BS as the home BS, ST should be the largest power among all the received signal powers. Let STI > SH > ... > STK >0. (5.5) In general, a fraction of the total power transmitted by any sector is devoted to the pilot signal and other overhead signals destined to all MS's. The remaining fraction p is then allocated to all M s users of the sector. Let fr be the relative received sector power at MS i where r v j-2 i = l,...,Ms. (5.6) 46 Then, it can be shown that [25] f=i Lb/No .=1 \ The background noise is usually negligible even when compared to the smallest received sector power from the home BS of any MS, i.e. min{5ri ,STt ,...,STi }. Therefore, the second sum in the right hand side of (5.7) is almost negligible. As the Eb/N0 requirement in the system is lowered, the value in the right hand side of (5.7) increases. However, the relative received sector power at MS i , ft, remains unchanged when Eb/N0 changes. Therefore, more users can be added to the system when the Eb/N0 requirement is lowered. For a given decrease in Eb/N0 , the number of users which can be added depends on their relative received sector powers, fi. The smaller these powers are, the larger is the number of additional users which can be supported, e.g. more MS's can be supported if they are close to their home BS's. 5.4.2 Multi-cell IS-2000 Reverse Link Capacity Similarly, we can estimate the reverse link capacity. In the reverse link, although MS's communicating via different sector antennas are power controlled by their respective BS's, the signal powers from these MS's constitute interference to the neighboring cells. Therefore, a loading factor /., which typically has a value between 0% and 100%, is used to account for this interference [26]. Furthermore, a fraction of the total power transmitted by the MS is devoted to the reverse pilot signal. The remaining fraction S is then used for traffic channel signal. Equation (5.3) then becomes 47 EJK-_ *"* . (5.8) (M.-1X1 + 0 + I7/S The capacity is „,.(i*Z«_lXJL) + ,. (5.9) The reverse link capacity is seen to be approximately inversely proportional to EJN0 . From the capacity analyses of the forward link and reverse link, it can be seen that a reduction in the Eb/Na requirement results in an increase in the system capacity. 48 6.0 Simulations In power controlled cellular networks, a power competition between users occurs since a power increase by one transmitter creates additional interference to unintended receivers, which can result in the receivers contending for more power to improve their SIR. The opposite is true when one transmitter reduces its power and the overall interference is reduced. The proposed CLPC algorithm can reduce power oscillation amplitude and improve SIR estimation, which means less fading margin is needed and the mutual interference in the system is reduced. In this chapter, system simulations using the IS-2000 model described in Chapter 4 are used to illustrate the performance of the proposed CLPC algorithm. Simulation runs have been carried out by changing the total delay, nt, and the channel condition. The effect of PCB errors on the proposed CLPC algorithm performance is also studied using system simulations. The numerical results from simulations are presented in sections 6.1, 6.2 and 6.3, and the results are analyzed in section 6.4. 6.1 Numerical Results for 800 MHz Band We first study the effect of loop delays on FER. The various delay values considered are n, = 1, 2 and 3 PCG slots. Furthermore, we compare the FER performance of the conventional and the proposed CLPC algorithms. Two results for the proposed CLPC algorithm, Proposed(D) and Proposed(D+0.5), where D is the number of PCG slots that is linearly extrapolated (D=«,-l) in order to obtain a SIR estimation are run. The two results show the performance of the proposed CLPC algorithm from equation (5.1) when linear extrapolation is used to predict fade values D PCG slots and D+0.5 PCG slots ahead. In our simulations, we use half of a PCG to 49 measure SIR and the SIR measurement is available in the middle of the PCG slot. As a PCB is executed at the beginning of a PCG, there is a gap of 0.5 PCG between the SIR estimation using Proposed(D) and the execution of the corresponding PCB. Since the channel condition is changing over time, Proposed(D) and Proposed(D+0.5) show the outcome of including the 0.5 PCG delay in the prediction algorithm. Figure 16 illustrates the difference between Proposed(D) and Proposed(D+0.5). Propos_ed(D+0.5)_ Proposed(D) ' PCB execution 0.5 PCG gap V | PCB execution -2H 1 PCG Figure 16 Difference between Proposed(D) and Proposed(D+0.5) Figure 17 illustrates the effects of delays on FER in a 1 path 3 km/hr Rayleigh fading environment at 870 MHz. The minimum FER requirement stated in [22] and the FER performance without any CLPC are shown for comparison purposes. As expected, the FER performance is degraded when loop delay is increased. Figure 18 and Figure 19 compare the proposed CLPC algorithm against the conventional CLPC algorithm in a 1 path 3 km/hr Rayleigh fading environment at 870 MHz when delay is 2 and 3 PCG respectively. 50 Similarly, different channel configuration simulations were run following the above structure. Table 8 summarizes the 800 MHz band simulation figures. Table 8 Summary of 800 MHz Band Simulation Figures Channel Configuration Description Figure Number 1 path 3 km/hr Effects of PCG delays on FER Figure 17 Comparison of conventional and proposed algorithms when n, = 2 Figure 18 Comparison of conventional and proposed algorithms when n, = 3 Figure 19 1 path 30 km/hr Effects of PCG delays on FER Figure 20 Comparison of conventional and proposed algorithms when nt - 2 Figure 21 Comparison of conventional and proposed algorithms when nt = 3 Figure 22 3 path 100 km/hr Effects of PCG delays on FER Figure 23 Comparison of conventional and proposed algorithms when nt - 2 Figure 24 Comparison of conventional and proposed algorithms when nt = 3 Figure 25 1 path 50 km/hr Effects of PCG delays on FER Figure 26 Comparison of conventional and proposed algorithms when nt = 2 Figure 27 Comparison of conventional and proposed algorithms when nt = 3 Figure 28 1 path 100 km/hr Effects of PCG delays on FER Figure 29 Comparison of conventional and proposed algorithms when nt - 2 Figure 30 Comparison of conventional and proposed algorithms when nt = 3 Figure 31 3 path 30 km/hr Effects of PCG delays on FER Figure 32 Comparison of conventional and proposed algorithms when nt '= 2 Figure 33 Comparison of conventional and proposed algorithms when nt = 3 Figure 34 51 RC3 Forward Fundamental Channel -•-C.S0011-A -*-NoCLPC —^—'Conventional Delay=l * Conventional Delay=2. —Conventional Delay=3 1 \ \\y IV IV \\ IV 1 i i i i i i i i . i i i i i i i i 1.9 3.9 5.9 7.9 9.9 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±7.3% ±8.9% Conventional Delay=l ±7.7% ±16.3% Conventional Delay=2 ±7.6% ±16% Conventional Delay=3 ±7.4% ±14.9% Figure 17 Effects of PCG Delays on FER (1 path 3 km/hr Rayleigh Fading at 870 MHz) 52 RC3 Forward Furxtemental Channel • Conventional Delay=2 —•— Proposed(l) Delay=2 Proposed(1.5) Delay=2 1 £ 0.1 "IS. U.U1 1.9 2.1 2.3 2.5 2.7 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±7.6% ±16% Proposed(l) Delay=2 ±7.7% ±16.5% Proposed(1.5) Delay=2 ±7.8% ±16.6% Figure 18 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 3 km/hr Rayleigh Fading at 870 MHz) 53 RC3 Forward Fundamental Channel -Conventional Delay-3 —•— Proposed(2) Delay-3 &• Proposed(2.5) Delay-3 1 iij 0.1 ii>i i i < > U.U1 1.9 2.1 2.3 2.5 2.7 2.9 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±7.4% ±14.9% Proposed(2) Delay=3 ±7.8% ±16.6% Proposed(2.5) Delay=3 ±7.8% ±16.8% Figure 19 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 3 km/hr Rayleigh Fading at 870 MHz) 54 RC3 Forward Fundamental Channel -•-C.S0011-A -"-No CLPC ~A— Conventional Delay=l Conventional Delay=2 X Conventional Delay=3 0.1 [±j 0.01 \ \ V \ \ K_ \ \ "i 1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7.4 8.4 9.4 10.4 11.4 12.4 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±18.9% •• ±23.3% Conventional Delay=l ±17.5% ±35.8% Conventional Delay=2 ±14.1% ±26.9% Conventional Delay=3 , ±11.6% ±1.9.5% Figure 20 Effects of PCG Delays on FER (1 path 30 km/hr Rayleigh Fading at 870 MHz) 55 RC3 Forward Fundamental Channel • Conventional Delay=2 —Proposed(l) Delay=2 _*~ Proposed(l.5) Delay=2 0.1 £ 0.01 -I U.UU1 7.5 8 8.5 9 9.5 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±14.1% ±26.9% Proposed(l) Delay=2 ±17.5% ±34.7% Proposed(1.5) Delay=2 ±18.2% ±35.2% Figure 21 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 30 km/hr Rayleigh Fading at 870 MHz) 56 RC3 Forward Fundamental Channel Conventional Delay=3 —•— Proposed© Delay=3 Proposed(2.5) Delay=3 0.1 fr] 0.01 1 L_J L_ 1 1 1 1 1 I 1 7.6 8.1 8.6 9.1 9.6 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±11.6% ±19.5% Proposed(2) Delay=3 ±16.4% ±34.7% Proposed(2.5) Delay=3 ±16.9% ±34.7% Figure 22 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 30 km/hr Rayleigh Fading at 870 MHz) 57 RC3 Forward Fuixiamental Channel -•-C.S0011-A -"-NoCLPC Conventional Delays 1 —*~ Conventional Delay=2 * Conventional Deiay=3 0.1 Vv\ \ \ \ \ \ \ \ \ \\ \ \ * X i V f" \ 1 I 1 1 i : 1 1 i i i i >III 1.9 2.9 3.9 4.9 5.9 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±11.8% ±30.7% Conventional Delay=l ±9.6% ±29.4% Conventional Delay=2 ±9.6% ±27.7% Conventional Delay=3 ±9.2% ±26.7% Figure 23 Effects of PCG Delays on FER (3 path 100 km/hr Rayleigh Fading at 870 MHz) 58 RC3 Forward Fundamental Channel —•— Conventional Delay=2 —•— Proposed(l) Delay=2 "A™ Proposed(1.5) Delay=2 0.1 I 1 1 1 1 1 1 0.001 1.9 2.1 2.3 2.5 2.7 Traffic Eb/Nt(dB) 2.9 3.1 Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±9.6% ±27.7% Proposed(l) Delay=2 ±9.4% ±28.2% Proposed(1.5) Delay=2 ±9.1% ±26% Figure 24 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 100 km/hr Rayleigh Fading at 870 MHz) 59 RC3 Forward Fundamental Channel Conventional Delay=3 • Proposed© Delay=3 Proposed(2.5) Delay=3 0.1 1 -• • 1 '"A i i i i 1 1 1 ! 1 1 1 1 i i I I 2 2.2 2.4 2.6 2.8 3 3.2 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±9.2% ±26.7% Proposed(2) Delay=3 ±9.1% ±24.1% Proposed(2.5) Delay=3 ±8.9% ±23.2% Figure 25 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 100 km/hr Rayleigh Fading at 870 MHz) 60 RC3 Forward Fundamental Channel -•-No CLPC —•— Conventional Delay-1 —•is— Conventional Delay=2 ~Conventional Delay=3 0.1 0.001 _J I l_ 7.4 8.4 9.4 10.4 Traffic Eb/N,(dB) 11.4 Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±16.5% ±27.7% Conventional Delay=l ±19% ±37.6% Conventional Delay=2 ±15.4% ±28.2% Conventional Delay=3 ±13.2% ±24.1% Figure 26 Effects of PCG Delays on FER (1 path 50 km/hr Rayleigh Fading at 870 MHz) 61 RC3 Forward Fundamental Channel • Conventional Delay=2 —•— Proposed(l) Delay=2 • Proposed(l .5) Delay=2 0.1 £ 0.01 1 1 1 1 1 1 1 1 1 U.UU1 7.5 8 8.5 9 9.5 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±15.4% ±28.2% Proposed(l) Delay=2 ±17.5% ±35.8% Proposed(1.5) Delay=2 ±17.9% ±36.4% Figure 27 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 50 km/hr Rayleigh Fading at 870 MHz) 62 RC3 Forward Fundamental Channel Conventional Delay=3 " Proposed© Delay=3 -~A'~"Proposed(2.5) Delay=3 0.1 1 1 1 1 1 1 1 1 ' 1 1 1 1 I 1 1 1 7.8 8.3 8.8 9.3 9.8 Traffic Eb/N,(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±13.2% . ; • ±24.1% . Proposed(2) Delay=3 ±16.6% ±33.2% " Proposed(2.5) Delay=3 ±16.7% ±32.4% Figure 28 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 50 km/hr Rayleigh Fading at 870 MHz) 63 RC3 Forward Furxjamental Channel -•-No CLPC —•— Conventional Delay=l Conventional Delay=2 XConventional Delay-3 0.1 fn 0.01 • • . • -i i i i 1 I [ 1 1 1 1 1 1 6.4 6.9 7.4 7.9 8.4 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±13.4% ±24.5% Conventional Delay=l ±18.9% ±31.9% Conventional Delay=2 ±15.9% ±25.9% Conventional Delay=3 ±14.6% ±21.8% Figure 29 Effects of PCG Delays on FER (1 path 100 km/hr Rayleigh Fading at 870 MHz) 64 RC3 Forward Funclamental Channel • Conventional Delay=2 —•— Proposed(l) Delay=2 —&~ Proposed(1.5) Delay=2 0.1 £ 0.01 -—.» ~-—^ m IIII IIII IIII 111! IIII U.UU1 6.6 6.8 7 7.2 7.4 7.6 7.8 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±15.9% ±26% Proposed(l) Delay=2 ±18.4% ±27.9% Proposed(1.5) Delay=2 ±18.9% ±29.2% Figure 30 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 100 km/hr Rayleigh Fading at 870 MHz) 65 RC3 Forward Fundamental Channel • Conventional Delay=3 —*— Proposed(2) Delay=3 Proposed(2.5) Delay=3 0.1 rH 0.01 i i i i IIII 6.8 7 7.2 7.4 7.6 7.8 8 8.2 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±14.6% ±21.9% Proposed(2) Delay=3 ±17.1% ±30.1% Proposed(2.5) Delay=3 ±17.3% ±27.9% Figure 31 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 100 km/hr Rayleigh Fading at 870 MHz) 66 RC3 Forward Fundamental Channel -•-No CLPC —•— Conventional Delay=1 —*v- Conventional Delay=2 >< Conventional Delay-3 0.1 £ 0.01 •---/> \ .... \ \ \ \ x * \ \ • \\ \ \ \ \ \\ \ \ "'\ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.9 2.4 2.9 3.4 3.9 4.4 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±7.8% ±25.7% Conventional Delay=l ±8.9% ±26.9% Conventional Delay=2 ±8.8% ±25.5% Conventional Delay=3 ±8.3% ±18.9% Figure 32 Effects of PCG Delays on FER (3 path 30 km/hr Rayleigh Fading at 870 MHz) 67 RC3 Forward Fundamental Channel Conventional Delay=2 —•— Proposed(l) Delay=2 —£— Proposed(1.5) Delay=2 0.1 ^ 0.01 ^\ X •X. 1 1 1 1 • III i 1 1 1 1 1 1 1 1.9 2.1 2.3 2.5 2.7 2.9 3.1 Traffic Eb/N,(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±8.8% ±25.5% Proposed(l) Delay=2 ±9% ±27.2% Proposed(1.5) Delay=2 ±9.1% ±28.8% Figure 33 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 30 km/hr Rayleigh Fading at 870 MHz) 68 RC3 Forward Fundamental Channel Conventional Delay=3 -*- Proposed(2) Delay=3 Proposed(2.5) Delay=3 o.i i 1 1 1 1 1 1—I 2 2.2 2.4 2.6 2.8 3 3.2 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±8.3% ±18.9% Proposed(2) Delay=3 ±9.2% ±26.6% Proposed(2.5) Delay=3 ±9.3% ±29.1% Figure 34 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 30 km/hr Rayleigh Fading at 870 MHz) 69 6.2 Numerical Results for 1.9 GHz Band Another popular carrier frequency used for IS-2000 is in the 1.9 GHz band. Fading is more severe in the 1.9 GHz band when compared to the 800 MHz band for the same mobile speed because the Doppler frequency is higher. Table 9 summarizes the 1.9 GHz band simulations figures. Table 9 Summary of 1.9 GHz Band Simulation Figures Channel Configuration Description Figure Number 1 path 3 km/hr Effects of PCG delays on FER Figure 35 Comparison of conventional and proposed algorithms when nt = 2 Figure 36 Comparison of conventional and proposed algorithms when nt = 3 Figure 37 1 path 30 km/hr Effects of PCG delays on FER Figure 38 Comparison of conventional and proposed algorithms when nt =2 Figure 39 Comparison of conventional and proposed algorithms when nt = 3 Figure 40 3 path 100 km/hr Effects of PCG delays on FER Figure 41 Comparison of conventional and proposed algorithms when n, = 2 Figure 42 Comparison of conventional and proposed algorithms when n, - 3 Figure 43 1 path 50 km/hr Effects of PCG delays on FER Figure 44 Comparison of conventional and proposed algorithms when nt =2 Figure 45 Comparison of conventional and proposed algorithms when nt = 3 Figure 46 1 path 100 km/hr Effects of PCG delays on FER Figure 47 Comparison of conventional and proposed algorithms when nt =2 Figure 48 Comparison of conventional and proposed algorithms when nl = 3 Figure 49 3 path 30 km/hr Effects of PCG delays on FER Figure 50 Comparison of conventional and proposed algorithms when nt =2 Figure 51 Comparison of conventional and proposed algorithms when nt = 3 Figure 52 70 RC3 Forward Fundamental Channel -•— C.S0011-A —•— No CLPC Conventional Delay=l Conventional Delay=2 -Conventional Delay=3 1 2.2 4.2 6.2 8.2 10.2 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±8.3% ±11% Conventional Delay=T ±7.2% ±13.7% Conventional Delay=2 ±6.9% ±12.7% Conventional Delay=3 ±6.4% ±11.1% Figure 35 Effects of PCG Delays on FER (1 path 3 km/hr Rayleigh Fading at 1.93 GHz) 71 RC3 Forward Fundamental Channel -•— Conventional Delay=2 —•— Proposed(l) Delay=2 —&— Proposed(1.5) Delay=2 1 al it! 0.1 IIII U.U1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±6.9% ±12.7% Proposed(l) Delay=2 ±7.2% ±13.6% Proposed(1.5) Delay=2 ±7.4% ±14.3% Figure 36 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 3 km/hr Rayleigh Fading at 1.93 GHz) 72 RC3 Forward Fuixlamental Channel • Conventional Delay=3 —•— Proposed© Delay=3 —Proposed(2.5) Delay=3 "Ik 1 1 1 1 IIII i i i i 2.4 2.6 2.8 3 3.2 3.4 3.6 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±6.5% ±11.2% Proposed(2) Delay=3 ±7.3% ±14% Proposed(2.5) Delay=3 ±7.5% ±15% Figure 37 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 3 km/hr Rayleigh Fading at 1.93 GHz) 73 RC3 Forward Fundamental Channel -•— C.S001 l-A -•-No CLPC Conventional Delay=l Conventional Delay=2 * Conventional Delay=3 0.1 i 1 1 1 1 1 6.6 7.6 8.6 9.6 10.6 Traffic Eb/N,(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±17.7% ±42.4% Conventional Delay=l ±16.8% ±43.3% Conventional Delay=2 ±14.5% ±34.7% Conventional Delay=3 ±13.2% ±30.4% Figure 38 Effects of PCG Delays on FER (1 path 30 km/hr Rayleigh Fading at 1.93 GHz) 74 RC3 Forward Fundamental Channel —•— Conventional Delay=2 —•— Proposed(l) Delay=2 ~*— Proposedd .5) Delay=2 0.1 [H 0.01 - - • A. 1 1 1 1 i i i i 6.9 7.4 7.9 8.4 8.9 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±14.5% ±34.7% Proposed(l) Delay=2 ±16.4% ±39.8% Proposed(1.5) Delay=2 ±16.2% ±41.5% Figure 39 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 30 km/hr Rayleigh Fading at 1.93 GHz) 75 RC3 Forward Fundamental Channel —•— Conventional Delay=3 —•— Proposed(2) Delay=3 Proposed(2.5) Delay=3 o.i i : 1 1 1 r~i 0.001 1—1 1 1 '—1 1 1 11111—1 < ' 1 1 ' 1 7.2 7.7 8.2 8.7 9.2 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±13.2% ±30.4% Proposed(2) Delay=3 ±15.2% ±37% Proposed(2.5) Delay=3 ±15.5% ±39% Figure 40 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 30 km/hr Rayleigh Fading at 1.93 GHz) 76 RC3 Forward Fundamental Channel -•-C.S0011-A -"-No CLPC "6- Conventional Delay=l Conventional Delay=2 * Conventional Delay=3 0.1 rH 0.01 \\\ \\\ \ \\\\ \\\\ AW \V W v\\ 1 1 1 1 IIII IIII 1111 1 1.7 2.7 3.7 4.7 5.7 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±14.2% ±41.5% Conventional Delay=l ±9.1% ±21.1% Conventional Delay=2 ±9.1% ±28.5% Conventional Delay=3 ±8.9% ±26.7% Figure 41 Effects of PCG Delays on FER (3 path 100 km/hr Rayleigh Fading at 1.93 GHz) 77 RC3 Forward FurxJamental Channel -•"- Conventional Delay=2 —•— Proposed(l) Delay=2 Proposed(l.5) Delay=2 0.1 8f 0.01 1 1 1 1 1 1 1 1 1.7 1.9 2.1 2.3 2.5 2.7 2.9 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±9.1% ±28.5% Proposed(l) Delay=2 ±7.8% ±21.1% Proposed(1.5) Delay=2 ±7.4% ±19.5% Figure 42 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 100 km/hr Rayleigh Fading at 1.93 GHz) 78 RC3 Forward Furxtemental Channel • Conventional Delay=3 -•- Proposed(2) Delay=3 —A— Proposed(2.5) Delay=3 0.1 I i 1 1 1 1 1 1 Q I 1 1 1 1 I I I I I I I I—I I I I I I I I I I I I I I I I I I I I I I I 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 Traffic Eb/N,(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±8.9% ±26.7% Proposed(2) Delay=3 ±10.9% ±33.7% Proposed(2.5) Delay=3 ±10.6% ±29.4% Figure 43 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 100 km/hr Rayleigh Fading at 1.93 GHz) 79 RC3 Forward Furxiamental Channel -•-No CLPC —•— Conventional Delay-1 Conventional Delay=2 >< Conventional Delay-3 0.1 §J 0.01 —X;— i i i i iii] i i i i 1 1 1 L_— i I i i 5.6 6.1 6.6 7.1 7.6 8.1 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±9.9% ±22.9% Conventional Delay=l ±13.3% ±45.5% Conventional Delay=2 ±12.6% ±33.7% Conventional Delay=3 ±11.2% ±32.8% Figure 44 Effects of PCG Delays on FER (1 path 50 km/hr Rayleigh Fading at 1.93 GHz) 80 RC3 Forward Fundamental Channel —•— Conventional Delay=2 —•— Proposed( 1) Delay=2 —•&-*• Proposed( 1.5) Delay=2 o.i i 1 1 1 1 1 fn 0.01 5.9 6.4 6.9 7.4 7.9 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±12.6% ±33.7% Proposed(l) Delay=2 ±12.8% ±46.7% Proposed(1.5) Delay=2 ±13.7% ±45.5% Figure 45 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 50 km/hr Rayleigh Fading at 1.93 GHz) 81 RC3 Forward Funciamental Channel • Conventional Delay=3 —B— Proposed(2) Delay=3 ~&~ Proposed(2.5) Delay=3 0.1 i 1 1 1 r n 6.1 6.6 7.1 7.6 8.1 8.6 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±11.2% ±32.8% Proposed(2) Delay=3 ±13.2% ±38.3% Proposed(2.5) Delay=3 ±13.4% ±38.3% Figure 46 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 50 km/hr Rayleigh Fading at 1.93 GHz) 82 RC3 Forward Funclamental Channel -•—No CLPC —•— Conventional Delay=1 —iii— Conventional Delay=2 X Conventional Delay-3 0.1 0.001 • i • • i i i 4.9 5.4 5.9 6.4 6.9 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±19.1% ±42.4% Conventional Delay=l ±13.8% ±35.2% Conventional Delay=2 ±13.5% ±26.9% Conventional Delay=3 ±12% ±23.8% Figure 47 Effects of PCG Delays on FER (1 path 100 km/hr Rayleigh Fading at 1.93 GHz) 83 RC3 Forward Fundamental Channel • Conventional Delay=2 —•— Proposed(l) Delay=2 Proposed(l .5) Delay=2 0.1 i 1 1 1 1 5.1 5.6 6.1 . 6.6 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±13.5% ±26.9% Proposed(l) Delay=2 ±15% ±31.5% Proposed(1.5) Delay=2 ±14% ±33.7% Figure 48 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 100 km/hr Rayleigh Fading at 1.93 GHz) 84 RC3 Forward Fundamental Channel Conventional Delay=3 —Proposed(2) Delay=3 —A—Proposed(2.5) Delay=3 0.1 £ 0.01 X. s\ s. 1 1 1 1 1 ! 1 1 1 1 1 1 i i i i 5.1 5.6 6.1 6.6 7.1 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±12% ±23.8% Proposed(2) Delay=3 ±13.3% ±25.8% Proposed(2.5) Delay=3 ±13.4% ±25.6% Figure 49 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 100 km/hr Rayleigh Fading at 1.93 GHz) 85 RC3 Forward Fundamental Channel -•- No CLPC M Conventional Delay=l Conventional Delay=2 X Conventional Delay-3 0.1 Q QQ1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2.1 2.6 3.1 3.6 4.1 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±16% ±40.6% Conventional Delay=l ±11.7% ±44.4% Conventional Delay=2 ±11.5% ±35.8% Conventional Delay=3 ±10.6% ±33.7% Figure 50 Effects of PCG Delays on FER (3 path 30 km/hr Rayleigh Fading at 1.93 GHz) 86 RC3 Forward FunrJamental Channel Conventional Delay=2 —•—Proposed(l) Delay=2 Proposed(1.5) Delay=2 0.1 [H 0.01 \o\ 1 1 1 1 i i t i i i i i 1 1 1 1 1 l_ 2.2 2.4 2.6 2.8 3 3.2 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±11.5% ±35.8% Proposed(l) Delay=2 ±11.6% ±40.6% Proposed(1.5) Delay=2 ±11.3% ±41.5% Figure 51 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 30 km/hr Rayleigh Fading at 1.93 GHz) 87 RC3 Forward Funckmental Channel -•— Conventional Delay=3 —••—• Proposed© Delay=3 —£r~ Proposed(2.5) Delay=3 0.1 I 1 1 : 1 1 1 1 2.3 2.5 2.7 2.9 3.1 3.3 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±10.6% ±33.7% Proposed(2) Delay=3 ±11.7% ±39% Proposed(2.5) Delay=3 ±11.6% ±39.8% Figure 52 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 30 km/hr Rayleigh Fading at 1.93 GHz) 88 6.3 Numerical Results for 800 MHz Band with 5% PCB Error Rate The PCBs in IS-2000 are not protected by coding so that a PCB can be used immediately after it is received and no decoding is required. However, this means that the PCBs are unprotected and subject to higher error rate. Since the MS does not know whether the PCB transmitted is correctly received by the BS or not, an increase in PCB error probability degrades the performance of the proposed CLPC algorithm. In this section, we study the effect of PCB errors on the FER and the performance of the proposed CLPC algorithm using the standard channel configurations in [22] (1 path 3 km/hr, 1 path 30 km/hr and 3 path 100 km/hr). The additional channel configurations (1 path 50 km/hr, 1 path 100 km/hr and 3 path 30 km/hr) are not used because the standard channel configurations are sufficient to show the effect of PCB errors on the proposed CLPC algorithm. The PCB error rate is set to 5%. Table 10 summarizes the 800 MHz band with 5% PCB error rate simulation figures. Table 10 Summary of 800 MHz Band with 5% PCB Error Rate Simulation Figures Channel Configuration Description Figure Number 1 path 3 km/hr Effects of PCG delays on FER Figure 53 Comparison of conventional and proposed algorithms when nt = 2 Figure 54 Comparison of conventional and proposed algorithms when nt = 3 Figure 55 1 path 30 km/hr Effects of PCG delays on FER Figure 56 Comparison of conventional and proposed algorithms when nt = 2 Figure 57 Comparison of conventional and proposed algorithms when nt - 3 Figure 58 3 path 100 km/hr Effects of PCG delays on FER Figure 59 Comparison of conventional and proposed algorithms when nt =2 Figure 60 Comparison of conventional and proposed algorithms when nt = 3 Figure 61 89 RC3 Forward Fundamental Channel -•- C.S0011-A -•- No CLPC -A- Conventional Delay=l Conventional Delay=2 * Conventional Delay=3 1 I 1 1 1 '• 1 1 1.9 3.9 5.9 7.9 9.9 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±7.3% ±8.9% Conventional Delay=l ±7.5% ±15.5% Conventional Delay=2 ±7.5% ±14.9% Conventional Delay=3 ±7.2% ±13.9% Figure 53 Effects of PCG Delays on FER (1 path 3 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 90 RC3 Forward Fundamental Channel • Conventional Delay=2 " Proposed(l) Delay=2 Proposed(1.5) Delay=2 1 al £ 0.1 ^^^^^^ IIII i II i IIII U.Ul 1.9 2.1 2.3 2.5 2.7 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±7.5% ±14.9% Proposed(l) Delay=2 ±7.5% ±15.4% Proposed(1.5) Delay=2 ±7.6% ±15.6% Figure 54 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 3 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 91 RC3 Forward FunrJamental Channel Conventional Delay=3 M Proposed(2) Delay=3 —*— Proposed(2.5) Delay=3 1 I I I I I I 1.9 2.1 2.3 2.5 2.7 2.9 s . Traffic Eb/N,(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±7.2% ±13.9% Proposed(2) Delay=3 ±7.4% ±14.8% Proposed(2.5) Delay=3 ±7.5% ±15% Figure 55 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 3 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 92 RC3 Forward Fundamental Channel —C.S0011-A No CLPC Conventional Delay=l —*~ Conventional Delay=2 * Conventional Delay=3 • 0.1 I 1 1 1 1 1 1 7.4 8.4 9.4 10.4 11.4 12.4 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±18.9% ±23.3% Conventional Delay=l ±15% ±34.7% Conventional Delay=2 ±12.9% ±29.1% Conventional Delay=3 ±10.9% ±22.4% Figure 56 Effects of PCG Delays on FER (1 path 30 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 93 RC3 Forward Fundamental Channel —Conventional Delay=2 —Proposed(l) Delay=2 Proposed(1.5) Delay=2 0.1 I 1 1 1 1 1 1 0.001 7.5 8.5 9 9.5 Traffic Eb/Nt(dB) 10 Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±12.9% ±29.1% Proposed(l) Delay=2 ±14.7% ±33.2% Proposed(1.5) Delay=2 ±15.7% ±33.7% Figure 57 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (1 path 30 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 94 RC3 Forward Fundamental Channel • Conventional Delay=3 —*— Proposed© Delay=3 --A— Proposed(2.5) Delay=3 0.1 1 1 1 1 1 1 1 1_ 1 1 1 1 i—_i i i 1 1 1 7.7 8.2 8.7 9.2 9.7 10.2 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±10.9% ±22.4% Proposed(2) Delay=3 ±14% ±31.5% Proposed(2.5) Delay=3 ±14.4% ±31.2% Figure 58 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (1 path 30 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 95 RC3 Forward Fundamental Channel -•-C.S0011-A —•— No CLPC Conventional Delay=l -XConventional Delay-2 * Conventional Delay=3 0.1 rH 0.01 \\\ \\ \\ \ \\ \\ A A. \\ \ \ V v A \ \ \ \ IIII IIII i i * i i L_l 1 'l •' II 1 — _J 1 1 1 l! 1 L_l IIII 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 6.1 Traffic Eh/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point No CLPC ±11.8% ±30.8% Conventional Delay=l ±10.7% ±35.8% Conventional Delay=2 ±10.7% ±31.2% Conventional Delay=3 ±10.3% ±28.5% Figure 59 Effects of PCG Delays on FER (3 path 100 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 96 RC3 Forward Fundamental Channel -•— Conventional Delay=2 —•— Proposed(l) Delay=2 —A— Proposed(l .5) Delay=2 0.1 I 1 1 1 1—: 1 U.UUl 2.1 2.3 2.5 2.7 2.9 Traffic Eb/Nt(dB) 3.1 3.3 Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=2 ±10.7% ±31.2% Proposed(l) Delay=2 ±10.2% ±30.8% Proposed(1.5) Delay=2 ±10% ±26.9% Figure 60 Comparison of Conventional and Proposed Algorithms when Delay=2 PCG Slots (3 path 100 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 97 RC3 Forward FurxJamental Channel •—•— Conventional Delay=3 —•— Proposed(2) Delay=3 —A— Proposed(2.5) Delay=3 • 0-1 I I IIII 0.001 ' 1 1 1 ' 2.2 2.4 2.6 2.8 3 3.2 Traffic Eb/Nt(dB) Statistical Accuracy: Higher FER Point Lower FER Point Conventional Delay=3 ±10.3% ±28.5% Proposed(2) Delay=3 ±9.9% ±26.9% Proposed(2.5) Delay=3 ±9.5% ±25.1% Figure 61 Comparison of Conventional and Proposed Algorithms when Delay=3 PCG Slots (3 path 100 km/hr Rayleigh Fading at 870 MHz with 5 % PCB Error Rate) 98 6.4 Discussion of Simulation Results As mentioned in Chapter 4, we use the mean traffic Eb/N, required to achieve the target FER for performance evaluation. The relative performance gain or degradation is the difference between the two traffic Eb/Nl values obtained. The lower the required mean traffic Eb/N, to achieve the target FER, the better is the performance of the CLPC algorithm. We first investigate the impact of loop delays on the FER performance of the conventional CLPC algorithm. Table 11 and Table 12 show the change in Eb/N, required to achieve the target FER. The required Eb/N, when there is no CLPC is shown for comparison purposes. Table 11 Impact of CLPC and Loop Delays on Eb/Nt Required by the Conventional CLPC Algorithm to Achieve the Target FER at 870 MHz Channel Configuration EJN, (No CLPC) EJN, (Delay=l) £fc/AT,(Delay=2)-£6/AT (Delay=l) £6/iV,(Delay=3)-£6/jV,(Delay=l) 1 path 3 km/hr 11.22 2.07 +0.046 +0.17 1 path 30 km/hr 12.42 7.78 +1.00 +2.21 1 path 50 km/hr 10.38 7.65 +0.91 +1.72 1 path 100 km/hr 8.07 6.56 +0.58 +1.10 3 path 30 km/hr 4.27 2.66 +0.16 +0.57 3 path 100 km/hr 3.03 2.59 +0.12 +0.25 Table 12 Impact of CLPC and Loop Delays on Eb/Nt Required by the Conventional CLPC Algorithm to Achieve the Target FER at 1.93 GHz Channel Configuration (No CLPC) EJN, (Delay=l) £6/tf,(Delay=2)-£jJV, (Delay=l) £fc/AT (Delay=3)-Eb/N, (Dday=l) 1 path 3 km/hr 10.1 2.62 +0.23 +0.60 1 path 30 km/hr 9.36 7.01 +0.67 +1.24 1 path 50 km/hr 7.74 6.37 +0.57 +0.89 1 path 100 km/hr 6.16 5.35 +0.34 +0.55 3 path 30 km/hr 3.43 2.56 +0.17 +0.32 3 path 100 km/hr 2.71 2.55 +0.024 +0.10 99 It can be seen that CLPC improves performance significantly at low Doppler frequencies and its performance decreases as Doppler frequency increases. This is because CLPC can keep up with the channel changes at lower Doppler frequencies. However, as the Doppler frequency increases, CLPC can hardly keep up with the channel changes. As the loop delay increases, the conventional CLPC algorithm requires a higher Eb/Nl to achieve the target FER in all the channel configurations. However, it is found that at low Doppler frequencies (1 path 3 km/hr at 870 MHz), the FER degradations due to loop delays are relatively small. Again, this is because the conventional CLPC algorithm can keep up with the channel changes at lower Doppler frequencies even when there is a small loop delay. At moderate Doppler frequencies (1 path 30 km/hr and 1 path 50 km/hr at 870 MHz), the FER performance of the conventional CLPC algorithm is very sensitive to loop delays. This is because the conventional CLPC algorithm can cope with fading in this Doppler frequency range when the loop delay is 1 PCG slot. However, any further loop delays slow down the reaction of the CLPC algorithm to a fade. As a result, the FER performance is degraded by a significant amount. It can be seen that the* delay sensitivity decreases as the Doppler frequency increases beyond some value (1 path 30 km/hr at 870 MHz and 1.93 GHz). At higher Doppler frequencies, the conventional CLPC algorithm is ineffective and interleaving is the main process that mitigates fading. Therefore, loop delay sensitivity decreases at high Doppler frequencies. The delay sensitivity is smaller when there are 3 multipaths. This is because the multipaths reduce the received signal power variance. Next we study the relative performance of the proposed CLPC algorithm compared to the conventional CLPC algorithm. Table 13 and Table 14 summarize the 100 relative performance gain of the proposed CLPC algorithm in dB (a positive gain corresponds to an improvement and a negative gain corresponds to a degradation). Table 13 Relative Performance Gain of Proposed CLPC Algorithm at 870 MHz Channel Delay (nt) Proposed(D) Proposed(D+0.5) Configuration Performance Gain (dB) Performance Gain (dB) Compared to Compared to Conventional Conventional 1 path 3 km/hr 2 PCG Delay 0.044 0.054 3 PCG Delay 0.16 0.17 1 path 30 km/hr 2 PCG Delay 0.85 0.97 3 PCG Delay 1.7 1.8 1 path 50 km/hr 2 PCG Delay 0.56 0.63 3 PCG Delay 0.93 0.92 1 path 100 km/hr 2 PCG Delay 0.14 0.13 3 PCG Delay 0.26 0.16 3 path 30 km/hr 2 PCG Delay 0.12 0.13 3 PCG Delay 0.41 0.43 3 path 100 km/hr 2 PCG Delay 0.043 -0.012 3 PCG Delay 0.0043 -0.033 101 Table 14 Relative Performance Gain of Proposed CLPC Algorithm at 1.93 GHz Channel Delay (nt) Proposed(D) Proposed(D+0.5) Configuration Performance Gain (dB) Performance Gain (dB) Compared to Compared to Conventional Conventional 1 path 3 km/hr 2 PCG Delay 0.19 0.24 3 PCG Delay 0.50 0.54 1 path 30 km/hr 2 PCG Delay 0.31 0.30 3 PCG Delay 0.40 0.43 1 path 50 km/hr 2 PCG Delay 0.059 0.023 3 PCG Delay -0.054 -0.13 1 path 100 km/hr 2 PCG Delay -0.41 -0.58 3 PCG Delay -0.67 -0.75 3 path 30 km/hr 2 PCG Delay 0.054 0.040 3 PCG Delay 0.085 0.082 3 path 100 km/hr 2 PCG Delay -0.16 -0.22 3 PCG Delay -0.17 -0.26 102 In the 800 MHz band with no PCB error (Table 13), the proposed CLPC algorithm has a positive gain for all channel configurations except for the 3 path 100 km/hr case with Proposed(D+0.5). The proposed CLPC algorithm shows the best performance in 1 path 30 km/hr with gains of approximately 1 dB and 1.8 dB using Proposed(D+0.5) when the loop delay is 2 PCG and 3 PCG slots respectively. The FER performances of the proposed CLPC algorithm when delay is 2 and 3 PCG slots are almost the same as the FER of the conventional CLPC when there is 1 PCG delay. This indicates that the proposed CLPC is quite effective in reducing the impact of the delay in the power control loop. As the speed is increased to 50 km/hr-with 1 signal path, the performance gain becomes smaller; but there is still 0.6 dB and 0.9 dB gain using Proposed(D+0.5) when delay is 2 PCG and 3 PCG slots respectively. It can be seen that when the mobile speed is low (1 path 3 km/hr), the improvement using the proposed CLPC algorithm is small. This is expected because the conventional CLPC algorithm can effectively track the fade variations when the channel changes slowly even when there are some delays. In general, when a single bit PCB scheme is used for CLPC, prediction will only improve CLPC performance when the Eb/Nl crosses the power control threshold. That is, with prediction, the future Eb/Nt value will be used for decision making for the current PCB. If the signal is entering or exiting a fade, the corresponding PCB based on the predicted Eb/N, value can be sent earlier to mitigate the effect of the upcoming channel condition. At low speed, the Doppler frequency is low and the number of times Eb/N, crosses the power control threshold in a given time interval is small. Therefore, the gain from the use of prediction is less obvious at low speeds. But TDC reduces power oscillation amplitudes when the Doppler frequency is low. This means that a smaller fade margin is required which in turn increases the capacity. At high speed (1 path 100 km/hr and 3 path 100 km/hr), 103 the improvement is small because the Doppler frequency is too high for accurate prediction of future fades. This is because for Eb/Nt to cross the power control threshold, there must be a local maximum or minimum. An increased number of local maxima or minima in a given time period generally results in poorer fade prediction accuracy. It is found that Proposed(D+0.5) gives similar results to Proposed(D) in all channel configurations. Therefore, the impact of the 0.5 PCG delay between the SIR estimation and the execution of the PCB is small. In the 1.9 GHz band with no PCB error (Table 14), the proposed CLPC algorithm has positive gains in all 3 km/hr and 30 km/hr simulations. However, the proposed CLCP algorithm has negative gains in the 1 path 50 km/hr simulation when delay is 3 PCG slots, and all 100 km/hr simulations. The performance of the proposed CLPC algorithm running in the 1.9 GHz band follows the observations made for the 800 MHz band. That is, the proposed algorithm performs better at low to moderate Doppler frequencies and its performance degrades at high Doppler frequencies, as fade prediction is inaccurate at high Doppler frequencies. In the 1.9 GHz band, the Doppler frequency is more than two times the Doppler frequency in the 800 MHz band. In Table 14, we can see that.the performance at low speed (1 path 3 km/hr) is improved when compared to the results in Table 13. As the proposed CLPC algorithm gives best performance at moderate speed (30,to 50 km/hr) in the 800 MHz band, we can expect similar performance at approximately 15 to 25 km/hr in the 1.9 GHz band. One way to avoid degradations caused by the proposed CLPC algorithm is to check the fade prediction accuracy during run time. When the differences between the predicted SIR's for successive PCG slots and the actual SIR's of these PCG slots are greater than some threshold value for a certain period of time, we can conclude that the proposed CLPC algorithm can no longer track the channel changes. In this case, 104 the proposed CLPC algorithm can run with TDC only until prediction is re-enabled when the differences between the predicted SIR's and the actual SIR's are below some threshold value for a certain period of time. When PCB errors occur at a rate of 5%, a higher Eb/N, is required to achieve the target FER in all the channel configurations simulated. Table 15 shows the impact of a 5% PCB error rate on the conventional CLPC algorithm. The Eb/Nt required to achieve the target FER when PCB error rate is 5% is compared to the case when PCB error rate is 0%. Table 15 Impact of 5% PCB Error Rate on Et/Nt for the Conventional CLPC Algorithm to Achieve the Target FER at 870 MHz Channel Configuration Es/N, 5% PCB error rate (Delay=l)-Eb/N, No PCB error (Delay=l) EjN, 5% PCB error rate (Delay=2) -Eb/N, No PCB error (Delay=2) Eb/N, 5% PCB error rate (Delay=3) -Eb/N, No PCB error (Delay=3) 1 path 3 km/hr +0.049 +0.061 +0.059 1 path 30 km/hr +0.58 +0.34 +0.14 3 path 100 km/hr +0.073 +0.096 +0.12 In the 1 path 3 km/hr and 3 path 100 km/hr simulations, the impact of a 5% PCB error rate on the required Eb/N, to achieve the target FER is relatively small. However, it is noted that the impact of PCB errors on the required Eb/N, to achieve the target FER in the 1 path 30 km/hr channel configuration is significant and the impact decreases as the loop delay increases. This is because with no PCB errors, the performance degrades as the loop delay increases. This is most noticeable for the 1 path 30 km/hr channel configuration as shown in Table 11. It is expected that PCB 105 errors will tend to have the greatest impact when the CLPC algorithm is. quite effective and the loop delay is small. Next, we ~ investigate the impact of PCB errors on the proposed CLPC algorithm. Table 16 summarizes the relative performance gain of the proposed algorithm in dB when the PCB error rate is 5%. Table 16 Relative Performance Gain of Proposed CLPC Algorithm at 870 MHz with 5% PCB Error Channel Delay (nt) Proposed(D) Proposed(D+0.5) Configuration Performance Gain (dB) Performance Gain (dB) Compared to Compared to Conventional Conventional 1 path 3 km/hr 2 PCG Delay 0.036 0.047 3 PCG Delay 0.11 0.13 1 path 30 km/hr 2 PCG Delay 0.55 0.74 3 PCG Delay 1.2 1.3 3 path 100 km/hr 2 PCG Delay 0.016 -0.067 3 PCG Delay 0.020 -0.037 In the 800 MHz band with 5% PCB error rate, the relative performance gain of the proposed CLPC algorithm is smaller compared to the case with no errors. The proposed CLPC algorithm still shows the best performance in the 1 path 30 km/hr channel configuration with gains of approximately 0.7 dB and 1.3 dB using Proposed(D+0.5) when delay is 2 PCG and 3 PCG respectively. The performance gains drop by about 0.3 dB and 0.5 dB for delay of 2 PCG and 3 PCG respectively when compared to the 1 path 30 km/hr channel configuration with no PCB errors. A PCB error results in cascaded errors in the proposed CLPC algorithm since previously 106 transmitted PCB values are used for delay compensation and fade prediction. From equation (5.1), it can be seen that in the proposed CLPC algorithm, a PCB error affects up to n, PCB decisions. Overall, with the proposed CLPC algorithm, the same system performance can be achieved with a lower traffic Eb/N, for a range of mobile speeds of interest, thereby increasing the capacity of the IS-2000 system. 107 7.0 Conclusion In this thesis, the effects of power control loop delays on the FER of an IS-2000 forward link using the conventional CLPC algorithm and a proposed delay compensated, fade prediction based CLPC algorithm have been studied. In this chapter, we summarize the main contributions of this thesis and provide some suggestions for further study. 7.1 Contributions of the Thesis 1. The effects of loop delays on IS-2000 forward link CLPC The FER performance of the conventional IS-2000 forward link CLPC algorithm in the presence of loop delays is studied. It is shown that the increase in power oscillation amplitude with loop delays reported in [17] exists in the conventional IS-2000 CLPC algorithm. Furthermore, simulations were used to show the impact of loop delays on the FER using a detailed system model that includes coding / decoding, interleaving / de-interleaving, and spreading / despreading. The forward link CLPC test configurations from [22] were used, and simulations were run for the 800 MHz and 1.9 GHz frequency bands with total delay w,=l, 2 and 3 PCG slots. It is also observed that the conventional CLPC algorithm FER degradations due to loop delays are relatively small at low Doppler frequencies. This is because at low Doppler frequencies, the CLPC algorithm can track the fading envelope even when there is a small time delay. For moderate Doppler frequencies, the FER performance of the conventional CLPC algorithm is sensitive to loop delays. However, the delay sensitivity decreases as the Doppler frequency increases 108 \ from moderate to high. At high Doppler frequencies, the CLPC algorithm is ineffective and interleaving is the main process that mitigates fading. 2. A delay compensated fade prediction based CLPC algorithm A delay compensated, fade prediction based CLPC algorithm that can reduce power oscillation amplitude and improve SIR estimation in the presence of loop delays is proposed. The proposed CLPC algorithm can reduce the required fading margin and lower the Eb/Nl needed to achieve the target FER thereby resulting in an increase in the system capacity. The proposed CLPC algorithm can be easily implemented in an IS-2000 compliant system with no additional hardware requirements. The only change required is an upgrade of the firmware which controls the generation of the PCBs. 3. FER performance comparison of the conventional and proposed CLPC algorithms A detailed IS-2000 system model was used to simulate the FER performance of the proposed CLPC algorithm. Using CLPC test setups from [22], simulation results for the forward link show that the proposed CLPC algorithm performs better than the conventional CLPC algorithm for a range of Doppler frequencies of interest. As the Doppler frequency increases from 0, the relative performance of the proposed CLPC algorithm improves until some threshold value, fl. Above fl, the relative performance degrades gradually. This is because the prediction algorithm cannot accurately track the fading envelope and the SIR estimation becomes inaccurate at high Doppler frequencies. Studies on the effect of PCB errors on the proposed CLPC algorithm show that the difference between the FER performance of the conventional and proposed algorithms decreases when the PCB error rate is 109 5%. This is because the proposed CLPC algorithm uses previously sent PCBs to correct the SIR estimation and PCB errors reduce the accuracy of the SIR estimation. It is found that the proposed CLPC algorithm offers a noticeable improvement in the FER performance compared to the conventional CLPC algorithm when the Doppler frequency is moderate. 7.2 Topics for Further Study Several methods by which the performance of the proposed CLPC algorithm can be improved are suggested below. 1. Suppression of fade prediction at high Doppler frequencies It was observed that at high Doppler frequencies, the proposed CLPC algorithm could have a worse FER performance than the conventional CLPC algorithm. Thus a scheme which disables fade prediction when the Doppler frequency exceeds some threshold value could be studied. Its performance could be compared with the scheme suggested in Chapter 6.4 which is based on the difference between the predicted SIR and the actual received SIR. 2. Application of prediction on each multipath The proposed CLPC algorithm uses the Eb/N, values after MRC to predict channel fades. Simulation results show that the relative FER performance of the proposed CLPC algorithm is better in the 1 path case than in the 3 path case at moderate Doppler frequencies. It is expected that if channel information from each multipath were used for prediction, the performance in the 3 path case would be improved. The predicted channel condition from each multipath can be combined at the end and then used to generate an 110 Eb/Nl estimation for future PCGs. The performance improvement which can be obtained by such an approach should be studied. Higher order prediction algorithm Linear extrapolation was used in this thesis to predict channel fades. Other fade prediction algorithms can be studied and used with delay compensation to possibly improve the proposed CLPC algorithm performance. For example, quadratic curve fitting can be used on the SIR samples to predict channel fades. It is expected that when a higher order prediction algorithm is used, more delay compensated Eb/N, samples will be needed by the prediction algorithm. Higher order prediction algorithm sensitivity to PCB errors should be studied. Ill Bibliography 1. Qualcomm Inc., "An Overview of the Application of Code Division Multiple Access (CDMA) to Digital Cellular Systems and Personal Cellular Networks", May 21, 1992. http://www.qualcomm.com 2. J. G. Proakis, Digital Communications, Fourth Edition, New York: McGraw-Hill, 2001. 3. Jakes, W. C, Microwave Mobile Communications, New York: John Wiley & Sons, 1974. 4. Simon Haykin, Communication Systems, Third Edition, New York: John Wiley & Sons, Inc., 1994. 5. B. Sklar, "Rayleigh Fading Channels in Mobile Digital Communication Systems Part II: Mitigation", IEEE Communications Magazine, vol. 35, no. 7, pp. 102-109, July 1997. 6. M. Schwartz et al., Communication Systems and Techniques, New York: McGraw-Hill, 1966. 7. T. Chulajata and H. M. Kwon, "Combinations of Power Controls for cdma2000 Wireless Communications System", IEEE Vehicular Technology Conference, vol. 2, pp. 638-645, September 2000. 8. Yang, Samuel C, CDMA RF System Engineering, London: Artech House, 1998. 9. D. M. Novakovic and M. L. Dukic, "Evolution of the Power Control Techniques for DS-CDMA Toward 3G Wireless Communication Systems", IEEE Communications Survey & Tutorials, vol. 3, no. 4, pp. 2-15, 4th Quarter 2000. 112 10. 3GPP2, C.S0002-0 v3.0 Physical Layer Standard for cdma2000 Spread Spectrum Systems - Release 0 - Version 3.0, June 15, 2001. http ://www. 3 gpp2 .org 11. A. J. Viterbi, A. M. Viterbi, and E. Zehavi, "Performance of Power-Controlled Wideband Terrestrial Digital Communication", IEEE Transactions on Communications, vol. 41, no. 4, pp. 559-569, April 1993. 12. Philippe Kauffmann, "Fast Power Control for Third Generation DS-CDMA Mobile Radio Systems", International Zurich Seminar on Broadband Communications, pp. 9-13, February 2000. 13. Grandhi, S. A., Vijayan, R., and Goodman, D. J., "Centralized Power Control in Cellular Radio Systems", IEEE Transactions on Vehicular Technology, vol. 42, no. 4, pp. 466-468, Novemberl993. 14. A. H. Sayed and M. A. Aldajani, "Inverse Closed-Loop Power Control For CDMA Wireless Systems", IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 3, pp. 2753-2756, May 2002. 15. F. Gunnarsson and F. Gustafsson, "Power Control with Time Delay Compensation", IEEE Vehicular Technology Conference, vol. 2, pp. 646-653, September 2000. 16. A. Chockalingam, P. Dietrich, L. B. Milstein and R. R. Rao, "Performance of Closed-Loop Power Control in DS-CDMA Cellular Systems", IEEE Transactions on Vehicular Technology, vol. 47, no. 3, pp. 774-789, August 1998. 17. F. Gunnarsson, and F. Gustafsson, "Time Delay Compensation for CDMA Power Control", IEEE Global Telecommunications Conference, vol. 3, pp. 1504-1508, December 2000. 113 18. F. Gunnarsson, F. Gustafsson, and Jonas Blom, "Dynamical Effects of Time Delays and Time Delay Compensation in Power Controlled DS-CDMA", IEEE Journal on Selected Areas in Communications, vol. 19, no. 1, pp. 141-151, January 2001. 19. M. L. Sim, E. Gunawan, B. H. Soong and C. B. Soh, "Performance Study of Close-Loop Power Control Algorithms for a Cellular CDMA System", IEEE Transactions on Vehicular Technology, vol. 48, no. 3, pp. 911-921, May 1999. 20. M. M. Alam and A. Chockalingam, "Performance of a Prediction Based Closed Loop Power Control Algorithm in WCDMA", Proceedings of NCC'2002, January 2002. 21. J. H. Wen, L. C. Yeh, and J. R. Chiou, "Short-term Fading Prediction-based Power Control Method for DS-CDMA Cellular Mobile Radio Networks", The 8th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, vol. 3, pp. 908-912, September 1997. 22. 3GPP2 C.S0011-A vl.O Recommended Minimum Performance Standards for cdrria2000 Spread Spectrum Base Stations - Release A - March 30, 2001. http ://www. 3 gpp2 .org 23. "Signal Processing Worksystem® Designer / BDE™ User's Guide", Alta Group™ of Cadence Design Systems, Inc., Version 3.5, February 1996. 24. A. J. Viterbi, CDMA: Principles of Spread Spectrum Communication, Massachusetts: Addison Wesley, 1995. 25. K. S. Gilhousen, I. M. Jacobs, R. Padovani, A. J. Viterbi, L. A. Weaver, Jr. and C. E. Wheatley III, "On the Capacity of a Cellular CDMA System", IEEE Transactions on Vehicular Technology, vol. 40, no. 2, pp. 303-312, May 1991. 114 J. B. Groe and L. E. Larson, CDMA Mobile Radio Design, London: Artech House, 2000. 115 

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