f Determination of Self-heating in Bipolar and Heterojunction Bipolar Transistors by Measurement and Simulation by A d a m Robert Reid B . S c , Physics, Mount Al l i son University, 1998 A T H E S I S S U B M I T T E D I N P A R T I A L F U L F I L L M E N T O F T H E R E Q U I R E M E N T S F O R T H E D E G R E E O F Maste r of A p p l i e d Science in T H E F A C U L T Y O F G R A D U A T E S T U D I E S (Department of Electrical and Computer Engineering) We accept this thesis as conforming to the acquired standard The University of British Columbia October 2000 © A d a m Robert Reid, 2000 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Abstract Self-heating in bipolar transistors, the effect which causes a rise in the device junction tem-perature due to the electrical power dissipation, is of interest for several reasons, including device reliability, model parameter extraction and electrothermal modeling. Self-heating is most commonly quantified by a thermal resistance, which relates the device steady-state temperature and power dissipation. In this work we present an improved setup for mea-suring thermal resistance, based on an isothermal characterization of the device by means of a pulsed-bias experiment. A 30 times increase in bias-pulse speed, compared to previ-ous setups, allows for the first time, accurate measurements to be made on devices with submicron emitter dimensions. Simultaneous to increased performance, we have achieved a significant reduction in the complexity of the setup through the elimination of specialized sample preparation, enabling measurements with conventional microwave on-wafer probes. To facilitate comparison with experimental measurements, an analysis tool based on the finite element method has been developed to solve detailed 3-D thermal models of bipolar transistors, including emitter metalization and trench-isolation effects. Thermal resistance measurements have been made on a collection of 9 single emitter silicon bipolar and 6 trench-isolated SiGe heterojunction bipolar transistors and compared ii to results from theoretical models. In addition, a collection of 15 GaAs heterojunction bipolar transistors have been studied theoretically and compared to measurements from a previous study. Results for silicon bipolar devices show that significant reductions in thermal resistance are achieved by using high aspect ratio emitter geometries. Comparison of results for silicon bipolar devices with trench-isolated SiGe devices of a similar emitter geometry show a threefold increase in thermal resistance due to the presence of trench isolation. This increase in thermal resistance is found to be attributable in roughly equal parts to the two isolation components, namely the deep and shallow trenches. The thermal resistance is found to scale weakly with emitter area for the small devices studied here, an effect which is most apparent in the GaAs devices. The origin of this effect is found to be the 3-D nature of the heat flow in the smallest devices. Emitter metalization is found to play a role in reducing the thermal resistance for high thermal resistance devices. Additionally, the emitter metalization is found to significantly increase the uniformity of the temperature across the emitter. ii i Contents Abst rac t " Contents v i Lis t of Tables v i i Lis t of Figures x Acknowledgements x i 1 In t roduct ion 1 1.1 Self-Heating 1 1.2 Motivation 2 1.2.1 Device Reliability 2 1.2.2 Parameter Extraction 3 1.2.3 Electrothermal Device Models 3 1.3 Models for Self-Heating 4 1.3.1 Thermal Resistance 5 1.3.2 Dynamic Modeling 7 iv 1.4 Previous work y 1.4.1 Thermal Resistance Simulation Techniques 9 1.4.2 Thermal Resistance Measurement Techniques 13 1.4.3 Existing Thermal Resistance Results 22 1.5 Overview 23 1.5.1 Summary of Thesis 23 1.5.2 Outline 28 2 D e v i c e s a n d M o d e l i n g 29 2.1 Devices 29 2.1.1 Silicon bipolar 29 2.1.2 GaAs 30 2.1.3 SiGe 31 2.2 Description of Models 31 2.2.1 Basic 3-D Source Model 32 2.2.2 Rockwell GaAs Models 35 2.2.3 Nortel GaAs Models 36 2.2.4 SiGe Model 40 2.3 Overview of solution technique 44 2.3.1 Discretization of the Thermal Model 45 2.3.2 Solution and Refinement 48 2.3.3 Interpretation of the Data 50 2.4 Verification of the Method 50 v 2.4.1 One dimensional heat flow 52 2.4.2 Comparison with Analytic Solution for Simple Patch Model 54 3 The rma l Resistance Measurement System Based on Pu lsed Isothermal Character iza t ion 56 3.1 Experimental Setup 56 3.2 Measurement Technique 60 3.2.1 Isothermal Voltage-Current Measurements 60 3.2.2 Determination of Thermal Resistance 65 3.3 Verification of Measurements 67 4 Results and Discussion 69 4.1 Layout Dependence of Thermal Resistance in Silicon Bipolar Devices . . . . 69 4.2 Trench Isolation Effects and Modeling 72 4.3 Weak Scaling in Small Devices 77 4.4 The role of metalization in temperature uniformity 85 5 Conclusions 90 Bib l iography 9 4 A Pulse C i r c u i t r y 99 v i List of Tables 4.1 Thermal resistance measurements and finite element model predictions for 0.5 u,m wide emitter silicon bipolar devices 71 4.2 Thermal resistance measurements and finite element model predictions for 1.1 /im wide emitter silicon bipolar devices 72 4.3 Thermal resistance measurements and finite element model predictions for SiGe devices 73 vii List of Figures 1.1 Simple equivalent-circuit thermal resistance model for self-heating 6 1.2 Time dependent model for self-heating 7 1.3 First order thermal model 8 1.4 The simple patch thermal model of a transistor 10 1.5 3-D heat source in semi-infinite medium thermal model 12 1.6 Pulsed I-V characteristics for a SiGe H B T 19 1.7 Determination of thermal resistance from isothermal and steady-state data . 21 1.8 Comparison of transient data from new and old experimental setups 25 1.9 Experimental and theoretical results for silicon and trench isolated SiGe de-vices of the same size 27 2.1 Basic 3-D heat source thermal model 33 2.2 Thermal model including metalization for single emitter Rockwell AlGaAs devices 37 2.3 Thermal model including metalization for circular emitter Rockwell AlGaAs devices 38 viii 2.4 Thermal model including metalization for Rockwell two-finger emitter AlGaAs devices 39 2.5 Thermal model including emitter metalization for Nortel AlGaAs device . . . 41 2.6 Thermal model including base metalization for Nortel AlGaAs device . . . . 42 2.7 Thermal model for trench-isolated SiGe devices 43 2.8 Surface patch thermal model for F E M solution 46 2.9 Representative data showing the initial mesh for a thermal model 47 2.10 Representative data showing a refined mesh for a thermal model 49 2.11 Temperature contours on the emitter of a 3 x 3 GaAs device using the surface patch model 51 2.12 F E M validation, 3-D model of 1-D heat flow in a bar 52 2.13 Verification of F E M solution technique for one-dimensional heat flow problem 53 2.14 Temperature contours for the 3x3 GaAs device from analytic solution . . . . 55 3.1 Schematic representation of the isothermal measurement setup 57 3.2 Simplified schematic of base pulse generation circuit 58 3.3 Simplified schematic of collector current monitor 59 3.4 Block diagram of experimental setup 61 3.5 Representative transient data for a 0.5 x 5/^m2 SiGe device 62 3.6 Fit of single exponential curve to collector current transient data 64 3.7 Isothermal and steady-state I-V curves for 0.5 x 5u.ni2 SiGe device 66 3.8 Comparison of SiGe thermal resistance measurements to existing results . . . 68 ix 4.1 Experimental and theoretical thermal resistance results for silicon bipolar de-vices 70 4.2 Thermal resistance versus emitter area for SiGe trench-isolated devices . . . 74 4.3 F E M prediction of thermal resistance for various trench models and compositions 76 4.4 Experimentally determined thermal resistances for GaAs devices 78 4.5 Experimental and theoretical thermal resistance results for square and circular emitters 80 4.6 Experimental and theoretical thermal resistances for one- and two-finger, rect-angular emitters 81 4.7 Maximum and minimum base-emitter junction temperature for square devices 82 4.8 Comparison of the shape of the BCSCRs of a large and small GaAs device . 84 4.9 Temperature contours on base-emitter junction of 8 x 8 /.im2 GaAs device . . 86 4.10 Temperature at base-emitter junction of 3x3/im 2 GaAs device as predicted by F E M simulation 89 A . l Schematic of base pulse circuitry 99 A.2 Top layer of printed circuit board layout for base pulse circuit 100 A.3 Bottom layer of printed circuit board layout for base pulse circuit 100 A.4 Schematic of collector current monitoring circuitry 101 A.5 Top layer of printed circuit board layout for collector current monitoring circuit. 101 A.6 Bottom layer of printed circuit board layout for collector current monitoring circuit 102 Acknowledgements I would like to thank M . K . Jackson, without his many long hours of hard work, none of this would have been possible. I am especially grateful for his patience, support and encouragement, and for his guidance in taking me from the world of physics to the world of electrical engineering. I would like to acknowledge the Natural Sciences and Engineering Research Council (NSERC) and the British Columbia Advanced Systems Institute (BCASI) for their funding throughout my degree program. Thanks also to Micronet and Strategic Grants for their funding of this project. Many industrial collaborators including P. J. Zampardi of Conexant, R. Pierson of Rockwell Semiconductor, D. Marchesan of Nortel Networks, S. J. Kovacic of SiGe Microsystems and J. R. Long of University of Toronto have contributed to this work, providing test devices and expertise. I would like to express m y gratitude to Rudolf Beck, Rainer Roitzsch and Bodo Erdmann for maintaining the very high quality Kaskade finite element code in the public domain. Their discussions and software were very helpful during the course of this work. I would also like to thank Stephen Vavasis for the Q M G meshing software which he provides for public use. I thank my friends and co-workers, R. Rosales, D. Jez, J. Zhang, S. Chandani, Z. Duan xi and R. Coenen for all of their assistance. I am especially grateful to G. Archibald for who is always available on a moments notice to lend a helping hand. xn Chapter 1 Introduction 1.1 Self-Heating Thermal effects on the operation of transistors have been an area of interest to researchers since at least as early as the late 1960's [1,2], when it was surmised that thermal effects would limit transistor speed improvements in the future [1]. Since that time it has been well known that the dissipation of electrical power in transistors leads to a rise in the device temperature, a phenomena known as self-heating. Self-heating is important when studying the electrical behavior of semiconductor devices, as it results in a device temperature that is not generally the same as it's ambient environment. Device temperature is an important factor in the electrical performance of semiconductor devices due to the strong temperature dependence of the electrical properties of semiconductor materials. This chapter will introduce the notion of self-heating and begin by discussing the reasons we are motivated to study this effect. We will then describe the ways in which self-heating in bipolar transistors is generally studied and the theoretical and experimental techniques which have been used in the past. The 1 chapter will conclude with an overview of how self-heating is studied in the present work and the results we have obtained 1.2 Motivation 1.2.1 Device Reliability Perhaps the most obvious reason to be concerned with self-heating in transistors is for purposes of reliability. A l l semiconductor devices have a maximum temperature above which permanent damage to the device may occur. Ensuring that a device will not fail when used in a circuit is obviously of great importance to circuit designers. For this reason, safe operating areas are usually given in specification sheets for transistors. In the case of modern integrated circuits, this information is often provided as a maximum junction temperature and a thermal resistance for computing the junction temperature. Perhaps more problematic than complete failure of a device, which would likely be detected in testing of a circuit, is the reduced lifetime of a device through continuous operation at elevated temperatures. This is particularly important in many telecommunications applications where devices are deployed in systems which are expected to operate over lifetimes of more than ten years. Many of these telecommunications systems are placed in inaccessible locations, such as satellites, where failure of a device may lead to costly system-wide failure. Thus, a good knowledge of self-heating can be invaluable for reliability studies. 2 1.2.2 Parameter Extraction A second area where knowledge of self-heating is of great importance is in the parameter extraction for compact device models [3, 4, 5]. The ability to model the behavior of transistors in a computer simulation has become a key step in modern integrated circuit design, where it is critical to minimize the number of circuit prototypes to reduce production costs and time to market for the product. Compact models consist of analytic expressions which describe the electrical behavior of a device in terms of independent variables, such as terminal voltages and temperature, as well as other parameters. The parameter values are often extracted by comparison of the measured behavior of a device to the analytic expressions. If the model correctly captures the behavior of the device then the extracted parameters may be used to predict the behavior of the device in a variety of conditions. Since all device models must be functions of temperature as well as other variables, the temperature must be well known during the extraction process. If self-heating is not considered in parameter extraction, often the self-heating effects become incorrectly incorporated into other model parameters. A well known example of this is the incorrect extraction of bipolar junction transistor (BJT) emitter resistance [3, 4] and Early voltage[5]. 1.2.3 Electrothermal Device Models If models are correctly extracted such that self-heating effects have been removed from the parameters, then it is critical that the correct temperature be input to the device model. Since this temperature will vary from the ambient and will depend on the power dissi-pation, accurate models for self-heating must be available and simultaneously solved with 3 the electrical models. To date there have been several instances reported in the literature which demonstrate the importance of using an electrothermal model to accurately predict the behavior of a circuit, such as thermal effects on heterojunction bipolar transistor (HBT) voltage comparators [6], sample and hold circuits [7] and power amplifiers [8]. Although electrothermal simulations yield more accurate results than purely electrical models, the added complexity may often cause problems with convergence of the results. This is mainly a limitation to our present simulation techniques and is a problem which must be overcome to facilitate the widespread use of electrothermal models. 1.3 Models for Self-Heating The goal of a study of the thermal properties of transistors includes quantifying the degree of self-heating in a device at any given state of operation, therefore providing knowledge of temperature of the device. In general, the temperature is a complex function of the magnitude and the duration of the power dissipation, and will vary over the volume of the device. A complete understanding of self-heating in a device requires a knowledge of the temperature as a function of power, time and position. Such a complete description of self-heating can only be described by an elaborate solution to the heat equation for a device, which is impractical to obtain for a real device. Therefore most thermal studies of transistors aim to provide simplified models for self-heating which are practical for circuit designers to work with and provide information that is reasonably accurate under a restricted set of conditions. 4 1.3.1 Thermal Resistance The most simplified and widely used model for self-heating considers only the temperature of the device under steady-state conditions and assumes that a single temperature is suffi-cient to describe the entire device. In this case, the temperature is only a function of the power dissipation. In the case where the relationship between the temperature and power dissipation is linear, a constant thermal resistance suffices, where the thermal resistance is defined as the ratio of the device temperature rise above ambient to the power dissipation. In the case of a nonlinear relation between temperature rise and power dissipation, a power dependent thermal resistance may be defined similarly. The thermal resistance is a useful quantity provided that it is used appropriately and the underlying assumption, namely that a single temperature describes the device, is not violated. The validity of this assumption depends on the reason for which the thermal re-sistance is defined. If we are concerned with the temperature of a device from a reliability standpoint, then a thermal resistance defined in terms of a maximum device temperature will be appropriate and provide the required information. If, on the other hand, we are con-cerned with device temperature from a electrical model stand point, then it must be assessed whether the temperature is uniform over the active area of the device and if not, whether a single average temperature provides enough information to model the device correctly. Provided that a thermal resistance may be defined, it is also necessary to assess whether the relation between temperature and power is linear, and therefore if the thermal resistance is a constant value. From a mathematical standpoint, the steady-state heat flow equation is linear if the thermal conductivity is temperature independent. In this case, the solution for 5 temperature as a function of power is always linear. However, most semiconductor materials have thermal conductivities which are functions of temperature. Thus only in the case where the temperature rises are small, a few tens of degrees, will the thermal conductivity of the semiconductor be sufficiently constant over that range to provide an approximately linear relationship. In certain cases, such as in power devices, there are large temperature rises, and the power dependence of the thermal resistance is observed. An example of this is in many GaAs devices where the temperature rises are relatively large due to the low thermal conductivity of GaAs, about one third of the thermal conductivity of silicon. Another source of power dependence in the thermal resistance may be due to nonlinearities introduced by electrothermal effects which change the spatial distribution of power dissipation as a function of power. Examples of such effects are electrical current crowding and thermal hot spots which are strongly dependent on emitter geometry. An analogy between thermal resistance and electrical resistance is often used to express the thermal resistance model in terms of an equivalent electrical circuit as shown in Fig. 1.1. In this model the current represents the device power dissipation and the resulting voltage represents the device temperature. This analogy is convenient as it allows the thermal model to be solved with electrical circuit simulators, along with the electrical behavior and to couple the electrical and thermal models to one another. Figure 1.1: Simple equivalent-circuit thermal resistance model for self-heating 6 1.3.2 Dynamic Modeling The concept of thermal resistance is very useful as it allows for a very simple computation of device temperature from the power dissipation and ambient temperature. Thermal resis-tance does not, however, give information about the temporal response of the temperature to changes in power dissipation. This temporal information is necessary when consider-ing devices undergoing large changes in the power operating point such as in large signal A C operation or switching applications. In order to provide information about the time response of the temperature of a device, it is convenient to introduce the notion of ther-mal capacitance. If the concept of thermal resistance is generalized into an infinite chain of R C one-port networks, as shown in Fig. 1.2, any possible linear temporal response can be described accurately. The sum of the distributed resistances is exactly the same as the Figure 1.2: Time dependent model for self-heating steady-state thermal resistance. In the case of one dimensional heat flow, the model may be greatly simplified since a single thermal capacitance and resistance are sufficient to describe the thermal response. Much work has been done on determining accurate models for the thermal transients of packaged integrated circuits [9], the results of which show that in most cases less than ten thermal resistances and capacitances are sufficient to accurately describe the thermal response. These studies associate each RC one-port network with a part of the packaging or die. For the case of a bare die mounted directly to a heat sink, results suggest 7 that only a few RC one ports are needed for an accurate description of the thermal response [10]. A few studies of the thermal response of transistors [11] in bare die form have used the simplifying assumption that the heat flow is approximately one dimensional and a single RC network is used to describe the thermal response. This model, shown in Fig. 1.3, although convenient, only provides a first order approximation to the actual thermal response. A l -though a study of the transient thermal models is not a direct topic of this work, the validity of the single RC network to describe the thermal response of a device will be discussed in more detail in Chapter 3. The concept of the RC one port chain of thermal elements is also useful in the context of this work, as it provides an intuitive sense of how the temperature responds to changes in power dissipation, by analogy with the well known electrical sys-tem. Two important observations can be made from the electrical analogy. The first is that the device is a low pass filter and therefore very rapid changes in power dissipation do not change the temperature instantaneously. The second is that the temperature response to a step in power dissipation can be expressed as a sum of exponential functions with various time constants. Both of these concepts will be referred to in Chapter 3 when discussing the isothermal measurement technique. R t h Figure 1.3: First order thermal model 8 1.4 Previous work 1.4.1 Thermal Resistance Simulation Techniques There are several different methods reported in the literature for theoretical study of self-heating in transistors. In most cases, simplified thermal models for a device are solved to provide a means of validating experimental measurements, however in certain cases simula-tion has been used in predicting thermal behavior in new device designs [12]. The fundamental concept behind simulating thermal resistance is to calculate the tem-perature of a device by solving the heat equation for a geometric representation, which will be referred to in this thesis as a "thermal model" for a device. The heat equation, which is given in Equation 1.1, is a boundary value problem in time and space. dT c— = V-(kVT) + s(x,y,z,t) (1.1) In Eq. 1.1, k and c represent the thermal conductivity and heat capacity respectively, and are properties of the material which may vary with the spatial coordinates. The s term represents heat sources or sinks, and allows for a power dissipation which may vary with position and time. Eq. 1.1 can be simplified if we consider only the steady-state behavior of the temperature, this is appropriate if we are only interested in the thermal resistance, and not the transient thermal behavior. In steady-state case, the heat equation is reduced to V • (fcVr) + s{x,y,z) = 0 (1.2) The semiconductor materials from which transistors are made are normally sufficiently homo-geneous that it is reasonable to assume that the thermal conductivity term is constant within 9 regions of the same material. The boundary conditions that are relevant to self-heating prob-lems can be classified as either Cauchy or Neumann type conditions, the Cauchy condition specifies the temperature on a surface whereas the Neumann condition specifies a heat flux across a surface. The physical interpretation of these conditions is that a Cauchy condition specifies a heat sink of fixed temperature and a Neumann condition either specifies an insu-lating boundary (heat flux equal to zero) or a heat source on the surface. Using Eq. 1.2, the problem of simulating self-heating becomes that of specifying a model of a transistor which includes a geometric description of a device, the thermal conductivity of regions of different materials, the location of power dissipation and boundary conditions for the external surfaces of the device. The most simplified thermal model for a bipolar transistor is that of a rectangular heat source centered on the surface of a rectangular slab, as shown in Fig. 1.4. In this model the Figure 1.4: The simple patch thermal model of a transistor. The dark patch is 2-D a heat source of uniform power dissipation centered on a rectangular die. The walls of the die are considered adiabatic except for the bottom surface which is held at the ambient temperature. die is assumed to be of uniform material with constant thermal conductivity. In certain cases 10 this may be a valid assumption since the difference in thermal conductivity between the die and the doped regions is small, however in using this assumption we ignore the presence of any materials such as metals or oxides with differing thermal conductivities. The surfaces of the die are assumed to be insulating except for the bottom surface which is held at the fixed temperature of the ambient. These assumptions are consistent with the traditional style of mounting a die on a much larger heat sink and where negligible heat is lost by convection into the surroundings. The heat source is taken to have the same dimensions as the drawn emitter, which is the size specified for the emitter in the device layout. These dimensions are approximately the same dimensions as the active area of the device. The source is assumed to be so thin that it can be modeled by a two dimensional heat flux on the top surface of the die. The heat equation can be solved analytically for this simple model; the solution in terms of a series solution is documented in Refs. [13, 14]. While an analytic solution is convenient, it is computationally intensive to obtain convergent solutions [11]. As a slight variation to this model, it has been shown in Ref. [15] that if a constant angle of heat spreading is assumed, much more simplified expressions for the thermal resistance can be obtained for both rectangular and circular emitters and for devices which are not centered on the die. This solution provides a convenient compact analytic expression which is more general, but it relies on a constant heat spreading angle which must be determined analytically. The simple patch model of Fig. 1.4 can be generalized to allow for off center placement of the heat source on the die, and allow for multiple heat sources to model multi-emitter devices or multiple devices [16]. Once again, an analytic solution may be obtained in terms of infinite series. The evaluation of this solution must be performed numerically as described in Ref. [16]. 11 A second thermal model which has been documented in the literature is that shown in Fig. 1.5 [1]. In this case the device is modeled as a rectangular heat source embedded in a Figure 1.5: The semi-infinite medium thermal model for a transistor. The grey rectangular box is a region of uniform power dissipation embedded in a semi-infinite medium (the die). The surface of the die is assumed to be insulating. semi-infinite medium. The heat source is three dimensional and has the lateral dimensions of the emitter and a thickness equal to that of the base-collector space charge region ( B C S C R ) , where most of the power of a bipolar transistor is dissipated. As in the simple patch model, convection from the top surface of the die is ignored and this surface is assumed insulating. As there is only the one surface in this model, the only remaining boundary condition is that the temperature at infinity is that of the ambient. The assumption that the die extends to infinity is clearly unphysical, but is convenient since it allows for an analytic solution to the time dependent heat flow equation as described in Ref. [1]. From this solution, the steady-state thermal resistance can be computed in addition to the thermal response to a step function in power. In comparison to the simple patch model described above, this model captures a more realistic view of the heat generating region in the device. This more realistic view comes at the cost of assuming an infinite die, which fails if the substrate thickness is 12 not much greater than the dimensions of the emitter. There are very few thermal models other than the two described above which may be solved analytically. These analytic solutions are in terms of infinite power series and, al-though they are, in principal exact, numerical techniques are required to evaluate the series. Obtaining solutions which converge may be difficult and computationally demanding. There-fore for most other thermal models of transistors, numerical techniques are required to solve the heat flow equation. Of the available numerical techniques, the finite element method (FEM) is the preferred method as it is better suited to handle very complex geometries than the finite difference method (FDM), which is also used. The use of numerical techniques allows simulation of more complex geometries, as well as devices composed of multiple ma-terials. For example, in Ref. [12] models have been solved for multi-emitter devices with highly conductive layers deposited on the topside of the die, and large vias on the backside of the die for improved thermal performance. Although the numerical techniques allow for more detailed and complex models to be solved, limitations still exist and new techniques are constantly being developed to allow for more complete solutions. Several of these limitations which are relevant to the problem of a bipolar transistor will be discussed in greater detail in Chapter 2. 1.4.2 Thermal Resistance Measurement Techniques Direct measurement of self-heating has been attempted by a wide variety of methods. The problem consists of measuring the temperature within a solid three dimensional object. Since it is rather difficult to map the temperature in three dimensions, and the important 13 temperature information is in a small region near the device, most studies only attempt to measure a single average temperature of the device which is consistent with the thermal resistance model for self-heating. The task of measuring device temperature is not trivial since advanced devices have submicron dimensions and are embedded beneath the surface of the die and several other layers of metal and oxides. The two types of measurements which have been employed to measure device temperature are direct mapping and indirect measurement by the effects on electrical performance of the device. Direct mapping of temperature can be done in several ways. One method is to use optical imaging techniques to probe the temperature of an active device which can then be used to calculate a thermal resistance [8, 16]. These methods produce a two dimensional temperature map of the top surface of the die by either detecting infrared radiation or imaging of polarization changes due to liquid crystal phase transitions. The infrared method is the most direct, the infrared radiation from a hot device is imaged and calibrated to yield a temperature map. This technique is non-invasive but suffers from low temperature resolution due to difficulties in calibration of the emissivity. The liquid crystal technique images the polarization of light reflected off a thin liquid crystal film which is applied to cover the top of the die. At a known temperature, the liquid crystal undergoes a phase transition which changes the polarization of the reflected light. In this way a single temperature contour can be imaged with very high spatial resolution, however it is very difficult to measure a number of temperature contours for the same device. A second method for direct temperature mapping is to use a very small temperature probe which may be scanned across the emitter of a device in contact with the die. While this technique is also non-invasive, it suffers from possible temperature gradients from the location of the tip to the heat generating region of 14 the device. Although the methods described above are the among the only existing methods which give spatial information about the temperature, a common limitation is that they do not measure the temperature within the active area of the device. These temperature imaging methods have been applied successfully to large power transistors in the past but are less suitable for modern submicron devices which are much smaller and have more layers of metal covering the device. Almost all techniques that are presently employed to measure thermal resistance rely on inferring the temperature from measurements of the device electrical performance. These methods are generally favored since they probe the internal device temperature without any alteration in the way the device is operated or packaged for normal use. Several methods for electrical measurement of thermal resistance have been documented in the literature. The reason for the interest in this subject is a desire for a simple measurement technique which provides accurate results and can preferably be applied to a wide variety of devices. A number of DC techniques have been employed which offer a simple method of mea-suring thermal resistance. The advantage of these techniques is that they are based on measurements which may be made with easily accessible and reasonably inexpensive equip-ment. An early DC measurement technique [17] relies on measurements of a temperature sensitive parameter, typically the base-emitter voltage or the DC current gain. Measure-ments are performed at two ambient temperatures of a known difference while keeping the temperature sensitive parameter and collector current constant. Under the assumption that the temperature sensitive parameter is not a function of the collector-emitter voltage, or equivalently that the device obeys the ideal junction law [16], the junction temperature must be the same for both measurements. Based on this assumption, the difference in tem-15 perature rise between the measurements is known and the thermal resistance, by definition, is the ratio of that difference to the difference in power at the two operating points. It is well recognized that few devices actually obey the ideal junction law, due to effects such as base width modulation, and this assumption is violated for most bipolar transistors operating in regions where self-heating occurs. In contrast, HBTs are widely believed to have greatly reduced base width modulation due to their highly doped bases. Based on this assumption, recent work has applied a slightly modified version of this technique to HBTs[18]. Results of the present work, as well as other studies, suggest that the small HBTs are not completely immune to base-width modulation, due to the very thin bases. This suggests that these types of D C techniques may not be globally applied to HBTs as well as bipolar transistors. Several studies such as those reported in Refs. [4, 5] have used a more sophisticated version of this approach by considering more detailed compact models with temperature dependent parameters, that describe bipolar and heterojunction bipolar devices more accurately than the ideal junction law. These approaches employ curve fitting techniques and analytical relationships derived from compact models to extract a thermal resistance from a series of DC measurements. In the study reported in Ref. [4], further improvements in the extraction are made by iteratively extracting the thermal resistance and the emitter resistance. These techniques, while better than the simple methods discussed above, still rely on the ability of the compact model to accurately describe the operation of the device. Other DC techniques, such as the one reported in Ref. [19] rely on fitting a linear rela-tionship to a temperature sensitive parameter and temperature for HBTs. This assumption of linearity, which has been shown to be invalid over large temperature ranges for common temperature sensitive parameters such as base-emitter voltage [19], limits the accuracy of 16 this technique. Recent work has attempted to improve upon this method by performing measurements over sufficiently small temperature deviations that linearity is only required over a small region about the measurement temperature [20]. This technique, which has only been applied to large AlGaAs power transistors, is limited by measurement accuracy for temperature deviations of less than 10 K. For this reason, it seems that it would be difficult to extend this technique to small devices which have smaller junction temperature rises, as will be shown in Chapter 4. Other thermal resistance measurement techniques are based on the use of pulsed measure-ments in which the terminal biases are rapidly changed and measurements taken immediately after switching. These methods take advantage of the fact that the thermal time constants are much longer than the electrical time constants. The earliest versions of this technique [17] use standard DC measurements of a temperature sensitive parameter, such as the base-emitter voltage, as a function of temperature at a particular low power bias point, where there is little self-heating and an ambient junction temperature is assumed. The device is then driven to a high power state where self-heating occurs and the junction temperature is elevated. The junction temperature is measured by rapidly switching the bias back to that of the low power state and measuring the temperature sensitive parameter. The DC measurements made in the low power state are then used as a calibration to convert the temperature sensitive parameter to temperature. The primary source of error in this tech-nique results from the assumption that the junction temperature at the low power bias is equal to the ambient; more recent variations on this technique[l3] have attempted to make corrections for this error. Recently, a new pulsed thermal measurement technique, which characterizes a device in 17 the absence of self heating, has received attention in the literature [21, 22, 23]. This isother-mal characterization is performed by maintaining a device at a known temperature in a state of negligible power dissipation, such that the device temperature is precisely determined. The device is then rapidly driven into a state of high power dissipation, where self-heating occurs, by the application of pulsed bias voltages, and the resulting collector current is sampled im-mediately after the bias voltages have been applied. If the current is sampled in a time frame that it is much less than the thermal time constants of the device, negligible self-heating will have occurred at the time of measurement and therefore the temperature is known to be the value determined before the bias pulse is applied. By performing these measurements at a variety of bias-voltages, current-voltage (I-V) relationships at constant base-bias and constant temperature may be obtained. An example of isothermal characterization data for a SiGe device is shown by the solid lines in Fig. 1.6, after Ref. [22]. Fig. 1.6 shows pulsed measurement data where the collector-current has been measured at various intervals after the bias-pulse is applied, to illustrate the effects of the pulsed measurement. For the longest interval, the device has had sufficient time to heat up and the resulting characteristic ap-proaches that which would be measured with steady-state techniques. As the measurement time interval is decreased, the resulting characteristics show decreasing output conductance, as expected for an H B T where base-width-modulation is expected to be small due to the highly doped base, and the output conductance is generally attributed to self-heating. For a sufficiently short pulse, in this case 4 /us, the output conductance no longer decreases, which indicates that the measurements are being made on a time scale too short for heating to occur and the resulting measurements (solid line) are isothermal. Several studies have shown that this isothermal device characterization can be used to 18 0.35 - r 0-00 5.00 10.00 15.00 20.00 y« (V) Figure 1.6: Pulsed I-V characteristics for a SiGe H B T for pulse lengths of 4 ps (solid line), 40 /ts (semi-dashed line), 100 /ts (dashed line) and 200 u,s (dotted line). After Ref. [22] 19 calculate a thermal resistance by comparison of the isothermal I-V characteristics to steady-state I-V characteristics taken at the same bias[11, 24]. Representative data is shown in Fig. 1.7, where the symbols represent the isothermal characteristic and the solid line a steady-state characteristic taken at the same bias voltages. At the point of intersection between the steady-state and isothermal data, the terminal biases are equal and therefore the temperatures must be the same and equal to that of the steady-state data. Both the temperature and power dissipation, which is approximated by the product of the collector current and collector-emitter voltage, are known at the intersection point. This allows for the calculation of thermal resistance. Contrary to the other thermal resistance measurement techniques presented earlier, the pulsed-bias isothermal measurement technique requires no assumptions about the electrical performance of the device as a function of temperature. As a result, the isothermal technique is not dependent on the applicability of a particular compact electrical model to a device, and can be applied to a wide variety of devices. Klecknerfll] has applied this technique to small AlGaAs and SiGe HBTs, while Mcintosh and Snowden [24] have applied the technique to power AlGaAs devices. Isothermal measurements have also been made on silicon bipolar devices [25] and power SiGe devices [22] which could easily have been extended to calculate thermal resistance. The isothermal technique is in no way limited to bipolar and heterojunction bipolar transistors, and has been shown to work for certain metal oxide semiconductor field effect transistor (MOSFET) devices as well. The versatility of the pulsed-bias techniques come at the cost of a more complicated experimental setup, compared to the D C techniques, due to the requirements to make precise voltage and current measurements while switching the device on a time scale faster than that for self-heating. Since these thermal time constants are largely determined by the 20 4 0 1 2 3 4 Collector-Emitter Voltage (V) Figure 1.7: Determination of thermal resistance from isothermal and steady-state data. The symbols represent the isothermal measurements and the solid line the steady state data taken at the same base-emitter voltage. The thermal resistance is calculated at the point of intersection. After Ref. [11]. 21 physical size of the device, the required switching speed of the bias-pulse is dependent on the device under test. For larger power devices the thermal time constants have been shown to be on a time scale greater than 1 /is [24, 25, 22] whereas for smaller devices, Kleckner has shown that the self-heating occurs on time scales less than 250 ns. Due to the speed requirements, existing experimental setups for this measurement incorporate an array of pulse generators, precision DC sources, oscilloscopes, F E T switches, current monitors and bias networks. Additionally, specialized sample preparation which is both time consuming and destructive to the sample device may be required [11]. These issues with the isothermal pulsed-bias experimental setup and measurement technique will be discussed in greater detail in Chapter 3 as it is the method chosen for the present work. As will be shown, significant advancements have been made in simplifying the measurement setup and eliminating the requirement for special sample preparation, while at the same time increasing the pulse speed to allow for thermal measurements on sub-micron devices. 1.4.3 Existing Thermal Resistance Results A wide variety of thermal resistance results have been obtained using the various methods presented above. The majority of thermal resistance studies have focused on large power transistors, due to the high junction temperatures under intended operating conditions. Extensive results for both B J T [16, 17, 22] and H B T [8, 18, 19, 20, 22] devices with emitter areas of 100 jim2 up to several thousand u,m2 have been reported. A smaller number of studies [1, 4, 11, 13, 26] have been reported on devices with emitter areas of less than 100 jim2 and very few results for the smallest devices offered by modern bipolar processes, 22 with emitter areas on the order of 1 /tm 2 to 10 /tm 2 [11, 4]. The most complete study to date of small devices is that of Kleckner [11], who presented a large number of results for both SiGe and AlGaAs HBTs with emitter areas from 0.6 /tm 2 to 64 /tm 2. From these results, Kleckner investigated the relative benefits of various emitter geometries. While many self-heating studies focus on characterizing existing devices, other studies have looked at improving device performance through designs which reduce self-heating. A number of results have been presented showing how self-heating may be reduced using exist-ing processing techniques through breaking large devices into interdigitated emitter fingers or discrete devices [11] and how the spacing may be optimized for thermal performance [12, 18]. Other studies have investigated the increased self-heating in devices which are electrically isolated, and in the same process unintentionally thermally isolated, from the substrate by buried layers and deep trenches made from silicon dioxide[4, 11, 26, 10]. Another class of studies has addressed the problem of improving thermal performance through specialized device processing such as backside thermal vias on the substrate [12] and flip-chip packaging with large planes of metal on the surface of the die for heat distribution [27]. 1.5 Overview 1.5.1 Summary of Thesis This thesis describes a study of self-heating in a large variety of bipolar and heterojunction bipolar transistors fabricated in silicon, silicon germanium and gallium arsenide processes, covering a range of emitter areas from 0.5 /tm 2 to 64 /tm 2. The devices are studied from 23 an experimental standpoint through measurement of thermal resistance using a significantly improved version of the isothermal pulsed-bias technique, modeled after the setup used by Kleckner [11]. Improvements to the performance of the experiment consist of a 30 times increase in the switching speed of the bias pulse. This improvement is shown in the top panel of Fig. 1.8 where the solid line is the base-bias pulse from present work, and the dashed line is that from the work of Kleckner [11]. This increase in speed is necessary for correct measurements on the smallest devices currently available as is apparent from the bottom panel of Fig. 1.8 which shows the collector current transients for both the data from the present work (solid line) and that of Kleckner (dashed line) for identical devices, at different base voltages. The data from the present work clearly indicates that for such a device, substantial self-heating occurs in a time frame shorter than the rise time of the former work. The extrapolation correction for heating during the switching of the device which Kleckner used to correct for this effect, as shown by the dash-dot line in Fig. 1.8, introduces some error in the isothermal measurements because the response is not a simple exponential. Simultaneous to improvements in the performance, the present work has greatly simplified the experimental setup by the incorporation of microwave probes and a thermally controllable chuck which eliminate sample preparation and reduce the measurement time from days to hours per device. To facilitate a theoretical study of the devices tested, a new tool has been developed to numerically solve detailed thermal models for transistors using the F E M . This tool is based upon a recently developed adaptive mesh generation algorithm and an iterative finite element solution and refinement technique developed in numerical analysis research labo-ratories elsewhere. These public-domain tools are ideally suited for use on the transistor 24 1 1.5 time (LIS) 0 0.5 1 1.5 2 time (LIS) Figure 1.8: Comparison of the base bias-pulses (top) and the collector current transients (bottom) between the improved measurement setup reported here (solid line) and that used by Kleckner (dashed line). The Dotted line in the bottom panel shows the extrapolation Kleckner had to use to extract the isothermal collector current. 25 heat flow problem, as well as other complex geometry heat flow problems, and provide the flexibility to move beyond the simple analytically-solvable thermal models used to date, and create models which more accurately represent the topography and composition of modern devices. Using this tool, models including trench isolation, metalization interconnect and electrothermal feedback have been simulated. Using the above tools, experimental measurements were made on a large collection of silicon and SiGe devices and compared to corresponding simulation results. In addition, the simulation tools were applied to a large collection of AlGaAs devices in order to compare with existing measurements found in Ref. [11]. The results obtained are organized into several studies which highlight their relevance to circuit design with current devices and their importance to future device design and modeling. A study of layout dependence of thermal resistance is performed based on results for ten silicon bipolar devices of two emitter widths and various lengths. Results for a subset of the silicon bipolar devices are compared to trench-isolated SiGe devices (Fig. 1.9) of similar emitter areas to investigate the effects of the isolation on self-heating. Detailed simulations of several models including different trench isolation components are performed to assess their relative importance to the thermal resistance. The full collection of results for Si, SiGe and AlGaAs along with simulation data is discussed in terms of the scaling of thermal resistance with area. From the scaling data, a new phenomena of weak scaling in small devices is observed and further investigated through detailed simulations including interconnect metalization and process specific details of topology. Several new results are obtained from these investigations including newly documented effects of the emitter metalization on self-heating. 26 4 2 3 4 5 6 8 10 Emitter Area (|um2) Figure 1.9: Experimental (symbols) and theoretical (lines) results for silicon (solid circles, dashed line) and trench isolated SiGe (solid triangle, solid line) devices for three identical emitter geometries. The emitters are 0.5 [im wide and 5, 10 and 20 \im in length. The results show similar scaling between the two technologies despite the large increase in magnitude of thermal resistance due to trench isolation. 27 1.5.2 Outline The remainder of this thesis is divided into three chapters covering the theoretical methods, experimental methods and results. Chapter 2 presents the tools that have been assembled to facilitate the theoretical predictions, and outlines the process involved in obtaining the solution. Methods of verifying the accuracy of the simulation process, as well as the specific issues relevant to transistors are also presented here, as is a detailed description of the devices and the models which are used to represent them. Chapter 3 provides the details of the experimental technique and the setup used. The specific details on the modifications to the technique for the purposes of this work are outlined and their relevance discussed in terms of new functionality and increased ease of use. Chapter 4 presents the results of experimental measurements and theoretical simulations. The thesis concludes with a discussion of the impact of the results and their relevance to present circuit designers, device modeling techniques and future device processing. Finally, Appendix A is included to provide details of the custom circuitry developed for the experimental setup which gives sufficient detail to those interested in duplicating the setup. 28 Chapter 2 Devices and Modeling 2.1 Devices 2.1.1 Silicon bipolar The silicon bipolar devices studied in the present work were fabricated using the NT25 process offered by Nortel Networks. NT25 is a full custom IC process offering N P N bipolar devices with an FT of 25 GHz. Using this process, two ICs were designed containing a wide variety of both standard design kit and custom devices specifically intended for thermal measurement. The design kit devices consist of single emitter devices with an emitter width of 0.5/im and lengths of 1.3, 2.5, 5, 10, 20 and 40/Ltm. In addition, custom single emitter devices with a non-standard width of 1.1/im and lengths of 1.3, 2.5, 5, 10, 20 and 40/Ltm were also fabricated. A l l devices tested are on the same 500/mi thick die which measures 5 x 5mm2 laterally. 29 2.1.2 GaAs One of the GaAs devices tested is a self-aligned, graded-emitter AlGaAs/GaAs H B T with a 3x3/tm 2 emitter fabricated by Nortel Networks; details regarding the performance and structure of the transistor can be found in Ref. [28]. The metalization used to contact the emitter and base is of particular importance in the present work. The emitter is contacted through an Ohmic layer with the same lateral dimensions as the emitter and 0.3/tm thick. Connection from the Ohmic layer to a 3/tm wide interconnect strap 1/tm thick and 9/tm long is made through an emitter post which has an area of approximately 2/tm2 and is Ifim in height. The interconnect strap connects to a large area metal stripline and bonding pad. The base is contacted through a base-metal 0.3/mi thick which surrounds the emitter with a clearance of 0.7/iin and is at least 2/tm wide on all sides. Connection from the base-metal to a 4.4/im wide interconnect strap 1/im thick and 11 /im long is provided through a cubic base post 2.4/im a side. A l l interconnect metalization is gold. The device has been fabricated on a 635/tm thick die which measures 2 x 2mm2 laterally. The majority of the GaAs H B T devices studied were fabricated at the Rockwell Science Center, using a process described in [3]. The devices investigated have square, circular, one- or two-finger rectangular emitters. Square devices measure 1.2, 1.4, 2, 4, and 8 //m a side and circular devices have diameters of 2.4 and 3.9 /tm. A l l rectangular devices have finger widths of 1.4 /tm, with lengths of 3, 6, 9 and 12 /tm; the two-finger devices have an inter-finger separation of 3.4 /tm. Contacts to the emitter of the devices is made with a 1/tm thick gold layer. The emitter contact is deposited directly on the T i / A u emitter Ohmic. For modeling purposes in this work, the emitter contact is assumed the same size as the emitter. 30 A l l devices were fabricated on the same wafer, the thickness of which is 635 /um; the die is approximately 5x5 mm2. 2.1.3 SiGe The SiGe H B T devices tested consist of single-finger, 0.5 /um wide rectangular emitters with lengths of 1, 1.3, 2.5, 5, 10 and 20 lira fabricated by I B M . The devices are electrically isolated, and consequently thermally isolated, using deep and shallow trench structures. The silicon dioxide shallow trench is approximately 1 /um deep and surrounds the active area of the device with a clearance of 0.35/um. The oxide extends laterally over the entire area of the die, with the exception of a subcollector via and a window around the emitter. The deep trench is embedded in the die and surrounds the entire device, including subcollector. The walls are approximately 1 /um thick and 6 /um deep and composed of silicon dioxide with a polysilicon interior. A l l devices are fabricated on the same 10 x 10mm 2 substrate which is thinned to approximately 250/um. Additional details on the process and electrical performance of the devices can be found in [29, 30]. 2.2 Description of Models As discussed in Section 1.1, the simulation of self-heating begins with the specification of a thermal model for which the heat equation, Eq. 1.2, is to be solved. The model includes information about the geometry and composition of the material, the boundary values to be applied and information about the location and magnitude of power dissipation. The specification of most thermal models requires many assumptions about these factors due 31 to the complexity of an actual device. Due to limitations in lithographic techniques, the exact geometry of a real device is not exactly as it was designed, and appears much more rounded with boundaries between materials not always well defined. Uncertainty also exists in the thermal conductivity of the materials, which may be affected by mixing of materials or impurities, either intentional or unintentional, introduced in processing. The location of the power dissipation must also be determined through electrical studies of the device. Section 1.4.1 introduced two of the commonly used thermal models which are based on a large number of assumptions in order to obtain a model for which an analytic solution can be obtained. A goal of the present work has been to remove some of the weaker assumptions by adding more realistic elements to the models. In the remainder of this section, the device models designed for this work and the technologies they represent will be described. 2.2.1 Basic 3-D Source Model The basic model used in this work, of which all others are variations, consists of a 3-D heat source embedded under the surface of a finite rectangular die, as pictured in Fig. 2.1, where only one quarter of the die is shown due to symmetry. This model combines the two traditional models discussed in Section 1.4.1, taking the more generalized view of a 3-D heat generating region and combining it with a realistic finite die. As in previous models, boundary conditions are applied which specify all external surfaces of the die to be insulating, with the exception of the bottom surface which is held at the ambient temperature, shown as the dark surface in Fig. 2.1. These boundary conditions are consistent with the traditional method of mounting the die on a heat sinking package, where heat loss due to convection 32 Figure 2.1: 3-D heat source thermal model showing one quarter of the symmetric die. The grey region located under the top surface of the die represents the base-collector space charge region. The bottom surface of the die (dark shading) is held at the ambient temperature. The diagram is to scale, but only shows the area around the active region. 33 from the exposed sides of the die are negligible in light of the low temperature rises and small area of the external surfaces. The 3-D heat generating region is taken to be the dimensions of the base collector space charge region (BCSCR) at an appropriate depth beneath the surface of the the die, shown by the shaded grey region in Fig. 2.1. This is the location at which most of the electrical power is dissipated under normal operation of the device. Where possible, the dimensions of the B C S C R are calculated from available process details for a typical bias at which self-heating occurs. The power dissipation is also computed from this operating point and assumed to be dissipated uniformly throughout the BCSCR. The composition of the die is assumed to be entirely uniform and variations of thermal conductivity due to dopants or impurities are ignored. This assumption is somewhat process dependent, but is generally true for impurity concentrations of less than 10 1 8cm~ 3[l]. It should be noted that this assumption may be violated by modern HBTs and may require further investigation. The planar adiabatic top surface in this model ignores any effects of metalization or oxide layers present; while this assumption may be valid for low thermal conductivity oxides, it may not be valid for high thermal conductivity metals. The planarity of the top surface of the die also leads to some ambiguity as many devices may be built on pedestals or surrounded by vias. In the present work the top of the die is taken in reference to the top surface of the emitter area. This model, which is sufficiently general to be applied to many processes, has been used to model the silicon bipolar NT25 devices using a thermal conductivity of 150 Wm~lK~l. The depth and thickness of the BCSCR are taken as 0.25 /im and 0.16 \xm respectively and the lateral dimensions are defined by the drawn emitter. 34 2.2.2 Rockwell GaAs Models Perhaps one of the weaker assumptions of the thermal models presented so far is the neglect of heat flow into the metalization interconnect on the top surface of the die. Due to the close proximity of the metal to the heat generating region, it is quite possible that some heat flows into the interconnect, which generally has a large area compared to the device, and the heat may be dissipated by processes such as conduction into the substrate and external wire connections, or convection to the ambient. Previous studies on silicon devices [1] have considered this a negligible effect, however, this assumption becomes more problematic for modern GaAs devices. Such devices have a low thermal conductivity substrate, a gold interconnect with thermal conductivity six times that of the GaAs substrate, and improved metalization contact to the emitter. To investigate the validity of this assumption, the model for the Rockwell GaAs devices is constructed by the addition of emitter interconnect metalization to the basic 3-D source model shown in Fig. 2.1. The resulting model is shown in Fig. 2.2 where the light shaded region is the metalization and the remainder of the model is identical to the basic 3-D source model. In this case, the entire die is simulated to allow for a geometry with no symmetry due to arbitrary metalization. The model for the interconnect metalization includes only the portion of the metalization near the device; at the point where it joins a large area of metalization, the strap is truncated and a boundary condition of the ambient temperature is applied. The use of the boundary condition provides a means to model the various processes through which a large area metal strap may dissipate heat. The remaining faces of the metalization are considered to be insulating; this assumption allows us to omit the thermally insulating oxide which encases the metalization, reducing 35 the complexity of the model. This neglects any heat flow from the metalization near the device back into the die, which is a reasonable assumption since such heat redistribution would occur only for great areas of metal, and is already accounted for in the use of the heat sink boundary condition at the end of the metal strap. This model has been extended to include the round and two-finger emitter Rockwell AlGaAs devices, as shown in Figs. 2.3 and 2.4. For the case of the round emitter, the BCSCR is simply changed to a cylindrical volume of the appropriate diameter. The emitter contact, which remains rectangular, is taken as a square with edge length equal to the emitter diameter. For the two-finger devices, two identical B C S C R are used; in this case the emitter metalization is split into two fingers covering each of the BCSCR. A l l dimensions for the die and metalization have been extracted from process details and layout data as described in Section 2.1. The depth and thickness of the B C S C R are calculated to be 0.31/mi and 0.35/tm respectively. The substrate conductivity is taken as that of GaAs at 300 K , 48 Wm^K'1. 2.2.3 Nortel GaAs Models A similar approach has been taken to model the Nortel AlGaAs device with several modifi-cations due to differences in process details. In this case, the emitter contact is made with a via from the metal interconnect layer to the emitter Ohmic layer, as described in Section 2.1. This emitter metalization configuration has been modeled appropriately as shown in Fig. 2.5, where the Ohmic contact, post and interconnect strap are all shaded light grey. A second modification to this model, compared to that of the previous section, is the addition of to-36 Figure 2.2: Thermal model including metalization for single emitter Rockwell AlGaAs de-vices. The metalization strap (light grey region) contacts the die only above the BCSCR (grey box). A l l surfaces are insulating except the bottom of the die (dark shading) and the far end of the metalization strap (not shown). The diagram is to scale, but only shows the area around the active region. 37 Figure 2.3: Thermal model including metalization for circular emitter Rockwell AlGaAs devices. The details of this model are identical to that of Fig. 2.2 with the exception that the BCSCR (grey disk) has been replaced by a cylindrical volume. The diagram is to scale, but only shows the area around the active region. 38 Figure 2.4: Thermal model including metalization for Rockwell two-finger emitter AlGaAs devices. The details of this model are similar to that of Fig. 2.2, with the addition of a second B C S C R (grey boxes). The emitter metalization (light grey region) has been modified to include a finger to contact each emitter. The diagram is to scale, but only shows the area around the active region. 39 pographical information for the die. As Fig. 2.5 shows, the B C S C R (grey box) is situated within an island of GaAs raised above the surface of the die. While this island may not affect heat flow greatly in this model, it is included for consistency with a second model for the Nortel AlGaAs device including base metalization. The base metal model, shown in Fig. 2.6, is included to investigate the relative effects of base metal on self-heating compared to the emitter metalization models. As shown in Fig. 2.6, the base contact metal covers the surface of the device island, with the exception of a window above the emitter. The base contact metal connects to the interconnect strap through a via; all of the metal is shown as a light grey shaded region. 2 . 2 . 4 S i G e M o d e l The model for the SiGe H B T devices requires the addition of deep and shallow trench structures, as described in Section 2.1. The shallow trench is modeled by placing the B C S C R within a small device island that is surrounded by a silicon dioxide region which extends to the outer boundary of the deep trench. The deep trench is embedded in the die, surrounding, but not centered on, the device. The deep trench is modeled as a uniform material with an average conductivity equal to the volume-weighted average of the silicon dioxide and polysilicon walls. The thickness of the deep trench is taken as the total thickness of the polysilicon, plus the external oxide walls. This simplification, which correctly models heat flowing horizontally through the trench walls, is used to reduce the complexity of the model. The resulting thermal model is shown in Fig. 2.7. The deep and shallow trenches are drawn with transparent faces to show their 3-D nature. 40 Figure 2.5: Thermal model including emitter metalization for Nortel AlGaAs device showing one half of the symmetric die. The emitter metalization (light grey region) includes the Ohmic contact, via and interconnect strap. The diagram is to scale, but only shows the area around the active region. 41 Figure 2.6: Thermal model for Nortel AlGaAs device including base metal showing one half of the symmetric device. The base contact, via and interconnect metalization are shaded light grey. The diagram is to scale, but only shows the area around the active region. 42 Figure 2.7: Thermal model for trench isolated SiGe devices showing one half of the sym-metric die. The region surrounding the B C S C R (grey box) represents the shallow trench silicon dioxide, under which the deep trench is embedded. Emitter metalization including an interconnect strap and via are shown as the light grey region.The diagram is to scale, but only shows the area around the active region. 43 2.3 Overview of solution technique The finite element method (FEM) is one of a number of techniques which can be used to numerically solve boundary value problem (BVP) differential equations. The details of this widely used technique are described in Refs. [31, 32]; in the following paragraph we only overview the main features. Initially developed to solve mechanical problems, the F E M was derived from an intuitive sense of breaking an object into many small elements which are considered to connect only at their corners, or vertices. This method has since been formalized by mathematicians in terms of the weak formulation of a differential equation and the Galerkin approximation, which approximates the solution of a B V P at a discrete number of N points by solving a system of N linear equations. This formalization has led to the use of the F E M to solve a variety of heat-flow, fluid-flow and electromagnetic field problems. The widespread use of this method is mainly due to the capability to handle very complex geometries, and suitability of the calculation to be automated by computer. The method is mainly limited by the computational capabilities and memory requirements of present computers to assemble and solve the set of linear equations. The assembly of the problem requires N3 numerical integrations over the elements, which rapidly limits the total number of elements. To overcome this limitation, two techniques are commonly used. The first is to use a varying element size to reduce the total number of elements, since the F E M has no requirement that the elements be of uniform size. The minimum number of elements is limited by the amount of error which may be tolerated as well as the number of locations at which the solution is desired. The second method to overcome computational limitations is to use alternate solution techniques which may include sparse matrix or iterative solvers. 44 Details of the derivation and computer implementation of the F E M will not be presented in this work as they are well documented elsewhere [31, 32]. The remainder of this chapter will focus on the implementation of the F E M in solving the steady-state heat flow problem for bipolar transistor devices and the specific challenges related to this problem. 2.3.1 Discretization of the Thermal Model In order to apply the F E M to solve a thermal model for a transistor, it is necessary to divide the model into elements which form the finite element mesh. The task is complicated for the transistor models presented above, due to the vastly different length scales between the actual device and the die, which differ by a factor of about 1000. If the element size were fixed at a fraction of the smallest length involved in the problem, it would require more than 10003 elements to mesh the entire model, which is far beyond the capabilities of F E M solvers. Instead it is necessary to use a computer to automate an algorithm which is capable of creating a mesh constructed of non-uniformly sized elements. The present work uses the Q M G quadtree/octree algorithm [33] which minimizes the number of elements while maintaining a low aspect ratio for the elements. This algorithm has been implemented in C++ and has made publicly available by S. Vavasis [34]. Representative data showing the surface patch thermal model and corresponding mesh generated by Q M G are shown in Figs. 2.8 and 2.9 respectively. The model in Fig. 2.8 corresponds to a 3 x 3u,m2 GaAs device at an ambient temperature of 300 K. 45 Figure 2.8: Surface patch thermal model of 3 x 3u.m2 GaAs device, for solution by F E M . Due to symmetry, only one quarter of the die need be simulated. The uniform heat source patch on the top surface is barely visible since this model is drawn to scale. 46 Figure 2.9: The mesh as produced by Q M G for the surface patch thermal model shown in Fig. 2.8. Only mesh points on the external surfaces have been plotted for increased clarity. 47 2.3.2 Solution and Refinement Once an initial mesh is obtained, the F E M may be applied to obtain a solution for the temperature. To ensure that an accurate solution is obtained in a reasonable amount of time, a multistep process is used. The process begins by applying the F E M to solve for the temperature on the initial mesh and then performs an error estimation for the solution. Elements which exceed the error tolerance are then locally refined and the solution process repeated until the entire solution falls within the error tolerance, set to 1%. To reduce the computation time for the F E M solver, a preconditioner and iterative solver are used. Fast convergence is obtained during mesh refinement stages by using the solution of the previous stage as the initial values for the iterative solver. This solution and refinement technique has been implemented by Beck, Roitzsch, and Erdmann [35] as a package of C++ code which is freely distributed under the name Kaskade. This is the solver which has been used in the present work since it is ideally suited to solve the complex geometrical problem of a transistor in a large die. In addition, Kaskade is distributed as source code so it may be integrated with the meshing and data processing portions of the solution process. Representative data of the refined solution mesh is shown in Fig. 2.10. Through comparison of the initial and refined mesh, Figs. 2.9 and 2.10 respectively, it is apparent that a large amount of mesh refinement is required in order to obtain a solution, even for the most basic model which we investigate. 48 Figure 2.10: The mesh for the surface patch model after three solution and refinement steps where temperature errors have been reduced below 2%. Only mesh points on the external surfaces have been plotted for increased clarity. 49 2.3.3 Interpretation of the Data Using the finite element solution it is possible to investigate the self-heating in the device by probing for the temperature at various locations. Primarily we are interested in the temperature near the base-emitter junction, which is sufficiently thin that no substantial temperature gradients exist in the vertical direction. Thus the temperature is extracted in a 2-D plane at an appropriate depth representing the base-emitter junction. In the case of the surface patch model example, the device is represented by a 2-D heat source and the temperature is measured in this plane. Representative data showing the temperature across the emitter for the surface patch model for a 3 x 3/^m2 device at a power dissipation of 5.3 mW and die temperature of 300 K is shown in Fig. 2.11. The data in Fig. 2.11 shows that the temperature is extremely non-uniform, the temperature rise varies by a a factor of 2, which suggests that a single thermal resistance is insufficient to model this device. To facilitate comparison with experiment, a thermal resistance may be calculated using an area based average of the temperature over the emitter area. For the data of Fig. 2.11, a thermal resistance of 3.3 K / m W is obtained. 2.4 Verification of the Method To assess whether the solution process described above provides a valid solution to the heat equation, several problems are solved for which analytic solutions exist. 50 Distance from center (urn) Figure 2.11: Solution temperature contours on the emitter for a 3 x 3/mi 2 GaAs device obtained using the surface patch model. One quarter of the symmetric emitter is shown. 51 2 . 4 .1 One dimensional heat flow The most trivial solution to the heat equation is that for one dimensional heat flow, as diagramed in Fig. 2.12. The bar, which measures 1 x 3 x 9 fj,m, is given the thermal Figure 2.12: F E M validation, model for one dimensional heat flow in a rectangular bar 1 x 3 x 9 (j,m. Heat flows only in the x direction, where a 300 K heat sink is placed at x=0 and a 5.3 mW heat source is placed at x=9 \ira. conductivity of aluminum, 235 Wm^K"1. A heat sink of 300 K is placed at one end of the bar while a heat source of 5.3 mW is placed at the opposite end. The dimensions and power dissipations are intentionally taken to be in the same units of the transistor problem. The solution for the temperature in the bar as a function of x is given by the linear function The F E M solution procedure described above is applied to the 1-D heat flow model shown in Fig. 2.12 and the results are presented in Fig. 2.13. The top panel of Fig. 2.13 shows Eq. (2.1). (2.1) 52 1 E CD 8(3.5 crj -t—1 00 b 0 0 380 00 00 o oo o oo cn O 2 4 6 Distance (LUTI) 2 4 6 Distance (LUTI) oo CO o 8 Figure 2.13: Top panel: Temperature contours on one face of the bar. Bottom Panel: Calculated temperatures (circles) compared to exact solution for one-dimensional heat flow problem (solid line). 53 temperature contours on one of the faces of the bar and indicates that solution temperature is only function of x as expected. The temperature of all solution points is plotted against the x coordinate and compared to Eq. (2.1) in the bottom panel of Fig. 2.13, which show exact agreement. 2.4.2 Comparison with Analytic Solution for Simple Patch Model A more thorough test of the capabilities of the F E M solution technique to solve the complex geometries of the transistor models is done through comparison with the analytical solution for the surface patch model, as described in Section 1.4.1. Fig. 2.11 has shown the results of the F E M technique applied to the surface patch model for a 3 x 3 jum2 GaAs device. This emitter geometry, power dissipation of 5.3 mW and die temperature of 300 K is chosen since the identical problem has been solved by Kleckner [11] using the power series approx-imation to the analytic solution to the problem. These results are shown in Fig. 2.14 as temperature contours for one quarter of the emitter and show excellent agreement with the results presented in Fig. 2.11. Small differences in the results may be attributed to the 1% error tolerance for the F E M results, as well as the low resolution in the analytic temperature data. The low resolution in the analytic data results from the large computational time required to obtain each solution point [11]. In the case of the F E M solution, a highly refined mesh of temperature points are obtained in several seconds, demonstrating the power of this technique. 54 0 0.5 1 1.5 Distance from center (LUTI) Figure 2.14: Temperature contours on the emitter for a 3x3/um2 GaAs device obtained from the analytic solution for the simple patch model. One quarter of the symmetric emitter is shown. After Ref. [11] 55 Chapter 3 Thermal Resistance Measurement System Based on Pulsed Isothermal Characterization 3.1 Experimental Setup The experimental setup used to make the isothermal current-voltage (I-V) measurements, based on the work of Kleckner[ l l ] , is shown in F ig . 3.1. In the present setup, the die is mounted on a temperature controlled chuck and held at a known temperature. A constant collector-emitter voltage and a low duty-cycle pulsed base-emitter voltage are applied at the device terminals and the resulting collector current is monitored as a function of time. There is an important difference between the setup shown in F ig . 3.1 and others which pulse both the base and collector voltages[24]. Pulsing only the base voltage prevents the device from passing through saturation during turn on, where large negative collector currents may 56 flow. Such large currents during the turn on may lead to self-heating which degrades the isothermal measurement. Figure 3.1: Schematic representation of the isothermal measurement setup. The base-emitter bias pulse is created and applied to the device using the custom circuitry shown in the simplified schematic of Fig. 3.2, consisting of a pulse generator and an output driver stage. The pulse is generated by an emitter coupled logic (ECL) gate circuit as shown in the left dashed box in Fig. 3.2. In this circuit, the current provided by the current source flows through one of the arms of the differential pair of bipolar transistors, based on the relative voltage of the trigger pulse and the reference voltage, Vref. In the case that the trigger pulse is less than Vref, the current flows through the right arm of the differential pair and the voltage at the output is the supply voltage, Vbe, minus the IR drop of 250 mV in the 50 0 resistor. In the case that the trigger pulse voltage is greater than Vref, the current flows through the left arm and the voltage at the output is exactly Vbe. The resulting output pulse therefore has a high state which is set by the reference voltage and a low state 250 mV less, 57 Pulse generator Output driver Figure 3.2: Simplified schematic of base pulse generation circuit sufficiently low to ensure that the device under test will be off in the low state. The accuracy of the voltage in the high state, which is the important quantity for this measurement, is determined solely by the reference voltage, and can be any precision voltage source. Since the output voltage precision is not dependent on the trigger pulse, a simple pulse source may be used to set the timing of the pulse. The rise time of the output pulse is also independent of the trigger pulse and is largely determined by the speed of the circuitry. The output of the pulse generator must be applied to the device under test through a high input impedance output buffer to avoid I R drops in the high state voltage due to current at the output. The output driver, shown on the right of Fig. 3.2, consists of a buffer with a capacitively-coupled 50 0 termination at the output to suppress oscillations of the D U T in the GHz range. A second buffer is used to drive a copy of the base pulse signal to an oscilloscope. The custom circuitry used to provide the collector-emitter voltage and monitor the re-58 suiting current is shown in F ig . 3.3. A feedback circuit is used to drive the output current through a current measuring resistor, Rmeas while fixing the output voltage to be equal to the input voltage, Vce. A differential amplifier is used to sense the voltage across Rmeas and the resulting voltage signal, which is proportional to the collector current, is monitored on an oscilloscope. As with the base output driver, a capacitively-coupled 50 fi termination is used at the output to eliminate parasitic oscillations of the D U T . The circuits shown in Figs. 3.2 and 3.3 have been implemented to meet a switching speed requirement of 5 ns. This requirement is based on the assumption of the isothermal measurement that the rise time must be less then the fastest thermal time constants of the devices, which have been shown to be on the order of several hundred nanoseconds for small devices [11]. To meet this speed requirement, the circuits have been implemented with 1 G H z operational amplifiers and 4 G H z N P N transistors; detailed schematics are shown in Appendix A . The circuits are assembled on high frequency printed circuit boards using surface mount components; the circuit board artwork is also shown in Appendix A . In order Scope Figure 3.3: Simplified schematic of collector current monitor 59 to minimize overshoots in the current and voltage outputs during the switching, care must be taken to eliminate capacitive load seen by the output drivers. This has been achieved through mounting the circuits directly on the microwave probes, eliminating the capacitive load of long coaxial cables. A block diagram of the entire experimental setup is shown in F i g . 3.4. The base pulse generator and collector current monitor are connected to the device v ia the microwave probes on which they are mounted. The precision base and collector voltages are provided to the pulse generator and current monitor by a HP4155A semiconductor parameter analyzer, act-ing as a simple voltage source. The base voltage and collector current signals are monitored by a Tektronix TDS320 digital averaging oscilloscope. The scope is triggered by the Tek-tronix 115 pulse generator, which also controls the t iming of the base voltage pulse. A P C computer is used to control the temperature of the chuck as well as the base and collector voltages such that the measurement may be automated. The P C is also used to collect the base voltage and collector current data, averaged over 256 base pulses, from the oscilloscope. 3.2 Measurement Technique 3.2.1 Isothermal Voltage-Current Measurements Representative data taken from the oscilloscope scope for a 0.5 x 5/Ltra 2 SiGe device is shown in F ig . 3.5 for a base-emitter voltage of 879.9 m V and collector-emitter voltage of 3.9 V . F ig . 3.5 (a) shows the base-emitter voltage pulse and F ig . 3.5 (b) shows the collector current response to the pulse; both sets of data are averaged over 256 pulses by the oscilloscope. The 60 Tektronix TDS320 scope Picoprobe microwave probes Base pulse gen. Signatone hotchuck Tektronix 115 pulse generator HP4155A Collector current monitor Figure 3.4: Block diagram of experimental setup averaging of a periodic pulse is useful in reducing the noise in the measurements and does not affect the fundamental assumption of the isothermal measurement, namely that the device temperature is equal to the die temperature at rising edge of the pulse, as the pulse duty cycle is less than 1%. Self-heating is evident in the collector current data over the duration of the pulse, where the collector current changes drastically despite the constant terminal biases, indicating a temperature change must be occurring. The isothermal current that we are interested in is the collector current immediately after the pulse is applied, before self-heating occurs. Although this may be obtained in a single measurement, the base pulse data and a portion of the collector current response are recorded to assist in better estimating 61 1 1.5 time (LIS) 1 1.5 time (LIS) 2.5 2.5 Figure 3.5: Representative transient data for a 0.5 x 5/jra 2 SiGe device taken at a base-emitter voltage of 879.9 m V a collector-emitter voltage of 3.9 V and a temperature of 308 K . Panel (a) shows the base-emitter bias pulse while panel (b) shows the collector current response to the pulse. 62 the isothermal collector current. The base pulse is used to establish the precise rise time of the pulse and the collector current transient is fit to a smooth curve to assist in estimating the isothermal current. Based on the previous work discussed in Section 1.3.2, we expect the temperature re-sponse may be expressed by a sum of exponential curves of various time constants. Assuming that for small temperature rises the collector current is a linear function of temperature [11], we also expect the collector current transient may be expressed as a sum of exponential curves. As discussed in Section 1.3.2, previous studies have assumed a single time constant is sufficient to describe the thermal response of a device in die form. Based on this, we use a single exponential curve to fit the collector current transient, for purposes of estimation of the isothermal current. Data and the corresponding fit for the entire transient curve are shown in the top panel of Fig. 3.6, where the dark ticks at the top of the panel indicate the range over which the fit was done. These results show a single exponential provides a reasonable fit to the collector current transient on the time scale of microseconds, however, the fit is quite poor over the first few tens of nanoseconds, showing that a much faster time constant dominates on that time scale. This indicates that a single time constant does not accurately represent the thermal response of a transistor in die form, and at least two time constants are needed for a good fit on all time scales. Since this work is not concerned with extracting thermal time constants, the single exponential is fit over a sufficiently short portion of the transient that it provides a good fit and allows estimation of the isothermal collector current, as shown in the bottom panel of Fig. 3.6. By performing isothermal current extractions for a range of collector-emitter voltages, an isothermal I-V curve at constant base-emitter voltage may be constructed. Representative 63 o o v - s • 1 • I I 0 0.5 1 1.5 2 2.5 time (LIS) Figure 3.6: F i t of single exponential curve to collector current transient data for 0.5 x 5//m 2 SiGe device. The range over which the data is fit is indicated by the dark ticks at the top of each panel. 64 data of isothermal I-V curves for the 0.5 x 5\xm2 SiGe device at a base-emitter voltage of 879.9 mV and temperatures of 308, 312, 317, 323 and 328 K are shown by the dashed lines in Fig. 3.7. 3.2.2 Determination of Thermal Resistance Thermal resistance may be computed by comparison of the isothermal I-V curves with steady-state curves taken at the same base-emitter voltage. The solid line of Fig. 3.7 shows such a steady-state curve taken at a temperature of 298 K . At the point of intersection be-tween an isothermal and steady-state curve, the bias voltages and resulting collector current are identical and therefore the temperature, the only remaining external variable, must also be equal. The temperature in steady-state is therefore equal to the isothermal temperature and the junction temperature rise may be calculated. The device power dissipation, esti-mated by the product of the collector-emitter voltage and collector current, is also known at the intersection points and the thermal resistance is calculated as the ratio of the temper-ature rise to this power dissipation. To ensure that the base-emitter voltage is exactly the same in both the steady-state and isothermal measurements, the same experimental setup is used to measure the steady-state curves by using a 100% duty cycle base pulse. Error bars are placed on the thermal resistance measurements by repeating the calculation and intro-ducing the maximum errors expected due to the calibration of the oscilloscope, calibration of the current monitor and uncertainty in the isothermal current estimation. 65 298 K 1 2 3 4 Collector-Emitter Voltage (V) Figure 3.7: Isothermal and steady-state I-V curves for 0.5 x 5u.m2 SiGe device. The dashed lines are isothermal curves taken at a base-emitter voltage of 879.9 mV and temperatures of 308, 313, 318, 323, and 328 K. The solid line is steady-state data taken at the same base-emitter voltage and 298 K . The thermal resistance may be computed at each intersection point between a steady-state and isothermal curve. 66 3.3 Verification of Measurements The thermal resistance measurement may be verified by comparing measurements made on a number of SiGe devices to results from other studies. Fig. 3.8 shows the thermal resistance results using the present technique for the 6 devices described in Section 2.1 as solid circles. Results obtained by Kleckner using a similar pulsed bias technique with a slower pulse rise time [11] are shown as hollow circles, a result from a simultaneous emitter resistance and thermal resistance extraction for a 0.5 x 10 u,m2 device shown as a hollow square[4], and a result from a pulsed collector-base voltage study [11] for a 0.5 x 20 / L i r a 2 device is shown as a hollow triangle. Excellent agreement is obtained in the results for the largest device for all three techniques, but a discrepancy between the present technique and the technique of Kleckner is observed as the device size becomes smaller. This discrepancy is due to the slower risetime of the former experiment, there the isothermal current is overestimated due to self-heating which has occurred during the rise of the bias pulse and leads to an underestimation of the thermal resistance. This discrepancy gets worse for smaller devices where the time constants get faster and more self-heating may occur during the application of the bias pulse. In light of the good agreement for the large device and predicted deviation for the smaller devices, we conclude that the present technique is more accurate than previous techniques, particularly for small devices. A more extensive validation of the measurements against model predictions will be presented in Chapter 4. 67 E CD O fZ crj -4—" CO '(/) CD DC "co E CD 6 5 4 t i 1 0.5' 1 2 3 4 5 6 8 10 Emitter Area (LUTI2) Figure 3.8: Comparison of SiGe thermal resistance measurements (solid circles) to exist-ing results from a similar pulsed base bias study (hollow circles), a simultaneous thermal resistance-emitter resistance extraction (hollow square) and a pulsed collector-base voltage study (hollow triangle). 68 Chapter 4 Results and Discussion 4.1 Layout Dependence of Thermal Resistance in Sili-con Bipolar Devices Measurements made on the large number of Silicon bipolar devices described in Section 2.1 are used to investigate the dependence of thermal resistance on device area and geometry. Results are summarized in Tables 4.1 and 4.2 and are shown in Fig. 4.1. In Fig. 4.1 the solid circles represent the 0.5 fj,m by 5, 10, 20 and 40 /urn emitter devices and the solid squares represent the 1.1 /um by 2.5, 5, 10, 20 and 40 yum emitter devices. Simulation results using the basic 3-D heat source model are shown by corresponding hollow faced symbols. Excellent agreement is obtained between the measured and theoretical results in Fig. 4.1. These results clearly indicate that for a given emitter area, the higher aspect emitter geom-etry yields a lower thermal resistance. While this result may be somewhat intuitive, it is surprising that the magnitude of the difference is quite large, about a factor of 1.5 for the 69 10 15 20 30 40 Emitter area (urn ) Figure 4.1: Experimental and theoretical thermal resistance results for silicon bipolar devices. Square and circular symbols represent emitter widths of 1.1/im and 0.5/mi respectively. Solid and hollow symbols represent measured and simulated results respectively. 70 Table 4.1: Thermal resistance measurements and finite element model predictions for 0.5 /um wide emitter silicon bipolar devices. LE Measured ( K / W ) Model ( K / W ) 5 /um 830 ± 90 1050 10 nm 540 ± 50 660 20 nm 370 ± 40 400 40 pm 230 ± 20 230 data in F ig . 4.1. Other than the difference in magnitude of the thermal resistance, the two emitter widths show a similar linear scaling relation in the log-log axes of F i g . 4.1. Using this linear fit, simple power laws for the thermal resistance as a function of emitter length may be obtained as given in Equations (4.1) and (4.2) for the 0.5/xm and 1.1/xm wide emitters, respectively. Rth = 732L~0MK/W (4.1) Rth = 2506L-°MK/W (4.2) These scaling laws are useful from a practical point of view as they provide a simple means of computing thermal resistance over a wide range of emitter lengths for two commonly-used widths. The ability of the basic 3-D heat source model to very accurately describe these devices indicates that specific details of the topside processing play no major role in the thermal resistance; it is completely determined by the emitter area, B C S C R thickness and depth and die thermal conductivity. In light of this result we conclude that these scaling relations should be applicable to any silicon bipolar device of a similar emitter geometry. 71 Table 4.2: Thermal resistance measurements and finite element model predictions for 1.1 /tm wide emitter silicon bipolar devices. LE Measured (K/W) Model (K /W) 2.5 jum 1100 ± 100 1330 5 /mi 800 ± 90 910 10 /tm 510 ± 5 0 590 20 /tm 340 ± 30 360 40 /tm 190 ± 20 220 4.2 Trench Isolation Effects and Modeling A detailed experimental and theoretical study of the effects of trench isolation on self-heating has also been completed using the tools developed in this work. Measurements for the 6 trench-isolated SiGe HBTs described in Section 2.1 are shown in Fig. 4.2 as solid triangles. For comparison, the diamond shows results measured using the pulsed-VCB technique and the open square shows a result from Ref. [4], obtained with an earlier version of the I B M Si/SiGe H B T technology using simultaneous extraction of the thermal and emitter resistances from steady-state current-voltage data. Considering the variety of techniques used, the consistency of the experimental data shown in Fig. 4.2 is excellent. The trench-isolated device results can be compared with several of the results presented in the previous section for silicon bipolar devices with identical geometries. This comparison is shown in Fig. 4.2, where the the solid circles and solid triangles represent the silicon devices and SiGe devices respectively. Due to the similar emitter geometry and substrate material 72 Table 4.3: Thermal resistance measurements and finite element model predictions for SiGe devices. Measured (K/mW) Model (K/mW) 1.0 fim 6.1 ± 0 . 8 5.38 1.3 /im 5.7 ± 0 . 4 4.79 2.5 ^m 4.4 ± 0 . 2 3.43 5.0 u.m 2.9 ± 0 . 1 2.24 10 u.m 1.72 ±0 .05 1.38 20 /um 1.04 ±0 .04 0.80 between the silicon and the SiGe trench-isolated devices, the only significant difference from a self-heating standpoint is the trench isolation. Clearly the effects of the trench are great, resulting in an increase in thermal resistance by a factor of more than 3 for the devices shown. The experimental results for the SiGe devices can be compared with the predictions of F E M modeling using the model shown in Fig. 2.7. The experimental and theoretical results are summarized in Table 4.3. The F E M results are also shown by the solid line in Fig. 4.2 and show good agreement with the experimental results. In light of this agreement, we conclude that the thermal model including the deep and shallow trenches and emitter metalization have correctly captured the important thermal effects in the device. The relative importance of these elements to the model are investigated through further simulations. To show the effect of emitter metalization, the dashed line shows the model prediction with the emitter 73 I • 1 2 3 4 5 6 8 10 Emitter Area (LUTI2) Figure 4.2: Thermal resistance versus emitter area for SiGe trench-isolated devices. Solid triangles, the open diamond, and the open square show results from the isothermal technique, the pulsed-VQB technique, and Ref. [4], respectively; the solid and dashed lines show F E M results with and without emitter metalization, respectively. The solid circles are thermal resistance measurements for silicon devices without trench isolation. 74 metalization removed from the model. The effect of the metalization is significant for the smaller devices but negligible for the larger devices. We have performed further calculations to show the relative importance of the deep and shallow trenches to the model. F ig . 4.3 shows the predicted thermal resistance for several trench models and compositions. A l l results are normalized to those for the full model, which includes deep and shallow trenches and accounts for the heterogeneous composition of the deep trench by an effective thermal conductivity. For reference, in F ig . 4.3 we show the full model results by the heavy solid line. We first consider the case when no trenches are included in the model; results shown by the dotted line indicate a substantial drop in thermal resistance, consistent with the measurements for the non trench-isolated silicon devices. It is interesting to examine the relative importance of the shallow and deep trenches; accordingly, the dashed line in F i g . 4.3 shows results of a model only including the deep trench. The surprising result from these data is that the shallow trench plays a significant role in increasing the thermal resistance. The dot-dashed line in F ig . 4.3 shows results of a model only including a shallow trench. The dashed and dot-dashed lines are quite close together, showing that the effect of the shallow trench is similar in magnitude to that of the deep trench. Whi le the importance of the deep trench on the thermal resistance is well known [10], the significant effect of the shallow trench is not well documented in the literature. Finally, we evaluate the magnitude of heat flow through the deep trench walls by considering the full model, but taking the deep trench to be completely insulating. These results, shown by the double-dot-dashed curve at the top of F ig . 4.3, show an over-estimation of the thermal resistance by approximately 15%. This indicates that heat conduction into the trench walls plays some role in the thermal resistance. It is interesting to examine the model of Ref. [10] in light of the results summarized in F ig . 4.3. The two 75 1.2 1.1 r 1 0 O c cd -I—> C/> C/) 0 cr 0.9 "CO £0.8 i— o0.7 N "CO ^0.6 o 0.5 0.4 1 2 3 4 5 6 8 10 Emitter Area (um2) Figure 4.3: F E M prediction of thermal resistance for various trench models and composition normalized to the full model predictions; curves are described in the text. 76 simplifying assumptions used in Ref. [10], namely the neglect of shallow trenches and the insulating nature of the deep trenches, tend to offset each other. 4.3 Weak Scaling in Small Devices An interesting feature in the thermal resistance measurements of both technologies presented so far, namely silicon bipolar and trench-isolated SiGe, is that the thermal resistance does not scale inversely proportionally with the emitter area. Examination of the experimental results shown in Figs. 4.1 and 4.2 indicate that the scaling of the thermal resistance is weaker than might be expected. A direct consequence of this fact is that given a constant power density across the emitter, small devices will operate at lower temperatures than larger emitter area devices. This is not a phenomena that is particular to silicon-based devices, the same result is found for small GaAs devices as reported by Kleckner [11], as shown in Fig. 4.4. In Fig. 4.4, square, circle, triangle and diamond markers represent square, circular, one-finger and two-finger GaAs devices respectively, as described in Section 2.1. These measurements were taken with a pulsed isothermal measurement setup similar to the one reported in this work, the main difference being a slower pulse rise time. To further investigate the weak scaling, the measurements for the large collection of GaAs devices are compared to the results of theoretical model predictions. In Figs. 4.5 and 4.6 we compare experimental results to theoretical predictions: Fig. 4.5 shows results for square and circular devices, while Fig. 4.6 shows a similar comparison for one and two-finger devices. The square, circle, triangle and diamond markers represent the square, circular, one-finger and two-finger devices respectively. In both figures, lines show results of the surface patch models, open 77 100 Emitter Area (tun ) Figure 4.4: Experimentally determined thermal resistances for GaAs devices as reported by Kleckner [11]. Square, circle, triangle and diamond symbols represent square, circular, one-finger and two-finger emitters respectively. The devices are as described in Section 2.1 78 symbols show results of the detailed model described in Section 2.2.2, and solid symbols the experimental results. Figs. 4.5 and 4.6 show that the surface patch model is a very poor predictor of measured thermal resistance; errors as great as a factor of 3 are seen for small devices. The detailed model has much better predictive accuracy, but st i l l errors are as great as a factor of 1.5 for some devices. The results of these simulations suggest that the origin of the weak scaling of thermal resistance can be attributed to either or both of the differences between the detailed thermal model for the G a A s devices and the surface patch model, namely the presence of emitter metalization and the 3-D modeling of the heat source. To quantify the effects of the emitter metal on the temperature distribution and thus thermal resistance in the devices, the de-tailed model is used to predict the maximum and minimum temperature on the base-emitter junction with and without the emitter metal present. In F ig . 4.7 (a), (b) and (c) we show the maximum and minimum temperatures versus power density for the 1.2, 4 and 8 jim2 devices, respectively. The solid and dashed lines show calculations with and without emit-ter metal, respectively. Realistic operating power densities for these devices are as high as 1 m W / / i m 2 , the maximum value shown in F ig . 4.7. There are two clear effects of the emitter metalization on the temperature distribution. The first is that the average temperature is reduced by removal of heat through the added heat flow path of the metal. This is most apparent for the 1.2 x 1.2 fj,m2 device, where both the maximum and minimum temperature lines shift to lower temperatures with the addition of emitter metal. The second effect is that the metal redistributes the heat and reduces the difference between the maximum and minimum temperatures. This is most apparent in the 8 x 8 u,m2 device, where a decrease in the maximum temperature and an increase in the minimum temperature are observed with 79 1 10 100 Emitter Area (jim2) Figure 4.5: Experimental and theoretical thermal resistance results for square and circular emitters shown by square and circle markers respectively. Solid symbols are experimental results and hollow symbols are results of detailed theoretical model for the GaAs devices simulation. Solid and dashed lines are results of the surface patch theoretical model for square and circular emitters respectively. 80 ' • • 1 10 100 Emitter Area (urn2) Figure 4.6: Experimental and theoretical thermal resistances for one- and two-finger, rect-angular emitters shown by triangle and diamond markers respectively. Solid symbols are experimental results and hollow symbols are results of detailed model for GaAs devices. Solid and dashed lines are results of the surface patch theoretical model for one- and two-finger emitters respectively. 81 310r Power Density (mW/|am2) Figure 4.7: M a x i m u m and minimum base-emitter junction temperature for 1.2 u.m (a), 4 pm (b) and 8 jtim (c) square emitter G a A s devices. Solid and dashed lines are for models with and without metal respectively. 82 the addition of metal. The increased minimum temperature is a clear indication that the metal is redistributing the heat. The increase in temperature uniformity does not greatly affect the thermal resistance, as the average temperature is not changed significantly. This is, however, an interesting effect and wi l l be discussed in greater detail in the following sec-tion. The temperature reduction effect which is most apparent in the small devices reduces the thermal resistance accordingly and contributes to the weak scaling. This effect is, how-ever, only a minor contribution to the weak scaling, on the order of 10 or 15%, and does not fully explain the 300% difference between the surface patch and detailed models. We therefore conclude that the principal origin of the weak scaling is the 3-D nature of the heat source. This conclusion becomes quite clear by examining the shape of the heat generating B C S C R regions of the small and large devices. F ig . 4.8 shows the shape of the B C S C R for 1.2xl .2/^m 2 and 8x8/um 2 devices, respectively. It is clear that for larger devices, the B C S C R looks much like a 2-D plane and is therefore better modeled by the surface patch model. For the smaller devices, the thickness of the B C S C R does not scale, the shape approaches that of a cube and therefore the 3-D nature becomes important. A quantitative measure of this can be obtained by comparing the area of the emitter to the area of the side walls of the B C S C R . In the case of the 8 x 8 / i m 2 device, the sidewall area is 17% of the emitter area whereas for the 1 .2x l . 2 / im 2 device, the sidewall area is 117% of the emitter area. Li t t le attention has been paid to the importance of the 3-D heat flow in the thermal resistance, despite the existence of an analytical thermal model including 3-D heat flow [1]. This can be attributed to the relatively few studies of thermal resistance in small devices and the success of the surface patch model to model the large power devices studied in the past. The 3-D heat flow effect now deserves attention since it is very relevant to modern submicron devices, 83 Figure 4.8: Comparison of the shape of the BCSCRs of a large and small GaAs device. The top and bottom panels show the B C S C R of 1.2x1.2/tm2 and 8x8/ im 2 devices respectively, and are drawn with different scales. 84 where the lateral emitter dimensions are being scaled aggressively while the thickness of the B C S C R may only be scaled by a limited amount due to breakdown voltage limitations. 4.4 The role of metalization in temperature uniformity As noted in the previous section, Fig. 4.7 shows that the presence of emitter metalization increases temperature uniformity across the emitter. These effects of metal on the tempera-ture uniformity are more apparent in Fig. 4.9, which shows contour plots of the temperature distribution for the 8 x 8 /jm 2 device. Figs. 4.9 (a) and (b) show results including metal, while Figs. 4.9 (c) and (d) neglect the metal contribution. The power densities are low (0.34mW//im 2) for Figs. 4.9 (a) and (c), and high (1 mW/u.m2) for Figs. 4.9 (b) and (d). As in Fig. 4.7, Fig. 4.9 shows a significant difference in peak temperatures between models with and without emitter metalization. Additionally, Fig. 4.9 confirms that the tempera-ture uniformity is much greater in the more realistic models including emitter metalization. The increased temperature uniformity by emitter metalization is significant for at least two reasons. First, it strengthens the assumption that a single temperature can characterize a device, which is inherent in the use of a single thermal resistance. Second, it suggests it may be possible to optimize this effect through improved metalization processing to further improve the performance of future devices. In actual devices, current uniformity may be further increased by current crowding in the device, which would tend to focus more power dissipation towards the outer edges of the emitter. To investigate this, we put together a full iterative electrothermal simulation to account for electrical current crowding due to a a non-zero base resistance and current 85 (c) (d) Figure 4.9: Temperature contours in 2 K increments on base-emitter junction of 8 x 8 /mi 2 device, (a) and (b) show results including metal, while (c) and (d) neglect the metal contri-bution. The power densities are low for (a) and (c), and high for (b) and (d). 86 concentration due to a thermal hot-spot. The model self-consistently solves for the power dissipation and temperature as a function of position across the emitter. Effects of the base resistance are accounted for by performing a 2-D finite element calculation of the base voltage for a base current uniformly entering the base from all sides. This calculation is performed with the same finite element tools used for the thermal problem, using an electrical analogy to the heat-flow equation. The temperature dependence of the electrical conductivity of the base is accounted for by computing the hole mobility at the appropriate temperature as a function of position in the base. Voltage drops in the base are used to scale the power dissipation using an appropriate exponential scaling factor of The effects of temperature on the power density are accounted for using an equivalent effect on the base-emitter voltage. Assuming a linear relation between base-emitter voltage and temperature with a slope of -1.5 m V / K , a value consistent with those reported for GaAs H B T devices, the power density is scaled by the factor Results of the electrothermal calculation indicate that the thermal current concentration dominates over any electrical current crowding for the well-designed HBTs used in this study. It is interesting to note, however, that the results of this model suggest that it is possible to engineer the distribution of power across the emitter by adjusting the relative amounts of electrical and thermal current crowding through adjustment of the emitter geometry. Thus far the increased temperature uniformity has only been demonstrated for a single device of a specific process. To investigate the universality of this effect, further theoretical (4.3) 1.5AT e *>T (4.4) 87 calculations were done for the 3x3 /um2 Nortel device fabricated from a different process. As described in Section 2.1, the Nortel process uses a different metalization near the device consisting of a thin emitter Ohmic, an emitter via and an interconnect strap. The thermal model used for the 3x3 /um2 device is as described in Section 2.2.3. Temperature contours across the emitter are shown in Fig. 4.10 where panel (a) includes emitter metalization and panel (b) excludes emitter metalization. As with the 8x8/um2 device, a significant increase in temperature uniformity is observed for the 3 x 3/um2 device with the presence of emitter metalization. This results suggests that this effect is not limited to a specific process and style of emitter metalization, nor to large devices. In the preceding discussions much attention has been paid to the effects of the emitter metalization on heat flow, with no mention of the base and collector metalizations. This is justified by a simple geometric argument that the emitter metalization is in much closer proximity to the B C S C R and therefore in much better thermal contact to the heat producing region. To confirm this assumption, a detailed model including the base metalization of the 3x3/um2 Nortel device as described in Section 2.2.3 is solved. Results of these simulations confirm that the base metalization has a negligible effect on both average temperature and temperature uniformity. A similar result is expected for collector metalization. 88 (b) Figure 4.10: Temperature at base-emitter junction of 3x3/um 2 G a A s device, as predicted by F E M simulation, (a) without the effects of the emitter metal, (b) including emitter metal; in both plots the contour interval is 1 K 89 Chapter 5 Conclusions In the course of this work, a substantially improved thermal resistance measurement tech-nique has been developed based on a pulsed-bias isothermal device characterization. The resulting setup is both simple to use and based on reasonably inexpensive equipment, a combination that has not been achieved in previous pulsed-bias designs. In comparison to DC measurement techniques, the present technique offers a measurement that requires a similar user effort and measurement time. Therefore the present technique offers a suit-able replacement for DC measurement of thermal resistance, which is mainly used for their convenience. As a complementary tool to the measurement setup, an analysis tool technique has been developed which uses the finite element method to numerically solve realistic 3-D geometric thermal models for bipolar transistors. This tool, based on leading mesh generation and finite element algorithms, has been shown to be capable of solving a variety of thermal models specific to bipolar transistors, and is among the most advanced presently used in the field. We have shown that this tool is useful for at least four purposes. First, it may 90 be used to validate experimental measurements. Second, it may be used to predict thermal resistances in the absence of experimental data. Third, it may be used as a means to easily investigate the relative importance of different physical elements in thermal models. Finally, it may be used to investigate interesting new devices designs and processes. Measurements of the thermal resistance for a large number of silicon bipolar devices of two emitter widths have been found to be in good agreement with a numerical 3-D thermal model. Based on these results, we have found that thermal resistance is significantly reduced for devices with higher aspect ratio emitters, given a constant emitter area. Despite the difference in magnitude, the thermal resistance is found to scale similarly with area for the different emitter widths. The thermal resistance scaling can be expressed conveniently as a simple power law relation which is capable of predicting thermal resistance of arbitrary emitter areas. Simulation results show that the thermal resistance is largely determined by the die conductivity, emitter geometry and base-collector space charge region thickness and therefore the scaling laws obtained here should be applicable to a large variety of silicon based devices. We have measured and modeled thermal resistance in single-emitter Si/SiGe trench-isolated heterojunction bipolar transistors. Theoretical predictions are in good agreement with the measurements provided that emitter metalization, deep trenches and shallow trenches are included in the model. Theoretical investigations indicate that shallow and deep trenches play comparable roles in significantly restricting heat flow and raising thermal resistance compared with junction or implant-isolated silicon devices. Measured results show that the thermal resistance is increased by more than a factor of three with the addition of the trench-isolation. Additionally, theoretical investigations show that some heat flows through 91 the deep trench walls, suggesting further reduction in the oxide thickness could reduce ther-mal resistance. A weak scaling with area has been observed in measured and theoretical thermal resis-tances for silicon bipolar and SiGe HBTs. This scaling is also observed in a theoretical study of the thermal resistance in a large collection of GaAs HBTs has and is consistent with mea-surements of a previous study. The origin of the weak scaling is due to the three-dimensional nature of the heat flow around the heat-generating base-collector space-charge region in small devices compared to the largely two-dimensional heat flow in larger devices. These results suggest the possibility of reducing the thermal resistance of large power devices by breaking them into two-dimensional arrays of smaller devices of an equivalent total emitter area. Theoretical studies of self-heating in GaAs H B T devices have shown that the presence of emitter metalization substantially increases temperature uniformity across the emitter. This effect has been shown to be significant in devices of varying emitter area and for two processes with very different metalization geometries. We conclude that this effect is relevant to many existing devices and processes, and suggest the possibility that it may be enhanced through improved processing. The results of this work lead to a variety of possibilities for future work. Improved power bipolar devices could be studied by breaking large devices into grids of varying numbers of transistors and optimizing the spacing between them. Reduced thermal resistance in trench-isolated devices may be investigated through a study of the impact on thermal resistance of the oxide wall thickness and and clearance to the emitter of deep trenches. Further improvements in the speed of the bias-pulse in the isothermal measurement setup will be required in order to apply the technique to future deep-submicron devices. Coupling of 92 the theoretical thermal model to electrical models would provide an extremely powerful simulation tool capable of modeling electrothermal feedback effects and more accurately accounting for the spatial dependence of power dissipation. 93 Bibliography [1] Richard C. Joy and E. S. Schlig, "Thermal Properties of Very Fast Transistors," IEEE Trans. Electron Devices, vol. 17, pp. 586-594, Aug. 1970. [2] O. Muller, "Internal Thermal Effect in Transistors and their Thermal Equivalent Cir-cuit," NTZ journal, vol. 3, pp. 116-123, 1963. [3] G. Hanington, C. E. Chang, P. J. Zampardi, and P. M . Asbeck, "Thermal effects in H B T emitter resistance extraction," Electronics Letters, vol. 32, pp. 1515-1516, Aug. 1996. [4] H. Tran, M . Schroter, D. J. Walkey, D. Marchesan, and T. J. Smy, Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting, IEEE, Piscataway, NJ , 1997. [5] Michael Reisch, "Self-heating in B J T Circuit Parameter Extraction," Solid-State Elec-tron., vol. 35, pp. 677-679, May 1992. [6] Keh-Chung Wang, Peter M . Asbeck, Mau-Chung F. Chang, D. L. Miller, Gerard J. Sullivan, Jon J. Corcoran, and Thomas Hornak, "Heating Effects on the Accuracy of H B T Voltage Comparators," IEEE Trans. Electron Devices, vol. 34, pp. 1729-1735, Aug. 1987. 94 [7] Ken Poulton, Knud L. Knudsen, John J. Corcoran, et al., "Thermal simulation and design of a gaas hbt sample and hold circuits," GaAs IC Symposium, pp. 129-132, 1991. [8] J. P. Bailbe, L. Andrieux, A . Cazarre, T. Camps, A . Marty, J. Tasselli, and H. Granier, "Theory and Experiment of the Temperature Dependence of GaAlAs/GaAs HBTs Char-acteristics for Power Amplifier Applications," Solid-State Electron., vol. 38, pp. 279-286, Feb. 1995. [9] V . Szekely, "A new evaluation methodd of thermal transient measurement results," Microw. J, vol. 28, pp. 277-292, 1997. [10] D. J . Walkey, Proceedings of the 1996 Bipolar/BiCMOS Circuits and Technology Meet-ing, IEEE, Piscataway, NJ , 1999. [11] T. C. Kleckner, "Self-Heating and Isothermal Characterization of Heterojunction Bipo-lar Transistors," M.S. thesis, University of British Columbia, 1998. [12] J. Aiden Higgins, "Thermal Properties of Power HBT's," IEEE Trans. Electron Devices, vol. 40, pp. 2171-2177, Dec. 1993. [13] Michael G. Adlerstein and Mark P. Zaitlin, "Thermal Resistance Measurements for A l -GaAs/GaAs Heterojunction Bipolar Power Transistors," IEEE Trans. Electron Devices, vol. 38, pp. 1553-1554, June 1991. [14] Lee L. Liou, John L. Ebel, and Chern I. Huang, "Thermal Effects on the Charac-teristics of AlGaAs/GaAs Heterojunction Bipolar Transistors Using Two-Dimensional Numerical Simulation," IEEE Trans. Electron Devices, vol. 40, pp. 35-43, Jan. 1993. 95 [15] Francesc N . Masana, "A closed Form Solution of Junction to Substrate Thermal Resis-tance in Semiconductor Chips," IEEE Trans, on Components, Packaging, and Manu-facturing Technology-Part A, vol. 19, pp. 539-545, Dec. 1993. [16] Kevin J. Negus, Robert W. Franklin, and M . M . Yovanovich, "Thermal Modeling and Experimental Techniques for Microwave Bipolar Devices," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 12, pp. 680-689, Dec. 1989. [17] Frank F. Oettinger, David L. Blackburn, and Sherwin Rubin, "Thermal Characteriza-tion of Power Transistors," IEEE Trans. Electron Devices, vol. 23, pp. 831-838, Aug. 1976. [18] Steve P. Marsh, "Direct Extraction Technique to Derive the Junction Temperature of HBT's Under High Self-Heating Bias Conditions," IEEE Trans. Electron Devices, vol. 47, pp. 288-291, Feb. 2000. [19] Dale E. Dawson, Aditya K . Gupta, and Mike L. Salib, "CW Measurement of H B T Thermal Resistance," IEEE Trans. Electron Devices, vol. 39, pp. 2235-2239, Oct. 1992. [20] N . Bovolon, P. Baureis, J.-E. Muller, P. Zwicknagl, R. Schultheis, and E. Zanoni, "A Simple Method for the Thermal Resistance Measurement of AlGaAs/GaAs Heterojunc-tion Bipolar Transistors," IEEE Trans. Electron Devices, vol. 45, pp. 1846-1848, Aug. 1998. [21] Bob Schaefer and Mark Dunn, Proceedings of the 1996 Bipolar/BiCMOS Circuits and Technology Meeting, IEEE, Piscataway, NJ , 1996. 96 [22] Scott A . Wartenberg and Charles R. Westgate, "Modeling of the Temperature-Dependent Early Voltage of a Silicon Germanium Heterojunction Bipolar Transistor," IEEE Trans. Electron Devices, vol. 46, pp. 1207-1211, June 1999. [23] K. A. Jenkins and J. Y . - C . Sun, "Measurement of I-V Curves of Silicon-on-Insulator (SOI) MOSFET's Without Self-Heating," Electron Dev. Lett, vol. 16, pp. 145-147, Apr. 1995. [24] P. M . Mcintosh and C. M . Snowden, "Measurement of heterojunction bipolar transistor thermal resistance based on a pulsed i-v system," Electronics Letters, vol. 33, no. 1, pp. 100-101, 1997. [25] Bob Schaefer and Mark Dunn, "Pulsed Measurements and Modeling for Electro-Thermal Effects," Proceedings of the 1996 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 110-117, 1996. [26] P. R. Ganci, J-J. J. Hajjar amd T. Clark, P. Humphries, J. Lapham, and D. Buss, "Self-Heating in High Performance Bipolar Transistors Fabricated on SOI Substrates," IEEE Electron Device Meeting, pp. 15.7.1-15.7.4, 1992. [27] Burhan Bayraktaroglu, Fazal A l i , John Mason, and Paul Smith, "Flip-chip x-band operation of thermally-shunted microwave hbt's with sub-micron emitters," 1996 IEEE MTT-S International Microwave Symposium Digest, pp. 685-688, 1996. [28] T. Lester, R. K . Surridge, S. Eicher, J. Hu, G. Este, H. Nentwich, B. MacLaurin, D. Kelly, and I. Jones, Gallium Arsenide and Related Compounds 1993: Proceedings 97 of the 20th International Symposium, Institute of Physics Conference Series 136. IOP, B r i s t o l 1993. [29] D. L . Harame, J . H . Comfort, J . i D . i Cressler andi E . F . Crabbe, J . Y . - C . Sun, B . S. Meyerson, and T . Tice, "S i /S iGe Epitaxial-Base Transistors-Part LMater ia ls , Physics, and Circuits ," IEEE Transactions on Electron Devices, vol. 42, pp. 455-468, Mar . 1995. [30] D . L . Harame, J . H . Comfort, J . D . Cressler, E . F . Crabbe, J . Y . - C . Sun, B . S. Meyer-son, and T . Tice, "S i /S iGe Epitaxial-Base Transistors-Part ILProcess Integration and Analog Applications," IEEE Transactions on Electron Devices, vol. 42, pp. 469-482, Mar. 1995. [31] R. W . Lewis and Roland Wynne, The Finite Element Method in Heat Transfer Analysis, Wiley, Chichester, New York, 1996. [32] O. C. Zienkiewicz, The Finite Element Method, M c G r a w - H i l l , London, New York, 1989. [33] S. Mitchel l and S. Vavasis, "Quality Mesh Generation in Higher Dimensions," SIAM Journal on Computing, in press. [34] S. Vavasis, "Qmg 2.0," www.es.Cornell.edu/home/vavasis/qmg2.0/qmg2_0_home.html. [35] R. Beck, "Kaskade 3.2," www.zib.de/SciSoft/kaskade. 98 Appendix A Pulse Circuitry V B E 49.9 49.9 T R I G B F R 9 2 A B F R 9 2 A 49.9 =F 0.1u 1k B F R 9 2 A . 0.1u 100 B F R 9 2 A 4 9 . 9 ? 0 _ 1 u ^ . ? 4 9 . 9 6 V E E O -6V 510 ? ? 510 V E E O -r- 0.1 u V C C O 6V Q AD8009 6 V E E O 301 10 DUT base - 0 49.9 =P 47p V C C O <? > v J \ D 8 0 0 9 49.9 6 V E E O 301 CH1 Scope 301 Figure A . l : Schematic of base pulse circuitry. 99 Figure A.2: Top layer of printed circuit board layout for base pulse circuit. c n o o o Cl Cl 6 o "O o o 6. o Zol o "o" ° o o o ° (_l (_ Figure A.3: Bottom layer of printed circuit board layout for base pulse circuit. 100 49.9 -Q CH2 Scope V C E o -402 V E E O CLC449 -o VCCO 402 3 249 VCCO P 27 J AD8009 Rm = 10 or 100 V E E O 301 DUT collector - 0 49.9 - i - 47p Figure A.4: Schematic of collector current monitoring circuitry. Figure A.5: Top layer of printed circuit board layout for collector current monitoring circuit. 101 Figure A.6: Bottom layer of printed circuit board layout for collector current monitoring circuit. 102
- Library Home /
- Search Collections /
- Open Collections /
- Browse Collections /
- UBC Theses and Dissertations /
- Determination of self-heating in bipolar and heterojunction...
Open Collections
UBC Theses and Dissertations
Featured Collection
UBC Theses and Dissertations
Determination of self-heating in bipolar and heterojunction bipolar transistors by measurement and simulation Reid, Adam Robert 2000
pdf
Page Metadata
Item Metadata
Title | Determination of self-heating in bipolar and heterojunction bipolar transistors by measurement and simulation |
Creator |
Reid, Adam Robert |
Date Issued | 2000 |
Description | Self-heating in bipolar transistors, the effect which causes a rise in the device junction temperature due to the electrical power dissipation, is of interest for several reasons, including device reliability, model parameter extraction and electrothermal modeling. Self-heating is most commonly quantified by a thermal resistance, which relates the device steady-state temperature and power dissipation. In this work we present an improved setup for measuring thermal resistance, based on an isothermal characterization of the device by means of a pulsed-bias experiment. A 30 times increase in bias-pulse speed, compared to previous setups, allows for the first time, accurate measurements to be made on devices with submicron emitter dimensions. Simultaneous to increased performance, we have achieved a significant reduction in the complexity of the setup through the elimination of specialized sample preparation, enabling measurements with conventional microwave on-wafer probes. To facilitate comparison with experimental measurements, an analysis tool based on the finite element method has been developed to solve detailed 3-D thermal models of bipolar transistors, including emitter metalization and trench-isolation effects. Thermal resistance measurements have been made on a collection of 9 single emitter silicon bipolar and 6 trench-isolated SiGe heterojunction bipolar transistors and compared to results from theoretical models. In addition, a collection of 15 GaAs heterojunction bipolar transistors have been studied theoretically and compared to measurements from a previous study. Results for silicon bipolar devices show that significant reductions in thermal resistance are achieved by using high aspect ratio emitter geometries. Comparison of results for silicon bipolar devices with trench-isolated SiGe devices of a similar emitter geometry show a threefold increase in thermal resistance due to the presence of trench isolation. This increase in thermal resistance is found to be attributable in roughly equal parts to the two isolation components, namely the deep and shallow trenches. The thermal resistance is found to scale weakly with emitter area for the small devices studied here, an effect which is most apparent in the GaAs devices. The origin of this effect is found to be the 3-D nature of the heat flow in the smallest devices. Emitter metalization is found to play a role in reducing the thermal resistance for high thermal resistance devices. Additionally, the emitter metalization is found to significantly increase the uniformity of the temperature across the emitter. |
Extent | 5084406 bytes |
Genre |
Thesis/Dissertation |
Type |
Text |
FileFormat | application/pdf |
Language | eng |
Date Available | 2009-07-13 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0065349 |
URI | http://hdl.handle.net/2429/10760 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
GraduationDate | 2000-11 |
Campus |
UBCV |
Scholarly Level | Graduate |
AggregatedSourceRepository | DSpace |
Download
- Media
- 831-ubc_2000-0545.pdf [ 4.85MB ]
- Metadata
- JSON: 831-1.0065349.json
- JSON-LD: 831-1.0065349-ld.json
- RDF/XML (Pretty): 831-1.0065349-rdf.xml
- RDF/JSON: 831-1.0065349-rdf.json
- Turtle: 831-1.0065349-turtle.txt
- N-Triples: 831-1.0065349-rdf-ntriples.txt
- Original Record: 831-1.0065349-source.json
- Full Text
- 831-1.0065349-fulltext.txt
- Citation
- 831-1.0065349.ris
Full Text
Cite
Citation Scheme:
Usage Statistics
Share
Embed
Customize your widget with the following options, then copy and paste the code below into the HTML
of your page to embed this item in your website.
<div id="ubcOpenCollectionsWidgetDisplay">
<script id="ubcOpenCollectionsWidget"
src="{[{embed.src}]}"
data-item="{[{embed.item}]}"
data-collection="{[{embed.collection}]}"
data-metadata="{[{embed.showMetadata}]}"
data-width="{[{embed.width}]}"
async >
</script>
</div>
Our image viewer uses the IIIF 2.0 standard.
To load this item in other compatible viewers, use this url:
http://iiif.library.ubc.ca/presentation/dsp.831.1-0065349/manifest