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Power supply for an electric resistance melting furnace Alimadadi, Mehdi 2000

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P O W E R SUPPLY F O R A N E L E C T R I C RESISTANCE M E L T I N G F U R N A C E by M E H D I A L I M A D A D I B.Sc, University of Science and Technology of Iran, Tehran, Iran, 1989 A THESIS SUBMITTED IN P A R T I A L F U L F I L L M E N T O F T H E R E Q U I R E M E N T S F O R T H E D E G R E E O F M A S T E R O F SCIENCE in T H E F A C U L T Y O F G R A D U A T E STUDIES (Department of Electrical Engineering) We accept this thesis as conforming to the required standard T H E UNIVERSITY O F BRITISH C O L U M B I A July 2000 ® Mehdi Alimadadi, 2000 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department o, g ^ C T n C A L g A K U V g g W g . The University of British Columbia Vancouver, Canada Date DE-6 (2/88) ABSTRACT In recent years, the field of power electronics has experienced a large growth due to the confluence of several factors. Revolutionary advances in microelectronics methods have led to the development of controllers that include linear ICs and DSPs. Moreover, advances in semiconductor fabrication technology have made it possible to significantly improve the voltage/current handling capabilities and the switching speeds of power switches. This work is intended as a pilot 400kW unit for testing in the Advanced Material and Process Engineering Laboratory (AMPEL) building. The eventual goal of this project is to produce a full size commercial unit at 2.4MW. The conventional supply for an electric resistance-melting furnace consists of a single-phase low voltage source obtained from a 60Hz transformer. This high power single-phase load is becoming increasingly unacceptable to customers and a method of transforming the load into an effective balanced three-phase equivalent is sought. In single-phase sinusoidal loads the instantaneous power pulsates at twice the source frequency but the total instantaneous power drawn by a balanced three-phase load is constant. This implies that a substantial energy requirement must be present in any converter between the two systems or an unbalanced load to the three-phase source will be presented. Among the possible solutions, an A C / D C / A C conversion was chosen. A thyristor bridge rectifier is used as the AC/DC converter and a voltage source inverter is used as the DC/AC converter. Several previous papers have been reviewed to have a better idea on designing the DC-bus filter, the effect of non-sinusoidal voltage/current on the transformers, etc. Practical considerations were one the most important factors in the design and choosing of the elements. ii TABLE OF CONTENTS ABSTRACT ii TABLE OF CONTENTS iii LIST OF TABLES v LIST OF FIGURES vi ABBREVIATIONS ix ACKNOWLEDGEMENTS xi CHAPTER 1 INTRODUCTION 1 CHAPTER 2 CONCEPTIONAL OVERVIEW 4 2.1. Introduction 4 2.2. Filters 4 2.3. Transformers And Inductors 10 2.4. Power Switches 20 2.5. Static Frequency Converters 29 2.6. Control Schemes 33 CHAPTER 3 THE OLD SYSTEM 36 3.1. Introduction 36 3.2. The Transformer 36 3.3. Conductors and the Furnace 37 3.4. Conclusions 37 CHAPTER 4 THE NEW SYSTEM 38 4.1. Introduction 38 4.2. AC/DC Conversion 43 4.3. DC/AC Conversion 49 4.4. Power Components List 58 4.5. PSIM Simulation 59 4.6. Protections 68 4.7. Communications 69 4.8. Cooling 69 4.9. Microprocessor Boards 65 4.10. Controller Schemes 72 4.11. Monitoring 79 4.12. Current Sensors 85 4.13. RMS-to-DC Converter 85 4.14. The Control circuit 87 iii 4.15. Mechanical Designs 91 4.16. Conclusions 91 C H A P T E R 5 P R A C T I C A L E X P E R I M E N T S AND RESULTS 92 5.1. Introduction 92 5.2. Half-Load 93 5.3. Full-Load 93 5.4. Current mode 96 5.5. Sudden Changes in The Load 99 5.6. Conclusion 99 C H A P T E R 6 O V E R A L L CONCLUSIONS AND F U T U R E POSSD3BLITTES 102 6.1. Overall Conclusion 102 6.2. Future Possibilities 103 R E F E R E N C E S 104 APPENDIX A TESTS D O N E O N T H E EXISTING T R A N S F O R M E R 108 APPENDIX B E V A L U T I O N B O A R D S O F T W A R E A N D P O W E R UP 110 B . l . IRISM-IECM Software 110 B.2. Powering Up And Connecting To The PC 110 B. 3. Program Execution 111 APPENDIX C A S S E M B L Y CODES F O R T H E C O N T R O L L E R 112 C. l . The 80C196KB.INC File 112 C.2. The Interrupt Vectors Code Segment (CSEG) 113 C.3. The Complete Code 113 APPENDIX D C++CODE F O R DAQ-801 121 APPENDIX E M E C H A N I C A L DRAWINGS 124 iv LIST OF TABLES T A B L E 2.1. Waveform characteristic 18 T A B L E 2.2. Typical gate drive characteristics 25 T A B L E 2.3. Loss characteristics 26 T A B L E 2.4. Comparison of current source inverters and voltage source inverters 32 T A B L E 3.1. Summarized short circuit test results 37 T A B L E 4.1. The new power supply specifications 38 T A B L E 4.2. Component specifications as was used for the PSIM simulation 58 T A B L E 4.3. Losses in the system 69 T A B L E 4.4. Determining change of switching_on_time 74 T A B L E 4.5. Controller board IP 1 pin connections 79 T A B L E 4.6. Controller board JP2 pin connections 79 T A B L E 4.7. Monitor board D-68 pin connections 82 T A B L E A. 1. Old transformer output voltages 108 V LIST OF FIGURES FIGURE 1.1. Block diagram of a power electronic system FIGURE 1.2. A typical furnace schematic diagram FIGURE 2.1. The second order parallel LCR resonator FIGURE 2.2. Shunt filters FIGURE 2.3. Equivalent circuits for two winding transformers 1 FIGURE 2.4. Three-winding transformer 12 FIGURE 2.5. Normalized loss characteristic 19 FIGURE 2.6. Voltage Source Inverter Phase Leg Comparison 23 FIGURE 2.7. HVIGBT and GCT gate drive current 24 FIGURE 2.8. Proposed application range of HVIGBT and GCT 27 FIGURE 2.9. Common IGBT snubber circuits 28 FIGURE 2.10. Three-phase converter with Ls and a constant dc current 30 FIGURE 2.11. Commutation in the presence of L s 30 FIGURE 2.12. Line current in the presence of Ls 30 FIGURE 2.13. Main current control schemes 33 FIGURE 2.14. PWM duty ratio versus current-mode control 35 FIGURE 4.1. Simplified models used for PSIM 39 FIGURE 4.2. Power circuit diagram 40 FIGURE 4.3. Typical gating waveforms for the IGBTs 41 FIGURE 4.4. Typical voltage waveforms across the IGBTs 41 FIGURE 4.5. Typical current waveforms for the IGBTs and FWDs 42 FIGURE 4.6. Possible positions for semiconductor fuses in bridge converters 45 FIGURE 4.7. Tuned high pass filter 5 FIGURE 4.8. Low pass filter 5 FIGURE 4.9. Simulation results for the load current and the inverter output voltage waveforms at a fraction of full load. FIGURE 4.10. Simulation results for the DC-bus voltage after the filter and before the filter waveforms at a fraction of full load. FIGURE 4.11. Simulation results for the filter capacitor current and the input current waveforms at a fraction of full load. FIGURE 4.12. Simulation results for the IGBT/diode (in the same module) current waveforms at a fraction of full load. FIGURE 4.13. Simulation results for the load current and the inverter output voltage waveforms at full load. FIGURE 4.14. Simulation results for the DC-bus voltage after the filter and before the filter waveforms at full load. FIGURE 4.15. Simulation results for the filter capacitor current and the input current waveforms at full load. FIGURE 4.16. Simulation results for the IGBT/diode (in the same module) current waveforms at full load. vi FIGURE 4.17. Simulation results for the DC-bus voltage after the filter and before the filter waveforms with short circuit at the load 64 FIGURE 4.18. Simulation results for the short circuit current and the input current waveforms with short circuit at the load 64 FIGURE 4.19. Simulation results for the DC-bus voltage after the filter and before the filter waveforms with short circuit after the 1-ph transformer 65 FIGURE 4.20. Simulation results for the short circuit current and the input current waveforms with short circuit after the 1-ph transformer 65 FIGURE 4.21. Simulation results for the DC-bus voltage after the filter and before the filter waveforms with short circuit with short circuit before the 1-ph transformer 66 FIGURE 4.22. Simulation results for the short circuit current and the input current waveforms with short circuit before the 1-ph transformer 66 FIGURE 4.23. Simulation results for the DC-bus voltage after the filter and before the filter waveforms with the open circuit after the 1-ph transformer 67 FIGURE 4.24. Simulation results for the short circuit current and the input current waveforms with the open circuit after the 1-ph transformer 67 FIGURE 4.25. Current mode control with two control loops 73 FIGURE 4.26. General flowchart for the code 74 FIGURE 4.27. Subroutine flowchart for ad_done_ISR 74 FIGURE 4.28. Subroutine flowchart for external_int 74 FIGURE 4.29. Subroutine flowchart for hso_subroutine 75 FIGURE 4.30. Subroutine flowchart for io_subroutine 75 FIGURE 4.31. Subroutine flowchart for sw_on_subroutine 76 FIGURE 4.32. Subroutine flowchart for soft_timer_ISR 77 FIGURE 4.33. LabVIEW front panel 83 FIGURE 4.34. LabVIEW block diagram 83 FIGURE 4.35. Typical AD636 output waveform for sinusoidal input 86 FIGURE 4.36. RMS-to-DC converter shown with optional components and double voltage supply 87 FIGURE 4.37. Control circuit block diagram 88 FIGURE 4.38. Circuit diagram of the control circuit (analog) 89 FIGURE 4.39. Circuit diagram of the control circuit (digital) 90 FIGURE 5.1. Inverter output current at half load 94 FIGURE 5.2. Inverter output voltage at half load 94 FIGURE 5.3. Inverter output current at full load 95 FIGURE 5.4. Inverter output voltage at full load 95 FIGURE 5.5. Inverter output current with shorted resistance at nominal full load 97 FIGURE 5.6. Inverter output voltage with shorted resistance at nominal full load 97 FIGURE 5.7. Inverter output current with shorted resistance at above nominal full load 98 FIGURE 5.8. Inverter output voltage with shorted resistance at above nominal full load 98 FIGURE 5.9. Inverter output current with increased DC-bus voltage at above nominal full load 100 FIGURE 5.10. Inverter output voltage with increased DC-bus voltage at above nominal full load 100 FIGURE 5.11. Changes in actual current when load resistance is shorted at full load 101 FIGURE 5.12. Changes in actual current when load resistance is backed at full load 101 vii FIGURE A . l . Trans, characteristics at different output voltages 109 FIGURE A.2. Secondary circuit dimensions 109 FIGURE F. 1. DWG-100-9 general cubicle layout 125 FIGURE F.2. DWG-600-5 laminated busbar layout 126 FIGURE F.3. DWG-300-0 cold plate layout 127 viii ABBREVIATIONS a Delay angle P Conductor resistivity APLC Active Power Line Conditioning A Maximum flux density BJT Bipolar Junction Transistors Cbase Base value of the snubber capacitance C R Rated capacitance Cs Snubber capacitor CSI Current Source Inverter d Insulation thickness D A Q Data AcQuisition DSP Digital Signal Processor E C M Embedded Controller Monitor Fsw Switching frequency Esw-off Turn off energy per pulse Esw-on Turn on energy per pulse G C T Gate Commutated turn-off Thyristor G P M Gallon Per Minute G T O Gate Turn Off thyristors Ic Continuous collector current IC Integrated Circuit IDRM Maximum repetitive off state current IG Gate current IGT Gate trigger current h Peak inductor current IRRM Maximum repetitive reverse current IT On state current IT(AV) Average on state current IGBT Insulated Gate Bipolar Transistor K Dielectric constant LESL Equivalent series inductance LabVIEW Laboratory Virtual Instrument Engineering Workbench M Mutual inductance MOSFET Metal Oxide Semiconductor Field Effect Transistor N Number of layers N Ratio of transformation (N=n2/ni) ix Pd Dissipated power PdQ Dissipated power for the IGBT element of the switch PdR Dissipated power for the diode element of the switch POSL Stray loss in components other than the windings PEC Winding eddy current loss PLL Total load loss PC Personal computer PCC Point of Common Coupling PSIM Power SIMulation software Q Quality factor RDS(on) On state drain-source resistance RESR Equivalent series resistance rF Slope resistance Ri Leakage resistance Ropt Optimal value of the snubber resistor Rs Snubber resistor IT Slope resistance RSSA Thermal resistance between cold plate and ambient Recs Thermal resistance between the switch casing and cold plate Rejc Thermal resistance between the junction and the casing of switch RISM Reduced Instruction Set Monitor S/s Samples per second SCR Silicon-Controlled Rectifiers t Conductor thickness T a Ambient temperature Tj Junction temperature trr Diode reverse recovery time U Commutation interval U P K V A Of the P winding U S K V A of the S winding U T K V A of the T winding VcES Collector-emitter blocking voltage VcE(sat) Collector-emitter saturation voltage VDRM Maximum repetitive off state voltage V F O Threshold voltage V F M Diode forward voltage VRRM Maximum repetitive reverse voltage V T O Threshold voltage V J M Maximum on state voltage drop VI Virtual Instruments VSI Voltage Source Inverter w Energy Xc A C side reactance X ACKNOWLEDGEMENTS First and foremost, I wish to express my appreciation to Dr. W. G. Dunford for being my thesis supervisor and for his guidance during the project. I thank Dr. R. W. Donaldson for being the chair of my final exam committee and also Dr. J. R. Marti for being the co-reader in my final exam committee. I feel thankful to all these people for serving on my advising committee, and for offering their helpful suggestions. I appreciate the support of all the faculty and staff members of the Department of Electrical Engineering. I should mention Bruce Dow for his assistance with office/laboratory procedures. I am grateful to The University of British Columbia for awarding me a Graduate Student Bursary, the Faculty of Electrical Engineering for awarding me a four-term Teaching Assistantship and for awarding me the Graduate Research Assistantship for more than one year of my study. The encouragement and prayers of my dear parents has surely had an essential role in the accomplishment of this work. At last, it would be almost impossible to complete this work without understanding and support of my dear wife, Afsaneh, whose patience is greatly admired. xi CHAPTER 1 INTRODUCTION In recent years, the field of power electronics has experienced a large growth due to the confluence of several factors. Revolutionary advances in microelectronics methods have led to the development of powerful controllers. Moreover, advances in semiconductor fabrication technology have made it possible to significantly improve the voltage- and current-handling capabilities and the switching speeds of power semiconductor devices, which make up the power processor unit of Figure 1.1. The controller in the block diagram of Figure 1.1. consists of linear integrated circuits and/or digital signal processors [1]. FIGURE 1.1. Block diagram of a power electronic system Power input : Power processor : Power output /""""^x H '01 Is Measurements ;nce i k Cont signc Controller •<— Refer* In a conventional electric resistance-melting furnace the power supply for the furnace consists of a single-phase low voltage (about 40V) source obtained from a 60Hz transformer. The voltage across the furnace is selected with the transformer's tap. The current is then controlled by positioning the electrode in the slag (shorter distance, electrode bottom to ingot top, equals more amps and vice versa). The problem with this electrode immersion control is 1 that the distance from the top of the slag bath to the electrode tip is almost non-existent, and this is an important process parameter (especially in a large furnace). Typically there is a saturable reactor in series with the primary of the transformer to provide some current control as shown in Figure 1.2. The current is set with the reactor and the electrode is positioned at a set immersion, which in turn determines the voltage drop across the slag. A high current is supplied to a single electrode in the middle of the crucible, which passes through the molten metal and returns from the conducting wall of the crucible. F I G U R E 1.2. A typical furnace schematic diagram Saturable Reactor 3-ph 1-ph V V System Transformer J= Furnace This high power single-phase load is becoming increasingly unacceptable to customers and a method of transforming the load into an effective balanced three-phase equivalent is sought. In single-phase sinusoidal loads the instantaneous power pulsates at twice the source frequency but the total instantaneous power drawn by a balanced three-phase load is constant. This implies that a substantial energy requirement must be present in any converter between the two systems or an unbalanced load to the three-phase source would be presented. To convert the three-phase input system to a single-phase system, either an A C / A C converter or an AC/DC with a DC/AC converter could be used. The A C / A C converter (cycloconverter) is mostly used in low-speed and very high horsepower applications. The cycloconverter output is derived directly from the line frequency input without an intermediate DC link. In case of the sinusoidal output waveform, the . 2 maximum output frequency is limited to about one third of the input A C frequency to maintain an acceptable waveform with a low harmonic content [1]. Moreover, it would not provide the storage component mentioned before. In the second solution, a thyristor bridge rectifier is used as the AC/DC converter and a current source inverter (CSI) or voltage source inverter (VSI) could be used as the DC/AC converter. As the term implies the basic difference between the VSI and CSI is the following: In the VSI, the DC input appears as a DC voltage source (ideally with no internal impedance) to the inverter while in the CSI, the DC input appears as a DC current source (ideally with the internal impedance approaching infinity) to the inverter. A disadvantage of CSI is that since a thyristor rectifier bridge is used and the DC link inductor provides the energy storage requirements, the power factor is typically poor. Using a DC/DC conversion stage in the DC-link can solve the problem. In the last option, which was chosen, the rectifier bridge would supply a DC voltage bus via an L C filter. It should be noted that DC is not acceptable for the load. It would have its own problems anyway due to the need for high current rectifier. 3 CHAPTER 2 CONCEPTIONAL OVERVIEW 2.1. Introduction Many papers have been studied to have a better idea on designing the DC-bus filter, selecting the switches, selecting the controller scheme, understanding the effects of the non-sinusoidal voltage/current pattern on the transformers and inductors, etc. In this chapter the most important subjects are discussed in detail. 2.2. Filters The objective is the reduction or attenuation of harmonics appearing at the output of the fdter. There are several types available. Series filters must carry full load current and be insulated for full line voltage. In contrast, shunt fdters carry only a fraction of the current that a series filter must carry. Given the higher cost of a series filter, and the fact that shunt filters may supply reactive power at the fundamental frequency, the most practical approach usually is to use shunt filters. For effective filtering, the filter impedance must be comparable to the source. The basic considerations in designing a filter to attenuate certain harmonics adequately are [4]: • Minimizing K V A requirements of the input. • Minimizing of the variation in the output voltage, as the load is varied over its range. • Minimizing of the filter cost. • Minimizing of the filter size and weight. 4 During the actual operation of the six- or twelve-pulse rectifiers, thyristor firing times may vary slightly from the desired 60° delay. This fact and the system unbalance result in the existence of some noncharacteristic harmonics [4]. 2.2.1. The Second Order L C R Resonator The natural modes of the parallel resonance circuit of Figure 2.1.a. can be determined by applying an excitation that does not change the natural structure of the circuit. Two possible ways of exciting the circuit are shown in Figures 2.1.b. and 2. I.e. FIGURE 2.1. The second order parallel LCR resonator a. Circuit diagram b. Circuit excited by a current source c. Circuit excited by a voltage source In Figure 2. Lb. the resonator is excited with a current source I, connected in parallel. Since as far as the natural response of a circuit is concerned, an independent ideal current source is equivalent to an open circuit, the excitation of Figure 2.1.b. does not alter the natural structure of the resonator. Thus the circuit in Figure 2.1.b. can be used to determine the natural modes of the resonator by simply finding the poles of any response function. Consider the response function: — = — = —. . Equating the denominator to the I Y s2 +s(l/CR) + (\/LC) standard form leads to wQ = \HLC and Q=w0CR An alternative way of exciting the parallel LCR resonator for the purpose of determining its natural modes is shown in Figure 2.I.e. Since as far as the natural response of a circuit is concerned, an ideal independent voltage source is equivalent to a short circuit, the excitation of the circuit does not alter the natural structure of the resonator. This would lead to the natural modes determined above. In a design problem, we would be given wo and Q and will be asked to determine L, C, and R. Equations w0 = \I4L~C and Q=w0CR are two equations with three unknowns. The one available degree of freedom can be utilized to set the impedance level of the circuit to a value that results in practical component values [1]. For high pass filters, typical values of Q vary from 0.5 to 2.0. With a high Q, i.e., 2.0, the filtering action is more pronounced at the corner frequency, while at higher frequencies the filter impedance rises steadily. For lower values of Q, the response at the corner frequency is not noticeable, and as the frequency increases, the impedance is roughly constant [4]. 2.2.2. Cascaded L C Filters There are some factors, which may influence the decision of whether to use a cascaded filter. When the filter involved is included in a closed loop voltage regulation system, the presence of the two L C networks can cause a great deal of difficulty in stabilizing. This problem can be alleviated somewhat by separating the filter resonance frequencies by a factor of four or more. Another consideration is the overall size and construction cost of the filter. If the cascaded filter sections were assumed identical to each other, calculations indicate that in filter applications where attenuations of up to approximately 26:1 are required, the single stage filter is most desirable. In cases where attenuations greater than 26:1 are required, the cascaded filter should be considered. 6 2.2.3. Shunt Filters The general layout of shunt filters is shown in Figure 2.2. FIGURE 2.2. Shunt filters * C 2 CI R A") 8) C ) 01 a) Single tuned filter c) Second order high pass filter b) First order high pass filter d) Third order high pass filter The single most used harmonic filter topology is, perhaps, the single tuned filter, which is typically used to filter a single discrete harmonic frequency. The damping resistance is usually set by the physical limitations of the equivalent series inductor resistance and the equivalent series capacitor resistance and no external resistance is added to the circuit [3]. At low frequencies the filter is dominantly capacitive and, therefore, provides reactive power to the system. At high frequencies, the filter is inductive and provides little attenuation for high frequency distortion. At the resonant frequency, the capacitive reactance cancels the inductive reactance and the filter is entirely resistive and the lower the filter resistance, the more attenuation. However, there are practical limits to the value of the R. For high voltage applications (low filter current magnitudes), filter quality factors of 50 < Q < 150 are typical and for low voltage applications (high filter current magnitudes), filter quality factors of 10 < Q < 50 are typical [3]. The value of Q is seldom considered in regards to filtering action. This is due to the fact that the values of R, which must be used to 7 significantly alter the filter response, usually result in a significant increase in losses within the filter. It is advantageous to tune a filter to a frequency somewhat below that at which it is desired. This will provide for sufficient harmonic filtering action, yet will also allow for operation of the filter bank in the event of the removal of a few capacitor units. Typically, filter banks are tuned to approximately 3 to 10 percent below the desired frequency [2], [4]. Another popular topology of the second order series resonant filters is to provide an inductor bypass resistance. Depending on the value selected for the inductor bypass resistance, many different transfer function characteristics are possible. The main application of these filters is to provide attenuation for harmonic frequency components over a wide frequency range. The tuning of these filters is accomplished similar to the second order series resonant filter [3]. 2.2.2. Active Power Line Conditioning Methodologies (APLC) Two fundamental approaches for improving power quality with APLCs are correction in the time domain and correction in the frequency domain. Either can be used in conjunction with voltage type converters or current type converters. Therefore, there are four basic methodologies, each of which contains many possible control strategies. APLCs use an inverter and a DC source to produce the precisely chopped waveform needed to correct a distorted system voltage or current [6] providing that the system is not too stiff. The DC source receives its power from the A C power system, either intentionally through the switching action [7] or through a separate charging circuit [8]. Some references propose that APLCs be used in conjunction with conventional tuned harmonic high pass filters [8]. These hybrid systems offer the advantages of reduced converter size and cost. 8 2.2.2.1. Advantages And Disadvantages of The A P L C Methodologies Correction in the time domain is based on the principle of holding the instantaneous voltage or current within some reasonable tolerance of a sine wave. An instantaneous error function is computed online, and it can be, for example, the difference between the actual and reference waveforms or possibly a more elaborate function such as instantaneous reactive power compensation [5]. Correction in the frequency domain is based on the principle of Fourier analysis and periodicity of the distorted voltage or current waveform to be corrected. While one early reference [9] suggests the use of predetermined harmonic injection for situations where there are a few predominant and fixed harmonics present, more recent references [10] use a Fourier transform to determine the harmonics to be injected. Once the Fourier transform is taken, an inverter switching function is computed to produce the distortion canceling output. The inverter switching frequency must be more than twice the highest compensating harmonic frequency [11]. The greatest advantage of time domain correction is its fast response to changes in the power system [15]. Also, it is easy to implement and has little computational burden. Of course, it ignores periodic characteristics of the distorted waveform, and does not learn from past experiences. The greatest disadvantage of frequency domain techniques lies in increased computational requirements [10]. Therefore, as the order of the highest harmonic to be eliminated increases, the number of calculation also increases, resulting in longer response times [5]. The choice of current type APLCs or voltage type APLCs depends on source of distortion at the specified bus, equipment cost, and amount of correction desired [5]. Voltage type converters have an advantage in that they can be readily expanded in parallel to increase 9 their combined rating [12]. Generally speaking, voltage type converters are lighter and less expensive than current type converters [13]. The main drawback of voltage type converters lies in the increased complexity of their control systems [14]. Current type converters are, on the other hand, claimed to be simpler and more reliable [13]. Higher losses are their main drawback. APLCs are good for harmonic corrections purposes so that the size of the extra inverter would be small compared to the system inverter. In this project, we would need a large energy requirement for the extra inverter so the conventional method of using a storage element at DC-bus is used. 2.3. Transformers And Inductors 2.3.1. Equivalent Circuit For Transformers The equivalent circuit for a two winding transformer is shown in Figure 2.3.a. The shunt resistance branch in Z M represents the iron losses and the shunt reactive branch ti (jw—M) provides a path for the no load, or exciting current of the transformer. M is the n2 mutual inductance between the two windings. The variation in M during the cycle of instantaneous current and voltage variations is ignored and a mean value is used. The branches, ZP=RP + jw(Lp—-M) and Zs =RS + jw(Ls ——M) are essentially constant, regardless of instantaneous current variations, since their corresponding leakage fluxes he mostly in air. Z P and Zs are components of the leakage impedance between the P and S windings such that Zps - ZpJr-^-Zs (Equation 2.1.) where N=n2/ni. Z P S is defined as the leakage impedance between the P and S windings, as measured in ohms on the P winding with 10 the S winding short-circuited. Actually it is not possible to segregate Zps into two parts, Zp associated with the P winding and Zs associated with the S winding by any method of test. For example, Zp, the portion of ZPs associated with the primary winding, varies with excitation and load conditions. It is customary, in many calculations involving the equivalent circuit, to make FIGURE 2 .3. Equivalent circuits for two winding transformers -AAAAA- r.N 2 " I I I 2 s J i . , Es (a) D O E Z(>3 - w w -I:N oa' ao-(b) 2P3X - W W A -IsP-u-oa' E8K (C) a. Equivalent circuit in ohms, with magnetizing current considered b. Equivalent circuit in ohms, with the magnetizing branch neglected c. Equivalent circuit in percent The ideal transformer can be shifted to the right, to get all branches of the circuit on the same voltage base. Since the impedance of the shunt branch is large compared to Zps, it can be omitted for most calculations involving transformer regulation, and the equivalent circuit becomes that of Figure 2.3.b. A notable exception to those cases where the shunt branch can be disregarded is the case of the three-phase core-form transformer excited with zero-sequence voltages. The equivalent circuit using percentage impedances, percentage voltages, and 11 currents in per unit is given in Figure 2.3.c. In this case, an ideal transformer to maintain transformation ratios is not required [16]. The equivalent circuit for a transformer having three windings on the same core is shown in Figure 2.4. where the magnetizing branches have been omitted. The number of turns in the P, S, and T windings are m, n 2, and n3, respectively. The equivalent circuit is shown in Figure 2.4.a. with all impedance in ohms on the P winding voltage base and with ideal transformers included to preserve actual voltage and current relationships between the P, S, and T windings. On the P winding voltage base: ZR = —{ZPS +ZFT — ——-ZSR) ZS = — ( ZSR +ZRS —ZPT) 2 TV,2 2 TV,2 ZT =\{Z„ +-±TZsr-ZPS) N.=^- and N2=^ 2 TV,2 n, «, FIGURE 2.4. Three-winding transformer a. Equivalent circuit in ohms b. Equivalent circuit in percent Note that Zp and Zs as defined and used here, differ from Zp and Zs in Equation 2.1. The equivalent circuit expressed in percent is given in Figure 2.4.b. with all impedances referred to the K V A of the P winding. 12 Zp % = -{Zps % + % -jf-ZST %) Z , % = -(-f-Zsr % + Zps % - Z^ %) Z r % = - ( Z ^ % +—ZST % - Zps %) 2 [/j, The quantities can be expressed in percent on any arbitrary K V A base, Uc, by multiplying each impedance by the ratio Uc/Up. The notation used is defined as: U P =KVA Of the P winding U S =KVA of the S winding U T =KVA of the T winding Zps=leakage impedance between the P and S windings as measured in ohms on the P winding with the S winding short-circuited and the T winding open-circuited. ZpS%=leakage impedance between the P and S windings, with the T winding open-circuited, expressed in percent on the K V A and voltage of the P winding. ZpT=leakage impedance between the P and T windings as measured in ohms on the P winding with the T winding short-circuited and the S winding open-circuited. Zpx%=leakage impedance between the P and T windings, with the S winding open-circuited, expressed in percent on the K V A and voltage of the P winding. ZsT=leakage impedance between the S and T windings as measured in ohms on the S winding with the T winding short-circuited and the P winding open-circuited. ZST%=leakage impedance between the S and T windings, with the P winding open-circuited, expressed in percent on the K V A and voltage of the S winding. The equations given in Figure 2.13.a. and Figure 2.13.b. for Z P , Z P %, etc., are derived from the relationships below: Zps=Zp+Zs Zpx=Zp+Zx Zsx=Ni2(Zs+Zx) ZPS%=Zp%+Zs% ZPT%=Zp%+ZT% ZST%=(US/UP)(Z S %+Z T %) 13 Also: Zp=RP+jXp, Zps=Rps+jXps=RP+Rs+j(Xp+Xs), Zps%=RPs%+jXpS%, etc. where Xps is the leakage reactance between the P and S windings (with T open-circuited) and Rps is the leakage resistance, or total effective resistance between the P and S windings, as measured in ohms on the P winding with S short-circuited and T open-circuited. RPs% and Xps% are the same quantities expressed in percent on the K V A and voltage of the P winding. The equivalent circuits completely represent the actual transformer as far as leakage impedances, mutual effects between windings, and losses are concerned (except exciting currents and no load losses). It is possible for one of the three legs of the equivalent circuit to be zero or negative [16]. 2.3.2. I E E E Recommended Practice For Establishing Transformer Capability When Supplying Nonsinusoidal Load Currents The recommended practice applies to all power transformers covered by ANS/IEEE C57.12.01-1979 [19] and to power transformers up to 50MVA maximum nameplate rating covered by ANSI/IEEE C57.12.00-1987 [20], when subjected to nonsinusoidal load currents having a harmonic factor exceeding 0.05 per unit. Harmonic factor is defined in ANSI/IEEE C57.12.80-1978 [21] as the ratio of the effective value of all the harmonics to the effective value of the fundamental [18]. 2.3.2.1. Transformer Losses ANSI/IEEE C57.12.90-1987 [21] and ANSI/IEEE C57.12.91-1979 [22] categorize transformer losses as: no load loss (excitation loss), load loss (impedance loss), and total loss (the sum of no load loss and load loss). Load loss is subdivided into I2R loss and stray loss. Stray loss is determined by subtracting the I R loss (calculated from the measured resistance) from the measured load loss (impedance loss). 14 Stray loss can be defined as the loss due to stray electromagnetic flux in the windings, core, core clamps, magnetic shields, enclosure or tank walls, etc. Thus, the stray loss is subdivided into winding stray loss and stray loss in components other than the windings (POSL)-The winding stray loss includes winding conductor strand eddy current loss and the loss due to circulating currents between strands or parallel winding circuits. All of these losses may be considered to constitute winding eddy current loss, PEC- The total load loss can then be stated as PLL=I 2R+PEC+POSL (Equation 2.2.) [18]. If the RMS value of the load current is increased due to the harmonic components, the I 2R loss will be increased accordingly. Winding eddy current loss in the power frequency spectrum is proportional to the square of the load current and the square of the frequency [23]. It is this characteristic that can cause excessive winding loss and hence abnormal winding temperature rise in transformers supplying nonsinusoidal load currents. It is recognized that other stray loss in the core, clamps, and structural parts will also increase as a result of nonsinusoidal load current. However, temperature rise in these regions will be less critical than in the windings [18]. A DC component of load current will increase the transformer core loss slightly, but will increase the magnetizing current and audible sound level more substantially. Relatively small DC components (up to the RMS magnitude of the transformer excitation current at rated voltage) are expected to have no effect on the load carrying capability of a transformer determined by this recommended practice. Higher DC load current components may adversely affect the transformer capability and should be avoided [18]. 15 2.3.2.2. Transformer Capability Equivalent Calculation Using Data Available from Certified Test Report In order to make the calculation with this limited data, certain assumptions have been made that are considered to be conservative. (1) The certified test report includes all data listed in the appendixes to ANSI/IEEE C57.12.90-1987 [26] or ANSI/IEEE C57.12.91-1979 [22]. (2) All of the stray loss is assumed to be winding eddy current loss. (3) The-I2R loss is assumed to be uniformly distributed in each winding. (4) The division of eddy-current loss between the windings is assumed to be as follows: (a) 60% in the inner winding and 40% in the outer winding for all transformers having a maximum self cooled current rating of less than 1000 amperes-(regardless of turns ratio). (b) 60% in the inner winding and 40% in the outer winding for all transformers having a turns ratio of 4:1 or less. (c) 70% in the inner winding and 30% in the outer winding for all transformers having a turns ratio greater than 4:1 and also having one or more windings with a maximum self cooled current rating greater than 1000 amperes. (5) The eddy-current loss distribution within each winding is assumed to be nonuniform. The maximum eddy current loss density is assumed to be in the region of the winding hottest spot and is assumed to be 400% of the average eddy current loss density for that winding. A high percentage of the leakage flux flowing axially in and between the windings is attracted radially inward at the ends of the windings, because there is a lower reluctance return path through the core leg than through the unit permeability space outside the windings. As a result, the highest magnitude of the radial component of leakage flux density (and highest eddy loss) occurs in the end regions of the inner winding. In the absence of other information, the 16 inner winding may be assumed to be the low voltage winding. The eddy loss distribution assumptions (4) and (5) are very conservative [18]. As established in test codes ANSI/IEEE C57.12.90-1987 [26] and ANSI/IEEE C57.12.91-1979 [22], the stray loss component of the load loss is calculated by subtracting the I 2 R loss of the transformer from the measured load loss. By assumption (2) of this section, all of the stray loss is taken to be winding eddy current loss. Therefore: PEC-R=PLL-K[(II. r) 2RI+(I 2-R) 2R2] watts (Equation 2.7). Where K=l for single-phase transformers and K=1.5 for three phase transformers (ANSI/IEEE C57.12.91-1979 [26], 9.2.5.1). Many test reports for three phase transformers show the resistance of three phases in series. In these cases values for Ri and R 2 may be calculated as follows: • Delta Winding: Ri or R2=2/9 of three phase resistance. • Wye Winding: Ri or R2=2/3 of three phase resistance. The low-voltage (inner) winding eddy current loss can be calculated from the value of PEC-R determined from Equation 2.7. as either 0.6PECR watts or 0.7PEC-R watts, depending on the transformer turns ratio and current rating. The low voltage winding eddy current loss in per unit of that winding's I2R loss will be either PEC_R (pu) = ®'^^EC-R—pU (Equation 2.8.) or assumed to be uniformly distributed within the winding, and by assumption (5) the maximum eddy current loss density is assumed to be 400% of the average value, K(I2_R) R2 PEC-R(PU) = pu (Equation 2.9.). Since by assumption (3) above the I2R loss is MaxPEC_R(pu) = ^•^L EC-R K(I2_R)2R2 pu (Equation 2.10.) or MaxPEC_R(pu) = K(I2_R)2R2 pu (Equation 2.11.) [18]. 17 2.3.3. Losses And Flux Penetration In Non-Grain-Oriented Low-Loss Steel With Nonsinusoidal Excitation A comparatively large harmonic voltage results in considerably less harmonic flux. The component of harmonic flux density is attenuated more rapidly than the fundamental flux density with depth [29], [58]. T A B L E 2.1. Waveform characteristic Waveform Relative values for same crest Ratio voltage 9 6,. RMS voltage V fundamental voltage V, max. flux density 6.. V Sine . 1 0707 1.0 0.637 0.901 Square to 2n 1 1.0 1.273 10 1.0 Quasisquare A to | _ J w 0.816 1.103 0.667 0 817 Quasisquare B 0.707 0.955 0.667 0.943 Lavers et al [31] assume that hysteresis loss is a function of peak flux density only, and this is verified in the paper [30] for thin laminations with frequencies of order 50Hz in which the flux density distribution is sensibly constant across the lamination. Reference [32] gives expressions for eddy current loss, and for hysteresis loss including minor loop effects. A paper [33] by O'Kelly has described a computer simulation technique to represent the family of hysteresis loops of a ferromagnetic material. Using a multi layer approach [34], losses and flux penetration in laminations owing to both hysteresis and eddy current action are evaluated. 18 Three typical wave shapes of the inverters are shown in Table 2.1. The major loss A A component is due to hysteresis, which depends upon Bav . Hence the BJV ratios of Table 2.1. give an indication of the relative losses of the three nonsinusoidal voltage waveforms and a sinusoidal voltage for a specified voltage level [30]. FIGURE 2 .5. Normalized loss characteristic d = thickness in p.u.;/ * frequency in p.u. - - - classical loss (sine wave excitation) —•—-sinusoidal ~) — square wave Vcomputed values • • —-quasisquare wave A j With an assumed uniform flux distribution in a lamination the loss may be simply evaluated from the classical loss expression given by: Classical core loss=hysteresis loss+eddy current loss (Equation 2.12.) 19 With the multi layer theory [34] the influence of eddy current action modifies the flux distribution in the lamination. Losses are then evaluated by summing the hysteresis loss and the eddy current loss in each layer. Results given for a range of magnetization levels and harmonic frequencies show that Equation 2.12. is not quite as accurate for the assessment of losses with excitation voltages consisting of a fundamental and one harmonic component. Figure 2.5. shows the loss characteristics for the four voltage wave shapes defined in Table 2.1. Several other useful diagrams are also available in reference [30]. 2.4. Power Switches Ultra high power, high voltage, power electronics is on the verge of a new era. Two new power semiconductor technologies, the high voltage IGBT and the G C T (Gate Commutated Thyristor) are improving the performance, simplifying the design and increasing the reliability of applications ranging from 100's of k V A to many M V A . They seek to replace the venerable GTO by offering snubberless turn off capability and higher operating frequencies. Here the characteristics and application considerations of these revolutionary new technologies are discussed [36]. 2.4.1. Types of Power Switches 2.4.1.1. GTOs The Gate Turn Off Thyristor (GTO) is a very high power semiconductor switch, destined for use in industrial applications demanding the ultimate in voltage blocking and current carrying capabilities. GTOs differ from conventional thyristors, in that they are designed to turn off when a negative voltage is applied to the gate electrode, thereby causing a reversal of gate current. Like all bipolar devices, the GTO is a current controlled device 20 imposing certain demands on its gate drive circuitry. A relatively high gate current is needed to turn off the device, with typical turn off gains being in the range of 4 to 5 [37]. 2.4.1.2. IGBTs And HVIGBTs The IGBT, Insulated Gate Bipolar Transistor, is a switching transistor that is controlled by voltage applied to the gate terminal. Because the IGBTs are voltage-controlled devices, they only require voltage on the gate to maintain conduction through the device. IGBT modules can be connected in parallel for applications requiring very high currents. In such applications parallel operation should only be considered when the highest current module available is not large enough. It may be observed that Powerex IGBTs have a negative temperature coefficient of saturation voltage over a wide range of collector currents. This is not a deterrent to parallel operation and, in fact, is an advantage as it yields lower conduction loss at high junction temperature. The homogeneous process of H-series IGBTs produce VCE(SAT) characteristics that track as a function of current and temperature such that once a VCE(SAT) rank is chosen, the parallel devices will share within the given derating factor. Parallel devices should be mounted on the same heatsink near each other [40]. 2.4.1.3. IGCTs Conventional GTOs require costly dv/dt and di/dt snubber circuits as well as bulky gate drive circuits. Hard turn off in which all of the main current is commutated to the gate drive circuit with a turn off gain of one has been looked upon as a way to reduce the dv/dt limitations of the conventional GTO. The new Gate Commutated Turn-Off (GCT) Thyristor is optimized for this mode and is coupled with a low inductance gate drive circuit to greatly reduce the di/dt limitation and allow operation without a dv/dt snubber. 21 As the GCT Thyristor has fast turn on and turn off operation, the associated free wheel and clamp circuit diodes must also have high speed switching capability. A new soft recovery diode has been developed to provide the capability necessary to apply the superior characteristics of the new GCT in actual application. With the ring gate terminal the inductance between the gate and cathode is about one tenth that of a conventional GTO Thyristor. As with the IGBT, the device's inherent di/dt capability is very high but that of the accompanying FWD is not urilimited and it is for the latter that turn on di/dt must be restricted. Here a major difference appears between IGBTs ad IGCTs: the IGCT must have an external di/dt snubber, whereas the IGBT can limit di/dt via gate control. In both approaches, power is wasted at each commutation: internally for the IGBT and in the clamp resistance (Figure 3.6) for the IGCT. 2.4.2. Application Considerations In Choosing The Power Switch The deciding factors in choosing a power switch are discussed below [36]. 2.4.2.1. Power Circuit Topology Figure 2.6. shows one arm of a single level voltage source inverter constructed using GTOs, GCTs, and HVIGBTs. The GCT uses a voltage clamp circuit instead of an RCD snubber because it is not necessary to limit the dv/dt at turn off. The clamp circuit is typically smaller and considerably lowers loss than the GTO's dv/dt snubbers. In addition, the GCT has higher turn on di/dt capability. This makes it possible to significantly reduce the size of the di/dt snubber reactor and its associated losses. These circuit changes combined with the GCT's inherently lower turn off losses permit a significant increase in operating frequency. While GTOs are typically 22 limited to switching frequencies of a few hundred Hertz in most applications, the GCT can be operated at frequencies greater than 1kHz. FIGURE 2.6. Voltage Source Inverter Phase Leg Comparison G T O G C T HVIGBT Clearly, the HVIGBT topology is simplest of all. The reason is that unlike the GTO and GCT, the IGBT can control the turn on di/dt. This eliminates the need for a di/dt snubber. If low inductance laminated buswork is used, it is possible to operate the HVIGBT without any additional snubbers or clamping circuits. However, using the power device to control the di/dt results in substantially higher turn on losses [36]. 2.4.2.2. Gate Drive Figure 2.7. shows a comparison of the typical gate drive current required for HVIGBTs and GCTs. Table 2.2. shows typical gate driver characteristics for GTOs, GCTs and HVIGBTs. The GCT requires an initial high current pulse to bring the entire device area into full conduction. For the 4000A GCT, this current pulse is typically 200A for about 5ps. In order to achieve the data sheet turn on di/dt rating of 1000A/u,s this pulse must be applied at a rate of at least 1 OOA/ps. At first, this may sound difficult, but it is relatively easy compared to turn off. During steady on state operation, a continuous current of at least the devices IQT rating must be 23 applied to insure that the device's entire area stays fully on. For the 4000A GCT, a continuous current of about 1 OA is required in the on state. At turn off a reverse current pulse equal to the device's main current must be applied. For full rated snubberless turn off capability, the driver must be able to supply a 4000A pulse applied at a rate of 6000A/u.s. This requires a large number of paralleled low voltage MOSFETs and a bank of electrolytic capacitors. The Powerex/Mitsubishi GU-C40 gate driver's output MOSFET has an effective PvDS(on) of less than 300p.Q and its output capacitor is 40,000pF. The MOSFETs and capacitors are arranged on a multi layer PCB to form a low inductance parallel plate structure with an effective inductance to the GCT gate of around 3nH. FIGURE 2.7. HVIGBT and GCT gate drive current 200A + 100A + 10A -10A: 1000A + 2000A GCT -HVIGBT Turn-On On-State Turn-Off t: 2u.s/div V H — I > IGQ I^T HVIGBT GCT 24 The HVIGBT's gate drive is basically the same as lower voltage IGBTs. The gate of the HVIGBT is similar to a capacitor. To turn the device on and off, the capacitor must be charged and discharged. Like lower voltage IGBTs, the recommended turn on voltage is 15V. In the off state, a reverse bias of -10V to -15V should be applied to maintain good noise immunity. T A B L E 2.2. Typical gate drive characteristics Characteristic GTO GCT HVIGBT Turn on Peak current (A) 25 200 15 Duration (u.s) 10 5 1.5 On state Current (A) 10 10 0 Turn off Peak current (A) 850 4000 15 Duration 30 2 1.5 Total charge (mC) 20 9 0.01 Total power (W) 300 150 1 Clearly, HVIGBT gate drive is simpler and requires less power than G C T gate drive. One of the most significant contributions to the higher power requirements of the GCT gate drive is the need for continuous current in the on state. This current can be reduced if the GCT is designed with a lower gate trigger current. This approach has been adopted by at least one manufacturer. The problem that arises with this approach is that off state noise immunity is degraded. The low trigger current device may be turned on with as little as 20mA at elevated junction temperature [36]. 2.4.2.3. Losses Table 2.3. summarizes the key loss characteristics of the HVIGBT and GCT. This comparison is not a particularly good one because these devices are not of the same rating. 25 As expected, the GCT has a clear advantage in conduction losses while the IGBT has a clear advantage in turn off losses. Turn-on losses cannot be compared because the normal circuit topology for these devices is different (see Figure 2.18.). If a di/dt liiniting turn on snubber were used with both devices the turn on losses would be about the same [36]. T A B L E 2.3. Loss characteristics Characteristic Condition GCT W } = 1 2 0 0 A , V D R M = 4 5 0 0 V HVIGBT I C =1200A,V C E S =3300V VTM/VC E(Sat) max I=1200A, Tj=125°C 2.6 5.1 E0ff (J/pulse) Inductive load, Snubberless I=1200A, Tj=125°C, VDC=1650V 2.5 1.2 2.4.2.4. Reliability By itself, the GCT's simpler monolithic design is likely to be more reliable than the relatively complex multi-chip HVIGBT module. In addition, the GCT's pressure contact (hockey puck) design has well known advantages in terms of thermal cycle capability. On the other hand, the HVIGBT has a simpler, lower power gate drive, and does not require the array of external clamp and snubber devices that are needed with the GCT. Furthermore, the HVIGBT module does not require the precision mechanical clamping assembly that is needed with large hockey puck devices. Clearly, reliability will be driven by the requirements of the end application and the system design. In any case, both devices have been shown to have rehability advantages over the GTO's that they are intended to replace [36]. 2.4.2.5. Application Range Figure 2.8. shows today's concept of the appropriate application range for HVIGBTs and GCTs. Six thousand volt GCTs with snubberless turn off capability in excess of 4000A 26 have been demonstrated by a manufacturer and will soon be commercially available. The HVIGBT appears to be best suited for the lower end of high power applications. In these applications, the HVIGBT offers increased performance and greatly simplifies design and assembly. Research on both the HVIGBT and GCT continues [36]. FIGURE 2.8. Proposed application range of HVIGBT and GCT 100 1000 Current A R M S 10.000 2.4.3. IGBT Snubber Design The function of IGBT snubbers is different from classical bipolar transistor snubbers in two ways. First, it is only necessary for the snubber to control transient voltages. Second, snubbers that are discharged through the device on every switching cycle dissipate too much power for these applications [40]. Figure 2.9. shows four common IGBT snubber circuits. Snubber circuit "A" consists of a single low inductance film capacitor connected from CI to E2 on a dual IGBT module. In low power designs this snubber will often provide effective, low cost control of transient voltages. As power levels increase, snubber "A" may begin to ring with parasitic bus 27 inductance. Snubber "B" solves this problem by using a fast recovery diode to catch the transient voltage and block oscillations. FIGURE 2.9. Common IGBT snubber circuits C 0 The RC time constant of snubber "B" should be approximately one third of the switching period (x=T/3=l/3f). With large IGBTs operating at high power levels, the parasitic loop inductance of snubber "B" may become too high for it to effectively control transient voltages. In these high current applications snubber "C" is usually used. This snubber functions similarly to "B" but it has lower loop inductance because it is connected directly to the collector and emitter of each IGBT. Snubber "D" is useful for controlling transient voltages, parasitic oscillations, and dv/dt noise. Unfortunately its losses are quite high and it is generally not suitable for high frequency applications. In very high power IGBT circuits, it is often helpful to use a small snubber "D" in conjunction with a main snubber "C" in order to help control parasitic oscillations in the main snubber loop. In very high power applications it 28 may be helpful to combine types "A" and "C" in order to reduce the stresses on the snubber diode [40]. 2.5. Static Frequency Converters Perhaps the most rapidly growing area in modern power electronics is the static frequency conversion, the conversion of ac power at one frequency to ac power at another frequency by means of solid-state electronics. Traditionally there have been two approaches to static ac frequency conversion: the cycloconverter and the rectifier-inverter. The cycloconverter is a device for directly converting ac power at one frequency to ac power at another frequency, while the rectifier-inverter first converts ac power to DC power and then converts the DC power to ac power again at a different frequency [43]. 2.5.1. Rectifier-Inverters 2.5.1.1. Rectifiers The three-phase full wave rectifier is one of the most common rectifier circuits used in the industry. When SCRs are used instead of diodes in the rectifier circuit to get control of the dc voltage output, this output voltage will have more harmonic content than a simple rectifier would, and some form of filter on its output is important [43]. To investigate the rectifier circuit in more details, the ac-side inductance Ls is included in Figure 2.10. which cannot be ignored in practical thyristor converters. Now for a given delay angle a, the current commutation takes a finite commutation interval u (Figure 2.11.). It can be shown that during the commutation interval, vPn = - ^ ( v a „ + v c n ) . The input current waveform is shown in Figure 2.12. [44]. 29 FIGURE 2.10. Three-phase converter with Ls and a constant dc current FIGURE 2.11. Commutation in the presence of Ls FIGURE 2.12. Line current in the presence of Ls 30 2.5.1.1.1. Twelve Pulse Rectifiers To obtain output DC voltages and input currents with low ripple factor, from an A C voltage network, twelve pulse rectifiers could be used. The input A C voltages must be shifted by a half period of the output voltage. This phase shift is obtained with an appropriate connection of transformers at the input of the rectifiers. Also, to obtain high output voltages and/or high output currents, it is essential to use more than one rectifier, making the parallel or serial associations [47]. The interphase reactors could be included to ensure the independent operation of the two three-phase bridge rectifiers in parallel and supplying nonlinear loads [25], [45]. The simulation results had concluded that the twelve-pulse thyristor converter with the optimal interphase reactor behaves like a 36-pulse thyristor converter [46]. On the other hand, in twelve pulse diode rectifiers, the parallel circuit needs no interphase transformer because the rectifiers are uncontrolled and the slight extra loading on the main transformer can be accepted. The main transformers are double-tiered, however, with two separate windings on the input side [42]. The interphase reactor could be specified according to the following guidelines: • Voltage: Should be equal to the difference between the full load voltages of the transformers. • Current: The number of turns in the two parts of the winding should be inversely proportional to the rated currents of the transformers. Currents in both halves of the reactor and consequently in the two transformers will be the same. 2.5.1.2. Inverters There are three major types of inverters. Current and voltage source inverters are simpler than PWM inverters and have been used for a longer time. PWM inverters require more 31 complex control circuitry and faster switching components than CSIs and VSIs. Current source inverters and voltage source inverters are compared in Table 2.4. T A B L E 2.4. Comparison of current source inverters and voltage source inverters Current source inverter Voltage source inverter Main circuit configuration Rectifier inverter Rectifier Inverter Type of source Current source —/ almost constant Voltage source- V' ylrnostconstant Output impedance High Output waveform ( 1 8 0 ° c o n d u c t i o n ) (1 20° conduction) voltage Characteristics 1. Easy to control overcurrciH conditions with this design 2. Output voltage varies widely with changes in load 1. Difficult to limit current due to capacitor 2. Output voltage variations small due to capacitor Pulse-width modulation is the process of modifying the width of the pulses in a pulse train in direct proportion to a small control signal; the greater the control voltage, the wider the resulting pulses become. By using a sinusoid of the desired frequency as the control voltage for a PWM circuit, it is possible to produce a high-power waveform whose average voltage varies sinusoidally [43]. 32 2.5.2. Cycloconverters Cycloconverters are devices for directly converting ac power at one frequency to ac power at another frequency. Compared to rectifier-inverter schemes, cycloconverters have many more switches and much more complex gating circuitry. Despite these disadvantages, cycloconverters can be less expensive than rectifier-inverters at higher power ratings. The cycloconverter generates its desired output waveform by selecting the combination of the three input phases, which most closely approximates the desired output voltage at each instant of time [43]. 2.6. Control Schemes Among the current control schemes for PWM inverters, the main schemes are: linear control, hysteresis control and predictive current control. Figure 2.13. shows simplified diagrams illustrating the operation principle of these schemes. FIGURE 2.13. Main current control schemes In the linear control scheme, the output currents are compared to the references and the errors are processed by conventional proportional-integral controllers to provide a control 33 signal for a PWM modulator. The latter produces constant-frequency pulse width modulated drive signals for the inverter switches. The controller parameters are adjusted to optimize the system transient response and to minimize the magnitude and phase errors in the motor line currents. In the basic hysteresis control scheme, the output currents are sensed and compared to the references using hysteresis comparators. The inverter switches are driven directly by the comparators' output signal. The output currents are thus forced to follow the references within the hysteresis band. Hysteresis controllers can produce very fast transient response, and they are more robust than linear controllers due to their operation principle [51]. The predictive current control scheme uses the sampled data approach and is based on the space vector concept. An appropriate voltage space vector that would force the actual current vector to follow the reference vector is computed using the model of the load and is then applied to the load [24]. Because of the large amount of computation required, the implementation of predictive controllers is complex and requires high-speed microprocessors [39], [54], [53]. The accuracy of predictive controllers depends largely on the accuracy of the load model used in the calculations. As a result, the robustness of this control scheme is poor with regard to the variations of load parameters and DC voltage supply [51]. 2.6.1. Current Mode Control The PWM direct duty ratio control discussed so far is shown in Figure 2.14.a., where the control voltage v c (amplified error signal between the actual output and the reference) controls the duty ratio of the switch by comparing the control voltage with a fixed frequency sawtooth waveform. This control of the switch duty ratio eventually brings the output voltage to its reference value. 34 In a current mode contro l , an addi t ional inner contro l loop is used as shown in F igure 2.14.b., where the control voltage v c d irect ly controls the output current that feeds the output stage and thus the output voltage [44]. FIGURE 2.14. P W M duty ratio versus current-mode contro l Output voltage reference Control E r r o r \ ^ v o l t a g e vc [Amplifier^ Sawtooth waveform (a) Compa- Drive rator Circuitry Output voltage reference u Control E r r o r \ voltage uc lAmplitier, Comparator and Latch lb) Drive Circuitry K • Measured current a. PWM duty ratio control b. Current mode control 35 C H A P T E R 3 T H E O L D S Y S T E M 3.1. Introduction The old system in the Advanced Material and Process Engineering Laboratory (AMPEL) building was investigated carefully and the capability of the existing feeder to supply the three-phase load was verified. The old system was fed from a 4 M V A 12.48kV/600V transformer. It has an impedance of 6.82%. The 12.48kV bus is fed from a paralleled 25MVA 69kV/12.8kV transformers. The impedance of these should be low enough to be neglected for all practical purposes. The old system was consisting of a 250kVA single-phase transformer, two tap switches, a 660V 250kW AC3 contactor and a 600A three-phase circuit breaker. Several tests were carried out to find the characteristics of the transformer, conductors and the furnace. Details of the tests done on the old system are included in Appendix A. 3.2. The Transformer With the two tap switches installed on the cabinet, different output voltage and currents could be selected. At different tap switch positions several tests have been done on the old single-phase transformer, which are included in appendix A. These tests were carried out to find out if the existing transformer could be used in the new system. 36 3.3. C o n d u c t o r s a n d the F u r n a c e According to the short circuit tests done at the place of the furnace, the inductance of the furnace and the conductors between the output of the transformer and the furnace were calculated as well. The test results are summarized in Table 3.1. T A B L E 3.1. Summarized short circuit test results Physical Inductance (ii.H) Conductors between the secondary and the electrode/furnace 4.3 Electrode/furnace 1.8 3.4. C o n c l u s i o n s At the end, our client had identified lOkA at 40V as the maximum power they may use on the furnace. It was concluded that the existing transformer is too small for the new load and it was not designed for operation from an inverter, which voltage waveform would subject the turn-to-turn insulation to voltage stresses it was never designed for. Therefore a new transformer is used for the new power supply. 37 C H A P T E R 4 T H E N E W S Y S T E M 4.1. Introduction In the extensive meetings that we had with our client, the system specifications were discussed in detail. Listed in Table 4.1. are the most important specifications for the new power supply. Our client states that the slag in a resistive melting furnace is purely resistive while the conductor between the output transformer and the furnace behaves as a big inductor. T A B L E 4.1. The new power supply specifications Item Specification Input 600V, 3ph DC-bus 1800VD C (Nominal) Output 40V (Square wave), lOkA Slag 4m£2, Pure resistive Practical considerations were one the most important factors in the design and choosing of the elements. The complete power circuit diagram is shown in Figure 4.2. It consists of two separate AC/DC and DC/AC converters. In accordance to the manufacturers datasheets and technical handbooks, component models were prepared to be used in the simulation. For the busbars and cables, an inductor in series with a resistor was used [16], [38]. The slag was considered as the load and was modeled as a pure resistance. For the capacitors, IGBTs and diodes, the models shown in Figure 4.1. were used. 38 F I G U R E 4.1. Simplified models used for PSIM a. b. c a. Capacitors b. IGBTs c. Diodes In the first half period, T4 is always on and T l is switching (Figures 4.2., 4.3., 4.4. and 4.5.). When T l turns on, the load current will pass through T l and T4. Because of the inductance present in the load circuit, when T l turns off, load current does not stop immediately. As the result the load current passes through D2 and T4. If there was a big DC-bus inductance present, T l current couldn't stop immediately as well and there would be some voltage spikes across the switch. At this time, when T l turns on again, if there be a big DC-bus inductance, the current in T l cannot start immediately thus the current in D2 does not stop immediately. This means that the inductance of the DC-bus could limit the rise of current in T l and T3 when they are switching. In the case of using a laminated bus bar, this induce is very small so the current rise should be limited via gate control of the IGBT. At the beginning of each period we would have some currents in the FWDs as long as we have inductance at the load circuit. If T l be gated while the diode D l is on, there would be no effect to the system since current is passing through D l and V0ut=+VDc (T4 is also on). At that time load current is in the negative direction and it is giving back energy to the DC-bus. 39 FIGURE 4.2. Power circuit diagram F I G U R E 4.3. Typical gating waveforms for the IGBTs. From top to bottom: for the upper left, lower left, upper right and lower right IGBT FIGURE 4.4. Typical voltage waveforms across the IGBTs. From top to bottom: across the upper left, lower left, upper right and lower right IGBT 41 F I G U R E 4 .5. Typical current waveforms for the IGBTs and FWDs. From top to bottom: for the upper left IGBT, upper left FWD, lower left IGBT, lower left FWD, upper right IGBT, upper right FWD, lower right IGBT and lower right FWD 200 DO 1S0O0 10000 30X0 0£O A -SO 00 -1000) -150.00 -250.00 | -00005 I 13)10 ICOJOO SOJCO Q U I OJOO -3000 -tOOOO -13100 -200DO 23300 200.00 13)00 1000) 3)00 000 When the current in diode D l reaches zero, load current begins to pass through T l in the positive direction. Therefore, dead time between the gating signals of the same leg doesn't have any effect on the performance of the system with an inductance present at the output. 42 As can be seen in the Figure 4.3., the first switching-on-time for T l and T3 are considered to be twice as the rest. This would cause the output current to rise more quickly at the beginning of each half period. At full load, the switches are gated in pair sets of (Tl , T4) and (T2, T3) to have a square wave voltage waveform at the output of the inverter. 4.2. A C / D C Conversion To have a smoother DC-bus voltage with less input harmonic currents, a twelve-pulse rectifier circuit was considered. 4.2.1. Input Transformer For the transformers, simplified models were used. The three-phase input transformer parameters were calculated considering: ZPS%=ZpT%=4%, SP=500kVA ZST%=2%, Ss=ST=250kVA Hence: Zp%=Z s%=ZT%=2% and ZP=Zs=ZT=14.4mn. The voltage drop was considered to be 1.3% therefore RP=Rs=RT=4.7imQ and at 60Hz, Lp=Ls=Lx=36.1p:H (All the values are referred to the primary side). The three-phase transformer was specified to be 500kVA 600/660/660V, A/Y/A connected. The voltage ratio of the transformer was chosen according to the following facts: • Two rectifiers are in series. Therefore, each rectifier should provide 1 800/2=900VDC-• The three phase rectifier output voltage formula is VDC=1.36VLL=900VDC. 43 At no-load, the DC-bus capacitor charges up to the maximum voltage and the DC-bus voltage would be VDC=660XV2 X2=1865VDC unless the DC-bus voltage be adjusted by reducing the firing angle of the thyristors. 4.2.2. Thyristor Rectifier Bridge 4.2.2.1. Thyristor Protection Against Short Circuits The silicon chip in a thyristor or in a rectifier diode has a very low thermal capacitance and therefore can be destroyed within a few milliseconds by a high, rapidly increasing surge current as would occur in the case of short circuit. The usual low voltage fuse links, even the quick operating types, are not suitable for protecting rectifier diodes and thyristors against short circuits. Special types have therefore been developed which are described as super fast, ultra fast or simply, semiconductor fuse links. The most common reasons for short circuits with converters are: • Short circuit of the load or of the busbars between the converter equipment and the load. • Short circuit of a rectifier diode or a thyristor due to the loss of its blocking capability (random failure). • With inverters conduction-through (or shoot-through) as a consequence of a commutation failure or false firing. If suitable semiconductor fuse links are connected in series with each rectifier diode and each thyristor used in the principle arms, then these semiconductor components will be protected from destruction in all the cases listed above. Simultaneously all other components in the main circuit of the equipment will be protected: the coils, transformers, resistors etc., since these are generally much less sensitive to surge currents than the semiconductor components. 44 With bridge circuits each A C connection is common to two principal arms. These can therefore be protected by a common fuse link in the A C line (Figure 4.6.b.), which is called Line Fusing. It has the advantage that less fuse links are used and, when they operate, their switching voltages are not applied across the semiconductor components in the circuit. With the high current ratings of thyristors or rectifier diodes, as can be achieved with forced cooling, it can be impossible to find a fuse link which has a sufficiently high nominal current to be connected in the line (The RMS current in the line is -Jl times that of a single arm) and whose 11 value is lower than the equivalent rating of either of the two semiconductor components. This situation is more likely to occur with high voltage circuits, since the I2t value of a fuse link increases with voltage. In this case a fuse link must be connected in each arm of the circuit, which is called Arm Fusing (Figure 4.6.a.) [27]. FIGURE 4.6. Possible positions for semiconductor fuses in bridge converters 2T ir 0 II [] 11 r r r r a) a. Arm fuse links b) b. Line fuse links To protect the thyristors from short circuit, fast acting fuses from Cooper Bussmann were considered to be installed in series with the thyristors but because of their price, which were almost the same as the thyristors', they were not included in the final design. 45 4.2.2.2. T h y r i s t o r Se lec t i on The permissible currents for thyristors are shown by the average value. There could be two situations [28]: • When no inrush current flows: Load current% 1.3tl .5 permissible current for thyristor • When inrush current flows, the inrush current should be measured and a detailed heat calculation should be made. The current is roughly estimated to be twice as the calculated value when no rush current flows. Withstanding voltage of thyristors (VDRM) are calculated according [28]: Supply voltage%2.5t3 Withstanding voltage of the thyristor In this project, there is a 10% (40kW) power loss in the devices at the front of the thyristor bridges, the total power at DC-bus would be 440kW. Supposing a 10% voltage drop at full load, the full load DC-bus voltage is about VDc=1865%0.90=1680VDC and the full load DC-bus current is about lAv=440k/1685=260ADc- Later on, the DC-bus capacitor is identified bigger than what is calculated for a 10% voltage drop at DC-bus, therefore, the actual voltage drop at DC-bus would be less than 10% and Uv would be smaller than what was calculated here. Since each thyristor only conducts one third of the fundamental period, for each thyristor IAVE=260/3=87A. Therefore, the permissible current for thyristor=87%1.5=130A. The supply line-to-line (RMS) voltage is 660V so VDRM=660%3=1980V. IRKT142-20 from International Rectifier with VDRM=2000V, IT(AV)=140A was chosen among other thyristors from other manufacturers because of its lower price. 46 4.2.2.3. Thyristor Snubbers To calculate the snubber components, the design procedures provided in the reference [44] is used. Supposing that the reverse recovery time be trr=10|is and the A C side reactance be Xc=5%, the reverse recovery current would be Irr=0.09xIDC=0.09x260=23.4A. The base . „ 0.6xlnr 0.6x260 n „ r ^ T J ? , . . capacitor is Cs = — = =0.25p.F. If the snubber capacitor is chosen as VLL 6 6 0 ^ , n 2 0 x V „ 20x660 ^ 1 . A . Cs=Cbase, then Rs = Ropt = — = =500. The total energy dissipated in each IDC 260 snubber (energy loss in resistor Rs and the energy stored in the capacitor Cs which is dissipated in the thyristor at the next turn-on of the thyristor) is W=3xCsxVLL2=3x0.25uJFx6602=0.327J. 4.2.2.4. Thyristor Losses The thyristor losses are divided into two portions: the conduction loss and the switching loss. The conduction loss is related to the forward voltage drop across the thyristor and the current forward. Thus conduction 1OSS=VFMXIAV=1.32x87=115W. The switching loss is related to the frequency of switching, the turn-on switching loss, and turn-off switching loss. Supposing that Esw-on=Esw-off=20mJ, then switching loss=Fswx(Esw-on+Esw-off)=60Hzx(2x20mJ)=2.4W. The total power loss would be P=l 15+2.4=117.4W for each thyristor and 117.4x6x2=1410W for the two rectifier bridges. There is a graph in the datasheet that directly provides the same result without any calculation. 47 4.2.2.5. Thyristor Cold Plate Calculations A cold plate is a water-cooled aluminum plate. Supposing that the inlet water be at 25°C and water temperature rise be only 20°C, the outlet water temperature would be T a =25+20=45°C. According to the cold plate datasheets, with the water flow rate of 0.25GPM, the thermal resistance between a four way cold plate and the water is ResA=0.03°C/W. According to the thyristor datasheets, the thermal resistance between the thyristor casing and the cold plate, when thermal compound is applied, is Recs=0.035°C/W and the thermal resistance between the junction and the casing of the thyristor is Rejc=0.17°CAV. Hence Tj=Pdx (ResA+Recs+R8Jc)+Ta=117.4x(0.03+().035+0.17)+45=73oC. A system intended to have high reliability would be designed for a worst-case junction temperature in the semiconductor devices of 20-40°C below 125°C. Otherwise a value of 125 is commonly used in the worst-case design [44]. In this project, 85°C is chosen as the worst case. The failure rate for semiconductor devices doubles for each 10 to 15°C temperature rise above 50°C [44]. On the other hand, thermal fatigue is not an issue when ATj is kept below 30°C [40]. Therefore a very conservative design would be based on the inlet water temperature of 50-30=20°C. Considering the water flow rate of 1.0GPM, the thermal resistance between a four way cold plate and the water is ResA=0.02°C/W and the outlet water temperature would be T a =23.6°C. This means that a forced heat exchanger might be necessary for this design to keep the inlet water below 20°C. 4.2.2.6. Thyristor Gate Drivers For gating of the thyristors, FCOG-1200, which is a twelve-pulse firing board from Applied Power Systems, is used. This board has some special features that include: power-on reset, soft-start and soft-stop, phase loss inhibit, phase reference sensing and gate drive outputs. 48 For starting, the bridge output voltage will be ramped up gradually to charge the DC link capacitor. Under normal circumstances it will be fully on and control of the load current will be through PWM control of the inverter unit. 4.3. D C / A C C o n v e r s i o n The output voltage waveform was decided to be a square wave so no output filter is used. However the current waveform is more of the exponential type due to parasitic inductance at the output circuit. 4.3.1. O u t p u t T r a n s f o r m e r To have 40VR Ms at load (load current lOkA), the output voltage of the single-phase transformer should be about 10kA%(4.14mn+j6.1|iH%co)=47.5yms.<290 (at F=60Hz). This is equivalent to 95Vpeak-Peak since at this point the voltage has a square form. Considering five percent power loss in the transformer, the transformer power rating would be 47.5%10k%1.05=500kVA. The RMS value of the input voltage to the single-phase transformer at full load is about 1685VRMs- The input current to the transformer is around 500k/1685=300ARMs. The transformer turns ratio is 1685/47.5. With reference to the DC-bus nominal voltage (1800VDc) the transformer turns ratio is 1800/51 (-1800/55). The power rating is redefined as 500k(l 800/1685)=534kVA (~550kVA) in case more capacitors be added to the system and there be less voltage drop at the DC-bus. The single-phase output transformer parameters were calculated considering: ZP%=Zs%=4%, SP=550kVA Hence: Zp=Zs=235.64ma 49 The voltage drop was considered to be 1.3% therefore RP=Rs=28.3mQ and at 60Hz, Lp=Ls=295|iH (All the values are referred to the primary side). 4.3.2. L C D C F i l t e r The RMS input current to the inverter is the same as the RMS output current of the inverter. Thus the filter output current is 300AR Ms. Considering the energy balance between the energy stored in the inductances of the circuit after the filter and the filter capacitor: W=-LI2 = 4 1 7 / = - C A V 2 >C = 25750uF 2 2 This calculation is done with the assumption of a 10% voltage drop across the capacitor when it is discharged. In practice, this capacitor consists of several smaller capacitors in parallel thus the capacitor was defined as C=30000uF for redundancy. To bring down the filter losses at full load and reduce the voltage drop across the filter, a tuned high pass filter was designed first (Figure 4.7.). Here T=If/Vf. The first harmonic is at 120Hz so for the filter, Fmax=12()Hz and with Q=2, F0 = F jl ^T=112.25Hz. Now the V 2 2 resistance and inductance can be calculated: R = —— =95m£2 and L = — \ — =67uH. Adding CcoG u)0 C the damping resistor in series with the capacitor will cause the DC-bus voltage to have more fluctuations. We may need to have some tuned filter units in parallel and our client didn't like the idea of using parallel tuned filters so a conventional low pass filter was designed (Figure 4.8.). Here T=Vo/Vi. Here since the resistor should be in parallel to the output, it dissipates a lot of power. Later, the damping resistor is replaced so that it is in series with the filter inductor. 50 FIGURE 4.7. Tuned high pass filter a) a. Circuit diagram b) b. Frequency response F I G U R E 4.8. Low pass filter V i L , l/YYYV- I Vo a) a. Circuit diagram b) b. Frequency response Now, R-oo thus Q=RC(£)o=o= and uw=C0b and the DC gain is one. To attenuate the 120Hz harmonics, the filter gain should be less than unity at w=120Hz. Since T = a)0 - of thus F 0 <85Hz and L>—^— =117uH. If L=117uH, then at F0=85Hz, the capacitor will u)0 C resonate with the inductor and the impedance of the filter seen from the input will be zero. As we increase the inductance L, F0 will become smaller. If F0 be considered to be one tenth of the first harmonic frequency, F0=120/10=12Hz. This will result in L=5870uH. At this time 51 2 71 = CD, T =0.01 which is 40dB attenuation at 120Hz. A value of L=7000p:H was proved to be a good value by simulation. The other reason to choose this value was to make the input line current ripple around 5% at full load. Also a resistance of 25m£2 was specified to be in series with the filter inductor. This value for the resistance is big enough to damp the oscillations and is small enough so its power loss is acceptable. This resistance is actually the resistance of the inductor itself. Manufacturers can adjust the inductance by changing the air gap of the core and can adjust the resistance by using conductors with different cross sectional area. To define the discharge resistor needed to discharge the capacitor for maintenance, it was supposed that the capacitor be discharged in about t=10s. Therefore 4.3.3. IGBT Inverter Bridge 4.3 .3 .1 . IGBT Protection Against Short Circuits To control fault currents, it may be necessary to dump the DC link (short it by turning on both IGCTs in one leg of the inverter, or even all the inverter IGCTs if this is required to handle the peak current) as well as turning off the rectifier thyristors. A major part of the design exercise is to examine what happens in various fault situations (e.g. shorted output). According to the information received from ABB, to limit the peak currents, which must be turned off, some customers have decided to make the assumption that the unit will not be self-protecting (i.e. without IGCT damage) for short circuits within the power supply enclosure, or within a certain length of busbar outside of the enclosure. This provides some minimum inductance to limit di/dt. W=-CV2 =-2 2 X 1 8 6 5 2 ) = 52173/ . So P=W/t=52173/10=5.2kW and R=V2/P=670a 52 In the event of a short circuit, once the emitter bonding wires have fused open inside the module, arcing is likely to start. The high temperature of the arc can expand the silicon gel inside the module and cause the case to explode. Such explosions are not uncommon. Even with fusing, a ruptured case is still a real possibility. 4.3.3.2. I G B T Se lec t i on For the proper selection of an IGBT, the peak collector current during operation including any required overload current must be less than twice the rated current [40]. The maximum value of the output current is: 47.5V/4.15mQ=11.4kAPEAK- So the peak current passing through the IGBTs would be 11.4kA%47.5V/1685V=321 APEAK- Considering 20% for ripple current, the required nameplate current would be 321%1.20%2=770A. From the voltage point of view, the maximum off state collector-emitter voltage should be around one and half times the DC-bus voltage [40]. Thus Considering 20% for ripple voltage 1865%1.20%1.50=3350V. Our client was interested in using an IGBT module with the highest available power rating. He also wanted to put two of them in parallel to have some practical experiences with those very high power devices specially how they share the load between them. So CM1200HB-66H from Mitsubishi with IC=1200A and VCEs=3300V was chosen. The total turn-on time for this device is about 3.60p:s and the total turn-off time is about 3.50(xs. 4.3.3.3. I G B T Losses The IGBT losses are divided into two portions: the conduction loss and the switching loss [40]. 53 The conduction loss is then divided into two portions. One part is related to the collector-emitter saturation voltage and the collector current and the other part is related to the conduction loss in the flywheel diode. Suppose the average diode current be one tenth of the RMS current (a very conservative assumption) then Idiode-Av=300/10=30A. Thus conduction 1OSS=VCE-SATXIC-AV+ VFMXldiode-Av=5x300+3.64x30=1525+110=1635W. The switching loss is related to the frequency, of turn on and off and the turn-on switching loss and turn-off switching loss. Suppose Esw-on=Esw-off=100mJ/pulse, switching loss=Fswx(Esw-on+Esw-off)=600Hzx(2xl00mJ/pulse)=120W. The turn-on loss includes the losses caused by the hard recovery of the opposite free-wheel diode. The total power loss would be P=1635+120=1755W for each IGBT and 1755x4=7020W for the inverter bridge. Since two devices are going to be put in parallel, the power loss of each device would be 1755/2=877.5W. 4.3.3.4. I G B T C o l d P l a t e C a l c u l a t i o n s According to the datasheets, the thermal resistance between the IGBT casing and the cold plate, when thermal compound is applied, is Recs=0.006°C/W, the thermal resistance between the IGBT junction and the casing is RejcQ=0.008°C/W, the thermal resistance between the FWD junction and the casing is RBJCR=0.016°C/W, and the thermal resistance between a four way cold plate and the water is ResA=0.03°C/W at the water flow rate of 0.25GPM. The following calculation is done for each device based on the fact that two devices are in parallel. Suppose that the switching loss of the IGBT be the same as the FWD. So PdQ= 1525 120 2 2x2 + =85W. 54 Hence Tc=(PdQ+PdR)x(ResA+Recs)+Ta=(795+85)x(0.03+0.006)+45=77oC. The IGBT junction temperature TjQ=PdQxRejcQ+Tc=795x0.008+77=83.5oC and the FWD junction temperature is TjR=P dRxRejCR+Tc=85xO.016+77=78.5°C. So the junctions' temperatures are less than 85°C in this project. Calculation for the conservative design (based on the inlet water temperature of 20°C, ATj Q =30°C and the water flow rate of 1.0GPM), would result in: Tc=TjQ-PdQxRejcQ= 50-795x0.008=43.64°C and T a=T c-(P dQ+P dR)x(ResA+Recs)=43.64-(795+85)x(0.02+0.006)=20.76°C. This means that a forced heat exchanger might be necessary for this design to keep the inlet water well below 20°C. 4.3.3.5. I G B T D r i v e r s These IGBTs have extra terminals for Out of Saturation Short Circuit Detection. As the short circuit current, which would be higher than the rated current, passes through the device the voltage drop across the device will increase (device exhibits a transistor mode operation characteristics). These terminals could be connected to the gate drive circuit and the gate signal could be turned off. It is recommended to reduce the gate voltage either in steps or by a ramp so that the short circuit current is reduced and its di/dt is also reduced as the IGBT turns off. In this project, APS-1318 HVIGBT gate driver boards are used. They include HFBR-1524/2524 fiber optic terminals, DC/DC isolated converter and M57959L and Darlington power transistors. Isolated power supplies are required for high side gate drivers because the emitter potential of high side IGBTs is constantly changing [40]. M57959L is a hybrid integrated circuit designed for driving n-channel IGBT modules in any gate amplifier application. This device operates as an isolation amplifier for these modules and provides the 55 required electrical isolation between the input and output with an optocoupler. Short circuit protection is provided by a built in desaturation detector. A fault signal is provided if the short circuit protection is activated. IGBTs were tested in the factory before the shipment and the test results were included in the Shipping Inspection Report. The most important parameter is VCE that shows the mismatch between the switch pairs. V C E of the modules that was received are: 4.072, 4.117, 3.978, 3.989, 4.074, 4.014, 4.095V. Thus the worst mismatch between the modules in a pah-would be 0.058V. After the devices were arrived, they were tested by running them in parallel. The test was carried out using the driver boards and the fiber optic links. When the supply voltage to a driver board is increased, the current drawn by the board increases softly. Around 3.0V the current is around 0.5A and a negative voltage appears at the Gate terminal. From this point on, the current drawn increases aggressively and around 3.5V, the current is about 1.5A and both positive and negative voltages appear at the Gate terminal (suppose we have an input to the optocoupler). After that as the voltage increases, the current decreases softly and at 15V, current is 0.25A. When the power is turned on to a driver board, if the voltage were set at 15V and the current be limited at 0.25A, the driver will not start working. If the voltage were decreased from 15V, the same sequence would be seen backwards. Therefore, when the power is disconnected, first the positive section of the output disappears and then the negative part, providing a safe turn off for the IGBTs. 4.3.3.6. B u s B a r s 4 .3 .3 .6 .1 . T y p e s o f B u s B a r s There are basically three types of bus bars: single conductor, laminated multiconductor and planar. 56 The simplest type is the single-conductor bus bar. It is used for high-current applications and when low voltage drop is a prime requirement. Its general construction is also simple. The laminated multilayer bus bar is a widely used design offering the most advantages. Its construction is of alternate layers of rectangular copper stock and dielectric. The exposed edges are often sealed by an epoxy resin. Because it is of multiconductor design, it can handle mixed power levels with integral ground returns. The flat, stacked, laminar configuration also provides a built-in capacitance for power filtering. The planar type bus bar is basically a flexible circuit having thicker and wider conductors such as in the form of conventional ground planes. These are spaced side-by-side and enclosed within an insulating film of polyester or polyimide. 4.3.3.6.2. L a m i n a t e d B u s B a r In this project laminated busbars are used to provide low-inductance connections to individual IGBT modules and to the DC capacitor bank. According to the manufacturer catalogue, the resistance, inductance and capacitance of the laminated busbar over the IGBTs can be calculated as follows. Suppose the length of the bus bar be l=0.65m=26" and the width of the bus bar be w=30cm=12"=12000mils. If copper alloy #110 be used as the conductor material with a thickness of t=2.5mm=100mils and with a conductor resistivity of p=8.09O/sqmil/ft and Mylar be used as the insulation material with a thickness of d=5mils and with a dielectric constant of K=3A, and the number of layers N=3, then: r = £- = = e.lAu.Q.1 ft = 22AluD.Im -> R = 22.12x0.65 = UAu£l for each layer. wt 12000x100 ^ J ^ <~ 57 „ 0.225^(^-1) 0.225x3.4x(12x26) x(3-1) n c c „ C = = = 95.5pF T 0.385ri/ 0.385x5x26 . „ r r w 12 4.4. P o w e r C o m p o n e n t s L i s t The list of the power components with their specifications is provided in Table 4.2. These values were used for the PSIM simulation. The transformer values are referred to the primary side. The values for bus bars were calculated with the assumption of using all solid bars. Later to be able to eliminate the IGBT snubbers, it was decided to use laminated busbars over the capacitors and the IGBTs, which have much less inductance and resistance than what are identified in Table 4.2. T A B L E 4.2. Component specifications as were used for the PSIM simulation I t e m S p e c i f i c a t i o n I t em S p e c i f i c a t i o n 3-ph trans. 500kVA, 600/660/660V, A / Y / A RP=RS=RT=4.7mQ LP=Ls=LT=36.lM.H RL-in 740uX2, 16.2uH RL-ac-in-cable 250uA 1.3UH RL-dc-busl 280M.Q, L3u.FI 1-ph trans. 550kVA, 1800/55V Rp=Rs=28.3mQ LP=Ls=295(lH RL-dc-bus2 280uI2, 1.3uH RL-ac-bus 70[iQ, 1.1 uH RL-cable/bar 140ui2, 4.3U.H Thyristors 1980V, 130A L-electrode/furnace 1.8|iH IGBTs 3350V, 770A Cfilter 30000U.F, 1900VD C Lfilter 7000uH, 25ma 260AD C 58 4.5. P S I M S i m u l a t i o n Simulation studies of the proposed inverter were carried out by PSIM, which provided a good result. Resistive loads were chosen and the output voltage and currents, DC-bus voltage and currents were checked out. All the simulations are done using the components in Table 4.2. Figures 4.9. to 4.12. are the typical waveforms with a load of a fraction of the full load (In the case shown, the duty cycle of the switching frequency is 0.5) and Figures 4.13. to 4.16. are the full load waveforms. Figures 4.17. to 4.22. are the results for a short circuit at the load, after the output transformer and before the output transformer and Figures 4.23. and 4.24. are the results for an open circuit after or before the output transformer. The short circuit and open circuit are done at t=550ms and the initial condition is the steady state full load condition. In all cases, it was supposed that the input rectifiers are always fully on and there is no feedback to the inverter controller. The results are discussed in more detail in the Protection section. 59 F I G U R E 4.9. Simulation results for the load current (upper) and the inverter output voltage (lower) waveforms at a fraction of full load 320.00 Time (mj) F I G U R E 4.10. Simulation results for the DC-bus voltage after the filter (upper) and before the filter (lower) waveforms at a fraction of full load W N Y W VVVV\!W 52D.00 "Time (ms) 60 FIGURE 4.11. Simulation results for the filter capacitor current (upper) and the input current (lower) waveforms at a fraction of full load F I G U R E 4.12. Simulation results for the IGBT (upper) and diode (lower) (in the same module) current waveforms at a fraction of full load 500.00 400.00 200.00 0.00 •200.00 400.00 200.00 0.00 •200.00 •400 00 •600.00 I 61 FIGURE 4.13. Simulation results for the load current (upper) and the inverter output voltage (lower) waveforms at full load F I G U R E 4.14. Simulation results for the DC-bus voltage after the filter (upper) and before the filter (lower) waveforms at full load \*Jc-bus2 2.DDK j 1 1 i — I.90K -J- ! r I.TDK i.eoK I.S0K Ntic-busl i 6DO.DD 5I0.DD 62D.OO 53D.DD 6*110 Time (ms) 62 F I G U R E 4.15. Simulation results for the filter capacitor current (upper) and the input current (lower) waveforms at full load FIGURE 4.16. Simulation results for the IGBT (upper) and diode (lower) (in the same module) current waveforms at full load 520.00 Time (ms) 63 F I G U R E 4.17. Simulation results for the DC-bus voltage after the filter (upper) and before the filter (lower) waveforms with short circuit at the load FIGURE 4.18. Simulation results for the short circuit current (upper) and the input current (lower) waveforms with short circuit at the load h fl h--J\ J • ,~S\ A A A A A A A A A A A A A A V v V r ^ V \f \f, V V / V v V V V v \r X? V v —-v — \ i v y- i | D.70 Time (s) 64 FIGURE 4.19. Simulation results for the DC-bus voltage after the filter (upper) and before the filter (lower) waveforms with short circuit after the 1-ph transformer 65 F I G U R E 4.21. Simulation results for the DC-bus voltage after the filter (upper) and before the filter (lower) waveforms with short circuit with short circuit before the 1-ph transformer " * > i l t a r t t D.eo Tim* (t) F I G U R E 4.22. Simulation results for the short circuit current (upper) and the input current (lower) waveforms with short circuit before the 1-ph transformer 66 F I G U R E 4.23. Simulation results for the DC-bus voltage after the filter (upper) and before the filter (lower) waveforms with the open circuit after the 1-ph transformer FIGURE 4.24. Simulation results for the short circuit current (upper) and the input current (lower) waveforms with the open circuit after the 1-ph transformer 67 4.6. P r o t e c t i o n s The system is conservatively designed, with as many fail-safe features as possible. Internal hardware protections override the software control in emergency situations. Input three-phase circuit breaker with overload and over current protection is also installed. This circuit breaker could be equipped with remote on/off push buttons. Current signals are derived using Hall effect sensors and the output impedance of the unit is sufficient to allow for a current mode control into a bolted short circuit at the output transformer terminals. To protect the IGBTs in different cases of abnormality, signals from under voltage detection circuit, cross conduction detection circuit, peak current detection circuit and desaturation detection circuit are used to inhibit all the gating. Also an emergency shutdown push button would inhibit the gating signals as well. When a short circuit occurs at the output terminals of the 1-phase transformer, the inductance seen from the input side would be 2xl25.7u.H=251.4uH and the worst-case rate of current change at the input side would be di/dt=VDc/L=1800/251.4u.=7.16A/|is. This is very small compared to the di/dt capability of the switches and also shows that we can easily limit the current at a predefined level. If it were supposed that all the energy for the short circuit would be provided by the capacitor, the worst-case maximum short circuit current at the input side of the 1-phase transformer would be: W = -CV2 = 48600/ = —LI2 >I = 19.718M. F 2 2 From the simulation results, it can be seen that in some cases, the short circuit current is so high that there may not be any way to protect the IGBTs and the devices in the enclosure should be considered as if it is not self-protecting. There are some ways to minimize the damage or even eliminate it, especially in the case of open circuit, which results the DC-bus voltage be increased abnormally. While putting a pure resistor across the capacitor will cut the energy stored in it [17], a better way is to phase-68 back the input rectifiers and decrease the energy stored in the capacitor by feeding it back to the input system. This requires that a closed loop control system be employed for the rectifier bridges as well [55], [57]. 4.7. C o m m u n i c a t i o n s Communication with the control module under the anticipated noisy conditions is best done optically. Some simple controls and status indicators would be provided on the cabinet, with an infrared link to the computer providing more extensive two-way communication. To minimize the effect of the radiated switching noise, the fiber optic links were used between the IGBT gate driver circuit and the controller board. For the connection between the current sensors and the control board, shielded/twisted wires are used 4.8. C o o l i n g The power losses of the magnetic devices were estimated by the manufacturers as is indicated in Table 4.3. To calculate the total power loss in the system, we need to calculate the power losses in the capacitor and the output conductor as well. T A B L E 4.3. Losses in the system Each device No. of devices Total for the devices 3-ph transformer 5.5kW 1 5.5kW THYs 117.4W 12 1410W Inductor 1625W 1 1625W Capacitor 0.4W 4 Negligible IGBTs 877.5W 8 7020W 1-ph transformer 16kW 1 16kW Output conductor 1820W/m 8m 13.6kW Total 45.2kW 69 To calculate the ripple current through the capacitor, consider that all the DC current from the rectifiers go only through the inverter and all the ripple current of the inverter be only provided by the filter capacitor. The inverter ripple current could be calculated by: RMST0TAL = JDCAVE2 + RMSRIPPLE thus the ripple current is 160ARMs at full load. This assumption is not that accurate and the simulation shows that the RMS current through the capacitor is 189A at full load. Four capacitors are in parallel and the series resistance of each capacitor is about 0.25mQ so the power loss would be 0.4W. The conductor between the output transformer and the furnace is also water-cooled. It was decided to use the existing conductor so the power loss is: p=RI2=18.2(u,fl/m)x(10kA)2x7.5(m)=13.6kW. In the system the overall efficiency is around 90% and the losses in the system is around 45kW, and about 8.5kW must be extracted from the solid-state devices by the cooling system. This would be done using a closed loop water system, possibly with a remote heat exchanger. Over-temperature detection will be provided directly on the device heat sinks. 4.9. M i c r o p r o c e s s o r B o a r d s Gating of the phase-controlled bridges with digital circuits is implemented using a large number of integrated circuits or a microprocessor. Typically, the methods using microprocessors rely on different proportions of hardware and software. The software solutions have the disadvantage of limiting the timing precision of the gating pulses [49]. On the other hand hardware solutions lead to increased inflexibility and to an increased chip count [50], [56]. However, with the recent introduction of low cost micro controllers with integrated special hardware timing capabilities, many limitations of the hardware have been overcome [49]. 70 In this project, the control of the inverter bridge is achieved by using a microprocessor and the software will be designed to achieve various protection objectives. The production of the signals in software will provide added flexibility for the future improvements. Several types of microprocessors and DSPs were investigated. Most of the models that had enough AID and input/output ports on board were suitable for this purpose. At the end the existing 80C196KB microprocessor, which is widely used in industry, was chosen. 4.9.1. 80C196KB The MCS-96 class members are all high performance micro controllers with a 16-bit CPU and at least 230 bytes of on chip RAM. They can handle high-speed calculations and fast input/output operations. Typical applications using the MCS-96 products include closed loop control and mid-range digital signal processing. One of the CHMOS type members of the MCS-96 family is the 80C196KB. All of the MCS-96 components have the same instruction set and architecture. However, the CHMOS components have enhancements to provide higher performance with lower power consumption since idle and power-down modes are available on these devices. The 80C196KB has also an I/O subsystem and can perform 16-bit arithmetic instructions including multiply and divide operations [52]. 4.9.2. EV80C196KB The EV80C196KB is designed to be a software evaluation tool for the ROMless 80C196KB 16-bit micro controller. The EV80C196KB micro controller evaluation board is delivered with an 80C196KB, 8K-words and 8K-bytes of user code/data memory, a UART for host communications and analog-input filtering with a precision voltage reference. Also included is programmable chip-select, bus-width and wait-state-counter logic, which allows to 71 custom tailor the board. The board's physical dimensions are 61/£"x7%" with an overall height of 3/4". There are six main sections to the EV80CT96KB board: Processor, Memory, Host Interface, Digital I/O, Analog Inputs and Decoding [48]. The evaluation is discussed in more details in Appendix B. 4.10. Controller Schemes Two method of controlling the output voltage were proposed and investigated. The hystersis method uses a table to decide how much and how fast the output voltage is changing while the PI controller uses the conventional phase and gain margin concepts to decide the characteristics of the output voltage. At the end, the hystersis method was implemented and used as the controller because of the simplicity and the fact that it can limit the maximum current level. 4.10.1. PI Controller Since the system is a very slow one, it can easily be linearized and PI approach be used. Using the current mode control (Figure 4.17.) with an outer voltage loop and an inner current loop has the following advantages: • The system has built in short circuit protection. • For the outer voltage loop, the inner current loop transfer function could be simplified to a gain factor since the inner current loop is much faster than the outer voltage loop. It is so, to let the inner current loop to follow I r e f resulted form the outer voltage loop. If the outer loop were faster, it will change the reference for the inner loop before the inner loop reaches it. 72 In this project, since a capacitor is present before the inverter, the output of the inverter is of the voltage type and it is controllable via changing the PWM pattern. It is a VSI configuration so an inductor should be present at the output of the inverter. Suppose the output voltage needs to be regulated. According to the output voltage, the inductor (which is at the output of the inverter) current is adjusted and according to the inductor current the inverter output voltage is adjusted, in other word, the PWM pattern is adjusted. So the current controller should be the inner loop and the voltage controller should be the outer loop. 4.10.2. Hystersis controller To keep the switching frequency fixed at 600Hz, constant-frequency control with turn-on at clock time is employed. The RMS output current determines the turn-off time. 4.10.2.1. Determining Change of switching_on_time The actual_current is measured and compared with the referencecurrent. Also changes in the error current are calculated as well: error_current=reference_current - actualcurrent delta error current=error current new - error current old FIGURE 4.25. Current mode control with two control loops Re f . C u r r e n t T o u t 73 The results, error_current and delta_error_current, are used to determine delta_switching_on_time (change of switching_on_time) according to a 5x5 table as in Table 4.4. The load type is of heating nature so the process is a very slow one. T A B L E 4.4. Determining change of switching_on_time delta_on_time ((is) error_current — - 0 + + + delta_erro r_current — -25 -5 -1 0 0 — -5 -1 0 0 +1 0 -5 -1 0 +1 +5 + -1 0 0 +1 +5 + + 0 0 +1 +5 +25 4.10.2.2. Flowchart The flowcharts for different subroutines are provided in Figures 4.18. to 4.24. Figure 4.18. shows the general relationship between the different blocks of the code. For simphcity, the sw_on_sub flowchart is shown for a 3x3 table. The software was written in assembly language and is included in Appendix C. First ini_sub is called for the initialization purposes. Then the hso_sub is called for the first time to force the operations to start at the specific times. The program will wait until a software timer interrupt is happened. Then based on that, soft_timer_ISR will start A/D conversion, will call io_sub or will call hso_sub, which will loop the operations. When A/D conversion of the input signals are completed, ad_done_ISR will call the sw_on_sub to calculate the on-time for the switches based on the hystersis table. The on-time will be used by hso_sub to set the time for the execution of the software timer interrupts. On the other hand if the external interrupt happens, a flag will be set and the io_sub is called to set/clear the gating of the switches for the current mode state. 74 FIGURE 4.26. General flowchart for the code ini_sub hso_sub external_int softJimerJSR • io_sub * ad_done_ISR • sw_on_sub FIGURE 4.27. Subroutine flowchart for ad_done_ISR pusha ad2 popa ret F I G U R E 4.28. Subroutine flowchart for external_int pusha ei2=1 popa call io_sub ret 75 F I G U R E 4.29. Subroutine flowchart for hso subroutine hh8 N *_ sw_on_adj=sw_on tt2(new)=tt2(old)+sw_priod • soft_timer2 ISR When: timerl =tt2(new) • softJimerO ISR When: timerl =tt2(new)+sw_delay & sw_on_adj=2*sw_on soft_timer3 ISR When: timerl =tt2(new)+s w_on_adj hh1 ret. F I G U R E 4.30. Subroutine flowchart for io subroutine ioportl ,ioport1_image ret 76 FIGURE 4.31. Subroutine flowchart for sw_on_subroutine del_sw_on=table row[col] i_err_old=i_error sw on=sw_on+del_sw_on N 77 FIGURE 4.32. Subroutine flowchart for soft_timer_ISR 4.10.2.3. Emergency Shutdown The external interrupt input can be used for either "current mode" or "software emergency shutdown", since there is only one external interrupt available on the board. In case of "current mode", the external interrupt routine 1 should be chosen and the shutdown process will be provided by the hardware. In case of "software emergency shutdown", external interrupt routine 2 should be chosen. Routine 1 turns off only the two upper switches for the remaining time of the half period, while routine 2 turns off all the switches and a blinking pattern is displayed on the Port 1 LED (on the board) and on an external LED. In both cases, jumpers S3 and S4 on the control circuit, should be selected accordingly (refer to Figure 4.29. and 4.31.). 78 4.10.2.4. Controller Board Pin Connections External connections to the connector JP1 of the controller board should be as in Table 4.5. T A B L E 4.5. Controller board JP1 pin connections JP1 pin# Connection JP1 pin# Connection 5 Analog ground (AGND) 11 Analog ground (AGND) 6 Reference current (ACH1) 12 Actual current (ACH3) External connections to the connector JP2 of the controller board should be as in Table 4.6. T A B L E 4.6. Controller board JP2 pin connections JP2 pin # Connection JP2 pin # Connection 3,5,7,9, 11,21,49 Digital ground (DGND) 10 Gating, switch #4 (PI.4) 4 Gating, switch #1 (Pl.l) 12 External L E D (PI.5) 6 Gating, switch #2 (PI.2) 22 Emergency shutdown (P2.2/Extint) 8 Gating, switch #3 (PI.3) 50 +5V output (+5Vcc) Pin 22 of JP2 should be held at LOW logic level for normal operation and go to HI logic level in case of an emergency. If a push button is used for this purpose, pin 22 of JP2 should be connected to pin 50 of JP2 via the push button in case of an emergency. In this case, also pin 22 of JP2 should always be connected to pin 1 of JP2 by a IKQ. resistor. 4.11. Monitoring D A Q boards were needed for monitoring voltages and currents at various points of the power circuit. Although there were enough resources in the microprocessor board for this 79 purpose, it was decided that another board be used for monitoring purposes so the two systems would be completely independent. 4.11.1. The DAQ-801 First the existing board DAQ-801 from Quatech was investigated. It is a low cost data acquisition board with 12-bit resolution, eight unipolar or bipolar analog input channels, two analog output channels, 32 digital I/O channels, and three 16-bit programmable counter/timers. The maximum sampling rate is 40kS/s for A/D with internal or external triggering. The DAQ-801 provides programmable gains of 1, 10, 100, and 1000 and has auto zeroing and a self-calibrating facility for A/D conversion. The monitoring program can be written in C++. A sample C++ program that was used with DAQ-801 is included in Appendix D. It was found that it couldn't be programmed for continues data acquisition and several program tricks were implemented to resemble a circular buffer but the board didn't respond well enough Thus a new DAQ board was purchased. 4.11.2. 6023E The 6023E is one of the lowest cost families of devices that use E Series technology to deliver high performance and reliable data acquisition capabilities in a wide range of applications. One can get up to 200 kS/s, 12-bit performance on 16 single-ended analog inputs. Depending on the type of the hard drive, these devices can stream to disk at rates up to 200 kS/s. These E Series devices feature digital triggering capability, as well as two 24-bit, 20 MHz counter/timers; and 8 digital I/O lines. The 6024E and 6025E also feature two 12-bit analog outputs. 80 4.11.2.1. LabVIEW LabVIEW (Laboratory Virtual Instrument Engineering Workbench) is a development environment based on the graphical programming language G. LabVIEW is integrated fully for communication with hardware such as GPIB, RS-232, and plug-in data acquisition boards. Using LabVIEW, one can create 32-bit compiled programs that give fast execution speeds. One also can create stand-alone executables because LabVIEW is a true 32-bit compiler. All LabVIEW programs, or virtual instruments (Vis), have a front panel and a block diagram. The front panel is the graphical user interface of the LabVIEW VI. This interface collects user input and displays program output. The front panel can contain knobs, push buttons, graphs, and other controls and indicators. The block diagram contains the graphical source code of the VI. It consists of nodes such as Vis, structures, and terminals from the front panel. These nodes are connected by wires, which define the flow of data through the program. LabVIEW Vis follow a dataflow model for program execution. The execution of a node occurs when all its inputs are available. 4.11.2.2. LabVIEW Block Diagram And Front Panel Figure 4.25. shows the front panel of the LabVIEW program and Figure 4.26. shows the block diagram that was designed for this project. First, the output text file is opened or created and then the DAQ board is initialized and configured. Then the board starts sampling the defined channels and the data is shown on the screen. When the digital input line goes low, it will stop sampling and reads the previous two-second samples from the buffer and writes them to the hard disk in a correct format. The Scan Rate and the Number Of Seconds To Write To Hard Disk can be selected from the front panel. Other parameters such as the Buffer Size can be changed in the block diagram. The Buffer 81 Size is chosen to be ten times the Scan Rate and the Number Of Scans To Be Shown At A Time is chosen to be five times the Scan Rate. 4.11.2.3. D A Q board Pin Connections External connections to the D-68 connector of the monitor board should be as in Table 4.7. T A B L E 4.7. Monitor board D-68 pin connections D-68 pin # Connection D-68 pin # Connection 14 +5V output 67 Analog ground (ACHOGND) 32 Analog ground (ACH1GND) 68 Actual current (ACHO) 33 Reference current (ACH1) 64 Analog ground (ACH2GND) 52 Emergency shutdown (DIO0) 65 Input Current (ACH2) 53 Digital ground (DGND) Pin 52 should be held at LOW logic level for normal operation and go to HI logic level in case of an emergency. If a push button is used for this purpose, pin 52 should be connected to pin 14 via the push button in case of an emergency. In this case, also pin 52 should always be connected to pin 53 by a 1KX2 resistor. 82 FIGURE 4.33. LabVIEW front panel -101 x|. File Fdil Operate Project Windows Help IC-I^  [ji] |)3plAppk:j>ionFort 2.0i 1JH •2.0-. 16:00:41 1 31/12/03 16:00:41 2 31/12/03 JlOOOO number of scans shown 412000 Out Volt (CH-0) Ref.Vc* (CH 1) number ol the last secounds to write on hard disk 0 1 2 3 4 5 6 7 hi 2T1 FIGURE 4.34. LabVIEW block diagram (continued) SCAPicqcaj^esWabcrnal IntitiulinentsSLabVlrlWW-rfuJaSt^ [Enter File Name j I 'XT it legate or repfacejgl-EH Ichanrel;f Oil ^L..,,,., . ..... 3p M ~ .COWK. 1 aaB. ..„•„ 0—-f> puffer Size] ^cari_i,alg) K^biJAIirivi.lti.i; *• r Ea~j' IScan Rate H°'"»atgl 83 FIGURE 4.34. LabVIEW block diagram (continued) <t> s> -<o op [number ol scans showijIiMj] : llwaveloirn chart! (number of scans to ishow at*time numbet of the last secounds to virile on haid disk 0 FIGURE 4.34. LabVIEW block diagram (continued) 84 4.12. Current Sensors In this project, Hall effect current transducer from L E M is used. L E M transducers are used for the electronic measurement of currents with galvanic isolation between the primary circuit (high power) and the secondary circuit (electronic circuit). They use closed loop (compensated) circuits to have excellent accuracy and very good linearity. The output of the current sensor is of current source type. The load current is very huge and it was decided to sample the inverter output current instead of the load current. At full load the inverter current is 300ARMs- For the current sensor that is used in this project, the conversion ratio is KN=l/5000. Therefore the output current of the current sensor would be IS=IPXKn=300/5000=0.06ARMS and the required resistor to have 200mVRMs voltage drop (maximum R M S input voltage for the R M S - t o - D C converter circuit) would be RM=V/IS=200UI/0.06=3.333£2. The power dissipated in R M is calculated to be P=RMxIs2=3.333x0.062=12mW. 4.13. RMS -to-DC Converter AD636 from Analog Devices is used to measure the R M S value of the output voltage. The AD636 is a low power IC that computes the true root-mean-square of a complex A C (or A C plus DC) input signal and gives an equivalent DC output level. The true R M S value of a waveform is a more useful quantity than the average rectified value since it is a measure of the power in the signal. The only external component required to perform measurements to the fully specified accuracy is the averaging capacitor. The value of this capacitor can be selected for the desired trade off of low frequency accuracy and ripple. The standard connection will show an error for 85 low frequency inputs as a function of the filter capacitor CAV but at higher frequencies the error is also a function of the input signal frequency (Figure 4.27.). F I G U R E 4.35. Typical AD636 output waveform for sinusoidal input ^ IDEAL 6 0 . OCeitROA-E^-eo(IMEAL) AVERAGE Eo - E7 DOUBLE-FREQUENCY •» TIME There are two methods to reduce the ripple. The first method involved using a larger value of CAV- Since the ripple is inversely proportional to CAV, a tenfold increase in this capacitance will affect a tenfold reduction in ripple. When measuring waveforms with low duty cycle, the averaging time constant should be at least ten times the signal period (time constant=25ms per pF). A better method for reducing output ripple is the use of a different filtering method with more external components (Figure 4.28.). Some more external components could be added to improve the accuracy. The trimming process is: • Ground the input signal and adjust "offset" to give zero volts at output. • Connect the desired full-scale input, either DC or calibrated A C signal (1kHz is the optimum frequency), and adjust scale factor to get the correct output. • The remaining errors are due to non-linearity. AD636 is specified for a signal range of OmV to 200mVrms and can work with either single or double voltage supplies. 86 FIGURE 4.36. RMS-to-DC converter shown with optional components and double voltage supply + o-input o_ 1 CAV l u dp 200 o^ vVV— scale f a c t o r AD 63 6 OUtpUt . o_ 0 . l u ' 10k 4. 7u - A A A / — ' 15 4 • 470k 4. 7u " 1 of f se t 500k 0. l u 4.14. The Control circuit The complete control block diagram is shown in Figure 4.29. The circuit diagram for the analog part is shown in Figure 4.30. A gain amplifier is used to match the output voltage of the RMS-to-DC circuit to the input voltage of the A/D converter and a comparator is used to determine if the current level is above a predefined level for the current mode control purposes. Some buffer circuits are included between the various blocks of the circuit to match the voltage/current levels or adjust the offset of the signals. Also three under voltage detection circuits are provided for the three power supply lines. The circuit diagram for the digital part is shown in Figure 4.31. Cross conduction detection circuit would inhibit the gating signals if the software try to turn on these two switches at the same time: • The two switches in the same leg. • The two upper switches. • The two lower switches. 87 The desaturation detection circuit of the IGBT drivers or the manual push button can also inhibit the gating. Some LEDs are provided on the control circuit to indicate the nature of the problem in the event an abnormality has been sensed. The values of the different components used in the control circuit are given in the diagrams. F I G U R E 4.37. Control circuit block diagram JP1.6,, Micro Controller Board (+/-12V, +5V) JP1.5 I JP2.1 r JP2.4 JP2.6 JP2.B JP2.10 UP2.22 -a* -S4 Monitor Board 671 53 TTT ffl 5V Refrence Current T1. C M Out Buffer, Cross Cond., Driver & Opt Coupler (+5V) X Hold & O R (+5V) TTT Current Mode Comparators (+/-15V) TTT Current Sensor (+/-15V) Actual Current • VRm Buffer & Offset Adj. (+/-15 V) Opt Coupler & NOT (+5V) TTT RMS/DC Converter (+/-15V) Input. Output T1-1 (+15V) T2-1 (+15V) Manual Shutdown (+5V) & Under Volt. (+/-15V, +5V) TTT Non-Inverting Amplifier (+/-15V) T3-1 (+15V) T4-1 (+15V) T1-2 T2-2 T3-2 T4-2 (+15V) 88 F I G U R E 4.38. Circuit diagram of the control circuit (analog) Offsac A d j . RS 25k 50% 10 50* Scala Adj 3^  sir Scale A d j . < R17 < 500 50% Bout RI> 1N4148 4 ^ | \Pf U17A -±- i MCd741 J Offsat A d j . -15V R15 10k 40% Raf. Currant T U17D MC4741 R14 650 3= OP4N25 T —E>68.64 > -p6S.< R39 i 25k 50% > Offset A d j . ? ^ 2 in •> 89 F I G U R E 4.39. Circuit diagram of the control circuit (digital) 90 4.15. Mechanical Designs One of the latest steps in the designing of the power supply was the design of the cabinets, busbars and the cold plates (mechanical drawings). Mechanical drawings are included in the Appendix E. Some of the drawings have been revised several times as the components changed over the time. The most important drawing is the one that shows the laminated busbar layout. Other drawings were also prepared to show the details of the cabinets and the cold plates. 4.16. Conclusions According to the specifications given by the client, power components were identified. The realistic models from datasheets and handbooks were used in the simulation. The simulation results showed that the specified components were chosen properly. The power loss in the system was also investigated and the effectiveness of the cooling system was verified. On the other hand, a hysteresis current control scheme was investigated thoroughly and the required software was prepared in Assembly language. The logic circuit was designed so that the hardware would protect the switches in case of the software failure. Moreover, a monitoring program was also prepared and several mechanical drawings were prepared for the laminated busbars, etc. 91 CHAPTER 5 PRACTICAL EXPERIMENTS AND RESULTS 5.1. Introduction Practical studies of the proposed hystersis controller were carried out by an experimental H-bridge inverter at low voltage and current levels in the lab. The actual high power IGBTs were used as the switching devices in the inverter bridge with 30VDC supply voltage. The gating signals were provided to the drivers by means of fiber optic links. The hardware part was built on three pieces of breadboards and the logic circuitry was tested thoroughly under the abnormal situations. The effectiveness of the controller software and hardware were verified by practical experiments in the lab. Several control/hardware modifications were made to meet or exceed the required performance specifications. Loads with the same time constants as the actual system loads were chosen and the reaction of the controller to the changes in the load at different load conditions and DC-bus voltages were tested and the hystersis table was adjusted accordingly. At full load, the time constant of the actual system is 1.512msec thus an 11.6mH inductor (which has an internal resistance of 0.67Q) in series with a 1.0Q. resistor is used for the experiments. Also a twenty-turn winding is used to increase significantly the ampere-turn of the primary current of the current sensor. Thus at full load, the current sensed by the current sensor would be 62.5ARMS which is 156Ap e a k -to-peak-The figures in the following sections are the inverter output currents and voltages of the experimental set-up at different situations. The vertical axis is the normalized peak value 92 (=experiment peak value/nominal peak value) of the signal and the horizontal axis is time in ms. The DC offset seen in the voltage waveforms in the following sections, is due to the current circulating in the load and the two lower switch devices when the upper switch devices are off. The switch devices are very high current IGBTs and the voltage drop across the transistor device is 4V typical (at the rated conditions) and the voltage drop across the FWD device is 2.8V typical (at the rated conditions). 5.2. Half-Load Figures 5.1. and 5.2. are the inverter output current and voltage at half load. At this time the reference current is set at 50 percent and the output RMS current is half of the nominal RMS current. 5.3. Full-Load Figures 5.3. and 5.4. are the inverter output current and voltage at full load. At this time the reference current is set at 100 percent and the output RMS current is equal to the nominal RMS current. 93 F I G U R E 5.1. Inverter output current at half load 1 -• H -1.5 Time (ms) F I G U R E 5.2. Inverter output voltage at half load - 1 - PI - r-| - i n n I—| ) 1 \—1 5 r 1( -ie l_l • \—i 20 25 - -3C _ -Time (ms) 94 FIGURE 5.3. Inverter output current at full load Time (ms) F I G U R E 5.4. Inverter output voltage at full load Time (ms) 95 5.4. Current mode At the time of abnormality, it was supposed to limit the peak current to 125 percent of the peak rated current by means of the current mode control scheme. Three separate experiments were done to simulate the current mode situation. 5.4.1. Shorted resistance at nominal full load In case of the short circuit across the load resistance at nominal full load, the inductance of the circuit, will limit the rate of rise of current. Eventually, the current mode control would activate and would turn off the upper switches for the rest of the half period. On the other hand, the controller will detect the increase in RMS current and will decrease the sw_on time (switch on time) of the switches. This will result in the waveforms shown in Figures 5.5. and 5.6. where the waveforms are governed by both PWM switching and current mode reactions. 5.4.2. Shorted resistance at above nominal full load In case of the short circuit across the load resistance, when the reference current is set above the nominal full load current, the controller might not sense the increase in RMS current and may not decrease the sw_on time (switch on time) of the switches. This will result in the waveforms shown in Figures 5.7. and 5.8. where the waveforms are governed by only the current mode reaction. For this experiment, the reference current is set at 20 percent above the nominal current. 96 FIGURE 5.5. Inverter output current with shorted resistance at nominal full load 1.5 -1.5 J Time (ms) FIGURE 5.6. Inverter output voltage with shorted resistance at nominal full load "~1 -J CI pi iV~l n p. -| ) — LJ 0 -- 5 2 0 5 L -0 -1.5 Time (ms) 97 FIGURE 5.7. Inverter output current with shorted resistance at above nominal full load 1.5 -1.5 Time (ms) FIGURE 5.8. Inverter output voltage with shorted resistance at above nominal full load 1-S I ! -1.5 J Time (ms) 98 5.4.3. Increased DC-bus voltage In case when the reference current is set at nominal full load current and the DC-bus voltage is increased, the controller would react and regulate the output current by PWM switching. If the reference current is set above the nominal full load current while the DC-bus voltage is increased, the controller might not sense the increase in RMS current. This will result in the waveforms shown in Figures 5.9. and 5.10. where the waveforms are governed by only the current mode reaction. For this experiment, the reference current and the DC-bus voltage are set at 20 percent above the nominal value. 5.5. Sudden Changes in The Load Figure 5.11. shows the reaction of the controller when at full load, the resistance of the load is suddenly short-circuited and Figure 5.12. shows the reaction of the controller when the resistance of the load is suddenly backed on. The vertical axis is the normalized RMS value of the actual current and the horizontal axis is time in seconds. In both experiments, sudden change is done at t=1.5s. In case of short circuit at full load, the PWM controller is designed so that it would also detect the current mode signal and will decrease the sw_on time (switching on time) much faster than regular. Thus the controller reaction in Figure 5.11. is faster than in Figure 5.12. 5.6. Conclusion Linear loads with the same time constants as the real loads were chosen and the reaction of the controller to the changes in the load at different load conditions and DC-bus voltage were tested and the hystersis table was adjusted accordingly. Several control/hardware modifications were made to meet or exceed the required performance specifications. 99 FIGURE 5.9. Inverter output current with increased DC-bus voltage at above nominal full load 1.5 T -0.5 Time (ms) FIGURE 5.10. Inverter output voltage with increased DC-bus voltage at above nominal full load Time (ms) 100 F I G U R E 5.11. Changes in actual current when load resistance is shorted at full load 1.25 H 0.75 0.25 H F I G U R E 5.12. Changes in actual current when load resistance is backed at full load 1.25 H 0.75 0.25 101 C H A P T E R 6 O V E R A L L C O N C L U S I O N S A N D F U T U R E P O S S I B I L I T I E S 6.1. O v e r a l l C o n c l u s i o n The conventional supply for an electric resistance-melting furnace consists of a single-phase low voltage source, which is becoming increasingly unacceptable to customers and a method of transforming the load into an effective balanced three-phase equivalent is sought. In this project the objectives were to design, build, and test a 400kW power supply. This is actually a pilot unit for testing in the A M P E L building and the eventual goal of this project is to produce a full size commercial unit at 2.4MW. The specified component verification was confirmed by the simulation results. To extract the dissipated heat from the system, water cooled devices were used. The effectiveness of the cooling system was also verified by calculating the power losses in the system. The inverter portion consists of eight HVIGBTs, two switch in parallel, to study the subject of the paralleling the new devices. Moreover, some mechanical drawings were prepared to show the cubicle and busbar layouts. A micro controller was used as the controller and a separate monitoring system was included. Practical experiments in the lab were carried out to ensure the effectiveness of the controller and the logic circuit and the necessary modifications were made to meet the required performance specifications. The monitoring program was verified by the practical experiments as well. 102 6.2. Future Possibilities The goals for the full version converter include deep studying of some parts of the system, which may consist of: • Optimum inverter PWM pattern. The goal is to draw a smooth current from the DC-bus while not to switch the IGBTs for a short amount of time and also to minimize the harmonics by using a carefully selected PWM pattern. • Integrated process control. This also includes the controlling of the electric motor that adjusts the electrode depth in the furnace. The goal is to have a centralized control block to command and synchronize different parts of the system to have an overall efficient operation during the long periods of running the furnace. • Optimum circuit configuration. By investigating the behavior of the pilot system in the real world, the circuit configuration would be optimized for the full version. The pilot version would help to have a realistic idea of the differences between the theoretical simulations and the practical results at such high power levels. • Advanced monitoring. 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Le-Huy H, Slimani K, Viarouge P (1991) A predictive current controller for synchronous servo drives. Presented at EPE'91, European Conference on Power Electronics Applications, Firenze, Italy. 54. Le-Huy H, Dessaint L (1989) An adaptive current control scheme for PWM synchronous motor drives: Analysis and simulation. IEEE Transactions on Power Electronics 4:486-495. 55. Vincenti PD, Jin H (1996) An optimized single phase A C power supply with DC bus synchronization. IEEE (0-7803-3044-7/96):905-910. 56. Duan y, Jin H (1999) Digital controller design for switchmode power converter. IEEE (0-7803-5160-6/99):967-973. 57. Zhang W, Isaksson AJ, Bkstron A (1998) Analysis on the control principles of the active DC filter in the Lindome converter station of the Konti-Skan H V D C link. IEEE Transactions on Power System 13 (2):374-381. 58. Hurley WG, Wollle WH, Bresliri JG (1998) Optimized transformer design: Inclusive of high-frequency effects. IEEE Transactions on Power Electronics 13 (4):651-659. 107 A P P E N D I X A T E S T S D O N E O N T H E E X I S T I N G T R A N S F O R M E R With the two tap switches installed on the cabinet, different output voltage and currents could be selected as shown in Table A. 1. T A B L E A . l . Old transformer output voltages V o u t (V) l o u t (A) Tap 1 position Tap 2 position 25 10000 1 1 35 7140 3 2 45 5555 4 3 55 4545 5 2 65 3845 5 5 At different tap switch positions the following tests have been done on the old (existing) single-phase transformer: • Insulation test: The insulation of the transformer was tested with a Megger (2mA at 1000V) that proved the insulation was in a good shape (>999M£2). • Capacitance test: The capacitance of the transformer between the primary and the ground and between the primary and the secondary were measured to be 2260pF. • Short circuit and open circuit test with sinusoidal voltage input at a reduced secondary current. • Short circuit and open circuit test with square wave voltage input at a reduced secondary current. Since the short circuit tests were done at a low current level, the effect of the heat produced by the passing current was included by calculation (considering the allowable 108 transformer temperature rise of 115°C). The measured transformer characteristics are graphed in Figure A. 1. Figure A.2. shows the secondary circuit dimensions. This diagram was sent to the client to confirm the value of the conductor inductance. F I G U R E A . l . F I G U R E A.2. Trans, characteristics at different output voltages Secondary circuit dimensions Sacorrfciyarcirtt Dkrensfcxs Rov.O By: MA Das. 109 APPENDIX B EVALUTION BOARD SOFTWARE AND POWER UP B . l . IRISM-IECM Software The EV80C196KB board uses an Embedded Controller Monitor (ECM) written for the MCS-96 family of micro controllers. This monitor supports basic debug facilities (LOAD, GO, STEP etc.) in the user's target system. The E C M is broken into two independent programs, one of these executes in the EV80C196KB (IRISM96KB) and the other executes in an IBM PC or BIOS compatible clone (iECM-96). These two programs communicate via an asynchronous serial channel using a binary protocol defined specifically for this application. The E C M developed for the MCS-96 family makes the assumption that the user interface will always be a personal computer. By making this assumption it is possible to reduce the size and complexity of the code that must be installed in the target system. The term RISM has been coined for this code, which is resident in the target. The term RISM stands for Reduced Instruction Set Monitor and is a takeoff of the term RISC (Reduced Instruction Set Computer) used to describe a class of computer architectures. The RISM consists of about 300 bytes of MCS-96 code, which provide primitive operations. Software running in the host uses the RISM commands to provide a complete user interface to the target system [48]. B.2. Powering Up And Connecting To The PC Power (+5, ±12 Volts) must be connected to JP4 as shown on the board's silkscreen next to JP4. Upon power-up (or after a reset) the board goes through initiahzations and a shifting-pattern is displayed on the Port 1 LEDs when initialization has completed properly. 110 Once the power is applied to the board, PI is needed to be connected to a PC serial port. PI is configured to interface pin-to-pin with a standard ninepin AT-type serial connector. A cable providing all nine signals should be used, as they are all needed for proper operation of the host interface. After connecting the cable, it may be observed that the 80C196KB are held in reset, and all the LEDs turn on. This is because one of the host signals is used to reset the part, and the signal is often in a reset condition prior to invoking the host software on the PC. To invoke the host interface, "C:ECM96 -com2"<CR> should be typed at the DOS prompt and the PC should eventually display the iECM-96 monitor screen. The option "-com2" tells the iECM-96 software that the serial communication port "com2" is to be used [48]. B . 3 . P r o g r a m E x e c u t i o n After writing the code by a text editor, the Assembly Code Generator should be used to convert the text file, to the Intel object format file loadable by iECM-96. Then with the L O A D <filename> command, the content records of the object file <filename> loads into the target memory and any associated symbolic information will also load into a symbol table maintained in the host system's memory. GO command starts execution of the user's code while H A L T command stops the execution by forcing the processor to execute a jump to self instruction in a reserved location. On the other hand, by STEP command, the code can be run step by step. B Y T E <byte_address> command is used to examine and possibly change one or more sequential B Y T E variables and WORD <word_address> command does the same for WORD variables [48]. I l l APPENDIX C ASSEMBLY CODES FOR THE CONTROLLER The program is written in assembly language and is made of about 500 lines. The execution time within one sampling interval is about 20u.s with about 200 lines. All calculations are carried out with 16-bit word length. The two reference and actual currents are sampled and held at every period and the A/D conversion time is about 20(i.s. C . l . The 80C196KB.INC File This file includes the symbols for the register mapped I/O locations: . * * ; * 8 0 C 1 9 6 K B . I N C D e f i n e s y m b o l s f o r t h e r e g i s t e r mapped I / O l o c a t i o n s * . * * z e r o e q u 00H w o r d R/W Z e r o R e g i s t e r a d _ r e s u l t _ l o e q u 02H b y t e R Low b y t e o f r e s u l t a n d c h a n n e l ad_cornmand e q u 02H b y t e W A t o D command r e g i s t e r a d _ r e s u l t _ h i e q u 03H b y t e R H i g h b y t e o f r e s u l t h s i _ m o d e e q u 03H b y t e W C o n t r o l s HSI t r a n s i t i o n d e t e c t o r h s i _ t i m e e q u 04H w o r d R HSI t i m e t a g h s o _ t i m e e q u 04H w o r d W HSO t i m e t a g h s i _ s t a t u s e q u 0 6H b y t e R HSI s t a t u s r e g i s t e r ( r e a d s f i f o ) h s o _ c o m m a n d e q u OSH b y t e W HSO command t a g s b u f e q u 07H b y t e R/W S e r i a l p o r t b u f f e r i n t _ m a s k e q u 08H b y t e R/W I n t e r r u p t mask r e g i s t e r i n t _ p e n d i n g e q u 09H b y t e R/W I n t e r r u p t p e n d i n g r e g i s t e r t i m e r l e q u OAH w o r d R T i m e r l r e g i s t e r w a t c h d o g e q u OAH b y t e W W a t c h d o g t i m e r i o c 2 e q u OBH b y t e W I / O c o n t r o l r e g i s t e r 2 t i m e r 2 e q u OCH w o r d R T i m e r 2 r e g i s t e r i o p o r t O e q u OEH b y t e R I / O P o r t O b a u d _ r a t e e q u OEH b y t e W B a u d r a t e r e g i s t e r i o p o r t l e q u OFH b y t e R/W I / O P o r t l i o p o r t 2 e q u 10H b y t e R/W I / O P o r t 2 s p _ s t a t e q u 11H b y t e R S e r i a l p o r t s t a t u s r e g i s t e r s p _ c o n e q u 11H b y t e W S e r i a l p o r t c o n t r o l r e g i s t e r i n t _ p e n d l e q u 12H b y t e R/W I n t e r r u p t p e n d i n g r e g i s t e r i n t _ m a s k l e q u 13H b y t e R/W I n t e r r u p t m a s k i n g r e g i s t e r w s r e q u 14H b y t e R/W Window s e l e c t r e g i s t e r i o s O e q u 15H b y t e R I / O s t a t u s r e g i s t e r 0 i o c O e q u 15H b y t e W I / O c o n t r o l r e g i s t e r 0 ( H S I / O ) i o s l e q u 16H b y t e R I / O s t a t u s r e g i s t e r 1 i o c l e q u 16H b y t e W I / O c o n t r o l r e g i s t e r 1 ( P o r t 2 ) i o s 2 e q u 17H b y t e R I / O s t a t u s r e g i s t e r 2 p w m _ c o n t r o l e q u 17H b y t e W PWM c o n t r o l r e g i s t e r s p e q u 18H w o r d R/W S y s t e m s t a c k p o i n t e r 112 C.2. The Interrupt Vectors Code Segment (CSEG) The location of the interrupt vectors are predefined as presented below: C S E G A T 2000H dew t i m e r _ o v e r f l o w dew a d _ d o n e dew h s i _ d a t a dew h s o _ e v e n t dew h s i _ z e r o dew s o f t w a r e _ t i m e r dew s e r i a l p o r t dew e x t e r n a l _ i n t dew t r a p dew i n v a l i d _ o p c o d e dew t i dew r i dew h s i _ f i f o dew t i m e r 2 c dew t i m e r 2 o dew e x t e r n a l _ i n t l dew h s i _ f i f o _ f u l l dew n m i C . 3 . The Complete Code The complete code is presented below, same lines respectively. t e s t 2 2 1 m o d u l e m a i n . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * • * * * * * * * * * * $ i n c l u d e ( c : \ i E C M 9 6 \ 8 0 C 1 9 6 K B . i n c ) .••it******************************************** RSEG A T 3 OH r e s e r v e l : dsw 8 t e m p _ t i m e r 2 : dsw 1 s w _ p e r i o d : dsw 1 s w _ o n _ m i n : dsw 1 sw_on_max: dsw 1 s w _ o n : dsw 1 s w _ o n _ a d j : dsw 1 s w _ d e l a y : dsw 1 d e l _ s w _ o n : dsw 1 a d _ i m a g e 2 : dsw 1 i _ r e f : dsw 1 i _ e r r _ o l d : dsw 1 i _ e r r o r : dsw 1 i _ a c t : dsw 1 d e l _ e r r : dsw 1 i _ e r r _ h y s t N : dsw 1 i _ e r r _ h y s t N N : dsw 1 i _ e r r _ h y s t P : dsw 1 i _ e r r _ h y s t P P : dsw 1 d e l _ e r r _ h y s t N : dsw 1 i n t e r r u p t v e c t o r s C o d e SEGment s t a r t s h e r e t i m e r o v e r f l o w A / D c o m p l e t i o n H SI d a t a a v a i l a b l e HSO e v e n t H SI b i t z e r o s o f t w a r e t i m e r s s e r i a l I / O e x t e r n a l i n t e r r u p t s o f t w a r e t r a p u n i m p l e m e n t e d o p c o d e T I R I 4 t h e n t r y i n t o HSI F I F O t i m e r 2 c a p t u r e t i m e r 2 o v e r f l o w e x t e r n a l i n t e r r u p t 1 H SI F I F O f u l l n o n m a s k i n g i n t e r r u p t All commands are described in detail at the ;my p r o j e c t b y M e h d i A l i m a d a d i 85686970 UBC *******************+*+*********************++ ,- i n c l u d e f i l e 8 0 C 1 9 6 K B . i n c , - R e g i s t e r SEGment s t a r t s h e r e (30H=48D) ; r e s e r v e d s p a c e i n RISM ; t e m p o r a r y t i m e r 2 ; s w i t c h i n g p e r i o d (#1D=1 m i c r o s e c ) .•minimum s w i t c h on t i m e .•maximum s w i t c h on t i m e . • s w i t c h i n g o n t i m e ,- a d j u s t e d s w i t c h i n g o n t i m e . • s w i t c h i n g d e l a y ( d e a d t i m e ) . • d e l t a s w i t c h i n g o n t i m e ; c o p y o f a d _ r e s u l t _ l o (word) . • r e f e r e n c e c u r r e n t (#1D=*** A r m s ) ; o l d e r r o r c u r r e n t ; e r r o r c u r r e n t . • a c t u a l c u r r e n t ; d e l t a e r r o r c u r r e n t ; e r r o r c u r r e n t h y s t e r s i s N ; e r r o r c u r r e n t h y s t e r s i s NN ; e r r o r c u r r e n t h y s t e r s i s P ; e r r o r c u r r e n t h y s t e r s i s PP ; d e l t a e r r o r c u r r e n t h y s t e r s i s N 113 d e l _ e r r _ h y s t N N dsw 1 ,- d e l t a e r r o r c u r r e n t h y s t e r s i s NN d e l _ e r r _ h y s t P : dsw 1 ; d e l t a e r r o r c u r r e n t h y s t e r s i s P d e l _ e r r _ h y s t P P dsw 1 ; d e l t a e r r o r c u r r e n t h y s t e r s i s PP k k l : dsw 1 ; t e m p o r a r y c o u n t e r n o _ e i t : dsw 1 ;no e x t e r n a l i n t e r r u p t t i m e c o l : dsw 1 ; c o l u m n number k : d s b 1 ; p u l s e c o u n t e r i o s l _ i m a g e : d s b 1 ; c o p y o f i o s l i o p o r t l _ i m a g e : d s b 1 ; c o p y o f i o p o r t l a d _ i m a g e : d s b 1 ; c o p y o f a d _ r e s u l t _ l o ( b y t e ) e i 2 : d s b 1 ; e x t e r n a l i n t e r r u p t c h e c k s e c _ r o w : d s b 1 ; s e c o u n d row c h e c k n o _ e i 2 : d s b 1 ; n o e x t e r n a l i n t e r r u p t c h e c k . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C S E G dew A T 2002H a d _ d o n e _ I S R ; i n t e r r u p t v e c t o r s C o d e SEGment s t a r t s h e r e ; A / D c o m p l e t i o n i n t e r r u p t s e r v i c e r o u t i n e C S E G dew A T 200AH s o f t _ t i m e r _ I S R ; i n t e r r u p t v e c t o r s C o d e SEGment s t a r t s h e r e ; s o f t w a r e t i m e r s i n t e r r u p t s e r v i c e r o u t i n e C S E G dew A T 200EH e x t e r n a l i n t ; i n t e r r u p t v e c t o r s C o d e SEGment s t a r t s h e r e ; e x t r n a l i n t e r r u p t C S E G I d c a l l l d b d i l d b c l r b e i p u s h a c a l l p o p a A T 2080H s p , # 1 0 0 H i n i _ s u b r o u t i n e i o c 2 , # 1 0 0 1 0 0 0 0 B i n t _ m a s k , # 1 0 1 0 0 0 1 0 B i n t m a s k l h s o _ s u b r o u t i n e u s e r C o d e SEGment s t a r t s h e r e i n i t i a l i z e s t a c k p o i n t e r c a l l i n i _ s u b r o u t i n e c l e a r CAM+A/D c l o c k p r e s c a l a t o r d i s a b l e d i s a b l e i n t e r r u p t s e n a b l e e x t e r n a l , s o f t _ t i m e r , A / D _ d o n e i n t . mask a l l o t h e r i n t e r r u p t s e n a b l e i n t e r r u p t s s a v e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR c a l l h s o s u b r o u t i n e f o r t h e f i r s t t i m e r e s t o r e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR L O O P 1 : s j m p L 0 0 P 1 ; l o o p f o r e v e r , w a i t h e r e f o r i n t e r r u p t . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * i n i _ s u b r o u t i n e : c i r c i r c i r c i r I d I d I d s u b sw_on s w _ o n _ a d j d e l _ s w _ o n a d _ i m a g e 2 s w _ p e r i o d , # 0 6 8 3 H s w _ d e l a y , # 0 A H t e m p _ t i m e r 2 , t i m e r l n o _ e i t , s w _ p e r i o d , # 0 6 4 H ; i n i t i a l i z e s u b r o u t i n e . • a d j u s t e d s w i t c h i n g on t i m e = 0 ; s w i t c h i n g on t ime=0 ; d e l t a s w i t c h i n g on t ime=0 , -copy o f a d _ r e s u l t _ l o = 0 ; s w _ p e r i o d = 1 6 6 7 D ( 1 / 6 0 0 ) ; s w _ d e l a y = 1 0 D ; t e m p _ t i m e r 2 = t i m e r l ; n o _ e i t = s w _ p e r i o d - 1 0 0 D ; I d s w _ o n _ m i n , # 0 0 H I d c o l , # 0 8 H I d s w _ o n _ m i n , T a b l e 5 [ c o l ] s u b s w _ o n _ m a x , s w _ p e r i o d , s w _ o n _ m i n ; I d sw_on_max,# 0 6 0 0 H ; f o r t e s t o n l y , sw_on_min=#00H (maximum ; s w _ o n _ m i n = T a b l e 4 [ c o l : # 0 8 H ] ) ; co l=#8D ; s w _ o n _ m i n = T a b l e 5 [ c o l ] ; s w _ o n _ m a x = s w _ p e r i o d - s w _ o n _ m i n ; f o r t e s t o n l y , sw_on_max=#0600H c i r c i r c i r c i r c i r i _ e r r _ o l d i _ e r r o r i _ a c t i _ r e f d e l e r r o l d e r r o r c u r r e n t = 0 e r r o r c u r r e n t = 0 a c t u a l c u r r e n t = 0 r e f e r e n c e c u r r e n t = 0 d e l t a e r r o r = 0 I d i _ e r r _ h y s t P , # 0 5 H I d i _ e r r _ h y s t N , i _ e r r _ h y s t p n o t i _ e r r _ h y s t N i n c i _ e r r _ h y s t N ; i _ e r r _ h y s t P = + 5D ; i _ e r r _ h y s t N = i _ e r r _ h y s t P ; i _ e r r _ h y s t N = n o t i _ e r r _ h y s t N ; i _ e r r _ h y s t N = i _ e r r _ h y s t N + l I d i _ e r r _ h y s t P P , # 0 1 9 H I d i _ e r r _ h y s t N N , i _ e r r _ h y s t P P n o t i _ e r r _ h y s t N N i n c i _ e r r _ h y s t N N : i _ e r r _ h y s t P P = + 2 5 D r i _ e r r _ h y s t N N = i _ e r r _ h y s t P P r i _ e r r _ h y s t N N = n o t i _ e r r _ h y s t N N r i _ e r r _ h y s t N N = i _ e r r _ h y s t N N + l 114 I d d e l _ e r r _ h y s t P , # O A H I d d e l _ e r r _ h y s t N , d e l _ e r r _ h y s t P n o t d e l _ e r r _ h y s t N i n c d e l _ e r r _ h y s t N d e l _ e r r _ h y s t P = + 1 0 D d e l _ e r r _ h y s t N = d e l _ e r r _ h y s t P d e l _ e r r _ h y s t N = n o t d e l _ e r r _ h y s t N d e l _ e r r _ h y s t N = d e l _ e r r _ h y s t N + l I d I d n o t i n c c l r b c l r b c l r b c l r b l d b c l r b c l r b r e t d e l _ e r r _ h y s t P P , #032H d e l _ e r r _ h y s t N N , d e l _ e r r _ h y s t P P d e l _ e r r _ h y s t N N d e l _ e r r _ h y s t N N i o s l _ i m a g e i o p o r t l _ i m a g e a d _ i m a g e c o l , # 0 4 H e i 2 s e c row d e l _ e r r _ h y s t P P = + 5 0 D d e l _ e r r _ h y s t N N = d e l _ e r r _ h y s t P P d e l _ e r r _ h y s t N N = n o t d e l _ e r r _ h y s t N N de l _ e r r _ h y s tNN=de l _ e r r _ h y s tNN+1 k=0 i o s l _ i m a g e = 0 i o p o r t l _ i m a g e = 0 ad_ image=0 c o l = 4 D e i 2 = 0 D sec_row=0D ; r e t u r n f r o m s u b r o u t i n e t a b l e O : dcW t a b l e l : dcW #0H #2H #4H 0 F F E 7 H , O F F F B H , O F F F F H 00000H, 00000H ;<<< c o l u m n # ; r o w #0 ( d e l _ s w _ o n ( u s ) ) ; r o w #1 t a b l e 2 : dew t a b l e 3 : dew O F F F B H , O F F F F H , 00000H 00000H, 00001H ; r o w #2 ; r o w # 3 t a b l e 4 : dcW t a b l e 5 : dcW O F F F B H , O F F F F H , 00000H 00001H, 00005H ,-row #4 ; r o w # 5 t a b l e 6 : dcW t a b l e 7 : dcW O F F F F H , OO0O0H, 00000H 00001H, 00005H ; r o w # 6 ,-row #7 t a b l e 8 : dew t a b l e 9 : dew 00000H, 00000H, 00001H 00005H, 00019H ; r o w #8 ; r o w # 9 h s o _ s u b r o u t i n e : a d d t e m p _ t i m e r 2 , s w _ p e r i o d ; h s o s u b r o u t i n e ; t e m p _ t i m e r 2 = t e m p _ t i m e r 2 + s w _ p e r i o d l d b I d n o p n o p n o p n o p h s o _ c o m m a n d , # 0 0 0 1 1 0 1 0 B h s o _ t i m e , t e m p _ t i m e r 2 , - g e n e r a t e s o f t w a r e t i m e r 2 i n t e r r u p t when: ; t i m e r l = t e m p _ t i m e r 2 = t e m p _ t i m e r 2 + s w _ p e r i o d ,-no o p e r a t i o n ; n o o p e r a t i o n ,-no o p e r a t i o n ;no o p e r a t i o n hh77 : hh33 : h h 8 8 : h h 7 : cmpb j n e s jmp cmpb j n e l d b a d d n o p n o p n o p n o p cmpb j n e ; l d b s jmp cmpb j n e ; l d b k, #09H hh77 hh33 k, #04H hh88 hso_command ,#00011001B h s o _ t i m e , t e m p _ t i m e r 2 , n o _ e i t k , #00H hh7 s w _ o n , s w _ o n _ f d _ h i hh3 k, #05H hh8 s w _ o n , s w _ o n _ f d _ l o c o m p a r e k w i t h #9D ( i f n o t e q u a l ) jump hh77 ( i f e q u a l ) j ump t o hh3 3 ( i f n o t e q u a l ) c o m p a r e k w i t h #4D ( i f n o t e q u a l ) ( i f n o t e q u a l ) jump t o hh88 ( i f e q u a l ) g e n . s o f t w a r e t i m e r l i n t . when: ( i f e q u a l ) t i m e r l = t e m p _ t i m e r 2 + n o _ e i t ( i f e q u a l ) no o p e r a t i o n ( i f e q u a l ) no o p e r a t i o n ( i f e q u a l ) no o p e r a t i o n ( i f e q u a l ) no o p e r a t i o n c o m p a r e k w i t h #0D ( i f n o t e q u a l ) jump hh7 ( i f e q u a l ) s w _ o n = s w _ o n _ f d _ h i ( i f e q u a l ) jump t o hh3 ( i f n o t e q u a l ) c o m p a r e k w i t h #5D ( i f n o t e q u a l ) ( i f n o t e q u a l ) jump t o hh.8 ( i f n o t e q u a l ) ( i f e q u l ) s w _ o n = s w _ o n _ f d _ l o hh3 : l d b a d d n o p n o p n o p h s o _ c o m m a n d , # 0 0 0 1 1 0 0 0 B h s o _ t i m e , t e m p _ t i r a e r 2 , s w _ d e l a y ( i f e q u a l ) g e n . s o f t w a r e t i m e r O i n t . when: ( i f e q u a l ) t i m e r l = t e m p _ t i m e r 2 + s w _ d e l a y ( i f e q u a l ) no o p e r a t i o n ( i f e q u a l ) no o p e r a t i o n ( i f e q u a l ) no o p e r a t i o n 115 hb.8: hh2 : h h l : n o p s h l s jmp I d cmp j g e l d b a d d n o p n o p n o p n o p r e t s w _ o n _ a d j , # 01H hh2 s w _ o n _ a d j , s w _ o n s w _ o n _ a d j , s w _ o n _ m a x h h l h so_command ,#00011011B h s o _ t i m e , t e m p _ t i m e r 2 , s w _ o n _ a d j ; ( i f e q u a l ) no o p e r a t i o n ; ( i f e q u a l ) sw_on_adj=sw_on+sw_on ; ( i f e q u a l ) jump t o hh2 ; ( i f n o t e q u a l ) s w _ o n _ a d j = s w _ o n ; c o m p a r e s w _ o n _ a d j w i t h sw_on_max ; ( i f g r a t e r o r e q u a l ) jump t o h h l ( i f l e s s ) g e n . s o f t w a r e t i m e r 3 i n t . when: ( i f l e s s ) t i m e r l = t e m p _ t i m e r 2 + s w _ o n ( i f l e s s ) no o p e r a t i o n ( i f l e s s ) no o p e r a t i o n ( i f l e s s ) no o p e r a t i o n ( i f l e s s ) no o p e r a t i o n . • r e t u r n f r o m s u b r o u t i n e . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * s o f t _ t i m e r _ I S R : p u s h a l d b a4 : a l l l : e 2 2 2 : a222 : a l l : a l 2 : e 2 : i o s l _ i m a g e , i o s l j b c i o s l _ i m a g e , 0 1 B , a4 l d b n o _ e i 2 , # 0 1 H j b c i o s l _ i m a g e , 1 0 B , a l i n c b k o r b i o p o r t l _ i m a g e , # 0 0 0 0 0 0 0 1 B cmpb k , # 0 2 H j n e a l l l s j m p e222 cmpb k , # 0 7 H j n e a222 c l r b n o _ e i 2 cmpb k , # 0 1 H j n e a l l a n d b i o p o r t l _ i m a g e , # 1 1 1 1 1 0 1 1 B l d b e i 2 , # 0 0 H s j m p e2 cmpb k , # 0 6 H j n e a l 2 a n d b i o p o r t l _ i m a g e , # 1 1 1 0 1 1 1 1 B l d b e i 2 , # 0 0 H s j m p e2 cmpb k , # 0 A H j n e e2 c l r b k l d b ad_command,#00001011B c a l l h s o _ s u b r o u t i n e ; s o f t w a r e t i m e r s i n t e r r u p t s e r v i c e r o u t i n e ; s a v e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR ; i o s l _ i m a g e = i o s l ; jump t o a4 i f no s o f t _ t i m e r l _ i s r ; ( i f s o f t _ t i m e r l _ i s r ) n o _ e i 2 = l D rjump t o a l i f no s o f t _ t i m e r 2 _ i s r : ( i f s o f t _ t i m e r 2 _ i s r ) k=k+ l r ( i f s o f t _ t i m e r 2 _ i s r ) b i t 0 o f i o p o r t l = l ( i f s o f t _ t i m e r 2 _ i s r ) ( i f s o f t _ t i m e r 2 _ i s r ) jump t o a l l l ( i f s o f t _ t i m e r 2 _ i s r ) jump t o e222 ( i f s o f t _ t i m e r 2 _ i s r ) ( i f s o f t _ t i m e r 2 _ i s r ) jump t o a222 ( i f s o f t _ t i m e r 2 _ i s r ) c o m p a r e k a n d 2D ( i f n o t e q u a l ) ( i f e q u a l ) c o m p a r e k a n d 7D ( i f n o t e q u a l ) ( i f e q u a l ) n o _ e i 2 = 0 D c o m p a r e k a n d ID ( i f n o t e q u a l ) ( i f s o f t _ t i m e r 2 _ i s r ) ( i f s o f t _ t i m e r 2 _ i s r ) jump t o a l l ( i f t i m e r 2 _ i s r ) ( i f e q . ) b i t 2 o f i o p o r t l = 0 ( i f t i m e r 2 _ i s r ) ( i f e q . ) e i 2 = 0 D ( i f s o f t _ t i m e r 2 _ i s r ) ( i f e q u a l ) jump t o e2 ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) c o m p a r e k a n d SD ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) ( i f n o t e q u a l ) jump t o a l 2 ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) ( i f e q u a l ) b i t 4 o f i o p o r t l = 0 ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) ( i f e q u a l ) e i 2 = 0 D ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) ( i f e q u a l ) jump t o e2 ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) ( i f n o t e q u a l ) c o m p a r e k a n d 10D ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) ( i f n o t e q u a l ) ( i f n o t e q u a l ) jump t o e2 ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) ( i f n o t e q u a l ) ( i f e q u a l ) k=0 ( i f s o f t _ t i m e r 2 _ i s r ) ( i f n o t e q u a l ) ( i f n o t e q u a l ) ( i f e q u a l ) e n a b l e A / D c h a n n e l 3 now ; ( i f s o f t _ t i m e r 2 _ i s r ) ( i f e q u a l ) c a l l h s o s u b r o u t i n e a l : j b c i o s l _ i m a g e , 0 0 B , a 3 cmpb k , # 0 1 H ; j u m p t o a2 i f no s o f t _ t i m e r O _ i s r ; ( i f s o f t _ t i m e r O _ i s r ) c o m p a r e k w i t h #1D 116 a l O : a3 : a2 : o r b s jmp cmpb j n e o r b j b c a n d b c a l l ; l d b p o p a r e t a l O i o p o r t l _ i m a g e , ttOOOlOOOOB a3 k, #06H a3 i o p o r t l _ i m a g e , # 0 0 0 0 0 1 0 0 B i o s l _ i m a g e , 1 1 B , a2 i o p o r t l _ i m a g e , # 1 1 1 1 1 1 1 0 B i o _ s u b r o u t i n e i o p o r t l , i o p o r t l _ i m a g e ( i f s o f t _ t i m e r O _ i s r ) ( i f n o t e q u a l ) jump t o a l O ( i f s o f t _ t i m e r O _ i s r ) ( i f e q u a l ) b i t 4 o f i o p o r t l = l ( i f s o f t _ t i m e r O _ i s r ) ( i f e q u a l ) jump t o a3 ( i f s o f t _ t i m e r O _ i s r ) ( i f n o t e q u a l ) c o m p a r e k w i t h #6D ( i f s o f t _ t i m e r O _ i s r ) ( i f n o t e q u a l ) ( i f n o t e q u a l ) jump t o a3 ( i f s o f t _ t i m e r O _ i s r ) ( i f n o t e q u a l ) ( i f e q u a l ) b i t 2 o f i o p o r t l = l rjump t o a2 i f no s o f t _ t i m e r 3 _ i s r : ( i f s o f t _ t i m e r 3 _ i s r ) b i t 0 o f i o p o r t l = 0 c a l l i o _ s u b r o u t i n e f o r t e s t o n l y , i o p o r t l = i o p o r t l _ i m a g e r e s t o r e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR ; r e t u r n f r o m i n t e r r u p t ch3 : c h O : _ I S R : p u s h a l d b a d _ i m a g e , a d _ r e s u l t _ l o a n d b a d _ i m a g e , # 0 0 0 0 0 1 1 1 B cmpb a d _ i m a g e , # 0 3 H j e ch3 cmpb a d _ i m a g e , # 0 0 H j e chO l d b i _ a c t , a d _ r e s u l t _ h i s h l i _ a c t , # 0 2 H a n d i _ a c t , # 0 3 F C H l d b a d _ i m a g e 2 , a d _ r e s u l t _ l o s h r a d _ i m a g e 2 , # 0 6H o r i _ a c t , a d _ i m a g e 2 l d b ad_command,#00001000B s jmp ad2 l d b i _ r e f , a d _ r e s u l t _ h i s h l i _ r e f , # 2 H a n d i _ r e f , # 0 3 F C H l d b a d _ i m a g e 2 , a d _ r e s u l t _ l o s h r a d _ i m a g e 2 , # 6H o r i _ r e f , a d _ i m a g e 2 c a l l s w _ o n _ s u b r o u t i n e p o p a r e t ; A / D c o m p l e t i o n i n t e r r u p t s e r v i c e r o u t i n e ; s a v e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR a d _ i m a g e = a d _ r e s u l t _ l o k e e p t h r e e f i r s t b i t s , d i s c a r d t h e r e s t c o m p a r e a d _ i m a g e w i t h #3D ( i f e q u a l ) jump t o ch3 ( i f n o t e q u a l ) c o m p a r e a d _ i m a g e w i t h #0D ( i f e q u a l ) jump t o chO ( i f c h 3 _ i s r ) i _ a c t = a d _ r e s u l t _ h i ( i f c h 3 _ i s r ) s h i f t i _ a c t 2 b i t s t o l e f t ( i f c h 3 _ i s r ) k e e p b i t 2 t o 9, d i s c a r d r e s t ( i f c h 3 _ i s r ) a d _ i m a g e 2 = a d _ r e s u l t _ l o ( i f c h 3 _ i s r ) s h i f t i _ a c t 6 b i t s t o r i g h t ( i f c h 3 _ i s r ) i _ a c t = i _ a c t o r a d _ i m a g e 2 ( i f c h 3 _ i s r ) e n a b l e A / D c h a n n e l O now ( i f c h 3 _ i s r ) jump t o ad2 i s r ) i _ r e f = a d _ r e s u l t _ h i i s r ) s h i f t i _ r e f 2 b i t s t o l e f t i s r ) k e e p b i t 2 t o 9, d i s c a r d r e s t i s r ) a d _ i m a g e 2 = a d _ r e s u l t _ l o i s r ) s h i f t i _ r e f 6 b i t s t o r i g h t i s r ) i _ r e f = i _ r e f o r a d _ i m a g e 2 i s r ) c a l l sw_on s u b r o u t i n e ( i f ( i f ( i f ( i f ( i f ( i f ( i f c h 3 . ch3_ c h 3 . c h 3 . ch3_ c h 3 . c h 3 . ad2 : . it************************************************* ; r e s t o r e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR ; r e t u r n f r o m i n t e r r u p t sw o n s u b r o u t i n e : c330 : s u b i _ e r r o r , i _ r e f , i _ a c t j b s i _ e r r o r , 1 1 1 1 B , c l 2 3 cmp i _ e r r o r , i _ e r r _ h y s t P P j l e c330 I d c o l , # 0 2 H l d b s e c _ r o w , # 0 1 H s j m p c l O O cmp i _ e r r o r , i _ e r r _ h y s t P j l e c30 I d c o l , # 0 0 H l d b s e c _ r o w , # 0 1 H : sw_on s u b r o u t i n e : i _ e r r o r = i _ r e f - i _ a c t r ( i f b i t #15D i s s e t = i f n e g . number) ; jump c l 2 3 ( i f p o s . ) c o m p a r e i _ e r r o r w i t h i _ e r r _ h y s t P P ( i f p o s . ) ( i f l e s s o r e q u a l ) jump t o c330 ( i f p o s . ) ( i f g r a t e r ) co l=#2D ( i f p o s . ) ( i f g r a t e r ) s e c _ r o w = # l D ( i f p o s . ) ( i f g r a t e r ) jump c l O O ( i f p o s . ) c o m p a r e i _ e r r o r _ n e w w i t h i _ e r r _ h y s t P ( i f p o s . ) ( i f l e s s o r e q u a l ) jump t o c30 ( i f p o s . ) ( i f g r a t e r ) co l=#0D ( i f p o s . ) ( i f g r a t e r ) s e c _ r o w = # l D 117 s jmp c l O O ( i f p o s . ) ( i f g r a t e r ) jump c l O O c l 2 3 : cmp i _ e r r o r , i _ e r r _ h y s t N N ( i f n e g . ) c o m p a r e i _ e r r o r w i t h i _ e r r _ h y s t N N j g e c430 ( i f n e g . ) ( i f g r a t e r o r e q u a l ) jump t o c43 0 I d c o l , # 0 0 H ( i f n e g . ) ( i f l e s s ) co l=#0D l d b s e c _ r o w , # 0 0 H ( i f n e g . ) ( i f l e s s ) sec_row=#0D s jmp c l O O ( i f n e g . ) ( i f l e s s ) jump c l O O c 4 3 0 : cmp i _ e r r o r , i _ e r r _ h y s t N ( i f n e g . ) c o m p a r e i _ e r r o r w i t h i _ e r r _ h y s t N j g e c30 ( i f n e g . ) ( i f g r a t e r o r e q u a l ) jump t o c30 I d c o l , # 0 2 H ( i f n e g . ) ( i f l e s s ) co l=#2D l d b s e c _ r o w , # 0 0 H ( i f n e g . ) ( i f l e s s ) sec_row=#0D s jmp c l O O ( i f n e g . ) ( i f l e s s ) jump c l O O c30 : I d c o l , # 0 4 H co l=#4D l d b s e c _ r o w , # 0 0 H sec_row=#0D c l O O : s u b d e l _ e r r , i _ e r r o r , i _ e r r _ o l d d e l _ e r r = i _ e r r o r - i _ e r r _ o l d j b s d e l _ e r r , 1 1 1 1 B , c l 2 4 ( i f b i t #15D i s s e t = i f n e g . number) jump C124 cmp d e l _ e r r , d e l _ e r r _ h y s t P P ( i f p o s . ) c o m p a r e d e l _ e r r w i t h e r r _ h y s t P P j l e c340 ( i f p o s . ) ( i f l e s s o r e q u a l ) jump t o c340 cmpb s e c _ r o w , # 0 1 H ( i f p o s . ) ( i f g r a t e r ) c o m p a r e s e c _ r o w w i t h #1D j n e g g l ( i f p o s . ) ( i f g r a t e r ) ( i f n o t e q u a l ) jump t o g g l I d d e l _ s w _ o n , t a b l e 9 [ c o l ] ( i f p o s . ) ( i f g r a t e r ) ( i f e q u a l ) d e l _ s w _ o n = t a b l e 9 [ c o l ] s jmp gg2 ( i f p o s . ) ( i f g r a t e r ) ( i f e q u a l ) jump gg2 g g l : I d d e l _ s w _ o n , t a b l e 8 [ c o l ] ( i f p o s . ) ( i f g r a t e r ) ( i f n o t e q u a l ) d e l _ s w _ o n = t a b l e 8 [ c o l ] g g 2 : s jmp c200 ( i f p o s . ) ( i f g r a t e r ) jump c200 c340 : cmp d e l _ e r r , d e l _ e r r _ h y s t P ( i f p o s . ) c o m p a r e d e l _ e r r w i t h d e l _ e r r _ h y s t P j l e c40 ( i f p o s . ) ( i f l e s s o r e q u a l ) jump t o c40 cmpb s e c _ r o w , # 0 1 H ( i f p o s . ) ( i f g r a t e r ) c o m p a r e s e c _ r o w w i t h #1D j n e gg3 ( i f p o s . ) ( i f g r a t e r ) ( i f n o t e q u a l ) jump t o gg3 I d d e l _ s w _ o n , t a b l e 7 [ c o l ] ( i f p o s . ) ( i f g r a t e r ) ( i f e q u a l ) d e l _ s w _ o n = t a b l e 7 [ c o l ] s jmp gg4 ( i f p o s . ) ( i f g r a t e r ) ( i f e q u a l ) jump gg4 gg3 : I d d e l _ s w _ o n , t a b l e 6 [ c o l ] ( i f p o s . ) ( i f g r a t e r ) ( i f n o t e q u a l ) d e l _ s w _ o n = t a b l e 6 [ c o l ] g g 4 : s jmp c200 ( i f p o s . ) ( i f g r a t e r ) jump c200 c l 2 4 : cmp d e l _ e r r , d e l _ e r r _ h y s t N N ( i f n e g . ) c o m p a r e d e l _ e r r w i t h d e l _ e r r _ h y s t N N j g e c440 ( i f n e g . ) ( i f g r a t e r o r e q u a l ) jump t o c440 cmpb s e c _ r o w , # 0 1 H ( i f n e g . ) ( i f l e s s ) c o m p a r e s e c _ r o w w i t h #1D j n e gg5 ( i f n e g . ) ( i f l e s s ) ( i f n o t e q u a l ) jump gg5 I d d e l _ s w _ o n , t a b l e l [ c o l ] ( i f n e g . ) ( i f l e s s ) ( i f e q u a l ) d e l _ s w _ o n = t a b l e l [ c o l ] s jmp gg6 ( i f n e g . ) ( i f l e s s ) ( i f e q u a l ) jump gg6 g g 5 : I d d e l _ s w _ o n , t a b l e O [ c o l ] ( i f n e g . ) ( i f l e s s ) ( i f n o t e q u a l ) d e l _ s w _ o n = t a b l e O [ c o l ] g g 6 : s jmp c200 ( i f n e g . ) ( i f l e s s ) jump c200 c440 : cmp d e l _ e r r , d e l _ e r r _ h y s t N ( i f n e g . ) c o m p a r e d e l _ e r r w i t h d e l _ e r r _ h y s t N j g e c40 ( i f n e g . ) ( i f g r a t e r o r e q u a l ) jump t o c40 cmpb s e c _ r o w , # 0 1 H ( i f n e g . ) ( i f l e s s ) c o m p a r e s e c _ r o w w i t h #1D j n e gg7 ( i f n e g . ) ( i f l e s s ) ( i f n o t e q u a l ) jump gg7 I d d e l _ s w _ o n , t a b l e 3 [ c o l ] ( i f n e g . ) ( i f l e s s ) ( i f e q u a l ) d e l _ s w _ o n = t a b l e 3 [ c o l ] 118 s j m p gg8 ( i f n e g . ) ( i f l e s s ) ( i f e q u a l ) jump gg8 g g 7 : I d d e l _ s w _ o n , t a b l e 2 [ c o l ] ( i f n e g . ) ( i f l e s s ) ( i f n o t e q u a l ) d e l _ s w _ o n = t a b l e 2 [ c o l ] g g 8 : s j m p c200 ( i f n e g . ) ( i f l e s s ) jump c 2 0 0 c40 : cmpb s e c _ r o w , # 0 1 H c o m p a r e s e c _ r o w w i t h #01H j n e gg9 ( i f n o t e q u a l ) jump gg9 I d d e l _ s w _ o n , t a b l e 5 [ c o l ] ( i f e q u a l ) d e l _ s w _ o n = t a b l e 5 [ c o l ] s j m p g g l O ( i f e q u a l ) jump g g l O g g 9 : I d d e l _ s w _ o n , t a b l e 4 [ c o l ] ( i f n o t e q u a l ) d e l _ s w _ o n = t a b l e 4 [ c o l ] g g l O : s j m p c200 jump c200 c200 : I d i _ e r r _ o l d , i _ e r r o r i _ e r r _ o l d = i _ e r r o r ; l d i _ e r r _ o l d , # 0 H f o r t e s t o n l y , i _ e r r _ o l d = 0 D cmpb e i 2 , # 0 1 H c o m p a r e e i 2 a n d ID j n e cb2 ( i f n o t e q u a l ) jump t o cb2 j b s d e l _ s w _ o n , 1 1 1 1 B , c d l 2 3 ( i f b i t #15D i s s e t = i f n e g . n u m b e r ) jump c d l 2 3 c i r d e l _ s w _ o n ( i f c l e a r ) c l e a r d e l _ s w _ o n s j m p cb2 ( i f c l e a r ) jump t o cb2 c d l 2 3 : s h l d e l _ s w _ o n , # 0 2 H ( i f s e t ) d e l _ s w _ o n = d e l _ s w _ o n / #4D o r d e l _ s w _ o n , # 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B ( i f s e t ) s e t b i t #15D o f d e l _ s w _ o n cb2 : a d d s w _ o n , d e l _ s w _ o n sw_on=sw_on+de l_sw_on cmp s w _ o n , s w _ o n _ m i n c o m p a r e sw_on w i t h s w _ o n _ m i n j g e c50 ( i f g r a t e r o r e q u a l ) jump t o c50 I d sw_on ,#0H ( i f l e s s ) sw_on=#0H s j m p c300 ( i f l e s s ) jump c300 c50 : cmp sw_on , sw_on_max ( i f g r a t e r o r e q u a l ) c o m p a r e sw_on w i t h sw_on max j l e c300 ( i f g r a t e r o r e q u a l ) ( i f l e s s o r e q u a l ) jump t o c300 I d s w _ o n , s w _ p e r i o d ( i f g r a t e r o r e q u a l ) ( i f g r a t e r ) sw_on =sw p e r i o d c 3 0 0 : r e t r e t u r n f r o m s u b r o u t i n e . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * i o _ s u b r o u t i n e i o s u b r o u t i n e cmpb e i 2 , # 0 1 H c o m p a r e e i 2 a n d ID j n e b2 ( i f n o t e q u a l ) jump t o b2 a n d b i o p o r t l _ i m a g e , # 1 1 1 1 0 1 0 1 B ( i f e q u a l ) c l e a r i o p o r t l _ i m a g e . 1 & .3 s j m p b6 ( i f e q u a l ) jump t o b6 b 2 : j b c i o p o r t l _ i m a g e , 1 0 0 B , b3 ( i f i o p o r t l _ i m a g e . 4 c l e a r ) jump t o b3 j b c i o p o r t l _ i m a g e , 0 0 O B , b 3 ( i f i o p o r t l _ i m a g e . 0 c l e a r ) jump t o b3 o r b i o p o r t l _ i m a g e , # 0 0 0 0 0 0 1 0 B ( i f i o p o r t l _ i m a g e . 0 a n d i o p o r t l _ i m a g e . 4 s e t ) s e t i o p o r t l _ i m a g e . 1 s j m p b4 ( i f i o p o r t l _ i m a g e . 0 a n d i o p o r t l _ i m a g e . 4 s e t ) jump t o b4 b3 : a n d b i o p o r t l _ i m a g e , # 1 1 1 1 1 1 0 1 B ( i f i o p o r t l _ i m a g e . 0 o r i o p o r t l _ i m a g e . 4 c l e a r ) c l e a r i o p o r t l _ i m a g e . 1 b 4 : j b c i o p o r t l _ i m a g e , 0 1 0 B , b5 ( i f i o p o r t l _ i m a g e . 2 c l e a r ) jump t o b5 j b c i o p o r t l _ i m a g e , 0 0 O B , b5 ( i f i o p o r t l _ i m a g e . 0 c l e a r ) jump t o b5 o r b i o p o r t l _ i m a g e , # 0 0 0 0 1 0 0 0 B ( i f i o p o r t l _ i m a g e . 0 a n d i o p o r t l _ i m a g e . 2 s e t ) s e t i o p o r t l _ i m a g e . 3 s j m p b6 ( i f i o p o r t l _ i m a g e . 0 a n d i o p o r t l _ i m a g e . 2 s e t ) jump t o b6 b 5 : a n d b i o p o r t l _ i m a g e , # 1 1 1 1 0 1 1 1 B ( i f i o p o r t l _ i m a g e . 0 o r i o p o r t l _ i m a g e . 2 c l e a r ) c l e a r i o p o r t l _ i m a g e . 3 b S : l d b i o p o r t l , i o p o r t l _ i m a g e i o p o r t l = c o p y o f i o p o r t l r e t r e t u r n f r o m s u b r o u t i n e . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * e x t e r n a l _ i n t : p u s h a cmpb n o _ e i 2 , # 0 1 H ; e x t e r n a l i n t e r r u p t s e r v i c e r o u t i n e 1 ; s a v e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR ; c o m p a r e n o _ e i 2 a n d ID 119 b s 2 : b s 6 : jne s j m p l d b c a l l ; a n d b p o p a b s 2 b s 6 e i 2 , # 0 1 H i o _ s u b r o u t i n e i o p o r t l , # 1 1 1 1 0 1 0 1 B ( i f n o t e q u a l ) jump t o b s 2 ( i f e q u a l ) jump t o b s S e i 2 = l D c a l l i o s u b r o u t i n e f o r t e s t o n l y , c l e a r i o p o r t l . 1 & .3 r e s t o r e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR c a l l i o _ s u b r o u t i n e ; a n d b i o p o r t l , t t l l l l O l O l B ; c a l l i o s u b r o u t i n e ; c l e a r i o p o r t l . 1 & .3 ; r e t u r n f r o m i n t e r r u p t * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ; e x t e r n a l _ i n t : p u s h a l d b i o p o r t l , # 0 0 1 0 0 0 0 0 B l d b i o c 2 , # 1 0 0 1 0 0 0 0 B p o p a ; e x t e r n a l i n t e r r u p t s e r v i c e r o u t i n e 2 ; s a v e P S W , I N T _ M A S K , I N T _ M A S K 1 & WSR ; o n l y b i t 5 o f i o p o r t l = l ; c l e a r CAM + A / D c l o c k p r e s c a l a t o r d i s a b l e ; r e s t o r e P S W , I N T M A S K , I N T MASK1 & WSR 12: ; s j m p 12 c a l l d e l a y _ s u b r o u t i n e l d b i o p o r t l , # 0 O O 0 0 0 0 0 B c a l l d e l a y _ s u b r o u t i n e l d b i o p o r t l , ttOOlOOOOOB s j m p 12 l o o p f o r e v e r h e r e , f o r s t e a d y o u t p u t c a l l d e l a y s u b r o u t i n e a l l b i t s o f i o p o r t l = 0 c a l l d e l a y s u b r o u t i n e o n l y b i t 5 o f i o p o r t l = l jump t o 12 , do i t a g a i n r e t ; r e t u r n f r o m i n t e r r u p t . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * d e l a y _ s u b r o u t i n e : 1 1 : I d s u b cmp j n e r e t k k l , # 0 F F F F H k k l , # 0 1 H k k l , # 0 0 H 11 k k l = # O F F F F H k k l = k k l - 1 c o m p a r e k k l w i t h #0D ( i f n o t e q u a l ) jump 11 ( i f e q u a l ) b a c k t o t h e m a i n r o u t i n e . * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * e n d ; e n d o f p r o g r a m m i n g 120 APPENDIX D C++ CODE FOR DAQ-801 A sample C++ program that was used with DAQ-801 is provided below. /******************************************************************************* PROGRAM: D A Q - 8 0 1 P r o g r a m mhd2 P U R P O S E : I n p u t 10 s a m p l e s e a c h f r o m A / D c h a n n e l s 0 t o 4 k******************************************************************************* # i n c l u d e < c o n i o . h > # i n c l u d e < s t d l i b . h > # i n c l u d e < s t d i o . h > # i n c l u d e < t i m e . h > # i n c l u d e < b i o s . h > # i n c l u d e " u s e r d a t a . h " # i n c l u d e " d a q d r i v e . h " • i n c l u d e " d a q o p e n c . h " • i n c l u d e " d a q 8 0 0 . h " / * * * When d e f i n e d g l o b a l o r s t a t i c , s t r u c t u r e s a r e +**/ / * * * a u t o m a t i c a l l y i n i t i a l i z e d t o a l l 0 * * * / s t r u c t D A Q D R I V E _ b u f f e r m y _ d a t a [ 2 ] ; s t r u c t A D C _ r e q u e s t u s e r _ r e q u e s t ; / * * D e c l a r e d a t a g l o b a l * * * / u n s i g n e d s h o r t m a i n ( ) { u n s i g n e d s h o r t l o g i c a l _ d e v i c e ; u n s i g n e d s h o r t r e g u e s t _ h a n d l e ; u n s i g n e d s h o r t c h a n n e l [ 5 ] = { 0, 1, 2, 3 , 4 ) ; u n s i g n e d s h o r t s t a t u s ; s h o r t i n p u t _ d a t a [ 1 0 ] [ 5 ] ; f l o a t g a i n [ 5 ] = { l . O f , l . O f , l . O f , l . O f , l . O f }; u n s i g n e d l o n g e v e n t _ m a s k ; c h a r * d e v i c e _ t y p e = " D A Q - 8 0 1 " ; c h a r * c o n f i g _ f i l e = " D A Q - 8 0 1 . d a t " ; u n s i g n e d s h o r t i , k; c l o c k _ t s t a r t , e n d ; F I L E • * o u t p u t _ f i l e ; o u t p u t _ f i l e = f o p e n { " A D C _ D A T A . A S C " , "w"); / * o p e n t h e f i l e * / /******************************************************************************* S t e p 1: I n i t i a l i z e H a r d w a r e ******************************************************* l o g i c a l _ d e v i c e = 0; s t a t u s = D a q O p e n D e v i c e ( D A Q 8 0 0 , & l o g i c a l _ d e v i c e , d e v i c e _ t y p e , c o n f i g _ f i l e ) ; i f ( s t a t u s != 0) { p r i n t f ( " E r r o r o p e n i n g d e v i c e . S t a t u s c o d e % d . \ n " , s t a t u s ) ; e x i t ( s t a t u s ) ; } a g a i n : s t a r t = c l o c k ( ) ; 121 / * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * + +'**** + * * * * * * * * * * * * * * * * * S t e p 2: P r e p a r e B u f f e r S t r u c t u r e * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * , m y _ d a t a [ 0 ] . d a t a _ b u f f e r m y _ d a t a [ 0 ] . b u f f e r _ l e n g t h m y _ d a t a [ 0 ] . n e x t _ s t r u c t u r e m y _ d a t a [ 0 ] . b u f f e r _ s t a t u s i n p u t _ d a t a O ; 50; & m y _ d a t a [ 1 ] ; B U F F E R _ E M P T Y ; / * s e t p o i n t e r t o o u t p u t d a t a * / / * number o f p o i n t s i n b u f f e r * / / * i n d i c a t e no more b u f f e r s * / / * i n d i c a t e b u f f e r e m p t y ( r e a d y ) * / my. . d a t a 1] . d a t a _ b u f f e r = i n p u t _ d a t a l ; / * s e t p o i n t e r t o o u t p u t d a t a my_ . d a t a 1] . b u f f e r _ l e n g t h = 50; / * number o f p o i n t s i n b u f f e r my_ _ d a t a 1] . n e x t _ s t r u c t u r e = & m y _ d a t a [ 0 ] ; / * i n d i c a t e no more b u f f e r s ray_ d a t a 1] . b u f f e r _ s t a t u s = B U F F E R _ E M P T Y ; / * i n d i c a t e b u f f e r e m p t y ( r e a d y ) P r e p a r e t h e A / D r e q u e s t s t r u c t u r e * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * / u s e r _ r e q u e s t c h a n n e l _ a r r a y _ p t r = c h a n n e l ; /* a r r a y o f c h a n n e l s */ u s e r _ r e q u e s t g a i n _ a r r a y _ p t r = g a i n ; /* a r r a y o f g a i n s */ u s e r _ r e q u e s t a r r a y _ l e n g t h = 5; /* number o f c h a n n e l s */ u s e r _ r e q u e s t A D C _ b u f f e r = m y _ d a t a ; /* p o i n t e r t o d a t a */ u s e r _ r e q u e s t t r i g g e r _ s o u r c e = I N T E R N A L _ T R I G G E R ; /* i n t e r n a l t r i g g e r */ u s e r _ r e q u e s t t r i g g e r _ m o d e = CONTT.NUOUS_TRT.GGER; /* i n p u t a l l p o i n t s */ u s e r _ r e q u e s t IO_mode = BACKGROUND_IRQ; /* b a c k g r o u n d mode */ u s e r _ r e q u e s t c l o c k _ s o u r c e = I N T E R N A L _ C L O C K ; /* u s e o n - b o a r d c l o c k */ u s e r _ r e q u e s t s a m p l e _ r a t e = 10; /* Hz i n p u t r a t e */ u s e r _ r e q u e s t n u m b e r _ o f _ s c a n s = 10; /* # s c a n s */ u s e r _ r e q u e s t s c a n _ e v e n t _ l e v e l = 0; /* no s c a n e v e n t s */ u s e r _ r e q u e s t c a l i b r a t i o n = A U T O _ C A L I B R A T E | A U T O _ Z E R O ; /* no c a l i b r a t i o n */ u s e r _ r e q u e s t t i m e o u t _ i n t e r v a l = 0; /* d i s a b l e t i m e - o u t */ u s e r _ r e q u e s t r e q u e s t _ s t a t u s = 0; /* i n i t i a l i z e s t a t u s */ r e q u e s t _ h a n d l e = 0; /* new r e q u e s t */ s t a t u s = D a q A n a l o g l n p u t ( l o g i c a l _ d e v i c e , & u s e r _ r e q u e s t , & r e q u e s t _ h a n d l e ) ; i f ( s t a t u s != 0) { p r i n t f ( " A / D r e q u e s t e r r o r . S t a t u s c o d e % d . \ n " , s t a t u s ) ; p r i n t f ( " \ n P r e s s <ESC> t o c o n t i n u e " ) ; w h i l e ( g e t c h ( ) != 0 x 1 b ) ; D a q C l o s e D e v i c e ( l o g i c a l _ d e v i c e ) ; e x i t ( s t a t u s ) ; } /*****************************************+*+************************************************* S t e p 3 : A r m t h e R e q u e s t ********************************************************************************************* j s t a t u s = D a q A r m R e q u e s t ( r e q u e s t _ h a n d l e ) ; i f ( s t a t u s .'= 0) ( p r i n t f ( " A r m r e q u e s t e r r o r . S t a t u s c o d e % d . \ n " , s t a t u s ) ; p r i n t f ( " \ n P r e s s <ESC> t o c o n t i n u e " ) ; w h i l e ( g e t c h ( ) != 0 x 1 b ) ; D a q R e l e a s e R e q u e s t ( r e q u e s t _ h a n d l e ) ; D a q C l o s e D e v i c e ( l o g i c a l _ d e v i c e ) ; e x i t ( s t a t u s ) ; } / * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * S t e p 4: T r i g g e r t h e R e q u e s t * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * / s t a t u s = D a q T r i g g e r R e q u e s t ( r e q u e s t _ h a n d l e ) ; i f ( s t a t u s != 0) { p r i n t f ( " T r i g g e r r e q u e s t e r r o r . S t a t u s c o d e % d . \ n " , s t a t u s ) ; p r i n t f ( " \ n P r e s s <ESC> t o c o n t i n u e " ) ; w h i l e ( g e t c h ( ) != 0 x 1 b ) ; D a q R e l e a s e R e q u e s t ( r e q u e s t _ h a n d l e ) ; D a q C l o s e D e v i c e ( l o g i c a l _ d e v i c e ) ; e x i t ( s t a t u s ) ; } 122 /******************************************************************************************** S t e p 5: W a i t f o r c o m p l e t i o n o r e r r o r * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * i e v e n t _ m a s k = C O M P L E T E _ E V E N T | RUNTIME_ERROR__EVENT ; w h i l e ( ( u s e r _ r e q u e s t . r e q u e s t _ s t a t u s & e v e n t _ m a s k ) == 0 ) ; / * w a i t f o r e v e n t * / i f ( ( u s e r _ r e q u e s t . r e q u e s t _ s t a t u s & C O M P L E T E _ E V E N T ) != 0) { I*** s u c c e s s f u l , d i s p l a y d a t a * * * / c l r s c r ( ) ; p r i n t f ( " c h a n n e l * : 0 1 2 3 4 \ n " ) ; r e w i n d ( o u t p u t _ f i l e ) ; f p r i n t f ( o u t p u t _ f i l e , " c h a n n e l * : 0 1 2 3 4 \ n " ) ; f o r d = 0; i < 10; i + +) { p r i n t f ( " s a m p l e #%4d: ", ( i ) ) ; f p r i n t f ( o u t p u t _ f i l e , " s a m p l e #%4d: " , ( i ) ) ; . f o r ( k = 0; k < 5; k++) { p r i n t f ( " %6d", i n p u t _ d a t a [ i ] [ k ] ) ; f p r i n t f ( o u t p u t _ f i l e , " %6d", i n p u t _ d a t a [ i ] [ k ] ) ; } p r i n t f ( " \ n " ) ; f p r i n t f ( o u t p u t _ f i l e , " \ n " ) ; } } e l s e C p r i n t f ( " R u n - t i m e e r r o r . O p e r a t i o n a b o r t e d . \ n " ) ; p r i n t f ( " \ n P r e s s <ESC> t o c o n t i n u e " ) ; w h i l e ( g e t c h ( ) != 0 x 1 b ) ; D a q R e l e a s e R e q u e s t ( r e g u e s t _ h a n d l e ) ; D a q C l o s e D e v i c e ( l o g i c a l _ d e v i c e ) ; e x i t ( s t a t u s ) ; } /********************************************************************************************* S t e p 6: R e l e a s e t h e R e q u e s t *********************************************************************************************i s t a t u s = D a q R e l e a s e R e q u e s t ( r e q u e s t _ h a n d l e ) ; i f ( s t a t u s != 0) { p r i n t f ( " C o u l d n o t r e l e a s e c o n f i g u r a t i o n . S t a t u s c o d e % d . \ n " , s t a t u s ) ; p r i n t f ( " \ n P r e s s <ESC> t o c o n t i n u e " ) ; w h i l e ( g e t c h l ) != 0 x 1 b ) ; e x i t ( s t a t u s ) ; } e n d = c l o c k ( ) ; p r i n t f ( " T h e t i m e was : % f \ n " , ( end - s t a r t ) / C L K _ T C K ) ; i f ( b i o s k e y ( l ) == N U L L ) { g o t o a g a i n ; } I********************************************************************************************* S t e p 7 : C l o s e H a r d w a r e D e v i c e *********************************************************************************************/ s t a t u s = D a q C l o s e D e v i c e ( l o g i c a l _ d e v i c e ) ; i f ( s t a t u s != 0) p r i n t f ( " E r r o r c l o s i n g d e v i c e . S t a t u s c o d e % d . \ n " , s t a t u s ) ; f c l o s e ( o u t p u t _ f i l e ) ; r e t u r n ( s t a t u s ) ; } 123 APPENDIX E MECHANICAL DRAWINGS In this appendix, the drawings for the cabinets, laminated busbars and the cold plates (mechanical drawings) are included. 124 FIGURE E . l . DWG-100-9 general cubicle layout 125 FIGURE E.2. DWG-600-5 laminated busbar layout 1 en © ® © o o o 0 0 0 © © © o o ® © © © © © o o o St o o o © © s ! mas TJ 5 o-B ? S j g S S51IS — o * a . _• • 1 1 s * i ? . 1 5 ? g § *" > o < _ i 9 ^ 3 ^ © o 'O P 9 * 9 , 9 i -fe© G © o 0 o 0 -1-4*-0 o SI* O " Q 0 o o 0 O 0 © O 0 O © O 0 0 0 m " m 5 <u a" > n aj o g-ce S - l " =]£!•_ m u_ <_, •a 5 t= QJ C O L-T * • O O S4-O G , —j-pi ! o : -sl O O o o 126 FIGURE E.3. DWG-300-0 cold plate layout o o o o o o o o o o o 8 8 ' 8 T . $~ s. O O O O O o o o o o o p o 3 8 ! = ,S = : > < (' 127 

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