T I M E D E L A Y COMPENSATION OF DIGITAL CONTROL FOR S W I T C H M O D E D C P O W E R SUPPLIES USING PREDICTION TECHNIQUES by Stephane B I B I A N Engineering Diploma Ecole Superieure d'Ingenieurs en Electronique et Electrotechnique Amiens, France, 1997 A thesis submitted i n partial fulfillment o f the requirements for the degree o f Master o f A p p l i e d Science in T H E F A C U L T Y OF G R A D U A T E Department of Electrical STUDIES and Computer Engineering W e accept this thesis as conforming to the required standard T H E UNIVERSITY O F BRITISH June 1999 © Stephane Bibian, 1999 COLUMBIA In presenting degree at the this thesis in partial fulfilment of the University of British Columbia, I agree that the freely available for reference and study. I further copying of this thesis for scholarly purposes department or requirements by his or her representatives. for an advanced Library shall make it agree that permission for extensive may be granted It is by the head of my understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department The University of British Columbia Vancouver, Canada Date DE-6 (2/88) ABSTRACT The control of switchmode dc power supplies has been traditionally implemented in analog electronics for its low cost, high bandwidth, and proven technology. However, the emergence of advanced microprocessors and Digital Signal Processors (DSPs) has made it possible for power supply manufacturers to consider digital technology a suitable option. As compared to analog control, digital control provides a number of advantages such as reduced susceptibility to aging and environmental variation (temperature, humidity, etc.), better noise immunity, ability to handle complex control schemes and monitoring functions, possibility to implement communication functions for fault and status information, and easy re-programming for different applications. With the downward trend of microprocessor prices and the versatility of the hardware architecture, digital control offers a cost-effective solution which can compete with analog technology. However, one of the major drawbacks of digital control is the limited bandwidth caused by the inherent time delay required for A / D conversion, computation and P W M generation. Such delay degrades the control loop performance, which makes it difficult to comply with technical specifications in many high-performance products. In this thesis, a simple and straightforward predictive technique based on linear extrapolation is presented to compensate for this delay. Two predictive controllers are derived and applied to a full bridge dc power supply. Simulation and experimental results show that the performances of the converter with respect to dc bus ripple and load disturbances can be significantly improved. Those schemes are characterized by a low computational cost which makes them particularly attractive in the demanding real-time environment due to the ever increasing switching frequency of the converter. A similar prediction concept based on a second order parabolic extrapolation is also presented. This predictor substantially reduces the amount of calculation needed to obtain similar results to a conventional controller, thus freeing valuable processor resources. These resources can be used for less critical tasks such as communication and user interface. As a result, the processor is not solely dedicated to the control of the power supply but can incorporate other functions, thus adding functionality and expandability to the system. Finally, this thesis assesses typical digital control issues such as word length, A / D resolution and fixed point programming. ii RESUME DE THESE COMPENSATION D U RETARD P U R L I E A U CONTROLE NUMERIQUE D'ALIMENTATIONS A DECOUPAGE PAR L'UTILISATION D E TECHNIQUES D E PREDICTION Le controle des alimentations a decoupage a ete traditionnellement implements en analogique du fait du faible cout, de la large bande passante et de la fiabilite reconnue de cette technologie. Toutefois, l'emergence de microprocesseurs et processeurs de traitement du signal puissants a fait que la technologie numerique est devenue une option viable pour les manufacturiers d'alimentations de puissance. Compare au controle analogique, le controle numerique offre un certain nombre d'avantages, entre lesquels une susceptible reduite au vieillissement et aux variations de temperature et d'humidite, et une plus grande immunite contre le bruit. II peut gerer des algorithmes de controle complexes et des fonctions de surveillance et de communication pour la detection de fautes. II permet aussi une reprogrammation aisee pour differentes applications. Avec la baisse constante des prix des microprocesseurs et 1'universalis de leur architecture, le controle numerique offre une solution rentable qui peut aller jusqu'a concurrencer la technologie analogique. Toutefois, un des inconvenients majeur du controle numerique est sa faible bande passante qui resulte du retard pur provenant de la conversion analogique/digitale, des calculs de Palgorithme de controle et de la generation des impulsions a largeur modulee. Ce retard reduit les performances de la boucle de controle. II est alors improbable que des produits haute qualite remplissent le cahier des charges qui leur est associe. Une technique de prediction par extrapolation lineaire concue pour compenser ce retard est presentee dans cette these. Deux controleurs predictifs en sont derives et sont appliques a une alimentation a decoupage a pont complet. Des simulations et des resultats experimentaux montrent une nette amelioration des performances du convertisseur soumis a des ondulations du bus continu et a des variations de charge. Ces deux techniques de controle sont caracterisees par un faible cout calculatoire ce qui les rend tres interessantes dans un environement temps reel deja fortement contraint par la frequence de commutation elevee du convertisseur. iii Un concept de prediction similaire utilisant une extrapolation parabolique du second ordre est aussi presente. Cette methode de prediction reduit substantiellement la quantite de calculs necessites pour l'obtention d'un resultat similaire a celui d'un controleur conventionel, ce qui libere de precieuses resources calculatoires. Ces resources peuvent alors etre utilisees pour des taches a charactere moins critique telles que la communication et l'interface utilisateur. En consequence, le processeur n'est plus dedie uniquement au controle de 1'alimentation, mais peut incorporer aussi d'autres fonctions, ce qui rend le systeme plus fonctionnel et extensible. Finalement, les problemes typiques lies au controle numerique, a savoir la resolution limitee du convertisseur analogique/numerique et du microprocesseur, et la programmation en point fixe, sont etudies dans cette these. iv T A B L E OF C O N T E N T S THESIS A B S T R A C T ii R E S U M E D E THESE iii LIST OF T A B L E S ix LIST OF FIGURES x LIST OF A C R O N Y M S xiii ACKNOWLEDGEMENTS xiv Chapter 1 : 1 INTRODUCTION 1.1 Digital Control of Switching Mode Power Supplies: Pros and Cons 1.1.1 1.1.2 1 Advantages 1 1.1.1.1 Better Hardware Stability 1 1.1.1.2 Cost Effective Solution 2 1.1.1.3 Computational Power 2 Drawbacks 2 1.1.2.1 Lower Performances 3 1.1.2.2 New Technology 3 1.2 Problem Statement and Literature Review 3 1.2.1 Derivative Action 4 1.2.2 Model Based Predictive Control 6 1.3 Thesis Objectives 8 1.4 Thesis Outline 9 Chapter 2 : S Y S T E M STRUCTURE 2.1 Power Circuit Topology and Modeling 10 10 2.1.1 Topology 10 2.1.2 Continuous Time Domain Model 13 2.1.3 Major Sources of Disturbance 16 2.2 Control Circuit Structure 17 2.2.1 Peak Current Mode Control 19 2.2.2 Average Current Mode Control 22 2.2.2.1 Inner Loop Control Design 22 2.2.2.2 Outer Loop Control Design 23 2.2.2.3 Load Current Feedforward 24 2.2.3 One-Cycle Control and Charge Control 2.3 Summary Chapter 3 : DIGITAL CONTROL DESIGN 3.1 From Analog to Digital 24 26 27 27 3.1.1 Quantization Effect of the A / D Converter 28 3.1.2 Computational Time Delay 30 3.1.3 Zero-Order-Hold 32 3.1.4 Anti-Aliasing Filter 33 3.1.5 Discussion 33 3.2 Discrete Equivalent of Continuous Time Domain Controllers 34 3.2.1 Approximation Methods 34 3.2.2 Matched Pole-Zero Method 35 3.2.3 Discrete PI Compensator 36 3.2.4 Effect of Quantization 37 3.3 Control Design and Application 37 3.3.1 Specifications 38 3.3.2 Analog Control Design 38 3.3.3 Digital Control Design 39 3.3.4 Simulation Results 41 3.3.5 Quantization Effect 45 3.4 Summary 46 Chapter 4 : PREDICTIVE C O N T R O L FOR T I M E D E L A Y 47 COMPENSATION 4.1 Proposed Predictive Control Technique 47 4.1.1 Prediction Concept 48 4.1.2 Modified and Simplified Predictors 49 4.2 Effect on the Control Design 53 4.2.1 Continuous Time Domain Analysis 54 4.2.2 Application to Switchmode Converters 57 4.2.3 Simulation Results 58 4.3 Extended Simplified Predictor 62 4.3.1 Derivation of the Prediction Function 63 4.3.2 Application and Comparison with Conventional Digital Control Performance 65 4.4 Summary Chapter 5 66 : EXPERIMENTAL RESULTS 5.1 Experimental Setup 5.1.1 67 67 Power Stage Design 67 5.1.1.1 Diode Bridge and dc Bus Filter 68 5.1.1.2 Inverter 69 5.1.1.3 Transformer 69 5.1.1.4 Output Filter 70 5.1.2 Sensors 71 5.1.3 DSP Platform 72 5.1.4 Control Algorithm 74 5.1.4.1 Interrupt Routine 74 5.1.4.2 PI Algorithm 77 5.1.4.3 PWM Generation 78 5.2 Experimental Results 81 5.2.1 Control Performances 81 5.2.2 Computation Time 85 5.3 Summary 86 vii Chapter 6 : CONCLUSION 88 6.1 About Digital Control 88 6.2 Contribution 89 6.3 Suggestions for Future Work 90 BIBLIOGRAPHY 92 A P P E N D I X A : S I M U L A T E D P E R F O R M A N C E S OF T H E XFR-2.8 kW 95 A P P E N D I X B : P R O G R A M LISTING 99 L I S T OF T A B L E S Table 3.1 Full bridge main parameters and specifications 38 Table 3.2 Analog control parameters 39 Table 3.3 Conventional digital control parameters 40 Table 3.4 Performance of analog and digital controllers 43 Table 3.5 A / D converter quantization effect 45 Table 3.6 A / D converter quantization effect with level shifting 45 Table 3.7 D / A converter quantization effect 46 Table 4.1 Simplified and Modified Predictor control parameters 59 Table 4.2 Performance of the predictive controllers 61 Table 4.3 Resulting delay associated with each control structure 66 Table 5.1 Computational time for different control schemes 86 Table A . l X F R 2.8 kW parameters and specifications 95 Table A.2 Control parameters 96 Table A.3 Control performances 98 ix L I S T OF F I G U R E S Fig. 1.1 Block diagram of the control loop of a process with delay 4 Fig. 1.2 Effect of the derivative action of the interacting PID controller 4 Fig. 1.3 Smith Predictor structure 6 Fig. 1.4 Internal Model Control structure 7 Fig. 2.1 Full bridge dc-dc converter 11 Fig. 2.2 Switching pattern 11 Fig. 2.3 Qualitative switched waveforms of a full bridge converter in steady state 12 Fig. 2.4 States of the system (continuous mode) 13 Fig. 2.5 Line rectification 16 Fig. 2.6 Models frequency response 18 Fig. 2.7 Concept o f P C M C based controllers 20 Fig. 2.8 Peak current mode control schematic 21 Fig. 2.9 Average Current Mode Control block diagram 22 Fig. 2.10 Analog control structure for A C M C schemes 23 Fig. 2.11 Charge and Quasi-Charge control structure 25 Fig. 3.1 Digital equivalent of an analog control loop 28 Fig. 3.2 Phase lag of a pure time delay 31 Fig. 3.3 Duty ratio update in digital scheme 31 Fig. 3.4 Frequency response of a zero-order-hold 33 Fig. 3.5 Equivalent time-domain digital control loop block diagram 39 Fig. 3.6 Discrete PI structure 41 Fig. 3.7 Comparison between analog and digital control - dc bus ripple rejection 42 Fig. 3.8 Comparison between analog and digital control - step-up load change (28 % to full 43 load) Fig. 3.9 Comparison between analog and digital control - step-down load change (full load to 44 28 %) x Fig. 4.1 Discrete time domain feedback control system 48 Fig. 4.2 Typical step response of a second order process 49 Fig. 4.3 Control loop block diagram 51 Fig. 4.4 Representation of the prediction functions mechanism 52 Fig. 4.5 Timing sequence of the different control schemes 53 Fig. 4.6 Equivalent control loop for digital control design 54 Fig. 4.7 Inherent phase lag of the feedback path for different control structures 55 Fig. 4.8 Phase lag compensation factor 56 Fig. 4.9 Implementation of the Modified Predictor for a current mode controller 58 Fig. 4.10 Comparison between the two predictor schemes - dc bus ripple rejection 59 Fig. 4.11 Comparison between the two predictor schemes - step-up load change (28% to full 60 load) Fig. 4.12 Comparison between the two predictor schemes - step-down load change (full load 61 to 28%) Fig. 4.13 Extended Simplified Predictor concept 63 Fig. 4.14 Extended Simplified Predictor Control loop block diagram 64 Fig. 4.15 Timing sequence of the Extended Simplified Predictor 64 Fig. 4.16 Comparison between conventional digital control and ESP control 65 Fig. 5.1 Power stage schematic diagram of the experimental setup 68 Fig. 5.2 Transformer winding schematic 70 Fig. 5.3 TMS320F240 internal structure 73 Fig. 5.4 Interrupt routine - Conventional Digital Control and Modified Predictor 75 Fig. 5.5 Interrupt routine - Simplified Predictor 76 Fig. 5.6 Interrupt routine - Extended Simplified Predictor 77 Fig. 5.7 PI algorithm 79 Fig. 5.8 Pulse Width Modulation scheme 80 Fig. 5.9 Simulation and experimental results of the output voltage ripple with the 83 conventional digital controller Fig. 5.10 Simulation and experimental results of the output voltage ripple with the Modified 83 Predictor Fig. 5.11 Simulation and experimental results of the output voltage ripple with the Simplified 84 Predictor xi Fig. 5.12 Simulation and experimental results of the output voltage ripple with the Extended 84 Simplified Predictor Fig. 5.13 Duty ratio for the different control schemes 85 Fig. 5.14 Computation time of the DSP with different control algorithms 87 Fig. A . l Harmonic spectrum of the output voltage 96 Fig. A.2 Load disturbance compensation (10% to full load) 97 Fig. A.3 Load disturbance compensation (full load to 10%) 97 xii L I S T OF A C R O N Y M S A/D Analog-to-Digital AC Analog Controller ACMC Average Current Mode Control AWG American Wire Gauge CDC Conventional Digital Control CMC Current Mode Control D/A Digital-to-Analog DSP Digital Signal Processor EMI Electromagnetic Interference ESP Extended Simplified Predictor ESR Equivalent Series Resistance IGBT Insulated Gate Bipolar Transistor IMC Internal Model Control IPM Intelligent Power Module MBPC Model Based Predictive Control MP Modified Predictor PCMC Peak Current Mode Control PI Proportional-Integral PID Proportional-Integral-Derivative PFC • Power Factor Correction PSIM . Power Electronic Circuit Simulator PWM : Pulse Width Modulation Root Mean Square rms SMPS : Switching Mode Power Supply SP : Simplified Predictor ZOH Zero-Order-Holder xiii ACKNOWLEDGEMENTS I wish to express my deepest gratitude to my supervisor, Dr. Hua Jin, for his valuable support, advice, and guidance throughout the course of my research. I am also indebted to Wayne Butner and Dr. Djordge Garabandic from Xantrex Technology Inc. for sharing with me their practical experience and optimism in digital technology. Thanks are extended to my colleagues in the Power Electronics Research Lab, who made the period of my research more pleasant and fruitful. Special thanks are to A n i l Tuladhar, Yingran Duan and Kenneth Wicks for many helpful discussions we shared and enjoyed. Finally, I would like to thank all my friends here in Vancouver for providing unfaltering support during those final hectic days, and in particular Dorothy Kieft and Sarah Walker for reviewing part of this thesis. Financial support from Xantrex Technology Inc. is also gratefully acknowledged. xiv Chapter I INTRODUCTION The main reasons which spurred the interest of power supplies manufacturers in digital control are identified in the first section of this introductory chapter. The problem we are addressing and the literature review are presented in the second section, while the main goal of the thesis is summarized in the third section. Finally, we conclude this first chapter by presenting the general outline of this thesis. 1.1 Digital Control of Switching Mode Power Supplies: Pros and Cons The regulation of Switching Mode Power Supplies has been traditionally handled by analog controllers, providing the user with a high quality voltage or current source. In this section, the alternative consisting of replacing the analog board by a digital board is investigated in terms of its advantages and disadvantages. 1.1.1 Advantages As compared to analog control, digital control has a number of advantages [1-4]. Our goal in this paragraph is not to redefine the functionality of a traditional supply using what digital technology has to offer, but to give an overview of what benefits designers can expect from digital control. 1.1.1.1 Better Hardware Stability In digital control, the regulation of the power supply is done through computation rather than through a combination of analog components. Microprocessor based devices are therefore used. Instead of using analog signals, the computation is done internally inside the microprocessor by manipulating streams of bits. Because of this, the controller is less susceptible to radiated noise than its analog equivalent. This can be a major advantage where high power applications are concerned. 1 Also, quite often analog components may see their characteristics drift with time and temperature, whereas a digital device will always give the user the same performance. From a manufacturer's point of view, this can be a major advantage since the manufacturer can provide stable and consistent products in different operating environments. 1.1.1.2 Cost Effective Solution Digital control boards are increasingly cost-effective as compared to analog control boards because of a number of reasons briefly summarized below. Due to its very nature, a digital control board has much less components. For instance, a digital board will include a microprocessor, a crystal, most probably some memory banks and A / D converters and maybe an additional D/A converter chip, whereas an analog board will have a number of resistors, capacitors, analog components and possibly logic chips for protection purposes. A digital control board is also versatile. The same board can be used on the products of the same series, and can also be extended to different applications. As a result, since the only difference between the two control boards resides in their program rather than the hardware structure, the manufacturing process of the power supply can be simplified. For a long time, one of the major disadvantages of digitally controlled power supplies has been their rather high cost, limiting their use to only very limited applications. However, the current trend shows that microprocessor based devices have begun to be cost competitive with analog components. Today for instance, a Digital Signal Processor (DSP) can be bought for as little as $5 U S D . According to some DSP manufacturers, the goal is to reduce their cost to less than $3 U S D in the near future [3]. The same trend can be observed in the microprocessor industry. 1.1.1.3 Computational Power Because of its programmability, a digital control board allows the designer to develop more complex "intelligent" control schemes, including high level security, monitoring functions and communication in the power supply. The same microprocessor or DSP can therefore be used for a number of different tasks, ranging from the control to monitoring functions, thus eliminating the need of having dedicated devices for each function. 1.1.2 Drawbacks Despite the advantages of functionality, flexibility, and price, digital technology has several disadvantages that must be overcome before it can be considered for wider applications. 2 1.1.2.1 Lower Perform ances The major drawback of digital control is the limited control loop bandwidth. The additional delays resulting from the computation time and the zero-order-holder degrades the stability of the closed loop system. A s a result, the bandwidth of the controller is reduced. In SMPS applications, this could be a major issue since the specification for power supplies are usually very tight, especially for high-end products. Also, quantization errors and limited word length are known to affect the control algorithm. This used to be a major concern in the early days of digital technology, where only-8 bit devices were available. A lot of work has been done in this domain to reduce these factors by taking them into account in the algorithm itself. Nowadays, with 16-bit technology, this problem tends to disappear or be much less severe. However, in any case, quantization noise and limit cycle effects have to be assessed beforehand to validate the viability of the new design. 1.1.2.2 New Technology For the majority of power supply manufacturers, digital technology is new, and the investments needed to cross the gap between analog and digital are huge. The development costs associated with the design of a digital control board is much higher than that of an analog control board and manufacturing a prototype is a lengthy task. Moreover, new skills are needed for the digital control design. For instance, the selection of the microprocessor is a key issue in the design. Designers have to make sure that they will be able to meet the real-time constraints imposed by their control algorithm and the additional functions they choose to implement. 1.2 Problem Statement and Literature Review Nevertheless, the numerous advantages of digital control versus analog control make this technology very attractive. The main issue addressed in this thesis is how to compensate for the time delay inherent to the digital control structure, and how to enhance the control loop performances. The problem of compensating for a time delay in a control loop can be considered either in the continuous or the discrete time domain. In the first case, the time delay compensation can be achieved using a derivative action. In the second case, a Model Based Predictive Control is used to predict the future process output, thus compensating for the time delay. These two approaches are discussed below. 3 .2.1 Derivative action Let's consider the analog control loop represented in Fig. 1.1. u(s) G{s) r Controller Delay Process Fig. 1.1 Block diagram of the control loop of a process with delay The delay x det is chosen to be a multiple of the sampling period T , that IS Tfel— rt" 1 • s s When dealing with analog control structures, a commonly used technique to improve the stability of the system is the derivative action. It consists of adding an additional zero to the controller structure which will eventually introduce a 90 degrees phase lead in the control loop. To illustrate the effect of the derivative action, let's consider a classical PI compensator. There are different ways to add a derivative action to this controller. The interacting structure is one of the most commonly used: G (S) PJD = K- 1 1+X; • S (1.1) As shown in Fig. 1.2, the term (l + x • s) acts on the input of the controller as a linear extrapolation over d a span of x d seconds, thus providing the PI control structure with a prediction of the future error. s(0 A ,e(f-x ) rf e(t + x ) d d e (0 at Fig. 1.2 Effect of the derivative action of the interacting PID controller Therefore, to compensate for the delay, we would choose x d x . del 4 There are three major limitations to this scheme. First, the addition of a zero increases the gain at high frequency and thus increases the noise sensitivity of the controller. This limitation is particularly present in switchmode power supplies where the feedback quantities have strong switching harmonic components. This problem is usually solved by implementing an additional low pass filter with the derivative action. The PID controller becomes: G (S) = K- P!D 1 + *d •• 1+- (1.2) 1+ ^ - 5 , N J Where TV is usually chosen between 4 and 20. Second, another limitation is that the prediction is performed on both the process output and the setpoint of the control loop. In servo problems, this has to be avoided in order to limit the overshoot of the control action in presence of setpoint changes. In some applications, a setpoint weighting technique [6] can be implemented using the expanded form of (1.2): ; d T x \i x GPID( ) S = K — 1+ -+ - d J + 1+ \i x + x •s (1.3) N d J x The control action u(s) is calculated as: \i x u(s) = k • — d J •Srf(-S) ( i+ d)x +x x 1+ v - d x +X J (1.4) N With: ^) = y (s)-y(s) re/ (1.5) Zd( )= -y f( )-y( ) s b s s re Where 0 < a < 1 and 0 < b < 1. It can be noted that a and b do not influence the response to load changes. Decreasing a towards zero reduces the overshoot on setpoint changes, while setting b to zero avoids the large derivative action on setpoint changes. Finally, the third limitation of using a derivative action is that the prediction does not take into account the future changes in the process output. As a result, the prediction span of the derivative action 5 is often limited to very short periods, and therefore cannot be used to predict over a large horizon [5]. In many cases, the derivative action would only be efficient to compensate for a fraction of the delay. 1.2.2 Model Based Predictive Control In computer controlled system, the compensation of time delays has been an early subject of study and has led to a variety of techniques, all of them based on the knowledge of the process model. As such, they are commonly designated as Model Based Predictive Control. A popular model based predictive technique is the Smith Predictor introduced by O.J.M. Smith in 1957. The block diagram of the predictor is represented in Fig. 1.3 where H (z) m is the process model. • e(z) yf re G(z) z — Yl H(z) (\-z~")H (z) m Controller Fig. 1.3 Smith Predictor structure The controller input s(z) results from the summation of the process true output y(z) with the calculated response of the block (l-z~ JH (z). In the ideal situation of perfect modeling, that is n> m H (z) m = H(z), the controller will behave as i f the controlled process was delay free. The additional feedback from the actual process output is used to give information on load disturbances and modeling errors. The major drawback of the Smith Predictor comes from the heavy calculations needed to evaluate the response of the process model. In some cases, the model used to represent the process can be simplified to a lower order. Also, the Smith Predictor can be difficult to tune if the plant model is poorly identified or i f large non-linearities in the process itself makes it difficult to formalize into a difference equation. It can be noticed that the Smith Predictor is not solely restricted to the discrete time domain but can also be implemented in a continuous time domain scheme. A n interesting application of the Smith 6 Predictor can be found in [8] where the right half plane zero of a boost converter is compensated, leading to a much improved phase margin. The controller G(z) associated with the predictor is often a PI controller. However, this structure leads to an easier tuning when using the Internal Model Control concept introduced in the early 80's by C E . Garcia and M . Morari [7] (see Fig. 1.4). In this case, the controller is reduced to a simple gain or filter followed by an approximation of the inverse of the process model without delay. In the ideal case, i f the model and the inverse are exact, it is sufficient to take G(z) = 1 to get a perfect compensation of any load disturbance. Quite often though, the inverse has to be multiplied by a pure delay to keep the causality in the system. To improve the robustness and reduce the effect of model uncertainties, it is common to use a first order low pass filter structure for G(z). w(z) -d Z G(z) H(z) y(z) z-"H (z) m Controller J Fig. 1.4 Internal Model Control structure The structure of the Smith Predictor has been the basis of a number of technical papers [9-12]. For the major part, those papers assess the problem of the loss of robustness of the predictor in the presence of unmodeled dynamics. It appears that special care has to be taken if the model of the process is not fixed and perfectly defined. The eventual changes which can occur in the model have to be assessed properly in order to determine if the close-loop system will remain stable in any operating condition. This weakness of the Smith Predictor where robustness is concerned is one of the major limiting factor of this technique. A solution consists of using an adaptive algorithm which modifies the coefficients of the model by minimizing a performance index representing the difference between 7 model and process response when exited by the same inputs. Adaptive schemes are, however, very demanding in calculation and are reserved mostly for slow processes with large non-linearities. 1.3 Thesis Objectives In this thesis, we restricted our study to high-end dc power supplies. Because of their very tight specification concerning the output voltage quality, their control is still mainly based on analog technology, even though few attempts have been done in the past to develop fully digital prototypes. One of the major reproaches was that there was no microprocessor which could provide enough computational power to ensure the proper control of the power supply [2]. The primary objective of this thesis is to improve the control performance of a digital dc power supply in terms of dc bus ripple rejection and load change compensation. This can be achieved by compensating for the time delay introduced by the inherent digital structure of the controller. To be considered practical, any new digital control scheme for this particular application must comply with the three following requirements: i. no modification of the circuit in terms of topology and sensors position should be necessary, ii. the design of the controller parameters should not require any additional tuning as compared to a conventional controller and should remain similar to the existing traditional control design. iii. since real time constraints can be very tight, the modifications of the control structure in terms of algorithm complexity must remain as minimum as possible. The second objective is to propose a control structure which improves the computational efficiency of the algorithm. The advantage of using advanced microprocessors or DSPs is that these devices can handle other functions than only the control of the power supply. B y reducing the amount of computational resources needed for the control calculations, more functionality can be programmed into the control board. The other objectives are the assessment of the quantization, word length and limit cycle effects on the control performance. The validation of the new control concepts is provided through simulation and experimentation. 8 1.4 Thesis Outline This thesis is organized as follows: Chapter 2 details both the power circuit of a typical dc converter based on the full bridge topology and different current mode control schemes. The main sources of disturbance are also investigated and their influence on the output voltage quality discussed. In Chapter 3, a conventional digital controller based on the average current mode control scheme is designed and applied in simulation to a full bridge converter. The chapter begins with a description of digital control specificity by comparing a digital control loop with its analog equivalent. Different design approaches are presented. Simulations are extensively used in this chapter to assess both the control performances and the influence of the quantization noise and the limit cycle phenomenon. Finally, general comments concerning the choice of A / D and D / A converters are given in this chapter. Chapter 4 proposes three control schemes, each of them based on a prediction technique. The first two schemes, referred as Modified and Simplified Predictor, are designed to improve the control performance through the compensation of the inherent time delay. A detailed analysis of these schemes is provided and validated through simulations. Results have shown that both schemes considerably improve the output voltage quality of the converter. The third predictive scheme is an extension of the Simplified Predictor, and is aimed towards the improvement of the computational efficiency of the control algorithm. Chapter 5 presents experimental results. Even though a modern simulation package allows the designer to simulate with good accuracy both power and control structures of any power electronics system, validation through experimentation has to be carried out in order to confirm the simulated results and identify eventual difficulties related to the implementation. The design of the converter is detailed and comparison between experimental and simulation results is also provided. Finally, Chapter 6 concludes this thesis and identifies some areas for future research work. 9 Chapter SYSTEM II STRUCTURE In this chapter, a dc switchmode power supply is investigated in terms of power circuit and control structure. This system is subject to digital control techniques as proposed in this thesis. The analysis of the power circuit topology and its switching sequence leads to the derivation of the mathematical models describing the dynamic behavior of the converter. Different analog control strategies based on Current Mode Control are then investigated and compared in terms of dynamic response, noise immunity, circuitry complexity and functionality. 2.1 Power Circuit Topology and Modeling In this section, the power circuit of a full bridge converter is described and modeled. We assume the power converter is working in the continuous mode of operation at its nominal load. 2.1.1 Topology A full bridge converter can be represented as in Fig. 2.1. A n unregulated dc bus voltage v dc is derived from the ac mains by a diode rectifier. A full bridge inverter delivers a high frequency ac voltage V] to an isolation transformer. Two diodes connected at the secondary of the transformer rectify v, into a dc chopped voltage v . The switching harmonics of v are then filtered out by a lowe e pass L C filter so that only the voltage average value remains at the load. The rms amplitude of v can t be modified by adjusting the switching pattern of the inverter, thus regulating the output voltage. In Fig. 2.1, m is the transformer turns ratio, defined as the ratio of the number of primary turns over the secondary turns. Both secondary have the same amount of turns. 10 '£11 Dl 1 X ->- OH AC- Vdc D2 Q4 ii H c 'D2 PWM Generator Fig. 2.1 Full bridge dc-dc converter The switches gating pattern are shown in Fig. 2.2. To avoid short circuiting the dc bus, the gating of the upper and lower switch of the same leg is complementary. a ;04 ON OFF] t4 to ON OFF to Fig. 2.2 Switching pattern In the figure, T xw represents the switching period. According to the switching pattern, we can differentiate four states of operation which are represented qualitatively in Fig. 2.3. 11 Fig. 2.3 Qualitative switched waveforms of a full bridge converter in steady state From those waveforms, we can notice that States 1 and 3 correspond to the active mode of operation of the converter. During these states, energy is transferred from the source to the load, part of it being stored in the output filter inductor L. Conversely, when the primary side of the transformer is short circuited (States 2 and 4), the energy used by the load is taken from the output inductor and the magnetizing current /,„ of the transformer is shorted by the inverter switches. Since no power is drawn from the inverter, this mode of operation is called passive. The ratio between the duration of the active state and the switching period T xw is called duty ratio and noted d. We have the general relations: (2.1) It can be easily understood that increasing the duty ratio of the switches (i.e. the duration of the active state) results in more energy sent to the load. Consequently, both inductor current and output voltage rise. On the other hand, a low duty ratio results in a low output voltage. This relationship between duty ratio and output voltage serves as a basis for the control of the converter. 2.1.2 Continuous Time Domain Model A switched power converter is a highly nonlinear system because of the switching operation. The main goal of the following analysis is to linearize the model so that classical control design tools such as the Nyquist stability criterion, the root locus method, and the Bode plots can be used to design the controller. The state space averaging technique, proposed by Middlebrook, Cuk, et al., is used here for the linearization. From the previous analysis, it has been shown that the operation of a full bridge converter can be simplified to an active and passive state, such as represented in Fig. 2.4. k k ~ k: i i - k: L L a) Fig. 2.4 States of the system (continuous mode) a) Active state (0 < t < d. T ) b) Passive state (d. T < t < T ) sw sw sw 13 Let's consider that an equivalent resistive load R is connected at the output of the power stage. From the analysis of the active and passive states, we can deduce two sets of equations: at [ -{'L R ~ic) c + r -i +L-^ L m +v L ->c) c + v c L +r (2.2) (passive state) (2.3) r -i =0 c Rii -i ) + (active state) =0 c c -'c = 0 Let's choose the inductor current i and the capacitor voltage v L c to be the state variables representing the system. Introducing: C- (2.4) dt (2.2) can be written under a state space form as: X =A X+B C X r -r +R-r c Where X = L +R-r L L-(r +R) R c "1" R-r ,B = T , c = r +R 0 L-(r +R) 1 C-(r +R)_ r c C-(r +R) (2.5) m R c c v dc v c R r +R c c c Using the same notation, (2.3) becomes: fx-A-X (2.6) K=C-X The active and passive state duration are respectively d-T and sw (\-d-T ). sw Averaging the state equations over one switching period leads to: X = A - X + B- dv -C-X m (2.7) 0 Considering that the state vector X, the duty ratio and the output voltage of the system are the sum of dc and ac components, we can extract from (2.7) two sets of equations corresponding to the dc and small signal ac models of the converter: 14 R+r m L R+r m R R+r Vdc L (2.8) (small signals) (2.9) D m L (dc) x = A x+B I \ m m v =C-x 0 Where the superscript"~" denotes small signal ac values. Given the nominal dc output voltage V on as well as the output power rating P 0 of the supply, we define the nominal equivalent resistance R„ as: (2.10) R„=•* o,n As shown by the steady state model, it is possible to pre-calculate the duty ratio for which output voltage and output power reach their nominal value. For instance, the nominal duty ratio of the converter can be determined as: in A. (2.11) dc,n Supposing v constant, the s-domain transfer functions can be easily derived from (2.9) by using dc the Laplace transform operator. We find: R vd ) d(s) s T As)v kM d{s) s -L-C-(r +R) + s-(R-C-r 2 c c L L C -(R + r )-s s -L-C-(r +R) + s-(R-C-r 2 c c L RCr -s Vg(£)_ s •L-C-(r +R) c + s-(RC-r c L + (R + r ) m L +R r 2 dc +r -r -C + L +R-C-r ) c L +l c = d(s) C + L + RC• r ) + (R + r ) m +r -r c +r -r c L V,dc C + L + RC-r ) L + (R + r ) m L (2.12) Since the capacitor voltage cannot be measured, only the inductor current and output voltage are of interest. As shown in (2.12), they are both modeled by second order transfer functions of identical natural frequency oo and damping £ . To simplify (2.12), we adopt the following notation: 0 15 (2.13) s + a„ T (s) = K. s +2-£,-(0 -s+ v (£> 2 o 2 0 Where: 1 ' 'dc L-(R + r ) c C-(R + r ) c 1 a. m (2.14) And: R+r L L-C-(R + r ) c ]_ R-C-r +r -r -C c ~T c +L+ L jL-C-(R (2.15) RC-r L + r )-(R + r ) c L These models result from the averaging of the converter operative states over one switching period. As such their validity is limited to a frequency range lower than the switching frequency. 2.1.3 Major Sources of Disturbance Dc bus ripple and load variations are the two major sources of disturbance encountered in the system. First, let's consider the dc bus voltage supplying the inverter. Such a voltage is generally obtained from the ac mains by a classical diode bridge rectifier such as shown in Fig. 2.5. For higher power outputs this structure would be replaced by a three phase diode bridge rectifier. 5 c. L O A D AC(120-240) Voltage doubler link Fig. 2.5 Line rectification 16 In many commercial power supplies, a link between the middle point of the input filter and the bridge allows the use of the supply in a 120 V or 240 V environment. In both cases, the theoretical nominal dc bus is 310V. However, the source resistance R and the limited action of the input filter capacitors have x to be taken into account. For instance, the source resistance reduces the average voltage of the dc bus whenever the load power becomes high. In an industrial environment, the resistance can be as high as half an ohm, resulting in a substantial voltage drop which has to be taken into consideration when setting the nominal operating point of the converter. Also, there is a low frequency voltage ripple which reaches its maximum amplitude when the converter is operating at the nominal power. For a single phase input, this ripple is essentially composed by harmonics at 120 Hz, 240 Hz and 360 Hz. These harmonics usually cannot be filtered out by the output filter. Other means must be used to reduce their effect on the output voltage quality. The second source of disturbance is related to the load itself. Power converters are designed to supply a wide variety of loads whose value and nature can change suddenly. Without any proper compensation the output voltage cannot reach its nominal dc value, resulting in steady state error. To evaluate the performance of the control action for load changes, the dynamic response of the converter is compared in terms of settling time and maximum overshoot and undershoot. 2.2 Control Circuit Structure Specification concerning the output voltage quality of SMPS can be quite stringent. As illustrated in the previous section, load changes and dc bus ripple have a great adverse effect on the output. Control loops must be properly designed to compensate for those effects. A common and straightforward control technique achieving the regulation of the output voltage can be performed by using a single feedback loop based on the output voltage itself [13]. However, the frequency response of the output voltage transfer function reveals that the stability margin is quite limited due to the second order L C filter. For application where the natural frequency co is high enough, a controller designed in the stable 0 frequency range would be sufficient to offer a proper regulation of the converter. Also, to further improve the control loop bandwidth, controllers offering a lead action can be considered. Techniques such as the K factor [14] have been developed to tune those controllers. 17 For high power low switching frequency converters, the natural frequency co is seldom higher than a 0 few hundred hertz. In this case, even the lead action provided by an additional zero would not be sufficient to compensate for the phase margin. To solve this problem, an inner current loop, so called current mode control, is introduced. To present this control method, let's first consider the inductor current transfer function 7} (5). As compared to J (s), T (s) has its numerator zero at a very low v t[ frequency. This zero has a strong cancellation effect on one of the pole, resulting in a much lower phase lag characteristic. Indeed, as shown in Fig. 2.6(b), the maximum phase lag does not exceed 90 degrees. (a) (b) Fig. 2.6 Modelsfrequencyresponse (a) Output voltage transfer function (gain and phase) (b) Inductor current transfer function (gain and phase) In current mode control, the higher stability characteristic of the inductor current is used to achieve a better bandwidth in the regulation of the output voltage. Instead of designing a controller which sets directly the duty ratio of the switches according to the output voltage feedback, in current mode control the output voltage loop sets a reference for the inductor current. A faster inner loop based on 18 the current feedback will then track this reference by updating the duty ratio of the switches. Assuming the inner loop is much faster than the outer loop, the regulation of the output voltage is not based on the second order transfer function T (s) any longer, but on a first order function defined as: v T (s) K T utis) = —— = — v v s + a 0 (2.16) There are many different current mode control schemes. Only those based on a constant switching frequency are investigated in this work. They can be classified into two groups, that is Peak Current Mode Control (PCMC) and Average Current Mode Control ( A C M C ) . A recent control scheme called One-Cycle Control (OCC) is also briefly discussed at the end of this section. 2.2.1 Peak Current Mode Control In the Peak Current Mode Control scheme the instantaneous value of the inductor current is used to control the switches. To illustrate the concept of P C M C , let's consider a one-quadrant buck topology (see Fig. 2.7). 19 (c) Fig. 2.7 Concept of PCMC based controllers a) Application to a buck converter b) Principle c) Slope compensation technique Let i / be a fixed peak current reference for the inductor current. The reference is compared to the Lre measured current i . As long as i L At t = t AP L is below the reference, the inverter is maintained in its active state. (see Fig. 2.7(a-b)), the transition from the active to the passive state is triggered by the flip flop circuit. In order to guarantee a fixed switching frequency, all inner loop control operations are hold till the next switching period. Because the instantaneous value of the inductor current is used in the feedback loop, this control scheme has high dynamic performance. Another interesting feature is that a very efficient protection against short circuits is automatically provided by setting properly the maximum allowable peak current. Whenever this limit is reached, the inverter is switched to its passive state. We can also note that any ripple present on the dc bus is automatically compensated at each switching cycle, which guarantees an almost ripple-free output voltage. Furthermore, applied to the full bridge topology, a peak current mode controller based on the primary side current feedback corrects automatically the transformer flux unbalance, improving the reliability of the power supply. However, a peak current mode controller is inherently unstable for any duty ratio greater than 0.5. To prevent the subharmonic oscillations resulting from this instability, a slope compensation waveform is added to the current reference, as shown in Fig. 2.7(c). Typically, the slope of the compensation waveform is equal to one half the decaying slope of the inductor current. Taking the nominal operation point as a reference, the slope a of the compensation waveform is approximated as: 20 ® =1.1.V 2 Z -T (2.17) v (2.17) shows that a depends strongly on the output voltage. In applications where the output voltage can be set by the user, the slope compensation waveform has to be modified accordingly. As a result, the complexity of the circuitry is increased. Another important limitation of the P C M C scheme is its high sensitivity to measurement noise, which perturbs greatly the inner loop controller. The voltage compensator G (s) is designed using (2.16). Indeed, we can consider that the inner v current loop has a much higher dynamic than the outer voltage loop, and as such it can be represented by an unitary linear gain. A PI structure is selected so that there is no steady state error on the output voltage. G (S) V 1+- =K V 1 (2.18) Non-linearities such as saturation blocks and saturable integrators for anti-windup have to be added to the control structure. It's important to note that the mathematical design of the control parameters is limited to linear systems and therefore does not take into account those non-linearities. Since they have important effects on the dynamic behavior of the converter during large transients, tuning based on trial and error is sometimes needed to set the control parameters more adequately. The resulting control structure of peak current mode controllers is represented in Fig. 2.8. slope compensation • saturation o,ref K v flip-flop S Q R O trigger active state trigger saturable integrator Fig. 2.8 Peak current mode control schematic 21 2.2.2 Average Current Mode Control In the Average Current Mode Control scheme [15], the inner loop controls the average of the inductor current. The control problem is reduced to the classical design of two compensators, G (s) and v Gj(s) . The block diagram is shown in Fig. 2.9. V, o,ref d(s) G (s) v (s) 0 out( ) T v s Fig. 2.9 Average Current Mode Control block diagram To provide the control loop with the mean value of the inductor current, a first order low pass structure is generally added to G ( s ) . This filter acts not only on the measured current but also on the reference ; provided by the outer loop, and by extension on the measurement of the output voltage. In some cases, a PI structure might already provide a good enough filtering action. For higher rippling currents, a stronger second order filter might be needed. Having it on both the outer and inner loop will reduce the bandwidth of the whole system. A more appropriate solution is to implement the filter only in the feedback path of the inner current loop. The advantage of A C M C as compared to P C M C is that it has a higher noise immunity. Also, since it controls the average inductor current, this scheme is useful in applications where a constant current source is needed, such as battery charger circuits [16]. However, this kind of controller does not provide an efficient protection against short-circuits and some additional circuitry might be needed. General guidelines concerning the design of the outer and inner loop compensators are given below. 2.2.2.1 Inner Loop Control Design A common choice for Gj(s) is a conventional PI control structure. 1 1+ T i (2.19) -j s The advantage of this compensator is that it introduces a pure integral action in the inner open loop. Noticing that the average of the inductor current is equal to the output current, the inner loop can 22 therefore be used to provide an output current regulation. In some cases, a single proportional gain can also be considered [17], thus offering lesser complexity and higher phase margin. However, depending on the value of its gain, a steady state error will appear. The first step in calculating both proportional and integral gains consists of defining the cross over frequency of the controller. Since the current loop phase delay does not exceed 90 degrees, the cross over frequency can be set quite high. However, it's common practice to limit its range to around one fifth of the switching frequency. 2.2.2.2 Outer Loop Control Design In Average Current Mode Control, the bandwidth of the inner current loop is not wide enough to neglect its effect on the outer loop. A s a consequence, the inner close loop transfer function has to be taken into account in the design of G (s). The equivalent open loop transfer function is: v 1 (s + a )- 1 + s•X v T (s) = eq K -K V (2.20) I s +2-£ -(£> -s + Q>l+K -K -(s 2 > 0 J i + a )I s•x Since T (s) does not have any pole at the origin, the proper regulation of the output voltage cannot be eq achieved without including an integral action in the compensator. The commonly chosen structure for G (s) is also a PI. A derivation action might be needed in some specific cases. In order to limit the v high frequency amplification associated with the derivative term, an additional first order low pass function is generally added. G (s) v can be evaluated by defining the minimum allowable phase margin at the cross over frequency. The integrator time constant and the gain of the controller can be set accordingly. The analog control structure corresponding to the A C M C scheme is represented in Fig. 2.10. saturation r V,o,ref filter ^ > K, saturation s + a, iAvh i saturable integrator saturable integrator Fig. 2.10 Analog control structure for ACMC schemes 23 2.2.2.3 Load Current Feedforward It can be easily shown that the open loop system controlled by the output voltage compensator is strongly dependent on the output load resistance/?. For instance, the gain of T (s) is equal to: eg T (0) = R (2.21) eq As a result, the close loop system will behave differently when connected to different loads. In some specific cases, the system might even become unstable. Since it would be difficult to guarantee mathematically the stability for any load, a common practice is to reduce the controller bandwidth to improve the robustness of the system. Load sensitivity can be a very serious issue when designing power supplies for highly demanding applications. For instance, to power the new generation of microprocessor chips, as the device voltage goes down, a higher current is needed and the rate of load current step changes can reach high values such as 30 A p s " ' [23]. To reduce the influence of the equivalent load resistance, a solution using the load current as a feedfoward quantity was introduced in [21] and [22]. It can be shown that the control law (2.22) reduces significantly the load sensitivity [24] for any buck-type topology: d(s) = K [i ( )-(i (.s)-i {s))] r Ltref S L 0 (2.22) This control law is equivalent to a conventional A C M C based on the capacitor current feedback. The gain of the equivalent transfer function T (s) is then : eq V°) =T ^ — K < - — ( 2 " 2 3 ) As compared to (2.23), the use of the capacitor current reduces considerably the influence of the load on the gain of the equivalent system, thus ensuring that the design of the voltage compensator leads to a stable controller for any passive load. However, this particular implementation is not often used since it is generally difficult and expensive to measure the capacitor current. Also, this scheme does not provide any control on the average current delivered to the load. It is therefore difficult to limit the maximum average inductor current which can flow through the inductor without saturating its core. 2.2.3 One-Cycle Control and Charge Control One-Cycle Control is a recent current mode control scheme, proposed by K . M . Smedley and S. Cuk in 1991 [18,19]. The interest relies on the fact that this technique takes advantage of the nonlinear nature of the converter by controlling the average value of a switching quantity (primary side current, 24 chopped voltage of the output rectifier, etc.) at every switching cycle, thus providing fast dynamic response and automatic dc bus ripple compensation. Also, this scheme is quite insensitive to noise measurement and its implementation is simple. In the Charge Control scheme proposed in [19], the instantaneous switch current is integrated and compared to a fixed reference (see Fig. 2.11). In this particular case of O C C , the integrated value of the current corresponds to the total charge drawn from the source to the load. In the same fashion than in peak current mode control, when the reference is reached the inverter is turned into its passive state and the integrator performing the calculation of the charge is reset and disabled till the beginning of the next switching cycle. Charge control is characterized by subharmonic oscillations when operating at low loads. ref V (a) (b) Fig. 2.11 Charge and Quasi-Charge control structure (a) Schematic (b) Waveforms In [20], a Quasi-Charge Control scheme is proposed. Instead of using a pure resetable integrator at the output of the current sensor, a R C circuit providing low pass filtering is connected in parallel to a switch which is turned on during the passive state of the converter (see Fig. 2.11(a)). According to its authors, this hybrid solution between an average current mode control and a charge control scheme provides a better noise immunity. 25 2.3 Summary In this chapter, the switching circuit and the different applicable control structures have been reviewed. Depending on the application, designers will have to choose between either a peak current mode control or an average current mode control structure. For conventional converters working at a fixed output voltage, a peak current mode controller should be a better solution since it offers high bandwidth, inherent short circuit protection and automatic dc bus ripple and flux-unbalance compensation. For more sophisticated power supplies where the user can set the output voltage level at any desired value or can choose between having the supply delivering a constant voltage or a constant current, the average current mode controller represents a better solution in term of circuit complexity and robustness. One-cycle control and charge control schemes present interesting features but the design of the control structure is more difficult. Also, they do not offer any short circuit protection or average current limiting characteristic. To comply with existing specification, additional circuitry is therefore needed, reducing the economic interest of these schemes. The use of instantaneous values in peak current mode control and one-cycle control makes them poor candidates for an implementation on microprocessors. In some cases though, the voltage compensator can be implemented in digital while the inner loop remains implemented in analog. But since the objective of this work is to implement a fully digitally controlled SMPS, the average current mode control will be used since it is the only current mode control scheme which exhibits the properties of a sampled system [16]. 26 Chapter DIGITAL III CONTROL DESIGN In this chapter, a conventional digital control based on the average current mode control scheme is designed and applied to a full bridge converter. Simulations are provided to validate the results of the design. In the first section, the inherent elements in digital control, that is zero-order-hold, analog-to-digital converters, computational time delay and anti-aliasing filters are discussed. Then, a control design based on the digitalization of continuous time domain controllers is introduced and applied to a given converter. Comparisons between analog and digital control in terms of dc bus ripple rejection and load change are also provided. Finally, the quantization effects due to the inherent digital structure is assessed and conclusive remarks are provided at the end of this chapter. 3.1 From Analog to Digital As compared to a classical analog feedback control system, a digital structure will include new elements affecting the control loop internal gains and stability. To illustrate those effects, let's consider the analog close loop system of Fig. 3.1(a) where a controller G(s) regulates the output of the process H(s). A small first or second order low pass filter represents the limited bandwidth of the sensor or any eventual additional filter designed to damp unwanted high frequency noise. The parameters of such a filter are usually selected so that the associated lagging effect does not have noticeable effects on the overall stability of the system. In some very noisy applications, however, a stronger filtering action might be needed and the control parameters must be derated accordingly. Let's consider the equivalent digital representation of the analog system in Fig. 3.1(b), where T is s the sampling period of the sampler. Four new elements are added to the forward and feedback paths: i. two quantization blocks representing the A / D and D / A limited resolution, ii. a time delay accounting for the computational time, iii. a zero-order-hold representing the holding effect of the D / A converter, iv. an anti-aliasing filter. 27 y r e f ^ y Y - > u(s) G(s) (a) Quantization yref Zero-\>rderhMd D(z) Computational time delay ZQH T < o 7 " Quantization Anti-aliasing fdter Discrete time domain Continuous time domain (b) Fig. 3.1 Digital equivalent of an analog control loop (a) Analog control loop (b) Digital control loop Those elements are inherent to any digital control systems. Their effect on the control loop design and the control performance is discussed below. 3.1.1 Quantization Effect of the A / D Converter Whenever a measured analog signal is sent to a digital control structure, an analog-to-digital converter is needed to perform the discretizing and quantization of the incoming signal. A / D converters are characterized by a maximum sampling rate and a limited resolution expressed in bits. 28 The resolution of the A / D converter determines the number of discrete steps which can be used to represent the measured quantity. Let R be the desired measurement range of y(s). One quantization g step q is equal to: q = R -2~ (3.1) b g Where b is the resolution of the converter and q is expressed in the same unit as R . When selecting the g A / D converter, the designer has to make sure that the desired accuracy of the regulated output of the process is greater than q, otherwise the digital controller will not be able to get a proper feedback when reaching the steady state which will lead to a large offset. Let qj .i be the minimum desired accuracy. e The minimum requirement of the A / D resolution is given by: b > ^\n{R j J )-\n(q ) des ( 3 2 ) In 2 The quantization of the analog signal does not have any influence on the stability of the close loop system [25]. The only effect is the addition of measurement noise which will induce a limit cycle phenomenon. The quantization effect of the analog signal used to be a major issue in the early days of microprocessor controlled processes. In those days, only the 8-bit technology was available, offering a maximum resolution of 256 discrete steps. In order to increase the accuracy of the measurement, different techniques can be implemented: i. Level shifting: In many case, it is possible to reduce the measurement range to a smaller window around the nominal working point of the output process. The quantization step q is then reduced. ii. A / D cascading: When the output of the process can vary across a wide range of values, such as in ac power supplies, multiple A / D converters are cascaded over the measurement range, each of them measuring only a specific window. The signal is then reconstructed by the microprocessor. This technique results in higher complexity and cost since more analog parts and A / D channels are needed. iii. Over-sampling: Instead of acquiring the input just once at every sampling time, a fast succession of conversion can be done. The sampled output is then calculated taking the mean value of the group of samples. This technique can be implemented only if high sampling rate A / D converters are available. Also it increases considerably the computational time since more sampling is needed. 29 Nowadays, with the common use of 16-bit technology, the limitation of digital control structure due to the quantization problem tends to disappear and those techniques are used only in systems having very tight specifications. Quantization effects can also be generated by D / A converters. However, the D / A converter has less impact on the controller performance since no more calculations are performed on the D / A output data. If the resolution is poor, the control variable will then oscillate between two levels in the steady state. 3.1.2 Computational Time Delay Once the A / D conversion is achieved, the quantified output value y„ is processed by the control algorithm in order to determine the proper control action u„. Between the sampling of the process output and the moment the control variable is updated, some time will have elapsed due to the limited working frequency of the microprocessor and the A / D - D / A conversion time. This delay is referred in this thesis as computational time delay. The Laplace transfer function of a pure delay is given by: G (s) = e-^' (3.3) s del Where x del is the total duration of the delay. x det depends mainly on how the control algorithm is implemented. The more straightforward implementation consists in updating the input of the control variable as soon as the calculations are achieved. The resulting delay only depends on the C P U frequency clock, the A / D sampling rate and the eventual D / A conversion time. Thus, x del can be minimized by choosing higher rated components. In systems where the computational delay is small as compared to the sampling time, this implementation is preferred. A n alternative is to update the control variable only at the beginning of the next sampling period, thus ensuring a fixed and known delay which does not depend on any software glitches which might shorten or lengthen the number of computational cycles. In this case x del is equal to a complete sampling period T . In systems where T is only slightly longer than the computational delay, this s s implementation is often preferred. A pure delay is a non-minimum phase element which degrades considerably the stability of the system. The lagging effect of (3.3) is represented in Fig. 3.2. 30 Phase (deg.) io-r, 100-r. Fig. 3.2 Phase lag of a pure time delay In switchmode power supplies, only the last option can be considered due to the switching nature of the process. To illustrate this last point, let's consider the switching pattern of a buck converter. Typically, the sampling time is equal to the switching period. The duration of the control algorithm is equal to x . c It is shown in Fig. 3.3(a) that updating the control variable right after the control calculations does not have any noticeable effect on the switching pattern before the next sampling period. It might even cause serious problems during large transients since the gating of the switch can be triggered twice in one switching cycle, such as shown in Fig. 3.3(b). PWM carrier & duty ratio Switching pattern (b) (a) Fig. 3.3 Duty ratio update in digital scheme (a) Late duty ratio update (b) Two switching actions during the same switching period 31 However, this can be avoided by designing a P W M generator which includes additional circuitry preventing multiple switching during one cycle. Also, it can be noticed that, as long as: d-T >x s (3.4) c The first implementation can be used successfully. However, as the power supplies are operating at increasingly higher switching frequency, the condition (3.4) is difficult to meet in the majority of applications. 3.1.3 Zero-Order-Hold The interface between a discrete signal and its continuous equivalent is achieved by a zero-order-hold which reconstructs the continuous signal based on a train of pulses by holding its input during a complete sampling cycle. The effect of the hold circuit is described by the following Laplace transfer function: l-e~ 'T s GHO(S) = — (3-5) T -s s When plotting the Bode plots of this function, it appears that the gain of a zero-order-holder is similar to the gain of a first order low-pass filter whose time constant is half the sampling period, with the advantage that any frequency multiple of the sampling frequency is completely filtered out. However, it is also clear that the lagging effect of (3.5) is much stronger than a single first order filter (see Fig. 3.4). In fact a zero-order-hold has a non-minimum phase characteristic which reduces the stability of the open loop. It can be shown that the phase of a zero-order-hold is similar to the phase of a pure delay of half of the sampling frequency. 32 Fig. 3.4 Frequency response of a zero-order-hold 3.1.4 Anti-Aliasing Filter For applications rich in noise, a strong additional low-pass filter is needed to damp the analog high frequencies contained in the measured signal so that the frequency folding effect inherent to any sampled system is avoided. Anti-aliasing filters are generally high order filters. Depending on the specification of the filter, different structures can be used. One of the most commonly selected structure for high-performance systems is the Bessel structure which offers a linear phase lag, and can be approximated as a pure delay in the control design [6]. Depending on the order of the filter, the equivalent delay can reach several sampling periods. For switchmode power supplies, where the sampling frequency is much higher than the highest dynamic of the process, the anti-aliasing filter can be reduced to a high frequency low-pass filter with a high cut-off frequency whose influence on the stability of the open loop system can be neglected in the frequency range of the cross-over frequency of the controller. 3.1.5 Discussion The above discussion shows that the inherent structure of a digital controller degrades seriously the stability of the overall system. Elements such as zero-order-hold and computational time delay must be taken into account in the controller design. As a consequence, the bandwidth of the controller will have to be reduced as compared to a pure analog control design. To benefit from the inherent filtering action of the zero-orderhold, it is clear that the sampling time T, should be a multiple of the switching period T . Also, in order sw 33 to reduce the phase lag introduced by the zero-order-hold and the computational time delay, the best choice is to take 7^ = T . sw The quantization effect of the A / D and D / A converters, as well as the limited word length of the microprocessor will also degrades the performances. However, this problem is less critical when using 16-bit technology. 3.2 Discrete Equivalent of Continuous Time Domain Controllers Two basic approaches can be used in designing a digital controller. The first approach is to first design the controller in the s-domain. However, as compared to other analog control design, the zero-order-hold effect and the computational time delay have to be included in the calculation. The resulting compensator is then digitized in order to obtain a difference equation which can be directly programmed. The advantage of this approach is that the control design is achieved using well-known tools such as frequency analysis and Nyquist stability criteria. The second approach is to calculate a discrete equivalent of the process model and use the root locus method in the z-domain to design a proper compensator. This technique is more difficult to use since there is no clear representation of the effect of the compensator poles and zeroes. In this project, we chose to design the controllers with the first approach to be able to compare the control performance with existing analog controllers. The main issue of this approach resides in the derivation of the equivalent z-domain transfer function D(z) from the s-domain compensator G(s): m G{s) = if (3.6) ;=0 This particular problem has been the subject of many technical papers [1, 27-29]. Only the most common methods are briefly reviewed below. 3.2.1 Approximation Methods In many cases, a z-domain equivalent of G(s) can be approximated by substituting the Laplace operator s with a function of the discrete operator z. The common approximation functions are the 34 Backward Euler method and the bilinear transformation (also called Tustin approximation). They are expressed as: s= s= 1 z-l 2 z-l (Backward Euler) (bilinear transformation) T, z + l (3.7) (3.8) Using (3.7) and (3.8), D(z) is given by: ' z - l 2>^ D(z) »=0 " /=0 s v * J 1 ' z - l 1 D(z) = (=0 Z«/ ;=0 (Backward Euler) (3.9) v s v * J l f „ V 2> v z-l z+l (bilinear transformation) (3.10) z-l z +l Those methods are accurate when the sampling rate is in the order of ten times smaller than the smallest time constant of the compensator. The bilinear transformation gives a better mapping than the Backward Euler method in terms of the location of the pole and zeroes of the transfer function. 3.2.2 Matched Pole-Zero Method The operator z _ 1 denotes a pure delay and can be written as : z- =e-° * x T (3.11) In the pole-zero match method, the compensator G(s) is first factored so that each pole and zero are explicitly defined: m G(s) = K-^ (3.12) i=0 35 Then, the poles and zeroes of D(z) are calculated using (3.11) so that they "match" the analog poles and zeroes of G(s). Please note that D(z) has to be adjusted so that both D(z) and G(s) have the same gain. The equivalent discrete compensator can be written as: n n \.\-e-*- ' j T D(z) = K ;=0 -PrL z—e (3.13) Pi 1- i=0 -Pr s T The pole-zero match method is also called w-prewarping method [6, 26-27]. For high sampling rates, this method gives similar results than the bilinear transformation. 3.2.3 Discrete PI Compensator As stated in Chapter 2, a commonly used compensator found in switchmode power supplies is the PI structure: G (S) = K- PI i -L + (3.14) Expressing (3.14) in the form of (3.6) and using the approximation functions and the pole-zero match method, we find the following discrete equivalents for G (s): P} 1+D (Z) P1 = K- •z-1 z-1 T-2-x 2+T +2 •T T 4- 9 z-1 Dpi (z) = K — 2-T 1 D ,(z). P v l-e / x (Backward Euler) (3.15) (3.16) (bilinear transformation) -T/ z-e (matched pole-zero method) z-1 (3.17) Each of those expressions includes an integral action due to the presence of the unit pole. Also, when the sampling time becomes small as compared to the integrator time constant, those expressions tends to be equivalent. 36 3.2.4 Effect of Quantization When the sampling period is much smaller than the smallest time constant of the compensator, the location of poles and zeroes are close to each others and near z = 1. When implementing the difference equation on a microprocessor, the designer is confronted to the problem of rounding the compensator coefficients. As a consequence, the location of the poles and zeroes might shift, resulting in large discrepancies between the desired and actual behavior of the compensator [26]. In some cases, the resulting digital compensator might even lead to internal instability. In order to reduce the sensitivity of the rounding and quantization effects, it is preferable to expand D(z) into a series of elementary functions and use parallel programming to implement their discrete equivalents. In the case of the PI compensator, better discrete equivalents are obtained by keeping the proportional and integral actions separate: D (z) PI D (Z) P1 D P 1 = K +K — (Backward Euler) x z-l T z+l 2-x z-l T z T z-l (bilinear transformation) (3.19) (matched pole-zero method) (3.20) =K+K (z) = K + K (3.18) Also, since the integral action appears clearly in the difference equation, a structure similar to the antiwindup feature of the analog PI controller can be easily implemented in the control algorithm. Then, from a structure point of view, those functions are closer to an analog PI compensator. We can notice that both Backward Euler and matched pole-zero structures lead to the same controller. As a matter of fact, the polynomial ( l - z ) happens to be the exact equivalent of a pure _ l integrator. 3.3 Control Design and Application In this section, a digital controller regulating the output voltage of a full bridge converter is designed. The dc bus ripple rejection and load change compensation capability of the controller is compared with the performance obtained with an analog structure. Both analog and digital designs are based on an average current mode control scheme and follows the general guidelines given in the previous chapter. 37 3.3.1 Specifications The converter under study is an 1 kW full bridge power supply whose specifications and power circuit parameters are summarized in Table 3.1. The dc bus is obtained using a voltage doubler, such as indicated in Chapter 2. The resulting dc bus ripple at nominal load is about 16 V peak-peak. Other practical details concerning the hardware structure are given in Chapter 5. Table 3.1 Full bridge main parameters and specifications Value Unit V 100 V ' o,n ^'dc,n 280 V 1 kW 100 us Symbol Nominal values : Output voltage dc bus voltage Output power P 1 Switching period o,n T sw Transformer : Turns ratio m 2 Capacitor C, 2.6 mF Inductor Capacitor L C 1.8 6.9 mH mF c *20 mQ « 150 mQ Input filter Output filter : Parasitic elements : Capacitor ESR Inductor winding resistance r The maximum allowed output voltage drift is fixed to 100 mV rms, which corresponds to 0.1% of the nominal output voltage. This value is typical of high performance commercial power supplies. 3.3.2 Analog Control Design Following what has been presented in Chapter 2, the design of an average current mode controller for this converter is straightforward. A double PI structure is selected and the control parameters are derived based on the model transfer functions. They are summarized in Table 3.2. 38 Table 3.2 Analog control parameters Outer loop: Cross-over frequency Phase margin 1 K X 0.9 kHz 75 ° 17 A - V V 180 u.s v Inner loop : Cross-over frequency Phase margin 2 kHz 45 ° 0.12 A" 1 80 u.s The maximum average inductor current is set to 15 A . The duty ratio is bounded between 0.05 and 0.95. The saturation blocks and anti-windup integrators are adjusted accordingly. Finally, a first order low-pass filter is connected at the output of the inner loop PI. Its cutoff frequency is set to 10 kHz. This filter does not have any noticeable effect on the stability of the system. 3.3.3 Digital Control Design The design of the digital controller is first carried out in the continuous time domain. The resulting compensators are then discretized using the Backward Euler transformation method. The design of the inner and outer loop compensators follows the same steps as in analog control, with the exception that the effect of the computational time delay and zero-order-hold is added to the forward path of the control loop as shown in Fig. 3.5. As a result, the phase margin of the inner loop controller drops significantly and the cross-over frequency of the controller has to be reduced by more than 85%. Similarly, the outer loop bandwidth is also greatly reduced. The resulting control parameters are given in Table 3.3. o,ref G (s) v ^ G l(s) de G (s) h0 d{s) v w T (s) h v (s) 0 out( ) T s Fig. 3.5 Equivalent time-domain digital control loop block diagram 39 The maximum average inductor current and duty ratio limits are set to the same values as in the analog case. Also, since the zero-order-hold filters out the switching harmonics, there is no need of extra filtering. Table 3.3 Conventional digital control parameters Outer loop: Cross-over frequency Phase margin 115 Hz 45 2.9 A - V 1.38 ms 0 V Inner loop: Cross-over frequency Phase margin 280 Hz 35 ° 0.0165 A 1 - 1 570 us i x The resulting analog PI.controllers are discretized using (3.19). D (z) v and D (z) t are therefore expressed as: D (z) = 2.9 + 0.21v Z — ~ (3.21) X D (z) = 16.5-10" +2.9-10~ • — z-1 3 3 t There are different ways to implement the anti-windup for the integrator. One scheme is the incremental algorithm, where the integral action / „ is calculated as the sum of the past action I_ n x and a function of the error at time n: +/(e„) (3-22) / „ is then compared to an upper and lower limit corresponding to the anti-windup saturation block. If the limit is reached, the integral action is clamped to this limit. This method of calculating a discrete integral with anti-windup is represented in the block diagram of Fig. 3.6. 40 Sampling delay Fig. 3.6 Discrete PI structure In Fig. 3.6, P„ represents the proportional action. The sampling delay is equal to T X} 3.3.4 Simulation Results The simulations of both analog and digital controllers and the full bridge power circuit have been carried out using PSIM, a simulation package specifically designed for power converter simulation. P S I M also integrates a complete set of tools for the simulation of analog and digital control systems, which makes this package particularly helpful in the scope of this work. In Fig. 3.7, the digital controller is compared with the analog controller in term of dc bus ripple rejection. It shows clearly that the reduced bandwidth of the digital controller results in lower performance. The output voltage is perturbed by a substantial low-frequency ripple. The rms noise reaches 150 m V which is greater than the maximum allowed ripple. It is also interesting to note that, as compared to an analog controller, the duty ratio given by the digital controller is free of any switching harmonics. This is due to the strong filtering action of the zero-order-hold. 41 1 v (V) i 100.40 ' 1 1 i 1 t i y (y) 0 0 100.20 1 1 1 1 1 1 1 1 1 1 1 1 ~ I 100.00 _ _ J 1 1 1 1 1 99.80 ^\ f \ i V \ JA- . i_ (5!ms/div) i i (5;ms/div) 1 99.60 0.80 1 1 1 d I 0.76 _ _A 1 J tJ / 1 1 1 0.72 1 1 1 0.68 (a) i 1 t/ 1 1 1 1 1 / J f (5 ms/Wv) (b) Fig. 3.7 Comparison between analog and digital control - dc bus ripple rejection (a) Analog controller (b) Digital controller In Fig. 3.8, a large load change from light load to full load is simulated. In order to be consistent with the experimental setup, a light load corresponds to 28 % of the nominal power, that is 280 W. It's also assumed that the dc bus is free of any ripple. The dynamic response of the controlled system is quite slow. A s a result, the settling time of the output voltage is longer than in the analog controller case. Also, the overshoot and undershoot are larger. Similar remarks can be drawn for a step-down load change (full load to 28 %). The corresponding simulations are given in Fig. 3.9. 42 1.20K (lOms/div) (lOms/div) O.OOK 100.50 ^ (V) V Qf) 0 0 100.00 V 99.50 93.00 (10ms/div) (lOms/div) 98.50 | d f-'i 1.00 | 1 1 1 1 d 0.80 1 0.60 1 T i l l l 0.40 l l l i i (lOms/div) (lOms/div) 0.20 (a) (b) Fig. 3.8 Comparison between analog and digital control - step-up load change (28 % to full load) (a) Analog controller (b) Digital controller The different results obtained in the simulation can be summarized in the Table 3.4. Table 3.4 Performance of analog and digital controllers Analog Controller Digital Controller 4mV 140 mV 2.6 ms 2.1 ms 12 ms 17 ms Overshoot Undershoot 0.1 V 0.25 V 0.2 V 1.2 V Overshoot Undershoot 0.2 V <0.05 V 1.2 V 0.2 V Output voltage quality: R M S noise Setting time for load change : 28 % to full load Full load to 28 % Step-up load change: Step-down load change: 43 pm i 1.20K 1 pm 0 0 i i i (10ms/div) O.COK 101 .SO V (V) v (V) : 0 0 A, 101.03 I \ J J J 100.93 1 * r i h i ' \ \ I i i i \ \ i r 1 1 : : i i • i i i i i ; | (lOms/div) 0.80 i *V (10 ms/div) 1 1 1 09.93 1 1 — i \ 1 (lOms/div) 1.00 — V r V 1 100.00 d (10ms/div) 1 d —-—" »—n 0.93 0.40 (10ms/div) 0.20 (b) (a) Fig. 3.9 Comparison between analog and digital control - step-down load change (full load to 28 %) (a) Analog controller (b) Digital controller The large discrepancies between analog and digital control performances are partially caused by the very low switching frequency of the experimental setup. The choice of 7^^ for this particular converter was limited by real time constraints (see Chapter 5). In Appendix A , a similar comparative study has been conducted on the X F R 2.8-kW from Xantrex Technologies Inc. It can be noticed that the bandwidth of the digital controller is also reduced by 80%. However, in the X F R 2.8-kW case, the loss of performance is not as dramatic as in this case. 44 3.3.5 Quantization Effect The limited A / D converter resolution is included in the simulations. We assume that both current and voltage are sampled by the same converter. In order to evaluate the effect of the quantization on the output voltage, the resulting rms noise and dc offset is compared for different resolutions. In the first set of simulations (see Table 3.5), the measured range of the current is 0-20 A , and the measured range for the voltage is 0-120 V . It is noted that the minimum acceptable A / D resolution is 12 bits. Indeed, a lower resolution will lead to a significant increase of the dc offset and slightly higher rms noise. Table 3.5 A/D converter quantization effect Quantization step: Current Voltage Output voltage: R M S noise dc offset 16 bit 14 bit 12 bit 10 bit 8 bit 0.3 mA 1.8 mV 1.2 mA 7.3 m V 4.9 mA 29 mV 19 m A 117mV 78 mA 470 mV 140 mV 1 mV 140 mV 5mV 145 mV 15 mV 150 mV 60 m V 160 mV 250 mV As stated previously, the A / D resolution can be improved by reducing the measurement window. However, the level shifting technique can be carried out only on the output voltage since the current level depends on the load. With a measurement window reduced to 90-110 V , the following results were observed: Table 3.6 A/D converter quantization effect with level shifting 10 bit 8 bit Quantization step: Current Voltage Output voltage: R M S noise dc offset 19 mA 4.9 mV 78 mA 78 mV 150 mV 6 mV 150 mV 36 mV Using a 10-bit A / D converter with the level shifting technique leads to similar results as with a 14-bit converter. This result is particularly interesting when poorly accurate converters have to be used. In Table 3.7, the D / A limited resolution is simulated. We suppose the A / D resolution is fixed to 10 bit. The current measurement range is kept to 0-20 A , while the level shifting technique is implemented for the voltage measurement. According to the simulations, the quantization effect of the D / A converter can be easily neglected, even for low resolution D / A . 45 Table 3.7 D/A converter quantization effect Quantization step: Duty ratio Output voltage: R M S noise dc offset Mbit 12 bit 10 bit 8 bit 6 bit 4.8 u 19 u 76 u 305 u 0.015 150 mV 6 mV 155 mV 5 mV 150 mV 6mV 155 mV 6 mV 150 m V 7 mV 3.5 Summary In this chapter, a digital controller based on a continuous time domain approach is designed and applied to a full bridge converter. It has been shown that the computational time delay and the zero-order-hold introduced by the digital control structure introduces a large phase lag on the close loop system. To compensate for this effect, the bandwidth of the inner and outer controllers have to be significantly reduced, resulting in low control performances. The effect of quantization was also discussed. Results show that the resolution of the A / D converter has to be chosen with care in order to avoid the limit cycle phenomenon. However, the resolution of the A / D converter has negligible effects on the system stability. 46 Chapter IV PREDICTIVE CONTROL FOR T H E T I M E D E L A Y COMPENSATION In the previous chapter, it was shown that the delay introduced by the calculations and the zeroorder-hold significantly reduces the system stability, and thus the controller bandwidth. The compensation of the computational delay is the prime objective of this chapter. The phase boost resulting from this compensation is used to increase the controller bandwidth, thus improving the performance of the regulation. In the first section, we will see why none of the traditional techniques for the compensation of time delay presented in the introduction provide a satisfactory solution when applied to SMPS. Based on some concluding remarks, a predictive controller using a linear extrapolation technique is developed. Two predictive schemes are proposed and applied to the system in the case study. Comparison between conventional digital control and these two schemes is provided. Finally, the concept of prediction is extended to improve the computational efficiency of the microprocessor. 4.1 Proposed Predictive Control Technique Where the compensation of the computational time delay is concerned, neither the derivative action or Model Based Predictive Control present satisfactory solutions. i. The derivative action leads to a robust controller; however, the improvement in phase margin is limited due to the fact that future changes in the process are not accounted for [5]. ii. Although the M B P C concept often leads to good control performance, it has been shown that these schemes are usually very demanding in calculation and cannot be successfully implemented on microprocessors working at high sampling frequency. Also, their implementation on fixed point devices can be difficult since they require an accurate representation of the coefficients of the process model difference equation. In the following paragraph, the simplicity of the linear extrapolation is used as a basis for a predictive controller. The model of the converter also intervenes in the derivation of the predictor in 47 order to solve the limitation of the extrapolation technique, that is, the lack of information in the future change of the system. 4.1.1 Prediction Concept To understand the time delay problem and to illustrate the proposed concept, consider the following general feedback control system described in the discrete time domain: yref ) 1 z G(z) > Controller n-\ u H(z) Sampling time delay Plant Fig. 4.1 Discrete time domain feedback control system The discrete control system shows that the control variable u , calculated to compensate the error n between y n and the setpoint y j, is used only at the next sampling period. The basic idea behind the re prediction concept is to update the controller using j>„ , estimated value of y . +1 control variable w„ +1 n+l Then a predicted is obtained at time t = n-T . As a result, the plant output is adjusted without delay. s The computational time delay is fully compensated whenever the estimated value equals the future output value, that is: C-) y \=y +\ n+ 4 n 1 The problem of compensating the sampling time delay is, therefore, reduced to the calculation of the process estimated output j>„ . Let us consider the step response of a second order process (see +1 Fig. 4.2). Intuitively, it appears clearly that the easiest way to perform the prediction of the future value of the process output is to use the two previous output values y _ n x and y , n and obtain y n+l by extrapolation. 48 t + T< t-T. (b) (a) Fig. 4.2 Typical step response of a second order process (a) Complete transient (b) Detail over three sampling cycles The idea is simple and relies on information which is available at time t = n • T . It is also obvious that s the extrapolation leads to an accurate estimate only i f the sampling rate is high enough as compared to the natural frequency of the process. 4.1.2 Modified and Simplified Predictors The analysis of the power circuit has shown that the continuous time domain model for both the output voltage and inductor current is a second order transfer function which can be expressed in a general form as: *(.)- + (4.2) 2 s +2-^-co -s + ® 0 0 The resonant frequency co , the damping factor £,, and the coefficients k 0 i and k 2 can be obtained through open loop identification or analytical analysis. Let us define 7^ to be the sampling period. The function H(s) can be converted into the discrete time domain using classical zero-order-hold equivalents: H f z ) = k * - [ l - « - f o + cose)]+a-[a + l>-cose] z - 2 • a • cos(9) • z + a 2 2 Where: 49 a -^oT = e x sin 9 • = T. (4.4) '2j Rewriting (4.3) under the difference equation form, the exact value of y n+l y can be calculated as: = 2 • a- cos(0) • y - a • y _ + k • [l - a • (b + cos 8)]- u + k -a-[a + b- cosGJ- u _ (4.5) 2 n+l n n x 2 n 2 n x Such formula would be used in model oriented predictive schemes (Internal Model Control, Smith Predictor, etc.). However, i f we assume the term ^(£> T to be small enough to yield the following 0 S simplification: - e The estimate of y n+l M « ( l - ^ a , 0 T > l (4.6) can be expressed as: y *y n+x =2-y„-y„_ n+x +k T -[u„ x r s -u ] nA (4.7) Equation (4.7) shows that, given the historic values of the output and the control variable, an estimate of y n+l can be calculated. Also, we notice that i f the control variable is updated only once in every 2 sampling periods, we have the equality u = u _ . As a result, we have: n n x y +\=i-y -y -\ n Finally we conclude that the estimate y n+1 n (4-8) n can be calculated by using either (4.7) or (4.8). As a result, we define the following two prediction schemes: i) Modified Predictor (MP) based on: j>(z) = ^-1 • y(z) + *, • T • — z s z • uiz) = P, (z) • y(z) + M(z) • u(z) (4.9) ii) Simplified Predictor (SP) based on: 2-z-l y(z) = P (z)-y(z) l (4.10) The discrete control loop system with these predictors can be represented in Fig. 4.3. 50 yref z)—* G(z) *n-l -l H(Z) M(z) (a) yref G(z) •12. 7. 300 2.71 Control period : 2.7; Sampling period : T x (b) Fig. 4.3 Control loop block diagram (a) Modified Predictor (b) Simplified Predictor Both predictors are based on the same linear extrapolation function P (z). Fig. 4.4 gives a graphical t representation of the prediction techniques. In Fig. 4.4(a), the control variable is updated at every sampling period, and the exact curve of the process output is represented by a dotted line. With the Modified Predictor, the predicted value y n+l is equal to the value from the linear extrapolation, added to a correction term. If the control variable is maintained constant for two sampling periods, the simplification (4.8) yields and the estimated output value is simply the result of the linear extrapolation, as shown in Fig. 4.4(b). The main drawback of the Modified Predictor is that the coefficient k needs to be determined l accurately from the system. In situations where the parameters of the plant are poorly evaluated, or drift with time and temperature, this value will be inaccurate, reducing the effectiveness of the technique and the robustness of the controller. 51 y,, \ .£> + 1 -*'*""" Correction term : k • T .(u -w„_, ) / x s n >n+l y(t) (exact curve) Linear extrapolation » "»-l « B < ( W »- M H-l) t t-T. (a) Linear extrapolation ^(exact curve) t-T. r+r. (b) Fig. 4.4 Representation of the prediction functions mechanism (a) Modified Predictor (b) Simplified Predictor Compared to the Modified Predictor, the Simplified Predictor does not give as good a performance since the control frequency is reduced by half. However, it does not require any knowledge of the system, as long as the simplification in (4.6) is valid. The timing events of the conventional digital control and the proposed prediction schemes can be illustrated as shown in Fig. 4.5. 52 y„ i + Control Conuol A A (a) y \ y„ \ n+ MP V„+2 + Control CJonn ol MP A A A uH+l -*n+2 (b) y„ \ y„ y„ 2 + JH+2 + I 4 SP Free Resources Control A A "n+2 J n 1 'H+2 H+l (C) Fig. 4.5 Timing sequence of the different control schemes (a) Conventional digital controller (b) Modified Predictor (c) Simplified Predictor In conventional digital control, the output value y n is sampled at time T . A new control value u is n n calculated based on y but used only at T . In comparison, with the Modified Predictor, the estimated n output value y„ +l u„ . +l n+l is calculated at time T and used in the control algorithm to generate the control value n In addition, with the Simplified Predictor the control variable is updated only once in every two sampling periods. In the second sampling period, the estimate y n+2 is used by the control algorithm to calculate w „ . +2 4.2 Effect on the Control Design Both predictive schemes can be used to compensate for the sampling time delay. However, the prediction function P, (z) does not completely compensate for the effect of the delay. Therefore, when 53 designing a controller based on the predictive schemes, the amplification caused by the linear extrapolation function and the remaining time delay have to be accounted for. This issue is assessed below. 4.2.1 Continuous Time Domain Analysis To study the impact of the proposed predictors on the control loop design, we represent the control system in the continuous time domain, such as in Fig. 4.6. u(s) yref G (s) v c H(s) Feedback path Fig. 4.6 Equivalent control loop for digital control design The transfer function Tj (s) models the dynamic behavior of the feedback path. In digital control, this b function represents both the zero-order-hold and the inherent sampling time delay. TJJ,(S) is expressed as: \-e (4.11) Tjb ( ) = del ( ) • zoh (*) = e > s T s T sT T h ' s zo Typically, the zero-order-hold period T zoh Simplified Predictor, T zoh is equal to the sampling period T . However, for the s equals 2 • T . s The effectiveness of the proposed prediction technique can be estimated by calculating the phase lag of the feedback path with and without prediction. The problem consists in expressing P (z) in the t frequency domain and then using the Bode analysis. It has been shown in simulation that the inverse Z transform approximations do not lead to accurate results in terms of phase and gain. It appeared that the best solution is to combine the Backward Euler transformation (for an accurate phase) and the bilinear transformation (for an accurate gain). The equivalent of P;(z) in the frequency domain can be written as: 54 2 + 3-7WC0 2-7-,-yG) 1 + 7; (4.12) • 703 The feedback path behavior with and without prediction is represented in Fig. 4.7. 10 m g o Conventional Digital control 10 Modified Predictor TMT zuh]r (s).P,(s) Js -20 Simplified Predictor A -30 0.01 . C0/(B . A Modified Predictor -60 Simplified Predictor ID ^)T \ T zllh £ (s).P,(s) Conventional Digital Control -120 -180 0.01 0.1 co/co v Fig. 4.7 Inherent phase lag of the feedback path for different control structures The reduction of the phase lag using'the linear extrapolation function is shown clearly by the phase diagram. It should be noted that the gain of the feedback path is greater than 1 for some high frequencies before being damped by the fdtering action of the zero-order-hold. Since the zero-order-hold period is twice as large for the Simplified Predictor than for the Modified Predictor, the amplification of the noise in the Simplified Predictor scheme is not as important. In any case, the control design must take into account the gain of the prediction in order to avoid unwanted noise, thus guaranteeing an appropriate gain margin. 55 The phase lag (p (co) introduced by T^is) can be expressed analytically as: r f q Tjh (co) = a n g l e ^ (yco)] = -co • T T s \ + (4.13) (©7;) (4.14) The phase lead cp (co) given by (4.13) is expressed as: P cp (co) = a n g l e d (yco)] = t a n -1 P/ We define the phase lag compensation factor % as the ratio of the phase lag before and after prediction. For both predictors, we have: 3con <l% (<») 97> (<») 9/} + 3a>7; - 2 t a n fa) - 1 (cor,) (4.15) 9r„ (©) 9 7 > ( > ) + Pfl(ffl) fi 3©r c 4co7; -2tan (co7;) _1 ( '^=2-7; The compensation capability of both predictors is plotted in Fig. 4.8. X 2.5 1.5 0.1 0.2 0.3 Fig. 4.8 Phase lag compensation factor 0.4 0.5 co/co. This diagram shows that the effectiveness of the predictors decreases with the frequency. For instance, if the sampling frequency is much higher than the cross over frequency of the controller, the compensation of the sampling time delay is almost complete. The phase lag generated by T^is) is reduced by a factor 3 with the Modified Predictor, while it is reduced by a factor 1.5 with the Simplified Predictor. If the cross-over frequency of the control loop is about four tenths of the sampling frequency, the phase lag 56 compensation using both predictor is reduced. With the Simplified Predictor, no improvement should be expected since % is below 1. It should be noticed that, even if the prediction is able to compensate fully for the sampling time delay, the phase lag introduced by the sampler is still present. 4.2.2 Application to Switchmode Converters As stated previously, in order to apply successfully the linear extrapolation technique on a generic second order process, the condition (4.6) has to be verified. Using the results derived in Chapter 2, we find that for switchmode power supplies, (4.6) is equivalent to: 1 e RCr +r r,C+L+RCr, c ~2 c < T LC(R+r ) c ( x 1 R-C-r +r -r -C c 2 c + L + R-C-r L LC-(R L + ^ r) *1 (4.16) c Given that T = T , (4.16) is generally valid for any converter whose natural frequency is much lower s SW than the switching frequency. However, it should be noted that for very high switching frequency converters, and because of the computational limitation of the microprocessor, the sampling period can be a multiple of T . In this particular case, it is recommended to evaluate (4.16) before implementing sw any predictive scheme. Given a reasonable damping factor (>0.1), the simulations and experiments have shown that a prediction technique based on linear extrapolation will give good results as long as the ratio between the sampling frequency and the natural frequency is greater than 200. A lower ratio will result in larger high frequency noise due to the poor accuracy of the estimated values. The control of the power converter is based on a two-loop structure. Both loops have to include the predictive term so that both feedback quantities are based on predictive values of the inductor current and output voltage. The implementation of the Simplified Predictor is straightforward and does not rely on any knowledge of the converter parameters. For the Modified Predictor, the correction term has to be evaluated by the functions M M v (z), such as shown in Fig. 4.9. The coefficient k is equal to K x v ; (z) and for the output voltage and Kj for the inductor current. It can be noticed that in many cases, since the capacitor E S R is supposed to be low, the correction function M ( z ) can be neglected, thereby reducing the amount of calculations v needed to perform the prediction. 57 P,{z) v (z) 0 T (z) vo o,ref Y D {z) u(z) < 1 iL T (z) k M: v {z) 0 out( ) T z (Z) Fig. 4.9 Implementation of the Modified Predictor for a current mode controller 4.2.3 Simulation Results Both predictive schemes are included in the digital controller designed in the previous chapter. Using the control design discussed in this section, new sets of control parameters are calculated and applied in simulation. These parameters are summarized in Table 4.1. Please note that the simulation includes the quantization effect of 10 bits A / D with level shifting. For an easy comparison with the analog and conventional digital control, the following results are displayed using the same scale as the results given in Chapter 3. As compared to the conventional digital controller, the bandwidth of the resulting predictive controllers is larger, while maintaining similar phase margins. As a result, the performance of the controller in terms of the dc bus ripple rejection is much better (see Fig. 4.10). Since the Modified Predictor has a higher phase lag compensation characteristic, the results obtained with this scheme are also better than those obtained with the Simplified Predictor. However, in order to reduce the sensitivity of this scheme to measurement noise, the phase margin of the outer loop compensator has been slightly increased. This will also improve the robustness of this scheme in the presence of parameter uncertainties in the choice of the correction factor. 58 Table 4.1 Simplified and Modified Predictor control parameters Outer loop: Cross-over frequency Phase margin Simplified Predictor Modified Predictor 170 Hz 45 ° 4A-V 220 Hz 48 ° 4.4 A-V" 930 ps 720 ps 370 Hz 35 ° 0.021 A 600 Hz 35 ° 0.032 A"' 430 ps 265 ps 1 Inner loop : Cross-over frequency Phase margin - 1 1 290.00 275.00 260.00 i 100.40 , i V (V) i i ..^/\.. -A \s \ A/ n. L 99.80 . 1 1 y_ I (5;ms/div) 1 99.60 i i i i i d I 1 1 1 , 1 J J 0.76 A. T r j ii i JLj\rJ '1_ JT_r i j I J i \J • 1 1 1 (5 !ms/div) _ [ " 100.00 t 0.80 A 1 i i i d i i i i 100.20 1 1 i v on 0 0 j (5 msrdiv) 0.72 _J 1- ! H- r r r "} (5 Tis/div) 0.68 (a) (b) Fig. 4.10 Comparison between the two predictor schemes - dc bus ripple rejection (a) Simplified Predictor (b) Modified Predictor 59 1.20K (10 ms/div) (10 ms/div) O.OOK 100.50 V QO V (S) 0 0 100.00 99.50 99.00 (10 ms/div) (10 ms/div) 98.50 1.00 d 0.S0 0.60 0.40 (10 ms/div) (lOms/div) 0.20 (a) (b) Fig. 4.11 Comparison between the two predictor schemes - step-up load change (28% to full load) (a) Simplified Predictor (b) Modified Predictor The effect of the predictive controllers can also be observed for step load changes. The higher bandwidth of those controllers results in a lower overshoot, undershoot and settling time (see Fig. 4.11 and Fig. 4.12). Those simulations did not include the dc bus ripple. However, we can notice that a slight noise is present on the output voltage. This is mainly the result of the quantization effect. The control performance of the predictive controllers is summarized in Table 4.2. 60 1.20K 1.20K 0.00 K 0.00K 101.50 101.50 r (V) V (V) 0 0 101.00 101.00 100.50 100.50 100.00 (10 ms/div) ————'—V 100.00 •- — — \ ^ (10 ms/div) (10 ms/div) 99.50 1.00 99.50 1.00 d d 0.80 0.80 —* >- 1 J~i^ V J - 1 _ - " — * — — • — - 0.60 0.60 0.40 0.40 (lOms/div) (10 ms/div) 0.20 0.20 (b) (a) Fig. 4.12 Comparison between the two predictor schemes - step-down load change (full load to 28%) (a) Simplified Predictor (b) Modified Predictor Table 4.2 Performance of the predictive controllers Modified Simplified Predictor Predictor Output voltage quality : 30 mV R M S noise 65 mV Setting time for load change : 28 % to full load Full load to 28 % 10 ms 10 ms 8 ms 8 ms Overshoot Undershoot 0.1 V 0.85 V 0.1 V 0.65 V Overshoot Undershoot 0.9 V 0.15 V 0.65 V 0.1 V Step-up load change: Step-down load change: 61 Even though the performance of the predictive controllers is much better than a conventional controller, it still cannot compete with its analog equivalent. The discrepancies between analog and predictive control tends to disappear for higher switching frequencies (see Appendix A ) . 4.3 Extended Simplified Predictor The concept of the Simplified Predictor can be further extended. Instead of performing the prediction using a linear extrapolation over two samples, an idea is to define a second order function giving the estimated value of the process output based on three consecutive samples. This predictive scheme is referred to in the following as the Extended Simplified Predictor. Unlike the conventional digital control or the Modified Predictor where the control variable is updated at every sampling period, and the Simplified Predictor where the control variable is updated at every second sampling period. The control variable is updated only once every three sampling periods with the Extended Simplified Predictor. The first and second sample periods remain idle; that is, no control calculation is performed. The advantage of this predictor is a higher accuracy of the predicted values since a parabolic extrapolation technique is used, and also an improved computational efficiency. As compared to a conventional digital control algorithm, this method only requires (theoretically) the third of the computational resources previously used in the conventional digital control method. As a result, some of the computational resources of the microprocessor are freed for secondary tasks (see Fig. 4.15). These resources can then be used to implement other less critical functions such as communication, user interface or fan and temperature management inside the power supply. Untill now, these functions have been handled by secondary processors dedicated to those specific tasks. B y increasing the computational efficiency of the control algorithm, the objective is to use only one processor for all the power supply functions. As a result, less components are needed and the P C B layout is simplified. From a stability point of view, we can consider the computational time delay to be completely compensated while the zero-order-hold period is increased to 3 • T . As a result, the phase lag s characteristic of the close loop system is not altered by the predictive scheme. The major drawback of the Extended Simplified Predictor is its increased sensitivity to noise measurement and A / D accuracy. 62 4.3.1 Derivation of the Prediction Function The derivation of the prediction function P (z) for the Extended Simplified Predictor can be p achieved by considering a general second order function y {t) whose trajectory is defined by the three P samples y _ , y -\ n 2 n a r , d yn s u c n yp(0 = —^-T-(y*.2 a s shown in Fig. 4.13. A n analytical solution is easily reached, and: - 2 - J V i +y„)-t 2 2-77 +-^—\-?>-y - +2-y _ -y )-t 2-T n 1 n x +y _ n n 2 (4.17) s The predicted value of the process output at time t = {n + \)-T is given by: s Pn+i =yp( s)=i-yn-i-yn-i+y -2 (4-18) T n This result can be verified by using the difference equation (4.5) and deriving this relationship for both y and y . Then, we obtain two equations whose difference is expressed as: n n+1 t-2-T t-T s t x t+ T x Fig. 4.13 Extended Simplified Predictor concept If the control variable is maintained constant over three sampling periods, (4.19) can be written as: y x -y =2-an+ n cos(6) • y - (a + 2 • a • cos(9) •)• y _ + a • y _ 2 n 2 n x n 2 (4.20) 63 As compared to the linear extrapolation, this technique does not have recourse to any simplification to remove the control variable from the equation. As a result, the prediction is more accurate. Finally, using (4.6) we get: (4.21) We check that (4.18) and (4.20) lead to the same result. The prediction function expressed in the zdomain is defined as: -3-z +l 3-z z P(z) = (4.22) The corresponding control loop block diagram (see Fig. 4.14) is similar to the Simplified Predictor: yf re G(z) H(z) — s f o — + •43.7V 3.7V Control period :3.T S 1 Sampling period : T s Fig. 4.14 Extended Simplified Predictor Control loop block diagram The timing sequence of the Extended Simplified Predictor is given in Fig. 4.15. y -\ y» n y +2 y +\ n n y»+2 i i Free Resources Free Resources 1 rsp C.ontiol .t t n+2 u n-\ u T,n+1 'n-2 Fig. 4.15 Timing sequence of the Extended Simplified Predictor 64 4.3.2 Application and Comparison with Conventional Digital Control Performance The Extended Simplified Predictor is simulated and compared to the conventional digital control structure detailed in Chapter 3. Only the response to dc bus ripple is assessed here. From Fig. 4.16, we can note that the predictive scheme leads to a slightly noisier result. Simulations have shown that this scheme will give better results when using higher A / D resolution. i v <y) i i /\ A 0 \ jA. i_ 1 1 1 r <y) 1 0 i A 100.20 1 III / 100.00 \ 99.80 1 1 1 i 1 1 i /% 1 / 1 ii I J kf / i 1 1 1 i • (5 ms/div) \i J \ \ 1 V. V (5 ms/div) 99.60 ii d -A- -i f/ I _ - L 0.80 ! M 0.76 1 \ li ' I 1 / 1 1 1 1 1 1 1 _I J f 1 0.72 (5 ms/W) 0.68 (a) d "If i i • • ii (5 ms/aiv) » (b) Fig. 4.16 Comparison between conventional digital control and predictive control (a) Conventional digital control (b) Extended Simplified Predictor Those two schemes give similar performances in terms of dc offset and rms noise. We can therefore conclude that they are equivalent. 65 4.4 Summary In this chapter, it has been shown that it is possible to reduce the phase lagging effect inherent to the digital controller by using a very straightforward prediction technique based on a simple linear extrapolation. It has been shown that both Modified and Simplified Predictor can be implemented with success as long as the process order is limited to 2 and its natural frequency is much smaller than the sampling frequency. The application to a full bridge dc switchmode power supply has also been presented. The results show a clear improvement of the controller bandwidth and performance. The Modified Predictor presents the best phase lag compensation, and as such, it allows the designer to achieve a wide bandwidth as compared to a conventional digital control structure. However, it remains a model based scheme which can perform poorly if some of the converter parameters change overtime. Also, it is more demanding in calculation and more prone to measurement noise. The Simplified Predictor presents the best compromise between performances and robustness. Further, its implementation is very simple since it relies on only two additions. As compared to the Modified Predictor, it is also less prone to measurement noise. One of the major advantage of the Simplified Predictor is that it significantly improves the computational efficiency of the control algorithm. B y implementing the Extended Simplified Predictor structure, it has been shown that the computational effort needed to perform the control calculation can be reduced by a factor of 3, without any control parameters re-design or re-tuning. The advantage of such a technique is then to be able to implement more of the converter functions within a single microprocessor, considerably reducing the cost associated with the control board, and improving also the reliability of the product. Finally, the compensating effect of the predictors is represented in the Table 4.3 where the overall time delay is compared for each controller. Table 4.3 Resulting delay associated with each control structure Zero-order-hold Time delay Overall Conventional Digital Control 0.5 1 1.5 Modified Predictor 0.5 0* 0.5 1 0* 1 1.5 0* 1.5 Simplified Predictor Extended Simplified Predictor Only in the low frequency range 66 Chapter V EXPERIMENTAL RESULTS In this chapter, the control concepts presented previously are validated using an experimental set-up based on the full bridge topology discussed in Chapter 2. First, the design of the power stage and the control algorithm is presented. The equipment used for the experimental power supply is discussed and its limitations are identified. In the third section, experimental results are presented and compared to results obtained by simulation. Finally, the constraints in terms of processor computation time are assessed and discussed for each control schemes. 5.1 Experimental Setup The objective of the experimental prototype is not to develop a commercial-type power supply, but to build a basic power structure and validate the different control schemes proposed in the previous chapters. As such, performances in terms of efficiency, E M I , power factor, size, weight, acoustic noise, wiring and thermal management are not considered as major issues in the setup. This section discusses the design of the converter power stage. Detailed flow charts of the control algorithm are provided, the complete program being given in the annexes. 5.1.1 Power Stage Design Fig. 5.1 shows the power stage schematic diagram of the experimental setup. The system consists of a diode bridge rectifier with its input filter, a P W M inverter, a high frequency transformer, an output filter and the resistive load. The parameters of the converter were already given in the Table 2.1. The power supply is an 1 kW, 100 V device supplied from a single phase ac source using a voltage doubler structure. The operating switching frequency is set to 10 kHz and the average output current is limited to 15 A during transients. 67 (381LX |22 5io v - | O^FT 60 Hz >iow > , 381LX_ PH114/93-N27 PM20CSJ060 + HFA50PA60C IX—I I IPM PH87/70-N27 ' T Y Y 1.9mH M%150m 43^F~ 'lOW u 36DX 2mF LT3 25-NP LTS 2S-NP 1^-^- >ESR yZOm n 1^^- HCPL-4506 rKr P Gating signals W M ""HCPL-4506 Fig. 5.1 Power stage schematic diagram of the experimental setup 5.1.1.1 Diode Bridge and dc Bus Filter The input is constituted by two diodes and a capacitor bank. A three phase diode bridge rectifier from International Rectifier provides the rectification of the line. The selected component is the 26MT20, rated for 25 A and 200 V maximum peak voltage. The choice of the input filter capacitor results from a tradeoff between capacitance, ripple current, and source current distortion. A very high capacitance offers a ripple free dc bus, but the cost and size are too high. Also, since the conduction of the diode is limited to a very short period, the source current spikes are higher and a bigger input filter would be needed to reduce the associated harmonic distortion in the line. Using a voltage doubler, a common choice for the capacitance is 3 uF/W for each capacitor [30]. In our case we need two electrolytic capacitors of 3 mF. A simple simulation of the line rectifier shows that a ripple current of 13 A rms flows through the capacitors when supplying a nominal load of 1 kW. The capacitor has to be selected so that it can withstand such a current. Generally, the maximum ripple current can be found in the manufacturer catalog. In order to reduce the necessary capacitor rating, a common practice is to connect a number of 68 smaller capacitors in parallel. Our choice was to use twelve 220 pF Cornell Dubilier electrolytic capacitors from the 381LX family. Their rated maximum ripple current at 120 Hz is 1.0 A rms and their working voltage is 200 V . The total measured capacitance is 2.7 mF. Two 10 W/15 kQ resistors have been connected across the capacitor to facilitate the discharge of the circuit when the inverter is turned off. 5.1.1.2 Inverter In order to simplify the wiring of the inverter, an Intelligent Power Module (IPM) from Powerex has been selected. This device features a 3-phase inverter with its gate drive circuit. Basic protection against short circuit, over current, over temperature and under voltage is also embedded in the module. For this specific application, we selected the PM20CSJ060 which can typically handle a dc bus voltage of 400 V and delivers a maximum output current of 20 A . Based on the IGBT technology, the switches can be operated up to 20 kHz under hard switching P W M generation. The drivers supply voltage is typically 15 V . A difficulty resides in the fact that for the bottom switches the supply voltage is referenced to the negative node of the dc bus voltage, while for the top switches the supply voltage is referenced to the middle point of each leg. As such, 4 different isolated voltage sources are needed to supply the inverter. These sources are obtained through a dedicated push pull dc-dc converter also distributed by Powerex under the reference M57140-01. Optocouplers connected between the P W M generator outputs and the input of the drivers are added to provide the isolation. The HCPL-4506 from Helwett Packard has been specifically designed for T T L and I P M applications. It provides an isolation up to 2.5 k V rms for 1 minute and a propagation delay of half a microsecond. Finally, in order to reduce the voltage spikes generated by the commutation of the switches, a small capacitor of 43 pF is soldered directly on the input leads of the I P M module. 5.1.1.3 Transformer It can be shown that the harmonic distortion of the output voltage due to the switching harmonics depends on the duty ratio during the steady state. A duty ratio of 0.5 will give the maximum switching noise while very low or very high duty ratios would limit this noise. To keep a reasonable margin for the compensation of disturbances, we cannot set too high a value for the duty ratio. Then, to reduce the noise related to the switching harmonics, the desired nominal duty ratio is set to 0.7 which represents an adequate compromise. As a result, we find that the transformer turns ratio should be 2:1. With a switching frequency limited to 10 kHz, only few ferrite cores can be used. Our choice was the PM144/93-N27 from Siemens Matsushita, which is the biggest pot core available. Since the 69 transformer is wound by hand, the wire gauge has been limited to A W G #18. To reduce the conduction losses, four strands of wire are winded in parallel. The number of turns at the primary side is 20 while the number of turns at both secondary sides is 10. Both copper and core losses can be neglected, and no shield have been added to the design. The transformer structure is shown in Fig. 5.2. In order to reduce the leakage inductance, the primary winding is split into two windings forming the inner and outer layers. Second secondary (10 turns) 4 strands are winded in parallel to reduce the copper losses •Q 0 0 0 Q 0 0 Q Primary winding (first layer) Primary winding (second layer) PM114/93-N27 First secondary (10 turns) Fig. 5.2 Transformer winding schematic 5.1.1.4 Output Filter Output filters are usually designed to attenuate strongly the switching harmonics present in the output voltage and output current. The ratio between the switching frequency and the filter cut-off frequency is about the same than for the X F R 2.8 kW. The rectifier is composed by two ultra fast, soft recovery diodes connected directly at the output of the transformer. The HFA50PA60C from International Rectifier is selected. Based on the HEXFRED™ technology, this device is rated for 600 V and 50 A at the nominal operating point. The output filter capacitor bank is composed of 3 electrolytic capacitors from Sprague, connected in parallel. Each capacitor is rated to 2 mF, however a direct measurement as shown an overall capacitance of around 6.8 mF. The inductance L has been initially set to 1.5 mH. The core used for the inductor is the PM87/70N27 also from Siemens Matsushita with an air-gap of 3.5 mm. To avoid the saturation of the inductor 70 during large transients (i.e. when the inductor current rises up to 20 A), the number of turns is set to 84. Five layers of wires ( A W G #18) are needed, each turn being composed of two parallel strands to reduce the copper losses. At 20 kHz, the equivalent resistance of the complete winding is approximately 150 mQ. The resulting inductance was 2.3 mH, and as such a bigger air-gap was needed to reduce its value. Finally, after experimentation, the inductance has been tuned to 1.9 mH. 5.1.2 Sensors Sensors are one of the most sensitive aspect of the design. Poorly chosen sensors will generate measurement noise which will perturb the control calculations. Three sensors are needed: two current sensors measuring the primary side and inductor current and one voltage sensor measuring the output voltage. Each of those sensors must have the three following characteristics: i. they must provide isolation between the control board and the power circuit, ii. they must have a sufficient bandwidth, iii. they must have a sufficient measurement range. The most convenient sensors are transducers using the Hall effect. A s such, they provide a wide bandwidth and inherent galvanic isolation. The selected current sensor is the L T S 25-NP from L E M Instrument. This ASIC-based transducer has an extended measurement range up to 25 A rms. It has a wide bandwidth from dc up to 200 kHz, an intrinsic accuracy of 0.2 %. One major advantage of this component is that its output is set at 2.5 V for zero current with a variation span of 0.625 V at the nominal current. This allows the sensor output to be connected directly to the input of any A / D converter. This feature is very interesting mostly when dealing with the measurement of ac signals. However, since the A / D resolution is quite low, the full range 0-5 V must be used for the measurement of the inductor current. Therefore, a small analog interface have been implemented to offset and scale the output of the sensor. The measurement of the primary side current is mainly used for protection purposes. When a short circuit appears in the power circuit, the primary side current will rise and eventually cross a defined boundary. In this case, all operations of the DSP are hold and the P W M pulses automatically switched to their idle state. The voltage sensor has also been selected from the L E M Instrument catalog. The L V 25-P is a voltage transducer based on the closed loop Hall effect. This component is connected directly across the voltage to be measured. A resistance in series with the winding of the transducer taps a current 71 proportional to the resistance value. The image of this current is then used to supply another resistive element, typically a potentiometer. The resulting voltage across the potentiometer is then a measurement of the higher voltage at the primary side of the transducer. The bandwidth using this technique is also 200 kHz, and the measurement range is from 10 to 500 V . A n analog interface is generally needed to scale the voltage across the potentiometer to a more suitable range. 5.1.3 DSP Platform A digital controller can be implemented on three different devices: microprocessor, microcontroller, or Digital Signal Processor (DSP). A microprocessor is a simple algorithmic unit performing calculations and having a limited memory. A number of peripherals are therefore needed for input/output operations and memory management. A microprocessor is generally selected for its flexibility, and is mainly used for general computational tasks. For more specific tasks, a microcontroller can be used. The microcontroller is generally based on a low-end microprocessor with the advantage that some of the peripherals needed for the task are already embedded inside the chip itself, therefore reducing the amount of components needed and the complexity of the digital board. However, microcontrollers are generally limited in terms of computational power and word length. DSPs represent a good alternative between microcontrollers and microprocessors. More powerful than microcontrollers, DSPs are able to perform either fixed point or floating point operations. Their pipeline structure allows some basic operations to be run in parallel, and as a result, basic arithmetic operations such as additions and multiplications can be achieved in only one clock cycle. The computational power of DSPs is mainly used in applications involving heavy computational tasks such as fast Fourier transform, filtering, state estimator, adaptive control, etc. The major drawback of DSPs has been for a long time their rather high price, but the current trend shows that they will become cost competitive with most of the traditional solutions in the near future. The DSP chosen for the control of the power supply is the TMS320F240 from Texas Instrument (see Fig. 5.3). This 16-bit fixed point DSP has been specifically designed for the control of motor drives and switching devices. 72 A H 5-0] Data R A M Program Flash 544 words 16K words Event manager Three timers 12 P W M output J\ Prog^-.'D; Nine compares output Deadband logic D(15-0) T M S 3 2 0 F 2 4 0 D S P core 10-bit register 10-bit barrel 16-bit x 16-bit multiply shifter (L) 32-bit P register Four input captures with quadrature encoder pulse interface Three 8-bit I/O, ports Shift L 32-bit A L U Watchdog timer 32-bit accumulator Shift L (0-7) Eight auxiliary registers SPI r*—• SCI Eight level hardware stack Repeat count T w o status registers 10-bit ADC1 10-bit ADC2 Fig. 5.3 TMS320F240 internal structure Among its most interesting features, we find: i. ii. 3 general-purpose 16-bit timers 12 P W M channels iii. 1 dual 10-bit 8-channel A / D converter iv. synchronous and asynchronous communication peripherals v. 16K words of on-chip flash memory. The clock frequency can be set either at 20, 10 or 5 M H z . To benefit from the full extent of the DSP capability, the 20 M H z clock frequency is selected. The P W M unit has the advantage that the dead time between the turning on of both switches of a same leg can be programmed by the user. As a result, the analog interface between the optocouplers and the DSP board is simplified. The major drawback of this DSP is the low A / D converter resolution. But as stated previously, this can be partially solved by using the level shifting technique introduced in Chapter 3. The conversion time of 6.6 ps is also quite long. On the other hand, the dual A / D architecture allows two conversions to be triggered at the same time. The DSP can be programmed in either C language or assembly. According to its manufacturer, the most efficient programs use both languages where the general structure is written in C and the 73 functions involving numerous calculations and iterations are written in assembly [4]. In this work, only the C language is used for convenience. 5.1.4 Control Algorithm The control algorithm is implemented on a fixed point DSP. Even though the development of the control algorithm in C gives the possibility to use the floating point representation, this method would not be efficient in a real time environment. As such, all the arithmetic operations have to be performed as fixed point, and as a result, the control parameters designed in the previous chapters cannot be used directly and have to be scaled to an integer. The control parameters are scaled by multiplying them by a power of 2. Once the arithmetic operation involving the scaled value is achieved, the result is then scaled back to its true value by simply using the right bit shifting command. Using power of 2 as scaling factors has the advantage that the division reversing the scaling effect can be easily performed by the DSP. 5.1.4.1 Interrupt Routine Before discussing the specific algorithm of the PI controller, we will first take a global view of the interrupt routine. In Fig. 5.4, the structures corresponding to the conventional digital control and the proposed Modified Predictor are represented. Both structures exhibit the same characteristic, that is they are repeatedly called at every sampling period. At the end of the routine, a timer represented by a clock holds all operations till the period register reaches the defined value of the sampling period T . s At the beginning of the interruption routine, the DSP automatically updates the duty ratio and samples both inductor current and output voltage. A simple waiting loop check the A / D converter control register to detect the end of conversion and then store the measured value into a specific memory location. The measured values are then used by the outer voltage loop to calculate the inductor current reference, and finally by the inner current loop to calculate the duty ratio. In the Modified Predictor case, an intermediate operation computing the predicted values is implemented right after the acquisition. 74 Update control variable Trigger A/D acquisition Update control variable 0 Trigger A/D acquisition © Output voltage (Vomeas) and inductor current (iLmeas) measurements are available Outer loop calculation iLref The inductor current reference is calculated Outer loop calculation iLref Inner loop calculation The new duty ratio value is obtained (a) Inner loop calculation (b) Fig. 5.4 Interrupt routine (a) Conventional digital control (b) Modified Predictor Fig. 5.5 shows the flowchart of the interrupt routine for the proposed Simplified Predictor. Even though the Simplified Predictor reduces the amount of calculation needed to perform the control of the power supply, its inherent structure is slightly more complex and include another conditional loop. The Simplified Predictor interrupt routine can take two different states: an idle state where the samples are stored and an active state where the new and old samples are used to calculate the estimated values. It should be noticed that, even though the duty ratio is loaded into the compare register of the P W M unit at every sampling period, its value is only updated once every two sampling periods. 75 Each path is activated only once every two sampling periods... Fig. 5.5 Interrupt routine - Simplified Predictor The Extended Simplified Predictor has the same structure as the Simplified Predictor with the difference that a third path is added to the conditional loop. This path represents another idle state where the samples are stored for a future use. The prediction of the future values of the system is also performed in the active path. Part of those calculations can be re-directed into the second idle path to spread out the computational effort more equitably between the three different states. 76 Update control variable Trigger A/D acquisition 0 Each path is activated only once every three sampling periods... Flag=l 2 • r Flag=2 Store measured values Store measured values omeas_old2 ILmeas o l d : omeas_old ILmeas o l 1 Predict future values Vopred iLpred • / Outer loop calculation iLref Inner loop calculation Fig. 5.6 Interrupt routine - Extended Simplified Predictor 5.1.4.2 PI Algorithm Even though the PI controller has the simple structure shown in the block diagram of Fig. 3.6, its implementation on a fixed point microprocessor with limited word length is not as straightforward (see Fig. 5.4). The first difficulty is to keep the information of the sign of the error e . The A / D converter always n converts the sampled value into a 16-bit format. Since the resolution of the converter is limited to 10 bit, the last 6 bits are automatically set to 0. Before computing the difference between y ref and y, n both setpoint and process outputs are converted into a 15-bit format. The last bit represents the sign of the difference. 77 In the 15-bit fractional arithmetic format, the maximum positive number is 32767 (corresponding to 7FFFh in hexadecimal). Adding 1 to this number and the hexadecimal value becomes 8000h. Since the processor is working in a signed environment, the equivalent decimal number becomes -1 instead of 32768. The consequence of overflow on the control action can be quite disruptive since it changes the polarity of the control action from positive to negative. As a result each time a multiplication or addition is done, a conditional loop checking for overflow has to be included. If the overflow is detected, the result of the operation has to be reset to a maximum or minimum value. Also, the result of the multiplication of the feedback error with the proportional or integral gain has to be scaled down by shifting the binary representation of the value by a fixed number of bit, as indicated in the flow chart of Fig. 5.7. The proportional and integral terms can be evaluated independently. The order in which they are calculated does not matter. The PI control action is finally derived by adding both proportional and integral terms and checking if the summation result is within the limits defined by the saturation block. 5.1.4.3 P W M Generation The last aspect of the control algorithm concerns the programming of the P W M generator. The scheme most favored by industrials is the sliding waveform which provides soft switching [31-32]. In this scheme, the command pulses of each switch is equal to half the switching period. The relative position of the pulses of the first leg as compared to the pulses of the second leg corresponds to the duty ratio, as was reviewed in Chapter 2. This method is difficult to implement on the DSP since it relies on the generation of a delayed train of pulses. The P W M generator used to control the switches of the I P M is based on the hard switching scheme described in Fig. 5.8. A triangular carrier of amplitude 2 is compared to the duty ratio d. Whenever the carrier waveform is below the reference the inverter is turned into its active state (Q| is turned on while Q stays off), thus supplying the primary side of the transformer with the dc bus voltage. Since 3 the duty ratio cannot be greater than 1, the maximum duration for the positive active state is limited to half the switching period. The switching pattern of the second leg is similar to the first leg with the difference that it is phase-shifted by half of a switching period. 78 Err=Yref-Ymeas / E r r Error on the setpoint Paction=P*Err < min >max Check overflow else Paction=min Paction=max Paction » p Paction / Re-scaling by bit shifting Proportional action Iaction=I*Err > max Check overflow else Iaction=min Iaction=max T Taction » 1 Iaction = Taction + Iold Re-scaling by bit shifting Integral action increment > max < min Anti-windup else Iaction=min Iaction=max Iold = Iaction Iaction Store old integral action for future increment ~7 J g l PIaction= Paction +Iaction nte ra ion act Summation of the proportional and integral actions > m a x Saturation of the control variable else PIaction=min PIaction=max Fig. 5.7 PI algorithm This technique has two advantages: i. only one timer is needed to generate the carrier waveform, ii. each A / D conversion is triggered when the period register of the timer reaches 0. As a result, each sample is taken in the middle of the active pulse where the waveform is usually less affected by noise. 80 5.2 Experimental Results In this section, experimental results obtained from the converter designed previously are presented and compared to the simulation results obtained in the previous chapters. The two major parameters evaluated here are the output voltage ripple and the computation time corresponding to the different control schemes. 5.2.1 Control Performances The full bridge converter has been designed based on the parameters given in Table 2.1. The parameters of components, such as input and output filter capacitors and inductor were measured. Slight discrepancies between the expected and actual values were noticed. The simulation parameters were modified accordingly. Some of the power circuit parameters such as the capacitor E S R and the winding resistance of the inductor cannot be identified easily. Also, certain aspects of the practical set-up have not been simulated, such as the non-ideal characteristic of the semiconductors, the dead time of the switches, the different stray elements of the transformer, and the eventual E M I noise perturbing the measurements. As a result, we expect the experimental waveforms to be slightly different from those obtained in simulation. It is important to note that the control parameters used in the setup are exactly the same than those used in simulation. No tuning was required and each set of control parameters calculated using the converter models led to a stable system. This validates the accuracy of the models used to calculated those parameters. A function monitoring some of the parameters used by the processor when running the control algorithm has been developed. Based on serial communication, this function allows the user to download to a host computer the values of some of the microprocessor memory locations and registers. A visual interface is then used to display those values, and thus get a better insight on how they vary in time. This function is useful to track the variation of the duty ratio and other intermediate values such as the current reference of the inner loop. In the first set of experiments, the conventional digital control structure was implemented. The corresponding results are shown in Fig. 5.9. The rms noise on the output voltage reached a value of 145 mV, which is very close to the results obtained in simulation (150 mV). Also the comparison between the simulation and the experimental waveforms shows that simulation results are very similar to the experimental results, both in shape and in amplitude. Finally, the duty ratio corresponding to this 81 scheme was downloaded from the DSP to a host computer (see Fig. 5.13). Its shape is also similar to the waveform presented in Fig. 3.7(b). The average duty ratio is however slightly higher in the experiment than in the simulation, which is mainly the result of the voltage drop across the rectifying diodes. The proposed Modified Predictor was then implemented. The output voltage waveform is presented in Fig. 5.10. As expected, the Modified Predictor presents a much better output voltage quality with a noise of only 20 mV rms. In this case also, simulations and experimental results are close. However, it's important to note that this scheme presents a much noisier duty ratio as compared to any other scheme (see Fig. 5.13(b)). This is the result of prediction noise generated by the correction term which depends on accurate system values. The output voltage waveform obtained with the Simplified Predictor control structure are displayed in Fig. 5.11. The Simplified Predictor also gives good results since the rms noise is reduced to 65 mV, which is below the maximum tolerated noise level of 100 mV. In the scope of this work, the control parameters have been calculated beforehand, however we can easily imagine starting with the conventional digital control parameters and re-tuning those with a trial and error method. From a designer perspective, the Simplified Predictor represents then the best practical solution. Its implementation is simple and can be carried out without any difficulties. It's interesting to notice that since both Modified and Simplified Predictors have a larger bandwidth, the duty ratio corresponding to those schemes is similar to the inverted shape of the dc bus ripple. In fact, it appears that an additional feed-forward loop based on a measurement of the dc bus voltage would give the best results in terms of dc bus ripple rejection. The prohibitive cost of voltage sensors however is a strong deterrent for this kind of controller. Finally, the last controller to be implemented is the Extended Simplified Predictor. The results are given in Fig. 5.12. The resulting rms noise is about 155 mV which is slightly higher than the conventional digital controller. This is mainly due to the poor accuracy of the A / D converter which induces prediction noise. The waveforms between simulation and experiment are also slightly different, while the general shape remains the same. 82 100.5 (V) V Q \ \ A Simulati result ^ 100 ^ Experimental result M (5 m s / d i v ) 99.5 Fig. 5.9 Simulation and experimental results of the output voltage ripple with the conventional digital controller 100.5 1 v 0 (V) j i : Simulation result . N 100 Experimental rejsult (5 m s / d i v ) 99.5 i Fig. 5.10 Simulation and experimental results of the output voltage ripple with the Modified Predictor 83 100.5 V (V) 0 Simulation result 100 Experimental result (5 ms/div) 99.5 Fig. 5.11 Simulation and experimental results of the output voltage ripple with the Simplified Predictor 100.5 v 0 (V) A A Simulation result f 1 \ 100 / 99.5 \y '• Experimental resul;t i if A M \ \^ (5 ms/div) Fig. 5.12 Simulation and experimental results of the output voltage ripple with the Extended Simplified Predictor 84 No experimental results have been taken for load changes. In order to separate the effect of the load changes with the effect of the dc bus ripple, the converter should be supplied by a fixed dc bus voltage. Therefore, a much bigger input filter capacitor bank would be needed. However, since simulations and experiments have been quite similar as far as the dc bus ripple rejection was concerned, we assume that the response to load changes is also reasonably close to the simulation results. 0.84 0.84 0.80 0.80 0.76 I D.76 0.72 0.72 0.84 0.84 0.80 0.80 0.76 0.76 0.72 0.72 c) Fig. 5.13 Duty ratio for the different control schemes (a) Conventional digital control (b) Modified Predictor (c) Simplified Predictor (d) Extended Simplified Predictor 5.2.2 Computation Time The computation time of the microprocessor with the different control algorithms is represented in Fig. 5.14. At the beginning of each interrupt routine, a signal is raised indicating that the processor is executing the control task. When the new duty ratio is obtained, or when no more operations related to the control need to be performed, the signal returns to its low impedance state. The communication 85 function is not included in the measurement to avoid any overhead. The main results of this analysis are summarized in the Table 5.1. Fig. 5.14 shows clearly that the predictive schemes are more demanding in calculation during their active state than a conventional controller. However, the additional computational effort is kept reasonably small. For instance, it is only of 4 % for the Simplified Predictor, 10 % for the Extended Simplified Predictor, and 15 % for the Modified Predictor. The major advantage of both Simplified and Extended Simplified Predictor is that, on average, the computation time of the processor for control tasks is much lower. As compared to a conventional structure, 45% to 60%> of the computational resources dedicated to the control algorithm can be freed by simply implementing either the SP or ESP structures. As a result, other functions such as monitoring, diagnosis, interface, security, etc... can be handled by the same processor, thus adding expandability to existing hardware boards. Table 5.1 Computational time for different control schemes MP CDC* SP ESP Computational time: Maximum time per cycle (in p.u.) Average time per cycle (in p.u.) 1 1.15 1.04 1.1 1 1.15 0.55 0.40 The conventional digital controller maximum and average time per cycle is taken as basis for the comparison Another interesting application of the Simplified or Extended Simplified predictors is that more than one converter can be controlled by the same DSP. This could be particularly useful in power supplies integrating an additional converter for power factor correction (PFC). 5.3 Summary In this chapter, different control concepts based on predictive schemes have been validated through experimentation. It has been proved that prediction by linear extrapolation can improve the control performances of the supply for a very limited additional computational cost. Also, it has been shown that up to 60 % of the 86 microprocessor resources can be re-directed to other task, while keeping the same control performances as the conventional controller. Finally, the simplicity of the implementation makes of this technique a considerable asset to any digitally controlled power supply. 3-T. Fig. 5.14 Computation time of the DSP with different control algorithms (a) Conventional digital control (b) Modified Predictor (c) Simplified Predictor (d) Extended Simplified Predictor 87 Chapter VI CONCLUSION In this thesis, a number of issues regarding the implementation of a digital controller applied to a dc switchmode power supply has been investigated. A brief section opens this chapter by summarizing the major concluding remarks obtained in the early chapters concerning digital control. The contribution of this thesis is then presented and finally some suggestions for future work are discussed at the end of this chapter. 6.1 About Digital Control Chapter 2 and 3 of this thesis have been dedicated to the study of digital control applied to a dc power supply application. Chapter 2 emphasized mostly some background material concerning the structure of a current mode controller, while Chapter 3 was oriented towards the design of a conventional digital controller based on an analog design. The following conclusions concerning digital control can be drawn from those two chapters: i. The average current mode control is the only control scheme which can be digitalized. Because of the switching nature of the converter, peak current mode control schemes do not have any equivalent in digital. As a result, the maximum sampling frequency at which the controller can be operated is equal to the switching frequency. Therefore, it is not possible to improve the control performance by increasing the sampling frequency as it is often the case with other applications. ii. The time delay inherent to the digital control structure substantially degrades the controller bandwidth. This time delay consists of two distinct parts: the zero-order-hold and the sampling delay which results from the A / D conversion, computation, and P W M generation. The overall time delay has been estimated to be equal to 1.5 the sampling period. The case study presented in this thesis has shown that, as compared to an analog controller, the bandwidth of a digital controller is reduced by about 85% because of this delay. A similar result has been obtained with another converter (see Appendix A). The effect of the 88 time delay on the control performance of the converter is then very significant. For instance, it has been shown that a conventional digital controller designed to control the output voltage of the full bridge converter presented in this thesis was not able to meet with the technical specification required by the manufacturer. It has been concluded that for high-end products, digital control does not provide the designers with a satisfactory solution, iii. The last point tackled in this thesis concerns the effect of quantization noise and limited word length. It has been observed through simulation and experimentation that a limited A / D resolution does not reduce the system stability. However, it has a strong effect on the output voltage quality since a low resolution adds noise and a large dc offset. Regulating dc quantities gives the advantage that a level shifting technique can be used to increase the A / D resolution to an appropriate level. Finally, the resolution of the P W M (or the D / A converter) does not degrade the control performance. 6.2 Contribution The primary objective of this thesis is the compensation of the digital control time delay to improve the stability of the control loop, and thus increase the controller bandwidth. This objective has been met by using a simple and straightforward extrapolation technique. Two control schemes based on this technique were proposed: i. The Modified Predictor is a model based predictive controller which reduces the overall time delay to half a sampling period in the low frequency range. It has a high phase lag compensation capability which allows the designer to significantly increase the controller bandwidth. However, this scheme requires an accurate knowledge of some of the converter parameters. As a result, it is not as robust as a conventional controller and might lead to instability if poorly designed. It also uses more computational resources. The calculation of the estimate values requires an additional computational time of 15% as compared to the conventional structure. ii. A n alternative solution is to use the Simplified Predictor. This control scheme reduces the overall time delay to one sampling period. As such, it has a lower phase lag compensation capability than the Modified Predictor, but can still improve the controller bandwidth. Its major advantage is that it is not based on the process model, and as such can be considered as a robust control scheme. It is also very simple to implement and the additional computation time is limited to 4%, which makes it efficient in a tight real-time environment. 89 The proposed Modified and Simplified Predictor both rely on the assumption that the sampling frequency is much higher than the natural frequency of the converter. They also rely on the fact that the process is modeled by a second order transfer function. These schemes are therefore not valid for higher order processes, but can be implemented on any second-order system verifying (4.6). Their interest is then not solely restricted to the SMPS applications. This thesis also focuses on the improvement of the control algorithm computational efficiency. It has been shown that: i. The Simplified Predictor reduces the average computational time of the control algorithm by 45%. The control variable in this scheme is updated only once in every two sampling periods, which frees a large amount of computational power which can be used for other functions. ii. The computational efficiency can be further improved by using the parabolic extrapolation technique. The control scheme based on this technique and referred to as the Extended Simplified Predictor results from an extension of the Simplified Predictor concept. The control variable is updated only once in every three sampling periods. The overall time delay is therefore similar to a conventional digital controller. No improvement of the control loop stability should be expected. Experimental results have shown that 60% of the computational resources are freed as compared to a conventional controller. The Extended Simplified Predictor provides a simple way to add expandability and flexibility to existing control boards. In this thesis, three predictive control structures have been proposed and commented. It appears that the Simplified Predictor represents a good compromise in terms of robustness, bandwidth and computational efficiency. 6.3 Suggestions for Future Work This work has mostly emphasized the potential of the linear and parabolic extrapolation techniques as predictive schemes. We have been able to significantly improve on both the control loop bandwidth and the computational efficiency of the control algorithm. Also, the calculation cost associated with each predictive structure has been kept reasonably small. 90 A n interesting area of research would be to derive a control scheme which reduces the real time constraints by spreading the computation of the PI algorithm over two sampling periods. A combination of linear and parabolic extrapolation can then be used to compensate for the time delay. This control scheme would allow the designer to select a lesser processor or achieve a higher sampling frequency. Another interesting area of research concerns PFC stages and their control. As stated previously, the Simplified Predictor can be used to control both the power supply converter and the P F C converter. This technique's advantage is that information on the dc bus voltage is available and can be used directly as a feedforward quantity to compensate fully for the dc bus ripple, achieving therefore a higher quality in the output voltage or current regulation. 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Andreycak, "Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 P W M Controller", in Unitrode Application Note U-136A, pp. 3-300 to 3-311 94 Appendix A A P P L I C A T I O N TO T H E X F R 2.8 k w Appendix A presents simulated results when applying the different control structures to the power circuit of the X F R 2.8 kW from Xantrex Technology Inc (see Table A . l ) . Table A . l XFR 2.8 kW parameters and specifications Value Unit 40 V 280 V P 2.8 kW T 35 us Symbol Nominal values : Output voltage dc bus voltage Output power Switching period V o,n Vdc,n * o,n •* sw Transformer: Turns ratio m 4.6 Capacitor c, 8 mF Inductor Capacitor L C 150 14 uH mF c «8 mQ «80 mQ Input filter Outputfilter: Parasitic elements : Capacitor ESR Inductor winding resistance r As compared to the power circuit considered throughout this thesis, the X F R 2.8 k W is a commercial product already distributed in its analog version. Its switching frequency is higher with 28.7 kHz. As a result, the bandwidth of the conventional digital controller is wider than the experimental setup, which results in a better rejection of the dc bus ripple. As stated in Chapter 3, the difference between digital control and analog control tends to dim for higher switching frequencies, as far as the dc bus ripple is concerned. This particular disturbance might not be an issue anymore for high switching frequency © 95 converters, which is the actual technology trend. Nevertheless, the prediction structures improves considerably the performance of the power supply under load changes. The higher computational efficiency of the SP and ESP might also provide designers with new possibilities as for the definition of the power supply functionality. Table A.2 Control parameters AC* CDC MP SP 5.7 kHz >90° 2.0 kHz 55 ° 4.1 kHz 55 ° 2.7 kHz 55 3.0 kHz >80° 0.8 kHz 55 ° 2.1 kHz 58° 1.6 kHz 55 ° 0.088 92 0.031 45 0.041 83 0.035 60 53 ps 200 ps 76 ps 100 ps Inner loop : Cross-over frequency Phase margin 0 Outer loop: Cross-over frequency Phase margin Control Parameters : K v A C : Analog Controller CDC : Conventional Digital Controller 5.00m Digital Uontrollef 4.00m Simplified Trec!icfo~r Moiified "Preolictdr" Analog Controller mlm 120.00 Fig. A . l 180.00 240.00 300.00 Frequency (H^i 360.00 420.00 Harmonic spectrum of the output voltage 96 40.40 40.20 39.60 39.40 31.00 31 .SO 32.00 32.50 33.00 33.50 Time (ms) Fig. A.3 Load disturbance compensation (full load to 10%) 34.00 Table A.3 Control performances AC CDC MP SP 3.8 mV 1.6 mV 1.9 mV 2.7 ms 4 ms 1.6 ms 2.5 ms 1.8 ms 3 ms 1 1.15 1.04 1 1.15 0.55 Output voltage quality : R M S noise 1.5 mV (including switching noise) Setting time for load change : 1.4 ms 10% to full load Full load to 10% 2.5 ms Computation time : Maximum time per cycle ' N / A . (in p.u.) Average time per cycle N/A. (in p.u.) Appendix PROGRAM B LISTING In this appendix, the C240 program controlling the power supply is listed and commented. The four different control schemes are programmed in the functions CDC (), MP (), SP ( ) , and ESP ( ) . The user can then choose between either one of them. A function S t a r t u p () is also included for the soft start of the converter. # include " C 2 4 0 Re g. h " /* Header file containing the address of the C240 registers */ #include "Comm2.h" /* Headerfilecontaining the communication functions */ int i ; int i i ; i n t flag=0; i n t flags=0; i n t s=0,ss=0; unsigned i n t Voref=18550; s i g n e d l o n g i n t P=0; s i g n e d l o n g i n t 1=0; i n t err=0; /* Outputvoltage reference */ s t r u c t SRComm u; /* Structure defined in Comm2.h - usedfor communication */ s t r u c t C o n t r o l l e r /* Definition of the controller structure which contains information relative to control parameters, samples, and saturation values */ { /* Sampled data */ unsigned i n t i L ; u n s i g n e d i n t Vo; unsigned i n t iLmeas; u n s i g n e d i n t Vomeas; unsigned i n t iLraeas_old; unsigned i n t Vomeas_old; unsigned i n t iLmeas_old2; u n s i g n e d i n t Vomeas_old2; . 99 /* Control parameters */ i n t innKd, innTd; /* parameters for CDC */ i n t outKd, outTd; i n t i n n K s , i n n T s ; /* parameters for SP */ i n t outKs, outTs; i n t i n n K s 2 , i n n T s 2 ; /* parameters for ESP */ i n t outKs2, outTs2; i n t innKdm, innTdm; /* parameters for MP */ i n t outKdm, outTdm; /* Intermediate values */ i n t out I n t ; /* Old integral values */ int innlnt; i n t K l ; /* Correction term for MP */ /* Controllers outputs */ u n s i g n e d l o n g i n t i L r e f , d, d _ o l d ; /* Saturation and anti-windup values */ i n t iLref_min, iLref_max; i n t d_min, d_max; } c; void { Init() /* Control parameters */ c c c c iLmeas Vomeas iLmeas Vomeas = 0; = 0; o l d = 0; o l d = 0; c c c c innKd innTd outKd outTd = = = = 13; 9; 8; 36; c c c c innKs innTs outKs outTs = = = = 4; 7; 11; 150; c c c c innKs2 innTs2 outKs2 outTs2 = = = = 13; 27; 8; 108; c c c c innKdm innTdm outKdm outTdm = = = = 23; 34; 13; 110; c.outlnt=0; c.innlnt=0; c.iLref=0, c.d=0, c . d _ o l d = 0 ; c.iLref_min=0; c.iLref_max=19650; c.d_min=25; c. d__max=4 7 5 ; main() { asm asm asm asm asm asm asm (" . g l o b a l c i n t O ") ; (" . s e c t \ " . i n i \ " ") ; (" b _ c _ i n t O ") ; (" r e t c " ) ; ( "r e t c " ) ; (" b c int2 " ) ; ( ". s e c t \ " . t e x t \ " " ) ; w a i t s t a t e () ; /* This function comes from an assembly file linked with the main program — it defines the number of waitstates for I/O operations */ I n i t () ; /* Initialization of main flags */ f l a g = 0; ii=0; s=0; ss=0; /*Serial Communication*/ SerConfig(9600) ; InitComm(&u); /* Interrupt initialization */ * I MR = 0 x 0 0 0 2 ; /* Only the interrupt 2 is unmasked */ *IFR = O x f f f f ; *EVIMRA = 0 x 2 0 0 ; *EVIVRA = 0 x 0 ; *EVIFRA = O x f f f f ; /* PWM initialization */ * T1 PR = 10 0 0; /* The period is fixed to 100 us V *ACTR = 0 x 0 6 6 6 ; *CMPR1 = 0; *CMPR2 = 1 0 0 0 ; *COMCON = 0 x 0 3 0 7 ; *DBTCON = 0 x 3 0 6 0 ; *GPTCON = 0 x 4 1 ; *TlCON = 0x2842; *COMCON = 0 x 8 3 0 7 ; /* A/D control register initialization */ *ADCTRL1 = 0 x 3 8 5 a ; *ADCTRL2 = 0 x 0 0 0 6 ; 101 asm(" asm(" CLRC INTM ") ; CLRC CNF ") ; f or (; ; ) ; /* Infinite loop */ } v o i d Startup () /* Soft start function */ { i++; while(*ADCTRL1 & 0x80) { }; /* Waiting loop for end oJacquisition *< c . i L m e a s = ( u n s i g n e d i n t ) *ADCFIF01 >> 1; c.Vomeas = ( u n s i g n e d i n t ) *ADCFIF02 » 1; if(i>=100) { i=0; if(c.Vomeas<18500) { c.d++; ( c . d > c . d _ m a x ) ? c.d= ( c . d < c . d m i n ) ? c.d= c.d_max:1; c.d min:1; *CMPR2 = 1 0 0 0 - c . d ; *CMPR1 = c . d ; } else { flag=l; c.innlnt=c.d; c.outInt=c.iLmeas; c.d_old=c.d; c.iLmeas_old=c.iLmeas; c.Vomeas_old=c.Vomeas; } } } v o i d CDC () /* Conventional Digital Control */ { while { *ADCTRL1 & 0x80) { } ; /* Waiting loop for end ofacquisition *, c . i L m e a s = ( u n s i g n e d i n t ) *ADCFIF01 » 1; c.Vomeas = ( u n s i g n e d i n t ) *ADCFIF02 » 1; e r r = ( s i g n e d long i n t ) Voref-c.Vomeas; P= ( s i g n e d l o n g i n t ) c . o u t K d * e r r » 2; /* Proportional term ( P > 3 2 7 6 7 ) ? P= 3 2 7 6 7 : 1 ; /* Check overflow */ ( P < - 3 2 7 6 8 ) ? P= - 3 2 7 6 8 : 1 ; 1=(signed long i n t ) c.outTd*err » !+=( s i g n e d l o n g i n t ) c o u t I n t ; 8; /* Integral term */ ( I > c . i L r e f _ m a x ) ? 1= c. i L r e f _ m a x : 1; /* Anti Windup */ ( K c . i L r e f _ m i n ) ? 1= c. i L r e f _ m i n : 1 ; c.outInt=I; c . i L r e f = ( s i g n e d l o n g i n t ) P+I; (c . i L r e f >c. i L r e f _ m a x ) ? c . i L r e f = c . i L r e f _ m a x : 1; /* Saturation*/ (c.iLref<c.iLref_min)? c.iLref= c.iLref_min:1; err=(signed long i n t ) c.iLref-c.iLmeas; P = ( s i g n e d l o n g i n t ) c . i n n K d * e r r » 1 1 ; /* Proportional term */ ( P > 3 2 7 6 7 ) ? P= 3 2 7 6 7 : 1 ; /* Check overflow */ ( P < - 3 2 7 6 8 ) ? P= - 3 2 7 6 8 : 1 ; 1=(signed long i n t ) c.innTd*err I+= ( s i g n e d l o n g i n t ) c . i n n l n t ; ( I > c . d_max) ? 1= c. d_max: 1; ( K c . d_min) ? 1= c . d _ m i n : l ; c.innlnt=l; >> 1 3 ; /* Integral term*/ /* Anti Windup */ c . d = ( u n s i g n e d l o n g i n t ) P+I; ( c . d>c. d_max) ? c. d= c. d_max: 1; /* Saturation */ ( c . d < c . d _ m i n ) ? c.d= c . d _ m i n : l ; * CMPR2 = 1 0 0 0 - c . d ; /* Load new duty ratio */ *CMPR1 = c . d ; v o i d MP () /* Modified Predictor */ { while ( *ADCTRL1 & 0x80) { } ; /* Waiting loop for end of acquisition */ c . i L = ( u n s i g n e d i n t ) *ADCFIF01; c.Vo = ( u n s i g n e d i n t ) * A D C F I F 0 2 ; c.Kl=(int) (c.d-c.d_old)*8; c.iLmeas=c.iL-c.iLmeas_old; c.iLmeas=c.iLmeas+c.Kl ; c.Kl=(int) (c.d-c.d_old) » c.Vomeas=c.Vo-c.Vomeas_old; c.Vomeas=c.Vomeas+c.Kl; 2; c . V o m e a s _ o l d = ( u n s i g n e d i n t ) c.Vo.>> 1; c . i L m e a s _ o l d = ( u n s i g n e d i n t ) c . i L >> 1; c.d_old=c.d; err=(int) Voref-c.Vomeas; P= ( s i g n e d l o n g i n t ) c. o u t K d m * e r r » 2; /* Proportional term */ (P>327 6 7 ) ? P= 327 67:1; /* Check overflow */ ( P < - 3 2 7 6 8 ) ? P= - 3 2 7 6 8 : 1 ; I = ( s i g n e d l o n g i n t ) c.outTdm*err » 8; I+=(signed l o n g i n t ) c . o u t l n t ; /* Integral term */ (I>c . i L r e f _ m a x ) ? 1= c. i L r e f _ m a x : 1; /* Anti Windup */ ( K c . i L r e f _ m i n ) ? 1= c. i L r e f _ m i n : 1 ; c.outInt=I; c . i L r e f = ( s i g n e d l o n g i n t ) P+I; (c. i L r e f >c. i L r e f _ m a x ) ? c . i L r e f = c. i L r e f _ m a x : 1; /*Saturation V (c.iLref<c.iLref_min)? c.iLref= c.iLref_min:1; err=(int) c.iLref-c.iLmeas; P = ( s i g n e d l o n g i n t ) c.innKdm*err >> 11; /* Proportional term */ (P>327 67)? P= 32767:1; /* Check overflow */ (P<-32768)? P= -32768:1; 1 = ( s i g n e d l o n g i n t ) c.innTdm*err >> 13; I+=( s i g n e d l o n g i n t ) c . i n n l n t ; /* Integral term */ (I>c. d_max) ? 1= c. d_max: 1; /* Anti Windup */ ( K c . d _ m i n ) ? 1= c . d _ m i n : l ; c.innlnt=l; c.d=(unsigned l o n g i n t ) P+I; (c.d>c.d_max) ? c.d= c.d_max:l; /* Saturation*/ (c.d<c.d_min)? c.d= c . d _ m i n : l ; * CMPR2 = 10 0 0 - c. d; /* Load new duty ratio */ *CMPR1 = c.d; } v o i d SP () { /* Simplified Predictor */ if(s==0) { s=l; } else . { s=0; w h i l e ( *ADCTRL1 & 0x80) { }; /* Waiting loop for end of acquisition */ c . i L m e a s _ o l d = (unsigned c.Vomeas_old = (unsigned c.iLmeas = (unsigned c.Vomeas = (unsigned i n t ) *ADCFIF01 » i n t ) *ADCFIF02 » 1; 1; i n t ) *ADCFIF01; i n t ) *ADCFIF02; c.iLmeas=c.iLmeas-c.iLmeas_old; c.Vomeas=c.Vomeas-c.Vomeas_old; err=(signed l o n g i n t ) Voref-c.Vomeas; P= ( s i g n e d l o n g i n t ) c . o u t K s * e r r >> 2; /* Proportional term */ 104 (P>327 6 7 ) ? P= 327 67:1; /* Check overflow V ( P < - 3 2 7 6 8 ) ? P= - 3 2 7 6 8 : 1 ; I = ( s i g n e d l o n g i n t ) c . o u t T s * e r r >> 8; I+=(signed long i n t ) c . o u t l n t ; /* Integral term */ ( I > c . i L r e f _ m a x ) ? 1= c. i L r e f _ m a x : 1; /* Anti Windup */ ( K c . i L r e f _ m i n ) ? 1= c. i L r e f _ m i n : 1 ; c.outInt=I; c . i L r e f = ( s i g n e d l o n g i n t ) P+I; (c . i L r e f >c . i L r e f _ m a x ) ? c. i L r e f = c. i L r e f _ m a x : 1; /* Saturation */ (c.iLref<c.iLref_min)? c.iLref= c.iLref_min:1; err=(signed long i n t ) c.iLref-c.iLmeas; P = ( s i g n e d l o n g i n t ) c . i n n K s * e r r » 9; /* Proportional term */ ( P > 3 2 7 6 7 ) ? P= 3 2 7 6 7 : 1 ; /* Check overflow */ ( P < - 3 2 7 6 8 ) ? P= - 3 2 7 6 8 : 1 ; 1 = ( s i g n e d l o n g i n t ) c . i n n T s * e r r >> 1 1 ; I+=( s i g n e d l o n g i n t ) c . i n n l n t ; /* Integral term */ ( I > c . d _ m a x ) ? 1= c . d _ m a x : l ; /*Anti Windup */ ( K c . d _ m i n ) ? 1= c . d _ m i n : l ; c.innlnt=l; c . d = ( u n s i g n e d l o n g i n t ) P+I; ( c . d>c. d_max) ? c. d= c. d_max: 1; /* Saturation */ ( c . d < c . d _ m i n ) ? c.d= c . d _ m i n : 1 ; *CMPR2 = 1 0 0 0 - c . d ; /* Load new duty ratio */ *CMPR1 = c . d ; } } v o i d ESP () /* Extended Simplified Predictor */ { if(ss==0) { ss=l ; } else { if(ss==l) { ss=2 ; c.iLmeas_old2 = (unsigned c.Vomeas_old2 = (unsigned i n t ) *ADCFIF01 i n t ) *ADCFIF02 » » 1; 1; } else { while (* ADCTRL1 & 0x80) { }; /* Waiting loop for end of acquisition */ c . i L m e a s _ o l d = ( u n s i g n e d i n t ) * A D C F I F 0 1 » 1; c . V o m e a s _ o l d = ( u n s i g n e d i n t ) *ADCFIF02 >> 1; c . i L m e a s = ( u n s i g n e d i n t ) * A D C F I F 0 1 >> 1; c.Vomeas = ( u n s i g n e d i n t ) *ADCFIF02 » 1; c.iLmeas=c.iLmeas-c.iLmeas_old; c.iLmeas=3*c.iLmeas+c.iLmeas_old2; c.Vomeas=c.Vomeas-c.Vomeas_old; c.Vomeas=3*c.Vomeas+c.Vomeas_old2; err=(signed long i n t ) Voref-c.Vomeas; P=( s i g n e d l o n g i n t ) c . o u t K s 2 * e r r >> 2; /* Proportional term */ (P>327 6 7 ) ? P= 327 67:1; /* Check overflow */ ( P < - 3 2 7 6 8 ) ? P= - 3 2 7 6 8 : 1 ; I = ( s i g n e d l o n g i n t ) c . o u t T s 2 * e r r >> 8; I+=( s i g n e d l o n g i n t ) c . o u t l n t ; /* Integral term */ ( I > c . i L r e f _ m a x ) ? 1= c . i L r e f _ m a x : 1 ; /* Anti Windup */ ( K c . i L r e f _ m i n ) ? 1= c. i L r e f _ m i n : 1 ; c.outInt=I; c . i L r e f = ( s i g n e d l o n g i n t ) P+I; ( c . i L r e f >c. i L r e f _max) ? c. i L r e f = c . i L r e f _max: 1; /* Saturation*/ (c.iLref<c.iLref_min)? c.iLref= c.iLref_min:1; err=(signed long i n t ) c.iLref-c.iLmeas; P = ( s i g n e d l o n g i n t ) c . i n n K s 2 * e r r >> 1 1 ; /* Proportional term */ (P>327 6 7 ) ? P= 327 67:1; /* Check overflow */ ( P < - 3 2 7 6 8 ) ? P= - 3 2 7 6 8 : 1 ; 1 = ( s i g n e d l o n g i n t ) c . i n n T s 2 * e r r » 13; I+=( s i g n e d l o n g i n t ) c . i n n l n t ; /* Integral term */ (I >c. d_max) ? 1= c . d_max: 1; /* Anti Windup */ ( K c . d _ m i n ) ? 1= c . d _ m i n : l ; c. i n n l n t = l ; c . d = ( u n s i g n e d l o n g i n t ) P+I; ( c . d>c. d_max) ? c. d= c. d_max: 1; /* Saturation */ ( c . d < c . d _ m i n ) ? c.d= c . d _ m i n : l ; *CMPR2 = 1 0 0 0 - c . d ; /* Load new duty ratio */ *CMPR1 = c . d ; ss=0 ; 106 nterrupt v o i d c_int2 () /* Interrupt routine */ ADCTRL1 = 0x3 8 5b; /* Start acquisition again */ if(flag==0) { Startup () ; /* Soft start */ } else { /* Control structure to be chosen by programmer */ /* CDC(); */ /* MP(); */ /* SP(); */ /* ESP(); */ } Comm ( & u) ; /* Call to the communication functions */ *EVIFRA=0xffff;
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Time delay compensation of digital control for switchmode DC power supplies using prediction techniques Bibian, Stéphane 1999
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Title | Time delay compensation of digital control for switchmode DC power supplies using prediction techniques |
Creator |
Bibian, Stéphane |
Date Issued | 1999 |
Description | The control of switchmode dc power supplies has been traditionally implemented in analog electronics for its low cost, high bandwidth, and proven technology. However, the emergence of advanced microprocessors and Digital Signal Processors (DSPs) has made it possible for power supply manufacturers to consider digital technology a suitable option. As compared to analog control, digital control provides a number of advantages such as reduced susceptibility to aging and environmental variation (temperature, humidity, etc.), better noise immunity, ability to handle complex control schemes and monitoring functions, possibility to implement communication functions for fault and status information, and easy re-programming for different applications. With the downward trend of microprocessor prices and the versatility of the hardware architecture, digital control offers a cost-effective solution which can compete with analog technology. However, one of the major drawbacks of digital control is the limited bandwidth caused by the inherent time delay required for A/D conversion, computation and PWM generation. Such delay degrades the control loop performance, which makes it difficult to comply with technical specifications in many high-performance products. In this thesis, a simple and straightforward predictive technique based on linear extrapolation is presented to compensate for this delay. Two predictive controllers are derived and applied to a full bridge dc power supply. Simulation and experimental results show that the performances of the converter with respect to dc bus ripple and load disturbances can be significantly improved. Those schemes are characterized by a low computational cost which makes them particularly attractive in the demanding real-time environment due to the ever increasing switching frequency of the converter. A similar prediction concept based on a second order parabolic extrapolation is also presented. This predictor substantially reduces the amount of calculation needed to obtain similar results to a conventional controller, thus freeing valuable processor resources. These resources can be used for less critical tasks such as communication and user interface. As a result, the processor is not solely dedicated to the control of the power supply but can incorporate other functions, thus adding functionality and expandability to the system. Finally, this thesis assesses typical digital control issues such as word length, A/D resolution and fixed point programming. |
Extent | 4779980 bytes |
Genre |
Thesis/Dissertation |
Type |
Text |
File Format | application/pdf |
Language | eng |
Date Available | 2009-06-16 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0065283 |
URI | http://hdl.handle.net/2429/9251 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Graduation Date | 1999-11 |
Campus |
UBCV |
Scholarly Level | Graduate |
Aggregated Source Repository | DSpace |
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