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Design and VLSI implementation of a convolutional encoder and majority logic decoder for forward error… Friedman, David 1992

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Design and VLSI Implementation of aConvolutional Encoder and Majority LogicDecoder for Forward Error Correction inIntrabuilding Power Line CommunicationsbyDavid FriedmanB. Sc. Computer Eng., Kiev Polytechnical Institute, 1986M. Sc. Computer Eng., Kiev Polytechnical Institute, 1986A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR ThE DEGREE OFMASTER OF APPLIED SCIENCEJnTHE FACULTY OF GRADUATE STUDIESDEPARTMENT OF ELECTRICAL ENGINEERINGWe accept this thesis as conforming_fretandardTHE UNIVERSITY OF BRITISH COLUMBIASeptember 1992© David Friedman, 1992.In presenting this thesis in partial fulfilment of the requirements for an advanceddegree at the University of British Columbia, I agree that the Library shall make itfreely available for reference and study. I further agree that permission for extensivecopying of this thesis for scholarly purposes may be granted by the head of mydepartment or by his or her representatives. It is understood that copying orpublication of this thesis for financial gain shall not be allowed without my writtenpermission.(Signature)Department of Ei &.The University of British ColumbiaVancouver, CanadaDate E’fT 23 ZDE.6 (2/88)AbstractThe need for simple and effective forward error correction (FEC) schemes for use inmodern low-cost communication systems continues, especially for intrabuilding power line(IPL) communications. In particular, the use of short random error correcting convolutionalcodes with a moderate degree of interleaving has been shown to be a viable FEC optionthat enhances the performance of communications over the power line channel.In this thesis, a VLSI convolutional encoder and threshold decoder (codec) chip foruse in intrabuilding power line communications was successfully designed, fabricatedand tested. The chip implements the rate 1/2 (2, 1, 6) self-orthogonal convolutional codetogether with programmable degrees of interleaving = 1, 3, 5, 7). This code providesrandom and burst error correcting capabilities. Threshold or majority—logic decoding wasselected as the algorithm to be used, due to the ease of its implementation and itsappropriateness for burst error channels. Interleaving and deinterleaving can easily beincluded in the encoder and decoder, respectively.The codec is a semi-custom design that uses standard library cells, and was fabricated using 1.2 1tm CMOS technology. A maximum throughput of 50 Mbps is feasible.Built-In Self-Test was incorporated into the design providing 100% single stuck-at faultcoverage, with under 10% of silicon area overhead.To evaluate the effectiveness of the VLSI codec, the chip was integrated onto twoexisting power line modems. Performance tests were completed for coded and uncodeddata transmissions under conditions of varying channel quality. This study successfullydemonstrates that the use of this FEC chip is effective in increasing the error—freethroughput of intrabuilding power line communications. The chip provides the possibilityof maintaining reliable communications over channels that could otherwise not be usedfor data communications at 19.2 Kbps.11ContentsAbstract iiList of Figures vAcknowledgments ViiiChapter 1 IntroductionSection 1 Background and Motivation 1Section 2 Thesis Outline 4Chapter 2 Forward Error Correction Coding in Power LineCommunications 7Section 1 Data Communication Systems 7Section 2 Intrabuilding Power Distribution Circuits 9Topic 1 Building Wiring Plans 10Section 3 Intrabuilding Power Line Communication ChannelCharacteristics 13Topic 1 Power Line Error Sources 13Section 4 Evaluation of Forward Error Correction Codes for High SpeedPower Line Data Communications 16Topic 1 Block Codes 17Topic 2 Convolutional Codes 18Chapter 3 Convolutional Coding for Power Line Data Communications 21Section 1 Encoding of Convolutional Codes 21Section 2 Decoding of Convolutional Codes 23Section 3 Self-Orthogonal (2, 1, 6) Code 26Section 4 Properties and Pertormance of Threshold Decoding 30‘UChapter 4Section 1Section 2Section 3Section 4Section 5Topic 1Section 6Chapter 5Section 1Section 2Section 3Topic 1Topic 2Section 4Topic 1Topic 2Chapter 6Section 1Section 2Bib’iographyAppendix AAppendix BAppendix C353537394143485056565861626668688893VLSI Design and ImplementationGeneral DescriptionEncoderDecoderSupport BlocksBuilt—In Self—TestTest ProcedureDesign VerificationCodec Performance TestsSystem Level ImplementationTest ParametersPerformance in Controlled Environments.AWGN ChannelBurst Error ChannelPerformance over the Power-Line ChannelLocal Area CommunicationsExtensive Area Communications over the General Sub-Systemand across Sub-Systems 72Summary 84Concluding Remarks 84Suggestions for Future Research 86Codec Schematic and Layout Representations.Codec Bonding DiagramsEnhanced PLM Schematic Diagrams99103ivList of FiguresFigure 1 Block diagram of a data communication system 8Figure 2 Block diagram of a simplified communication system 9Figure 3 Residential power delivery scheme 11Figure 4 Commercial/Industrial three-phase power delivery scheme. . 12Figure 5 Block diagram of a (2, 1, 6) convolutional encoder 22Figure 6 Block diagram of a (2, 1, 6) threshold decoder 29Figure 7 Syndrome register (feedback links marked a-d) 31Figure 8 Schematic diagram of a (2, 1, 6) convolutional encoder 38Figure 9 Schematic diagram of a (2, 1, 6) majority—logic decoder. . . 40Figure 10 Variable interleaving implementation 43Figure 11 Schematic diagram of 7CelI block 44Figure 12 Schematic diagram of 3Cell block 45Figure 13 Built-In Self-Test schematics 47Figure 14 Built-In Self-Test simulation (without faults in the CUT) 49Figure 15 Built-In Self-Test simulation (with a single stuck-at fault in thedecoder) 51Figure 16 Example of STL program 53Figure 17 Packet Format 57Figure 18 Enhanced modem performance for AWGN channel: (a) BER,(b) BLKER 63Figure 19 Channel BER vs (a) Decoded BER, and (b) BLKER for AWGNChannel 65Figure 20 Channel BER vs Decoded BER (a), and BLKER (b) for aBursty channel 67Figure 21 Channel BER vs Decoded BER (a), and BLKER (b) for X to Ychannel 69VFigure 22 Channel BER vs Decoded BER (a), and BLKER (b) for Y to Ychannel 70Figure 23 Channel BER vs Decoded BER (a), and BLKER (b) for Z to Ychannel 71Figure 24 BER as a function of time for transmissions from Rm 458 toRm 214. (a) Transmissions over the General PowerSub-system, (b) Transmissions across Power Sub-systems. 74Figure 25 Throughput as a function of time for transmissions from Rm458 to Rm 214. (a) Transmissions over the General PowerSub-system, (b) Transmissions across Power Sub-systems. 75Figure 26 BER as a function of time for transmissions from Rm 458 to the3rd floor stairwell. (a) Transmissions over the General PowerSub-system, (b) Transmissions across Power Sub-systems. . 76Figure 27 Throughput as a function of time for transmissions from Rm458 to the 3’ floor stairwell. (a) Transmissions over theGeneral Power Sub-system, (b) Transmissions across PowerSub-systems 77Figure 28 Average BLKER (over 24 hours) for each of the testedchannels 79Figure 29 Schematic diagram of the (2,1,6) convolutional encoder andthreshold decoder with fixed interleaving degree =7) 93Figure 30 Layout representation of the (2,1,6) convolutional encoder andthreshold decoder with fixed interleaving degree (A=7). Designidentification name BCCOD. (Only the metal layers areshown) 94Figure 31 Schematic diagram of the (2,1,6) convolutional encoder andthreshold decoder with programmable interleaving degrees(A=1, 3, 5, 7) 95viFigure 32 Layout representation of the (2,1,6) convolutional encoder andthreshold decoder with programmable interleaving degrees(A=1, 3, 5, 7). Design identification nam.e BCMAJ. (Only themetal layers are shown) 96Figure 33 Schematic diagram of the (2,1,6) convolutional encoder andthreshold decoder with programmable interleaving degrees(A=1, 3,5,7) and BIST 97Figure 34 Layout representation of the (2,1,6) convolutional encoder andthreshold decoder with programmable interleaving degrees(A=1, 3, 5, 7) and B 1ST. Design identification name BCBST.(Only the metal layers are shown) 98Figure 35 68—Pin PGA (a) pin numbering scheme, and (b) bondingdiagram 99Figure 36 BCCOD bonding diagram 100Figure 37 BCMAJ bonding diagram 101Figure 38 BCBST bonding diagram 102VIIAcknowledgmentsI would like to express my sincere gratitude to my supervisors Dr. R. W. Donaldson,and Dr. A. lvanov for their support, guidance and encouragement throughout the courseof this research.I am very grateful to Dave Gagne for his support during the initial stages of the chip’sdesign. I would also like to thank Barry Buternowsky for his assistance in the constructionand testing of the enhanced modem prototypes, as well as for his helpful suggestionsand enlightening discussions.viiiChapter 1Introduction1.1 Background and MotivationThroughout the previous decade the utilization and application of computer equipmenthas become increasingly widespread, causing an increase in the demand for more efficient and reliable communication technologies. This trend has affected the developmentof Local Area Networks (LANs) used forfactory and office automation, smart homes, datacommunications, remote sensing, security and access control, and energy management.The common element of all these network systems is the need for intrabuildingcomputer communications, for which different types of physical communication mediacan be used. Such media includes twisted pair wires, coaxial cables, infrared linksand fiber optic lines. However, the practical application of these networks has beenlimited to a great extent by the costs, inconveniences, time and complexities of installingcommunications wiring in existing buildings and production sites. Scheduling delays,dislocations during installation, preservation of building appearances, and the logistics ofallocating installation personnel are a few of the problems encountered. Furthermore, withinstalled cabling the network has limited flexibility, reconfigurability, and expandability [1].The use of the already installed and virtually universal power lines as a communicationmedia has long been recognized as a possible alternative to a dedicated channel. Theevident advantages include:1. Presence of an already existing and widespread physical communication media inthe form of power electric distribution lines at no incremental cost.2. Easily accessible interface in the form of a standard wall plug.3. Universal coverage over the entire building.4. Reconfigurable, expandable and flexible power line LANs have no need for timeconsuming and costly rewiring.1Several commercial power line communication systems have been developed recently, including modems from Signetics, National Semiconductor, NONWIRE, BSR andExpertNet. However, the performance of these commercial systems is still limited, eventhough the demand for more efficient and reliable systems steadily grows.Power lines were not designed as a communication media and provide an inhospitable environment for data communications; noise and frequency dependent signalattenuation are common impairments. At low data rates, power line impulse noise isrelatively small; energy per data bit is high; and, reliable performance is achievable withlow transmitter power levels. As transmission speed increases the detrimental effects ofimpulse noise and fading similarly increase. At data rates above 4.8 Kbps impulse noisetends to become a dominant factor in determining the performance of the communicationchannel [2].Increases in transmission speeds of power line moderns generates a series of newproblems. The most significant of these is a steady growth in the Bit Error Rate (BER) ofthe transmitted data. It has been shown in previous studies [2] that an effective way tolower the BER while maintaining high data rates is the use of a method which detects andcorrects errors which occur during data transmissions due to the inevitable impairmentsof the power line channel. Such a technique is termed Forward Error Correction (FEC).Much work has been done to study and characterize the power line channel; someof this work has been used as a platform for this thesis. Chan and Donaldson showedin [2, 3], that rate 1/2 convolutional codes are effective and robust codes for the powerline channel (PLC). Specifically, the (2,1,6) self-orthogonal convolutional code with amoderate degree of interleaving has been shown to be a viable FEC option that willreduce the adverse effects of using the PLC as a communication channel. However,in some very noisy environments (channel BER>102)the use of FEC is not alwayssufficient to ensure reliable communications. In such cases FEC is used together withpacket retransmission and code combining which enable reliable communications evenover very hostile channels [4].The general structure of convolutional codes is relatively straight forward and the2encoders are simple to implement. However the decoding of such codes is a muchmore complex procedure. Viterbi [5] decoders must perform computations (where kis the number of inputs of the encoder) for each bit that is to be decoded, in order tomaintain high data rates the complexity and cost of these decoders grows exponentiallywith k. For this reason it is infeasible for use in low cost applications such as power linemodems. In such cases an alternative decoding scheme, such as majority logic decoding(MLD) may be employed, providing a less complex and cost-effective solution (wherecost is primarily measured by the gate count of the design). Majority logic or thresholddecoding, developed by Massey [6, 7], decodes the value of each bit according to thedata of only one constraint length. This limitation considerably simplifies the decodingprocedure, while minimizing the coding gain penalty.After system performance, the most important considerations when developing powerline communication equipment is cost, complexity, reliability, and size. The decisionto include FEC depends primarily on the affordability of the different schemes underdiscussion, since the overall cost of a high speed power line modem should not exceeda few hundred dollars to be considered a commercially attractive solution. Thresholddecoding, because of its simplified decoding procedure, is an excellent candidate for alow cost power line communications FEC scheme.Due to practical limitations regarding cost, complexity, reliability, and size, the use ofFEC in existing PLMs has been limited to prototype devices. FEC on these prototypes hasbeen successfully implemented using primarily medium scale integration (MSI) integratedcircuits (ICs), but cannot be considered a viable solution due to its large size and lowreliability. The need of a convolutional encoder and threshold decoder with variabledegrees of interleaving, all on one chip, is clear. The design and implementation of sucha chip, using very large scale integration (VLSI) technology, is motivated by the followingfactors:1. Convolutional encoder I majority-logic decoder chips (codecs) are not commonlyavailable and existing Viterbi codecs are overly expensive for this type of application,costing $20 to $100 per chip.32. Commercially available convolutional codecs do not have variable interleaving capabilities integrated on the chips.3. The decoding algorithm is very similar to the encoding process. Because of thissimilarity certain structures are repeated in both blocks, making threshold decodingan attractive alternative for VLSI implementation.4. The number chips needed to implement the FEC scheme using MSI technology isexceedingly high (over 50 ICs), making the dimensions of the complete PLM to largefor use in many applications. The reliability of the completed device also decreasesdue to the large number of ICs and corresponding interconnections. The use of asingle chip VLSI codec provides minimum size and maximum reliability.5. The use of VLSI technology enables further integration of the PLM. Future designsmay integrate the entire modem (such as the modem implemented by Lee in [8]) andFEC modules onto a single chip.The testing of complex VLSI circuits is currently one of the most pressing problemsin VLSI design, due to the complexity of this task. Because of this fact and to complyto a rapidly growing industry wide standard testing technique, Built-In Self-Test (BIST)was incorporated into the design. BIST has become one of the most popular design fortestability (DFT) techniques, due to the fact, that it allows thorough testing of VLSI circuitsat reasonable cost, since the chip overhead due to BIST can be minimized by a properchoice of the implementation techniques. The inclusion of BIST on the codec will alsobe of great importance in future designs, when the entire modem and FEC modules areintegrated onto one chip, which could then have separate BIST circuitry for each of itsfunctional blocks.1.2 Thesis OutlineThe purpose of this thesis is to design, implement and evaluate a VLSI convolutionalencoder and threshold decoder for forward error correction on intrabuilding power linecommunication channels. Design simplicity and the use of reliable low cost solutions areof concern and are greatly emphasized.4The coder/decoder (codec) circuit was designed and fabricated using 1 .2 m CMOStechnology, and was evaluated on a variety of different power line communication environments with transmission rates up to 19.2 Kbps. The data collected from the testsshows the benefits of using FEC coding to combat power line channel impairments.After this introductory chapter, this thesis is organized as follows:Chapter 2 describes the power line communication channel, the importance andpotential benefits obtainable using FEC coding, as well as possible difficulties that canarise when codes that do not match the channel conditions or requirements are used.A summary of previous work (by others) comparing the performance of various randomand burst error correcting codes used on the power line channel (PLC) is presented.Chapter 3 presents several general considerations and comparisons regarding convolutional encoding and decoding and the use of interleaving in such cases, as well asa detailed theoretical description of the (2,1,6) self-orthogonal convolutional code and itsmajority-logic decoding. Specific aspects are emphasized, such as the effective constraintlength and the maximum error-correcting capability of the code. These aspects are important for understanding some of the design solutions and the BIST scheme implemented.Chapter 4 describes the codec hardware design and VLSI implementation. A generaldescription of each of the functional blocks, as well as a detailed overview of each ofthe hardware blocks is provided. Some particular codec features are presented anddiscussed, including the variable degree of interleaving and the BIST scheme employed.Also described are the test and verification processes involved in the different steps ofVLSI chip design and fabrication. These processes include design simulation during thepre-fabrication period and different post-fabrication tests performed on the codec usingspecialized automated test equipment (ATE) and bit error analyzers.Chapter 5 details the hardware aspects related to the interfacing of the codec to thepower line modem. Actual performance results obtained from a series of tests completedduring power line communications with and without the use of FEC are summarized.Several different parameters were recorded in each case such as bit error rate (BER),block error rate (BLKER), percent of lost packets and throughput (C). The tests were5repeated while varying the following: (1) degrees of interleaving, (2) channel conditions,(3) period of the day, and (4) transmitter power level.Chapter 6 provides a summary of the research results obtained. Details of the codecchip are given, which show that the VLSI implementation of the (2,1,6) convolutionalencoder and threshold decoder with variable degrees of interleaving is 10 to 50 timesmore efficient, with respect to silicon area, than other codecs of similar characteristics.The performance results demonstrate that the utilization of suitable, inexpensive FECcoding can foster efficient and reliable data transmission over otherwise unreliable powerline channels. Suggestions for further research are also included in this chapter.6Chapter 2Forward Error Correction Coding inPower Line CommunicationsThe theory and practice of error-correction coding is concerned with the protectionof digital information against errors that occur during data transmission. Error detectingand correcting techniques have a broad range of capabilities and are widely used in aseries of diverse and important applications. The recurrent problem with any high speeddata communication system is providing a method to control the errors that occur duringdata transmission through a noisy channel. In order to achieve reliable communicationseffective codes and efficient decoding algorithms must be developed and implemented.The use of error control techniques has grown substantially in the last decade and willcontinue to grow considerably with the use of anticipated advances in integrated circuittechnology.2.1 Data Communication SystemsIn a communication system data is transmitted from an information source through aphysical channel to a destination. Because a channel is normally subject to different typesof noise, distortion, and interference, the output of the channel often differs from its inputdue to the errors that result from impaired transmissions. The major concern in designingFEC codes is the control of errors such that reliable reproduction of information can beobtained.To efficiently design and implement FEC codes a well-known model of data communication systems is used extensively. The block diagram in figure 1 illustrates the basicsystem elements [91.Since the focus of FEC techniques are the channel encoder and channel decoder asimplified model of a coded data transmission system is generally used for their analysis.Such a model is represented in figure 2. Within this model the information source andsource encoder are combined into a digital source with output U; the modulator, channel7Figure 1 Block diagram of a data communication system.and demodulator are combined into a coding channel with input v and output r; and, thesource decoder and destination are combined into a digital sink with input u. QuantitiesU, v, e, r, and U may be either scalars or vectors.To properly design and implement an encoder/decoder pair, as we have set out to doin this thesis, the following issues must be considered: information must be transmittedin a noisy environment at high speeds and with low overhead; reliable reproduction ofthe information should be obtainable at the decoder output; and, the complexity of thecodec should be kept as low as possible.One of the requirements in the design of a communication system is extensiveknowledge of the characteristics of the communication channel. Signal attenuationand channel noise behavior must be understood to obtain high performance. SuchNoise8Figure 2 Block diagram of a simplified communication system.understanding is needed, particularly in designing or selecting FEC coding schemes. Theuse of an inappropriate code that does not match the channel conditions and impairmentswill result in inefficient or even incorrect error handling. The result is an unsatisfactorysystem error rate, which causes unacceptable delays and consequent degradation ofsystem throughput.2.2 Intrabuilding Power Distribution CircuitsThe way electrical power is distributed within a building is an essential point that mustbe understood in order to properly design systems that can effectively make use of theintrabuilding power lines as a communication channel.The network that distributes electric power from the generating plants to the endconsumers is a large and complex structure. Three-phase high voltage lines transmitNoise9power from generating plants to the substations, from where transmission to distributiontransformers occurs [10]. The secondary side of the distribution transformer connects tocircuit panels in the buildings. A single distribution transformer may provide power forseveral residential buildings, or for single buildings in industrial/commercial sectors. Froma circuit panel power is delivered to electrical loads via intrabuilding branch circuits [2].2.2.1 Building Wiring PlansIn residential housing or apartment units, the secondary side of the distributiontransformer delivers split-single-phase power to circuit panels by two 120 V lines 180° outof phase and a neutral conductor as shown in figure 3. The neutral conductor is normallyconnected to the grounded circuit panel. Electrical power is distributed throughout thebuilding on general purpose branch circuits which consisting of a 120 V line and a neutralconductor deliver power to small loads using standard wall plug-in sockets.Large appliances, such as refrigerators, washers, freezers, and dishwashers, areconnected to the distribution system using a special individual dedicated branch circuit.Appliances with large heating elements such as electric stoves, water heaters and dryersusually require a 240 V branch circuit. These appliances are connected to both 120 Vline, and the neutral [2].Commercial and industrial buildings are typically supplied with three—phase electricalpower as shown in figure 4. In large buildings, each floor or floor group may be suppliedby separate three-phase transformers. Standard branch circuits consisting of a 120 Vand neutral line supply small loads. Larger loads are supplied by circuits that delivereither single—phase or polyphase power [3].On each phase, the hot wire directly connects all loads. In addition, electric loadsprovide signal transmission paths between a 120 V line and a neutral line. Loadsconnected across two 120 V lines provide signal transmission paths from one phase toan other, together with the signal transmission path provided by the inherent capacitivecoupling across the supply transformer secondary.1025KV POWER LINEFigure 3 Residential power delivery scheme.DISTRIBUTIONTRANSFORMERTO RESIDENCE B120v &°NEUTRAL120V ORESIDENCE AI-i-METER., _SERVICE PANELCIRCUITBREAKERSSWITCHESLOADSBRANCH CIRCUITS11DISTRIBUTION TRANSFORMERLINESFigure 4 Commercial/Industrial three-phase power delivery scheme.rLFPANELL_ — —BRANCH CIRCUITS12All the electrical components and loads connected to a power distribution circuit forpart of the PLC, and affect signal transmission. Altogether, the differences in physicaldistance between nodes, together with constantly varying electrical loads causes thepower line network to be a hostile and complex communication environment [3].2.3 Intrabuilding Power Line CommunicationChannel CharacteristicsIt has been demonstrated through a series of commercial and industrial applications[11—13] that power lines may be used as an efficient and reliable communication channels. However, power line channels remain as an inhospitable environment for datacommunications. Substantial noise and frequency attenuation are found on most powerlines. Without well—designed error control coding means, bit errors in power line environments occur at unacceptably high rates. Hence, the actual throughput could representa fraction of the raw data rate [1].2.3.1 Power Line Error SourcesTo encourage successful use of PLC channels, extensive studies of its characteristicshave been performed [2, 14, 15]. These studies have shown that the signal transmissioncharacteristic and noise structure can be extremely complex, highly variable, and loaddependent. Communication signals on power lines are subject to channel attenuation,distortion, intersymbol interference, frequency and time fading, and both impulse andrandom noise. Of these error sources impulse noise is the most dominant.Attenuation is the amount by which a signal decreases in amplitude during transmission. The number and type of loads attached to any power line circuit will vary overtime; consequently, the signal attenuation will be highly variable and unpredictable. Suchvariations can exceed 20dB [2], even when the transmitter and receiver use the samephase. These attenuation values tend to be higher if the transmitter and receiver arenot on the same phase, and tend to increase on long transmission paths with manyloads. Attenuation is frequency dependent and increases with frequency, although suchincreases are not always monotonic. The signal may also exhibit periodic 6 Hz and 12013Hz fades that will cause periodic degradation in received signal to noise ratio which inturn causes periodic burst errors in digital transmissions [2].Variations in signal attenuation indicate that a signal transmission level which isadequate for a PLC with moderate attenuation may not be sufficient for networks withlarge attenuation. The use of the “worst case” approach is not a practical solution, sincein some cases, transmission may be subject to large attenuation of up to 50 dB [3]. Largetransmitter power levels to combat high attenuation would bring attached increases incost, power consumption, and interference.There are a series of approaches to solve this problem which include: applicationof suitable error control coding, use of appropriate data link protocols, use of repeatersin LAN5 with severe attenuation, and signal bypassing between different power phasesof the power system.Because attenuation may greatly vary on different links of a power line LAN, the biterror rate (BER) performance for such links will also vary. Some links may have relativelygood BER values while others can have very poor performance at any given moment.In contrast to attenuation, noise tends to decrease as frequency increases, sincenoise levels together with the data signals show increased attenuation with frequency;noise sources nearest to a receiver are a primary cause of bit errors [11]. Consequentlythe choice of signalling frequency is a compromise between a relatively high noise levelwith low signal attenuation and a high signal attenuation with reduced noise power.Noise. Power line noise contains both background and impulse components. Suchnoise requires an adequate description if we are to counteract its detrimental effects ondata transmissions. Previous studies contain estimates of the probability distributions forthe amplitude, width, and interarrival time of noise impulses [2], and noise spectral densityestimates [16]. Such knowledge is essential in the design of effective error control codesand data link protocols.Power line noise is composed of continuous, relatively low-level background noisepunctuated by relatively strong noise impulses. The impulse noise characteristics are ofprimary concern since this noise is the major cause of channel errors.14Noise impulses are typically of more than 10 dB above the background noise leveland in some cases can exceed 40 dB. The strength varies according to the noise sourceand its proximity to the receiver. The frequency for the dominant impulse train is 120 Hzin synchronism with the cycles of the 60 Hz power voltage. In some cases, impulses willoccur in proximity to each other, forming long error bursts [3].In addition to periodic impulse noise, high-level random noise impulses can result fromrandom load switching, such as thermostat switching, lightning strikes, and switching ofpower factor correction capacitors. The effect of sources close to the receiver will havegreater effect on the received noi structure due to the fact that noise impulses alsosuffer from attenuation.The presence of periodic impulse noise on the PLC can cause unacceptably high biterror rates that may seriously affect the system throughput since a large portion of thetransmitted packets would be subject to retransmission. Actual values of the bit errorprobability during noise impulses depend on the impulse amplitudes and widths relativeto the received signal level and data bit duration.To overcome the harmful effects of impulse noise, various methods have beendeveloped which involve the use of adaptive, on-line filtering techniques. The success ofsuch methods greatly depends on the continuous accurate estimation of the fluctuatingpower line noise. The work done using this approach, shows the obtained BER to be inthe order of 10 even for low data rates under 1 Kbps [17]. Other methods are basedon the use of FEC and are discussed in section 2.4.Fading. Power line fading is normally periodic at double the 60 Hz power voltagefrequency or its submultiples and varies with time in accordance with the electrical loadprofile. Under severe periodic fading, digital transmissions are subject to periodic bursterrors. The effect of fading is analogous to periodic impulse noise impairment, sincethe occurrence of either signal drop-out or impulse noise results in signal-to-noise ratiodegradation. For this reason, the same FEC coding techniques used in combatingimpulse noise may be used in handling periodic signal fading.Severe signal fading is rare and over 90% of all fading occurrences are less than a15few dB from the median level. Nevertheless, in the cases when deep signal fades dooccur, they cause large numbers of periodic burst errors [3].After performing a detailed analysis of all the sources of PLC errors. One concludesthat the PLC is not a “random error channel”. In most cases the PLC is not a simple “bursterror channel” either. The PLC is not a “random error channel”, due to the overwhelmingpresence of periodic error burst sources. A simple “burst error channel” has two states:a “good state” in which transmission errors occur infrequently with the probability of errorapproximately 0 (these error-free spans are called guard spaces); and a “bad state” inwhich transmission errors are highly likely. The channel is in the good state most of thetime, but occasionally shifts to the bad state, during which errors occur in clusters orbursts that never exceed a certain length [9]. The PLC does not meet these conditions;the guard spaces or good states are often corrupted with random errors, and the length ofthe error bursts are often difficult to predict. For such reasons the PLC may be describedmore accurately as a “messy” channel [3].2.4 Evaluation of Forward Error Correction Codes for HighSpeed Power Line Data CommunicationsThe selection of a specific code and an appropriate decoding algorithm for a givencommunication system requires the consideration of many factors. These include: channel characteristics and parameters, decoding performance and complexity, coding efficiency and delay, storage requirements, and decoder speed, cost and complexity. As wellas these direct considerations that are, other more general ones, including: message sizeand format, nature of data traffic, transparency of the codec during data transmissions,and, the connectivity of such devices to existing systems.Cost and complexity are our major concerns with regard to the implementation requirements. From a system design point of view, the codec’s efficiency and performancewill be the most important factors.The two different types of codes in common use today are block codes and convolutional codes. In previous work Chan and Donaldson [2, 14] provided a detailed study of16the performance of a wide range of convolutional and block codes in high speed powerline data communications. In their studies they used interleaving techniques to disperseclustered errors. For block codes, interleaving may be implemented by arranging A codewords from the original code into A rows of a rectangular array and subsequently transmitting them in column order. The parameter A is the interleaving degree. The effectof interleaving is such that adjacent bits of a codeword are actually separated in thetransmission by A—i bits. At the receiving end codewords must be deinterleaved into theoriginal order for decoding.Interleaving is also applicable to convolutional codes. Interleaving requires themultiplexing of the outputs of A separate encoders before transmission over the channel.The received bits are then demultiplexed and sent to A separate decoders. An error burstof length A will look like single errors to each of the separate decoders. In practice it isnot necessary to use A separate encoders and decoders, but to implement one pair insuch a way that their operation is equivalent to that of A pairs.Interleaving does not involve additional redundancy but does add decoding delay andstorage costs. For interleaving to be effective, an adequate interleaving degree must bechosen, which has low overhead (regarding both delay and costs), and disperses theerrors that occur during impulse noise and signal fading into intervals between theseimpairments.2.4.1 Block CodesFor evaluation purposes, Chan [3] chose two types of block codes: a set of randomerror correcting block codes was selected from the class of BCH codes with lengthsranging from 15 to 63 and with different error correcting capabilities. Secondly, for bursterror correction some very efficient burst error correcting cyclic and shortened cycliccodes were analyzed. The burst error correcting codes were selected with parameterssimilar to those of the random BCH codes, thereby allowing a comparative analysis ofcode performance.17The evaluation was performed for different types of channel impairments at differentBER with and without interleaving [2, 3]. The effects of interleaving in each case werethoroughly investigated. The principal effects of parameter variation in code selection aresummarized as follows:1. For a fixed code rate R and variable block length n:a. Interleaved short random error codes were the most effective and reliable meansof improving the PLC performance.b. Interleaving periods should not be comparable in length to the period of theimpulse noise disturbance, since errors tend to be periodic. For this reason ashort code with moderate interleaving or a longer but more powerful code with asmall degree of interleaving would be among the best choices.2. For a fixed block length n and a variable code rate R:a. The effect of interleaving increases with the error correcting capability t of thecode, which also causes a decrease in throughput R.b. For codes with inadequate error correcting capability, the use of interleaving isvirtually useless.c. For codes with nearly adequate errorcorrecting capability, interleaving noticeablyupgrades their performance.d. Interleaving may reduce the error correction performance at some multiples ofthe error period when the interleaving block contains additional periodic noiseimpulses.e. For codes with high error correcting capability, error correction performanceimproves monotonically with interleaving. Unfortunately the loss of throughputdue to the excessive overhead of the code, in most of these cases is prohibitive.2.4.2 Convolutional CodesIn contrast to block encoding where the data is processed as codewords that arebasically independent of each other, convolutional encoders process an input bit stream18continuously. . The specifics of encoding and decoding convolutional codes, as well astheir characteristics are detailed in Chapter 3. Here, we summarize some of the resultsobtained in previous studies [2], as a point of comparison.For testing purposes three different convolutional codes were selected from the wellknown classes of self-orthogonal and diffuse codes [7, 9]. These were all systematic rate1/2 convolutional codes including: the self-orthogonal (2, 1, 6) code, the self-orthogonal(2, 1, 35) code, and, the diffuse (2, 1, m) code with m=3d+1, where d is any positiveinteger greater than 1. In every case, threshold decoding was used. It is the mostattractive option for low cost applications, due to its ease of implementation.The error correction effectiveness of the previously mentioned codes against periodicimpulse noise, random noise, signal distortion, phase distortion, and other impairmentsencountered on the PLC, are summarized as follows:1. The use of a simple short constraint length convolutional code with threshold decodingand a moderate degree of interleaving can reduce the decoded BER several ordersof magnitude below uncoded transmissions, thus proving that the use of a suitable,inexpensive FEC technique makes feasible data communications over an otherwiseunreliable PLC.2. Significant improvements in performance were obtained by introducing moderateamounts of interleaving (A 7), after which the improvements became much moregradual. Large interleaving degrees are also less economical and impractical toimplement.3. Due to the constant variations in the PLC, interleaving a random error correctingcode that is able to combat both burst and random errors, was found to be a muchmore robust and reliable FEC technique, than was trying to select a particular codeto correct a fixed number of errors.4. The initial delay and overhead due to coding is negligible compared with the delay ofretransmitting packets with errors, since packets are generally over a thousand bitslong. The packet reception rate with coding increased from close to 0% to over 90%,drastically improving the throughput of any retransmission scheme.195. Retransmission of those packets with uncorrected errors, under an appropriate ARQstrategy, should be used to assure highly reliable data link communications.As stated previously the selection of a suitable FEC code for the PLC is a complexissue involving many factors. A remarkably simple, reliable and inexpensive scheme tocombat the impairments of the PLC, is to use a short random error correcting code witha moderate degree of interleaving. Due to the simplicity of the structure of the decoderand its inherent suitability its for interleaving, convolutional coding and threshold decodingwas chosen as the most appropriate. The self-orthogonal (2, 1, 6) convolutional codewith variable degrees of interleaving (A=i, 3, 5, 7) was selected for implementation.20Chapter 3Convolutional Coding for PowerLine Data CommunicationsIn section 2.4 a summary of previous work done by Chan and Donaldson [2, 3] waspresented. In their studies the performance of two types of codes, block and convolutionalwas practically evaluated within a PLC environment. The use of a short random errorcorrecting code with a moderate degree of interleaving was shown to be the mostappropriate solution. The (2, 1, 6) convolutional code with variable degrees of interleavingwas selected as a code complying with these requirements. Threshold decoding waschosen due to the simplicity of the decoding algorithm and its appropriateness for usewith code interleaving.3.1 Encoding of Convolutional CodesThe information sequences of block codes are grouped into k—bit blocks which areindependently encoded into n—bit code words. In this manner the coded sequencebecomes a sequence of fixed-length independent code words. Convolutional codes onthe other hand greatly differ from this approach, since the convolutional encoder containsmemory and then encoder outputs depend not only on the k inputs but also on m previousinput blocks. Therefore, convolutional codes have a more complex structure than blockcodes, which makes them harder to analyze but sometimes easier to decode.A convolutional encoder code accepts k-bit blocks of the information sequence u andproduces an encoded sequence v of n-symbol blocks. Each encoded block depends notonly on the corresponding k-bit message block at that time unit, but also on m previousmessage blocks; and hence the encoder has a memory order of m. The set of encodedsequences produced by a k-input, n-output encoder of memory m is called an (n, k. m)convolutional code [9].The ratio R=k/n is called the code rate; redundant bits for combating channel impairments can be added to the information sequence when in which case Rcrl. Typically,2141)U— _42)Figure 5 Block diagram of a (2, 1, 6) convolutional encoder.kand n are small integers and more redundancy is added by increasing the memory orderm of the code while keeping the other parameters constant. The memory order of a codedetermines its constraint length which is generally accepted as A= (m÷1)xn [6]. Thus,the constraint length of a convolutional code will increase when redundancy is increasedby augmenting the memory order rn of the code.Next, we describe the encoding process for a R=112 systematic convolutional codewill be described. A system block diagram of such an encoder is shown in figure 5.The information sequence u=(uo,u1,u2...) enters the encoder one bit at a time. Sincethe encoder is a linear system, the two encoder output sequencesv(1)=(vo(,(2,...)andv(2)=(vo(,vi(,(...) can be obtained as the convolution of the input sequenceu with the two encoder “impulse responses”. Since the encoder has an rn-time unitmemory, the impulse responses can last at most rn÷1 time units, and are writteng(l)=(g(l),g(l),...,g(l)) andg(2)=(g(,g,...,). The impulse responses g(fl andg(2) are called generator sequences of the code.The generator sequences of a R=112 systematic convolutional code, are describedas: g(=( 1 0 0 . .. ), g(2)=(g0(g1(2)g2() . .. ) and generator matrix G as follows:221 2) o g(2) o g(2) . o1 2) 0 g2) o g1 o g)(2) (2) (2) (2)1 g0 . . 0 gm—2 0 g_1 ° g1 (1)For an information sequence u, the encoding equations are given by:(2)v(2)u * g(2) (3)where * denotes convolution. The transmitted code word is v=uG. If v is transmitted, thebinary received sequence r can be written asr = (r1) r’ r2), r’...) = v+e, (4)where the binary sequence e is called the channel error sequence. The receivedsequence r can be divided into a received information sequencer(1) =(r1),r1),r1),...)=v(1)+e(1)= u+e(1), (5)and a received parity sequencer(2) (r2), r2),...)= v(2)+e(2)= u * g(2)+e(2), (6)where e1 is the information error sequence, and e2 is the parity error sequence. Thereceived information sequence (5), and the received parity sequence (6) are used by thedecoder to estimate the values of the information bits.32 Decoding of Convolutional CodesThe three different methods that are widely used for decoding convolutional codes:Viterbi decoding [5], sequential decoding [18], and threshold decoding [6]. These decoding methods have different characteristics, and the selection of any particular scheme23depends to a great extent on the particular application. Important parameters used forcomparisons include: probability of bit errors, implementation complexity, and decodingspeed.Viterbi decoding is an optimum decoding algorithm, (i.e. it achieves the lowestprobability of bit errors). However, the complexity of the decoder grows exponentiallywith code constraint length and the number of encoder states. For this reason Viterbidecoding is generally used for short constraint codes. The complexity of sequentialdecoding is essentially independent of constraint length, which allows it to decode longconstraint length codes. The performance of sequential decoding is slightly suboptimum(regarding the probability of decoded bit errors), compared to Viterbi decoding, becausethe number of computations needed to decode a frame of data is random. Although mostframes are decoded very quickly, in some cases long searches may result, and causeoccasional erasures.Threshold decoding (or majority-logic decoding) is a practical decoding techniqueoriginally proposed by Massey [6] which can achieve moderate coding gains with relatively simple implementations. Threshold decoding has received much attention dueto its simplicity and its suitability to internal interleaving. Majority-logic decoding rules,definitions and theorems are given in detail in [6, 9].The performance of a threshold decoder is inferior to Viterbi or sequential decoderregarding the bit error probability of the decoded bit stream. Viterbi decoders delaydecision making until the entire received sequence is processed, basing its decisions onthe total or free distance between sequences. In contrast, threshold decoders require adelay of only one constraint length. Due to the simplicity of the algebraic approach usedand that decisions are based on the minimum distance over just one constraint length,majority-logic decoders are capable of higher speeds than that of Viterbi1 or sequentialdecoders. For example Viterbi decoders perform 2I computations per decoded bit, with adecoding delay, d, of L÷m cycles (where L is the length of the entire frame, and m is the1 Presently a wide range of high-speed Viterbi decoders have been implemented taking advantage of parallel architectures, but this greatly increases the cost of the decoder.24memory order of the decoder). A majority-logic decoder only requires one computationper decoded bit, and the decoding delay, d, is of m data cycles.Threshold decoders are inherently simpler to implement since the decoder onlycontains a replica of the encoder, several modulo-2 adders, a syndrome register, and amajority—logic gate. These modest requirements make threshold decoders very attractivefor low cost applications such as power line LAN5, where a reasonable amount of codinggain is desired at the minimum cost.As stated previously interleaving of the code symbols effectively randomizes theerrors as they appear at the decoder. Interleaving can be implemented by substitutingeach single shift register cell by a A stage cell in its place causing the code symbols tobe spaced A symbols apart. Deinterleaving is accomplished by the A—stage cells in thedecoder registers. If channel bursts are less than A symbols long, the performance, interms of the bit error probability, of such a encoder-decoder will be identical to that ofone without interleaving [19].The syndrome sequence S is defined ass rHT, (7)where H is the parity check matrix given by:g2)(2) (2)g1 g0g2) o g(2)1 0 42) 111= 2) (2) (2) (2) 1 (8)gm—i gm—2 V . . g0(2) (2) (2) (2)gn 0 gm—i 0 . . g 0 g0 1(2) (2) (2) (2)g 0 g2 0 g 0 g 1The condition vHT=O will be true if and only if v is a code word. Since r=v+e, we25can rewrite (7) ass = (v+e)HT vHT + eHT. (9)Since VHT=O, the syndrome depends only on the channel error sequence and not on thecode word transmitted, i.e.,s= eHT. (10)For decoding purposes, knowing s is equivalent to knowing r. Hence, the decoder can bedesigned to operate on s rather than on r. Such a decoder is called a syndrome decoder[9]. After substituting (8) in (7), the syndrome sequence at the receiver is formed as:s= r’ *g(2) +r(2). (11)Substituting the appropriate received sequences r1 and r2 for their correspondingexpressions we obtain:s = [u+e(1) ] *g() + u*g(2) +e(2) = e’ *g(2) +e2. (12)Any syndrome bit, or any sum of syndrome bits, represents a sum of channel errors andis called a parity-check sum. If the received sequence is a code word, all syndrome bits,thus all check sums, must be zero. If the received sequence is not a code word, somecheck sums will not be zero. The next section describes in detail how this property isused in majority-logic decoding.3.3 Self-Orthogonal (2, 1, 6) CodeThe self-orthogonal (2, 1, 6) systematic R=112 convolutional code is characterizedby the generator sequences:g(’)(D)= landg(2)(D)= 1+D+D4+6. (13)A block diagram of a (2, 1, 6) convolutional encoder was given in figure 5. The constraintlength of this codes is expressed as,nA=(m+1)xn=(6+l)x2=14. (14)26From (10) we can obtain an expression for the truncated syndrome sequence,[]6 = [e]6HT]where [s]6=(so, s1, . . . , s6). Transposing both sides of (15),[sT]6= [H]6 [eT]6 or(15)(16)Because the error bit e01 is the only bit that appears in every check sum, we may saythat (19) is a set of check sums orthogonal on e01, and that the code is self-orthogonal1011010000000HT form[eT]6.11101100101[5T]6= 0 0 0 0 1 (17)10000 1100100 101110001 001011Since the even numbered columns of an identity matrix, (17) can be rewrittenin the following form,111011= 0 0 1 1 (18)100110100111010011The matrix which multiplies the information error sequence is called the parity triangle ofthe code. Its first column is g(2) and the kth column is a shifted down version of columnk-i. From (18) the orthogonal check sum equations are obtained and given by:I Ti[S J6SOS2S3S485Ls6?i)1)e1)e’e’’1)_e6 -+(2).e0(2)2)2)e2)e2)e!2).(1) (2)s0=e +e0(1) (1)si= e0 +e1(1)84=6 e’ +e1)+e1) +e2)(19)27[6, 9, 7]. Since there are a total of four (symbolized as orthogonal check sums, thiscode will correctly estimate e10 whenever tML [J/2J = 2 or less of these 11 noise bitsare channel errors [9].The total number of distinct noise bits checked by the set of check sums is called theeffective constraint length of the code and will be denoted !7; for this code E=1 1. Wemust note that nE< A, since not all of the bits of the parity error sequence in thegiven constraint length A, form part of the set of J check sums.However, the set of check sums given by (19), only estimates e01 from the firstconstraint length of syndrome bits s0,s1,..., Sm. In general, we must estimate the valuesof all the other information error bits as well. The procedure to implement this is relativelysimple; the estimated e01 is subtracted from each syndrome equation it affects to form anew modified syndrome setS0’,S1,..., Sm’. Together with the new syndrome bit Sm÷i thismodified set is used to estimate e1. If we assume that e01 was correctly estimated, anew set of orthogonal e1 check sums may be formed which will replicate the previousones. Thus, the same decoding rule may also be used. The 1t1? iteration yields an estimateof (1)• Since each estimate must be fed back to modify the syndrome register beforethe next estimate is made, resulting in a feedback decoder. Each estimate depends onlyon one constraint length of error bits because the effect of previously estimated error bitshas been removed by the feedback.Assuming that previous estimates of errors are correct the syndrome equations from(19) can be expressed in a more general manner(1) (2)= +e1(1) (1)+1 = j +e1 (20)— (1) (1) (1) (2)i+4—+ei÷3+4 +ej+4(1) (1) (1) (1) (2)+€j+2 +ej+56eThe same error correcting capabilities will apply for this set of syndrome equations; thatis, e(1) will be correctly estimated if there are tML=2 or fewer errors among the n5=llerror bits checked. A block diagram of such a decoder is shown in figure 6.28r?8 UI’.r6+61Si+Si+SThreshold Gatee,Figure 6 Block diagram of a (2, 1, 6) threshold decoder.In general, the operation of a threshold decoder for a (2, 1, 6) systematic code canbe divided into the following steps:1. The syndrome bits for the first constraint length are calculated.2. From these previously calculated syndrome bits a set of four check sums onis formed.3. The results from the four check sums are fed into a majority-logic gate. This gateproduces a 1 at its output if and only if more than half of its inputs are 1. Thepresence of a 1 at its output indicates the presence of an error. Thus, the receivedinformation sequence must be corrected (by adding the output of the majority gateto the corresponding bit of the received sequence). This output is also fed back andsubtracted from each syndrome it affects.4. The estimated information bit t20’=r1+ê is shifted out of the decoder. Thesyndrome registers are shifted once to the right. The next 2 bits are shifted intothe decoder, and finally, the next syndrome bit is calculated and shifted into theleftmost stage of the syndrome register.295. The syndrome register now contains the modified syndrome bits, together with thenew syndrome bit. Steps 2, 3 and 4 are repeated to estimate the next informationbit. All the following information error bits are estimated in the same manner.It should be noted once again that each independent bit that is estimated dependsonly on one constraint length of the of error bits, since the effect of the previouslyestimated bits are removed by the feedback to the syndrome register. In the nextsection we will discuss the extent to which this feedback affects the performance anderror correcting capabilities of the decoding scheme itself.34 Properties and Performance of Threshold DecodingBecause estimates of the error bits are subtracted from the syndrome register, errorswill propagate when their estimate is incorrect, hence generating the same effect ashaving additional channel errors. This effect is known as the error propagation effect[20], and will be present in any decoder which feeds back the estimated values.There are a number of approaches that can be taken to limit the error propagationeffect, such as resynchronizing the decoder with a “zero sequence” that “flushes” allthe possible post-decoding errors, alternatively a code with automatic resynchronizationproperties may be used, such that if the channel is error free for more than a constraintlength, the effects of previous errors will be removed from the decoding circuitry. Self-orthogonal codes possess this automatic resynchronization properties with respect toerror propagation. Further discussion and proof of this property may be found in [20].The elimination of the use of feedback in the decoder completely avoids the problemof error propagation, as Robinson suggested [21]. However this approach, known asdefinite decoding, in most cases, will not provide better performance than feedbackdecoding, since the effects of previously estimated channel error bits are not removedfrom the syndrome register and will continue to affect following bit estimates, thusincreasing the probability of decoding errors.Definite decoding is of great interest because certain single “stuck at” faults in thecircuit can transform (or partially transform) the feedback decoder into a definite one.30(1) (2)r1÷6* g e1Figure 7 Syndrome register (feedback links marked a-d).The absence of a link (which would in effect be equivalent to a “stuck at zero” fault) inthe feedback of the syndrome register would yield the same decoding estimate as wouldthe feedback decoder with all the links. In figure 7 the positions of such faultsthat couldtransform a feedback decoder to a definite decoder are marked a-d.During the analysis that follows, we will only consider the effects of stuck at zerofaults, since the effect of any stuck at one fault will clearly generate incorrect estimatesthat can be easily detected during the test procedure. In what follows stuck at zero faultswill be referred to simply as faults.Case A: If a fault were to occur at point a, there would be no feedback at all to thesyndrome registers, a definite decoder would result, for which the checksums of (20)would becomeSj = + e’? + +e1’ + ej(2)— (1) (1) (1) (1)..Le(2)e_5 +e_3 e i+1—(1) (1) (1) () e(2)81+4 e1_2 + €j +e+3e4 i+4—(1) (1) (1) (1) (2)€1 +ef2 +e+56d(2)r÷6•131The checksums in (21) show that definite decoding still forms a set of four orthogonalchecksums on However, the effective constraint length of the code E is no longer11, as in the previous feedback decoder, but has increased to 17. The decoder in thiscase will only correctly estimate e1 if 2 or fewer of these 17 error bits are 1. Thisclearly shows the manner in which the error correcting capability of the code decreases.Whenever there are more channel error bits present in the decoding of any given bit, thepossibilities of incorrectly estimating the bits value increases.In cases such as this one where the resulting effective constraint length is larger thanthe constraint length of the code (flE>flA), it is relatively simple to detect the presence ofa fault in the decoder. The error correcting capability of the code is weakened, causingthe previous maximum error correcting capability of the code to be no longer obtainable.Such is the case if there is a fault at a.Case B: If a fault were to occur at point b then the checksums from (20) wouldbecome= + e1) +e2(22)(1) (1) (1) (2)+ej ++3+€j+4 +ei+4— (1) (1) (1) (1) (2)81+6— +e2 +e+5i6In this case only one more term is added to the equation set, increasing the effectiveconstraint length by one to E=12 Similar results can be obtained for such cases whenfaults occur at locations c or d. The effective constraint length in each case will be E=13and E=14, respectively. Decoders with these faults are still able to maintain the erràrcorrecting capability of the code, thus correcting any two errors in any 14 consecutivechannel bits.However, as can be seen from the expression given by Lin in [9], the difference inthe effective constraint lengths in these cases will affect the decoded bit error probability,Pb(E). For channels with bit error probabilities for which n9p<<1 (i.e. p < 102) the32decoded bit error probability is expressed as follows:Pb(E)-i( (23)k tML+lFrom (23) it is clear that an increase in the effective constraint length E will in effectalso increase the bit error probability. A comparison of the actual effect of such faultson Pb(E)For a feedback majority-logic decoder,Pb(E) (1)3= 165p3. (24)For a decoder with fault b,Pb(E) (1)p3= 220p3. (25)For a decoder with fault c,Pb(E) ()P3=286P3. (26)For a decoder with fault d,Pb(E) ()p3= 364p. (27)• From the syndrome equations in (20), it was shown that the effective constraint lengthof the code using a feedback decoder is E=1 1, that means that there are three channelerror bits which are not used to compute the values of the syndromes in a given moment.This fact allows the decoder to achieve correct estimates in the presence of certainpatterns of triple errors during the transmission of 14 consecutive channel bits. Forexample the estimated information bit, U, will be correctly estimated if the following tripleerror patterns occur: e1)+ej1)+e2 , e1)+e1)+e2) or e1)+e1)+e2)This knowledge will be used in the BIST scheme, since from the sets of syndromeequations for the cases with faults at points b, c or d, it is clear that the effective constraintlength, E, increases with any of these faults. Thus it will always be possible to find a33certain set of triple channel errors that can be correctly estimated by the decoder with nofaults, but will generate an incorrect estimate if used with a decoder with faults b, c or d.The first pattern shown previously will cause incorrect decoding for a codec with faults b ord, while the second error set will generate an incorrect estimate for decoders with faults bor c. In the next chapter a detailed description of the realized BIST procedure is provided.34Chapter 4VLSI Design and Implementation41 General DescriptionIn this chapter the issues related with the design and implementation of a VLSIcodec are discussed, such as: schematic capture, layout generation, schematic andlayout simulations, as well as post-fabrication tests of the chip. A detailed description ofthe functional blocks and signals that form part of the chip is also presented.Before the process of designing a chip starts, several technological factors andpossible trade-offs between them must be taken into consideration, to ensure that theIC meets its given set of specifications while expending minimal resources within a givenconstraint of time [22]. The most relevant of these factors are: the choice of the minimumfeature size of the fabrication process, and the selection of the design scheme.In this case the selection of the minimum feature size of the fabrication process wasnot difficult, since the choice was limited to those processes offered by Northern TelecomElectronics (NTE) through Canadian Microelectronics Corporation (CMC) for universityresearch. Both the CMOS3DLM 3 m process and the CMOS4S 1 .2 m processes wereadequate for the fabrication of the codecs. The CMOS4S 1 .2 tm process was selectedtaking into account the future possibility of integrating both the modem and codec modulesonto one chip, and due to its favorable fabrication schedules.Three possible alternatives of design schemes were analyzed: full—custom design,semi—custom design, and the use of a field programmable gate array (FPGA). The usea full-custom design approach includes the design of each of the basic cells (NAND,NOR, flip-flops and others). The process of designing, simulating and extensively testingeach of the independent cells is time consuming and costly. Since the codecs’ designsare composed entirely by commonly used standard cells, redesigning and optimizing theexisting library cells would not bring a substantial decrease in the silicon area of the chips,making the use of a semi-custom design approach the most suited alternative.35The last of the design schemes considered was the use of an FPGA based designof the codecs. Unfortunately, the use of FPGAs for low-cost, large volume applications,such as the PLM5 is not yet feasible due to their cost ($300—$400 for a suitable XiIinkTMFPGA). FPGAs at this stage could be used for prototypes, but cannot be seen as acommercially viable solution.All the schematics and layout generations were done using EDGETM (CADENCE)CAD tools [23, 24], in the VLSI laboratory of the University of British Colombia. Thechip design was based on the use of standard cells from the Canadian MicroelectronicsCorporation’s (CMC) CMOS4S Library [25], which contains all the basic low level cellsnecessary to realize a hierarchical bottom-up design. Simulations of the designs wererun with SILOS Il® Logic and Fault Simulator [26]. In this manner, verification of thecorrectness of the circuit was performed before the generation of the layout.The codecs were fabricated using the Northern Telecom Electronics 1 .2gm doublepolysilicon, double-metal CMOS process, and packaged in a 68—pin ceramic pin gridarray (PGA). Of the actual 68 pins only a small portion is used in each case, but the68—pin PGA is the only packaging used for prototypes at Northern Telecom Electronics(NTE). Three chips were designed and manufactured, each time increasing in complexityand available features. Each of these chips were:• This chip is a (2, 1, 6) convolutional encoder & threshold decoder with fixed interleaving degree (A=7). This chip has 10 input/output pins, 1 power and 1 ground pin,and a total area of 6.0 mm2 (2760 m x 2190 tm). The core area is of 1.73 mm2,and has approximately 1,260 gates.• This chip is (2, 1, 6) convolutional encoder & threshold decoder with variable interleaving degree (A=1, 3, 5, 7).This chip has 14 input/output pins, 1 power and 1ground pin, and a total area of 6.98 mm2 (2850 m x 2450 gm). The core area isof 2.11 mm2, and has approximately 1,480 gates.• This chip is (2, 1, 6) convolutional encoder & threshold decoder with variable interleaving degree (A=1, 3, 5, 7) and built-in self-test. This chip has 15 input/output pins,361 power and 1 ground pin, and a total area of 7.57 mm2 (2910 m x 2600 am). Thecore area is of 2.32 mm2, and has approximately 1,620 gates.The VLSI codec designed, fabricated and tested as part of this thesis work consist oftwo major blocks as the name suggests: the encoder and the decoder. Both blocks weredesigned to be fabricated on one chip, thus reducing the total size and cost of the finalmodem and this way supporting half and full duplex transmissions using a single chip.Integration of the encoder and decoder onto one chip, this provided an ideal situation forthe use of BIST [27]. A detailed description of the BIST scheme used in this case, andits implementation, which provides 100% fault coverage for single stuck-at faults [28], isgiven in section 4.5.From the initial stages of the design, the necessary steps were taken to provide asimple approach towards the use of variable degrees of interleaving (A= 1, 3, 5, 7) inthe encoder and decoder blocks . The use of an interleaved code make it necessaryto introduce a few additional support blocks which provide proper synchronization andstructure to the encoded bits being multiplexed for transmission over the channel.In what follows, the notation “—“ denotes the presence of a negative edged or activelow signaL The pin number for each of the signals varies in each case for the threeversions of the chip. In appendix A the schematic and layout representations of eachversion of the codec are shown. In appendix B the bonding diagrams of the differentchips are given.4.2 EncoderThe structure of a convolutional encoder is shown in the previous in figure 5 of theprevious chapter. In this case we set out to design a self-orthogonal (2, 1, 6) systematicR=112 convolutional encoder characterized by the generator sequences in (13).In this section a description of the encoder signals and their functions is given. Theschematic diagram of the encoder is shown in figure 8.37Figure 8 Schematic diagram of a (2, 1, 6) convolutional encoder.38—U UChip pin descriptions are as follows:Ui (Input) : Information sequence input. This is a negative edge triggered synchronous serial input. An extra flip-flop (150) is placed in front of the actual encoderto avoid the propagation of undesirable asynchronous changes on the input that couldalter the values of the Vi and V2 outputs in at any time other than after the negativeedge of the clock cycle.Vi, V2 (Output): Output sequences, which are the encoded outputs of the informationsequence Ui, after passing through each of its respective encoding equations, characterized by the generator sequences: g(’)(D)= 1 and g(2)(D)= 1 + D+D4+D6.Both of these signals are negative edge triggered.Ci, C2 (Input) : These control signals select the interleaving degree which is to beused (A= 1, 3, 5, 7).—CLK (Input): Clock Signal. Negative edged clock, with a maximum frequency, fmax,of 50 MHz.SET, —RESET (Input) : Set (active high) and Reset (active low) signals for initializingthe encoder. The hold time, thold, for these signals is 1 .5 ns in both cases.4.3 DecoderFrom chapter 3, the received information sequence, r(1)and the parity sequence r2at the decoders were expressed by (5) and (6). These signals are received at the Ri,R2 inputs of the decoder, from which the syndrome sequence at the receiver is formedas in (ii) and (12).A schematic diagram of the (2, 1, 6) majority logic decoder with variable degrees ofinterleaving is shown in figure 9.The decoder is split in two separate functional blocks, the syndrome generator andthe syndrome register. The syndrome generator is formed by a replica of the encoder.It takes the convolution of r1> and g(2) and adds it (mod 2) to r2>, thus forming thesyndromes such as in (ii). The output of gate 128 in figure 9 will be the resultingsyndrome bit s, which will be zero unless an error has occurred during the transmission.39H ‘nq_V=____!EEIFigure 9 Schematic diagram of a (2, 1, 6) majority—logic decoder.40The output from the syndrome generator goes to the input of the syndrome register,(input B of gate 129 in figure 9), to be used in the estimation of e1. The syndromeregister is designed to realize the set of orthogonal check sums described in (20). Thesyndrome bits , s1, s÷4, s÷6 are used to estimate the error bit using the majority-logic gate (138). This gate produces an estimate of “1”, if more than two of the syndromebits are “1 ‘s”. The output from the majority-logic gate is fed back to the syndrome registerand subtracted from each syndromebit that it affects, in order to generate the correctnext set of syndrome equations.The estimate of e(1) is used as well to calculate the estimate of information bit 0. Thisis accomplished by adding (mod2), the received information bit ,(I) with the estimatederror bit. The result is obtained at the output of gate 140. An additional flip-flop (144) wasadded to clean the output signal of small spikes, that are created due to differences inthe response times of the various components.Chip pin description are as follows:Ri (Input) : Received Information Sequence. This is a negative edge triggeredsynchronous serial input.R2 (Input) : Received Parity Sequence. This is a negative edge triggered synchronous serial input.Ui (Output) : Estimated Information Bit. This is a negative edge triggered synchronous serial output.Ci, C2 (Input) : These control signals select the interleaving degree which is to beused (A= 1, 3, 5, 7).—CLK (Input): Clock Signal. Negative edged clock, with a maximum frequency, tmax,of 50 MHz.SET, —RESET (Input) : Set (active high) and Reset (active low) signals for initializingthe encoder. The hold time, thold, for these signals is 1 .5 ns in both cases.4.4 Support BlocksThe use of a R=i12 code generates 2 symbols per clock cycle. These symbols are41multiplexed onto one transmission line, demultiplexing is performed at the receiver. Forthis reason two additional blocks were implemented, a multiplexer and a demultiplexer.The multiplexor (MUXL) takes the two outputs from the encoder block and alternatelyoutputs them onto the channel. The information sequence Vi is output during the lowlevel of the clock, and parity sequence V2 is output during the high level of the clock.The demultiplexor (DMUXL) accepts two symbols from the channel and places themon the appropriate inputs of the decoder, Ri and R2. Two important issues must be notedregarding the demultiplexor. First, the values at the outputs must be generated such thatboth outputs are valid at the negative edge of the clock signal. For this reason an extradelay must is inserted in the DMUX cell which assures data synchronization. Second,great care must be taken to ensure that the transmitter clock and the receiver clock areco-phased, making sure that one is not the inversion of the other. With inversion, thedemultiplexed values of the received information sequence and that of the received paritysequence would be the wrong inputs of the decoder, thus resulting in incorrect decodingof the whole data stream.The clock signal must be distributed to over 200 cells on the chip. The drivingcapacity of the input pads cannot assure this distribution without degradation of the signal.Consequently, a tree was implemented for clock distribution in order to avoid clock skewsat different places of the codec. Buffers were used to drive the clock signal from its “root”to its “branches” in an organized and balanced manner. Each distribution path has thesame delay between the clock signal at the input pad and any of its destinations withinthe chip core.A block diagram of the process involved for accomplishing the interleaving is shownin figure 10. This procedure is described in further detail in the previous chapter as wellas in [3] and [19]. The realization of variable interleaving is accomplished by means oftwo separate blocks, each of which is a shift register of variable length. The first block,7Cell, has programmable lengths of 1, 3, 5 and 7 units. The second block, 3Cell, can varyin length from 0 to 3 units. The structure of these cells appear in figures 11 and 12.42pcebystages with cha )c-stage a >s—stageshift shiftregister register(X—1)/2 stagesFigure 10 Variable interleaving implementation4.5 Built—In Self—TestThe complexity of testing a VLSI circuit can be converted into costs associatedwith the testing process which include: the cost of test pattern generation, the cost ofgenerating fault location information, the cost of the automatic test equipment (ATE), andthe cost of the testing process itself. Because these costs can be high, it is importantthat they be kept within reasonable bounds. Design for testability (DFT) is one of theways this may be accomplished, by means of using design procedures that ensure thata device is testable [27].Many design for testability techniques , such as: level—sensitive scan design (LSSD),boundary—scan, and other scan path-based techniques, are widely used in many electronic systems [29]. However, the increasing complexity of VLSI circuits leads to harderaccessibility of internal logic nodes, and to greater complexity in the process of generating test patterns.Built—In Self—Test (BIST) emerged in the last decade as a technique that deals notonly with the limited accessibility problem, but the costly test generation and testerproblems as well. BIST can be defined as the capability of a circuit (chip, board orsystem) to test itself without requiring any external test equipment [29]. 81ST has becomeincreasingly widespread because of its great potential in VLSI testing, due to the following:43-I, CD -A Cl)C-) CD a 0) 0•0) 0) 3 0 C-) CDCK0 C)ClC2Inter.001013105117C2 Cl S_Rb• The need for a cost effective testing approach that can be applicable to all categoriesof testing, from production to field maintenance.• The increasing time, cost, and complexity of test pattern generation, due to thegrowing density of VLSI circuits.• The cost of ATE has steadily increased, as well as the fact that the performanceand speed of the circuits under test has become comparable to that of the testersthemselves, making the use of very costly ATE much less productive.• Substantial increases in the time and cost involved in the testing process itself, dueto the size and complexity of the circuits that need to be tested.However, incorporating BIST to a design is accompanied by some additional costs,which are reflected through: increased silicon area, extra pins, decreased reliability dueC2ClS_CI<_RbDFigure 12 Schematic diagram of 3Cell block.45to silicon area overhead, performance penalties due to additional circuitry, and additionaldesign time and cost.Since the BIST procedure designed for this case is based on the tact that both theencoder and decoder are situated on the same chip, a minimal amount of additionalcircuitry is needed (less than 10% area overhead and only 1 extra pin) to achieve 100%fault coverage of single stuck—at faults. In this scheme there is no performance penalty,since no components have been introduced in the critical paths of the codecs.The primary logic components that form part of the BIST scheme are the following:• Circuit Under Test (CUT): This block is formed by both the encoder and decoder,which in test mode are interconnected in a loop-back fashion. The output of theencoder is fed back into the input of the decoder directly. The input sequence at Ui(Encoder Input) should be exactly the same as the output sequence at Ui (DecoderOutput) after decoding.• BIST Control: This block generates all the appropriate signals that control the self-testprocedure, whenever the BIST signal is “high”.• Automated Test Pattern Generator (ATPG): The generation of input test patterns isaccomplished with a linear feedback shift register (LFSR) that serially outputs finitepseudorandom sequences (16 bits long) repeatedly. Two such blocks are used,since the output of the CUT must be compared, after the encoding/decoding processis complete, with a sequence identical to the input one.• Comparator (COMP): The decoded output sequence (ul) is compared with the“delayed” test pattern. In the case of a mismatch the output will be set to “high”,indicating the presence of a circuit fault. In the initialization of the test, this outputwill be toggled to ensure that the block itself does not contain a “stuck at” fault.• Multiplexors (MUX): A series of multiplexors, blocks Ii, 110, and 124, are used tomultiplex the normal inputs/outputs of the CUT with their BIST inputs/outputs.A schematic diagram of the BIST circuits is given in figure 13. A description of thetest procedure and control signals used by the BIST follows.46-IlCo CD C)-CI)CD C,) U) C, Zr CD 3 U) C) Cl)4.5.1 Test ProcedureThe test procedure developed for this BIST scheme was designed to provide 100%fault coverage (for single stuck at faults). The scheme is based upon the fact that both theencoder and decoder circuits are on the same chip, and that in test mode the output of thedecoder will be directly attached to the input of the decoder. These two blocks togetherwill form the circuit under test (CUT). In this manner we can obtain a decoded outputsequence that should be identical to the input sequence, after a certain decoding delay,d, where d=Am÷(A—1)/2÷c. As before A is the interleaving degree, m is the memoryorder of the encoder; and c is a constant related to the delays that are due to the need tomultiplex encoded bits over the channel (in this case c=3). The sequential characteristicsof the codec design guarantee that all the gates and interconnections must be fault-freeto obtain the correct result at the output.To test the syndrome register and its components it was necessary to introducechannel errors in the connection between the encoder and decoder. This will force thecodec to work at the maximum error-correcting capability of the code. The self-test isdivided into two separate cycles, ti, where A=1, and t2, where A=7. This test will ensurethat all the interconnections are free of faults. In the ti cycle specific. error patterns wereintroduced that will also check for faults in the feedback of the syndrome register, aswas discussed previously in section 3.4. During the t2 cycle, the burst error correctingcapabilities of the codec are tested. In this case 14 channel-bit burst errors are introduced,which test the circuits at their highest capabilities. Figure 14 shows simulation results thatillustrate the BIST test procedure. The timing of each of the signals involved in the BISTroutine can be observed in detail.The BIST routine as shown in figure 14, is formed by these steps:1. Check the bist input. If bist=0, continue in normal operation, if bist=1 start BISTprocedure.2. The signals —rstl and —bstl which were resetting the CUT and the ATPG blocks, gohigh, nabIing the start of the test. The control block outputs a toggle pulse, which48LogicSimulation(xintime_units]El—/16.tclkV-/$istCDC—/16._bstlC—/l6toQgIeC—A6.t112--28tpI—/16.eliLu_____________0—/130.ul0—/129.tcU—/121.outlØøu200u300u400u500u600u7øØu8ØØumakes the comp output go high for 1 test clock cycle, tclk, in this way testing thecomparator block itself.3. The signal tlt2 (16.tlt2 in figure 14) of the BIST control block goes low, indicatingthat the first phase of the test is in progress, with A set tol.The input (Ui) of theCUT block is switched from external data to the internal test pattern generated by theATPG block ( in figure 14). At the same time that the ATPG block outputs thetest pattern, the control block generates the corresponding error pattern, el (16.el infigure 14), to force the decoder to work at its maximum error-correcting capability.4. After a delay of d=9 tclk cycles, the valid signal becomes active, which enables theoutput ATPG block ( in figure 14) to start generating the sequence which willbe compared with the decoded output of the CUT (l30.ul in figure 14).5. The COMP block continues comparing both outputs for 64 tclk cycles. If an erroris. detected its output, (121 .out in figure 15) is set high, thus indicating the presenceof a fault.6. The second phase of the test starts when tlt2=1 , setting A to 7.The —rstl and —bstlsignal reinitialize the CUT and ATPGs. During the period in which the ATPG (l28.tpin figure 14) is outputting test patterns, the channel error signal, el (16.el in figure14), outputs error bursts of maximum correctable length.-7. The valid signal becomes active after a delay d=48 tclk cycles, after which theoutput ATPG block ( in figure 14) starts generating the sequence which will becompared with the decoded output of the CUT (ul). The COMP block will analyzeboth outputs. If an error is detected its output is set high, thus indicating the presenceof a fault. The self-test will continue in this state while the bist pin is kept high. Thisprovides the possibility of using this feature for when prolonged periods of testing aredesired, such as burn-in tests.4.6 Design VerificationDuring the process of designing and fabricating a chip various steps must be taken toensure the correct functionality of its components and eventually of the whole circuit. The50LogicSimulation[xintime_units)D—/16.tclk—/bist0—/16._bstlCi)CD =0—,16.toleCl) Cl)0—/16.tit2H.—/128.tø/130.ul—0—/129tpCD—/121.outCD C) a0—/outløøu200u300u400u500u600u700u800ufollowing tests were performed in order to confirm and validate the actual implementationof each of the design stages:1. Schematic Capture Simulations are used as a tool to verify the correctness of theinitial schematic designs developed with the EDGE design entry tools [23]. Thesimulation program used was SILOS II ® Logic and Fault Simulator [26], obtainingas a result of each simulation the corresponding waveforms.Previous to each simulation it is necessary to create an STL (Simulation and TestLanguage) program, which defines the parameters to be used as well as describingthe test vectors. An example of such a file is given in figure 16.As stated previously, the codec was designed using a bottom-up approach, withsimulations at each level:a. Independent block simulations evaluate the correctness and functionality of eachof the logic blocks.b. Simulations of the completed design evaluate the correctness of the whole designand determine possible timing and/or functional discrepancies between blocks.2. Physical Design Verification is employed as a means to countercheck the physicaland functional parameters of the layout generated from the schematics. This processis done by two separate and distinct programs:a. Design Rule Checker (DRC), checks that the technology rules (CMOS4S, Northern Telecom’s 1.2 tm process) have not been violated in the generation of thecompleted layout.b. Place and Route Verification. To verify the placement and the routing of the layoutit is necessary to generate a netlist of the layout and then compare it with theprevious netlist that was generated from the schematics. This process ensuresthat the interconnections of the layout are the same as the ones described inthe schematics.3. Post-Fabrication Functional and Parametric Tests. Prior to fabrication the designedchip passes a series of tests, all of which are based on simulation models of the cells52;/* STL Input File for BIST Convolutional CODEC (2,l,6)x7 */settarget silosstlinitdefpin vdd pwrdefpin gnd gnddefpin data in cmosdefpin bist in cmosdefpin _reset in cmosdefpin clk cik cmosdefpin out outdeflevel cmos vil=0 vih=5 vol=l voh=4deftiming ips 200ns 2000nsdefclock “ 11111” clkdefpulse _reset Ons:0 2500ns:ldefpulse bist Ons:0 4500ns:ldef format datadeftest#0#0#0for(i 0 511 a=i xv(a))#1#1#0.#0#0endtestFigure 16 Example of STL program.and their properties. One cannot be sure that the fabricated chip will actually realizeits functions properly, due to the limits of the simulation models as well as problemsencountered due to the fabrication process.For this reason a series of tests must be realized to certify its adequacy. Some ofthese might include:a. Automated Test Equipment (ATE) is used to do both functional and parametrictesting of the chip. The facilities at Simon Fraser University have an IMS XL1 00TM53tester, which was used in this case, that allows the user to control by softwarethe in/out signals from each of its probes. Functional tests are performed in asimilar manner to the SILOS ll simulations. The vectors from the STL programsare used on the actual chip. Instead of applying the test vectors to a schematicmodel they can be directly linked through the tester to the appropriate pin of thecodec. The responses from the chip are read directly into the test file for itsfurther analysis.Parametric tests are executed with the joint use of the IMS tester and a Tektronix2246ATh 100MHz oscilloscope. For this purpose the input vectors are set in aloop and the clock frequency is gradually incremented. At the same time theoutput responses should be observed through the oscilloscope. In this mannerthe rise and fall times of the output waveform can be accurately measured. Themaximum clock frequency tested was 50MHz.b. Data Error Analyzer tests are used to evaluate the performance of the codecover extended periods of time. For this procedure a Hewlett PackardTM DataError Analyzer (HP 1645A) was used. Pseudorandom data was generated bythe HP 1645A and used as an input to the encoder. The decoded data wasthen compared to the input pattern. Any errors detected during this processare counted, obtaining in this manner an upper bound on the BER of theencoding/decoding process. In all cases the tests were run until a BER of atleast iO was obtained.c. Built-In Self-Test (BIST) can be used as a substitute for some of the previousfunctional tests, avoiding the use of costly ATE and other such devices as well.The tests in this case are more exhaustive than the ones performed formerly,since the BIST introduces errors on the internal channel during its execution. Asimple testbed was designed to denote the detection of a fault in a chip beingtested.4. Application Specific Functional Tests provide benchmark results for the use of thecodec in different environments, thereby determining the chip’s performance under54diverse channel conditions. In contrast to the previous steps where the chip wastested independently, here the codec is interworked with the power line modem (PLM)for which it was designed. A detailed report on these tests is given in the next chapter,since it is a focal point of this research. A distinction is made for the following cases:a. Controlled environment tests were completed for channels where Additive WhiteGaussian Noise (AWGN) and Burst Errors were added in a supervised manner,thereby obtaining the statistics of the actual error rate value of the chip undersuch conditions.b. Practical channel performance tests were done for data transmissions over actualpower line communication channels. In each case a comparative analysis wasdone for each of the different degrees of interleaving.55Chapter 5Codec Performance TestsIn this chapter a complete report on the results of performance measurements ofthe codec during its operation on real communication channels is given. The chip wasemployed as a FEC device for high speed power line communications, by coupling it withtwo existing power line modems (PLM5). Each modem was developed in the Departmentof Electrical Engineering at the University of British Columbia.The objective of this study was to evaluate and gain in-depth knowledge of theactual benefits of the use of error-control on PLC data communications. A series oftests was performed that covered a wide range of operating conditions, from relativelyclean channels to very noisy ones. In every case various of parameters were measured,including: Bit Error Rate (BER), Block Error Rate (BLKER) and Throughput.5.1 System Level ImplementationTo realize practical communication tests over the PLC, two sets of high speed PLMswere enhanced with FEC. One modem uses Binary Phase Shift Keying (BPSK) and theother Minimum Frequency Shift Keying (MFSK). Each modem provides an opportunityto compare the performance of these different modulation schemes together with error-control techniques. To interface the modems with the CODEC, minor changes had to beperformed to the modems’ hardware and firmware.The enhanced PLMs (EPLM5) were designed to allow software control of the datatransmission speed (2400, 4800, 9600, 19200 Bauds) and the encoding parameters(Bypass Coding, A=1, 3, 5, 7). The values of these parameters are set in the softwarethat is used to analyze the received data which is called A Bit Error Tester for PowerLine Modems [30].The format of a transmitted packet is shown in figure 17. The preamble is used bythe data link layer of the receiver to facilitate the recognition of a high percentage of theincoming packets and to provide the receiver with a synchronization sequence on which56the receive clock (RxClk) can lock. Since the RxClk is not property synchronized withthe received bit stream until after the preamble has been processed, no data is clockedinto the decoder before the moment of synchronization acquisition. For this reason, thepreamble is not encoded before it is transmitted, hence creating the need for a procedurethat will enable the EPLMs to bypass the codec when sending or receiving the preamble,and encoding or decoding immediately thereafter the packet header, data and trailerfields.Preamble Header Data Trailer9 Bytes 11 Bytes 125 Bytes 2 Bytes—Figure 17 Packet FormatThe preamble bypass procedure was realized by inserting an extra multiplexor (U91,appendix C) and reconfiguring one of the control pins (P1.2) of the microcontroller (U24),such that this signal is high during the duration of the preamble and low during thetransmission of the rest of the packet. A D flip-flop (U93) was added at the data input ofthe encoder to synchronize edges the TxClk with the data signal.The use of a R=1/2 code implies that for every data bit two channel bits will betransmitted, or conversely, for every two channel bits received only one decoded databit will be produced. For this reason it is necessary to generate two clocks. The dataclock (CLK) is half the frequency of the channel clock (2CLK) for both the encoder anddecoder blocks. The flip-flops in U92 generate CLK from 2CLK. In future designs theseflip-flops (U92, U93) may be included as part of the codec.Similar to other convolutional decoding techniques, one of the most delicate problemsthat must be dealt with is that of synchronization, i.e., the necessity of distinguishing57between information and parity symbols. Since these two types of symbols are sentalternately on a single channel, the receiver must decommutate these bits in the properorder. For this purpose, pin P1.6 of the micro-controller (U24) has been configured asClock Set (CLK SET), which enables the clock (CLK) at the transmitter and the receiverto be set high immediately after the preamble is finished. In this way, the start of thedata is identified and the data clocks can be adjusted such that the receiving data clockphase agrees with the transmitting data clock phase and there is no uncertainty as to thelocation of information and parity bits.Apart from these minor changes, the use of the codec is transparent to the user, sincethe operational conditions of the modems remain unchanged. The schematic diagramsof the enhanced BPSK modem are given in appendix C. The performance results shownin the following sections correspond to tests executed using the enhanced BPSK powerline modem.5.2 Test ParametersTo provide a better, understanding of the performance results that will be providedlater in this chapter, a detailed description of the test parameters is given first. Thesoftware used to obtain the data for statistical analysis is called A Bit Error Tester forPower Line Modems [30]. For test purposes, packets such as the one shown in figure17 are sent from the transmitting host to the receiving host. The receiving host analyzesthe packets using this software [30], which outputs the performance parameters.During the reception of a packet, the preamble is stripped off by the data link layer,after which the host begins to examine the header. The header marks the beginning of apacket and is itself checked and terminated by a cyclic redundancy check (CRC) number,formed by its last two bytes. Following FEC decoding if no errors are detected in theheader or in the trailer then the packet is analyzed; otherwise the packet is flagged asdamaged. A detailed description of the parameter calculations that follow can be foundin [31],58For test purposes a data field of 125 eight-bit characters was used. The test patternis user selectable, in this case a string of ASCII characters was employed2. The BERis computed by counting the number of error bits detected within the data field of thepackets, divided by the number of received bits:BER — # of Bits in Error (28)— # of Received BitsThe BLKER (29) is the number of blocks received with one or more errors in the datafield, relative to the total number of received blocks:# of Blocks Received with ErrorsBLKER .. 100% . (29)# of Received BlocksBLKER is one of the most important parameters. The BLKER indicates the number ofpacket retransmissions that an actual system would have to sustain, in order to achievean error-free communication link. The number of retransmissions (RET) is given by:RET— BLKER 301—BLKERFor a valid comparison regarding the benefits of applying FEC, we must point out thatwith the use of a R=112 code, the actual data rate will be half of the actual transmissionrate without encoding. Therefore in most of what follows we will relate encoded 19200bps transmissions to unencoded 9600 bps transmissions, since in both cases the datarate after decoding, RD, will be the same.The Overhead involved in the transmission of a data packet is the number of databytes in an uncoded packet relative to the total number of bytes in the packet:h d — 1 — ( Data Bytes (31)ver ea—\Preamble + Header + Data Bytes + Trailer + Decoding DelayThe value of each of the elements that form part of (31) is:Data Bytes: A packet consists of 125 data bytes (1000 bits).2 Although a string of ASCII characters was used, a set of pseudorandom data could have also been selected, previoustests have shown that the results using different data types are virtually identical.59• Preamble: 9 bytes in length. For communications with FEC the rate at which it istransmitted, is double that of the data rate, since it is the only part of the packetwhich is not encoded. For this reason the effective length in an encoded packet willbe equivalent to 4.5 bytes.• Header: 11 bytes long.• Trailer: 2 bytes.• Decoding Delay for each case is:I. Unencoded (Bypass FEC): 0 bytes.II. Encoded A=1: 1 byte.Ill. Encoded A=3: 3 bytes.IV. Encoded A=5: 5 bytes.V. Encoded A=7: 6 bytes.Thus, the value of the Overhead factor for each instance is:1. Unencoded : Overhead=1 —(125/1 47)=1 —0.8503=0.1492. Encoded A=1: Overhead=1 —(125/1 43.5)=1 —0.871=0.1293. Encoded A=3: Overhead=1 —(125/1 45.5)=1—0.859=0.1 414. Encoded A=5: Overhead=1 —(125/1 47.5)=1 —0.847=0.153.5. Encoded A=7: Overhead=1—(125/148.5)=1—0.841=0.159.The differences in the values of the Overhead, is at most of 3%, which translates to adecrease in the throughput of up to 288 bps (9600 bps x 3%). It should also be notedthat, surprisingly, the Overhead of encoded transmissions (for A=1) is lower than that ofunencoded transmissions by 2%, which will account for an increase in the throughput forcoded data of up to 200 bps over unencoded data.Throughput, C, is calculated as follows:C = Bit Rate (1 — BLKER)( # of Received pkts— Overhead). (32)\. # of Transmitted pkts jThe error-free throughput is the most complete of all the indicators observed, since ittakes into consideration all the different variables. On the other hand, since several60factors are considered for its calculation, variations, of independent parameters may notbe always easily detected.To give a proper evaluation of the effectiveness of FEC, an explicit and completeanalysis can be derived from examining the Throughput, C, of each system. From(32), one sees that all major factors involved in evaluating the network performance, areincluded when calculating its Error-Free Throughput. These parameters include: DataRate, BLKER, % of Lost Packets, and Overhead.Lost Packets are those which are not analyzed by the software (Bit Error Tester forPower Line Modems) [30]. One or more errors in the preamble, header or trailer of apacket, Will result in a lost packet. The packet will not be recognized as valid by thereceiver, and will not be processed, even though its data field might not contain anyerrors. To indicate the rate at which packets are lost the indicator % of Lost pkts iscalculated as follows:% of Lost pkts = (i — # of Received pkts (33)\. # of Trausnutted pktsjA major issue that affects lost packetperformance, is that the preamble, comprised of ninebytes, is not encoded. Consequently the percent of lost packets for coded transmissionsat 19.2 Kbps is higher than for lower rates. This is one area for further work, to enhancethe performance of EPLMs at high data rates.Since the data rate of a system with FEC, using a R=1/2 code, is half of theactual channel transmission speed, encoded transmissions at 19.2 Kbps are comparedto unencoded communications at 9.6 Kbps. However, the results obtained for uncodedtransmissions at 19.2 Kbps are also shown in all the graphs, in this way providing a betterunderstanding of the channel’s characteristics and the amount and types of errors whichmust be corrected to achieve reliable levels of error-free throughput.5.3 Performance in Controlled EnvironmentsIn this section, the performance of the EPLM in two types of controlled channels issummarized. The improvement obtained by the use of FEC for each type of channel is61described. The channel consists of a 6 foot long copper cable, to which certain “errorsignals” are added. All tests were run for at least a 1000 packets. In some low BERcases, 10,000 packets were transmitted.5.3.1 AWGN ChannelTo simulate the effects corresponding to an AWGN channel, a white noise generator(Bruel & Kjr 1405TM Noise Generator) is used. The white noise is added in a directedmanner to the transmitted signal.Figure 18 outlines the results obtained in these trials for: (a) BER and (b) BLKERversus Eb/No, where Eb is the energy per bit and N0 is the noise spectral density. Theequations for determining these parameters are:(34)where V2 is the received signal power and R0 is the data rate after decoding, andN0 = (35)where V,2 is the received noise power and WR is the receiver noise bandwidth (in thiscase WR=8O KHz). Both V and V, in (34, 35) are true rms voltage values. To collectthese measurements a Fluke 45TM Dual Display Voltmeter was used.Figure 18 (a) shows that a coding gain of 1—4 dB can be obtained in AWGN channel(2dB for channel BER of 10). Using 1000 bit data packets and rate 1/2 convolutionalcoding, virtually no communication can be achieved on channels with BER approaching10-2, since for channels with BER near 10-2 the preamble and header have a highprobability of being corrupted, and hence, very few packets will be processed by thereceiver. However, code combining and packet retransmission can provide for significantthroughput even for channels with BER of 10—2. In part (b) of figure 18, the relationshipwith the BLKER is plotted. On average the BLKER of the encoded signal with interleave7 will decrease by 33%. In both cases the encoded signals are only shown for A=1, 7in order to provide a less cluttered graph. There is no real loss of information, since theresults for A=3, 5 fall between the ones shown in figure 18. This statement applies62_________ _______Theor. BPSK9600 Baud/B__ ___ ___19200 Baud/i19200 Baud/7____________ _ ___ _9600 Baud/B19200 Baud/i19200 Baud/7Figure 18 Enhanced modem performance for AWGN channel: (a) BER, (b) BLKER.(a)BERie-O11 e-021 e-03ie-04le-05le-06le-07le-08N\J0.00BLKER (%)5.00 10.00(b)Eb/No (dB)1 e+0252le+O1521 e+00wq’4•.—•54’‘.54 5.4’4 5.5.4,4.‘‘I,.‘lI‘l‘‘I‘‘I‘‘I: I_____0.00 5.00 10.00Eb/No (dB)63throughout most of this chapter, unless some specific regarding codec performancerequires consideration of all degrees of interleaving.The results in figure 18, are not explicit in regards to the effects of FEC on the BER,BLKER and throughput of a received bit stream. For this purpose the clearest relationshipis shown in graphs where these values are displayed versus the uncoded channel BER.Since the data rate for coded 19.2 Kbps is 9.6 Kbps, the BER of uncoded transmissionsat 9.6 Kbps is taken as the channel BER. However, the BER of uncoded transmissionsat 19.2 Kbps is also shown for reference. The solid line in figure 18 represents thetheoretical decoded bit error probability as expressed by (23). The theoretical decodedBLKER is calculated as follows:BLKERDec= (i — (1 — p)L) .100% (Lp).100%, (36)where L is the lenght of the data frame, and p is the theoretical decoded bit errorprobability.The graph in figure 19 shows the relationship between the channel BER and thedecoded BER and BLKER. From graph 19 (a) and (b) it is evident that for channelBER<1O the decoded BER decreases noticeably, ranging from 1 to over 2 orders ofmagnitude in improvement. The BER for the uncoded 19.2 Kbps channel on the otherhand is 1 to 2 orders of magnitude larger than that of the 9.6 Kbps channel BER. TheBLKER is also reduced substantially, being on the average three times lower than withoutcoding.The theoretical decoded bit error probability for a random-error channel (representedby the solid line in figure 19 (a)), falls slightly below the practical decoded BER for A=1 (nointerleaving), due to the fact that the theoretical decoded bit error probability as expressedby (23), is for a truly random channel, and considers all the previous bit estimates fedbackinto the syndrome register of the decoder to be correct. This is not always the case inpractical realizations of the AWGN, where the generated noise patterns are not completelyrandom. The spectrum of the white noise generator used is band-limited to 100 KHz,generating pseudorandom white noise. The practical decoded BER for A=7 on the other64Theor BLKER9600 Baud/B19200 Baud/B19200 Baud/i19200 Baud/7Figure 19 Channel BER vs (a) Decoded BER, and (b) BLKER for AWGN Channel.(a)JTheor Dec BER9600 Baud/B19200 Baud/B19200 Baud/i19200 Baud/7Channel BERDecoded BERle-0ile-02le-03le-041 e-05le-06le-07Decoded BLKER (%)1 e+0252le+01521 e+001 e-05 1 e-03(b)1 e-05 1 e-03Channel BER65hand is very close to the theoretical value, since the interleaving further randomizes theerrors generated by the pseudorandom AWGN generator.5.3.2 Burst Error ChannelTo evaluate the burst error correcting capabilities of the CODEC, a burst error channelwas implemented, where the burst lengths and interarrival times could be controlled.The channel was designed in such a manner that the bursts would be periodic (this isa common effect seen on the power lines). For the duration of a burst the signal wasseverely attenuated (over 30 dB). A moderate level of background white noise was addedconstantly to the bit stream to generate conditions that would approximate those on anactual communication channel. After completing a wide range of tests, where both theinterarrival times and the burst lengths were varied, it was concluded that the actual bursthandling capabilities of the chip corresponded to its theoretical capacity.The experiments done with maximum correctable length bursts were found to be theones of most interest. In figure 20, the results of an experiment done on a burst errorchannel with 14 channel-bit (19.2 Kbps) burst errors are presented. It can beseenfrom figure 20 (a), that the codec with interleaving degree 7, starts correcting all theerrors as soon as the channel BER drops below 2.0x10,which in this case representsthe maximum correctable error-burst frequency (196 Hz). This value may be obtainedanalytically by using the following arguments:• A (2, 1, 6) threshold decoder with A=1, can correct 2 out of 14 channel-bit errors.• If interleaving techniques are used and A=7, such a decoder can correct 14 out of98 channel-bit errors.• For a 19.2 Kbps channel transmission speed, 98 bits represent 19200 KHz/ 98 =196 Hz.Figure 20 also illustrates that for error bursts of length 14, neither A=1, 3 or 5 is sufficientto eliminate all of the bursts. There is a considerable improvement for case A=5, sincein many cases a burst of length 14 will not necessarily corrupt all the bits it attenuates.66Ile-Ol319-02319-033le-043le-05318-063ie-07Decoded BLKER (%)9600 Baud/B19200 Baud/B19200 Baud/i19200 Baud/319200 Baud/519200 BaudI7le-05 ie-04 le-03 le-02 ie-01Figure 20 Channel BER vs Decoded BER (a), and BLKER (b) for a Bursty channel.Decoded BER(a):____- ..,‘ ,,II-ii/ I,1’9600 Baud/B19200 Baud/B19200 Baud/I19200 Baud/319200 Baud/519200 Baud/7Channel BERie-05 le-04 le-03 le-02 le-Ol(b)ie÷0252le+0l52le+00--,;‘I_ /- /Ir I’ ,I -,‘i2’ , I I•/,// ,I,‘/,‘,,,I,-. I I II,,,,,,,, ,,,,,,,/: ,‘ I: ‘ I-I - Channel BER675.4 Performance over the Power-Line ChannelA wide series of tests were completed over various channels in the Electrical Engineering building. In general, the power lines in this building constitute a harsh communication environment. Very diverse types of loads are encountered, ranging from industrialmotors and machinery to office equipment and computers.The basic issues that are of concern for an appropriate understanding of the resultsobtained through our experiments are:• The general power distribution system is divided into two three phase sub-systems,one for all the laboratories and machine shops and the other for all lighting and walloutlets. Each of these systems has an independent distribution bus.For ease in cross referencing we will use the terminology used in [31]; the first systemwill be referred to as Lab Sub-System and the second as General Sub-System.• Power flows from the building’s three phase transformer to the General Sub-System,and from there, across a link, to the Lab Sub-System.• The three phases of each of the systems will be denominated X, Y and ZThree different types of tests were completed on this network, providing ample rangeof channel quality:I. Local Area communications within the Lab Sub-System, in this case communicationlinks are limited to a room.II. Extensive Area communications throughout the General Sub-System.Ill. Extensive Area communications, with transmissions across the link interconnectingthe Lab Sub-System and the General Sub-System.5.4.1 Local Area CommunicationsThe environment selected to run the local area communication tests was the Communications Laboratory (Rm. 458), where a large number of electronic equipment isconstantly in use. The tests were performed over three different representative channels, X-Y, Y-Y and Z-Y, having in this way same phase and cross phase transmissions.Figures 21, 22 and 23 show the results obtained in this study.68Output BLKER (%)9600 Baud/B19200 Baud/B19200 Baud/i19200 Baud/79600 Baud/B19200 Baud/B19200 Baud/i19200 Baud/7Figure 21 Channel BER vs Decoded BER (a), and BLKER (b) for X to Y channel.(a).. IOutput BERle-Olie-021 e-03ie-041 e-05ie-06le-07/I/SII,‘II’I II,IIle-05 le-03 le-OlInput BER(b)le+02521 e+0i521 e+001I sI :1I ./:1I :‘I t II ‘II( :‘SIle-05 ie-03 le-OlInput BER69le-06ie-07Output BLKER (%)(a)(b)9600 Baud/B19200 Baud/B19200 Baud/i19200 Baud/79600 Baud/B19200 Baud/B19200 Baud/i19200 Baud/7Figure 22 Channel BER vs Decoded BER (a), and BLKER (b) for Y to Y channel.Output BER1 e-01ie-021 e-03ie-04ie-05.9/•4’!/ss11 e-05 1 e-03 1 e-0iInput BERle+0252ie+01521 e+00;4i:i71 e-05 1 e-03 1 e-0iInput BER70Output BLKER (%)(a)(b)I 9600 Baud/B19200 Baud/B19200 Baud/i19200 Baud/79600 Baud/B19200 Baud/B19200 Baud/i19200 BaudI7Figure 23 Channel BER vs Decoded BER (a), and BLKER (b) for Z to Y channel.Output BERle-Olie-02ie-03ie-04le-05ie-06ie-071 e-05 19-03 1 e-OiInput BER1 e+02521 e+Oi521 e+00•,/L/I ‘‘II II II II II II ‘I;_____/1;I:,I1 e-05 1 e-03 1 e-0iInput BER71To obtain distinct channel BER and BLKER over the same channel, the transmitter’soutput voltage is varied accordingly, thus changing the signal to noise ratio of the signal.However, since the object of this research is to examine the effects of FEC on power-linecommunications, graphs that emphasize transmitter power are not shown, but it must benoted that to obtain the same BER over different links, the transmitter voltage must beincreased for cross phase transmissions. For these trials the transmitter voltages variedin the following ranges: for X-Yfrom 61 to 72 dBmV, for Y-Yfrom 35 to 43 dBmV, andfor Z-Y from 57 to 71 dBmV.Comparing the results obtained in figures 21, 22 and 23 with the corresponding plotsin figure 19, we can see that the total effect of all the channel impairments on these linksis similar to that of a AWGN channel. In all cases, the results obtained show the positiveeffects that FEC has on the reliability of the data transmissions. On average the BER canbe reduced from one to two orders of magnitude (for uncoded channel BER of 10 andi0, respectively). These graphs indicate decreases in the BLKER ranging from 30%to over 100% of the original channel BLKER5 for unencoded transmissions. By reducingthe need for packet retransmissions drastically in these cases, a substantial increase inthe general throughput of the system results.5.4=2 Extensive Area Communications over the GeneralSub-System and across Sub-SystemsIt should also be pointed out that there are great variations in the behavior ofeach of the channels during different times of the day. For this reason the extensivearea communication tests were done in a different manner. The fluctuations of thecharacteristics of each channel over 24 hours, as well as the effect of error controltechniques in each case, was observed and recorded. The results obtained from theseof tests provide a practical indication of the performance of intrabuilding power linecommunications over a wide range of different communication links. As stated earlierthe communications links were established over channels of a single power sub-system,as well as connections across both power sub-systems.72Test Procedure. The tests were conducted in the following manner: the transmittingmodem was connected to either the wall outlet (General Sub-System) orto the Yphase ofthe power bars (Lab Sub-System) in room 458. The receiver was moved among differentlocations across the building, in this way providing a wide range of channels with variedcharacteristics. Since the PLC is a highly time-variant channel, the trials were executed for24 hours in each site, and averages over this period were taken for evaluation purposes.The locations where the receiver was situated were the following:• Room 113 (ZPhase).• Room 214 (Y Phase).• 3rd Floor Stairwell (X Phase).• 4th Floor Stairwell (X Phase).• Room 402 (Y Phase).Due to the routing of the wiring within the building [32], physical proximity of a transmitter-receiver pair does not necessarily imply a shorter communication channel. Actually, sincethe main distribution buses are located in the basement, proximity between transmitterand receiver often results in very long communication paths. Examples that illustratethese cases can be found in [31]. A summary of the structure of this power-line networkis given in [31], and detailed plans of the wiring layout may be found in [32].Figures 24, 25, 26, and 27 were selected as being the most representative ofthe results obtained during the extensive area transmissions. These results representperformance of the “best” and “worst” channels. In each case the tests were duplicated,once for transmissions within the general sub-system and the other for communicationsacross sub-systems.It can be seen from the graphs in figures 24—27, that the channels that have linksacross power sub-systems are of considerably lower quality than those that are limitedto just one of the sub-systems. For unencoded transmissions at 19.2 Kbps the BER isrelatively constant, fluctuating between 10-2 and 10, even for very “clean” channels.An example of this is the one between Rm 458X and the 3rd Floor stairwell, where theBER9600 was under i0 the BER19200 rarely dropped below 10.73__________ __________60O/B‘i6o?f__96001B1i5ö7•, o_&Figure 24 BER as a function of time for transmissions from Rm 458 to Rm 214.(a) Transmissions over the General Power Sub-system,(b) Transmissions across Power Sub-systems.74(a)BERle-Olle-02le-031 e-04le-05le-06le-07BERle-Olle-021 e-031 e-04le-05le-061 e-07Time(hours)-.i\ aA-D.%.i W‘Z\r’_I II II I. a ‘II •a.‘I III,I’’ •—— II I I,‘I I I. II I I I1I II IIIII4.40.00 10.00 20.00(b)0..DJEESAf’T1IiIII II I 1dIiI I qI1’ I ftLI, , ; I III , III.I III I I II• II II I III II II I4 80.00 10.00 20.00Time(hours)(a) x io3.•.e-03 •ae- .G.ARi.; ,‘0.00 10.00Throughput(bps) x 1 o320.00(b)96001Bó?iiA01 öod7fTime(hours)96001B01Time(hours)0.00 10.00 20.00Figure 25 Throughput as a function of time for transmissions from Rm 458 to Rm 214.(a) Transmissions over the General Power Sub-system,(b) Transmissions across Power Sub-systems.75(a)BER1 e-011 e-02le-03le-041e-051 e-06le-07BERle-Olle-02le-03le-041 e-05le-061 e-070.00 10.00 20.00(b)9600/BTime(hours)96001B5ô7éDjTime(hours)0.00 10.00 20.00Figure 26 BER as a function of time for transmissions from Rm 458 to the 3rd floor stairwell.(a) Transmissions over the General Power Sub-system,(b) Transmissions across Power Sub-systems.76Throughput(bps) x 27 Throughput as a function of time for transmissions from Rm 458 to the 3rd floor stairwell.(a) Transmissions over the General Power Sub-system,(b) Transmissions across Power Sub-systems.77‘:; r.$crW0.00 10.00Throughput(bps) x io20.00(b)9600/Bi5iS1Gjod7fTime(hours)96001B°i äoo7iTime(hours)I’- I’: : ‘.• I •I I! ‘ I— I I* I,.4e . SI L1I’ ‘. -...pp. annn-n0.00 10.00 20.00For very noisy links, FEC with interleaving degree 7 proved to be the most effectivescheme. For channels such as those between Rm 458Y—Rm 214 and Rm 458Y—3 Floorstairwell (Figures 25 and 27) a considerable increase in the throughput can be obtainedin this way, achieving an average throughput of over 1600 bps over links that previouslywere virtually unusable.Since the PLC is a highly variable channel, the BER between two links may havefluctuations anywhere in the range from 10-2 to 10, over a 24 hour period. For thisreason the average BER is not a parameter by which the effectiveness of FEC can bejudged, since the weight of one high BER sample (e.g. 10-2) will out weigh a series of lowBER samples (e.g. 1 0) obtained throughout the rest of the day. The average BLKER willgive a much better idea of the real performance of the system throughout the test period.The average BLKER over a 24 hour period for each of the trial channels is shown in figure28. The results show that on average the BLKER of encoded 19.2 Kbps transmissions(9.25%) is three times lower than that of uncoded 9.6 Kbps transmissions (30.18%), andseven times lower than that of uncoded 19.2 Kbps transmissions (71.67%).Table 1 provides a summary of the average throughput for each communication link.Table 1 shows the error-free throughput of the system taking into account the percent oflost packets, which is due primarily to the use of an uncoded preamble even with the useof FEC. In table 2 the resulting error-free throughput is shown, considering the percentof losf packets to be zero.78X-Denotes transmissions over the general power sub-system.Y-Denotes transmissions across power sub-systems.Figure 28 Average BLKER (over 24 hours) for each of the tested channels.7R113X R113Y R214X R214Y HaII3X HaII3Y HaII4X HaII4Y R402X R402YLocation79Mode! 9600 19200 19200 19200 19200 19200Location Bypass Bypass Intlv=1 Intlv=3 Intlv=5 Intlv=7Rm 6124 1102 5813 5495 5633 5998113*Rm 7863 4057 8077 7936 7808 7797113tRm 6815 2437 7904 7736 7720 7677214*Rm 5412 2506 7222 7162 7150 70812 14Stairs 8273 8455 8407 8281’ 8188 81303rd*Stairs 441.1 2.366 1479 1847 2515 28033rdStairs 8246 6729 8365 8224 8128 80714th*Stairs 2256 67.28 5043 4706 4625 43124thRm 8274 15297 8246 8166 8019 8023402*Rm 0.000 0.000 1097 1037 1700 1651402Average 5370 4065 6165 6059 6148 6155Table 1 Average Error-Free Throughput for communications from room 458.Transmissions over the General Sub-system are marked .Transmissions across Sub-systems are marked t.80Table 2 Average Error-Free Throughput forcommunications from room 458. % of Lost Packets = 0.Transmissions over the General Sub-system are marked .Transmissions across Sub-systems are marked .Mode/ 9600 19200 19200 .19200 19200 19200Location Bypass Bypass Intlv=1 lntlv=3 Intlv=5 Iritlv=7Rm 6829 2036 7815 7819 7588 7702113*Rm 7912 4985 8478 8359 8245 81901 13Rm 7062 3266 8369 8253 8215 8157214*Rm 6446 3666 8322 8261 8176 8080214Stairs 8275 9243 8480 8362 8247 81913rd*Stairs 889 2.4 4297 5562 5472 55983rdtStairs 8250 7714 8480 8361 8247 81914th*Stairs 3813 170 7725 7527 7472 71754thtRm 8275 15787 8480 8362 8247 8191402*Rm 0.000 0.000 3006 3330 4744 4852402Average 5775 4686 7345 7420 7465 743281Summarizing the results obtained in the experiments that were completed as part ofthis research, the following conclusions may be drawn:Forward Error Correction proved to be an effective way to increase the Error-FreeThroughput of Intrabuilding Power Line Communications, providing in this manner thepossibility of maintaining reliable communications over channels with highly variablecharacteristics.II. The application of FEC is extremely effective for very hostile environments. In suchcases, the burst error-correcting capabilities of the CODEC are utilized extensively,making the employment of such features indispensable for obtaining reliable communications.Ill. Even for relatively “clean” channels it is more efficient to transmit at higher speedswith FEC, rather than at unencoded lower data rates. The overall throughput will behigher due to the reduction in overhead by 2%, providing in this way an increase ofapproximately 200 bps.IV. The throughput of the EPLM increased by an average of 15% with the use of error-control techniques for the 10 test locations. If methods that would allow externalsynchronization were to be used, (thus permitting the preamble to be encoded), anadditional 15% increase could be achieved, obtaining a total increment of up to 30%in the error-free data rate.V. The use of coding with higher levels of interleaving, (A=5, 7), in many cases did notresult in superior performance over that of FEC with A=1. This puts in evidence thefact, that in many cases, the compounded effect of all the error sources on the PLC willbe similar to that of random noise. However, in the cases where there were a largepercentage of burst-errors, interleaving increased considerably the performance ofthe system.VI. An increase of the channel transmission speed by a factor of 2, will result on average,in an increase in the BER of 10 to 100 times for unencoded transmissions, resultingalso in a substantial increase in the BLKER.82VII. The packet throughput (the amount of packets that are received and processed)decreases by 10% to 70% when 19.2 Kbps communications are used. The use ofFEC limits this loss of packets, but does not eliminate the problem completely, sincethe preamble is transmitted without encoding. The use of encoded preambles wouldincrease the packet throughput by another 15% to 20%.VllI.The effect of local error sources, close to the receiver, can be substantial because thereceived signal can be severely attenuated and faded; consequently local noise ofrelatively low power (such as the host computer) can be the origin of a large numberof errors.83Chapter 6Summary6.1 Concluding RemarksThis thesis summarizes the research involved in the design, implementation, fabrication, testing and evaluation of a VLSI convolutional encoder and threshold decoder.The focus throughout the development of the codec was to achieve a design with relatively low complexity that could provide the necessary performance for its application inintrabuilding power line communications.The codec consists of a rate 1/2 (2, 1, 6) convolutional encoder and thresholddecoder, with programmable degrees of interleaving. Threshold (majority-logic) decodingwas selected due to the ease of its implementation, and because the algorithm isvery well suited for use with interleaving, making it easily extendable to correct errorbursts. Performance capability and implementation simplicity make threshold decoding anattractive alternative to more complex and expensive decoders, such as Viterbi decoders.The main features of the developed FEC chip are:1. Random and burst error correcting capabilities (for A=1, 2 errors of every 14 channelbits can be corrected; or for )=7, error bursts of up to 14 channel bits can becorrected).2. Automatic error resynchronization properties with respect to error propagation.3. Programmable degrees of interleaving =1, 3, 5, 7).4. Maximum throughput of 50 Mbps.5. Small decoding delay compared to other methods.6. Independent encoder and decoder circuits on one chip, supporting full duplex communications.7. Built-In Self-Test that provides 100% single stuck-at fault coverage, with under 10%of area overhead.848. Total core area of 2.32 mm2, which represents less than 10 to 50 times the area ofViterbi decoders of similar characteristics [33].The VLSI codec was fabricated using 1 .2im CMOS technology and is a semi—customdesign that uses standard CMOS4S CMC library cells. Its total complexity is 1,600gates (5K transistors), with a core area of 2.32 mm2. This area includes the BIST andinterleaving circuitry.To evaluate the benefits of FEC in power line communications, the codec wasinterfaced to two existing PLM5. A wide range of tests were performed to determine themodem’s performance with and without FEC. Trials were carried out over channels withcontrolled error sources, and over actual operational power line channels. Tests werecompleted for local area communications as well as for extensive area transmissions.Original data was collected which permitted a statistical analysis of the BER, BLKER,percent of lost packets, and throughput in every case.The results of this study show that the use of forward error correction is an effectivemethod of increasing the Error-Free Throughput of intrabuilding power line communications, providing in this manner the possibility of maintaining reliable communicationsover channels that could otherwise not be used for data communications at 9.6Kbps and19.2Kbps. The positive effects of FEC are prominent during transmissions over veryhostile environment, where error bursts are very frequent due to channel impairments.Even for communications over “clean” channels, the use of a higher data rate combinedwith FEC proved to be slightly more efficient than transmitting at a lower data rate.Throughout this research a wide range of channels with different characteristicswere used. A common factor in all circumstances was that the increase of the channeltransmission speed by a factor of 2, will result on average, in an increase in the BER by1 to 2 orders of magnitude for uncoded transmissions. However, with the use of this typeof error-control technique an increase in the throughput of the system, ranging from aminimum of 10% to several times that of uncoded transmissions, can be obtained. Thisis primarily due to a steady decrease in the BLKER for coded communications, whichlowers the number of packet retransmissions due to corrupted data. -85The test results also indicate that the frequent presence of error bursts is not acommon factor to all power line channels. For this reason the use of higher degrees ofinterleaving (A=5, 7) will not always provide the best results. This is proof of the need ofa codec that can handle variable interleaving degrees.62 Suggestions for Future ResearchEnhanced power line modems can reliably support high speed power line communications at 19.2 Kbps in relatively hostile environments. This is due in part to two recent,significant developments: namely the design and fabrication of an all-digital MSK modem chip, and of a low cost FEC codec chip. At present both these chips, togetherwith a micro-controller form the EPLM, which at this stage is already small enough to beimplemented as an internal expansion card of a personal computer (PC).The reliability of power line communications has increased substantially due to thefact that FEC is now an integral part of the modem, and also because the number ofexternal interconnections (wire-wrapping or soldering) has drastically decreased. Manyof the modem functions are implemented by these three major chips.There are several enhancements which can be performed to the existing EPLMs.The first and most noticeable would be the unification of the modem and the codec ontoone single chip, increasing further the level of integration and component reliability.The second enhancement would be to find alternatives that would allow the encodingof the preamble. This could be achieved by using some type of external synchronizationtechnique, and would generate an increase in the throughput of the system, probably bymore than 15%.A third possible improvement would be the use of a faster microcontroller to enablethe EPLM to double its bit rate to 38.4 Kbps. However, the use a higher speed could beaccompanied by other detrimental effects, such as unreasonably high BER and BLKER,which would decrease the overall throughput of the system. A complete evaluationof the system’s performance, together with the effects of FEC in different operationalenvironments would have to be repeated for this case.86From a statistical and practical point of view, further studies should be done whichcould define the limits (worst cases), for which the EPLMs can be used. Focal points ofsuch work could be directed towards finding maximum in-building distances for reliablecommunications, with the use of the maximum allowable transmitter signal power, andevaluation of the performance of coded 38.4 Kbps communications versus uncoded 19.2Kbps transmissions.These above suggestions are not exhaustive. Much work could be done in relatedareas. Examples include development of means for eliminating the local noise generated by the host computer, the development of the higher level protocol layers, alsoconduct a wider and more extensive series of tests, in different buildings with differentcharacteristics. Use of some sort of adaptive modulation/FEC coding is also of interest,to optimize throughput performance under conditions of varying channel quality. Recent work reported in [4] is a viable approach, in which the use of FEC together withpacket retransmissions and code combining is proposed, as a mean to obtain reliablecommunications even in very hostile environments.87Bibliography[1] R. Gershon and M. Propp. A Token Passing Network for Powerline Communications.IEEE Trans. on Consumer Electronics, vol. CE—37:pp. 129—134, May 1 99t.[2] M. H. L. Chan and R. W. Donaldson. Amplitude, Width, and Interarrival Distributionsfor Noise Impulses on lntrabuilding Power Line Communication Networks. IEEETrans. on Electromagnetic Compatibility, vol. EMC-31 :pp. 320—323, Aug. 1989.[3] M. H. L. Chan. Channel Characterization and Forward Error Correction Coding forData Communications on Intrabuilding Electric Power Lines. PhD thesis, Universityof British Columbia, 1988.[4] J. 0. Onunga and R. W. Donaldson. A Simple Packet Retransmission Strategy forThroughput and Delay Enhancement on power line communication channels. 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SAC-5:pp. 724—748, May 1987.92Appendix A Codec Schematic andLayout RepresentationsPRUEBA CODECIinpod ENCO(pad)outpod4mAnpodA MUXL113 o INbuf(—)inpodrii0________vddpodgndpadDECODERfl1o%___inpod[I° Ri(pad)IN 0ot rIk2bufinpod(pad)inpodFigure 29 Schematic diagram of the (2,1,6) convolutional encoderand threshold decoder with fixed interleaving degree (=7).93CD—-\\\\\\N\\\\N\\\\\K\\\\ \\\ N\\\\\__I, 1j IIII.__I______ ________: c:__ __a_s...[1___ __ _ _:_________ __ _ __s Li__I ii I’ I i I iRNtL\\\\\\\\___ _____________\\\\ \\\\\\\ç-’ç-ZFigure 30 Layout representation of the (2,1,6) convolutional encoderand threshold decoder with fixed interleaving degree =7). Designidentification name BCCOD. (Only the metal layers are shown).94VAR INTERLEAVE CODEC2ENCODERinpodri Cl C2 nt.,.inpad e 1 3L36o,._________ii 51 1 7inpod_..l C2 Cl(pnd) Ioupad4mAtnpad________________________________Et2.1.6___ _ _ _ _LTh ,t jig_32inpodt ufrii310iripodrtl II)IDECODERinpodinpod1k9_________ __ __ ___ _ _1 31 51 1 7inpodinpadinpodTh___d)Figure 31 Schematic diagram of the (2,1,6) convolutional encoder andthreshold decoder with programmable interleaving degrees 3, 5, 7).95VARINTERLEAVECODEC2I-I:-‘._,-‘CDCDCl)Cl)Ci)r’)CD0 0.0 -‘Z3•CD6CDC)3ö>0)0DcT‘0-.CDCD 5C)CD•.<CDCDCDCD-Cl)C) 0)-..J0Tireseticikiseti119114113IiiI.’Y/Y7Y7’1I’7Y½1[‘‘/‘I17/77/7reset2118set2115Ri116decC2134.t—tt.t—p,s-is,s-.t’aa%7/77/7/___________//C//t7‘IILLLL/V_LZ.LL77Z7//////177/7V)//////i///-,-a-———c———g——a———a.-.-c———c——e--_________V///Ui112eneCi137encC2136VDD123VA’799IIZ///////1/,‘/JW7444Iclk2decCiGNDul11713512412011?J____II I(-)m1LIç_) IH__C17———-— — — — —iHwFigure 33 Schematic diagram of the (2,1 ,6) convolutional encoder and thresholddecoder with programmable interleaving degrees (=1, 3, 5, 7) and BIST.97BISTCODECCODEC3encC2resetlclklUiRi12121Ii11818___7/7J9/7Z/44//%///-__________III‘5I______Bset2_1Ii4‘p4eiH•IP1LdIII‘IflIu‘jI__decCi__)r4I_istCD.LF-.IJI1p-p______TCD-‘U)U)__________________________///___LI___/74///VDDsetireset2clk21917119123Appendix B Codec Bonding DiagramsTopViewBottomView(a)1\\yfFi8(b) Ii’Figure 35 68—Pin PGA (a) pin numbering scheme, and (b) bonding diagram.99ILLf-- 4 JJ -‘:7Figure 36 BCCOD bonding diagram.PACXAGE LIDKD84840A C-804no substrate connections required, all pins should be floatingWIRE ALLOY 99% A1/ly. Si DIA. .001” ELONG. — T.S. 1(4—16 ms99% A1/1% SI 00125” 1.5 — (4% 16—22 urnsD/A PREFORM ALLOY 98% Au/2% Si RECOMMENDED SIZE W/8 METHOD U.S.BONDING D!AGRM KCT!5 1. DIE ATTACH PAD SiZE:.400 X .4002. ZERO GROUND34 2 18T7/j/7 &LJI—1—1?1612I’10S43100BONDING DIAGRAM NOTES:.400 X .400Figure 37 BCMAJ bonding diagram.PACKAGE LIDKD84840A C—804no substrate connections required, all pins should be floatingWIRE ALLOY 99% Aifi% Si DIA. .001” ELONG.i’5 T.S. l—16 Qms99% A1/i% Si.00125” 1.5— % J8—22 omjD/A PREFORM ALLOY 98% Au/2% Si RECOMMENDED SIZE_________W/B METHOD U.S.1. DIE ATTACH PAD SIZE:2. ZERO GROUNDZ251 59 g 6fl101BONDING DIAGRAM NOTES:.400 X .400Figure 38 BCBST bonding diagram.PACEAGE LIDKD84840A C-804no substrate connections required, all pins should be floatingWIRE ALLOY 99% Aifi% Si DIA.______________ELONG. - % T.S. 1’4—16 Qms99% A1/i% Si.00125” 1.5— % 18—22 omD/A PREFORM ALLOY 98% Au/2% Si RECOMMENDED SIZE_________W/B METHOD U.S.1. DIE ATTACH PAD SIZE:2. ZERO GROUND25 24102Appendix C Enhanced PLM Schematic DiagramsThe schematic diagrams of the EPLM given in this appendix are the sections in whichchanges were made to the BPSK PLM developed by Buternowsky. Schematics of otherfunctional blocks not related to the encoding/decoding process may be found in [31].The schematic diagrams that are shown on the following pages are:1. Functional block diagram of the EPLM.2. Enhanced power line modem control block.3. Enhanced power line modem PSK modulator block.4. Enhanced power line modem FEC encoder/decoder block.103MXG.cJNALI120VAC(1)1120VAC()IIPREAI4.COOECINIPREAMONFFBflSYNCIOI.cBETMXBITSOEOOUTTXDATACLX•TXBITSPREAM’OOOEOIN,PREAMONIOEF4CLXSETBITBYDEOOU1FILTTXSIGIFILTTXBIGTXSIGNALIITXSIGNALTXBITS1.8432MH4840D34BAUDO1RXSIGNALFILTMXT.C(DTE4T,D(DTE)14.745SMI-4B....4FILTMXBIGMXBITS1TE4INALWdTEMFACET,O(OTE)r-.D(OTE)________BflBYNCfIRGt.IIZP.TIONE::z4OWEMWJPY I20VAC(2120VAC(1mMmeTSooO011SOTmzI>z0rn000rnrz00m00z-0r-f00)>C000C3CzzC3aCgCC>CC(C-COCD(CCCp.0rnr0aR47-a 04-5’, 140474.213TL.O2÷5v..-5v÷5’,÷5’,5v÷5v.,-12VG7O..C71072a1..0?3-V..G74...075IQNFIONF1ONF1ONF1ONF1ONf’f1ONI076ONF-12iCOMMUNICATIONSLABDEPARTMENTOFELECTRICALENGINEERING.UBOritiENHANCEDPLM-PSKMODULATOR$IDocumentNumberREVAEPLM-00440AUOUSt5.19921Sheet4ct11LOT-‘4.oo0C) C)0CzC)0zrCC00C3C2C3A’.’ra4.‘UUDDaA’zI)zC) A’0r‘AC)mzC)0UA’CmC)00mU•0-‘Az-I0‘Am-I0I‘Azz‘AA’z0‘AC)D4


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