E m b e d d e d Test Circuits a n d M e t h o d o l o g i e s for Mixed-Signal ICs by Sassan Tabatabaei-Zavareh M . Sc. (Electrical & Computer Engineering), The University of Calgary, 1994 B . Sc. (Electrical & Computer Engineering), Isfahan University of Technology, 1991 A THESIS SUBMITTED I N PARTIAL F U L F I L L M E N T O F THE REQUIREMENTS FORTHE DEGREE OF Doctor of Philosophy in THE F A C U L T Y OF G R A D U A T E STUDIES (Department of Electrical and Computer Engineering) We accept this thesis as conforming to the required standard The University of British C o l u m b i a February 2000 © Sassan Tabatabaei-Zavareh, 2000 In presenting degree at the this thesis in partial fulfilment of the University of British Columbia, freely available for reference department or by his or I agree that the and study. I further copying of this thesis for scholarly purposes her representatives. requirements for an advanced Library shall make it agree that permission for extensive may be granted It is by the head understood that of my copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of &Jbsju'Cg The University of British Columbia Vancouver, Canada Date DE-6 (2/88) Qz^ Cil^jl^Uf G^t^e/tLcj ^-^ A b s t r a c t The rapid pace of the integrated circuit industry towards more miniaturization is making system-on-chip (SOC) a reality. For practical implementations of S O C , however, the test issues of such devices must be addressed through the integration of design-for-testability (DFT), built-in self-test (BIST), and embedded test for embedded blocks, such as digital, memory, and mixed-signal circuits. This thesis presents two novel embedded test solutions for mixed-signal circuits. The first one is a built-in current monitor ( B I C M ) suitable for power supply current (IDD) testing. The B I C M includes a built-in current sensor (BICS) which provides high measurement sensitivity without introducing a large impedance i n the IDD path. Although the B I C S structure has been proposed before, the new circuit analysis and chip measurement results provide important insights into the B I C S characteristics and design trade-offs. The B I C M also includes a mixed-signal built-in current integrator (BICI) which generates a digital signature proportional to the average IDD (IDD)- TWO different circuits have been developed for B I C I : a single-phase and a double-phase B I C I ; the first is less accurate but requires less silicon area. These new B I C I architectures offer an advantage over previously proposed circuits because they can perform integration over large time windows (T > 1 ms) while occupying a chip area equivalent to a only few hundred N A N D gates. The B I C M is com- ii pact, accurate (error < 2%), and insensitive to process and temperature variations. The second embedded test circuit is designed for non-intrusive functional testing of high-speed clock-recovery units ( C R U ) and clock-synthesis units ( C S U ) . To the author's knowledge, this new structure is the first circuit which can perform on-chip, single-shot jitter measurement with high resolution and precision without requiring element matching. The simulation and analysis predict a jitter measurement resolution o f lOps and a precision of 1 lps in a 0.35 fim C M O S technology under typical power supply and thermal noise conditions. Combined with a jitter generator block, it can test intrinsic jitter, and jitter transfer characteristics of C R U s and C S U s . The circuit is digital, partially synthesizable, and automatically placeable and routable. Novel gate delay model and analysis techniques, supported by simulation, are also introduced to evaluate the accuracy of the circuit. iii C o n t e n t s Abstract ii Contents iv L i s t o f Tables ix L i s t o f Figures x Claims of Originality xiv Acknowledgements xvi Dedication 1 xviii Motivations and Overview 1.1 1.2 1 Built-in current monitoring .2 1.1.1 On-chip current sensing 3 1.1.2 On-chip current averaging 5 P L L testing 7 1.2.1 8 Jitter testing iv 1.3 2 Motivations and Contributions B a c k g r o u n d A n d Survey 13 2.1 I C Testing 14 2.1.1 W h y test integrated circuits? 16 2.1.2 Test and diagnosis 17 2.1.3 Functional versus structural testing 18 2.1.4 Defects and faults 19 2.1.5 Test generation 21 2.1.6 Design for testability (DFT), built-in-self-test (BIST), and embed- 2.1.7 2.2 2.3 3 9 ded test 22 Digital circuit testing 24 Analog and Mixed-Signal Testing 26 2.2.1 History 27 2.2.2 Testing analog circuits 29 2.2.3 Analog and mixed-signal D F T 34 2.2.4 Mixed-signal B I S T 35 Conclusions 37 B u i l t - i n C u r r e n t M o n i t o r for Testing A n a l o g C i r c u i t B l o c k s 38 3.1 B u i l t - i n Current Sensor (BICS) 40 3.1.1 B I C S circuit 40 3.1.2 B I C S accuracy 42 3.1.3 Calculating Z ic 43 B v 3.2 3.3 3.4 4 Single-phase B I C I . . 47 3.2.1 Basis 47 3.2.2 Notation and definitions 49 3.2.3 Circuit operation 50 3.2.4 B I C I two-point calibration 55 3.2.5 Single-phase B I C I accuracy 57 3.2.6 Circuit implementation 58 Simulation and Experimental Results 61 3.3.1 BICS 61 3.3.2 Single-phase B I C I 65 Conclusions 68 Double-Phase B u i l t - i n Integrator 70 4.1 Introduction 70 4.2 Double-phase B I C I Circuit 71 4.2.1 Basis 71 4.2.2 Notation and definitions 73 4.2.3 Circuit operation 75 4.2.4 Half-wave current integrator ( H C l ) 4.2.5 Double-phase B I C I two-point calibration 81 4.2.6 B I C I accuracy 82 4.2.7 Circuit implementation 82 . 76 4.3 Simulation and Experimental Results 85 4.4 Conclusions 86 vi 5 O n - C h i p J i t t e r Specification Testing of H i g h - P e r f o r m a n c e P L L s 5.1 5.2 89 Jitter Definitions 90 5.1.1 92 P L L jitter specifications Jitter Measurement Circuit ( J M C ) 92 5.2.1 State of the art in T D C design 93 5.2.2 High-resolution T D C 98 5.2.3 Notation and definitions 99 5.2.4 Time quantizer 100 5.2.5 Measurement range extension 105 5.2.6 Calibration 108 5.2.7 Automatic resolution adjustment 110 5.2.8 Controlled load ( C L ) cell design 5.2.9 Resolution adjustment control block 5.2.10 T D C error sources . 116 119 . 132 5.2.11 Accuracy, Precision, and Resolution 136 5.3 Jitter Generator 141 5.4 Schemes for On-Chip Jitter Specification Testing 142 5.4.1 Cycle-to-cycle jitter measurement 142 5.4.2 Relative jitter measurement 142 5.5 Implementation 146 5.6 Simulation Results 150 5.6.1 Jitter measurement circuit 150 5.6.2 Accuracy estimation 151 vii 5.7 6 Conclusions 153 S u m m a r y a n d Conclusions 6.1 159 Future Research 163 Bibliography 165 Appendix A B I C S Frequency Response Analysis 178 Appendix B A'" a n d I Relationship i n the Single-Phase B I C I 181 Appendix C N a n d I Relationship i n the Double-Phase B I C I 185 Appendix D T D C Calibration 187 D.l Two-point Calibration 187 D.2 n-point Calibration Technique 190 Appendix E Metastability window of a D Appendix F Range E x t e n d e r B l o c k A n a l y s i s Appendix G Two-Parameter M o d e l for Vdd-induced flip-flop 194 197 G a t e Delay Variations 199 G.l Test 1: Single Gate Delay Simulations 199 G.2 Test 2: Ring Oscillator Test 201 Appendix H T D C Power S u p p l y Noise Analysis viii 205 L i s t o f T a b l e s 3.1 Area overhead comparison of two current mirror matching techniques . . . 3.2 L o w frequency impedance and bandwidth of Z ic 61 3.3 Single-phase B I C I test signals 66 3.4 Simulation results for the average current measurements by single-phase B 43 B I C I circuit 68 4.1 Double-phase B I C I test signals 86 4.2 Simulations of average current measurements by double-phase B I C I . . . . 88 5.1 Tdij and S ^ s v for different styles of C L cells. Numbers 1 through 6 i n the first column refer to the states a = 000001,000011, 000111,001111, 011111, 111111 in test bench circuit shown in F i g . 5.10, respectively 120 5.2 Specifications of the implemented C L cells 147 A.1 Number of product terms in the coefficients of N BIC (s) and D ic{s) B . . . 180 G . 1 7 and p estimates and the resulting model errors for four different digital gates201 ix L i s t o f F i g u r e s 1.1 C U T and the current sensor 3 1.2 IDD dependence on the duration and beginning of the averaging window . . 6 2.1 Integrated circuit design and test 2.2 Integrated circuit test stages 18 2.3 Examples of faults due to local defects 20 2.4 Inductive fault analysis flow diagram 33 3.1 The proposed current monitor. 39 3.2 The block diagram of the current sensor 41 3.3 Current sensor circuit 44 3.4 A C model of a M O S transistor 45 3.5 Single-phase B I C I functional block diagram 48 3.6 Single-phase B I C I circuit schematic 50 3.7 Timing diagram and different waveforms in the B I C I circuit of F i g . 3.6 3.8 The transistor-level schematic of the integrator circuit 59 3.9 Schematic of the comparator 60 flow 3.10 ZBIC versus frequency 15 : . 52 62 x 3.11 I se IK IDD sen S transfer function for I D — 1 m A at the operating point ( A ' D s = 1/6) .63 3.12 VBIC versus IDD D C characteristics 3.13 Measurement and simulation results for ERR 64 versus IDD considering the parasitic resistances in the circuit 65 3.14 Current waveforms S P K 1 , S P K 2 , and S Q for validating the operation of the single-phase B I C I circuit 67 4.1 Double-phase B I C I functional block diagram 71 4.2 Quantization residue feed forward technique used in the A D C of doublephase B I C I 74 4.3 Current integrating circuit schematic 75 4.4 Timing diagram and different waveforms in the integrator circuit o f F i g . 4.3 77 4.5 Half-wave current integrating circuit schematic 79 4.6 The transistor-level schematic of the half-wave integrator circuit ( H C l ) . . . 84 4.7 Schematic of the comparator 85 4.8 Current waveforms for validating the operation of the integrator c i r c u i t . . . 87 5.1 (a) Measuring cycle-to-cycle or period jitter, (b) Measuring accumulative jitter using a reference clock, (c) Measuring relative jitter 91 5.2 B l o c k diagram of the proposed jitter measurement circuit 93 5.3 Time digitization using a delay chain 95 5.4 Time digitization using differential delay technique 97 5.5 B l o c k diagram of the proposed T D C circuit 99 5.6 Time digitization using two oscillator period difference method xi 102 5.7 Measurement range extension to (2 — 1)TA 106 5.8 KT f 109 5.9 Automatic resolution adjustment circuit k re interval selection circuit 112 5.10 C L cell evaluation test bench 116 5.11 Different C L cell styles: (al, bl, cl, dl, el) Circuits; (a2, b2, c2, d2, el) simplified models 117 5.12 Circuit for checking the necessary condition that TA > TB 123 5.13 Alternative circuit for checking the condition T 124 A 5.14 Circuit to generate r \ A + T2 < T < T A d B > TB f o r T A T B checker circuit . . . . . 125 5.15 Algorithms for selecting a and b in uniform load C L method, (a) exhaustive search, (b) directed search 127 5.16 Exhaustive search algorithms for selecting a and b in the 'incremental step' C L cell method 128 5.17 Semi-exhaustive search algorithm for selecting a and b in the 'incremental step' C L cell method 129 5.18 Fast search algorithm for selecting a and b in the 'incremental step' C L cell method 130 5.19 Jitter generator circuit 141 5.20 Cycle-to-cycle jitter measurement 143 5.21 Relative jitter measurement 145 5.22 Top block-level schematic of the jitter measurement circuit . 155 5.23 Implemented T Q circuit 156 5.24 T D C resolution adjustment simulation waveforms . . 157 xii 5.25 T D C measurement error for resolution of 34.1 ps 158 E.l The test bench for estimating the metastability window of a D flip-flop . . . 1 9 5 E.2 Simulation results of the flip-flop output for five different values of T E.3 Simulated clk-to-Q delay versus r p D . . . 196 196 G . 1 The test bench for validating the two parameter model for V^-induced gate delay variations G.2 200 The ring oscillator test bench to validate the two-parameter model for V dd induced gate delay variations G.3 202 Ring oscillator period jitter from simulation and the two-parameter model for Kw-induced gate delay variations, a ) / = l . 1 G H z , b)/=350 M H z , c)/=50 M H z , d)/=5 M H z , xiii 204 Claims of Originality C h a p t e r 3: A novel analytical method for obtaining the frequency response of a built-in current sensor (BICS). This analysis leads to closed-form equations for the frequency domain characteristics of the B I C S . IC Prototype measurement results for the B I C S . Such results leads to conclusions about the critical importance of the routing resistances in B I C S layout design. A novel single-phase built-in current integrator (BICI). Both the current integration technique and the circuit implementation are new. This design is small enough to reside on-chip, provides a digital signature, and is robust against process variations. C h a p t e r 4: A novel quantization residue feed forward technique. This technique prevents accumulation of A D C quantization noise which significantly enhances the accuracy of the B I C I . Using this technique leads to a new, double-phase B I C I which provides high accuracy for any power supply current waveform. C h a p t e r 5: A novel time quantizer (TQ) structure. This T Q structure achieves high resolution and high accuracy simultaneously. N e w resolution adjustment ( R A ) techniques for time interval measurement. techniques guarantee high resolution under process variations. xiv These A high-resolution time to digital converter ( T D C ) . The T D C uses the designed T Q and resolution adjustment circuits to measure time interval with high-resolution and accuracy. The design of this circuit is compatible with a conventional digital design flow. A jitter measurement circuit ( J M C ) . The J M C uses the designed T D C to perform highresolution and accuracy single-shot jitter measurement with resolution and accuracy of approximately 10 ps. A jitter generator circuit. This circuit performs digital phase modulation using only digital gates. It can be used for jitter tolerance testing of phase locked loops. A novel power supply noise-induced gate delay variation model. This model has only two fitting parameters and is used to show the immunity of the T Q to power supply noise. xv A c k n o w l e d g e m e n t s M y special thanks goes to Dr. Andre Ivanov, my supervisor, whose invaluable support and constant help, encouragement and guidance made this contribution possible. He has been a great source of inspiration and a role model to me not only in technical and educational sense but also in many aspects of life as a person. M a n y thanks also to my supervisory committee, specially Dr. M i k e Jackson, for reading my thesis carefully and giving me precious feedback which resulted i n great amount of improvement in both style and content of this thesis. I also thank M r . Yong Luo, M r . Zhurang Zhao for their help in testing the fabricated chips, writing 'vhdF codes and also for their feedback and interesting discussions about different circuits. M y thanks also to Mr. Farinam Farahmand and M r . Alireza Moshtaghi for writing the C A D tools which were used from time to time in the course of this research. I ' d like also to thank Micronet, P M C - S i e r r a for their financial support and C M C for providing design tools and access to fabrication facilities. Throughout the years of my Ph.D., so many family and friends have been great sources of motivation and inspiration to me which enabled me to complete this work. Thousands of thanks to all of them specially my loving parents and my wonderful sisters, Nasrin and Nooshin. xvi A n d , so many thanks to my fiancee, Mojgan, who understood, helped, and encouraged me during the intense and sometimes difficult months that I was busy writing this thesis. S A S S A N The University of British Columbia February 2000 xvii T A B A T A B A E I - Z A V A R E H To my loving parents xviii C h a p t e r M o t i v a t i o n s a n d 1 O v e r v i e w Testing is an integral part of the integrated circuit (IC) production which ensures the correct functionality of the final product shipped to the customer. Smaller geometry technologies, higher density [ 1], increased performance and implementation of different sub-systems (analog, digital, memory, micro-electro-mechanical systems ( M E M S ) , ...) on the same chip require new test methodologies. Without such methodologies, testing cost can become the major hurdle in the way of the future progress of I C production industries [2]. This work is an effort to provide effective test solutions for testing widely used mixedsignal circuits, more specifically phase-locked loop ( P L L ) circuits. Two different strategies have been developed for testing embedded mixed-signal circuits: power supply current testing and jitter testing. The first scheme can be used to test any analog and mixed-signal circuit, whereas the second one is more appropriate for timing circuits such as clock recovery, clock synthesis, and clock skew compensation circuitry, which are often P L L based. This chapter outlines the state of the art and motivations of the research reported in the rest of this thesis. Sec. 1.1 and 1.2 review the literature and the incentive for designing 1 the on-chip current monitor and jitter test circuits, respectively. A background of I C testing, and analog and mixed-signal test methodologies, including the definitions of the major concepts, is given in Chapter 2 for readers who are interested or do not have sufficient background in mixed-signal I C testing. 1.1 Built-in current monitoring The success of supply current monitoring in digital C M O S integrated circuits ( I D D Q testing) [3, 4, 5] has prompted researchers to investigate the feasibility of monitoring supply current (IDD) in analog circuits as a testing methodology [6, 7, 8, 9]. The results of these investigations suggest that IDD testing, although not sufficient by itself, can offer additional fault coverage for analog circuits. Often, IDD testing in analog circuits is based on measuring the average, rms, or the value of the current at specific times, and comparing these against a pre-defined tolerance range. If the measured value falls outside the associated fault-free tolerance range, the circuit is declared faulty [6, 7, 8]. Average IDD is a convenient and attractive test signature because it is a compact indicator of the current value over time. It also serves as a means of power monitoring when the supply voltage is constant [10]. Due to the lack of resolution of off-chip current sensors, parasitic currents of pads, and also fault masking effects (e.g., the I D of one block masking the faulty IDD of another D one), it is necessary to isolate the analog blocks in small groups, sense the supply current of each group using built-in current sensors (BICS), and average the associated chip [6]. 2 IDD'S on the 1.1.1 O n - c h i p current sensing A number of different B I C S ' s have been proposed for current monitoring. A l l these sensors insert a current sensing device [11, 12, 13, 14] or rely on the circuit intrinsic impedance in the IDD path [15], as shown in Fig. 1.1. A voltage drop across the sensing device (VBIC) Figure 1.1: C U T and the current sensor. results as IDD passes through it. Therefore, the circuit under test ( C U T ) supply voltage, VCUT, is: VCUT = VDD — VBIC Drawbacks of the VBIC (1-1) voltage drop include performance degradation of the C U T , i.e., ad- ditional delay and noise in the circuit [16]. VBIC can usually be expressed as: VBIC = V DC + Vj = V DC + f(I ) DD (1.2) where VDC a n d Vj are the IDD-independent and I -dependent DD components of VBIC, re- spectively, and / is the function relating Vj to IDD- VDC is often a D C voltage whose effect is the reduction of the C U T supply voltage. The Vi component of VBIC, to a first order, can be modeled by an impedance (ZBIC) The impact of VDC o n in the supply current path (as illustrated in F i g . 1.1). the operation of the C U T can be minimized by choosing small values of VDC and designing the C U T to operate with reduced supply voltage. ZBIC, however, can cause an unacceptable degradation in the C U T performance due to the induced noise, i.e., VBIC = ZBICIDD, resulting from IDD variations. Most current sensors proposed in the literature use a resistor or a M O S transistor b i ased in the triode region as the current sensing device. The voltage drop across the sensing device is used as the current value indicator. Such sensing devices trade sensitivity for i m pact on C U T performance. Designing for small values of Z ic B reduces the impact o f the sensor on the C U T performance by reducing VBIC variations [17], which in turn reduces the sensitivity of the sensor. In digital circuit I D D Q testing, high current sensor sensitivity is not required because the sensor only needs to distinguish two values of current which are typically at least one or more orders of magnitude apart [4]. In analog circuits, however, both a high sensitivity and a low Z ic B value are required for acceptable performance. The current sensor from [6] uses an N M O S transistor operating in the triode region for sensing IDD of embedded analog blocks. This sensor cannot provide a high sensitivity and a low ZBIC simultaneously. Even i f the sensitivity requirement is relaxed, the sensor needs a very large N M O S transistor (width ~ 1 m m — 10mm) to obtain an acceptably small ZBIC (e.g., lOfl to l f i ) . In [18], a low voltage current mirror based on a N M O S device and a buffer is used as the sensor. Although this design reduces VDC, it has two problems: (i) 4 VDC is process dependent and (ii) it does not reduce ZBIC- provides both a small ZBIC and a low process-insensitive The circuit proposed in [10] VDC- However, in [10] the ZBIC characteristics have not been analyzed. Such an analysis is essential to optimize the sensor's characteristics to achieve a low in a wide frequency range while minimizing the sensor ZBIC area. 1.1.2 On-chip current averaging The current sensed by a B I C sensor has to be integrated over a time window to obtain the average IDD current, I D as shown below: D TEE(T,t ) = i U b b+T b i (t)dt DD (1.3) where T and U are the duration and the starting time of the averaging time window. E q n . 1.3 indicates that by choosing a fixed averaging period T , averaging can be replaced with integration. In general, I D depends on T and tf,; for example, F i g . 1.2 shows how IDD varies D for three different selections of T and tb when IDD is a sinusoid with offset. This requires timing circuitry to synchronize the averaging operation with IDD- However, i f T is chosen such that T » IDD ~ IDD{DC) 1/BWi where where BWi IDD(DC) is the IDD is the bandwidth of IDD A C component, then D C component which is independent of T or h. Therefore, to avoid the need for synchronizing circuitry, averaging should be performed over a long period of time, e.g., T = 100/BWi. This condition results in long averaging windows in the range of a few tens of milliseconds for circuits such as audio frequency filters in which BWi ~ 4 kHz. 5 ( ) mA 'DD 1.50.5 f (ms) 2 l^=g(i; ,t,)=i+(2/3K) ~i ~ = 9(T ,t )=1 D D 2 1 + (2/7K) Figure 1.2: IDD dependence on the duration and beginning of the averaging window A simple method of integrating IDD is to pass it through a capacitor; the voltage stored across the capacitor at the end of the integration window w i l l be proportional to IDD [10], (1.4) Using this method may require a large capacitor. For example, assuming a supply voltage of 3.3V, an IDD — 100 fiA and T = 1 msec, a 30 nF capacitor would be required to ensure that Vc < VDD during integration, and therefore the electronics providing the current to the capacitor do not saturate. Such a large capacitor would obviously not be able to reside on-chip. In [19] a capacitor connected between Vss and VDD terminals of the C U T , and the power supply is switched periodically to estimate the C U T power consumption. This estimate also provides an indirect estimate of IDD- This method, however, does not measure IDD directly and also requires a large capacitor. Therefore, an on-chip bus or multiplexer is 6 needed to direct the IDD from different analog blocks on the chip to an output pin. In addition to requiring an extra pin, the bus and pad parasitics reduce IDD measurement accuracy. 1.2 P L L testing A n example of a widely used class of circuits requiring functional testing is phase-locked loops ( P L L ) , since most structural test methods are either too intrusive (affect the performance) or provide poor correlation to important P L L specifications such as jitter. P L L testing has gained significant interest recently due to the widespread integration of P L L s in mixed-signal communications and data processing ICs. P L L s are used in timing applications such as clock synthesis, clock recovery, and clock skew compensation. In such applications, the single most important set of specifications for a P L L is its jitter characteristics, such as intrinsic jitter, jitter transfer function, and jitter tolerance[20]. In fact, jitter specifications are critical in most high-speed interfaces because of a limited available timing budget. Jitter testing, however, is an expensive test because it requires costly equipment and long test time [21 ]. A number of authors have tried to find cost-effective test methods for P L L s [22, 23, 8 , 2 4 , 2 5 , 2 6 , 2 7 , 2 8 , 2 9 , 3 0 , 31,32]. Works in [22] suggests partial specification testing such as lock range, lock time, and power supply current for P L L testing. Dalmia et al. [8, 29] also show the viability of power supply current monitoring for P L L testing. The authors of [24, 25] propose methods for efficient fault simulation of P L L s and suggest lock frequency range measurement for P L L testing. Although a combination of these techniques seems to provide a good fault coverage, it is difficult to correlate the test results to important jitter specifications, partly because simulating jitter for fault-free and faulty circuits is extremely 7 difficult due to a lack of tools capable of simulating noise in non-linear dynamic circuits. Azias et al. [26] proposes a reconfiguration technique for testing ring oscillator-based P L L s . This technique has the advantage of being compatible with digital test methods, but it requires reconfiguring sensitive parts of a P L L . Also, it exhibits the problem of unknown correlation of test results and functional specifications. A practical solution to P L L testing is to directly measure the jitter characteristics of the P L L s on the chip. The following section reports major methods for on-chip jitter testing. 1.2.1 Jitter testing Jitter testing often requires jitter measurement. Jitter measurement techniques are divided into two categories: frequency domain and time domain. Historically, spectrum-based techniques have been used more often because of the availability of high-frequency spectrum analyzers [33, 21]. The drawback of this method is that the amplitude distortion and noise degrade the measurement accuracy. Also, this method is not suitable for on-chip measurement because performing high-resolution spectrum analysis on the chip requires a significant amount of design time and silicon area. In the time domain, jitter measurement can be performed using modulation domain analysis [34], histogram-based [21] or undersampling [21] techniques. In [30], a B I S T circuit is proposed which is capable of measuring lock range and loop gain of a P L L in addition to performing a jitter test. Because of its statistical nature and dependence on bit error rate ( B E R ) , the application of the jitter testing approach in [30] is limited primarily to clock recovery P L L s . A l s o , high-resolution measurement requires generation of precise, high-resolution and stable delays. Two U S patents in [27] and [28] outline on-chip jitter 8 measurement techniques for P L L testing. The B I S T circuits proposed in these patents are mixed-signal and their resolution is limited to one gate delay, which is inadequate for testing high-speed P L L s . In [31], a jitter transfer function measurement circuit is proposed for P L L testing; however the jitter measurement circuit proposed does not have sufficient resolution for intrinsic jitter testing. Veillette et al. [32] proposes an interesting method for generating jitter at the input of the P L L for jitter transfer testing. This method, however, requires reconfiguration of the feedback in the P L L loop, which could affect the performance of the loop. Since most of the time domain techniques require some sort of time interval measurement, on-chip accurate jitter measurement necessitates high resolution on-chip time measurement circuitry. For on-chip time interval measurement, a number of time-to-digital converters ( T D C ) circuits, used in physics experiments, have been proposed in the literature [35, 36, 37, 38, 39]. Such circuits, however, are mixed-signal, require custom design and layout, occupy a large area, do not provide high resolution, or rely heavily on matching of the elements. The idea of a controlled delay line used in T D C s is also used as an on-chip jitter measurement method in [27]. This circuit, however, is mixed-signal and suffers from the same limitations as most T D C s . 1.3 Motivationsand Contributions Although power supply current testing is proposed as an attractive structural testing method for mixed-signal circuits, it has limited applicability due to the lack of a practical B I C M scheme. Two issues have to be addressed in an effective B I C M : 9 1. The current has to be sensed with high resolution without introducing large impedance in t h e p a t h 2. The IDD signature has to be digital and accurate. In addition, it has to be generated without requiring large chip area These requirements led to the design o f a B I C M reported in Chapter 3. This B I C M is capable of sensing IDD without introducing significant impedance in the power supply current path. It averages the current and generates a digital signature. Since the circuits are compact and easy to design, they are suitable for B I S T and D F T applications. The circuits can provide an rms error less than 2% i f the IDD contains significant A C components which are uncorrelated with the system clock. A s another contribution of this thesis, a double-phase built-in current integrator is reported in Chapter 4. This integrator occupies slightly larger area than the single-phase integrator introduced in Chapter 3, but it can measure the average current with an rms accuracy of 1% for any current waveform. The design of on-chip jitter test circuit was undertaken because the effectiveness of structural tests or non-jitter based partial specification tests can not be proven, and also existing external jitter testing methods are costly, i f possible at all. A t the start of this effort, there was no solution for high-precision on-chip jitter testing. Even today, the new high-precision on-chip jitter testing technique by Logic Vision, Inc. [30] is based on bit-error-rate whose application is limited to clock-recovery P L L s . Another recent technique has been announced by Fluence Technology, Inc. , but no information is available in the public domain about the 1 specifics of the technique. For a practical and widely applicable jitter B I S T solution, we set 'See the VCOBIST data sheets at http://www.opmaxx.com/products/products.htm 10 the following objectives for the jitter measurement circuit: 1. Single-shot jitter measurements (similar to those performed by an external equipment). This is to make the test solution independent of the circuit under test 2. Compatibility with digital design flow 3. Ability to generate digital signatures 4. High-resolution and precision (better than 10 ps in a 0.35^ra technology) The search for on-chip jitter test solutions resulted in the novel jitter measurement and generation circuit for B I S T of P L L s which is presented in Chapter 5. The circuit satisfies all the conditions for a practical B I S T circuit mentioned in Sec. 2.2.4 as well as the objectives mentioned above. The measurement circuit is fully digital and automatically synthesizable, occupies an area equivalent to 1200 2-input N A N D gate, provides a resolution of approximately 10 ps (~ 1/5 of a gate delay in a standard 0.35 /j,m technology) and a precision of 11 ps, and generates a digital signature which can be read out by an inexpensive tester. The digital signature can be further analyzed by the tester to obtain the jitter characteristics. In addition to the circuit structures, a number of design and analysis techniques have been employed in these designs which have wider applications. These techniques are: 1. The approximation technique used in Appendix A to obtain a closed form for the frequency response of the B I C S 2. The noise feed-forward technique presented in Chapter 4, which is an effective method for quantization noise reduction in averaging analog to digital converters 11 3. The differential method used for jitter measurement which provides power supply noise rejection. This property proved in Appendix H makes such architecture a strong candidate for a multitude of high-precision timing circuits 4. The VDD -induced modeling of gate delay variation presented in Appendix G . This model can be used for estimating the effect of power supply noise on digital circuits 12 C h a p t e r B a c k g r o u n d A n d 2 S u r v e y Today's electronic integrated circuits are extremely complex and dense. N e w technologies allow multi-million transistors [1] and mixed-signal circuitry on the same chip. This progress has led to the design of integrated circuits possessing an unprecedented functionality with the expectation that this trend w i l l continue. A s the complexity of integrated circuits increases, I C manufacturers face many new challenges, one of which is developing effective test solutions for ICs. This chapter provides the background, terminology, and principles often used in the field of I C testing. Sec. 2.1 reviews major concepts and the terminology used in I C testing. Sec. 2.2 reports the major issues encountered and techniques developed for testing mixedsignal circuits in more detail. Sec. 2.3 concludes this chapter by summarizing the important concepts and describing some active research areas in the field of mixed-signal testing. i 13 2.1 I C Testing The typical I C design flow starts with a concept which leads to a set of functionalities and specifications. After that, an appropriate technology is selected which is believed to yield the required performance. Using the appropriate technology models, the specifications are mapped to an implementable design, which is analyzed and simulated to ensure that the design satisfies all the requirements. Subsequently, some prototype ICs are fabricated, characterized and diagnosed thoroughly to determine i f the device meets all its specifications under the given process variations. The design and/or fabrication process is corrected according to the results before the IC is sent for production (Fig. 2.1) [40]. In the last stage of production flow, each fabricated device undergoes a series of tests before it is shipped to the customers. Some tests are performed on the wafer before cutting the dies (wafer test), and more extensive tests are run on the packaged devices (final test). Since time-to-market is a critical factor in the success of an electronic product, the test procedures are often devised parallel to design verification and prototype characterization, and automatic test equipment (ATE) programs are developed before the first batch of devices is fabricated. This section reviews the major concepts in the field of I C testing. First, in Sec.2.1.1, the fundamental question as to why ICs must be tested is addressed. Then, a definition of test and the difference between test and its close relative, diagnosis, is presented in Sec. 2.1.2. The major test disciplines, functional and structural testing, are defined and compared in Sec. 2.1.3. Often, regardless of the test discipline selected, the concepts of defect and fault are used to generate or evaluate different test methodologies. These concepts are reviewed in Sec. 2.1.4. They are also used in Sec. 2.1.5 to briefly describe the two general test gen- 14 Concept and circuit specification Circuit design and analysis Fabrication parameters Simulation and Design verification Test development ^Prototype fabrication Extensive test and diagnosis \Jjyield prediction)J Figure 2.1: Integrated circuit design and test flow 15 eration methodologies, automatic and ad-hoc. Next, in Sec. 2.1.6, Design-for-testability (DFT), built-in self-test (BIST) and the embedded test concepts are defined. These techniques are used when it is difficult to generate or apply the test to the circuit under test. F i nally, a very brief review of major test methodologies for digital circuit testing is presented in Sec. 2.1.7 since many of the basic ideas have also found their way into the mixed-signal test domain. 2.1.1 W h y test i n t e g r a t e d c i r c u i t s ? If a device functions properly under the nominal variations of a fabrication line, why is there a need to test each device at the end of the line? The answer lies in the imperfections of the fabrication line. These imperfections result in some random failures at various stages of the line; e.g., mask misalignments, missing or extra metal, polysilicon or oxide due to spot defects and cracks [40]. Some experts believe that these failures can be avoided by improving the fabrication line, and subsequently increasing the yield to about 100%. Assuming this opinion to be theoretically correct, the need for testing is still unavoidable because 1. fabrication line improvement would require resources that may not be justified by the resulting increase in yield. This becomes especially true for the devices with short product life times; 2. as fabrication line technology improves, industry demands smaller device geometries and more masking stages which drive the yield down; therefore, the need for testing. In reality, almost all I C manufacturers test (in-house or outsource to test houses) their final products to bridge the gap between the fabrication imperfections and their customer's expected quality [2]. 16 In some applications such as aviation systems, military equipment, and deep space systems, where correct functionality can be life-critical, the test quality is the important factor and the cost is a secondary concern. However, in commercial and consumer applications, the test choice depends on the trade-off between test quality and test cost. For today's complex chips the test cost can account for 30% of the total cost of the product [41], and may even surpass the cost of manufacturing in near future [2]. A s a result, industry has focused on finding efficient ways of testing circuits and systems to increase the quality to cost ratio. In addition to quality assurance, testing is sometimes used as a critical tool to locate and diagnose failures and to take corrective measures where possible. However, there are distinctions between test and diagnosis which are described next. 2.1.2 Test a n d diagnosis In general, testing is the process of identifying a faulty device, while diagnosis is the procedure of locating the source of the malfunction. A s shown in F i g . 2.1, during early production stages of a design, extensive diagnosis procedures are run on the samples of the device in order to locate the most frequent faults i n the circuit and improve the design or the production line in order to achieve an acceptable yield. When the device is approved for mass production, each device undergoes two stages of electrical testing. The first one is called wafer probe and is performed prior to packaging (Fig. 2.2). A t this stage thin probes are used to apply and monitor signals at various nodes of the circuit. Devices declared faulty at this stage are discarded in order to save the high cost associated with packaging a faulty device. Furthermore, there are a number of non-electrical test and quality control procedures that can be used at this stage such as optical, infrared, scanning microscopy, and thermal 17 imaging analysis [42]. Figure 2.2: Integrated circuit test stages. Since packaging can introduce some faults [40, Chapter 16], and also because of the difficulty in applying high-performance tests on the wafer, a second test, called final test, is run on the device. Since there is no direct access to the internal nodes of the device during the final test, the test must determine the status of the chip using only package pins. In each electrical testing step (wafer probe and final test), different approaches to test development can be chosen. These are generally divided into two groups: functional and structural. These two approaches are described in the next section. 2.1.3 F u n c t i o n a l versus structural testing Functional testing is defined as testing the conformance of the functionality of a circuit to its specifications. Historically, this type of testing has been the method most commonly used, but as the functionality of chips increased, such testing became costly and in many cases impossible. For example, for a combinational logic circuit with 64 inputs with a testing 18 speed of 10 patterns per second, it can take 5849 years to test the complete functionality of 8 the chip! In other circuits such as complex analog or mixed-signal circuits, the functional testing would require a large amount of time and resources, translating into higher cost per device. Another approach is to assume that a well-designed and analyzed circuit which has been thoroughly debugged, i.e., all systematic or design errors have been eliminated prior to sending it for fabrication, w i l l meet its specifications except when there is a fault in the circuit due to physical defects. Therefore, after identifying and modeling the possible faults in the circuit, the test procedure tries to determine their existence or absence. Should a fault be detected, the device is declared faulty and is discarded. This approach, called structural testing, is expected to achieve a more efficient outcome. But is this expectation reasonable? A supportive argument is that different functional specifications of a system are correlated, i.e., i f a defect exists in the circuit, it w i l l most likely affect several circuit specifications. This notion implies that functional testing might be overkill, and detecting faults in the system would require less effort. This can be compared to data compression in which the key to compression is to transform highly correlated data to a set of uncorrelated data which carries the same information. The next section provides the definition of defect and fault which are used to generate tests and also measure the quality of a test. 2.1.4 Defects a n d faults A defect usually refers to physical failures in a circuit, while a fault is the dysfunctional electrical effect of the defect on the operation of the circuit. In a defect-oriented test method- 19 a) A dust particle can cause open fault c) Short fault b) Thinning of metal or polysilicon can create large resistance between two nodes. Figure 2.3: Examples of faults due to local defects ology, to devise or evaluate a test strategy for a circuit, fault models based on the possible defects are first chosen, and then a test methodology is selected to detect the modeled faults. The faulty circuit is simulated to ascertain whether the selected test can detect the fault. The percentage of faults detected by a test is one measure of the test quality. The effects of different defects are technology-dependent. M u c h research has focused on identifying and modeling defects in different technologies. For example, a missing oxide could cause a gate-substrate short in a C M O S transistor. Some of the common defects in most technologies include missing or extra oxide, metal, or polysilicon, and inaccuracy in the etching or doping processes. The electrical consequences of these defects include opens, shorts, as well as significant stray elements and large deviations in component values. Examples of shorts and opens due to spot defects are shown in F i g . 2.3.. Hnatek [40] reviews possible physical defects and their sources at each stage of the fabrication process in detail. 20 Faults are not always mapped directly to defects. In fact, sometimes faults are defined at higher levels of abstraction because of advantages such as the ease of test generation (e.g., stuck-at fault model [43, Sec. 4.5]) and tight connection to performance parameters (e.g., performance-dependent faults [44]). 2.1.5 Test generation Fault models are often used to generate test strategies. To detect a fault, the fault should be activated by a set of inputs that cause a significant deviation i n a circuit output parameter from its nominal value i n the presence of the fault. To activate the fault, it should be both controllable, i.e., the fault-free and faulty status of the area affected by the fault are significantly different, and observable, i.e., the outputs reflect the change in the expected behavior of the faulty area. There are two methods used i n test pattern generation: 1. Automatic test pattern generation (ATPG) algorithms. Examples are A T P G algorithms for combinational digital circuits [43, Chapter 6] [45] 2. A d hoc methods. This methods are applicable to specific circuits The A T P G methods cannot be used easily for generating test patterns for some circuits, e.g., analog circuits, because the interaction of the signals at different nodes is too complex. A n ad hoc approach used in these cases is to consider an input pattern and simulate the faulty circuit to determine whether the selected pattern can activate the fault. Fault simulation requires simulating the circuit under different faulty conditions and input signals. Simulations in low levels of abstraction (circuit level) for large circuits are computationally prohibitive. This problem is alleviated by modeling the circuit at higher levels o f abstraction. 21 Sensitivity analysis [46] has been also proposed as a test generation method. This method is regarded as a fast substitute for fault simulation because it can help to identify appropriate test stimulus in the possible space of stimulus. Functional testing is also an ad hoc method as it is circuit specific. Once the test input stimulus has been identified, the test is exercised on each chip by applying the stimulus to the circuit and observing the outputs with a tester. However, in some cases, applying a test to a circuit with an external tester does not suffice or is not possible; in such cases, other methods are used such as design for testability ( D F T ) , builtin-self-test (BIST), and Embedded Test, which are explained next. 2.1.6 D e s i g n for testability ( D F T ) , built-in-self-test ( B I S T ) , a n d embedd e d test In many high-density devices it may be extremely difficult to generate the test pattern for a fault using only primary inputs and observing outputs. In such cases, additional circuitry or techniques can increase the testability of the circuit significantly. M a n y manufacturers, realizing the importance of testing and the cost involved, include these test circuits on their devices as a means of decreasing test expenses, and, as a result, cost per device. There are two main categories of D F T methods: general purpose, and ad hoc methods. D F T can mean adding some additional circuitry or modifying the C U T to increase the accessibility of internal nodes of a device, or can be as complete as a built-in-self-test (BIST) scheme. Perhaps, the best example of a standard D F T method is scan chain in sequential digital circuits [43, Sec. 9.4]. In a B I S T scheme, the device under test ( D U T ) is switched to test mode, in which after a specified time required for completion of the test operation 22 in the chip, a flag indicates whether the D U T is faulty or not. B I S T for digital technology has been well investigated and is widely used in cases such as memory testing. Some of the advantages of B I S T are as follows: 1. It eliminates the need for expensive test equipment. A s technology improves and circuits with higher speeds and increased functionality are designed, the test equipment has to be upgraded correspondingly, adding to the testing cost 2. A large number of chips can be tested simultaneously, resulting in cost reduction 3. Tests can be performed on-site repeatedly. Therefore, i f the customer needs, he/she can run a field test on the chip under his/her required conditions 4. It provides automatic and fast diagnosis which reduces time-to-market considerably [47] B I S T can be viewed as moving the tester into the chip. Inclusion of a full B I S T in present day mixed chips (containing analog macros, memory, M E M S and digital circuit) may not be practical due to the area overhead. A n alternative approach is to move part of the tester to the chip and leave the rest to external equipment. Such an approach is called Embedded Test. Usually embedded test circuits are designed to perform very high speed tests which are difficult to perform because of the gap between external and internal bandwidth [2]. A s the chip complexity and performance increases and access to internal circuits and embedded blocks is reduced, embedded test becomes more and more necessary. 23 2.1.7 Digital circuit testing Digital circuit testing is a relatively mature field, and today, A T P G tools are able to generate efficient test patterns for digital circuits. The key to the success of these tools is the existence of efficient fault models, fault simulators for digital circuits and A T P G algorithms. In a combinational digital circuit, any logic node can have one of two logical values. The status of a logic node depends on the inputs to the circuit. It can be assumed there is a fault in the circuit i f a logic node does not change according to the design, or changes too late or too quickly. Consequently, stuck-at and delay faults models have been proposed for digital circuits [43, Chapter 4]. In a stuck-at fault model, it is assumed that a faulty logic node is stuck at one of the logic values ( stuck-at-1 and stuck-at-0 ) and does not change when it is supposed to. B y applying proper patterns to the inputs, a stuck-at-u (v = 0,1) fault can be activated to v (controllability) and observed as a discrepancy between obtained and expected outputs (observability). To detect a delay fault, at least two patterns are needed. Sequential circuits contain memory elements. Therefore, the outputs depend not only on the circuit inputs, but also on the current state of the system, which is a function of previous inputs and states. Forcing the circuit to a known state and then applying a specific input is a challenging problem. Two alternate methods which are sometimes used to test sequential circuits are Scan Path and Crosscheck [48]. The idea of the scan path method is to divide the circuit into two parts in test mode; a combinational block and a serial shift register containing all the flip-flops in the circuit. Test patterns for the combinational part can be generated using A T P G . Entering a sequence o f l ' s and O's from one end of the test shift register and reading it from the other end can determine whether any of the flip-flops in the 24 chain are faulty. In the Crosscheck method some circuitry is added to each logic block of the device so that those blocks are accessible through external pins. Therefore, each logic block including flip flops can be accessed, initialized, and probed directly. Test strategies based on these models have proven sufficient for most applications, although there are defects which the voltage-based test strategies do not cover. Additional test such as I D D Q testing is needed [49, 50] for these defects. I D D Q testing Using the quiescent supply current (IDDQ) as a testing parameter for C M O S circuits has be- come increasingly popular, mostly because it is simple and effective [3] [4]. Research shows that for some faults, the D U T draws significantly more (or less) current from its power supply than the nominal value. Therefore, many faults can be detected by monitoring I DD for specific inputs. I D D Q testing is an example of massive observability because for each i n put pattern, a large number of faults can be detected by monitoring IDDQ • In fact, some researchers claim that there are some types of defects that only I D D Q testing detects because they do not alter the functionality of the D U T , but the chip is still faulty because it draws an excessive amount of current [49]. This may lead to reliability problems. In order to detect a defect by I D D Q testing, it should be activated by an input pattern. Currently, A T P G tools are able to generate I D D Q testing patterns for digital circuits. Although there is a conjecture that these techniques could also be used to test analog circuits, not much research has been done in this area. 25 2.2 Analog and Mixed-Signal Testing The art of testing of analog circuits, unlike its digital counterparts is far from maturity. Most test engineers use ad hoc approaches that do not represent a unified test generation methodology applicable to all analog circuits. Functional testing is still widely used to test these circuits, but as the technology of mixed-signal and analog V L S I circuits progress, the cost of thorough functional testing becomes increasingly prohibitive. Currently, industry is facing serious issues with respect to testing analog and mixed-signal circuits, and it is calling for solutions to this matter, which in some cases has become a bottleneck for manufacturers. This section reviews the major developments in analog and mixed-signal testing to date. Analog circuits are different from digital circuits in their operation. The input and output signals of an analog circuit are continuous waveforms, and since internal components do not work as switches, their values and characteristics become more important in the operation of the circuit. Digital D F T methods based on partitioning the circuit are often not applicable in the case of analog circuits due to negative impact of D F T circuitry on the performance of the circuit. Also, for many circuits expressing the outputs in an analog circuit in terms of inputs and element values cannot be formulated in a generic form applicable in faulty conditions. The lack of effective fault models in higher levels of abstraction is one of the most important problems in analog testing. Simulating or analyzing an analog circuit at the circuit level is lengthy and computationally expensive. Proposed fault models in analog circuits are basically of two types: 1. h a r d o r catastrophic faults, including shorts and opens. Shorts can be capacitive or resistive. These faults can change the topology of the circuit, posing a problem in 26 using topology methods for analog testing and diagnosis. 2. Soft o r parametric faults including some variations in element values for which some functional parameters of the circuit are affected significantly. Catastrophic faults generally degrade the performance of the system significantly and can be detected by simple tests. For soft faults a decision has to be made regarding the amount of element value variation which is considered faulty. This is a difficult problem, especially when multiple fault models are included. 2.2.1 History Research on test and diagnosis of analog circuit testing started in the 1970's, almost one decade after digital testing had attracted attention. A number of reasons have been given for this late start [51]. Analog circuits were still largely discrete and relatively small, therefore, functional testing was possible. Consequently, there was no industrial motive to pursue research in this area. The other reason was the lack of any major breakthrough in the academic research [51]. Since the 1970's, there have been some important results achieved largely in the area of diagnosis of linear circuits. Today's modern analog circuits are mostly non-linear, or become non-linear under faulty conditions. Some researchers have attempted to extend the linear methods to non-linear problems with some degree of success. Some of the efforts in the area of analog fault diagnosis are as follows: Post measurement simulations o r simulation after test ( S A T ) : Assuming a certain circuit connectivity, this method tries to solve for the element values using the voltage and currents of accessible nodes and branches, and therefore, determine which component 27 in the circuit is faulty. Berkowitz [52] initiated the subject of solvability of a network based on knowing the currents and voltages in a circuit. Trick et al. [53], and Navid et al. [54], provide some necessary and sufficient conditions for the solvability of a network and i n troduce algorithms for efficient element value computation. They investigate linear circuits using a single-frequency measurement. Navid et al. suggest their scheme could be used for non-linear circuits by linearizing them around the operating points. Since then, a number of papers on different linear and non-linear methods suggested for fault diagnosis have followed using methods such as multi-frequency measurements [55], element modulation [56], neural networks [57], and artificial intelligence-based techniques [51, Chapter 7]. Piecewise linear ( P W L ) modeling of non-linear elements is one of the approaches suggested for nonlinear analog fault diagnosis[51]. Estimation methods is also a S A T category. These schemes, using some estimation algorithms such as least square criteria, try to estimate circuit element values by minimizing the error between nominal and measured values. Statistical methods have also been used to select test parameters[58]. S i m u l a t i o n before test: In this method, a fault dictionary (FD) is formed through determining the response of the circuit to a set of stimuli in the presence of some specified faults. The faults can be isolated by matching the measured values to the closest set of responses in the dictionary. Schreiber [59] proposes an algorithm based on state space analysis to design an efficient stimulus for the fault dictionary. The accuracy of this method depends on the accuracy of the fault dictionary. Depending on how the F D is formed, some processing of measured values may be necessary; for example, the transient response of the circuit may have to be estimated. 28 Some research has focused on efficient stimulus design, by which a fault can be located with minimal measurement points and computation. Multi-frequency measurements [55] and element modulation techniques [56] provide examples of such efforts. 2.2.2 Testing analog circuits With the advent of analog V L S I circuits and mixed-signal technology, the field of test development for analog circuits gained significant momentum. In recent years much research has been devoted to exploring and solving the analog testing problems. This section reviews some of these efforts. Test optimization Every second of test on the tester adds to the cost of the device. Testing cost for some dense and complex ICs is estimated to account for up to 30% of the total manufacturing cost. Therefore it is imperative to minimize the testing time by optimizing the test strategy. M i l o r et al. [41] introduce an algorithm for this optimization. Using the statistics of defects and faults, and the time associated with each test, their algorithm tries to minimize the test time by selecting and ordering the best set of tests. Using this algorithm, only the specifications of the device that provide maximum fault coverage in minimal time are tested. F a u l t simulation In the case of analog circuits, fault simulation is one method of test pattern generation. After forming a fault list, the circuit is simulated under faulty conditions to determine whether a specific parameter (test parameter) varies beyond its specified tolerance. The input signals 29 used in fault simulation are chosen to make the test parameter observable. Analog circuit simulation is computationally intensive, and simulating a large circuit for a large number of faults can be quite lengthy and almost impossible. A number of attempts have been made to model analog circuits at higher levels of abstraction to decrease the simulation time [60]. Nagi et al. [61], suggest a solution for linear circuits by transforming the circuit to the s and then z-domain. This approach is limited because it applies only to linear circuits, and also assumes that the faulty circuit remains linear as well. Macromodeling is another approach to analog circuit modeling in which the circuit is divided into behavioral blocks and then a circuit simulator such as S P I C E or S P E C T R E is used to simulate the system. This method decreases simulation time by lumping the effect of a number of circuit level elements into a behavioral block. These blocks should be selected such that the circuit level defects can be easily incorporated in them for fault simulation. Harvey et al. use a macromodeling technique in the fault simulation of a P L L circuit [22] and a current mode A D C [62]. Spinks, et al. [63] review some of the major works in this area. Sensitivity analysis One method used to determine an efficient set of test parameters is using sensitivity analysis. In this method the sensitivity of each output parameter to each circuit element is used to select an optimum test set. The test set stimulus and test parameters are chosen for maximum observability and controllability of the modeled faults. Slamani and Kaminska[46] analyze this scheme and suggest an algorithm to optimize the test set for maximum coverage. Their study includes single and multiple fault model cases, and concludes that as the number of 30 faults in multiple fault model increases, testing approaches diagnosis. Although promising, sensitivity analysis is mostly applicable to linear or near-linear circuits. D C and A C tests Different parameters of an analog circuit can be tested. A D C test is an attractive option due to its simplicity. In a D C test, D C operating points of the circuit are tested for a set of D C inputs. This test generally offers good fault coverage for catastrophic faults and is suitable at the wafer test stage. Soma [64] suggests that some open circuit faults cannot be detected by a D C test. Also, capacitive faults escape detection in a D C test. Bishop et al. [65, 66] evaluate fault coverage of D C tests for two common classes of analog circuits, operational amplifiers and operational transconductance amplifiers (OTAs), and conclude that up to 80% of catastrophic faults in these circuits can be detected. Sometimes A C tests are used to achieve higher fault coverage. In the A C case, single or multi-tone signals can be used. Multi-tone signals are especially useful in testing linear analog circuits such as filters because the sensitivities of output parameters vary with frequency. Using a multi-tone signal can help to detect more faults in one test. Inductive fault analysis (IFA) In forming a fault list for a C U T , it is important to select realistic faults to avoid testing for defects that are rare or nonexistent. Such a realistic fault list can be created by using the i n formation on the process variations and possible physical defects. This list also depends on the layout of the circuit. This approach is viewed as more practical. F i g . 2.4 shows different stages of inductive fault analysis test generation method. Currently some tools capable of 31 inserting defects on the layout and generating a fault list [67] [68] exist. Although global defects due to some process failure do occur, mostly spot defects (local defects) are considered because the probability of global defects is low, and in general, detecting them is easy. In a typical single-poly, double-metal C M O S process, some common spot defects include ([40]) 1. short between wires; 2. open in wires; 3. pin holes in oxide, gate oxide, pn junctions; 4. missing contacts or vias; and, 5. extra contacts or vias. The appropriate fault model for each defect depends on the condition of the defects and the processing technology. For example, a wire short can be low or high resistance depending on the amount of metal connecting the wires (Fig. 2.3). Defect statistics can also be used to optimize the test. I F A has been the focus of some recent papers. It has been suggested as a means of evaluating test strategies such as functional testing [69]. Harvey, et al. use it to generate and evaluate different tests on circuits such as an A D C [62] and a P L L [22]. Sachdev [70] applies it to a class A B amplifier, and X i n g [71] uses it to improve fault coverage for an air-bag control circuit. Sachdev in [72] gives an overview of IFA. 32 Realistic fault list extracted from the layout and technology information A n a l o g fault modeling A n a l o g fault simulation Test generation Figure 2.4: Inductive fault analysis flow diagram. 33 2.2.3 Analog and mixed-signal D F T Some D F T schemes have been proposed to improve the testability of analog circuits by i n creasing the observability of internal nodes of the circuit. Sunter [73] introduces a wideband analog test bus circuit which can be used for monitoring internal analog signals. Soma [74] exploits the serial structure of active filters and adds some switches to the circuit making it possible to test individual internal blocks. Slamani and Kaminska [75] suggest using parameter to D C converters. These on-chip converters produce a D C voltage which is a function of an internal parameter, and a comparator determines whether this voltage is within the acceptable range. This information is stored in a shift register and can be used to test and diagnose the device. Wey [76] and Wurtz [77] propose B I S T structures for analog circuits which are in fact, the analog shift register ( A S R ) . Taps (inputs of different stages) of this shift register are connected to different nodes in the circuit and by clocking it, the internal voltages of the circuit can be accessed. The authors of [76] also propose a current-based A S R which can alleviate the problem of limited voltage swing in a voltage-based A S R . One of the problems with Slamani and Wey's methods is that the D F T (although the authors call it B I S T ) circuit can be comparable to the C U T in terms of chip area. In such cases, using these methods cannot be justified. x Another mixed-signal D F T method for solving problems with controllability and observability of embedded blocks is using an analog test bus. These efforts have led to a new standard: IEEE1149.4 mixed-signal test bus [78]. This standard is aimed at solving the problem of analog access and also is a means of extending the digital boundary scan standard IEEE1149.1 to full board-level connectivity test as well as testing on-board discrete passive components. Some implementation issues regarding the standard have been 34 addressed in [79, 80]. 2.2.4 Mixed-signal BIST Submicron mixed analog and digital technologies have enabled I C manufacturers to achieve high levels of integration, making system-on-chip a reality. One of the consequences, however, is difficulty in testing embedded analog and mixed-signal blocks because of: (i) limited access to these blocks, and (ii) the long time and expensive equipment needed for specificationbased testing. To solve the first challenge, on-chip D F T techniques such as internal buses have been proposed to increase the access to embedded blocks. Structural testing has been suggested to address the second problem by replacing expensive specification tests with less costly ones. Although structural testing has been partially successful, specification testing in many cases is often seen as necessary. This is mostly due to the existence of soft faults, lack of proper fault models, and poor correlation between structural tests and specifications. To reduce the cost of functional testing, one solution is to use design for test ( D F T ) and built-in self test (BIST) techniques to reduce the test time and also the cost of test equipment needed. A practical D F T or B I S T method has to satisfy several conditions; it must 1. occupy small area in comparison with the C U T ; 2. be easy to design (preferably automatically synthesizable); 3. be sufficiently accurate for targeted tests; 4. generate a signature which can be analyzed conveniently on-chip or off-chip, such as a string of digital numbers. 35 The analog and mixed-signal B I S T proposed in the literature can be divided to two groups: the general ones, which are. applicable to a large class of circuits, and the more specific ones, which are used for limited classes of circuits such as active filters, switchedcapacitor op-amps, A D C / D A C and P L L . Roberts et al. proposed mixed-signal B I S T ( M A D B I S T ) which is primarily based on generating single- and multi-tone sine waveforms on the chip using an over-sampling oscillator [81, 82]. They have applied their method for testing sigma-delta analog to digital converters [83] and a wireless communication system [84]. This method, although very attractive for on-chip signal generation, is limited to cases where spectrum-based testing is possible and also requires on-chip digital signal processing capability for response analysis. On-chip sine generation is also used in [85]. However, a large portion of circuits proposed in [85] are analog, and therefore prone to process variations and also occupy large chip area. Another B I S T approach proposed by Arabi et al. is oscillation-based B I S T (O-BIST) [86, 87, 88, 89,90]. This method is based on modifying the C U T or adding some amount of circuitry on the chip to turn the C U T to an oscillator in test mode. Since oscillation parameters such as frequency and amplitude are functions of C U T parameters, O - B I S T can detect many faults. Although effective is some cases, O - B I S T is basically a structural test because the specifications of the C U T are not tested directly. Therefore, it is difficult to correlate the test results with actual specifications. O - B I S T has been used to test A D C s [86, 87], operational amplifiers [89], active filters [88] and even digital circuits [90]. More specific B I S T structures have been designed for A D C s and D A C s (e.g., [91]) and P L L s . The A D C and D A C test scheme in [91] includes a significant amount of analog circuitry which makes it difficult to design and occupies large area. The details of P L L B I S T 36 schemes have been reviewed in Sec. 1.2. 2.3 Conclusions One of the major problems facing industry is balancing the need for testing to ensure product quality and the cost of testing. Since the final goal of testing is ensuring the functionality of the final product, functional testing is perhaps the most intuitive test method. However, the fault-based structural test generation approach for digital testing proved to guarantee correct functionality while reducing the test cost. This success prompted a large amount of research to develop structural tests for mixed-signal circuits, resulting in some partially successful techniques. However, the complex nature of mixed-signal circuits hampers the efforts to develop efficient fault models, fault simulation tools, and automatic test generation methodologies. These problems, combined with the expensive external tests, have made many experts believe that functional B I S T or embedded test is the best solution for testing high-performance mixed-signal circuits, at least until the mixed-signal fault modeling and simulation issues are resolved. This chapter reviewed a number of existing mixed-signal B I S T and D F T techniques available for widely used circuits such as amplifiers, filters, A D C s , D A C s and P L L s . H o w ever, many of these techniques have limitations, such as impact on the C U T , insufficient accuracy, limited to specific applications and/or large area. Therefore, new cost-effective mixed-signal B I S T and embedded test techniques are required to meet industry needs. 37 C h a p t e r B u i l t - i n C u r r e n t M o n i t o r A n a l o g f o r C i r c u i t 3 T e s t i n g B l o c k s In this chapter, a built-in current monitor ( B I C M ) capable of sensing and averaging the supply current of embedded analog circuit blocks is presented. The current monitor has two main parts: a built-in current sensor (BICS) [92] and a built-in current integrator (BICI) [93], as shown in F i g . 3.1. The current sensor circuit has a structure similar to that in [10] and [94, Chapter 12]. It can have a small ing device (w = 72 /j.m/0.35 nm). ZBIC (~ 20) for a medium-sized current sens- It also provides C U T supply voltage regulation. Such regulation can be exploited to decrease the sensitivity of the C U T to power supply variations [95]. B y analyzing the Z ic B characteristic of the sensor, we can optimize the design to minimize area and performance impact. The B I C I generates a digital signature proportional to IDD- The features of the B I C I include: 1. The possibility of on-chip integration since (/) it uses small capacitors (~74 pF in 38 CUT BIC DD I'sense (from another BICS) —— o Built-in Current Sensor (BICS) Built-in Current Integrator (BICI) n-bit > N Built-in C u r r e n t M o n i t o r (BICM) Figure 3.1: The proposed current monitor. total), and (ii) the circuit area increases only marginally (one flip-flop and 2 gates) for a twofold increase in T (in contrast to almost doubling the size i f simple capacitive integration is used). Only one integrator is needed on the whole chip by multiplexing the current from a number of C U T s to the B I C I (as illustrated in F i g . 3.1) 2. Suitability for B I S T applications since it generates a digital signature which can be easily evaluated on chip by simple digital circuitry The B I C I circuit, presented in this chapter, performs integration during one phase of a digital control signal, hence the name single-phase B I C I . Chapter 4 presents a double-phase B I C I circuit which performs integration during both phases of the control signal. The current monitor has been implemented using a standard 0.35 /j,m C M O S technology. Analytical 39 models, simulation results and some silicon measurements are also presented. The organization of the paper is as follows. The detailed operation and analytical model of the current sensor circuit are presented in Sec. 3.1. In Sec. 3.2, the current integrator circuit details are described. Sec. 3.3 reports the simulation and experimental measurement results. Sec. 3.4 provides further discussion on the proposed circuits, and draws some conclusions. 3.1 3.1.1 Built-in Current Sensor (BICS) B I C S circuit A block diagram of the proposed current sensor circuit appears in F i g . 3.2. The main part of the circuit is a current mirror composed of transistors M 1 2 and M l 3. The C U T supply current IDD is sensed by M 1 2 and mirrored onto M l 3 as a current I sense given by: Isense = &SIDD where K = ^ / j ^ (w/lis s (3.1) the aspect ratio of the transistors). The differential amplifier ( D I F F A M P ) amplifies the voltage difference between VBIC and a reference V f. This difference, used in the negative feedback loop, stabilizes re VBIC, forcing VBIC to be close to V jre We assume that V j is supplied from an on-chip voltage source (e.g., a bandgap voltre age source [95]). V j has to be small to allow a large portion of VDD to be supplied to the re C U T . However, choosing a very small value for V j could cause M l 2 to operate in the re triode region, which would result in increased ZBIC (see Sec. 3.1.3). In the circuit implementation shown in F i g . 3.3, V j = re O.IVDD- 40 DD V T CUT V c Bl IDD B I C Monitor Average current measurement block /' i sense f p—|["^M13a' ds9 M13 M12 From another BIC sensor ^—^J[M13 Vamp Figure 3.2: The block diagram of the current sensor. D I F F A M P is a single stage differential amplifier instead of the two-stage op-amp used in [10] for the following two principal reasons: 1. The second stage of an op-amp provides additional gain and output drive. For our sensor application, sufficient gain can be achieved with only one stage (the gain is sufficient to yield a ZBIC = 2f2), and large output drive is not necessary because the amplifier is not driving a resistive load. Therefore, in addition to simplifying the design, eliminating this second stage saves area without inducing performance loss. 2. Using a two-stage op-amp in conjunction with M 1 2 creates an amplifier with three poles in the frequency domain. Such a structure is difficult to stabilize. 41 The negative feedback also reduces Z ic B since: ZBIC = T 1 , (3-2) whereri2 i s M 1 2 ' s drain-source resistance and AD is the differential amplifier gain (Sec. 3.1.3 gives justification for the latter claim). rise to noise at VBIC ZBIC, however, increases at high frequencies giving which appears as supply noise at the C U T ground terminal. Sec. 3.1.3 offers a bandwidth definition for the sensor. 3.1.2 B I C S accuracy The accuracy of the current mirror is indicated by ERR = 1 — K IDD S 11sense- It is possible to achieve an error close to 1% by using layout matching techniques [96], assuming the effect of mismatch between Vdsn and Vd sl3 is negligible. This mismatch can safely be neglected i f long channel transistors (/ > 5 \±m) are used, as these result in very large transistors M l 2 and M l 3 . Instead, we choose short channel transistors (/ = 0.35 \im) and use an op-amp ( O P A M P in F i g . 3.3) to ensure v<i \2 = Vd s sl3 [10]. A n advantage of this technique is that ERR w i l l remain small even i f M 1 2 moves to its triode region of operation due to a large faulty IDD- Also, the area overhead of the O P A M P can be less than that of using longer M l 2 and M 1 3 . For example, Table 3.1 compares the area overhead of the two techniques for the design illustrated in F i g . 3.3. Another advantage of this technique is that as the width of M 1 2 is increased to accommodate larger values of IDD, the area of O P A M P remains the same. This results in a larger amount of area saved than when long channel transistors are used. 42 ERR reduction Technique Approximate area L o n g channel M l 2 and M l 3 /u>? 500JJ SOfi \ V / „ - 5u ' I,., - 5u > Using an op-amp for Vds matching 9000 nm 2 l: 4700 nm 2 Table 3.1: Area overhead comparison of two current mirror matching techniques 3.1.3 Calculating ZBIC F i g . 3.3 shows a transistor level diagram of the sensor circuit. signal analysis of the circuit. To calculate ZBIC is obtained from a small in this circuit, the C U T is modeled with ZBIC the current source IDD and the CCUT capacitor (effective capacitance at the C U T supply node). The capacitance is assumed to be 3 pF which is the equivalent capacitance at the G N D node of an example V C O circuit investigated in [8]. The differential amplifier ( M l M l 1), the sensing transistor ( M l 2 ) , and the IDD current source, in effect, form a two-stage operational amplifier (op-amp) connected in a unity-gain configuration[97, Chapter 5]. The compensation capacitor, C , comp To obtain ZBIC{J), is used to achieve a 60° phase margin for sufficient stability. a small signal analysis is performed as follows. F r o m F i g . 3.3: Z (s) cz where Z (s) cz and Zi (s) DD = Z ic(s)\\Z ( ) B lDD s are the Laplace transforms of the closed-loop op-amp output impedance and the IDD current source impedance, respectively. Since Zi (s) DD = oo, it can be concluded that: ZBIC{S) = Z (s) cz We denote the Laplace transform of the open-loop gain and output impedance of the resulting op-amp by H (s) og and Z (s), oz respectively. Algebraic manipulation yields the fol43 lowing closed-loop output impedance of the unity gain connected op-amp [98]: Zcz(s) = VBIC Z (S) OZ IBIC 1+ og V =3.3V DD DD JM5 16(1/ 1.4(1 M10 8(1/ 1.4(1 1 j|_|M2 Ml P 16(1/ 1.4(i 16(1/ 1.4[J 1 Mil 6 2.4(1/ 1.4(1 l M 3 'DD = 2mA) M7 M8 J16U/1.4UJ 16(1/ 1.4(1 1 1 M13a 12(1/0.35(1 _1_ <~ CUT - [ - 3pF ref Mlla 2.4(1/ 1.4u M4 8(1/1.4(1 (3.3) H (z) M6J 1 pF —Ccomp M12 M9 16(1/ 1.4(1 72(1/0.35(1 H M13 12(1/0.35(1 r 3 4 16(1/1.4(1 16(1/1.4(1 16(1/1.4(1 16(1/1.4(1 V i 8(1/ 1.4(1 ^ 8(1 /1.4(1 16(1/ 1.4(1 H 3 Figure 3.3: Current sensor circuit. To find an approximate closed-form expression for Z ic, B we replaced each transistor with the small signal model shown in F i g . 3.4. From [97, Chapter 5], for the frequency of 0 H z ( D C ) , all the capacitances in the model can be replaced by open-circuits, resulting in 44 Figure 3.4: A C model of a M O S transistor. the following equations for Z (0) oz Z {0) oz where g mi and r di = r dl2 and H (0): og and Hog(0) = 9mi2rdi2g i{r i\\r ) m d d3 (3.4) denote the transconductance and drain-source resistance of the transistor M i (i = 1 , . . . , 13). Substituting these values in Eqn. 3.3 yields the following for ZBIC(0) ^12/(1 + ^ 1 2 ^ 1 2 ^ 1 ( ^ 8 1 1 ^ 9 ) ) ^/g i2g i(r \\r ) m where AD = gmiifdsWda) m d8 d9 = ZBIC(0): (3.5) r /A 12 D is the differential amplifier gain, and n 2 = l/g \2 m is M 1 2 ' s drain-source resistance. Note that g i decreases as M 1 2 moves to the triode region. Therem 2 fore, M 1 2 should operate in saturation region to ensure larger values of g ml2 which, in turn, yield a smaller ZB IC (0). To determine the characteristics of ZBIC at frequencies other than zero, we derive approximate expressions for the dominant zeros and poles of ZBIC{S)> as they specify the fre- quency response of the current sensor. To do so, the symbolic toolbox of M A T L A B [99] was used in conjunction with simulated operating point values for transconductances, capacitors and resistor in the small signal model. Details of the technique used for this derivation can be found in Appendix A . 45 The result of the small signal analysis indicates that has only one dominant ZBIC{S) zero given by: Zd =-l/(C + C ){rd8\\rd9) comp Since has one dominant zero, ZBIC(S) ( - ) 3 gsl2 6 increases at frequencies exceeding Zd- This \ZBIC\ implies that the sensor w i l l have a frequency limit beyond which w i l l be too large \ZBIC\ to be acceptable. Practically, the sensor w i l l have a limited acceptable bandwidth which depends on the C U T performance specifications. For example, assuming that a C U T can tolerate 25 mV of supply voltage noise (|VB/C| ( c amplitude) a = ^5 mV) and that the high frequency components of IDD have maximum amplitude of 1mA, the maximum acceptable value for ZBIC is frequency range / = 0 to f , where RMAX as the B where JR is the frequency such that \Z ic(s R RMAX = 250. We define the sensor bandwidth, BW ic VBIC/IDD = j27r/#| B = is a specified maximum acceptable value for the magnitude of the sen- sor impedance. To obtain a closed-form expression for zero system expression (with s = Z ic(jf) B If Z ic(0) B <C we approximate by a single- ZBIC{$) jf): = Z(0)(1 + -l) Zd \Z ic(jf )\ 3 RMAX BWBIC, B R = Z ic(0)\(l + -^)\ Zd then z <C JR. Therefore, substituting Zd and d (3.7) 3 B ZBIC(0) from Eqns. 3.5 and 3.6 in Eqn. 3.7 leads to the following simple expression for /#: f — D jR-iiMAX-^ D <7ml<7ml2 TfX = n.MAXJ^ ~~ 7 ABICXy) \ygsl2-r^comp) . (3.8) Z d From Eqn. 3.8, the sensor bandwidth is directly proportional to g ml and g i2- Various design techniques can be used to increase m to choose wider M l and M 2 transistors. 46 BWBIC- Q (and also g m2 = g i) m A simple measure is 3.2 Single-phase B I C I Here, we propose a single-phase B I C I circuit which performs integration only in one phase of a control signal <f> (when </>=LOW) which controls the integration operation. 3.2.1 Basis For a feasible on-chip IDD integration, the integrator circuit should not require a large capacitor. To avoid the use of a large capacitor, the circuit proposed here exploits the following two principles: • Reducing the integration time, T, results in a proportional reduction in the size of the integrating capacitor (Eqn. 1.4). • Integration over a specific time can be expressed as the summation of a series of integrations over shorter periods of time, i.e., M-l Idt where T - MT S (3.9) and I is the B I C I input current. The functional block diagram in Fig. 3.5 illustrates the basis of this integrator circuit. In this circuit, the total integration window of duration T is divided into M smaller integration sub-windows of duration T , i.e., T = MT . s S The 'short-time analog integrator' (STAT) integrates an input current / for the time T (the initial condition at the beginning of each s integration sub-window must be OV). B y making T sufficiently short, an arbitrarily small s capacitor C can be used to generate the voltage u.-(r) proportional to the integral of the input current: (3.10) 47 1 Short-time analog integrator (STAI) v,(t) Sample & Hold (S&H) V/ ADC Accumulator (ACC) Figure 3.5: Single-phase B I C I functional block diagram where Kc is a constant dependent on S T A I design. The S T A I output at the end of the i-th integration sub-window, denoted by K , is given by: Vi = u,-(r)|t=(.-+i)T = K J [ ii+1)Ts c I(r)dT (3.11) JiT s Vi is sampled and held by the S & H block. The ADC block converts Vi to an n-bit digital number Ni proportional to Vi, i.e., : V = N,V + Vf A where V A is the ADC quantization step and 0 < V (3.12) < V A is the A D C ' s quantization voltage R error in the i-th integration sub-window. The ACC block adds all the JV,-'s {i = 0 , . . . , M—1) to generate the number N, i.e., N = YliLo The following formally summarizes the 1 current integrator functionality: = HfioW - V*)/VA = (l/Vk)E^o ^c/^ 1 = R 1 MT c (3.13) A R 0 A (Kc/V )tfldt-V /V R A = E ^ o V. 1 /^-(l/VA)E^o V« (K /V )f <Idt-V /V = where V 1 ) T 3 R A The above is an idealized analysis. Actual limitations arising in practice are discussed later. 48 3.2.2 N o t a t i o n a n d definitions The notation and definitions used in describing the details of the single-phase B I C I circuit and its operation are as follows: • T : total integration time window duration • T : integration sub-window duration such that T = MT s S • M : the number o f integration sub-windows in T • fa: i-th [i = 0 , . . . , M — 1) integration sub-window • T ( fjy. s "effective integration interval". Portion o f T i n which integration is per- e s formed. • TR = T — T ( f /)'• reset time. Portion o f T in which the circuit is reset for the next s s e s integration sub-window. • ti\ beginning time o f the sub-window </>,-. • t•= U+ T( ) s ef} • C L K : clock signal • cf>: signal with period T controlling the integration timing. s • A^ : digital number proportional to integration of I i n fa t • N: final number proportional to integration of / over time T (N = Yliio 1 • Q{. A D C quantization noise associated with 49 Ni) • Q: total quantization noise over time T • R{\ reset noise associated with Ni • R: total reset noise over time T ,2.3 Circuit operation v,DD X ramp i rst S6 • rararararararararatsrarararara s • V:s3 7 XS4 X - — r — r r r T :analog Integrator; ; \ S&H v 8 ' 1' r_rst D Inhibit < r r [ Q FF2 <L rst COUNTER CLK , clk< clr Clr elk 4 IJ ' •Q D FF1 r1 , clk< clr t_i COMP + n-bit ADC & ACC rst Figure 3.6: Single-phase B I C I circuit schematic 50 S 7 The single-phase B I C I schematic is given in Fig. 3.6. Transistors M l and M 2 form a scaling current mirror to supply the current I se from the sensor to the integrating capacitor sen C int = Ci + C V The value of Ci nt is chosen such that M 2 does not enter its triode region of operation during the integration over time T . For example, assuming that M 2 enters its s triode region at Vc = 2 . 5 V , T = 1 /-is, and the maximum average current flowing into C\ s during an integration sub-window, lT ( ), a required since C int = h ( )T /V 3 max s max is 150 fj,A, a 60 pF capacitor or larger would be = 60 p F . c A timing diagram of the circuit operation illustrating the significant waveforms is shown in F i g . 3.7. The input current I is assumed to be a sinusoid with D C offset. 0 is a signal with period T which controls the integration timing. Since T — MT , a complete s S integration requires M consecutive periods of <f>. In each sub-window 4>i, two parallel operations are performed: 1. / i s integrated over time T ( j j) resulting in the voltage waveform Vc- In the subses e quent time TR, a part of the integration result is stored as the Voltage V on C 3 (Vs waveform). T R is the reset time during which C\ is discharged and the control circuitry is reset (initialized) 2. Concurrently to the above, the ADC & ACC blocks digitize V^ x end of the previous integration sub-window stored on C at the 3 and accumulate the result These operations are repeated over M integration sub-windows to obtain the integral of I over the time MT . S 51 CLK Figure 3.7: Timing diagram and different waveforms in the B I C I circuit of F i g . 3.6 52 S h o r t - T i m e analog integrator (STAI) a n d S & H The operation o f S T A I and S & H blocks are tightly coupled, and thus both are described in this section. F r o m Figs. 3.6 and 3.7, in the interval fa, switches S l and S3 are closed for time T ( ;j), while switches S2 and S4 are open. During such a time interval, I flows through G \ s e and C . The voltage at node C at the end of the i-th integration interval, VQ, is given by: 2 V = Vc{t\) = - ^ - ^ c [*' Idt + K V^ (3.14) 2l where K - i is the initial condition on C at the beginning of fa, K 2 U = iT s and t % = iT s + T s{eff) 21 = (i + 1)T S = C /{Ci 2 + C ), 2 - TR. Note that we assume C\ is fully discharged at the end of each interval fa. For the subsequent time TR in fa, switches S l and S3 are opened, and switches S2 and S4 are closed. This effectively results in two functions: (i) G \ is discharged through S2 to initialize C\ for the next integration sub-window; (ii) the charge stored on C at t = t\ is 2 distributed between C and C . Therefore, the voltage on node S at time t - = t[+c (e —> 0) + 2 3 denoted by V, is: Vi = TT^—rVi G3 "T ^2 where K 23 — C /(C 2 3 = (3.15) + C ). The waveforms Vs and VA in F i g . 3.7 illustrate this operation 2 for K 3 = 0.5. 2 In the subsequent interval fa+u the switch S4 is opened causing Vi to be held on C . 3 Therefore, switches S3 and S4 in conjunction with C and C perform a sample and hold 2 3 operation. The advantage of this circuit over more conventional sample and hold circuits is that it does not require analog buffers in front of the sampling switches S3 and S4. This 53 simplifies the design significantly because there is no need to design wideband buffers with very small input D C offset voltages [97]. Not using an isolating buffer between C\ and C means that the charges on C in fa affect the integration in fa 2 +1 2 (see Eqn. 3.14). However, as shown in Appendix B , this affects only the proportionality factor K of B I C I characteristics (Eqn. 3.16) which is obtained through calibration. A D C & accumulator ( A C C ) During fa (time ti to t •), the ADC and ACC blocks digitize the voltage stored on C3 (node S) and add the converted voltage to the digital number accumulated using a counter. The single slope technique is used to perform the analog-to-digital conversion because it can be implemented with small area and provides good linearity. When (f> goes from H I G H to L O W , the flip-flop F F 2 is set (r_rst signal turns L O W ) causing the counter to start counting (incrementing by one at each C L K rising edge). The C L K period must be much less than T ( jf), e.g., T ( /f) = s e s e ^OTCLK- Concurrently, switches S5 and S7 are opened, and S6 is closed. This causes the constant current I p ram to flow into C4, generating a ramp voltage waveform with constant slope at node R. The comparator C O M P output, r l , switches state when VR>VS = Vi-i- A t this moment, FF1 is set. This, in turn, resets F F 2 , which stops the counter. A t the end of such a cycle of operations, a number /Y,-_i proportional to K _ i is added to the value already accumulated in the counter. After stopping the counter, S6 is opened and switches S5 and S7 are closed to discharge C and C4. Also, F F 1 is reset to initialize F F 1 and F F 2 for conversion in the next 3 integration sub-window. A s shown in Appendix B , the relationship between the final counter state, N, and 54 the average current over time T, is obtained from the following: N =Kfifldt + 0 + E = KTI+ (3.16) 0 + E where K is a constant, O is an offset value, and E is a random number resulting from A D C quantization noise Q, and a reset error R, i.e., : E = Q + R (3.17) Q and R are the result of the accumulation of quantization noises Qi's, and reset errors i ? ' s t in each integration sub-window, respectively: Q= E ^ o R= Efio ^ 1 ^ (3-18) (3-19) 1 The reset error factor is due to the reset time TR in each integration sub-window during which I is not integrated. A s shown in Appendix B , E has a Gaussian distribution with a zero mean and a variance given by: where K M = c^i-K K ) {Cl+ i3 2i a n d K ' = ^ P / ^ ' Sec. 3.2.4 describes how K and 0 can be obtained through calibration, while Sec. 3.2.5 discusses guidelines for minimizing E. 3.2.4 B I C I two-point calibration To calibrate the integrator circuit, two known current signals, 7 cl integrator circuit. In each case, for given C L K , T, T , TR and I s • 55 and I , are applied to the c2 , ramp the corresponding av- erages N cX and N c2 are recorded by the counter: N = cX N= KTl7x + 0 + E (3.20) cl KT772 + 0 + E c2 (3.21) c2 The calibrating current signals, I and I , must be A C signals with a large average (e.g., cX c2 more than 30% of the maximum average current the circuit is designed for (IMAX))- The large average current yields relatively large values for iVys. This reduces the ratio Qi/N t because the statistics of Qi are independent of Ni (they are only a function of the ADC quantization step (refer to Appendix B)). The A C component reduces E cl and E c2 by randomiz- ing the Qi's and the reset errors i ? ' s in each integration sub-window. The frequency of the t A C components, denoted by /CAL, should satisfy the relationship l/T be uncorrelated with <f>. Assuming negligible E cX N cX N= c2 = < JCAL < l/T and s and E , Eqns. 3.20 and 3.21 simplify to: c2 KTL7+0 (3.22) KTIT2 + O (3.23) Computing K and 0 in the above completes the calibration process. Eqns. 3.16, 3.22 and 3.23 yield the following relationship between N and / : N = (N c2 The D C values of / c i - N and I e c2 l )(=L ) + *c2 — Icl r N * J- — « ^ Icl I lc2 N + e (3.24) signals must be precisely known but the frequency, am- plitude and waveform of their A C components are not critical because the A C components only serve as an error randomizer to reduce the factor E. A n y A C signal available on the chip could be used for this purpose as long as it satisfies the conditions mentioned above. The precise D C current I cX has to be generated on-chip or be supplied from off-chip. I c2 be generated using a properly matched current mirror I c2 56 = nI . cX can In a B I S T application, the current measurement result should be evaluated on-chip by comparing JV with limit values Ni and N corresponding to the predetermined minimum h and maximum average current thresholds I\ and 1^, respectively. Assuming I c2 I = H t c2 and Ih = rnl c2 = 2/ , c l where I and m are integers, from Eqn. 3.24, the calculation of Ni and Nh, only requires simple integer multiplication and addition as shown below: N = (2l-l)N -(2l-2)N l N h d2 (3.25) cl = (2m - l)N - (2m - 2)N c2 (3.26) cl The above operation can be implemented using a shift register and an adder. Digital multipliers and adders, usually readily available on mixed-signal ICs, can also be used to calculate Ni and Nh. This is important, as each chip has to be calibrated and therefore standard ./V; and Nh values cannot be downloaded from an external source (e.g., tester). 3.2.5 Single-phase B I C I accuracy To achieve a high measurement accuracy, sources of error have to be identified and their i m pact minimized by design. The factors affecting the measurement accuracy of the integrator circuit are as follows: 1. M l and M 2 should be long transistors to reduce the effect of V^s variations on I 2. The M 1 / M 2 mismatch, C\, C , C , C , and I p 2 3 4 ram variations, and the propagation de- lays in the comparator, flip-flops and the gates (denoted by i n F i g . 3.7), affect the factors K and O in Eqn. 3.16; this is shown by the analysis in Appendix B . Using a two-point calibration scheme, K and O can be determined. Therefore, any process 57 and temperature variations affecting K and O w i l l affect measurement accuracy, i.e., these can be accounted for via the calibration process explained in Sec. 3.2.4 3. The clock feedthrough associated with the S3 and S4 switches can alter the charges on Ci, C and C , thereby affecting measurement accuracy. Avoiding very small val2 3 ues for these capacitors and using complementary switches w i l l minimize the clock feedthrough problem [97] 4. Power supply (VDD) variation w i l l not deteriorate the performance of the integrator circuit because it affects the value of I , ramv the delay and the offset of the comparator, and the delays of the gates and flip-flops in the circuit, all of which are compensated for during calibration 5. The error term E in Eqn. 3.16 w i l l generally be the major source of reduced degradation. E has two components: the quantization noise Q; and R that results because / is not integrated during a reset time TR. The R can be minimized by making A s for Q, increasing T or increasing the C L K frequency w i l l reduce this factor s A s discussed above, the integrator circuit accuracy is independent of process variation when using a two-point calibration scheme. This property makes the circuit especially suitable for integration on high volume mixed-signal chips. 3.2.6 Circuit implementation Assuming that the integrator circuit is to be used in an application where the maximum of I is 150 n A and the available C L K frequency is 20 M H z , the following parameters were chosen to design the integrator circuit: 58 • T = 1 ms, T = 1 ps, M = 1000 s • T*(eff) = 0.95/us, T R = 50 ns • Tamp — 11.2 • Counter size: 18-bits 26/0.6 r_rst 1 - analog integrator X X : I Inhibit r_rst COUNTER CLK rst clr elk < v CM JHtttaflD Q D 1 ' 1' FF2 (fo , clk^ clr o s 1 n-bit ADC & Accumulator •Q D FF1 r1 clk clr u COMP + rst Figure 3.8: The transistor-level schematic of the integrator circuit 59 These parameters imply that C i = 60 pF. The transistor level schematics of the main circuit and the comparator are shown in Figs. 3.8 and 3.9. The component values and transistor sizes are shown for critical components. These values have been chosen to achieve reasonable integration accuracy (error < 2%) as explained in Sec. 3.2.5 and to reduce the circuit area. Since the delay and offset of the comparator are not critical, a simple two-stage comparator was chosen. It is possible to use faster comparator structures such as the one in [100, Chapter 26], but a larger circuit area would be required. 4> and 4> are non-overlapping control signals constructed from cf>. They are used a b instead of <f> and 4> in Fig. 3.6 to avoid sample and hold errors [97]. The total area of the circuit is 45500 (pm) . This is equivalent to the area of a digital 2 circuit consisting of 250 N A N D gates in a 0.35 pm digital cell library. Figure 3.9: Schematic of the comparator 60 3.3 3.3.1 Simulation and Experimental Results BICS The current sensor circuit has been simulated with SpectreS [101] and SpectreSVerilog from Cadence Design System. The B I C sensor's main performance measure is its output impedance response versus frequency, /.e., = j2nf). ZBIC(S F i g . 3.10 reports Z ic B vs. frequency from our approx- imate first-order analytical model, simulations, and I C measurements for the circuit illustrated in F i g . 3.3. The dc impedance,Z /c(0), and bandwidth for R 5 = 250 results are m a x tabulated in Table 3.2. ZBIC(0) (0) 2.7 2.7 2.7 3 lst-order analytical model Simulation (CCUT = 3 pF) Simulation (CCUT = 30 pF) Measurement BW S (MHz) (Rmax 250) . 5.7 5.4 5.3 5.3 = Table 3.2: L o w frequency impedance and bandwidth of Z ic B The parameter values needed for first-order model calculation are obtained from the operating point simulation. These parameters were found to be: r s ds 720 kto, g = 166 ufl' , 1 ml g = 6.1 m f l " , C 1 mU gsl2 = 700 fcO, r ^ 9 = = 88/F. The high frequency poles, from measurement, are located at frequencies lower than expected from simulation. This is primarily because of the pad and oscilloscope probe capacitance. Repeating simulations for CCUT = 30 pF (shown in F i g . 3.10) confirms this hypothesis. 61 300 /(Hz) Figure 3.10: ZBIC versus frequency Plots of the simulated transfer function for I se/K IDD sen S appear in F i g . 3.11. This figure shows that even fairly high frequency components ( / ~ 20 MHz) of the current are sensed adequately (i.e., without significant attenuation). However, since the high frequency components do not contribute to the average current (see Sec. 1.1.1), the limited bandwidth does not affect the accuracy of the B I C monitor. F i g . 3.12 shows the simulated and measured D C characteristic of V ic versus IDDB A s expected, for current values larger than a threshold value, VBIC increases rapidly with the current, because the differential amplifier D I F F A M P output saturates. Consequently, v i gs 2 does not increase further as IDD is elevated. In other words, for large currents the negative feedback does not exist, which results in increased ZBICdynamic range of this sensor with regards to ZBIC 62 Therefore, an upper limit for the is Ith = 10 mA from simulation and 5 0 CQ T3 -5 -10 Simulation Ccut=3p Simulation Ccut=30p Q _P - 1 5 * -20 § -25 CD tn -30 -40 -35 10 Figure3.11: I nse/K IDD 1/6) se I S 10* f (Hz) 10 transfer function for IDD = 1 m A at the operating point ( A ' = s = 7.8 mA from chip measurement. The difference between the simulation and mea- th surement result can be justified by the fact that the model file parameters used in simulation are extracted from a different fabrication run than the one in which the tested chip was manufactured. To achieve a larger dynamic range, a wider M l 2 should be chosen. F i g . 3.13 shows the simulated and measured current mirror gain error, ERR = 1 — (K IDD/hut), for different IDD levels. The dashed-dotted line shows the ideal value of S ERR when I out is the drain current of M 1 3 (in F i g . 3.3). A s expected, this ERR value is very small (< 0.1%) even when M 1 2 operates in the triode region (I D D dotted plot shows ERR when I out = I sesen > 10 m A ) . The In this case, ERR has relatively large value (~ 2%) because of the leakage currents of transistor M 1 3 a in F i g . 3.3. However, as IDD i n creases, this leakage current becomes less significant and ERR decreases to less than 1.2% 63 1 0.9 0.8 0.7 > o 0.6 m > 0.5 0.4 0.3 0.2 0 5 10 15 20 Figure 3.12: VBIC versus IDD D C characteristics for IDD > 2mA. The chip measurement results, shown with circles, are significantly different from the simulation results. Upon investigation of the layout, it was discovered that this difference is due to the resistance of the metal lines and vias connecting the input V ic node to B the drain of M 1 2 . This resistance, denoted by Rp, is approximately 3fl. Repeating the simulations considering Rp = 3fi yields the solid-line plot in F i g . 3.13, which matches the measurement results well. In the designed layout, we modified the layout to decrease this resistance to 0.5H. The dashed plot in F i g . 3.13 shows that this layout modification reduces the systematic mismatch to a maximum of 1.6%. 64 10 0 2 4 6 8 10 12 14 16 18 Figure 3.13: Measurement and simulation results for ERR versus IDD considering the parasitic resistances in the circuit. 3.3.2 Single-phase B I C I Cadence SpectreS [101] and SpectreSVerilog simulators were used to simulate the B I C I circuit described in Sec. 4.2.7. B S I M 3 M O S models were used for analog and mixed-signal simulations. Table 3.4 reports simulation results for the average current measured by the B I C I for a set of 13 different current signals with different waveforms, frequency, amplitude, and 65 Name Waveform Parameters DC1 DC2 DC3 DC4 SIN1 SIN2 SIN3 TRG1 TRG2 TRG3 SPK1 SPK1 SQ DC DC DC DC sinusoid sinusoid sinusoid triangular triangular triangular Shown in F i g . 4.8(a) Shown in F i g . 4.8(b) Shown in F i g . 4.8(c) IDC = 150/1A I = 140^ A I = 1001* A IDC = 50/i A f=3 M H z , D C offset=60 /J,A, Amplitude=40 / i A f=100 k H z , D C offsets 100 pA, Amplitude=50 /J,A f=5 k H z , D C offset=80 \xA, Amplitude=70 \xA f=3.57 M H z , D C offset=50 fiA, Amplitude=20 [iA f=20 k H z , D C offset=70 fiA, Amplitude=30 / / A f=2.5 k H z , D C offset=120 pA, Amplitude=30 / i A DC DC Table 3.3: Single-phase B I C I test signals offset values. The large set was to test the performance of the circuit for a wide range of input signals described in Table 3.3. Signals SIN2 and T R G 2 were used as calibration signals because they satisfy the conditions mentioned in Sec. 3.2.4. The second column in Table 3.4 reports the true average current for each signal and the fourth column indicates the average current estimated by the B I C I circuit. The relative error of the estimated average current is reported in the last column. A relatively large error occurs when the average current is small and the current is constant for a large portion of its period (signals S P K 1 and S P K 2 ) . This is due to the quantization noise Q because: (i) Q,-'s becomes significant as the value of the current decreases; (ii) since current integration in each integration sub-window yields a constant voltage, Qi is constant for i = 0 , . . . , M — 1, causing the error to accumulate over time. The same reasoning explains the relatively large errors for signals D C 4 and S Q . Such inaccuracy, however, 66 may not be a limiting factor in using this circuit for test purposes because the faulty current may be well below the lower threshold of the current tolerance band. For example, assume the fault-free current is 100 a-A, and the current lower threshold is 50 \iA. If the average current measured for a faulty circuit is 20 pA, even with 25% error for this value (the actual average current could be 25 pA < 50 pA), the decision to discard this circuit is correct. The signals S P K 1 and S P K 2 (Figs. 3.14a and 3.146) are in fact similar to smallvalued D C currents but with periodic short time current spikes in each period. Such signals model supply current of circuits such as V C O s and digital circuit blocks. The error is also significant for signal SIN1. The reason is that signal SIN1 is correlated with the 4> signal, causing both Q and R to accumulate over time. In summary, simulations indicate that the B I C I circuit provides < 2% error provided the current ac component is not correlated with <f>. Figure 3.14: Current waveforms S P K 1 , S P K 2 , and S Q for validating the operation of the single-phase B I C I circuit 67 Waveform True I N DC1 DC2 DC3 DC4 SIN1 SIN2 SIN3 TRG1 TRG2 TRG3 SPK1 SPK2 SQ (M) 150 140 100 50 60 100 80 50 70 123 18.3 33 72.4 16985 15986 11990 6994 7993 11826 9688 6710 8737 14207 2999 4388 9266 I estimated (jiA) 150.1 140.4 101.6 53.1 62.8 100 79.2 47.2 70 123.1 14.3 27.7 74.6 100(A//7) 0.1 0.3 1.6 6.1 4.6 0 (Cal. point) -1 0.6 0 (Cal. point) 0.1 -22 -16 3 Table 3.4: Simulation results for the average current measurements by single-phase B I C I circuit 3.4 Conclusions We presented a built-in current (BIC) monitor suitable for power supply current (IDD) testing of analog circuit blocks. The B I C monitor senses the IDD and generates a digital signature by averaging the current over a programmable time window. The B I C monitor provides a low impedance, of the C U T . ZBICU) ZBIC, (2.70) in the power supply path has a bandwidth of about 5.3 M H z . The B I C sensor could be used in circuits where the C U T supply current has large D C and smaller ac components. This is the case in many analog circuits because (i) the biasing circuitry contributes a large D C current, and (ii) most embedded analog circuits do not drive large ac loads. The B I C sensor could also be used in high speed submicron digital circuits by adding a bypass capacitor on the C U T connection to the sensor. Such a capacitor would reduce the 68 maximum impedance of the sensor (as shown in F i g . 3.10), which would result in less power supply noise. For BIST, a necessary functional block, besides the sensing block, is a measurement block. In this chapter, a measurement block was proposed that measures average current, i.e., integrates current over a time window. The B I C I requires small area (equivalent to a circuit consisting of 250 N A N D gates). B y using any linear feedback shift register ( L F S R ) or a register already available on chip (e.g., as part of digital BIST) to implement the counter needed for this circuit, a saving of 28% in area is possible. B I C I also yields a digital signature which is convenient to interface to standard digital external or internal A T E and standards like I E E E 1149.1. Our circuit provides a good accuracy (error < 2%) i f the current levels are not too small relative to the maximum current for which the circuit has been designed (e.g., I/IMAX > 0.3). The digital signature makes the monitor suitable for B I S T application. 69 C h a p t e r D o u b l e - P h a s e 4.1 B u i l t - i n 4 I n t e g r a t o r Introduction A s discussed in Sec. 1.1, averaging is an effective method for generating current signatures. In Sec. 3.2 a single-phase B I C I circuit was presented that performs on-chip current integration. Although sufficient for some applications, the single-phase B I C I might be inadequate for applications where higher measurement accuracy is required. This chapter presents a double-phase B I C I circuit which performs integration during both phases of the control signal (hence, the name 'double-phase'). This novel B I C I architecture uses the same principles as those in Sec. 3.2.1. However, the circuit proposed here provides significantly more accurate measurements at the expense of a slightly larger area (approximately 20% more). The higher accuracy is achieved by: (i) using two integrators which operate at two complementary time intervals in each cycle of a control signal, hence eliminating reset error; and, (ii) feeding forward the quantization residues from each integration interval to the next, thereby preventing the accumulation of quantization noise. 70 The double-phase B I C I generates a digital signature proportional to IDD- L i k e the single-phase B I C I , this circuit is also compact and can provide a worst-case error less than 1% for any IDD waveform. The organization of this chapter is as follows. In Sec. 4.2, the details of B I C I circuit are described. Sec. 4.3 reports the simulation results. Sec. 4.4 provides further discussion regarding the proposed circuits, and concludes. 4.2 4.2.1 Double-phase B I C I Circuit Basis The functional block diagram in F i g . 4.1 illustrates the basis of double-phase B I C I . In this Figure 4.1: Double-phase B I C I functional block diagram circuit [93], the total integration window of duration T is divided into M smaller integration sub-windows of duration T sec, i.e., T = MT . s S 71 the input current is split into two components: I = IA + where IA = ctl and I B = (1 — a)I. IB a is a periodic function with period of T , whose one s period is defined as: 1 0 < t < a = < ( 0 T /2<t< T /2 s T s I A and I B are integrated by the two half-wave current integrators H C I ( A ) and H C I ( B ) over the time T to generate two digital numbers, N A where Q A s and and N , B respectively, such that: are H C I ( A ) and H C I ( B ) quantization errors. The digital adder sums N A and NB to obtain N which is proportional to the integration of I over T : A H C l block generally functions according to the principles described in Sec. 3.2.1, but it uses a different A D C method than the one described in Sec. 3.2.1. The A D C presented in Sec. 3.2.3 generates a number A , such that V = iV; V A + V f where V is the quantizaA tion step of the A D C , and V f < V A is the A D C ' s quantization voltage error in the i-th integration sub-window. Therefore, from Eqn. 3.13, V R = Yliio 1 V f ' which may result in significant quantization error. We propose a different A D C design to reduce V . R A D C uses a quantization The new residue feed forward technique, which enhances the accuracy of the B I C I by preventing the accumulation of quantization errors V f . In this technique, V f , , 72 the residual voltage from digitization in the (i — l ) - t h sub-window is fed forward for digitization in the i-th sub-window. This is illustrated i n F i g . 4.2 for an example A D C with seven quantization thresholds. Using this technique, A D C converts Vf — (Vi + V ^ J to an n-bit digital number Ni, such that: = NiV + V? A (4.1) F r o m Eqns. 3.11, 4.1, and the above discussion, the B i d ' s functionality is summarized as follows: Kef? Idt = J2 c i•r, =0 I JH- * K NV 0 A Idt iT + (V + K R 0 J c T Idt) + £ c I Idt i=2 N V + ^ 1 4 + (Vf + K K J x T s = 0 A c f 3T Idt) I2T J2T, 3 3 (4.2) 3 M-l i=3 • o = VA (i+l)T, "° Jil f iT M-l £ Ni + F r o m Eqn. 4.2, it is evident that V R V*_ x = V^_ . x The above is an idealized analysis. Actual limitations arising in practice are discussed later. 4.2.2 Notation a n d definitions The notations and definitions used in describing the integrator circuit and its operation are as follows: • C L K : Clock signal 73 Figure 4.2: Quantization residue feed forward technique used in the A D C of double-phase BICI • fa Signal with period T controlling the integration timing. s • $ : Signal with period T controlling the integration timing in a half-wave current ins tegrator. • T: Total integration time window duration . • T : Integration sub-window duration such that T = s MT S • M: The number of integration sub-windows in T • fa: i-th (i = 0 , . . . , M — 1) integration sub-window • T ( jjy. "effective integration interval"; the portion of T in which integration is pers e s formed. • T R = TS T ( y. s e}f "reset time"; portion of T in which the circuit is reset for the next s integration sub-window. • U: Beginning of the period fa. 74 • t = U+ { T s(e}f) • Ni'. The integer number proportional to integration of I in • N: Final number proportional to integration of / over time T (N = YJiLo 1 Ni) • Q: Total quantization noise over time T A n y parameter with a (A) or (B) in its subscript refers to the corresponding parameter in H C I ( A ) or H C I ( B ) , respectively. 4.2.3 Circuit operation COUNTER elk Inhibit cnt_ctrl elk CLK HCI (A) cnt_ctrl HCI f l in telk \ m DIVIDER elk Figure 4.3: Current integrating circuit schematic The B I C I schematic and its important waveforms are given in Figs. 4.3 and 4.4, respectively. The D I V I D E R divides the frequency of the clock by an even number, L, and generates the signal <f> with 50% duty cycle. The C O U N T E R increments at each rising edge 75 of the clock i f its i n h i b i t input is L O W and keeps its value otherwise. For implementation reasons, we use two half-wave current integrators ( H C l ) in parallel. H C I ( A ) and H C I ( B ) integrate 1$ and l-r, respectively, where I x (X = <j> or fa) is defined as below: I X = 0 X = HIGH Ix=l H C I ( A ) integrates I only when fa = LOW LOW (fa(L) interval). During fa(L), H C I ( A ) turns its c n L c t r l output L O W for a time proportional to the current integration in fai-\)(L)This causes a number N (A) to be added to the counter value. Similarly, during fa(H) a num1 ber Ni(B) proportional to the current integration during fai~i)(H) is added to the counter value. Since H C I ( A ) and H C I ( B ) perform integration during complementary times, the counter state at the end of the operation w i l l be proportional to the integral of I over T. 4.2.4 Half-wave current integrator ( H C l ) The H C l operates based on principles described in Sec. 4.2.1. The H C l circuit schematic is illustrated in F i g . 4.5, while a timing diagram of its significant waveforms is shown in Fig. 4.4. The input current / is assumed to be a sinusoid with D C offset. $ is a signal with period T which controls the integration timing. Since T = MT , s S tegration requires M consecutive periods of $ . In the interval a complete half-wave i n two parallel operations are performed: 1. / is integrated for effective integration time interval T ( j j) resulting in the voltage s e waveform Vc 2. Concurrently to the above, the ADC & ACC blocks digitize and accumulate the voltage ( V i _ i + V f j) stored on C at the end of the previous integration sub-window <& _i 3 t 76 CLK ^i(L) s(eff) : T Figure 4.4: Timing diagram and different waveforms in the integrator circuit of F i g . 4.3 77 During the two parallel operations are also performed: 1. During the reset time TR = duration of^^n), C i is discharged and the control circuitry is reset (initialized) for the next integration sub-window 2. A voltage, Vi, indicating the integration result is added to the V voltage stored on C R waveform). Therefore, at the end of 4>i(H), Vc3 = V: + V X 3 (Vs R l These operations are repeated over M integration sub-windows to obtain the half-wave integral of I over the time MT . Further details are given next. S Short-time analog integrator (STAI) a n d S & H Since the operation of S T A I and S & H blocks are tightly coupled, both are described in this section. F r o m Figs. 4.5 and 4.4, in the interval $;(£,)» for time T ( /f) switches S I , S3 and s e S5 are closed, and switches S2, S4 and S6 are open. During such a time interval, / flows through C i and Ci. The voltage at node C, i.e., Vc, at the end of i.e., V , is given c by: (4.3) where V is a constant voltage remained on C from fa-i period, K \ a U = iT s 2 and t\ = iT s 2 + T ( / / ) = (i + 1)T - T . s e S R = Cij(C\ Note that we assume d + Ci), is fully discharged at the end of each interval T,-. For the time TR, i.e., during switches S 1 , S3 and S5 are opened, and switches S2, S4 and S6 are closed. This effectively results in two functions: (i) C is discharged X through S2 to initialize C\ for the next integration sub-window; (ii) the charge stored on 78 Figure 4.5: Half-wave current integrating circuit schematic 79 C at the end of $ (L) is transfered to C . The charge transfer is accomplished as follows. 2 t 3 A current starts flowing from VDD through C and C to V ji- A s soon as the voltage on 2 3 re C crosses OV, the comparator C M P 1 switches state causing the switch S6 to open and hold 2 the voltage on C . This results in the charge Qci = C Vf 3 2 to be added to C and held: 3 (4.4) = where K 23 + v = C / C . The waveforms Vs and VA in F i g . 4.4 illustrate this operation for 23 K y^i 2 3 = 1/3. A D C & accumulator During (timet,- to t\), the ADC and ACC blocks digitize the voltage ( K _ i + V ^ ? ) stored 2 on C (node S) and add the converted voltage to the number accumulated in a counter. The 3 single slope technique is used to perform the analog-to-digital conversion because it can be implemented with small area and provides good linearity. The principle of the ADC ACC blocks operation is further explained next. - When $ turns LOW, the flip-flop F F 2 is set (r_rst signal turns L O W ) causing the counter to start counting (incrementing by one at each C L K rising edge). The C L K period must be smaller than T ( j/), s e e.g., T ( - ) = This causes the constant current I s ramp e} } 10T LKC Concurrently, the switch S7 closes. to flow through C generating a ramp voltage wave3 form with constant slope at node R. The comparator C M P 2 output, r l , switches state when VR > V j . A t this moment, F F 1 is set. This, in turn, resets F F 2 , which causes the counter re 2 to stop at the next clock edge. A t the end of such a cycle of operations, a number 7Vj_i proportional to ( K - i + V ) R { 2 is added to the previous value already accumulated in the counter. 80 After stopping the counter, S7 is opened which causes the voltage V f j to remain on C . A l s o , F F 1 is reset to initialize F F 1 and F F 2 for conversion in the next integration 3 sub-window. A s shown in Appendix C , the relationship between the final state of the counter, N, and the average current over time T for H C I ( Y ) ( Y = A or B ) is obtained as follows: Nry) = K(Y) Jo I*dt + 0{Y) + E(Y) (4.5) where K is a constant factor, O is the offset value, and E is a random number resulting from A D C quantization noise Q. E( ) can be shown to have a uniform distribution in the range Y [0,1) with a mean of 0.5 and a variance a = ^ (see Appendix C ) . Sec. 4.2.5 describes E how K and O can be obtained through calibration. 4.2.5 Double-phase B I C I two-point calibration From F i g . 4.3 and Eqn. 4.5, N is obtained below: N= N N= K A)Iohdt (A) + N {B) + 0 { {A) + (B) Jo ^ K Assuming K( ) A = K( ) B = K, 0( ) A d = 0( ) B t + E + 0(B) + (4.6) (A) E (B) = O, and E = E( ) + E( ), the following A B relationship results: N = KTl +0 + E (4.7) where 0 < E < 2 (from Appendix C). For large values of M, N is a large number, therefore E is negligible and can be ignored. 81 To calibrate the integrator circuit, two known D C current signals, Ia and I , c2 are applied to the integrator circuit, and the calibration is performed as explained in Sec. 3.2.4. The precise D C current I i has to either be generated on-chip or be supplied from off-chip. c I c2 can be generated using a properly matched current mirror I c2 4.2.6 = nl i. c B I C I accuracy To achieve a high measurement accuracy, sources of error must be identified and their i m pact minimized by design. Factors affecting the measurement accuracy of the integrator circuit are as follows: 1. A s shown in Appendix C , C\, C , C , and I 2 3 ramp variations and the propagation delays in the comparators, flip-flops and the gates affect the factors K and O in Eqn. 4.6. K and O can be determined using a two-point calibration scheme (obtaining N for two known I values). Therefore, as in single-phase B I C I the process, temperature and power supply variations affecting K and O w i l l not affect measurement accuracy 2. The error due to clock feedthrough associated with the switches in the circuit can be minimized as described in Sec. 3.2.5 3. The error term E in Eqn. 4.6 is between 0 and 2, whereas the number N is much larger for large values of M. Therefore, E is negligible 4.2.7 Circuit implementation Assuming that the integrator circuit is to be used in an application where the maximum average current in one period of <> / is 120 \xA and the available C L K frequency is 20 M H z , the 82 following parameters were chosen to design the integrator circuit: • T = 1 ms, T = 1 ps, M = 1000, s • T s ( e / / ) = 0.5 ps, T • fcLK = 20 R - 0.5 p, MHz, • Iramp ~ 11.2^fA • Counter size: 18-bits These parameters imply Ci(yi) = Ci(B) = 30pF. The transistor level schematic of the main circuit and the comparator [100, Chapter 26] are shown in Figs. 4.6 and 4.7, respectively. The component values and transistor sizes are shown for critical components. These values have been chosen to achieve reasonable integration accuracy (error < 1%) as explained in Sec. 4.2.6, and to reduce the circuit area. In each H - C I block, 4> and <f> are non-overlapping control signals constructed from a b <j>. They are used instead of 4> and <f> in F i g . 4.5 to avoid sample and hold errors [97]. The total area of the circuit is 72500 (pm) . This is equivalent to the area o f a digital 2 circuit consisting of 280 N A N D gates in a 0.35 \im digital cell library. 83 I Short-time I analog integrator V iD D - .t/7Cr l"*50/0.6 —*— <E>. 3 ftrl-ctri: i i6/o:6: 50/0:6-. :2 : P .10/1. V i •T ' 16/0.6 .1- • 1_ - J l 7 k. <+* :;!! O .1 ' j: 1/ XI1 4 FF3 #^ - T J . . Q. elk . >•••<Hr S& H : •Ji ••ti m Q clr D c l k 'l' < ° b Q v 7 clr O D elk < Figure 4.6: The transistor-level schematic of the half-wave integrator circuit ( H C l ) 84 4.3 Simulation and Experimental Results The Cadence SpectreVerilog mixed-signal simulator was used to simulate the integrator circuit described in Sec. 4.2.7. Table 4.2 reports the simulation results for the average current measured by the circuit for a set of 13 different current signals, each with different waveforms, frequency, amplitude, and offset values to test the performance of the circuit for a wide range of input signals, described in Table 4.1. Signals D C 3 and D C 6 are used as calibration signals. The second column in Table 4.2 reports the true average current for each signal, while the fourth column indicates the average current estimated by the B I C I . The relative error of the estimated average current is 85 Name Waveform Parameters DC1 DC2 DC3 DC4 DC5 DC6 DC7 DC8 SIN1 DC DC DC DC DC DC DC DC sine SIN2 sine SIN3 sine TRG1 triangular TRG2 triangular TRG3 triangular SQ square = 10/i A = 17// A I c = 25// A IDC = 36/i A I c = 53ApA I = 83.2/x A IDC = 105.6// A IDC = 122 Ap A f=l M H z , D C offset=36 pA, Amplitude=15.5 pA f=4.3 kHz, D C offset=87.5 pA, Amplitude=20.6 pA f=101 kHz, D C offset=20 pA, Amplitude=10 pA f=35.7 M H z , D C offset=50 pA, Amplitude=20 pA f=20 kHz, D C offset=65 pA, Amplitude=45 pA f=4 kHz, D C offset=74 pA, Amplitude=30 pA Shown in Fig. 4.8 IDC IDC D D DC Table 4.1: Double-phase B I C I test signals given in the last column. Simulations indicate that the B I C I provides a very good accuracy (< 1% error) for all the current signals chosen. 4.4 Conclusions This chapter presented a mixed-signal built-in current integrator (BICI) used to perform current integration for the purpose of analog block testing. The B I C I generates a digital signature by averaging the current over a programmable time window. 86 'I (HA) 60 10 " t ( Hs) 12 16 Figure 4.8: Current waveforms for validating the operation of the integrator circuit The B I C I requires small area (equivalent to a circuit consisting of 280 N A N D gates). B y using any L S F R or register already available on chip (e.g., as part of J T A G or digital B I S T ) to implement the counter needed for this circuit, a saving of 25% in area is possible. B I C I also yields a digital signature which is convenient to interface to standard digital external or internal A T E and standards such as IEEE1149.1. Our circuit provides good accuracy (error < 1%). The monitor is suitable for current-based embedded test application but also for on-chip power monitoring because it is compact and generates a digital signature. In addition, the B I C I generates digitized samples of IDD during the integration window. A d ditional processing of these samples may be used to generate more complex signatures with potentially higher fault coverage. 87 Waveform True I N DC1 DC2 DC3 DC4 DC5 DC6 DC7 DC8 SIN1 SIN2 SIN3 TRG1 TRG2 TRG3 SQ (M) 10 17 25 36 53.4 83.2 121.7 105.6 36 88.67 20 50.1 65 74 22.63 2740 3403 4157 5196 6825 9634 13322 11778 5181 10142 3690 6505 7925 8763 3929 I estimated (fiA) 9.9 17.0 25 36 53.4 83.2 122.4 106 36 88.6 20 50 65 73.9 22.6 100(A7/7) 1 0 0 (Cai. point) 0 0 0 (Cai. point) 0.6 0.4 0 0.07 0 0.2 0 0.14 0.1 Table 4.2: Simulations of average current measurements by double-phase B I C I 88 C h a p t e r O n - C h i p J i t t e r S p e c i f i c a t i o n T e s t i n g H i g h - P e r f o r m a n c e 5 o f P L L s This chapter presents a jitter measurement and generation circuit for B I S T of P L L s . The circuit satisfies all the conditions for a practical B I S T circuit described in Sec. 2.2.4. The measurement circuit is fully digital and automatically synthesizable, occupies an area equivalent to 1200 2-input N A N D gate, provides a resolution of approximately lOps ( ~ l / 5 of a gate delay in a standard 0.35 fim technology), and generates a digital signature which can be read out by an inexpensive tester for further analysis to obtain the jitter characteristics. The remainder of this chapter is organized as follows. In Sec. 5.1, various jitter specifications are defined. Sec. 5.2 describes the jitter measurement circuit. Sec. 5.3 details the jitter generator circuit. Sec. 5.4 outlines ways in which the jitter generation and measurement circuits can be used for testing various jitter specifications of P L L s . Sec. 5.5 contains the circuit implementation details. Sec. 5.6 reports some simulation results, and Sec. 5.7 concludes the chapter. 89 5.1 Jitter Definitions The definition of jitter varies depending on the fields of application. In sequential circuits, e.g., C P U s , jitter is defined as the variation of the clock period, known as cycle-to-cycle or period jitter. Such variation is best modeled as a frequency modulation of the clock signal. More formally we can write: V (t) FM = sgn[sm( f \ Jo l 0 where VFM(£) ^ + lj{t) )dt)] is the clock signal, T is the average clock period, Tj(t) 0 (5.1) is the frequency modulating jitter signal and sgn[x] is the sign function: sgn[x] 1 x > 0 0 x < 0 (5.2) F i g . 5.1(a) illustrates how the period jitter samples are collected by measuring the duration of each period of the signal I N I . In serial communication applications, jitter is defined as the short-term variations of a digital signal's significant instants, e.g., rising edges, from their ideal position in time [20]. Such jitter is often often denoted as accumulative jitter and is described as a phase modulation of a clock signal. Formally: VpM{t) = sgn[sin(u t 0 + u> Tj(t))] 0 where VpM{t) is the jittered clock, u> is the average angular frequency, and rj(t) 0 (5.3) is the phase modulating jitter signal. In a clock synthesis circuit, where the absolute jitter is i m portant, often a jitter-free (practically low-jitter) reference signal is used for jitter measurement. In such a case, the difference between the position of corresponding edges of the 90 signal (INI) relative to the reference clock (REF) indicates the jitter. F i g . 5.1(b) illustrates how accumulative jitter samples, TJ^ for i = 1,..., are collected. Sometimes, the relative jitter between two signals is of interest i f neither of the two signals is a jitter-free signal, e.g., in data recovery circuits. F i g . 5.1(c) shows how relative jitter between the edges of signal I N I and I N 2 is measured. IN1 (with jitter) Period Jitter Measurement IN1 perioch^ T T T jitter ^ ( >' ( >' ( )' J 1 J 2 J IN1 3 j(D J(2> \J T J(3) (a) IN1 (with jitter) IN1 Accumulative Jitter on Jitter REF flitter-free) Measurement IN1 edgea REF J(1) • J(2) • J(3) • T X X J(2) Z (b) IN1 (with jitter) IN2 (with jitter) Relative Jitter Measurement J(3) J(4) T X IN1 Relative jitter , IN2 J(1j > J(2) . J(3) < X % Z 'J(1> (c) J(2) T J(3) J(4) T X Figure 5.1: (a) Measuring cycle-to-cycle or period jitter, (b) Measuring accumulative jitter using a reference clock, (c) Measuring relative jitter For both period and accumulative jitter measurements, M jitter samples, Tj^ or r j ) (j (i = 1 , . . . , M ) are collected to calculate jitter characteristics, such as rms, peak-to-peak, or 91 frequency components. For example, the rms and peak-to-peak period jitter is obtained as: M-l 1/M £ \ Tj( -to-pk) pk 5.1.1 = max(Tj) - T] 0 (l) min(Tj) P L L jitter specifications The important jitter specifications for P L L s used in digital communication interfaces are intrinsic jitter, jitter tolerance and jitter transfer. These specifications are given in standards for each application (e.g., see [20] for S O N E T interfaces). 1. Intrinsic j i t t e r is defined as the jitter at the output of the P L L when the input is jitterfree. This is often expressed in terms of unit interval U I , which is defined as the period of a signal with a frequency equal to the average frequency of the original signal. For example in 155.54 M H z S O N E T network application, 1 U I is 6.429 ns 2. J i t t e r transfer is defined as the ratio of the output jitter to input jitter of the P L L as a function of frequency 3. J i t t e r tolerance is the peak-to-peak amplitude of the sinusoidal jitter applied to the input of the P L L which causes l d B power penalty (in terms of bit error rate) 5.2 Jitter Measurement Circuit ( J M C ) Here a digital circuit is presented which is capable of measuring jitter not only of P L L s , but of any signal with high resolution, as illustrated in F i g . 5.2. The core of this circuit is a 92 high-resolution time-to-digital converter ( T D C ) which measures a time interval T : d Td —tsTOP —tSTART (5.4) where tsTOP and tSTART are the time instances at which the rising edges of the S T O P and S T A R T signals occur, respectively. In this circuit, the Edge Sampler block controlled by the ES Controller selects the appropriate S T A R T and S T O P edges and passes them to the T D C . For measuring different jitter specifications, the Edge Sampler and the E S Controller have to be adapted accordingly while T D C remains the same. Examples of Edge Samplers (and their associated controllers) are given later i n Sec. 5.4 for cycle-to-cycle and relative jitter measurements. ES Controller (ESC) High resolution TDC Reference ref IN1 IN2 ln1 Edge Sampler (ES) START STARTJn STOP STOPjn Figure 5.2: Block diagram of the proposed jitter measurement circuit The T D C circuit details follow. However, before delving into the details of this circuit, the state of the art in T D C design is reviewed. 5.2.1 State o f the art i n T D C design A classic method of measuring a time interval Td is to start a counter at the beginning of the interval and stop it when the interval ends. The resulting number in the counter w i l l 93 be proportional to Td- The resolution in this method is the period of the clock controlling the counter. To measure intrinsic jitter of a high-speed P L L (e.g., 1 5 5 M H z clock synthesis P L L ) , where a high resolution in the range of 20 ps is required, a clock frequency of 50 G H Z would be needed! Obviously such method is not suitable for on-chip high resolution time measurement when the maximum clock available is i n the range of a few hundreds of M H z . In [102] a T D C based on the use of a delay chain as shown in F i g . 5.3 is presented. In this circuit, the output of the delay elements in the delay chain are set H I G H as the S T A R T rising edge travels through them. When the S T O P rising edge arrives, only the flip-flops with a H I G H on their D inputs w i l l have their outputs set H I G H . That is, the final flip-flop settings correspond to a snap shot of the delay chain at the time of the S T O P rising edge. Therefore the number of set flip-flops indicates the number of delay elements (N) that the S T A R T edge travels through before the S T O P edge arrives. Consequently, Td = tsrop — t ST ART = NTA + Tc + TQ where T A , the quantization step, is the delay of each delay element, 0 < TQ < T A is the quantization error, and Tc is a constant offset delay due to set-up time of the D F F s and any delay difference in the paths of the S T A R T and S T O P signals to the delay chain and the recording flip-flops. A delay locked loop ( D L L ) is used to calibrate the delay elements to a known delay T A = T j/M, re where T j is the period of a reference clock and M is the re number of delay elements. Such a calibration requires very good matching between all the delay elements in both the delay chain and the D L L . In [35] an alternative circuit is proposed to combine the delay chain and the D L L , hence obviating the need for element matching. In schemes mentioned above, the D L L and the controlled delay elements are analog. Eliminating the D L L and using digital gates as delay elements make the circuit fully 94 Delay-Locked Loop Charge Pump + Loop filter Phase detector H > — I DE1 *H DEM H DE2 " WDelay eTemerils " i Delay C h a i n START DEM Recording flip-flops STOP Clk Rst Clk 1 Clk Digital control circuit (Asynchronous) In1 Sync jClk Rst 1 In2 InM Peak-to-peak, RMS measurement Clk Pass/Fail D1 4 START r R2 A N-bit data (N < M) D3 I I : I I I _1._.1...J STOP Figure 5.3: Time digitization using a delay chain 95 digital. In that case, a two-point (instead of one-point) calibration scheme can be used to extract T A and Tc- The trade-off is decreased accuracy due to the quantization error associated with calibration reference inputs, as demonstrated in Appendix D . l (Eqns. 5.35 and 5.32). The resolution ( T ) of such methods without time interpolation is limited to one gate A delay at best. In a 0.35 /im C M O S technology, the smallest gate delay is approximately 50 ps, whereas a resolution and precision of about 20ps is required for functional testing of high-speed P L L s with 155 M H z center frequency[20]. A l s o , since this delay is dependent on process variations and temperature, the resolution in such schemes is not controllable. The authors of [36] propose the use of an array of D L L s to improve the measurement resolution, while those of [103] propose an R C delay line approach to increase the measurement resolution through time interpolation. Although resolutions in the range of 25ps (rms) have been reported in these papers, the design of the circuit requires a great deal of care because of the need for a high degree of matching. Also, the design and layout of the D L L need careful attention due to the presence of significant power supply noise in large mixed-signal ICs. In [37] a differential delay technique based on using two delay chains is used (Fig. 5.4). One chain is composed of gates (each with a delay of r ) , while the other is made of latches 3 (each with a delay of 77). The latch in chain 2 samples the signal at the z-th tap of the chain 1 ( A ) on the rising edge of the signal Fi. Since Fi is delayed with respect to Di, latch L 0 samples H I G H . Since r < 77, Di approaches passes Di and as time progresses until the edge on Fi g samples a L O W for i = N. In this method, the time quantization step is the difference between the delay of the delay elements in two delay chains: ?A = n - T g 96 (5.5) STOP (Jitter-free signal) Each delay= Tg I I Delay C h a i n 1 I DM 1 r\ i Each delay= T| I START (JJttered clock) i Delay C h a i n 2 L D Q •— D Qr»r Rst Lp J- Rst I-) Clk Clk Digital control circuit (Asynchronous) Clk J" Clk M 1 In2 In1 Sync \ D Q Rst L FM InM Peak-to-peak, RMS measurement Clk N-bit data (N < M) Pass/Fail T - T =N(1.- 1J START STOP / g (N: The number of set FFs) 1 *START F1 f S T O p I F2 ;F3 7—r~ START ! Ij i I From this point on the latches will sample '0' (N = 4) DI :D2 ;D3 I STOP L ^t 0 4j L set ; ^ 2 L-| set ^ L3 set Figure 5.4: Time digitization using differential delay technique 97 Since gates and latches are very different structures, 77 and r may differ significantly, makg ing it difficult to achieve high resolution (in the range of 20 ps or less). A l l the schemes mentioned above require good matching of the elements in the delay chains, something which is difficult to achieve within an accuracy of 1% under typical process variations. A s the time interval to be measured becomes longer, more elements must be added to the delay chains, making it even more difficult to assure matching of delays in the chains; when more elements more added, the elements w i l l have to be placed further apart and more routing delay w i l l have to be accounted for. Therefore, these schemes do not provide good T D C linearity. In addition, they do not lend themselves well to automatic place and route. Furthermore, the resolution is set by the process parameters on each chip and cannot be controlled or adjusted. In the following section, we introduce a high-resolution T D C which provides good linearity, is automatically placeable and routable, and has an adjustable resolution. 5.2.2 High-resolutionT D C Fig. 5.5 illustrates the block diagram of the proposed T D C circuit. The Time Quan- tizer (TQ) block quantizes time with a quantization step of which is set by the Resolu- tion Adjustment ( R A ) block to a value less than a programmable threshold. This threshold is supplied to the circuit as a 16-bit digital number. Since the maximum time interval measurable by the T Q is limited, the Range Extender (RE) block is used to extend the capability of the T Q to measure longer time intervals. The Calibration Controller (CC) calibrates the T Q using a reference low jitter clock to provide a precise estimate of T - The T D C Controller A (TC) controls the communication and sequence of operation of the different blocks. After 98 Range Extender (RE) TDC Controller (TC) START STOP START STOP Quantizer (TQ) To Edge Sampler | Ref (jitter-free)^ T i m e n-bits Calibration Controller ref (CC) StartCal EOCal -A Resolution Adjustment (RA) V. Block Figure 5.5: B l o c k diagram of the proposed T D C circuit resolution adjustment and T Q calibration, the T C instructs the Edge Sampler controller to pass jitter samples as time intervals to the T Q for measurement. The following section describes the principle of high resolution time measurement and reports the details of each block. 5.2.3 N o t a t i o n a n d definitions The notation and definitions used throughout the remainder of the chapter are listed next. Note that any variable denoted by t refers to an instant in time, T refers to a time interval, and T refers to a time delay associated with a physical structure in the circuit, e.g., gates, routing, etc. • tSTART'- The time when the S T A R T signal is set H I G H 99 • tsrop- The time when the S T O P signal is set H I G H • Tj, = tsrop — tSTART- the time interval to be measured • c l k A : The output signal of oscillator A (Osc-A) • c l k B : The output signal of oscillator B (Osc-B) • T (T ): A B c l k A ( c l k B ) period • tx(i)'- The time when the i-th rising edge of c l k X (X = A or B) occurs. • TA = TA — TB'- The time quantization step. This is also the resolution of the T D C . • N: The final T Q number indicating Td value • M (M ): A 5.2.4 B The output state of the k-bit counter CntrA(CntrB) T i m e quantizer The circuit proposed here uses a differential method to obtain high resolution. It relies on the difference between the periods of two oscillators for time quantization rather than on gate delay, therefore, reducing the need for circuit matching. In fact, the circuit is made virtually insensitive to mismatches by using a period adjustment scheme discussed in Sec. 5.2.7. This makes the circuit fully synthesizable and automatically placeable and routable using standard digital circuit electronic design automation ( E D A ) tools. The operational principle of the T Q is as follows. Assume Td as defined in Eqn. 5.4 is to be measured. F i g . 5.6(a) shows the schematic of the T Q circuit which is the core of the jitter measurement scheme. It consists of two ring 100 oscillators, one flip-flop, and one counter. The resolution of the scheme is dictated by the time quantization step, T A , obtained as: T = T- A T A (5.6) B To conceptualize the operation of T Q , assume that in a sample chip, T A is a small time about 20 ps. Sec. 5.2.7 describes a circuit which automatically adjusts the resolution to guarantee the required resolution under typical process and temperature variations. The waveforms in F i g . 5.6(b) illustrate the operational principle of the circuit. Oscillators A and B (T B < T ) start oscillating at the rising edge of S T A R T and STOP, respecA tively. The counter M A I N starts counting at the S T O P rising edge. The output of oscillator B , c l k B , is sampled at the rising edge of c l k A by the D flip-flop E O C J D F F to set the end-ofconversion flag, EOC_Flag. Assuming T is larger than T , EOC_Flag w i l l be L O W for the d A first cycle of c l k B . However, for every cycle of c l k B , the i-th. rising edge of c l k B approaches that of c l k A by T , until eventually the A^-th rising edges of c l k B precedes that of c l k A by A the setup time of E O C JDFF, causing EOC_Flag to be set H I G H : tB(N) where T E O C = t (N) A (5.7) ~ TEOC — TQ is the setup time of E O C _ D F F , and 0 < T < T Q is the quantization error. A A t this time, the M A I N counter stops and the digital control circuitry is able to process the output of the counter, N, which indicates the value of T . The t ( ) d A N and t (N) are obtained B as below: ^A(N) = t ST ART + T + NT (5.8) . *B(JV) = tsTOP + T + NTs (5.9) A B 101 A Figure 5.6: Time digitization using two oscillator period difference method 102 where T and r are delays from S T A R T and S T O P signals to the D and C L K inputs of A B E O C J D F F , respectively. From Eqns. 5.7, 5.8 and 5.8: tsrop - tsTART = N(T - TB) - T + T - T OC - TQ A B A (5.10) E Therefore: NT A where Tc = TB — T + r c A EO = T + T + T + T d c Q (5.11) R is a constant offset time, and TR is a random error term due to intrinsic jitter of the gates and flip-flops (refer to Sec. 5.2.10 for more details). The setting of EOC_Flag is also used by the T D C controller to initiate processing of the data and to initialize measurement of another time interval. Sec. 5.2.6 demonstrates how to estimate T A and Tc through a two-point calibration scheme, while Sec. 5.2.10 provides an analysis of the random errors terms TQ and TR in Eqn. 5.11. Completing one measurement requires some time, denoted by T - T meas meas depends on the value of the T . Assuming that the error terms in Eqn. 5.11 are negligible, then T + d Tc = NT A • Since it takes d cycles of c l k A to perform the measurement, the required measurement time is: ATHT T ~\~ Tc f-p meas — ^ J-A — d Tp J-A 'A For example, i f Tc = 0, measuring an interval of 1 ns (T d = Ins) with a resolution of T A = 20 ps (N = 50) requires 507^ of time. If TB = Ansec, the measurement time is approximately 200 nsec. 103 E O C J D F F metastability F r o m Fig. 5.6 E O C L D F F is used to set E O C _ F l a g indicating that the measurement is complete when Eqn. 5.7 is satisfied. If for some value of Td, TEOC — T /2 mw where T mw < t (N) ~ tB(N) < TEOC + A T /2 mw is a small time interval, E O C L D F F may exhibit a metastable behavior. This means that the E O C J D F F output might take significantly longer than r ^ _ _ g to set its outc put H I G H . T mw E, T mw i o is called the metastability window of the E O C _ D F F . A s shown in Appendix is less than 0.01 ps for a flip-flop is a 0.35 \im C M O S digital cell library. The ex- cessive delay due to metastability can cause a logic error in synchronous circuits with asynchronous inputs [104, Sec. 3.11]. However, in the T Q , i f this delay results in no decision after the 7V-th rising edge of c l k B , the decision to end the measurement w i l l be made by E O C _ D F F at the next rising edge of c l k B , i.e., on (N + l)-th edge. This is because the relative delay between the N + 1-th edges of c l k A and c l k B w i l l increase by T A which is larger than T , mw and therefore, no metastable behavior can occur on the successive edge. A s discussed in Sec. 5.2.10, since T mw is less than 0.01 ps, it does not significantly affect the precision of the T Q . E O C - F l a g is also used by the T D C Controller to control the sequence of operations in the T D C . Therefore, synchronizers must be used to ensure the reliable operation of the synchronous circuit in the T D C controller [104, Sec. 3.11]. In the implementation of T D C described i n Sec. 5.5 a single flip-flop (TQEOC_sync_DFF in Fig. 5.22) is used for synchronization. 104 5.2.5 Measurement range extension F r o m the waveforms in Fig. 5.6(b), it can be concluded that i f T > T d A — DT B (D is the duty cycle of c l k B ) , E O C L D F F w i l l sample a H I G H at the second rising edge of c l k A , which signals an end-of-conversion erroneously. Also, i f T < —Tc, the first rising edge of c l k A d w i l l sample a H I G H regardless of the value of T . Therefore, the valid measurement range d of Td for this circuit is: -T c < T < T d A - DT (5.12) B To extend this range, a Range Extender (RE) circuit is used. The R E block ensures that the i-th rising edge of c l k B and c l k A are within the valid measurement range of the T Q (given in Eqn. 5.12) before allowing E O C J D F F in the T Q to start sampling c l k B at c l k A rising edges. The R E block consists of three flip-flops, two counters and a £>bit comparator as shown in Fig. 5.7(a). The waveform diagram of the circuit is also given in Fig. 5.7(b). This block generates a flag signal (REJFlag) when t ^ — t (i) < T \, where —Tc < r A T — DT . A B A Ax < The details of the R E block operation follows. B The signal c l k A is delayed by r \ and T A A1 + r , using the delay buffers D b u f l and A2 Dbuf2, to generate c l k A l and c l k A 2 , respectively. The two k-bit counters, C n t r A and C n trB, which are initialized to 1 and 0, count the number of rising edges of c l k A 2 and c l k B , respectively. Fig. 5.7(b) shows different waveforms in the circuit for T = 2.6T . A s shown d A in Fig. 5.7(b), the number in C n t r A (i.e., M ) remains larger than the number in CntrB (i.e., A M) B as long as t ^ equal to M A2 B - t B{i) > T AI + r . A2 When t A2{i) - t B{i) < r A1 + T , M A2 A becomes for a short amount of time, causing the comparator to generate a pulse which becomes wider at the subsequent c l k B rising edges. This pulse, when sufficiently wide, sets the REJFlag, allowing E O C J D F F to start recording the relative position of the rising edge 105 To EOC_DFF rst input clkA Dbufl Dbuf2 clkA1 clkA2 k-bit counter (CntrA) > rst Irb ^ > k-bit comparator r cmp_out D Q Esampl Ext..DFF1 clkA1 Cl k rst Yrb D Q Esamp2 Ext_ DFF2 clkA2 Clk rst Irb k-bit counter (CntrB) clkB * rst V V Irb RE-Flag 0 Q clkA2 Clk rst Irb (a) -r„—. clkA clkA1 clkA2 (Idealp • 2 t 3 n 4 . 5 . 6 i 7 . 8 i 9 • 10 i 11 • 12 • 13 i 14 • 15 i 16 i 17 • 18 • 19 22i 2023I1 2I1 24 | ! CntrA < 3-bit 6 71: o I: 2 3 4 5 ; 6 ; 7. : o ; 1 2; ; 3 4 ; 5 6 ; 7 ; 0 1 2 3 4 ( 2-bit ©: ©: ©: ©: © : © : © © :©I:©I: ©I ©:: ©: 0 ©: ©: © © © © © clkB i \\\ f Ideal 0 2 . 3 i 4 .5 . 7 i 8 . 9 . 10 1 12 i 13 i 14 .15 . 16 i 17 . 18 .19 i 20 21 .22 •£3 . i 1 . CntrB < 3-bit 0 1 2 j3j 4 j5 ; o ; 1 ; 2 3; | 4 ; 5 | 6 |©i o ; 1 ; 2 ; 3 ; 4 5 ; 6 ;;7 | ( 2-bit if 2-bit © 0 ©: ©: ©: 0 ! ©: ©: ©! ©: ©: ©| ©; ©: ©: ©: ©: © :©: :©: ©: lounter used" \ J short glitches that might. J cmp_out i ) \ ^setlEsamp2 erroneously ^ '!>K r a n d o m short glitches that might random glitch Esamp2 set Esampl erroneously \ glitch 4 A Esampl ER_Flag •eq (b) Figure 5.7: Measurement range extension to (2 k 106 l)T A of c l k A and c l k B . Appendix F presents the operation of the R E block more rigorously from a mathematical viewpoint. Since the R E block is asynchronous, a novel time diversity sampling technique is used to ensure valid sampling of the comparator output. O n each rising edge of c l k A 2 , the output of C n t r A changes. Since the C L K - t o - Q delay for each output bit of C n t r A w i l l differ for a short period of time after the rising edge of c l k A 2 , the number M A can a have tran- sient random value. This random value, i f equal to MB, may result in a short pulse at the comparator output. Since this short pulse occurs after the rising edges of c l k A l and c l k A 2 , it w i l l not be sampled by E x t J D F F l and Ext_DFF2. However, such random glitches may also occur after the rising edge of c l k B due to C L K - t o - Q delay differences in the output bits of CntrB. These glitches, i f close to the rising edges of c l k A 2 (or c l k A l ) , may be sampled by Ext_DFF2 (or E x t _ D F F l ) . Choosing T A2 such that it is larger than the maximum width of such glitches guarantees that Ext J D F F 1 and Ext J D F F 2 w i l l not be set H I G H in the same cycle of c l k A 2 due to such glitches. A s t ^ A2 — t {i) becomes smaller, the cmp_out B pulse becomes wider until it is also sampled by E x t J D F F l . A t this time, the R E J ^ l a g is set H I G H . In summary, when E s a m p l and Esamp2 are both set H I G H , it is concluded that the cmp_out pulse has been wider than any possible glitch due to the asynchronous nature of the R E block. From the above discussion, r A2 is chosen such that it exceeds the maximum glitch width. The glitch width can be reasonably assumed to be 50% of TCLK-IO-Q , where T LK-toC rs, the worst case C L K - t o - Q delay for an output bit of CntrB. This assumes that the variations of TcLK-to-Q, denoted by variations. The actual value of is less than Q.2bT LK-to-Q ATCLK-IO-Q, ATCLK-IO-Q C under process can be obtained by running monte-carlo anal- 107 ysis on the D flip-flops used in CntrB. T must be within the range in Eqn. 5.12. We chose AX r A1 = —Tc 4- 3 T t s e u p (T is the maximum setup time for E O C JDFF) i n a standard 0.35 setup / i m C M O S process since this value is well within the required range. It is worthwhile to note that this R E circuit does not affect the precision or accuracy of the measurement because it only ensures the closeness of the i-th rising edges of c l k A and clkfi without interfering with the path of c l k A and c l k B signals to E O C _ D F F , which is the critical path for precision and accuracy. F r o m Fig. 5.7(b), the range extension achieved by this circuit is Td < (2 — l)T . In k A this case, since Td = 2ST , both 3-bit and 2-bit counters for CntrA and CntrB can be used. A This is also evident from the mathematical analysis of the R E given in Appendix F . 5.2.6 Calibration F r o m Eqn. 5.11, the relationship between N and T is linear. Therefore, knowing the values d of Tc and T suffices to estimate Td from the number N. To estimate Tc and T A , two accuA rately known time intervals T / i and T / (typically supplied from off-chip) are measured c a c a 2 and the resulting T D C numbers, Ni and N , are recorded: 2 N llTA = T u + Tc + TQI + TR\ N 12TA = T l2 + Tc + TQ + TR ca CCI ca ca 2 (5.13) 2 where T Q I and TQI are the quantization errors, and Tm and T R are the random errors asso2 ciated with measuring T n and T / , respectively. These two measurements are used in a ca c a 2 two-point calibration scheme, described in Appendix D . l , to estimate Tc and T A . This A p pendix also shows how the random terms T Q I , T Q , Tm and T R in Eqn. 5.13 result in T 2 and T estimation errors, denoted by T A Ce and T 108 A e 2 c . From Eqn. 4 D , the standard deviation of TAe, &T , AC is less than 0 . 1 % i f T d and T i are chosen such that ./V ( - A ^ i > 200. H o w c a ca 2 ca ever, Eqn. 7 D shows that the standard deviation of T b , a e T c e 2 , can be several T A ' S , which results in measurement accuracy degradation. This inaccuracy can be decreased using the n-point calibration scheme described i n Sec. D.2. In this calibration scheme, N is obtained for n calibration time intervals T /(j) = 0, T f,..., ca re (n — l ) T / for i = 1 , . . . , n. The r e correlation between the n measurements is used to shrink the range o f Tc variations and provide a more accurate estimate of Tc • Ref IN1 START D Q ST._DFF Clk rst MUX1 - rst s Cai Ref J 1 J U U U 1 I I K=0 (K-1) cycle delay generator SP_in (K_DGen) Clk K= 1 MD SP_DFF Clk rst STOP Q Ref >0 MUX2 IN2 11 S K=2 I rst Cai (a) Figure 5.8: KT (b) ref interval selection circuit Since a low-jitter reference clock is often available on the chip, for two-point or npoint calibration it is convenient to choose T call 109 =T , T reJ cal2 = 2T ,..., ref T caln = nT . re} A circuit that allows reliable generation of KT j re intervals is shown in Fig. 5.8(a). In this circuit, when Cal=0, the R e f signal is connected to the elk inputs of S P J D F F and ST JDFF. Since D input of ST J D F F is always H I G H , S T A R T is set high at the first rising edge of the Ref signal. The S T O P signal always is set H I G H one R e f cycle after SP J n turns H I G H . Since the K J D G e n state machine block sets S P J n to H I G H ( K — 1) cycles after the rising edge of the R e f signal, K R e f cycles delay results between the edges of S T A R T and STOP. The waveforms in Fig. 5.8(b) illustrate the operation of the circuit for K = 0,1 and 2. Constant delay is generated in the path of calibration signals in this circuit. The same delay w i l l be used in the actual measurement, except for the term ATMUXI — Ar ux2, M which represents the variation of the difference in propagation delays from 10 and II inputs to output in the multiplexers M U X 1 and M U X 2 , respectively. If the mismatch is significant, estimated value for Tc during calibration w i l l not be the same as the one used in actual measurements, resulting in additional error. Therefore, the Ref signal paths to elk inputs of S P J D F F and ST J D F F must be matched to the I N I and IN2 signal paths to the same inputs, respectively. Here, it is assumed that this matching is achieved, and therefore the term ATMUXI — ATMUX2 is negligible. This matching, however, is not required in a differential measurement method because in this method Tc does not affect the measurement accuracy or precision (refer to Sec. 5.2.11 for details). 5.2.7 Automatic resolution adjustment The circuit in F i g . 5.6 provides a high resolution, i.e., a small T , A by generating a small difference in loop-around delay in the two oscillators A and B . This small delay can be achieved by using additional capacitive loading (CL) at the output of a logic gate in either 110 of the ring oscillators. However, any mismatch between the gate delays and interconnect wiring in the oscillators A and B also contributes to T . This mismatch can cause a signifiA cant increase i n T A , resulting in resolution degradation. The mismatch might also result in TB > TA, causing a measurement error. To overcome the effects of mismatch, we use the resolution adjustment technique shown i n F i g . 5.9. Using this technique, TA and T g are controlled digitally [105]. To do so, a series of digitally controllable capacitive loads are connected to a number of nodes in both oscillators A and B through switches. Each load and its associated switch form a controlled load ( C L ) cell. Turning O N the switch in a C L cell connected to a node in one of the oscillators adds some loading to the corresponding nodes, resulting in longer output oscillation periods. C L cells can be designed and added to the standard digital cell library of a technology to preserve the possibility of automatic place and route. The actual design considerations for the C L cells are addressed in Sec. 5.2.8. The details regarding the control of the oscillators output period are as follows. Assume that some C L cells are activated. The calibration control circuit performs calibration using two known time intervals T j and 2T f. re then subtracted to yield the difference N A negligible, N A re = N — N . Assuming the measurement error is 2 r and T are related by: A Since T f is constant, a larger N re A indicates a smaller T A . Assume a resolution of T h is required, therefore: t Tf re The two resulting counts are = NthTh 111 icij f<*5 \ci°, PI ! iC,-r- 4 ft t>»<- Counter Clk n rb r rb rb rb Oscillator B clkB r STOP rb r £ H > clkA r Irb D ^ £ I rb X A-I •// x Oscillator ^ vi A > D Q 1-iEOC-Flag EOC_DFF| Clk rst "rb ^ Digital control circuit (Synchronous) CLK rb START I CLK Resolution Adjustment Controller a„ a, cells Figure 5.9: Automatic resolution adjustment circuit 112 b. fe where N h is the T D C output number associated with the resolution T . t th loading condition, If, for a specific is smaller than the pre-determined threshold N h, the switch in a C L t cell is turned O N and A^A is obtained again. Turning O N a C L switch increases T A allowing for smaller TA = TA — TB- For example, assume T A or TB, = 3.255ns and T B = 3.205 ns. Therefore, T A = 50 ps. If activating a C L cell in the oscillator B results in TB = 3.235 ns, a better resolution of T A = 20 ps can be obtained. The resolution adjustment ( R A ) control circuit searches for the vectors a = a ... a/_ 0 and b = b ... 6;_i such that the only C L cells activated (switch turned O N ) are those that 0 result in a T A < T h (or equivalently A^A > N h)- The algorithm used by R A block depends t t on how much delay each controlled load adds to TA or TB when it is activated. This algorithm is given in Sec. 5.2.9. Two different approaches in designing C L cells, the uniform toad and the incremental step load, are described in detail. U n i f o r m load One method for resolution adjustment is to use the same cell for all the controlled loads CLf,i = l,...,l and CLf,j = 1 , . . . , / . The switch and the loading capacitor of each C L cell should be designed in such a way that when a cell is activated, the nominal added delay to TA or T B is less than 0.5T h- This can be done by choosing a correct size for the pass t transistor by implementing the switch and/or the capacitor value. Therefore, as a (b) goes from 0..0 to 1..1, TA (TB) steps through / values which are T step T A = T A0 - T B0 + [ONE(a) = T A0 - T B0 + \[ONE(a) 113 - = 0.5T<^ apart. Therefore: ONE(b)]T step - ONE(b)}T th (5.14) x where TAO = T \a=o..o, TBO = ^fi|? o..o A a n ( = * ONE(x) is a function yielding the number of ' l ' s in a binary number x. If the initial difference between TA and is in the range (—1/2(1 — l)T ,1/2(1 i.e., (T o — TBO), A — l)T h) there exist two vectors a and b which w i l l th t result in T < T . A th Eqn. 5.14 assumes an ideal case where the T and TB change with constant step of A T step = 0.5T h as ONE(a) and ONEib) t increase. O n a real chip it is difficult to guarantee the uniformity of the steps because the value of T stev varies with process variations, and also because it is affected by turning O N the neighboring C L cells. Assume that T (i) < step T step < T ( ), step u where T {i) and T ^ step step are the lower and upper 3<r thresholds of T u) step probability density function (PDF) obtained through monte-carlo simulations of loaded ring oscillators. A s long as T ( ) step < T h, a and b that satisfy the resolution requirement can be u t found under process variations if: —lT p(i) < T o — TBO < lT (i) ate A (5.15) step If T (\) is small relative to T h (e.g., 0.2T h), larger values o f / must be chosen to ensure siev t t valid resolution adjustment for large T o—TBO- Using 3<r thresholds of T A and T 5 i e p step P D F for T (i) step ( ) , 99% of the manufactured circuits are guaranteed to meet the required resoluu tion, whereas, using 6a thresholds guarantees a successful resolution adjustment for 99.94% of the circuits. The maximum time for resolution adjustment, T j( ), ad max occurs when all 2(1 + 1) combinations of a and b with different number o f ' l ' s in a or b have to be tried before the required resolution is achieved. Therefore: T dj(max) a 21-1 } y T lH,^ i=0 ca 114 where T iib{i) is the time needed for a two-point calibration for the i-th state of a, b. Since ca Tf re and 2T j re are used for calibration: _ 37^+27^ where T (i) is the T A for the i-th selection of a and b. A For small values of T h, a large number of C L loads might be needed. This is because t the T tep must be small and a large / is required to guarantee successful resolution adjustment s for possibly large TAO — TBO- In that case, the incremental step design (described next) is preferable. Incremental step load Another method for delay control is to design C L cells such that where T A CL is the delay added to the total ring oscillator A loop delay where CLf is acti- vated and 0 < £ < 1 is a constant. Such design allows for different resolution adjustment steps. For example, i f = Sps and £ = 0.5, then T A 40.5 ps, 60.75 ps fori = 1 , . . . , 6. Therefore, assuming T A T A CL can be adjusted by steps of T step = ±T A, CL ..., ±T A. CL CL CL = 8ps, 12ps, 18ps, 27ps, = T B CL for % = 1 , . . . , / , T This method effectively provides different levels of coarse and fine resolution adjustment steps. This enables the circuit to achieve very fine resolutions (less than 5 ps in a 0.35 fim C M O S process) while reducing the average adjustment time T # , using binary-like search algorithms explained Sec. 5.2.9. a To guarantee the resolution adjustment, the maximum of the smallest adjustment step should be less than T . th The maximum of the smallest adjustment step, denoted by , T A CL l(u) 115 A can be chosen as the upper 3a threshold of T A CL P D F under process variations, xi has to be selected such that under process variations, for any a, the difference between T A for a and a + 1 is less than T h- Ideally, xi could be derived from 3cr variation of t T A CL (i = 1 , . . . , I), however, since this derivation is cumbersome, an arbitrary value of £ = 0.5 is chosen for the implemented circuit reported in Sec. 5.5. 5.2.8 C o n t r o l l e d load ( C L ) cell design osc Figure 5.10: C L cell evaluation test bench In this section, advantages and disadvantages of different C L cell design styles are described. The evaluation test bench is the circuit shown i n F i g . 5.10, where a ring oscillator is loaded by 6 C L cells (/ = 6) and the output oscillation period, T osc is measured for a = 000001,000011,000111,001111,011111, and 111111. Then difference between T osc To = T osc and 15=000000 is calculated. This difference is denoted by Tdij. A standard 0.35 [im C M O S technology has been used for evaluation purposes. F i g . 5.11 illustrates different design styles for C L cells and their simplified models. 116 r - h Ctrl • r con P con P Ctrl ] |—i 4(1/0.6(1 -L ' 10 fF Ctrl ; •— 4n/o.6n •-HE 1 < M, L 4jl / 0.6n i (al) con i i con P T 1 0 , F (cl) felj con P Ctrl ! Ctrl > D-r- Ctrl Ctrl • ga; gb (L> R . :T_ -srs; V (a2) Ctrl• Dr--. db(L} i (c2) Ce2j Figure 5.11: Different C L cell styles: (al, bl, cl, dl, el) Circuits; (a2, b2, c2, d2, e2) simplified models The important design consideration for C L designs are: 1. The cell area for achieving a unit of T<HJ. This area should be minimized 2. The sensitivity of T j to control voltage (V i) di ctr T , _ ATdif ov.«" . — T Q variations: V trl di c AV v dif ctrl If this sensitivity is high, V i noise w i l l add jitter to c l k A and c l k B when the C L ctr cells are connected to oscillators A and B in F i g . 5.6. This, in turn, increases T R in Eqn. 5.11, which translates into a loss of precision in the T D C . In the following, C ( ), gs X C (x), gd C (x), gb 117 C () dh X and C ^ ) denote the gate-source, sb X gate-drain, gate-bulk, drain-bulk and source-bulk capacitances of the transistor Mx, respectively, where X is a transistor identifier. The voltage-controlled N M O S capacitor design (style a) has been proposed in [105] to implement a controlled delay line. Although it provides a relatively large T ij in a small d area, the T j is quite sensitive to V i because the equivalent capacitive loading of the C L di ctr cell is a function of V i. Values for S *' are listed in Table 5.2.8 for the different C L cell ctr v t styles for comparison. In F i g . 5.11(bl), a capacitor is used as the load. A simple model for such a C L cell, shown in Fig. 5.11(b2), consists of an ideal switch S, the switch resistance Rs, the switch drain capacitance C (s) = C b(s) + C {s), the switch source capacitance C (s) = C &(s) + d d gd s s Cg (s), and the load capacitance C L - Rs is in the range of a few tens of MVt when the switch S is O F F and a few KVi when it is O N . A s is evident in the model, the C i ) and C < ) d S S a r e S also loading the oscillator. Since Cdb(s), Cgd(s)> C b(s), and C (s) are functions o f Vctri,s gs this style has a high T ij sensitivity to V i. In fact, any design with the switch connected d ctr to the oscillator node suffers from this high sensitivity characteristic. A n alternate circuit and its simple model are shown in Fig. 5.11(d) and (c2). In the model, C (s) = C f ) d dh S + C (s)gd This design provides a low T dii sensitivity to V i (see ctr Table 5.2.8) because when the switch transistor Ms is O N , the impedance of C (s), %d(S) = d l/2irfCd(s) » Rs- Therefore, the C (s) variations do not affect the total loading of the d C L cell significantly. Note also that Rs variation due to V i does not affect the capacitive ctr loading of the cell noticeably. If the Ms area is large such that CL « dominates (i.e., Z (s) « d C (s) and Z i ) d d S Rs), then the C L load variation due to V i variations is not ctr 118 significant because: CL(con) = + Cd(S)) ~ CLCCL(S)I{CL CL In this case, the effect of Rs is significantly diminished, which means that the C L load variations for O N and O F F states of switch M are small. This is a disadvantage when larger s C L load variations are required. Therefore, special attention must be paid to switch size in this design. Finally, style (c) occupies a small area for a given load. However, the target technology has to permit fabrication of floating capacitors. F i g . 5.1 l ( d l ) shows a design similar to the one in F i g . 5.11(d), with the difference that a N M O S gate capacitor is used instead of a parallel-plate capacitor. In the associated model, shown in F i g . 5.11(d2), C ( ) g = C ) L gs(L + C (L) and C = C (L) + C (L) + C (s) + gd d sb db db Cd (s)- The Tdij sensitivity to V i is only marginally greater than that of style (c). The g ctr style in F i g . 5.11(e) shows a good S * , but requires more area to achieve the same delay s v as style (d). In the model for style (e) shown in F i g . 5.11(e2), C (L) = Cgs(L) + C d(L) and d C d g = C b(L) + C (s) + C (s)- In the prototype implementation, described is Sec. 5.5, style g db dg (d) is chosen because it provides 10 ps delay in an area of a single-drive N O T gate and it exhibits low s l . ctrl d t l v 5.2.9 Resolution adjustment control block Using either 'uniform load' or 'incremental load' strategy before measuring i V , it is reA quired to check the assumption that T A > TB- A T A T B checker circuit is used to perform this check. Two possible methods for designing the T A T B checker circuit are outlined below: 119 Vctri 2.5V 2.6V 2.7V 2.8 V 2.9V 3V 3.1V 3.2V 3.3V al a2 a3 a4 a5 a6 bl b2 b3 b4 b5 b6 cl c2 c3 c4 c5 c6 dl d2 d3 d4 d5 d6 el e2 e3 e4 e5 e6 (PS) 24.3 75.7 154.6 269.1 423.8 636.4 57.4 142.8 250.2 387.5 555.0 771.5 34.8 121.1 262.4 484.0 789.4 1248 9.44 33.19 73.19 130.3 210.6 316.9 0.844 3.33 7.14 15.72 28.17 49.38 (ps) 25.9 80.3 162.9 284.0 447.5 672.7 61.6 153.2 268.8 417.3 598.3 834.7 34.8 121.3 262.8 484.9 791.0 1251 9.47 33.25 73.40 131.1 211.7 318.7 0.825 3.27 7.16 15.83 28.42 49.47 (ps) 27.4 84.7 170.9 299.1 471.5 708.7 65.89 163.6 287.3 446.9 642.3 898.6 34.9 121.4 263.1 485.7 792.4 1253 9.43 33.35 73.62 131.5 212.5 320.6 0.904 3.30 7.18 15.68 28.25 49.56 (ps) 28.9 89.0 179.8 314.2 495.0 743.5 70.2 173.9 306.1 476.5 686.2 962.8 34.9 121.5 263.4 486.4 793.5 1255 9.44 33.53 73.95 131.9 213.2 321.6 0.757 3.26 7.28 15.73 28.49 49.40 (ps) 30.2 93.4 187.9 328.5 518.2 777.7 74.3 184.3 324.6 506.4 730.1 1020 34.9 121.6 263.8 486.9 794.5 1257 9.45 33.59 74.19 132.3 213.9 323.0 0.891 3.35 7.42 15.71 28.29 49.46 (PS) 31.5 97.7 195.9 342.7 540.4 811.1 78:4 194.7 342.9 535.6 773.9 1090 35.0 121.7 264.0 487.5 795.4 1259 9.39 33.67 74.33 132.8 214.6 324.0 0.938 3.16 7.14 15.73 28.41 49.47 (ps) 32.8 101.6 203.7 356.2 561.1 843.4 82.4 204.7 361.0 564.8 817.1 1150 35.0 121.9 264.2 488.0 796.3 1260 9.44 33.69 74.37 133.1 215.2 325.1 0.952 3.47 7.27 15.75 28.41 49.56 (ps) 34.0 105.8 211.2 369.4 581.8 875.1 86.5 214.6 378.9 593.8 859.9 1210 35.0 121.9 264.3 488.4 797.0 1262 9.55 33.73 74.59 133.4 215.7 326.2 0.791 3.19 7.15 15.82 28.41 49.53 (ps) 35.2 109.5 218.7 382.1 601.8 905.2 90.2 224.3 396.4 622.2 902.5 1280 35.0 122.1 264.6 488.9 797.84 1263 9.49 33.80 74.62 133.7 216.3 327.1 0.761 3.31 7.31 15.77 28.62 49.48 AT*, AV (ps/V) 13.5 42.2 80.2 141.2 222.6 336.0 40.9 101.9 182.8 293.4 434.4 636.7 0.308 1.23 2.77 6.09 10.55 18.35 0.063 0.755 1.78 4.23 7.1 12.72 -0.104 -0.303 0.211 0.594 0.569 0.123 ctr( S'v" Vctri 1.3 1.3 1.2 1.2 1.2 1.2 1.5 1.5 1.5 1.6 1.3 1.64 0.029 0.033 0.034 0.041 0.044 0.048 0.022 0.073 0.078 0.104 0.108 0.128 -0.451 -0.302 0.095 0.124 0.065 0.008 Table 5.1: T and S * for different styles of C L cells. Numbers 1 through 6 i n the first column refer to the states a = 000001,000011, 000111,001111, 011111, 111111 i n test bench circuit shown i n Fig. 5.10, respectively. f dif v rl 120 1. The circuit in F i g . 5.12 can be used to check the condition that T > TB- A zero A time interval (Td = 0) is applied as input to the T Q . A s the waveforms of T A illustrate, when T A <TB, D F F J E O C samples L O W until the z-th rising edge of c l k A matches that of c l k B after ((D-1)T A samples a H I G H after T /T c If T and TB A +T )/T C A cycles of c l k A . However, D F F J E R R I cycles of c l k A , i.e., D F F J E R R I is set before D F F J E O C . > TB, the reverse occurs, i.e., D F F J E O C is set before D F F J E R R I . Therefore, A the R A control block can check the condition T A < TB by monitoring the two flags E O C J L A G and E R R L F L A G . When the condition T A < T B is being checked, the reset lines of both E O C J D F F and E R R 1 J D F F must be inactive. The R A control block sets these reset lines H I G H through the O R gate. A n important requirement for this circuit is ensuring that [((D — l)T A [T /T C A + Tc)/T \ A ^ J ([ J means integer part), otherwise the two flags are set in the same cycle of c l k A resulting i n a decision deadlock which causes failure i n checking the condition T> A TB- However, such a requirement is easily met by a typical design under typical process variations. For example, in a circuit implementation i n a 0.35 fim C M O S process, the minimum (D — \)T A is 1.5 ns, maximum Tc is 0.4 ns, and maximum T A is 0.15 ns. Therefore, in the worst case: and [Tc/T \ A = 2 Another design requirement is in regard to the first rising edges of c l k A and c l k B . Since setup and hold time for D F F J E R R I and D F F J E O C could be different, D F F J E R R I and D F F J E O C might be set H I G H simultaneously on the first or second edges of c l k A 121 and c l k B , respectively. Such a case results in decision deadlock. The circuit proposed next solves this issue but requires more hardware. 2. From the waveforms in F i g . 5.13, i f T < TB, CntrA w i l l count faster than CntrB A which causes the difference M —M A to increase rather than decrease as time pro- B gresses. Assuming T = 0, the difference between the two counters is initially 0 or 1. d Therefore, M — MB > 2 implies that T A A < T . This method requires more hardware B than the first method, but its operation does not depend on the values of T , Tc and A T A or on the setup and hold times of the flip-flops as in previous circuit. F i g . 5.13 depicts the T A T B checker circuit. The Cntr3A and Cntr3B are 3-bit counters initialized to 0 and 2, respectively. To save hardware, instead of Cntr3A, the three least significant bits of CntrA in R E block could be used. The 3-bit comparator 'cmp3', compares the outputs of Cntr3A and Cntr3B, denoted by M 3 A and M 3 B , respectively. The same technique used in the R E block is used here for the reliable detection of the event MSA > MZB + 2. Detecting such an event implies that c l k B has been slower than c l k A (i.e., TB > T ). A In order to use the time diversity technique, the c l k A l and c l k A 2 signals from the R E block must be used. In addition, a T such that d TAI + T~A2 < T < TB has to be applied to the T Q , where T \ and T d A A2 are as defined in Sec. 5.2.5. The circuit in F i g . 5.14 is used to generate an appropriate T . d If M 3 A < MW, it is deduced that T B < T A and E O C F l a g is set before E R R _ F l a g . If the 'uniform load' approach is used for selecting the C L loads, one hardware efficient method to search for a and b is the exhaustive search. In this method, the R A block is composed of a 2/-bit state machine, R A - S M . / bits of the state machine are connected to a ... 0 and the other / bits to b ... o/_i. The R A - S M sequentially tests all the distinct 0 122 Counter Clk T >T A B ERR1 DFF is set clkB D Q EOC_DFF Clk rst clkA I EOC_Flag I I I clkA clkB ERR1_Flag L f l i l • \ EOC_DFF is set Clk rst RE_FLAG (from RE block) T< T A B ERR1_DFF is set v —• \— (D-1) Tg ERR1_Flag EOC_Flag clkA rst_ctrl Resolution Adjustment Controller CLK i - clkB N EOC_DFF is set l i l To CL cells control inputs (a) (b) Figure 5.12: Circuit for checking the necessary condition that T A 123 > T B To RA Block From CntrA (least 3 significant bits) or From Cntr3A Initilized at 2 3-bit counter (Cntr3B) clkB rst k-bit comparator cmp3_out D Q EsampChkl Ext..DFF1 clkA1 Cl k rst (From <> Yrb ERR-Flag clkA2 D Q EsampChk2 Ext. .DFF2 clkA2 Clk rst (From RE block) Irb Clk rst Irb r*- A2 x clkA clkA1 clkA2 CntrA 1 j • 2 | 3j 4J 5| 6| 7 j 0 J 1 J 2 J 3 J 4 J 5 J 6 J 7 J 0 J 1 (3 lowest bits) ClkB CntrChkB 3-bit (3 CntrB lowest bits). :2 :3 ! 4 , 4| 5 j 2j 3 cmp3_out cmp_out ERR_Rag RE_EOC clkB CntrChkB 3-bit CntrB (3 lowest bits) cmp3_out cmp_out ERR_Flag RE_EOC Figure 5.13: Alternative circuit for checking the condition T A 124 > TB T ST_check D Q ST..DFF. Clk rst SP_check D Q SP__DFF Clk rst rst chck rst chck '11 D Q SysClk ST _DFF ST_edge Clk rst rst chck SP_edge X 1 +1A2 < T A d < T B SysClk rst_chck ST_check SP_check T n ?ure 5.14: Circuit to generate T A1 +r A2 125 <T <T d B for T A T B checker circuit combinations of a and b: ae {0 . . . 0 0 0 , 0 . . . 0 0 1 , 0 . . . O i l , 0 . . . I l l , 1 . . . 1} be {0 . . . 000,0 . . . 0 0 1 , 0 . . . O i l , 0 . . . I l l , 1 . . . 1} The flowchart of the algorithm used to select a and b is given in F i g . 5.15(a). Note that distinct combinations for a are sequences with different number o f ' 1 's in them. Therefore, a = 110000 and a = 000011 result i n the same T A because all the C L cells are the same. If all the distinct combinations are tried and the required resolution is not obtained, the circuit sets a failure flag R A E R R _ F l a g . If the circuit has been designed to operate under typical process variations, setting this flag means that the B I S T circuit is faulty. The exhaustive search approach, though more efficient i n terms of hardware, can result in long resolution adjustment time. To reduce this time, a heuristic can be added to the algorithm as shown in the flowchart of Fig. 5.15(b). The main difference here from the exhaustive algorithm in F i g . 5.15(a) is that given the condition T A > T , only combinations — > B of 6 or a are tested, but not both. If the 'incremental step load' strategy is used, the search algorithms must be adjusted accordingly. The exhaustive test strategy now requires potentially testing all the combinations o f a and b: ae {0 . . . 000, 0 . . . 001,0 . . . 010,0 . . . 0 1 1 , 1 . . . 1} be { 0 . . . 000,0... 001,0... 010,0... 0 1 1 , . . . , 1...1} The flowchart of the algorithm is shown in Fig. 5.16. Again, the hardware implementation is simple because one 2/-bit counters can be used to generate b or a. However, the resolution adjustment time can be very long because a maximum of 2 ' combinations might have to be 2 checked (in the worst case scenario). 126 (a) (b) Figure 5.15: Algorithms for selecting a and b in uniform load C L method, (a) exhaustive search, (b) directed search 127 Increment a Resolution adjustment^ failed. ) set RAERFLFlag J Figure 5.16: Exhaustive search algorithms for selecting a and b in the 'incremental step' C L cell method 128 3,., ...ao = 0...0 fc ...b = 0...0 M 0 T ; i> T A N o Increment a Yes No Increment b lYes Evaluate A/ A A > "tn?* N 5 • 0 9 f Resolution adjustment^ ( completed. ) V Set ERA_Flag J Figure 5.17: Semi-exhaustive search algorithm for selecting a and b in the 'incremental step' C L cell method 129 a b M H ...ao = 0...0 ...b = 0...0 0 I i=0 1=0 Figure 5.18: Fast search algorithm for selecting a and b in the 'incremental step' C L cell method 130 A semi-exhaustive search w i l l reduce the adjustment time with small modifications in hardware. The flowchart for this method is given in Fig. 5.17. The main difference with the exhaustive search is that either a or b is incremented during the search, but not both. The decision on which counter to be incremented depends on whether T A > T B or TA < T. B Therefore, the maximum number of combinations to be tested is 2'. A fast search algorithm is depicted in the flowchart in F i g . 5.18. In this algorithm, if T A < T , only a is adjusted because T B TA and T must be increased until the difference between A satisfies the required resolution. Similarly, i f T B increase T A B so that the required T A B on whether TA < T or T B A B only b is adjusted to is achieved. In this algorithm, since the two oscillators A and B are similar, there is a high probability that TA and T choice is a = 0..0 and b = 0..0. If > T, < N, ih are close. Therefore, the first the lowest significant bit of a or b (depending > T ) is set high to increase T B A or T B by the smallest amount possible. If the required resolution is still not achieved, the next bit of a or b is set H I G H and all other bits are set L O W . This is continued until setting the i-th bit H I G H implies that T A or T B has been increased too much. Then the i-th and (i — 1)-thbit are set L O W and H I G H , respectively, and the process starts over by setting the 0-th bit. To illustrate the algorithm, assume that T A > T, B I = 6 and the required resolution achieved for b = 001001. The algorithm goes through the following sequence to find the required b: 000000,000001, 000010,000100,001000,010000,001001 This is i n contrast with the exhaustive and semi-exhaustive searches, which go through the following sequence: 000000,000001,000010,000011,000100,000101,000110,000111,001000,001001 131 A s can be seen from above, the fast algorithm finds the solution in 7 steps, while the exhaustive and semi-exhaustive search require 10 steps. 5.2.10 T D C e r r o r sources From Eqn. 5.11, one of the maj or sources of measurement error is T R , which is due to different noise sources in T Q (in F i g . 5.6). Also, the measurement accuracy (accuracy is formally defined in Sec. 5.2.11) is degraded due to the delay variations in the circuit of Fig. 5.8, causing random variation between the arrival of rising edges of I N I and IN2, and S T A R T and STOP, respectively. In this section, we identify these noise sources and w i l l show how the proposed T D C architecture can significantly reduce power supply noise effect on the rms value of TR. To identify different noise sources, we obtain the relationship between JV and the interval being measured by T D C , where T T = T S = t TD IN2 t ST ART = tlNl + TST (5.17) tsTOP =tlN2 + Tsp (5.18) + r T(dk-to-Q) muxl — £JJVI, as follows. In F i g . 5.8: and T S SP = T mux2 + r p(dk-to-Q) S ( ST(dk-to-Q) and T Tsp(dk-to-Q) are the clk-to-Q delays of S T _ D F F and SPJDFF, respectively, and r m u x i and T ux2 are the delays from input 10 to out in M U X 1 and M U X 2 , respectively). Substituting m Eqns. 5.17 and 5.17 in Eqn. 5.10 yields: T D = N(T - T ) - TEOC + T - r A B A B + r p - TT S From Eqn. 5.19, Different sources of errors affecting TR include: 132 S (5.19) 1. TSP and TST- the edge sampling flip-flops ST J D F F and SPJDFF, and multiplexers MUX1 andMUX2 2. TEOC- D F F J E O C flip-flop setup time and metastability window 3. T ,TB,TA and T g : ring oscillators jitter A The TST, SP and T OC can be expressed as: T E TST — T TO + T T( ) TSP = T po + TSP(e) and TEOC, TEOCO S e S = TEOC where T5ro» TSPO and S TEOCO + TEoc{e) are the nominal values (under noise-free conditions) of T T, S TSP respectively, and r ( ) , T p( ) and T oc(e) are the jitter of ST JDFF, and S P J D F F S T e S e E clk-to-Q delays, and the E O C J D F F set-up time and metastability window, respectively. The delay and setup time jitters are due to different sources such as thermal noise and power supply noise. The metastability error, however, is due the inability of the D F F J E O C to decide its output state i f the delay between the arrival time of the signals at the clk and D inputs are very close the setup time of the D F F J E O C . Therefore: EOC(e) = TEOC(en) + TEOC(m) T where T oc(en) is the variation of E O C J D F F setup time due to noise source and T oc(m) is E E the error induced by E O C J D F F metastability window. The characterization of E O C J D F F through simulation, reported in Appendix E , shows that this window is less than 0.01 ps. Therefore, for practical applications, this error is negligible in comparison with T D C resolution of about 10 ps. The T TO, TSPO S and T OCO E 133 w i l l be accounted for during calibration because they only contribute to the offset Tc (refer to Sec. 5.2.6). However, T T(e), sp(e) T S and T c(e) cause loss of precision. The inaccuracy due to the above three sources is given EO by: TDFF(e) = SP(e) ~ ST(e) + ^EOC(e) T T The inaccuracy caused by the jitter in ring oscillators A and B used in the T Q , is analyzed next. Jitters i n r i n g oscillator A a n d B The outputs of both ring oscillators A and B , c l k A and c l k B signals, include some amount of jitter. In general, the rms jitter of a ring oscillator increases with the square-root of the number of gates in its oscillating loop [106]. When a rising edge passes through the i-th. gate of the loop, the output of the gate output switches after Tg^y. 9(i) = 9{i)0 +. 9(i)e T where T ^ 3 Q T T is the average gate propagation delay and T ^ g e is the random variation of this value due to different noise sources. The period at the output of the oscillator A can be expressed as: 2M -1 J2 9(i) i=0 2M -1 A A T = T A = ( 9(i)0 + g(i)e) T i=o T 2M -1 2M -1 A A X ] g(i)0 + 1=0 = TAO + T = T Ae 134 ] L g(i)e 8=0 T (5.20) where M A is the number of gates in the ring oscillator A , T is the average period, and T A0 Ae is the period jitter of c l k A : 2M -\ E **)* t'=0 A Ae= T (5-21) Assuming r ( ) ' s are independent, normally distributed random variables with standard de5 t e viation u and mean of 0, the variance of T g Ae w i l l be: <?Ae= \[2M G A (5.22) a Similarly, •j2M~ cjg A where cr Be is c l k B ' s period jitter. In a measurement sample, the T D C stops after N cycles of c l k A and c l k B . If the noise sources are independent, the jitter in each cycle w i l l be independent from the jitter in any other cycle in either c l k A or c l k B . In such case, the effect of the jitter on T is as follows: d T d = N(T A0 N-l - TBO) + X I (TA(j)e - T (j) ) + TQ B e 3=0 Therefore, the measurement error due to the jitter in the ring oscillators is: N-l Tm = Yl {TA(j)e - T (j) ) B The variance of T R1 (5.23) e is obtained as: < = N(<r + * ) = 4NM a 2 Ae 2 Be A g (5.24) Eqn. 5.24 is valid when the noise sources in the gates are independent, such as thermal noise. However, the noise sources due to power supply and substrate noise for each gate are not independent. These correlations are inherent to the structure of the T D C , making it 135 resistant to such noise sources. The analysis i n Appendix H shows that when measuring a time interval T , the inaccuracy of the T D C due to the V^-induced jitter in Oscillator A and d B is: Eps = Td[K.V M \(t ,t ) d e 0 V t )(t ,t )} d dd e d where t is the time at which S T A R T edge occurs; t = t +T ; t 0 d 0 (5.25) eoc d eoc is the time at which mea- surement completes; K and 7 are two constants modeling the V ^ - i n d u c e d gate delay jitter (see Appendix G . l ) ; V ( ) is the power supply noise term; V d( )(to, t ) and V d( ){td, teoc) dd e d e d d e are the averages of V d(e) over the window [t , td] and [td, t ], respectively. Eqn. 5.25 indid 0 eoc cates that Eps is proportional to the time interval measured by T Q , Td. This was to be expected because the larger the interval T , the greater the number o f switching events in the d oscillator loops. Eps is also proportional to the power supply noise averaged over a time window. Due to noise power reduction because of noise averaging and differential noise rejection, this circuit is capable o f high-precision measurements. Sec. 5.6.2 shows that the rms value o f Ep$ is approximately 5.5 ps under a typical conditions i n a 0.35/zm C M O S implementation of the circuit. 5.2.11 Accuracy,Precision,and Resolution Accuracy, precision and resolution are three important characteristics of a measurement circuit or device. This section evaluates these characteristics for the T D C circuit. Definitions The formal definition of accuracy, precision and resolution are [107]: 136 1. Accuracy is the degree of exactness (closeness) of a measurement when compared to the expected (most probable) mean of the variable being measured. For example, i f the value Y is measured for a variable with expected value of X, the measurement accuracy is: A = l - | ^ H = l - f (5-26) where e — X — Y is the absolute error. Since e is mathematically more convenient to calculate and is directly mapped to accuracy, throughout this document we calculate £ as a measure of accuracy. 2. Precision is the measurement sample deviation relative to measurement mean. Therefore, * — I ^ I where Y is a sample measurement and Y is the the measurement mean i f a large number of measurements are performed on the variable to be measured. Precision is, in fact, an indicator of the consistency of the measurements taken by an measurement device. We define precision error as: x] = Y - Y (5.27) Since r\ is mathematically more convenient to calculate and is directly mapped to precision, hereafter we w i l l use r\ to analyze the precision of the T D C . 3. Resolution is defined as smallest change in a measured variable to which a measurement device responds. Therefore, the resolution of the T D C circuit is T . A Using the above definitions, we can say that i f a measurement is accurate it is also precise, but the reverse is not necessarily true. This is because some unknown variables 137 affect all the measurement the same way, e.g., measurement offset in the measurement device. These random reduce the accuracy but not the precision. To illustrate this, assume that a measurement device measures the value Y for a variable with expected value of X such that Y =X +e (5.28) where e is a random variable with a mean of m and a standard deviation of a . Therefore, £ E the rms error, e , is rms elm. =E[e } 2 = E[{e-e + e) } (5.29) 2 = al + m 2 E where E[ ] represents the Expectation function [108]. F r o m Eqns. 5.27 and 5.28 the precision error, n, for this example, is obtained as below: V 2 = E[ } 2 rms V = E[(X + e - ( X + i ) ) ] 2 (5.30) = °l Comparing Eqn. 5.29 and Eqn. 5.30 shows r\l < e 2 ms rms due to the ml, which can be inter- preted as the offset error of the measurement device. T D C accuracy a n d precision We analyze the T D C accuracy, precision and resolution for two different measurement: absolute and differential methods. In an absolute measurement of a time interval Td, the measured values by T D C are used directly, whereas in a differential method, the differences of 138 measurements from a reference measurement are analyzed. Consequently, the set of meaningful quantities for the two methods are: where N j re Absolute: Ni.A^,... Differential: N - N , x (5.31) N - re} N 2 re} is a number obtained for a reference measurement. In an absolute measurement of an time interval Td, the T D C measurement error is (from Eqn. 8D): e abs The error terms T Ae and Tc e = NT Ae + Tee + T Q + T (5.32) R are due to calibration, but their values remain constant for all the measurement samples following calibration. In fact, T and Tc Ae c e a n be interpreted as offset error. Therefore, the T D C precision error is given as: riabs = T Q + T (5.33) R In the differential measurement method, the offset error can be eliminated through subtraction. Assume N and N correspond to the measurement of two time interval sample a b T and T , respectively. Therefore: a b T ab where T ab = (N a - N )T b + T A - T Qa + T Qb - T Ra (5.34) Rb is the measured difference between T and T . Therefore, in differential measurea b ment, the error, Sdi//, and precision error, rjdi/j, are given as: edi/f = {N - N )T a b Ae + T Qa - T Vdijj = TQ - TQt, + T Qb a Ra 139 + T Ra - T Rb - T Rb (5.35) (5.36) If Tee variations are significant compared to that of other error sources, from Eqns. 5.32, 5.33, 5.35, and 5.36, it can be concluded that in differential measurement mode, the error decreases (accuracy improves) because the constant Tc term disappears, but the precision error increases (precision degrades) due to accumulating effects of additional independent random variables. Using a two-point calibration scheme to calibrate the T D C , the improved accuracy in differential measurement over absolute measurement significantly outweighs the reduced precision. To illustrate this claim, consider an example in which two sample time intervals T and T , the T D C generates two numbers i V and N . Assume that N a b and N a « b N i2 — N n. ca b a Using the variances of T ca and Tc Ae = 2 aH ms { N ^ 2 J V c a i l ) 2 ( f + 2 4 + i f ) + 5 a « N i2 — N n ca ca obtained in Sec. D . l , the e rms error in the absolute and differential measurement modes are: jy2 rp2 (e r )) « + ( rp2 i f + 4 ) (5.37) - 6 ( § + ^) (<? \1 — (Nb — Ng) 2 T A _2\ n , o / ^ A , _2 \ (5.38) - 2 ( | + 4) The rms precision error in absolute and differential measurement modes are: j>2 (Vabs(rms)) = y j - + o\ (5.39) 2 (ri ff(rms)) 2 dt = 2(^ + a ) 2 R (5.40) Comparison of Eqns. 5.37 and 5.38 show that using the differential measurement method decreases rms error, while Eqns. 5.39 and 5.40 indicate that this method increases the rms precision error. 140 5.3 Jitter Generator For the jitter tolerance and jitter transfer test of C R U s , it is necessary to supply the C R U with a signal which has a known jitter. Here, a circuit is proposed which is capable of generating a controlled jittered signal out of a jitter-free clock signal. The circuit is shown in F i g . 5.19. The circuit is composed of a delay line, a multiplexer, and a sequence counter. Different taps of the delay line are multiplexed to the output J. The counter specifies which tap is multiplexed to the output at any clock edge. For example, with 8 taps and a 3-bit up/down counter, it is possible to generate a triangular shaped jitter signal with the maximum peak-topeak amplitude of 8r , where r is the delay of each delay element in the delay line. Using a g g counter with a count sequence which follows a sinusoidal pattern, the circuit w i l l generate a signal with sinusoidal jitter. B y designing a programmable counter, the circuit can generate different jitter signals according to the stored program in the counter. Such counters can be implemented as general state-machines. Delay elements (DE) J (Jittered clock) Figure 5.19: Jitter generator circuit 141 5.4 5.4.1 Schemes for O n - C h i p Jitter Specification Testing Cycle-to-cycle jitter measurement Cycle-to-cycle or period jitter is defined as variations i n the period of a signal. A histogram approach can provide statistics of such jitter. Using this approach, to measure period jitter, two consecutive rising (or falling) edges of the signal K „ are passed to the time measurement circuit as S T A R T and S T O P signals by a control circuit (Fig. 5.20). After this is completed, the control circuit reads the N stored in the T Q counter and sends it to an external tester (possibly through a J T A G controller if it exists on the chip) or to an on-chip processing unit [ 109] for post-analysis. Concurrently, the test controller can pass two other consecutive edges of Vi to the T D C . This procedure can be repeated until a predetermined number of n samples of the Vi periods are measured. Subsequently, the external tester (or on-chip pron cessor) can form a histogram of the data and calculate the variance and peak-to-peak jitter. The tester does not have to be a high-speed or high-performance mixed-signal type because the data is digital and can be sent off-chip using a low-speed serial bus. If the information about the times at which the jitter samples are taken is supplied to the tester along with the jitter sample measurements, frequency components of the jitter can also be analyzed. This feature enables the J M C to perform full jitter standard compliance tests, i f required. However, this feature is not fully detailed in this thesis. 5.4.2 Relative jitter measurement In some applications such as serial communications, it is important to ensure that the relative displacement of corresponding edges of two signals, for example, I N I and IN2, meets a 142 START D Q D DFF1 Clk rst IN1 START STOP Q DFF2 Clk rst STOP CLK TDC CLK EOC CLK Next_sample Digital Controller ~ i _ r N Ready for measuring yf, next period sample ! Figure 5.20: Cycle-to-cycle jitter measurement given specification. Here, without loss of generality, we assume that the specification sheet requires that the corresponding edges of the signals I N I and I N 2 occur within a tight time window (e.g., 0.001UI, where U I is the unit interval or period duration). Based on this assumption, we propose the circuit in F i g . 5.21 to measure the relative jitter between the edges of I N I and IN2. In this circuit, DFFi samples an edge of I N I and, DFF 2 samples the edge of I N 2 closest to the sampled I N I edge. The delay element D 2 ensures that the setup&hold time of DFFi, i-e., TS&HI , is met so that the D F F I output is set before an IN2 edge arrives. This condition is satisfied i f tlN2 > tlNl — T~D2 + T l +s2T. q where T D2 is the delay of the D 2 delay element, t IN1 the sampled edges of I N I and IN2 occur, r ql and t IN2 are the time instants at which is the C L K - t o - Q delay of D F F I , and r 143 s2 is the setup time of D F F 2 . F i g . 5.21(b) shows the timing diagram of the circuit for one positive and one negative value of Tj = ti i N —t . The generated S T A R T and S T O P sig- IN2 nals are passed to the T D C to measure the time displacement. After the completion of a measurement, DFFi and DFF are reset and are ready for the next sample. Note that the 2 sample&hold time of the flip-flops DFF , X DFF affect the actual time displacement being 2 measured, since the measured T is d T d where Tj — tiN since T , T 2 D2 Q2 and r — tmi ? 1 = Tj + T D2 + T q2 — Ti q is actual time displacement between I N 2 and I N I edges. But are constant, they can be accounted for through calibration. In such a measurement scheme, the meaningful data is the variation of measurement values from one sample to the next. Jitter statistics can be obtained from a sufficient number of sample measurements. In the scheme described, the measurement range is limitedto approximately — Tm + Tqi + T s2 where TTDC < Tj < T TDC ~ T D2 + Ti + T q s2 is the maximum measurement range of the T D C . rm cannot be more than 0.5UI, otherwise the displacement on the I N I edge and a non-adjacent edge of IN2 w i l l be measured. This, however, is generally not a limitation for test purposes because the acceptable edge displacement variations is usually a small fraction of unit interval (e.g., 0.1UI). The relative jitter measurement scheme can also be used to perform a jitter tolerance limit test on clock recovery units (CRUs). For a jitter tolerance test, a signal with known jitter is applied to the C R U . The T D C measures the relative jitter between the input clock and the recovered clock. This relative jitter cannot exceed a certain threshold for jitter signals 144 START "1" IN1 START STOP D Q DFF2 IN2D Clk rst D Q DFF1 Clk rst TDC STOP EOC • D2 • IN2-! H : ( T 2 ': i. . . . . . .1 D I S Ready for measuring ^ next period sample ! Next_sample Digital Controller (a) IN1 IN2 1s2 START ' 1 ts2 1V 'TD2 IN2D STOP -1q2 */W2 Figure 5.21: Relative jitter measurement 145 N specified in standards such as [20]. The excessive relative jitter indicates the inability of the C R U to meet its rated bit-error-rate. For production test purposes, we suggest testing the jitter tolerance at two different frequency/amplitude points: one frequency inside the loop bandwidth of the C R U and one frequency point outside it. For each case maximum amplitude given in standards should be selected. Performing tolerance tests at more points is also possible but requires more test time. 5.5 Implementation The jitter measurement circuit proposed in Sec. 5.4.1 has been designed and implemented using a 0.35^ C M O S technology. The C L cells have been designed as standard cells to allow for automatic place and route. The uniform C L cell style has been used for implementing the resolution adjustment circuits. The rest of the cells used i n the implementation have been taken from a standard digital cell library. The top block level schematic of the jitter measurement circuit is shown in F i g . 5.22. It contains the following blocks: 1. T Q : Time Quantizer 2. R E _ T A T B : Range extender and T A > TB condition checker 3. M a i n C o u n t e r a n d the D i v B y 2 circuit 4. R E E O C _ s y n c _ D F F , T Q E O C j s y n c D F F a n d E R R l _ s y n c _ D F F : R E J 3 0 C , T Q J E O C and E R R l . f l a g synchronizer flip-flops 146 T A T B C h e c k Delay G e n : Generates a small time delay for checking T A > TB Delay Generator: Controls the selection of the delays needed for resolution adjustments, calibration and measurement. The implementation details of each part of the circuit follows. C L cells A total of six different C L cells have been designed using style (d) in F i g . 5.11. The transistor sizes for each of these cells are given in Table 1. In the forth row of this table, the additional delay i n the oscillator A or B loops obtained by activating the cell is listed. Such a selection of C L cells allows for ± 2 8 8 ps or ± 8 . 5 % period mismatch between c l k A and c l k B (this is obtained when all the cells are activated). The last row lists the area of each cell. The height of all the cells is the same as standard cell library height. The area of the smallest cell is equivalent to the area of a double-drive 2-input N A N D gate. CL CL 0 2 CL 3 CL 4 c u Ms [w(fj,m) 1'l(pm)) ML [w(fim) 1'l(jim)} Delay (ps) 4/0.35 4/0.35 6/0.5 23 4/0.35 4/0.35 4/0.35 4/0.35 3/0.5 11 9/0.5 35 6.3x21 7.9x21 9.4x21 18/0.5 67 11x21 27/0.5 101 Area (width(^m) x height(^m)) 13.5/0.5 50 9.4x21 14x21 Table 5.2: Specifications of the implemented C L cells 2. T i m e Q u a n t i z e r ( T Q ) Oscillators A and B in the T Q block consists o f 11 N A N D gates and one A N D gate. 147 Six taps for each oscillator are connected to six different C L cells. The outputs of oscillators A and B are directly connected to the clk and D inputs of D F F _ E O C . These outputs are buffered before being used in other control blocks which are less time sensitive. The output of D F F _ E O C is sampled and held by another flip-flop to ensure that the end-of-conversion signal, E O C _ F l a g , can be observed by the control blocks operating with the system clock. In addition to Start and Stop inputs, two other inputs have been reserved for applying StartCheck and StopCheck signals to oscillators A and B , respectively (see F i g . 5.23). These inputs are used to apply a Tj. (as defined in Sec. 5.2.9) for the purpose of checking the condition T A > TB- Without these inputs, an additional multiplexer would be required. However, when Start and Stop are applied to the T Q StartCheck and StopCheck signals must be inactive ( H I G H ) , and vice versa. The main controller block ensures this condition using four control signals: MainSet, rbMain, CheckSet, and rbCheck. The flip-flop T Q E O C _ s y n c _ D F F has been used to synchronize the T Q J E O C signal with the system clock, S C L K , in order to avoid sampling erros by the Main_Controller block. 3. R E _ T A T B : The implementation of this block closely follows the structure shown in F i g . 5.7(a) and 5.13(a) with A; = 6,r Ai = 1.2ns and T AX = 0.4ns. The flip-flop R E E O C _ s y n c _ D F F synchronizes the R E _ E O C signal with the system clock, S C L K . This prevents errors in sampling by the M a i n Controller block. The buffers B u f 1 to Buf6 are not needed in the actual implementation, but are necessary to perform mixed-signal simulations. Without these, during simulation the sig148 nals R E J E O C 1 and E R R l . f l a g l w i l l become 'unknown' due to intentional setup & hold violations i n the internal flip-flops of the R E _ T A T B block. The propagation of the unknown states prohibits meaningful simulations. To overcome this problem, B u f l , Buf3, Buf4 and Buf6 are simulated as digital cells, and Buf2 and Buf5 are simulated as analog cells. This arrangement, effectively, translates the R E _ E O C l and E R R l _ f l a g l signals from the digital domain to the analog one and then back to digital. Since the 'unknown' digital state at the input of the analog block is interpreted as a voltage of OV, an 'unknown' digital state does not propagate to the rest of the circuits. 4. M a i n C o u n t e r a n d D i v B y 2 circuit: A 16-bit counter is used to count the number N. A s shown in Fig. 5.6, c l k A should drive the counter's clock input. However, the maximum operational frequency of the 16-bit counter is 250 M H z , whereas f \]^ c 350 MHz. The divider circuit divides frf^A = by two enabling the counter to count the number of c l k A edges. The state of the D i v B y 2 circuit recovers the lost bit due to division as follows: N = 2N cntrl6 where N c n t r l 6 - clkDiv2 is the state of the 16-bit counter and c l k D i v 2 is the state of the D i v B y 2 DFF. 5. Delay Generator: This block generates Start and Stop edges with tst op T j,2T re ref and (t IN2 - t ) IN1 — tstart = for [ S e l D l , SelD0]=[01], [10], and [11], respectively. When [ S e l D l , SelD0]=[00], both Start and Stop are set H I G H and the StartCheck and StopCheck signals are activated to check for the condition TA > T g . 6. T A T B C h e c k Delay Generator: This block generates a delay of 1.8 nsec between 149 the StartCheck and StopCheck edges in the T A > TB check mode. The outputs of this block are set H I G H in other modes. 7. M a i n C o n t r o l l e r : This controller monitors the outputs of all other blocks and generates required signals for controlling the operation of the T D C . The T D C operation starts by loading a threshold N h t re serially. The serial data is read through SThre input while TestStart is H I G H . Then, the controller controls the Delay Genrator while the T A T B Check Delay Generator block performs resolution adjustment. After adjustment, calibration is performed and the T D C switches to measurement mode. In this mode, the M a i n Controller instructs the Delay Generator block to pass jitter samples to the T Q . Upon completion of each measurement, the data is sent off-chip serially through DataOut output. The InputReady, MeasReady, and DataReady signals are used for handshaking between the external tester and T D C . 5.6 5.6.1 Simulation Results Jitter measurement circuit A l l the individual blocks in the J M C as well as the complete circuit were simulated under a variety of conditions to verify their functionality and performance. The T Q , Edge Sampler, R E , and R A blocks were verified through analog simulation because of timing and loading sensitivity. The controller and counter blocks were simulated as digital blocks. The Spectre and Verilog simulators were used for analog and digital simulations. The complete circuit were simulated using SpectreSVerilog mixed-signal simulator. For this simulation, the T Q block is considered as an analog block while the rest of 150 the circuits are treated as digital cells. Analog high-level description language (ahdl) code was written to perform measurements during simulations and to emulate the external tester which handshakes with the J M C . To test the full capability of the circuit, oscillator A was loaded with an additional capacitive load to model a mismatch of 35 ps between T A and T g . In addition, T j = 6 ns re and Nth — 272. Therefore, the required resolution is T h = t T j/N h re t = 22ps. The waveforms in F i g . 5.24 show how T D C successfully adjusts its resolution by controlling the Bc[0 : 5] = b tabs to achieve a resolution better than T h- In this case a resolution of t approximately 11 ps is achieved. The resolution adjustment took approximately 16.4 (is. The result of the last step in the resolution adjustment is also used for calibration. The rippling seen on waveforms TU and T g in F i g . 5.24 represents simulation artifacts caused by numerical coupling of the two oscillators A and B in the simulator. Tightening the accuracy parameters of the simulator mitigates the ripples, but increases the simulation time significantly. A resolution of 34.1 ps was achieved in a separate simulation. In this case, a number of time intervals from T d = 1 ns to 11 ns with a step of 200 ps were measured. F i g . 5.25 shows the difference between the simulated measured intervals and the expected values. The measurement rms error is 12.1 ps, which matches the rms quantization error estimated in Eqn. 5.40. 5.6.2 A c c u r a c y estimation In this section, the accuracy of the T D C is estimated assuming a typical condition on the chip based on the analysis in Sees. 5.2.10 and 5.2.6. These calculations assume that 151 1. power supply noise (Vdd( )) is e a high-frequency signal with a lower bandwidth of 50 M H z and rms value of 50mV; 2. the thermal noise jitter for a N A N D gate delay is approximately 25 fsec [106] (a g = 25 fsec); 3. the thermal noise jitter in a flip-flop delay is negligible compared to its Vdd-induced noise; 4. the resolution ( T A ) is 10 ps; 5. T = l ns; d 6. the constant offset Tc = 0. To estimate the V^-induced noise, a number of sinusoidal noise components, Vdd( ) e with frequencies between 5 0 M H z and 2 G H z and eight phases between 0 and 2VT have been selected and the resulting jitter in ring oscillators and flip-flops are simulated for each selection. The rms value of each jitter term is estimated by obtaining the rms value of the simulated jitters of that term for all the selections of Vdd(e)Based on the above assumptions, different jitter terms i n Sec. 5.2.10 are estimated as follows: 1. TsT(e) and T p(e)'- The rms value of the sampling flip-flop clk-to-Q jitter is: S °ST{e) = <TSP(e) = (5.41) 2. T c(e)'- The rms value of the D F F J E O C flip-flop is: EO VEOc(e) = l.Sps 152 (5.42) 3. Oscillators A and B : F r o m Eqn. 5.24, for M = 12, N = T /T d A = 100, and a g = 25 fsec, the rms error due to thermal noise is am = 1.73 ps Eqn. 5.25 is used to evaluate V^-induced jitter term. The required n and 7 values are extracted from Table G . 1. a P S = 5.5 ps (5.43) Assuming different jitter terms are independent, the resulting inaccuracy is: VR = \j<y OC + ST + SP + PS + °R1 = a a a E '3P 7 S Therefore, total rms error in differential measurement mode is: a = ^2*a d 5.7 R + Tl/Q = lips Conclusions We have developed a high-resolution jitter measurement circuit and jitter generator block. A l l the circuits are digital and fit well in a digital A S I C design flow. The total area of the circuits in a 0.35^m technology is 450//m x 500/im, which is equivalent to 1200 doubledrive 2-input N A N D gates. The M a i n Controller was written as synthesizable V H D L code and the rest of the circuits were described at the schematic level. Automatic place & route were performed for all the circuits. Exhaustive simulations and analysis show that the jitter measurement circuit is capable of jitter measurement with resolution and accuracy in the order of 10 ps. 153 The digital and compact nature of this T D C circuit makes it very attractive for B I S T applications for testing high-speed serial communication interfaces, e.g., clock and data recovery, timing circuits, and edge placement circuits. Since the T D C provides a very highresolution time measurement capability, it is also suitable for use in design of all digital clock recovery and clock synthesis circuits. 154 Figure 5.22: Top block-level schematic of the jitter measurement circuit 155 Figure 5.23: Implemented T Q circuit 156 Bc2 i Bc1 I BcO I 3.670n A> B^ Checking T 3.660n T 2T measurement ref 3.650n ref ! measurement T 3.640n 11 ps ,-. 3.630n o a> 3.620n D- 34 ps 25 ps | f ^ ^ ^ w N ^ ^ A v ^ A ^ W J V ^ v M •B 3.610n 3.600n 3.580n 3.0u 7.0u 9.0u Time (s) 11 u 13u Figure 5.24: T D C resolution adjustment simulation waveforms 157 15u 17u Figure 5.25: T D C measurement error for resolution of 34.1 ps 158 C h a p t e r S u m m a r y a n d 6 C o n c l u s i o n s The IC industry is undergoing a constant evolution. This has major implications on test. Notably, two important requirements emerge. These are 1. the requirement for block re-use; and, 2. the need for cost-effective high-performance test capability. From the above, embedded test provides an attractive solution approach provided certain features are achieved. Such features include 1. compactness: i.e., small area comparing to the circuit under test ( C U T ) ; 2. design simplicity and robustness: i.e., resistant to process variations, temperature and power supply variations; 3. digital output generation: i.e., generate one or more digital signatures which can be sent off-chip at relatively low speed, e.g., serially; 4. accuracy: measurement accuracy must be sufficient for the test; 159 5. calibration: i.e., calibration-free, self-calibrating, or use signal readily available signals to the chip for calibration; 6. performance impact: i.e., the impact on the C U T performance must be minimal. Meeting all the requirement above is a challenging task especially for functional B I S T or embedded test of high-performance high-speed circuits which require high resolution and high accuracy. A t the outset of this research only a few solutions with limited applicability were known to exist. In this research, two different embedded test methodologies for mixedsignal circuits were developed: (i) on-chip power supply current (IDD) monitoring, and, (ii) on-chip jitter testing. One important demonstration of this research is that designing feasible embedded test methods for testing high performance mixed-signal circuits is possible. This demonstration counters the often widely-held opinion to the contrary. A reason for such capability is that often the test circuits are not required to test the full functionality of the C U T , thereby relaxing the requirements of the test circuits. In regards to current monitoring, the main challenges in devising an effective on-chip IDD test scheme is designing a built-in current monitor ( B I C M ) that has minimal impact on the analog C U T performance while maintaining a good measurement sensitivity, and also generates an on-chip signature in a relatively small silicon area. We met this challenge by designing a novel B I C M structure. The B I C M has two major pars: a current mirrorbased built-in current sensor (BICS) and a single-phase built-in current integrator (BICI). The B I C S structure had been reported previously but the novel, thorough performance analysis and actual chip fabrication and characterization were performed. Results confirm that the B I C S impedance can be decreased to acceptable levels (~ 3fl) while providing a high 160 sensitivity and accuracy by using only a single-stage feedback amplifier. A l s o , we found that i n submicron C M O S technologies, even small routing resistances can cause significant error in current mirror operation. Our investigation shows that a 2% accuracy is achievable if special attention is paid in routing the current mirror connections. Moreover, the specific B I C S impedance has a bandwidth of 5 M H z and the current mirror bandwidth of 120 M H z . These are sufficient characteristics for many practical purposes. The B I C S is a relatively simple design that requires matching only two transistors in a current mirror. With respect to the B I C I , we designed a new integrator structure to meet the challenge of reducing the size of an integrator circuit with a long time constant. This structure employs a novel technique of breaking the long time constants in analog domain to shorter ones and transforming the remainder of the operations to digital domain. This results in a drastic saving in silicon area while providing the additional benefit of yielding a digital signature at the end. The implementation of this structure is simple because it contains only switches, capacitors, a comparator, and a small digital circuit. A l s o , a two-point calibration makes the circuit robust against process variations, temperature, and power supply variations. However, an off-chip or on-chip current source is needed for this calibration. The specific implementation of B I C I yields an accuracy of 2% i f the I D is not correlated with D the integration control signal. The B I C M can be used to test different analog blocks where IDD contains A C components. Typically, this test is not conclusive but it can reduce test cost by weeding out many faulty devices earlier in the test. The novel technique of 'quantization residue feed forward' was invented to achieve more integration accuracy for arbitrary IDD waveforms. In this technique, instead of discarding quantization residues at each digitization cycle, they are stored and used in sub- 161 sequent cycles. Employing this technique in combination with using two complementary integrators in parallel led to the design of a double-phase B I C I . This structure is about 20% larger than the single-phase B I C I , but it is accurate to within 1 % regardless of the IDD waveform. This B I C I extends the use of B I C M for IDD testing to a larger number of analog circuits in comparison with single-phase B I C I because of its higher accuracy which is i n dependent of IDD waveform. In regards to jitter testing, our novel approach is the first circuit which can perform single-shot jitter measurement with accuracy and resolution in 10 ps range, while satisfying all the requirements for a practical embedded test scheme. Prior to this research, there has been no such circuit reported in open literature. The circuit is composed of two parts: a jitter generator and a jitter measurement block. The jitter generator occupies an area equivalent to 200 2-input N A N D gates. It accepts a jitter-free signal and digitally modulates it to generate an output signal with controlled jitter. The amplitude and frequency of the jitter signal are programmable. The jitter measurement circuit (JMC) uses a differential ring-oscillator technique to achieve high-resolution. The resolution of this circuit is programmable; the minimum guaranteed resolution depends on process variations. A very important side product of the differential nature of the circuit is robustness against power supply noise which result in a significant accuracy improvement. Since parts of the circuit are asynchronous, a new technique, time-diversity sampling, was developed to ensure valid sampling and correct operation. J M C calibration is practical and simple because the same signal which is used for clock synthesis is also used for calibration purpose. 162 A J M C prototype has been designed in a standard 0.35 pom C M O S technology. Simulation and analysis predict a measurement accuracy of about 11 ps rms and a a resolution of 10 ps for this implementation. The total area of the circuit is equivalent to approximately 1200 2-input N A N D gates; less than 10% of this area is occupied by time-sensitive circuitry. The time-to-digital (TDC) circuit at the core of J M C , can measure 1 ns time interval in about 400 ns. Therefore, the approximate test time for measuring 1000 jitter samples on a 155.54 M H z P L L (OC-3 Sonet standard) including resolution and calibration time is about 0.5 ms. This number of samples is sufficient for histogram-based testing. The predicated resolution and accuracy of the J M C is sufficient for testing S O N E T OC-3 (155 M H z ) and even OC-12 (622 M H z ) signals because the measurement resolution required for testing these signals are approximately 64 ps and 16 ps, respectively. Because of the single-shot measurement capability of the the J M C , it can be used to analyze the jitter frequency components, thereby, enabling frequency-dependent jitter standard compliance test. This is an important additional advantage over previously reported J M C ' s . 6.1 Future Research This research demonstrated the feasibility of designing high performance and robust embedded test circuits. More embedded test circuits are needed for testing future high-performance mixed-signal circuits such as high-speed A D C s , D A C s , and analog equalizers. Calibration is a very important aspect of any measurement circuit. The B I C M and B I C I in this work require accurate current sources for calibration. Some ICs may have such sources available on the chip. However, for the more general cases, new self-calibration techniques w i l l be required, or calibration should use typically accurately-controlled power 163 supply voltage and/or clock signals. The 11 ps (rms) precision in the jitter test circuit is sufficient for testing 155.54 M H z and possibly 622.2 M H z clock recovery and synthesis circuits. However, new techniques capable of reducing the noise in the jitter measurement circuit would have to be devised to extend the ability of this circuit for testing 1.2 G H z circuits and beyond. Some proposals include using faster ring oscillators, using clean (low jitter) clock signals in measurement and not just in calibration, and extending the differential structure to other parts of the circuits. Also, the use of C L cells requires the ability to add cells to digital cell libraries. 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Test Conf, pp. 805-814, 1993. 177 A p p e n d i x B I C S F r e q u e n c y R e s p o n s e A A n a l y s i s This appendix shows how the symbolic toolbox of M A T L A B [99] has been used to determine the frequency response of the B I C S circuit in Fig. 3.3. First, the following steps are performed: 1. The nodal equations of the circuit ac model are written in terms of resistances, transconductances and'Capacitances. 2. The nodal equations are solved to obtain , , 7 Z where NBIC(S) and B DBIC(S) I C { S VBIC(S) ) J D M = NBIC(S) = BSMS) are the numerator and denominator of the ZBIC(S), re- spectively. 3. In NBW(S) = a + as + ... + a s 3 0 x 3 and D ic{s) B = b + b s + ... + b s , each of 4 Q x 4 coefficients a,-, i = 1 , . . . , 3, and bj, j = 1 , . . . , 3, is expressed as a sum of products: Li i=\ 178 1=1 where Li, Kj are the number of product terms in a bj, respectively, and, PDu, PN i iy 3 are the /-th product term in ai,bj, respectively. The second column in Table A . l reports the number of product terms in each of the coefficients (Z/ s and KJS). 8 4. For each a, and bj, the magnitude of some product terms is negligible compared to that of others. To identify such terms, the operating point values of various resistances, transconductances and capacitances in the circuit's ac model are substituted in the expressions for each product term. These operating point values are obtained by circuit simulation. For the circuit in Fig. 3.3, the Spectre [101] simulator and B S I M 3 M O S models were used. 5. For the coefficient a,-, i = 0 , 1 , 2 , 3, and bj, j = 0 , 1 , 2 , 3 , 4 , only the significant product terms with a magnitude greater than 1/10 of the maximum of all the terms are kept while the rest of the terms are assumed negligible, and consequently eliminated, i.e.,: if where PDi max PDu<PD J10 then ima = m a x ( P D , PD ,...). t l PDu = 0 The number of retained terms i n each co- i2 efficient is given in the third column of Table A . 1. The general forms of the resulting product terms for coefficients ai and bj are given in the fourth column of Table A . 1, where the i, j, k and / subscripts indicate the indices of different transconductances, resistances and capacitances. Initially, we assume that N ic{s) B root, s = Zd, at which a s 3 3 and a s 2 2 are negligible in comparison with a : Therefore: 0 z = a /a d 0 1 = 179 l/{r C ) 13 t has a Coefficient Total # of product terms # of significant product terms a a 10 45 a-2 as b 59 22 13 107 243 208 59 2 2 8 8 1 5 2 0 x 0 b bs b 2 4 General form of significant product terms QmiQmj 1 ^dl C iQmiQmj CiCjQmi Ci Cj Cl 1 QmiQmj QmlQmk Qmi Qmj Qm I Ck QmiQmj CiCk 8 8 Qmi Cj Cl Ck Ci Cj Cl Ck Table A . 1 : Number of product terms in the coefficients of where r 1 3 = r | j r and C = C x 3 t comp and NBIC{S) D ic{s) B + C \gs 2 N o w we verify that a s and a s are indeed much smaller than a by showing that 3 2 3 a s /a 3 3 <C 0 and a s /a 2 of O.lpF to 0.55pF, r 0 -C 0. To do so, note that the C;'s, C / s and G V s are in the range 2 0 2 0 and r -'s in the range of 0.7 Mfl to 1.3 MQ, and g s between 1 0 / O _ 4 1 3 t mi and 1.3 x 1 0 / f i . Hence, the ratio of a s _ 4 3 3 and a s 2 2 (C;C,-C,)/(r?,C?) gm,g i/ri 3 / m ' gmigmi/ri 9mi9mi /i r to a at s = z<i evaluate to: 0 1 g i9mir'( ~ I O " m 4 (IA) 3 IO" gmiri3 2 The above approximation verifies the assumptions used to calculate s = z . Numerical d solutions of NBIC(S) = 0 and DBIC(S) = 0 show that the rest of the poles and zeros of the circuit are located at frequencies at least 10 times higher than z . Therefore, z , rewritten d d below, is considered a dominant zero: d z = -I I {Ccomp + 180 C )(r \\r ) gsl2 dl d3 (2A) A p p e n d i x N a n d I R e l a t i o n s h i p i n t h e B S i n g l e - P h a s e B I C I This appendix contains the derivation of Eqn. 3.16: N =KT7+0 + E (IB) In the circuit shown in F i g . 3.6, the counter is incremented by the value Ni at the end of the integration sub-window ch . Ni corresponds to the number of clock ( C L K ) cycles i+1 that span the time takes for Vs to ramp from 0 to V (voltage stored on C ) . Since the ramp 4 slope is K r = Iramp/Ci, the counter is enabled for a time Td during the (i + l ) - t h period of 0: T C < = h T where r is the delay between the time Vs = Vi and the time counter stops counting, r is due to the comparator delay and input offset voltage, and the propagation delay from node 181 r l to ijrst. Therefore, A ,- can be obtained from Eqn. 2 B . 7 N = ^ - Q , CLK l ( 2 B = Vi + ' rp J-CLK . jy rp J^rJ-CLK where T LK C ) Qi ^ 1 1 is the period of C L K , and Qi is the quantization noise. Assuming that the / and C L K signals are uncorrelated, Qi can be considered as a random number uniformly distributed in the range (0,1) with a mean and variance given by: m =0.5 Qi Since N = E ^ o N 1 if (3B) from (2B), M-I x = E ( 7 ^ Vi + Qi) i=0 r J-CLK J-CLK M-l = i^v— E (V) + T ^ - - Q l\ JCLK JCLK N (5B) A 1 r where Q = Ylfio 1 (6B) i = 0 Qi- Since the Qi's are independent and M is generally large, from the central limit theorem Q has a Gaussian distribution with a mean and variance given by: m Q =0.5M (7B) = ff (8B) a\ To complete the derivation, V = E ^ o Vi is obtained from Eqns. 3.15 and 3.14: M-l v = £ Vi i=0 M-l 1 M M , M-I = K * E t=0 (9B) (T^TTT j Idt + KiiV^] "r - < M-l J. = 7^~7T E / ' Idt + K K <^1 + ^2 , ; Jti U l l /2 Jt 23 =n 182 21 M-1 J2 Vi Replacing V and V from Eqns. 3.15 and 3.14 recursively in Eqn. 9 B yields: c jyVM = M-l E [1 + (#23^21) + (K K ) + ... + (K K ) - - } 2 u i + °2 K 23 M 21 23 1 / ' Idt Jn 1 21 i = 0 - (K K ) -\ r< M 23 23 + C2 ^i=o 21 i - A23A21 f f ( UJn 1 i = 0 M t (10B) Generally, C , » C , therefore, A 2 r 2 3 ii r < 1 and [1 - ( A ' / < 2 i ) - ] = 1 for i = 0, M - 2. M 2 1 J 2 3 Hence, Eqn. 10B simplifies to: V M-i ; s < / , ' * * > t M ( c 1 c + where the term K K 23 2 ) ( i f ™_l 2X 3 - [ M l ) K * K * 1 1 : ^ ( I I B ) Idt is the effect of the residual remained on C at the begin- t 2 ning of M - t h integration sub-window. This term can be ignored because (i) (K23K21) <C 1 and (ii) the term J i ^ J Idt is the result of integration in only one integration sub-window, 1 whereas, TJ^LQ (/ / /<i£) is the integration result over a large number of sub-windows. This 1 t yields: V M where A " = c c ) a - A - A - ) • M ( 1+ 2 23 = K M S u b s t i t u t i n 21 £ t'=0 'idt (12B) ' Jt g U = s iT a n d = (* + 1)T, - T R into Eqn. 12B yields: V M = K M Y ( = K M where R = J2iio 1 I(!+I)T!-T R f Jo I Idt - d t - / ) Idt KR M The reset error, /?, results from not integrating 7 for a time T R in each sub-window. This is required to reset the circuit for integration in the subsequent sub-window. Denoting each term in J? as i ? , then: t r-(i+l)X r(i+l)l Ri = / s s 183 Idt (14B) TR can be such that -C 1. Assuming 1 / T R is much larger than the bandwidth of I, I TR/T S can be considered as approximately constant during the time TR. Therefore, we can express Ri as: Ri = I(t")T R where t" = iT — TR/2. Since the time t" is set by <j> which is independent of I, I(t") can s be considered as a random variable. Assuming t" is uniformly distributed over one period of I, the mean and variance of Ri are given by: m •= T ^ Rl R f' Jo I(t)dt = T II < =T [~J^\l{t)-l)dtf t 2 C R = R where Tj is the period of I and J 1T lJ Tl c is the ac power of the signal I. Assuming i?,'s to be mutually independent, then: m= MlT (15B) a= Mlf n (16B) R R R c F r o m Eqns. 6 B , 13B: N = K jK T K M r f Idt + MT/TCLK Jo - K R/K T K T CL M r - Q CL (17B) Substituting the mean of Q and R from Eqns. 7 B , 7 B , 15B and 16B into Eqn. 17B, yields: N = K f Idt + O - E Jo (18B) T where K = KM/K TCLK, 0 = r - M ( 0 . 5 - K 1TRJK T K) MT/TCLK M r CL and E is a random variable with zero mean and variance: ' 4 = M ^ ( / d 184 ^ ) 2 ^ ] U 9 B ) A p p e n d i x T V a n d I R e l a t i o n s h i p D o u b l e - P h a s e i n C t h e B I C I From F i g . 4.5, assume a half-wave integrator integrates the current I from U = iT to t • = iT + T/2. Therefore, the voltage vc {t) across C is 2 2 The voltage vC2(t) is sampled and held at t • = iT + T/2 such that: 1 V 2 = vc2(t)\ . C t=t iT+T/2 r = j — ^ I Idt (IC) F r o m t = iT + T/2 tot = (i + 1)T, the charge on C is transfered into C . Therefore, the 2 3 voltage across C at t = (i + 1)T is 3 C 2 K73 = 7=r^c2-+ K - i + V C M P I u 3 where V ^ is the initial voltage on C remaining from the previous digitization cycle and i VCMPI 1 3 is a constant voltage resulting from charge accumulation on C due to comparator 3 185 input voltage offset and delay. F r o m t = (i + 1)T to t = (i + 1)T + T/2, V £ is digitized 3 by counting the number of clock cycle it takes to discharge C . The discharge is performed 3 using current I until v (t) becomes negative. Therefore: ramp C3 C (V£ 3 where TQMP2 - V£) = (NiTck + 3 r P2)I, ramp CM is delay due to input voltage offset and switching delay of the C O M P 2 , T ik c is clock period, C is the effective capacitance being discharged, and N is the number of 3 cycles it takes to discharge C' . Note that two different values for C are considered for 3 3 charge and discharge cycles to include different parasitic capacitances that affect C in these 3 two cycles. N's (i = 1 , . . . , M) are added to obtain half-wave integration result for / , N, as follows: M =]£>,• =1 N _ — MT P2 CM T clk ± C V MPI 3 C' C C 3 ^ 2 • T T r T T J-clk-^ramp clk ramp _Q C M 2 _ ! (2C) R 1 t Substituting V£ from Eqn. I C into 2 C yields: 2 ~ iT+T/2 N =K J 2 . Idt + O + Q „_n i=0 JiT M x r where Q = V^' 1 is the quantization voltage error, K = c' c — is the proC J- clklramp(Cl + t>2) 3 3 portionality coefficient, and O = (Ml£^l f-clk + 186 ^ W i J-clk + ramp ) i s ± Q o f f § e t 2 A p p e n d i x T D . l Two-point D C D C a l i b r a t i o n Calibration A s shown in Sec. 5.2.6, the following relates T , the time interval to be measured, and N, d the measurement made by the T D C : NT =T A d +T +T +T c In a two-point calibration scheme, T Q (ID) R and Tc are estimated by measuring two ref- A erence time intervals: N nT& = T i + T + TQI + T ca cat c RX (2D) NcattTfr = T l2 + Tc + TQ + T R ca 2 2 Therefore, T _ T i2 - r ca ~ N cal2 7q -T c a j l - N 2 + call Q l N cal2 187 -\-T - N R 2 call - T R1 = T A O + r A e ( 3 D ) where T A 0 is the estimated T A and T TAO is the error associated with this estimation: A e T l2 — T n ca — ca N l2 — N n ca ca — TQI + Tm — TQ 2 T Ae TRI N i2 — N n ca ca TQI and TQI are two independent and uniformly distributed random variables in the range [0, TA) (with mean of T / 2 and variance of T / 1 2 ) , and, T R I and TR are two independent A A 2 normally distributed random variable with a mean of zero and standard deviation of Therefore, from Eqn. 3 D , T A e A e = 0 rp2 6(iV cal2 R is a random variable with the following mean and variance: ™r The larger the term (N a. co/2 — N n), n 2 - N y + call (N cal2 - N y ' K call the less the error in estimating T . ca A Tc is obtained as below: rp _ T i N n J-C ju ca 2 ca — T uN i 77 ca ca 2 r (TQ + T )N n 72 where Tco is the Tb estimate and Tc e R2 — (T 77 ca Q1 + T )N i R1 ca 2 - i CO + 1 Ce is the random variable indicating the uncertainty in estimating Tc: ^ T iN n — T nN i lco = M al2 — Ncall ca 2 ca ca ca 2 (5D) C _ {TQ.2 + T )N - (TQI + J-Ce 77 ^Vca/2 — i V / T R2 can ca The mean and variance of Tc e x are obtained as below: TA 188 T )N i Rl ca 2 (6D) ~2 l l , ,2^ + T ( cal2/N^) ! N 2 Using the number N associated with measuring an interval T i n Eqn. I D , the T d d estimate given by the T D C , T , is: d Td = NTAO — Tco Therefore the measurement error is: T,u = T -f d = NT d Ae +T +T Ce +T Q (8D) R The mean and variance of the measurement error are: m = NrriT Tde 4 , =N ^ +a 2 N (T /6 2 = +a 2 TAe 2 Tce + a Tce + rn + m R - A ^ ) = (1 + ,* 2N + Assuming T cal2 N 2 + 2 Nj^ \ + R = 0 (9D) R 2 2 Q 2 Q + 2a ) 2 +m Ae { ^ I J fffl) 2 + T J 2 U + a R ( 1 0 D ) )(T1/12 + ^ ) = 2T n and T ca + Nj, (£HvJ U + > > T , one can conclude that N ; c a / 1 c ca 2 ~ 2A^ ca/1 . Under this assumption the statistics of Tc are: e 2 _ A Jc« 01 Furthermore, assuming N < < (N i2 — N ii), ca T - a de yTl/2 + Qa . If a R ca , c2 ' rt the rms measurement error is is considered negligible, the rms measurement error due to R quantization is obtained as T / \ / 2 and the worst case error (3cr band) is ±(3/\/2)T A A ±2T . A 189 ~ It is noteworthy that in Eqn. 8 D Tc and T e are constant for all the actual measure- Ae ments since they are a result of calibration, whereas, TQ and TR vary for each measurement sample. D.2 n-point Calibration Technique A method to increase the accuracy of measurement accuracy is to limit the variation range of Tc, Tce, in Eqn. 8D. This means reducing the variance a T c e . This may be done by the using n-point calibration technique described next. In this technique, n accurately known time intervals are measured by the T D C . These time intervals are multiples of a reference interval T i = 0, T f, 2T f,..., ca re re (n — l)T f. re Assuming TR is negligible, the measurements can be expressed as below: N±T A =T C +T (UD) Q1 NT = T f + Tc + TQ NT = TTref + T 2 3 A A re (12D) 2 C + TQ ' 3 (13D) (14D) (15D) (16D) NT n A = (n - l)T ref +T + T c Qn (17D) The objective o f n-point calibration is to limit the range o f T Q I variations, which i n turn reduces <J . Tce 190 In Eqn. 11D to 17D, T f and T A are assumed to be known ( T A can be estimated re within a 0.1% accuracy using two of the chosen calibration points as discussed in Sec. D . 1). Assume the following is denned: N T ref where N f re =T A reJ +T . Qref (18D) is an integer and TQref is a time interval i n the range [0, T ) . Since T f and A T A are accurately known, N j re and TQ f are also known from Eqn. 18D. Substituting T j re re re and Tc from 18D and 11D, respectively, in Eqn. 12D yields: NT 2 A -N T ref - A ^ T A = T Q - TQI - T A 2 (19D) QreJ The right side o f Eqn. 19D is a multiple of T A . Therefore, the left side must also be a multiple of T . Since T Q I and TQref must be i n the range [0, T A ) , the two following cases are A possible: CASE 1 : T Q — TQI — r 2 TQ = T 2 CASE 2 : g i Q1 2 (21D) r( Q TQ = T (20D) + TQ ,f T -T -T ref Q2 =0 Q r e / = -T (22D) - T (23D) A Q1 +T f Qre A Since T Q € [0, T A ) , Eqns. 21D and 23D result in two different ranges for T Q . The inter2 2 section of these ranges with [0, T ), results in a smaller range for T Q as shown below: A 2 C A S E 1: TQI <G [-TQref, T - T f) A Qre f|[0, T ) A (24D) e[0,T -T f) A Qre and N =N 2 ref 191 +N 1 (25D) C A S E 2: TQI € [ T A - T j, Qre 2T - T ) A f|[0, T ) QreJ A (26D) € [ T A — TQ f, T A ) re and ^ 2 = A^re/ + A^i - 1 (27D) Therefore, i f Eqn. 25D holds, the range of variation for TQI is limited to the range in Eqn. 24D. Similarly, the range in Eqn. 26D applies i f Eqn. 27D holds. The process of limiting the range of variations for TQI can be continued by adding another calibration point, e.g., 2T j (Eqn. 13D). Substituting T j and Tc from 18D and re re 11D, respectively, in Eqn. 13D results in: {N - 2N 3 ref - Nr)T A =T - T Q2 Ql - 2T Q r e / (28D) Using the same reasoning as before, three cases are possible: C A S E 3: TQ — TQI — 2TQ j TQ = TQI + 2 2 =0 re (29D) 2T f Qre Therefore: TQI G [-T , Qref T A - 2T ) Qre} f][0, T ) A (30D) € [0, T A — 2TQ f) re and W = 2W 3 r e / + (3 ID) C A S E 4: TQ2 ^ T Q I — 2TQ f re =—TA (32D) TQ2 = TQI + 2TQ y — T A re 192 Therefore: TQI € [T - 2T j 2T A Qre 1 e [0, 2 r A - 2T f) A fl[0, 7 A ) Qre - 2T ) Qref if T if T - 2T € [ T - 2T ,T ) A Qref A - 2T A <0 Qref A Q r e / (33D) > 0 and N = 2N 3 + A! - 1 (34D) 7 reS C A S E 5: TQ — TQI — 2TQ j = —2T TQ2 = TQI + 2TQ f —2T 2 re re A (35D) A Therefore: TQI G [ 2 T - 2T , A Qre} 3T - 2r A ) fl[0, T ) Q r e / A G [ 0 , 3 T - 2T ) A e [2T - 2T , A if Qref Qref T) 2T if A - 2T A <0 2T Qref A - 2T Qref (36D) >0 and A^ = 2N 3 If both T ref ref + N -2 (37D) x and 2T j are used, the intersections of C A S E 1 or 2 with C A S E 3, 4 or 5 w i l l re result i n tighter bounds on T Q I which yield a more accurate estimate of T . c 193 A p p e n d i x M e t a s t a b i l i t y w i n d o w o f a D E f l i p - f l o p This appendix provides an estimate of the metastability window for a D flip-flop in a 0.35 lim digital cell library obtained through simulation. Assuming the two signals D i n and clkin are applied to the D and c l k inputs o f a flipflop, respectively, we define TD as: I'D — Welkin where t£> and t i in c kin ^Din indicate the times at which the rising edges of D i n and clkin signals occur. Denoting the flip-flop's setup time by r flip-flop as the time interval [—T /2, T /2] mw Tsetup T j2 mw mw *C setup , we define metastability window of a such that i f Tsetup ~\~ Tfnyj j2, then the nominal clk-to-Q delay o f the flip-flop (r ik-t -Q.) c We choose r m t 0 is increased by an amount r . mt = 3 ns [104] because this value is close to TB, the oscillation period of the oscillator B i n the prototype T D C implemented (details given i n Sec. 5.5). A n y delay exceeding this threshold may result in a T& measurement error, as explained in Sec. 5.2.4. 194 The test bench shown in F i g . E . l (a) is used to estimate T . The buffers and the mw vss (a) (b) Figure E . 1: The test bench for estimating the metastability window of a D flip-flop O R gate are used to model the inverters and the loading at the output of E O C . D F F in the T Q of F i g . 5.6, respectively. The timing diagram for input signals D i n , clkin, and rb are shown in Fig. E . l ( b ) . This circuit is simulated for different values of TD and the Q output is monitored. The simulated D F F output for five values of T , illustrated in F i g . E.2, show D that the D F F output switching delay increases as TO approaches T . Plots of Fig. E.3 setup show T ik-to-Q versus T . These plots indicate that for T c L O W , whereas for r D D D = 80.17ps, the output remains — 80.18ps, the output switches H I G H . The additional clk-to-delay (compared to the nominal delay) for T D — 80.18ps is approximately 460 ps which is still less that the 3 ns threshold. This result suggests that the metastability window of the D F F is T mw < (80.18 - 80.17) ps = 0.01 ps. 195 196 A p p e n d i x R a n g e E x t e n d e r B l o c k F A n a l y s i s In F i g . 5.7(b), the numbers at the outputs of cntrA and cntrB versus time can be expressed as follows: (IF) M (t)= B where M~A(0) and M (0) A L ^ ^ J + 1 + M (0) S (2F) are the initial numbers in c n t r A and c n t r B at times t < 0, respec- tively, and To in the delay between the first rising edge of c l k A and that of c l k B , and [X\ represents the integer part of X . A s time progresses, for some value of i, the i-lh rising edge of c l k B precedes that of c l k A 2 , i.e., t 2(i) > ts(i)- A this time, the outputs of cntrA and t A cntrB become equal for a very short amount of time (t eg in F i g . 5.7(b)). Therefore: M (0) + ±- = N + M (0) + t-—^- = N + e A A B l-e l t 197 A (3F) B (4F) where Ni is the state of cntrA and cntrB, and e and e A are two very small real numbers. B Assuming c and e are almost zero at t , eliminating Ni from Eqn. 3F and Eqn. 4F, yields: A A eq M (0) A + ±- = M (0) B + •LA + 1 (5F) 1A Therefore, t = ^T A ^ + (M (0) - M (0) A B - l)~T (6F) A is the number of cycles it takes for the i-th edge rising of c l k A 2 and that of c l k B to match. Therefore j^T A is the total time needed for this edge matching to occur. Since the goal is to have these edges match after j£T , the term (M (0) A A - M (0) B - l)^T A must be identically zero, i.e., M (Q) A = M (0) + 1 B (7F) Eqn. 7F shows that c n t r A must be initialized to a number corresponding to the initial state of c n t r B plus one. 198 A p p e n d i x T w o - P a r a m e t e r M o d e l G a t e f o r G V ^ - i n d u c e d D e l a y V a r i a t i o n s In this appendix, two different tests are described to validate the two parameter noise model in Eqn. 4 H . We wish to model the effect of power supply voltage variations ( V ^ e ) ) on gate delay. We denote this variation by r . e G . l T e s t 1: S i n g l e G a t e D e l a y S i m u l a t i o n s Assume the propagation delay variations of a digital gate is obtained as below: Te = iVe + RToVe where r is the static delay of the gate (assuming no power supply noise) and 0 Ve = ~ T Jt=t 0 V (t) dd(e) 0 199 (IG) where t is the time the input of the gate crosses the gate switching threshold. A first test 0 to validate the model in Eqn. I G is to assume the above model for delay variations of this digital gate, and obtain 7 and p by fitting simulation results to the model. The discrepancies between the simulation results and the fitted model w i l l indicate the model accuracy. To perform the test, as shown in Fig. G . l , a digital gate is loaded with a capacitor to generate different static delays. For each case, r is measured through simulation for differe ent values of V . For each value of V , the coefficients jV e e e and pV in Eqn. I G are obtained e by fitting the simulation data for different loading values to a straight line in M A T L A B . Then, these coefficients are divided by V to estimate 7 and p for each value of V . The ave e erage value of all these estimated coefficients is used as an estimate of 7 and p, respectively. VDD, VSS VSS 3.3V0.33V Vin t 3ir*\ 200n Figure G . l : The test bench for validating the two parameter model for V -induced delay variations dd 200 gate Parameter 7 (ps/V) P (IV) rms error (%) LOW-to-HIGH transition INVX1 I N V X 2 N A N D X 1 N A N D X 2 HIGH-to-LOW transition INVX1 I N V X 2 N A N D X 1 N A N D X 2 -4.4 -3.81 -3.76 -3.67 -2.27 -1.93 -2.94 -2.83 -0.135 -0.153 -0.166 -0.172 -0.219 -0.222 -0.217 -0.218 4.5 4.3 4.5 4.5 4.6 4.45 4.8 4.2 Table G . 1: 7 and p estimates and the resulting model errors for four different digital gates The above test was performed on four different types of gates in a standard digital cell library for a 0.35 p.m C M O S technology: a single-drive inverter; a double-drive inverter; a single-drive 2-input N A N D ; and a double-drive 2-input N A N D gate. The loading capacitances used were 0 to 70 fF in steps of 5 fF. Also, Vdd(nominai) — 3.3V and —165 ?nV < Vdd(e) < 165 mV which is equivalent to 10% peak-to-peak variations on V . dd Table G . l , lists the estimated values of 7 and p for L O W - t o - H I G H and H I G H - t o - L O W input transition for each type of gate. The rms error in each case, given in the last column, is less than 5% in all cases which proves that the two-parameter model of Eqn. I G is adequate to model gate delay variations due to power supply noise. G.2 Test 2: R i n g Oscillator Test A ring Oscillator is an efficient circuit to test gate delays. In this section, we validate the twoparameter gate delay variation model by comparing the simulation and modeling results for the output period and accumulative V -induced dd jitter. The output period of a ring oscillator (Fig. G.2) is a summation of the L O W - t o - H I G H 201 Ring Oscillator Digital Gate Digital Gate 1 I VSS Figure G.2: The ring oscillator test bench to validate the two-parameter model for V induced gate delay variations dd and H I G H - t o - L O W propagation delays of all the gates in the loop: T 2N = XX <7«0 + T ) i=l T g{i)e where T is the output oscillation period, T ^ g and r ^ 0 g are the i-th gate's static delay and e delay variation, respectively. Therefore, the period jitter T is e 2N e = Y2 9We *=1 T T Using the two-parameter model for gate delay variations yields the following for T : e I r i+ ati)0 Te = E l 7 ( — / ^) ,=1 9(i)0 > t V T Assuming T g{i)e « d t Jt r ), g{i 1 T 0 and also that r r i+ g(i)0 ) +^ « o ( / Me)dt)} 9(i)0 < t T (2G) V T g W o =T 5 ( 2 ) 0 Jt = . . . = T )o, Eqn. 2 G simplifies g{2N to: T e = ( — + p) f ' fU+T = «y # where K is a constant and + T V dt dd(e) (3G) v dt dd(e) is the beginning time of the i-th period. Note that T in Eqn. 3 G e is independent of the number of gates N and the output loading of each gate. To validate 202 Eqn. 3 G , a ring oscillator consisting of 21 N A N D gates in a 0.35 fim C M O S digital cell library was simulated with a number of sinusoidal power supply noise waveforms of the form: V dd(e) for V E = V sm(2nft) (4G) E = 0.165V, denoting ± 5 variations, and /=5 M H z , 50 M H z , 150 M H z , 350 M H z , 650 M H z and 1.1 G H z . A wide range of frequencies have been chosen to validate model for a large frequency range. Figs. G.3 shows that the derived model with parameters obtained previously matches the simulation results within 2% in for all the tested frequencies. A s a by-product of the above analysis, we obtain the peak-to-peak period jitter, T ( ) , e pp for sinusoidal noise. This gives insight in the jitter behavior of ring oscillators in the presence of power supply noise. This is especially important whenever ring oscillators are used for timing purposes such as in the T D C application. Substituting V ( ) from Eqn. 4 G in 3 G : dd V T ( p)=4K—sin(—-) ui E e P e LOT Z The above shows that the jitter at output of a ring oscillator decreases as the noise frequency increases. 203 -0.2 -0.1 0 V (V) 0.1 0.2 e -0.2 -0.1 0 V (V) 0.1 0.2 e Figure G.3: Ring oscillator period jitter from simulation and the two-parameter model for Kw-induced gate delay variations, a ) / = l . 1 G H z , b)/=350 M H z , c)/=50 M H z , d)/=5 M H z 204 A p p e n d i x T D C P o w e r S u p p l y N o i s e H A n a l y s i s In this appendix, we analyze the effect of V^-induced jitter in T D C ' s Oscillators A and B on the accuracy of the T D C . We show that the differential nature of our T D C eliminates significant parts of the power supply noise. We denote the error component due to power supply noise by Eps- F r o m Eqns. 5.23 and 5.21: N-l 2M-1 EPS = £ [ £ j=0 «=o where ^ e and ^ e - 4.)e)l ( 1 H ) are the propagation delay jitter of the i-th gate of Oscillators A and B i n the j - t h period of c l k A and c l k B , respectively, and M — M A = Mp is the number of gates in oscillators A and B . Defining the index k = Nj + M, the double summation in Eqn. I H can be reduced to one summation: 2JVM-1 EPS = where r ^ f c ) e and r ^ f c ) e E ( g(k)e ~ f(k)e) k=0 T T (2H) are the variations of gate delay for the fc-th switching event in oscil205 lators A and B , respectively. To estimate the relationship between Eps and power supply noise Vdd( ) > gate delay e variations, r ^ j and T^ , f c e £ are modeled as follows: 9(k)e = (l + PT k )V k)e (3H) g(k)e = (7 + ^ (4H) T T A A 9 { )0 f c ) 0 { )V f ( ) e where 7 and p are constants; and: V - ^ l l i ^ V (k)e - ^ J ^ J * g(k)0 k A B V where t A { k k ) ) ° Vdd {t) (e) (5H) ° (t) (6H) V dd{e) and tf are the times at which the input switching thresholds are crossed in oscilla- tors A and B , respectively, and V^( ) is the difference between the actual Vdd e a n d the nominal noise-free value: V d( ) = Vdd — Vdd{nominai)- Note that in this analysis the switching threshd e old is Vdd(tk)/2. Eqns. 4 H and 4 H model V^-induced gate delay variation as a function of two Vdd-dependent components, one independent of and the other one proportional to static delay of the gate. To validate this model, two different tests have been performed. Details are described in Appendix G . F r o m F i g . 5.7, for the interval t = 0 to t = T , only oscillator A oscillates. Assume d A ! switching events of oscillator A occur during this interval. We split our noise analysis 7 into two parts, one due to switchings from t — t — 0 to t — td = Td, and the second 0 part due to switchings events from t = t to t — t d eoc = T oc, where t E E O c ( E O C : end of conversion) is the time the T D C requires to terminate the measurement ( 2 M W - t h edges of switching events in O s c - A and Osc-B occur at the same time). Therefore: Ep S = Ep [ ) S a 206 + Eps(b) (7H) where: Ni-l E a) = PS( E ^1*)e, k=0 2MN-1 2MN-1 E r ^ - E k=Ni k=0 E = PS{b) ) (8H) ( e 9 R ) Assuming that the power supply noise in the [0, td] window is independent of the noise during interval [t , t ], the total rms noise is: d eoc PS - \J PS{a) + PS(b) a a a To determine Ep$( ), we use the analysis technique explained in Sec. G.2: a E =K f Vdd(e)(t) Jt=o (10H) Td PS{a) where K is a constant (see Appendix G . l ) . To obtain v , we substitute Ep and from 4 H and 4 H into 9 H to yield: T b) = T + r PS{ 1 (11H) 2 where: 2MN-1 ^TV, rt + T A q g(k)0 k 2MN-1 ,t +r T =[ 2 Since t^ P =t = t: E / * B E / V rt +T B k=Q g(k)0 2MN-1 t +T Jt=t A r 2MN-1 i A T A B B k Jt=t B r w ° W 0 - E / y w ° W t ) ] (i3H) d A " " ° ^ , ( t ) = E r . " w ^ r ^ w Therefore: T = 0 2 207 (14H) Assume that all the gates in oscillator A have the same static delay, and similarly for the gates in oscillator B , i.e., = T for fc = 0 , . . . ,2MN - 1 and T^ AO 0 k = 0 , . . . , 2MN - 1. F r o m t = t tot =t d = T O for B , there are 2MN - N and 2MN switching eoc x events in oscillators A and B , respectively: ™ T f l 0 2MN - N, ^eoc ~ td ^ M A T = = ( 1 ( 1 5 6 H ) , I T H ) where A i is the number of switching events occurring in oscillator A from t = 0 to t = T . d Therefore: ri =-iN (-^-- ) 1 ''eoc = — e d v (t) tc c dd{e) (17H) ^d Jt—td jNiV ' )(t ,t ) dd e where V ( ){t , t ) is the average o f V )(t) dd f° r eoc dd{e d eoc over the time interval [t , t ]. d eoc F r o m Eqns. 7 H , 10H, 11H 14Hand 17H, the following relationship follows for Eps: EPS = K f Vdd{e){t) - jNiV^iUfeoc) Jt=o (18H) Td Since T = d therefore: N±T , AO Tp S = T [nV e)(t ,t ) d dd{ 0 d • A0 V (t ,t c)] dd{e) d (19H) e0 T where V r (t ,t ) dd e) 0 the V -induced dd is the average of 1 4 ^ ) over the interval [t ,t ]. d 0 d Eqn. 19H shows that inaccuracy i n the ring oscillators is proportional to the time interval being measured, i.e., T . d 208 ,
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Embedded test circuits and methodologies for mixed-signal ICs Tabatabaei-Zavareh, Sassan 2000
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Title | Embedded test circuits and methodologies for mixed-signal ICs |
Creator |
Tabatabaei-Zavareh, Sassan |
Date Issued | 2000 |
Description | The rapid pace of the integrated circuit industry towards more miniaturization is making system-on-chip (SOC) a reality. For practical implementations of SOC, however, the test issues of such devices must be addressed through the integration of design-for-testability (DFT), built-in self-test (BIST), and embedded test for embedded blocks, such as digital, memory, and mixed-signal circuits. This thesis presents two novel embedded test solutions for mixed-signal circuits. The first one is a built-in current monitor (BICM) suitable for power supply current (IDD) testing. The B I CM includes a built-in current sensor (BICS) which provides high measurement sensitivity without introducing a large impedance in the IDD path. Although the BICS structure has been proposed before, the new circuit analysis and chip measurement results provide important insights into the BICS characteristics and design trade-offs. The BICM also includes a mixed-signal built-in current integrator (BICI) which generates a digital signature proportional to the average IDD (IDD)- TWO different circuits have been developed for BICI: a single-phase and a double-phase BICI; the first is less accurate but requires less silicon area. These new BICI architectures offer an advantage over previously proposed circuits because they can perform integration over large time windows (T > 1 ms) while occupying a chip area equivalent to a only few hundred NAND gates. The BICM is compact, accurate (error < 2%), and insensitive to process and temperature variations. The second embedded test circuit is designed for non-intrusive functional testing of high-speed clock-recovery units (CRU) and clock-synthesis units (CSU). To the author's knowledge, this new structure is the first circuit which can perform on-chip, single-shot jitter measurement with high resolution and precision without requiring element matching. The simulation and analysis predict a jitter measurement resolution of 10ps and a precision of 11ps in a 0.35 μm CMOS technology under typical power supply and thermal noise conditions. Combined with a jitter generator block, it can test intrinsic jitter, and jitter transfer characteristics of CRUs and CSUs. The circuit is digital, partially synthesizable, and automatically placeable and routable. Novel gate delay model and analysis techniques, supported by simulation, are also introduced to evaluate the accuracy of the circuit. |
Extent | 7296425 bytes |
Genre |
Thesis/Dissertation |
Type |
Text |
File Format | application/pdf |
Language | eng |
Date Available | 2009-07-23 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0065266 |
URI | http://hdl.handle.net/2429/11198 |
Degree |
Doctor of Philosophy - PhD |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Graduation Date | 2000-11 |
Campus |
UBCV |
Scholarly Level | Graduate |
Aggregated Source Repository | DSpace |
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