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Embedded test circuits and methodologies for mixed-signal ICs Tabatabaei-Zavareh, Sassan 2000-12-31

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Embedded Test Circuits and Methodologies for Mixed-Signal ICs by Sassan Tabatabaei-Zavareh M. Sc. (Electrical & Computer Engineering), The University of Calgary, 1994 B. Sc. (Electrical & Computer Engineering), Isfahan University of Technology, 1991 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Doctor of Philosophy in THE FACULTY OF GRADUATE STUDIES (Department of Electrical and Computer Engineering) We accept this thesis as conforming to the required standard The University of British Columbia February 2000 © Sassan Tabatabaei-Zavareh, 2000 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of &Jbsju'Cg Qz^ Cil^jl^Uf G^t^e/tLcj The University of British Columbia ^-^ Vancouver, Canada Date DE-6 (2/88) Abstract The rapid pace of the integrated circuit industry towards more miniaturization is making system-on-chip (SOC) a reality. For practical implementations of SOC, however, the test issues of such devices must be addressed through the integration of design-for-testability (DFT), built-in self-test (BIST), and embedded test for embedded blocks, such as digital, memory, and mixed-signal circuits. This thesis presents two novel embedded test solutions for mixed-signal circuits. The first one is a built-in current monitor (BICM) suitable for power supply current (IDD) test ing. The BICM includes a built-in current sensor (BICS) which provides high measure ment sensitivity without introducing a large impedance in the IDD path. Although the BICS structure has been proposed before, the new circuit analysis and chip measurement results provide important insights into the BICS characteristics and design trade-offs. The BICM also includes a mixed-signal built-in current integrator (BICI) which generates a digital sig nature proportional to the average IDD (IDD)- TWO different circuits have been developed for BICI: a single-phase and a double-phase BICI; the first is less accurate but requires less silicon area. These new BICI architectures offer an advantage over previously proposed circuits because they can perform integration over large time windows (T > 1 ms) while occupying a chip area equivalent to a only few hundred NAND gates. The BICM is com-ii pact, accurate (error < 2%), and insensitive to process and temperature variations. The second embedded test circuit is designed for non-intrusive functional testing of high-speed clock-recovery units (CRU) and clock-synthesis units (CSU). To the author's knowledge, this new structure is the first circuit which can perform on-chip, single-shot jit ter measurement with high resolution and precision without requiring element matching. The simulation and analysis predict a jitter measurement resolution of lOps and a precision of 1 lps in a 0.35 fim CMOS technology under typical power supply and thermal noise con ditions. Combined with a jitter generator block, it can test intrinsic jitter, and jitter transfer characteristics of CRUs and CSUs. The circuit is digital, partially synthesizable, and au tomatically placeable and routable. Novel gate delay model and analysis techniques, sup ported by simulation, are also introduced to evaluate the accuracy of the circuit. iii Contents Abstract ii Contents v List of Tables ix List of Figures x Claims of Originality xiv Acknowledgements xvi Dedication xvii1 Motivations and Overview 1 1.1 Built-in current monitoring .2 1.1.1 On-chip current sensing 3 1.1.2 On-chip current averaging 5 1.2 PLL testing 7 1.2.1 Jitter testing 8 iv 1.3 Motivations and Contributions 9 2 Background And Survey 13 2.1 IC Testing 4 2.1.1 Why test integrated circuits? 16 2.1.2 Test and diagnosis 17 2.1.3 Functional versus structural testing 18 2.1.4 Defects and faults 19 2.1.5 Test generation 21 2.1.6 Design for testability (DFT), built-in-self-test (BIST), and embed ded test 2 2.1.7 Digital circuit testing 24 2.2 Analog and Mixed-Signal Testing 6 2.2.1 History 27 2.2.2 Testing analog circuits 29 2.2.3 Analog and mixed-signal DFT 34 2.2.4 Mixed-signal BIST 35 2.3 Conclusions 37 3 Built-in Current Monitor for Testing Analog Circuit Blocks 38 3.1 Built-in Current Sensor (BICS) 40 3.1.1 BICS circuit 43.1.2 BICS accuracy 2 3.1.3 Calculating ZBic 43 v 3.2 Single-phase BICI . . 47 3.2.1 Basis 43.2.2 Notation and definitions 49 3.2.3 Circuit operation 50 3.2.4 BICI two-point calibration 55 3.2.5 Single-phase BICI accuracy 7 3.2.6 Circuit implementation 58 3.3 Simulation and Experimental Results 61 3.3.1 BICS 63.3.2 Single-phase BICI 65 3.4 Conclusions 8 4 Double-Phase Built-in Integrator 70 4.1 Introduction 74.2 Double-phase BICI Circuit 71 4.2.1 Basis4.2.2 Notation and definitions 73 4.2.3 Circuit operation 5 4.2.4 Half-wave current integrator (HCl) . 76 4.2.5 Double-phase BICI two-point calibration 81 4.2.6 BICI accuracy 82 4.2.7 Circuit implementation 84.3 Simulation and Experimental Results 5 4.4 Conclusions 86 vi 5 On-Chip Jitter Specification Testing of High-PerformancePLLs 89 5.1 Jitter Definitions 90 5.1.1 PLL jitter specifications 92 5.2 Jitter Measurement Circuit (JMC)5.2.1 State of the art in TDC design 93 5.2.2 High-resolution TDC 8 5.2.3 Notation and definitions 99 5.2.4 Time quantizer 100 5.2.5 Measurement range extension 105 5.2.6 Calibration 108 5.2.7 Automatic resolution adjustment 110 5.2.8 Controlled load (CL) cell design . 116 5.2.9 Resolution adjustment control block 119 5.2.10 TDC error sources . 132 5.2.11 Accuracy, Precision, and Resolution 136 5.3 Jitter Generator 141 5.4 Schemes for On-Chip Jitter Specification Testing 142 5.4.1 Cycle-to-cycle jitter measurement 145.4.2 Relative jitter measurement 142 5.5 Implementation 146 5.6 Simulation Results 150 5.6.1 Jitter measurement circuit 155.6.2 Accuracy estimation 151 vii 5.7 Conclusions 153 6 Summary and Conclusions 159 6.1 Future Research 163 Bibliography 165 Appendix A BICS Frequency Response Analysis 178 Appendix B A'" and I Relationship in the Single-Phase BICI 181 Appendix C N and I Relationship in the Double-Phase BICI 185 Appendix D TDC Calibration 187 D.l Two-point CalibrationD.2 n-point Calibration Technique 190 Appendix E Metastability window of a D flip-flop 194 Appendix F Range Extender Block Analysis 197 Appendix G Two-Parameter Model for Vdd-induced Gate Delay Variations 199 G.l Test 1: Single Gate Delay Simulations 19G.2 Test 2: Ring Oscillator Test 201 Appendix H TDC Power Supply Noise Analysis 205 viii List of Tables 3.1 Area overhead comparison of two current mirror matching techniques ... 43 3.2 Low frequency impedance and bandwidth of ZBic 61 3.3 Single-phase BICI test signals 66 3.4 Simulation results for the average current measurements by single-phase BICI circuit 68 4.1 Double-phase BICI test signals 86 4.2 Simulations of average current measurements by double-phase BICI .... 88 5.1 Tdij and Sv^s for different styles of CL cells. Numbers 1 through 6 in the first column refer to the states a = 000001,000011, 000111,001111, 011111, 111111 in test bench circuit shown in Fig. 5.10, respectively 120 5.2 Specifications of the implemented CL cells 147 A.1 Number of product terms in the coefficients of NBIC (s) and DBic{s) ... 180 G. 1 7 and p estimates and the resulting model errors for four different digital gates201 ix List of Figures 1.1 CUT and the current sensor 3 1.2 IDD dependence on the duration and beginning of the averaging window . . 6 2.1 Integrated circuit design and test flow 15 2.2 Integrated circuit test stages 18 2.3 Examples of faults due to local defects 20 2.4 Inductive fault analysis flow diagram 33 3.1 The proposed current monitor. 9 3.2 The block diagram of the current sensor 41 3.3 Current sensor circuit 44 3.4 AC model of a MOS transistor 45 3.5 Single-phase BICI functional block diagram 48 3.6 Single-phase BICI circuit schematic 50 3.7 Timing diagram and different waveforms in the BICI circuit of Fig. 3.6 : . 52 3.8 The transistor-level schematic of the integrator circuit 59 3.9 Schematic of the comparator 60 3.10 ZBIC versus frequency 2 x 3.11 Isense IKSIDD transfer function for IDD — 1mA at the operating point (A's = 1/6) .63 3.12 VBIC versus IDD DC characteristics 64 3.13 Measurement and simulation results for ERR versus IDD considering the parasitic resistances in the circuit 65 3.14 Current waveforms SPK1, SPK2, and SQ for validating the operation of the single-phase BICI circuit 67 4.1 Double-phase BICI functional block diagram 71 4.2 Quantization residue feed forward technique used in the ADC of double-phase BICI 74 4.3 Current integrating circuit schematic 75 4.4 Timing diagram and different waveforms in the integrator circuit of Fig. 4.3 77 4.5 Half-wave current integrating circuit schematic 79 4.6 The transistor-level schematic of the half-wave integrator circuit (HCl) ... 84 4.7 Schematic of the comparator 85 4.8 Current waveforms for validating the operation of the integrator circuit... 87 5.1 (a) Measuring cycle-to-cycle or period jitter, (b) Measuring accumulative jitter using a reference clock, (c) Measuring relative jitter 91 5.2 Block diagram of the proposed jitter measurement circuit 93 5.3 Time digitization using a delay chain 95 5.4 Time digitization using differential delay technique 97 5.5 Block diagram of the proposed TDC circuit 99 5.6 Time digitization using two oscillator period difference method 102 xi 5.7 Measurement range extension to (2k — 1)TA 106 5.8 KTref interval selection circuit 109 5.9 Automatic resolution adjustment circuit 112 5.10 CL cell evaluation test bench 116 5.11 Different CL cell styles: (al, bl, cl, dl, el) Circuits; (a2, b2, c2, d2, el) simplified models 117 5.12 Circuit for checking the necessary condition that TA > TB 123 5.13 Alternative circuit for checking the condition TA > TB 124 5.14 Circuit to generate rA\ + TA2 < Td < TB forTATB checker circuit ..... 125 5.15 Algorithms for selecting a and b in uniform load CL method, (a) exhaustive search, (b) directed search 127 5.16 Exhaustive search algorithms for selecting a and b in the 'incremental step' CL cell method 128 5.17 Semi-exhaustive search algorithm for selecting a and b in the 'incremental step' CL cell method 129 5.18 Fast search algorithm for selecting a and b in the 'incremental step' CL cell method 130 5.19 Jitter generator circuit 141 5.20 Cycle-to-cycle jitter measurement 143 5.21 Relative jitter measurement 145 5.22 Top block-level schematic of the jitter measurement circuit . 155 5.23 Implemented TQ circuit 156 5.24 TDC resolution adjustment simulation waveforms . . 157 xii 5.25 TDC measurement error for resolution of 34.1 ps 158 E.l The test bench for estimating the metastability window of a D flip-flop . . .195 E.2 Simulation results of the flip-flop output for five different values of TD ... 196 E.3 Simulated clk-to-Q delay versus rp 19G. 1 The test bench for validating the two parameter model for V^-induced gate delay variations 200 G.2 The ring oscillator test bench to validate the two-parameter model for Vdd-induced gate delay variations 202 G.3 Ring oscillator period jitter from simulation and the two-parameter model for Kw-induced gate delay variations, a)/=l. 1 GHz, b)/=350 MHz, c)/=50 MHz, d)/=5 MHz , 204 xiii Claims of Originality Chapter 3: A novel analytical method for obtaining the frequency response of a built-in current sensor (BICS). This analysis leads to closed-form equations for the frequency domain characteristics of the BICS. IC Prototype measurement results for the BICS. Such results leads to conclusions about the critical importance of the routing resistances in BICS layout design. A novel single-phase built-in current integrator (BICI). Both the current integration technique and the circuit implementation are new. This design is small enough to re side on-chip, provides a digital signature, and is robust against process variations. Chapter 4: A novel quantization residue feed forward technique. This technique prevents accu mulation of ADC quantization noise which significantly enhances the accuracy of the BICI. Using this technique leads to a new, double-phase BICI which provides high accuracy for any power supply current waveform. Chapter 5: A novel time quantizer (TQ) structure. This TQ structure achieves high resolution and high accuracy simultaneously. New resolution adjustment (RA) techniques for time interval measurement. These techniques guarantee high resolution under process variations. xiv A high-resolution time to digital converter (TDC). The TDC uses the designed TQ and resolution adjustment circuits to measure time interval with high-resolution and accuracy. The design of this circuit is compatible with a conventional digital design flow. A jitter measurement circuit (JMC). The JMC uses the designed TDC to perform high-resolution and accuracy single-shot jitter measurement with resolution and accuracy of approximately 10 ps. A jitter generator circuit. This circuit performs digital phase modulation using only digital gates. It can be used for jitter tolerance testing of phase locked loops. A novel power supply noise-induced gate delay variation model. This model has only two fitting parameters and is used to show the immunity of the TQ to power supply noise. xv Acknowledgements My special thanks goes to Dr. Andre Ivanov, my supervisor, whose invaluable support and constant help, encouragement and guidance made this contribution possible. He has been a great source of inspiration and a role model to me not only in technical and educational sense but also in many aspects of life as a person. Many thanks also to my supervisory committee, specially Dr. Mike Jackson, for reading my thesis carefully and giving me precious feedback which resulted in great amount of improvement in both style and content of this thesis. I also thank Mr. Yong Luo, Mr. Zhurang Zhao for their help in testing the fabricated chips, writing 'vhdF codes and also for their feedback and interesting discussions about dif ferent circuits. My thanks also to Mr. Farinam Farahmand and Mr. Alireza Moshtaghi for writing the CAD tools which were used from time to time in the course of this research. I'd like also to thank Micronet, PMC-Sierra for their financial support and CMC for providing design tools and access to fabrication facilities. Throughout the years of my Ph.D., so many family and friends have been great sources of motivation and inspiration to me which enabled me to complete this work. Thousands of thanks to all of them specially my loving parents and my wonderful sisters, Nasrin and Nooshin. xvi And, so many thanks to my fiancee, Mojgan, who understood, helped, and encour aged me during the intense and sometimes difficult months that I was busy writing this the sis. SASSAN TABATABAEI-ZAVAREH The University of British Columbia February 2000 xvii To my loving parents xviii Chapter 1 Motivations and Overview Testing is an integral part of the integrated circuit (IC) production which ensures the correct functionality of the final product shipped to the customer. Smaller geometry technologies, higher density [ 1], increased performance and implementation of different sub-systems (ana log, digital, memory, micro-electro-mechanical systems (MEMS), ...) on the same chip re quire new test methodologies. Without such methodologies, testing cost can become the major hurdle in the way of the future progress of IC production industries [2]. This work is an effort to provide effective test solutions for testing widely used mixed-signal circuits, more specifically phase-locked loop (PLL) circuits. Two different strategies have been developed for testing embedded mixed-signal circuits: power supply current test ing and jitter testing. The first scheme can be used to test any analog and mixed-signal cir cuit, whereas the second one is more appropriate for timing circuits such as clock recovery, clock synthesis, and clock skew compensation circuitry, which are often PLL based. This chapter outlines the state of the art and motivations of the research reported in the rest of this thesis. Sec. 1.1 and 1.2 review the literature and the incentive for designing 1 the on-chip current monitor and jitter test circuits, respectively. A background of IC test ing, and analog and mixed-signal test methodologies, including the definitions of the major concepts, is given in Chapter 2 for readers who are interested or do not have sufficient back ground in mixed-signal IC testing. 1.1 Built-in current monitoring The success of supply current monitoring in digital CMOS integrated circuits (IDDQ test ing) [3, 4, 5] has prompted researchers to investigate the feasibility of monitoring supply current (IDD) in analog circuits as a testing methodology [6, 7, 8, 9]. The results of these investigations suggest that IDD testing, although not sufficient by itself, can offer additional fault coverage for analog circuits. Often, IDD testing in analog circuits is based on measuring the average, rms, or the value of the current at specific times, and comparing these against a pre-defined tolerance range. If the measured value falls outside the associated fault-free tolerance range, the cir cuit is declared faulty [6, 7, 8]. Average IDD is a convenient and attractive test signature because it is a compact indicator of the current value over time. It also serves as a means of power monitoring when the supply voltage is constant [10]. Due to the lack of resolution of off-chip current sensors, parasitic currents of pads, and also fault masking effects (e.g., the IDD of one block masking the faulty IDD of another one), it is necessary to isolate the analog blocks in small groups, sense the supply current of each group using built-in current sensors (BICS), and average the associated IDD'S on the chip [6]. 2 1.1.1 On-chip current sensing A number of different BICS's have been proposed for current monitoring. All these sensors insert a current sensing device [11, 12, 13, 14] or rely on the circuit intrinsic impedance in the IDD path [15], as shown in Fig. 1.1. A voltage drop across the sensing device (VBIC) Figure 1.1: CUT and the current sensor. results as IDD passes through it. Therefore, the circuit under test (CUT) supply voltage, VCUT, is: VCUT = VDD — VBIC (1-1) Drawbacks of the VBIC voltage drop include performance degradation of the CUT, i.e., ad ditional delay and noise in the circuit [16]. VBIC can usually be expressed as: VBIC = VDC + Vj = VDC + f(IDD) (1.2) where VDC and Vj are the IDD-independent and IDD-dependent components of VBIC, re spectively, and / is the function relating Vj to IDD- VDC is often a DC voltage whose effect is the reduction of the CUT supply voltage. The Vi component of VBIC, to a first order, can be modeled by an impedance (ZBIC) in the supply current path (as illustrated in Fig. 1.1). The impact of VDC on the operation of the CUT can be minimized by choosing small values of VDC and designing the CUT to operate with reduced supply voltage. ZBIC, however, can cause an unacceptable degradation in the CUT performance due to the induced noise, i.e., VBIC = ZBICIDD, resulting from IDD variations. Most current sensors proposed in the literature use a resistor or a MOS transistor bi ased in the triode region as the current sensing device. The voltage drop across the sensing device is used as the current value indicator. Such sensing devices trade sensitivity for im pact on CUT performance. Designing for small values of ZBic reduces the impact of the sensor on the CUT performance by reducing VBIC variations [17], which in turn reduces the sensitivity of the sensor. In digital circuit IDDQ testing, high current sensor sensitivity is not required because the sensor only needs to distinguish two values of current which are typically at least one or more orders of magnitude apart [4]. In analog circuits, however, both a high sensitivity and a low ZBic value are required for acceptable performance. The current sensor from [6] uses an NMOS transistor operating in the triode region for sensing IDD of embedded analog blocks. This sensor cannot provide a high sensitivity and a low ZBIC simultaneously. Even if the sensitivity requirement is relaxed, the sensor needs a very large NMOS transistor (width ~ 1mm — 10mm) to obtain an acceptably small ZBIC (e.g., lOfl to lfi). In [18], a low voltage current mirror based on a NMOS device and a buffer is used as the sensor. Although this design reduces VDC, it has two problems: (i) 4 VDC is process dependent and (ii) it does not reduce ZBIC- The circuit proposed in [10] provides both a small ZBIC and a low process-insensitive VDC- However, in [10] the ZBIC characteristics have not been analyzed. Such an analysis is essential to optimize the sensor's characteristics to achieve a low ZBIC in a wide frequency range while minimizing the sensor area. 1.1.2 On-chip current averaging The current sensed by a BIC sensor has to be integrated over a time window to obtain the average IDD current, IDD as shown below: TEE(T,tb) = i Ubb+T iDD(t)dt (1.3) where T and U are the duration and the starting time of the averaging time window. Eqn. 1.3 indicates that by choosing a fixed averaging period T, averaging can be replaced with inte gration. In general, IDD depends on T and tf,; for example, Fig. 1.2 shows how IDD varies for three different selections of T and tb when IDD is a sinusoid with offset. This requires timing circuitry to synchronize the averaging operation with IDD- However, if T is cho sen such that T » 1/BWi where BWi is the bandwidth of IDD AC component, then IDD ~ IDD{DC) where IDD(DC) is the IDD DC component which is independent of T or h. Therefore, to avoid the need for synchronizing circuitry, averaging should be per formed over a long period of time, e.g., T = 100/BWi. This condition results in long averaging windows in the range of a few tens of milliseconds for circuits such as audio fre quency filters in which BWi ~ 4 kHz. 5 'DD (mA) 1.5-0.5 f (ms) 2 l^=g(i; ,t,)=i+(2/3K) ~iD~D = 9(T2,t1)=1 + (2/7K) Figure 1.2: IDD dependence on the duration and beginning of the averaging window A simple method of integrating IDD is to pass it through a capacitor; the voltage stored across the capacitor at the end of the integration window will be proportional to IDD Using this method may require a large capacitor. For example, assuming a supply voltage of 3.3V, an IDD — 100 fiA and T = 1 msec, a 30 nF capacitor would be required to ensure that Vc < VDD during integration, and therefore the electronics providing the current to the capacitor do not saturate. Such a large capacitor would obviously not be able to reside on-chip. In [19] a capacitor connected between Vss and VDD terminals of the CUT, and the power supply is switched periodically to estimate the CUT power consumption. This esti mate also provides an indirect estimate of IDD- This method, however, does not measure IDD directly and also requires a large capacitor. Therefore, an on-chip bus or multiplexer is [10], (1.4) 6 needed to direct the IDD from different analog blocks on the chip to an output pin. In addi tion to requiring an extra pin, the bus and pad parasitics reduce IDD measurement accuracy. 1.2 PLL testing An example of a widely used class of circuits requiring functional testing is phase-locked loops (PLL), since most structural test methods are either too intrusive (affect the perfor mance) or provide poor correlation to important PLL specifications such as jitter. PLL testing has gained significant interest recently due to the widespread integration of PLLs in mixed-signal communications and data processing ICs. PLLs are used in timing applications such as clock synthesis, clock recovery, and clock skew compensation. In such applications, the single most important set of specifications for a PLL is its jitter character istics, such as intrinsic jitter, jitter transfer function, and jitter tolerance[20]. In fact, jitter specifications are critical in most high-speed interfaces because of a limited available tim ing budget. Jitter testing, however, is an expensive test because it requires costly equipment and long test time [21 ]. A number of authors have tried to find cost-effective test methods for PLLs [22, 23, 8,24,25,26,27,28,29,30, 31,32]. Works in [22] suggests partial specification testing such as lock range, lock time, and power supply current for PLL testing. Dalmia et al. [8, 29] also show the viability of power supply current monitoring for PLL testing. The authors of [24, 25] propose methods for efficient fault simulation of PLLs and suggest lock frequency range measurement for PLL testing. Although a combination of these techniques seems to provide a good fault coverage, it is difficult to correlate the test results to important jitter specifications, partly because simulating jitter for fault-free and faulty circuits is extremely 7 difficult due to a lack of tools capable of simulating noise in non-linear dynamic circuits. Azias et al. [26] proposes a reconfiguration technique for testing ring oscillator-based PLLs. This technique has the advantage of being compatible with digital test methods, but it re quires reconfiguring sensitive parts of a PLL. Also, it exhibits the problem of unknown cor relation of test results and functional specifications. A practical solution to PLL testing is to directly measure the jitter characteristics of the PLLs on the chip. The following section reports major methods for on-chip jitter testing. 1.2.1 Jitter testing Jitter testing often requires jitter measurement. Jitter measurement techniques are divided into two categories: frequency domain and time domain. Historically, spectrum-based tech niques have been used more often because of the availability of high-frequency spectrum analyzers [33, 21]. The drawback of this method is that the amplitude distortion and noise degrade the measurement accuracy. Also, this method is not suitable for on-chip measure ment because performing high-resolution spectrum analysis on the chip requires a signifi cant amount of design time and silicon area. In the time domain, jitter measurement can be performed using modulation domain analysis [34], histogram-based [21] or undersampling [21] techniques. In [30], a BIST cir cuit is proposed which is capable of measuring lock range and loop gain of a PLL in ad dition to performing a jitter test. Because of its statistical nature and dependence on bit error rate (BER), the application of the jitter testing approach in [30] is limited primarily to clock recovery PLLs. Also, high-resolution measurement requires generation of precise, high-resolution and stable delays. Two US patents in [27] and [28] outline on-chip jitter 8 measurement techniques for PLL testing. The BIST circuits proposed in these patents are mixed-signal and their resolution is limited to one gate delay, which is inadequate for testing high-speed PLLs. In [31], a jitter transfer function measurement circuit is proposed for PLL testing; however the jitter measurement circuit proposed does not have sufficient resolution for intrinsic jitter testing. Veillette et al. [32] proposes an interesting method for generat ing jitter at the input of the PLL for jitter transfer testing. This method, however, requires reconfiguration of the feedback in the PLL loop, which could affect the performance of the loop. Since most of the time domain techniques require some sort of time interval measure ment, on-chip accurate jitter measurement necessitates high resolution on-chip time mea surement circuitry. For on-chip time interval measurement, a number of time-to-digital con verters (TDC) circuits, used in physics experiments, have been proposed in the literature [35, 36, 37, 38, 39]. Such circuits, however, are mixed-signal, require custom design and layout, occupy a large area, do not provide high resolution, or rely heavily on matching of the elements. The idea of a controlled delay line used in TDCs is also used as an on-chip jitter measurement method in [27]. This circuit, however, is mixed-signal and suffers from the same limitations as most TDCs. 1.3 Motivations and Contributions Although power supply current testing is proposed as an attractive structural testing method for mixed-signal circuits, it has limited applicability due to the lack of a practical BICM scheme. Two issues have to be addressed in an effective BICM: 9 1. The current has to be sensed with high resolution without introducing large impedance in thepath 2. The IDD signature has to be digital and accurate. In addition, it has to be generated without requiring large chip area These requirements led to the design of a BICM reported in Chapter 3. This BICM is capable of sensing IDD without introducing significant impedance in the power supply current path. It averages the current and generates a digital signature. Since the circuits are compact and easy to design, they are suitable for BIST and DFT applications. The circuits can provide an rms error less than 2% if the IDD contains significant AC components which are uncorrelated with the system clock. As another contribution of this thesis, a double-phase built-in current integrator is reported in Chapter 4. This integrator occupies slightly larger area than the single-phase integrator introduced in Chapter 3, but it can measure the average current with an rms ac curacy of 1% for any current waveform. The design of on-chip jitter test circuit was undertaken because the effectiveness of structural tests or non-jitter based partial specification tests can not be proven, and also exist ing external jitter testing methods are costly, if possible at all. At the start of this effort, there was no solution for high-precision on-chip jitter testing. Even today, the new high-precision on-chip jitter testing technique by Logic Vision, Inc. [30] is based on bit-error-rate whose ap plication is limited to clock-recovery PLLs. Another recent technique has been announced by Fluence Technology, Inc.1, but no information is available in the public domain about the specifics of the technique. For a practical and widely applicable jitter BIST solution, we set 'See the VCOBIST data sheets at 10 the following objectives for the jitter measurement circuit: 1. Single-shot jitter measurements (similar to those performed by an external equipment). This is to make the test solution independent of the circuit under test 2. Compatibility with digital design flow 3. Ability to generate digital signatures 4. High-resolution and precision (better than 10 ps in a 0.35^ra technology) The search for on-chip jitter test solutions resulted in the novel jitter measurement and generation circuit for BIST of PLLs which is presented in Chapter 5. The circuit sat isfies all the conditions for a practical BIST circuit mentioned in Sec. 2.2.4 as well as the objectives mentioned above. The measurement circuit is fully digital and automatically syn-thesizable, occupies an area equivalent to 1200 2-input NAND gate, provides a resolution of approximately 10 ps (~ 1/5 of a gate delay in a standard 0.35 /j,m technology) and a precision of 11 ps, and generates a digital signature which can be read out by an inexpensive tester. The digital signature can be further analyzed by the tester to obtain the jitter characteristics. In addition to the circuit structures, a number of design and analysis techniques have been employed in these designs which have wider applications. These techniques are: 1. The approximation technique used in Appendix A to obtain a closed form for the fre quency response of the BICS 2. The noise feed-forward technique presented in Chapter 4, which is an effective method for quantization noise reduction in averaging analog to digital converters 11 3. The differential method used for jitter measurement which provides power supply noise rejection. This property proved in Appendix H makes such architecture a strong candidate for a multitude of high-precision timing circuits 4. The VDD -induced modeling of gate delay variation presented in Appendix G. This model can be used for estimating the effect of power supply noise on digital circuits 12 Chapter 2 Background And Survey Today's electronic integrated circuits are extremely complex and dense. New technolo gies allow multi-million transistors [1] and mixed-signal circuitry on the same chip. This progress has led to the design of integrated circuits possessing an unprecedented functional ity with the expectation that this trend will continue. As the complexity of integrated circuits increases, IC manufacturers face many new challenges, one of which is developing effective test solutions for ICs. This chapter provides the background, terminology, and principles often used in the field of IC testing. Sec. 2.1 reviews major concepts and the terminology used in IC testing. Sec. 2.2 reports the major issues encountered and techniques developed for testing mixed-signal circuits in more detail. Sec. 2.3 concludes this chapter by summarizing the important concepts and describing some active research areas in the field of mixed-signal testing. i 13 2.1 IC Testing The typical IC design flow starts with a concept which leads to a set of functionalities and specifications. After that, an appropriate technology is selected which is believed to yield the required performance. Using the appropriate technology models, the specifications are mapped to an implementable design, which is analyzed and simulated to ensure that the de sign satisfies all the requirements. Subsequently, some prototype ICs are fabricated, char acterized and diagnosed thoroughly to determine if the device meets all its specifications under the given process variations. The design and/or fabrication process is corrected ac cording to the results before the IC is sent for production (Fig. 2.1) [40]. In the last stage of production flow, each fabricated device undergoes a series of tests before it is shipped to the customers. Some tests are performed on the wafer before cutting the dies (wafer test), and more extensive tests are run on the packaged devices (final test). Since time-to-market is a critical factor in the success of an electronic product, the test procedures are often devised parallel to design verification and prototype characterization, and automatic test equipment (ATE) programs are developed before the first batch of devices is fabricated. This section reviews the major concepts in the field of IC testing. First, in Sec.2.1.1, the fundamental question as to why ICs must be tested is addressed. Then, a definition of test and the difference between test and its close relative, diagnosis, is presented in Sec. 2.1.2. The major test disciplines, functional and structural testing, are defined and compared in Sec. 2.1.3. Often, regardless of the test discipline selected, the concepts of defect and fault are used to generate or evaluate different test methodologies. These concepts are reviewed in Sec. 2.1.4. They are also used in Sec. 2.1.5 to briefly describe the two general test gen-14 Concept and circuit specification Circuit design and analysis Fabrication parameters Simulation and Design verification ^Prototype fabrication Test development Extensive test and diagnosis \Jjyield prediction)J Figure 2.1: Integrated circuit design and test flow 15 eration methodologies, automatic and ad-hoc. Next, in Sec. 2.1.6, Design-for-testability (DFT), built-in self-test (BIST) and the embedded test concepts are defined. These tech niques are used when it is difficult to generate or apply the test to the circuit under test. Fi nally, a very brief review of major test methodologies for digital circuit testing is presented in Sec. 2.1.7 since many of the basic ideas have also found their way into the mixed-signal test domain. 2.1.1 Why test integrated circuits? If a device functions properly under the nominal variations of a fabrication line, why is there a need to test each device at the end of the line? The answer lies in the imperfections of the fabrication line. These imperfections result in some random failures at various stages of the line; e.g., mask misalignments, missing or extra metal, polysilicon or oxide due to spot de fects and cracks [40]. Some experts believe that these failures can be avoided by improving the fabrication line, and subsequently increasing the yield to about 100%. Assuming this opinion to be theoretically correct, the need for testing is still unavoidable because 1. fabrication line improvement would require resources that may not be justified by the resulting increase in yield. This becomes especially true for the devices with short product life times; 2. as fabrication line technology improves, industry demands smaller device geometries and more masking stages which drive the yield down; therefore, the need for testing. In reality, almost all IC manufacturers test (in-house or outsource to test houses) their fi nal products to bridge the gap between the fabrication imperfections and their customer's expected quality [2]. 16 In some applications such as aviation systems, military equipment, and deep space systems, where correct functionality can be life-critical, the test quality is the important fac tor and the cost is a secondary concern. However, in commercial and consumer applications, the test choice depends on the trade-off between test quality and test cost. For today's com plex chips the test cost can account for 30% of the total cost of the product [41], and may even surpass the cost of manufacturing in near future [2]. As a result, industry has focused on finding efficient ways of testing circuits and systems to increase the quality to cost ratio. In addition to quality assurance, testing is sometimes used as a critical tool to locate and diagnose failures and to take corrective measures where possible. However, there are distinctions between test and diagnosis which are described next. 2.1.2 Test and diagnosis In general, testing is the process of identifying a faulty device, while diagnosis is the proce dure of locating the source of the malfunction. As shown in Fig. 2.1, during early produc tion stages of a design, extensive diagnosis procedures are run on the samples of the device in order to locate the most frequent faults in the circuit and improve the design or the pro duction line in order to achieve an acceptable yield. When the device is approved for mass production, each device undergoes two stages of electrical testing. The first one is called wafer probe and is performed prior to packaging (Fig. 2.2). At this stage thin probes are used to apply and monitor signals at various nodes of the circuit. Devices declared faulty at this stage are discarded in order to save the high cost associated with packaging a faulty de vice. Furthermore, there are a number of non-electrical test and quality control procedures that can be used at this stage such as optical, infrared, scanning microscopy, and thermal 17 imaging analysis [42]. Figure 2.2: Integrated circuit test stages. Since packaging can introduce some faults [40, Chapter 16], and also because of the difficulty in applying high-performance tests on the wafer, a second test, called final test, is run on the device. Since there is no direct access to the internal nodes of the device during the final test, the test must determine the status of the chip using only package pins. In each electrical testing step (wafer probe and final test), different approaches to test development can be chosen. These are generally divided into two groups: functional and structural. These two approaches are described in the next section. 2.1.3 Functional versus structural testing Functional testing is defined as testing the conformance of the functionality of a circuit to its specifications. Historically, this type of testing has been the method most commonly used, but as the functionality of chips increased, such testing became costly and in many cases impossible. For example, for a combinational logic circuit with 64 inputs with a testing 18 speed of 108 patterns per second, it can take 5849 years to test the complete functionality of the chip! In other circuits such as complex analog or mixed-signal circuits, the functional testing would require a large amount of time and resources, translating into higher cost per device. Another approach is to assume that a well-designed and analyzed circuit which has been thoroughly debugged, i.e., all systematic or design errors have been eliminated prior to sending it for fabrication, will meet its specifications except when there is a fault in the circuit due to physical defects. Therefore, after identifying and modeling the possible faults in the circuit, the test procedure tries to determine their existence or absence. Should a fault be detected, the device is declared faulty and is discarded. This approach, called structural testing, is expected to achieve a more efficient outcome. But is this expectation reasonable? A supportive argument is that different functional specifications of a system are correlated, i.e., if a defect exists in the circuit, it will most likely affect several circuit specifications. This notion implies that functional testing might be overkill, and detecting faults in the sys tem would require less effort. This can be compared to data compression in which the key to compression is to transform highly correlated data to a set of uncorrelated data which carries the same information. The next section provides the definition of defect and fault which are used to generate tests and also measure the quality of a test. 2.1.4 Defects and faults A defect usually refers to physical failures in a circuit, while a fault is the dysfunctional elec trical effect of the defect on the operation of the circuit. In a defect-oriented test method-19 a) A dust particle can cause open fault c) Short fault b) Thinning of metal or polysilicon can create large resistance between two nodes. Figure 2.3: Examples of faults due to local defects ology, to devise or evaluate a test strategy for a circuit, fault models based on the possible defects are first chosen, and then a test methodology is selected to detect the modeled faults. The faulty circuit is simulated to ascertain whether the selected test can detect the fault. The percentage of faults detected by a test is one measure of the test quality. The effects of different defects are technology-dependent. Much research has fo cused on identifying and modeling defects in different technologies. For example, a missing oxide could cause a gate-substrate short in a CMOS transistor. Some of the common defects in most technologies include missing or extra oxide, metal, or polysilicon, and inaccuracy in the etching or doping processes. The electrical consequences of these defects include opens, shorts, as well as significant stray elements and large deviations in component val ues. Examples of shorts and opens due to spot defects are shown in Fig. 2.3.. Hnatek [40] reviews possible physical defects and their sources at each stage of the fabrication process in detail. 20 Faults are not always mapped directly to defects. In fact, sometimes faults are de fined at higher levels of abstraction because of advantages such as the ease of test generation (e.g., stuck-at fault model [43, Sec. 4.5]) and tight connection to performance parameters (e.g., performance-dependent faults [44]). 2.1.5 Test generation Fault models are often used to generate test strategies. To detect a fault, the fault should be activated by a set of inputs that cause a significant deviation in a circuit output parameter from its nominal value in the presence of the fault. To activate the fault, it should be both controllable, i.e., the fault-free and faulty status of the area affected by the fault are signifi cantly different, and observable, i.e., the outputs reflect the change in the expected behavior of the faulty area. There are two methods used in test pattern generation: 1. Automatic test pattern generation (ATPG) algorithms. Examples are ATPG algorithms for combinational digital circuits [43, Chapter 6] [45] 2. Ad hoc methods. This methods are applicable to specific circuits The ATPG methods cannot be used easily for generating test patterns for some cir cuits, e.g., analog circuits, because the interaction of the signals at different nodes is too complex. An ad hoc approach used in these cases is to consider an input pattern and simu late the faulty circuit to determine whether the selected pattern can activate the fault. Fault simulation requires simulating the circuit under different faulty conditions and input signals. Simulations in low levels of abstraction (circuit level) for large circuits are computationally prohibitive. This problem is alleviated by modeling the circuit at higher levels of abstrac tion. 21 Sensitivity analysis [46] has been also proposed as a test generation method. This method is regarded as a fast substitute for fault simulation because it can help to identify appropriate test stimulus in the possible space of stimulus. Functional testing is also an ad hoc method as it is circuit specific. Once the test input stimulus has been identified, the test is exercised on each chip by applying the stimulus to the circuit and observing the outputs with a tester. However, in some cases, applying a test to a circuit with an external tester does not suffice or is not possible; in such cases, other methods are used such as design for testability (DFT), built-in-self-test (BIST), and Embedded Test, which are explained next. 2.1.6 Design for testability (DFT), built-in-self-test (BIST), and embed ded test In many high-density devices it may be extremely difficult to generate the test pattern for a fault using only primary inputs and observing outputs. In such cases, additional circuitry or techniques can increase the testability of the circuit significantly. Many manufacturers, realizing the importance of testing and the cost involved, include these test circuits on their devices as a means of decreasing test expenses, and, as a result, cost per device. There are two main categories of DFT methods: general purpose, and ad hoc meth ods. DFT can mean adding some additional circuitry or modifying the CUT to increase the accessibility of internal nodes of a device, or can be as complete as a built-in-self-test (BIST) scheme. Perhaps, the best example of a standard DFT method is scan chain in sequential digital circuits [43, Sec. 9.4]. In a BIST scheme, the device under test (DUT) is switched to test mode, in which after a specified time required for completion of the test operation 22 in the chip, a flag indicates whether the DUT is faulty or not. BIST for digital technology has been well investigated and is widely used in cases such as memory testing. Some of the advantages of BIST are as follows: 1. It eliminates the need for expensive test equipment. As technology improves and cir cuits with higher speeds and increased functionality are designed, the test equipment has to be upgraded correspondingly, adding to the testing cost 2. A large number of chips can be tested simultaneously, resulting in cost reduction 3. Tests can be performed on-site repeatedly. Therefore, if the customer needs, he/she can run a field test on the chip under his/her required conditions 4. It provides automatic and fast diagnosis which reduces time-to-market considerably [47] BIST can be viewed as moving the tester into the chip. Inclusion of a full BIST in present day mixed chips (containing analog macros, memory, MEMS and digital circuit) may not be practical due to the area overhead. An alternative approach is to move part of the tester to the chip and leave the rest to external equipment. Such an approach is called Embedded Test. Usually embedded test circuits are designed to perform very high speed tests which are difficult to perform because of the gap between external and internal band width [2]. As the chip complexity and performance increases and access to internal circuits and embedded blocks is reduced, embedded test becomes more and more necessary. 23 2.1.7 Digital circuit testing Digital circuit testing is a relatively mature field, and today, ATPG tools are able to generate efficient test patterns for digital circuits. The key to the success of these tools is the existence of efficient fault models, fault simulators for digital circuits and ATPG algorithms. In a combinational digital circuit, any logic node can have one of two logical values. The status of a logic node depends on the inputs to the circuit. It can be assumed there is a fault in the circuit if a logic node does not change according to the design, or changes too late or too quickly. Consequently, stuck-at and delay faults models have been proposed for digital circuits [43, Chapter 4]. In a stuck-at fault model, it is assumed that a faulty logic node is stuck at one of the logic values ( stuck-at-1 and stuck-at-0 ) and does not change when it is supposed to. By applying proper patterns to the inputs, a stuck-at-u (v = 0,1) fault can be activated to v (controllability) and observed as a discrepancy between obtained and expected outputs (observability). To detect a delay fault, at least two patterns are needed. Sequential circuits contain memory elements. Therefore, the outputs depend not only on the circuit inputs, but also on the current state of the system, which is a function of pre vious inputs and states. Forcing the circuit to a known state and then applying a specific input is a challenging problem. Two alternate methods which are sometimes used to test sequential circuits are Scan Path and Crosscheck [48]. The idea of the scan path method is to divide the circuit into two parts in test mode; a combinational block and a serial shift reg ister containing all the flip-flops in the circuit. Test patterns for the combinational part can be generated using ATPG. Entering a sequence of l's and O's from one end of the test shift register and reading it from the other end can determine whether any of the flip-flops in the 24 chain are faulty. In the Crosscheck method some circuitry is added to each logic block of the device so that those blocks are accessible through external pins. Therefore, each logic block including flip flops can be accessed, initialized, and probed directly. Test strategies based on these models have proven sufficient for most applications, although there are defects which the voltage-based test strategies do not cover. Additional test such as IDDQ testing is needed [49, 50] for these defects. IDDQ testing Using the quiescent supply current (IDDQ) as a testing parameter for CMOS circuits has be come increasingly popular, mostly because it is simple and effective [3] [4]. Research shows that for some faults, the DUT draws significantly more (or less) current from its power sup ply than the nominal value. Therefore, many faults can be detected by monitoring IDD for specific inputs. IDDQ testing is an example of massive observability because for each in put pattern, a large number of faults can be detected by monitoring IDDQ • In fact, some researchers claim that there are some types of defects that only IDDQ testing detects be cause they do not alter the functionality of the DUT, but the chip is still faulty because it draws an excessive amount of current [49]. This may lead to reliability problems. In order to detect a defect by IDDQ testing, it should be activated by an input pat tern. Currently, ATPG tools are able to generate IDDQ testing patterns for digital circuits. Although there is a conjecture that these techniques could also be used to test analog circuits, not much research has been done in this area. 25 2.2 Analog and Mixed-Signal Testing The art of testing of analog circuits, unlike its digital counterparts is far from maturity. Most test engineers use ad hoc approaches that do not represent a unified test generation method ology applicable to all analog circuits. Functional testing is still widely used to test these circuits, but as the technology of mixed-signal and analog VLSI circuits progress, the cost of thorough functional testing becomes increasingly prohibitive. Currently, industry is fac ing serious issues with respect to testing analog and mixed-signal circuits, and it is calling for solutions to this matter, which in some cases has become a bottleneck for manufacturers. This section reviews the major developments in analog and mixed-signal testing to date. Analog circuits are different from digital circuits in their operation. The input and output signals of an analog circuit are continuous waveforms, and since internal components do not work as switches, their values and characteristics become more important in the op eration of the circuit. Digital DFT methods based on partitioning the circuit are often not applicable in the case of analog circuits due to negative impact of DFT circuitry on the per formance of the circuit. Also, for many circuits expressing the outputs in an analog circuit in terms of inputs and element values cannot be formulated in a generic form applicable in faulty conditions. The lack of effective fault models in higher levels of abstraction is one of the most important problems in analog testing. Simulating or analyzing an analog circuit at the circuit level is lengthy and computationally expensive. Proposed fault models in analog circuits are basically of two types: 1. hard or catastrophic faults, including shorts and opens. Shorts can be capacitive or resistive. These faults can change the topology of the circuit, posing a problem in 26 using topology methods for analog testing and diagnosis. 2. Soft or parametric faults including some variations in element values for which some functional parameters of the circuit are affected significantly. Catastrophic faults generally degrade the performance of the system significantly and can be detected by simple tests. For soft faults a decision has to be made regarding the amount of element value variation which is considered faulty. This is a difficult problem, especially when multiple fault models are included. 2.2.1 History Research on test and diagnosis of analog circuit testing started in the 1970's, almost one decade after digital testing had attracted attention. A number of reasons have been given for this late start [51]. Analog circuits were still largely discrete and relatively small, there fore, functional testing was possible. Consequently, there was no industrial motive to pur sue research in this area. The other reason was the lack of any major breakthrough in the academic research [51]. Since the 1970's, there have been some important results achieved largely in the area of diagnosis of linear circuits. Today's modern analog circuits are mostly non-linear, or be come non-linear under faulty conditions. Some researchers have attempted to extend the linear methods to non-linear problems with some degree of success. Some of the efforts in the area of analog fault diagnosis are as follows: Post measurement simulations or simulation after test (SAT): Assuming a cer tain circuit connectivity, this method tries to solve for the element values using the voltage and currents of accessible nodes and branches, and therefore, determine which component 27 in the circuit is faulty. Berkowitz [52] initiated the subject of solvability of a network based on knowing the currents and voltages in a circuit. Trick et al. [53], and Navid et al. [54], provide some necessary and sufficient conditions for the solvability of a network and in troduce algorithms for efficient element value computation. They investigate linear circuits using a single-frequency measurement. Navid et al. suggest their scheme could be used for non-linear circuits by linearizing them around the operating points. Since then, a number of papers on different linear and non-linear methods suggested for fault diagnosis have fol lowed using methods such as multi-frequency measurements [55], element modulation [56], neural networks [57], and artificial intelligence-based techniques [51, Chapter 7]. Piecewise linear (PWL) modeling of non-linear elements is one of the approaches suggested for non linear analog fault diagnosis[51]. Estimation methods is also a SAT category. These schemes, using some estimation algorithms such as least square criteria, try to estimate circuit element values by minimizing the error between nominal and measured values. Statistical methods have also been used to select test parameters[58]. Simulation before test: In this method, a fault dictionary (FD) is formed through determining the response of the circuit to a set of stimuli in the presence of some speci fied faults. The faults can be isolated by matching the measured values to the closest set of responses in the dictionary. Schreiber [59] proposes an algorithm based on state space analysis to design an efficient stimulus for the fault dictionary. The accuracy of this method depends on the accuracy of the fault dictionary. Depending on how the FD is formed, some processing of measured values may be necessary; for example, the transient response of the circuit may have to be estimated. 28 Some research has focused on efficient stimulus design, by which a fault can be lo cated with minimal measurement points and computation. Multi-frequency measurements [55] and element modulation techniques [56] provide examples of such efforts. 2.2.2 Testing analog circuits With the advent of analog VLSI circuits and mixed-signal technology, the field of test de velopment for analog circuits gained significant momentum. In recent years much research has been devoted to exploring and solving the analog testing problems. This section reviews some of these efforts. Test optimization Every second of test on the tester adds to the cost of the device. Testing cost for some dense and complex ICs is estimated to account for up to 30% of the total manufacturing cost. Therefore it is imperative to minimize the testing time by optimizing the test strategy. Milor et al. [41] introduce an algorithm for this optimization. Using the statistics of defects and faults, and the time associated with each test, their algorithm tries to minimize the test time by selecting and ordering the best set of tests. Using this algorithm, only the specifications of the device that provide maximum fault coverage in minimal time are tested. Fault simulation In the case of analog circuits, fault simulation is one method of test pattern generation. After forming a fault list, the circuit is simulated under faulty conditions to determine whether a specific parameter (test parameter) varies beyond its specified tolerance. The input signals 29 used in fault simulation are chosen to make the test parameter observable. Analog circuit simulation is computationally intensive, and simulating a large circuit for a large number of faults can be quite lengthy and almost impossible. A number of attempts have been made to model analog circuits at higher levels of abstraction to decrease the simulation time [60]. Nagi et al. [61], suggest a solution for linear circuits by transforming the circuit to the s and then z-domain. This approach is limited because it applies only to linear circuits, and also assumes that the faulty circuit remains linear as well. Macromodeling is another approach to analog circuit modeling in which the circuit is divided into behavioral blocks and then a circuit simulator such as SPICE or SPECTRE is used to simulate the system. This method decreases simulation time by lumping the effect of a number of circuit level elements into a behavioral block. These blocks should be selected such that the circuit level defects can be easily incorporated in them for fault simulation. Harvey et al. use a macromodeling technique in the fault simulation of a PLL circuit [22] and a current mode ADC [62]. Spinks, et al. [63] review some of the major works in this area. Sensitivity analysis One method used to determine an efficient set of test parameters is using sensitivity analysis. In this method the sensitivity of each output parameter to each circuit element is used to select an optimum test set. The test set stimulus and test parameters are chosen for maximum observability and controllability of the modeled faults. Slamani and Kaminska[46] analyze this scheme and suggest an algorithm to optimize the test set for maximum coverage. Their study includes single and multiple fault model cases, and concludes that as the number of 30 faults in multiple fault model increases, testing approaches diagnosis. Although promising, sensitivity analysis is mostly applicable to linear or near-linear circuits. DC and AC tests Different parameters of an analog circuit can be tested. A DC test is an attractive option due to its simplicity. In a DC test, DC operating points of the circuit are tested for a set of DC inputs. This test generally offers good fault coverage for catastrophic faults and is suitable at the wafer test stage. Soma [64] suggests that some open circuit faults cannot be detected by a DC test. Also, capacitive faults escape detection in a DC test. Bishop et al. [65, 66] evaluate fault coverage of DC tests for two common classes of analog circuits, operational amplifiers and operational transconductance amplifiers (OTAs), and conclude that up to 80% of catastrophic faults in these circuits can be detected. Sometimes AC tests are used to achieve higher fault coverage. In the AC case, single or multi-tone signals can be used. Multi-tone signals are especially useful in testing linear analog circuits such as filters because the sensitivities of output parameters vary with fre quency. Using a multi-tone signal can help to detect more faults in one test. Inductive fault analysis (IFA) In forming a fault list for a CUT, it is important to select realistic faults to avoid testing for defects that are rare or nonexistent. Such a realistic fault list can be created by using the in formation on the process variations and possible physical defects. This list also depends on the layout of the circuit. This approach is viewed as more practical. Fig. 2.4 shows different stages of inductive fault analysis test generation method. Currently some tools capable of 31 inserting defects on the layout and generating a fault list [67] [68] exist. Although global defects due to some process failure do occur, mostly spot defects (local defects) are con sidered because the probability of global defects is low, and in general, detecting them is easy. In a typical single-poly, double-metal CMOS process, some common spot defects include ([40]) 1. short between wires; 2. open in wires; 3. pin holes in oxide, gate oxide, pn junctions; 4. missing contacts or vias; and, 5. extra contacts or vias. The appropriate fault model for each defect depends on the condition of the defects and the processing technology. For example, a wire short can be low or high resistance depending on the amount of metal connecting the wires (Fig. 2.3). Defect statistics can also be used to optimize the test. IFA has been the focus of some recent papers. It has been suggested as a means of evaluating test strategies such as functional testing [69]. Harvey, et al. use it to generate and evaluate different tests on circuits such as an ADC [62] and a PLL [22]. Sachdev [70] applies it to a class AB amplifier, and Xing [71] uses it to improve fault coverage for an air-bag control circuit. Sachdev in [72] gives an overview of IFA. 32 Realistic fault list extracted from the layout and technology information Analog fault modeling Analog fault simulation Test generation Figure 2.4: Inductive fault analysis flow diagram. 33 2.2.3 Analog and mixed-signal DFT Some DFT schemes have been proposed to improve the testability of analog circuits by in creasing the observability of internal nodes of the circuit. Sunter [73] introduces a wideband analog test bus circuit which can be used for monitoring internal analog signals. Soma [74] exploits the serial structure of active filters and adds some switches to the circuit making it possible to test individual internal blocks. Slamani and Kaminska [75] suggest using param eter to DC converters. These on-chip converters produce a DC voltage which is a function of an internal parameter, and a comparator determines whether this voltage is within the acceptable range. This information is stored in a shift register and can be used to test and diagnose the device. Wey [76] and Wurtz [77] propose BIST structures for analog circuits which are in fact, the analog shift register (ASR). Taps (inputs of different stages) of this shift register are connected to different nodes in the circuit and by clocking it, the internal voltages of the circuit can be accessed. The authors of [76] also propose a current-based ASR which can alleviate the problem of limited voltage swing in a voltage-based ASR. One of the problems with Slamani and Wey's methods is that the DFT (although the authors call it BIST) circuit can be comparable to the CUT in terms of chip area. In such cases, using these methods cannot be justified. x Another mixed-signal DFT method for solving problems with controllability and observability of embedded blocks is using an analog test bus. These efforts have led to a new standard: IEEE1149.4 mixed-signal test bus [78]. This standard is aimed at solving the problem of analog access and also is a means of extending the digital boundary scan standard IEEE1149.1 to full board-level connectivity test as well as testing on-board dis crete passive components. Some implementation issues regarding the standard have been 34 addressed in [79, 80]. 2.2.4 Mixed-signal BIST Submicron mixed analog and digital technologies have enabled IC manufacturers to achieve high levels of integration, making system-on-chip a reality. One of the consequences, how ever, is difficulty in testing embedded analog and mixed-signal blocks because of: (i) limited access to these blocks, and (ii) the long time and expensive equipment needed for specification-based testing. To solve the first challenge, on-chip DFT techniques such as internal buses have been proposed to increase the access to embedded blocks. Structural testing has been suggested to address the second problem by replacing expensive specification tests with less costly ones. Although structural testing has been partially successful, specification testing in many cases is often seen as necessary. This is mostly due to the existence of soft faults, lack of proper fault models, and poor correlation between structural tests and specifications. To re duce the cost of functional testing, one solution is to use design for test (DFT) and built-in self test (BIST) techniques to reduce the test time and also the cost of test equipment needed. A practical DFT or BIST method has to satisfy several conditions; it must 1. occupy small area in comparison with the CUT; 2. be easy to design (preferably automatically synthesizable); 3. be sufficiently accurate for targeted tests; 4. generate a signature which can be analyzed conveniently on-chip or off-chip, such as a string of digital numbers. 35 The analog and mixed-signal BIST proposed in the literature can be divided to two groups: the general ones, which are. applicable to a large class of circuits, and the more specific ones, which are used for limited classes of circuits such as active filters, switched-capacitor op-amps, ADC/DAC and PLL. Roberts et al. proposed mixed-signal BIST (MADBIST) which is primarily based on generating single- and multi-tone sine waveforms on the chip using an over-sampling oscillator [81, 82]. They have applied their method for testing sigma-delta analog to digital converters [83] and a wireless communication system [84]. This method, although very attractive for on-chip signal generation, is limited to cases where spectrum-based testing is possible and also requires on-chip digital signal processing capability for response analysis. On-chip sine generation is also used in [85]. However, a large portion of circuits proposed in [85] are analog, and therefore prone to process variations and also occupy large chip area. Another BIST approach proposed by Arabi et al. is oscillation-based BIST (O-BIST) [86, 87, 88, 89,90]. This method is based on modifying the CUT or adding some amount of circuitry on the chip to turn the CUT to an oscillator in test mode. Since oscillation param eters such as frequency and amplitude are functions of CUT parameters, O-BIST can detect many faults. Although effective is some cases, O-BIST is basically a structural test because the specifications of the CUT are not tested directly. Therefore, it is difficult to correlate the test results with actual specifications. O-BIST has been used to test ADCs [86, 87], opera tional amplifiers [89], active filters [88] and even digital circuits [90]. More specific BIST structures have been designed for ADCs and DACs (e.g., [91]) and PLLs. The ADC and DAC test scheme in [91] includes a significant amount of analog circuitry which makes it difficult to design and occupies large area. The details of PLL BIST 36 schemes have been reviewed in Sec. 1.2. 2.3 Conclusions One of the major problems facing industry is balancing the need for testing to ensure product quality and the cost of testing. Since the final goal of testing is ensuring the functionality of the final product, functional testing is perhaps the most intuitive test method. However, the fault-based structural test generation approach for digital testing proved to guarantee correct functionality while reducing the test cost. This success prompted a large amount of research to develop structural tests for mixed-signal circuits, resulting in some partially successful techniques. However, the complex nature of mixed-signal circuits hampers the efforts to develop efficient fault models, fault simulation tools, and automatic test generation methodologies. These problems, combined with the expensive external tests, have made many experts believe that functional BIST or embedded test is the best solution for testing high-performance mixed-signal circuits, at least until the mixed-signal fault modeling and simulation issues are resolved. This chapter reviewed a number of existing mixed-signal BIST and DFT techniques available for widely used circuits such as amplifiers, filters, ADCs, DACs and PLLs. How ever, many of these techniques have limitations, such as impact on the CUT, insufficient accuracy, limited to specific applications and/or large area. Therefore, new cost-effective mixed-signal BIST and embedded test techniques are required to meet industry needs. 37 Chapter 3 Built-in Current Monitor for Testing Analog Circuit Blocks In this chapter, a built-in current monitor (BICM) capable of sensing and averaging the supply current of embedded analog circuit blocks is presented. The current monitor has two main parts: a built-in current sensor (BICS) [92] and a built-in current integrator (BICI) [93], as shown in Fig. 3.1. The current sensor circuit has a structure similar to that in [10] and [94, Chapter 12]. It can have a small ZBIC (~ 20) for a medium-sized current sens ing device (w = 72 /j.m/0.35 nm). It also provides CUT supply voltage regulation. Such regulation can be exploited to decrease the sensitivity of the CUT to power supply varia tions [95]. By analyzing the ZBic characteristic of the sensor, we can optimize the design to minimize area and performance impact. The BICI generates a digital signature proportional to IDD- The features of the BICI include: 1. The possibility of on-chip integration since (/) it uses small capacitors (~74 pF in 38 CUT BIC DD I'sense (from another BICS) —— o Built-in Current Sensor (BICS) Built-in Current Integrator (BICI) n-bit > N Built-in Current Monitor (BICM) Figure 3.1: The proposed current monitor. total), and (ii) the circuit area increases only marginally (one flip-flop and 2 gates) for a twofold increase in T (in contrast to almost doubling the size if simple capacitive integration is used). Only one integrator is needed on the whole chip by multiplexing the current from a number of CUTs to the BICI (as illustrated in Fig. 3.1) 2. Suitability for BIST applications since it generates a digital signature which can be easily evaluated on chip by simple digital circuitry The BICI circuit, presented in this chapter, performs integration during one phase of a digital control signal, hence the name single-phase BICI. Chapter 4 presents a double-phase BICI circuit which performs integration during both phases of the control signal. The current monitor has been implemented using a standard 0.35 /j,m CMOS technology. Analytical 39 models, simulation results and some silicon measurements are also presented. The organization of the paper is as follows. The detailed operation and analytical model of the current sensor circuit are presented in Sec. 3.1. In Sec. 3.2, the current inte grator circuit details are described. Sec. 3.3 reports the simulation and experimental mea surement results. Sec. 3.4 provides further discussion on the proposed circuits, and draws some conclusions. 3.1 Built-in Current Sensor (BICS) 3.1.1 BICS circuit A block diagram of the proposed current sensor circuit appears in Fig. 3.2. The main part of the circuit is a current mirror composed of transistors M12 and Ml 3. The CUT sup ply current IDD is sensed by M12 and mirrored onto Ml3 as a current Isense given by: I sense = &SIDD (3.1) where Ks = ^/j^ (w/lis the aspect ratio of the transistors). The differential amplifier (DIFFAMP) amplifies the voltage difference between VBIC and a reference Vref. This difference, used in the negative feedback loop, stabilizes VBIC, forcing VBIC to be close to Vrej-We assume that Vrej is supplied from an on-chip voltage source (e.g., a bandgap volt age source [95]). Vrej has to be small to allow a large portion of VDD to be supplied to the CUT. However, choosing a very small value for Vrej could cause Ml2 to operate in the triode region, which would result in increased ZBIC (see Sec. 3.1.3). In the circuit imple mentation shown in Fig. 3.3, Vrej = O.IVDD-40 VDD T CUT VBlc BIC Monitor IDD Average current measurement block M12 /' i sense f p—|["^M13a' ds9 From another BIC sensor M13 ^—^J[M13 Vamp Figure 3.2: The block diagram of the current sensor. DIFFAMP is a single stage differential amplifier instead of the two-stage op-amp used in [10] for the following two principal reasons: 1. The second stage of an op-amp provides additional gain and output drive. For our sensor application, sufficient gain can be achieved with only one stage (the gain is sufficient to yield a ZBIC = 2f2), and large output drive is not necessary because the amplifier is not driving a resistive load. Therefore, in addition to simplifying the design, eliminating this second stage saves area without inducing performance loss. 2. Using a two-stage op-amp in conjunction with M12 creates an amplifier with three poles in the frequency domain. Such a structure is difficult to stabilize. 41 The negative feedback also reduces ZBic since: ZBIC = T1, (3-2) whereri2 isM12's drain-source resistance and AD is the differential amplifier gain (Sec. 3.1.3 gives justification for the latter claim). ZBIC, however, increases at high frequencies giving rise to noise at VBIC which appears as supply noise at the CUT ground terminal. Sec. 3.1.3 offers a bandwidth definition for the sensor. 3.1.2 BICS accuracy The accuracy of the current mirror is indicated by ERR = 1 — KSIDD 11 sense-It is possible to achieve an error close to 1% by using layout matching techniques [96], as suming the effect of mismatch between Vdsn and Vdsl3 is negligible. This mismatch can safely be neglected if long channel transistors (/ > 5 \±m) are used, as these result in very large transistors Ml2 and Ml3. Instead, we choose short channel transistors (/ = 0.35 \im) and use an op-amp (OPAMP in Fig. 3.3) to ensure v<is\2 = Vdsl3 [10]. An advantage of this technique is that ERR will remain small even if M12 moves to its triode region of operation due to a large faulty IDD- Also, the area overhead of the OPAMP can be less than that of using longer Ml2 and M13. For example, Table 3.1 compares the area overhead of the two techniques for the design illustrated in Fig. 3.3. Another advantage of this technique is that as the width of M12 is increased to ac commodate larger values of IDD, the area of OPAMP remains the same. This results in a larger amount of area saved than when long channel transistors are used. 42 ERR reduction Technique Approximate area Long channel Ml2 and Ml3 /u>l:? 500JJ SOfi \ V /„ - 5u ' I,., - 5u > 9000 nm2 Using an op-amp for Vds matching 4700 nm2 Table 3.1: Area overhead comparison of two current mirror matching techniques 3.1.3 Calculating ZBIC Fig. 3.3 shows a transistor level diagram of the sensor circuit. ZBIC is obtained from a small signal analysis of the circuit. To calculate ZBIC in this circuit, the CUT is modeled with the current source IDD and the CCUT capacitor (effective capacitance at the CUT supply node). The capacitance is assumed to be 3 pF which is the equivalent capacitance at the GND node of an example VCO circuit investigated in [8]. The differential amplifier (Ml-Ml 1), the sensing transistor (Ml2), and the IDD current source, in effect, form a two-stage operational amplifier (op-amp) connected in a unity-gain configuration[97, Chapter 5]. The compensation capacitor, Ccomp, is used to achieve a 60° phase margin for sufficient stability. To obtain ZBIC{J), a small signal analysis is performed as follows. From Fig. 3.3: Zcz(s) = ZBic(s)\\ZlDD(s) where Zcz(s) and ZiDD(s) are the Laplace transforms of the closed-loop op-amp output impedance and the IDD current source impedance, respectively. Since ZiDD(s) = oo, it can be concluded that: ZBIC{S) = Zcz(s) We denote the Laplace transform of the open-loop gain and output impedance of the resulting op-amp by Hog(s) and Zoz(s), respectively. Algebraic manipulation yields the fol-43 lowing closed-loop output impedance of the unity gain connected op-amp [98]: VBIC ZOZ(S) Zcz(s) = IBIC 1 + Hog(z) (3.3) VDD=3.3V DD M10 8(1/ 1.4(1 Mlla 2.4(1/ 1.4u Mil 6 2.4(1/ 1.4(1 r M7 M8 JM5 J16U/1.4UJ 1 16(1/ 1.4(1 1 1 1 j|_|M2 Ml P 16(1/ 1.4(i 16(1/ 1.4[J M4 8(1/1.4(1 ref 16(1/ 1.4(1 'DD = 2mA) lM3 M6J M9 16(1/ 1.4(1 1 pF —Ccomp _1_ <~ CUT -[- 3pF M13a 12(1/0.35(1 M12 72(1/0.35(1 H M13 12(1/0.35(1 4 16(1/1.4(1 3 16(1/1.4(1 16(1/1.4(1 16(1/1.4(1 Vi ^ 8(1/ 1.4(1 8(1 /1.4(1 H 16(1/ 1.4(1 3 Figure 3.3: Current sensor circuit. To find an approximate closed-form expression for ZBic, we replaced each transistor with the small signal model shown in Fig. 3.4. From [97, Chapter 5], for the frequency of 0Hz (DC), all the capacitances in the model can be replaced by open-circuits, resulting in 44 Figure 3.4: AC model of a MOS transistor. the following equations for Zoz(0) and Hog(0): Zoz{0) = rdl2 and Hog(0) = 9mi2rdi2gmi{rdi\\rd3) (3.4) where gmi and rdi denote the transconductance and drain-source resistance of the transistor Mi (i = 1,..., 13). Substituting these values in Eqn. 3.3 yields the following for ZBIC(0): where AD = gmiifdsWda) is the differential amplifier gain, and n2 = l/gm\2 is M12's drain-source resistance. Note that gmi2 decreases as M12 moves to the triode region. There fore, M12 should operate in saturation region to ensure larger values of gml2 which, in turn, yield a smaller ZB IC (0). To determine the characteristics of ZBIC at frequencies other than zero, we derive ap proximate expressions for the dominant zeros and poles of ZBIC{S)> as they specify the fre quency response of the current sensor. To do so, the symbolic toolbox of MATLAB [99] was used in conjunction with simulated operating point values for transconductances, capacitors and resistor in the small signal model. Details of the technique used for this derivation can be found in Appendix A. ZBIC(0) ^12/(1 +^12^12^1(^811^9)) ^/gmi2gmi(rd8\\rd9) = r12/AD (3.5) 45 The result of the small signal analysis indicates that ZBIC{S) has only one dominant zero given by: Zd =-l/(Ccomp + Cgsl2){rd8\\rd9) (3-6) Since ZBIC(S) has one dominant zero, \ZBIC\ increases at frequencies exceeding Zd- This implies that the sensor will have a frequency limit beyond which \ZBIC\ will be too large to be acceptable. Practically, the sensor will have a limited acceptable bandwidth which depends on the CUT performance specifications. For example, assuming that a CUT can tolerate 25 mV of supply voltage noise (|VB/C| (ac amplitude) = ^5 mV) and that the high frequency components of IDD have maximum amplitude of 1mA, the maximum accept able value for ZBIC is VBIC/IDD = 250. We define the sensor bandwidth, BWBic as the frequency range / = 0 to fR, where JR is the frequency such that \ZBic(s = j27r/#| = RMAX where RMAX is a specified maximum acceptable value for the magnitude of the sen sor impedance. To obtain a closed-form expression for BWBIC, we approximate ZBIC{$) by a single-zero system expression (with s = jf): ZBic(jf) = Z(0)(1 + 3-l) \ZBic(jfR)\ = ZBic(0)\(l + 3-^)\ (3.7) Zd Zd If ZBic(0) <C RMAX then zd <C JR. Therefore, substituting Zd and ZBIC(0) from Eqns. 3.5 and 3.6 in Eqn. 3.7 leads to the following simple expression for /#: f — D Zd D <7ml<7ml2 Q. jR-iiMAX-^ TfX = n.MAXJ^ ~~ 7 (3.8) ABICXy) \ygsl2-r^comp) From Eqn. 3.8, the sensor bandwidth is directly proportional to gml (and also gm2 = gmi) and gmi2- Various design techniques can be used to increase BWBIC- A simple measure is to choose wider Ml and M2 transistors. 46 3.2 Single-phase BICI Here, we propose a single-phase BICI circuit which performs integration only in one phase of a control signal <f> (when </>=LOW) which controls the integration operation. For a feasible on-chip IDD integration, the integrator circuit should not require a large ca pacitor. To avoid the use of a large capacitor, the circuit proposed here exploits the following two principles: • Reducing the integration time, T, results in a proportional reduction in the size of the integrating capacitor (Eqn. 1.4). • Integration over a specific time can be expressed as the summation of a series of in tegrations over shorter periods of time, i.e., where T - MTS and I is the BICI input current. The functional block diagram in Fig. 3.5 illustrates the basis of this integrator circuit. In this circuit, the total integration window of duration T is divided into M smaller integra tion sub-windows of duration Ts, i.e., T = MTS. The 'short-time analog integrator' (STAT) integrates an input current / for the time Ts (the initial condition at the beginning of each integration sub-window must be OV). By making Ts sufficiently short, an arbitrarily small capacitor C can be used to generate the voltage u.-(r) proportional to the integral of the input current: 3.2.1 Basis M-l Idt (3.9) (3.10) 47 1 Short-time analog integrator (STAI) v,(t) Sample & Hold (S&H) V/ ADC Accumulator (ACC) Figure 3.5: Single-phase BICI functional block diagram where Kc is a constant dependent on STAI design. The STAI output at the end of the i-th integration sub-window, denoted by K, is given by: Vi = u,-(r)|t=(.-+i)TJ = Kc [ii+1)Ts I(r)dT (3.11) JiTs Vi is sampled and held by the S&H block. The ADC block converts Vi to an n-bit digital number Ni proportional to Vi, i.e., : V = N,VA + Vf (3.12) where VA is the ADC quantization step and 0 < VR < VA is the ADC's quantization voltage error in the i-th integration sub-window. The ACC block adds all the JV,-'s {i = 0,..., M—1) to generate the number N, i.e., N = YliLo1 The following formally summarizes the current integrator functionality: = HfioW - V*)/VA = (l/Vk)E^o1^c/^1)T3/^-(l/VA)E^o1V« (3.13) = (Kc/VA)f0MT<Idt-VR/VA = (Kc/VA)tfldt-VR/VA where VR = E^o1 VR. The above is an idealized analysis. Actual limitations arising in practice are discussed later. 48 3.2.2 Notation and definitions The notation and definitions used in describing the details of the single-phase BICI circuit and its operation are as follows: • T: total integration time window duration • Ts: integration sub-window duration such that T = MTS • M: the number of integration sub-windows in T • fa: i-th [i = 0,..., M — 1) integration sub-window • Ts(efjy. "effective integration interval". Portion of Ts in which integration is per formed. • TR = Ts — Ts(ef /)'• reset time. Portion of Ts in which the circuit is reset for the next integration sub-window. • ti\ beginning time of the sub-window </>,-. • t • = U + Ts(ef}) • CLK: clock signal • cf>: signal with period Ts controlling the integration timing. • A^t: digital number proportional to integration of I in fa • N: final number proportional to integration of / over time T (N = Yliio1 Ni) • Q{. ADC quantization noise associated with 49 • Q: total quantization noise over time T • R{\ reset noise associated with Ni • R: total reset noise over time T ,2.3 Circuit operation v, DD X rararararararararatsrarararara • V:s3 7 XS4 s • X-—r—rrr :analog Integrator; ;\ v 8 S&H rst Inhibit COUNTER Clr elk 4 r_rst <rr[ CLK n-bit ADC & ACC Q D ' 1' •Q D FF2 , clk< clr IJ ' <L FF1 , clk< clr t_i r1 COMP + rst ramp i rst S6 T S7 Figure 3.6: Single-phase BICI circuit schematic 50 The single-phase BICI schematic is given in Fig. 3.6. Transistors Ml and M2 form a scaling current mirror to supply the current Isense from the sensor to the integrating capacitor Cint = Ci + CV The value of Cint is chosen such that M2 does not enter its triode region of operation during the integration over time Ts. For example, assuming that M2 enters its triode region at Vc = 2.5V, Ts = 1 /-is, and the maximum average current flowing into C\ during an integration sub-window, lTa(max), is 150 fj,A, a 60 pF capacitor or larger would be required since Cint = h3(max)Ts/Vc = 60 pF. A timing diagram of the circuit operation illustrating the significant waveforms is shown in Fig. 3.7. The input current I is assumed to be a sinusoid with DC offset. 0 is a signal with period Ts which controls the integration timing. Since T — MTS, a complete integration requires M consecutive periods of <f>. In each sub-window 4>i, two parallel op erations are performed: 1. /is integrated over time Ts(ej j) resulting in the voltage waveform Vc- In the subse quent time TR, a part of the integration result is stored as the Voltage V on C3 (Vs waveform). TR is the reset time during which C\ is discharged and the control cir cuitry is reset (initialized) 2. Concurrently to the above, the ADC & ACC blocks digitize V^x stored on C3 at the end of the previous integration sub-window and accumulate the result These operations are repeated over M integration sub-windows to obtain the integral of I over the time MTS. 51 CLK Figure 3.7: Timing diagram and different waveforms in the BICI circuit of Fig. 3.6 52 Short-Time analog integrator (STAI) and S&H The operation of STAI and S&H blocks are tightly coupled, and thus both are described in this section. From Figs. 3.6 and 3.7, in the interval fa, switches Sl and S3 are closed for time Ts(e;j), while switches S2 and S4 are open. During such a time interval, I flows through G\ and C2. The voltage at node C at the end of the i-th integration interval, VQ, is given by: Vc = Vc{t\) = -^-^ [*' Idt + K2lV^ (3.14) where K-i is the initial condition on C2 at the beginning of fa, K21 = C2/{Ci + C2), U = iTs and t% = iTs + Ts{eff) = (i + 1)TS - TR. Note that we assume C\ is fully discharged at the end of each interval fa. For the subsequent time TR in fa, switches Sl and S3 are opened, and switches S2 and S4 are closed. This effectively results in two functions: (i) G\ is discharged through S2 to initialize C\ for the next integration sub-window; (ii) the charge stored on C2 at t = t\ is distributed between C2 and C3. Therefore, the voltage on node S at time t -+ = t[+c (e —> 0) denoted by V, is: Vi = TT^—rVi = (3.15) G3 "T ^2 where K23 — C2/(C3 + C2). The waveforms Vs and VA in Fig. 3.7 illustrate this operation for K23 = 0.5. In the subsequent interval fa+u the switch S4 is opened causing Vi to be held on C3. Therefore, switches S3 and S4 in conjunction with C2 and C3 perform a sample and hold operation. The advantage of this circuit over more conventional sample and hold circuits is that it does not require analog buffers in front of the sampling switches S3 and S4. This 53 simplifies the design significantly because there is no need to design wideband buffers with very small input DC offset voltages [97]. Not using an isolating buffer between C\ and C2 means that the charges on C2 in fa affect the integration in fa+1 (see Eqn. 3.14). However, as shown in Appendix B, this affects only the proportionality factor K of BICI characteristics (Eqn. 3.16) which is obtained through calibration. ADC & accumulator (ACC) During fa (time ti to t •), the ADC and ACC blocks digitize the voltage stored on C3 (node S) and add the converted voltage to the digital number accumulated using a counter. The single slope technique is used to perform the analog-to-digital conversion because it can be implemented with small area and provides good linearity. When (f> goes from HIGH to LOW, the flip-flop FF2 is set (r_rst signal turns LOW) causing the counter to start counting (incrementing by one at each CLK rising edge). The CLK period must be much less than Ts(ejf), e.g., Ts(e/f) = ^OTCLK- Concurrently, switches S5 and S7 are opened, and S6 is closed. This causes the constant current Iramp to flow into C4, generating a ramp voltage waveform with constant slope at node R. The comparator COMP output, rl, switches state when VR>VS = Vi-i- At this moment, FF1 is set. This, in turn, resets FF2, which stops the counter. At the end of such a cycle of operations, a number /Y,-_i proportional to K_i is added to the value already accumulated in the counter. After stopping the counter, S6 is opened and switches S5 and S7 are closed to dis charge C3 and C4. Also, FF1 is reset to initialize FF1 and FF2 for conversion in the next integration sub-window. As shown in Appendix B, the relationship between the final counter state, N, and 54 the average current over time T, is obtained from the following: N =Kfifldt + 0 + E (3.16) = KTI+ 0 + E where K is a constant, O is an offset value, and E is a random number resulting from ADC quantization noise Q, and a reset error R, i.e., : E = Q + R (3.17) Q and R are the result of the accumulation of quantization noises Qi's, and reset errors i?t's in each integration sub-window, respectively: Q= E^o1^ (3-18) R= Efio1^ (3-19The reset error factor is due to the reset time TR in each integration sub-window during which I is not integrated. As shown in Appendix B, E has a Gaussian distribution with a zero mean and a variance given by: where KM = {Cl+c^i-Ki3K2i) and K' = ^P/^' Sec. 3.2.4 describes how K and 0 can be obtained through calibration, while Sec. 3.2.5 discusses guidelines for minimizing E. 3.2.4 BICI two-point calibration To calibrate the integrator circuit, two known current signals, 7cl and Ic2, are applied to the integrator circuit. In each case, for given CLK, T, Ts, TR and Iramp, the corresponding av-• 55 erages NcX and Nc2 are recorded by the counter: NcX = KTl7x + 0 + Ecl (3.20) Nc2= KT772 + 0 + Ec2 (3.21) The calibrating current signals, IcX and Ic2, must be AC signals with a large average (e.g., more than 30% of the maximum average current the circuit is designed for (IMAX))- The large average current yields relatively large values for iVys. This reduces the ratio Qi/Nt because the statistics of Qi are independent of Ni (they are only a function of the ADC quan tization step (refer to Appendix B)). The AC component reduces Ecl and Ec2 by randomiz ing the Qi's and the reset errors i?t's in each integration sub-window. The frequency of the AC components, denoted by /CAL, should satisfy the relationship l/T < JCAL < l/Ts and be uncorrelated with <f>. Assuming negligible EcX and Ec2, Eqns. 3.20 and 3.21 simplify to: NcX = KTL7+0 (3.22) Nc2= KTIT2 + O (3.23) Computing K and 0 in the above completes the calibration process. Eqns. 3.16, 3.22 and 3.23 yield the following relationship between N and /: N = (Nc2 - Nel)(=Lr) + N*-N«^ + e (3.24) *c2 — Icl J- — Icl I lc2 The DC values of /ci and Ic2 signals must be precisely known but the frequency, am plitude and waveform of their AC components are not critical because the AC components only serve as an error randomizer to reduce the factor E. Any AC signal available on the chip could be used for this purpose as long as it satisfies the conditions mentioned above. The precise DC current IcX has to be generated on-chip or be supplied from off-chip. Ic2 can be generated using a properly matched current mirror Ic2 = nIcX. 56 In a BIST application, the current measurement result should be evaluated on-chip by comparing JV with limit values Ni and Nh corresponding to the predetermined minimum and maximum average current thresholds I\ and 1^, respectively. Assuming Ic2 = 2/cl, It = Hc2 and Ih = rnlc2 where I and m are integers, from Eqn. 3.24, the calculation of Ni and Nh, only requires simple integer multiplication and addition as shown below: Nl = (2l-l)Nd2-(2l-2)Ncl (3.25) Nh = (2m - l)Nc2 - (2m - 2)Ncl (3.26) The above operation can be implemented using a shift register and an adder. Digital multi pliers and adders, usually readily available on mixed-signal ICs, can also be used to calcu late Ni and Nh. This is important, as each chip has to be calibrated and therefore standard ./V; and Nh values cannot be downloaded from an external source (e.g., tester). 3.2.5 Single-phase BICI accuracy To achieve a high measurement accuracy, sources of error have to be identified and their im pact minimized by design. The factors affecting the measurement accuracy of the integrator circuit are as follows: 1. Ml and M2 should be long transistors to reduce the effect of V^s variations on I 2. The M1/M2 mismatch, C\, C2, C3, C4, and Iramp variations, and the propagation de lays in the comparator, flip-flops and the gates (denoted by in Fig. 3.7), affect the factors K and O in Eqn. 3.16; this is shown by the analysis in Appendix B. Using a two-point calibration scheme, K and O can be determined. Therefore, any process 57 and temperature variations affecting K and O will affect measurement accuracy, i.e., these can be accounted for via the calibration process explained in Sec. 3.2.4 3. The clock feedthrough associated with the S3 and S4 switches can alter the charges on Ci, C2 and C3, thereby affecting measurement accuracy. Avoiding very small val ues for these capacitors and using complementary switches will minimize the clock feedthrough problem [97] 4. Power supply (VDD) variation will not deteriorate the performance of the integrator circuit because it affects the value of Iramv, the delay and the offset of the comparator, and the delays of the gates and flip-flops in the circuit, all of which are compensated for during calibration 5. The error term E in Eqn. 3.16 will generally be the major source of reduced degrada tion. E has two components: the quantization noise Q; and R that results because / is not integrated during a reset time TR. The R can be minimized by making As for Q, increasing Ts or increasing the CLK frequency will reduce this factor As discussed above, the integrator circuit accuracy is independent of process varia tion when using a two-point calibration scheme. This property makes the circuit especially suitable for integration on high volume mixed-signal chips. 3.2.6 Circuit implementation Assuming that the integrator circuit is to be used in an application where the maximum of I is 150 n A and the available CLK frequency is 20 MHz, the following parameters were chosen to design the integrator circuit: 58 • T = 1 ms, Ts = 1 ps, M = 1000 • T*(eff) = 0.95/us, TR = 50 ns • Tamp — 11.2 • Counter size: 18-bits 1 - analog integrator X X : I v CM JHtt tta flD rst Inhibit r_rst 1 ' 1' •Q D Q D COUNTER clr elk < CLK FF2 , clk^ (fo FF1 clks clr o 1 clr u n-bit ADC & Accumulator r1 COMP + 26/0.6 r_rst rst Figure 3.8: The transistor-level schematic of the integrator circuit 59 These parameters imply that Ci = 60 pF. The transistor level schematics of the main circuit and the comparator are shown in Figs. 3.8 and 3.9. The component values and transistor sizes are shown for critical components. These values have been chosen to achieve reasonable integration accuracy (error < 2%) as explained in Sec. 3.2.5 and to re duce the circuit area. Since the delay and offset of the comparator are not critical, a simple two-stage comparator was chosen. It is possible to use faster comparator structures such as the one in [100, Chapter 26], but a larger circuit area would be required. 4>a and 4>b are non-overlapping control signals constructed from cf>. They are used instead of <f> and 4> in Fig. 3.6 to avoid sample and hold errors [97]. The total area of the circuit is 45500 (pm)2. This is equivalent to the area of a digital circuit consisting of 250 NAND gates in a 0.35 pm digital cell library. Figure 3.9: Schematic of the comparator 60 3.3 Simulation and Experimental Results 3.3.1 BICS The current sensor circuit has been simulated with SpectreS [101] and SpectreSVerilog from Cadence Design System. The BIC sensor's main performance measure is its output impedance response versus frequency, /.e., ZBIC(S = j2nf). Fig. 3.10 reports ZBic vs. frequency from our approx imate first-order analytical model, simulations, and IC measurements for the circuit illus trated in Fig. 3.3. The dc impedance,Z5/c(0), and bandwidth for Rmax = 250 results are tabulated in Table 3.2. ZBIC(0) BWS (MHz) (0) (Rmax = 250) lst-order analytical model 2.7 . 5.7 Simulation (CCUT = 3 pF) 2.7 5.4 Simulation (CCUT = 30 pF) 2.7 5.3 Measurement 3 5.3 Table 3.2: Low frequency impedance and bandwidth of ZBic The parameter values needed for first-order model calculation are obtained from the operating point simulation. These parameters were found to be: rdss = 700 fcO, r^9 = 720 kto, gml = 166 ufl'1, gmU = 6.1 mfl"1, Cgsl2 = 88/F. The high frequency poles, from measurement, are located at frequencies lower than expected from simulation. This is primarily because of the pad and oscilloscope probe ca pacitance. Repeating simulations for CCUT = 30 pF (shown in Fig. 3.10) confirms this hypothesis. 61 300 /(Hz) Figure 3.10: ZBIC versus frequency Plots of the simulated transfer function for Isense/KSIDD appear in Fig. 3.11. This figure shows that even fairly high frequency components (/ ~ 20 MHz) of the current are sensed adequately (i.e., without significant attenuation). However, since the high frequency components do not contribute to the average current (see Sec. 1.1.1), the limited bandwidth does not affect the accuracy of the BIC monitor. Fig. 3.12 shows the simulated and measured DC characteristic of VBic versus IDD-As expected, for current values larger than a threshold value, VBIC increases rapidly with the current, because the differential amplifier DIFFAMP output saturates. Consequently, vgsi2 does not increase further as IDD is elevated. In other words, for large currents the negative feedback does not exist, which results in increased ZBIC- Therefore, an upper limit for the dynamic range of this sensor with regards to ZBIC is Ith = 10 mA from simulation and 62 CQ T3 5 0 -5 -10 Q _P -15 * -20 § -25 CD tn -30 -35 -40 10 Simulation Ccut=3p Simulation Ccut=30p 10* f (Hz) 10 Figure3.11: Isense/KSIDD transfer function for IDD = 1 mA at the operating point (A's = 1/6) Ith = 7.8 mA from chip measurement. The difference between the simulation and mea surement result can be justified by the fact that the model file parameters used in simulation are extracted from a different fabrication run than the one in which the tested chip was man ufactured. To achieve a larger dynamic range, a wider Ml2 should be chosen. Fig. 3.13 shows the simulated and measured current mirror gain error, ERR = 1 — (KSIDD/hut), for different IDD levels. The dashed-dotted line shows the ideal value of ERR when Iout is the drain current of M13 (in Fig. 3.3). As expected, this ERR value is very small (< 0.1%) even when M12 operates in the triode region (IDD > 10 mA). The dotted plot shows ERR when Iout = Isense- In this case, ERR has relatively large value (~ 2%) because of the leakage currents of transistor M13a in Fig. 3.3. However, as IDD in creases, this leakage current becomes less significant and ERR decreases to less than 1.2% 63 1 0.9 0.8 0.7 > o 0.6 m > 0.5 0.4 0.3 0.2 0 5 10 15 20 Figure 3.12: VBIC versus IDD DC characteristics for IDD > 2mA. The chip measurement results, shown with circles, are significantly different from the simulation results. Upon investigation of the layout, it was discovered that this differ ence is due to the resistance of the metal lines and vias connecting the input VBic node to the drain of M12. This resistance, denoted by Rp, is approximately 3fl. Repeating the sim ulations considering Rp = 3fi yields the solid-line plot in Fig. 3.13, which matches the measurement results well. In the designed layout, we modified the layout to decrease this resistance to 0.5H. The dashed plot in Fig. 3.13 shows that this layout modification reduces the systematic mismatch to a maximum of 1.6%. 64 10 0 2 4 6 8 10 12 14 16 18 Figure 3.13: Measurement and simulation results for ERR versus IDD considering the par asitic resistances in the circuit. 3.3.2 Single-phase BICI Cadence SpectreS [101] and SpectreSVerilog simulators were used to simulate the BICI cir cuit described in Sec. 4.2.7. BSIM3 MOS models were used for analog and mixed-signal simulations. Table 3.4 reports simulation results for the average current measured by the BICI for a set of 13 different current signals with different waveforms, frequency, amplitude, and 65 Name Waveform Parameters DC1 DC IDC = 150/1A DC2 DC IDC = 140^ A DC3 DC IDC = 1001* A DC4 DC IDC = 50/i A SIN1 sinusoid f=3 MHz, DC offset=60 /J,A, Amplitude=40 /iA SIN2 sinusoid f=100 kHz, DC offsets 100 pA, Amplitude=50 /J,A SIN3 sinusoid f=5 kHz, DC offset=80 \xA, Amplitude=70 \xA TRG1 triangular f=3.57 MHz, DC offset=50 fiA, Amplitude=20 [iA TRG2 triangular f=20 kHz, DC offset=70 fiA, Amplitude=30 //A TRG3 triangular f=2.5 kHz, DC offset=120 pA, Amplitude=30 /iA SPK1 Shown in Fig. 4.8(a) SPK1 Shown in Fig. 4.8(b) SQ Shown in Fig. 4.8(c) Table 3.3: Single-phase BICI test signals offset values. The large set was to test the performance of the circuit for a wide range of input signals described in Table 3.3. Signals SIN2 and TRG2 were used as calibration signals because they satisfy the conditions mentioned in Sec. 3.2.4. The second column in Table 3.4 reports the true aver age current for each signal and the fourth column indicates the average current estimated by the BICI circuit. The relative error of the estimated average current is reported in the last column. A relatively large error occurs when the average current is small and the current is constant for a large portion of its period (signals SPK1 and SPK2). This is due to the quan tization noise Q because: (i) Q,-'s becomes significant as the value of the current decreases; (ii) since current integration in each integration sub-window yields a constant voltage, Qi is constant for i = 0,..., M — 1, causing the error to accumulate over time. The same reason ing explains the relatively large errors for signals DC4 and SQ. Such inaccuracy, however, 66 may not be a limiting factor in using this circuit for test purposes because the faulty current may be well below the lower threshold of the current tolerance band. For example, assume the fault-free current is 100 a-A, and the current lower threshold is 50 \iA. If the average current measured for a faulty circuit is 20 pA, even with 25% error for this value (the actual average current could be 25 pA < 50 pA), the decision to discard this circuit is correct. The signals SPK1 and SPK2 (Figs. 3.14a and 3.146) are in fact similar to small-valued DC currents but with periodic short time current spikes in each period. Such signals model supply current of circuits such as VCOs and digital circuit blocks. The error is also significant for signal SIN1. The reason is that signal SIN1 is corre lated with the 4> signal, causing both Q and R to accumulate over time. In summary, simulations indicate that the BICI circuit provides < 2% error provided the current ac component is not correlated with <f>. Figure 3.14: Current waveforms SPK1, SPK2, and SQ for validating the operation of the single-phase BICI circuit 67 Waveform True I N I estimated 100(A//7) (M) (jiA) DC1 150 16985 150.1 0.1 DC2 140 15986 140.4 0.3 DC3 100 11990 101.6 1.6 DC4 50 6994 53.1 6.1 SIN1 60 7993 62.8 4.6 SIN2 100 11826 100 0 (Cal. point) SIN3 80 9688 79.2 -1 TRG1 50 6710 47.2 0.6 TRG2 70 8737 70 0 (Cal. point) TRG3 123 14207 123.1 0.1 SPK1 18.3 2999 14.3 -22 SPK2 33 4388 27.7 -16 SQ 72.4 9266 74.6 3 Table 3.4: Simulation results for the average current measurements by single-phase BICI circuit 3.4 Conclusions We presented a built-in current (BIC) monitor suitable for power supply current (IDD) test ing of analog circuit blocks. The BIC monitor senses the IDD and generates a digital signa ture by averaging the current over a programmable time window. The BIC monitor provides a low impedance, ZBIC, (2.70) in the power supply path of the CUT. ZBICU) has a bandwidth of about 5.3 MHz. The BIC sensor could be used in circuits where the CUT supply current has large DC and smaller ac components. This is the case in many analog circuits because (i) the biasing circuitry contributes a large DC current, and (ii) most embedded analog circuits do not drive large ac loads. The BIC sensor could also be used in high speed submicron digital circuits by adding a bypass capacitor on the CUT connection to the sensor. Such a capacitor would reduce the 68 maximum impedance of the sensor (as shown in Fig. 3.10), which would result in less power supply noise. For BIST, a necessary functional block, besides the sensing block, is a measurement block. In this chapter, a measurement block was proposed that measures average current, i.e., integrates current over a time window. The BICI requires small area (equivalent to a circuit consisting of 250 NAND gates). By using any linear feedback shift register (LFSR) or a register already available on chip (e.g., as part of digital BIST) to implement the counter needed for this circuit, a saving of 28% in area is possible. BICI also yields a digital signa ture which is convenient to interface to standard digital external or internal ATE and stan dards like IEEE 1149.1. Our circuit provides a good accuracy (error < 2%) if the current levels are not too small relative to the maximum current for which the circuit has been de signed (e.g., I/IMAX > 0.3). The digital signature makes the monitor suitable for BIST application. 69 Chapter 4 Double-Phase Built-in Integrator 4.1 Introduction As discussed in Sec. 1.1, averaging is an effective method for generating current signatures. In Sec. 3.2 a single-phase BICI circuit was presented that performs on-chip current integra tion. Although sufficient for some applications, the single-phase BICI might be inadequate for applications where higher measurement accuracy is required. This chapter presents a double-phase BICI circuit which performs integration dur ing both phases of the control signal (hence, the name 'double-phase'). This novel BICI architecture uses the same principles as those in Sec. 3.2.1. However, the circuit proposed here provides significantly more accurate measurements at the expense of a slightly larger area (approximately 20% more). The higher accuracy is achieved by: (i) using two integra tors which operate at two complementary time intervals in each cycle of a control signal, hence eliminating reset error; and, (ii) feeding forward the quantization residues from each integration interval to the next, thereby preventing the accumulation of quantization noise. 70 The double-phase BICI generates a digital signature proportional to IDD- Like the single-phase BICI, this circuit is also compact and can provide a worst-case error less than 1% for any IDD waveform. The organization of this chapter is as follows. In Sec. 4.2, the details of BICI circuit are described. Sec. 4.3 reports the simulation results. Sec. 4.4 provides further discussion regarding the proposed circuits, and concludes. 4.2 Double-phase BICI Circuit 4.2.1 Basis The functional block diagram in Fig. 4.1 illustrates the basis of double-phase BICI. In this Figure 4.1: Double-phase BICI functional block diagram circuit [93], the total integration window of duration T is divided into M smaller integra tion sub-windows of duration Ts sec, i.e., T = MTS. the input current is split into two 71 components: I = IA + IB where IA = ctl and IB = (1 — a)I. a is a periodic function with period of Ts, whose one period is defined as: (0 Ts/2<t< Ts IA and IB are integrated by the two half-wave current integrators HCI(A) and HCI(B) over the time T to generate two digital numbers, NA and NB, respectively, such that: where QA and are HCI(A) and HCI(B) quantization errors. The digital adder sums NA and NB to obtain N which is proportional to the integration of I over T: A HCl block generally functions according to the principles described in Sec. 3.2.1, but it uses a different ADC method than the one described in Sec. 3.2.1. The ADC presented in Sec. 3.2.3 generates a number A, such that V = iV; VA + Vf where VA is the quantiza tion step of the ADC, and Vf < VA is the ADC's quantization voltage error in the i-th integration sub-window. Therefore, from Eqn. 3.13, VR = Yliio1 Vf' which may result in significant quantization error. We propose a different ADC design to reduce VR. The new ADC uses a quantization residue feed forward technique, which enhances the accuracy of the BICI by preventing the accumulation of quantization errors Vf. In this technique, Vf,, 1 0 < t < Ts/2 a = < 72 the residual voltage from digitization in the (i — l)-th sub-window is fed forward for digiti zation in the i-th sub-window. This is illustrated in Fig. 4.2 for an example ADC with seven quantization thresholds. Using this technique, ADC converts Vf — (Vi + V^J to an n-bit digital number Ni, such that: = NiVA + V? (4.1) From Eqns. 3.11, 4.1, and the above discussion, the Bid's functionality is summarized as follows: Kef? Idt = J2 Kc I Idt •r, JH i = 0 -iT* N0VA + (V0R + Kc JT Idt) + £ Kc I Idt i=2 JxTs 3T3 = N0VA + ^14 + (Vf + Kc f 3 Idt) (4.2) J2T, I2T3 M-l f(i+l)T, • o Jil i=3 "iT° M-l = VA £ Ni + V*_x From Eqn. 4.2, it is evident that VR = V^_x. The above is an idealized analysis. Actual limitations arising in practice are discussed later. 4.2.2 Notation and definitions The notations and definitions used in describing the integrator circuit and its operation are as follows: • CLK: Clock signal 73 Figure 4.2: Quantization residue feed forward technique used in the ADC of double-phase BICI • fa Signal with period Ts controlling the integration timing. • $: Signal with period Ts controlling the integration timing in a half-wave current in tegrator. • T: Total integration time window duration . • Ts: Integration sub-window duration such that T = MTS • M: The number of integration sub-windows in T • fa: i-th (i = 0,..., M — 1) integration sub-window • Ts(ejjy. "effective integration interval"; the portion of Ts in which integration is per formed. • TR = TS- Ts(e}fy. "reset time"; portion of Ts in which the circuit is reset for the next integration sub-window. • U: Beginning of the period fa. 74 • t{ = U + Ts(e}f) • Ni'. The integer number proportional to integration of I in • N: Final number proportional to integration of / over time T (N = YJiLo1 Ni) • Q: Total quantization noise over time T Any parameter with a (A) or (B) in its subscript refers to the corresponding parameter in HCI(A) or HCI(B), respectively. 4.2.3 Circuit operation CLK DIVIDER elk COUNTER elk Inhibit cnt_ctrl HCI (A) f elk lin cnt_ctrl HCI telk \m Figure 4.3: Current integrating circuit schematic The BICI schematic and its important waveforms are given in Figs. 4.3 and 4.4, re spectively. The DIVIDER divides the frequency of the clock by an even number, L, and generates the signal <f> with 50% duty cycle. The COUNTER increments at each rising edge 75 of the clock if its inhibit input is LOW and keeps its value otherwise. For implementation reasons, we use two half-wave current integrators (HCl) in parallel. HCI(A) and HCI(B) integrate 1$ and l-r, respectively, where Ix (X = <j> or fa) is defined as below: Ix=l I X = HIGH 0 X = LOW HCI(A) integrates I only when fa = LOW (fa(L) interval). During fa(L), HCI(A) turns its cnLctrl output LOW for a time proportional to the current integration in fai-\)(L)-This causes a number N1(A) to be added to the counter value. Similarly, during fa(H) a num ber Ni(B) proportional to the current integration during fai~i)(H) is added to the counter value. Since HCI(A) and HCI(B) perform integration during complementary times, the counter state at the end of the operation will be proportional to the integral of I over T. 4.2.4 Half-wave current integrator (HCl) The HCl operates based on principles described in Sec. 4.2.1. The HCl circuit schematic is illustrated in Fig. 4.5, while a timing diagram of its significant waveforms is shown in Fig. 4.4. The input current / is assumed to be a sinusoid with DC offset. $ is a signal with period Ts which controls the integration timing. Since T = MTS, a complete half-wave in tegration requires M consecutive periods of $. In the interval two parallel operations are performed: 1. / is integrated for effective integration time interval Ts(ej j) resulting in the voltage waveform Vc 2. Concurrently to the above, the ADC & ACC blocks digitize and accumulate the volt age (Vi_i + Vf j) stored on C3 at the end of the previous integration sub-window <&t_i 76 CLK ^i(L) : Ts(eff) Figure 4.4: Timing diagram and different waveforms in the integrator circuit of Fig. 4.3 77 During the two parallel operations are also performed: 1. During the reset time TR = duration of^^n), Ci is discharged and the control circuitry is reset (initialized) for the next integration sub-window 2. A voltage, Vi, indicating the integration result is added to the VRX voltage stored on C3 (Vs waveform). Therefore, at the end of 4>i(H), Vc3 = V: + VRl These operations are repeated over M integration sub-windows to obtain the half-wave in tegral of I over the time MTS. Further details are given next. Short-time analog integrator (STAI) and S&H Since the operation of STAI and S&H blocks are tightly coupled, both are described in this section. From Figs. 4.5 and 4.4, in the interval $;(£,)» for time Ts(e/f) switches SI, S3 and S5 are closed, and switches S2, S4 and S6 are open. During such a time interval, / flows through Ci and Ci. The voltage at node C, i.e., Vc, at the end of i.e., Vc, is given where Va is a constant voltage remained on C2 from fa-i period, K2\ = Cij(C\ + Ci), U = iTs and t\ = iTs + Ts(e//) = (i + 1)TS - TR. Note that we assume d is fully discharged at the end of each interval T,-. For the time TR, i.e., during switches S1, S3 and S5 are opened, and switches S2, S4 and S6 are closed. This effectively results in two functions: (i) CX is discharged through S2 to initialize C\ for the next integration sub-window; (ii) the charge stored on by: (4.3) 78 Figure 4.5: Half-wave current integrating circuit schematic 79 C2 at the end of $t(L) is transfered to C3. The charge transfer is accomplished as follows. A current starts flowing from VDD through C2 and C3 to Vreji- As soon as the voltage on C2 crosses OV, the comparator CMP1 switches state causing the switch S6 to open and hold the voltage on C3. This results in the charge Qci = C2Vf to be added to C3 and held: (4.4) = y^i + v where K23 = C2/C3. The waveforms Vs and VA in Fig. 4.4 illustrate this operation for K23 = 1/3. ADC & accumulator During (timet,- to t\), the ADC and ACC blocks digitize the voltage (K_i+V^?2) stored on C3 (node S) and add the converted voltage to the number accumulated in a counter. The single slope technique is used to perform the analog-to-digital conversion because it can be implemented with small area and provides good linearity. The principle of the ADC ACC blocks operation is further explained next. - When $ turns LOW, the flip-flop FF2 is set (r_rst signal turns LOW) causing the counter to start counting (incrementing by one at each CLK rising edge). The CLK period must be smaller than Ts(ej/), e.g., Ts(e}-}) = 10TCLK- Concurrently, the switch S7 closes. This causes the constant current Iramp to flow through C3 generating a ramp voltage wave form with constant slope at node R. The comparator CMP2 output, rl, switches state when VR > Vrej2. At this moment, FF1 is set. This, in turn, resets FF2, which causes the counter to stop at the next clock edge. At the end of such a cycle of operations, a number 7Vj_i pro portional to (K-i + V{R2) is added to the previous value already accumulated in the counter. 80 After stopping the counter, S7 is opened which causes the voltage Vf j to remain on C3. Also, FF1 is reset to initialize FF1 and FF2 for conversion in the next integration sub-window. As shown in Appendix C, the relationship between the final state of the counter, N, and the average current over time T for HCI(Y) (Y=A or B) is obtained as follows: Nry) = K(Y) Jo I*dt + 0{Y) + E(Y) (4.5) where K is a constant factor, O is the offset value, and E is a random number resulting from ADC quantization noise Q. E(Y) can be shown to have a uniform distribution in the range [0,1) with a mean of 0.5 and a variance aE = ^ (see Appendix C). Sec. 4.2.5 describes how K and O can be obtained through calibration. 4.2.5 Double-phase BICI two-point calibration From Fig. 4.3 and Eqn. 4.5, N is obtained below: N= N(A) + N{B) N= K{A)Iohdt + 0{A) + E(A) (4.6) + K(B) Jo ^dt + 0(B) + E(B) Assuming K(A) = K(B) = K, 0(A) = 0(B) = O, and E = E(A) + E(B), the following relationship results: N = KTl +0 + E (4.7) where 0 < E < 2 (from Appendix C). For large values of M, N is a large number, therefore E is negligible and can be ignored. 81 To calibrate the integrator circuit, two known DC current signals, I a and Ic2, are applied to the integrator circuit, and the calibration is performed as explained in Sec. 3.2.4. The precise DC current Ici has to either be generated on-chip or be supplied from off-chip. Ic2 can be generated using a properly matched current mirror Ic2 = nlci. 4.2.6 BICI accuracy To achieve a high measurement accuracy, sources of error must be identified and their im pact minimized by design. Factors affecting the measurement accuracy of the integrator circuit are as follows: 1. As shown in Appendix C, C\, C2, C3, and Iramp variations and the propagation delays in the comparators, flip-flops and the gates affect the factors K and O in Eqn. 4.6. K and O can be determined using a two-point calibration scheme (obtaining N for two known I values). Therefore, as in single-phase BICI the process, temperature and power supply variations affecting K and O will not affect measurement accuracy 2. The error due to clock feedthrough associated with the switches in the circuit can be minimized as described in Sec. 3.2.5 3. The error term E in Eqn. 4.6 is between 0 and 2, whereas the number N is much larger for large values of M. Therefore, E is negligible 4.2.7 Circuit implementation Assuming that the integrator circuit is to be used in an application where the maximum av erage current in one period of </> is 120 \xA and the available CLK frequency is 20 MHz, the 82 following parameters were chosen to design the integrator circuit: • T = 1 ms, Ts = 1 ps, M = 1000, • Ts(e//) = 0.5 ps, TR - 0.5 p, • fcLK = 20 MHz, • Iramp ~ 11.2^fA • Counter size: 18-bits These parameters imply Ci(yi) = Ci(B) = 30pF. The transistor level schematic of the main circuit and the comparator [100, Chapter 26] are shown in Figs. 4.6 and 4.7, respectively. The component values and transistor sizes are shown for critical components. These values have been chosen to achieve reasonable integration accuracy (error < 1%) as explained in Sec. 4.2.6, and to reduce the circuit area. In each H-CI block, 4>a and <f>b are non-overlapping control signals constructed from <j>. They are used instead of 4> and <f> in Fig. 4.5 to avoid sample and hold errors [97]. The total area of the circuit is 72500 (pm)2. This is equivalent to the area of a digital circuit consisting of 280 NAND gates in a 0.35 \im digital cell library. 83 I- Short-time I analog integrator Cr Vi DD .t/7-l"*50/0.6 —*— ftrl-ctri: i i6/o:6: <E>. :2P: 3 50/0:6-. .10/1. 16/0.6 1_ - Jl Vi7 1/ •T ' .1- • k. <+* O .1 :;!! ' j : XI1 4 FF3 # ^ - TJ.. Q. elk . •Ji >•••< Hr ••ti S& H : m Q D 'l' Q D clr clk< °b v7 clr O elk < Figure 4.6: The transistor-level schematic of the half-wave integrator circuit (HCl) 84 4.3 Simulation and Experimental Results The Cadence SpectreVerilog mixed-signal simulator was used to simulate the integrator cir cuit described in Sec. 4.2.7. Table 4.2 reports the simulation results for the average current measured by the circuit for a set of 13 different current signals, each with different wave forms, frequency, amplitude, and offset values to test the performance of the circuit for a wide range of input signals, described in Table 4.1. Signals DC3 and DC6 are used as calibration signals. The second column in Table 4.2 reports the true average current for each signal, while the fourth column indicates the average current estimated by the BICI. The relative error of the estimated average current is 85 Name Waveform Parameters DC1 DC IDC = 10/i A DC2 DC IDC = 17// A DC3 DC IDc = 25// A DC4 DC IDC = 36/i A DC5 DC IDc = 53ApA DC6 DC IDC = 83.2/x A DC7 DC IDC = 105.6// A DC8 DC IDC = 122 Ap A SIN1 sine f=l MHz, DC offset=36 pA, Amplitude=15.5 pA SIN2 sine f=4.3 kHz, DC offset=87.5 pA, Amplitude=20.6 pA SIN3 sine f=101 kHz, DC offset=20 pA, Amplitude=10 pA TRG1 triangular f=35.7 MHz, DC offset=50 pA, Amplitude=20 pA TRG2 triangular f=20 kHz, DC offset=65 pA, Amplitude=45 pA TRG3 triangular f=4 kHz, DC offset=74 pA, Amplitude=30 pA SQ square Shown in Fig. 4.8 Table 4.1: Double-phase BICI test signals given in the last column. Simulations indicate that the BICI provides a very good accuracy (< 1% error) for all the current signals chosen. 4.4 Conclusions This chapter presented a mixed-signal built-in current integrator (BICI) used to perform cur rent integration for the purpose of analog block testing. The BICI generates a digital signa ture by averaging the current over a programmable time window. 86 60 10 'I (HA) " t ( Hs) 12 16 Figure 4.8: Current waveforms for validating the operation of the integrator circuit The BICI requires small area (equivalent to a circuit consisting of 280 NAND gates). By using any LSFR or register already available on chip (e.g., as part of JTAG or digital BIST) to implement the counter needed for this circuit, a saving of 25% in area is possible. BICI also yields a digital signature which is convenient to interface to standard digital exter nal or internal ATE and standards such as IEEE1149.1. Our circuit provides good accuracy (error < 1%). The monitor is suitable for current-based embedded test application but also for on-chip power monitoring because it is compact and generates a digital signature. In addition, the BICI generates digitized samples of IDD during the integration window. Ad ditional processing of these samples may be used to generate more complex signatures with potentially higher fault coverage. 87 Waveform True I N I estimated 100(A7/7) (M) (fiA) DC1 10 2740 9.9 1 DC2 17 3403 17.0 0 DC3 25 4157 25 0 (Cai. point) DC4 36 5196 36 0 DC5 53.4 6825 53.4 0 DC6 83.2 9634 83.2 0 (Cai. point) DC7 121.7 13322 122.4 0.6 DC8 105.6 11778 106 0.4 SIN1 36 5181 36 0 SIN2 88.67 10142 88.6 0.07 SIN3 20 3690 20 0 TRG1 50.1 6505 50 0.2 TRG2 65 7925 65 0 TRG3 74 8763 73.9 0.14 SQ 22.63 3929 22.6 0.1 Table 4.2: Simulations of average current measurements by double-phase BICI 88 Chapter 5 On-Chip Jitter Specification Testing of High-Performance PLLs This chapter presents a jitter measurement and generation circuit for BIST of PLLs. The circuit satisfies all the conditions for a practical BIST circuit described in Sec. 2.2.4. The measurement circuit is fully digital and automatically synthesizable, occupies an area equiv alent to 1200 2-input NAND gate, provides a resolution of approximately lOps (~l/5 of a gate delay in a standard 0.35 fim technology), and generates a digital signature which can be read out by an inexpensive tester for further analysis to obtain the jitter characteristics. The remainder of this chapter is organized as follows. In Sec. 5.1, various jitter spec ifications are defined. Sec. 5.2 describes the jitter measurement circuit. Sec. 5.3 details the jitter generator circuit. Sec. 5.4 outlines ways in which the jitter generation and measure ment circuits can be used for testing various jitter specifications of PLLs. Sec. 5.5 contains the circuit implementation details. Sec. 5.6 reports some simulation results, and Sec. 5.7 concludes the chapter. 89 5.1 Jitter Definitions The definition of jitter varies depending on the fields of application. In sequential circuits, e.g., CPUs, jitter is defined as the variation of the clock period, known as cycle-to-cycle or period jitter. Such variation is best modeled as a frequency modulation of the clock signal. More formally we can write: VFM(t) = sgn[sm( f\ ^ )dt)] (5.1) Jo l0 + lj{t) where VFM(£) is the clock signal, T0 is the average clock period, Tj(t) is the frequency modulating jitter signal and sgn[x] is the sign function: sgn[x] 1 x > 0 (5.2) 0 x < 0 Fig. 5.1(a) illustrates how the period jitter samples are collected by measuring the duration of each period of the signal INI. In serial communication applications, jitter is defined as the short-term variations of a digital signal's significant instants, e.g., rising edges, from their ideal position in time [20]. Such jitter is often often denoted as accumulative jitter and is described as a phase modulation of a clock signal. Formally: VpM{t) = sgn[sin(u0t + u>0Tj(t))] (5.3) where VpM{t) is the jittered clock, u>0 is the average angular frequency, and rj(t) is the phase modulating jitter signal. In a clock synthesis circuit, where the absolute jitter is im portant, often a jitter-free (practically low-jitter) reference signal is used for jitter measure ment. In such a case, the difference between the position of corresponding edges of the 90 signal (INI) relative to the reference clock (REF) indicates the jitter. Fig. 5.1(b) illustrates how accumulative jitter samples, TJ^ for i = 1,..., are collected. Sometimes, the relative jitter between two signals is of interest if neither of the two signals is a jitter-free signal, e.g., in data recovery circuits. Fig. 5.1(c) shows how relative jitter between the edges of signal INI and IN2 is measured. IN1 (with jitter) Period Jitter Measurement IN1 perioch^ T T T jitter ^ J(1>' J(2>' J(3)' IN1 j(D TJ(2> \JJ(3) (a) IN1 (with jitter) REF flitter-free) Accumulative Jitter Measurement Jitter on IN1 edgea IN1 REF TJ(1) • XJ(2) • XJ(3) • (b) IN1 (with jitter) IN2 (with jitter) Relative Jitter Measurement Relative jitter , XJ(1j > %J(2) . ZJ(3) < (c) IN1 IN2 'J(1> ZJ(2) TJ(3) XJ(4) TJ(2) TJ(3) XJ(4) Figure 5.1: (a) Measuring cycle-to-cycle or period jitter, (b) Measuring accumulative jitter using a reference clock, (c) Measuring relative jitter For both period and accumulative jitter measurements, M jitter samples, Tj^ or rj(j) (i = 1,..., M) are collected to calculate jitter characteristics, such as rms, peak-to-peak, or 91 frequency components. For example, the rms and peak-to-peak period jitter is obtained as: \ M-l 1/M £ T](l) 0 Tj(pk-to-pk) = max(Tj) - min(Tj) 5.1.1 PLL jitter specifications The important jitter specifications for PLLs used in digital communication interfaces are intrinsic jitter, jitter tolerance and jitter transfer. These specifications are given in standards for each application (e.g., see [20] for SONET interfaces). 1. Intrinsic jitter is defined as the jitter at the output of the PLL when the input is jitter-free. This is often expressed in terms of unit interval UI, which is defined as the period of a signal with a frequency equal to the average frequency of the original signal. For example in 155.54 MHz SONET network application, 1 UI is 6.429 ns 2. Jitter transfer is defined as the ratio of the output jitter to input jitter of the PLL as a function of frequency 3. Jitter tolerance is the peak-to-peak amplitude of the sinusoidal jitter applied to the input of the PLL which causes ldB power penalty (in terms of bit error rate) 5.2 Jitter Measurement Circuit (JMC) Here a digital circuit is presented which is capable of measuring jitter not only of PLLs, but of any signal with high resolution, as illustrated in Fig. 5.2. The core of this circuit is a 92 high-resolution time-to-digital converter (TDC) which measures a time interval Td: Td —tsTOP —tSTART (5.4) where tsTOP and tSTART are the time instances at which the rising edges of the STOP and START signals occur, respectively. In this circuit, the Edge Sampler block controlled by the ES Controller selects the appropriate START and STOP edges and passes them to the TDC. For measuring different jitter specifications, the Edge Sampler and the ES Controller have to be adapted accordingly while TDC remains the same. Examples of Edge Samplers (and their associated controllers) are given later in Sec. 5.4 for cycle-to-cycle and relative jitter measurements. ES Controller (ESC) Reference IN1 IN2 ref Edge Sampler ln1 (ES) START STOP High resolution TDC STARTJn STOPjn Figure 5.2: Block diagram of the proposed jitter measurement circuit The TDC circuit details follow. However, before delving into the details of this cir cuit, the state of the art in TDC design is reviewed. 5.2.1 State of the art in TDC design A classic method of measuring a time interval Td is to start a counter at the beginning of the interval and stop it when the interval ends. The resulting number in the counter will 93 be proportional to Td- The resolution in this method is the period of the clock controlling the counter. To measure intrinsic jitter of a high-speed PLL (e.g., 155MHz clock synthesis PLL), where a high resolution in the range of 20 ps is required, a clock frequency of 50 GHZ would be needed! Obviously such method is not suitable for on-chip high resolution time measurement when the maximum clock available is in the range of a few hundreds of MHz. In [102] a TDC based on the use of a delay chain as shown in Fig. 5.3 is presented. In this circuit, the output of the delay elements in the delay chain are set HIGH as the START rising edge travels through them. When the STOP rising edge arrives, only the flip-flops with a HIGH on their D inputs will have their outputs set HIGH. That is, the final flip-flop settings correspond to a snap shot of the delay chain at the time of the STOP rising edge. Therefore the number of set flip-flops indicates the number of delay elements (N) that the START edge travels through before the STOP edge arrives. Consequently, Td = tsrop — t ST ART = NTA + Tc + TQ where TA , the quantization step, is the delay of each delay element, 0 < TQ < TA is the quantization error, and Tc is a constant offset delay due to set-up time of the DFFs and any delay difference in the paths of the START and STOP signals to the delay chain and the recording flip-flops. A delay locked loop (DLL) is used to calibrate the delay elements to a known delay TA = Trej/M, where Trej is the period of a reference clock and M is the number of delay elements. Such a calibration requires very good matching between all the delay elements in both the delay chain and the DLL. In [35] an alternative circuit is proposed to combine the delay chain and the DLL, hence obviating the need for element matching. In schemes mentioned above, the DLL and the controlled delay elements are ana log. Eliminating the DLL and using digital gates as delay elements make the circuit fully 94 Delay-Locked Loop H>— I DE1 H DE2 *H DEM Charge Pump Phase detector + Loop filter START STOP Clk Digital control circuit (Asynchronous) " WDelay eTemerils " i Delay Chain Clk 1 Rst DEM Clk Recording flip-flops jClk 1 Rst Sync Clk In1 In2 InM Peak-to-peak, RMS measurement Pass/Fail N-bit data (N < M) D14 R2 START rA D3 I I : I I I _1._.1...J STOP Figure 5.3: Time digitization using a delay chain 95 digital. In that case, a two-point (instead of one-point) calibration scheme can be used to extract TA and Tc- The trade-off is decreased accuracy due to the quantization error asso ciated with calibration reference inputs, as demonstrated in Appendix D.l (Eqns. 5.35 and 5.32). The resolution (TA) of such methods without time interpolation is limited to one gate delay at best. In a 0.35 /im CMOS technology, the smallest gate delay is approximately 50 ps, whereas a resolution and precision of about 20ps is required for functional testing of high-speed PLLs with 155 MHz center frequency[20]. Also, since this delay is dependent on process variations and temperature, the resolution in such schemes is not controllable. The authors of [36] propose the use of an array of DLLs to improve the measurement reso lution, while those of [103] propose an RC delay line approach to increase the measurement resolution through time interpolation. Although resolutions in the range of 25ps (rms) have been reported in these papers, the design of the circuit requires a great deal of care because of the need for a high degree of matching. Also, the design and layout of the DLL need careful attention due to the presence of significant power supply noise in large mixed-signal ICs. In [37] a differential delay technique based on using two delay chains is used (Fig. 5.4). One chain is composed of gates (each with a delay of r3), while the other is made of latches (each with a delay of 77). The latch in chain 2 samples the signal at the z-th tap of the chain 1 (A) on the rising edge of the signal Fi. Since Fi is delayed with respect to Di, latch L0 samples HIGH. Since rg < 77, Di approaches as time progresses until the edge on Fi passes Di and samples a LOW for i = N. In this method, the time quantization step is the difference between the delay of the delay elements in two delay chains: ?A = n - Tg (5.5) 96 Clk I I STOP I (Jitter-free signal) 1 Delay Chain 1 Each delay= Tg i START (JJttered clock) i Delay Chain 2 Digital control circuit (Asynchronous) DM r\ Each delay= T| I L D Clk Q •— D Clk Qr»-r Rst Lp J- Rst I-) FM J"1 \ D Clk Q Rst LM Sync In1 In2 InM Peak-to-peak, RMS measurement Clk Pass/Fail N-bit data (N < M) *START fSTOp F1 I F2 ;F3 START ! Ij T - T =N(1.- 1J START STOP 1 / g (N: The number of set FFs) 7—r~ i I DI :D2 ;D3 STOP 4-From this point on the latches will sample '0' (N = 4) I L0 ^t j L2 set ; ^ ^ L-| set L3 set Figure 5.4: Time digitization using differential delay technique 97 Since gates and latches are very different structures, 77 and rg may differ significantly, mak ing it difficult to achieve high resolution (in the range of 20 ps or less). All the schemes mentioned above require good matching of the elements in the delay chains, something which is difficult to achieve within an accuracy of 1% under typical pro cess variations. As the time interval to be measured becomes longer, more elements must be added to the delay chains, making it even more difficult to assure matching of delays in the chains; when more elements more added, the elements will have to be placed further apart and more routing delay will have to be accounted for. Therefore, these schemes do not provide good TDC linearity. In addition, they do not lend themselves well to automatic place and route. Furthermore, the resolution is set by the process parameters on each chip and cannot be controlled or adjusted. In the following section, we introduce a high-resolution TDC which provides good linearity, is automatically placeable and routable, and has an adjustable resolution. 5.2.2 High-resolution TDC Fig. 5.5 illustrates the block diagram of the proposed TDC circuit. The Time Quan tizer (TQ) block quantizes time with a quantization step of which is set by the Resolu tion Adjustment (RA) block to a value less than a programmable threshold. This threshold is supplied to the circuit as a 16-bit digital number. Since the maximum time interval measur able by the TQ is limited, the Range Extender (RE) block is used to extend the capability of the TQ to measure longer time intervals. The Calibration Controller (CC) calibrates the TQ using a reference low jitter clock to provide a precise estimate of TA- The TDC Controller (TC) controls the communication and sequence of operation of the different blocks. After 98 TDC Controller (TC) START STOP To Edge Sampler | Ref (jitter-free)^ Calibration Controller ref (CC) StartCal EOCal Range Extender (RE) START STOP Time Quantizer (TQ) -A n-bits Resolution Adjustment (RA) . Block V-Figure 5.5: Block diagram of the proposed TDC circuit resolution adjustment and TQ calibration, the TC instructs the Edge Sampler controller to pass jitter samples as time intervals to the TQ for measurement. The following section de scribes the principle of high resolution time measurement and reports the details of each block. 5.2.3 Notation and definitions The notation and definitions used throughout the remainder of the chapter are listed next. Note that any variable denoted by t refers to an instant in time, T refers to a time interval, and T refers to a time delay associated with a physical structure in the circuit, e.g., gates, routing, etc. • tSTART'- The time when the START signal is set HIGH 99 • tsrop- The time when the STOP signal is set HIGH • Tj, = tsrop — tSTART- the time interval to be measured • clkA: The output signal of oscillator A (Osc-A) • clkB: The output signal of oscillator B (Osc-B) • TA(TB): clkA(clkB) period • tx(i)'- The time when the i-th rising edge of clkX (X = A or B) occurs. • TA = TA — TB'- The time quantization step. This is also the resolution of the TDC. • N: The final TQ number indicating Td value • MA(MB): The output state of the k-bit counter CntrA(CntrB) 5.2.4 Time quantizer The circuit proposed here uses a differential method to obtain high resolution. It relies on the difference between the periods of two oscillators for time quantization rather than on gate delay, therefore, reducing the need for circuit matching. In fact, the circuit is made virtu ally insensitive to mismatches by using a period adjustment scheme discussed in Sec. 5.2.7. This makes the circuit fully synthesizable and automatically placeable and routable using standard digital circuit electronic design automation (EDA) tools. The operational principle of the TQ is as follows. Assume Td as defined in Eqn. 5.4 is to be measured. Fig. 5.6(a) shows the schematic of the TQ circuit which is the core of the jitter measurement scheme. It consists of two ring 100 oscillators, one flip-flop, and one counter. The resolution of the scheme is dictated by the time quantization step, TA, obtained as: To conceptualize the operation of TQ, assume that in a sample chip, TA is a small time about 20 ps. Sec. 5.2.7 describes a circuit which automatically adjusts the resolution to guarantee the required resolution under typical process and temperature variations. The waveforms in Fig. 5.6(b) illustrate the operational principle of the circuit. Os cillators A and B (TB < TA) start oscillating at the rising edge of START and STOP, respec tively. The counter MAIN starts counting at the STOP rising edge. The output of oscillator B, clkB, is sampled at the rising edge of clkA by the D flip-flop EOC JDFF to set the end-of-conversion flag, EOC_Flag. Assuming Td is larger than TA, EOC_Flag will be LOW for the first cycle of clkB. However, for every cycle of clkB, the i-th. rising edge of clkB approaches that of clkA by TA, until eventually the A^-th rising edges of clkB precedes that of clkA by the setup time of EOC JDFF, causing EOC_Flag to be set HIGH: where TEOC is the setup time of EOC_DFF, and 0 < TQ < TA is the quantization error. At this time, the MAIN counter stops and the digital control circuitry is able to process the output of the counter, N, which indicates the value of Td. The tA(N) and tB(N) are obtained as below: TA = TA- TB (5.6) tB(N) = tA(N) ~ TEOC — TQ (5.7) ^A(N) = t ST ART + TA + NTA (5.8) . *B(JV) = tsTOP + TB + NTs (5.9) 101 Figure 5.6: Time digitization using two oscillator period difference method 102 where TA and rB are delays from START and STOP signals to the D and CLK inputs of EOCJDFF, respectively. From Eqns. 5.7, 5.8 and 5.8: tsrop - tsTART = N(TA - TB) - TB + TA - TEOC - TQ (5.10) Therefore: NTA = Td + Tc + TQ + TR (5.11) where Tc = TB — TA + rEOc is a constant offset time, and TR is a random error term due to intrinsic jitter of the gates and flip-flops (refer to Sec. 5.2.10 for more details). The setting of EOC_Flag is also used by the TDC controller to initiate processing of the data and to initialize measurement of another time interval. Sec. 5.2.6 demonstrates how to estimate TA and Tc through a two-point calibration scheme, while Sec. 5.2.10 provides an analysis of the random errors terms TQ and TR in Eqn. 5.11. Completing one measurement requires some time, denoted by Tmeas- Tmeas depends on the value of the Td. Assuming that the error terms in Eqn. 5.11 are negligible, then Td + Tc = NTA • Since it takes cycles of clkA to perform the measurement, the required measurement time is: ATHT Td ~\~ Tc f-p meas — ^ J-A — Tp 'A J-A For example, if Tc = 0, measuring an interval of 1 ns (Td = Ins) with a resolution of TA = 20 ps (N = 50) requires 507^ of time. If TB = Ansec, the measurement time is approximately 200 nsec. 103 EOCJDFF metastability From Fig. 5.6 EOCLDFF is used to set EOC_Flag indicating that the measurement is com plete when Eqn. 5.7 is satisfied. If for some value of Td, TEOC — Tmw/2 < tA(N) ~ tB(N) < TEOC + Tmw/2 where Tmw is a small time interval, EOCLDFF may exhibit a metastable behavior. This means that the EOCJDFF output might take significantly longer than rc^_io_g to set its out put HIGH. Tmw is called the metastability window of the EOC_DFF. As shown in Appendix E, Tmw is less than 0.01 ps for a flip-flop is a 0.35 \im CMOS digital cell library. The ex cessive delay due to metastability can cause a logic error in synchronous circuits with asyn chronous inputs [104, Sec. 3.11]. However, in the TQ, if this delay results in no decision after the 7V-th rising edge of clkB, the decision to end the measurement will be made by EOC_DFF at the next rising edge of clkB, i.e., on (N + l)-th edge. This is because the relative delay between the N + 1-th edges of clkA and clkB will increase by TA which is larger than Tmw, and therefore, no metastable behavior can occur on the successive edge. As discussed in Sec. 5.2.10, since Tmw is less than 0.01 ps, it does not significantly affect the precision of the TQ. EOC-Flag is also used by the TDC Controller to control the sequence of operations in the TDC. Therefore, synchronizers must be used to ensure the reliable operation of the synchronous circuit in the TDC controller [104, Sec. 3.11]. In the implementation of TDC described in Sec. 5.5 a single flip-flop (TQEOC_sync_DFF in Fig. 5.22) is used for synchro nization. 104 5.2.5 Measurement range extension From the waveforms in Fig. 5.6(b), it can be concluded that if Td > TA — DTB (D is the duty cycle of clkB), EOCLDFF will sample a HIGH at the second rising edge of clkA, which signals an end-of-conversion erroneously. Also, if Td < —Tc, the first rising edge of clkA will sample a HIGH regardless of the value of Td. Therefore, the valid measurement range of Td for this circuit is: -Tc < Td < TA - DTB (5.12) To extend this range, a Range Extender (RE) circuit is used. The RE block ensures that the i-th rising edge of clkB and clkA are within the valid measurement range of the TQ (given in Eqn. 5.12) before allowing EOCJDFF in the TQ to start sampling clkB at clkA rising edges. The RE block consists of three flip-flops, two counters and a £>bit comparator as shown in Fig. 5.7(a). The waveform diagram of the circuit is also given in Fig. 5.7(b). This block generates a flag signal (REJFlag) when tA^ — tB(i) < TA\, where —Tc < rAx < TA — DTB. The details of the RE block operation follows. The signal clkA is delayed by rA\ and TA1 + rA2, using the delay buffers Dbufl and Dbuf2, to generate clkAl and clkA2, respectively. The two k-bit counters, CntrA and Cn-trB, which are initialized to 1 and 0, count the number of rising edges of clkA2 and clkB, respectively. Fig. 5.7(b) shows different waveforms in the circuit for Td = 2.6TA. As shown in Fig. 5.7(b), the number in CntrA (i.e., MA) remains larger than the number in CntrB (i.e., MB) as long as tA2^ - tB{i) > TAI + rA2. When tA2{i) - tB{i) < rA1 + TA2, MA becomes equal to MB for a short amount of time, causing the comparator to generate a pulse which becomes wider at the subsequent clkB rising edges. This pulse, when sufficiently wide, sets the REJFlag, allowing EOCJDFF to start recording the relative position of the rising edge 105 clkA To EOC_DFF rst input Dbufl clkA1 Dbuf2 clkA2 clkB k-bit counter (CntrA) > rst ^> k-bit comparator Irb r cmp_out k-bit counter (CntrB) * rst V Irb V clkA1 clkA2 D Q Ext. .DFF1 Clk rst Yrb D Q Ext_ DFF2 Clk rst Esampl RE-Flag clkA2 0 Q Clk rst Irb Esamp2 Irb clkA clkA1 clkA2 (Ideal CntrA < 3-bit ( 2-bit p • 2 t 3 n 4 . 5 . 6 i 7 . 8 i 9 • 10 i 11 • 12 • 13 i 14 • 15 i 16 i 17 • 18 • 19 i 20 I 21 clkB f Ideal CntrB < 3-bit ( 2-bit cmp_out Esamp2 Esampl ER_Flag (a) -r„—. 2 ©I 3 ©:: 4 5 ; 6 ; 7. : o ; 1 ; ©: ©: ©: ©: ©: 2 ; 3 ©:© 4 ; ©: 5 0 6 ; 7 ; ©: ©: 0 © 1 © 2 © 3 © 4 © if 2-bit lounter used" 0 0 © 1 0 2 . 2 j ©: 3 i 4 . 3 j 4 j ©: ©: 5 . 5 ; 0! 7 i 8 . 9 . 10 i o ; 1 ; 2 ; ©: ©: ©! 11 . 3 | ©: 12 i 4 ; ©: 13 i 14 . 5 | 6 | ©| ©; 15 . ©i 16 i o ; ©: 17 . 18 . 1 ; 2 ; ©: ©: \ 4 J short glitches that might. J ) \ ^setlEsamp2 erroneously ^ '!>K 19 i 20 3 ; 4 ©: © i random glitch short glitches that might A set Esampl erroneously \ random glitch 22 6 © 231 I 24 | ! 71: o I: :©I:©I: \\\ i 21 . 5 ; :©: 22 • 6 ; :©: £3 . ;7 | ©: •eq (b) Figure 5.7: Measurement range extension to (2k - l)TA 106 of clkA and clkB. Appendix F presents the operation of the RE block more rigorously from a mathematical viewpoint. Since the RE block is asynchronous, a novel time diversity sampling technique is used to ensure valid sampling of the comparator output. On each rising edge of clkA2, the output of CntrA changes. Since the CLK-to-Q delay for each output bit of CntrA will differ for a short period of time after the rising edge of clkA2, the number MA can a have tran sient random value. This random value, if equal to MB, may result in a short pulse at the comparator output. Since this short pulse occurs after the rising edges of clkAl and clkA2, it will not be sampled by ExtJDFFl and Ext_DFF2. However, such random glitches may also occur after the rising edge of clkB due to CLK-to-Q delay differences in the output bits of CntrB. These glitches, if close to the rising edges of clkA2 (or clkAl), may be sam pled by Ext_DFF2 (or Ext_DFFl). Choosing TA2 such that it is larger than the maximum width of such glitches guarantees that Ext JDFF 1 and Ext JDFF2 will not be set HIGH in the same cycle of clkA2 due to such glitches. As tA2^ — tB{i) becomes smaller, the cmp_out pulse becomes wider until it is also sampled by ExtJDFFl. At this time, the REJ^lag is set HIGH. In summary, when Esampl and Esamp2 are both set HIGH, it is concluded that the cmp_out pulse has been wider than any possible glitch due to the asynchronous nature of the RE block. From the above discussion, rA2 is chosen such that it exceeds the maximum glitch width. The glitch width can be reasonably assumed to be 50% of TCLK-IO-Q , where TCLK-to rs, the worst case CLK-to-Q delay for an output bit of CntrB. This assumes that the vari ations of TcLK-to-Q, denoted by ATCLK-IO-Q, is less than Q.2bTCLK-to-Q under process variations. The actual value of ATCLK-IO-Q can be obtained by running monte-carlo anal-107 ysis on the D flip-flops used in CntrB. TAX must be within the range in Eqn. 5.12. We chose rA1 = —Tc 4- 3Tsetup (Tsetup is the maximum setup time for EOC JDFF) in a standard 0.35 /im CMOS process since this value is well within the required range. It is worthwhile to note that this RE circuit does not affect the precision or accuracy of the measurement because it only ensures the closeness of the i-th rising edges of clkA and clkfi without interfering with the path of clkA and clkB signals to EOC_DFF, which is the critical path for precision and accuracy. From Fig. 5.7(b), the range extension achieved by this circuit is Td < (2k — l)TA. In this case, since Td = 2STA, both 3-bit and 2-bit counters for CntrA and CntrB can be used. This is also evident from the mathematical analysis of the RE given in Appendix F. 5.2.6 Calibration From Eqn. 5.11, the relationship between N and Td is linear. Therefore, knowing the values of Tc and TA suffices to estimate Td from the number N. To estimate Tc and TA, two accu rately known time intervals Tca/i and Tca/2 (typically supplied from off-chip) are measured and the resulting TDC numbers, Ni and N2, are recorded: NcallTA = Tcau + Tc + TQI + TR\ (5.13) NCCI12TA = Tcal2 + Tc + TQ2 + TR2 where TQI and TQI are the quantization errors, and Tm and TR2 are the random errors asso ciated with measuring Tcan and Tca/2, respectively. These two measurements are used in a two-point calibration scheme, described in Appendix D.l, to estimate Tc and TA. This Ap pendix also shows how the random terms TQI, TQ2, Tm and TR2 in Eqn. 5.13 result in Tc and TA estimation errors, denoted by TCe and TAe. From Eqn. 4D, the standard deviation of 108 TAe, &TAC, is less than 0.1%ifTcad and Tcai2 are chosen such that ./Vca(2 - A^i > 200. How ever, Eqn. 7D shows that the standard deviation of Tbe, aTce, can be several TA'S, which results in measurement accuracy degradation. This inaccuracy can be decreased using the n-point calibration scheme described in Sec. D.2. In this calibration scheme, N is obtained for n calibration time intervals Tca/(j) = 0, Tref,..., (n — l)Tre/ for i = 1,..., n. The correlation between the n measurements is used to shrink the range of Tc variations and provide a more accurate estimate of Tc • Ref IN1 MUX1 D Q ST. _DFF Clk rst rst START Ref Cai (K-1) cycle delay generator (K_DGen) Clk SP_in Ref IN2 >0 MUX2 11 S MD Q SP_DFF Clk rst STOP I rst Cai (a) K = 0 K= 1 K = 2 - J1JUUU1 I I s (b) Figure 5.8: KTref interval selection circuit Since a low-jitter reference clock is often available on the chip, for two-point or n-point calibration it is convenient to choose Tcall = TreJ, Tcal2 = 2Tref,..., Tcaln = nTre}. 109 A circuit that allows reliable generation of KTrej intervals is shown in Fig. 5.8(a). In this circuit, when Cal=0, the Ref signal is connected to the elk inputs of SPJDFF and ST JDFF. Since D input of ST JDFF is always HIGH, START is set high at the first rising edge of the Ref signal. The STOP signal always is set HIGH one Ref cycle after SP Jn turns HIGH. Since the KJDGen state machine block sets SPJn to HIGH (K — 1) cycles after the rising edge of the Ref signal, K Ref cycles delay results between the edges of START and STOP. The waveforms in Fig. 5.8(b) illustrate the operation of the circuit for K = 0,1 and 2. Constant delay is generated in the path of calibration signals in this circuit. The same delay will be used in the actual measurement, except for the term ATMUXI — ArMux2, which represents the variation of the difference in propagation delays from 10 and II inputs to output in the multiplexers MUX1 and MUX2, respectively. If the mismatch is signifi cant, estimated value for Tc during calibration will not be the same as the one used in ac tual measurements, resulting in additional error. Therefore, the Ref signal paths to elk inputs of SPJDFF and ST JDFF must be matched to the INI and IN2 signal paths to the same in puts, respectively. Here, it is assumed that this matching is achieved, and therefore the term ATMUXI — ATMUX2 is negligible. This matching, however, is not required in a differential measurement method because in this method Tc does not affect the measurement accuracy or precision (refer to Sec. 5.2.11 for details). 5.2.7 Automatic resolution adjustment The circuit in Fig. 5.6 provides a high resolution, i.e., a small TA, by generating a small difference in loop-around delay in the two oscillators A and B. This small delay can be achieved by using additional capacitive loading (CL) at the output of a logic gate in either 110 of the ring oscillators. However, any mismatch between the gate delays and interconnect wiring in the oscillators A and B also contributes to TA. This mismatch can cause a signifi cant increase in TA, resulting in resolution degradation. The mismatch might also result in TB > TA, causing a measurement error. To overcome the effects of mismatch, we use the resolution adjustment technique shown in Fig. 5.9. Using this technique, TA and Tg are controlled digitally [105]. To do so, a series of digitally controllable capacitive loads are connected to a number of nodes in both oscillators A and B through switches. Each load and its associated switch form a controlled load (CL) cell. Turning ON the switch in a CL cell connected to a node in one of the oscillators adds some loading to the corresponding nodes, resulting in longer output oscillation periods. CL cells can be designed and added to the standard digital cell library of a technology to preserve the possibility of automatic place and route. The actual design considerations for the CL cells are addressed in Sec. 5.2.8. The details regarding the control of the oscillators output period are as follows. Assume that some CL cells are activated. The calibration control circuit performs calibration using two known time intervals Trej and 2Tref. The two resulting counts are then subtracted to yield the difference NA = N2 — Nr. Assuming the measurement error is negligible, NA and TA are related by: Since Tref is constant, a larger NA indicates a smaller TA. Assume a resolution of Tth is required, therefore: Tref = NthTh 111 t>»<-f<*5 icij \ci°, PI ! ft iC,-r- 4 n rb rb Oscillator B rb r rb rb Counter Clk clkB r STOP r Irb D^£X ^> I A-I •// x vi START I rb Oscillator A r£H> clkA D Q EOC_DFF| Clk rst 1-iEOC-Flag "rb CLK -^ Digital control circuit (Synchronous) rb Resolution Adjustment Controller a„ a, b. CLK fe cells Figure 5.9: Automatic resolution adjustment circuit 112 where Nth is the TDC output number associated with the resolution Tth. If, for a specific loading condition, is smaller than the pre-determined threshold Nth, the switch in a CL cell is turned ON and A^A is obtained again. Turning ON a CL switch increases TA or TB, allowing for smaller TA = TA — TB- For example, assume TA = 3.255ns and TB = 3.205 ns. Therefore, TA = 50 ps. If activating a CL cell in the oscillator B results in TB = 3.235 ns, a better resolution of TA = 20 ps can be obtained. The resolution adjustment (RA) control circuit searches for the vectors a = a0 ... a/_x and b = b0 ... 6;_i such that the only CL cells activated (switch turned ON) are those that result in a TA < Tth (or equivalently A^A > Nth)- The algorithm used by RA block depends on how much delay each controlled load adds to TA or TB when it is activated. This algo rithm is given in Sec. 5.2.9. Two different approaches in designing CL cells, the uniform toad and the incremental step load, are described in detail. Uniform load One method for resolution adjustment is to use the same cell for all the controlled loads CLf,i = l,...,l and CLf,j = 1,..., / . The switch and the loading capacitor of each CL cell should be designed in such a way that when a cell is activated, the nominal added delay to TA or TB is less than 0.5Tth- This can be done by choosing a correct size for the pass transistor by implementing the switch and/or the capacitor value. Therefore, as a (b) goes from 0..0 to 1..1, TA (TB) steps through / values which are Tstep = 0.5T<^ apart. Therefore: TA = TA0 - TB0 + [ONE(a) - ONE(b)]Tstep (5.14) = TA0 - TB0 + \[ONE(a) - ONE(b)}Tth 113 where TAO = TA\a=o..o, TBO = ^fi|?=o..o an(* ONE(x) is a function yielding the number of 'l's in a binary number x. If the initial difference between TA and i.e., (TAo — TBO), is in the range (—1/2(1 — l)Tth,1/2(1 — l)Tth) there exist two vectors a and b which will result in TA < Tth. Eqn. 5.14 assumes an ideal case where the TA and TB change with constant step of Tstep = 0.5Tth as ONE(a) and ONEib) increase. On a real chip it is difficult to guarantee the uniformity of the steps because the value of Tstev varies with process variations, and also because it is affected by turning ON the neighboring CL cells. Assume that Tstep(i) < Tstep < Tstep(u), where Tstep{i) and Tstep^u) are the lower and upper 3<r thresholds of Tstep probability density function (PDF) obtained through monte-carlo simulations of loaded ring oscillators. As long as Tstep(u) < Tth, a and b that satisfy the resolution requirement can be found under process variations if: —lTatep(i) < TAo — TBO < lTstep(i) (5.15) If Tsiev(\) is small relative to Tth (e.g., 0.2Tth), larger values of / must be chosen to ensure valid resolution adjustment for large TAo—TBO- Using 3<r thresholds of Tstep PDF for Tstep(i) and T5iep(u), 99% of the manufactured circuits are guaranteed to meet the required resolu tion, whereas, using 6a thresholds guarantees a successful resolution adjustment for 99.94% of the circuits. The maximum time for resolution adjustment, Tadj(max), occurs when all 2(1 + 1) combinations of a and b with different number of' l's in a or b have to be tried before the required resolution is achieved. Therefore: 21-1 Tadj(max) } y TcalH,^ i=0 114 where Tcaiib{i) is the time needed for a two-point calibration for the i-th state of a, b. Since Tref and 2Trej are used for calibration: _ 37^+27^ where TA(i) is the TA for the i-th selection of a and b. For small values of Tth, a large number of CL loads might be needed. This is because the Tstep must be small and a large / is required to guarantee successful resolution adjustment for possibly large TAO — TBO- In that case, the incremental step design (described next) is preferable. Incremental step load Another method for delay control is to design CL cells such that where TCLA is the delay added to the total ring oscillator A loop delay where CLf is acti vated and 0 < £ < 1 is a constant. Such design allows for different resolution adjustment steps. For example, if TCLA = Sps and £ = 0.5, then TCLA = 8ps, 12ps, 18ps, 27ps, 40.5 ps, 60.75 ps fori = 1,..., 6. Therefore, assuming TCLA = TCLB for % = 1,...,/, TA can be adjusted by steps of Tstep = ±TCLA, ..., ±TCLA. This method effectively provides different levels of coarse and fine resolution adjustment steps. This enables the circuit to achieve very fine resolutions (less than 5 ps in a 0.35 fim CMOS process) while reducing the average adjustment time Ta#, using binary-like search algorithms explained Sec. 5.2.9. To guarantee the resolution adjustment, the maximum of the smallest adjustment step should be less than Tth. The maximum of the smallest adjustment step, denoted by TCLA , l(u) 115 can be chosen as the upper 3a threshold of TCLA PDF under process variations, xi has to be selected such that under process variations, for any a, the difference between TA for a and a + 1 is less than Tth- Ideally, xi could be derived from 3cr variation of TCLA (i = 1,..., I), however, since this derivation is cumbersome, an arbitrary value of £ = 0.5 is chosen for the implemented circuit reported in Sec. 5.5. 5.2.8 Controlled load (CL) cell design osc Figure 5.10: CL cell evaluation test bench In this section, advantages and disadvantages of different CL cell design styles are described. The evaluation test bench is the circuit shown in Fig. 5.10, where a ring oscillator is loaded by 6 CL cells (/ = 6) and the output oscillation period, Tosc is measured for a = 000001,000011,000111,001111,011111, and 111111. Then difference between Tosc and To = Tosc 15=000000 is calculated. This difference is denoted by Tdij. A standard 0.35 [im CMOS technology has been used for evaluation purposes. Fig. 5.11 illustrates different design styles for CL cells and their simplified models. 116 r-h Ctrl • r •-HE < M, L 4jl / 0.6n i i (al) Ctrl > D-r-con P (a2) con P Ctrl ] |—i 4(1/0.6(1 T10,F i con P Ctrl ! :T_ -srs; con P -L ' 10 fF Ctrl ; •—1 4n/o.6n (cl) Ctrl V (c2) con felj ga; Ctrl • gb (L> R. Ctrl• Dr--. db(L} i Ce2j Figure 5.11: Different CL cell styles: (al, bl, cl, dl, el) Circuits; (a2, b2, c2, d2, e2) sim plified models The important design consideration for CL designs are: 1. The cell area for achieving a unit of T<HJ. This area should be minimized 2. The sensitivity of Tdij to control voltage (Vctri) variations: QTdi, _ ATdif Vctrl ov. . — v«" Tdif AVctrl If this sensitivity is high, Vctri noise will add jitter to clkA and clkB when the CL cells are connected to oscillators A and B in Fig. 5.6. This, in turn, increases TR in Eqn. 5.11, which translates into a loss of precision in the TDC. In the following, Cgs(X), Cgd(x), Cgb(x), Cdh(X) and Csb^X) denote the gate-source, 117 gate-drain, gate-bulk, drain-bulk and source-bulk capacitances of the transistor Mx, respec tively, where X is a transistor identifier. The voltage-controlled NMOS capacitor design (style a) has been proposed in [105] to implement a controlled delay line. Although it provides a relatively large Tdij in a small area, the Tdi j is quite sensitive to Vctri because the equivalent capacitive loading of the CL cell is a function of Vctri. Values for Sv*'t are listed in Table 5.2.8 for the different CL cell styles for comparison. In Fig. 5.11(bl), a capacitor is used as the load. A simple model for such a CL cell, shown in Fig. 5.11(b2), consists of an ideal switch S, the switch resistance Rs, the switch drain capacitance Cd(s) = Cdb(s) + Cgd{s), the switch source capacitance Cs(s) = Cs&(s) + CgS(s), and the load capacitance CL- Rs is in the range of a few tens of MVt when the switch is OFF and a few KVi when it is ON. As is evident in the model, the CdiS) and CS<S) are also loading the oscillator. Since Cdb(s), Cgd(s)> Csb(s), and Cgs(s) are functions of Vctri,-this style has a high Tdij sensitivity to Vctri. In fact, any design with the switch connected to the oscillator node suffers from this high sensitivity characteristic. An alternate circuit and its simple model are shown in Fig. 5.11(d) and (c2). In the model, Cd(s) = CdhfS) + Cgd(s)- This design provides a low Tdii sensitivity to Vctri (see Table 5.2.8) because when the switch transistor Ms is ON, the impedance of Cd(s), %d(S) = l/2irfCd(s) » Rs- Therefore, the Cd(s) variations do not affect the total loading of the CL cell significantly. Note also that Rs variation due to Vctri does not affect the capacitive loading of the cell noticeably. If the Ms area is large such that CL « Cd(s) and ZdiS) dominates (i.e., Zd(s) « Rs), then the CL load variation due to Vctri variations is not 118 significant because: CL(con) = CLCCL(S)I{CL + Cd(S)) ~ CL In this case, the effect of Rs is significantly diminished, which means that the CL load vari ations for ON and OFF states of switch Ms are small. This is a disadvantage when larger CL load variations are required. Therefore, special attention must be paid to switch size in this design. Finally, style (c) occupies a small area for a given load. However, the target technology has to permit fabrication of floating capacitors. Fig. 5.1 l(dl) shows a design similar to the one in Fig. 5.11(d), with the difference that a NMOS gate capacitor is used instead of a parallel-plate capacitor. In the associated model, shown in Fig. 5.11(d2), Cg(L) = Cgs(L) + Cgd(L) and Cd = Csb(L) + Cdb(L) + Cdb(s) + Cdg(s)- The Tdij sensitivity to Vctri is only marginally greater than that of style (c). The style in Fig. 5.11(e) shows a good Sv*s, but requires more area to achieve the same delay as style (d). In the model for style (e) shown in Fig. 5.11(e2), Cd(L) = Cgs(L) + Cgd(L) and Cd = Cgb(L) + Cdb(s) + Cdg(s)- In the prototype implementation, described is Sec. 5.5, style (d) is chosen because it provides 10 ps delay in an area of a single-drive NOT gate and it exhibits low sldtl. vctrl 5.2.9 Resolution adjustment control block Using either 'uniform load' or 'incremental load' strategy before measuring iVA, it is re quired to check the assumption that TA > TB- A TATB checker circuit is used to perform this check. Two possible methods for designing the TATB checker circuit are outlined be low: 119 Vctri 2.5V 2.6V 2.7V 2.8 V 2.9V 3V 3.1V 3.2V 3.3V AT*, AVctr( (ps/V) S'v" Vctri (PS) (ps) (ps) (ps) (ps) (PS) (ps) (ps) (ps) al 24.3 25.9 27.4 28.9 30.2 31.5 32.8 34.0 35.2 13.5 1.3 a2 75.7 80.3 84.7 89.0 93.4 97.7 101.6 105.8 109.5 42.2 1.3 a3 154.6 162.9 170.9 179.8 187.9 195.9 203.7 211.2 218.7 80.2 1.2 a4 269.1 284.0 299.1 314.2 328.5 342.7 356.2 369.4 382.1 141.2 1.2 a5 423.8 447.5 471.5 495.0 518.2 540.4 561.1 581.8 601.8 222.6 1.2 a6 636.4 672.7 708.7 743.5 777.7 811.1 843.4 875.1 905.2 336.0 1.2 bl 57.4 61.6 65.89 70.2 74.3 78:4 82.4 86.5 90.2 40.9 1.5 b2 142.8 153.2 163.6 173.9 184.3 194.7 204.7 214.6 224.3 101.9 1.5 b3 250.2 268.8 287.3 306.1 324.6 342.9 361.0 378.9 396.4 182.8 1.5 b4 387.5 417.3 446.9 476.5 506.4 535.6 564.8 593.8 622.2 293.4 1.6 b5 555.0 598.3 642.3 686.2 730.1 773.9 817.1 859.9 902.5 434.4 1.3 b6 771.5 834.7 898.6 962.8 1020 1090 1150 1210 1280 636.7 1.64 cl 34.8 34.8 34.9 34.9 34.9 35.0 35.0 35.0 35.0 0.308 0.029 c2 121.1 121.3 121.4 121.5 121.6 121.7 121.9 121.9 122.1 1.23 0.033 c3 262.4 262.8 263.1 263.4 263.8 264.0 264.2 264.3 264.6 2.77 0.034 c4 484.0 484.9 485.7 486.4 486.9 487.5 488.0 488.4 488.9 6.09 0.041 c5 789.4 791.0 792.4 793.5 794.5 795.4 796.3 797.0 797.84 10.55 0.044 c6 1248 1251 1253 1255 1257 1259 1260 1262 1263 18.35 0.048 dl 9.44 9.47 9.43 9.44 9.45 9.39 9.44 9.55 9.49 0.063 0.022 d2 33.19 33.25 33.35 33.53 33.59 33.67 33.69 33.73 33.80 0.755 0.073 d3 73.19 73.40 73.62 73.95 74.19 74.33 74.37 74.59 74.62 1.78 0.078 d4 130.3 131.1 131.5 131.9 132.3 132.8 133.1 133.4 133.7 4.23 0.104 d5 210.6 211.7 212.5 213.2 213.9 214.6 215.2 215.7 216.3 7.1 0.108 d6 316.9 318.7 320.6 321.6 323.0 324.0 325.1 326.2 327.1 12.72 0.128 el 0.844 0.825 0.904 0.757 0.891 0.938 0.952 0.791 0.761 -0.104 -0.451 e2 3.33 3.27 3.30 3.26 3.35 3.16 3.47 3.19 3.31 -0.303 -0.302 e3 7.14 7.16 7.18 7.28 7.42 7.14 7.27 7.15 7.31 0.211 0.095 e4 15.72 15.83 15.68 15.73 15.71 15.73 15.75 15.82 15.77 0.594 0.124 e5 28.17 28.42 28.25 28.49 28.29 28.41 28.41 28.41 28.62 0.569 0.065 e6 49.38 49.47 49.56 49.40 49.46 49.47 49.56 49.53 49.48 0.123 0.008 Table 5.1: Tdif and Sv*frl for different styles of CL cells. Numbers 1 through 6 in the first column refer to the states a = 000001,000011, 000111,001111, 011111, 111111 in test bench circuit shown in Fig. 5.10, respectively. 120 1. The circuit in Fig. 5.12 can be used to check the condition that TA > TB- A zero time interval (Td = 0) is applied as input to the TQ. As the waveforms of TA and TB illustrate, when TA <TB, DFFJEOC samples LOW until the z-th rising edge of clkA matches that of clkB after ((D-1)TA +TC)/TA cycles of clkA. However, DFF JERRI samples a HIGH after Tc /TA cycles of clkA, i.e., DFF JERRI is set before DFFJEOC. If TA > TB, the reverse occurs, i.e., DFFJEOC is set before DFF JERRI. Therefore, the RA control block can check the condition TA < TB by monitoring the two flags EOC JLAG and ERR LFL AG. When the condition TA < TB is being checked, the reset lines of both EOC JDFF and ERR 1 JDFF must be inactive. The RA control block sets these reset lines HIGH through the OR gate. An important requirement for this circuit is ensuring that [((D — l)TA + Tc)/TA\ ^ [TC/TA J ([ J means integer part), otherwise the two flags are set in the same cycle of clkA resulting in a decision deadlock which causes failure in checking the condition TA> TB- However, such a requirement is easily met by a typical design under typical process variations. For example, in a circuit implementation in a 0.35 fim CMOS process, the minimum (D — \)TA is 1.5 ns, maximum Tc is 0.4 ns, and maximum TA is 0.15 ns. Therefore, in the worst case: and [Tc/TA\ = 2 Another design requirement is in regard to the first rising edges of clkA and clkB. Since setup and hold time for DFF JERRI and DFFJEOC could be different, DFF JERRI and DFFJEOC might be set HIGH simultaneously on the first or second edges of clkA 121 and clkB, respectively. Such a case results in decision deadlock. The circuit proposed next solves this issue but requires more hardware. 2. From the waveforms in Fig. 5.13, if TA < TB, CntrA will count faster than CntrB which causes the difference MA — MB to increase rather than decrease as time pro gresses. Assuming Td = 0, the difference between the two counters is initially 0 or 1. Therefore, MA — MB > 2 implies that TA < TB. This method requires more hardware than the first method, but its operation does not depend on the values of TA, Tc and TA or on the setup and hold times of the flip-flops as in previous circuit. Fig. 5.13 de picts the TATB checker circuit. The Cntr3A and Cntr3B are 3-bit counters initialized to 0 and 2, respectively. To save hardware, instead of Cntr3A, the three least signif icant bits of CntrA in RE block could be used. The 3-bit comparator 'cmp3', com pares the outputs of Cntr3A and Cntr3B, denoted by M3A and M3B, respectively. The same technique used in the RE block is used here for the reliable detection of the event MSA > MZB + 2. Detecting such an event implies that clkB has been slower than clkA (i.e., TB > TA). In order to use the time diversity technique, the clkAl and clkA2 signals from the RE block must be used. In addition, a Td such that TAI + T~A2 < Td < TB has to be applied to the TQ, where TA\ and TA2 are as defined in Sec. 5.2.5. The circuit in Fig. 5.14 is used to generate an appropriate Td. If M3A < MW, it is deduced that TB < TA and EOCFlag is set before ERR_Flag. If the 'uniform load' approach is used for selecting the CL loads, one hardware ef ficient method to search for a and b is the exhaustive search. In this method, the RA block is composed of a 2/-bit state machine, RA-SM. / bits of the state machine are connected to a0 ... and the other / bits to b0 ... o/_i. The RA-SM sequentially tests all the distinct 122 clkB clkA Counter Clk D Q EOC_DFF Clk rst EOC_Flag Clk rst RE_FLAG (from RE block) ERR1_Flag EOC_Flag CLK ERR1_Flag rst_ctrl Resolution Adjustment Controller i-l i-l To CL cells control inputs (a) N TA>TB ERR1 DFF is set clkA clkB I I I I Lflil • \ EOC_DFF is set TA< TB ERR1_DFF is set v —• \— (D-1) Tg clkA clkB EOC_DFF is set (b) Figure 5.12: Circuit for checking the necessary condition that TA > TB 123 To RA Block From CntrA (least 3 significant bits) or From Cntr3A Initilized at 2 clkB 3-bit counter (Cntr3B) rst Irb k-bit comparator cmp3_out clkA1 (From clkA2 (From RE block) D Q Ext. .DFF1 Clk rst <> Yrb D Q Ext. .DFF2 Clk rst EsampChkl ERR-Flag clkA2 Clk rst Irb EsampChk2 clkA clkA1 clkA2 CntrA (3 lowest bits) ClkB CntrChkB 3-bit CntrB (3 lowest bits). cmp3_out cmp_out ERR_Rag 1 j • 2 | 3j 4J 5| 6| 7 j 0J1J2J3J4J5J6J7J0J1 : 2 : 3 ! 4 RE_EOC clkB CntrChkB 3-bit CntrB (3 lowest bits) cmp_out ERR_Flag RE_EOC r*-xA2 , 4 | 5 j 2 j 3 cmp3_out Figure 5.13: Alternative circuit for checking the condition TA > TB 124 T '11 SysClk D Q ST _DFF Clk rst D Q ST. .DFF. Clk rst ST_check rst chck ST_edge SP_edge rst chck SysClk XA1 +1A2 < Td < TB rst_chck ST_check SP_check Tn D Q SP_ _DFF Clk rst SP_check rst chck ?ure 5.14: Circuit to generate TA1 + rA2 <Td<TB for TATB checker circuit 125 combinations of a and b: ae {0 ... 000,0... 001,0... Oil, 0 ... Ill,1... 1} be {0 ... 000,0 ... 001,0... Oil, 0 ... Ill,1... 1} The flowchart of the algorithm used to select a and b is given in Fig. 5.15(a). Note that distinct combinations for a are sequences with different number of' 1 's in them. Therefore, a = 110000 and a = 000011 result in the same TA because all the CL cells are the same. If all the distinct combinations are tried and the required resolution is not obtained, the circuit sets a failure flag RAERR_Flag. If the circuit has been designed to operate under typical process variations, setting this flag means that the BIST circuit is faulty. The exhaustive search approach, though more efficient in terms of hardware, can result in long resolution adjustment time. To reduce this time, a heuristic can be added to the algorithm as shown in the flowchart of Fig. 5.15(b). The main difference here from the exhaustive algorithm in Fig. 5.15(a) is that given the condition TA > TB, only combinations —> of 6 or a are tested, but not both. If the 'incremental step load' strategy is used, the search algorithms must be adjusted accordingly. The exhaustive test strategy now requires potentially testing all the combina tions of a and b: ae {0 ... 000, 0 ... 001,0 ... 010,0 ... 011,1... 1} be {0... 000,0... 001,0... 010,0... 011,..., 1...1} The flowchart of the algorithm is shown in Fig. 5.16. Again, the hardware implementation is simple because one 2/-bit counters can be used to generate b or a. However, the resolution adjustment time can be very long because a maximum of 22' combinations might have to be checked (in the worst case scenario). 126 (a) (b) Figure 5.15: Algorithms for selecting a and b in uniform load CL method, (a) exhaustive search, (b) directed search 127 Increment a Resolution adjustment^ failed. ) set RAERFLFlag J Figure 5.16: Exhaustive search algorithms for selecting a and b in the 'incremental step' CL cell method 128 3,., = 0...0 fcM ...b0 = 0...0 TA;Ti>No Increment b Yes Increment a No lYes Evaluate A/A •0 NA > "tn?*5 9 f Resolution adjustment^ ( completed. ) V Set ERA_Flag J Figure 5.17: Semi-exhaustive search algorithm for selecting a and b in the 'incremental step' CL cell method 129 aM = 0...0 bH ...b0 = 0...0 I i=0 1 = 0 Figure 5.18: Fast search algorithm for selecting a and b in the 'incremental step' CL cell method 130 A semi-exhaustive search will reduce the adjustment time with small modifications in hardware. The flowchart for this method is given in Fig. 5.17. The main difference with the exhaustive search is that either a or b is incremented during the search, but not both. The decision on which counter to be incremented depends on whether TA > TB or TA < TB. Therefore, the maximum number of combinations to be tested is 2'. A fast search algorithm is depicted in the flowchart in Fig. 5.18. In this algorithm, if TA < TB, only a is adjusted because TA must be increased until the difference between TA and TB satisfies the required resolution. Similarly, if TA > TB, only b is adjusted to increase TB so that the required TA is achieved. In this algorithm, since the two oscillators A and B are similar, there is a high probability that TA and TB are close. Therefore, the first choice is a = 0..0 and b = 0..0. If < Nih, the lowest significant bit of a or b (depending on whether TA < TB or TA > TB) is set high to increase TA or TB by the smallest amount possible. If the required resolution is still not achieved, the next bit of a or b is set HIGH and all other bits are set LOW. This is continued until setting the i-th bit HIGH implies that TA or TB has been increased too much. Then the i-th and (i — 1)-thbit are set LOW and HIGH, respectively, and the process starts over by setting the 0-th bit. To illustrate the algorithm, assume that TA > TB, I = 6 and the required resolution achieved for b = 001001. The algorithm goes through the following sequence to find the required b: 000000,000001, 000010,000100,001000,010000,001001 This is in contrast with the exhaustive and semi-exhaustive searches, which go through the following sequence: 000000,000001,000010,000011,000100,000101,000110,000111,001000,001001 131 As can be seen from above, the fast algorithm finds the solution in 7 steps, while the ex haustive and semi-exhaustive search require 10 steps. 5.2.10 TDC error sources From Eqn. 5.11, one of the maj or sources of measurement error is TR, which is due to differ ent noise sources in TQ (in Fig. 5.6). Also, the measurement accuracy (accuracy is formally defined in Sec. 5.2.11) is degraded due to the delay variations in the circuit of Fig. 5.8, caus ing random variation between the arrival of rising edges of INI and IN2, and START and STOP, respectively. In this section, we identify these noise sources and will show how the proposed TDC architecture can significantly reduce power supply noise effect on the rms value of TR. To identify different noise sources, we obtain the relationship between JV and the interval being measured by TDC, TD = tIN2 — £JJVI, as follows. In Fig. 5.8: t ST ART = tlNl + TST (5.17) tsTOP =tlN2 + Tsp (5.18) where TST = Tmuxl + rST(dk-to-Q) and TSP = Tmux2 + rSp(dk-to-Q) (TST(dk-to-Q) and Tsp(dk-to-Q) are the clk-to-Q delays of ST_DFF and SPJDFF, respectively, and rmuxi and Tmux2 are the delays from input 10 to out in MUX1 and MUX2, respectively). Substituting Eqns. 5.17 and 5.17 in Eqn. 5.10 yields: TD = N(TA - TB) - TEOC + TA - rB + rSp - TST (5.19) From Eqn. 5.19, Different sources of errors affecting TR include: 132 1. TSP and TST- the edge sampling flip-flops ST JDFF and SPJDFF, and multiplexers MUX1 andMUX2 2. TEOC- DFFJEOC flip-flop setup time and metastability window 3. TA,TB,TA and Tg: ring oscillators jitter The TST, TSP and TEOC can be expressed as: TST — TSTO + TST(e) TSP = TSpo + TSP(e) TEOC = TEOCO + TEoc{e) where T5ro» TSPO and TEOCO are the nominal values (under noise-free conditions) of TST, TSP and TEOC, respectively, and rST(e), TSp(e) and TEoc(e) are the jitter of ST JDFF, and SPJDFF clk-to-Q delays, and the EOC JDFF set-up time and metastability window, respectively. The delay and setup time jitters are due to different sources such as thermal noise and power sup ply noise. The metastability error, however, is due the inability of the DFFJEOC to decide its output state if the delay between the arrival time of the signals at the clk and D inputs are very close the setup time of the DFFJEOC. Therefore: TEOC(e) = TEOC(en) + TEOC(m) where TEoc(en) is the variation of EOC JDFF setup time due to noise source and TEoc(m) is the error induced by EOC JDFF metastability window. The characterization of EOC JDFF through simulation, reported in Appendix E, shows that this window is less than 0.01 ps. Therefore, for practical applications, this error is negligible in comparison with TDC res olution of about 10 ps. The TSTO, TSPO and TEOCO will be accounted for during calibration 133 because they only contribute to the offset Tc (refer to Sec. 5.2.6). However, TST(e), Tsp(e) and TEOc(e) cause loss of precision. The inaccuracy due to the above three sources is given by: TDFF(e) = TSP(e) ~ TST(e) + ^EOC(e) The inaccuracy caused by the jitter in ring oscillators A and B used in the TQ, is analyzed next. Jitters in ring oscillator A and B The outputs of both ring oscillators A and B, clkA and clkB signals, include some amount of jitter. In general, the rms jitter of a ring oscillator increases with the square-root of the number of gates in its oscillating loop [106]. When a rising edge passes through the i-th. gate of the loop, the output of the gate output switches after Tg^y. T9(i) = T9{i)0 +. T9(i)e where T3^Q is the average gate propagation delay and Tg^e is the random variation of this value due to different noise sources. The period at the output of the oscillator A can be expressed as: 2MA-1 TA = J2 T9(i) i=0 2MA-1 = (T9(i)0 + Tg(i)e) i=o (5.20) 2MA-1 2MA-1 = X] Tg(i)0 + ]L Tg(i)e 1 = 0 8 = 0 = TAO + TAe 134 where MA is the number of gates in the ring oscillator A, TA0 is the average period, and TAe is the period jitter of clkA: 2MA-\ TAe= E **)* (5-21) t'=0 Assuming r5(t)e's are independent, normally distributed random variables with standard de viation ug and mean of 0, the variance of TAe will be: <?Ae = \[2MAGa (5.22) Similarly, •j2M~Acjg where crBe is clkB's period jitter. In a measurement sample, the TDC stops after N cycles of clkA and clkB. If the noise sources are independent, the jitter in each cycle will be inde pendent from the jitter in any other cycle in either clkA or clkB. In such case, the effect of the jitter on Td is as follows: N-l Td = N(TA0 - TBO) + XI (TA(j)e - TB(j)e) + TQ 3=0 Therefore, the measurement error due to the jitter in the ring oscillators is: N-l Tm = Yl {TA(j)e - TB(j)e) (5.23) The variance of TR1 is obtained as: < = N(<rAe + *2Be) = 4NMAa2g (5.24) Eqn. 5.24 is valid when the noise sources in the gates are independent, such as ther mal noise. However, the noise sources due to power supply and substrate noise for each gate are not independent. These correlations are inherent to the structure of the TDC, making it 135 resistant to such noise sources. The analysis in Appendix H shows that when measuring a time interval Td, the inaccuracy of the TDC due to the V^-induced jitter in Oscillator A and B is: Eps = Td[K.VdMe\(t0,td) Vddte)(td,teoc)} (5.25) where t0 is the time at which START edge occurs; td = t0+Td; teoc is the time at which mea surement completes; K and 7 are two constants modeling the V^-induced gate delay jitter (see Appendix G.l); Vdd(e) is the power supply noise term; Vdd(e)(to, td) and Vdd(e){td, teoc) are the averages of Vdd(e) over the window [t0, td] and [td, teoc], respectively. Eqn. 5.25 indi cates that Eps is proportional to the time interval measured by TQ, Td. This was to be ex pected because the larger the interval Td, the greater the number of switching events in the oscillator loops. Eps is also proportional to the power supply noise averaged over a time window. Due to noise power reduction because of noise averaging and differential noise rejection, this circuit is capable of high-precision measurements. Sec. 5.6.2 shows that the rms value of Ep$ is approximately 5.5 ps under a typical conditions in a 0.35/zm CMOS implementation of the circuit. 5.2.11 Accuracy, Precision, and Resolution Accuracy, precision and resolution are three important characteristics of a measurement cir cuit or device. This section evaluates these characteristics for the TDC circuit. Definitions The formal definition of accuracy, precision and resolution are [107]: 136 1. Accuracy is the degree of exactness (closeness) of a measurement when compared to the expected (most probable) mean of the variable being measured. For example, if the value Y is measured for a variable with expected value of X, the measurement accuracy is: A = l-|^H = l-f (5-26) where e — X — Y is the absolute error. Since e is mathematically more convenient to calculate and is directly mapped to accuracy, throughout this document we calculate £ as a measure of accuracy. 2. Precision is the measurement sample deviation relative to measurement mean. There fore, * — I^I where Y is a sample measurement and Y is the the measurement mean if a large num ber of measurements are performed on the variable to be measured. Precision is, in fact, an indicator of the consistency of the measurements taken by an measurement device. We define precision error as: x] = Y - Y (5.27) Since r\ is mathematically more convenient to calculate and is directly mapped to pre cision, hereafter we will use r\ to analyze the precision of the TDC. 3. Resolution is defined as smallest change in a measured variable to which a measure ment device responds. Therefore, the resolution of the TDC circuit is TA. Using the above definitions, we can say that if a measurement is accurate it is also precise, but the reverse is not necessarily true. This is because some unknown variables 137 affect all the measurement the same way, e.g., measurement offset in the measurement de vice. These random reduce the accuracy but not the precision. To illustrate this, assume that a measurement device measures the value Y for a variable with expected value of X such that Y = X + e (5.28) where e is a random variable with a mean of m£ and a standard deviation of aE. Therefore, the rms error, erms, is elm. =E[e2} = E[{e-e + e)2} (5.29) = al + m2E where E[ ] represents the Expectation function [108]. From Eqns. 5.27 and 5.28 the precision error, n, for this example, is obtained as be low: V2rms = E[V2} = E[(X + e - (X+i))2] (5.30) = °l Comparing Eqn. 5.29 and Eqn. 5.30 shows r\lms < e2rms due to the ml, which can be inter preted as the offset error of the measurement device. TDC accuracy and precision We analyze the TDC accuracy, precision and resolution for two different measurement: ab solute and differential methods. In an absolute measurement of a time interval Td, the mea sured values by TDC are used directly, whereas in a differential method, the differences of 138 measurements from a reference measurement are analyzed. Consequently, the set of mean ingful quantities for the two methods are: Absolute: Ni.A^,... (5.31) Differential: Nx - Nre}, N2 - Nre} where Nrej is a number obtained for a reference measurement. In an absolute measurement of an time interval Td, the TDC measurement error is (from Eqn. 8D): eabs = NTAe + Tee + TQ + TR (5.32) The error terms TAe and Tce are due to calibration, but their values remain constant for all the measurement samples following calibration. In fact, TAe and Tce can be interpreted as offset error. Therefore, the TDC precision error is given as: riabs = TQ + TR (5.33) In the differential measurement method, the offset error can be eliminated through subtraction. Assume Na and Nb correspond to the measurement of two time interval sample Ta and Tb, respectively. Therefore: Tab = (Na - Nb)TA + TQa - TQb + TRa - TRb (5.34) where Tab is the measured difference between Ta and Tb. Therefore, in differential measure ment, the error, Sdi//, and precision error, rjdi/j, are given as: edi/f = {Na - Nb)TAe + TQa - TQb + TRa - TRb (5.35) Vdijj = TQa - TQt, + TRa - TRb (5.36) 139 If Tee variations are significant compared to that of other error sources, from Eqns. 5.32, 5.33, 5.35, and 5.36, it can be concluded that in differential measurement mode, the error decreases (accuracy improves) because the constant Tc term disappears, but the precision error increases (precision degrades) due to accumulating effects of additional independent random variables. Using a two-point calibration scheme to calibrate the TDC, the improved accuracy in differential measurement over absolute measurement significantly outweighs the reduced precision. To illustrate this claim, consider an example in which two sample time intervals Ta and Tb, the TDC generates two numbers iVa and Nb. Assume that Na « Ncai2 — Ncan and Nb « Ncai2 — Ncan. Using the variances of TAe and Tce obtained in Sec. D.l, the (5.37) (5.38) rms error in the absolute and differential measurement modes are: jy2 rp2 rp2 (eaHrms))2 = {N^2 JVcail)2(f + 24) + if + 5a« + (if + 4) -6(§ + ^) (<? \1 — (Nb — Ng)2 TA n_2\ , o/^A , _2 \ -2(| + 4) The rms precision error in absolute and differential measurement modes are: j>2 (Vabs(rms))2 = yj- + o\ (5.39) (ridtff(rms))2 = 2(^ + a2R) (5.40) Comparison of Eqns. 5.37 and 5.38 show that using the differential measurement method decreases rms error, while Eqns. 5.39 and 5.40 indicate that this method increases the rms precision error. 140 5.3 Jitter Generator For the jitter tolerance and jitter transfer test of CRUs, it is necessary to supply the CRU with a signal which has a known jitter. Here, a circuit is proposed which is capable of generating a controlled jittered signal out of a jitter-free clock signal. The circuit is shown in Fig. 5.19. The circuit is composed of a delay line, a multiplexer, and a sequence counter. Different taps of the delay line are multiplexed to the output J. The counter specifies which tap is multiplexed to the output at any clock edge. For example, with 8 taps and a 3-bit up/down counter, it is possible to generate a triangular shaped jitter signal with the maximum peak-to-peak amplitude of 8rg, where rg is the delay of each delay element in the delay line. Using a counter with a count sequence which follows a sinusoidal pattern, the circuit will generate a signal with sinusoidal jitter. By designing a programmable counter, the circuit can generate different jitter signals according to the stored program in the counter. Such counters can be implemented as general state-machines. Delay elements (DE) J (Jittered clock) Figure 5.19: Jitter generator circuit 141 5.4 Schemes for On-Chip Jitter Specification Testing 5.4.1 Cycle-to-cycle jitter measurement Cycle-to-cycle or period jitter is defined as variations in the period of a signal. A histogram approach can provide statistics of such jitter. Using this approach, to measure period jitter, two consecutive rising (or falling) edges of the signal K„ are passed to the time measure ment circuit as START and STOP signals by a control circuit (Fig. 5.20). After this is com pleted, the control circuit reads the N stored in the TQ counter and sends it to an external tester (possibly through a JTAG controller if it exists on the chip) or to an on-chip processing unit [ 109] for post-analysis. Concurrently, the test controller can pass two other consecutive edges of Vin to the TDC. This procedure can be repeated until a predetermined number of samples of the Vin periods are measured. Subsequently, the external tester (or on-chip pro cessor) can form a histogram of the data and calculate the variance and peak-to-peak jitter. The tester does not have to be a high-speed or high-performance mixed-signal type because the data is digital and can be sent off-chip using a low-speed serial bus. If the information about the times at which the jitter samples are taken is supplied to the tester along with the jitter sample measurements, frequency components of the jitter can also be analyzed. This feature enables the JMC to perform full jitter standard compliance tests, if required. However, this feature is not fully detailed in this thesis. 5.4.2 Relative jitter measurement In some applications such as serial communications, it is important to ensure that the rela tive displacement of corresponding edges of two signals, for example, INI and IN2, meets a 142 IN1 D Q DFF1 Clk rst START D Q DFF2 Clk rst STOP CLK START TDC STOP CLK EOC ~i_r Ready for measuring yf, next period sample ! Next_sample Digital Controller CLK N Figure 5.20: Cycle-to-cycle jitter measurement given specification. Here, without loss of generality, we assume that the specification sheet requires that the corresponding edges of the signals INI and IN2 occur within a tight time window (e.g., 0.001UI, where UI is the unit interval or period duration). Based on this as sumption, we propose the circuit in Fig. 5.21 to measure the relative jitter between the edges of INI and IN2. In this circuit, DFFi samples an edge of INI and, DFF2 samples the edge of IN2 closest to the sampled INI edge. The delay element D2 ensures that the setup&hold time of DFFi, i-e., TS&HI , is met so that the DFFI output is set before an IN2 edge arrives. This condition is satisfied if tlN2 > tlNl — T~D2 + Tql + T. s2 where TD2 is the delay of the D2 delay element, tIN1 and tIN2 are the time instants at which the sampled edges of INI and IN2 occur, rql is the CLK-to-Q delay of DFFI, and rs2 is 143 the setup time of DFF2. Fig. 5.21(b) shows the timing diagram of the circuit for one pos itive and one negative value of Tj = tiNi — tIN2. The generated START and STOP sig nals are passed to the TDC to measure the time displacement. After the completion of a measurement, DFFi and DFF2 are reset and are ready for the next sample. Note that the sample&hold time of the flip-flops DFFX, DFF2 affect the actual time displacement being measured, since the measured Td is Td = Tj + TD2 + Tq2 — Tqi where Tj — tiN2 — tmi is actual time displacement between IN2 and INI edges. But since TD2, TQ2 and r?1 are constant, they can be accounted for through calibration. In such a measurement scheme, the meaningful data is the variation of measurement values from one sample to the next. Jitter statistics can be obtained from a sufficient number of sample measurements. In the scheme described, the measurement range is limitedto approximately — Tm + Tqi + Ts2 < Tj < TTDC ~ TD2 + Tqi + Ts2 where TTDC is the maximum measurement range of the TDC. rm cannot be more than 0.5UI, otherwise the displacement on the INI edge and a non-adjacent edge of IN2 will be measured. This, however, is generally not a limitation for test purposes because the accept able edge displacement variations is usually a small fraction of unit interval (e.g., 0.1UI). The relative jitter measurement scheme can also be used to perform a jitter tolerance limit test on clock recovery units (CRUs). For a jitter tolerance test, a signal with known jitter is applied to the CRU. The TDC measures the relative jitter between the input clock and the recovered clock. This relative jitter cannot exceed a certain threshold for jitter signals 144 START "1" IN1 D Q DFF1 Clk rst IN2D D Q DFF2 Clk rst • D2 • IN2-! H : ( TD2 ': i. ..... .1 STOP START TDC STOP EOC IS Ready for measuring ^ next period sample ! Next_sample Digital Controller N (a) IN1 IN2 START IN2D STOP 1s2 'TD2 -1q2 '1 ts2 1 V */W2 Figure 5.21: Relative jitter measurement 145 specified in standards such as [20]. The excessive relative jitter indicates the inability of the CRU to meet its rated bit-error-rate. For production test purposes, we suggest testing the jitter tolerance at two different frequency/amplitude points: one frequency inside the loop bandwidth of the CRU and one frequency point outside it. For each case maximum amplitude given in standards should be selected. Performing tolerance tests at more points is also possible but requires more test time. 5.5 Implementation The jitter measurement circuit proposed in Sec. 5.4.1 has been designed and imple mented using a 0.35^ CMOS technology. The CL cells have been designed as standard cells to allow for automatic place and route. The uniform CL cell style has been used for imple menting the resolution adjustment circuits. The rest of the cells used in the implementation have been taken from a standard digital cell library. The top block level schematic of the jitter measurement circuit is shown in Fig. 5.22. It contains the following blocks: 1. TQ: Time Quantizer 2. RE_TATB: Range extender and TA > TB condition checker 3. Main Counter and the DivBy2 circuit 4. REEOC_sync_DFF,TQEOCjsyncDFFandERRl_sync_DFF:REJ30C,TQJEOC and ERRl.flag synchronizer flip-flops 146 TATB Check Delay Gen: Generates a small time delay for checking TA > TB Delay Generator: Controls the selection of the delays needed for resolution adjust ments, calibration and measurement. The implementation details of each part of the circuit follows. CL cells A total of six different CL cells have been designed using style (d) in Fig. 5.11. The transistor sizes for each of these cells are given in Table 1. In the forth row of this table, the additional delay in the oscillator A or B loops obtained by activating the cell is listed. Such a selection of CL cells allows for ±288 ps or ±8.5% period mismatch between clkA and clkB (this is obtained when all the cells are activated). The last row lists the area of each cell. The height of all the cells is the same as standard cell library height. The area of the smallest cell is equivalent to the area of a double-drive 2-input NAND gate. CL0 CL2 CL3 CL4 cu Ms [w(fj,m) 1'l(pm)) 4/0.35 4/0.35 4/0.35 4/0.35 4/0.35 4/0.35 ML [w(fim) 1'l(jim)} 3/0.5 6/0.5 9/0.5 13.5/0.5 18/0.5 27/0.5 Delay (ps) 11 23 35 50 67 101 Area (width(^m) x height(^m)) 6.3x21 7.9x21 9.4x21 9.4x21 11x21 14x21 Table 5.2: Specifications of the implemented CL cells 2. Time Quantizer (TQ) Oscillators A and B in the TQ block consists of 11 NAND gates and one AND gate. 147 Six taps for each oscillator are connected to six different CL cells. The outputs of oscillators A and B are directly connected to the clk and D inputs of DFF_EOC. These outputs are buffered before being used in other control blocks which are less time sensitive. The output of DFF_EOC is sampled and held by another flip-flop to ensure that the end-of-conversion signal, EOC_Flag, can be observed by the control blocks operating with the system clock. In addition to Start and Stop inputs, two other inputs have been reserved for applying StartCheck and StopCheck signals to oscillators A and B, respectively (see Fig. 5.23). These inputs are used to apply a Tj. (as defined in Sec. 5.2.9) for the purpose of check ing the condition TA > TB- Without these inputs, an additional multiplexer would be required. However, when Start and Stop are applied to the TQ StartCheck and StopCheck signals must be inactive (HIGH), and vice versa. The main controller block ensures this condition using four control signals: MainSet, rbMain, CheckSet, and rbCheck. The flip-flop TQEOC_sync_DFF has been used to synchronize the TQJEOC signal with the system clock, SCLK, in order to avoid sampling erros by the Main_Controller block. 3. RE_TATB: The implementation of this block closely follows the structure shown in Fig. 5.7(a) and 5.13(a) with A; = 6,rAi = 1.2ns and TAX = 0.4ns. The flip-flop REEOC_sync_DFF synchronizes the RE_EOC signal with the system clock, SCLK. This prevents errors in sampling by the Main Controller block. The buffers Buf 1 to Buf6 are not needed in the actual implementation, but are neces sary to perform mixed-signal simulations. Without these, during simulation the sig-148 nals REJEOC1 and ERRl.flagl will become 'unknown' due to intentional setup & hold violations in the internal flip-flops of the RE_TATB block. The propagation of the unknown states prohibits meaningful simulations. To overcome this problem, Bufl, Buf3, Buf4 and Buf6 are simulated as digital cells, and Buf2 and Buf5 are simulated as analog cells. This arrangement, effectively, translates the RE_EOCl and ERRl_flagl signals from the digital domain to the analog one and then back to digital. Since the 'unknown' digital state at the input of the analog block is interpreted as a voltage of OV, an 'unknown' digital state does not propagate to the rest of the circuits. 4. Main Counter and DivBy2 circuit: A 16-bit counter is used to count the number N. As shown in Fig. 5.6, clkA should drive the counter's clock input. However, the maximum operational frequency of the 16-bit counter is 250 MHz, whereas fc\]^ = 350 MHz. The divider circuit divides frf^A by two enabling the counter to count the number of clkA edges. The state of the DivBy2 circuit recovers the lost bit due to division as follows: N = 2Ncntrl6 - clkDiv2 where Ncntrl6 is the state of the 16-bit counter and clkDiv2 is the state of the DivBy2 DFF. 5. Delay Generator: This block generates Start and Stop edges with tstop — tstart = Trej,2Tref and (tIN2 - tIN1) for [SelDl, SelD0]=[01], [10], and [11], respectively. When [SelDl, SelD0]=[00], both Start and Stop are set HIGH and the StartCheck and StopCheck signals are activated to check for the condition TA > Tg. 6. TATB Check Delay Generator: This block generates a delay of 1.8 nsec between 149 the StartCheck and StopCheck edges in the TA > TB check mode. The outputs of this block are set HIGH in other modes. 7. Main Controller: This controller monitors the outputs of all other blocks and gen erates required signals for controlling the operation of the TDC. The TDC operation starts by loading a threshold Nthre serially. The serial data is read through SThre input while TestStart is HIGH. Then, the controller controls the Delay Genrator while the TATB Check Delay Generator block performs resolution adjustment. After adjust ment, calibration is performed and the TDC switches to measurement mode. In this mode, the Main Controller instructs the Delay Generator block to pass jitter samples to the TQ. Upon completion of each measurement, the data is sent off-chip serially through DataOut output. The InputReady, MeasReady, and DataReady signals are used for handshaking between the external tester and TDC. 5.6 Simulation Results 5.6.1 Jitter measurement circuit All the individual blocks in the JMC as well as the complete circuit were simulated under a variety of conditions to verify their functionality and performance. The TQ, Edge Sampler, RE, and RA blocks were verified through analog simulation because of timing and loading sensitivity. The controller and counter blocks were simulated as digital blocks. The Spectre and Verilog simulators were used for analog and digital simulations. The complete circuit were simulated using SpectreSVerilog mixed-signal simula tor. For this simulation, the TQ block is considered as an analog block while the rest of 150 the circuits are treated as digital cells. Analog high-level description language (ahdl) code was written to perform measurements during simulations and to emulate the external tester which handshakes with the JMC. To test the full capability of the circuit, oscillator A was loaded with an additional capacitive load to model a mismatch of 35 ps between TA and Tg. In addition, Trej = 6 ns and Nth — 272. Therefore, the required resolution is Tth = Trej/Nth = 22ps. The waveforms in Fig. 5.24 show how TDC successfully adjusts its resolution by controlling the Bc[0 : 5] = b tabs to achieve a resolution better than Tth- In this case a resolution of approximately 11 ps is achieved. The resolution adjustment took approximately 16.4 (is. The result of the last step in the resolution adjustment is also used for calibration. The rippling seen on waveforms TU and Tg in Fig. 5.24 represents simulation arti facts caused by numerical coupling of the two oscillators A and B in the simulator. Tight ening the accuracy parameters of the simulator mitigates the ripples, but increases the sim ulation time significantly. A resolution of 34.1 ps was achieved in a separate simulation. In this case, a number of time intervals from Td = 1 ns to 11 ns with a step of 200 ps were measured. Fig. 5.25 shows the difference between the simulated measured intervals and the expected values. The measurement rms error is 12.1 ps, which matches the rms quantization error estimated in Eqn. 5.40. 5.6.2 Accuracy estimation In this section, the accuracy of the TDC is estimated assuming a typical condition on the chip based on the analysis in Sees. 5.2.10 and 5.2.6. These calculations assume that 151 1. power supply noise (Vdd(e)) is a high-frequency signal with a lower bandwidth of 50 MHz and rms value of 50mV; 2. the thermal noise jitter for a NAND gate delay is approximately 25 fsec [106] (ag = 25 fsec); 3. the thermal noise jitter in a flip-flop delay is negligible compared to its Vdd-induced noise; 4. the resolution (TA) is 10 ps; 5. Td = l ns; 6. the constant offset Tc = 0. To estimate the V^-induced noise, a number of sinusoidal noise components, Vdd(e) with frequencies between 50MHz and 2GHz and eight phases between 0 and 2VT have been selected and the resulting jitter in ring oscillators and flip-flops are simulated for each se lection. The rms value of each jitter term is estimated by obtaining the rms value of the simulated jitters of that term for all the selections of Vdd(e)-Based on the above assumptions, different jitter terms in Sec. 5.2.10 are estimated as follows: 1. TsT(e) and TSp(e)'- The rms value of the sampling flip-flop clk-to-Q jitter is: °ST{e) = <TSP(e) = (5.41) 2. TEOc(e)'- The rms value of the DFFJEOC flip-flop is: VEOc(e) = l.Sps (5.42) 152 3. Oscillators A and B: From Eqn. 5.24, for M = 12, N = Td/TA = 100, and ag = 25 fsec, the rms error due to thermal noise is am = 1.73 ps Eqn. 5.25 is used to evaluate V^-induced jitter term. The required n and 7 values are extracted from Table G. 1. aPS = 5.5 ps (5.43) Assuming different jitter terms are independent, the resulting inaccuracy is: VR = \j<yEOC + aST + aSP + aPS + °R1 = 7'3PS Therefore, total rms error in differential measurement mode is: ad = ^2*aR + Tl/Q = lips 5.7 Conclusions We have developed a high-resolution jitter measurement circuit and jitter generator block. All the circuits are digital and fit well in a digital ASIC design flow. The total area of the circuits in a 0.35^m technology is 450//m x 500/im, which is equivalent to 1200 double-drive 2-input NAND gates. The Main Controller was written as synthesizable VHDL code and the rest of the circuits were described at the schematic level. Automatic place & route were performed for all the circuits. Exhaustive simulations and analysis show that the jitter measurement circuit is capable of jitter measurement with resolution and accuracy in the order of 10 ps. 153 The digital and compact nature of this TDC circuit makes it very attractive for BIST applications for testing high-speed serial communication interfaces, e.g., clock and data re covery, timing circuits, and edge placement circuits. Since the TDC provides a very high-resolution time measurement capability, it is also suitable for use in design of all digital clock recovery and clock synthesis circuits. 154 Figure 5.22: Top block-level schematic of the jitter measurement circuit 155 Figure 5.23: Implemented TQ circuit 156 Bc2 i-Bc1 I BcO I 3.670n 3.660n 3.650n 3.640n ,-. 3.630n o a> 3.620n D-3.610n 3.600n 3.580n 34 ps TA>TB^ Checking •B 3.0u 2Tref measurement 11 ps 25 ps | f^^^wN^^Av^A^ WJV^vM 7.0u 9.0u 11 u Time (s) Tref ! measurement 13u 15u 17u Figure 5.24: TDC resolution adjustment simulation waveforms 157 Figure 5.25: TDC measurement error for resolution of 34.1 ps 158 Chapter 6 Summary and Conclusions The IC industry is undergoing a constant evolution. This has major implications on test. Notably, two important requirements emerge. These are 1. the requirement for block re-use; and, 2. the need for cost-effective high-performance test capability. From the above, embedded test provides an attractive solution approach provided certain features are achieved. Such features include 1. compactness: i.e., small area comparing to the circuit under test (CUT); 2. design simplicity and robustness: i.e., resistant to process variations, temperature and power supply variations; 3. digital output generation: i.e., generate one or more digital signatures which can be sent off-chip at relatively low speed, e.g., serially; 4. accuracy: measurement accuracy must be sufficient for the test; 159 5. calibration: i.e., calibration-free, self-calibrating, or use signal readily available sig nals to the chip for calibration; 6. performance impact: i.e., the impact on the CUT performance must be minimal. Meeting all the requirement above is a challenging task especially for functional BIST or embedded test of high-performance high-speed circuits which require high resolution and high accuracy. At the outset of this research only a few solutions with limited applicability were known to exist. In this research, two different embedded test methodologies for mixed-signal circuits were developed: (i) on-chip power supply current (IDD) monitoring, and, (ii) on-chip jitter testing. One important demonstration of this research is that designing feasible embedded test methods for testing high performance mixed-signal circuits is pos sible. This demonstration counters the often widely-held opinion to the contrary. A reason for such capability is that often the test circuits are not required to test the full functionality of the CUT, thereby relaxing the requirements of the test circuits. In regards to current monitoring, the main challenges in devising an effective on-chip IDD test scheme is designing a built-in current monitor (BICM) that has minimal impact on the analog CUT performance while maintaining a good measurement sensitivity, and also generates an on-chip signature in a relatively small silicon area. We met this challenge by designing a novel BICM structure. The BICM has two major pars: a current mirror-based built-in current sensor (BICS) and a single-phase built-in current integrator (BICI). The BICS structure had been reported previously but the novel, thorough performance anal ysis and actual chip fabrication and characterization were performed. Results confirm that the BICS impedance can be decreased to acceptable levels (~ 3fl) while providing a high 160 sensitivity and accuracy by using only a single-stage feedback amplifier. Also, we found that in submicron CMOS technologies, even small routing resistances can cause significant error in current mirror operation. Our investigation shows that a 2% accuracy is achievable if special attention is paid in routing the current mirror connections. Moreover, the specific BICS impedance has a bandwidth of 5 MHz and the current mirror bandwidth of 120 MHz. These are sufficient characteristics for many practical purposes. The BICS is a relatively simple design that requires matching only two transistors in a current mirror. With respect to the BICI, we designed a new integrator structure to meet the chal lenge of reducing the size of an integrator circuit with a long time constant. This structure employs a novel technique of breaking the long time constants in analog domain to shorter ones and transforming the remainder of the operations to digital domain. This results in a drastic saving in silicon area while providing the additional benefit of yielding a digital sig nature at the end. The implementation of this structure is simple because it contains only switches, capacitors, a comparator, and a small digital circuit. Also, a two-point calibration makes the circuit robust against process variations, temperature, and power supply varia tions. However, an off-chip or on-chip current source is needed for this calibration. The specific implementation of BICI yields an accuracy of 2% if the IDD is not correlated with the integration control signal. The BICM can be used to test different analog blocks where IDD contains AC components. Typically, this test is not conclusive but it can reduce test cost by weeding out many faulty devices earlier in the test. The novel technique of 'quantization residue feed forward' was invented to achieve more integration accuracy for arbitrary IDD waveforms. In this technique, instead of dis carding quantization residues at each digitization cycle, they are stored and used in sub-161 sequent cycles. Employing this technique in combination with using two complementary integrators in parallel led to the design of a double-phase BICI. This structure is about 20% larger than the single-phase BICI, but it is accurate to within 1 % regardless of the IDD wave form. This BICI extends the use of BICM for IDD testing to a larger number of analog circuits in comparison with single-phase BICI because of its higher accuracy which is in dependent of IDD waveform. In regards to jitter testing, our novel approach is the first circuit which can perform single-shot jitter measurement with accuracy and resolution in 10 ps range, while satisfying all the requirements for a practical embedded test scheme. Prior to this research, there has been no such circuit reported in open literature. The circuit is composed of two parts: a jitter generator and a jitter measurement block. The jitter generator occupies an area equivalent to 200 2-input NAND gates. It ac cepts a jitter-free signal and digitally modulates it to generate an output signal with con trolled jitter. The amplitude and frequency of the jitter signal are programmable. The jitter measurement circuit (JMC) uses a differential ring-oscillator technique to achieve high-resolution. The resolution of this circuit is programmable; the minimum guar anteed resolution depends on process variations. A very important side product of the dif ferential nature of the circuit is robustness against power supply noise which result in a sig nificant accuracy improvement. Since parts of the circuit are asynchronous, a new tech nique, time-diversity sampling, was developed to ensure valid sampling and correct oper ation. JMC calibration is practical and simple because the same signal which is used for clock synthesis is also used for calibration purpose. 162 A JMC prototype has been designed in a standard 0.35 pom CMOS technology. Sim ulation and analysis predict a measurement accuracy of about 11 ps rms and a a resolution of 10 ps for this implementation. The total area of the circuit is equivalent to approximately 1200 2-input NAND gates; less than 10% of this area is occupied by time-sensitive circuitry. The time-to-digital (TDC) circuit at the core of JMC, can measure 1 ns time interval in about 400 ns. Therefore, the approximate test time for measuring 1000 jitter samples on a 155.54 MHz PLL (OC-3 Sonet standard) including resolution and calibration time is about 0.5 ms. This number of samples is sufficient for histogram-based testing. The predicated resolution and accuracy of the JMC is sufficient for testing SONET OC-3 (155 MHz) and even OC-12 (622 MHz) signals because the measurement resolution required for testing these signals are approximately 64 ps and 16 ps, respectively. Because of the single-shot measurement capability of the the JMC, it can be used to analyze the jitter frequency components, thereby, enabling frequency-dependent jitter standard compliance test. This is an important additional advantage over previously reported JMC's. 6.1 Future Research This research demonstrated the feasibility of designing high performance and robust embed ded test circuits. More embedded test circuits are needed for testing future high-performance mixed-signal circuits such as high-speed ADCs, DACs, and analog equalizers. Calibration is a very important aspect of any measurement circuit. The BICM and BICI in this work require accurate current sources for calibration. Some ICs may have such sources available on the chip. However, for the more general cases, new self-calibration techniques will be required, or calibration should use typically accurately-controlled power 163 supply voltage and/or clock signals. The 11 ps (rms) precision in the jitter test circuit is sufficient for testing 155.54 MHz and possibly 622.2 MHz clock recovery and synthesis circuits. However, new techniques capable of reducing the noise in the jitter measurement circuit would have to be devised to extend the ability of this circuit for testing 1.2 GHz circuits and beyond. Some proposals in clude using faster ring oscillators, using clean (low jitter) clock signals in measurement and not just in calibration, and extending the differential structure to other parts of the circuits. Also, the use of CL cells requires the ability to add cells to digital cell libraries. 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Test Conf, pp. 805-814, 1993. 177 Appendix A BICS Frequency Response Analysis This appendix shows how the symbolic toolbox of MATLAB [99] has been used to deter mine the frequency response of the BICS circuit in Fig. 3.3. First, the following steps are performed: 1. The nodal equations of the circuit ac model are written in terms of resistances, transcon-ductances and'Capacitances. 2. The nodal equations are solved to obtain 7 , , VBIC(S) NBIC(S) ZBIC{S) = JDM = BSMS) where NBIC(S) and DBIC(S) are the numerator and denominator of the ZBIC(S), re spectively. 3. In NBW(S) = a0 + axs + ... + a3s3 and DBic{s) = bQ + bxs + ... + b4s4, each of coefficients a,-, i = 1,..., 3, and bj, j = 1,..., 3, is expressed as a sum of products: Li i=\ 178 1=1 where Li, Kj are the number of product terms in aiy bj, respectively, and, PDu, PN3i are the /-th product term in ai,bj, respectively. The second column in Table A.l re ports the number of product terms in each of the coefficients (Z/8s and KJS). 4. For each a, and bj, the magnitude of some product terms is negligible compared to that of others. To identify such terms, the operating point values of various resis tances, transconductances and capacitances in the circuit's ac model are substituted in the expressions for each product term. These operating point values are obtained by circuit simulation. For the circuit in Fig. 3.3, the Spectre [101] simulator and BSIM3 MOS models were used. 5. For the coefficient a,-, i = 0,1,2, 3, and bj, j = 0,1,2,3,4, only the significant prod uct terms with a magnitude greater than 1/10 of the maximum of all the terms are kept while the rest of the terms are assumed negligible, and consequently eliminated, i.e.,: if PDu<PDimaJ10 then PDu = 0 where PDimax = max(PDtl, PDi2,...). The number of retained terms in each co efficient is given in the third column of Table A. 1. The general forms of the resulting product terms for coefficients ai and bj are given in the fourth column of Table A. 1, where the i, j, k and / subscripts indicate the indices of different transconductances, resistances and capacitances. Initially, we assume that NBic{s) has a root, s = Zd, at which a3s3 and a2s2 are negligible in comparison with a0: Therefore: zd = a0/a1 = l/{r13Ct) 179 Coefficient Total # of # of significant General form of product terms product terms significant product terms a0 10 2 QmiQmj 1 ^dl ax 45 2 C1 iQmiQmj a-2 59 8 CiCjQmi as 22 8 Ci Cj Cl b0 13 1 QmiQmj QmlQmk 107 5 Qmi Qmj Qm I Ck b2 243 2 QmiQmj CiCk bs 208 8 Qmi Cj Cl Ck b4 59 8 Ci Cj Cl Ck Table A.1: Number of product terms in the coefficients of NBIC{S) and DBic{s) where r13 = rx | jr3 and Ct = Ccomp + Cgs\2-Now we verify that a3s3 and a2s2 are indeed much smaller than a0 by showing that a3s3/a0 <C 0 and a2s2/a0 -C 0. To do so, note that the C;'s, C/s and GVs are in the range of O.lpF to 0.55pF, r13 and rt-'s in the range of 0.7 Mfl to 1.3 MQ, and gmis between 10_4/O and 1.3 x 10_4/fi. Hence, the ratio of a3s3 and a2s2 to a0 at s = z<i evaluate to: 3/ (C;C,-C,)/(r?,C?) 1 gm,gmi/ri gmi9mir'(3 9mi9mi / ri ~ IO"4 IO"2 (IA) ' gmigmi/ri gmiri3 The above approximation verifies the assumptions used to calculate s = zd. Numerical solutions of NBIC(S) = 0 and DBIC(S) = 0 show that the rest of the poles and zeros of the circuit are located at frequencies at least 10 times higher than zd. Therefore, zd, rewritten below, is considered a dominant zero: zd = -I I {Ccomp + Cgsl2)(rdl\\rd3) (2A) 180 Appendix B N and I Relationship in the Single-Phase BICI This appendix contains the derivation of Eqn. 3.16: N =KT7+0 + E (IB) In the circuit shown in Fig. 3.6, the counter is incremented by the value Ni at the end of the integration sub-window chi+1. Ni corresponds to the number of clock (CLK) cycles that span the time takes for Vs to ramp from 0 to V (voltage stored on C4). Since the ramp slope is Kr = Iramp/Ci, the counter is enabled for a time Td during the (i + l)-th period of 0: TC<=hT where r is the delay between the time Vs = Vi and the time counter stops counting, r is due to the comparator delay and input offset voltage, and the propagation delay from node 181 rl to ijrst. Therefore, A7,- can be obtained from Eqn. 2B. N = ^-Q, lCLK (2B) = Vi + Qi jy rp 1 ' rp ^1 J^rJ-CLK J-CLK . where TCLK is the period of CLK, and Qi is the quantization noise. Assuming that the / and CLK signals are uncorrelated, Qi can be considered as a random number uniformly distributed in the range (0,1) with a mean and variance given by: mQi =0.5 (3B) Since N = E^o1 Nif from (2B), M-I x N = E(7^ Vi + - Qi) (5B) i=0 Ar J-CLK J-CLK M-l = i^v— E (V) + T^1- - Q (6B) l\rJCLK i=0 JCLK where Q = Ylfio1 Qi- Since the Qi's are independent and M is generally large, from the central limit theorem Q has a Gaussian distribution with a mean and variance given by: mQ =0.5M (7B) a\ = ff (8BTo complete the derivation, VM = E^o1 Vi is obtained from Eqns. 3.15 and 3.14: M-l vM = £ Vi i=0 M-l M-I , (9B) = K* E (T^TTT j Idt + KiiV^] t=0 Ul "r l-/2 Jt< M-l J. M-1 = 7^~7T E / ' Idt + K23K21 J2 Vi <^1 + ^2 ,;=n Jti 182 Replacing V and Vc from Eqns. 3.15 and 3.14 recursively in Eqn. 9B yields: jy- M-l VM = E [1 + (#23^21) + (K23K21)2 + ... + (K23K21)M-1-1} / ' Idt ui + °2 i=0 Jn K23 - (K23K21)M-\ r< ^( iff U Mt i=o 1 - A23A21 Jn + C2 i=0 (10B) Generally, C, » C2, therefore, Ar23iir21 < 1 and [1 - (A'23/<2i)M-J] = 1 for i = 0, M - 2. Hence, Eqn. 10B simplifies to: M-i t; VM (c1+c2)(i3-Ml)[s</,'**>-K*K* 11:^ (IIB) where the term K23K2X ft™_l Idt is the effect of the residual remained on C2 at the begin ning of M-th integration sub-window. This term can be ignored because (i) (K23K21) <C 1 and (ii) the term Ji^J1 Idt is the result of integration in only one integration sub-window, whereas, TJ^LQ 1 (/t/ /<i£) is the integration result over a large number of sub-windows. This yields: VM = KM £ 'idt (12B) t'=0 Jt' where A"M = (c1+c2)a-A-23A-21) • Substituting U = iTs and = (* + 1)T, - TR into Eqn. 12B yields: VM =KMY( Idt - / Idt) = KM f Idt - KMR Jo where R = J2iio1 I(!+I)T!-TR The reset error, /?, results from not integrating 7 for a time TR in each sub-window. This is required to reset the circuit for integration in the subsequent sub-window. Denoting each term in J? as i?t, then: r-(i+l)Xs r(i+l)ls Ri = / Idt (14B) 183 TR can be such that TR/TS -C 1. Assuming 1/TR is much larger than the bandwidth of I, I can be considered as approximately constant during the time TR. Therefore, we can express Ri as: Ri = I(t")TR where t" = iTs — TR/2. Since the time t" is set by <j> which is independent of I, I(t") can be considered as a random variable. Assuming t" is uniformly distributed over one period of I, the mean and variance of Ri are given by: mRl •= TR^ fT' I(t)dt = 1TR II Jo <t=TR[~J^\l{t)-l)dtf = lJcTl where Tj is the period of I and J2C is the ac power of the signal I. Assuming i?,'s to be mutually independent, then: mR= MlTR (15B) aR= Mlfcn (16BFrom Eqns. 6B, 13B: N = KMjKrTCLK fT Idt + MT/TCLK - KMR/KrTCLK - Q (17B) Jo Substituting the mean of Q and R from Eqns. 7B, 7B, 15B and 16B into Eqn. 17B, yields: N = K fT Idt + O - E (18B) Jo where K = KM/KrTCLK, 0 = MT/TCLK - M(0.5 - KM1TRJKrTCLK) and E is a random variable with zero mean and variance: ' 4 = M^(/d^)2^] U9B) 184 Appendix C TV and I Relationship in the Double-Phase BICI From Fig. 4.5, assume a half-wave integrator integrates the current I from U = iT to t • = iT + T/2. Therefore, the voltage vc2{t) across C2 is The voltage vC2(t) is sampled and held at t • = iT + T/2 such that: 1 riT+T/2 VC2 = vc2(t)\t=t. = j—^ I Idt (IC) From t = iT + T/2 tot = (i + 1)T, the charge on C2 is transfered into C3. Therefore, the voltage across C3 at t = (i + 1)T is C2 K73 = 7=r^c2-+ K-i + VCMPI u3 where Vi^1 is the initial voltage on C3 remaining from the previous digitization cycle and VCMPI is a constant voltage resulting from charge accumulation on C3 due to comparator 185 input voltage offset and delay. From t = (i + 1)T to t = (i + 1)T + T/2, V£3 is digitized by counting the number of clock cycle it takes to discharge C3. The discharge is performed using current Iramp until vC3(t) becomes negative. Therefore: C3(V£3 - V£) = (NiTck + rCMP2)I, ramp where TQMP2 is delay due to input voltage offset and switching delay of the COMP2, Tcik is clock period, C3 is the effective capacitance being discharged, and N is the number of cycles it takes to discharge C'3. Note that two different values for C3 are considered for charge and discharge cycles to include different parasitic capacitances that affect C3 in these two cycles. N's (i = 1,..., M) are added to obtain half-wave integration result for /, N, as follows: M N =]£>,• =1 _ MTCMP2 C3VCMPI C'3C2 ^ • M_! — T T T r T T C2 R ±clk J-clk-^ramp clk1 ramp t_Q Substituting V£2 from Eqn. IC into 2C yields: (2C) M~x riT+T/2 N = KJ2. Idt + O + Q „_n JiT i=0 c' c where Q = V^'1 is the quantization voltage error, K = 3 2 — is the pro-C3J- clklramp(Cl + t>2) portionality coefficient, and O = (Ml£^l + ^ Wi) is ±Q off§et f-clk J-clk + ramp 186 Appendix D TDC Calibration D.l Two-point Calibration As shown in Sec. 5.2.6, the following relates Td, the time interval to be measured, and N, the measurement made by the TDC: NTA =Td + Tc + TQ + TR (ID) In a two-point calibration scheme, TA and Tc are estimated by measuring two ref erence time intervals: Therefore, NcanT& = Tcati + Tc + TQI + TRX (2D) NcattTfr = Tcal2 + Tc + TQ2 + TR2 T _ Tcai2 - rcajl 7q2 -TQl-\-TR2- TR1 ~ Ncal2 - Ncall + Ncal2 - Ncall = TAO + rAe (3D) 187 where TA0 is the estimated TA and TAe is the error associated with this estimation: Tcal2 — Tcan TAO — T Ae Ncal2 — Ncan TQ2 — TQI + Tm — TRI Ncai2 — Ncan TQI and TQI are two independent and uniformly distributed random variables in the range [0, TA) (with mean of TA/2 and variance of TA/12), and, TRI and TR2 are two independent normally distributed random variable with a mean of zero and standard deviation of aR. Therefore, from Eqn. 3D, TAe is a random variable with the following mean and variance: ™rAe = 0 rp2 n 2 6(iVco/2 - Ncally + (Ncal2 - Ncally K ' The larger the term (Ncal2 — Ncan), the less the error in estimating TA. Tc is obtained as below: rp _ Tcai2Ncan — TcauNcai2 (TQ2 + TR2)Ncan — (TQ1 + TR1)Ncai2 J-C - ju 77 r 7- 77 - i CO + 1 Ce where Tco is the Tb estimate and Tce is the random variable indicating the uncertainty in estimating Tc: ^ Tcai2Ncan — TcanNcai2 lco = - (5D) MCal2 — Ncall T _ {TQ.2 + TR2)Ncan - (TQI + TRl)Ncai2 J-Ce - 77 - (6D) ^Vca/2 — iVca/x The mean and variance of Tce are obtained as below: TA 188 ~2 lTl , ,2^! + (Ncal2/N^)2 Using the number N associated with measuring an interval Td in Eqn. ID, the Td estimate given by the TDC, Td, is: Td = NTAO — Tco Therefore the measurement error is: T,u = Td-fd = NTAe + TCe + TQ + TR (8D) The mean and variance of the measurement error are: mTde = NrriTAe + mTce + rnQ + mR = 0 (9D) 4, =N2^TAe + a2Tce + a2Q + a2R = N2(T2/6 + 2a2R) 2 2 Nj^ + Nj, 2 2 - A^)2 + {IJU + fffl)(£HvJ + TJU + aR (10D) = (1 + 2N,* + N\+ ^ )(T1/12 + ^) Assuming Tcal2 = 2Tcan and Tca/1 >> Tc, one can conclude that Nca;2 ~ 2A^ca/1. Under this assumption the statistics of Tce are: 2 _ 01A , c 2 Jc« ' rt Furthermore, assuming N << (Ncai2 — Ncaii), the rms measurement error is aTde - yTl/2 + QaR. If aR is considered negligible, the rms measurement error due to quantization is obtained as TA/\/2 and the worst case error (3cr band) is ±(3/\/2)TA ~ ±2TA. 189 It is noteworthy that in Eqn. 8D Tce and TAe are constant for all the actual measure ments since they are a result of calibration, whereas, TQ and TR vary for each measurement sample. D.2 n-point Calibration Technique A method to increase the accuracy of measurement accuracy is to limit the variation range of Tc, Tce, in Eqn. 8D. This means reducing the variance aTce. This may be done by the using n-point calibration technique described next. In this technique, n accurately known time intervals are measured by the TDC. These time intervals are multiples of a reference interval Tcai = 0, Tref, 2Tref,..., (n — l)Tref. Assuming TR is negligible, the measurements can be expressed as below: N±TA =TC + TQ1 (UD) N2TA = Tref + Tc + TQ2 (12D) N3TA = TTref + TC + TQ3 ' (13D) (14D) (15D) (16D) NnTA = (n - l)Tref + Tc + TQn (17D) The objective of n-point calibration is to limit the range of TQI variations, which in turn reduces <JTce. 190 In Eqn. 11D to 17D, Tref and TA are assumed to be known (TA can be estimated within a 0.1% accuracy using two of the chosen calibration points as discussed in Sec. D. 1). Assume the following is denned: NrefTA = TreJ + TQref . (18D) where Nref is an integer and TQref is a time interval in the range [0, TA). Since Tref and TA are accurately known, Nrej and TQref are also known from Eqn. 18D. Substituting Trej and Tc from 18D and 11D, respectively, in Eqn. 12D yields: N2TA -NrefTA - A^TA = TQ2 - TQI - TQreJ (19D) The right side of Eqn. 19D is a multiple of TA. Therefore, the left side must also be a mul tiple of TA. Since TQI and TQref must be in the range [0, TA), the two following cases are possible: CASE 1 : TQ2 — TQI — rQre/ = 0 (20D) TQ2 = Tgi + TQr(,f (21D) CASE 2: TQ2-TQ1-TQref = -TA (22D) TQ2 = TQ1 + TQref - TA (23D) Since TQ2 € [0, TA), Eqns. 21D and 23D result in two different ranges for TQ2. The inter section of these ranges with [0, TA), results in a smaller range for TQ2 as shown below: CASE 1: TQI <G [-TQref, TA - TQref) f|[0, TA) (24D) e[0,TA-TQref) and N2 = Nref + N1 (25D) 191 CASE 2: TQI € [TA - TQrej, 2TA - TQreJ) f|[0, TA) (26D) € [TA — TQref, TA) and ^2 = A^re/ + A^i - 1 (27D) Therefore, if Eqn. 25D holds, the range of variation for TQI is limited to the range in Eqn. 24D. Similarly, the range in Eqn. 26D applies if Eqn. 27D holds. The process of limiting the range of variations for TQI can be continued by adding another calibration point, e.g., 2Trej (Eqn. 13D). Substituting Trej and Tc from 18D and 11D, respectively, in Eqn. 13D results in: {N3 - 2Nref - Nr)TA = TQ2 - TQl - 2TQre/ (28D) Using the same reasoning as before, three cases are possible: CASE 3: TQ2 — TQI — 2TQrej = 0 TQ2 = TQI + 2TQref (29D) Therefore: TQI G [-TQref, TA - 2TQre}) f][0, TA) € [0, TA — 2TQref) (30D) and CASE 4: W3 = 2Wre/+ (3 ID) TQ2 ^ TQI — 2TQref = —TA TQ2 = TQI + 2TQrey — TA (32D) 192 Therefore: and CASE 5: TQI € [TA - 2TQrej12TA - 2TQref) fl[0, 7A) e [0, 2rA - 2TQref) if TA - 2TQref < 0 (33D) € [TA - 2TQref,TA) if TA - 2TQre/ > 0 N3 = 2NreS + A7! - 1 (34D) TQ2 — TQI — 2TQrej = —2TA TQ2 = TQI + 2TQref — 2TA Therefore: and (35D) TQI G [2TA - 2TQre}, 3TA - 2rQre/) fl[0, TA) G [0,3TA - 2TQref) if 2TA - 2TQref < 0 (36D) e [2TA - 2TQref, TA) if 2TA - 2TQref > 0 A^3 = 2Nref + Nx -2 (37D) If both Tref and 2Trej are used, the intersections of CASE 1 or 2 with CASE 3, 4 or 5 will result in tighter bounds on TQI which yield a more accurate estimate of Tc. 193 Appendix E Metastability window of a D flip-flop This appendix provides an estimate of the metastability window for a D flip-flop in a 0.35 lim digital cell library obtained through simulation. Assuming the two signals Din and clkin are applied to the D and clk inputs of a flip-flop, respectively, we define TD as: I'D — Welkin ^Din where t£>in and tcikin indicate the times at which the rising edges of Din and clkin signals occur. Denoting the flip-flop's setup time by rsetup, we define metastability window of a flip-flop as the time interval [—Tmw/2, Tmw/2] such that if Tsetup Tmwj2 *C Tsetup ~\~ Tfnyj j2, then the nominal clk-to-Q delay of the flip-flop (rcik-t0-Q.) is increased by an amount rmt. We choose rmt = 3 ns [104] because this value is close to TB, the oscillation period of the oscillator B in the prototype TDC implemented (details given in Sec. 5.5). Any delay exceeding this threshold may result in a T& measurement error, as explained in Sec. 5.2.4. 194 The test bench shown in Fig. E.l (a) is used to estimate Tmw. The buffers and the vss (a) (b) Figure E. 1: The test bench for estimating the metastability window of a D flip-flop OR gate are used to model the inverters and the loading at the output of EOC.DFF in the TQ of Fig. 5.6, respectively. The timing diagram for input signals Din, clkin, and rb are shown in Fig. E.l(b). This circuit is simulated for different values of TD and the Q output is monitored. The simulated DFF output for five values of TD, illustrated in Fig. E.2, show that the DFF output switching delay increases as TO approaches Tsetup. Plots of Fig. E.3 show Tcik-to-Q versus TD. These plots indicate that for TD = 80.17ps, the output remains LOW, whereas for rD — 80.18ps, the output switches HIGH. The additional clk-to-delay (compared to the nominal delay) for TD — 80.18ps is approximately 460 ps which is still less that the 3 ns threshold. This result suggests that the metastability window of the DFF is Tmw < (80.18 - 80.17) ps = 0.01 ps. 195 196 Appendix F Range Extender Block Analysis In Fig. 5.7(b), the numbers at the outputs of cntrA and cntrB versus time can be expressed as follows: where M~A(0) and MA(0) are the initial numbers in cntrA and cntrB at times t < 0, respec tively, and To in the delay between the first rising edge of clkA and that of clkB, and [X\ represents the integer part of X. As time progresses, for some value of i, the i-lh rising edge of clkB precedes that of clkA2, i.e., tA2(i) > ts(i)- At this time, the outputs of cntrA and cntrB become equal for a very short amount of time (teg in Fig. 5.7(b)). Therefore: (IF) MB(t)= L^^J + 1 + MS(0) (2F) MA(0) + ±- = Nl + l-eA (3F) MB(0) + t-—^- = Nt + eB A (4F) 197 where Ni is the state of cntrA and cntrB, and eA and eB are two very small real numbers. Assuming cA and eA are almost zero at teq, eliminating Ni from Eqn. 3F and Eqn. 4F, yields: MA(0) + ±- = MB(0) + + 1 (5F) •LA 1A Therefore, t = ^TA + (MA(0) - MB(0) - l)~TA (6F) ^ is the number of cycles it takes for the i-th edge rising of clkA2 and that of clkB to match. Therefore j^TA is the total time needed for this edge matching to occur. Since the goal is to have these edges match after j£TA, the term (MA(0) - MB(0) - l)^TA must be identically zero, i.e., MA(Q) = MB(0) + 1 (7F) Eqn. 7F shows that cntrA must be initialized to a number corresponding to the initial state of cntrB plus one. 198 Appendix G Two-Parameter Model for V^-induced Gate Delay Variations In this appendix, two different tests are described to validate the two parameter noise model in Eqn. 4H. We wish to model the effect of power supply voltage variations (V^e)) on gate delay. We denote this variation by re. G.l Test 1: Single Gate Delay Simulations Assume the propagation delay variations of a digital gate is obtained as below: Te = iVe + RToVe (IG) where r0 is the static delay of the gate (assuming no power supply noise) and Ve = ~ Vdd(e)(t) T0 Jt=t0 199 where t0 is the time the input of the gate crosses the gate switching threshold. A first test to validate the model in Eqn. IG is to assume the above model for delay variations of this digital gate, and obtain 7 and p by fitting simulation results to the model. The discrepancies between the simulation results and the fitted model will indicate the model accuracy. To perform the test, as shown in Fig. G.l, a digital gate is loaded with a capacitor to generate different static delays. For each case, re is measured through simulation for differ ent values of Ve. For each value of Ve, the coefficients jVe and pVe in Eqn. IG are obtained by fitting the simulation data for different loading values to a straight line in MATLAB. Then, these coefficients are divided by Ve to estimate 7 and p for each value of Ve. The av erage value of all these estimated coefficients is used as an estimate of 7 and p, respectively. VDD, VSS VSS 3.3V-0.33V Vin t 3ir*\ 200n Figure G.l: The test bench for validating the two parameter model for Vdd-induced gate delay variations 200 Parameter LOW-to-HIGH transition HIGH-to-LOW transition INVX1 INVX2 NANDX1 NANDX2 INVX1 INVX2 NANDX1 NANDX2 7 (ps/V) -4.4 -3.81 -3.76 -3.67 -2.27 -1.93 -2.94 -2.83 P (IV) -0.135 -0.153 -0.166 -0.172 -0.219 -0.222 -0.217 -0.218 rms error (%) 4.5 4.3 4.5 4.5 4.6 4.45 4.8 4.2 Table G. 1: 7 and p estimates and the resulting model errors for four different digital gates The above test was performed on four different types of gates in a standard digital cell library for a 0.35 p.m CMOS technology: a single-drive inverter; a double-drive inverter; a single-drive 2-input NAND; and a double-drive 2-input NAND gate. The loading capaci tances used were 0 to 70 fF in steps of 5 fF. Also, Vdd(nominai) — 3.3V and —165 ?nV < Vdd(e) < 165 mV which is equivalent to 10% peak-to-peak variations on Vdd. Table G.l, lists the estimated values of 7 and p for LOW-to-HIGH and HIGH-to-LOW input transition for each type of gate. The rms error in each case, given in the last column, is less than 5% in all cases which proves that the two-parameter model of Eqn. IG is adequate to model gate delay variations due to power supply noise. G.2 Test 2: Ring Oscillator Test A ring Oscillator is an efficient circuit to test gate delays. In this section, we validate the two-parameter gate delay variation model by comparing the simulation and modeling results for the output period and accumulative Vdd-induced jitter. The output period of a ring oscillator (Fig. G.2) is a summation of the LOW-to-HIGH 201 Ring Oscillator Digital Gate Digital Gate 1 I VSS Figure G.2: The ring oscillator test bench to validate the two-parameter model for Vdd-induced gate delay variations and HIGH-to-LOW propagation delays of all the gates in the loop: 2N T = XXT<7«0 + Tg{i)e) i=l where T is the output oscillation period, Tg^0 and rg^e are the i-th gate's static delay and delay variation, respectively. Therefore, the period jitter Te is 2N Te = Y2T9We *=1 Using the two-parameter model for gate delay variations yields the following for Te: I rti+Tati)0 1 rti+Tg(i)0 Te = El7(— / V^)dt) + ^«o( / VMe)dt)} (2G) ,=1 T9(i)0 Jt> T9(i)0 Jt< Assuming Tg{i)e « rg{i)0, and also that rgWo = T5(2)0 = ... = Tg{2N)o, Eqn. 2G simplifies to: Te =(— + p) f'+T Vdd(e)dt fU+T = «y# vdd(e)dt (3G) where K is a constant and is the beginning time of the i-th period. Note that Te in Eqn. 3G is independent of the number of gates N and the output loading of each gate. To validate 202 Eqn. 3G, a ring oscillator consisting of 21 NAND gates in a 0.35 fim CMOS digital cell library was simulated with a number of sinusoidal power supply noise waveforms of the form: Vdd(e) = VEsm(2nft) (4G) for VE = 0.165V, denoting ±5 variations, and /=5 MHz, 50 MHz, 150 MHz, 350 MHz, 650 MHz and 1.1 GHz. A wide range of frequencies have been chosen to validate model for a large frequency range. Figs. G.3 shows that the derived model with parameters obtained previously matches the simulation results within 2% in for all the tested frequencies. As a by-product of the above analysis, we obtain the peak-to-peak period jitter, Te(pp), for sinusoidal noise. This gives insight in the jitter behavior of ring oscillators in the pres ence of power supply noise. This is especially important whenever ring oscillators are used for timing purposes such as in the TDC application. Substituting Vdd(e) from Eqn. 4G in 3G: VE LOT Te(Pp)=4K—sin(—-) ui Z The above shows that the jitter at output of a ring oscillator decreases as the noise frequency increases. 203 -0.2 -0.1 0 0.1 0.2 -0.2 -0.1 0 0.1 0.2 Ve(V) Ve(V) Figure G.3: Ring oscillator period jitter from simulation and the two-parameter model for Kw-induced gate delay variations, a)/=l. 1 GHz, b)/=350 MHz, c)/=50 MHz, d)/=5 MHz 204 Appendix H TDC Power Supply Noise Analysis In this appendix, we analyze the effect of V^-induced jitter in TDC's Oscillators A and B on the accuracy of the TDC. We show that the differential nature of our TDC eliminates significant parts of the power supply noise. We denote the error component due to power supply noise by Eps- From Eqns. 5.23 and 5.21: N-l 2M-1 EPS = £ [ £ - 4.)e)l (1H) j=0 «=o where ^e and ^e are the propagation delay jitter of the i-th gate of Oscillators A and B in the j-th period of clkA and clkB, respectively, and M — MA = Mp is the number of gates in oscillators A and B. Defining the index k = Nj + M, the double summation in Eqn. IH can be reduced to one summation: 2JVM-1 EPS = E (Tg(k)e ~ Tf(k)e) (2H) k=0 where r^fc)e and r^fc)e are the variations of gate delay for the fc-th switching event in oscil-205 lators A and B, respectively. To estimate the relationship between Eps and power supply noise Vdd(e) > gate delay variations, r^fcje and T^£, are modeled as follows: T9(k)e Tg(k)e where 7 and p are constants; and: VA -VB -V(k)e -where tA and tf are the times at which the input switching thresholds are crossed in oscilla tors A and B, respectively, and V^(e) is the difference between the actual Vdd and the nominal noise-free value: Vdd(e) = Vdd — Vdd{nominai)- Note that in this analysis the switching thresh old is Vdd(tk)/2. Eqns. 4H and 4H model V^-induced gate delay variation as a function of two Vdd-dependent components, one independent of and the other one proportional to static delay of the gate. To validate this model, two different tests have been performed. Details are described in Appendix G. From Fig. 5.7, for the interval t = 0 to t = Td, only oscillator A oscillates. Assume A7! switching events of oscillator A occur during this interval. We split our noise analysis into two parts, one due to switchings from t — t0 — 0 to t — td = Td, and the second part due to switchings events from t = td to t — teoc = TEoc, where tEOc (EOC: end of conversion) is the time the TDC requires to terminate the measurement (2MW-th edges of switching events in Osc-A and Osc-B occur at the same time). Therefore: EpS = EpS[a) + Eps(b) (7H) 206 = (l + PT9A{k)0)V{Ak)e (3H) = (7 + ^fc)0)V(f)e (4H) ^lli^{k)° Vdd(e){t) (5H) ^J^J*k)° Vdd{e)(t) (6H) g(k)0 k where: Ni-l EPS(a) = E ^1*)e, (8H) k=0 2MN-1 2MN-1 EPS{b)= E r^)e- E (9R) k=Ni k=0 Assuming that the power supply noise in the [0, td] window is independent of the noise dur ing interval [td, teoc], the total rms noise is: aPS - \JaPS{a) + aPS(b) To determine Ep$(a), we use the analysis technique explained in Sec. G.2: EPS{a)=K fTdVdd(e)(t) (10H) Jt=o where K is a constant (see Appendix G.l). To obtain vEp , we substitute and from 4H and 4H into 9H to yield: TPS{b) = T1 + r2 (11H) where: 2MN-1 q rtA + TA 2MN-1 i rtB+TB ^TV, Tg(k)0 Jt=tk k=Q Tg(k)0 Jt=tk 2MN-1 ,tA+rA 2MN-1 rtB+TB r2 =P[ E /Vw°W0- E /yw°Wt)] (i3H) Since t^ = tB = td: E /*A""°^,(t)= E r."w^r^w Therefore: T2 = 0 (14H) 207 Assume that all the gates in oscillator A have the same static delay, and similarly for the gates in oscillator B, i.e., = TAO for fc = 0,... ,2MN - 1 and T^0 = TBO for k = 0,..., 2MN - 1. From t = tdtot = teoc, there are 2MN - Nx and 2MN switching events in oscillators A and B, respectively: ™= 2MN - N, (15H) ^eoc ~ td ,IT, Tfl0= ^MAT (16H) where Ai is the number of switching events occurring in oscillator A from t = 0 to t = Td. Therefore: ri =-iN1(-^--r) ftc°c vdd{e)(t) ''eoc ^d Jt—td = — jNiVdd'e)(td,teoc) (17H) where Vdd(e){td, teoc) is the average of Vdd{e)(t) over the time interval [td, teoc]. From Eqns. 7H, 10H, 11H 14Hand 17H, the following relationship follows for Eps: EPS = K fTd Vdd{e){t) - jNiV^iUfeoc) (18H) Jt=o Since Td = N±TAO, therefore: TpS = Td[nVdd{e)(t0,td) Vdd{e)(td,te0c)] (19H) • TA0 where Vddre)(t0,td) is the average of 14^) over the interval [t0,td]. Eqn. 19H shows that the Vdd-induced inaccuracy in the ring oscillators is proportional to the time interval being measured, i.e., Td. 208 


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