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On power-supply current testing of mixed-signal phase-locked-loops Dalmia, Maneesha 1997

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On Power-Supply Current Testing of Mixed-Signal Phase-Locked-Loops By Maneesha Dalmia B.E., University of Delhi, Delhi, India, 1994 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA July 1997 © Maneesha Dalmia, 1997 Abstract Abstract Due to rapid advances in the speed and complexity of VLSI circuits, analog and mixed-signal circuits are going through a resurgence. Today, the state-of-the-art of the analog and mixed-signal integrated circuit testing is to use application-specific test techniques for individual modules. Efforts have been made to develop simple, generic test techniques to tackle this problem. Current-mode testing is one such approach. The effectiveness of power supply current testing for digital IC's has led researchers to explore the possibility of extending this concept to testing analog blocks of mixed-signal ICs. Unfortunately, current-mode test techniques developed for commonly-studied analog blocks, such as op-amps and filters, do not apply to non-linear blocks such as phase-locked loops. This thesis focuses on investigating the effectiveness of using power supply current monitoring techniques to detect potential faults in phase-locked loop (PLL) circuits. The decision for declaring a circuit as fault free, or- faulty, is made by defining a simple threshold which takes into account the tolerances on the circuit parameters and process variations. Table of Contents Table of Contents Abstract i i List of Tables vii List of Figures . viii Acknowledgements xi 1 Introduction 1 1.1 Scope of thesis 3 2 Mixed-Signal Testing 6 2.1 Fault model for digital circuits 6 2.2 Test techniques for digital testing • 8 2.2.1 Conventional testing 8 2.2.2 Design-for-testability 8 2.2.2.1 Ad-hoc testing . 9 2.2.2.2 Scan-based approaches .9 2.2.2.3 Built-in self-test 9 2.2.3 I d d q testing 10 2.3 Fault model for mixed-signal circuits . . 11 2.3.1 Structural fault model . . . ". . . 12 2.3.2 Behavioral fault model . . . . . . . . 12 Table of Contents iv 2.4 Mixed-signal testing approaches 13 2.4.1 Conventional testing 13 2.4.2 Design-for-test techniques 13 2.4.2.1 Support for external equipment - I ad testing 14 2.4.2.2 Access to embedded blocks 14 2.4.2.3 Built-in self-test 15 3 Phase-Locked Loops 16 3.1 Introduction 16 3.2 P L L applications 18 3.3 General theory of a P L L '•• 19 3.3.1 Loop-filter 21 3.4 Charge-pump PLLs ' . . . 26 3.4.1 Phase/frequency detector .. . 27 3.4.2 Charge-pump circuit . : . 30 3.5 Design of the P L L circuit-under-test 31 3.5.1 Feasibility 31 3.5.1.1 Simulation. . . . . 32 3.5.1.2 Behavioral model '. . 36 3.5.2 Structural design , 41 3.5.2.1 Phase/frequency detector (PFD) . .' 41 3.5.2.2 Charge-pump and Loop-filter 43 3.5.2.3 . Voltage-controlled oscillator (VCO) 44 3.5.3 Physical design 48 Table of Contents v 4 Power Supply Current Testing of the PLL Circuit-Under-Test 50 4.1 Fault model 50 4.2 Test techniques 52 4.2.1 "Operating" I d d test 52 4.2.1.1 Statistical modeling 54 4.2.2 "Non-operating" I d d test ; 55 4.2.3 "Frequency-lock" test ' 57 4.2.3.1 Conventional frequency testing methods 58 4.2.4 Simulation issues 59 4.3 Results 61 4.3.1 "Operating" I d d test 61 4.3.2 "Non-operating" I d d test 65 4.3.3 "Frequency-lock" test 66 4.3.4 Overall fault coverage 68 5 Conclusions and Future Work 70 5.1 Conclusions 70 5.2 Future work , 71 References 73 Appendix A List of Acronyms 78 Appendix B Layouts 80 Appendix C Simulation Results 84 Appendix D Hspice Code 88 Appendix E MATLAB Code . 95 Appendix F PD Faults 99 Table of Contents vi Appendix G VCO Faults 101 List of Tables vii List of Tables Table 3.3.1 Approximate values of up and H p for three damping cases. 24 Table 4.2.1 Device model parameters 55 Table F . l Effect of stuck-at 1 faults in PD on power supply current 9 9 Table F.2 Effect of stuck-at 0 faults in PD on power supply current. . . . . . . . . 100 Table G . l Effect of G-D shorts in V C O on power supply current 101 Table G.2 Effect of G-S shorts in V C O on power supply current. . . . . . . . . . . 102 Table G.3 Effect of Source opens in V C O on power supply current 103 Table G.4 Effect of Drain opens in V C O on power supply current 104 List of Figures viii List of Figures Figure 2.1.1 Illustration of stuck-at fault model for a N A N D gate 7 Figure 2.2.2 Ljdq test for an inverter 11 Figure 3.1.1 The block diagram of a P L L . . 17 Figure 3.1.2 Typical waveforms of a P L L 18 Figure 3.3.3 The linear model of a generic P L L [Wol9.1, Raz96]. 20 Figure 3.3.4. A passive loop-filter. . 21 Figure 3.3.5 The frequency response of the low-pass loop-filter. 22 Figure 3.3.6 Open and closed-loop responses of the P L L 23 Figure 3.3.7 Step response of the P L L . . 25 Figure 3.4.8 Basic architecture of a charge-pump PLL. 26 Figure 3.4.9 The state diagram of the PFD. . 28 Figure 3.4.10 The operation of the phase/frequency detector 28 Figure 3.4.11 The phase characteristic of the PFD 30 Figure 3.4.12 Functioning of the charge-pump circuit 31 , Figure 3.5.13 The step response of the P L L circuit-under-test 34 Figure 3.5.14 The filter response of the P L L under test. . . 35 Figure 3.5.15 The open loop response of the P L L under test 35 Figure 3.5.16 The closed-loop response of the P L L under test. 35 Figure 3.5.17 The block diagram of the behavioral model of the P L L 38 Figure 3.5.18 Verilog code for the PFD model. . 39 ' List of Figures Figure 3.5.19 A H D L code for the V C O model 40 Figure 3.5.20 PFD Schematic 43 Figure 3.5.21 The transistor level implementation of the charge-pump with the passive loop-filter 44 Figure 3.5.22 A three-stage ring oscillator . 44 Figure 3.5.23 The desired V C O characteristic 45 Figure 3.5.24 The V C O schematic 46 Figure 3.5.25 The V C O characteristic 47 Figure 3.5.26 The floorplan of the P L L chip. 48 Figure 4.1.1 MOS transistor fault model [Cam92] 51 Figure 4.2.2 "Non-operating" I d d test for the VCO. 57 Figure 4.3.3 Variations in power supply current for our P L L under parametric deviations 62 Figure 4.3.4 P L L fault coverage obtained by the "operating" Idd t e s t - 63 Figure 4.3.5 Fault coverages obtained for the V C O by "operating" Idd for different thresholds (a) ±10%, (b) ±20%, and (c) ±50% . 6 4 Figure 4.3.6 PD fault coverage for various "operating" Ljd thresholds 65 Figure 4.3.7 P L L fault coverage using the "frequency-lock" test 67 Figure 4.3.8 V C O fault coverage using the "frequency-lock" test. 67 Figure 4.3.9 PD fault coverage using the "frequency-lock" test . 67 Figure 4.3.10 Fault coverage obtained using various test techniques ("operating" Idd threshold of ±10%). . .. ' . 68 List of Figures x Figure 4.3.11 Fault coverage obtained using various test techniques ("operating" Idd threshold of ±20%) '. . . . . 68 Figure 4.3.12 Fault coverage obtained using various test techniques ("operating" Idd threshold of+50%) 68 Figure B . l P L L layout 81 Figure B.2 V C O layout 82 Figure B.3 Charge-pump layout . 83 F i g u r e d Various output waveforms for the behavioral model. . . 84 Figure C.2 Reference input and V C O output for the behavioral model 85 Figure C.3 Various output waveforms for the P L L under test 86 Figure C.4 Reference input and V C O output for the P L L under test 87 Acknowledgements xi Acknowledgements I wish to express my sincere gratitude to my advisor Professor Andre'Ivanov for his guidance, support and advice. In addition, I thank the other members of my dissertation committee, Professor Samir Kallel and Professor Steve Wilton for their precious time. I also thank Mr. Sassan Tabatabaei for his comments and discussions; his contributions to chapter 3 are especially acknowledged: I would also like to thank Roozbeh Mehrabadi for his help in suggesting and providing solutions to my VLSI tool problems. I would like to acknowledge Micronet, PMC-Sierra, Inc., C M C , and NSERC for providing financial support for this research. Special thanks to Kamal for his love, patience and encouragement throughout this thesis. Lastly, even though words cannot fully explain, I wish to express my deep gratitude and indebtness to my parents and family for their love, encouragement, support and understanding at every stop of the way. Maneesha Dalmia Chapter 1 Introduction With the rapidly increasing size and complexity of application-specific integrated circuits (ASICs), testing for manufacturing defects and fault diagnosis are vital for quality assurance and low defect levels of electronic components. Rapid advances in the electronics industry has enabled the implementation of mixed-signal circuits, where complex digital circuits along with analog circuitry can be integrated into a single integrated chip. These mixed-signal integrated-circuits (ICs) are cost-effective and provide improved system reliability and flexibility. However, to exploit these merits, we need to develop adequate test methods in order to test these ICs. There are a number of well established techniques for the testing of digital circuits, such as automatic test pattern generation (ATPG), design for testability (DPT), built-in-self-test (BIST), level sensitive scan design (LSSD) and approaches based on the D-algorithm [Eck93, Wes85]. However, analog test and fault diagnosis techniques are still modest compared to their digital counterparts. Analog circuits, being "application-specific", are by their very nature difficult to test. VLSI test engineers face issues such as whether the well established test techniques for digital circuits should be used for testing analog and mixed-signal circuits, or, whether new techniques based on existing knowledge in digital and analog test domains should be developed. The testing of analog and mixed-signal circuits is still in its infancy due to a lack of adequate fault models, as compared to the digital domain, where it is possible to map a large 1 1. Introduction 2 number of physical defects onto the stuck-at 0 and stuck-at 1 fault model. Analog testing is more complex, compared to that for purely digital circuits, for several other reasons [Shy96] such as: . (i) The need to measure currents and voltages at internal nodes which are difficult to access. (ii) Diagnosis errors caused by parametric faults which are due to the process variations of the components. (iii) The additional costs resulting from silicon area overhead required for built-in self-test techniques. Analog circuits have traditionally been tested to meet design specifications. Moreover, today, state-of-the-art of analog circuit testing is still such that, in practice, the most widely-used approach is based on relatively complex, expensive, and specific functional testing. In general, unacceptable amounts of time are spent on the test development of analog portions of mixed-signal ICs [Bis95]. Efforts have been made to tract this general analog test problem. Many DFT techniques have been proposed to test analog circuits, e.g., (i) use of MOS switches to isolate filter and op-amp stages [Fas88], (ii) use of signal multiplexing [Wag88], (iii) BIST for analog modules [Chi90, Dal96]. Many of these techniques involve careful partitioning of the digital and analog sections of the IC in order to gain access to the internal embedded nodes. Such partitioning methods require two sets of test equipment as well as additional IC pins, resulting in an added cost factor. The cost of analog and mixed-signal testing is a major issue in this area of analog and I. Introduction 3 mixed-signal testing [Dev96]. Hence, new techniques that can be simple, cost effective, and generic need to be developed. In order to alleviate this problem, for both digital and analog circuits, considerable efforts have been spent in developing cost-effective, simple, and generic tests. Power supply current-based testing is one approach towards such a development. Power supply current testing, in the form of quiescent power supply current (Iddq) testing, has been successfully used for testing CMOS digital circuits [Sod92]. Typically, a fault is excited by an application-specific test stimuli, and the effect of a defect is observed as a potential change in the quiescent state power supply current. A major advantage of this technique is the associated high fault observability, i.e., obviation of the need to propagate the effect of a fault to-a circuit's primary outputs [Mce9-l]v The success of Id q testing for digital circuits has stimulated efforts towards extending this concept to the testing of analog circuits. 1.1 Scope of thesis Recognizing that application-specific functional testing of analog and mixed-signal cir-cuits suffers from cost penalty, this thesis deals with the analog and mixed-signal test problem through a simple, cost effective and generic, current based testing perspective. Most of the recent efforts investigating supply current testing of analog circuits tend to focus on basic building blocks, such as op-amps, filters etc. Eckersall et al. investigated the use of current testing for op-amps and A/D converters [Eck93]. Zhihua et al. investigated the current test-ing approach on an op-amp, a bipolar differential pair circuit, and an analog bandpass filter [Wan94]. Most of these circuits have been investigated in open-loop circuit configurations. Phase-locked loops (PLLs) inherently differ from such analog blocks as they constitute an 1. Introduction 4 example of a closed-loop circuit. PLLs are the most commonly used components in clock generation and clock recovery applications. Generally, production testing of PLLs is done using functional testing. The "frequency-lock" test is the most widely-used functional test for testing PLLs in the electronics industry [Sto96]. This thesis focuses on investigating the efficiency of power supply current (Idd) tests, versus that of frequency-lock test, for testing PLLs. Chapter 2 presents a review of fault models used for digital and mixed-signal testing. A background on conventional test methodologies and various DFT and BIST approaches to test VLSI circuits is presented. Chapter 2 also addresses power supply current monitoring techniques for testing digital and mixed-signal ICs. Chapter 3 focuses on the design aspects of the circuit-under-test (CUT). An overview of the general theory of PLLs is presented, followed by design details. A mathematical analysis of PLLs is presented in order to obtain the design parameters. A behavioral model is also presented in order to determine the feasibility of the design. Finally, the structural and physical designs of the P L L are presented. A comprehensive fault model based test approach is used to evaluate the effectiveness of various test methods for the mixed-signal P L L circuit-under-test in Chapter 4. Test techniques for the fault diagnosis of PLLs are presented based on the observation of power supply currents. Fault simulation is used to distinguish the defective circuits from the good ones for given input test sets. Tolerances in circuit parameters due to process variations are taken into account in order to determine a suitable threshold for fault detection. An approach to test the digital components of a mixed-signal P L L circuit using analog power supply 1. Introduction 5 current is developed. By systematic fault simulation, a quantitative comparison between the functional production test ("frequency-lock" test) and the current test techniques is presented. A contribution to mitigate the problems related to the fault simulation of PLLs is made, i.e., techniques to reduce fault simulation time are presented. The research presented in this thesis addresses many critical areas in the testing of PLLs, but the problem is by no means completely solved. The current test techniques presented in this study can be extended to other classes of analog and mixed-signal circuits. This study opens up exciting new areas for future work, mentioned in Chapter 5, along with conclusions. Chapter 2 Mixed-Signal Testing The testing of VLSI circuits plays a vital role in the electronics industry and an exponentially increasing amount of effort is being expended on test development to ensure a working final product. The testing of digital circuits is relatively well-understood and efficient test techniques have relatively long existed. This chapter presents various existing test techniques for digital circuits along with a review of the existing approaches for analog and mixed-signal testing. 2.1 Fault model for digital circuits Like any manufacturing process, VLSI technology is not without its faults. These faults may arise in a VLSI chip from a variety of sources from fabrication defects and contamination of the base material to packaging and subsequent handling. In order to deal with defective VLSI chips, we require an understanding of the failure mechanisms. Attempts have been made to represent the effect of these failure modes at the logical level with the use of fault models. In order to distinguish the good from the bad parts it is essential to propose a "fault model". This model could demonstrate, for example, how certain faults occur, as well as their impact on circuit performance. One of the major reasons for the success of digital testing is the existence of well-developed fault models. The popular fault model for digital circuit 6 2. Mixed-Signal Testing 7 testing is called the 'stuck-at' model [Wes85]. Most of the potential physical defects that might occur in digital circuits can be mapped to a physical node being stuck-at a logical 1 or 0 [Nag94]. The stuck-at fault model assumes that faults in the circuit, cause the interconnect lines present in the circuit to become fixed at logical 1 (stuck-at 1) or logical 0 (stuck-at 0). The stuck-at fault model can be applied at various levels of abstraction of a circuit, e.g., it can be applied at the pin level, where the I/O pins of a device are assumed to be stuck; or at the gate level, where the I/O pins of any gate can be stuck. Node stuck-at Test vectors A 0 0 1 1 o-B 0 1 0 1 o-Good response Out Fault detection vector Faulty response 2-input NAND gate Figure 2.1.1 Illustration of stuck-at fault model for a N A N D gate. A single stuck-at (SSA) model, is a subset of the stuck-at model, wherein, at any given time, a single node in a circuit is assumed to be fixed at logical 1 or 0. the motivation being practicality, since it is not feasible to model multiple stuck-at faults for large circuits. Many other failure mechanisms that are common in MOS devices, such as stuck-open, bridging and delay faults are not modeled by the stuck-at fault model [Wes85]. Yet, despite its shortcomings, the classical stuck-at fault model is the most widely used fault model for testing digital circuits. 2: Mixed-Signal Testing 8 2.2 Test techniques for digital testing The testing of digital circuits is performed by stimulating the circuit with test vectors, and comparing the observed behavior with the desired response. The metric of measure of the quality of a test program is the amount of fault coverage it achieves, i.e., the proportion of faults, for the considered fault model, detected by a set of test vectors applied. Fault simulation is the most popular method to determine the effectiveness of input test vectors which are used to discriminate defective circuits from good ones. Fault simulation involves the creation of faulty versions of the circuit by injecting targeted faults into the fault free circuit and simulating with the test program. The fault is detected if the behavior of the faulty circuit is different from the fault free case under the test stimulus applied. 2.2.1 Conventional testing Conventional test methodologies use external equipment to monitor the I/O pins of a device to determine the correct operation. During production testing, automatic test equipment (ATE) is used to apply the test stimulus to the inputs of a device and to then monitor the output response under the given test set. By detecting a malfunctioning chip at an earlier stage of production, overall costs can be lowered. The conventional testing methods are becoming increasingly difficult to implement due to a lack of internal circuit observability and controllability. 2.2.2 Design-for-testability Design-for-testability (DFT) techniques enable an IC to be more testable by increasing the accessibility of the internal nodes. DFT techniques can be categorized as [Wes84]: 2. Mixed-Signal Testing 9 (i) ad-hoc testing, (ii) scan-based approaches, (iii) built-in seft-test. 2.2.2.1 Ad-hoc testing Common ad-hoc testing techniques involve partitioning large sequential circuits, adding test points, adding multiplexers and providing an easy reset state [Puc93, Wes85]. As process densities and chip complexities increase, ad-hoc techniques become less effective, and a necessity for structural approach to testing arises. 2.2.2.2 Scan-based approaches Structural design techniques, such as scan-path designs, use special latches or flip-flops that provide an additional set of data and clock inputs [Puc93]. In these techniques, the circuit is reconfigured into a scan register and a combinational circuit. The scan-based approach allows control of an internal state by shifting the appropriate state bits into the register, and the observation of any internal state, by shifting the state bits out of the register. Level sensitive scan design (LSSD) is a popular scan path technique adopted by IBM. Often, the costs associated with this approach are extra hardware, additional circuit complexity, additional pins and a relatively slower test speed [Ism94]. 2.2.2.3 Built-in self-test Built-in self-test (BIST) proposes to improve VLSI testing by providing additional circuits in a design that are capable of testing the design from within a chip. The BIST circuit contains on-chip circuitry which generates test patterns and evaluates the response of the 2. Mixed-Signal Testing 10 circuit under the test stimuli [Ism94, Bar87]. The on-chip circuitry alleviates the problem of internal accessibility of embedded nodes in the circuit. Besides improved controllability and observability, BIST offers additional benefits, such as the possibility of reducing test time development. The main costs associated with BIST are the area and the design overhead. The design overhead includes additional design time and complexity. 2.2.3 Iddq testing Quiescent power supply current (Iddq) testing of CMOS integrated circuits is a technique that has gained popularity for testing bridging faults that can occur in ICs [Wes85]. An example is a gate-oxide short illustrated in Fig. 2.2.2(a). This technique relies on the fact that when a CMOS logic gate is not switching, it practically draws no dc current (just the leakage current). In the presence of a fault, for some specific test stimuli, this current is raised to abnormal levels and a measurable Id d q current flows. The concept is illustrated in Fig. 2.2.2(b) for a CMOS inverter. V j n is the input to the inverter and V o u t is the output voltage. Idd is the power supply current and Iddq is the quiescent state power supply current. 2. Mixed-Signal Testing 11 V D D i , . ^ —TZ vss (a) (b) Figure 2.2.2 Ljdq test for an inverter. This technique has a number of benefits. It can indicate the presence of a defect directly without the need to propagate the effects to the primary output pins of the circuit. Also, it is capable of detecting defects which are missed by the traditional stuck-at testing method. One limitation of this technique is its slow testing speed. 2.3 Fault model for mixed-signal circuits Unlike digital circuits where only discrete values are meaningful, in analog circuits, the entire waveform has significance. Hence, the application of digital fault models does not yield much insight into the behavior of analog circuits in the presence of faults. Hence, appropriate fault models are required for analog components of mixed-signal ICs. The faulty 2. Mixed-Signal Testing 12 behavior of a circuit can be modeled at various levels of abstraction. The fault models for analog circuits can be categorized as [Dev96]: (i) Structural level fault model, (ii) Behavior level fault model. The choice of the level of abstraction depends on the trade-off between the required accuracy and the computational complexity. 2.3.1 Structural fault model Structural level fault models can be further classified, as: (i) Device level - In the case of the device level fault model, spot defects are inserted on the layout and then simulations of the defective circuits are performed using a defect . simulator such as VLASIC [Ohl96, Har93]. (ii) Circuit level - Fault models are developed by forming macromodels of the fault free circuit and incorporating some parameter values or adding extra components like resistors, switches, etc. [Nag94]. The fault model at the circuit level are used to analyze the good and the faulty behavior of the circuit. 2.3.2 Behavioral fault model A behavioral fault model is derived by evaluating the output response of the good and the faulty circuits and modeling them by a curve fitting algorithm [Dev96, Zwo96, Tab97]. A transistor level simulation is performed in order to extract the parameters which describe the behavior of the block. These parameters are then mapped, by a behavioral simulator, to a 2. Mixed-Signal Testing 13 higher level. Typically, the circuit is partitioned into smaller blocks, enabling a hierarchical fault modeling approach. Once the design has been decomposed into smaller blocks, a model structure is chosen. 2.4 Mixed-signal testing approaches The testing of mixed-signal circuits is performed in a fashion similar to their digital counterparts [Agr96]. The faults in the circuit are excited by a set of specific test stimuli and the output response is compared with the fault-free response. Fault simulation is used to determine the effectiveness of a test program. Various mixed-signal test approaches are discussed below. 2.4.1 Conventional testing This methodology is similar to that used for digital testing. A carefully chosen test stimuli is applied to the inputs by the external equipment (ATE) and the output signals are recorded. These signals are evaluated to determine if the CUT is free from faults or not. The ATE used for analog components present in mixed-signal ICs generally contain special function generators and signal analysis units. In some cases, digital ATE can be used with other specialized external equipment, such as sampler and digital signal processors. Usually, these extra sets of external equipments imply considerable additional cost [Agr96]. 2.4.2 Design-for-test techniques A number of DFT techniques have been proposed to assist analog testing. These are quite similar to the 'ad-hoc' testing techniques for testing digital circuits. The general principles underlying these techniques are [Wil82, Wag89]: 2. Mixed-Signal Testing 14 (i) Partitioning of the circuit in macro blocks; (ii) Control over macro inputs; (iii) Observe macro outputs; (iv) Disable feedback paths in the closed-loop system; . (v) Place digital storage elements at analog-to-digital and digital-to-analog interfaces; (vi) Use a digital test access port to select test mode. The commonly used DFT approaches are: 2.4.2.1 Support for external equipment - Ljd testing As discussed earlier, quiescent power supply current monitoring, or Ijdq testing, has become a standard testing method for digital testing. This technique may be feasible for testing mixed-signal ICs if appropriate circuit partitioning techniques are employed [Ric96, Agr96, Meh93]. Various current testing methods have been investigated for testing linear analog circuits by ensuring a separate power supply for analog circuitry. In certain cases, it may be feasible to use additional on-chip built-in current sensors to effectively mirror the bias current for an analog block to an additional probe pad [Wag89]. 2.4.2.2 Access to embedded blocks Structural approaches to access embedded nodes are discussed in this section. Scan path and the IEEE 1149.4 [Ric96, Sun95] standard proposal are examples of these structured test techniques. The IEEE 1149.4 is an extension of IEEE 1149.1 boundary scan architecture for analog circuits. This proposed standard is compatible with the digital standard, thus enabling the testing of mixed analog-digital systems. The Scan path and IEEE 1149.4 standard allow 2. Mixed-Signal Testing 15 observation and control of selected nodes, by on-chip or off-chip test techniques. One disadvantage is the pin overhead. The IEEE 1149.4 standard requires six dedicated pins and several analog switches at every analog pin [Sun95]. Other techniques to access internal nodes without the need of additional pins involve the use of on-chip analog-to-digital converters (ADC) and digital-to-analog convertors (DAC) in the test circuitry. The cost associated with this approach is the design and the area overhead. In addition to the general requirement regarding the observability of internal nodes,: interfaces to inject test stimuli into the signal path circuitry are also required. One method of achieving this is to employ a 'swap-amp', which is a configurable op-amp that can operate in a normal mode, or, as a transparent block in the test mode [Fas88]. This is usually done by using MOS switches. 2.4.2.3 Built-in self-test In BIST, the device-under-test (DUT) incorporates the test generation and response evaluation hardware. The test method is customized to the DUT and test times can be drastically reduced. Various macro-specific BIST techniques have been proposed, such as self-test through the comparison of reconfigured identical circuit modules, self-test by the utilization of a time redundancy scheme in order to compare the conversion result of a A D C with a second sign inverted one [Wey90, Ter93, Ton93]. A major disadvantage associated with such BIST techniques is the large area overhead. Chapter 3 Phase-Locked Loops In this chapter we present the design of the phase-locked loop (PLL) circuit-under-test. PLLs are widely used in areas such as communications, wireless systems, and disk drive electronics and can be implemented in a variety of ways [Raz96]. In this thesis we focus on a clock synthesis P L L designed to run at 155 MHz. The frequency of operation is chosen to be 155 MHz since it corresponds to a popular class of telecommunication ICs operating at SONET OC-3 rate [Hot92]. In this chapter, we first present an introduction to PLLs along with some common applications. A brief review of the principles of P L L design is presented. Following the review of the basic building blocks of the PLL, we then analyze the dynamic behavior of PLLs. Finally, we describe the design of a charge-pump PLL. In the design section (Section 3.5), we first describe a form of mathematical modeling to obtain design parameters. This is followed by the design of a macromodel to determine the feasibility of the design. Finally, the structural and the physical design of the charge-pump P L L under test is presented. 3.1 Introduction A P L L is a feedback control loop circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal both in frequency as well as in phase. The basic architecture of a P L L is shown in Fig. 3.1.1. A phase detector (PD) is used to compare the 16 3. Phase-Locked Loops 17 phase difference between the input signal and the signal generated by a voltage-controlled oscillator (VCO). The phase-difference signal at the output of the phase detector is filtered by a low-pass loop-filter (LPF) to generate the control voltage for the VCO. The P L L is considered to be in 'lock' if the phase error 6t is constant with time, thus resulting in equal input and output frequencies. Reference input Output Figure 3.1.1 The block diagram of a PLL. When the P L L is in 'lock', all the signals in the loop reach a steady state. The operation of the P L L in the 'locked' state is as follows: The output of the phase detector is a dc value which is proportional to 9e (constant phase error). The low-pass loop-filter attenuates the high frequency components of the output of PD, allowing the dc value to control the V C O frequency ^ The VCO, in the 'locked' state, oscillates at a frequency equal to the input frequency and a phase difference of 9C. Fig. 3.1.2 shows the signals at various points of a typical PLL. In this example, assume that the input and the output have equal frequencies but have a finite phase difference. The 3. Phase-Locked Loops 18 PD then generates pulses whose widths are equal to the time difference between the zero crossings of the input and the output signals. The pulses at the output of the PD are filtered by the loop-filter to produce an average dc voltage. This dc voltage controls the V C O frequency. Static phase error (0e) Reference input \ j i i i i i | : : ~ — — : : — V C O output I I I I I I I I 1 PD output LPF output t Figure 3.1.2 Typical waveforms of a P L L . 3.2 PLL applications PLLs circuits are used in a variety of applications including clock and data recovery in transceiver circuits, as tracking filters, phase and frequency modulators and demodulators, and synthesis of accurate frequencies. (i) In digital communication systems, the receiver typically processes the incoming serial data for clock and data recovery. To process the information, the receiver needs a synchronous clock, such that the clock frequency f0 equals the bit rate (baud) fe of the incoming data signal. The process of synchronizing the phase and the frequency of the clock to the data signal is called "clock recovery" [Bes84, W6191]. PLLs are also used 3. Phase-Locked Loops 19 to accomplish clock recovery in applications such as compact disk players, floppy disk readers, and satellite data links. (ii) A P L L can be used as a tracking filter [Bes84]. A tracking filter is a bandpass filter whose center frequency is tuned to the reference carrier frequency. In this application, the P L L is able to continue oscillating even if the reference signal undergoes fading (the signal is lost temporarily from time to time), or the input signal is buried in noise. (iii) A P L L finds its use as a modulator/demodulator in modems [Gar79, Raz96]. The P L L can be used as a communication device for many kinds of modulation, such as amplitude modulation (AM), frequency modulation (FM), phase modulation (PM) or a combination of these. (iv) A P L L is capable of generating frequencies that are integer multiples of a reference input frequency [Enc93, Ega81]. PLLs are widely used as frequency synthesizers in F M receivers, television receivers, and the like. 3.3 General theory of a PLL The transient response of a P L L is generally a non-linear process. Nevertheless, a linear approximation can be used (once the P L L is in the 'locked' state) to understand the basic theory of the P L L design [Raz96, Wol91]. To study the mathematical theory of a PLL, we use a linear model of the PLL. The linear model, illustrated in Fig. 3.3.3, represents a generic phase-locked loop. 3. Phase-Locked Loops 20 G(s) 0M F(s) 1/s e (s) o v 7 Figure 3.3.3 The linear model of a generic P L L [Wol91, Raz96]. In Fig. 3.3.3, kj is the PD gain, F(s) is the frequency response of the loop-filter and kQ is the V C O gain. Let r?,(s) be the phase of the input signal, let 60(s) be the phase of the output signal generated by the VCO, and let 0e(s) be the phase error (or the phase difference signal) between the input signal and the V C O output. The forward path gain of the P L L loop, G(s), is then given by e0(s) kdk0F(s) G(s) (3-1) From the model shown in Fig. 3.3.3, ee(s) = 6i(s) - 0o(s) From Eq. 3.1 and Eq. 3.2 we get (3.2) 0o(s) G(s) 0i(s) 1 + G(s) (3.3) The function j s known as the closed-loop phase transfer function H(s) of the P L L [Wol91]. The 3dB bandwidth of the P L L is determined by the frequency for which \G{jto)\ = 1. From Eq. 3.1, this occurs at the frequency (3.4) 3. Phase-Locked Loops 21 where % is the gain of the loop-filter. For the P L L analysis, the standard notation, k, is used for u U B . , Next, we investigate various response functions of the P L L discussed in this section, i.e., H(s), G(s), and F(s). The example P L L under consideration is based on a simple passive RC loop-filter with one pole and one zero. 3.3.1 Loop-filter The loop-filter considered is shown in Fig. 3.3.4. The filter is a first-order passive RC filter with a pole at u\ and a zero at UJ2. . RI IN(s) A/VV R2 ^7 Figure 3.3.4 A passive loop-filter. OVT(s) The transfer function of the loop-filter is given by lJy(s) s + UJ\ (3.5) where, kh = RI+R2, W2 =• A N C * U L = (RI+R.2)C" T n e t v p i c a l frequency response of this filter is shown in Fig. 3.3.5. At dc, the filter gain is 7 (^0) = 1, and at frequencies greater than OJ2, the gain is k^ The filter acts as an attenuator at high frequencies. 3. Phase-Locked Loops 22 CO, co2 Figure 3.3.5 The frequency response of the low-pass loop-filter. For the example PLL, the gain of the forward path of the P L L is obtained from Eq. 3.1 and Eq. 3.5 as G(s) = k ' + U 2 (3.6) s(s + UJl) where k is the P L L bandwidth and is given by Eq. 3.4. Hence, the closed-loop transfer function of the second-order P L L is given by TT, . ks + ku2 H ( s ) = - 5 — n —;— (3-7) The frequency response of the forward path gain, |G(ju;)| and the closed-loop P L L response, H(s) are plotted in Fig. 3.3.6. 3. Phase-Locked Loops 23 Gain (dB) Open-loop response( |G(ja>)|) Figure 3.3.6 Open and closed-loop responses of the P L L . To obtain the 3dB bandwidth of the PLL, it was assumed that \F(juj)\ m k^ when UJ = k. But from Fig. 3.3.5, \F(JUJ)\ k^ only for UJ > UJ2. Therefore, we require that UJ2 be less than k. Next, we see the effect of UJ2 on the response \H(JUJ)\ for the PLL. Let us assume LO\ « k. Then, by neglecting UJ\, H(s) can be rewritten as ks + ktU2 H(s) s2 + ks + kuj2 Eq. 3.8. can be expressed in terms of a damping ratio £ and a natural frequency ujn as, (3.8) s2 + 2(ujns + co2 (3.9) where ( = 0.5y^-, w n = ^ku2. Let the frequency for which |/J(s)| is a maximum be referred to as the peaking frequency UJ?. By setting (-£j)\H(JUJ)\2 = 0 and then solving for UJ, we get UJp = UJ2 k 2— + 1 UJ2 (3.10) 3. Phase-Locked Loops 24 Let the value of \H(ju>)\ at the peaking frequency be H p . This gives Hn= 11 - 2a - 2a2 + 2a{2a + a2)- (3.11) where a = jr.. Let us now investigate LOP and H p for the three damping cases: over-damped, critically damped and under-damped. The corresponding approximate values for various parameters are listed in Table 3.3.1. Damping u2lk Hp Over < 0.25 1.2u3/42km l+cv2/k Critical = 0.25 1.4u>2 1.15 • Under > 0.25 (kw2)m (to2/k)m Table 3.3.1 Approximate values of uip and Hp for three damping cases. To study the correlation between the ratio u2/k and the P L L response, we see the effect of some selected dampings on the P L L step response. Fig. 3.3.7 shows the plot of the step response of the example P L L for (i) u2=0 (over-damped), (ii) to2-k/4 (critically damped), and (iii) c u 2 = / c (under-damped). The step response of the P L L is plotted for the normalized values of k. 3. Phase-Locked Loops 25 1.8 0 0.1 0.2 0.3 0.4 0.5. 0.6 0.7 0.8 0.9 1 Time (sees)—> x Figure 3.3.7 Step response of the P L L . The responses were plotted using M A T L A B [Mat94]. Note that as OJ2 gets closer to k, the amount of overshoot increases. From the various step responses it appears that in order to make the system stable u2 should be as low as possible [Wol91, Bes84]. This slows the response but makes the P L L system very stable. But, since u>2 = TRYJC' m a ^ n 8 w 2 small requires a large capacitor. A large capacitor would take a longer time to charge during the lock acquisition. Hence, in cases where peaking is not an important factor, OJ2 can be chosen as k/4, assuring fast acquisition. Such a P L L is critically damped. Another important parameter of a P L L is the pull-in time. The pull-in time is defined as the time required by a P L L to acquire 'lock' from a given initial frequency difference [Wol91, 3. Phase-Locked Loops 26 Bes84]. The pull-in time of all second-order PLLs can be approximately given by [Bes84]: ALO2 1P ~ O A ,3 (3.12) where ALJ0 is the initial difference between the input and the output frequencies. 3.4 Charge-pump PLLs A charge-pump P L L was designed as the circuit-under-test. In this section, we present the general theory of a charge-pump PLL. The architecture of the P L L is shown in Fig. 3.4.8. A charge-pump P L L consists of four major blocks: (i) the phase/frequency detector (PFD), (ii) the charge-pump circuit, which transforms the digital U and D signals into analog voltages, (iii) the loop-filter, which attenuates the high frequency components from the analog voltage generated by the charge-pump, (iv) the V C O , which generates a clock whose frequency is controlled by the control voltage which is generated by the loop-filter. Reference input _TLn_r R U PFD V D Charge pump Loop Filter V C O output Figure 3 .4.8 Basic architecture of a charge-pump P L L . 3. Phase-Locked Loops 27 The charge-pump P L L incorporates the charge-pump circuit and the loop-filter in order to convert the logic states of the PFD into analog signals thereby making them suitable to control the oscillation of the VCO [Gar90]. The combination of the PFD and the charge-pump offers two important advantages [Raz96, Wol91, Bes84]: . (i) the range over which the P L L can lock to the input frequency is only limited by the VCO output frequency range. (ii) the static phase error is zero. The following describes the working of the various building blocks of the charge-pump P L L in detail. 3.4.1 Phase/frequency detector The PFD is a 3-state statermachine triggered by the trailing edges of the input signals R and V, where R is the reference input to the PD and V is the VCO output [Bes84]. The state diagram of the PD is shown in Fig. 3.4.9 [Pae94J. As illustrated in Fig. 3.4.9, the PD has three valid states encoded by two flip-flops U and D. The state U=D=1 never occurs. At the trailing edge of the signal R (R|), one of three changes can occur: (i) Transition from state 1 to state 0, i.e., reset of'D; (ii) Transition from state 0 to state 2, i.e., set of U ; (iii) No change occurs and the. output remains in state 2. At the falling edge of V (Vj), transitions take place in a similar way. Waveforms showing the working of the PFD are shown in Fig. 3.4.10. From Fig. 3.4.10, U is used to increase, and D used to decrease the frequency of the signal V. 3. Phase-Locked Loops 28 R U D (a) (b) R n _ _ i u D u D i J—1 (c) . . (d) Figure 3.4.10 The operation of the phase/frequency detector. 3. Phase-Locked Loops 29 In Fig. 3.4.10(a), R input phase leads the V input phase. A falling edge of R sets the U output terminal true. The next falling edge of V input signal resets the U output terminal false. As long as R leads V, the D output signal remains false. In Fig. 3.4.10(b), the R input phase lags behind the V input phase, then a falling V edge sets D true and the next falling R edge resets D false. As long as R lags behind V, the U output signal remains false. The PFD has three allowable states: both U and D signals can be false simultaneously, or, either one alone can be true, but both cannot be true simultaneously. In Fig. 3.4.10(c), R leads V, then a falling edge of R sets U signal. The TJ signal remains set until a falling edge of signal V occurs which resets the U signal. The next falling edge of R again sets the U signal. The D signal remains inactive as long as R leads V . Conversely, in Fig. 3.4.10(d), R lags V, a falling V edge sets D. The D signal remains set until a falling edge of signal R occurs, which resets the D signal. The next falling edge of V again sets the D signal. The TJ signal remains inactive. When both the TJ and D signals are inactive, the charge-pump/loop-filter circuit generates a free-running voltage Vd 0 , which is v corresponding to 6&=0. When the P L L 'locks' to the desired frequency, there is no activity in the TJ and D signals, and v is the analog voltage generated at the output of the charge-pump/loop-filter circuit. Fig. 3.4.11 shows the phase characteristic of the PFD. The average of the output voltage generated by the PD (V o u t) is plotted against the phase error 6>e. The slope of the characteristic is given by the PD gain, k^. 3. Phase-Locked Loops 30 Voutf - 2 7 C 2TC ee Figure 3.4.11 The phase characteristic of the PFD. 3.4.2 Charge-pump circuit The charge-pump consists of two switches controlled by the three states of the PFD encoded through outputs U and D. The basic architecture of the charge-pump is shown in Fig. 3.4.12(a). The functioning of the charge-pump is shown in Fig. 3.4.12(b). When the switch U is closed, a voltage V D D is delivered to the node v^, which is the output of the charge-pump, and when the switch D is closed, the node is connected to the GND. When both U and D are open, the loop-filter is isolated from the PFD and the voltage v ( free-running voltage generated by charge-pump/loop-filter circuit) appears at the output of the charge-pump. 3. Phase-Locked Loops 31 6 u u D 6 D V 0 ^7 (a) (b) Figure 3.4.12 Functioning of the charge-pump circuit. 3.5 Design of the PLL circuit-under-test To study the effectiveness of power supply current monitoring test techniques, we designed a 155MHz charge-pump PLL. The design was performed in three major steps: a) mathematical analysis to obtain design parameters, b) behavioral modeling for the initial verification of the design parameters (obtained in step a), and, c) final structural design. The physical design was also done as a part of the structural design. The following describes the mathematical analysis and behavioral modeling as parts of the initial study, followed by a description of the detailed design. 3.5.1 Feasibility A mathematical analysis based on the principles described in previous sections was performed in order to determine the design parameters. The analysis was performed using 3. Phase-Locked Loops 32 M A T L A B . The mathematical analysis was followed by the behavioral modeling of the PLL. It is a common practice to create behavioral models for digital circuits before performing an actual circuit-level implementation. However, behavioral modeling of analog and mixed-signal circuits is relatively new and uncommon due to the lack of adequate design tools. In our case, we found that the design could be adequately modeled by using the available C A D tools. Hence, a mixed-signal behavioral model was created, as described later in this section. 3.5.1.1 Simulation To obtain the design parameters we first need to choose the PFD gain, the V C O gain, and the bandwidth of the PLL. (i) The desired P L L frequency is 155 MHz. Hence, the center frequency of the V C O was chosen to be 155 MHz. (ii) We choose a sequential 3-state type of PFD due to its wide linear range. As shown in Fig. 3.4.11, the slope of the phase characteristics is the gain kj. In our case, VDD=5V and GND=0V. Hence, we get k d = 2 ^ 2 w ) =0 .38 V/rad. (iii) In order to achieve a fast lock acquisition, a high gain V C O was designed. The V C O gain was. arbitrarily chosen to be 190 MHz /V . (iv) A low gain loop-filter is desirable to highly attenuate the high frequency components of the signal generated by the phase detector. Therefore, the loop-filter gain was arbitrarily chosen to be 0.003. Next, we calculate the design parameters of the loop-filter. The passive filter discussed earlier, and as shown in Fig. 3.3.4, is used. We know from Section 3.3.1 that the loop-filter 3. Phase-Locked Loops 33 gain is given by, h = mTT2' ( 3 - 1 3 ) where = 0.003. We arbitrarily choose RI = 60 kf). The Eq. 3.13 can be rewritten as, R2 - hK 1 ' (3.14) . 1 - h On substituting the values of kh and R2 in Eq. 3.14 we obtain, 112 = 175 o (3.15) From Eq. 3.4, the 3dB bandwidth of the P L L is given by, k = khk0kd (3.16) On substituting.the values of kh, kj and kQ in Eq. 3.16 we get, k = 13.81 Mrad/s (3.17) As mentioned earlier, it is desirable to design PLLs with over-damped parameters for stability reasons. Hence, the required relationship between the loop-filter zero (UJ2) and k is given by < 0.25 [Table 3.3.1]. Therefore, we choose UJo y = 0.2 . (3.18) Hence, from Eq. 3.17 and Eq. 3.18 we get, UJ2 = 2.85 Mrad/s (3.19) 3. Phase-Locked Loops 34 .Also, u>2 is given by L02 {R2)C (3.20) On substituting the value of LO2 and R2 in Eq. 3.20, we get C = 200 PF (3.21) Thus, we obtain all the design parameters for the PLL. Next, we confirm the calculation of these parameters through M A T L A B simulations. The step response of the P L L is shown in Fig. 3.5.13. From the step response we can see that the system is over-damped (HP<1.15) and hence stable. Hp= 1.118 ' 0 Figure 3.5.13 The step response of the P L L circuit-under-test. 0 0.1 0.2 0,3 0.4 0.5 0.6 0.7 0.8 0.9 Time (sees) x 10 -6 The frequency response of the loop-filter is shown in Fig. 3.5.14. The open loop response of the P L L circuit-under-test is shown in Fig. 3.5.15. The closed-loop response of the P L L circuit-under-test is illustrated in Fig. 3.5.16. From the closed-loop response we see that the peaking is not very high and the system stable. 3. Phase-Locked Loops 35 F(s) frequency(Hz)—> Figure 3.5.14 The filter response of the P L L under test. 3. Phase-Locked Loops 36 Next, we calculate the pull-in time of the P L L using the parameters obtained in this section. The initial frequency difference is arbitrarily chosen as 5 MHz. From Eq. 3.12, the pull-in time Tp is given by (2TT x 5 x 1 0 6 ) 2 Tv « ^ • =• = 1.82 us (3.22) 2 x 1.1 x ( 6 . 2 7 x 1 0 6 ) 3 where ujn = \f(/cu^) = 6 . 2 7 Mrad/s and ( = = 1-1. 3.5.1.2 Behavioral model PLLs used in applications, ranging from data recovery in communication systems to clock synthesis in digital systems, have varying implementations. They can be implemented as all-analog systems, mixed analog-digital systems or all-digital systems. Commonly used P L L architectures have digital inputs and outputs but have intermediate analog signals. In order to verify the correct operation of a PLL, i.e., whether the P L L 'locks' to a desired frequency, a complete mixed-signal simulation is essential. However, a complete P L L simulation is often excessively time consuming due to two major reasons [Ant93]: (i) P L L systems are a form of feedback control loop and involve mixed analog-digital signals, (ii) a large number of clock cycles need to be simulated to ensure correct operation. For example, consider a 155 MHz (6.43 ns time period) frequency PLL, simulation of such a circuit requires a time step on the order of 6.43 ns in order to provide adequate resolution in the output. Let us assume that the pull-in time of the P L L is 10 ms, then the circuit must be simulated for g ^ ^ o - a = 1 .55 x 106 points. 3. Phase-Locked Loops 37 The use of conventional circuit simulators such as SPICE can deal with the mixed-signal nature of the PLL, but results in impractical simulation times. To overcome these drawbacks, attempts have been made to simulate PLLs at a behavioral level [Can88]. These attempts were based on developing a stand-alone simulator for specific PLLs. The drawback with this approach is that normally one would like to incorporate device level components in the design which cannot be simulated by such a stand-alone simulator. To eliminate the problem of impractical simulation run times, our approach is to use mixed-level behavioral models that represent the essential characteristics of the PLL. Also, we simulate these models in the mixed-signal simulator framework "SpectreSVerilog" which allows mixed-signal and multilevel simulation and thus makes 'locking' simulations both fast and practical [Spr94, Ver90]. The SpectreSVerilog simulator runs SpectreS on the analog blocks and Verilog on the digital blocks. The SpectreS is an analog simulator that performs circuit-level or behavior-level verification of the design. The Verilog digital logic simulator is a software tool that performs functional verification of a design and identifies design errors. The Verilog simulator can simulate logic-level, switch-level or behavioral-level design. The block diagram of the-behavioral model of the P L L under test is shown in Fig. 3.5.17. 3. Phase-Locked Loops 38 Figure 3.5.17 The block diagram of the behavioral model of the P L L . The P L L is modeled by partitioning the circuit into the following major functional blocks: (i) The 3-state phase/frequency detector was modeled using Verilog. The state diagram of the PFD is shown in Fig. 3.4.9. The state diagram was explained in Section 2.4.2.2.1. A direct state diagram implementation was done using Verilog. The Verilog code is given in Fig. 3.5.18. 3. Phase-Locked Loops 39 module pd_model(R, V, U,D); input R, V; output U,D; regsO,sl,s2,U,D; initial begin U=0;D=0;sO=l;sl=0;s2=0; end always @(posedge R or posedge V) begin fork @ (posedge V) begin if(sl ==l) begin sl=0;sO=l;U=0;D= 0; end else if(sO==J) begin sO=0;s2=l;U=0;D= I; end else if(s2= = l) begin s2=l;U=0;D=l; end end @ (posedge R) begin if(sO==l) begin sO=0;sl=l;U=l;D= 0; end else if(sl= = l) begin U=1;D=0; end else if(s2==l) begin s2=0;sO=l;U=0;D= 0;end end join end endmodule Figure 3.5.18 Verilog code for the PFD model. (ii) The first-order passive loop-filter was implemented with passive components i.e., resis-tances and capacitances. (iii) The charge-pump switches were implemented using two ideal MOS transistors (switches). (iv) The V C O was modeled using the analog hardware description language (AHDL) [Spt94]. 3. Phase-Locked Loops 40 The underlying concept is to implement the basic equation of the V C O through A H D L . The basic equation is given by [Can88], ;' Vout = A * sin (2 * vr * (-/c + k0 *Vin)), . (3.23) where/ c is the center frequency of the V C O and k0 is the V C O gain. The A H D L code is given in Fig. 3.5.19. #define PI 3.141592 module vco(in, out) (amplitude, centerJreq, vco_gain) node [V, I] in, out; parameter real amplitude = 1; parameter real center_freq = 155M; parameter real vco_gain = 190M; I analog V(out) <--- amplitude*sin(2*PI*(center_freq*$time() + integ(vco_gain*V(in), 0))); I Figure 3.5.19 AHDL code for the VCO model. The key parameter values used in the simulation are (i) *y=0-38 V/rad (ii) Rl=60 kQ (iii) R2=175 Vl (iv) C=200 pF (v) fc = V C O center frequency=155 MHz (vi) fco=190 MHz/V 3. Phase-Locked Loops 41 In the simulation a fixed reference frequency signal of 155 MHz was applied at the input of the P L L and the P L L was simulated to verify its acquisition characteristics. In order to verify the acquisition characteristics of the behavioral model of the PLL, we focus on the pull-in time parameter. According to mathematical calculation is Section 3.5.1.1, Eq. 3.22, the pull-in time of the P L L is expected to be 1.82 /is for an initial frequency difference of 5 MHz. The behavioral model of the P L L was simulated with an initial voltage of 2.6 V on the loop-filter capacitor. This initial voltage causes the V C O to oscillate at 150 MHz, thus providing an initial frequency difference of 5 MHz between the input and the output frequency of the P L L model. It was observed that the pull-in time for the behavioral model is 1.91 fxs. This is within 5% of the calculated value of the pull-in time. Hence, it is verified that the behavioral design matches the calculated parameters. The output of the phase detector, the charge-pump and the loop-filter are shown in Appendix C, Fig. C . l . Both the Reference input and the V C O output in the 'locked' state are shown in Appendix Q Fig. C.2. 3.5.2 Structural design Next, the implementation of the charge-pump P L L is presented. The PFD is designed at the gate level. The charge-pump and the V C O are designed at the transistor level. The loop-filter consists of only passive elements. 3.5.2.1 Phase/frequency detector (PFD) The phase detector (PD) used for the P L L is a 3-state phase/frequency detector. The gate-level schematic of the PFD is shown in Fig. 3.5.20. This type of PFD has a range of - 2 7 r to + 2 7 T . The gain, kd, of this type of PD is given by ^ f 2 - . In our case, the gain, kd, 3. Phase-Locked Loops •42 is 5/47T = 0.38 V/rad. The device is basically built from two RS latches and two additional RS latches, which have been designated U and D, respectively. The PFD consists of two reset signals to initialize the latches. Reset signal, Reset_Jii_lo is initialized to logic 1 in order to initialize the U latch. The signal is returned to logic 0 after 100 ns. Reset signal, Reset_lo_hi is initialized to logic 0 in order to initialize the D latch. The signal is returned to logic 1 after 100 ns. The operation of the PFD is briefly described below: • If the signal V has the same frequency as the signal R but is lagging R in phase, the output of the U latch is pulsed in proportion to the phase error. The D latch is in its inactive state. • If the signal V has the same frequency as R, but is leading R, the input of the D latch is pulsed in proportion to the phase error, and the T J latch remains inactive. • If the frequency of signal R is greater than the frequency of the signal V , the TJ latch is pulsed, and the D latch stays inactive all the time. • If the frequency of signal V is greater than the frequency of the signal R, the D latch is pulsed, and the TJ latch stays inactive all the time. The output of the PFD is shown in Fig. C.3. 3. Phase-Locked Loops 43 R + v »-u Figure 3.5.20 PFD Schematic. 3.5.2.2 Charge-pump and Loop-filter The charge-pump consists of two MOS switches controlled by the 3 states of the PFD. The transistor level implementation of the charge-pump along with the passive loop-filter components is shown in Fig. 3.5.21. The working of the charge-pump is as follows: (i) If U and D are high, then the transistor M l is in its cut-off region since Vin > Vdd —\Vtp\ and the transistor M2 is on since V[n > Vtn. Hence, the node is connected to GND. (ii) If U and D are low, then the transistor M l is on since Vin. < Vdd — \Vtp\ and the transistor M2 is in its cut-off region since Vin < Vtn. Hence, the node vd is connected to Vdd-(iii) If U is high and D is low, then the transistor M l . i s in its cut-off region since Vin > Vdd - \Vtp\ and the transistor M2 is in its cut-off region since V{n < Vtn. Hence, the voltage across the node Vd is equal to the voltage developed across the capacitor (C). The output of the charge-pump and the loop-filter is shown in Fig. C.3. 3. Phase-Locked Loops 44 vdd Figure 3.5.21 The transistor level implementation of the charge-pump with the passive loop-filter. 3.5.2.3 Voltage-controlled oscillator (VCO) For our P L L design, we use a voltage-controlled oscillator based on a ring oscillator topology [Joh88]. The basic design of a ring oscillator consists of a cascade of M gain stages with a total phase shift of 180°, placed in a feedback loop. The V C O starts oscillating when there is a net inversion around the ring. A basic 3-stage ring oscillator is shown in Fig. 3.5.22. Delay Control 11 ^ Figure 3.5.22 A three-stage ring oscillator. 3. Phase-Locked Loops 45 In order to vary the frequency of oscillation, either the gate delay or the number of the gain stages should vary. In our design, we use the first approach, i.e., varying the gate delay. The frequency of oscillation (four) is given by where dl, d2, d3 are the gate delays of the three inverter stages. The V C O characteristic, or, the control voltage versus the frequency (V-f) characteristic, plays an important role in V C O design. A linear characteristic is desirable since it minimizes the V C O sensitivity (characteristic slope) variation as a function of the control voltage of the V C O . Also, it provides P L L stability over a wide frequency range [Joh88]. A maximum operating frequency is achieved at a maximum control voltage. This frequency is limited by the maximum VDD applied to the circuit. The desired V C O characteristic is shown in Fig. 3.5.23. The V C O was designed for a gain of 190 MHz /V . four 1 2(dl + d2 + d3) (3.24) f Slope = Gain of .VCO (k0) V c (VCO control voltage) Figure 3.5.23 The desired V C O characteristic. 3. Phase-Locked Loops 46 The V C O schematic is shown in Fig. 3.5.24. The V C O consists of three inverter stages with a buffered output. Transistors M3, M4, M5, M6, M7, M8, M i l , M12, M13, M18, M19, M20 form the three inverter stages. Transistors M14, M15, M9, M10 form the inverting buffer stages. The n and p transistors were sized to achieve equal rise and fall times in the output waveform. The control voltage V j n , sets the current in the n current source M l and the current source M2. The current is mirrored by transistors M16 and M17 [Wes85]. The delay through the inverter stages is controlled by the drain current through the transistors M3, M4, M5, M18, M19 and M20 which, in turn, is controlled by the drain current of transistors M17 and M2. l! M16 , » J M17 _ M11 _ J M12 - J M 1 3 H E HE . r f HE HE 4 HE M 9 HE Buffer stages Inverter stages Figure 3.5.24 The V C O schematic. VCO Output j The control voltage V i n is applied to a series connected delay element [Geo87]. This voltage V i n can "current starve" an inverter. The drain current in M l is mirrored by a 3. Phase-Locked Loops 47 current mirror (formed by transistors M16 and M17) to the drain of transistor M2. Hence, the control voltage V ; n modulates the ON resistance of the pull-up transistors M18, M19 and M20. Also, the drain current in M l 7 is mirrored by transistors M2 and M3 to the drain of M3. Hence, V ; n modulates the ON resistance of the pull-down transistors M3, M4 and M5. These variable resistances control the current available to charge and discharge the load capacitance on each inverter stage. If the control voltage V ; n is large, then a large current will flow, producing a small resistance and thus a small delay. The V C O was simulated for various values of the control voltage V j n and corresponding frequency at the output was measured for each case. Fig. 3.5.25 shows the V- f characteristic of the VCO. The V C O has a center frequency of 155 MHz (for an input dc voltage of 2.635V) and a gain of k0 =190 MHz/V over a range of 2.3V to 3.8V input voltage. The output of the V C O and the reference clock are shown in Fig. C.4 in the locked state of the PLL. 400 r ^ — , r— , T , , VCO control voltage —> Figure 3.5.25 The V C O characteristic. 3. Phase-Locked Loops 48 3.5.3 Physical design The physical design of the charge-pump P L L was created in a 0.8 fim BICMOS NT process [Bic93] provided by Canadian Microelectronics Corporation (CMC). As discussed earlier, the charge-pump P L L consists of digital and analog circuitry. The layout of the phase-detector was created using the standard cell layout from the BICMOS 'tcells' library [Bic93]. The layout of the analog blocks, i.e., the V C O and the charge-pump were created manually. The V C O and the charge-pump layouts are shown in Fig. B.2 and Fig. B.3 respectively. The passive components constituting the loop-filter are external to the IC and hence not laid out. Fig. 3.5.26 shows the floorplan of the P L L chip. The placement of various blocks was performed manually. The routing of the interconnect lines was done automatically using the Cadence Place and Route tool [Cad94]. The final layout of the P L L chip is shown in Fig. B . l . • • |—| |—| |—| CP - Charge_pump | j - ICpads Figure 3.5.26 The floorplan of the P L L chip. The overall, size of the P L L chip is 2.88 sq. mm. The core area is 0.25 sq. mm. The V C O area is 0.10 sq. mm, the PD area is 0.14 sq. mm and the charge-pump area is 0.01 sq. mm. 3. Phase-Locked Loops 49 Post-layout verification of the design was performed in three stages: (i) design-rule-check; (ii) layout-versus-schematic check; and, (iii) simulation of the 'extracted' circuit. The Diva verification tool [Cad94] was used to perform the design-rule-check (DRC) to verify that the layout conforms to the 0.8 /im BICMOS technology design rules. Such design rules include aspects such as minimum transistor sizing, separation between various metal and poly layers, minimum metal/poly widths etc. The DRC performs various checks ranging from single layer, single dimension checks, to multilayer, and multidimensional checks. The comparison between the layout and the schematic was performed using layout-versus-schematic (LVS) program from Cadence [Cad94]. In our case, the layout-versus-schematic (LVS) program, was used to compare the structural and physical design of the P L L and isolate any differences between them. The LVS program compares two schematics, a schematic and a layout or two layouts for structural similarity. The final verification of the layout was done by simulating the 'extracted' version of the layout. The Diva verification tool was used to 'extract' the layout to a SPICE level netlist. This netlist was simulated using SpectreS simulator. The P L L was simulated with an initial voltage of 2.5 V at the loop-filter capacitor. The pull-in time was observed to be 49.2 ^s. The voltage at the loop-filter capacitor in the 'locked' state was found to be 2.64 V. This is within 1% of the result obtained from simulating the schematic for which this voltage is 2.635 V. Chapter 4 Power Supply Current Testing of the PLL Circuit-Under-Test In this chapter, we present power supply current testing of PLLs. A fault-model-based test approach is used to evaluate the effectiveness of a common production testing method versus a power supply current monitoring approach. Recognizing that due to manufacturing tolerances, the signals in analog and mixed-signal circuits are not single nominal values, but are rather, random variables, a Monte Carlo analysis is performed in order to take into account the variations in the process parameters. In addition, an approach to test the digital components of a mixed-signal P L L circuit, using analog power supply current, is presented. Methods for improving the fault simulation time, and subsequent speeding-up the task of test generation are presented. 4.1 Fault model The fault coverage for the P L L under test was investigated on the basis of the following catastrophic [Cam92] fault model: (i) The conventional single 'stuck-at' fault-model is used for the digital sub-circuits (in our case the phase detector). The 'stuck-at' fault model is described in Chapter 2. This fault model is chosen because it is the most widely accepted fault model for digital circuits [Wes85, Ism94]. 50 4. Power Supply Current Testing of the PLL Circuit-Under-Test 51 (ii) A transistor-level fault model is used for analog sub-circuits, i.e., the V C G and the charge-pump [Cam92]. For each MOS transistor in the analog subcircuit, the following faults are considered: (a) Gate to drain shorts; (b) Gate to source shorts; (c) Drain opens; (d) Source opens. The above fault model is chosen because it is a commonly-used fault model for MOS transistors in analog circuits [Eck93]. The fault model is illustrated in Fig. 4.1.1 [Cam92]. The shorts are modeled by a 100 'shunt' resistance (Rs), and the opens are modeled by a 10 MO resistance (Ro). The above values of Ro and Rs are chosen since they are commonly used for catastrophic fault modeling [Cam92]. The switches shown in Fig. 4.1.1 are ideal. With this fault model, there can be 65 different faults to be considered in the V C O circuit D Ro = l O M f i Rs= lOOfl Figure 4.1.1 MOS transistor fault model [Cam92]. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 52 and 8 different faults in the low-pass loop-filter circuit. We assume the occurrence of a single fault at a time. A l l repeated faults are eliminated from the fault list. For example, in Fig. 3.5.24, open drain in transistor M3 is same as source open in transistor M6. Therefore, only one of them is considered in the fault list. 4.2 Test techniques We propose two power supply current (Idd) test techniques for PLLs and compare their effectiveness, when applied to our PLL, to that of a "functional test". 4.2.1 "Operating" Id d test Power supply current testing in the form of quiescent power supply current (Id q) testing has been successfully used for the testing of digital circuits [Gul93]. This technique relies on the fact that when a CMOS logic gate is not switching, it draws negligible amount of dc current. In the presence of a fault, for some specific stimulus, this current is raised to abnormal levels and by measuring this current, a fault can be detected. One limitation of this technique is a long test time since the test vectors need to be applied for a relatively long duration of time to diminish the effects of parasitic capacitance in a device under test. Another form of power supply current testing is the "operating" power supply current testing. An "operating" Idd test is carried out by measuring the power supply current during the normal operation of the CUT. We propose to use the "operating" Idd for the testing of PLLs. In this study, we propose to monitor the operating power supply current drawn by the P L L circuit in its normal mode of operation ('locked' state). Since, the testing is done 4. Power Supply Current Testing of the PLL Circuit-Under-Test 53 at the normal rate of operation, the test can be executed at a higher speed as compared to I d d q testing. Our method relies on the assumption of having a separate power supply for the analog portions of mixed-signal ICs. This can be safely assumed because most mixed-signal ICs use separate power and ground pins for digital and analog circuitry to avoid noise coupling [Agr96]. We propose to monitor the analog power supply current for the detection of all faults in the PLL, including the digital sub-circuit of the PLL, in this case, the phase-detector. The P L L circuit shown in Fig. 3.4.8 was simulated with a fixed clock at the reference clock input of the P L L for each fault. In actual applications, this reference clock would be provided by a crystal. The expected output frequency of oscillation of the P L L was 155 MHz. The "operating" power supply current for the P L L was found to be oscillatory in nature. Hence, the root-mean-square (rms) value of the "operating" Idd was recorded for each faulty case, such as stuck-at faults for the PD, and transistor-level faults for the V C O and the charge-pump. In our case, we chose the window of measurement as 100 ns. The desired output frequency is 155 MHz in the fault free case by the virtue of the design. This results in a time period of 6.43 ns for one clock cycle. By having a sufficient number of clock cycles ("20 in this case) we can average out errors due to an insufficient number of sample points, which might occur if we take the rms value of current for only one clock cycle. In actual applications, the window of operation will also depend on the timing specifications of the ATE. It is vital to take parametric variations into account to find an acceptable tolerance band on the current. The effect of the variations in the fabrication process are random in 4. Power Supply Current Testing of the PLL Circuit-Under-Test 54 nature. These random variations in the fabrication process result in random variations in transistor parameters. These variations arise due to the drift in fabrication equipment with time, resulting in variations in the values of transistor parameters, or, due to gradients in implantation density and thereby causing the parameters of an individual die to be dependent on the relative placement of the die on a wafer. With the aid of statistical tools, these variations can be quantified. Next, we explain the process of quantifying these variations through statistical modeling. 4.2.1.1 Statistical modeling For the purpose of statistical modeling, the variations in transistor parameters can be lumped together as "interdie" parameter variations [Ism94]. Assume that the transistor parameters are normally distributed. Then, the "interdie" variations of any parameter is completely characterized by its variance and the mean value for the entire process [Ism94]. The random process variations can also cause mismatch between two equally sized transistors on the same die. These variations are termed as "intradie" variations and can be the result of variations in gate oxide thickness. Both "interdie" and "intradie" process variations can be modeled through Monte Carlo simulations with independent process parameters, such as threshold voltage, gate oxide thickness, etc. [Ism94]. The Monte Carlo simulation is a technique whereby a random (statistical) exploration of a component space is performed [Spe88]. For circuit simulation, a set of process parameters are chosen. Table 4.2.1 gives the list of the model parameters chosen for Monte Carlo simulation. These model parameters are chosen since they are the commonly used model parameters [Mil89]. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 55 Table 4.2.1 Device model parameters. Model Parameters Symbol 3(7 1 Oxide thickness Tox 10% 2 Substrate doping NSUB 10% 3 Substrate mobility Mo 10% 4 Threshold voltage V T O 10% 5 Junction depth Xj 10% 6 Transistor width W 5% 7 Transistor length L 5% The process parameters were modeled with Guassian random, variables, with variances of 3CT=10% for the device model parameters, and 5% for the geometric sizes of the MOS transistors [Wan94]. The accuracy of Monte Carlo simulations of integrated circuits depends on the generation of correct probability distributions of the random values of transistor parameters. For a large number of samples (~1000), the sample mean and variance is close to the parameter's actual mean and variance [Ism94]. For each simulation, random values are generated for each device model parameter. To account for variations in the parameters, a netlist description of the V C O is taken, and a set of 1000 time-domain Monte Carlo simulations are performed on the VCO. The V C O is simulated for a fixed dc input voltage (2.635V) and the "operating" Idd is recorded for each sample. The mean and standard deviations thus obtained are used for determining the detection threshold for the "operating" Idd test. 4.2.2 "Non-operating" Idd test 4. Power Supply Current Testing of the PLL Circuit-Under-Test 56 In order to achieve a higher fault coverage than the "operating" Idd test, for the V C O block, we investigate another current test technique in the form of a "non-operating" Idd test. In many cases the loop-filter components of the P L L are external to the IC. In such cases, we have control over the. input terminal of the VCO. In cases where one does not have control over the V C O input, this test cannot be performed. To perform the "non-operating" test, we excited the faults by the application of a dc voltage at the input of the V C O and a "non-operating" (no oscillation) state was achieved by reducing the input voltage to zero. This operation is partially similar to the I d d q test for digital circuits. For the I d dq test of a faulty node, the node must be toggled by the application of a suitable test vector. The fault is 'excited' during the transition and causes a higher Iddq to flow. This current is observed while the circuit is kept dormant. In our case, we toggle the nodes (and hence excite the circuit) by applying the dc control voltage to the VCO. This concept is illustrated in Fig. 4.2.2. This technique is the 'reverse' operation of the "operating" I d d in which the V C O is initially dormant and is later excited. In practical realization one would operate the V C O for a predetermined amount of time that is considered sufficient for bringing the V C O in its normal mode of operation before reducing the control voltage to zero in order to achieve the 'quiescent' state. This time period would depend on the V C O circuit and the design parameters. For example* VCOs running at lower frequencies would need a larger window to accommodate sufficient number of clock cycles. However, for the purpose of fault simulation, we need to operate the V C O for a shorter time since our V C O achieves the steady state is a very short period of time. During simulation, we apply a predetermined control voltage to the V C O input after 20 ns and reduce it to zero after 120 ns. In our 4. Power Supply Current Testing of the PLL Circuit-Under-Test 57 case, the V C O achieves the steady state in 10 ns after the application of the control voltage and hence 100 ns is sufficiently long time to perform the operation. The rms value of the "non-operating" current is recorded for the fault free and the faulty cases. V C O output VCO input voltage (EXTERNAL) "Operating" state "Non-operating" state Figure 4.2.2 "Non-operating" I d d test for the VCO. 4.2.3 "Frequency-lock" test A common application of PLLs is to generate appropriate clocks. This implies that frequency measurement is an important functional test for PLLs. The "frequency-lock" test is the most commonly used functional test for PLLs [Sto96]. A "frequency-lock" test is a basic P L L functional test in which the output frequency of a P L L is observed for a particular input reference frequency in the 'locked' state. Therefore, in this study, we use the "frequency-lock" test as a basis for a comparative analysis between the functional and the power supply current test technique for the PLL. Other common functional tests for a P L L are locking time, locking frequency range and capture frequency range, but we do not consider them in this thesis because in most cases they are difficult to implement on commercial ATE. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 58 4.2.3.1 Conventional frequency testing methods The following describes different conventional approaches used for measuring the output frequency of P L L circuits for test purposes. . 4.2.3.1.1 External counter (Non-ATE) An external counter is used to measure the output frequency of the circuit-under-test [Sto96]. The frequency is measured by counting signal transitions over a fixed period of time. In order to increase the accuracy, the gating time needs to be increased at the expense of the throughput. This type of frequency measurement suffers from a slow test speed. 4.2.3.1.2 Using automatic test equipment (ATE) resources The frequency measurement techniques using ATE resources can be further classified as: (i) Zero crossing method - A simple way of frequency measurement is to count.0-to-l transitions in the tester's memory [Sto96]. The measured frequency is / = £ , • ' (4.1). where, N is the total number of detected transitions and f# denotes the total time during which N transitions occur. The time tN is limited by the length of the tester's memory. Also, the strobe distances are given by the tester period. Hence, for high speed and accurate frequency requirements, this might result in limited applicability. (ii) Time domain parameter estimation - A software approach to perform frequency mea-surement has been proposed in [Sto96]. In this approach, the P L L is stimulated and at the same time the stimulus is fed to a model. An algorithm is used to compare the 4. Power Supply Current Testing of the PLL Circuit-Under-Test 59 outputs of the P L L under test and the model and error signal is derived. This frequency measurement technique is dedicated to the HP8300 F660. 4.2.4 Simulation issues Fault simulation is one of the most popular methods to determine the effectiveness of test techniques and to distinguish defective circuits from good circuits for digital circuits. However, fault simulation for mixed-signal circuits in general, and P L L circuits in particular, is very cumbersome. The fault simulation of P L L circuit tends to be a major bottleneck due to the following reasons: (i) The respionse of a P L L circuit prior to locking is highly non-linear and therefore difficult to evaluate. The system parameters used to characterize the P L L are usually assumed to be linear, which is valid, once the P L L locks. Hence, a closed-loop simulation of the P L L is essential to discriminate the good circuits from the faulty ones. (ii) The mixed-signal nature of the circuit. (iii) A large number of clock cycles have to be simulated to ensure the correct behavior of the circuit. (iv) To perform fault simulation, several faulty versions of the same circuit have to be simulated. For example, in our P L L we consider 115 different faults. (v) To ensure accuracy, SPICE level simulations need to be performed, which results in excessive CPU run times. (vi) The simulation of the P L L results in excessive CPU run time due to the presence of a tight, feedback loop in the P L L circuit with largely varying time constant elements [Dev96]. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 60 Conventional circuit simulators can deal with the mixed-signal nature of the P L L circuits but result in impractical simulation run times. In this thesis, we focus on using a mixed-signal simulator which is capable of defining various blocks of a circuit at various levels of abstraction. We propose the following techniques to cut down on fault simulation time: (i) For the faults in the V C O block of the PLL, we first simulated the V C O separately. We applied a fixed dc voltage of 2.635 V to the V C O input. 2.635 V was applied since this is the voltage at which the V C O operates at its center frequency of 155 MHz. For the faults in the VCO, the rms value of the analog power supply current was measured for each fault. The average simulation time for each fault with the SpectreS simulator was 10 s (CPU time). For 89% of the faults the VCO does not oscillate. In two cases the V C O starts oscillating at a very high frequency (greater than 300 MHz). Therefore, we did not need to run the V C O in a closed-loop configuration for these cases. For the remainder of the V C O faults (5 out of the total fault set of 65) we simulated the P L L in a closed-loop configuration, described next, along with the description of the fault simulation for the PD and the charge-pump faults. (ii) For the remainder of the P L L faults, we simulated the P L L in a closed-loop configuration. In the fault free case, our P L L 'locks' in 27 //s. The rms of the analog power supply current was recorded after 27 ps for each faulty case. We used the mixed-signal simulator [Ana94] "SpectreSVerilog" to simulate the faults. The "SpectreSVerilog" simulator runs "SpectreS" [Spr94] on the analog sub-circuits and "Verilog" [Ver90] on the digital sub-circuits. This provides a significant saving in the simulation time compared to the analog simulator such as SPICE, SpectreS etc. Such analog simulators are known 4. Power Supply Current Testing of the PLL Circuit-Under-Test 61 to be excessively slow for simulating digital circuits and circuits with widely varying time constants. The actual CPU time taken for this simulation was 23 minutes on the SunSparc-20 workstation. On the SPICE level simulator such as "Hspice" or "SpectreS" simulator it would take about 3 days of CPU time to simulate one fault in the PLL. Hence, by using the mixed-signal simulator we can cut down significantly on simulation time. The Monte Carlo simulation was run only on the analog blocks of the P L L since digital circuits are not susceptible to process variations. The simulation was run on the Sparc-20 station which took 3 hrs 37 minutes of CPU time. Hence, the total fault simulation time for all the faults in the PLL, including the Monte Carlo simulation, was 24 hrs and 43 minutes (CPU time). 4.3 Results The results obtained by various test techniques discussed in the previous section are summarized in this section. 4.3.1 "Operating" Id d test For our fault free analog V C O circuit, Monte Carlo simulation was performed (1000 samples) with an assumed variation of 3<r = 10% from the nominal value for the model parameters and 3cr=5% from the nominal value for the geometric sizes of the MOS transistors. The power supply current was found to have a standard deviation of 0.032 mA and a mean of 1.2 mA. We grouped the current deviations of 1000 samples in bands of 0.01mA from the mean value of 1.2 mA. Fig. 4.3.3 gives the distribution of current under the assumption of parametric variations obtained by Monte Carlo simulations. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 62 Power supply current in mA — > Figure 4.3.3 Variations in power supply current for our P L L under parametric deviations. Fig. 4.3.3 shows that the current deviation lies in the range of ±3<T under parametric variations. Only in one case does the current lie outside the 3<r band. Hence, to provide a conservative, robust test threshold, a variation in rms current (Idd) of greater than ±6cr, which corresponds to ±20% deviation from the nominal value, was chosen as the detection threshold. Based on this criterion, 86.7% of all P L L faults are detectable. Fig. 4.3.4 gives a breakdown of percentage faults detected in various blocks of the PLL. Fig. 4.3.4 also gives the percentage faults detected by varying the detection threshold to ±10% and ±50%. The "operating" Idd currents for individual PD and VCO faults are listed in Appendix F and G. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 63 Percentage faults detected Figure 4.3.4 PLL fault coverage obtained by the "operating" Lj^ test. We observed that 89% of the faults caused a reduction in the power supply current since the V C O stops oscillating. In such cases, there is minimal activity in the circuit, and hence only the MOS leakage currents flow. This current is in the order.of nanoamperes. The V C O fault coverages using current thresholds of 10%, 20% and 50% are illustrated in Fig. 4.3.5 (a), (b) and (c) respectively. The PD fault coverages using current thresholds of 10%, 20% and 50% are illustrated in Fig. 4.-3.6 (a), (b) and (c) respectively. In the case of the charge-pump, 100% of the faults were detected using this test. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 64 100 80 60 40 20 0 Percentage faults detected fe'i -I l l 111 illl! • 1 1 • 1 % 1 : G-D shorts 'J G-Sshoiis J S openj. - j D open (a) A ± 10% threshold for "operating" I 100 Percentage faults detected 80 60 40 20 0 1- -1 'A 111 G-D shorts G-S shorts S open | | D open (b) A ± 20% threshold for "operating" I d d 100 Percentage faults detected 80 G-D shorts C -1 G-S sh.nK Li S open D open (c) A + 50% threshold for "operating" I d d Figure 4.3.5 Fault coverages obtained for the V C O by "operating" I d d for different thresholds (a) +10%, (b) +20%, and (c) +50%. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 65 Percentage faults detected • Stuck-at 0 faults I = stuck-at 1 faults (a) A threshold of ± 10%. 100 Percentage faults detected 80 60 40 20 Stuck-at 0 faults tuck-at 1 faults (b) A threshold of ±20%. 100 Percentage faults detected 80 60 40 20 0 1^ Stuck-at 0 faults | | | | Stuck-at 1 faults (c) A threshold of ±50%. Figure 4.3.6 PD fault coverage for various "operating" Idcj thresholds. 4.3.2 "Non-operating" L j d test From simulations, the "non-operating" current in the fault free case is in the order of nanoamperes. Since commonly available ATE have a current measurement resolution and 4. Power Supply Current Testing of the PLL Circuit-Under-Test 66 accuracy in the range of a few hundred nanoamperes, only the faults resulting in a "non-operating" current greater than one microampere were considered detectable [HP94]. Based on this criterion, 46% of the total faults are detectable. The combination of the "operating" Idd test and the "non-operating" Idd test yields a fault coverage of 96.5%, 92.3% and 79.1% for operating Idd thresholds of ±10%, ±20% and ±50% respectively. 4.3.3 "Frequency-lock" test Our total fault set is comprised of 115 different faults for the whole PLL. To derive our results, mixed-signal simulations were performed using the SpectreSVerilog simulator [Spr94, Ver90]. The circuit was declared faulty if the frequency was not equal to 155 MHz. Based on the "frequency lock" test criterion, 94.7% fault coverage was obtained for the PLL. Fig. 4.3.7 gives the breakdown of the percentage of faults detected by this testing method for the various building blocks of the PLL. Further breakdown of the obtained coverages for the V C O and the PD are illustrated in Fig. 4.3.8 and Fig. 4.3.9 respectively. Fig. 4.3.8 gives the VCO coverage for the transistor level fault model and Fig. 4.3.9 gives the PD coverage for the 'stuck-at' fault model. In the case of the charge-pump, 100% of the faults were detected using the "frequency-lock" test. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 67 100 Percentage faults d»"":ted 80 60 40 20 0 All faults Charge-pump faults VCO faults : ..- PD faults Figure 4.3.7 P L L fault coverage using the "frequency-lock" test. 100 Percentage faults detected 80 60 40 20 J G-D shorts jg G-S shorts S open I JD open Figure 4.3.8 V C O fault coverage using the "frequency-lock" test. Percentage faults detected Stuck-at 0 faults BEg Stuck-at 1 faults Figure 4.3.9 PD fault coverage using the "frequency-lock" test. 4. Power Supply Current Testing of the PLL Circuit-Under-Test 68 4.3.4 Overall fault coverage The Venn diagrams illustrating the cumulative fault coverage using the "frequency-lock" and the current test techniques are shown in Fig. 4.3.10 through Fig. 4.3.12. "Operating" 1 test ±10% threshold Non-operating" I d c ] test 0 Undetected faults "Frequency-lock" test Figure 4.3.10 Fault coverage obtained using various test techniques ("operating" 1 ^ threshold of ±10%). "Operating" Idd test + 2 0 % threshold "Non-operating" I ddtest 0 Undetected faults "Frequency-lock" test Figure 4.3.11 Fault coverage obtained using various test techniques ("operating" I d d threshold of +20%). "Operating" \ M test ± 1 0 % threshold 'Non-operating" I test 0 Undetected faults "Frequency-lock" test Figure 4.3.12 Fault coverage obtained using various test techniques ("operating" I d d threshold of ±50%). 4. Power Supply Current Testing of the PLL Circuit-Under-Test 69 Our results show that the "frequency-lock" test provides the highest fault coverage (94.7%). However, the coverage can be enhanced to 97.3% when the "frequency-lock" test is used in conjunction with the "non-operating" Ljd test. It is also noted that the "operating" Idd test does not provide significant incremental coverage over the "frequency-lock" test. However, the combination of the "operating" Idd test and the "non-operating" I d d test provides a fault coverage of 93.8%, which is comparable to the "frequency-lock" test. Chapter 5 Conclusions and Future Work 5.1 Conclusions In this thesis, problems and issues related to the testing of PLLs have been outlined. This thesis focuses on developing generic, cost-effective current test techniques for testing PLLs. We have studied the effectiveness of power supply current monitoring techniques against the traditionally used "frequency-lock" test for testing the PLLs. The focus of this thesis is on investigating the effectiveness of power supply current monitoring techniques in order to detect potential faults. Our experimental results show that the technique can be very effective at easily and cheaply screening faulty circuits. Our study reveals that using a simple "operating" 1^ test, depending upon the threshold, a fault coverage varying from 60% to 95% is obtained. By taking parametric variations into account, we have deduced that a threshold of ±20% can be considered an acceptable, realistic detection level, yielding a fault coverage of 86.7%. Though, it is not possible to detect all catastrophic faults by current testing, the current testing method provides an economical solution for the early screening of faulty circuits. A fault coverage of 93.8% was obtained using a combination of the "operating" Idd (assuming a detection threshold of ±20%) and the "non-operating" Idd test techniques. This is comparable to the fault coverage obtained using the "frequency-lock" test (94.7%). This shows that the current test techniques can be used as an alternative to the "frequency-lock" test. An additional 70 5. Conclusions and Future Work 71 advantage of the current testing is low test development and implementation cost. This is due to the fact that all commercial ATEs are capable of measuring currents whereas they may or may not be able to perform the "frequency-lock" test. In the cases where the ATE cannot perform frequency test one must use external equipment to perform the test which implies higher cost. In applications which require high reliability and test quality that would be obtained by "frequency-lock" test or current tests individually, a combination of the "frequency-lock" test and "non-operating" current test technique can be used to enhance the overall fault coverage to 97.3%. It is thus shown that relatively simple and cost effective current tests can be used as an alternative to functional tests or to enhance the total fault coverage when used in conjunction with functional tests. An important limitation of the "non-operating" Ljd test is its applicability to specific circuit architectures. In general, it can be efficiently applied to the PLLs which employ external loop-filter components (thus providing access to the V C O input). The technique can be used for embedded VCQs but would require careful partitioning of the V C O by employing analog multiplexers. 5.2 Future work This research demonstrates the feasibility of current test techniques for PLLs. Since, the dynamic and the static behavior of all PLLs is similar, the techniques discussed in this thesis are likely to be applicable to most PLLs. However, more work is needed to verify this. Further, investigation needs to be carried out in order to determine the extent of applicability of current monitoring methodology to other classes of analog circuits. 5. Conclusions and Future Work 72 In this thesis, we considered the circuit-level (schematic-level) fault model and a circuit-level fault simulation approach to quantify the effectiveness of various test approaches. This approach does not take the circuit layout into account. Layout based fault simulation is another popular fault simulation approach. This approach should be applied to the circuits considered in this thesis and a comparative analysis should be performed. In this work, we do not target specific undetected faults since the cumulative fault coverage ranges from 93% to 97% which is considered satisfactory for most applications. However, if a higher coverage is desired, one could investigate design-for-test (DFT) techniques. Further work needs to be done where defects are introduced into large macros composed of several analog modules. Investigations regarding change in supply currents, in such cases, need to be carried out. In this work, the focus was on catastrophic faults. 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Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective, 2nd ed. Addison-Wesley, Reading Mass, 1985, Chapter 3. [Wey90] Chin-Long Wey, "Built-in Self-Test (BIST) Structure for Analog Circuit Fault Diagnosis ," IEEE Transactions on Instrumentation and Measurement, Vol. 39, No. 3, June 1990, pp. 517-521. [Wil82] T. W. Williams and K. P. Parker, "Design for Testability - A Survey," in IEEE Transactions, vol. 31, pp. 2-15, 1982. [Wol91] D. Wolaver, Phase-Locked Loop Circuit Design, Prentice Hall, Englewood Cliffs, N.J., 1991. [Zwo96] M . Zwolinski, C. Chalk and B. R. Wilkins, "Analogue Fault Modelling and Simulation for Supply Current Monitoring ," European Design and Test Conference,. 1996, pp. 547-552. Appendix A. List of Acronyms 78 Appendix A. List of Acronyms ac Alternating Current A D C Analog-to-digital Convertor A H D L Analog Hardware Description Language A M Amplitude Modulation ASIC Applications Specific Integrated Circuit ATE Automatic Test Equipment ATPG Automatic Test Pattern Generation BIST Built-in Self-test C M C Canadian Microelectronics Corporation CMOS Complementry Metal Oxide Semiconductor CUT Circuit Under Test D A C Digital-to-analog Convertor dc Direct Current DFT Design for Test DRC Design Rule Check DUT Device Under Test F M Frequency Modulation IC Integrated Circuit IEEE Institute of Electrical and Electronics Engineers I/O Input/Output LSSD Level Sensitive Scan Design LPF Low Pass Filter LVS Layout versus Schematic MHz MegaHertz MOS Metal Oxide Semiconductor ns nanosecond Appendix A. List of Acronyms 79 OC-3 Optical Carrier at level 3 PD Phase Detector PFD Phase/Frequency Detector P L L Phase-Locked Loop P M Phase Modulation P-P peak-to-peak ps picosecond rms root mean square SONET Synchronous Optical Network SSA Single Stuck-at V C O Voltage Controlled Oscillator VLSI Very Large Scale Integration Appendix B. Layouts 80 Appendix B. Layouts Appendix B. Layouts 81 Figure B . l P L L layout. Figure B.2 V C O layout. Appendix B. Layouts 83 Figure B.3 Charge-pump layout. Appendix C. Simulation Results 84 Appendix C. Simulation Results Transient Response x10 7 . 0 , D ! Charge-pump output 3. - 1 flr-i i i i 1 "I1 i x 1 0 w 2 g ~l D '• LPF output 2 .65 2 .63 LJ i i i i i i i i i L_I i -i x10 0.0 2 .0 4 .0 . 6.0 t ime - 6 Figure C . l Various output waveforms for the behavioral model. Appendix C. Simulation Results 85 6.( 1.G I.0 Transient Response / vco output ! reference clock -1. 5.76 J_l L 5.79 5.82 ...l I L [ x 1 0 " 5.85 time •6 Figure C.2 Reference input and V C O output for the behavioral model. Appendix C. Simulation Results 8 6 Transient Response j ^ 0 lllluluilUI 11 LUI x10 7 A Charge-pump output 3. - 1 . 0 x 1 0 2 2.69 J I L_l I I I I L LPF output J I I I I I I I I L J L 2 .65 2.61 J I I I I I I I I I I I I I I I I I I I I l I I I I I L 3.0 5. x10~ 0 t ime •6 Figure C.3 Various output waveforms for the P L L under test. Appendix C. Simulation Results 87 6i 5.( 4.1 3.0 It 2X 1.£ Transient Response o : /vco_out /refclk iJ u ni m r ..I ! I i I.. 4.70 4.72 4.74 i. x10" 4.76 time Figure C .4 Reference input and V C O output for the P L L under test. Appendix D. Hspice Code Appendix D. Hspice Code 1. The Hspice code for the Monte Carlo simulation. * # FILE NAME: /NFS/SHERRIE/COLOSSAL/VLSI/ *MANEESHA/CAD/CDS/BICMOS/ * * * V a r i a t i o n s i n the parameters modeled by*** ****gaussian random v a r i a b l e s * * * * .GLOBAL G2 .PARAM LI = GAUSS (2E-6, 0.05, 3) .PARAM L2 = GAUSS (800E-9, -0.05, 3)' .PARAM L3 = GAUSS (1.2E-6, 0.05, 3) .PARAM Wl = GAUSS (30E-6, 0.05, 3) .PARAM W2 = GAUSS (15E-6, ' 0 . 05, 3) .PARAM W3 = GAUSS (20E-6, 0.05, 3) .PARAM W4 = GAUSS (18E-6, 0.05, 3) .PARAM W5 = GAUSS (5.6E-6, 0.05, 3) .PARAM W6 = GAUSS (10E-6, 0.05, 3) .PARAM W7 = GAUSS (9E-6, 0.05, 3) .PARAM W8 = GAUSS (3.4E-6, 0.05, 3) .PARAM W9 = GAUSS (6E-6, 0.05, 3) .PARAM VTD1 = GAUSS (0.8115, 0.1, 3) Appendix D. Hspice Code 89 . P A R A M V T D 2 = G A U S S ( - 0 . 9 0 2 , 0 . 1 , 3 ) . . P A R A M V T N ^ V T D l . P A R A M V T P = V T D 2 . P A R A M T O X D 1 = G A U S S ( 1 7 . 5 2 E - 9 , 0 . 1 , 3) . P A R A M T O X N = T O X D l . P A R A M N S U B D 1 = G A U S S ( 3 . 6 1 8 E 1 6 , 0 . 1 , 3) . P A R A M N S U B D 2 = G A U S S ( 3 . 1 4 9 E 1 6 , 0 . 1 , 3) . P A R A M N S U B N = N S U B D 1 . P A R A M N S U B P = N S U B D 2 . P A R A M U O D 1 = G A U S S ( 4 7 5 , ' O . l , 3) . P A R A M UOD2 = G A U S S ( 1 5 4 , 0 . 1 , 3) . P A R A M U O N = U O D l . P A R A M U O P = U O D 2 . P A R A M X J N D 1 = G A U S S ( 1 6 0 . 4 E - 9 , 0 . 1 , 3) , P A R A M X J P D 1 = G A U S S (3 0 8 E - 9 , 0 . 1 , 3) , P A R A M X J N 1 = X J N D 1 P A R A M X J P 1 = X J P D 1 P A R A M X J N D 2 = G A U S S ( 1 6 2 . 6 E - 9 , 0 . 1 , 3) P A R A M X J P D 2 = G A U S S ( 1 3 2 E - 9 , 0 . 1 , 3) P A R A M X J N 2 = X J N D 2 P A R A M ' X J P 2 = X J P D 2 P A R A M X J N D 3 = G A U S S ( 9 5 . 7 6 E - 9 , 0 . 1 , 3 ) . Appendix D. Hspice Code 90 . PARAM XJPD3 = GAUSS (3 0.4E-9", 0.1, 3) .PARAM XJN3 =XJND3 " .PARAM XJP3=XJPD3 * * * * * * ]v^g £ T_ -j_ g * * * * * * V57 NET12 0 PWL 0.0 0.0 20E-9 2.635 V21 G2 0 5.0 XI19 NET12 0 SUB1 .LIB '/a/sherrie/chip/home/maneesha/Models/Hspice/ BICMOS.hspice' TYPICAL .SUBCKT SUB1 U N F_OUT MI52 NET15 NET15 G2 G2 MPCH L I Wl AD=+6.30000000E-11 +AS=+6.30000000E-11 PD=+6.42000000E-05- , . PS=+6.42000000E-05 ' MI35 F_OUT N4 G2 G2 MPCH L2 W2 AD=+3 . 150000.00E-11 +AS= + 3 .15000000E-11 PD=+3 . 420.00000E-05 ' PS=+3.42000000E-05 M I 2 4 N E T 3 5 N E T 1 5 G2 G 2 M P C H L I W3 A D = + 4 . 2 0 0 0 0 0 0 0 E - 1 1 + A S = + 4 . 2 0 0 0 0 0 0 0 E - 1 1 P D = + 4 . 4 2 0 0 0 0 0 0 E - 0 5 P S = + 4 . 4 2 0 0 0 0 0 0 E - 0 5 Appendix D. Hspice Code 91 M I 2 3 N I N3 N E T 3 5 N E T 3 5 M P C H L 3 W4 A D = + 3 . 7 8 0 0 0 0 0 0 E - 1 1 + A S = + 3 . 7 8 0 0 0 0 0 0 E - 1 1 P D = + 4 . 0 2 0 0 0 0 0 0 E - 0 5 P S = + 4 . 0 2 0 0 0 0 0 0 E - 0 5 M I 3 2 N4 N3 G2 G2 M P C H L 2 W5 A D = + 1 . 1 7 6 0 0 0 0 0 E - 1 1 . AS=+1 . 17 6 0 0 0 0 0 E - 1 1 + P D = + 1 . 5 4 0 0 0 0 0 O E - 0 5 P S = + 1 . 5 4 0 0 0 0 0 0 E - 0 5 . M I 9 N E T 9 7 N E T 1 5 G2 G2 M P C H L I W3 A D = + 4 . 2 0 0 0 0 0 0 0 E - 1 1 + A S = + 4 . 2 0 0 0 0 0 0 0 E - 1 1 P D = + 4 . 4 2 0 0 0 0 0 0 E - 0 5 P S = + 4 . 4 2 0 0 0 0 0 0 E - 0 5 M I 1 7 N E T 4 4 N E T 1 5 G2 G2 M P C H L I W3 A D = + 4 . 2 0 0 0 0 0 0 0 E - 1 1 +AS=+4 .200000 '00E-11 P D = + 4 . 4 2 0 0 0 0 0 0 E - 0 5 P S = + 4 . 4 2 0 0 0 0 0 0 E - 0 5 M I 1 8 N2 N I N E T 4 4 N E T 4 4 M P C H L 3 W4 A D = + 3 . 7 8 0 0 0 0 0 0 E - 1 1 + A S = + 3 . 7 8 0 0 0 0 0 0 E - 1 1 P D = + 4 . 0 2 0 0 0 0 0 0 E - 0 5 P S = + 4 . 0 2 0 0 0 0 0 0 E - 0 5 M I 2 N E T 3 0 N E T 1 5 G2 G2 M P C H L I W3 A D = + 4 . 2 0 0 0 0 0 0 0 E - 1 1 + A S = + 4 . 2 0 0 0 0 0 0 0 E - 1 1 P D = + 4 . 4 2 0 0 0 0 0 0 E - 0 5 Appendix D. Hspice Code 92 PS=+4.42000000E-05 Mil N3 N2 NET30 NET30 MPCH L3 W4 AD=+3.78000000E-11 +AS = + 3 . 78000000E-11 PD= + 4 . 02 00000.0E-05 PS=+4.02000000E-05 MI34 F_OUT N4 0 0 MNCH L2 W6 AD=+2.10000000E-11 AS=+2.10000000E-11 +PD=+2.42000000E-05 PS=+2.42000000E-05 MI28 NET60 NET97 0 0 MNCH LI W6 AD=+2.10000000E-11 AS=+2.10000000E-11 +PD=+2.42000000E-05 PS=+2.42000000E-05 MI21 NI N3 NET60 0 MNCH L3 W7 AD= + 1.89000000E-11 AS=+1.8900 0 000E-11 +PD=+2.22 000000E-05 PS=+2.22000000E-05 MI2 0 N2 NI NET72 0 AS=+1.89000000E-11 PS=+2 .2200-0000E-05 MNCH L3 W7 AD=+1.89000000E-11 +PD=+2.22000000E-05 Appendix D. Hspice Code 93 MI8 NET97 NET97 0 0 MNCH L l W6 AD=+2.10000000E-11 AS=+2.10 00000OE-11 +PD=+2.42 0 0 00 0 0E-05 PS=+2.42000000E-05 MI33 N4 N3 0 0 MNCH L2 W8 AD=+7.14000000E-12 AS=+7.14000000E-12 +PD=+1.10000000E-05 PS=+1.10000000E-05 MI50 NET15 UN 0 0 MNCH L l W9 AD=+1.26000000E-11 AS=+1.26000000E-11 +PD=+1.62000000E-05 PS=+1. 62000000E-05 MI19 NET72 NET97 0 0 MNCH L l W6 AD=+2.10000000E-11 AS=+2.10000000E-11 +PD=+2.42000000E-05 PS=+2.42000000E-05 MI3 NET38 NET97 0 0 MNCH L l W6 AD=+2.10000000E-11 AS=+2.10000000E-11 +PD=+2.42000000E-05 PS=+2.42000000E-05 MIO N3 N2 NET38 0 MNCH L3 W7 AD=+1.89000000E-11 AS=+1. 89000 00OE-11 +PD=+2 . 22000£IOOE-05 Appendix D. Hspice Code 9 4 PS=+2.22000000E-05 .ENDS SUB1 . IC V(XI19 .N2 ) =5 '• .TRAN 1.00000E-09 120.000E-09 SWEEP MONTE=1000 .MEAS TRAN RMSVAL RMS I(V21) FROM=20ns TO=120ns .MEAS TRAN AVGVAL AVG I(V21) FROM=2 0ns TO=120ns .PRINT TRAN V(O) .TEMP 25.0000 .OPTION INGOLD=2 .END Appendix E. MATLAB Code 95 Appendix E. MATLAB Code (i) The M A T L A B code for plotting various P L L parameters, c l e a r ; figure( 1 ) ; f=l : 500 : 4*10e6; Rl=60*1000; R2=175; C=200*10e-12; %%%%%%%%%%%%%%%%%%%%%% kd=5/(4*pi); ko=190*2*pi*10e6; kh=R2/(R1+R2); k=ko*kd*kh; khz =k/(2*pi);. ' %%%%%%%%%%%%%%%%%%%%%% w=2*pi*f; w2=l/(R2*C); w3=l/((R1+R2)*C); w2hz = w2/(2*pi); %%%%%%%%%%%%%%%%%%%%%%% Fs= (l+j*w*C*R2)./(l+j*w*C*(R1+R2)); Appendix E. MATLAB Code 96 Gs=kb*kd*Fs./(j*w); Hs=Gs. / (1+Gs). ; %%%%%%%%%%%%%%%%%%%%%%% magHs=abs(Hs) ; magGs=abs(Gs); magFs=abs(Fs); %%%%%%%%%%%%%%%%%%%%%%% subp l o t ( 3 , 1 , 1 ) ; semilogx(f,magFs); • t i t l e ( ' F (s) ' ) ; x l a b e l ( ' frequency (Hz.) --> ' ) ; y l a b e l ( ' m a g n i t u d e [ F ( s ) ] - - > ' ) ; %%%%%%%%%%%%%%%%%%%%%%%%%%%%% s u b p l o t ( 3 , 1 , 2 ) ; " " semi1ogx(f,magGs); t i t l e ( ' G ( s ) ' ) ; x l a b e l (.' frequency (Hz) -->' ) yla b e l ( ' m a g n i t u d e [ G ( s ) ] - - > ' ) ; % % % % % % % % % % % % % % % % % % % % % % % • subplot(3,1,3); semilogx(f,magHs) ; t i t l e (.'H (s) ' ) ;••• Appendix E. MATLAB Code 97 xlabel('frequency(Hz)-->'); ylabel('magnitude[H(s)]-->'); p r i n t hs; Appendix E. MATLAB Code 98 (ii) M A T L A B code for plotting the step response of the PLL. c l e a r ; R l=60*1000; R2=175; C=200*10e-12; k d = 5 / ( 4 * p i ) ; ko=190*2*pi*10e6; %%%%%%%%%%%%% num= [ko*kd*C*R2 k o * k d ] ; ' den= [C*(R1+R2) l+C*R2*ko*kd k o * k d ] ; s t e p ( n u m , d e n ) ; p r i n t s t e p _ r e s _ m o d e l . i ; Appendix F. PD Faults 99 Appendix F. PD Faults Gate No. Nodes stuck-at Idd (rms) Comments 1. O/p sal 2.21mA no lock 2. I/p 1 sal 2.01mA no lock 2. O/p sal 1.015mA no lock 3. O/p sal 2.01mA no lock 5. I/p 1 sal 544^A no lock 5. I/p 2 sal 327/tA no lock 5. I/p 3 sal 544^A no lock 5. O/p sal 2.01mA no lock 6. O/p sal 46nA no lock 8. I/p 2 sal 2.3mA no lock 9. I/p 2 sal 68^A no lock 10. I/p 3 sal 1.025mA no lock 10. I/p 4 sal 2.15mA no lock 11. O/p sal 67/*A no lock 12. I/p 2 sal 1.289mA no lock 12. O/p sal 2.1mA no lock "13. O/p sal IluA no lock 15. O/p sal IluA no lock 16. I/p 2 sal IluA no lock 17. O/p. sal 7\uA no lock 18. O/p sal 1.192mA P L L locks Table F. 1 Effect of stuck-at 1 faults in PD on power supply current. Appendix F. PD Faults 100 Gate No. Nodes stuck-at Idd (rms) Comments 1. O/p saO 995^A no lock 2. I/p 1 saO 45nA no lock 2. O/p saO 2.1mA no lock 3. O/p saO 511 pA no lock 5. I/p 1 saO 2.1mA no lock 5. I/p 2 saO 2.13mA no lock 5. I/p 3 saO 955/^A no lock 5. O/p saO 577^A no lock 6. O/p saO 2.01mA no lock 8. I/p 2 saO 577/xA no lock 9. I/p 2 saO 955//A no lock 10. I/p 3 saO 344/xA no lock 10. I/p 4 saO 344/xA no lock 11. O/p saO 2.14mA no lock 12. I/p 2 saO 511 p.k no lock 12. O/p saO 577^A no lock 13. O/p saO 2.1mA no lock 15. O/p saO 70/zA no lock 16. I/p 2 saO 70/iA no lock 17. O/p saO 1.19mA P L L locks 18. O/p saO •577j*A no lock Table F.2 Effect of stuck-at 0 faults in PD on power supply current. Appendix G. VCO Faults 101 Appendix G. VCO Faults Transistor Fault type Op. Idd (rms) Non-op. Comments No. Idd(rms) Fault free 1.186mA 284nA Osc. at 152Mhz M l G-D short 1.424mA 4.27mA Osc. at 175Mhz M2 G-D short redundant M3 G-D short 1.107mA 5.939mA no osc. •' M4 G-D short 1.182mA 320nA Osc. at 154Mhz M5 G-D short 1.175mA 207.5/xA Osc. at 152Mhz M6 G-D short 845//A 20.58nA no osc. M7 G-D short 826,uA 80nA no osc. M8 G-D short 845//A 25nA no osc. M9 G-D short 2.222mA 1.11mA no osc. M10 G-D short 2.06mA 1.20mA no osc. M i l G-D short 845/xA 20.58nA no osc. M12 G-D short 825//A 80.65nA no osc. M13 G-D short 845/uA 25.39nA no osc. M14 G-D short 2.222mA 1.108mA no osc. M15 G-D short 2.06mA 1.202mA no osc. M16 G-D short redundant M17 G-D short 2.211mA 1.425mA Osc. at 263Mhz M18 G-D short 919 u A 144.8MA no osc. M19 G-D short 1.089mA 21.78/iA Osc. at 146Mhz M20 G-D short 1.095mA 82.48MA Osc. at 146Mhz Table G.l Effect of G-D shorts in VCO on power supply current. Appendix G. VCO Faults 102 Trasistor Fault type Op. Non-Op. Idd(rms) Comments No. Idd (rms) Fault free 1.186mA 284nA Osc. at 152Mhz M l G-S short 513/iA 15nA no osc. M2 G-S short 513/iA 9.8/iA no osc. M3 G-S short 573/^A 9.8/iA no osc. M4 G-S short 513/iA 9.8/iA no osc. M5 G-S short 573^iA 9,8pA no osc. M6 G-S short 926^A 2.04/xA no osc. M7 G-S short 775//A 32nA no osc. M8 G-S short 775^A 2 . 0 7 M •• no osc. M9 G-S short 777/xA 19nA no osc. M10 G-S short 1.31mA 868/iA no osc. M i l G-S short 1.152mA 4.529/iA no osc. M12 G-S short 777/JA 33//A no osc. M13 G-S short lllliA 57nA no osc. M14 G-S short 777/iA 8nA no osc. M15 G-S short 1.381mA 30nA no osc. M16 G-S short 344jiA 15.58nA no osc. M17 G-S short 344/«A 15.58nA no osc. M18 G-S short 344/xA 15.58nA no osc. M19 G-S short 344^A 15.58nA no osc. M20 G-S short 344^A 15.58nA no osc. Table G.2 Effect of G-S shorts in VCO on power supply current. Appendix G. VCO Faults 103 Transistor Fault type Op. Idd(rms) Non-Op. Comments No. Id d(rms) Fault free 1.186mA 284nA Osc. at 152Mhz M l S open 79nA 29nA no osc. M2 S open 1.275mA 233/iA Osc. at 313Mhz M3 S open 588^A 37^A no osc. M4 S open 678^A 383nA no osc. M5 S open 802MA 1.2/iA no osc. M6 S open repeated fault M7 S open repeated fault M8 S open repeated fault M9 S open 905^A 339nA no osc. M10 S open 1.025mA 232nA no osc. M i l S open 653yuA 422nA no osc. -M12 S open 610MA 1.28/xA no osc. M13 S open 720^A 517nA no osc. M14 S open 904/iA 609MA no osc. M15 S open 1.018mA 463nA no osc. M16 S open 2.111mA 2.124mA Osc. at425Mhz M17 S open 330MA 3.18^A no osc. M18 S open 655/iA 323nA . no osc. M19 S open 622//A 951nA no osc. M20 S open 728/iA 33nA no osc. Table G.3 Effect of Source opens in V C O on power supply current. Appendix G. VCO Faults 104 Transistor No. Fault type Op. I d d (rms) Non-Op. Idd(rms) Comments Fault free 1.186mA 284nA Osc. at 152Mhz M l D open 40nA 28.9nA no osc. M 2 , D open 1.271mA 93//A Osc. at 313Mhz M3 D open 564/xA 2.167/iA no osc. M4 D open 628//A 703nA no osc. M5 D open 684^A 922nA no osc. M6 D open 571//A 1.92/iA no osc. M7 D open 558/iA 606nA no osc. M8 D open 557.8/iA 414nA no osc. M9 D open 904^A 641nA no osc. M10 D open 1.028mA 84nA no osc. M i l D open repeated fault M12 D open repeated fault M13 D open repeated fault M14 D open repeated fault M15 D open 1.028mA 278^A no osc. M16 D open repeated fault M17 D open repeated fault M18 D open repeated fault M19 D open repeated fault M20 D open repeated fault Table G.4 Effect of Drain opens in V C O on power supply current. 

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