CONTROL OF SURGE CURRENTS IN INVERTER FED LOADS by Jarmo Venalainen B.Sc, Simon Fraser University, 1989 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES V (Electrical Engineering) We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA June, 2000 © Jarmo Venalainen, 2000 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. 1 further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of The University of British Columbia Vancouver, Canada DE-6 (2/88) Abstract Switch mode power converters have been used in high power applications such as DC links and variable frequency motor drives for a number of decades. In these applications the load is fixed and well known, and therefore the nature of the power demand placed on the inverter is also well known. In more recent years, high frequency switch mode inverters have become available at smaller power levels as consumer products. These inverters are marketed as capable of providing AC power to ANY AC load which the customer may have. In this case the inverter is called upon to supply power to a diverse variety of loads, presenting it with very challenging operational issues, especially with regards start up surge currents. This thesis investigates the characteristics of the input current drawn by consumer type AC loads, when driven by a standard sinusoidal 60 Hz 110VAC source, with particular emphasis on the inrush current transients found during start up. It then goes on to look at how the surge currents differ when the driving voltage is a non-sinusoidal single step waveform as produced by the vast majority of small inverters. This is followed by a discussion on the benefit of having multiple step waveforms and trapezoidal waveforms, in terms of their effect on the surge current transients. From the discussion on multi step and trapezoidal waveforms, it is shown that a current regulated output is the optimum solution for Masc Thesis for Electrical Engineering Jarmo Venalainen ii small modified sinewave inverters when they are used to drive typical consumer type loads. This approach is demonstrated in a 300W inverter through the implementation of hysteretic output current control. Finally, AC output bridge switching losses are investigated, and the benefit of a small amount of series output inductance is demonstrated through simulations and circuit trials. Masc Thesis for Electrical Engineering Jarmo Venalainen iii Contents: Abstract ii List of Tables vi List of Figures vii Acknowledgments xi 1 Introduction 1 2 Inrush current characteristics of Typical AC loads 2.1 2.2 2.3 2.4 Incandescent Light Bulbs Capacitive Rectified Loads Compact Fluorescent Light Bulbs Inductive Loads 6 8 12 14 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 Load Simulations Analytical Investigation of the start up inrush current in AC loads Load Models Incandescent Light Bulbs Capacitive Rectified Loads Compact Fluorescent Light Bulbs Inductive Loads 16 16 21 21 25 27 29 4 4.1 4.2 4.2.1 4.2.2 4.3 4.3.1 4.3.2 4.4 Simulated Inverter Models Single and Multi Step Models THE) and RMS voltage One step waves Two, three and four step waves Simulations of surge currents with 1, 2, 3, and 4 step waves Incandescent Light Bulbs 13" Computer Monitor Trapezoidal waves 31 31 35 35 39 46 46 49 53 iv 6 5 5.1 5.2 5.3 Hysteretic Current Control Hysteretic current control simulation model Hysteretic current control circuit Experimental results with hysteretic current control 55 55 61 64 6 6.1 6.2 6.2 Switching Losses Theoretical analysis Switching Loss Simulations Experimental Switching Loss Measurements 71 71 73 79 7 Conclusion 85 Appendix A Matlab, T.H.D. minimization program listings Appendix B UC3525B PWM data sheets 91 Appendix C Typical circuit breaker trip time graph 100 Appendix D Typical SO A graph for a 200 Volt, 9 Amp power MOSFET 101 86 References 102 Masc Thesis for Electrical Engineering Jarmo Venalainen V List of Tables Table 1 Breaker trip times versus overload current in percent of rated current Table 2 Simulation results of peak surge current versus switching angle for monitor load Table 3 Minimum T.H.D. step voltages and pulse lengths for 1,2, 3 and 4 step waves Table 4 Output bridge device temperature versus series output inductor value vi 2 20 45 83 List of Figures Figure 1 Modified "sinewave" Figure 2 Two step wave Figure 3 Measured inrush current for a 75W incandescent light bulb Figure 4 Capacitive rectified power supply input stage Figure 5 Measured inrush surge current for 13" IBM PS/1 monitor Figure 6 Steady state input current into 13" IBM PS/1 monitor Figure 7 Inrush current into self starting compact fluorescent light bulb Figure 8 Inrush current into ballast type fluorescent light Figure 9 Start up surge into 300W handheld drill Figure 10 Series RC circuit Figure 11 Instantaneous load voltage at different switching points Figure 12 Simulated surge current for first A AC cycle Figure 13 Incandescent light bulb load simulation Figure 14 Simulated inrush current into 75 W incandescent light bulb Figure 15 Measured inrush current into 75W incandescent light bulb Figure 16 Typical capacitive rectified load Figure 17 Simulated inrush surge into 13" IBM PS/1 monitor Figure 18 Measured inrush surge current into IBM PS/1 monitor Figure 19 Simulated surge current into self starting compact fluorescent light bulb Figure 20 Measured surge current into self starting compact fluorescent light bulb Figure 21 Load current path during bridge device off state Figure 22 Measured inrush surge current for ballast driven fluorescent light when driven by modified sinewave inverter Figure 23 Measured inrush surge for 300W handheld drill when driven by modified sinewave inverter Figure 24 Output bridge of typical small inverter Figure 25 Gate drive signals for output bridge, to produce modified sinewave output Figure 26 Modified sinewave output waveform Figure 27 Multi step inverter simulation model Figure 28 Gate drive signals for multi step inverter Figure 29 Definition of pulse length and step height variables for modified sinewave l vii 3 4 7 9 10 11 13 14 15 16 18 19 21 23 23 25 26 26 .....28 28 29 30 30 31 32 32 33 34 35 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 T.H.D. as function of pulse length for a single step wave Variable definition for two step wave Variable definition for three step wave Decomposition of two step wave into two, single step waves Measured inrush surge for 75W incandescent light bulb when driven by inverter Figure 35 Simulated inrush surge for 75W incandescent light bulb when driven by inverter Figure 36 Simulated inrush surge for 75W incandescent light bulb when driven by 2 step wave Figure 37 Simulated inrush surge for 75W incandescent light bulb when driven by 3 step wave Figure 38 Simulated inrush surge for 75 W incandescent light bulb when driven by 4 step wave Figure 39 Measured inrush surge for 13" IBM PS/1 monitor when driven by modified sinewave Figure 40 Simulated inrush surge for 13" IBM PS/1 monitor when driven by modified sinewave Figure 41 Simulated inrush surge for 13" IBM PS/1 monitor when driven by 2 step wave Figure 42 Simulated inrush surge for 13" IBM PS/1 monitor when driven by 3 step wave Figure 43 Simulated inrush surge for 13" IBM PS/1 monitor when driven by 4 step wave Figure 44 Simulated inrush surge for 13" IBM PS/1 monitor when driven by sinewave Figure 45 Simulated inrush surge for 13" IBM PS/1 monitor when driven by modified sinewave Figure 46 Simulated inrush surge for 13" IBM PS/1 monitor when driven by trapezoidal wave Figure 47 Basic 300W inverter utilizing push-pull DC-DC stage and full bridge DC-AC stage Masc Thesis for Electrical Engineering Jarmo Venalainen viii 38 39 39 40 46 47 47 48 48 50 50 51 51 52 53 54 54 56 Figure 48 Simulation of 300W inverter with voltage control and hysteretic current control Figure 49 Simulated inrush surge for 13" IBM PS/1 monitor when driven current controlled inverter Figure 50 Simulated inrush surge for 13" IBM PS/1 monitor when driven by current controlled inverter, showing current control and HV bus voltage ramp up Figure 51 Simulated inrush surge current and inverter output voltage for 13" IBM PS/1 monitor when driven by modified sinewave inverter with current control Figure 52 DC-DC PWM circuit for 300W inverter Figure 53 Simulation of 300W inverter c/w voltage and current control Figure 54 Measured inrush surge for 13" IBM PS/1 monitor when driven by modified sinewave inverter Figure 55 Measured inrush surge current and inverter output voltage for 13" IBM PS/1 monitor when driven by modified sinewave inverter Figure 56 Measured inrush surge for 13" IBM PS/1 monitor with hysteretic current control in the inverter Figure 57 Measured inrush surge for 13" IBM PS/1 monitor when driven by inverter with hysteretic current control Figure 58 Measured inrush surge for 75 W incandescent light bulb with no current control Figure 59 Measured inrush surge for 75W incandescent light bulb with hysteretic current control Figure 60 Measured inrush surge for compact fluorescent light bulb with no current control Figure 61 Measured inrush surge for compact fluorescent light bulb with hysteretic current control Figure 62 Current, voltage and switching loss during switching transition Figure 63 Switch loss sensing model c/w switch loss integrator Figure 64 Simulated switch loss with differing voltage steps Figure 65 Simulated switch loss with differing rise rates Figure 66 Simulated switch losses with differing load values Figure 67 Series inductor location on output bridge output ix 58 60 60 61 62 63 65 65 66 67 68 68 69 70 72 73 74 74 75 76 Figure 68 Simulated output bridge switching loss with and without 1.8 uH output inductor Figure 69 Output current rise rate into compact fluorescent light bulb with no series output inductance Figure 70 Output current rise rate into compact fluorescent light bulb with 1 uH of series output inductance Figure 71 Output current rise rate into compact fluorescent light bulb with lOuH of series output inductance Figure 72 Current spike rate into 0.7 uF capacitor, with no series output inductance Figure 73 Current spike rate into 0.7 uF capacitor, with 20pH series output inductor Masc Thesis for Electrical Engineering Jarmo Venalainen 78 79 80 81 82 83 Acknowledgments The author would like to thank Dr. L. M. Wedepohl and Dr. W. G. Dunford, for their patient support and encouragement throughout the course of study through which this thesis has come to fruition. A special thank you goes to my parents and my two boys, Kevin and Erik, for their encouragement, love and support. And, thank you Kevin for helping me number all of the figures and equations. I also want to thank all my friends and associates who have helped me stay on the path to completion. Finally I would like to acknowledge Dr. Jin and the PSIM program, which has proved to be a very effective and efficient tool for fleshing out and simulating many of the ideas presented here. Masc Thesis for Electrical Engineering Jarmo Venaiainen xi Introduction In the past decade or so, high frequency switch mode power inverters in the range of 50W through to a few Kilowatts have become available for off grid AC power applications such as in solar power installations, boats and motor homes. These inverters are marketed as capable of driving any AC load which the customer may have. Typically the only stated stipulation on what loads a given size inverter is capable of driving is done by identifying steady state power requirements. However, steady state power requirements can be very misleading, primarily due to the large inrush current currents present in the vast majority of "generic" AC loads. In typical AC loads a large amount of surge power is required to energize and initialize circuitry, or in the case of incandescent light bulbs, a surge is created as the cold filament heats up. For example, a standard filament type light bulb, TV, monitor, or computer, all draw peak inrush surges of about 10 times their normal operating currents during the first AC half cycle after they are switched on, and often continue to draw many times their normal operating current for up to a full second. When the load is plugged into the AC grid, power is provided through a 15Amp circuit breaker and inrush currents are not a problem. This is because a standard 15 Amp service breaker has very generous over current trip limits. The full graphs are in Appendix C, but the Masc Thesis for Electrical Engineering Jarmo Venalainen -1- salient features are summarized in the table below. Current as a percentage of breaker rating Time to trip (minimum, seconds) 100% no trip 110% 300 200% 30 500% 5 1000% 0.9 Table J Breaker trip times versus overload current in percent of rated current Because of these generous surge limits, surge limiting during AC load design has generally not received very much attention. In the case of small inverters, however, the inrush surge is a serious problem. For example, when power is provided by a 300W inverter, the maximum surge current which it can supply is less than 3 Amps, and even in a 1500W inverter, peak currents are limited to about 10-12 Amps. The difficulty for inverter designers is in creating an overload protection circuit which will protect the inverters internal circuitry, while at the same time allow enough surge to start loads. Inverter manufacturers have arrived at solutions by introducing various over current sensing and re-start circuits but often with greatly varying degrees of success. Masc Thesis for Electrical Engineering Jarmo Venalainen -2- This thesis specifically focuses on the inrush current performance of small inverters, beginning by illustrating the fundamental causes of the start up surge in typical "generic" AC loads, when driven by a pure sinewave. Then investigating how the surge currents differ when loads are driven by a small inverter having a tri state, or also known as, a modified "sinewave" output voltage. Shown below is the modified "sinewave" waveform produced by a typical small inverter, superimposed on a regular sinewave. Figure I. Modified "sinewave The voltage swings from +MAX to ZERO to -MAX during each cycle, hence its designation as a tri state wave. The reference to modified "sinewave" is used to differentiate the tri-state wavefroma square wave. This is followed by an investigation of the surge performance of multi step modified sinewave inverters, focusing on how the peak inrush current transients vary with the introduction of additional steps. Masc Thesis for Electrical Engineering Jarmo Venalainen -3- A typical two-step wave has the form, Figure 2. Two step wave The two step wave looks like a staircase which loosely follows the sinewave. As additional steps are introduced, the output stepped voltage wave shape begins to approach the shape of a pure sinewave. Indeed, most "true" sinewave inverters produce their output sinewave by pulse width modulation, (PWM), techniques, whereby the output is a filtered multi step wave composed of thousands of steps. At this high step count, the Total Harmonic Distortion diminishes to virtually zero. Next, the benefit of having a reduced rise rate on the AC voltage is looked at through simulations of a trapezoidal output voltage waveform. Through the investigations into the multi-step and trapezoidal waveforms it is shown that optimum surge current performance for small inverters can be achieved, whether stepped, Masc Thesis for Electrical Engineering Jarmo Venalainen -4- trapezoidal or sinewave, by utilizing output current regulation in the inverter. This is demonstrated by implementing a hysteretic output current regulation circuit into a small generic 300W inverter. In the final section, switching losses in the output bridge devices are looked at in detail, and it is shown that they can be greatly reduced by the introduction of a small amount of series inductance. All simulations are done with PSIM, by Dr. Jin. Masc Thesis for Electrical Engineering Jarmo Venalainen -5- SECTION 2: Inrush Current Characteristics of Typical AC loads Experimental measurements of the start up inrush current in typical consumer type A C loads. 2.1 Incandescent Light Bulbs Filament type light bulbs are perhaps the most common A C load, and purely resistive. However, due to the fact that the filament must heat up from room temperature to more than a thousand degrees Kelvin, the resistance of the filament changes by an order of magnitude during start up. For example, a typical 100W light bulb starts off with a cold resistance of about 10 ohms, which then rises to a steady state operating resistance of approximately 100 ohms in a few mS. This large resistance swing results in start up surge currents an order of magnitude larger than the steady state current. Shown on the next page is the experimentally measured surge current for a Phillips 75 W soft white incandescent light bulb, Masc Thesis for Electrical Engineering Jarmo Venalainen -6- Ch2 Ch 1 SOOmV M 25ms Figure 3. Measured inrush current for a 75W incandescent light bulb In the graph above, the instantaneous voltage at the point where the switch is thrown is about 125 V, and the peak surge current is about 8.7 Amps, (870 mV with the current probe set to 100m V/Amp). This translates to an effective surge load of just under 1100 Watts. During the second half AC cycle, the peak current is down to about 3.6 Amps, and it settles to its steady state value after about three full AC cycles. Although the steady state load is very small, the transient load during the first AC cycle is Masc Thesis for Electrical Engineering Jarmo Venalainen more than an order of magnitude larger. When this current is provided by the output bridge of a small inverter, the surge pulse, though only about 2 mS in duration, is of a large enough amplitude that it comes close exceeding the safe operating area limits of a typical output FET such as an IRF630. SEE APPENDIX D. It should also be noted that this surge was created by only one light bulb, quite frequently inverters are asked to simultaneously switch on multiple light bulbs, which severely compounds the problem. 2.2 Rectified Capacitive Loads Another common type of household load is a capacitive rectified power supply. This kind of front end power supply circuit is very common, regardless of how the power isfilteredand regulated deeper within the load device, and is found in most modern, TV's, computers, stereos, VCR's, and many other such appliances and products. Masc Thesis for Electrical Engineering Jarmo Venalainen -8- Shown below is a typical capacitive rectified front end for a power supply, R C^; 110VAC IN DC POWER TO NEXT STAGE Figure 4. Capacitive rectified power supply input stage. Although the actual steady state load in these devices is often only a few hundred Watts, during start up, the fully discharged bus capacitor as well as all the rest of the discharged circuits in the load, present what is essentially a short circuit to the source AC voltage. This surge current is usually somewhat limited by designers by using series impedance, R, as shown in the schematic above. The amount of surge limitation however is typically very little given the generous AC grid current supply characteristics as was discussed above. Masc Thesis for Electrical Engineering Jarmo Venalainen A typical capacitive rectified load is a common computer monitor. Shown below is the start up surge for a 13" - IBM PS/1 monitor, Ch2 Ch 1 Chl" 100W HH T"V M 25ms Figure 5. Measured inrush surge current for 13 " IBM PS/1 monitor. The peak current is 22.2 Amps at a switching instant step voltage of 135 V, (just under 3000 W). The surge dies to 9.6 Amps peak during the next 14 AC cycle, then to 5 Amps peak for the next 10 cycles, finally decaying to a steady state current of about 2 amps peak after about 12 full AC cycles. In the case of capacitive rectified loads, even the steady state peak current is exaggerated from the actual steady state load requirements due to current cresting caused by the capacitive rectified input stage. In the graph on the next page, the monitor current is Masc Thesis for Electrical Engineering Jarmo Venalainen -10- shown under steady state conditions. The capacitive rectified load can be seen only drawing currentfromthe AC source while the voltage in the bulk capacitor is less than the instantaneous line voltage. Ch2 Ch 1 Chl 100 V\> MB 50mv M 2.5ms Figure 6. Steady state input current into 13" IBM PS/1 monitor Typical steady state peak currents drawn by various capacitive rectified loads are 4 - 7 times larger than would be the required peak current if the load were purely resistive. The ratio between the peak value drawn by the capacitive rectified load versus a resistive load of the same value is known as the crest factor. In this case, for small inverters, the problem is one of being able to provide the very large peak current at start up, and being able to provide the Masc Thesis for Electrical Engineering Jarmo Venalainen -11- steady state peak currents during every cycle of normal operation. When multiple computers and monitors are connected to a single inverter, the peak currents are ALL inherently synchronized with each other and therefore additive. Due to the start up and current crest factor problems, a typical 1000W inverter can only operate about 300 - 400W worth of capacitive rectified loads. 2.3 Compact Fluorescent light Bulbs Some very small loads, such as self starting compact fluorescent light bulbs, also use capacitive rectified front ends in their power supplies. In this case the actual load is very small, 10-30 Watts, so the value of the bus capacitance and its surge resistance is also very small. The result is that although the load itself is almost negligible for even the smallest inverters, the surge load into the low impedance bus capacitor can be of the order of 20 times larger than this. Masc Thesis for Electrical Engineering Jarmo Venalainen -12- 4 Amp Chl 100 VV 'QJffljj' 200mV " M " 5ms Figure 7. Inrush current into self starting compact fluorescent light bulb. Once again, as for the monitor, due to the nature of the capacitive rectified load, the peak currents of all the lights will be synchronized when many of them are connected in parallel. In practice, due to this problem, often no more than 3 compact fluorescent lights with can be operated from a small inverter, such as a 300W model. In this case the average load is only about 70W, versus the possible 300W which the inverter should be capable of providing. Masc Thesis for Electrical Engineering Jarmo Venalainen -13- 2.4 Inductive Loads Another class of standard consumer loads are inductive loads. Examples in this category are motor loads and ballast driven fluorescent lights. These types of loads do not present the surge current problems shown previously. In this case, although the series inductance shifts the phase of the output current, it also serves to limit surge currents. Shown below is the start up surge for a 75W ballast driven fluorescent light, and a 300W handheld drill. Chl 100 V% WiW 50mV M 5ms Figure 8. Inrush current into ballast typefluorescentlight. Masc Thesis for Electrical Engineering Jarmo Venalainen -14- VOLTAGE CURRENT CM 100 V HiB 500mV M 25ms Figure 9. Start up surge into 300W handheld drill Masc Thesis for Electrical Engineering Jarmo Venalainen -15- 3 Load Simulations 3.1 Analytical Investigation of the start up inrush current in AC loads: The largest peak surge current occurs during thefirsthalf AC cycle, and by the second AC half cycle, the peak is down by about 50% from thefirstcycle. Analytically the current during thefirstVi cycle can be described by a series RC circuit. 9 fort=0to8 l/3mSec Figure 10 Series RC circuit Where, the values of R, and C depend on the characteristics of the particular load. At the instant when the switch is thrown, the capacitor is fully discharged, leaving only the resistance, R, as the circuit impedance. At any time after the switch is thrown, the capacitor begins to charge up, and hence the current through the circuit begins to go down. Masc Thesis for Electrical Engineering Jarmo Venalainen -16- A series RC circuit follows a first order linear differential equation, V sincot = — + Rl where: 0 Q = charge on capacitor 1= current through circuit E q n J V smat = — + R ~ C dt 0 n For which the general solution is, i(t) = Ae t/r + Bs'm(cot-f)x Eqn2 r = RC where: (r 0 = arctan \R; Where A and B are determined by initial conditions, and in this case are a function of the point at which the load is turned on. In general, the load could be switched on at any point during the AC cycle. Shown on the next page is a graph of the load voltage with two different switching points, (p = 30° and (p = 40°, showing the step voltage change which results in each case. Masc Thesis for Electrical Engineering Jarmo Venalainen -17- 200 Figure 11 Instantaneous load voltage at different switching points To simulate a particular load, R is chosen to be equal to the surge resistance of the load and C is chosen to give the correct time constant for the surge in the load. For example, based on the experimental results for the 75 W light bulb the surge resistance is about 17 ohms, and the time constant is about 3 mS. Using these values, the required value of C can be computed using, T = RC, in this case giving a value of 175 uF. The graph on the following page shows the simulated surge current for the first half AC cycle for a 75 W bulb at four different switching angles. The time scale is in degrees, where 90° corresponds to one complete AC half cycle, i.e. 8 1/3 mSec. Masc Thesis for Electrical Engineering Jarmo Venalainen -18- I 0 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I TIME (milli seconds) Figure 12 Simulated- surge current for first 'A AC cycle Switching the load on at a zero crossing produces the lowest peak surge, since in this case the voltage ramps up gradually along with the 60 Hz AC cycle. If the load is switched on at any other point during the cycle, then the step change in voltage, produces a step change in current. For the step change conditions, the peak current at the switching instant is limited only by the surge impedance in the circuit, consisting of the circuit resistance and a negligible amount of inductance in the wiring. The table on the following page lists the peak surge current magnitude as a function of the switching delay in degrees. Masc Thesis for Electrical Engineering Jarmo Venalainen -19- switching angle (degrees) 0° 54° 90° 120° peak surge (Amps) 13.4 15.0 16.9 14.2 Table 2 Simulation results ofpeak surge current versus switching angle for monitor load In general, the long term solution for current is characterized by a decaying transient component and a driven steady state component. The peak surge current is determined primarily by the magnitude of the surge impedance, R in the load, and secondarily by the switching angle, which determines the step voltage at the point of switching. It is of interest to note that the single most significant factor which determines the peak surge current is the surge impedance of the load, and changing the switching pointfroma zero crossing to the worst case 90° point, only affects the peak surge by 20%. The preceding discussion focuses on the peak surge during the first half cycle, showing that the main determinant of the peak surge is simply the surge impedance of the load. The previous model, however, is only valid for the first A AC cycle. The next section goes on to l develop complete load models. Masc Thesis for Electrical Engineering Jarmo Venalainen -20- 3.2 Load Models 3.2.1 Incandescent light bulbs: A complete load model for the incandescent light could be created with a piecewise linear resistance. I.E. increasing values of resistance would be switched into the circuit as a function of time. Alternately, it can be created by utilizing a capacitive rectified circuit, where the transient capacitor current represents the increased current during the time the filament is heating up. In this model, a parallel resistance equal to the steady state resistance of the light bulb provides for the steady state current of the bulb. Below is the complete load model for a simulated incandescent light bulb load. AC SOURCE H<3 Figure 13 Incandescent light bulb load simulation Masc Thesis for Electrical Engineering Janno Venalainen -21- Rl is the primary load resistance which is chosen to give the normal operating Wattage of the bulb. R2 and C are chosen so that a simulated filament heating current surge is produced. For example to simulate the 75W bulb which was tested previously, Rl is chosen to be 210 ohms to simulate the steady state load of 75W. The surge current was measured at 8.7 Amps when driven by an initial step voltage of 147 volts, therefore the surge resistance needs to be 17 ohms. Finally the time constant for the filament heating surge current is about 3 mS, so C=T75uF. Shown on the next page is the simulated and measured surge current for the 75W incandescent light bulb. Masc Thesis for Electrical Engineering Jarmo Venalainen -22- 10 - 8 -• 6 £ 111 i 4 i -• tL 2 I -• 3° -2 I f A \I \i - -4 \/ /\ \/ / \ v TIME S\ \s / N Z X ,' > -6 Figure 14 Simulated inrush current into 75W incandescent light bulb Ch2 Ch 1 Chl 100W fflffi 500mV M 25ms Figure 15 Measured inrush current into 7SW incandescent light bulb Jarmo Venalainen Masc Thesis for Electrical Engineering -23- As can be seen the simulated load current closely follows the actual measured current. The primary difference being that in the capacitive rectified simulation, the transient surge current into the rectified series RC circuit is not drawn for complete half cycles. Rather, current is drawn into the capacitor only at the peaks of the AC cycles when the capacitor voltage is less than the instantaneous line voltage, as is characteristic for capacitive rectified loads. The simulation does however arrive at the same peak currents for all AC pulses, and very closely follows the measured load current during the criticalfirsthalf cycle. Masc Thesis for Electrical Engineering Jarmo Venalainen -24- 3.2.2. Rectified Capacitive Loads A typical rectified capacitive load is as shown below, ANY Rs C ^ ~W Rload i Figure 16 Typical capacitive rectified load The value of the bulk storage capacitor is typically quite large so as to minimize the ripple current in the load, Rload. For the PS/1 computer monitor which was previously measured, the steady state RMS load current is 350mA, and the peak surge current is 22.2 Amps at a step voltage of 147 Volts, which gives a surge resistance of 7.4 ohms. The value of the bulk capacitance is 1350 uF, and the steady state load is 600 ohms. Shown on the next page is the measured and simulated inrush surge into a capacitive rectified load, (13" IBM PS/1 monitor). Masc Thesis for Electrical Engineering Jarmo Venalainen -25- 10 5 H V ° 1 v " \i v/ 10 ~ B D O -15 TIME -20 i -25 F/gHrt; / 7 Simulated inrush surge into 13" IBM PS/1 monitor Ch2 Ch 1 cm IOO w TV M 25ms Figure 18 Measured inrush surge current into IBM PS/1 monitor Jarmo Venalainen Masc Thesis for Electrical Engineering -26- The simulated surge current closely follows the measured. The major difference being that the measured monitor load appears to be drawing some additional resistive current outside of the capacitive rectified current. This can be seen as a current drawn outside of the peak currents as shown on the graph inside the green circle. 3.2.3 Compact Fluorescent Light A compact fluorescent light is a rectified capacitive load, except that the values of the surge resistance and bus capacitance differ. For the 20W Phillips light which was tested, the surge current was 4Amps at a step voltage of 100V, giving a surge resistance of 25ohms. The steady state load is 0.28Amps, giving a steady state load resistance of 430ohms. Finally, the surge current transient lasted about 5mS, giving a required C value of 20uF. Shown on the next page is the simulation with these values as well as the original measured surge current, Masc Thesis for Electrical Engineering Jarmo Venalainen -27- 5 4 3 UJ I D O 0 -1 • -2 l»MHII I M A I y A A ft ft ft i/ ii TIME i/ y i > Figure 19 Simulated surge current into self starting compact fluorescent light bulb Ch2 Ch 1 CrTl 100 VK 200mV M 5ms Figure 20 Measured surge current into self starting compact fluorescent light bulb Masc Thesis for Electrical Engineering Jarmo Venalainen -28- 3.2.4 Inductive Loads Motor loads and ballast driven fluorescent lights are inductive, and do not exhibit the start up surge current problems associated with the incandescent and capacitive rectified loads. They do however, produce a large amount phase shift between the AC voltage and current. A full bridge topology as utilized in small inverters, however, has a path for this phase shifted current even during the off period of the bridge devices , by virtue of the MOSFET body diodes as shown below. CURRENT HV BUS C A P GATE DRIVES FROM CONTROLLER Figure 21 Load current path during bridge device off state On the following page are shown the start up current for the ballast driven fluorescent light and 300W handheld drill when driven by a small inverter. The current in either case is stable Jarmo Venalainen Masc Thesis for Electrical Engineering -29- and bounded, although it should be pointed out that the peak surge into the 300W drill at 5 Amps, is over limit for the 300W inverter. di1 ' ' 100 v \ ' MM 1 'SOmV "M ' 5ms Figure 22 Measured inrush current for ballast driven fluorescent light when driven by modified sinewave inverter Chl 100 V Mfri SOOmV M 25ms Figure 23 Measured inrush surge for 300Whandheld drill when driven by modified sinewave inverter Masc Thesis for Electrical Engineering Jarmo Venalainen -30- 4 Simulated Inverter Models 4.1 Single and Multi Step Models A typical output bridge in a small inverter consists of a full bridge configuration as shown below. 5" OUTPUT HIGH VOLTAGE DC INPUT GATE DRIVES FROM CONTROLLER Figure 24 Output bridge of typical small inverter To produce a tri state modified "sinewave", diagonally opposite pairs of switches are turned on with the timing sequence as shown on the next page. Masc Thesis for Electrical Engineering Jarmo Venalainen -31- OUTPUT ov -V 51 and S3 ON OFF, 52 and S4 ON OFF Figure 25 Gate drive signals for output bridge, to produce modified sinewave output And, the resulting output waveform is as follows, 169 V 145V OmS 16 2/3 mS Figure 26 Modified sinewave output waveform Masc Thesis for Electrical Engineering Jarmo Venalainen -32- In order to produce multi step waves, two approaches are possible. One is to use PWM techniques to switch the output bridge power devices to produce the desired output waveform. The second is to use additional DC-DC circuitry to create multiple DC potentials and switching circuits to switch them accordingly to produce the multi step output. For this analysis, multiple step waveforms are simulated by using separate DC sources as shown below. DC/DC n OUTPUT DC/DC 2 (+) dk DC/DC 1 (+) GATE DRIVES FROM DC/AC CONTROLLER GATE DRIVES FROM S T E P CONTROL Figure 27 Multi step inverter simulation model The gate drive signal for the step control is synchronized with the DC/AC bridge control to produce the desired step waveform. For a three step system, the complete timing sequence is Masc Thesis for Electrical Engineering Jarmo Venalainen -33- as follows, where signals SI, S2, S3 AND S4 are the bridge drive signals, and signals S5, S6, and S7 are the step control signals as shown labeled in diagram 27 on the previous page. S7J1 S5 | S1,S4 S2,S3 | | I 1 | 1 | | | [ | 1 1 | _ Figure 28 Gate drive signals for multi step inverter Regardless of the number of steps, the multi step waveforms are made to follow a pure sinewave as closely possible. In this regard, two parameters are of primary importance. The first one is that the Root Mean Square, (RMS) voltage of the stepped wave should be equal to that of a pure sinewave, and the second is that Total Harmonic Distortion, (THD), as compared to a pure sinewave, should be as low as possible. The following discussion goes through the process of determining the step heights and pulse lengths for a 1, 2, 3 and 4 step wave. Masc Thesis for Electrical Engineering Jarmo Venalainen -34- 4.2 THD and RMS Voltage 4.2.1 One Step Waves In a one step wave there are only two parameters to be set, the amplitude, E, and the pulse length, Q. t=0 \ hnrH \ Figure 29 Definition ofpulse length and step height variables for modified sinewave Since the amplitude of the wave must be set in the end to give the correct rms voltage regardless of the chosen pulse length, this leaves the on period of the wave as the determinant oftheT.H.D.. The wave is symmetrical and hence has no even harmonics. Taking the t=0 at the center of the single pulse as shown in figure 29 above, yields the following Fourier Series, Masc Thesis for Electrical Engineering Jarmo Venalainen -35- a.. = 0 b =— n f Ecosnxdx = ^-sin— nn 2 77 = 1,3,5,... which gives an RMS voltage for each term as, 242E RMS ( ) V N . =— s nO m — nn " = 1.3.5,. Eqn 4 2 The Total Harmonic Distortion Factor is defined as, V 2 T.H.D.= +V 2{rms) ^ v +V 2 v 2 3(rms) ^ V 1 r + 2 4(rms)^ 2 r V y n(rms) Eqn 5 1 (rms) Since the sum of the rms voltages of all the harmonic components is equal to rms voltage of the complete wave minus the rms voltage of the fundamental, equation 5 can be rewritten as, V 2 T.H.D.= -V 1 (rms) rms 1 Masc Thesis for Electrical Engineering Eqn 6 (rms) Jarmo Venalainen -36- Eqn3 Where V m s is the rms voltage of the quasi "sinewave", and V 1(rms) is the rms voltage of the fundamental component. Using the parameters as set in figure 29, the rms value of the complete wave is, Eqn 7 And the rms value of the fundamental component is given by equation 4, as jr 2^2E . 9 n 2 / 1 X Eqn 8 Substituting these into equation 6, yields the following expression, H9 T.H.D = V (2-J2E \n J (242E . e\ . 0} sin— Eqn 9 sin— V n Masc Thesis for Electrical Engineering 2) Jarmo Venalainen -37- This equation needs to be solved to find the value of 0 which will give the minimum T.H.D. Using numerical methods in Matlab, T.H.D. as a function of 9 has the following form, 0.551 0.25 1.5 1 T.H.D. versus pulse length for a quasi sinewave 1 . 1 2 1 2.5 Pulse legth. degrees 1 • 3 1 3.5 Figure 30 T.H.D. as function ofpulse length for a single step wave The minimum T.H.D. is 29% at a pulse length of 130°, however the trough is fairly wide, so any pulse length between 126° to 143° will give a T.H.D. of less than 30%. We want the rms output voltage to be 120 VAC, so using equation 7, and setting 9 to 130° degrees gives, E=141 V. The minimum T.H.D. for a single step modified sinewave occurs when the on period is 130°, and the step voltage isl41 V. Masc Thesis for Electrical Engineering • -38- Jarmo Venalainen 4.2.2 Two, Three and Four Step Waves For a two step waveform there are four parameters to set, the amplitude and on period of each step, as shown below, Figure 31 Variable definition for two step wave For a three step waveform, there are 6, and for a 4 step,8. C <> |3 5 <>2 Figure 32 Variable definition for three step wave Masc Thesis for Electrical Engineering Jarmo Venalainen -39- Regardless of the number of steps, the aim is still to get the correct R M S voltage while minimizing the THD. The problem of specifying the step sizes and pulse lengths for each individual step in a multi step waveform becomes an n-dimensional minimization problem, where n, is equal to 2 times the number of steps. Any step waveform can be decomposed into a sum of multiple single step quasi "sinewaves" as shown below, u=u'+u" E ' El' Figure 33 Decomposition of two step wave into two, single step waves Masc Thesis for Electrical Engineering Jarmo Venalainen -40- Referring to figure 32, and equation 7, the Vrms voltage for the complete two step wave is, rms rms Similarly, based on figure 32 and equation 4, the rms voltage of the fundamental is given by, • s i n - 71 + •sm— Eqn 11 By analogy, the rms voltage for a step wave with m steps, and its first harmonic is, v = IYE ^ -\ I / rms , Eqn 12 * - \ m=\ n m t~7 y m- 1,3,5, 2 w sin— 71 Masc Thesis for Electrical Engineering m = 1,3>5, n Eqn 13 Jarmo Venalainen -41- For the two step wave the T.H.D. expression becomes, 2y[2E, . 0, 2^2E . 0. sin— + sin V n 2 n 7 V T.H.D.= n n J 242E X V n . 0 2J2E sin— + 2 . 0, sin 2 X By normalizing the maximum voltage for the two step wave, E m a x Eqn 14 , one variable can be eliminated, ^max - E + E x 7 Eqn 15 Eliminating E from equation 14, 2 fl T.H.D.= v n (!-£,) fl 2V2(l-E,)—sin. 0 ) 2y[2E, . sin—+ 2 L 2 1 Eqn 16 it -sin— + 2 Masc Thesis for Electrical Engineering it sin Jarmo Venalainen -42- This three dimensional minimization problem can be solved by numerical methods by systematically computing the T.H.D. for all possible combinations of the given variables and looking for the minimum. Using Matlab, (see appendix A), gives the following result, Minimum T.H.D.. step lengths, and step sizes for a two step wave: T.H.D.(mm) = \6.6% at 9 - 2.1 rad X 9 = l.lrad 2 E = 0.5 x E = 0.5 2 Masc Thesis for Electrical Engineering Jarmo Venalainen -43- To complete calculation, the maximum voltage must be set so that the rms voltage of the two step wave is equal to the desired rms voltage, (120 VAC). V.ac-rms and, E\ ~ E = — E 2 M&X and, max 2 1 Eqn 17 (EV((2J-U)) 120 = V 2 J n J + (^max ) 2 120 = 0.318 2 v 2 max ; +0.54l(£ m a x y 120 = 0 . 0 7 9 5 ( £ L ) 0 . 5 4 l ( £ 2 + max ) 2 120 = 0.6205E 2 23207 = E Masc Thesis for Electrical Engineering max max Jarmo Venalainen -44- To reduce the dimension of the minimization, for 3 and 4 step waves, the incremental step sizes will be set to E MAX / 3 and E MAX / 4 respectively. Using equations 6, 12 and 13, and the numerical optimization programs in Appendix A, the minimum T.H.D and. pulse lengths for the three and four step waves were determined. After the minimum T.H.D. pulse lengths were known, the maximum voltage E M A X was determined using equation 12. The following table lists the complete results. #of e T.H.D. e 2 steps 3 1 29% 130° 2 17% 97° 155° 3 12% 80° 126° 160° 4 9% 69° 109° 138° e 4 166° E, step size 141V Emax 152V E /2 158V E /3 160V E /4 max max max Table 3 Minimum T.H.D. step voltages and pulse lengths for 1, 2, 3 and 4 step waves Masc Thesis for Electrical Engineering Jarmo Venalainen -45- 4.3 Simulations of surge currents with one, two, three and four step waves 4.3.1. Incandescent Light Bulb The following graph shows the measured surge for an incandescent light bulb when driven by a modified sinewave inverter, and on the following pages are simulations of how the input surge current varies with a 1, 2, 3, and 4 step waveform. VOLTAGE CURRENT Ch1 100 V HUM SOomV M 10ms Figure 34 Measured inrush surge for 75W incandescent light bulb when driven by inverter Masc Thesis for Electrical Engineering Jarmo Venalainen -46- 10 8 6 HI 4 TIME V § 2 O 0 TZJ Figure 35 Simulated inrush surge for 75W incandescent light bulb when driven by inverter 8 lil a: a: 3 U 0 -2 TIME Figure 36 Simulated inrush surge for 75 tV incandescent light bulb when driven by 2 step wave Masc Thesis for Electrical Engineering Jarmo Venalainen -47- As can bee seen the surge current in the one step simulation is very close to that of the measured. One difference is that AC output voltage droops briefly after the load is turned until the voltage control loop can respond. 6 5 Z 3 UJ OC 2 OC \J r\ r\ r\ /A w w w i TIME Figure 37 Simulated inrush surge for 7SW incandescent light bulb when driven by 3 step wave 6 5 4 31 -1 -2 r\ r\ r\ y w TIME w r\ Figure 38 Simulated inrush surge for 75W incandescent light bulb when driven by 4 step wave Masc Thesis for Electrical Engineering Jarmo Venalainen -48- In the simulations there is a 50% reduction in the maximum peak current, from 9.3 Amps with one step down to 5.2 Amps with four steps. However, this reduction is only available if the load is switched on at a zero crossing. For any other switching point the surge will be determined by the step voltage at the switching point. Also visible is the fact that the filament warms up during the first half cycle, I.E. the transient surge lasts only for the first half period. For loads which have surge currents of longer duration, there is much less reduction in peak surge currents between 1 step and 4 step waves, even if the load is switched on at a zero crossing. 4.3.2. 13" Computer Monitor Shown on the next page is the measured and simulated surge for the IBM PS/1 monitor when driven with a one step modified sinewave. Masc Thesis for Electrical Engineering Jarmo Venalainen -49- VOLTAGE CURRENT CHI F/gwre 3 9 TWV BOB 500mV M 10ms Measured inrush surge for 13" IBM PS/1 monitor when driven by modified sinewave 25 20 15 bo IS 5 \ 0 -10 •15 ! r^-i TIME > Figure 40 Simulated inrush surge for 13" IBM PS/1 monitor when driven by modified sinewave Masc Thesis for Electrical Engineering Jarmo Venalainen -50- 25 2 0 I— Z 1 5 1 0 U h U -10 " ^ TIME -15 Figure 41 Simulated inrush surge for 13" IBM PS/1 monitor when driven by 2 step wave 25 j 20 15 - Z 10 LU txL 5 - £ - 0 -O -5 10 -- 17 T J TIME Figure 42 Simulated inrush surge for 13" IBM PS/1 monitor when driven by 3 step wave Masc Thesis for Electrical Engineering Jarmo Venalainen -51- 25 20 15 •A H K \ O ( ,1 5 -10 -15 H V u TIME n u m u ^ Figure 43 Simulated inrush surge for 13" IBM PS/1 monitor when driven by 4 step wave In this case introducing additional steps does not significantly reduce the peak surge current, (22 Amps for one step down to 21 Amps for four steps), and this only if the load is turned on at a zero crossing. In the limit as the number of steps goes to infinity the system becomes equal to that of a pure sinewave. From the previous results shown earlier, this means that there will at most be 20% reduction in the peak surge current and this is only present if the load is switched on at zero crossing. Masc Thesis for Electrical Engineering Jarmo Venalainen -52- 4.4 Trapezoidal Waves From the analytical analysis into the surge current on pages 14 - 17, and from previous discussion on multi step waves, it is clear that reducing the rise rate of a modified sinewave will at best reduce the peak surge current by 20%, and this only under zero voltage switching conditions. The next three simulations, show the surge current for the 13" IBM PS/1 monitor when driven with a sinewave, a one step wave and trapezoidal wave. As can be seen the trapezoidal wave produces very little reduction in the peak surge. 20 -15 A Figure 44 Simulated inrush surge for 13" IBM PS/1 monitor when driven by sinewave Masc Thesis for Electrical Engineering Jarmo Venalainen -53- Figure 45 Simulated inrush surge for 13" IBM PS/1 monitor when driven by modified sinewave CE CC ZD U N UJ 1 - 1 E — ? Figure 46 Simulated inrush surge for 13" IBM PS/1 monitor when driven by trapezoidal wave Masc Thesis for Electrical Engineering Jarmo Venalainen -54- 5 Hysteretic Current Control 5.1 Hysteretic Current Control Simulation Model In the previous three sections it was shown that most AC loads have inrush surge currents with peak magnitudes up to 10 times their normal steady state values for the first few AC cycles. Furthermore it was shown that generating multiple step, trapezoidal, or even sinusoidal waveforms has negligible effect on reducing the peak inrush surge current, (reducing it by 2 0 % at best). Even the smallest inverters are nevertheless called to operate all such loads, and since they are inherently limited in their current sourcing ability, then current regulation is left as the solution. With current regulation, the inverter will behave as a voltage source when the output current is below the maximum which the inverter can source, and become a current source whenever the load tries to draw more current. The specific regulation level is set according to the capability of a particular inverter. Implementation of current regulation into a switch mode inverter requires a current control circuit in the form of a current loop. A number of approaches are well known, examples of which are average current control, peak current control and hysteretic current control. The current control method used in this instance is implemented through the use of hysteretic current control in the DC-DC section. Hysteretic current control has as its benefits inherent stability and simplicity at the expense of accuracy in the controlled current. Simplicity is Masc Thesis for Electrical Engineering Jarmo Venalainen -55- always desired in consumer electronics not only for reliability reasons, but also for achieving the lowest possible cost in a fiercely competitive market. Accuracy of the current control is not necessary here, because the intent is to control peak currents which are an order of magnitude out of bounds, so the residual ripple inherent in hysteretic current control is not significant in this application. The following schematic shows a typical 300W modified sinewave inverter utilizing a pushpull DC-DC section and full bridge DC-AC as discussed previously. Figure 47 Basic 300W inverter utilizing push-pull DC-DC stage andfull bridge DC-AC stage Masc Thesis for Electrical Engineering Jarmo Venalainen -56- This circuit can be operated open loop, since the push-pull topology DC-DC can only produce a peak high voltage DC bus voltage which is limited by the turns ratio of the transformer, analogous to how a conventional 60Hz transformer operates. In practice however, most inverters use a voltage feedback loop to make the DC bus voltage more stable. Shown on the following page is the simulation model of the hysteretically current limited inverter. The circuit is the same as shown on page 53, except now it has a voltage feedback loop and a hysteretic current limit circuit. In this circuit, the voltage loop operates normally provided Masc Thesis for Electrical Engineering Jarmo Venalainen -57- Masc Thesis for Electrical Engineering Jarmo Venalainen -58- that the output current is below the set point as set by the reference source, I limit set. When the output current goes above the set point, the current limit OP amp immediately goes low and shuts down the gate drive to the primary side FET's. With the DC-DC PWM shut down, the output current begins to decay as the DC bus capacitor discharges. After the bus capacitor has discharged to a point where the output current is below the set point, the current limit OP amp once again allows the DC-DC PWM to start up. The net effect is that the current control OP-AMP shuts down the primary side DC-DC PWM gate drives whenever the current is above the set point and allows them to occur whenever the output current is below the set point. Hysteresis is introduced into the system, by either having hysteresis on the current control OP-AMP itself, or by putting an integrator into the current sensing signal, and in this case the latter was used and can be seen as RX and CX on the inverting input of the current limit comparator. The amount of hysteresis determines the magnitude of the ripple in the controlled output current. The circuit itself has no impact on the steady state efficiency of the inverter since it neither introduces nor eliminates any switchings during normal steady state operation, merely eliminating some during transient conditions. Shown on the next page is the simulated surge current into the 13" IBM PS/1 monitor with the current limit circuit switched on, and set at a 2.5Amps. Masc Thesis for Electrical Engineering Jarmo Venalainen -59- Figure 49 Simulated inrush surge for 13" IBM PS/1 monitor when driven current controlled inverter Figure 50 Simulated inrush surge for 13" IBM PS/I monitor when driven by current controlled inverter, showing current control and HV bus voltage ramp up Masc Thesis for Electrical Engineering Jarmo Venalainen -60- As can be seen the output current is limited to 2.5 Amps for the first few AC cycles after start up. In the figure below, the current limit circuit can be seen cutting out after the 8 AC 14 th cycle. 0.02 0.04 0.06 Time (s) Figure 51 Simulated inrush surge current and inverter output voltage for 13" IBM PS/1 monitor when driven by modified sinewave inverter with current control 5.2 Hysteretic Current Control Circuit The hysteretic current control circuit was implemented in a readily available 300W inverter. In this inverter, the DC-DC PWM utilizes a 3525 PWM chip. This chip directly provides the required push-pull drive signals and also has a couple of other useful features Masc Thesis for Electrical Engineering Jarmo Venalainen -61- V error signal +Vin 3255 >Vref Rl 4S- • +IN R2 > -IN R3 HV out A« d^C2 • COMP B < SHUTDOWN Shutdown signal SOFT START Figure 52 DC-DC P WM circuit for 3001V inverter including a soft start circuit, built in 5V reference and an external compensation pin on the error amp. Figure 53 above shows a schematic for a 3525 PWM with the main signals. Voltage divider Rl and R2 set the set point for the desired HV bus voltage by utilizing the built in +5V, Vref signal. C2 and R3 provide for compensation on the error amp, typically in small inverters, as an integrator with fairly high time constant. Push-pull gate drive signals Masc Thesis for Electrical Engineering Jarmo Venalainen -62- are produced at the output pins A and B. The soft start capacitor value determines the rate at which the 3525 PWM starts up on power up, or at any time after the shutdown signal has commanded a shutdown. The hysteretic current control circuit as implemented, is shown in the schematic below in figure 54. V error signal 3255 . Vref Rl • +IN R2 • - IN AC OUT A R3 ^=:C2 1 , COMP 1 U F T ^ B SOFT START Cl Figure 53 Simulation of300W inverter c/w voltage and current control Comparator, COMP1, has an integrator on the input with a time constant of mS, which Masc Thesis for Electrical Engineering Jarmo Venalainen -63- provides the required hysteresis for the circuit, and also has a gain of 10 to amplify the sensed current signal. Given that the current sense resistor is 0.1 ohms, the output of COMP1 then becomes a voltage which is directly proportional to the output current. Resistors, R5 and R7, set the current limit, which given the +5V reference voltage and values shown, is set at 2.5 Amps, and it can be adjusted by changing R5/R7. The shutdown pin on the 3525 PWM has a small amount of capacitance to prevent noise signals from triggering the shutdown pin. 5.3 Experimental Results with Hysteretic Current Control Shown on the next page is the measured surge current graph for the 13" IBM PS/1 monitor without the current limit circuit switched on. Jarmo Venalainen Masc Thesis for Electrical Engineering -64- VOLTAGE CURRENT CFfi 100V Egig 500m\T M 10ms Figure 54 Measured inrush surge for 13" IBM PS/1 monitor when driven by modified sinewave inverter VOLTAGE CURRENT HJfl 100 V Ch2 SOOmV M 50 ms Figure 55 Measured inrush surge current and inverter output voltage for 13" IBM PS/1 monitor when driven by modified sinewave inverter Masc Thesis for Electrical Engineering Jarmo Venalainen -65- Without the current limit, the monitor draws a peak current of 22 Amps, and tries to draw more than 5 Amps for the next few cycles. The inverter cannot supply 5 Amps, as evidenced by the bus voltage which drops to about 105 V. The inverter output peak voltage eventually rises to near its normal value after about 30 full AC cycles. With the current limit circuit switched on, the output current is limited to 2.5 Amps. The hysteresis band is about 1 Amp peak to peak, and it has a period of about 0.8 mS. It should be noted that the current limit circuit cannot regulate the current at the very beginning of each AC cycle. This is because the HV bus capacitor is fully charged at these points, so that even Masc Thesis for Electrical Engineering Jarmo Venalainen -66- though the DC-DC is shutdown, high levels of current are provided directly by the HV bus capacitor. Shown below is the measured monitor start up surge current and shutdown signal as generated by the hysteretic current controller. SHUTDOWN SIGNAL OUTPUT CURRENT REDUCED RIPPLE-IN THEHYSTERETIC CURRENT REGULATION AS THE mm?-CURRENT DEMAND . OF THE MONITOR DECREASES Chi' ' U V' ' ' 'Higftl'' SOOmv ' iW '5ms Figure 57 Measured inrush surge for 13" IBMPS/1 monitor when driven by inverter with hysteretic current control The inrush surge current limiting can be seen ending after only 6 full AC cycles. Masc Thesis for Electrical Engineering Jarmo Venalainen -67- Similar results for the incandescent light. VOLTAGE Ch1 100 V SOOmV M 10ms Figure 58 Measured inrush surge for 75W incandescent light bulb with no current control CURRENT Chi' Tdd V''' aiB' 500nW ' M : '5ms' Figure 59 Measured inrush surge for 75W incandescent light bulb with hysteretic current control Masc Thesis for Electrical Engineering Jarmo Venalainen -68- In this case the load is switched on halfway through an AC A cycle. With the current limit l circuit switched on, the instantaneous output voltage can be seenfirstdecaying to about 30V during the latter half of thefirstV2 AC cycle as the current limit circuit has told the PWM to shut down. Once the output current is below 1.4 Amps, the PWM starts operating hysteretically and the output voltage can be seen rising up to its nominal value of 145 V by the fourth V2 AC cycle. As shown below, the results are similar in the case of the compact fluorescent light. VOLTAGE CURRENT Chl 100 V HiK 500mv M 2.5ms Figure 60 Measured inrush surge for compact fluorescent light bulb with no current control Masc Thesis for Electrical Engineering Jarmo Venalainen -69- In all cases the current limit circuit keeps the output current in bounds, with exception of the leading edge of each AC pulse. In order to control the current at the leading edge of the AC output pulses, the hysteretic power control would have to be implemented onto the AC bridge power switches, or alternately a method would have to be devised whereby the high voltage bus voltage is brought to zero after each AC half cycle. Perhaps more significant than the peak magnitude of the leading edge current peak is the fact that it occurs exactly at the leading edge of each AC pulse. Since it is exactly at the leading edge, it causes extremely large switching losses. This is looked at in the next section. Masc Thesis for Electrical Engineering Jarmo Venalainen -70- 6 Switching Losses 6.1 Theoretical Analysis In relation to the DC-DC switching devices, output bridge losses in a one step modified "sinewave" inverter are very small. Firstly, because the switching rate in the output bridge is only 120Hz versus about 70KHz for the DC-DC. Secondly, although the on resistance of the high voltage output bridge devices is higher than that of the DC-DC switching devices, this is more than offset by the fact that they need only switch 1/10 the current of the primary side th devices. However, as discussed in the previous sections, looking at the switching in detail shows that for most loads the bridge devices are called on to switch load currents which are many times the measured average load current. Under some circumstances, such as when many capacitive rectified loads, such as compact fluorescent lights are connected in parallel, the start up load can rise well beyond the safe operating region of the FET's, and even under steady state conditions the leading edge current spikes are up to 4 times the steady state current. Switching losses occur at the switching points, when both the current through, and the voltage drop across the switching devices is changing. Graphically this can represented as shown on the next page, Masc Thesis for Electrical Engineering Jarmo Venalainen -71- The peak loss occurs when the switching device is halfway through its switching transition, and the total loss is given by the area under the power, (VI), graph. The following section introduces the switch loss model. Masc Thesis for Electrical Engineering Jarmo Venalainen -72- 6.2 Switching Loss Simulations Shown below is the switching loss simulation model. SWITCH LOSS INTEGRATOR TIME BASE FOR INTEGRATOR Vsense I probe 1 ± ^ • LOAD fvcvs Figure 63 Switch loss sensing model c/w switch loss integrator In this model the voltage across the switching device is equal to the difference between Vs and Vc, which is simply the voltage across the resistor R. The current through the switching device is sensed by current sensor on the output of the Voltage Controlled Voltage Source, (VCVS). The value of R and C set the simulated switching rise rate. The voltage drop across the switching device and the load current are multiplied to produce the switch power loss signal. Finally, the power loss signal is integrated to compute the total energy lost during switching. On the following page are switch loss simulation results. Masc Thesis for Electrical Engineering Jarmo Venalainen -73- integrated switching losses 4 s switching loss with 4 V voltage step switching loss with 2 V voltage step switching loss with 1V voltage step o oc UJ z TIME UJ I iTm H I iTTl I'l I I • I I ' I . • I I I M l ! I ! I i , I ! I I I I I I | ! ! I I I !«• Figure 64 Simulated switch loss with differing voltage steps In the above graph the step voltage is changed from 7 V to IV to 2 V . The peak increases as a 2 function of V , as expected from ohms law. 2 integrated switch losses a 1 o switch loss with 1t rise rate switch loss with 2t rise rate switch loss with 4t rise rate UJ a. 3 UJ z UJ TIME l l l l l M i l l l l l l l I UM II l l l l ' H H l 111 [ M l M I III11 I I Ml IMI11 I M I 111111 111111 Figure 65 Simulated switch losses with differing rise rates The peak loss is independent of rise rate, but the total switching loss rises a function of ~ t 2 Masc Thesis for Electrical Engineering Jarmo Venalainen -74- The simulation below was done with relative load resistances of 1, 2 and 4. Figure 66 Simulated switch losses with differing load values In this case the both the peak loss and total loss vary directly as function of the load. For inverters this means that a 150W monitor will appear as a 3000W load for the output bridge FET's on a cold start up. And even during normal steady state operation any rectified capacitive load will appear by a ratio equal to the crest factor that it creates. This means that even under steady state conditions, loads such as computers and monitors, appear in terms of output bridge switching losses as loads which are 4 to 7 times larger. Or, in other words, a 300W computer system appears as a 1 to 2 kW effective load in terms of output bridge switching losses. Masc Thesis for Electrical Engineering Jarmo Venalainen -75- The step voltage of a modified sinewave needs to be 145 V to satisfy the rms voltage requirement, and since the minimum switching time is set by the characteristics of the power devices, there is only one other parameter which can be changed during the switching time, the current. The current during critical switching period can be reduced by introducing series inductance into the output circuit, as shown below. HV BUS CAP i OUTPUT GATE DRIVES FROM CONTROLLER Figure 67 Series inductor location on output bridge output The amount of inductance is chosen so that it will limit the rise of current for just longer than the switching time of the MOSFET's, i.e in this case about 300nS. Masc Thesis for Electrical Engineering Jarmo Venalainen -76- We know that the surge resistance in A C loads must be so that the surge current is limited to less than about 25 Amps, at voltages of 147V, giving a surge resistance of about 6 ohms. Using T=L/R, L T = — R Eqn 18 \L = TR = (3xl(T )(6) = IS/iH 7 As was shown for the inductive loads, the stored energy in the inductor can be dissipated into the load through the MOSFET body diodes at the end of every A C pulse, (see page 29). The simulation results on the following page show the leading edge switch loss for the 13" I B M PS/1 monitor with and without the 1.8uH series inductor. Masc Thesis for Electrical Engineering Jarmo Venalainen -77- Figure 68 Simulated output bridge switching loss with and without 1.8 uH output inductor With the inductor in place, the peak loss is down by a factor of 10, and the total loss by a factor of 5. Masc Thesis for Electrical Engineering Jarmo Venalainen -78- 6.3 Experimental Switch Loss Measurments The graph below shows the current ramping up on the leading edge of an AC pulse with a compact fluorescent light as the load. The compact fluorescent light appears as a virtually purely capacitive load during the turn on edge. Masc Thesis for Electrical Engineering Jarmo Venalainen -79- As can be seen, the current ramps up in about 500nS, and as this is the time during which the MOSFET voltage drop is also changing from 145V to OV, it is when the switching losses occur. It should be noted that the current is changing from OAmps to 3 Amps, since the shunt resistor used to measure the current, was 0.5ohms. Introducing just luH of inductance gives the following graph. : : : : : CURRENT 6—* '• 1..5uS RISE TIME Figure 70 Output current rise rate into compact fluorescent light bulb with 1 uH of series output inductance The rise time has already increased to 1500nS. Masc Thesis for Electrical Engineering Jarmo Venalainen -80- With a lOuH series inductor, the following graph results. : : : : : :J: : „..[....1 il uS RISE TIME win • H 2V r \ i.„.j.... ' CURRENT I ! IV! 2.5>1S Figure 71 Output current rise rate into compactfluorescentlight bulb with lOuH of series output inductance The rise time is up to 11 microseconds. An Empirical way to confirm that the switching losses are indeed reduced, is to measure the temperature rise of the output bridge FET's with different amounts of series inductance in the circuit. To do this we use a 0.7 uF capacitor as the load. This capacitor will produce quickly rising current edges, but will have a negligible steady state load. This will mean that the heating in the output FET's will be due only to switching losses. The following graph shows Masc Thesis for Electrical Engineering Jarmo Venalainen -81- the current spike on a leading edge of an A C cycle with the inverter driving the capacitor. i—!—r—j—!—•—!—!—j—!—r—i—:—;—:—'•—'•—:—TT—!—!—!—:—!—!—!—r-T~T—!—!—r-s—!—r Ch1 100 V Mftil 500mV M 2.5ms ' ' ' Figure 72 Current spike rate into 0.7 uF capacitor, with no series output inductance With the 0.7uF capacitor as the load, the output bridge FET's reached a temperature of 52.3°C, which was indicative of the switching losses they were experiencing. The following table lists the temperature of the output FET's as function of the output inductor value. Masc Thesis for Electrical Engineering Jarmo Venalainen -82- IND. OuH luH 2.8uH 5.3uH 8.7uH 20uH 40uH 60uH 80uH lOOuH I6O11H °C 52.3° 45.7° 44.4° 38.2° 36.4° 33.1° 32.3° 31.3° 30.7° 30.6° 42.4° Table 4 Output bridge device temperature versus series output inductor value The ambient temperature was 22°C. Clearly the inductor dramatically reduces the switching losses. The temperature figures show that switching losses are reduced by 25% with just 2.8uH of series inductance, and 50%, with 20uH. The graph below shows the rising current with 20uH of series inductance. Core saturation can be seen as a rise in the rate at which the current rises, but is not a problem in this case, since the current only needs to be limited for the 300nS turn on time of the bridge FET's. .... risinijrate ofriseof ciarent due tt saturation of inductor 1 Figure 73 Current spike rate into 0.7 uF capacitor, with 20series Masc Thesis for Electrical Engineering output inductor Jarmo Venalainen -83- Also visible is ringing produced by what is now a series LC circuit under the impact of a step voltage change. Masc Thesis for Electrical Engineering Jarmo Venalainen -84- CONCLUSION: Small inverters have become more and more popular in the last 10 or so years in portable power applications. These inverters are called on to power a very wide variety of typical AC devices. Many of these AC loads exhibit very large inrush currents during start up, as well as steady state current cresting in the case of rectified capacitive loads. Sourcing these large peaking currents presents a serious challenge for small inverters. In this thesis it was shown that using stepped or trapezoidal wave forms had negligible impact in terms of reducing the peak surges. A hysteretic current limit circuit was shown to be an effective solution for limiting inrush surge currents. It was also shown that output bridge switching losses in small single step inverters can be significantly reduced by the use of series inductance in the output circuit. Masc Thesis for Electrical Engineering Jarmo Venalainen -85- APPENDIX A: Matlab T.H.D. minimization program listings Masc ThesisforElectrical Engineering Jarmo Venalainen -86- % T h i s Matlab M - f i l e f i n d s t h e p l o t s t h e u a l u e o f THD u e r s u s % pulse length f o r a s i n g l e step uaueforn x=1.5:0.QQ5:pi d=(x./pi).*0.5 b=(0.9).*sin(x./2) sol=(((a.~2)-(b."2)).*0.5)./b thd=sol plotfx.thd.'b-') xlabel("Pulse length, degrees') y l a b e l ( ' T o t a l Harmonic D i s t o r t i o n F a c t o r , u n i t s ' ) t i t l e ( ' T . H . D . uersus pulse length f o r a quasi sinewaue') % T h i s Matlab l i - f i l e computes t h e minimum u a l u e o f THD f o r a % two s t e p waveform and o u t p u t s t h e p u l s e l e n g t h s and s t e p % s i z e s a t t h e minimum. echo o f f a l l min=1fl for i=1.5:0.81:1.75 for j=2.2:B.01:2.7 for k=0.4:8.81:0.55 echo o f f a l l a1=(i)/pi a2=(k*2)*((j-i)/pi) b=((0.9/2)*sin(i/2))+((0.9/2)*sin(j/2)) b=((0.9*(1-k))*sin(i/2))+((G.9*(k))*sin(j/2)) a=((a1+a2)*0.5) thd=(((a"2)-(b*2))*0.5)/b if t h d <= min min = t h d imin = i jmin = j kmin = k end end end end min jmin imin kmin % T h i s Matlab M - f i l e computes t h e minimum u a l u e o f THD f o r a % three s t e p waveform and o u t p u t s t h e p u l s e l e n g t h s and s t e p % s i z e s a t the minimum. echo o f f a l l min=10 for i=1:0.1:pi for j=1:0.1:pi for k=0:0.1:pi echo o f f a l l a1=(i)/pi a2=(V9)*((j-i)/pi) a3=(1/9)*((k-j)/pi) b=((8.9*(1/3))*sin(i/2))+((0.9*(1/3))*sin(j/2))+((8.9*(1/3))*sin( k/2)) a=((a1+a2+a3)*0.5) thd=(((a~2)-(b*2)ro.5)/b if t h d <= min min = t h d imin = i jmin = j knin = k end end end end min jmin imin knin % T h i s Matlab M - f i l e computes t h e minimum v a l u e o f THD f o r a % f o u r s t e p waveform and o u t p u t s t h e p u l s e l e n g t h s and s t e p % s i z e s a t the minimum. echo o f f all min=10 for i=1:8.1:pi/2 for j=1.5:0.1:pi for k=2:B.1:pi for l=2.5:0.1:pi echo o f f all a1=(i)/pi a2=(9/16)*((j-i)/pi) a3=(1A)*((k-j)/pi) aH=(1/16)*((l-k)/pi) b1=((0.9*(1/i»))*sin(i/2)) b2=((0.9*(1A))*sin(j/2)) b3=((B.9*(1/'»))*sin(k/2)) bit=((fl.9*(1M))*sin(l/2)) a=((a1+a2+a3+ai»)*B.5) b=b1+b2+b3+bi» thd=(((a 2)-(b*2))"B.5)/b A if t h d <= min min = t h d imin = i jmin = j kmin = k Imin = 1 end end end end end min imin jmin kmin Imin APPENDIX B: UC3525B Regulating Pulse Width Modulator Data Sheet. Courtesy of Texas Instruments Masc Thesis for Electrical Engineering Jarmo Venalainen -91- UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B INTEGRATED CIRCUITS mmm U N I T R O D E Regulating Pulse Width Modulators FEATURES DESCRIPTION 8 to 35V Operation The UC1525B/1527B series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when 5.1V Buried Zener Reference used in designing all types of switching power supplies. The on-chip +5.1V Trimmed to +0.75% buried zener reference is trimmed to ±0.75% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resis100Hz to 500kHz Oscillator Range tors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between Separate Oscillator Sync the CT and the discharge terminals provide a wide range of dead time adjustTerminal ment. These devices also feature built-in soft-start circuitry with only an external Adjustable Deadtime Control timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the P W M Internal Soft-Start latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout Pulse-by-Pulse Shutdown which keeps the outputs off and the soft-start capacitor discharged for sub-norInput Undervoltage Lockout with mal input voltages. This lockout circuitry includes approximately 500mV of hysHysteresis teresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a P W M pulse has been terminated for any reaLatching P W M to Prevent Multiple Pulses son, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of Dual Source/Sink Output Drivers sourcing or sinking in excess of 200mA. The UC1525B output stage features NOR logic, giving a LOW output for an O F F state. The UC1527B utilizes O R Low Cross Conduction Output Stage logic which results in a HIGH output level when OFF. Tighter Reference Specifications B L O C K DIAGRAM VREF OSC OUT 0 +VIN GNO [JU- QfJ- RT [T|- CT U]- DISCH [7]- COMP UV LOCKOUT T |~i~|— Nl fj]- SOFT-START [J]- [10| -OH V C -Tjl] TO OUTPUT A JL INTERNAL CIRCUITRY -THI OUTPUT B FLIP _fl FLOP 7 UC1525B f i ] - INV SHUTDOWN REFERENCE REGULATOR \l2\- SYNC m ERROR AMP OUTPUT STAGE -{ii] VC -Q7J OUTPUT A IT -[14] OUTPUT B "IT PWM LATCH WV- UC1527B OUTPUT STAGE I UDG-95055 7/95 A B S O L U T E MAXIMUM RATINGS UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B R E C O M M E N D E D OPERATING CONDITIONS Supply Voltage, (+VIN) 440V (Note 1) Collector Supply Voltage (VC) 440V Input Voltage (4-VIN) +8V to 435V Logic Inputs -0.3V to +5.5V Collector Supply Voltage (VC) 44.5V to +35V Analog Inputs -0.3VtoVIN Sink/Source Load Current (steady state) 0 to 100mA Output Current, Source or Sink 500mA Sink/Source Load Current (peak) 0 to 400mA Reference Output Current 50mA Reference Load Current 0 to 20mA Oscillator Charging Current 5mA Oscillator Frequency Range 100Hz to 400kHz Power Dissipation at T A = +25°C 1000mW Oscillator Timing Resistor 2k£2 to 150kO Power Dissipation at Te = +25°C 2000mW Oscillator Timing Capacitor 0.001uF to 0.1uF Operating Junction Temperature -55°C to +150°C Dead Time Resistor Range 0ft to 500Q Storage Temperature Range -65°C to +150°C Note 1: Range over which the device is functional and parameLead Temperature (Soldering, 10 sec.) +300°C ter limits are guaranteed. All currents are positive into, negative out of the specified terminal. Consult Packaging Section ofDatabook for thermal limitations and considerations of packages. CONNECTION DIAGRAMS DIL-16, SOIC-16 (Top View) J or N Package, DW Package INV [Tj NI PLCC-20, LCC-20 (Top View) Q or L Package ii] 15] VREF +VIN SYNC rjr 14] OUTPUT OUT (T 13] VC CT (T ii] GND RT [IT ~n] OUTPUT OSC N/CINVNl- -VREF -+VIN Zl_ 3 B SYNCH OSC OUTH N/C-i CTH RTH 4 5 6 7 8 9 A DISCH- 2 1 20 w 19 181-OUTPUT B 17 h-VC 16HN/C 151-GND 14 1-OUTPUT A 10 11 12 13 ZT~ -SHUTDOWN -COMP -N/C SOFT-STARTDISCH [T 10] SHUTDOWN SOFT-START (T T| COMP ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for T A = -55°C to +125°C for the UC1525B and UC1527B; -40°C to 485°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; 4-VIN = 20V, T A = T J . UC1525B/UC2525B UC3525B UC1527B/UC2527B PARAMETER TEST CONDITIONS UC3527B MIN TYP MAX MIN TYP MAX UNIT 5.062 5.10 5.138 5.036 5.10 5.164 V 5 10 5 10 mV Reference Section Output Voltage T J = 25°C Line Regulation VIN = 8 V t o 3 5 V Load Regulation IL = 0mA to 20mA 7 15 7 15 mV Temperature Stability (Note 2) Over Operating Range 10 50 10 50 mV Total Output Variation Line, Load, and Temperature 5.176 V Short Circuit Current V R E F = 0, T J =25°C 80 100 80 100 mA Output Noise Voltage (Note 2) 1 0 H z < f < 1 0 k H z , T j = 25°C 40 200 40 200 |j.Vrms Long Term Stability (Note 2) T J = 125°C, 1000 Hrs. 3 10 3 10 mV 2 5.036 5.164 5.024 UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply forTA - -55°C to +125°C for the UC1525B and UC1527B; -40°C to +85°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; + V I N = 20V,TA = TJ. UC1525B/UC2525B UC3525B UC1527B/UC2527B PARAMETER TEST CONDITIONS MIN | TYP I MAX UC2527B MIN I TYP I MAX UNIT Oscillator Section (Note 3) Initial Accuracy (Notes 2 & 3) T J = 25°C Voltage Stability (Notes 2 & 3) VIN = 8V to 35V Temperature Stability (Note 2) Over Operating Range Minimum Frequency RT = 200kii, C T = 0.1uF Maximum Frequency RT = 2k£2, C T = 470pF Current Mirror IRT T J = 25°C Sync Threshold Sync Input Current ±6 ±2 ±6 % ±0.3 ±1 ±1 ±2 % ±3 ±6 ±3 ±6 % 120 Hz 120 400 = 2mA Clock Amplitude (Notes 2 & 3) Clock Width (Notes 2 & 3) ±2 400 1.7 2.0 3.0 3.5 0.3 0.5 1.2 Sync Voltage = 3.5V 2.2 kHz 1.7 2.0 2.2 3.0 3.5 mA 1.0 0.3 0.5 1.0 us 2.0 2.8 1.2 2.0 2.8 V 1.0 2.5 1.0 2.5 mA 0.5 5 2 10 mV 1 10 1 10 uA V Error Amplifier Section (VCM = 5.1V) Input Offset Voltage Input Bias Current Input Offset Current 1 D C Open Loop Gain RL>10Meg£2 Gain-Bandwidth Product (Note 2) Av = OdB, T J = 25°C 60 1 Output Low Level 75 Output High Level Common Mode Rejection VCM = 1.5V to 5.2V Supply Voltage Rejection VIN = 8V to 35V 60 2 0.2 1 1 0.5 75 2 0.2 uA dB MHz 0.5 V 3.8 5.6 3.8 5.6 V 60 75 60 75 dB 50 60 50 60 dB 45 49 45 49 0.7 0.9 0.7 0.9 PWM Comparator Minimum Duty Cycle 0 Maximum Duty Cycle Input Threshold (Note 3) Zero Duty Cycle Input Threshold (Note3) Maximum Duty Cycle Input Bias Current (Note 2) 0 % % V 3.3 3.6 3.3 3.6 V 0.05 1.0 0.05 1.0 uA 50 80 50 80 uA 0.4 Shutdown Section Soft Start Current 25 V S H U T D O W N = OV, 25 V S O F T S T A R T = OV Soft Start Low Level V S H U T D O W N = 2.5V Shutdown Threshold TO OUtputS, V S O F T S T A R T = 5.1V, 0.6 0.7 0.4 0.7 V 0.8 1.0 0.8 1.0 V 0.6 T J =25°C Shutdown Input Current V S H U T D O W N = 2.5 V 0.4 1.0 0.4 1.0 mA Shutdown Delay (Note 2) V S H U T D O W N = 2.5V, T J = 25°C 0.2 0.5 0.2 0.5 us ISINK = 20mA 0.2 0.4 0.2 0.4 V ISINK = 100mA 1.0 2.0 1.0 2.0 V Output Drivers (Each Output) (VC = 20V) Output Low Level Output High Level ISOURCE = 20mA 18 19 18 19 ISOURCE = 100mA 17 18 17 18 6 7 6 7 Undervoltage Lockout V C O M P and V S O F T S T A R T = High Collector Leakage V C = 35V 8 200 3 V V 8 V 200 uA UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B E L E C T R I C A L C H A R A C T E R I S T I C S (cont.) Unless otherwise stated, these specifications apply forTA = -55°C to +125°C for the UC1525B and UC1527B; -40°C to +85°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; + V I N =2 0 Y T A = TJ. UC1525B/UC2525B UC3525B UC1527B/UC2527B PARAMETER TEST CONDITIONS MIN UC2527B TYP MAX MIN TYP MAX UNIT Output Drivers (Each Output) (VC = 20V) (cont.) Rise Time (Note 2) C L = 1nF,Tj = 25°C 100 600 100 600 Fall Time (Note 2) C L = 1nF,Tj = 25°C 50 300 50 300 Cross conduction charge Per cycle, T J = 25°C 30 VIN = 35V 14 ns ns 30 nc Total Standby Current Supply Current 20 14 mA 20 Note 2: Guaranteed by design. Not 100% tested in production. Note 3. Tested at fosc= 40kHz (Rr = 3.GQ, CT = 0.01\iF, RD = 0Q). Approximate oscillator frequency is defined by: 1 f= C T • (0.7 • R T + 3RD) PRINCIPLES O F OPERATION A N D T Y P I C A L C H A R A C T E R I S T I C S UC1525B Output Circuit (1/2 Circuit Shown) +VIN UC1525B Output Saturation Characteristics 13 +VC VIN=20V TA=25°C < I- Vi _1 (ynj o > z g < fll/lTI O U T P U T SOURCE SINK 15k CLOCK I F/F .01 10k |10k TO O- VOL .2 CURRENT, S O U R C E .3.4.5 OR .7 1A SINK ( A ) UDG-95057 UDG-95056 PWM + VSUPPLY SAT, .02.03.04.05.07.10 OUTPUT S A T , VC-VOH OUTPUT FILTER VSUPPLY OR1 vc O U T P U T A|11 UC1525B O U T P U T B|14 OUTPUT B[l4} GND [l2l GND -JiilRETURN RETURN O- O- ln conventional push-pull bipolar designs, forward base drive is controlled by R1-R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C, and C2. For single-ended supplies, the driver outputs are grounded. The V C terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. 4 UC1525B tVSUPPLYO- + VSUPPLY UC1527B UC2525B UC2527B UC3525B UC3527B O : RI VC OUTPUT A [ l l } UC1525B OUTPUT B 14 RETURN O RETURN O- UDG-95061 The low source impedance of the output drivers provides rapid charging of power F E T input capacitance while minimizing external components. Low power transformers can be driven directly by the UC1525B. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. applying a positive signal on Pin 10 performs two functions: the P W M latch is immediately set providing the fastest turn-off signal to the external soft-start capacitor. If the shutdown command is short, the P W M signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS Shutdown Options (See Block Diagram) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100uA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. UC1525B Oscillator Schematic VREF {Te}- ; 7.4k RT[6j CTITI Q6 Q9 ;2k SYNC rj}- DISCH (TJ- 25k •AWr 400(iA Q14l BLANKING TO OUTPUT 6pF 1k GND RAMP TO PWM <14k Q12 Q13 <3k <250 \^2\OSC 5 OUT UC1525B UC2525B UC3525B Oscillator Charge Time vs. RT and C T Oscillator Discharge Time vs. RD and C T 200 500 100 £ 50 oc O w 20 CD a 400 a CE RT=0 CC o 300 I- CO UJ cc LU <E O 10 LU < _l m CM I o o o o o oto w ' - c v i m oOJ o in o E E T - ej 200 100 L coco E m E o DISCHARGE TIME (us) CHARGE TIME (|is) UC1525B Error Amplifier Error Amplifier Open-Loop Frequency Response 80 60 < C5 40 < INV [Tr-J° • 5|-| 1 Q (V)200uA ( p i o o u A ^ TO PWM "COMPARATOR 5 8 V UC1527B UC2527B UC3527B o > 20 | 100 o o FREQUENCY 6 (Hz) UC1525B UC2525B UC3525B UC1527B UC2527B UC3527B L A B T E S T FIXTURE VREF i 1 J REFERENCE REGULATOR r -U L s}- -@ +VIN PWM ADJ. V/l METER f y VREF UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 7 -°|8- IMPORTANT NOTICE Texas Instruments and its subsidiaries (Tl) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality control techniques are utilized to the extent Tl deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING S E M I C O N D U C T O R P R O D U C T S MAY INVOLVE POTENTIAL RISKS O F DEATH, P E R S O N A L INJURY, O R S E V E R E P R O P E R T Y O R E N V I R O N M E N T A L D A M A G E ("CRITICAL APPLICATIONS"). Tl S E M I C O N D U C T O R P R O D U C T S A R E N O T DESIGNED, A U T H O R I Z E D , O R W A R R A N T E D T O B E SUITABLE F O R U S E IN LIFE-SUPPORT D E V I C E S O R S Y S T E M S O R O T H E R CRITICAL APPLICATIONS. INCLUSION O F Tl P R O D U C T S IN S U C H APPLICATIONS IS U N D E R S T O O D T O B E FULLY A T T H E C U S T O M E R ' S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Tl assumes no liability for applications assistance or customer product design. Tl does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of Tl covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Tl's publication of information regarding any third party's products or services does not constitute Tl's approval, warranty or endorsement thereof. Copyright © 1999, Texas Instruments Incorporated APPENDIX D: Typical Safe Operating Area plot for a 200Volt, 9Amp power F E T , showing maximum safe peak pulse currents at various pulse lengths and drain to source voltages. 100 c o 10 c *3 i_ Q •o (A 3 E5£lQ0mS Q_ a <i> Q. 0.1 1 100 10 1000 Drain to Source Voltage (V) Masc Thesis for Electrical Engineering Jarmo Venalainen -101- REFERENCES: [1] David E. Johnson, Johnny R. Johnson, and John L. Hilburn. Electric Circuit Analysis 2 Ed. Prentice Hall, New Jersey, 1992. nd [2] Kjeld Thorborg, Power Electronics, Prentice-Hall, New York, 1988. [3] Edwin C. Craig, Electronics via Waveform Analysis, Springer-Verlag, New York, 1993. [4] Cyril W. Lander, Power Electronics, 2 Ed. McGraw-Hill, Berkshire, England, 1987. [5] Keith Billings, Switchmode Power Supply Handbook. McGraw-Hill, New York, 1989. [6] John G. Kassakian, Martin F. Schlecht, and George C. Verghese, Principles of Power Electronics. Addison-Wesley, 1991. [7] George C. Chryssis, High Frequency Switching Power Supplies: Theory and Design. McGraw-Hill, New York, 1989. [8] B.M. Bird, K.G. King, D.A.G. Pedder, An Introduction to Power Electronics, 2 Ed. John Wiley and Sons, Chichester, England, 1993. nd nd [9] Paul Horowitz, and Winfield Hill, The Art of Electronics. Cambridge University Press, Cambridge, England, 1984. Masc Thesis for Electrical Engineering Jarmo Venalainen -102-
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Control of surge currents in inverter fed loads Venalainen, Jarmo 2000
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Title | Control of surge currents in inverter fed loads |
Creator |
Venalainen, Jarmo |
Date Issued | 2000 |
Description | Switch mode power converters have been used in high power applications such as DC links and variable frequency motor drives for a number of decades. In these applications the load is fixed and well known, and therefore the nature of the power demand placed on the inverter is also well known. In more recent years, high frequency switch mode inverters have become available at smaller power levels as consumer products. These inverters are marketed as capable of providing AC power to ANY AC load which the customer may have. In this case the inverter is called upon to supply power to a diverse variety of loads, presenting it with very challenging operational issues, especially with regards start up surge currents. This thesis investigates the characteristics of the input current drawn by consumer type AC loads, when driven by a standard sinusoidal 60 Hz 110VAC source, with particular emphasis on the inrush current transients found during start up. It then goes on to look at how the surge currents differ when the driving voltage is a non-sinusoidal single step waveform as produced by the vast majority of small inverters. This is followed by a discussion on the benefit of having multiple step waveforms and trapezoidal waveforms, in terms of their effect on the surge current transients. From the discussion on multi step and trapezoidal waveforms, it is shown that a current regulated output is the optimum solution for small modified sinewave inverters when they are used to drive typical consumer type loads. This approach is demonstrated in a 300W inverter through the implementation of hysteretic output current control. Finally, AC output bridge switching losses are investigated, and the benefit of a small amount of series output inductance is demonstrated through simulations and circuit trials. |
Extent | 10304125 bytes |
Genre |
Thesis/Dissertation |
Type |
Text |
File Format | application/pdf |
Language | eng |
Date Available | 2009-07-20 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0065180 |
URI | http://hdl.handle.net/2429/10994 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Graduation Date | 2000-11 |
Campus |
UBCV |
Scholarly Level | Graduate |
Aggregated Source Repository | DSpace |
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