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Fault characterization and testing of digital current mode logic circuits Devdas, Vikram 1999

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FAULT CHARACTERIZATION AND TESTING OF DIGITAL C U R R E N T M O D E LOGIC CIRCUITS By Vikram Devdas B . A . Sc. (Electrical Engineering) University of British Columbia, Canada, 1995 A T H E S I S S U B M I T T E D I N P A R T I A L F U L F I L L M E N T O F T H E R E Q U I R E M E N T S F O R T H E D E G R E E O F M A S T E R O F A P P L I E D S C I E N C E in T H E F A C U L T Y O F G R A D U A T E S T U D I E S E L E C T R I C A L A N D C O M P U T E R E N G I N E E R I N G We accept this thesis as conforming to the required standard T H E U N I V E R S I T Y O F B R I T I S H C O L U M B I A Apr i l 1999 © Vikram Devdas, 1999 In presenting this thesis in partial fulfillment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Electrical And Computer Engineering The University of British Columbia 2356 Main Mal l Vancouver, Canada V 6 T 1Z4 Date: Abstract The research reported in this dissertation describes a new approach to test differential cur-rent-mode logic (CML) circuits. The tests described in this thesis have been developed for high-speed digital interface circuits, such as multiplexors and demultiplexers, used in the tele-com/datacom industry. However, these tests are generic, and can be applied to any kind of current-mode logic circuit. To the authors' best knowledge, the test algorithms described in this thesis have not been previously proposed or used in the area of differential CML integrated circuit testing. The fault simulation and fault grading results show that the proposed test methodology is able to achieve a very high fault coverage and thereby exhibits an attractive and cost effective solution for CML testing. i i Contents Abstract ii List of Figures vi Acknowledgments x 1.0 Introduction 1 2.0 Bipolar Logic Circuit Families 4 2.1 Saturated versus Non-Saturated Bipolar Logic 5 2.2 Bipolar Logic versus CMOS Logic 8 2.2.1 Current-mode Logic - A Basic Introduction 9 2.2.2 Advantages and Disadvantages of CML 9 3.0 Fundamentals of Testing 11 3.1 Errors and Faults 12 3.1.1 Design Modeling and Simulation 14 3;1.2 Test Generation and Evaluation 14 3.1.3 Types of Testing 15 3.2 Fault Modeling 16 3.2.1 Fault Modeling Assumptions 16 3.2.2 Fault Model Classes 17 3.2.3 Fault Simulation 18 4.0 CML Test Circuits 23 4.1 Serial In Parallel Out (SIPO) Circuit 24 4.2 Parallel In Serial Out (PISO) Circuit 25 i i i 5.0 Defects In CML Circuits 28 5.1 Catastrophic (Hard) Faults 29 5.2 Soft (Parametric) Faults 30 5.3 Defect Modeling in CML circuits 31 5.3.1 Modeling defects which cause catastrophic failures 31 6.0 Fault Behavior Characterization and Production Testing of CML Circuits . . . 33 6.1 Production Test of CML Circuits 34 6.1.1 ldcj Testing of CML Circuits 34 6.2 Fault Behavior Characterization of CML Circuits 36 6.2.1 Fault Characterization of the 2:1 PISO Circuit 40 6.2.2 Fault Characterization of the 1:2 SIPO Circuit 47 6.2.3 Fault Detection During Production Test 49 7.0 Common Mode Testing of Differential CML Circuits 51 7.1 Common Mode Testing Methodology 51 7.1.1 Common Mode Testing of the PISO/SIPO Circuits 54 j . 8.0 Conclusion 59 Bibliography 61 Appendix A Schematics of SIPO/PISO Circuits 64 A.1 2:1 SIPO Circuit Schematics 64 iv A.2 1:2 PISO Circuit Schematics 76 Appendix B Fault Characterization Results of the PISO/SIPO CUTs 84 Appendix C Fault Insertion Perl Script - fault_sim.pl 89 Appendix D Fault Analyses Program 107 Appendix E HSPICE Device Model Parameters 113 Appendix F HSPICE Netlist of transistor switching from saturation/active to cut-off state 114 List of Figures Figure 2.1.1 A simple setup to illustrate the difference between saturating and non-saturating logic 6 Figure 2.1.2 Computed transient response for switching the transistor of Figure 2.1.1 from saturation to cut-off 7 Figure 2.1.3 Computed transient response for switching the transistor of Figure 2.1.1 from active to cut-off 8 Figure 2.2.4 A Typical CML 2-input OR/NOR Gate [1] 10 Figure 3.1.1 Types of Testing [14] 16 Figure 3.2.2 General use of fault simulation in test generation [14] 20 Figure 3.2.3 Fault simulation used in the selection of target faults for test generation [14] 20 Figure 4.1.1 Block Diagram of differential mode 1:2 SIPO circuit 25 Figure 4.1.2 Voltage levels of the Power, Data and Clock inputs of the 1:2 SIPO circuit (specific to NORTEL'S 3.3V CML Library) 25 Figure 4.2.3 Block level diagram of 2:1 differential mode PISO circuit. . . . 27 Figure 4.2.4 Voltage levels of the data and clock inputs (specific only to NORTEL'S 3.3V CML Library) 27 Figure 5.3.1 Open Circuit Faults are modeled by inserting a 100Kfi resistor between two nodes. Short Circuit Faults are modeled by shorting any two terminals with a 10 resistor 32 Figure 6.1.1 The emitter-coupled pair is the basic building block in CML circuits 35 Figure 6.1.2 l d d test circuit for CML circuit testing 36 Figure 6.2.3 Algorithm for fault characterization of the CML circuits 39 vi Figure 6.2.4 Voltage and current characteristics of the fault-free 2:1 PISO circuit 40 Figure 6.2.5 "Golden" test vectors for the 2:1 PISO circuit 41 Figure 6.2.6 Voltage characteristics of a parametric fault caused by defect SR28RaPib 41 Figure 6.2.7 Current characteristics of open-circuit fault OQ69E indicates an l d d failure 42 Figure 6.2.8 The voltage characteristics of open circuit fault OQ76B indicates a functional/logical fault 43 Figure 6.2.9 A "Like" fault caused by insertion of open circuit fault OR29C. 44 Figure 6.2.10 A "Hidden" fault as a result of inserting short circuit fault SQ109CB 45 Figure 6.2.11 Percentage of total faults in each fault class 46 Figure 6.2.12 The relationship between the various fault classes 47 Figure 6.2.13 Bar Graph to illustrate the number of faults in each fault category for the 1:2 SIPO circuit 48 Figure 6.2.14 Venn diagram to illustrate the intersection between the various fault classes 48 Figure 7.1.1 The Emitter Coupled Pair is the most basic element of any differential mode CML circuit 52 Figure 7.1.2 Common Mode Fault Simulation of 2:1 PISO Circuit 55 Figure 7.1.3 Common mode testing of a faulty 2:1 PISO circuit, with open circuit fault OQ92E 56 vii Figure 7.1.4 Venn Diagram to show the intersection between CMT, functional test and ldd test and the coverage of various fault classes within each test methodology 56 Figure 7.1.5 Simulated test results for the 2:1 PISO circuit, including Common Mode Test, Functional Test and ldd Test 57 Figure 7.1.6 Venn diagram to illustrate the faults detected for the 1:2 SIPO circuit 57 Figure 7.1.7 Simulated test results for the 1:2 SIPO circuit, including common mode test, functional test and l d d test 58 Figure A.1.1 2:1 SIPO circuit 64 Figure A.1.3 Master-Slave-Slave circuit (mss_3) 65 Figure A.1.2 Master-Slave-Slave circuit (mss_4p) 65 Figure A.1.4 Master-Slave circuit (ms_3) 66 Figure A.1.5 dlatch_5_1 67 Figure A. 1.6 dlatch_5_2 68 Figure A.1.7 dlatch_5_3 69 Figure A.1.8 mss_3_dlatch_3_1 70 Figure A.1.9 mss_3_dlatch_3_2 71 Figure A. 1.10 mss_3_dlatch_3_3 72 Figure A.1.11 ms_3_dlatch_3_1 73 Figure A. 1.12 ms_3_dlatch_3_2 74 Figure A.1.13 Bias Circuit for the SIPO circuit 75 Figure A.2.14 Top level block diagram of the 1:2 PISO circuit 76 Figure A.2.15 DFF_1 77 Figure A.2.16 DFF_2 78 viii Figure A.2.17 D-LATCH 79 Figure A.2.18 Clock Buffer Circuit 80 Figure A.2.19 Data Buffer Circuit. 81 Figure A.2.20 Output data selector 82 Figure A.2.21 Bias circuit for the PISO circuit 83 Figure B.1 Fault Characterization of the 2:1 PISO Circuit 86 Figure B.2 Fault Characterization of the 1:2 SIPO Circuit 88 ix Acknowledgments I would like to take this opportunity to thank my supervisor, Dr. Andre' Ivanov, without whose support, encouragement, patience, and guidance the completion of this thesis would not have been possible. I would like to thank Mrs. Katherine Beaumont, for her ever encouraging words of wisdom. I am greatly indebted to my friends Dave Gagne, Andrew Bishop, Herve Le Pocher, Barry Tsuji, Donald Gillies and Anders Svensson for the spirited discussions over lunch, coffee and fine wine, and for making UBC such a fun place to work and play. I would like to thank Mr. Roozbeh Mehrabadi, our VLSI lab manager, for ensuring the smooth operation of the VLSI lab. The work reported here would not have been possible without the support of NSERC, CMC, Micronet, and NORTEL. Finally, I would like to express my sincerest thanks to my parents for their support, encouragement and patience during this time. Fault Characterization and Testing of Differential Current-mode Logic Circuits Chapter 1 Introduction Testing of Very Large Scale Integrated (VLSI) circuits is an important part of their design and manufacture, and an exponential amount of effort is being expended on test development [17]. In the past, testing of integrated circuits (ICs) was considered a completely separate task from their design. It has become clear, in face of increasing circuit speed and complexity, that effective and high quality testing of present day ICs can only be achieved by designing some or all of the ability to test a circuit into the circuit itself. It is not sufficient to test the function of the circuit itself. Circuits must also be designed so that they can be efficiently tested to ensure that they have been properly fabricated. In the last decade, a considerable amount of research has been done in developing test algorithms for CMOS-based ICs. SCAN tools and automatic test pattern generation (ATPG) tools have been developed commercially for testing CMOS ICs. In comparison, very little research has been done in the area of testing high-speed bipolar circuits. This is primarily due to the emergence and dominance of CMOS technologies. CMOS circuits have a considerable advantage over bipolar logic families in that they consume lower power. However, in high-speed applications, bipolar circuits have an advantage over CMOS because they are capable of operating at higher speeds and can drive large fan-out loads. One big disadvantage of bipolar circuit families is that they have more complex failure modes than CMOS families and are more 1 Fault Characterization and Testing of Differential Current-mode Logic Circuits difficult to test than CMOS circuits [18]. Testing of certain bipolar circuit families, such as current-mode logic (CML), is an immature and scarcely researched area in the field of VLSI, though bipolar ICs have been tested in production for many years. Current-mode logic circuits have been, and still are, typically used in very niche areas of VLSI. CML circuits are usually implemented in high-speed communication applications such as ATM/SONET interface circuits. Examples of such high speed interface circuits are multiplexers and demultiplexers, serial to parallel converters and line interface circuits, which can run at line speeds up to 2.48 Gbps. Since CML circuits are used in very particular areas of VLSI, the demand for such ICs is generally very low. Therefore CML circuits tend to be low volume, high cost ICs. In the past, due to low production volume of CML circuits, most research and development resources were typically spent on ensuring that the circuit was designed to meet a certain functional specification. CML circuits were usually developed on a single monolithic IC. Therefore, it was easy to test these circuits during production, because it was easy to probe various nodes of the circuit under test (CUT) via test pins. These days, CML circuits are usually embedded in a mixed signal BiCMOS IC, along with other CMOS digital circuitry. It is usually not possible to have test pins to probe various nodes in current ICs due to the limited number of pins available for test purposes alone. Thus, testing the CML circuit along with the other digital parts of the circuit, in limited test time, has become a major challenge for the test engineer. CML circuits have traditionally been tested using at-speed functional vectors1. There are several problems associated with production test of a CUT using at-speed functional vectors. 1. Certain nodes of the CML circuit are extremely sensitive to loading. Therefore, these points cannot be brought off chip via a pad. because the pad and the oscilloscope probe will load 1 At-speed functional vectors are generated during functional simulation of the CUT. These vectors are run through the CUT during production test to verify that the CUT functions correctly at its rated operating frequency. These tests are non exhaustive in nature. 2 Fault Characterization and Testing of Differential Current-mode Logic Circuits down the node and cause the circuit to malfunction. The at-speed functional test may or may not test these sensitive nodes. 2. At-speed functional vectors are usually developed to test the most crucial features of the IC and are non-exhaustive in nature. To test the full functionality of the chip would require significant tester time, which would make the production slow and inefficient. 3. There are many defects which may not be detected by at-speed functional tests, because a particular part of the chip, which may contain a defect, may not be exercised during the test. Therefore, testing CUTS with at-speed functional vectors alone can prove to be very expensive due to inadequate test coverage and expensive field returns. The topic of fault characterization of CML circuits too remains vastly unattended in the literature. The research reported in this dissertation is a comprehensive study of fault modeling and fault characterization of differential mode CML circuits. After careful modeling and analyses of two CML circuits, three tests are proposed for testing CML circuits. These tests are \Y]At-Speed functional test, [2] Ijd test, and [3] Common mode test (CMT). While at-speed tests and supply current tests are quite common in the industry, CMT is a novel method of testing CML circuits. A major focus of this thesis has been in finding a non-intrusive method to test the CML circuit during production testing. The organization of this dissertation is as follows: Chapter 2 consists of a brief review of bipolar logic families. Chapter 3 comprises the basic fundamentals of testing, fault simulation, and fault modeling. In Chapter 4, the reader is introduced to the two CML test circuits used extensively in this thesis. In Chapter 5, the various kinds of physical defects, that may arise in CML circuits during the process of their manufacture are discussed. In Chapter 6, fault characterization of the PlSO/SfPO CML circuits is discussed. In Chapter 7, the circuits described in chapter 4 are subjected to at-speed functional test, CMT and ldd test, and the results of these tests are presented. Chapter 8 is the conclusion to this dissertation. 3 Fault Characterization and Testing of Differential Current-mode Logic Circuits Chapter 2 Bipolar Logic Circuit Families The development of integrated circuits has been strongly motivated by the increasing demand on the performance and economy of digital information-processing machines. A basic feature of the digital information processing system is that complex logic functions can be synthesized by the combination and repetitious use of one or a few elementary logic functions. The elementary logic functions (AND, NAND, Flip-flops, Adders etc.) must perform their basic function and also must be inter-connectable, without obstructing their basic operation. A wide array of bipolar logic families has been developed in the past. This includes logic families such as Resistor-Transistor-Logic (RTL), Diode- Transistor-Logic (DTL), Transistor-Transistor-Logic (TTL) and Schottky Clamped TTL (SCTTL). A detailed description of these families can be found in [1]. Al l the bipolar logic families just mentioned (with the exception of Schottky Clamped TTL) are saturated mode logic. Thus, they are subject to a delay time due to charge storage in the base of the transistor as it is driven into saturation [11]. One type of bipolar logic circuit family called "Current-Mode Logic" (CML), prevents transistor saturation. Al l the transistors in a CML circuit are biased such that the transistors never enter the saturation state. The transistors switch from active to cut-off and vice-versa. This eliminates storage time as a speed-limiting characteristic as the transistors are set at well defined levels other than GND and VCE,.,- In CML circuits, the voltage swing (250 mV for a 4 Fault Characterization and Testing of Differential Current-mode Logic Circuits 3.3V technology) is much smaller than saturated logic families (1-2 V), and the circuit speed is considerably improved. This implies that the intrinsic delay of the transistor is reduced, and therefore the time taken for a signal to propagate through the transistor is reduced. Conventional bipolar CML technology represents the state of the art in silicon speed, providing system propagation2 delay times of 300 to 500ps. The price paid for such high speeds is high power dissipation (1.5 mW or more per gate) [1,2] and reduced noise margins due to small signal swings. Recent advances in VLSI such as BIT1 [2] developed by Bipolar Integrated Technology have facilitated the production of bipolar CML circuits that take about l/20th the area of conventional CML devices with speeds comparable to the fastest CML in the market and consuming only l/10th the power [1]. The problem of reduced noise margins has been overcome by using fully differential CML circuits. The advantage of fully differential inputs is that they cancel the effects of noise common to both differential inputs and thereby increase noise immunity. 2.1 Saturated versus Non-Saturated Bipolar Logic The key to improved speed in current-mode logic is the fact that the input voltage swings are very small (typically 250-400mV) such that the transistors in the circuit are never driven into saturation. In this section, we illustrate the key difference between saturating (e.g. TTL) and non-saturating logic (e.g. CML). The simple circuit in Figure 2.1.1. is used to illustrate the difference between non-saturating and saturating bipolar logic families. The NPN bipolar transistor in Figure 2.1.1 is first setup such that when the transistor is on it is in the saturation mode (i.e. Vcoiiector < Vbase)- To turn off the transistor it is necessary to change the operating point from the saturation state to the cut-off state. Using HSPICE [24], transient analyses of the circuit in Figure 2.1.1 were performed. The HSPICE netlist of the circuit and the transient analyses are presented in Appendix F. The current 2 Propagation delay is the amount of time in which the signal passes through the data path of the system. Delays in the data-path are caused by R-C delays in the net and the intrinsic delays of transistors. 5 Fault Characterization and Testing of Differential Current-mode Logic Circuits Ic RL ovout Rb + Vino Vce lb Figure 2.1.1 A simple setup to illustrate the difference between saturating and non-saturating logic. switching characteristic of a transistor from saturation to cut-off is shown in Figure 2.1.2. The results of the transient analyses show the following [11]. 1. After the base current changes, signifying reverse biasing of the emitter-base junction, there is a discernible delay before the collector current begins to fall. 2. The base current switches to a negative value before attaining the near zero value expected for reverse-bias operation. "The delays in switching from saturation to cut-off can be explained if we look at the physics of the transistor. The large negative base current swing is due to the minority carriers which were injected into the base due to the prior forward bias condition, both at the emitter-base and base-collector junctions. The stored minority carrier charge is removed either by diffusion to the depletion regions or by recombination in the base with the majority carrier holes. V b e depends logarithmically on the excess electron concentration at the depletion region boundary with the base. Therefore, V b e changes very slowly as the excess electron concentration diminishes. Consequently the current driven by V b e through Rb (and hence recorded as a negative current) remains essentially constant. The base current inclines towards the very small value expected Fault Characterization and Testing of Differential Current-mode Logic Circuits • Q O O . O U : ON 6TIN B .ON 10. Ic falls to •^T" 0 Amps after a considerable delay due to charge accumulation in the base of transistor in saturation ON 1 Z . . N „ . O N O N S T A T E _ T I N E ( L I N ) Figure 2 .1 .2 Computed transient response for switching the transistor of Figure 2 .1 .1 from saturation to cut-off. for a reverse-biased junction only when the excess carrier concentration has been reduced to zero." [10] Figure 2.1.2 shows how much charge must be nullified before the device leaves the saturation mode. While in the saturation mode V c e is small and therefore I c stays constant at a value close to VCC/RL. Only when the saturation overcharge has been removed can V c e rise and the collector current starts to fall. In comparison to the transient switching characteristics of saturating bipolar logic shown in Figure 2.1.2, the characteristics of non-saturating bipolar logic is shown in Figure 2.1.3. The transistors in non-saturating mode logic switch between active and cut-off state. Thus they never enter the saturation mode. This implies that a very negligible amount of charge is stored in the base. Therefore, when the transistor switches from active to cut-off the collector current starts to fall as soon as the base current changes, with virtually no delay. The comparison of saturating versus non-saturating bipolar logic shows that non-saturating bipolar logic is the fastest bipolar logic available in bipolar technology[ll, 25]. Current-mode logic or emitter-coupled logic is an example of non-saturating bipolar logic. TTL is an example Fault Characterization and Testing of Differential Current-mode Logic Circuits BOO.OU — 2 0 0 . o u : 100.ou : o. -1 oo.ou : -200.ou : -300 .ou : - l o o . o u : -500.ou i - soo .ou : -700.ou : E : E E E E E \ E : I* : : : E l l E E : E » • : I 1 1 E \ m E E E E * | E E • • E Z i i i i i • 1 * 1 • < • i i • i i • i i • 5 .Ic lb 0 A m p s v e r y s h o r t l y : a f t e r l b is s w i t c h e d f r o m a c t i v e t o c u t - o f f m o d e . TIME CLIN) Figure 2.1.3 Computed transient response for switching the transistor of Figure 2.1.1 from active to cut-off. of saturating bipolar logic. 2.2 B i p o l a r L o g i c v e r s u s C M O S L o g i c In general, BJTs are preferable over CMOS in applications involving high speed [11]. To compare transistor operating speeds, consider the electrons moving from source to drain in an n-channel MOSFET, and electrons traversing the base in an npn BJT. In the former case, the limiting value of transit time is L rt(FET) vsat (1) where L is the channel length and vsat is the scatter-limited velocity [11]. For a 0.5 //m CMOS technology, this gives a transit time of 2ps. The corresponding cutoff frequency of the MOSFET is 1 1 h = = 32GHz 27TTJ 2n(5ps) For a BJT the base transit time can be approximated as (2) n(BJT) = i i 2D, (3) 8 Fault Characterization and Testing of Differential Current-mode Logic Circuits where LB is the neutral base width and DE is the electron diffusivity in the base [11]. For a modern BJT process the value of DE is 30 cm2/s and the value of L B is 0.07 /im. From these values and equation (3) the cutoff frequency of the BJT is about 60 GHz. Although these calculations are admittedly rough, they do indicate why the fastest silicon today is a bipolar technology (current-mode logic or emitter-coupled logic) [11]. 2.2.1 Current-mode Logic - A Basic Introduction High-speed logic is used whenever improved system performance would increase a product's market value [25]. For a given system design, high-speed logic is the most direct way to improve system performance and current-mode logic (CML) is today's fastest form of digital logic. Current-mode logic offers both logic speed and logic features to meet the market's demands for higher performance systems [25]. A schematic of a simple OR/NOR CML gate is shown in Figure 2.2.4. In Figure 2.2.4, A and B are the two inputs of the CML OR/NOR gate. AB and BB are the complements of A and B respectively. Transistors q7, q8, and q9 and resistors R l , R2, R4, R5 and R6 are used for biasing the OR/NOR gate. The inputs A and B are ORed using the transistors q3, q4, q5 and q6. Output q is the OR function of inputs A and B. qb is the complement of q and thereby represents the NOR of A and B. 2.2.2 Advantages and Disadvantages of CML The main reason for using CML is the enhancement of speed compared to other bipolar and CMOS logic families. Although CML consumes a large amount of power, relative to CMOS technology, it is the fastest logic yet available [25]. CML also has other advantages other than speed. CML is a current sterring logic and thus is almost a constant-current form of logic, since it shifts current from one transistor to another, whereas in TTL logic gates current is either switched ON or OFF. Thus the current in CML is the same from DC to the maximum operating frequency of the circuit. So once the power supply is designed and the bias established, the system can be 9 Fault Characterization and Testing of Differential Current-mode Logic Circuits Figure 2.2.4 A Typical CML 2-input OR/NOR Gate [1]. run at virtually any speed from DC to the maximum operating frequency, without re-design of the power supply. Also CML circuits have a unique ability to drive large load capacitance. The main disadvantages of CML are : 1. CML circuits consume more static power relative to TTL and CMOS technologies. 2. Single-ended CML circuits are less immune to noise than CMOS or TTL due to their very small voltage swings. The noise margin can be improved by using fully differential CML circuits. 10 Fault Characterization and Testing of Differential Current-mode Logic Circuits Chapter 3 Fundamentals of Testing Testing of a digital integrated circuit (IC) is an experiment in which the system is exercised and its resulting response is analyzed to ascertain whether the IC behaved as intended by the designer or not [14]. The main goal of testing is to differentiate the good parts from the bad parts before the parts are shipped to the customer. Thus, testing ensures that the manufacturer of the IC maintains a certain standard of quality. Testing of a chip can occur at various stages of IC production. at the wafer level. • at the packaged-chip level. • at the board level. • at the system level. • in the field. Semiconductor microprocessor manufacturers like Intel, DEC, SUN, and HP are currently manufacturing ICs with over nine million transistors on chip. To maintain their market share in the business, semiconductor companies must maintain very high standards of quality. A bad part that is shipped out to a customer is very damaging to the reputation of the company and it is also very expensive in an economic sense. By detecting a malfunctioning chip at an earlier 11 Fault Characterization and Testing of Differential Current-mode Logic Circuits level, the manufacturing cost may be kept low. For instance, the approximate cost to a company of detecting a fault at the various levels mentioned earlier are [19] • wafer - $0.01 - $0.10 • packaged chip - 0.10 - $1.00 • board - $1.00 - $10.00 • system level - $10.00 - $100.00 • field - $100.00 - $1000.00 Therefore, if faults in an IC can be detected at the wafer level, the cost of manufacturing is kept lowest. Hence, it makes practical and economic sense for the manufacturer of an IC to test it rigorously, before shipping it to the customer. In this chapter, we introduce the fundamental concepts of testing. The test jargon used in the test community, and various test methodologies currently used in the industry are discussed in this chapter. 3.1 Errors and Faults An instance of an incorrect operation of the circuit being tested (or CUT for circuit under test) is referred to as an (observed) error [14]. The concept of error has a different meaning at different levels. For example, an error observed at the diagnostic program level may appear as an incorrect result of an arithmetic operation, while for ATE ( automatic test equipment) an error usually means an incorrect binary value. The causes of the observed error in ICs may be design errors, fabrication errors, fabrication defects, and/or physical failures. Examples of design errors are [14] incomplete or incorrect design specification; incorrect mapping between different levels of design; violations of design rules. 12 Fault Characterization and Testing of Differential Current-mode Logic Circuits Errors occurring during fabrication are • wrong components; incorrect wiring; shorts caused by improper soldering. Fabrication defects are not directly attributed to human error; rather, they result from an imper-fect manufacturing process. For example, shorts and opens are common defects in manufacturing MOS Large-Scale Integrated (LSI) circuits. Other fabrication defects include improper doping profiles, mask alignment errors, and poor encapsulation. Accurate location of fabrication defects is important in improving the manufacturing yield [14]. Physical failures occur during the lifetime of an IC due to component wear-out and/or environmental factors. For example, the aluminium connectors inside an IC package thin out with time and may break because of metal migration or electromigration or corrosion. Environmental factors, such as temperature, humidity, and vibration, accelerate the aging of components. Cosmic radiation may induce failures in chips containing high-density RAMs [14]. Fabrication errors, fabrication defects, and physical failures are collectively referred to as physical faults [14]. According to their stability in time, physical faults can be classified as 1. permanent, i.e., always being present after their occurrence. 2. intermittent, i.e., existing only during some time intervals. 3. transient, i.e., a one-time occurrence caused by a temporary change in some environmental factor. In general, physical faults do not allow a direct mathematical treatment for testing and diagnosis. The solution is to deal with logical faults, which are a convenient representation of the effect of the physical faults on the operation of the system [14] . A fault is detected by observing an error caused by it. The basic assumptions regarding the nature of the logical 13 Fault Characterization and Testing of Differential Current-mode Logic Circuits faults are referred to as a fault model. The most widely used fault model is that of a single line (wire/node) being permanentiy stuck at a logic value. The subject of fault modeling is further discussed in Section 3.2. 3.1.1 Design Modeling and Simulation Design errors, if they occur, precede the fabrication process and therefore it is possible to eliminate such errors via design verification testing, whereby a model of the designed system can be verified by a testing experiment [14]. The model of the system can be a computer representation of the system in terms of a data structure and/or program such as an HSPICE netlist. The model can be exercised by stimulating it with a representation of the input signals. This process is referred to as logic simulation or design verification simulation [14]. Logic simulation determines the evolution in time of the signals in the model in response to the applied input stimuli. 3.1.2 Test Generation and Evaluation Test generation (TG) is the process of determining the stimuli necessary to test a digital system [14]. Test generation is usually done during the design phase of the IC. The test generation method depends primarily on the testing method employed. On-line testing methods do not require TG [14]. Little TG effort is needed when the input test patterns are provided by a linear feedback shift register working as a pseudo-random sequence generator. For off-line production test of digital ICs, TG has been automated using automatic test pattern generation (ATPG) programs [14]. Using ATPG, test patterns are generated and a model of the IC is simulated with the test patterns. The response of the IC to the test patterns is recorded in a golden database. During production, the test patterns produced by the ATPG are used as stimulus to the physical device. The response of the physical device to the test patterns is compared to the golden data base to ensure that the physical device behaves as expected. An important aspect in testing is test evaluation, which refers to the effectiveness, or quality, 14 Fault Characterization and Testing of Differential Current-mode Logic Circuits of a test. Test evaluation is usually done in the context of a fault model and the quality of test is measured by the ratio of faults it detects and the total number of faults in the assumed fault universe; this ratio is referred to as the fault coverage. Test evaluation ( or test grading j is done via a simulated testing experiment called fault simulation [14]. 3.1.3 Types of Testing Testing methods can be classified according to many criteria. Figure 3.1.1 summarizes the important attributes of testing and the associated terminology. Criterion Attribute of Testing Method Terminology When is testing performed ? 1. Concurrently with normal system operation. 2. As a separate activity. 1. On-line testing / Concurrent testing. 2. Off line Testing. Where is the source of the stimuli ? 1. Within the system itself. 2. Applied by an external deivce (tester). 1. Self Testing. 2. External Testing. What do we test for ? 1. Design errors. 2. Fabrication errors. 3. Fabrication defects. 4. Infancy physical failures. 5. Physical failures. 1. Design Verification Testing. 2. Acceptance testing burn-in. 3. Quality assurance testing. 4. Field testing. 5. Maintenance testing. What is the physical object being tested ? 1. IC 2. BOARD 3. SYSTEM 1. Component Level Testing. 2. Board Level Testing. 3. System-Level Testing. How are the stimuli and / or the expected response produced ? 1. Retrieved from storage. 2. Generated during Testing. 1. Stored pattern testing. 2. Algorithmic testing/ Comparison testing. Figure 3.1.1 Types of Testing [14]. (Continued) . . . 15 Fault Characterization and Testing of Differential Current-mode Logic Circuits Criterion Attribute of Testing Method Terminology How are the stimuli applied ? 1. Depending on the results obtained so far. 2. In a fixed predetermined manner. 1. Adaptive testing. How fast are the stimuli applied ? 1. Much slower than the normal operation speed. 2. At the normal operational speed 1. DC testing. 2. AC testing. / At speed testing. What are the observed results ? 1. The entire output patterns. 2. Some function of the output patterns. 1. Full functional test. 2. Compact Testing. What lines are accessible for testing ? 1. Only the I/O lines. 2. I/O and internal lines. 1. Edge - pin testing. 2. Guide probe testing, Bed of nails testing, E-Beam testing, In-circuit testing, In circuit emulation. Who checks the results ? 1. The system itself. 2. An external device (Tester) 1. Self Testing. 2. External testing. Figure 3.1.1 Types of Testing [14]. A detailed description of these test methodologies and the related jargon may be found in [14]. 3.2 Fault Modeling Fault models are abstractions of the mechanisms which could cause the circuit under test to behave incorrectiy. The quality of a test is strongly dependant on the quality of the fault models used. In this section, the fundamentals of fault modeling for digital circuits are reviewed. 3.2.1 Fault Modeling Assumptions Due to the complex nature of the failure mechanisms in digital circuits there are some assumptions common to most fault models. The most frequent fault model assumptions in the 16 Fault Characterization and Testing of Differential Current-mode Logic Circuits semiconductor industry for digital ICs are discussed below. 1. The Single Fault Assumption: To limit the problem space, it is usually assumed that only a single fault can occur at any time. This is done to avoid the complexity of considering the multiple fault case. For example, a circuit with n nodes can potentially contain 3 n - 2n - 1 distinct3 multiple stuck-at faults. For a circuit with 200 nodes, there are 400 single stuck-at faults and 2.66e+95 multiple faults. It is clear from this example that even a small circuit containing 200 nodes is impossible to test in reasonable time for multiple faults (even though many faults may be equivalent). 2. The Time Invariance Assumption: Fluctuating power supplies and alpha particle bom-bardment can cause a circuit to malfunction. However, failures due to such phenomena are temporary. 3. The Combinational Impact Assumption: One further simplification made in fault model-ing, especially for combinational circuits, is that the faults have a combinational impact on the circuit. Thus, it is assumed that a fault does not cause a memoryless section of the circuit to have the capacity of storing logic values. Stuck open faults and bridging faults both have the potential of inducing memory-like behavior in combinational circuits. 3.2.2 Fault Model Classes A fault model is a representation of the effect of failures that produce changes in the signal values of the logic circuit. Fault models can be classified according to the level of circuit representation to which they are applied. The major classes of fault models are [15] : 1. layout or physical level, 2. device (Circuit) or transistor level, 3. logic gate level, 3 Each node can be either be stuck- at zero, stuck-at one or fault-free. So there are 3" different cases. 2 n of them correspond to single-stuck faults and one of them is fault-free; therefore the remainder is 3" — 2n — 1. 17 Fault Characterization and Testing of Differential Current-mode Logic Circuits 4. and "high level" fault models e.g. RTL or behavioral models. The lower-level abstractions of fault models (such as layout/transistor level ) represent the fault more precisely, because they model the actual physical fault/defect very closely. However, at the low levels, test generation and tractability of the fault becomes more complex and difficult. For example, gate level simulation of an IC using a modern simulator such as CADENCE LEAPFROG is 3 orders of magnitude faster than transistor level simulation of the device using HSPICE. This is because HSPICE evaluates the voltages and currents at every node in the circuit at each new time step. Whereas a gate level simulator like LEAPFROG is an event driven simulator in which only those gates of the circuit are simulated which are effected by the current event and the rest of the gates of the circuit are ignored. Therefore a gate level simulator like LEAPFROG spends less time per fault than a transistor level simulator like HSPICE. However, since a transistor level simulator models all the possible faults that can occur in a device, it is far more accurate than a gate level simulator. Therefore, the choice of the appropriate fault is dependant on the complexity of the circuit as well as the quality of test required. 3.2.3 Fault Simulation Fault simulation involves simulating a circuit in the presence of faults. Comparing the fault simulation results with those of the fault-free simulation of the same circuit simulated with the same applied test T, we can determine the faults detected by T. Hence, one use of fault simulation is to evaluate (grade) a test T. Usually, the grade of T is given by its fault coverage, which is the ratio of the number of faults detected by T to the total number of faults in the test set. This figure is directly relevant only to the faults processed by the simulator, as even a test with 100% fault coverage may still fail to detect faults outside the considered fault model. The quality of the test greatiy influences the quality of the shipped product [14]. Let Y be the manufacturing yield, i.e., the probability that a manufactured circuit is defect-free. Let DL denote the defect level, which is the probability of shipping a defective part, and let d be the 18 Fault Characterization and Testing of Differential Current-mode Logic Circuits defect coverage of the test used to check for manufacturing defects. The relation between these variables is given by [19] DL = 1- (4) Assuming that the fault coverage is close to the defect coverage, we can use Equation (4) to determine the fault coverage required for a given defect level. For example, consider a process with 0.5 yield. Then to achieve a 0.01 defect level - i.e., 1% of the shipped products are likely to be defective, we need 99% fault coverage. A test with only 95% fault coverage will result in a defect level of 0.035. If, however, the yield is 0.8, then 95% fault coverage is sufficient to achieve a defect level of 0.01. Other aspects of the relation between product quality and fault coverage are analyzed in [20], [21], [22], and [23]. Fault simulation plays an important role in test generation. Many test generation systems use a fault simulator to evaluate a proposed test T (Figure 3.2.2) then change T according to the results of the fault simulation until the desired fault coverage is achieved. Another use of fault simulation in test generation is illustrated in Figure 3.2.3 [14]. Many test generation algorithms are fault-oriented. They generate a test for one specified fault, i.e., the target fault. Often, the same test also detects many other faults. Then all the detected faults are discarded from the set of simulated faults and a new target fault is selected from the remaining ones. Other uses of fault simulation include constructing fault dictionaries and performing post test diagnosis. There are various methods of fault simulation. Some techniques are described next [14]. Serial fault simulation Serial fault simulation is the easiest method of simulating faults. It consists of transforming the model of a fault-free circuit N so that it models the circuit Nf created by the fault / . Then Nf 19 Fault Characterization and Testing of Differential Current-mode Logic Circuits Generate Inital T 3 Evaluate T I Suffficient fault coverage DONE > Modify T Figure 3.2.2 General use of fault simulation in test generation [14]. Select Target Fault I Mn m n - f a i i l t c Generate test for target fault I DONE Fault Simulate I Discard detected faults Figure 3.2.3 Fault simulation used in the selection of target faults for test generation [14]. is simulated. The entire process is repeated for each fault of interest. Thus faults are simulated 20 Fault Characterization and Testing of Differential Current-mode Logic Circuits one at a time. The main advantages of the serial method of simulation are: 1. No special fault simulator is required as Nf is simulated by a fault-free simulator. 2. It can handle any type of fault provided that the model of Nf is known. If the number of nodes to be faulted is K, and the average number of test vectors is N, the number of test cycles, Sk is approximately given by Sk = (K + 1)(N) « KN (5) With a small vector set, a simple circuit, or a very fast simulator, the serial fault simulation approach is feasible. However, the serial method is impractical for simulating large circuits (i.e. greater than 100 nodes in a circuit), since it consumes a lot of CPU time. Parallel fault simulation Parallel fault simulation is one method for speeding up simulation of multiple machines. In this method m words in an n-bit computer are used to encode the state of n "machines" for a 2 m state simulator [26]. Two w-bit words may be used to encode n machines for a three state simulator and so on. Now if M circuits can be simulated in parallel, and the number of nodes to be faulted is K, and the average number of test vectors is N, the number of test cycles, Sk is approximately given by [14] KN Thus it is obvious from Equation (6) that parallel simulation of faults can significantly reduce fault simulation time as compared to serial fault simulation. Concurrent fault simulation Concurrent fault simulation uses a fault-free model of the circuit to create a "good" machine model. Each fault creates a new faulty machine that is simulated in parallel with the good 21 Fault Characterization and Testing of Differential Current-mode Logic Circuits machine. Thus N + 1 simulations may have to be completed, where N is the number of faults [14]. Concurrent simulators rely on a number of heuristics to reduce the total amount of simulation time. For instance, when a difference is detected between a faulted and good machine at an externally observable point, the faulty machine is dropped from the queue and the fault is "detected". If the bad machine has an X or Z compared to a 1 or 0 for the good machine, the fault is a "possible detect". Obviously the more externally observable nodes the circuit has, the quicker the bad machines get dropped from the simulation. Normally, only the good machine is stored with each node listing the fault machines that differ with the good machine [14]. The different state is often small, which often implies that there is a small amount of extra simulation required. In other words, most simulation for a faulty machine is exactly the same as the good machine. This is what concurrent simulation exploits best. Fault collapsing occurs when two different faults result in the same faulty machine. This is noted and one of the faulty machines is dropped [14]. The topic of fault simulation is very vast and is beyond the scope of this thesis. A good discussion on different kinds of fault simulation methodologies and their advantages as well as disadvantages can be found in [14]. In this thesis, the principle focus shall be on fault modeling, fault insertion, fault simulation and fault characterization of CML circuits. Fault coverage of various tests during production test is also of fundamental interest. 22 Fault Characterization and Testing of Differential Qirrent-mode Logic Circuits Chapter 4 CML Test Circuits Two basic CML circuits were chosen for fault simulation, fault characterization and for developing new methods of testing CML circuits. The two circuits are 1:2 differential mode Serial In Parallel Out (SIPO) circuit; • 2:1 differential mode Parallel In Serial Out (PISO) circuit. The PISO/SIPO circuits used in this thesis were developed at NORTEL [26] specifically for asynchronous transfer mode (ATM) applications. The PISO/SIPO test circuits fall under the category of sequential current-mode logic. Hessabi et. al. [18] have reported some results on testing current switched logic. However, the focus of their research is on testing combinational circuits such as adders, NAND gates, INVERTERS etc. Moreover, the logic tested by Hessabi et. al. [18] is in BiCMOS technology. No research is known to have been reported in the area of testing sequential bipolar CML circuits. In the telecom industry, the interface circuits (such as multiplexors and demultiplexors) work at very high speeds to take advantage of the massive bandwidth available in optical transmission lines. For example, current ATM circuits work in the 155 Mbps-10 Gbps range. Current-mode logic is the fastest silicon-based technology capable of driving circuits at such high speeds. Also, in most high-speed digital circuits, the longest delay path is usually found in the data path of the circuit. The long delays can be overcome in two ways: 23 Fault Characterization and Testing of Differential Current-mode Logic Circuits 1. Massive pipelining of circuit; 2. Using very high-speed technology (such as CML) with very low propagation delays. Since many real-time communication applications cannot afford the latency of a massively pipelined circuit, the only option for a digital designer is to use a technology which offers very high-speed data propagation. CML is the fastest technology in the industry and therefore many designers opt to use bipolar CML ( also referred to as ECL in the industry) for implementing the data-path of a high-speed circuit. 4.1 Serial In Parallel Out (SIPO) Circuit The block diagram of the 1:2 SIPO circuit is shown in Figure 4.1.1. This circuit is the basic unit of a 1:8 SIPO circuit. The 1:8 SIPO circuit was designed to demultiplex a 311 Mbps serial line into eight 39 Mbps serial lines. The 1:2 SIPO circuit shown here simply demultiplexes a single 311 serial line into two 311 Mbps lines. The SIPO circuit consists of two master-slave-slave (MSS) flip-flops, a master-slave flip-flop (MS), and a bias circuit. The master-slave (ms-3) and master-slave-slave (mss-4p and mss-3) circuits are further divided into several D-flip-flops. The differential input data is sampled by the master-slave-slave block mss-4p. The master-slave and master-slave-slave circuits have a differential data input labeled d and db, and a differential clock input labeled ck and ckb. The data sampled and stored by the master-slave-slave block mss-4p is re-sampled by the two blocks - the mss-3 and ms-3 blocks and the input bit stream is demultiplexed at the outputs datajx and datajb. data_ab and data_bb are the complimentary voltage levels of data_a and datajb respectively. The detailed transistor level schematics of these circuits are shown in Appendix A. In CML, the nomenclature used by the industry for various voltage levels is slightly different than that used for CMOS circuits. The positive potential of the power rail is referred to as V G N D -The negative potential of the power rail is referred to as V E E - V M is the highest potential for an 24 Fault Characterization and Testing of Differential Current-mode Logic Circuits datajn data_in_b ck311 ck311 b mss_4p m s s 3 q qb U db c k ckb ck155 ck155b d q db qb c k c k b ms_3 d q db qb c k c k b , data_a 'data ab , data_b •data bb Figure 4.1.1 Block Diagram of differential mode 1:2 SIPO circuit. V G N D 3.30V V E E o.oov V I H D A T A 3.30V V r L D A T A 3.05V V m _ C L O C K 2.60V( Diode Drop Below VIH DATA). V _ . _ C L O C K 2.35V( Diode Drop Below VIL DATA). Figure 4.1.2 Voltage levels of the Power, Data and Clock inputs of the 1:2 SIPO circuit (specific to NORTEL'S 3.3V CML Library). input differential signal. V I L is the lowest potential for an input differential signal. The value of V G N D , V E E and Vm and V_, for various pins of the SIPO circuit are given in Figure 4.1.2. 4.2 Parallel In Serial Out (PISO) Circuit A block diagram of the 2:1 PISO circuit used for serial fault insertion, fault characterization, serial fault simulation and fault grading is shown in Figure 4.2.3. The 2:1 PISO circuit shown in Figure 4.2.3 is the basic unit of a larger 8:1 PISO circuit. The 8:1 PISO circuit was designed to multiplex eight 77.78 Mbps serial data lines into a single 622 Mbps line. The circuit is a 2:1 differential input mode PISO circuit. The 2:1 PISO circuit shown here simply multiples two 25 Fault Characterization and Testing of Differential Current-mode Logic Circuits 77.78 Mbps lines into a single 155.52 Mbps line. The PISO circuit consists of two D-flip-flops, a D-latch and a 2:1 mux circuit. In the 2:1 PISO of Figure 4.2.3, there are two differential mode data inputs (data_0, data_l), one diffenential clock input. The phases of the clock ck78 define the select inputs (sO, sOb) of the 2:1 mux. A l l inputs and outputs of the 2:1 PISO circuit are differential. On the rising edge of the clock, the input data from datajO and data_l are sampled by the two D flip-flops DFF_1 and DFF_2. On the positive phase of the clock, the data from input datajO becomes transparent to the output data_out. The data from DFF_2 is latched by the d-latch on the positive edge of the clock and is held during the negative phase of the clock. On the negative phase of the clock, data_2 from the latch becomes transparent to the output data_out. The output of the PISO is then sampled by another flip-flop (not show in diagram) at twice the data rate (155.52 Mbps). Figure 4.2.4 lists the voltage levels of the clock and data and inputs. The voltage swing both for clock and data is 250 mV. For the data, one of the differential levels is at V G N D level (i.e., 3.3V), while the other is at V G N D - 250 mV (i.e., 3.05V). The voltage levels for the clock are one diode drop down from the data levels. Emitter follower droppers are used to derive the clock levels. Detailed, transistor level schematics of the 2:1 PISO circuit are presented in Appendix A. The 1:2 SIPO circuit and the 2:1 PISO circuits described in this chapter are the two circuits that are analyzed towards deriving effective test strategies for CML circuits. Although, these circuits are by no means representative of the entire class of CML circuits, the components of these circuits (D-latches, D-flip flops, AndVNand gates, Or/Nor gates, etc.) constitute a majority of circuits found in any CML library. 26 Fault Characterization and Testing of Differential Current-mode Logic Circuits x Z3 CM co T3 CO TJ CT qb o qb CO -O CO CO _Q bb o cn X o .Q X3 TJ .O O O Li. Q cr JH o o CM. T3 T3 JH O O ° i 8 . •_ CO CO -tr -o as CO I CO CO "° -CO TJ lis CO I s -O CO I s -O Figure 4.2.3 Block level diagram of 2:1 differential mode PISO circuit. V G N D 3.30V V E E o.oov Vffl D A T A 3.30V V l L D A T A 3.05V Vm_CL0CK 2.60V( Diode Drop Below VIH DATA). V I L _ C L O C K 2.35V( Diode Drop Below VIL DATA). Figure 4.2.4 Voltage levels of the data and clock inputs (specific only to NORTEL'S 3.3V CML Library). 27 Fault Characterization and Testing of Differential Current-mode Logic Circuits Chapter 5 Defects In CML Circuits Manufacturing or process defects can occur during the fabrication of integrated circuits. The conventional stuck-at fault model [14], used for CMOS technology, is found to be even more inadequate for modelling manufacturing defects in CML circuits [3]. This is because defects in CML circuits do not necessarily exhibit a stuck-at logic 1 or stuck-at logic 0 property at a given node. It has been found that current fault modeling and fault characterization techniques for CML circuits are extremely poor which naturally lends itself to a very poor fault coverage [3]. This leads to poor quality parts and system, and/or board level failures that are very difficult to diagnose. Faults found in VLSI circuits can be classified in two broad fields [14]: • Catastrophic or hard faults : These are permanent structural faults introduced in the circuit during the manufacturing of the IC. Examples of Catastrophic or hard faults are shorts and opens across resistors, capacitors, diodes and transistors. • Soft faults: These are faults introduced in circuit due to variations in the process parameters. These include variation of the beta values of the transistors, and variation of resistor and capacitor values. Faults can also occur due to electrostatic discharge (ESD) and electrical overstress (EOS). The EOS and ESD and certain metallization failures cause a decrease in the base-emitter, 28 Fault Characterization and Testing of Differential Current-mode Logic Circuits collector-emitter, and base-collector resistance value of the transistors, which can be modeled as base-emitter, collector-emitter, and base-collector shorts respectively [3]. Bulk and interface failure mechanisms cause an increase or decrease of the beta value of the transistors as well as base, collector and emitter open circuit faults [3]. In this chapter the sources of catastrophic faults and soft faults in current-mode logic circuits are analyzed. The algorithm and methodology for serial fault insertion, fault simulation, and fault analysis are also described in this chapter. The topic of soft faults is discussed in this chapter solely for the purpose of completeness. We shall only focus on the topic of catastrophic/hard fault characterization and simulation in this thesis. 5.1 Catastrophic (Hard) Faults The most prevalent catastrophic failures in a bipolar technology are [6]: 1. Open connections. 2. Shorts across transistor terminals. 3. "Piped" transistors with excessive emitter to collector leakage current. In [3,8] the authors refine the typical bipolar process defects into two categories: process defects and personalization defects. The process defects listed in [3,8] are : 1. Emitter-Base Shorts and opens: There may be a short or open circuit between the emitter and base of a transistor. 2. Collector-Base Shorts and opens: An open or shoirt circuit may exist between the collector and base of a transistor. 3. Contact Integrity : A contact between two metal lines may not be stable. 4. Resistor Opens: There may be an open circuit in the resistor. 29 Fault Characterization and Testing of Differential Current-mode Logic Circuits 5. Collector-Emitter leakage: There may be a very small short between the collector and ernitter of a BJT. The personalization defects are listed below: 1. Intra-level metal shorts : These are shorts between two same level metal lines e.g., a short between two metal-1 lines or a short between two metal-2 lines etc. 2. Intra-level metal opens: These are opens in a metal line, e.g., an open circuit in a metal-1 line or an open circuit in a metal-2 line etc. 3. Inter-level metal shorts. These are shorts between two different level metal lines, e.g. a short between metal-1 and a metal-2 line. 5.2 Soft (Parametric) Faults A grey area exists between manufacturing defects which cause catastrophic failures in an IC and defects which are redundant and do not effect the functionality of the IC at all. Such faults are termed soft faults. Soft faults usually occur due to variations in the process parameters in the IC foundry. Soft faults may not be immediately detrimental to the functional behavior of the circuit, but may cause the circuit to deteriorate/fail in the field. Whereas hard faults impact the quality of the product, soft faults have an impact on the reliability of the IC in the field. During the manufacture of ICs, general process parameters typically vary up to ±20% (from the nominal value) from one die to another. In order to accommodate the variations in process parameters, a designer must make a circuit robust enough to tolerate such variations. In CML circuits, soft faults due to parametric variations can occur in the following areas: 1. The value of one or more resistors in the circuit may vary from the nominal value causing the voltage/current characteristics of the original circuit to deteriorate. 2. The beta values of the transistor may change significantiy from the nominal value, which may deteriorate the voltage/current characteristics of the circuit. 30 ) Fault Characterization and Testing of Differential Current-mode Logic Circuits 3. The capacitor values may deviate from the nominal value, thereby causing a deterioration in the circuits' current or voltage characteristics. Although soft faults do not necessarily change the functional behaviour of a circuit, they do, however, alter the current/ voltage characteristics of the circuit. Therefore the circuit may become more susceptible to failure in a noisy environment. It is usually very difficult to detect soft failures, which may only have a marginal effect on the circuit behavior. Nevertheless, these faults can cause reliability problems and, if possible, should be detected. The topic of soft or parametric faults with respect to CML circuits is further discussed in Section 6.2 5.3 D e f e c t M o d e l i n g i n C M L c i r c u i t s . From recently published literature [2, 3], simple fault models can be used for modeling the process and personalization defects. 5.3.1 Modeling defects which cause catastrophic failures Using the parametric analyses option in HSPICE, shorts varying from lOfi to 1KH were introduced into the PISO/SIPO circuits. From the HSPICE simulations, it was observed that the voltage and current characteristics of the PISO/SIPO circuits did not vary significantly as the shorts varied from 10ft to lKf2. A similar behavior was noted for open circuits ranging from 100Kf2 to lOMfi. Therefore, we chose 10ft to model all short circuit faults, and lOOKfl to model all open circuit faults in the PISO/SIPO CUTs. 31 Fault Characterization and Testing of Differential Current-mode Logic Circuits 3 Rshort_collector_base = 10Q Ropen-Base =100Ki VVv-rA/VV Rshort_emitter_base = 10O ' Rshort_emitter_collector= 10O. Figure 5.3.1 Open Circuit Faults are modeled by inserting a 100KQ resistor between two nodes. Short Circuit Faults are modeled by shorting any two terminals with a 10 17 resistor. Open circuits are modeled with lOOKfi resistors as shown in Figure 5.3.1. Short circuits between terminals of a transistor are modeled with 10S7 resistors as shown in Figure 5.3.2. Shorts across resistors are modeled similarly with 10f2 resistors. It is assumed that the probability of all the defects occurring follows a uniform distribution. Inter and intra-metal opens are modeled with 100 Kf2 resistors and intra-level shorts are also modeled with 10fi resistors. 32 Fault Characterization and Testing of Differential Current-mode Logic Circuits Chapter 6 Fault Behavior Characterization and Production Testing of CML Circuits In Section 5.1, it was postulated that most defects in ICs which cause catastrophic faults can be modeled as transistor and metal line level shorts and opens. Transistor level fault models provide a higher and more accurate fault coverage than higher levels of fault models. In this chapter, we analyze the behavior of the PISO/SIPO CUTs in the presence of open and short defects. In this thesis, fault characterization of the PISO/SIPO CUTs only covers faults caused by hard defects. The area of fault characterization due to soft faults is not discussed in this thesis. Most of the work reported to date on CML logic families has concentrated on design issues and there is little emphasis on the issue of testability of these circuits. This chapter addresses testing issues by examining the two differential CML circuits discussed in Chapter 4, i.e., the 2:1 PISO and the 1:2 SIPO circuits. The PISO and SIPO circuits are representative of high-speed sequential data path elements, primarily targeted for high-speed interface circuits used in the telecom industry. Current methods used in the industry for the production-stage test of CML circuits are discussed in Section 6.1. Fault characterization of the differential CML PISO/SIPO circuits is studied in Section 6.2. The impact of each possible single defect on the behavior of these circuits is analyzed by simulation. A new class of faults, unique to differential circuits, is identified 33 Fault Characterization and Testing of Differential Current-mode Logic Circuits and its testability analyzed. Testing of the circuits by functional/logical testing and ldd current monitoring is simulated and the results reported. 6.1 P r o d u c t i o n T e s t o f C M L C i r c u i t s According to the literature, there are two tests that are typically performed to test CML circuits during production-stage test [26]. 1. At-speed functional/logical test: In this test the CUT is run at its normal clock frequency. The logical functionality of the CUT is tested using test vectors designed to exercise the CUT such that the major functionality of the CUT is tested. In smaller CUTs (<200 nodes), the vectors may be exhaustive, but in larger sized CUTs this is an impossible task. 2. Ida test: In this test, the supply current of the CUT is monitored. If the supply current exceeds the nominal operational supply current of the CUT by +/- X % , it is failed ( the value of X varies from circuit to circuit and is determined by the design engineer). In CML circuits, the ldd current can be monitored in conjunction with the at-speed functional test because the current consumed by the CUT is frequency independent. A new method to test CML circuits using ldd current measurement was developed and is discussed below: 6.1.1 Testing of C M L Circuits In CML circuits, the basic building block is an emitter- coupled differential amplifier as shown in Figure 6.1.1. The input voltage of the differential pair swings between V + and V - , which causes either of transistors QI or Q2 to cut-off, or operate in the active region. Therefore, the CML circuit works by switching the bias current, Ibias, between the two arms of the differential pair. Thus, unlike CMOS logic circuit elements, the same amount of bias current always flows from V G N D 34 Fault Characterization and Testing of Differential Current-mode Logic Circuits v+ Figure 6.1.1 The emitter-coupled pair is the basic building block in CML circuits. to V E E , regardless of switching the frequency of a circuit. This "constant" current constitutes the basis of Idd testing in CML/ECL circuits. Idd Test Circuit Fault simulation of the PISO/SIPO CML circuits revealed that certain hard faults increase, while others decrease the supply current of the CML circuit. The proposed test circuit used to test CML circuits is shown in Figure 6.1.2. In Figure 6.1.2, Imeas is the average current measured between V G N D and V E E during the normal operation of a particular CML circuit. I m + and I m . are the upper and lower bounds, respectively, of the supply circuit. Im- and I m + can be calculated using Monte Carlo Analyses. The operation of the test circuit is very simple. During the normal operation of the CUT, Idd is measured between V G N D and V E E and is compared to the upper and lower current thresholds Ith+ and Ith- If Was is greater than W or lower than Im-, the output of the comparator is a logic-1, thereby indicating a failure. In the case of the PISO circuit the nominal supply current threshold was -2.49 mA. Ith+ was 30% above and Im . was 30% below the nominal value. In the case of the 35 Fault Characterization and Testing of Differential Current-mode Logic Circuits lth+ > Imeas >• Ith- > ^Vout Figure 6.1.2 Idd test circuit for CML circuit testing. SIPO circuit, the nominal supply current threshold was -2.56 mA and the circuit could function properly at supply currents 30% above or below the nominal supply current value. Ida testing was performed on the PISO/SIPO circuits and the results are discussed later in this chapter. 6.2 Fault Behavior Characterization of CML Circuits Failure mechanisms in CML circuits were discussed in Chapter 5. It was stated that defects could be modeled as shorts and opens in the circuit. In [3] it has been shown that the conventional stack at fault model, used for CMOS technology, is found to be inadequate for modelling manufacturing defects in bipolar logic circuits. In this section, we insert open and short faults in the PISO/SIPO CUTs and the faults are binned into various fault classes depending on the effect of the fault on the current and/or voltage characteristics of the PISO/SIPO CUTs. To make it easier to locate a fault in the PISO/SIPO circuits, the following notation is used: 1. A short circuit between any two nodes of a transistor QI is referred to as SQ1XX, where X X are the two shorted nodes. For example a short between base and collector of a transistor QI is referred to as SQ1BC. 36 Fault Characterization and Testing of Differential Current-mode Logic Circuits 2. A short across a resistor RX, is referred to as SRXRaRb, where Ra and Rb are the two nodes of the resistor. 3. An open in one of the terminals of a transistor QI, is referred to as OQ1X, where X is the terminal with the open circuit. For example, an open circuit in the base of transistor QI is denoted OQ1B. To limit the problem space, it is assumed that no more than one defect can occur at a time. The single-fault assumption is justified by the frequent testing strategy, which states that we should test a system often enough so that the probability of more than one fault developing between two consecutive testing experiments is sufficiently small. But, even when multiple faults are present in a circuit, the tests derived under the single-fault assumption are usually applicable for the detection of multiple faults, because, in most cases, a multiple fault can be detected by the tests designed for the individual single faults that compose the multiple one [14]. For CML circuits, simulations show that process and personalization defects (discussed in Section 5.1 ) may result in any of the following fault classes [10]: 1. Parametric faults: certain hard defects in the circuit may change a continuous parameter of the circuit, like voltage, delay etc. The PISO/SIPO circuits are designed to handle upto +/-20 % change in their voltage transfer characteristics and AC timing. However, a change in the voltage characteristics of the circuit reduces the noise margins of the CUT and makes it more susceptible to noise. In the case of the PISO/SIPO CML circuits, if the voltage levels of the primary outputs vary between 10% and 20% from the nominal value, but do not cause a functional fault in the CUT, a parametric fault is declared. If a certain hard fault changes the AC timing of the output up to +/- 20% of the nominal value, but does not cause a functional fault, the fault is also categorized as a parametric fault. 2. Functional faults: these are a representation of the defects that cause a change in the logical behavior of the circuit. 37 Fault Characterization and Testing of Differential Current-mode Logic Circuits 3. Like faults : certain defects cause the differential circuit to lose its complimentary nature at the two outputs, i.e., both outputs of the differential circuit have the same voltage characteristic and are not opposite to one another. 4. ldd faults: certain defects may vary the supply current of the CUT by more than X % above or below the nominal value thereby making the circuit very susceptible to noise, or failure due to physical breakdown of the device.4 5. Hidden faults: certain defects neither change the circuits' logical behavior nor affect the supply current or voltage characteristics. These faults cannot be detected using the production test methodologies described in Section 6.1 and are called hidden faults. The algorithm used for fault behavior characterization of the 2:1 PISO and the 1:2 SIPO circuit is outiined in Figure 6.2.3. The process of serial fault insertion, fault simulation and fault effect characterization of the PISO and SIPO CUTs was automated using a PERL script. The fault insertion PERL script fault_sim.pl [12] can be found in Appendix C. The fault effect characterization PERL script fault_characterize.pl can be found in Appendix D. The fault characterization process begins with the SPICE netlist N of the CUT. Functional test vectors are hand generated by the designer to test the logical behavior of the PISO/SIPO CUTs. For example, a logical way of testing the SIPO circuit is to generate a serial stream and feed it into the input of the SIPO and to observe the parallel output for the expected data. The fault-free netlist is simulated with the hand generated golden test vectors, and the output voltage characteristics and supply at the CUT are recorded. Open and short faults are injected serially into the SPICE netlist of the fault-free CUT, thereby creating a new netlist N; for each fault/;. Each netlist Ni is simulated and the results are compared against the voltage and current characteristics of the "fault-free" netlist N. Depending on the results, Ni is binned into one of the fault categories. 4 Monte Carlo simulations show that the PISO/SIPO circuits are robust only up to a +/- 30% variation in supply current. The voltage and current characteristics of the PISO/SIPO changed significantly above and below the 30% level, which made the PISO/SIPO circuits extremely susceptible to noise. 38 Fault Characterization and Testing of Differential Current-mode Logic Circuits ( Analyze CUT y netlist. J I Generate a set of "golden" functional test vectors for the fault free CUT. i Create a golden vector file For the exhaustive Test Vectors,, I ^Insert short/open fault. I Simulate faulty netlist with Golden Functional Vectors. I Observe output voltage and current characteristics. Functional, parametric, . , like or ldd fault. J [ hidden fault. Figure 6.2.3 Algorithm for fault characterization of the CML circuits. This process of serial fault insertion, fault simulation and fault characterization is done exhaustively for all shorts (that can possibly occur between adjacent components/nodes) and open circuit faults that could possibly occur in the circuit during fabrication. It is important to note that in the fault effect characterization algorithm described in Figure 6.2.3, functional, parametric, and like faults are classified according to the voltage characteristics at the primary outputs of a CUT. I d d faults are based on the supply current provided to the CUT. Defects in the CUT, which neither change the voltage characteristics at the primary output of the CUT nor affect the supply current of the CUT are binned in the hidden fault category. 39 Fault Characterization and Testing of Differential Current-mode Logic Circuits 6.2.1 Fault Characterization of the 2:1 PISO Circuit Fault characterization of the 2:1 PISO circuit is based on the algorithm shown in Figure 6.2.3. To illustrate the fault characterization methodology, a simple example follows. It is important to refer to the PISO circuit schematics in Appendix A to follow the example. a .ao V L 1 1 ' 0 1 3.20 C L K - 7 8 - A = S 0 C L K - 7 8 - B =s0b • 3.30 V L 0 I 3.30 L N T 3 a L M " p 0 0 0 1 1 1 1 1 1 1 1 i — i — r DATfl.OUT.B • e . n i on 3 i I -S . M50M : • I I I I I I i ^ L i V V S i . •*.™*&^c~-r\—y-r\—yr~i—y.—\—i—\—ri—7-* m 1 1 f 1 I 1 1 1 11 I 1 1 1 f i l l 1 1 'I 1 1 1 1 I 1 1 1 1 I l i • 1 1 * Averaae I O O . O N S O O . O N aoo.oN t o o . O N S O O . O N E O O . O N rtvciaycs „ T I M E C L I N ] 7 0 0 . O N Idd cur rent = -2 .54 m A Figure 6.2.4 Voltage and current characteristics of the fault-free 2:1 PISO circuit. The voltage and current characteristics of the fault-free PISO circuit, simulated exhaustively with the "golden" vectors are shown in Figure 6.2.4. In Figure 6.2.4, sO and sOb are the complimentary select lines in the 2:1 mutiplexor circuit, dataj) and data_0b are comlimentary data lines. Similarly data_l and data_lb are comlimentary data lines. The complimentary output lines are labeled data_out and data_outb. The "golden" vectors in the case of the PISO circuit are shown in Figure 6.2.5. The golden vectors are all the 2 n possible combinations of inputs into the 2:1 PISO circuit. 40 Fault Characterization and Testing of Differential Current-mode Logic Circuits data_0 data_l sO 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Figure 6.2.5 "Golden" test vectors for the 2:1 PISO circuit. Time(lin) ns Figure 6.2.6 Voltage characteristics of a parametric fault caused by defect SR28RaRb. We illustrate the fault behavior characterization process with a few examples. Faults SR28RaRb, OQ69E, SQ109CB, OR29C are inserted in the HSPICE netlist of the PISO cir-cuit. The faulty circuits are simulated serially with the "golden" vectors and the fault simulations are illustrated in Figures 6.2.6 to 6.2.10. The results of fault simulation of the PISO circuit with the fault SR28RaRb inserted into the circuit are shown in Figure 6.2.6. The fault simulation was done using the "golden" vector set 41 Fault Characterization and Testing of Differential Current-mode Logic Circuits Average ldd Current is = -6.65 mA. Figure 6.2.7 Current characteristics of open-circuit fault OQ69E indicates an ldd failure. shown in Figure 6.2.5. A comparison of the output voltage characteristics between the fault-free circuit simulation (Figure 6.2.4) versus the results of the faulty circuit (Figure 6.2.6), shows that the short circuit fault SR28RaRb significantly increases the output voltage swing of the faulty circuit. The output voltage (DATA_OUT_A / DATA_OUT_B) of the fault-free circuit is between 3.3 V and 3.05 V. However, the faulty circuit has an output voltage (DATA_OUT_A / DATA_OUT_B) swing between 2.35 V and 3.3 V. A fault that causes such an effect on the output voltage swing is called a parametric fault. This fault does not constitute a functional fault because the voltage at the primary outputs exhibits the correct logical behavior. A comparison between the current characteristics of the faulty circuit, caused by an open circuit in the emitter of transistor Q69 (Figure 6.2.7) with the simulation results of the fault-free circuit (Figure 6.2.4), reveals that open circuit fault OQ69E causes the PISO supply current to jump from an average value of -2.50 mA to -6.65 mA. Since the simulated supply current is not within +/- 30% of the average current of a fault-free circuit, fault OQ69E constitutes an I d d 42 Fault Characterization and Testing of Differential Current-mode Logic Circuits 007GB.TR 0 C L K - 7 B - A C L K - 7 B . B 3 " "B 007GB .TRO : OATAO.A - A I OATAO-B - ca 007GB.TRO 0ATA1_A - O O T A l . B - Q ~\ " 0076B.TRO .0f lTn-0UT_n r I I i i i i i i i I I I I I 0 0 007EB.TRO 0ATA_0UT_B O.ON 00.ON 4 00 .ON 50 0.ON EOO.ON TIME ( L I N ) 700.ON Figure 6.2.8 The voltage characteristics of open circuit fault OQ76B indicates a functional/logical fault, or supply current fault. Fault OQ76B emulates an open circuit in the base of transistor Q76. The faulty circuit was simulated with the "golden" vectors shown in Figure 6.2.5 and the voltage characteristics at the primary outputs of the PISO are shown in Figure 6.2.8. On comparing the simulation results of the fault-free circuit (Figure 6.2.4) with the simulation of the faulty circuit (containing the fault OQ76B) shows that this fault causes a logical error at the primary output of the PISO circuit. Thus, fault OQ76B is categorized as a functional/logical fault. Fault OR29C emulates an open circuit in the in the resistor R29. The faulty circuit was simulated with the "golden" vectors shown in Figure 6.2.5 and the voltage characteristics at the primary outputs of the PISO are shown in Figure 6.2.9. On comparing the simulation results of the fault-free circuit (Figure 6.2.4) with the simulation of the faulty circuit (containing the fault OR29C) shows that this fault forces both primary outputs of the PISO circuit to the same potential. Thus, fault OR29C is categorized as a like fault. Fault OR29C can also be categorized 43 Fault Characterization and Testing of Differential Current-mode Logic Circuits 3 . 3 0 Both differential^ outputs are < ^ 3 . 2 9 9 0 at the same potentail = 3.3 V. 3 3 . 2 9 9 0 3 . 2 9 9 0 = I I I I I i i i i 0 . 1 0 0 . O N 2 0 0 . O N ' ' S O O . O N ' ' l O o ' . O N 5 0 0 . O N S O O . O N T I M E C L I N 3 7 0 0 . O N Figure 6.2.9 A "Like" fault caused by insertion of open circuit fault OR29C. as a functional/logical fault. 44 Fault Characterization and Testing of Differential Current-mode Logic Circuits 3 . 3 0 , , . S O 1 0 9 C B . T R 0 V : C L K . 7 8 - H - A C L K . 7 B . B • . " ° S Q 1 0 9 C B . T R 0 ' ; DATAO.A - A : DATAO.B • , P S Q 1 0 9 C B . T R 0 '/ i D A T A l . A - A z D A T A l . B Q Both differential 3 • 2 0 data outputs^^g 1 Q are the samf as that of the a golden netlist. 3 The average 3 current is the same as that measured in the golden netlist. - 2 . 5 OH • 1 • 1 1 1 1 1 1 1 1 . . i . . i • 1 I I 1 1 1 1 0 4 - 4 — t r 1 1 i i i I i , .1 , X ,, 1, , i i i - A-SO109CB . TR 0 DATA_OUT_A S O l 0 9 C B . T R 0 •ATA_OUT_B 9 Q 1 0 9 C B . T R 0 H V V S S A VI , , , , . . 100.ON 2 0 0.ON 3 0 0 . O N 4 0 0 . O N 5 0 0 . O N GOO.ON 0 . TIME ( L I N ) 7 0 0 . O N Figure 6.2.10 A "Hidden" fault as a result of inserting short circuit fault SQ109CB. The voltage and current characteristics of a faulty circuit with the short fault SQ109CB ( a lOfi short between the base and collector of transistor Q109) are shown in Figure 6.2.10. The CUT was simulated using the "golden" vectors shown in Figure 6.2.5. The average supply current and the output voltage characteristics of the faulty CUT are identical to that of the fault-free circuit. This constitutes a hidden fault because there is no indication of faulty behavior exhibited by the faulty circuit. A complete fault characterization of the PISO circuit was done and the results are tabulated in Figure B . l in Appendix B. To correlate the tabulated results to the transistor level schematics, refer to the schematics of the 2:1 PISO in Appendix A. 45 Fault Characterization and Testing of Differential Current-mode Logic Circuits 60 0 Functional Parametric Like Hidden ldd 6 Fault Category Figure 6.2.11 Percentage of total faults in each fault class. The results from the fault characterization table of the 1:2 PISO circuit (Figures B.l) are summarized in the bar graph shown in Figure 6.2.11. Al l the faults inserted into the PISO circuit can cause the CUT to behave in several different ways. If there is a logical fault at the primary output of the PISO, the fault inserted has induced a functional/logical fault in the circuit. In addition, the fault may induce a parametric or like fault in the circuit. Also, a fault that falls into the above three fault categories, may also change the average ldd or supply current of the PISO circuit by more than +/- 30%, thereby constituting an ldd fault. If a fault neither changes the voltage characteristics nor the current characteristics of the circuit, it constitutes a hidden fault. Therefore, we find that a certain fault may fall into more than one fault class. The Venn diagram in Figure 6.2.12 illustrates the intersection between the various fault classes for the PISO circuit. 46 Fault Characterization and Testing of Differential Current-mode Logic Circuits / Functional \ / 2 8 . 3 0 % \ / Parametric y V ( .ike f \ 8.00%J ^ \ 1 0 . 3 0 % \ I 7 . 6 0 % / 4 . 5 % ) / \ 2 . 7 0 % \ / ^===y=^-^ldd / \ \ 2 3 . 5 0 % / 1 Hidden \ \ . I 1 5 . 1 0 % J Total Faults Inserted = 438 Figure 6.2.12 The relationship between the various fault classes. A defect that causes a hidden fault, may not seem to affect the functionality of the CUT. However, such a fault may degrade the noise margins of the CUT. Thus a circuit with a hidden fault may fail in the field, if the IC is subjected to a noisy environment. Therefore, it is important to detect as many hidden faults as possible. In Chapter 7, a novel test methodology has been proposed, which addresses the problem of detecting hidden, like and parametric faults during production test. 6.2.2 Fault Characterization of the 1:2 SIPO Circuit The fault characterization of the 1:2 SIPO circuit is based on the algorithm shown in Figure 6.2.4. The fault characterization methodology is the same as that used for the PISO circuit. The results of fault characterization of the SIPO circuit are tabulated in Figure B.2 in Appendix B. To correlate the faults to the transistor level schematics of the SIPO circuit, refer to the SIPO circuit schematics in Appendix A and the fault characterization tables in Appendix B. The results from the fault characterization tables of the 2:1 SIPO circuit (Figure B.2) are summarized in the 47 Fault Characterization and Testing of Differential Current-mode Logic Circuits 60 0 Functional Parametric Like Hidden ldd Fault Category Figure 6.2.13 Bar Graph to illustrate the number of faults in each fault category for the 1:2 SIPO circuit. / Functional / 3 3 . 5 % \ / Parametric \ l\ \ 7 ' 0 % l ( Like/ \ \ 8 . 1 % / \ \ 2 . 9 % J 13 .6% J \ 1 . 3 % \ J 1 Hidden \ -15 .4% / ldd / l 18.2% J Total Faults Inserted = 476 Figure 6.2.14 Venn diagram to illustrate the intersection between the various fault classes. bar graph shown in Figure 6.2.13. The Venn diagram in Figure 6.2.14 illustrates the intersection between the various fault categories. 48 Fault Characterization and Testing of Differential Current-mode Logic Circuits From the Venn diagram in Figure 6.2.14 it can be observed that there is an intersection between functional, paramteric, like, and Idd faults. 6.2.3 Fault Detection During Production Test The fault characterization tables of the PISO/SEPO circuit (Appendix B.2) show that less than 60% of the total defects inserted into the PISO/SIPO CUT fall into the functional fault category. These are faults which exhibit a logical error at the primary output of the CUT and would be detected during at-speed functional production test. Also, 30-40% of the total hard faults inserted into the PISO/SIPO CUTs fall into the Idd fault category. Such faults would also be detected during production, using Idd test. Parametric hard faults either cause the voltage at the primary outputs to degrade or cause the output to switch faster or slower than the nominal switching behavior of the circuit i.e., they degrade the AC timing of the circuit. Parametric faults that degrade the voltage characteristics of the CUT do not necessarily change the logical behavior of the circuit. Such parametric faults may or may not cause a logical error at the primary output of the CUT. Thus, faults that cause a marginal degradation of the output voltage levels (i.e., less than +/-30% ) are not detected during production test. However, in very noisy conditions, such parametric faults may cause a logical error in the circuit and therefore it is important to detect such faults. The Idd current of such parametric hard faults may or may not violate the +/- 30% (of nominal supply current) tolerance margin defined for Idd test. Therefore, parametric faults that change the voltage behavior of a CUT may or may not get detected during production test. Parametric hard faults which cause a delay in the switching characteristic of the CUT can usually be detected during at-speed functional test, because such faults violate setup and hold times of flip-flops, thereby causing a logical fault. In the PISO/SIPO circuits, 4% of the parametric faults caused a logical error at the primary output of the CUT and therefore would be detected during production test. In a like fault both differential outputs of the circuit have the same voltage characteristics at 49 Fault Characterization and Testing of Differential Current-mode Logic Circuits one or more primary output of a CUT. Depending on the voltage characteristics of the output, like faults may or may not manifest themselves as logical faults at one or more primary output. In the PISO/SIPO circuits 3% of the like faults caused a logical error at the output during at-speed functional testing. None of the like faults caused an Idd failure in the PISO/SIPO CUTs. During our experiments with the PISO/SEPO circuits, we found an overlap between circuits that exhibit both logical faults at the primary outputs as well Idd faults. 80% of the total faults that caused a logical error at the primary output of the PISO/SIPO CUTs also caused an Idd test failure. Therefore, if at-speed functional/logical and Idd testing are the two primary tests used during production testing, due to the overlap between faults that exhibit a logical error at the output and Idd faults, the average number of faults detected during production test may vary between 75% to 80%. These results are similar to those found by Hessabi et. al. [18] while testing combinational CML circuits. Production testing of CML CUTs using at-speed functional/logical test and Idd test alone is not adequate. For larger CUTs ( > 5000 nodes), exhaustive at-speed functional/logical testing is an impossible task. Therefore, the percentage of faults that would be detected during at-speed functional test, where a limited functionality of the CUT is tested, would drop significantly. It is reasonable to assume that only 65-70% of the total hard faults would be detected in a large CUT, using at-speed functional/logical and Idd tests. For a reasonably large CUT ( > 1000 nodes), 65-70% fault coverage is obviously inadequate. Therefore, it is imperative that we find another non-intrusive method of testing CML circuits to enhance fault coverage. In the next chapter we propose a method to improve fault coverage of CML circuits during production test. 50 Fault Characterization and Testing of Differential Current-mode Logic Circuits Chapter 7 Common Mode Testing of Differential CML Circuits In this chapter a simple non intrusive method of testing CML circuits is introduced. This method of testing CML has never been documented in the literature and as per the authors' knowledge is a novel method to enhance the test coverage of CML circuits during production test. This method of testing sequential CML circuits is called common mode testing. 7.1 Common Mode Testing Methodology In common mode testing (CMT), both differential inputs of the emitter coupled pair are tied to a common dc potential equal to Vin(max). However, the clocks are allowed to run free as in normal operation of the circuit. This allows the combinational and sequential elements of the circuit to settle to a certain state, which is propagated to the primary outputs. In CMT, all the differential inputs (except clock and reset pins) of the fault-free circuit are tied high. The clock is allowed to run free at the nominal clock frequency of the circuit. The logical behavior at the primary outputs of the CUT is recorded in a "golden" data base. Since, the inputs of the CUT do not change state, the number of clock cycles required to simulate the entire circuit is n + 1, where n is the number of serial memory elements in the CUT. This is because it takes n + 1 clock cycles to propagate the results to the primary outputs via n memory elements. 51 Fault Characterization and Testing of Differential Current-mode Logic Circuits Hard faults are serially inserted into the CUT and the faulty CUTs are simulated serially under the same conditions (i.e., all inputs tied high and free running clocks) as the "golden" or fault-free netlist. The voltage transfer characteristics (VTCs), at the primary outputs of the faulty circuits are compared to that of the golden circuit for logical equivalence. If the VTCs of the fault-free CUT are logically different from those of the faulty CUT, the fault is detected. We now look at a simple emitter coupled circuit to understand common mode testing of a CML circuit. Vtn+ Vtn-,0 .OB Figure 7.1.1 The Emitter Coupled Pair is the most basic element of any differential mode CML circuit. The differential mode emitter-coupled pair of BJTs, which is the common building block of CML circuits, is shown in Figure 7.1.1. It is assumed that the differential pair is fully balanced. Thus, for all intents and purposes, the npn transistors (QI and Q2) and the resistors (Rl and R2) respectively are assumed fully matched. This is not an unrealistic assumption because 52 Fault Characterization and Testing of Differential Current-mode Logic Circuits all elements are in proximity to each other in silicon and are relatively immune to process variations. In common mode testing, the input voltages into both terminals Vin+ and Vin- are equal. Therefore, the bias current, 1^, is split equally into the two arms of the common-emitter circuit. The output voltages Vq and Vqb are therefore identical, since IDias/2 flows through each arm of the differential pair and each arm consists of an identical output load. Let us assume that a hard fault is introduced into the circuit. The hard fault causes the current flowing through QI to exceed the current flowing through Q2 (or vice versa) by AI. This causes the output voltage Vq and Vqb to differ by A V = 2RAI. If the output of this CUT is a primary output, the difference in voltage between the two primary outputs A V , will propagate to a primary output and the tester shall detect the presence of a hard fault. If the output of the common-emitter circuit is fed into the inputs of another CML circuit, the input differential pair of the following circuit will detect the difference between the input differential voltages and therefore the difference is propagated to the output of the following circuit. In this manner, the effect of the fault shall propagate to the primary output, where it is detected by the tester as a logical error. The 2:1 PISO and 1:2 SIPO circuit were subjected to common-mode testing. Many of the parametric, like, and hidden faults, not detected during at-speed functional or Idd test, were detected by common-mode testing of CML circuits. Common-mode testing also provides a better vehicle to expose parametric and/or delay faults in a CUT. This is because the voltage transfer characteristics of the circuit with the parametric (or any other fault) can be significantly different from the VTCs of the fault-free circuit and these voltage characteristics can be propagated to a primary output. Therefore, common mode testing in conjunction with Idd testing and at-speed functional testing can improve the testability of the CUT. In the case of the 1:2 PISO common-mode testing, in conjunction with at-speed and Idd testing, improved the fault coverage to 91.7%. Similarly, the fault coverage of the SIPO CUT improved to 88% using common-mode, at-speed functional and Idd test. 53 Fault Characterization and Testing of Differential Current-mode Logic Circuits 7.1.1 Common Mode Testing of the PISO/SIPO Circuits In order to understand the impact of common mode testing on the fault coverage of CML, the 1:2 PISO circuit, was subjected to a common mode test. Figure 7.1.2 shows the response at the primary outputs of the fault-free 2:1 PISO circuit. For example, let us introduce a fault into the 2:1 PISO circuit. The fault inserted is an open circuit fault OQ92E (Figure A. 14), which was neither detected by functional testing nor by Ida testing. In fact, fault OQ92E is a hidden fault. The fault-free PISO netlist and the faulty netlist are tested in common-mode, under the same conditions. The response at the primary outputs of the faulty 2:1 PISO circuit is shown in Figure 7.1.3. On comparing the voltage transfer characteristics at the output of the faulty circuit (Figure 7.1.3) with the response at the primary outputs of the fault-free circuit (Figure 7.1.2), we notice the difference in the output response of the two circuits during common-mode testing. Since the output response at the primary outputs of the faulty and fault-free circuit are different, the fault has been detected. This is an example of a hidden fault being detected by common-mode testing. The results of the common mode test along with at_speed functional and Idd tests of the 2:1 PISO circuit are tabulated in Figure 7.1.4. It was observed that common-mode testing of CML circuits facilitated the detection of various hidden and parametric faults, which manifest themselves as logical faults at the primary outputs of the CUT during CMT. Therefore, it is possible to detect such faults easily during production testing using common mode testing. Common mode testing was also performed on the 1:2 SIPO circuit. The combined results of common mode testing, Idd testing and functional testing of the SIPO circuit are shown in Figure 7.1.5. The test results in Figures 7.1.4 and 7.1.5 indicate that fault coverage during production test of CML circuits can be greatly enhanced using common-mode testing. A large percentage of hidden, like, and parametric faults can be detected as logical faults at the primary outputs of the 54 Fault Characterization and Testing of Differential Current-mode Logic Circuits Response at primary outputs of 2:1 mux circuit. 3 . 3 0 3 . 30 t 3 . 3 0 1 3 . 3 0 -m I I I I I I I I I I I I I I , - MUX21 . TR 0 Of lT f l0_ f l - A i i i i i 3 . 30 ; 3 . 3 0 I" 3 . 3 0 : 3 . 3 0 • i i i i i i i i i i i i i i • i i i , - MUX21 .TRO DATA1_A - A i i i I I I i 3 3 . 2 9 9 1 MUX21 .TRO OATA_OUT_A : M U X 2 1 . T R 0 _E OATO_OUT_B z A • i i i T i i i r-i—i—i i i I I— i— t - i i i V i a 1 0 0 . O N 2 0 0 . O N SOO.ON M00.ON 5 0 0 . O N GOO.ON TIME C L I N ) 70 0.ON Figure 7.1.2 Common Mode Fault Simulation of 2:1 PISO Circuit. PISO / SIPO circuits using a standard production phase tester5. A digital tester is assumed as the production phase tester. The tester should be able to tie all the inputs of the CUT high and sample the output of the CML CUT. The design engineer specifies the number of clock cycles for which the tester is run to propagate all the faults to the output of the tester. 55 Fault Characterization and Testing of Differential Current-mode Logic Circuits 3 . 3 D 3 . 3 0 3 . 3 0 3 . 3 0 i 0 0 1 3 9 B . T R O DflTAO.f l 3 .3 0 3~ i i t i I I I I i l i i i i l i i i i l i i i i l i i i i i I I i i s j 3 . 3 0 3 . 3 0 3 . 3 0 J L___A 1, * 1. A i A 1, * 1. Ji D Q 1 3 9 B . T R 0 { ^ s 1 DRTfl 0_B l i l t M 4 Response at primary outputs of faulty mux circuit. • i i i i i i i i i i i i • i i i i i i i ^ O O 1 3 9 B . T R 0 - Df lTA_OUT_fl - A • i i I i i i i I i i i i i i i I i i i i • 0 0 1 3 9 9 . T R O DATA _0UT _Q 3 . 1 0 -H — i — I T — i — k * - i — r * i — i — H = I I I I I I—i—r-*i—I—y—i—i r I 1 0 0 . O N 2 0 0 . O N 3 0 0 . O N t O O . O N 5 0 0 . O N B 0 0 . O N 0. TIME C L I N ) 7 0 0 . O N Figure 7.1.3 Common mode testing of a faulty 2:1 PISO circuit, with open circuit fault OQ92E. At-Speed Functional Test /Common Mode\ / Test \ / Functional \ / \ / faults \ / \ Parametric \ \ 23.78% Y8.37°/J faults \ 5% 3.30% J l^keFauJts \ 8.37% An 22% 1 l 7 . 5 9 y / 5 7 y \7 o.2\ y ^ \ — , J J ( /18.5%/ \9 1 %\\ faults / 7 (Hidden\ \ ldd \ faults \J / Test 6.0% Total Faults Inserted = 438 Figure 7.1.4 Venn Diagram to show the intersection between CMT, functional test and Idd test and the coverage of various fault classes within each test methodology. 56 Fault Characterization and Testing of Differential Current-mode Logic Circuits TESTS % of Total Shorts Detected % of Total Opens Detected Common Mode Test 68% 69% Idd test 34% 33% At-speed Functional test 58% 58% Total Fault Coverage of the intersection = 90.7% Figure 7.1.5 Simulated test results for the 2:1 PISO circuit, including Common Mode Test, Functional Test and I<jd Test. At-Speed Functional / \ Test / Common Mode \ / Test \ 7 Funct iona l^ / \ / fa lts \ / Parametric \ 2 4 . 8 6 % V5 . 05% i faults \ 5 % \ 5 % / / L i k e f a u H ^ 1 3 6 o / / \ 0 . 8 4 % u8-9°wJ 7 VJ 0 . 4 2 % \ ^ / \ % V Idd faults / l 2 . 6 % y /H ldder i \ l l . 5%\ . / Faults \ J-—" 7 % / Idd Test Total Faults Inserted = 476 Figure 7.1.6 Venn diagram to illustrate the faults detected for the 1:2 SIPO circuit. 57 Fault Characterization and Testing of Differential Current-mode Logic Circuits TESTS % of Total Shorts Detected % of Total Opens Detected Common Mode Test 69% 70% I d d test 38% 39% At-speed Functional test 58% 58% Total Fault Coverage of the intersection = 88% Figure 7.1.7 Simulated test results for the 1:2 SIPO circuit, including common mode test, functional test and hi test. 58 Fault Characterization and Testing of Differential Current-mode Logic Circuits Chapter 8 Conclusion During production test of differential input, current-mode logic circuits, it has been found that functional testing of circuits, using at-speed functional vectors alone, is inadequate to achieve a sufficiently high ( > 90%) fault coverage. To maintain a low rate of device failure in the field, manufacturers of CML devices must improve the fault coverage of their ICs. The main objective of this thesis was to find a non intrusive method to test differential current-mode logic circuits, which would increase the fault coverage of CML ICs during production test. Common-mode testing, a novel, yet non-intrusive, method to test CML circuits has been introduced in this thesis. A new method to test CML circuits using Idd test is also discussed. Two reasonably complex circuits - a 2:1 PISO and a 1:2 SIPO circuits were used for serial fault insertion, serial fault simulation and fault characterization. Although, the PISO/SIPO CUTs do not cover the entire library of CML circuits, they provide valuable insight into the test problems faced by engineers during production test of sequential CML circuits. Fault models of catastrophic open and short circuits were developed, and these fault models were used extensively for fault characterization of the PISO and SIPO circuits. The fault characterization results found in this thesis for sequential CML circuits are consistent with those found by Hessabi et. al. in [14] for combinational circuits. From simulations of the PISO and SIPO circuits it has been found that common-mode 59 Fault Characterization and Testing of Differential Current-mode Logic Circuits testing of CML circuits is vital to enhance production fault coverage. The results show that common-mode testing, coupled with Idd and at-speed functional testing can enhance production fault coverage up to 92% of the catastrophic faults in the 2:1 PISO and 1:2 SIPO circuits. Since common-mode tests induce logical errors at the primary output of the PISO/SIPO CUTs, such faults would propagate through a cascade of 2:1 PISOs and 1:2 SIPOs too. Therefore, common-mode test of the 2:1 PISO and 1:2 SIPO is quite generic for testing larger PISO/SIPO circuits. Future studies in the area of CML testing include: detecting soft faults in CML circuits, built-in self test (BIST) strategies to test CML circuits and incorporating circuits on-chip for Idd testing of the IC. Another possible area of research is design-for testability of CML circuits. 60 Fault Characterization and Testing of Differential Current-mode Logic Circuits Bibliography [1] G. Wilson, " Creating Low Power Bipolar ECL at VLSI densities," VLSI Systems Design, pp. 84-86, May 1986. [2] S.M. Menon, A.P. Jayasuma and Y.K. Malaiya, "Fault Modeling of ECL Devices," Electronic Letters, Vol. 26, No. 15, pp. 1105-1108, July 1990. [3] E. Kofi-Vida Torku, A. Parise, Rhonda K. Gaede, "Modeling of Bipolar DCS DOT circuits," Proc. of IEEE Midwest Symposium on Circuits and Systems, pp. 1124-1127, 1992. [4] M.O. Esonu, D. Al-Khalili and C. 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Torku, "Do Stuck Fault Models Reflect Manufacturing Defects," Proc. International Test Conference, pp. 35^-2, 1982. [10] S. Hessabi, M.Y. Osman, M.I. Elmasry, "Differential BiCMOS Logic Circuits: Fault Characterization and Design - for - Testability, " IEEE Transactions on VLSI Systems, pp. 437^145, Sept. 1995. 61 Fault Characterization and Testing of Differential Current-mode Logic Circuits [11] D.L. Pulfrey, N. Garry Tarr, Introduction To Microelectronic Devices, Prentice Hall, pp.375 - 377, 1989. [12] A.J. Bishop, A. Ivanov, "Fault Simulation and Testing of an OTA Biquadratic Filter," ISCAS - '95, Seattle, Washington, April, 1995. [13]Ingmar Andersson, B. Rudberg et. al.,"Silicon Bipolar Chipset for SONET/SDH 10 Gbit/s Fiber-Optic Links," Proc. of Custom Integrated Circuit Conference, pp. 617-618, 1994. [14] M . Abromovici, A. Breuer and A. D. Friedman, Digital System Testing and Testable design, Computer Science Press, 1990. [15] K.M. Butler and M.K. Mercer, Assessing Fault Models and Test Quality, Kluwer Academic Publications, 1992. [16]E.M.J.G. Bruls, "Reliability aspects of defect analysis,"Proc. of European Test Conference, pp. 17-25, 1993. [17]F.F. Tsui, LSI/VLSI Testability Design, McGraw-Hill, New York, 1987. [18] S. Hessabi, "Fault Characterization and Design-for- Testability of Digital BiCMOS Circuits, " Ph.D. Dissertation, University of Waterloo, Mar. 1996. [19]T.W. Williams and N.C. Brown, "Defect Level as a Function of Fault Coverage," IEEE Trans, on Computers , Vol. C-30, No. 12, pp. 987-988, December, 1981. [20]V.D. Agrawal, S.C. Seth, "Sampling Techniques for Determining Fault Coverage in LSI Circuits," Journal of Digital Systems, Vol. 5, No. 3, pp. 189-202, Fall, 1981. [21] S.C. Seth and V.D. Agrawal, "Characterizing the LSI Yield Equation from Wafer Test Data," IEEE Trans, on Computer Aided Design, Vol. CAD-3, No.2, pp 123-126, April 1984. [22]R.G.. Daniels and W.C. Bruce, "Built-in Self-Test Trends in Motorola Microprocessors," IEEE Design and Test of Computers Vol. 2, No. 2, pp. 64-71, April 1985. [23] E.J, McCluskey and F. Buelow, "IC Quality and Test Transparency," Proc. Intl. Test Conf., pp. 295-301, September, 1988. 62 Fault Characterization and Testing of Differential Current-mode Logic Circuits r241 HSPICE User's Manual: Simulation and Analyses, Vol. 2, ©1996 Meta Software Inc. [251 Motorola MECL Data Book, Ql/93, DL122/D, Rev. 5, pp. 1-2, 1993. [26] NORTEL - Northern Telecom CML Library, Project Pegasus, Revision 1, 1994. 63 Appendix A Schematics of SIPO/PISO Circuits A.1 2:1 SIPO Circuit Schematics o I cd co "a JH ° i "co •o X c r qb JH O qb CO JH JH o C/3 cvi CO CO JH JH LL a CT JH TJ TO O -O O LL LL Q .O TJ T3 JH O O ft* - J •g ~ TJ 00 j_ O Figure A.1.1 2:1 SIPO circuit 64 db mss3 dlatch 1 mss3_dlatch_2 « CKB bias mss3 dlatch 3 Figure A.l.3 Master-Slave-Slave circuit (mss_3) mss4p_dlatch_1 ckb ^ _ 0 0 DB oa CK CKB taos ross4p_dlatch 2 mss4p_dlatch_3 Figure A.1.2 Master-Slave-Slave circuit (mss_4p) 65 ms 3 dlatch.3 1 d db ck ckb bios D Q DB dlotch_3 OB CK CKB BIAS ms 3 dlatch3 2 D Q OB dlatch_3 QB CK CKB BIAS . qb Figure A.l.4 Master-Slave circuit (ms_3) 66 BIAS ^ Q101 Q-NN5C212X NN5C212X Q105 NN5C212X : R110 R109 S'tf 1 0Tj_. L K > 103 Q104 NN5C212X NN5C212X Q106, NN5C212X • k Q107 NN5C212X ?R108 • Q • QB Figure A. 1.5 dlatch_5_l 67 Q91 Q92 NNSC212X NN5C212X " Q9S NN5C212X VGND , ! | | R99 R100 Q94 Q93 NN5C212X NN5C212X Q96 NN5C212X y1 - - -a Q97 NN5C212X Figure A.l.6 dlatch_5_2 68 CKB W Q81 Q82 NN5C212X NN5C212X Q85 NN5C212X V E N D , R90 | K Q84 Q83 NNSC2I2X NN5C212X Q86 NN5C212X ?1 , Q87 NN5C212X • OB Figure A. 1.7 dlatch_5_3 69 VCNP , DB W Q7 Q6 NN5C212X NN5C2I2X Q10 NN5C212X i a m s BUS: Q8 Q9 NNSC212X NN5C212X NN5C212X Q12 NN5C212X 15 • QB Figure A.l.8 mss_3_dlatch_3_l 70 VGNP , D ^ Q17 Q16 NN5C212XNN5C2I2X ' Q20 NNSC212X * 53 R 2 S R24 % Q18 Q19 NN5C212X NNSC212X Q21 NN3C212X Q22 NNSC212X IS R23 VEE, • Q •QB Figure A. 1.9 mss_3_dlatch_3_2 71 VGND , R35 R34 3 « 1 ! fa i Q27 Q26 NN5C212X NN5C212X ' _Q28 Q29 NN5C212X NN5C212X Q30 NN5C212X Q31 NN5C212X Q32 NN5C212X I S R33 • 0 • QB Figure A.l.10 mss_3_dlatch_3_3 72 VGND , lit R44 R45 S < CKB ^ Q36 Q37 NNSC212X NN5C212X ' n Q39 Q38 NN5C212X NN5C212X Q40 NN5C2I2X Q41 NNSC212X , Q42 NN5C212X l a R43 • a • QB Figure A.l.11 ms_3_dlatch_3_l 73 VGND , DB W , R44 Q36 Q37 i NN5C212X SN5C212X h ^ _Q39 Q38 NN5C212X NN5C212X Q40 NN5C212X Q41 NNSC212X • k Q42 NN5C212X 1« VEE . - • Q B Figure A.l.12 ms_3_dlatch_3_2 74 Figure A. 1.13 Bias Circuit for the SIPO circuit 75 A.2 1:2 PISO Circuit Schematics o I as 03 TJ ft ft ° l CO •*—> CO "O X cr _Q J_l O 0~ CO o 03 6j CO CO JD JD o JD cr JD TJ TJ JD O O Li. Q O-JD CT JD " a TJ JD o o LL LL Q JD TJ TJ JD o o ft* ° , 8 . « J CO CO +-L - a « CO to TJ ft 00 _Q r> oo o o Figure A.2.14 Top level block diagram of the 1:2 PISO circuit. 76 o o 3v. -TV. IK" Figure A.2.15 DFF_1 77 a a rem 2v. *7 I V 4 Figure A.2.16 DFF_2 78 Figure A.2.17 D-LATCH 79 vgnd ABl b i a s -- - • k • ""Q126 IQ127 J R 1 3 3 SR134 w > R 1 3 5 fl>R136 I Q 1 3 1 Q 1 3 2 1 k Q B Figure A.2.18 Clock Buffer Circuit. 80 A B I bias vqnd -4 - - B Q 1 3 8 Q 1 3 9 B - -4-V , V • Q U O *tS R142 . Q B Figure A.2.19 Data Buffer Circuit. 81 • - V W W H 7 ^ 098 19« l-JVWW^—1 E9M CO u CD Figure A.2.20 Output data selector. 82 • r r nam =J 00 0 L =j bi I J U — i A V M P .uufl Figure A.2.21 Bias circuit for the PISO circuit 83 Appendix B Fault Characterization Results of the PISO/SIPO CUTs Fault Class Simulated Physical Defect Functional faults OQ105C OQ105E OQ106B OQ106C OQ106E OQ107C OQ107E OQ108B OQ108C OQ108E OQ109B OQ109C OQ109E OQ110E OQ111B OQ111C OQ112B OQ112C OQ112E OQ113B OQ113C OQ113E OQ114B OQ114C OQ114E OQ115B OQ115C OQ115E OQ116B OQ116C OQ116E OQ117B OQ117C OQ117E OQ118B OQ118C OQ118E OQ125B OQ125C OQ125E OQ126E OQ127E OQ128B OQ128C OQ128E OQ129B OQ129C OQ129E OQ130B OQ130C OQ130E OQ131B OQ131E OQ132B OQ132C OQ132E OQ138B OQ138E OQ139B OQ139E OQ140C OQ22B OQ22C OQ22E OQ64B OQ64C OQ64E OQ65B OQ65C OQ65E OQ66B OQ66C OQ66E OQ67B OQ67C OQ67E OQ68B OQ68C OQ68E OQ69B OQ69C OQ69E OQ70B OQ70C OQ70E OQ71B OQ71C OQ71E OQ72B OQ72C OQ72E OQ73E OQ74E OQ75B OQ75C OQ75E OQ76B OQ76C OQ76E OQ77C OQ77E OQ79C OQ81E OQ85B OQ86E OQ89C OQ89E OQ90C OQ93B OQ93C OQ94B OQ94C OQ94E OQ95B OQ95C OQ96B OQ96C OQ97B OQ97C OQ97E OQ98B OQ98C OQ98E OR103C OR104C OR120C OR121C OR122C OR123C OR124C OR135C OR136C OR137C OR141C OR143C OR41C OR43C OR44C OR45C OR46C OR47C OR48C OR82C OR99C SQ105BE SQ105CB SQ105CE SQ106BE SQ107BE SQ107CB SQ107CE SQ108BE SQ108CB SQ108CE SQ109BE SQ109CE SQ110BE SQ110CB SQ110CE SQ111CB SQ111CE SQ112BE SQ112CB SQ112CE SQ113BE SQ113CE SQ114BE SQ114CE SQ115BE SQ115CB SQ115CE SQ116BE SQ116CB SQ116CE SQ117BE SQ117CB SQ117CE SQ118BE SQ118CB SQ118CE SQ128BE SQ128CE SQ129BE SQ129CE SQ130BE SQ131BE SQ132BE SQ132CE SQ138BE SQ138CB SQ138CE SQ139BE SQ139CB SQ139CE SQ140BE SQ64CE SQ65CE SQ66CB SQ66CE SQ67CB SQ67CE SQ69CE SQ70CE SQ71BE SQ71CB SQ72BE SQ72CB SQ72CE SQ75BE SQ75CE SQ76BE SQ76CE SQ77CB SQ78CB SQ79BE SQ80BE SQ80CB SQ80CE SQ81BE SQ85BE SQ86BE SQ87BE SQ88BE SQ88CB SQ88CE SQ89BE SQ89CE SQ90BE SQ91CB SQ92CB SQ93BE SQ93CE SQ94BE SQ94CE SQ95BE SQ95CB SQ95CE SQ96BE SQ96CB SQ6CE SQ97BE SQ97CB SQ97CE SQ98BE SQ98CB SQ98CE SRIOORaRb SRIOlRaRb SR102RaRb SR103RaRb SR104RaRb SR119RaRb SR120RaRb SR121RaRb SR122RaRb SR123RaRb SR124RaRb SR133RaRb SR134RaRb SR136RaRb SR137RaRb SRHlRaRb SR143RaRb SR62RaRb SR63RaRb SR83RaRb SR84RaRb Figure B . l Fault Characterization of the 2:1 PISO Circuit. (Continued) . . . 84 Fault Class Simulated Physical Defect Parametric Faults OQ105B OQ111E OQ131C OQ138C OQ139C OQ140B OQ20B OQ20C OQ20E OQ21B OQ21C OQ23B OQ23C OQ73B OQ74B OQ79B OQ81B OQ81C OQ85C OQ86B OQ86C OQ87B OQ90E OQ95E OQ96E OR100C OR119C OR25C OR27C OR28C OR31C OR50C OR59C OR60C SQ106CB SQ126CB SQ127CB SQ130CB SQ20BE SQ20CB SQ20CE SQ21BE SQ22BE SQ22CB SQ23BE SQ23CE SQ64CB SQ65CB SQ68CE SQ69CB S70CB SQ71CE SQ73BE SQ73CB SQ74BE SQ74CB SQ86CB SR26RaRb SR28RaRb SR29RaRb SR30RaRb Like Faults OQ140E OQ22B OQ22C OQ22E OQ66E OQ67C OQ67E OQ68B OQ68C OQ68E OQ78C OQ78E OQ79C OQ79E OQ80C OQ80E OQ81B OQ81E OQ85E OQ87COQ87E OQ88C OQ88E OQ91E OQ93E OR101C OR102C OR29C OR42C OR83C OR84C SQ140CB SQ21CB SQ21CE SQ22CE SQ64BE SQ65BE SQ66BE SQ67BE SQ68BE SQ68CB SQ69BE SQ70BE SQ81CB SQ85CB SR142RaRb SR27RaRb SR31RaRb SR59RaRb SR60RaRb SR61RaRb SR82RaRb SR99RaRb Figure B . l Fault Characterization of the 2:1 PISO Circuit. (Continued) . . . 85 Fault Class Simulated Physical Defect Hidden Faults OQ107B OQ110B OQ110C OQ126B OQ126C OQ127B OQ127C OQ21E OQ23E OQ73C OQ74C OQ77B OQ78B OQ80B OQ88B OQ89B OQ90B OQ91B OQ91C OQ92B OQ92C OQ92E OR133C OR134C OR142C OR26C OR30C OR53C OR54C OR58C OR61C OR62C OR63C SQ106CE SQ109CB SQ111BE SQ113CB SQ114CB SQ125BE SQ125CE SQ126BE SQ126CE SQ127BE SQ127CE SQ128CB SQ129CB SQ130CE SQ131CB SQ131CE SQ132CB SQ140CE SQ73CE SQ74CE SQ75CB SQ76CB SQ77BE SQ77CE SQ78BE SQ78CE SQ79CB SQ79CE SQ81CE SQ85CE SQ86CE SQ87CB SQ87CE SQ89CB SQ90CB SQ90CE SQ91BE SQ91CE SQ92BE SQ92CE SQ93CB SQ94CB SR135RaRb SR25RaRb SR41RaRb SR42RaRb SR43RaRb SR44RaRb SR45RaRb SR46RaRb SR47RaRb SR48RaRb SR50RaRb SR53RaRb SR54RaRb SR58RaRb idd faults OQ105C OQ105E OQ106C OQ106E OQ107C OQ107E OQ108C OQ108E OQ109C OQ109E OQ110C OQ110E OQ111E OQ112E OQ113E OQ114E OQ115C OQ115E OQ116C OQ116E OQ117C OQ117E OQ118C OQ118E OQ125C OQ125E OQ126C OQ126E OQ127C OQ127E OQ128E OQ129E OQ130B OQ130C OQ130E OQ131E OQ132E OQ138E OQ139E OQ140C OQ140E OQ20B OQ20C OQ20E OQ21B OQ21C OQ22B OQ22C OQ22E OQ23B OQ23C OQ64E OQ65E OQ66C OQ66E OQ67C OQ67E OQ68C OQ68E OQ69E OQ70E OQ71C OQ71E OQ72C OQ72E OQ73C OQ73E OQ74C OQ74E OQ75C OQ75E OQ76C OQ76E OQ77C OQ77E OQ78C OQ78E OQ79C OQ79E OQ80C OQ80E OQ81C OQ81E OQ85C OQ85E OQ86C OQ86E OQ87C OQ87E OQ88C OQ88E OQ89C OQ89E OQ90C OQ90E OQ91E OQ92E OQ93E OQ94E OQ95C OQ95E OQ96C OQ96E OQ97C OQ97E OQ98C OQ98E OR27C OR28C OR29C OR31C OR45C OR48C OR50C SQ105CB SQ106CB SQ126CB SQ126CE SQ127CB SQ127CE SQ128BE SQ128CB SQ129BE SQ129CB SQ130BE SQ130CB SQ130CE SQ140CB SQ20BE SQ20CE SQ21BE SQ21CB SQ21CE SQ22CB SQ22CE SQ68CB SQ73CB SQ74CB SQ81CB SQ85CB SQ86CB SRIOORaRb SR119RaRb SR120RaRb SR13RaRb SR134RaRb SR137RaRb SR142RaRb SR25RaRb SR26RaRbSR27RaRb SR28RaRb SR29RaRb SR30RaRb SR31RaRb SR61RaRb SR62RaRb SR63RaRb SR82RaRb SR99RaR Figure B . l Fault Characterization of the 2:1 PISO Circuit. 86 Fault Class Simulated Physical Defect Functional faults OQ101B OQ101C OQ101E OQ102B OQ102C OQ102E OQ103C OQ103E OQ104C OQ104E OQ105B OQ105C OQ105E OQ106E OQ107B OQ107E OQ10B OQ10C OQ10E OQ11B OQ11C OQ11E OQ12B OQ12C OQ12E OQ16B OQ16C OQ16E OQ17B OQ17C OQ17E OQ18B OQ18E OQ19B OQ19E OQ20B OQ21B OQ21E OQ26B OQ26C OQ26E OQ27B OQ27C OQ27E OQ28E OQ29E OQ30C OQ31E OQ36B OQ36C OQ36E OQ37B OQ37C OQ37E OQ38B OQ38C OQ38E OQ39B OQ39C OQ39E OQ40B OQ40C OQ41B OQ41E OQ46B OQ46C OQ46E OQ47B OQ47C OQ47E OQ48E OQ49E OQ50C OQ51E OQ56E OQ57B OQ57C OQ59B OQ6B OQ6C OQ6E OQ7B OQ7C OQ7E OQ81B OQ81C OQ81E OQ82B OQ82C OQ82E OQ83C OQ83E OQ84C OQ84E OQ85B OQ85C OQ85E OQ86C OQ86E OQ87B OQ87C OQ87E OQ8B OQ8C OQ8E OQ91B OQ91C OQ91E OQ92B OQ92C OQ92E OQ93C OQ93E OQ94C OQ94E OQ95B OQ95C OQ95E OQ96C OQ96E OQ97B OQ97E OQ9B OQ9C OQ9E OR100C OR109C ORI IOC OR13C OR14C OR15C OR34C OR35C OR54C OR55C OR63C OR75C OR78C OR79C OR88C OR89C OR90C OR99C SQ101BE SQ101CB SQ101CE SQ102BE SQ102CB SQ102CE SQ105BE SQ106BE SQ106CE SQ107BE SQ107CB SQ10BE SQ10CB SQ10CE SQ11BE SQ11CB SQ11CE SQ12BE SQ12CB SQ16BE SQ16CE SQ17BE SQ17CE SQ18BE SQ18CE SQ19BE SQ19CE SQ20CB SQ20CE SQ21CE SQ22CB SQ26CE SQ27CE SQ30CB SQ31CE SQ32CB SQ32CE SQ36BE SQ36CB SQ36CE SQ37BE SQ37CB SQ37CE SQ38BE SQ38CE SQ39BE SQ39CE SQ40CB SQ40CE SQ41CE SQ42CB SQ46CE SQ47CE SQ50CB SQ51CE SQ52CB SQ52CE SQ56CE SQ57BE SQ58CB SQ6BE SQ6CB SQ6CE SQ7BE SQ7CB SQ7CE SQ81BE SQ81CE SQ82BE SQ82CE SQ83CB SQ84CB SQ85BE SQ86BE SQ86CE SQ87BE SQ87CB SQ8BE SQ8CB SQ8CE SQ91BE SQ91CE SQ92BE SQ92CE SQ95BE SQ96BE SQ96CE SQ97BE SQ97CB SQ9BE SQ9CB SQ9CE SRIOORaRb SR108RaRb SR109RaRb SRllORaRb SR13RaRb SR14RaRb SR15RaRb SR24RaRb SR25RaRb SR44RaRb SR45RaRb SR62RaRb SR64RaRb SR65RaRb SR88RaRb SR89RaRb SR90RaRb SR98RaRb SR99RaRb Parametric Faults OQ18C OQ19C OQ20C OQ21C OQ22B OQ22C OQ22E OQ30B OQ42B OQ42C OQ42E OQ50B OQ56B OQ56C OQ59C OR23C OR24C OR25C OR43C OR61C OR64C OR67C SQ18CB SQ19CB SQ20BE SQ21BE SQ21CB SQ22BE SQ26BE SQ26CB SQ27BE SQ27CB SQ31CB SQ38CB SQ39CB SQ40BE SQ41BE SQ41CB SQ42BE SQ46BE SQ46CB SQ47BE SQ47CB SQ51CB SQ56BE SQ58BE SQ59BE SQ59CE SR23RaRb SR34RaRb SR35RaRb SR43RaRb SR54RaRb SR55RaRb SR66RaRb Figure B.2 Fault Characterization of the 1:2 SIPO Circuit. (Continued) . . . 87 Fault Class Simulated Physical Defect Like Faults OQ20E OQ28B OQ28C OQ29B OQ29C OQ30E 0Q31B 0Q31C OQ32B OQ32C OQ32E OQ40E 0Q41C OQ48B OQ48C OQ49B OQ49C OQ50E OQ51B OQ51C OQ52B OQ52C OQ52E OQ58B OQ58C OQ58E OR33C OR44C OR45C OR53C OR65C OR73C OR76C OR77C OR80C SQ28BE SQ28CB SQ28CE SQ29BE SQ29CB SQ29CE SQ30BE SQ30CE SQ31BE SQ32BE SQ48BE SQ48CB SQ48CE SQ49BE SQ49CB SQ49CE SQ50BE SQ50CE SQ51BE SQ52BE SQ57CB SQ57CE SQ58CE SR33RaRb SR53RaRb SR63RaRb SR67RaRb Hidden Faults OQ103B OQ104B OQ106B OQ106C OQ107C OQ57E OQ59E OQ83B OQ84B OQ86B OQ93B OQ94B OQ96B OQ97C OR108C OR62C OR66C OR74C OR98C SQ103BE SQ103CB SQ103CE SQ104BE SQ104CB SQ104CE SQ105CB SQ105CE SQ106CB SQ107CE SQ12CE SQ16CB SQ17CB SQ22CE SQ42CE SQ56CB SQ81CB SQ82CB SQ83BE SQ83CE SQ84BE SQ84CE SQ85CB SQ85CE SQ86CB SQ87CE SQ91CB SQ92CB SQ93BE SQ93CB SQ93CE SQ94BE SQ94CB SQ94CE SQ95CB SQ95CE SQ96CB SQ97CE SR61RaRb SR73RaRb SR74RaRb SR75RaRb SR76RaRb SR77RaRb SR78RaRb SR79RaRb SR80RaRb idd faults OQ101C OQ101E OQ102C OQ102E OQ103C OQ103E OQ104C OQ104E OQ105C OQ105E OQ106C OQ106E OQ107C OQ107E OQ10C OQ10E OQ11C OQ11E OQ12C OQ12E OQ16C OQ16E OQ17C OQ17E OQ18C OQ18E OQ19C OQ19E OQ20C OQ20E OQ21C OQ21E OQ22C OQ22E OQ26E OQ27E OQ28E OQ29E OQ30C OQ30E OQ31C OQ31E OQ32C OQ32E OQ36C OQ36E OQ37C OQ37E OQ38C OQ38E OQ39C OQ39E OQ40C OQ40E OQ41C OQ41E OQ42C OQ42E OQ46E OQ47E OQ48E OQ49E OQ50C OQ50E OQ51C OQ51E OQ52C OQ52E OQ56B OQ56C OQ56E OQ57B OQ57C OQ58B OQ58C OQ58E OQ59B OQ59C OQ6C OQ6E OQ7C OQ7E OQ81C OQ81E OQ82C OQ82E OQ83C OQ83E OQ84C OQ84E OQ85C OQ85E OQ86C OQ86E OQ87C OQ87E OQ8C OQ8E OQ91C OQ91E OQ92C OQ92E OQ93C OQ93E OQ94C OQ94E OQ95C OQ95E OQ96C OQ96E OQ97C OQ97E OQ9C OQ9E OR100C OR109C OR110C OR14C OR15C OR44C OR45C OR63C OR64C OR65C OR67C OR75C OR77C OR78C OR89C OR90C OR99C SQ107BE SQ107CB SQ107CE SQ12CB SQ22CB SQ32CB SQ42CB SQ52CB SQ56BE SQ56CE SQ57BE SQ57CB SQ57CE SQ58CB SQ58CE SQ87BE SQ87CB SQ87CE SQ97BE SQ97CB SQ97CE SR108RaRb S R B R a R b SR23RaRb SR33RaRb SR43RaRb SR53RaRb SR61RaRb SR62RaRb SR63RaRb SR64RaRb SR65RaRb SR66RaRb SR88RaRb SR98RaRb Figure B.2 Fault Characterization of the 1:2 SIPO Circuit. 88 Appendix C Fault Insertion Perl Script - fault_sim.pl This Perl script was reproduced here with permission of Dr. Andrew Bishop, who is the original author of this script. #!/usr/public/bin/sun4/perl ###################################################################### AFS.pl (Analog F a u l t Simulator) P e r l s c r i p t f i l e to take s p i c e decks and i n j e c t f a u l t s i n t o the c i r c u i t and then c o l l a t e the data from simulations. F a u l t L i s t : open f a u l t s , short f a u l t s , f l o a t i n g gate f a u l t s and layout dependant f a u l t s ###################################################################### Method: input s p i c e n e t l i s t of c i r c u i t with t e s t bench t h i s program w i l l generate a l i s t of a l l p o s s i b l e s i n g l e f a u l t s i n the c i r c u i t , i n s e r t s each f a u l t , one at a time and then simulate the t e s t bench f o r each f a u l t case Simulations are performed i n p a r a l l e l on each of the hosts l i s t e d i n array ©hosts A l l output f i l e s w i l l return, automatically to $ return_dir on l o c a l machine ###################################################################### NOTES: the output (a p i l e of spice decks) w i l l be placed i n a d i r e c t o r y c a l l e d $outdir. i f dc convergence f a i l u r e , w i l l resubmit simulation with increase GMAX index, (see run.pl) Copyright: A Bishop, 1996 ###################################################################### $OPEN = 1; $ SHORT = 0; $LAYOUT = 0; ###################################################################### # # # I n i t i a l i z e some v a r i a b l e s # # # ###################################################################### $ i n f i l e $, $1 $outdirO $outdirS $outdirH $outdirF @node_list % m a c r o _ l i s t % e l e m _ v a l _ l i s t %elem_node_list # ©hosts = @ARGV[0] ; = 1; # input s p i c e n e t l i s t w/ t e s t bench # output f e i l d separator # output autoflush # OPEN FAULTS # SHORT FAULTS # LAYOUT DEPENDANT FAULTS # FLOATING GATE FAULTS # array f o r l i s t of nodes # array f o r l i s t of macros # array with l i s t of element values ('fridge', 'oven' ' l a r r y ' ' blender' 89 # @hosts = ( 'b lender %host = $host index = @faul t_ type = GconnectionM = @connectionMO = SconnectionCO = SconnectionC = @connectionRO = ©connectionLO = @connectionL = SconnectionR = (^connection!. = @connectionV = @connectionVO = @connectionIO = SconnectionFG = ©connectionQ = $num_nodes = 0; ' f r i c k ' , ' f r a c k ' , ' h a r r y ' ) ; ) ; ) ; ' s s ' , ' d d ' ,'0' ) ; ' D ' , ' G ' , ' S ' , ' s u b ' ) ; ' D' , ' G' , ' S' ) ; 'Ca ' ) ; ' C a ' , ' C b ' ) ; 'Ra ' ) ; ' L a ' ) ; ' L a ' , ' L b ' ) ; ' R a ' , ' R b ' ) ; ' i f a ' , ' i f b ' ) ; ' v f a ' , ' v f b ' ) ; ' v f a ' ) ; ' i f a ' ) ; ' G' ) ; ' C , ' B ' , ' E ' ) ; # some f i lenames w i t h paths = ' ~ a n d r e w b / b i n / p e r l / r u n . p l # $runspice $runspice $rsh $rcp $cp = ' / u s r / u c b / r s h ' ; = ' / u s r / u c b / r c p ' ; = ' / b i n / c p ' ; ###################################################################### # # # Get l o c a l hostname # # # ###################################################################### system " /b in /hostname > / tmp/ tmp$$" ; open( TMP, "/ tmp/tmp$$ ") ,-w h i l e (<TMP>) { chop ; Stmp = s p l i t ( / \ . / ) ; $ loca l_hos t = $tmp[0]; @tmp = ( ) ; } close(TMP); system " / b i n / r m / tmp/ tmp$$" ; ###################################################################### # # # Check t h a t l o c a l machine has / t m p / a j b d i r e c t o r y to pu t da ta i n # # i f i t doesnt e x i s t , make i t # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # . # # # # # unless (-d ' / t m p / a j b ' ) { system " / b i n / m k d i r / t m p / a j b " ; } ###################################################################### # Subrout ines # # # ###################################################################### sub ADD_ELEM { # Add element t o g l o b a l l i s t s o f elements, 90 # nodes, and va lues , r e s p e c t i v e l y # # $elem_name: i s the name of the element, may be a conca tena t ion # o f the element name w i t h the macro i n which i t # appears # $elem_val : i s the va lue o f the element, e . g . I k Ohms # $elem_nodes: are a l i s t o f the node names connected t o the element local($elem_name, $elem_val, $elem_nodes) = ©_,-$elem_val_l is t {$elem_name}=$elem_val ; $ e1em_node_li s t{$e1em_name} = $ e1em_nodes; r e t u r n ; } sub ADD_MACRO { # Add macro t o g l o b a l l i s t # o f macros w i t h num connect ions t o macro # # $subckt_name: i s the name of the macro or subckt element # $node_names: i s a l i s t o f a l l the connect ing nodes t o macro # $num_macro_nodes: i s the i n t e g e r number of e x t e r n a l nodes # connect ions w i t h macro l o c a l ($subckt_name, $node_names, $nunL_macro_nodes) = @_; $macro_l ist{$subckt_name} = $node_names; # no te the p l u s one f o r l a t e r use $macro_nodes_list{$subckt_name} = $num_macro_nodes + 1; r e t u r n ; sub COMPILE { # Do a l l t he s t u f f f o r each element encountered local($num_nodes, $ l i n e , $subckt_type) = @_; l o c a l Swords = s p l i t ( / \ s + / , $ l i n e ) ; i f ($subckt_type eq ' ' ) { l o c a l $elem_name = $words[0]; ) e l s e { l o c a l $elem_name = $ s u b c k t _ t y p e . ' . ' . $ w o r d s[0]; } l o c a l $elem_nodes = () ,-l o c a l $elem_val = () ; l o c a l ©val = ( ) ; l o c a l ©nodes = ( ) ; # loop from 1 t o nura_nodes words o f the # i n p u t l i n e and c o l l a t e them i n a l i s t of # node names connected to the element f o r ( $ i = 1; $ i < $num_nodes; $i++) { $ n o d e s [ $ i - l ] = $ w o r d s [ $ i ] ; } $elem_nodes = j o i n ( ' ' , ©nodes),-# loop through the remain ing words i n the i n p u t # l i n e and s t o r e as the element v a l u e . f o r ( $ i = $num_nodes; $ i < $#words+l; $i++) { $val [$i-$num_nodes] = $ w o r d s [ $ i ] ; } 91 $elem_val = j o i n ( ' ' , @val) ; # a) add the new element t o the g l o b a l l i s t of elements # b) add the l i s t o f nodes connected t o the new element # to the g l o b a l node a r r a y , indexed by new element # c) add new element va lue to a r r a y o f element va lues # index by new element do ADD_ELEM($elem_name, $elem_val, $elem_nodes); # a t tempt to make a l i s t o f subckt node names # # f o r ( $ i = l ; $ i < $num_nodes; $i++) { # i f (def ined($macro_type)) { # $NEW_NODE=$macro_type.' . ' .$tmp[$i]; # } # e l s e { # $NEW_NODE= $ tmp[$ i ] ; # ) # } r e t u r n ; sub CHECKELEM { # f i g u r e out what type o f c i r c u i t element i s i n p u t # a) s t o r e element name i n a s o c i a t i v e a r r a y of elements # b) pass on the number o f nodes connected to element l o c a l ( $ l i n e , $subckt_type) = @_; l o c a l Swords = s p l i t ( / \ s + / , $ l i n e ) ; i f < / A W ) { # sp ice c o n t r o l command, do n o t h i n g } e l s i f ( / ~ W ) { # sp ice comment, do n o t h i n g } e l s i f ( / ' \ + / l { # sp ice l i n e c o n t i n u a t i o n , do n o t h i n g } e l s i f ( / " R / i ) { # r e s i s t o r do COMPILE(3, } e l s i f ( /~M/ i ) { # mosfet do COMPILE(5, } e l s i f ( /~C/ i ) { # c a p a c i t o r do COMPILE(3, } e l s i f < / "D / i ) { # d iode do COMPILE(3, } e l s i f ( / " Q / i ) { # b j t 92 $ l i n e , $subck t_ type) ; $ l i n e , $subck t_ type) ; $ l i n e , $subck t_ type) ; $ l i n e , $subck t_ type) ; do COMPILE(5, $ l i n e , $subck t_ type) ; } e l s i f ( / " L / i ) { # i n d u c t o r do COMPILE(3, $ l i n e , $subck t_ type) ; } e l s i f ( /~X / i ) { # subckt # f i n d subckt name from l i s t # i d e n t i f y the number of nodes f o r subckt f o r ( $ i = 1; $ i < $#words+l; $i++) { # take subckt name as l a s t word t h a t does no t # ass ign a parameter va lue un less ($words[$ i ] =~ / ( . * ) \ = ( . * ) / ) { $subckt_name = $ w o r d s [ $ i ] ; } > $num_subckt_nodes=$macro_nodes_list{$subckt_name}; do COMPILE($num_subckt_nodes, $ l i n e , $subck t_ type) ; } } sub FORK { # f o r k a c h i l d process loca l ($ tmp) = @_; i f ($p id = f o r k ) { # dont want t o do any th ing } e l s i f (de f ined $pid) { # t h i s i s c h i l d process exec $ tmp; } sub SEND_SIM { # p i c k one of $hosts and send the sp ice j o b the re f o r p rocess ing l o c a l ( $ o u t f i l e ) = @_; i f ($host index > $#hosts) { # s imple way t o r o t a t e th rough a l l hosts $host index = 0; } # remote copy f i l e to $ h o s t s [ $ h o s t s i n d e x ] : / t m p / $ o u t f i l e # and l i s t f i lename i n a s s o c i a t i v e a r r a y e n t r y f o r hostname i f ($hos ts [$hos t index ] eq $ loca l_hos t ) { system $ c p . $ o u t f i l e . " / t m p / " . $ o u t f i l e ; $hos t {$hos ts [$hos t i ndex ] } = j o i n ( ' ' , $ h o s t ( $ h o s t s [ $ h o s t i n d e x ] } , $ o u t f i l e ) ) e lse { system $rcp. $out f i l e . " 11 . $hosts [$host index] . " : / tmp/ " . $out f i l $hos t {$hos ts [$hos t i ndex ] } = j o i n ( ' ' , $ h o s t { $ h o s t s [ $ h o s t i n d e x ] } , $ o u t f i l e ) } 93 $tmp = ( ) ; $hostindex++; sub PROCESSLIBFILE { # the model l i b r a r y f i l e $ l i b f i l e # the model l i b r a r y name $libname # s i n c e l i b r a r y may not e x i s t on remote machines # must copy i t to remote l o c a t i o n s a long wi th f i l e s . # s t o r e new l i b r a r y i n ( g l o b a l l y defined) $ s i m u l a t i o n _ l i b _ f i l e # ALSO # open the o r i g i n a l l i b r a r y f i l e and scan though i t f o r f l o a t i n g # gate model parameters # the parameters for $libname, # i . e . , TYPICAL, WORST, e t c . , must be used # f o r the f l o a t i n g gate model my ( $ l i b n a m e , $ l i b f i l e , $ p a r e n t l i b ) = @_; my $ l i b _ i n d e x = 0; my ($defined_lib_name, $ d e f i n e d _ p a r e n t l i b , $ l ib_ index , @sub_l ib ) ; open (LIBFILE, " < $ l i b f i l e " ) ; open (LIBNAMEFILE, " » $ s i m u l a t i o n _ l i b _ f i l e " ) ; whi le (<LIBFILE>) { i f ( / ~ \ . L I B $ l ibname/ i ) { # s t o r e the parameters d e f i n e d for t h i s # l i b r a r y i n LIBNAMEFILE $defined_lib_name = 1; } i f ( /" \ .ENDL $ l ibname/ i ) { $defined_lib_name = 0; p r i n t LIBNAMEFILE $_; c l o s e ( L I B F I L E ) ; c l o s e (LIBNAMEFILE) ,-} i f { / " \ . L I B \ ' $ l i b f i l e \ ' $ p a r e n t l i b / i | / ~ \ . L I B \ " $ l i b f i l e \ " $ p a r e n t l i b / i ) { $ d e f i n e d _ p a r e n t l i b = 1; } i f ( /" \ .ENDL $ p a r e n t l i b / i ) { $de f ined_parent l ib = 0; } i f ($defined_lib_name) { i f ($def ined_parent l ib) { } e l s e { i f ( / ' \ . l i b V ( . * ) V ( . * ) / i | / ' \ . l i b \ " (.*)\" ( . * ) / i ) { # sub l i b r a r y f i l e de f ined w i t h i n # l i b r a r y , p l a c e $ s u b _ l i b _ f i l e i n a l i s t # of l i b f i l e s to process and cont inue $ s u b _ l i b _ f i l e = $1; $sub_lib_name = $2,-$sub_l ib_parent = $libname; $lib_index++; $ sub_ l ib [$ l ib_ index ] = $ s u b _ l i b _ n a m e . " : • . $ s u b _ l i b _ f i l e . " : " . $ s u b _ l i b _ p a r e n t ; $de f ined_sub_f i l e = 1; p r i n t LIBNAMEFILE 94 " . l i b \ ' $ s i m u l a t i o n _ l i b _ f i l e \ ' $sub_lib_name\ } e l s e { p r i n t LIBNAMEFILE $_; } } # NOW scan through the l i b r a r y f i l e to p u l l out # the parameters f o r the f l o a t i n g gate f a u l t model. # For each t r a n s i s t o r : # - v t o = t h r e s h o l d v o l t a g e # - co = gate capaci tance per u n i t area # - uo = e f f e c t i v e m o b i l i t y # The names f o r each of these parameters # v a r i e s , depending on the l e v e l , # f o r l e v e l 1 , 2, 3, 4 SCHICHMAN-HODGES, # GROVE-FROHMAN, EMPIRICAL # o r l e v e l 5, 6, 7, 8 ASPEC, MSINC, ISPICE, # ENHANCED LEVEL 2 # COX, o r EOX/(TOX*le-10) = co # UO, UB or UBO = uo # VTO, o r VT = v t o # f o r l e v e l 13, 28 BSIM, MODIFIED BSIM # MUZ = uo # WX2M = v t o # EOX/(TOXM*le-10) = co # ALSO, t o account f o r semi -sca lab le dev ice l i b r a r i e s # parameters may va ry depending on the s i ze of # the t r a n s i s t o r # (sca lab le and semi -sca lab le dev ice l i b r a r i e s ) # so f o r each .model modelnamex xmos statement # t h e r e w i l l be l m i n , lmax, wmin, and wmax parameters # when mosfet i s encountered i n n e t l i s t # i . e . Mxxxx d r a i n gate source sub modelnamex 1=11 w=wl # must f i n d the a p p r o p r i a t e model such t h a t : # lm in < 11 < lmax # AND # wmin < w l < wmax # and use the parameters f o r t h a t modelnamex i n # f l o a t i n g gate model. # ALSO, the parameters w i l l change f o r the process # corners # (TYPICAL, BEST, WORST, TT, SS, FF, SF, FS) @ l i n e = s p l i t ; i f ( / " \ . m o d e l / i ) { $modelname = $ l i n e [ l ] ; $scaled_modelname=Smodelname; i f ( Smodelname =~ / ( . * ) \ . ( . * ) / ) { # i f t h i s i s a sca lab le model l i b r a r y # then the model parameters depend # on the s i z e o f the t r a n s i s t o r : L, and W. # Index the sca led model parameters # by a mapping f u n c t i o n f rom unsealed # $modelname ( i . e . nch) t o $scaled_modelname # ( i . e . nch.2) based on t r a n s i s t o r dimensions Utmpmodelname = s p l i t ( / \ . / , Smodelname); Smodelname = Stmpmodelname [0] ,-} } 95 i f ( / T O X M \ s * = \ s * ( . * ) / i ) { $ t o x = $ l ; i f ( $tox =~ / \ d + ? / ) { $cox{"$scaled_modelname"} = $ e o x / ( $ t o x * l e - 1 0 ) ; } e l s e { $eox=0.00001; $cox{"$scaled_modelnarae"} = ' ( ' . $ e o x . ' / ( ' . S t o x . ' * l e - 1 0 ) ) ' } i f ( / COX \ s * = \ s * ( . * ) / i ) { $cox{"$scaled_modelname"} = $ 1 ; i f ( / [U0 |UB|UBO] \s*= \s* ( . . ) \ s * ( . * ) / i ) { $uo{"$scaled_modelname"} = $ 1 ; i f ( / MUZ \ s * = \ s * ( . * ) / i ) { $uo{"$scaled_modelname"} = $ 1 ; i f ( / [ V T | V T O ] \ S * = \ S * ( . . ) \ s * ( . * ) / i ) { $vt{"$scaled_modelname"} = $ 1 ; i f ( / VFBO \ s * = \ s * ( ) { $vt{"$scaled_modelname"} = $ 1 ; i f ( / WMAX \ s * = \ s * ( . * ) / i ) { $wmax=$l; i f ( / WMIN \ s * = \ s * ( . * ) / i ) { $wmin = $ 1 ; i f ( / LMAX \ s * = \ s * ( ) { $lmax = $ 1 ; i f ( / LMIN \ s * = \ s * ( . * ) / i ) { $ lmin = $ 1 ; chop($ lm in ) ; chop($ lm in ) ; } $lmin_max{"$scaled_modelname"} = " ( $ l m i n : $ l m a x ) " ; $wmin_max{"$scaled_modelname"} = "($wmin:$wmax)"; } } p r i n t "LMINMAX=", %lmin_max," \ n " ; p r i n t "WMINMAX=", %wmin_max," \ n " ; i f ($de f ined_sub_ f i l e ) { my ( $ i ) ; f o r ( $ i = 1 ; $ i < $#sub_l ib + 1 ; $i++) { ($l ibname, $ l i b f i l e , $ l i b p a r e n t ) = s p l i t { A : / , $ s u b _ l i b [ $ i ] ) ; PROCESSLIBFILE($ l ibname,$ l ib f i le ,S l ibparen t ) ; } } $ s i m u l a t i o n _ l i b _ f i l e ; 96 ###################################################################### # # # MAIN LOOP # # # ###################################################################### open(IN, " $ i n f i l e " ) | | d i e "No such f i l e as $ i n f i l e ; $ ! \ n " ; open(NETLIST, " > p l . n e t " ) ; wh i le (< IN>) { # scan through once and i d e n t i f y a l l subckt macro and # s p e c i a l f l agged cases # p lace a copy o f n e t l i s t i n f i l e p l . n e t chop; # remove newl ine ©words = s p l i t ; # s p l i t i n p u t l i n e i n t o words i f ( /~ \ * / ) { # sp ice comment # OR # f l a g f o r l a y o u t dependant f a u l t p r i n t NETLIST $ _ , " \ n " ; # copy l i n e i n t o NETLIST un less ( /CRX/ ) { # t h i s i s my f l a g # check f o r ad jacent nodes and c ross ing w i res (t i n s e r t e d i n the node l i s t @tmp2 = ( ) ; @tmp2 = @words; $th isnode = $ t m p 2 [ l ] ; $ i = 3; # i = index o f element j u s t a f t e r the * ! separa tor # ge t l i s t o f nodes t h a t cou ld be shor ted # and s t o r e them f o r l a t e r p rocess ing $ # t m p l i s t = 0; w h i l e ( $ i <= $#tmp2) { i f ($ tmp2[$ i ] =~ /CRX/) { $ c r o s s l i s t { $ t h i s n o d e } = j o i n ( ' ' , S t m p l i s t ) ; } c h o p ( $ t m p 2 [ $ i ] ) ; # s t u f f the l i s t i n t o an a r r a y $ t m p l i s t [ $ i - 3 ] = $tmp2[$i ] , -$ i++ ; } } } i f ( / ~ \ . s u b c k t / i | / " . m a c r o / i ) { # i d e n t i f y each subckt b lock # c o l l e c t the number o f nodes f o r the subckt # i n a g l o b a l l i s t p r i n t NETLIST $ _ , " \ n " ; # copy l i n e i n t o NETLIST $subckt_type = $ w o r d s [ l ] ; $subckt_nodes = ( ) ; $ j = 0; 97 f o r ( $ i = 2 ; $ i < $#words + 1 ; $i++) { un less ( $words[$ i ] = " / ( . * ) = ( . * ) / ) { $subckt_nodes[$ i -2 ] = $ w o r d s [ $ i ] ; $ j++ ; } } do ADD_MACRO($subckt_type, j o i n ( ' ' , 9subckt_nodes) , $ j ) ; # sk ip th rough the subckt t i l l .ends or .eom # adding the elements of subckt as $subckt_type # elements do { $_ = <IN>; p r i n t NETLIST $_; chop ; CHECKELEM($_,$subckt_type); } u n t i l ( / \ . e n d s / i | / \ . e o m / i ) ; $subckt_type = () ,-} i f ( / " \ . m o d e l / i ) { # sp ice model l i b r a r y # do n o t h i n g YET # l a t e r on, w i l l use t h i s t o scan through t o # ge t model parameters f o r p a r a m e t r i z i n g f l o a t i n g gate # f a u l t mode l . . p r i n t NETLIST $ _ , " \ n " ; # copy l i n e i n t o NETLIST } i f ( / " \ . l i b V ( . * ) V ( . * ) / i | / " . l i b \ " ( . * ) \ " ( . * ) / i ) { $ l ibrary_name = $2; $ l i b r a r y _ f i l e = $ 1 ; $ s i m u l a t i o n _ l i b _ f i l e = $1 ibrary_name.$1 ibrary_ f i l e ; # ge t r i d o f any e x i s t i n g s i m u l a t i o n l i b r a r y f i l e system " / b i n / r m $ s i m u l a t i o n _ l i b _ f i l e " ,-$ s i m u l a t i o n _ l i b = PROCESSLIBFILE($library_name, $ l i b r a r y _ f i l e , "XXX" p r i n t NETLIST " . l i b \ ' $ s i m u l a t i o n _ l i b _ f i l e \ ' $ l ibrary_name \ n " ; } i f ( / " \ + / ) { # l i n e c o n t i n u a t i o n # do n o t h i n g p r i n t NETLIST $ _ , " \ n " ; # copy l i n e i n t o NETLIST } e lse { p r i n t NETLIST $ _ , " \ n " ; # copy l i n e i n t o NETLIST } close(NETLIST); open(IN, " $ i n f i l e " ) ; $subckt_def ined = 0; w h i l e ( < I N > ) { chop ; Swords = s p l i t ; un less ( / " \ * / | / ~ \ + / ) { 98 i f ( / " \ . s u b c k t / i | / " \ . m o d e l / i ) { # w i t h i n a subckt the elemnts have been # r e g i s t e r e d e a r l i e r , so dont do them aga in ! $subckt_def ined = 1 ; } e l s i f ( / " \ . e n d s / i | / ~ \ . e o m / i ) { # end o f model # end o f subckt $subckt_def ined = 0; } unless ($subckt_def ined) { do CHECKELEM($_, ' ' ) ; } } } c l o s e ( I N ) ; # now s o r t th rough cross node l i s t t o remove redundancies. # i . e . f o r each node i n each c r o s s l i s t f o r key # i f t h a t node has a c r o s s l i s t of i t s own # check t h a t i t s l i s t does no t c o n t a i n the o r i g i n a l key fo reach $key (keys % c r o s s l i s t ) { @ t m p l i s t = s p l i t ( ' ' , $ c r o s s l i s t { $ k e y } ) ; fo reach $node (Utmp l i s t ) ( i f ( $ c r o s s l i s t { $ n o d e ) ) { S n e x t t m p l i s t = s p l i t ! ' ' , $ c r o s s l i s t { $ n o d e } ) ; $ i = 0; Snewnex t l i s t = ( ) ; fo reach $nextnode (Snex t tmp l i s t ) { un less ($nextnode eq $key) { $ n e w n e x t l i s t [ $ i ] = $nextnode; $ i + + ; } } $ c r o s s l i s t ( $ n o d e ) = j o i n ( ' ' , Snewnext l i s t ) ; } } } ###################################################################### # # # Now i n s e r t f a u l t cases by genera t i ng a separate f i l e f o r each # # f a u l t case and s imu la te the f a u l t case w i t h hsp i ce . # # Note: each hsp ice s i m u l a t i o n i s run on a d i f f e r e n t $host computer # # t o speed t h i n g s up # # # ###################################################################### ###################################################################### # # # Open f a u l t s # # # ###################################################################### i f ($OPEN) { fo reach $elem (keys %elem_val_ l is t ) { i f ($elem =~ / ( . * ) \ . ( . * ) / ) { 99 # eg X I . M l # t h i s i s a subckt element # must handle i t sepa ra te l y # c rea te a s e r i e s o f f a u l t s i m u l a t i o n s f o r each # p o s s i b l e f a u l t case w i t h i n subck t . e l se { $ f lag_gate = 0; @nodes_to_test = s p l i t ( ' ' , $e lem_node_ l i s t {$e lem}) ; i f ($elem =~ / C ( . * ) / i ) { ©connection = ©connectionCO; } i f ($elem =~ / L ( . * ) / i ) { ©connection = ©connectionLO; } e l s i f ($elem =~ / R ( . * ) / i ) { ©connection = ©connectionRO; } e l s i f ($elem =~ / Q ( . * ) / i ) { ^connect ion = ©connectionQ; } e l s i f ($elem =~ / M ( . * ) / i ) { ©connection = ©connectionMO; } e l s i f ($elem =~ / l ( . * ) / i ) { ©connection = ©connect ionIO; } e l s i f ($elem =~ / V ( . * ) / i ) { ©connection = ©connectionVO; } e l s i f ($elem =~ / X ( . * ) / i ) { # f i n d the subckt from g l o b a l l i s t # f i n d out how many nodes are supposed to be # connected to t h i s type o f subckt # and generate an a r r a y w i t h t h a t many e n t r i e s ©connection = s p l i t ) / / , $ m a c r o _ l i s t { $ e l e m _ v a l _ l i s t { $ e l e m } } ) ; @nodes_to_test = ( s p l i t ) / / , $ m a c r o _ l i s t { $ e l e m _ v a l _ l i s t { $ e l e m } } ) , 'dummy') $b = 0; w h i l e ($b < $#nodes_to_test) { $subckt_def ined=0; $ o u t f i l e = ' O ' . $ e l e m . $ c o n n e c t i o n [ $ b ] . ' . s p ' ; open(NETLIST, " < p l . n e t " ) ; open(OUT, " > $ o u t f i l e " ) ; while(<NETLIST>) { chop ; ©words = s p l i t ; i f ( / * \ . s u b c k t / i | / * \ . m a c r c o / i ) { 100 # any c i r c u i t elements t h a t appear # w i t h i n the subckt d e f i n i t i o n are # separate from those of the # r e s t o f the c i r c u i t $subckt_def ined = 1 ; i f ( / ~ \ . e n d s / i | / " \ . e o m / i ) { $subckt_def ined = 0; } i f ($words[0] eq $elem && !$subck t_def ined ) { # I n s e r t open f a u l t on each node ($b) # o f elem, by p l a c i n g s e r i e s IM # r e s i s t o r be fo re node, except f o r # open gates which are t r e a t e d s e p a r a t e l y # depending on type of a n a l y s i s # f o r TRAN: # a smal l c a p a c i t o r i n s e r i e s w i t h the gate # and an i n i t i a l c o n d i t i o n ; # f o r DC: # s p e c i a l f l o a t i n g gate model. $elem_val = $ e l e m _ v a l _ l i s t { $ e l e m ) ; Selem_nodes = s p l i t ( ' ' , $e lem_node_ l i s t {$e lem}) ; $new_node = $elem_nodes [$b] . ' f a u l t ' ,-i f ($elem =~ / M ( . * ) / i && $connect ion[$b] =~ / G / i ) { # use f l o a t i n g gate model 9 s t u f f = s p l i t ( / / , $e lem_val ) ; $ m o d e l = $ s t u f f [ 0 ] ; i f ( $ s t u f f [ 1 ] =~ / L = ( . . ) / i ) { $ leng th = $ 1 ; } i f ( S s t u f f [ 2 ] =~ / W = ( . . ) / i ) { $width = $ 1 ; } # i f the l i b r a r y f i l e i s a semiscalable # or sca lab le l i b r a r y , then must f i n d # the c o r r e c t model based on l e n g t h # and w i d t h d e f i n e d here . p r i n t OUT "CO$elem_nodes[$b] ", $new_node, $elem_nodes[$b], " \ ' $ c o x { $ m o d e l } * $ l e n g t h * $ w i d t h \ ' \ n " ; p r i n t OUT ".param Vcharge=0\n" ; p r i n t OUT " . I C V($new_node)=Vcharge\n"; $elem_nodes[$b] = $new_node; $dra in [0 ]=$e lem_nodes[0 ] ; $elem_nodes[0] = $ d r a i n [ 0 ] . ' A' ; p r i n t OUT $elem, @elem_nodes, $elem_val, " \ n " , p r i n t OUT "Vsense$elem $ d r a i n [ 0 ] " , " $elem_nodes[0] DC 0 \ n " ; p r i n t OUT "R$elem $ d r a i n [ 0 ] $elem_nodes[0]B", " 100E6\n" ,-p r i n t OUT ".param pn0$elem=0\n"; p r i n t OUT ".param a n 0 $ e l e m = p a r ( \ ' - q g a t e / • , "$cox {$mode l } /$ leng th /$w id th " , • - $ v t { $ m o d e l } \ ' ) \ n " ; p r i n t OUT ".param p n l $ e l e m = p a r ( \ ' q g a t e * q g a t e * ' 101 "$uo{$model}/$cox{$model}" , "/$length/$length/$length/", •$width\')\n"; p r i n t OUT ".param anl$elem=par(\'pnl$elem*$length*" "$length/2/qgate/$uo{$model}", "+anO$elem\')\n"; p r i n t OUT"param ani$elem=par(\'-qgate/$cox{$model}" "/$length/$width+anO$elem\')\n"; p r i n t OUT ".param pn2$elem=par(\'2*qgate*qgate*", "$uo{$model}/$cox{$model}/", "$length/$length/$length/", "SwidthV)\n"; p r i n t OUT ".param an2$elem=par(\'ani$elem+sqrt(", "pn2$elem*2*$length/", "$cox{$model}/$uo{$model}/", "$width)\')\n"; p r i n t OUT ".param pn3$elem=par(\'pn2$elem*3\')\n"; p r i n t OUT ".param an3$elem=par(\'ani$elem+sqrt(", "pn3$elem*2*$length/", "$cox{$model}/$uo{$model}/", "$width)\')\n"; p r i n t OUT ".param pn4$elem=par(\'pn3$elem*4\')\n"; p r i n t OUT ".param an4$elem=par(\'ani$elem+sqrt(", "pn4$elem*2*$length/", "$cox{$model}/$uo{$model}/ " , "$width) \ ' ) \n" ,-p r i n t OUT ".param pn5$elem=par ( \'pn4$elem*5\' ) \n",-p r i n t OUT ".param an5$elem=par(\'ani$elem+sqrt(", "pn5$elem*2*$length/", "$cox{Smodel}/$uo{$model)/", "$width)\')\n"; p r i n t OUT ".param pn6$elem=par(\'pn4$elem*10\')\n"; p r i n t OUT ".param an6$elem=par(\'ani$elem+sqrt(", "pn6$elem*2*$length/", "$cox{Smodel}/$uo{Smodel}/", "$width)\')\n"; p r i n t OUT "H$elem $elem_nodes[0]B $new_node", " CCVS PWL(l) Vsense$elem\n", "+ pnO$elem,anO$elem\n", "+ pnl$elem,anl$elem\n", "+ pn2$elem,an2$elem\n", "+ pn3$elem,an3$elem\n", "+ pn4$elem,an4$elem\n", "+ pn5$elem,an5$elem\n", "+ pn6$elem,an6$elem\n"; $b++; } e l s e { p r i n t OUT "Rfault ",$new_node, $elem_nodes[$b],' lMeg', "\n"; $elem_nodes[$b] = $new_node,-p r i n t OUT $elem, @elem_nodes, $elem_val, "\n"; $b++; } } e l s e { # Do nothing to t h i s l i n e , p r i n t OUT $_, "\n"; } close(NETLIST); close(OUT); &SEND_SIM($outfile); 102 system " / b i n / r m S o u t f i l e " ; } # w h i l e ($b < $#nodes_to_test) ) } } ###################################################################### # # # Short f a u l t s next i f f l a g f o r shor ts # # ###################################################################### i f ($SHORT) { @node_pairs=() ; $num_node_pairs=0; fo reach $elem (keys %elem_val_ l is t ) { i f ($elem = ~ / ( . * ) \ . ( . * ) / ) { # eg X I . M l # t h i s i s a subckt element # must handle i t separa te l y # c rea te a s e r i e s o f f a u l t s imu la t i ons f o r each # p o s s i b l e f a u l t case w i t h i n subck t . # Except f o r those cases which are a l l r e a d y # covered, i . e . opens and sho r t s on the # e x t e r n a l connect ions } e lse { i f ($elem =~ / X ( . * ) / i ) { # f i n d the subckt from g l o b a l l i s t # f i n d out how many nodes are supposed t o be # connected t o t h i s type o f subckt # and generate an a r r a y w i t h t h a t many e n t r i e s @elem_nodes = s p l i t ( / / , $ m a c r o _ l i s t { $ e l e m _ v a l _ l i s t { $ e l e m ) } ) ; ) e lse { 9elem_nodes = s p l i t ( / / , $e lem_node_ l i s t {$e lem)) ; } # Create a l i s t o f @node_pairs t o s imu la te s h o r t f a u l t s # on by t r y i n g a l l p o s s i b l e combinat ions of node p a i r s f o r $elem. # A lso , check i f node p a i r i s a l ready i n l i s t o f # s t o r e d @node_pairs, i f no t s imula te s h o r t f a u l t # f o r t h a t p a i r o f nodes. f o r ( $ i = 0; $ i < $#elem_nodes + 1 ; $i++ ) { # f i r s t run th rough the l i s t t o s o r t out # i d e n t i c a l nodes connected t o $elem $ f i r s t _ n o d e = $elem_nodes[$ i ] ; f o r ( $ j = $ i + 1 ; $ j < $#elem_nodes + 1 ; $j++ ) { $second_node = $elem_nodes[$ j ] ; $done=0; un less ( $ f i r s t _ n o d e eq $second_node) { # i f the nodes are the same then dont s imu la te s h o r t 103 f o r ($k = 0; $k < $num_node_pairs; $k++) { # scan through node p a i r l i s t t o see i f the # node p a i r has been covered elsewhere @two_nodes = s p l i t ( / / , $ n o d e _ p a i r s [ $ k ] ) ; i f ( ( ($two_nodes[0] eq $ f i r s t _ n o d e ) && ($two_nodes[1] eq $second_node) ) I ( ($two_nodes[1] eq $ f i r s t _ n o d e ) && ($two_nodes[0] eq $second_node) ) ) { # pu t up a f l a g to add the node p a i r to # l i s t o f node p a i r s t o run s i m u l a t i o n on $done=l; } } unless ($done) { $node_pairs[$num_node_pairs] = " $ f i r s t _ n o d e $second_node $elem" $num_node_pairs + + ; } fo reach $pa i r (@node_pairs) { @tmp = s p l i t ( / / , S p a i r ) ; $nodel = $tmp [0] ,-$node2 = $ tmp[1 ] ; $elem = $tmp[2],-i f ($elem =~ / X ( . * ) / i ) { @connection = s p l i t ! / / , $ m a c r o _ l i s t { $ e l e m _ v a l _ l i s t { $ e l e m ) } ) ; @elem_nodes = s p l i t ! / / , $ m a c r o _ l i s t { $ e l e m _ v a l _ l i s t { $ e l e m } } ) ; } e l s e { ©connection = s p l i t ! / / , $elem_node_l is t {$elem)) ; @elem_nodes = s p l i t ! / / , $e lem_node_l is t {$elem)) ; } $elem_val = $e lem_va l_ l i s t {$e lem) ; $ o u t f i l e = ' S ' . $ e l e m . $ n o d e l . $ n o d e 2 . ' . s p ' ; open(NETLIST, " p l . n e t " ) ; open(OUT, " > $ o u t f i l e " ) ,-while(<NETLIST>) { chop ,-Swords = s p l i t ; i f (Swords[0] eq $elem) { # I n s e r t s h o r t f a u l t between $nodel and $node2 of $elem, # by p l a c i n g shunt r e s i s t o r of 1 ohm between nodes p r i n t OUT "Rshort ", $nodel , $node2, ' 1 0 ' , " \ n " ; p r i n t OUT $elem, @elem_nodes, $elem_val, " \ n " ; e l se { # Do n o t h i n g t o t h i s l i n e , p r i n t OUT $_, " \ n " ; } 104 } close(NETLIST); c lose(OUT); &SEND_SIM($outf i le); system ° / b i n / r m $ o u t f i l e " ; } } # next t h i n g i s f l agged ad jacent nodes from l a y o u t # and, # l i n e s t h a t cross each o the r i n the l a y o u t # and pads # the f l a g w i l l be a sp ice comment a t the end of the l i n e # where the nodes are l i s t e d . # fo rmat : # * node l i s t # * vdd * ! 1 , 3, 4, CRX # * gnd * ! 0, 3, 4, CRX # * mid * ! 2, 3, 4, CRX # * m2s * ! 3 * ! 1 , 2, CRX # A # t h i s i s the f l a g f o r nodes t h a t may # be shor ted i n the l a y o u t due to # o v e r l y i n g meta l l i n e s # * m3s * ! 4 # NOTE i n bo th cases the re may be one or more nodes i n the CRX # l i s t , separated by commas ALSO the l a s t one needs a comma a f t e r # i t . These l i s t s are s o r t e d by node name i n the a s s o c i a t i v e a r r a y # c r o s s l i s t i f {$LAYOUT) { fo reach $node (keys % c r o s s l i s t ) { # rep lace every ins tance of $node w i t h each of i t s # c r o s s i n g nodes i n each occurance of $node per sim f i l e . @nodes = s p l i t ( ' ' , $ c r o s s l i s t { $ n o d e ) ) ; fo reach $nodetoreplace (©nodes) { $ o u t f i l e = $ o u t d i r H . ' / S h ' . $ n o d e . ' _ ' . $ n o d e t o r e p l a c e . ' . s p ' ; open(NETLIST, " p l . n e t " ) ; open(OUT, " > $ o u t f i l e " ) ; while(<NETLIST>) { chop ; i f (/CRX/) { # do n o t h i n g $newline = $_,-} e l s i f ( A s $ n o d e \ s / ) { ©words = s p l i t ; f o r ( $ i = 0; $ i <= $#words; $i++) { i f ($words[$ i ] eq $node) { $words[$ i ] = $nodetoreplace; } e l s e { # do n o t h i n g } $newline = j o i n ( ' ' , ©words); } 105 } e lse { $newline = $_,-} p r i n t OUT $ n e w l i n e , " \ n " ; } } } } # now run sp ice on a l l the s p i c e f i l e s f l o a t i n g about fo reach $HOST (keys %host") { i f ($HOST =~ $ loca l_hos t ) { $tmp = $runspice.$host{$HOST}. ' ' . $ r e t u r n d i r . ' ' . $ l o c a l _ h o s t ; do FORK($tmp); } e lse { $tmp = $rsh.$HOST.' ' . $ runsp ice .$hos t {$HOST} . ' ' . $ r e t u r n d i r . ' ' . $ l o c a l _ h o s t ; do FORK($tmp); } } i f (-e ' p l . n e t ' ) { system n / b i n / r m p l . n e t " ; } 106 Appendix D Fault Analyses Program fault_ch.pl This script is used for fault characteriztion of the circuits. The voltage at the primary outputs of the CUT is sampled several times during the simulation using HSPICE and the samples are stored in a <CUT_NAME.mtO> file. The measurement file <CUT_NAME.mtO> for the golden CUT and the faulty CUT are compared by this PERL script and depending on the measurements the faulty circuit is binned in one of the four fault categories : (1) functional, (2) like, (3) parametric or (4) hidden. # ! / u s r / p u b l i c / b i n / s u n 4 / p e r l # S o r i g = ( [ 3.0607, 3.0610, 3.2956, 3.2952, 3.0607, 3 .0611, 3 .2956] , [3.2955, 3.2952, 3.0607, 3 .0611, 3.29 $vddhh = 3 .3 ; $vddhl = 3.26; $vddlh = 3.09; $ v d d l l = 3.00; $va l = 0; $ l i n e = 0; Shidden = 0; $inf i le=@ARGV[$f i le_num]; $ , = ' ' ; $ | = 1 ; w h i l e ( < > ) { chop ; 0ak = $_; i f ($ak[0] =~ / \ $ / ) {chop;} e l s i f ($ak[0] =~ / \ . T I T L E / ) {chop;} e l s i f <$ak[0] =~ / \ v / ) {chop;} e l s i f ($ak[0] == 25.000000 ) {chop;} 107 e l s e { ©tmp = s p l i t ; push @l ine , [ ©tmp ] ; } } &process_hidden_faul t ; & p r o c e s s _ l i k e _ f a u l t ; &process_parametr i c_ fau l t s ; & p r o c e s s _ f u n c t i o n a l _ f a u l t s ; sub p r o c e s s _ l i k e _ f a u l t { # # Detect L i k e Fau l t s i n Data A # for $ i ( 0 . . $#line-3 ) { for $ j ( 0 . . $ # { $ l i n e [ $ i ] } ) { i f ( a b s ( $ l i n e [ $ i ] [ $ j ] - $ l i n e [ $ i + l ] [ $ j ] ) < 0 .04) { open ( TMP, ">LIKE_DETECT"); c l o s e (TMP); } } } # # Detec t L i ke F a u l t s i n Data B # f o r $ i ( $ # l i n e - l . . $ # l i n e - l ) { f o r $ j ( 0 . . $ # { $ l i n e [ $ i ] } ) { i f ( a b s ( $ l i n e [ $ i ] [ $ j ] - $ l i n e [ $ i + l ] [ $ j ] ) < 0 .04) { open ( TMP, ">LIKE_DETECT"); c l o s e (TMP); } } } } # End process l i k e f a u l t s sub process_hidden_faul t { Shidden = 0 ; # # Detect Hidden F a u l t s i n Data A # 1 0 8 f o r $ i ( 0 . . 3 ) { f o r $ j ( 0 . . 6 ) { $h id = a b s ( $ l i n e [ $ i ] [ $ j ] - $ o r i g [ $ i ] [ $ j ] ) .-p r i n t $h id , " \ n " ; i f ($h id < 0.030) { Shidden = $hidden + 1 ; } } } p r i n t $hidden, " \ n " ; i f (Shidden > 27) { open ( TMP, ">HIDDEN_DETECT"); c lose (TMP); } } sub p rocess_paramet r i c_ fau l t s { f o r $ i ( 0 , 2 ) { f o r $ j ( 0 . . 6 ) { $ p a r _ l i n e _ d i f = a b s ( $ l i n e [ $ i ] [ $ j ] - $ l i n e [ $ i + l ] [ $ j ] ) ; i f ( $ p a r _ l i n e _ d i f > 0.100) { open ( TMP, " >PARAMETRIC_DETECTM) ,-c lose (TMP); } } } } sub p r o c e s s _ f u n c t i o n a l _ f a u l t s { $ f a u l t = 0; f o r $ i ( 0 , 2 ) { f o r $ j ( 0 . . 6 ) { $ l i n e _ d i f = a b s ( $ l i n e [ $ i ] [ $ j ] - $ l i n e [ $ i + l ] [ $ j ] ) ; $ d i f f = a b s ( $ l i n e [ $ i ] [ $ j ] - $ o r i g [ $ i ] [ $ j ] ) ; $ d i f f _ 2 = a b s ( $ l i n e [ $ i + l ] [ $ j ] - $ o r i g [ $ i + l ] [ $ j ] ) ; i f ( ( $ l i n e _ d i f > 0.220) && (( $ d i f f > 0.220 ) | | ( $ d i f f _ 2 > 0.220 ) ) ) { $ f a u l t = $ f a u l t + 1 ; p r i n t a b s ( $ l i n e t $ i ] [ $ j ] - $ o r i g [ $ i ] [ $ j ] ) , " \ n " ; } 109 } } p r i n t "There were $ f a u l t f u n c t i o n a l f a u l t s \n"; i f ( $ f a u l t > 0 ) { open ( TMP, ">FUNCTIONAI_DETECT" ) ; cl o s e (TMP); } idd_test.pl This program takes in two riles for input. It takes in the idd measurements from HSPICE for the golden netlist and the measurements from a netlist with an open or short fault. It compares the faulty circuit output file and compares the two and writes out the file into a pass / fail data base. The upper and lower idd thresholds can be set by the user of the script. ©Vikram Devdas April 21, 1996 #!/usr/public/bin/sun4/perl #Set up the upper and lower l i m i t s f o r the i d d currents. $ i d d l = -2.7e-03; $iddh = -2.3e-03; $pass_0 = 0; $x = 0; $infile=@ARGV[$file_num]; $,=' '; $|=1; while(<>){ chop ; @bk = $_; @bk = s p l i t ; 110 i f <$bk[0] =~ / \ $ / ) { chop; } e l s i f ($bk[0] =~ / \ . T I T L E / ) { c h o p ; } e l s i f ($bk[0] =~ / \ v / ) { c h o p ; > e l s i f ($bk[0] == 25.000000 ) {chop;} e l s i f ( $ b k [ l ] == 2.5.000000 ) {chop;} e l s i f ($bk[2] == 25.000000 ) {chop;} e l s i f ($bk[3] == 25.000000 ) {chop;} e l s i f ($bk[4] == 25.000000 ) {chop; } e l s i f ($bk[5] == 25.000000 ) {chop;} e l se { i f ( $x == 0 ) { & tes t_compi le_ l ; p r i n t '$x has the va lue ' , $x, " \ n " ; } i f (($pass_0 = = 3 ) && ($pass_l = = 3 ) && ($pass_2 = = 3 ) && ($pass_3 == 3) && ($pass_4 = = 3 ) && ($pass_5 {open ( TMP, ">PASSED"); c lose (TMP); } e lse{open ( TMP2, ">FAILED"); c lose (TMP2);} } $ X + + ; } sub t e s t _ c o m p i l e _ l { p r i n t ' t e s t _ c o m p i l e _ l ' , @bk, " \ n " ; i f ($bk[0] >= $ i d d l ) && ($bk[0] <= $ iddh)) { p r i n t $pass_0++; p r i n t 'pass_0 = ' , $pass_0 , ° \ t passed\n° ; } e lse { $pass_0-- ; p r i n t 'pass_0 = ' , $ p a s s _ 0 , " \ t f a i l e d \ n " ; } i f ( ( $ b k [ l ] >= $VOL_LOW) && ( $ b k [ l ] <= $VOL_HIGH)) { $pass_l++; p r i n t ' pass_ l =' , $ p a s s _ l , " \ t passed \n " ; } e l se { $ p a s s _ l - - ; p r i n t . 'pass_l = ' , $pass_l , " \ t f a i l e d \ n " ; } i f ($bk[2] =~ / 2 5 / i ) {chop ; ) e l se { i f <($bk[2] >= $VOH_LOW) && ($bk[2] <= $VOH_HIGH)) { $pass_2++; p r i n t 'pass_2 = ' , $ p a s s _ 2 , " \ t passed \n " ; } e l s e { $pass_2--,- p r i n t 'pass_2 = ' ,$pass_2, ' $bk [0 ] = ' , $bk[2] , " \ t f a i l e d \ n " ; } } 111 i f ( ($bk [3 ] >= $VOL_LOW) && ($bk[3] <= $VOL_HIGH)) { $pass_3++; p r i n t 'pass_3 = ' , $ p a s s _ 3 , " \ t passed \n " ; } e l se { $pass_3-- ; p r i n t 'pass_3 = ' ,$pass_3, ' $bk [3 ] = ' , $bk[3] , u \ t f a i l e d \ n i f ( ($bk [4 ] >= $VOL_LOW) && ($bk[4] <= $VOL_HIGH)) { ++$pass_4; p r i n t 'pass_4 = ' , $ p a s s _ 4 , " \ t passed \n " ; } e l se { $pass_4-- ; p r i n t 'pass_4 = ' , $ p a s s _ 4 , " \ t f a i l e d \ n " ; } i f <($bk[5] >= $VOH_LOW) && ($bk[5] <= $VOH_HIGH)) { $pass_5++; p r i n t 'pass_5 =' , $ p a s s _ 5 , " \ t passed \n " ; } e l se { $pass_5-- ; p r i n t 'pass_5 = ' , $ p a s s _ 5 , * \ t f a i l e d \ n " ; } 112 Appendix E HSPICE Device Model Parameters * * *T Y P I C A L * * * . M O D E L NN5C212X N P N + IS= 7.62E-18 BF= 1.04E+02 NF= 1.00E+00 + VAF= 1.18E+02 IKF= 1.01E-02 ISE= 8.47E-18 + NE= 1.50E+00 + BR= 1.00E+00 NR= 1.00E+00 VAR= 5.50E+00 + IKR= 0.00E+00 ISC= 0.00E+00 NC= 2.00E+00 + RB= 2.02E+02 IRB= 9.02E-07 RBM= 6.73E+01 + RE= 7.35E+00 RC= 8.22E+01 + CJE= 4.00E-14 VJE= 8.00E-01 MJE= 1.46E-01 + TF= 1.35E-11 XTF= 6.24E+02 VTF= 1.12E+00 + ITF= 1.82E-01 PTF= 2.50E+01 + CJC= 2.95E-14 VJC= 6.03E-01 MJC= 2.87E-01 + XCJC= 2.80E-01 TR= 4.00E-09 + CJS= 5.15E-14 VJS= 5.66E-01 MJS= 1.72E-01 + XTB= 1.38E+00 EG= 1.11E+00 XTI= 3.40E+00 + KF= 2.78E-10 AF= 1.86E+00 FC= 7.13E-01 ***BEST *** . M O D E L NN5C212X N P N + IS= 1.07E-17 BF= 1.97E+02 NF= 1.00E+00 + VAF= 8.22E+01 IKF= 1.89E-02 ISE= 8.47E-18 + NE= 1.50E+00 + BR= 1.00E+00 NR= 1.00E+00 VAR= 4.40E+00 + IKR= O.OOE+00 ISC= O.OOE+00 NC= 2.00E+00 + RB= 2.22E+02 IRB= 9.02E-07 RBM= 7.40E+01 + RE= 4.74E+00 RC= 6.78E+01 + CJE= 3.20E-14 VJE= 8.00E-01 MJE= 1.46E-01 + TF= 1.21E-11 XTF= 6.24E+02 VTF= 1.12E+00 + ITF= 2.00E-01 PTF= 2.50E+01 + CJC= 3.10E-14 VJC= 6.03E-01 MJC= 2.87E-01 + XCJC= 2.80E-01 TR= 4.00E-09 + CJS= 4.64E-14 VJS= 5.66E-01 MJS= 1.72E-01 + XTB= 1.38E+00 EG= 1.11E+00 XTI= 3.40E+00 + KF= 9.26E-11 AF= 1.86E+00 FC= 7.13E-01 * * * ^ O R S T * * * . M O D E L NN5C212X N P N + IS= 4.57E-18 BF= 7.26E+01 NF= 1.00E+00 + VAF= 1.53E+02 IKF= 7.10E-03 ISE= 8.47E-18 + NE= 1.50E+00 + BR= 1.00E+00 NR= 1.00E+00 VAR= 6.60E+00 + IKR= 0.00E+00 ISC= 0.00E+00 NC= 2.00E+00 + RB= 1.82E+02 IRB= 9.02E-07 RBM= 6.06E+01 + RE= 1.30E+01 RC= 9.75E+01 + CJE= 4.81E-14 VJE= 8.00E-01 MJE= 1.46E-01 + TF= 1.55E-11 XTF= 6.24E+02 VTF= 1.12E+00 + ITF= 1.64E-01 PTF= 2.50E+01 + CJC= 2.81E-14 VJC= 6.03E-01 MJC= 2.87E-01 + XCJC= 2.80E-01 TR= 4.00E-09 + CJS= 5.67E-14 VJS= 5.66E-01 MJS= 1.72E-01 + XTB= 1.38E+00 EG= 1.11E+00 XTI= 3.40E+00 + KF= 8.33E-10 AF= 1.86E+00 FC= 7.13E-01 ** 113 Appendix F HSPICE Netlist of transistor switching from saturation/active to cut-off state BJT switching characteristics Turn off transient of the BJT from active to cut-off. . o p t i o n s p o s t VCC 6 0 DC 3 V I C 6 5 V I B 1 2 V I N 1 0 P W L ( 0 n s 0 . 8 5 n s 0 . 8 6 n s 0 1 0 0 n s 0) R L 5 4 2 e 3 RB 3 2 l e 3 Q I 4 3 0 Q172 .MODEL Q172 N P N BF=122 B R = 0 . 2 IS=2.65E-17 + C J E = 9 . 3 7 E - 1 4 V J E = 0 . 9 4 T F = 1 . 4 E - 9 + C J C = 1 . 0 9 E - 1 4 V J C = 0 . 7 T R = l E - 9 . t r a n 0 . 5 n s 1 5 n s . e n d BJT switching characteristics Turn off transient of the BJT from saturation to cut-off. . o p t i o n s p o s t 114 VCC 6 0 DC 3 VIC 6 5 VIB 1 2 VIN 1 0 PWMOns 3 5ns 3 6ns 0 100ns 0) RL 5 4 2e3 RB 3 2 le3 QI 4 3 0 Q172 .MODEL Q172 NPN BF=122 BR=0.2 IS=2.65E-17 +CJE=9.37E-14 VJE=0.94 TF=1.4E-9 +CJC=1.09E-14 VJC=0.7 TR=lE-9 .tran 0.5ns 15ns . end 115 

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