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A Real time simulator for power electric networks Linares-Rojas, Luis R. 1993

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A REAL TIME SIMULATOR FOR POWER ELECTRIC NETWORKS by LUIS R. LINARES R. Ing. Elec., Universidad Central de Venezuela, 1981 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING  We accept this thesis as conforming to th required standard  The University of British Columbia April 1993 © Luis R. Linares R., 1993  In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of th is thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission.  Department of el--€c--47-7 / c42— E' University of British Columbia Vancouver, Canada  Date  DE-6 (2/88)  417RIL 16,  1.7,3  ABSTRACT.  The main task of a real-time power network simulator on an off-theshelf hardware platform, the IBM RISC System/6000 model 560 machine, is presented. Simplified models, based on those used in the EMIT'', are included for the network elements: lumped resistors, capacitors, inductors and constant distributed parameter transmission lines. Fast nonlinear models are used for current and potential transformers. New fast modelling schemes for switching operations are introduced. A very flexible, portable, and efficient algorithm, which takes advantage of the decoupling due to the signals time delay between sections of a power network separated by transmission lines, is introduced.  1^Acronym for Electromagnetic Transient Program, the standard software tool for electric power network transient analysis.  fi  TABLE OF CONTENTS Abstract^  ii  List of Tables^  vi  List of Figures^  vii  Acknowledgement^  ix  I.Introduction^  1  II. System Models and Constraints^  4  1. System Models^  4  2. On Notation^  5  3. Lumped Elements^  5  4. Transmission Lines^  6  4.1 Lossless Single Phase Transmission Line Model^  6  4.2 Lossy Single Phase Transmission Line Model ^  7  4.3 Multiphase Transmission Line Model^  9  5. Instrument Transformers^  12  5.1 Current Transformers^  12  5.2 Potential Transformers^  14  6. Frequency Bandwidth. Integration Rule and Accuracy Limitations ^15 7. Size of the Network^  16 18  III. The Solution^ 1. Network's Discrete-time Model Equations^  18  2. Simulator Tasks. The Target Machine^  20  iii  3. Network Topology and Sparsity^  22  4. Simplified Updating Schemes for the History Sources ^  23  4.1 Lumped Elements^  23  4.2 Lossless Transmission Lines^  24  5. Nodal Voltage Calculation^  25  6. Line History Source Calculation^  26  7. Switching Operations^  26  8. Voltage Sources^  27  9. Metal Oxide Varistors, MOV ^  27  IV. Implementation: The Preprocessor ^  29  1. The Preprocessor's Tasks^  29  2. The Preprocessor's Input File^  30  3. The Preprocessor's Classes^  33  4. The lista Object-Class^  33  5. The nodeList Class^  35  6. The block Class^  36  7. The sistema Class^  36  8. Switching Operations Preprocessing ^  37  V. Implementation: The Simulator's Core, WINS ^  39  1. The Simulator^  39  2. The node Structure^  39  3. The Block as Part of the System^  40  4. Galvanic Links (gaLinks)^  41  iv  5. Lumped Elements^  43  6. Transmission Lines^  44  7. Switching Operations^  46  7.1 The GoSwEvent Routine^  49 51  VI. Test Cases^ 1. Generalities^  51  2. Test Case A: 18-node/25-branch Case^  51  3. Test Case B: 30-node/46-branch Case ^  52  VII. Conclusions^  54  VIII. References^  55  Appendix I. Test Case A. Input File^  57  Appendix II. Test Case B. Input File^  60  Appendix III. Test Case B. EMTP Input File ^  63  v  LIST OF TABLES Table I. Magnitude errors in integration with trapezoidal rule for At = 50 p.s. ^16  vi  LIST OF FIGURES Figure 1. A case configuration.^  2  Figure 2. Inductor's and capacitor's equivalent circuit. ^  5  Figure 3. Lumped losses in the transmission line model. ^  6  Figure 4. Single phase lossless transmission line.^  6  Figure 5. Single phase lossless transmission line model. ^  7  Figure 6. Lossy single phase transmission line. ^  7  Figure 7. History voltage source equivalent circuit. ^  8  Figure 8. Lossy line equivalent circuit.^  8  Figure 9. Equivalent circuit for mode "i". ^  10  Figure 10. Multiphase transmission line model in phase-domain. ^12 Figure 11. CT equivalent circuit.^  13  Figure 12. CT's piecewise approximate magnetization characteristic.^13 Figure 13. PT's frequency response.^  14  Figure 14. Frequency response for several integration rules. ^ 15 Figure 15. Typical configuration of power networks for protective relay testing. ^17 Figure 16. a) Sample single phase power system. b) Discrete-time equivalent.^19 Figure 17. RTNS main tasks. ^  21  Figure 18. Power network topology.^  22  Figure 19. Transmission line i-mode equivalent circuit. ^  24  Figure 20. FIFO stacks of modal history values for mode i. ^ 25 vii  Figure 21. Error introduced by linear interpolation of the history stack. ^25 Figure 22. Ideal characteristic of RTNS's MOV's.^  28  Figure 23. A _lista class instance, a linked list object.^  34  Figure 24. Hot node in a switch current calculation.^  37  Figure 25. A block's array of _node's structures.^  39  Figure 26. Whole network node's array.^  40  Figure 27. The system broken into blocks.^  41  Figure 28. Data elements inside a block. ^  41  Figure 29. Galvanic link, "gaLink".^  42  Figure 30. Pointers in "_gaLink" and " Jumped" structures.^ 44 Figure 31. History sources updating scheme in transmission lines. ^45 Figure 32. Switching Events table (array "swEvent"). ^  46  Figure 33. The network's switches array, "sw".^  47  Figure 34. GaLinks feeding current into the switch's "hot" node. ^48 Figure 35. Switch current calculation related data elements. ^ 49 Figure 36. Test Case A.^  52  Figure 37. Test Case B.^  52  Figure 38. Voltage at bus FAUL I, phase b, case B. ^  53  Figure 39. Difference, in percentage, between EMTP's output and RTNS's.^53  viii  ACKNOWLEDGMENTS  This work had not been possible without the contribution and active support I received from a number of people and institutions. This short note does not represent the deep sense of gratitude that goes to all those who helped me. Particularly, I want to thank: •  My wife, Maria Josefina, whose skilled wordprocessing and CAD drafting produced the final written copy of this report, for her love and unending support.  •  My mother, Rita Elena, my siblings Rafael, Victoria and Maria Elena, and my daughter Maria Leonor for their endurance and love.  •  Dr. J.R. Marti, for the financial support and for trusting me with this very important topic.  •  Dr. H.W. Dommel, for sharing his insight in the enlighting meetings we had during the realization of this work.  Luis R. Linares R.  ix  L INTRODUCTION In this thesis an effort to develop an EMTP 1 -based real-time network simulator to test protective relays for power systems is described. During the last two decades, the electromagnetic transient program EMTP has been steadily gaining grounds that used to be the domain of the expensive and bulky analog network simulator TNA2, transient calculations in power systems. Today, the EMTP is the standard tool for this kind of simulations. Even if already existing TNAs remain in service, most new needs are covered by EMTP installations. Cost and room use are two main areas where the EMTP has clear advantage when compared with the TNA. Another advantage is enhanced flexibility: very accurate models for system components can be developed and incorporated into the EMTP. Such is the case of the power transmission line, whose distributed parameters nature is not representable with the scaled-down analog models available in a TNA. In spite of those advantages, in cases when testing some device requires real-time interaction between the device and the power system it is connected to, the analog simulator TNA is still the answer. If a computer program is to attain real-time performance while simulating a power network, the program has to be capable of solving the system equations fast enough to encompass the bandwidth required for the equipment under test. In protective relay tests, a bandwidth between 2,000 Hz and 4,000 Hz is adequate. Using the trapezoidal integration rule and keeping the maximum distortion error introduced by the rule under 10%, an integration time-step between 50gs and 1001-1S is then necessary. To perceive the performance improvement needed, the sample 30-node/46-branch Electromagnetic Transients Program. 2 Transient Network Analizer. 1  1  system in Fig. 1 was simulated with the Microtran® program (UBC's PC version of the EMTP) on a 33 MHz, i486 workstation. That simulation required 4,280gs per time step. An improvement in speed of 40 to 90 times would be necessary for real-time performance. 250 km  sys-f  celled  -  FAUL1  L  fault  150 km  S2  sys-2  500 kV 100 km  coupled  -ese—far-  BUSS  ^  BUS1  BUSS  FAUL2  BUS4  Figure 1. A case configuration.  In spite of the strict speed requirements, the new breed of microchips and computer architectures has been attracting researchers [e.g. 14, 15, 16] into trying to produce a digital real-time simulator. Most of those researchers have chosen a hardware approach. They mimic the topology of the power network with a convenient arrangement of either DSP's 3 [14] or transputers [15, 16]. Some other researchers [17] have attempted a transient stability analysis of a power network by splitting the simulation loops into spawned child processes, where each of these processes is assigned to a node in a hypercube architecture system, according to a sophisticated mapping pattern. The results reported in [17] show a speedup of 45% when moving from one to two processors; but an additional gain in speed, for the linear part of the problem, with four processors of only 15%. If more than four processors were used, the additional overhead actually increased the total execution time. In hardware based solutions like those in [15, 16], the close match between the particular network to be solved and the physical connection of boards or transputers may render the solution inflexible. Besides, the upgrading cycle may be much slower than in the case of commercially available off-the-shelf computer systems. In this thesis a software-based method is introduced. The topology of a power Digital Signal Processors. ' Toward newer and faster chips.  2  network is marked by the time-decoupling introduced by transmission lines between their two ends. The resulting topology is mimicked by a software counterpart. The highly efficient pipelining scheme used in the superscalar architecture IBM RISC System 6000 Model 560 proved to be an ideal complement for the software developed. Successful simulation timings were obtained for configurations like the one in Fig. 1: 107gs/step. (38gs/step for a configuration similar to the system in Ref. [14], Fig. 15.) This software-based solution has the advantages of enhanced flexibility and upgradability: it is not hardwired to the configuration of the network to be simulated, and, written —its core RTNS— in ANSI-C, it is painlessly movable to faster superscalar architecture workstations, as they become available. At the time of this writing the IBM RISC System/6000 Model 580, rated as 38% faster' than the older model used in this thesis, is already available in the market. Digital Equipment Corporation machines based on the AlphaTM chip are also available. In particular, the DEC 3000 model 500 machine has been rated 6 as 32% faster that the IBM 560. Another new alternative for a host to the RTNS simulator has been released by Hewlett-Packard, the HP Apollo 9000 series 735, rated at 147 specmarcs (62% faster than the IBM 560).  5  ^126.2 specmarcs in the 580 vs. 91.1 specmarcs in the 560 machine.  6  120 specmarcs.  3  II. SYSTEM MODELS AND CONSTRAINTS  1. System Models  To simulate a power network, its state —voltages and currents— needs to be calculated at an unspecified number of time points. This problem is equivalent to the solution of a set of time differential equations. To make this problem suitable for a digital computer solution, the set of differential equations can be replaced by an equivalent set of difference equations according to Dommel [1]. As discussed by Marti et alli [2], the nature of those difference equations depend on the numerical integration rule chosen. The considerations given in Ref. [2] support the original decision made by Dommel [1]: to use the trapezoidal integration rule'. That is the rule used in this work. Instead of producing the differential equations and applying the selected integration rule to them, Dommel [1] takes the discrete-time mathematical model of each network element and converts it into an equivalent discrete circuit that only contains resistors and dependent sources, as seen in the next sections. Then, he uses those discrete-time equivalent models to build an equivalent network that only includes independent sources, resistors and sources dependent on previous states of the network (thus already known). The basic network elements for which models were included in this initial implementation of the real-time simulator are: lumped resistors, lumped capacitors, lumped inductors, distributed constant-parameters transmission lines', metal-oxide-varistors MOV, measuring transformers, and switches. Marti et alli found, notwithstanding, that this selection introduces numerical oscillations under certain conditions and complemented it with the Backward Euler integration rule as described in [2]. This correction, known as CDA [2], has not been included in this thesis's simulator. As opposed to frequency-dependent parameter transmission lines [13].  4  2. On Notation  In what follows the element under study is connected between nodes k —initial node— and m —final node—; the time advances in discrete steps of fixed and predetermined size At. At the end of the current step, v(t) is the voltage across the element and i(t) the current through it; v(t - At) and i(t - At) correspond to the end of the previous step (they are known, of course). 3. Lumped Elements [1, 8]  The resistor is simply represented as a resistance berween k and m [1]. The inductor and the capacitor are modelled by the equivalent circuit in Fig. 2.  v(t) Figure 2. Inductor's and capacitor's equivalent circuit.  The parameters g and ha (t) in the equivalent circuit in Fig. 2 are [1], for the inductor g = At^ (II-3 . 1 a) ° 2L At h = -- • v(t –^ 2L  -  -  At),^(II-3.1b)  and for the capacitor [1] 2C g- At h s (t) =  (II-3.2a)  ^• v(t – At) + i(t – At)^(II-3.2b)  From Fig. 2 and equations (II-3.1b) and (II-3.2b) it is seen that the behaviour of the model depends on the element state at the previous step: its history, hs .  5  4. Transmission Lines [1, 8]  Given the distributed parameter characteristic of the power transmission line, modelling it is not as direct as for lumped L and C elements. In what follows, it is assumed that the parameters are independent of the frequency, a necessary compromise between performance and accuracy adequate for a large number of applications [10]. It will also be assumed that both the inductance and the capacitance are uniformly distributed along the line [7]. The per metre values for those parameters are: L, in H/m; C, in F/m. Shunt conductance is assumed negligible and series resistance is treated as lumped into two loss-equivalent resistances at each end of the line. Each of those resistances is equal to one half the total series resistance of the line. If R, nlm, is the series resistance per metre of the line, and / the total length in metres, the total series resistance is R T = R . 1. The previous simplification leaves a lossless transmission line surrounded by two R 712  resistors as in Fig. 3. ik(t) —3  RT/2  4  m• m  k—we k •  ► (;)1 km  v',77  '  (  )  RT/2  lossless line  lvdt)  • 4'Sik'kk:Saelko^  Figure 3. Lumped losses in the transmission line model. 4.1 Lossless Single Phase Transmission Line Model  Dommel demonstrated [1] that the single phase lossless transmission line of Fig. 4 can be represented by the equivalent circuit in Fig. 5, iffft) m  k V„, (t)  tfk(r)^  Figure 4. Single phase lossless transmission line. 6  hk(t)  Figure 5. Single phase lossless transmission line model. where Zc = IL/C is the surge or characteristic impedance of the line, in a History sources h„,(t) and hk(t) depend on the voltage and current at the other end of the line onds before [1] -T  =  T sec-  IE is the travelling time of the line, in seconds— according to .  + i m (t – t)^(II-4. 1. la)  hk(t) = v "' (t  h„,(t) – vk(t –1) + ik(t – T)^(II-4.1.1b) That is, the behaviour of this model depends on the state of the line T seconds before: its history. This model remains applicable to lines whose length is such that  T  At. The  model is exact, it does not depend on the selection of numeric integration rule since none is used. A decision that affects the accuracy of this model is that of the interpolation scheme for cases where T is not a multiple of At. This decision is postponed until the next chapter. 4.2 Lossy Single Phase Transmission Line Model Combining the model in the previous section with the lumped resistances proposed in Fig. 3, we arrive at the model sketched in Fig. 6.  k  vk  (t)1  hk (t)  Figure 6. Lossy single phase transmission line. If the history current sources in Fig. 6 are transformed into equivalent voltage 7  sources, the circuit becomes the one shown in Fig. 7. im (t)  tk (t)  —3 R/2  ,T  m  em (t  , R/2  vi 7 (t) tvm (t)  ek(t)  Figure 7. History voltage source equivalent circuit. The history voltage source is, for node k ek(t) = vi„,(1 — + Z c • i „,(t — . ^(II-4.2.1)  It depends upon the voltage of the fictitious node m'. To reduce the workload of the simulator it is convenient to hide this node (as well as node k, on the right side) inside the model. Voltage at m' can be written vi„,(t — -c) = v„,(t — t) — 11 • i m (t — t).^(11-4.2.2) Substituting Eq. (11-4.2.2) into Eq. (II-4.2.1) we finally obtain  ek(t)=v m (t —  T) [z — 111 • i (t — T),^(11-4.2.3) c  m  with an analogous expression for e m (t). Converting the voltage sources back into current sources, the complete lossy line equivalent circuit of Fig. 8 is obtained, iiit)^ --)^ k^ hm(t)  I  im(t) <--Z c+RT/2 Vm (t)  vk (t) 4+R T/2 hk(t)^  Figure 8. Lossy line equivalent circuit. where the history current sources are given in terms of historic values of current and  8  voltage at the real nodes of the line according to Eq. (II-4.2.4a) and Eq. (11-4.2.4b).  hk(t)  [Zc –^1 – t)^(II-4.2.4a) = ^ 1.(t -c) +^v,,,(t Rr Z,^Z, +  [Zc 4]^1 h „,(t) =^ik0^ R Vk(t^ (II-4.2.4b) Z, +  4.3 Multiphase Transmission Line Model If the two ends of an n-phase transmission line are named k —the sending 3 end— and m4 —the receiving end—, the state of the line is given by two vectors of voltages [vk(t)] and [vm (t)] and two vectors of currents KM and [im (t)]. The parameter characterization of this line includes two full matrices of size n x n, one with the inductances per metre, in H/m, [L]; and another with the capacitances per metre, in F/m, [C], Ref [7]. If the phase quantities given by the four vectors in the previous paragraph are transformed according to Wedepohl's [5] modal component transformation (Eq. II-4.3.1a, b, c, d), two vectors of modal voltages [Vk(t)] and [Vm(t)] —one for each end of the line— and two vectors of modal currents [Ik(t)] and [Im (t)] —same as with the voltages— are obtained  [Vk(t)] = [sr [vk(t)]  [vn,(0]^=^[5] -1 [v.(t)] ^ (II-4.3.1a, b, c, d) [4(t)]^=^[ Q]' [ Ik(O] n,(01 = [0 1 [ 1 O] where transformation matrices [S] and [Q] 5 depend on the physical configuration of the The names sending end and receiving end have historical roots in times when power networks used to be mostly radial. Actually, both k and m are vectors whose entries identify the individual nodes on each end of the line. In RTNS these matrices are determined in a pre-processing step (i.e. outside of the real-time loop) by MTLINE (part of the Microtran package).  9  conductors in the line [5]. The modal transformation diagonalizes the matrices [L] and [C], Ref. [4], into the matrices [Ld] and [Cd].  Voltages and currents for each mode are related in the same way voltages and currents in the single-phase line are related [1, 5]. An equivalent circuit can be established for each mode like the one in Fig. 9.  Figure 9. Equivalent circuit for mode "i". where = voltage of mode i at sending end k. = voltage of mode i at receiving end M.  = current of mode i at sending end k. = current of mode i at receiving end m. Z,„^= characteristic impedance for mode i. Hid^= history current source on sending end k for mode i. H,,,,^= history current source on receiving end m for mode i.  In terms of Lth and Cd, 6 , the characteristic impedance for mode i is Zvi^  L di  Cdi  (11-4.3.2)  The speed of propagation for waves of mode i along the transmission line is 1  a, —^ Xd,CTh  The i-th elements in transformed inductance and capacitance diagonal matrices [1,,,] and [Cd].  10  (11-4.3.3)  from which it follows that if 1 is the total length of the line, the travelling time for mode i is 1  (11-4.3.4) Lc ' Ti; = /.riCTli^  History current sources^and H. depend on modal current and modal voltage at the other end of the line T, seconds before according to Hki(t)  Hmi(t  —  Vrni(t^i) Zci  )  =  TI)  (II-4.3.5a)  + Iki(t T1)  (11-4.3.5b)  + InAt  Vki^1) CI  Equations (11-4.3.5) define the entries of two modal-history-source vectors, one for the sending end [Hk(t)] and another for the receiving end [H.(1)]. These two vectors are transformed back to the time domain through the corresponding inverse transformation, two history current source vectors are obtained for each phase —one for each end of the line—. [h k = OHM]  [17. (0] = OH.  ^  (I1-4.3.6a)  ^ (11-4.3.6b)  Applying the same inverse transformation to the decoupled modal-characteristicconductance matrix 1/Zci^0^•••^0  [g] = [Q]  0 1/Zc2^0  (11-4.3.7)  ••• lac,„  the full [g] matrix is obtained. Matrix [g] is the transmission line contribution' to the network bus conductance matrix [G] in Eq. (III-1.1). In the phase domain, the multiphase transmission line can be visualized by the vector/matrix-parameter equivalent circuit in Fig. 10. At both ends of the line.  11  [in(t)]  [ik(t)]  ^>^ [k]^ [vk(t)]i^[g]^  [m] [g]^ [vm(t)]  Figure 10. Multiphase transmission line model in phase-domain. [0 is a matrix, all the other parameters are vectors.  5. Instrument Transformers It is not what happens in the network, but what the instrument transformers make of it, what determines the relay reaction. Hence, it is essential to model accurately their nonlinear characteristics. Current and voltage transformer models are not part of the real-time core module RTNS. The corresponding C-code was prepared and tested, and is ready to be incorporated in the software/hardware modules that will allow RTNS to interact with the real world.  5.1 Current Transformers A model for the current transformer (CT) that incorporates the saturation characteristic of the CT's core was introduced by Dommel in Ref. [12]. In this model the secondary current of the CT, is, is calculated from the primary current, ip —determined by the simulator's module core RTNS—, and from the present saturation state of the CT's core. The circuit model for the CT is shown in Fig. 11. Losses in the core, from hysteresis and eddy current effects, are taken into account through the resistance Gp.e . The nonlinear magnetization characteristic of the core is approximated by a piecewise linear representation, Fig. 12. Each segment in that piecewise representation is determined 12  Figure 11. CT equivalent circuit.  by the inverse of its slope by the flux linkage value at the segment's end ^by  r lend  —  im(i)  Xend —  (II-5.1.1)  where ini (t), lend, Rend, X(t) s , are defined in figures 11 and 12; and by the constant km = lend F  Xend •  (11-5.1.2)  Figure 12. CT's piecewise approximate magnetization characteristic.  At each step the previous magnetization state A.(t - Al) is known. The secondary current is calculated as a functionof the primary current ip (t) according to  /AO = k i [  (  t)  (/  —^— h Fe (t) — 2 ,(01+ h s (t)^(II-5.1.3)  where a is the CT's turns ratio, and h Fe and h s are functions that take into account the Magnetic flux linkages in the CT's core.  13  magnetization history of the core. Finally, the magnetic status A.(t) of the core is updated and the active segment in the magnetization characteristic of Fig. 12 is determined. The system is ready to repeat the procedure with the next time-step's ip (t) value. 5.2 Potential Transformers The model used for the potential transformer (PT) is the one presented by Marti in Ref. [19]. He approximates the PT's non-flat frequency response in Fig. 13 by a two-pole transfer function of the form  Vo„,(s) k ^ V,„(s)^(s + p 1)(s + p 2)'  (11-5.2.1)  10 0 -10  -50 -60 10 1^10 ^102  10•-  Frequency Pk)  Figure 13. PT's frequency response. The output voltage is computed, in the time domain, as a function of the input voltage and the magnetization history of the PT's core.  14  6. Frequency Bandwidth, Integration Rule and Accuracy Limitations  The smaller the integration step At, the wider the bandwidth of the solution, but the higher the performance requirements on the simulator. The theoretical bandwidth is determined by the sampling rate and is given by the Nyquist frequency Ay _1 fNy 2At • I  (II-6.1)  ^  For an integration step At = 50 1.1s, the theoretical bandwidth would be  1 - 10, 000Hz. 2 x 50 x 10 -6  (11-6.2)  fNy -^  This theoretical bandwidth is drastically reduced by the distortion introduced by the integration rule. Marti and Lin [2] studied the distortion introduced by four integration rules: trapezoidal, Simpson's, backward Euler's and Gear's. The frequency response of those rules up to the Nyquist frequency can be seen if Fig. 14a for the magnitude, and in Fig. 14b for the phase. The ideal integration rule should have a flat amplitude response of ordinate y = 1, and a flat phase shift of zero degrees. 90 SO TO 00 60 40 SO 20 10  0.2  •  0 0.06 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 05  0.05 0.1 0.15 0.2 0.25 0.3 0.36 0.4 0.41  Frequency in per unit of (1/6 t)  Frequency in per unit of (1/h t)  0.5  (b)  (a)  Figure 14. Frequency response for several integration rules. (a) Magnitude. (b) Phase.  Marti and Lin [2] rule out Simpson's rule, despite its higher accuracy in the low frequency range, because it goes out of bounds when the frequency approaches Nyquist's, Fig. 14a. Gear's and Backward Euler's rules distort the signal by shifting the phase at each frequency by a different angle, Fig. 14b. On the other hand, trapezoidal rule has an 15  acceptable accuracy as can be seen from Table I [12] and introduces no phase error, Fig. 14b. f(Hz) Error  2,000 3%  4,000 10%  8,000 60%  10,000 100%  Table I. Magnitude errors in integration with trapezoidal rule fot dt = 50 ,us.  In protective relay tests, the range of frequencies of interest goes up to 2,000 Hz. Depending on the tolerated distortion, see Table I and Eq. II-6.1, the integration step should be At = 504s for error 3%  At = 100ps for error .^ 10% This coincides with the recommendations in Ref. [14] . 7. Size of the Network  The size of the power network to be simulated is given by the number of nodes and branches —one branch per lumped element or switch, 2n branches per n-phase line in the discretized equivalent network. That size is directly proportional to the workload imposed on the simulator during each step. To test a protective relay, it is necessary to model the network around it with sufficient detail to include the relay's protection zone and the simulated fault or switching operation. The network outside that zone may be represented by compact multiphase coupled-impedance Thevenin' s equivalent circuits [10]. The compromise between performance and accuracy sketched in the previous paragraph reduces the configuration of the network to be solved to one like that in Fig. 15, which is similar to the reported test case used in Ref. [14]. 16  -469Z-Av-  Figure 15. Typical configuration ofpower networks for protective relay testing. The actual size of a network such as that of Fig.15 depends on the possible multicircuit nature of some of the transmission links represented. In this thesis the capability of modelling multicircuit transmission links has been included.  17  1.111, SOLUTION 1. Network's Discrete-time Model Equations When the elements in the original power network are substituted by the discrete-time models of chapter II, the network becomes a circuit that only contains resistors, dependent current sources', and independent sources. If nodal network analysis is applied to such a circuit, the following matrix equation is obtained [G] [v(t)] = [h(t)] (111-1.1)  where [G] is the equivalent-network's node conductance matrix, [h(t)] is the vector of nodal injected currents', and [v(t)] the vector of node voltages with respect to the reference node. The nodes in the network are divided, out of convenience, into two groups: the "b nodes", or voltage-source-nodes, those which are the terminals of ideal voltage  sources4—nodes b, and b 2 in Fig. 16—; and the "a nodes", or non-voltage-source-nodes, nodes whose voltages are unknown —nodes a,, a 2 , and a3 in Fig. 16. If rows in Eq. (III 1.1) are ordered in such a way that the lowermost rows corre-  spond to the nodes to which independent voltage sources' are connected, that equation can be written as ^[Gaa  Gab 1[Va(i)^[ha(t) Gba Gbb^Vb(t)^hb(0  History sources, see chapter II. Includes history sources, of course. Ground, in RTNS. Generators ' s Thevenin-equivalent-sources.  18  (III-1.2)  where [vb (t)] is the vector of independent voltage sources in the network. That vector is known, and the terms associated with it can be moved to the right side [Gaa][va(0] = [ha(t)] — [Gab]ivb(01.^(III-1.3)  e_romp_e_  TRANSMISSION LINE  •^  a2  (a)  (b)  Figure 16. a) Sample single phase power system. b) Discrete-time equivalent circuit for system in (a). ^.  One of the major tasks of RTNS is to solve Eq. (III-1.3) 5 for the unknown nodal voltages [va (t)]. One possibility is to multiply Eq. (III-1.3) by [Goa t' [Va(t)] = [G a a] -1 [ha(t)] — [G a or [Gab][1'b(0] •^(III-1.4)  Matrices [G aa ]"', [Gab ], and vector [vb(t)] can be calculated before the actual real-time simulation begins. To solve for the system nodal voltages, RTNS establishes nodal cur rents [1 a (1)] , and applies Eq. (III-1.4). Were it not for switching operations, matrix [G a]"' would be a constant, and vector [C(t)] = [Gaar [Gab][vbW] could be precalculated. Fortunately (no switches to/from "b nodes") matrix [Gab ] is impervious to configuration changes produced by switching operations, so vector [D(t)] = [G a b][v b (0] can be precalculated. Equation (III-1.4) becomes Eq. (III-1.5), which is in the form used in RTNS. [v (0] = [A] ah a^— [D(t)])^  (III-1.5)  The Standard EMTP solves Eq. (III-I.1) using the Gauss elimination technique instead, and a remarkable scheme to take advantage of the high sparsity of the [G] matrix. A different approach in solving Eq. (1114 .3), and in considering the inherent sparsity of [G„) was taken in RTNS, as reported below.  19  where [A] = [G.] -1 . It will be seen in section 8 of this chapter, and section 1 of chapter IV, that for each switch position combination a different [A] matrix needs to be computed.  2. Simulator Tasks. The Target Machine  To solve the discrete-time equivalent circuit obtained by application of the models seen in chapter II, RTNS uses equation (III-1.5) at each time step. To apply that equation, RTNS needs the nodal current vector [I: a (t)]. But to add up this nodal current vector, RTNS uses the value of every current source in the network. this means that the simulator has to calculate the history current sources of every element. So, given in order of precedence, the three main tasks of the simulator are: 1.  History current sources updating. Using the values of voltages and currents at the previous time step (or initial condition values, if this is the first time step), the simulator determines the value of every history current source.  2.  Total nodal current vector [h a (t)] calculation. The simulator adds every current source coming into each node.  3.^Node voltages [va (t)] determination. The simulator uses equation (III-1.5) to solve for the voltage of every node in the system. Tasks (1) to (3) above, when followed as they stand, represent a formidable task of floating point, indexing, and decision making operations. The superscalar architecture, as implemented in the IBM RISC System/6000 Model 560, offers a pipelining scheme that promises the capability to execute a floating point, an indexing, and a decision operation simultaneously in one single clock pulse. This computer is rated at 91.1 specmarks. Programming tasks (1) to (3) in a prototype coded in C language, and running that prototype on the IBM RISC 560 workstation resulted, for a system equivalent in size to that in Fig. 20  1, in a timing of 520 ts/step. This is promising, but still does not meet the design goal. Profiling the produced code showed that the three tasks undertaken by the prototype were sharing the loop execution time as follows: history current sources updating, 14.7%; nodal current vector adding up, 19.6%; and nodal voltages calculation, 65.8%.  start preprocessing ■Jr t=0, dt, 2dt,...  A  update history '  sources  accumulate  nodal currents  1  calculate  nodal voltages  Figure 17. RTNS main tasks.  To reduce the workload represented by task (3) above, which is taking the largest slice of the execution time of the simulator main-loop, the topology of the network was taken advantage of, as explained in section 111.3. Simplification of the updating procedures for both lumped elements and transmission lines —see section 111.4 below—, proved effective in speeding up task (1). The block-breaking technique discussed in 111.3, when implemented as shown in the next chapter, also simplified task (2). 21  3. Network Topology and Sparsity A general power network can be visualized as separate blocks interconnected by transmission lines, Fig. 18a. As an example, the circuit in Fig. 16b (the discrete-time version of the network in Fig. 16a) is divided into two time-decoupled blocks by the model of the transmission line. The importance of this approach lies on the time-decoupling introduced by transmission lines between those blocks. If rows in matrix [G.] are reordered in such a way that all the nodes within the same block correspond to consecutive rows, [G.] becomes a block-diagonal matrix, Fig. 18b.  [G] matrix  2 3  (b)  Figure 18. a) Power network topology. b) Corresponding [G] matrix. This topology suggests the solution of each of the decoupled blocks separately, which is a much less formidable problem6 . Equation (III-1.5) can be applied to each of these blocks, where [G.] will then be the nodal conductance sub-matrix corresponding to non-voltage-source-nodes in that block, [I JO] will be the total currents injected into non-voltage-source-nodes in that block, and [vb (t)] the values of the voltage sources in that block. Solving the network as a set of such blocks takes account of sparsity of the network in a very efficient manner. The size of such blocks ranges, for a typical power network, between 3 —most of the blocks— and 12'. To stress the importance of this This task load varies approximately as n 2 , where n is the number of nodes in the subsystem.  22  block-breaking technique, a hypothetical case is presented: suppose a 90-node (non-voltage-source nodes) network. If it is composed of some thirty 3-node blocks, and Eq. (III-1.5) is applied "as is" to the total network, the solution requires some 8,100 multiplications and 8,100 additions'. If the block-breaking technique is used instead, the task's size goes down to nine multiplications and nine additions per block, that is 270 multiplications and 270 additions for the complete system. This reduces the floating-pointoperations load to less than 4%. 4. Simplified Updating Schemes for the History Sources 4.1 Lumped Elements To keep track of its past history, each lumped-element model in chapter II imposes on the simulator the calculation of the current through the element, as seen in equation (II-3.1b) and (II-3.2b). Marti [20] avoids this extra calculation by introducing an auxiliary history variable f, defined as  go = 2g • v(t — At) — 17,(t — At),^(III-4.1) where Its(t-At) and g are defined in equations (II-3.1) and (11-3.2) respectively, and h., is the history current source. The definition given by Eq. (III-4.1) implies that for an inductor 17,(0= —At), and for a capacitor h s (t) =At). Finally, and making use of the corollaries in the previous sentence, simplified updating expressions for the history current sources can be written for the inductor as  ^  and for the capacitor as  ^  13,(t) = h s (t — At) — 2g • v(t — At),^(III-4.2a)  h s (t). 2g• v(t — At) — h — At).^(III-4.2b)  Non-voltage-source nodes. Unless sparsity index tracking is used, as in the EMT'P. Some overhead for matrix-element fetching-time would have to be estimated in this case.  23  To update the history source value 140, with this simplified model, it is only necessary to keep track of the previous value of the source hs(t-At), since the voltage across the element is to be calculated at each time step anyways. 4.2 Lossless Transmission Lines The equivalent model represented by Eqs. (II-4.3.5) in the previous chapter implies the calculation of currents at both ends of the line for each transmission mode. Representing each mode of a multiphase transmission line by its equivalent circuit, Fig. 19, and defining the characteristic conductance of mode i as G,=11Z„, modal history source values can be updated —as demonstrated by Marti [20] after some manipulation of Eqs. (11-4.3.5)— by H = 2G, • V„„ (t – t) – H„„ (t – T) (111-4.2.1a)  = 2G, • V k7 (t - - H (i -^(III-4.2. lb)  Hid (t)  Figure 19. Transmission line i-mode equivalent circuit. The last two equations suggest that only the last n=inter/A0+1 values of both H. and  Hk, have to be kept in store, see Fig. 20. Unless the travelling time T of the line is a multiple of the integration time step At, the old value of the history sources H's needed in equations (III-4.2.1) is not found directly in the stored stack shown in Fig. 20. Some interpolating scheme has to be selected to calculate it. The method used for interpolation has to be fast. The first attempt used in RTNS was to use the closest of the last two values stored in the history stack. This approach, fast as it was, showed that even the apparently neglegible error committed in the rounded values of the modal-travelling times, 24  T'S, had  an  H  t  t-.^t  t-(n-2)dt  t-(n- 1)4 t  HI77%  t  t-^t  t-(n-2)dt  t-(n-1)4 t  ki  Figure 20. F7F0 stacks of modal history values for mode i. important distortioning effect on the output. It was decided to use the linear interpolation scheme, used by the EMTP. This decision also introduces an error in the travelling times, as seen in Fig. 21, but a significantly smaller one than that of the truncation method used before. It remains, however, the question of how big is the distortion of the output introduced by this EMTP's linear interpolation. It seems advisable, if not for a real time simulator, to study more sophisticated (and time consuming) interpolation methods'.  is the exact travelling time, lk is the travelling time used by the linear interpolating scheme, AT is the committed error.  t-(n-2)dt  Figure 21. Error introduced by linear interpolation of the history stack. 5. Node Voltage Calculation To obtain the node voltages, RTNS drives a group of 00P'-like dedicated methods that enhance the performance of the code. This approach takes advantage of the sparsity ^That task is left open for future research. Linear interpolation was used in RTNS. io^Object Oriented Programming. With the very important difference that OOP's instances of the same class  9  25  of the system in a very efficient manner, and puts big efforts on the preprocessing stage, where they belong, leaving the main loop of the simulator much lighter, as it should be. An extra bonus of this technique is eliminating the overhead of related loops in the traditional approach. 6. Line History Source Calculation  A technique similar to the one described in the previous section can be applied to the transmission-line-history sources updating. The improvement of the overall performance is not as important, however, as in the previous case. 7. Switching Operations  As seen in the last paragraph of section III. 1, each block in the network is characterized by the matrices [A] = [G a ,]" 1 and [Gob ]. If the configuration of the block does not change, those two are constant matrices and can be calculated in a preprocessing stage. Whenever a switch inside a block changes its position, however, the configuration of the block changes, and so does [A] = [G.]. For a block with n switches there are 2n possible configurations and T corresponding [A] = [Gaa ] 1 matrices. If the switches within the block are numbered from 0 to (n-1), each  configuration can be labelled by an integer number whose binary-representation's k-th-bit correspond to the status of the k-th-switch in the block. For example, in a block with three switches, they are numbered 0, 1, and 2; the configuration with switches 0 and 2 open, but switch 1 closed is labelled as 2. i.e. 0  switch (bit) no.--► 2  I  0  1  0  = 2 (base 10)  access the same code to perform the method's actions, which is not the case in RTNS.  26  During the real-time simulation, a switch status variable is kept for each block. Each time a switch changes its position, the switch's corresponding bit is toggled. The block's nodal-voltages-calculation routine begins by checking the switch status variable, if the status changed, the corresponding [A] = [G aa] -1 matrix is moved into the active space attached to that block. 8. Voltage Sources  Only sinusoidal voltage sources were included in this implementation. The source vector [vb (t)], for each block with sources, along a complete fundamental frequency period, at every At, is determined and stored during the preprocessing stage. The same is done with vector [D(t)], equations (III-1.4) and (III-1.5). For example, for a block with three voltage sources off = 60Hz, and using an integration step At = 50 1.1s, it is necessary to store (1/60)/(50x10) = 333 values for each source, i.e. a matrix with three rows (one per source) and 333 columns (one per time step inside the period). A similar approach applies for vector [D(t)]. There is one problem with this approach. If the source period is not a multiple of the integration step used, at the end of every cycle there will be some mismatch between the value delivered by this method, and the correct value delivered by the source. The time mismatch will be kept constant during the next cycle. With every new cycle, the phase shift of the wave will be bigger, attaining eventually unbearable discrepancies with the original signal of the source. One solution to this shifting is to use the submultiple of the sources' period closest to the requested At as the effective integration step. 9. Metal Oxide Varistor (MOV) -  An MOV operation, limiting the voltage across the capacitor in parallel with the MOV to a predefined maximum, is simulated in WINS by the ideal characteristic depicted 27  in Fig.22. Whenever the voltage across the protected capacitor goes over the maximum value tolerated, the model is activated and it chops the voltage, keeping it at the maximum value. Vout A  Vmax  Vin  Figure 22. Ideal characteristic of RTNS's MOV's.  28  IV. IMPLEMENTATION: THE PREPROCESSOR 1. The Preprocessor's Tasks As seen in chapter III, as much load as possible has been moved to the preprocessing stage of the simulation package, RTNS-PP, the Real-Time-Network-Simulator's Preprocessor. RTNS-PP is a separate OOP' module built on one custom designed circular double-linked list class and three descendent classes: the node-list object-class, the block object-class, and the system object-class. RTNS-PP was written in C++, and compiled on the target computer with the GNU's g++ compiler. This preprocessor receives the power network in an input file similar to the one shown in the next section. RTNS-PP separates all the nodes, lumped elements, switches and voltage sources into blocks, according to section 11-3. Within each block, RTNS-PP reorders the nodes in such a way that VSN nodes take the last consecutive positions. For the switches in each block, the preprocessor generates all the possible combinations of ON/OFF positions. Next RTNS-PP determines the [A] = [Gaa ] -1 matrix of the block for each of those switch combinations, with each combination's matrix adequatelly labelled for use in the main simulating loop of RTNS. The preprocessor generates the matrix [Gab ] and, for each time step along a full cycle of the fundamental frequency of the sources—section 111-9—, the vectors [vb (t)] and [D(t)] = [G ab ][v b (t)] 2 Object Oriented Programming. To minimize the size of the intermediate file, between the preprocessor and the simulator, the necessary vector [v b(t)], even if calculated in RTNS-PP, is not passed to RTNS. RTNS receives the matrix [G,,] and the source parameters and organization into the proper blocks. RTNS contains a minimal preprocessing stage that takes care of the chore of calculating vectors [v b(t)] and [D(t)] before the main simulation loop  29  2. The Preprocessor Input File The input file to the preprocessor is a free format text file, whose basic template can be generated by the included utility RTNS-TMP. The indentation shown in the following example is there to make reading easier for the human user, it is not necessary for the program, but recommended. The significant data in the file begins with the keyword FILE. Before  .BEGIN  that keyword any comment can be included for identification purposes, see  Appendix I. The data in the file is divided into six sections. Each section begins with the keyword .BEGIN, followed by a space and the label identifying the section: DATA, LUMPED, LINES, SOURCES, SWITCHES, OUTPUT.  GENERAL-  Each section ends with the key-  word .END followed by the corresponding section label. Some of the data items are preceded by a label, included by the template utility RTNS-TMP. Each of those labels explains the meaning of the following data item (see the example below). .BEGIN FILE .BEGIN GENERAL-DATA (...) .END GENERAL-DATA .BEGIN LUMPED (...)  .END LUMPED .BEGIN LINES .BEGIN LINE-0 (...)  .END LINE-0 .BEGIN LINE-1 (...)  .END LINE-1 .END LINES .BEGIN SOURCES (...)  .END SOURCES .BEGIN SWITCHES (...)  .END SWITCHES .BEGIN OUTPUT (...) .END OUTPUT .END FILE  The  GENERAL-DATA section  includes: the label integration step deltaT item, in  begins.  30  seconds; the total simulation time totalTime item, in seconds; the number of lumped elements in the network3 ; the number of transmission lines, numLines item; the number of sources in the system, numSources item; and the number of output nodes —nodes for which the voltage is output—, numOutNodes item. .BEGIN GENERAL-DATA deltaT: 50e-6 totalTime: 50e-3 numLumped: 6 numLines: 2 numSources: 6 numOutNodes: 3 .END GENERAL-DATA  The LUMPED section includes all the lumped elements —R, L, C— in the system. The section includes, for each lumped element, four data items: one of the letters R, L, or C; the parameter value (ohms in case of a resistor, millihenrys if an inductor, microfarads for a capacitor); next the two terminal nodes, each identified by a label with up to six characters; last comes the calcCurr labelled item, which is followed by no if current through the element is not to be calculated and included in the output, or ayes otherwise. .BEGIN LUMPED L 36.2 kark5 R 62e3 pluk2 C 75.2 gurkl .END LUMPED  pluk2 calcCurr: no tak6 calcCurr: yes pek2 calcCurr: yes  The LINES section has a subsection for each line. Lines should be included in increasing number of phases. Each line starts with the keyword  .BEGIN  followed by the label  LINE-#, and ends with the keyword .END followed by the same line label. The symbol # stands for the line input order, beginning from zero. For each line, five fields include the necessary data: the phases item, the line's total number of phases; the Zc item, the 3  ^  In a future version the preprocessor should skip this and the next three fields.  31  characteristic impedance (in ohms) of each transmission mode, in modal order (i.e. mode 0 first, mode 1 next, and so on); the delay item, travelling time, in seconds, for each of the transmission modes (same order as Zc); the nodes item, each node in the line followed by either a no (do not calculate the current entering this node) or a yes, (the order of the nodes is: first phase, sending end then receiving end; second phase, sending end then receiving end; and so on); last comes the q-matrix field, the modal transformation matrix entered by rows. The SOURCES section includes three data items for each source in the network: amplitude, in volts; phase angle, in degrees; and the source terminal node, a six character string. .BEGIN LINES .BEGIN LINE-0 phases: 3 Zc: 635.3 216.9 215.8 delay: 618e-6 418e-6 415e-6 nodes: klukl no pukl no kluk2 no puk2 yes kluk3 yes puk3 no q-matrix: 0.5924 -0.4132 -0.7171 0.5924 0.8214 0.0000 0.5418 -0.4132 0.7171 .END LINE-0 (...)  .END LINES  The SWITCHES section begins with the labelled data item total, that is followed by the number of switches in the network. Next, the section has, for each switch: two six character strings identifying the switch's terminal nodes; the labelled items close and open followed by the total number of close and open operations of that switch, respectively. To end each switch entry, and identified by the label close, a list of the closing times, in All voltage sources in RTNS are connected, as in the EMTP, between ground —the reference node— and a terminal node (the one included in the input file).  32  seconds; then, and identified by the label open, the corresponding list, also in seconds. An example of this section could be .BEGIN SWITCHES total: 1 kark3 pluk5 close: 3 open: 2 close: 2e-3 17e-3 50e-3 open: 25e-3 60e-3 .END SWITCHES  The OUTPUT section lists the nodes for which voltages will be included in the output stream, as six character strings.  3. The Preprocessor's Classes As mentioned in section IV-1, the working capabilities of RTNS-PP were built around an ancestor class: _lista, a doubly linked circular list class. Three other application specific classes inherit their basic methods and data elements from that _lista class. Those are: _nodeList, a list-class derived as public from _lista, with all the nodes in the system; block, a class—a public descendent of lista— that describes the activities associated  with a block in the networks; and sistema—publicly derived from lista—, a class that, as a linked list of block's, describes the system as a whole. The best way to describe the functionality of each of the object classes introduced above is to present its data and method elements.  4. The _lista Object Class -  This basic ancestor of the hierarchical family of classes in RTNS-PP is _lista, a  5  ^  A block defined in the sense seen in section III-3.  33  doubly linked circular list. It is built around a basic unit of data, the list-cell—see Fig. 23—, a structure with the type definition: typedef void *pointer; typedef struct _celda _ celda *prey;^//points to the previous _celda _celda *next;^//points to the next celda pointer contenido; //a generic pointer to a data cell } _celda, *_ptrCelda;  contents data  contents data  ^1  contents data ■^  Figure 23. A _lista class instance, a linked list object. The interface of the class lista is outlined here: typedef unisgned word; typedef enum {FALSE,TRUE} boolean;  class _lista {  protected: _ptrCelda cabeza;^//the head of the lisked list unisgnednumCeldas; //length of the list public: lista(); //Constructor -_lista(); //Destructor _ptrCelda CeldaNueva(pointer contenido,_ptrCelda anterior, _ptrCelda siguiente); //A new cell inline boolean EsNula(); //Is it the null list? inline word NumCeldas(); //Returns the number of cells inline _ptrCelda CeldaTerminal(); //Returns the list's head inline _ptrCelda PrimeraCelda(); //Returns the first cell inline _ptrCelda UltimaCelda(); //Returns the last cell _ptrCelda CeldaSiguiente(_ptrCelda celda); //Next cell _ptrCelda CeldaAnterior(_ptrCelda celda); //Previous cell void InsCelda(_ptrCelda celda, pointer contenido); //Insert cell void ElimCelda(_ptrCelda celda); //Eliminates a cell ptrCelda QueCeldaContiene(pointer contenido); //Which cell contains...? int Posicion(_ptrCelda celda); //Position of the cell "celda" (continues on next page)  34  (...begins on the previous page) _ptrCelda CeldaCuyaPosicion(int pos); //Returns the cell whose position is "pos" void InsAlPrincipio(pointer contenido); //Insert a cell at the beginning w/contents void InsAlFInal(pointer contenido); //Insert a cell at the end with the contents..  This is enough to describe the functionality of this class. 5. The _nodeList Class When the system data is read from the input file (see section IV.1), each node is included in this list. Nodes are characterized by their names, and by their type: terminal to a LUMPED element, a transmission LINE, or a voltage SOURCE. Associated with each node will be assigned, later in the preprocessing, a block identifying code. Meanwhile, each node has been marked as pending for block allocation. The basic unit of data in _nodeList is given by the structure: typedef enum {LUMPED, LINE, SOURCE} _typeOfNode; typedef struct _typeOfNode type; Char name[7]; int block; boolean pending; node, *_ptrNode;  The class functionality is described by the class's interface: class  _nodeList:public _lista  int currentBlock; public: nodeList(); //Class constructor int AgregueNodo(char *name, _typeOfNode type); //Adds a node _ptrNode BusqueNodo( int pos ); //Given its position in nodeList,returns the node int BusqueNodo( char *name ); //Given a node's name, returns its position _typeOfNode TypeOfNode( int code ); //Given a node's position, returns its type boolean QuedanPendientes(); //Any nodes pending processing? void SetPending( int pos ); //Set a node as pending for processing int GetStart( int *block ); //Activates "block",returns blk's first node position int GetNext(); //Returns position of the next node in the "activated" block  1;  35  6. The _block Class Each block, as defined in section III-3, is represented in RTNS-PP by an instance of the class _block defined as follows: class block:public _lista _ptrCelda firstSrcNode; //Points to the first VSN in the block double **matrix; //Points to the block's [A] matrix double **Gab; //Points to the block's [Gab] matrix void CreateklatrixIfNotThere(); //Allocates the [A] matrix int PrevSrcNode; //Auxiliary variable lista switches; //All switches in the block 'double **YCloseSw( int swlnBlk, double **Gaa ); //Given the [Gaa] matrix of a //block, and a switch position in the block, returns the //[Gaa] matrix once the switch is closed public: block(); //Class constructor void AgregueNodo( int code, _typeOfNode type ); //Add node with "code, type" int CodeNodo( int ordenEnBloque ); //Returns node's code, //given its order in the block int Pos( int code ); //Position of node in block (node given by its code) int NUmNonSrdNodes(); //Number of NVSN in the block int NumSrdNodes(); //Number of VSN in the block typeOfNode TypeOfNode( int code ); //given a block node's code, returns its type void SumeCasilla(int i, int j, double g); //Gaa[i,j] += g double **GetMatrix(); //Returns a pointer to the block's matrix. Use with care! double **GetGab(); //Returns the block's [Gab] matrix int NextSrcNode(); //Returns position in the block of the next VSN int NumSwitches(); //Returns Number of switches in the block int AgregaSwitch(int codeNodoln, int codeNodoFn); //Add switch between nodes //whose codes are "codeNodoln" and "codeNodotn" respectively double **A(int swStatus); //Returns block's [A] matrix of a switch configuration I;  7. The _sistema Class In RTNS-PP, the whole system is represented by an instance of the class _sistema. The interface, with describing comments, of this class is included: class _sistema:public _lista { int prevBlk; //Auxiliary historical variable used by "NextBlk" below int sizeSerched; //Auxiliary historical variable used by "NextBlk" below public: int NumBlk( int size ); //Rtns. the number of block of "size" in the system. //and reset prevBlk int NextBlk(); //Returns the code of the next block of the active size int NextSrcNode(int block); //Return the global code of a VSN in the "block" void AgregueNodo(int block, int code, _stypeOfNode type); //Adds node with "code" //and "type", to the "block" ^(continues in next page)  36  int CodeNodo( int block, int ordenEnBloque ); //Returns global code of the node //in "block" whose order in the block is "ordenEnBloque" int OrdenNodo( int block, int code ); //Returns the node's order in the "block", //given the node's global code void SumeCasilla( int block, int i, int j, double g ); //Adds "g" to the //"block"'s matrix element in row "i" and column "j" double **GetMatrix( int block ); //Returns a pointer to the "block" matrix double **GetGab( int block ); //Returns a pointer to the "block" [Gab] matrix int NumiNonSrdNodes( int block ); //Number of NVSN nodes in "block" int NUmSrdNodes( int block ); //Number of VSN nodes in "block" int NutNodes( int block ); //Total number of nodes in "block" int NumSwitches( int block ); //Number of switches in "block" int AgregaSwitch(int block, int codeNodoIn, int codeNodoFn); //Adds the switch //between nodes whose global codes are "codeNodoIn" and //"codeNodoFn", in the "block". Returns number of switches double **A(int block, int swStatus); //for the "block", and given the switches' //status "swStatus", returns the [A]=inverse[Gaa] matrix ^. ;  8. Switching Operations Preprocessing  The pair resistor/history current source appears in every model used by the EMTP. It is the basic unit of calculation in RTNS and is referred to, in what follows, as a "galvanic link" or "gaLink"  .  Figure 24. Hot node in a switch current calculation.  The current through the switch in Fig. 24 can be calculated by adding the contributions of gaLinks either at node k or at node m. In this case it is evident the convenience of choosing node k, with only two gaLinks, as the hot node. In general, the criteria used by RTNS-PP to select the hot node is: choose the node with no transmission line connected  37  to it (since it is very expensive —computationally— to calculate the current through a line's gaLink); if both nodes are connected to lines, or if none is, take the node with the smaller number of gaLinks. The preprocessor determines and records the block to which a switch belongs. RTNS-PP assigns the switch a position within the block. The preprocessor reports to the core RTNS each switch with the corresponding hot node, and an attached array of pointers to the necessary gaLinks.  38  V. IMPLEMENTATION: THE SIMULATOR'S CORE, RTNS  1. The Simulator  A general outline of the program's layout is given, stressing the data structures used and the relations among them, and with the tasks of the main loop. The approach followed in this chapter is to go from the specific, and simpler, to the general and, possibly, more complicated.  2. The _node Structure  The simplest data structure in RTNS is that of a node. A node is represented in RTNS by the structure struct node { float h; //Total current entering the node float v; //Node voltage  i.e. it contains two fields, one that keeps the total current entering the node, the other, the voltage of that node with respect to a reference node (ground in RTNS's case). The nodes in the system have been grouped into galvanically linked blocks (section 111.3) by the preprocessor (chapter IV). The nodes in each block are represented by a block's array of  an array of _node's  Figure 25. A block's array of _node's structures. 39  _node elements, see Fig. 25, one array of_node's per each block. Regardless of where the actual nodes are (each as an element of an array in one of the blocks' structures to be described in the next section), to keep track of all the system's nodes, an array of pointers to the nodes themselves is set up during the initialization stage. That array's definition is typedef struct char name[7]; /* 6-character string node's name node *dondEsta;^/*Points to the actual node } nodeId; nodeId *node;  ^  /*System's nodes array */  The global order of a node in the complete system is given by the corresponding index in the node array, see Fig. 26.  node  E  1 2  PIK9  3 o  -  4 TUN6 5  A  pointer to actual node (which is inside a block structure) node's name  Figure 26. Whole network node's array. 3. The Block as Part of the System RTNS's solution method relies strongly on breaking the total network into blocks. The network, as seen in section 111.3, is naturally fragmented into areas surrounded by 40  transmission lines. Each of those areas, which includes the nearest half of any transmission line terminating in the area, is what RTNS recognizes as a block. transmission line-link  transmission line-link  transmission line-link  Figure 27. The system broken into blocks.  Each of these blocks is represented by a structure _block that includes as fields: a small node resistance matrix [A], and a small vector for the node 's included in that block, [node]. If there are sources in the block, a full cycle for the periodic vector [D(t)] (see section 8 in chapter III) is also stored as a field of the _block structure, as shown in Fig. 28.  Figure 28. Data elements inside a block. 4. Galvanic Links (gaLinks)  The basic building unit of the discretized network is the parallel group formed by a conductance' and a history current source (Fig. 29), as is evidenced by the models For a multiphase transmission line there are mutual conductances between each pair of phases, but that does not invalidate this treatment.  41  reviewed in chapter II. Those pairs are called galvanic links (gaLink 2) in this work.  N(0)  Figure 29. Galvanic link, "gaLink". It is in galvanic links (gaLink) like that in Fig. 29 where all history sources are. The galvanic link's structure contains the history source value as a field. Each gaLink also knows which node it feeds, and which node it drains. Every galvanic link in the network is represented by a structure (_,gaLink), and all galvanic links are collected in an array according to: typedef struct { float hs; /* History current source */ float *nodInH; /*Points to initial node's h(total current) field */ float *nodEhH; /*Points to final node's "h" field */ boolean *calcCurr; /*Points to the "calculate current" flag in the element owner of this gaLink */ float current; /*Total current flowing accross the gaLink (Calculated only if *calcCurr==TRUE) I gaLink; gaLink *gaLink; /*Array of all network's galvanic links */  Assuming that the history source fields in all the gaLinks have already been updated, see sections 4 and 5 below, to perform the task (2) described in section 111.2 —calculate total nodal currents— RTNS traverses the gaLink array as follows for( i=0; i<numGaLinks; i++ ) { *(gaLink[i].nodInH)+= gaLink[i].h; if( gaLink[i].nodFnH ) /*If nodFn is not "ground" *(gaLink[i].nodfhH)-= gaLink[i].h;  "gaLink" is the name of the variable (an array) representing those galvanic links in RTNS.  42  5. Lumped Elements Each lumped element in RTNS has to know: ^ Where the element's history source field is (which is in a _gaLink, of course) to be able to update it. ^ Where the element's node voltages are stored (in a _block structure) to read them while updating its history sources These three pointers are hs, nodInV, and nodFnV in the _lumped structure that describes every lumped element in RTNS. All lumped elements in the system are grouped in an array lumped, defined as follows typedef enum {RESISTANCE, INDUCTANCE, CAPACITANCE} lumpedType; typedef struct { lumpedType type; /*Type of the lumped element */ float twiceG; /* 2*g */ float *hs; /*Points to the "hs" field in corresponding gaLink*/ float *nodInV; /*Points to the "v" field in initial node struc*/ float *nodFnV; /*Points to the "v" field in final node struc*/ boolean calcCurr; /*Flag to request current through element */ boolan notiMIOV; /*TRUE = no metal oxide varistor shunting it */ float maxVolt; /*Maximum voltage tolerated by the present NOV*/ lumped; -  lumped lumped[ MAX NUM LUMPED ];  Figure 30 shows the relation between the several pointers in the _lumped and in the  _gaLink structures. To update all history sources related to lumped elements, RTNS loops through the lumped array as follows for( i=0; i<numLumped; i++ ) { deltaVolt= *(lumped[i].nodInV)-*(lumped[i].nodFnV); if( lumped[i].type==INDUCTANCE ) /* h=h' - 2gv' */ *(lumped[i].hs)-= lumped[i].twiceG*deltaVolt; else if( lumped[i].type==CAPACITANCE ) /* h = 2gv' - h' */ *(lumped[i].bs)= lumped[i].twiceG*deltaVolt *(lumped[i].hs); -  43  lumped  ptr.to initial node's h ptr to final node's h history source  Figure 30. Pointers in "_gaLink" and "lumped" structures. 6. Transmission Lines  For each phase in a transmission line there is a corresponding pair of history sources: one on each end of the line, as seen in Fig. 10 of chapter II. An m-phase transmission line needs to keep track of 2m nodal voltages to update 2m history sources. Among other things, the data structure representing transmission lines in RTNS, _line, contains two arrays: V One with 2m pointers to the v fields of the corresponding 2m line's nodes. V Another with 2m pointers to the h 's fields of the 2m transmission line's galvanic links structures CgaLinks). All transmission lines in the system are grouped in the array line as follows: typedef struct { (...other fields...) float *hs[12]; /*Pointers to "hs" fields in the gaLinks */ float *nodeVolt[12]; /*Pointers to "v" in block's node's */ boolean calcCurr[12]; /*Flags requesting current entering line's nodes*/ } line; line line[ MAX NUM LINES ];  44  To update transmission-line-history-sources is more complicated, computationally, than for lumped elements. According to section III-4.2, for each transmission mode 3 there is a FIF04 stack of the previous n = int(T/A0+1 values of that mode's history source. Those FIFO stacks are implemented in RTNS as arrays with an index signalling the stack's top. As t—the travelling (delay) time— may be different for each mode, two additional arrays have been included in the _line structure: I An m-element array with the travelling (delay) times for each of the m-modes; I An m-element array with the m indices pointing to the m-history-stacks' tops.  I^  2 3^  these are the six pointers (3-phase line) of line[5] to six history values in the phase domain, in the corresponding gaLinks. —  4°1411111  pointers to hs's inters to node voltages  six pointers of line[5] to the voltages of its six nodes (inside the proper blocks).  Figure 31. History sources updating scheme in transmission lines.  With the last two items at the bottom of the stack, the simulator can interpolate for H(t-t), the needed value according to equations (I11-4.2. la, b). RTNS needs the line transformation matrix [Q] to convert node voltages into modal 3 4  The number of transmission modes is equal to the number of phases of the line. First-in-first-out stack data structure. These stacks behave in a curious way which cannot be fully described by an orthodox FIFO stack, though: the two data items at the bottom are popped out and interpolated. Next, the used-to-be next-to-the-last item is pushed back AT THE BOTTOM of the stack. Finally, a new data item is pushed on the top of the stack.  45  voltages before using Eq. (III-4.2.1 a, b) to obtain history sources. [Q] is included as a field in the _line structure. Finally, RTNS uses the [Q] matrix again to take the modal history sources to the phase domain into the corresponding gaLinks 's hs fields, Eq.(II-4.3.6). Up to this point, task (1) of RTNS, history sources updating according to section 2 of chapter III, has been successfully implemented.  7. Switching Operations A switching operation is stored in RTNS as a structure _swEvent. All switching events are collected in the array swEvent, see Fig. 32. typedef struct {  unsigned t; /*Instant for the event, in # of steps */ int sw; /*Which switch in the network operates in this event */ boolean openOperation; /*TRUE = this is an OPEN operation */ swEvent; seEvent *seEvent; /*Array of switching events (operations) */  An integer variable, next, points to the next switching event. In Fig. 32 the next event will occur at t = 120 At, the operation will be "close switch #5".  t  swEvent sw openOperation  ^  0  next  ^2  120  ^ ^ FALSE 5  Figure 32. Switching Events table (array "swEvent").  All the network's switches are grouped in the array sw whose elements are structures of type _switch, as shown below. Each switch is further identified by the block containing 46  it, and the position of the switch in that block (a number from zero to one less than the number of switches inside that block). typedef struct { boolean isClosed; /*Flag, TRUE = this switch is closed */ int blk; /*Block that contains this switch */ int pos; /*...position inside that block */ float current; /*Current through the switch */ boolean openPending; /*TRUE = an open operation has been */ /* requested waiting for current zero-crossing */ int numGaLinks; /*Total number of gaLinks connected to */ /* the "hot" node of the switch */ inGaLink *inGaLink; /*Array of gaLinks connected to the */ /* switch's "hot" node */ } _switch; switch sw; /*Array of all the switches in the system */  Figure 33 indicates that switch #5 is open right now, that it is the block-8's switch number 3 (the fourth in the block); and that the switch does not have any open operation pending.  SW  *sClosed  k pos penPending  ther fields  Figure 33. The network's switches array, "sw". A switching event can be either an open operation or a close operation. As seen in section 111-7, each block contains an integer variable swStatus —switches status— whose binary-representation's bits correspond to the switches in that block. Those bits indicate whether the corresponding block's switches are open or closed (see figure in section 47  111-7). The block keeps copy of its switches status in the variable newSwStatus, which is available for modification to the switching-event-processing routine GoSwEvent. To close (or to open) a switch in a particular block, GoSwEvent sets (or resets) the corresponding bit in that block's newSwStatus variable. The rest is done by the block's nodal-voltagesupdating-function (see the last paragraph of section 111-7). Closing or opening a switch appears to be a simple task for the GoSwEvent routine. Closing a switch is that simple indeed, but before resetting —to open— a switch's bit, Go-  SwEvent has to wait until current through the switch crosses zero.  Figure 34. GaLinks feeding current into the switch's "hot" node. To calculate the current through a switch, see Fig. 34, the currents contributed by all the gaLinks connected to one end of the switch (the "hot" node, selected by the preprocessor, see section IV-8) have to be added. Among the fields in the _switch structure is  numGaLinks, the number of gaLinks connected to the switch's hot node, and a variablelength array inGaLink whose elements are structures of the type  48  typedef struct boolean add; /*TRUE = this gaLink's current enters switch's hot node */ float *current; /*Point to the actual gaLink current field */ boolean *calcCurr; /*Points to the current calcCurr element's flag */ boolean prevCalcCurr; /*Old value of *calcCurr, to left it unchanged */ /* after the switches opens */ inGaLink;  Graphically, the data structures's relationships used by the RTNS to calculate currents through switches can be seen in Fig. 35. sw 0 1 2 3 4 5 6  o  -  o •  O O O  o)^o^-1c % R ^C^..5(^c .c Z t c^"Pe,^fa o^0 El.^CI^.c c R  E  Figure 35. Switch current calculation related data elements. 7.1 The GoSwEvent Routine  At the beginning of each time-step, RTNS calls the switching-event routine GoSwEvent. The routine checks if there is any switch with an open operation pending. If any such  switch is found, routine TryToOpen is invoked. Then GoSwEvent finds out if it is time for one or more switching events to take place, from the table swEvent; if this is the case, the routine, depending on whether the event is an open or a close operation, summons either MarkToOpenSw (which marks a switch as "pending to open") or CloseSw. . See the following code 49  void GoSwEvent( int t ) /* t = current time step */ { int i; for( i=0; i<numSwitdhes; i++ ) if( sw[i].openPending ) TryToOpenSw( i ); while( next<numSwitches && t>=swEvent[next].t ) { if( swEvent[next].openOperation ) MarkToOpen( swEvent[next].sw ); else CloseSw( swEvent[next].sw ); next++;  50  VI. TEST CASES  1. Generalities From more than forty cases used in testing and debugging the RTNS, two cases representative of the simulator's capabilities will be described in detail. The first case A (Fig. 36), was prepared in the general outline of the case reported in Ref. [14] for performance-comparison purposes. Very favourable results were obtained with RTNS for this case, as reported below. The second case B includes two sections of the system's transmission links where two 3-phase lines run along the same right-of-way, with mutual coupling between them requiring a 6-phase line representation (Fig. 37). In each case, the parts of the networks where no detailed behaviour was needed were replaced by their Thevenin's equivalent circuits. Every test case used in evaluating the simulator's accuracy and performance was also run with Microtran's EMTP, to make certain that the results between RTNS and EMTP agree.  2. Test Case A: 18 node/25 branch Case -  -  The one-line diagram for this 18-node/25-branch case , similar to the one reported in Ref. [14], can be seen in Fig. 36. This case resulted in an execution time per time-step of  51  38p.s, with RTNS running on the IBM RISC System/6000 Model 560. It is expected that this same case will run on the recently released IBM's Model 580, according to the 580's specifications, at around 27 µs/step (around 24 ps/step on the new Hewlett-Packard Apollo 9000 Series 700 workstations). The reported performance obtained in Ref. [14] with a case similar to this is between 50 gs/step and 100 µs/step (only a range is reported there). The simulator's input file for this case can be found in Appendix I of this thesis. sys-1  sys-2  fault  11V-0N--rEfl-044--1411—  -00A--1  Thevenin's coupled eq.  coupled eq.  Figure 36. Test Case A. 3. Test Case B: A 30-node/46-branch Case  This 30-node/46-branch case includes two sections of 6-phase multicircuit lines and a 3-phase line, as seen in the one-line diagram of Fig. 37 .  250 km  sys-1  1\ coupled  BUSS  FAUL1  k  fault  150 km  N c.  coupled  500 kV^  WOO  C2  100 km  sys-2  DI BUSS  FAUL2^BUS3^Bus4  Figure 37. Test Case B. Execution time for this case was 107 ps/step on the IBM RISC System/6000 Model 560 machine. According to specifications, the following results are to be expected: in the IBM Model 580, 77 ps/step; in HP Apollo 9000 Series 700, 65 p.s/step.  52  ^  To compare the accuracy of RTNS against Microtran EMIP, the results obtained by both programs were plotted on the same graphic. The close match between RTNS's output and EMTP's is made evident by Fig. 38, where voltage at bus FAUL1, phase b (see Fig. 37) as determined by the RTNS (solid line) and by the EMTP (dashed line) is shown. 1.5  I^11111/411111/1111M1111' 11111111111111/111111/1111111111 A  s 0.  z  0 —0.5  V  —1.0 —1.5  0.08  0.  •  0.00  "  0.08  "  0  s  o.se  Figure 38. Voltage at bus FAUL1, phase b, case No difference is evident visually, so the difference between the two mentioned outputs has been included, as a percentage, in Fig. 39. An isolated peak of less that 3% (occurring near a zero of the original curve) was removed to allow improved detail of the meaningful values. The curve in Fig. 39 presents a maximum difference between EMTP's results and RTNS's of 0.0025%. Input files for the real-time simulator and for Microtran's EMTP are included in Appendices II and III respectively.  ^0.5  ^ci)  Li^1.^I  1.0  ^ 0  r, —0.5 —1.0  -  F -1.5^-2.0  —2.5^.^  Figure 39. Difference, in percentage, between EMTP's output and RTNS's for Case B. 53  VII. CONCLUSIONS The main conclusion derived from this work is that it is indeed possible to build a real-time power network simulator for protective relay testing around an off-the-shelf workstation. The non-hardware-specific RTNS's core ANSI-C code makes it easy to move on to newer and faster machines', as they become available. Successful results were obtained on the IBM RISC System/6000 Model 560 rated at 91.1 specmarks. Model 580 of the same series (rated as 38% faster than the 560), already released, looks as the logical next host for the simulator's core RTNS. Some other alternatives have entered the market recently. DEC's ALPHA chip (150 MHz), rated at 120 specmark*89, offers a theoretical performance improvement of 32 %. The new HP Apollo 9000 Series 700 workstations, based on the superscalar PA-7100 chip, performs up to 147 specmark*89 (150.6 specfp92), which represents an improvement of 61%. These improved hardware platforms will enable the simulation of either larger systems —i.e. more detail in the neighbouring areas of the simulated network— or situations where the highest frequency of importance exceeds the present provisions and compromises. This enhanced performance passed on by more capable hardware hosts will also allow the inclusion of models for non-linear elements, keeping the detail of the simulation (At size) and the simulated network size within the boundaries outlined in this thesis.  Given the necessary real-time task handling of the operating systems available for that machine.  54  VIII. REFERENCES.  [1]  Dommel, Hermann W.: "Digital Computer Solution of Electromagnetic Transients in Single- and Multiphase Networks", IEEE Transactions on Power Apparatus and Systems, vol. PAS 88, No. 4, April 1969. pp.388 399. -  -  [2]  Marti, Jose R.; Lin, Jiming: "Suppression of Numerical Oscillations in the EMTP", IEEE/PES 1988 Summer Meeting. Paper 88 SM 732-0. Portland, 1988.  [3]  Pipes, Louis A.: "Applied Mathematics for Engineers and Physicists", (Book) Second Edition (International Student Edition) Ed. McGraw-Hill Book Company, Inc. New York, 1958.  [4]  Salazar, Frank E.: "ModelaciOn Modal de Lineas de TransmisiOn", (Thesis) Ed. Universidad Central de Venezuela. Caracas, 1982.  [5]  Wedepohl, L.M.: "Application of Matrix Methods to the Solution of Travelling-Wave Phenomena in Polyphase Systems", Proc. LEE. Vol. 110, No. 12, Dec. 1963, pp. 2200 2210. -  [6]  Hedman, D.E.: "Propagation on Overhead Transmission Lines, I Theory of Modal Analysis", IEEE Trans. PAS, Dec. 1964, pp. 200 205. —  -  [7]  Woodruff, L.F.: "Principles of Electric Power Transmission", (Book) Second Edition Thirteenth Printing, Ed. John Wiley & Sons, Inc. New York, 1956. -  [8]  H. W. Dommel, "EMU Theory Book, Second Edition", Microtran Power System Analysis Corporation, Vancouver, British Columbia, May 1992.  [9]  Marti, J.R.; Garrett, B.W.; Dommel H.W.; Wedepohl, L.M.: "Transients Simulation in Power Systems: Frequency Domain and Time Domain Analysis", Power System Planning & Operation Section, Canadian Electrical Association. Montreal, Quebec, March 1985.  )  [10] Dommel, H.W.: "ELEC 551 Class Notes, Winter Session 1992", The University of British Columbia, Department of Electrical Engineering. Notes taken by the author of this thesis report. [11] Chirlian, Paul M.: "Basic Network Theoly", (Book) McGraw-Hill. New York, 1969. [12] Dommel, H.W.: "A Current Transformer Model", The University of British Columbia. Department of Electrical Engineering. Internal Report, (1991). [13] J. R. Marti, "Accurate modelling of frequency-dependent transmission lines in electromagnetic transient simulations", IEEE Trans. on Power Apparatus and Systems, Vol. PAS-101, No. 1, pp. 147-157, January 1982. 55  [14] P. G. McLaren, R. Kuffel, R. Wierckx, J. Giesbrecht, L. Arendt, "A real time digital simulator for testing relays", IEEE Trans. on PWRD, Vol. 7, No. 1, pp. 207 213, January 1992. -  [15] R. C. Durie and C. Pottle, "An extensible real time digital transient network analyzer", IEEE Trans. PWRS, Paper WM 175-0, Winter Meeting, Jan. 1992. -  [16] D. M. Falcao, E. Kaszkurewicz, and H. L. Almeida, "Application of parallel processing techniques to the simulation of power system electromagnetic transients", IEEE Trans. on PWRS, Paper WM 287-3, Winter Meeting, Jan. 1992. [17] S. Y. Lee, H. D. Chiang, K. G. Lee, and B. Y. Ku, "Parallel power system transient stability analysis on hypercube multiprocessors", IEEE Trans. on Power Systems, Vol. 6, No. 3, pp. 1337-1342, August 1991. [18] R. Comerford, "How DEC developed Alpha", IEEE Spectrum, pp. 26-31, July 1992. [19] Marti, J. R.: "A Potential Transformer Non linear Model", The University of British Columbia. Department of Electrical Engineering. Internal Report, (1991). -  [20] Marti, J. R: "Simplified Updating Schemes for EMTP's Models", The University of British Columbia. Department of Electrical Engineering. Internal Report, (1991). [21] Dommel, H.W.: "Simulating an MOV operation ", The University of British Columbia. Department of Electrical Engineering. Internal Report, (1991). [22] Lawrence, P.R., Mauch, K.: "Real Time Microcomputer System Design: An Introduction," (Book) McGraw Hill Book Company. New York, 1987. -  -  [23] Brawer, S.: "Introduction to Parallel Programming," (Book) Academic Press, Inc. Boston 1989. [25] Haviland, K., Salama, B.: "UNIXrm System Programming", (Book) Addison-Wesley Publishing Company, Workingham, 1987. [26] Polychronopoulos, C.D.: "Parallel Programming and Compilers," (Book) Kluwer Academic Publishers, Boston 1988. [24] IBM-International Technical Support Centers: "AIX version 3.1. RISC System/6000 as a Real Time System". IBM's International Technical Support Center, Austin, 1991. -  56  APPENDIX I TEST CASE A. INPUT FILE  57  ^  +-  Input file for the Real Time preprocessor (Format: RTNS-PP V.3.02) Case: Case A. Master Thesis Report. File: CASE-A.RTP Date: Dec. 26, 1992. Author: Luis R. Linares Comments: .BEGIN FILE .BEGIN GENERAL-DAM deltaT: 100e-6 totalTime: 100e-3 numLumped: 7 numLines: 3 numSources: 6 numOutNodes: 3 .END GENERAL-DAM .BEGIN LUMPED R le-20 N7 GROUND calcCurr: no L 1.739 N1 N13 calcCurr: no L 1.739 N2 N14 calcCurr: no L 1.739 N3 N15 calcCurr: no L 3.685 N10 N16 calcCurr: no L 3.685 Nil N17 calcCurr: no L 3.685 N12 N18 calcCurr: no .END LUMPED .BEGIN LINES .BEGIN LINE-0 phases: 3 Zc: 637.9 278.7 328.1 delay: 0.5e-3 0.35e-3 0.35e-3 nodes: N1 no N4 no N2 no N5 no N3 no N6 no q-matrix: 0.592428855 -0.41233620 -0.70710678 0.545945520^0.81237774^0.00000000 0.592428855 -0.41233620^0.70710678 .END LINE-0 .BEGIN LINE-1 phases: 3 Zc: 637.9 278.7 328.1 delay: 0.5e-3 0.35e-3 0.35e-3 nodes: N4 no N7 no N5 no N8 no N6 no N9 no q-matrix: 0.592428855 -0. 41233620 -0.70710678 0.00000000 0. 81237774 0.545945520 0.70710678 0.592428855 -0. 41233620 .END LINE-1 .BEGIN LINE-2 phases: 3 Zc: 637.9 278.7 328.1 delay: 0.5e-3 0.35e-3 0.35e-3 nodes: N7 no N10 no N8 no N11 no N9 no N12 no q-matrix: 0.592428855 -0.41233620 -0.70710678 0.545945520^0.81237774^0.00000000 0.592428855 -0.41233620^0.70710678 .END LINE-2 .END LINES  58  .BEGIN SOURCES 100000^0 N13 100000 -120 N14 100000 +120 N15 100000^0 N16 100000 -120 N17 100000 +120 N18 .END SOURCES .BEGIN SWITCHES total: 0 .END SWITCHES .BEGIN OUTPUT N7 N8 N9 .END OUTPUT .END FILE  59  APPENDIX II TEST CASE B. INPUT FILE  60  +-  Input file for the Real Time preprocessor (Format: RTNS-PP V.3.02) Case: Case B. Master Thesis Report. File: CASE-B.RTP Date: Dec.13, 1992 Author: Luis R. Linares Comments:  +-  .BEGIN FILE .BEGIN GENERAL-DATA deltaT: 100e-6 totalTime: 100e-3 numLumped: 16 numLines: 3 numSources: 6 numOutNodes: 3 .END GENERAL-DATA .BEGIN LUMPED R 6.5 rigl rigal calcCurr: no MOV: no R 6.5 rig2 riga2 calcCurr: no MOV: no R 6.5 rig3 riga3 calcCurr: no MOV: no GROUND calcCurr: no MOV: no R le-20 bl L 345 rigal el^calcCurr: no MOV: no L 345 riga2 e2^calcCurr: no NOV: no L 345 riga3 e3^calcCurr: no MOV: no L 31.11 lefl al^calcCurr: no MOV: no L 31.11 lef2 a2^calcCurr: no MOV: no L 31.11 lef3 a3^calcCurr: no MOV: no dl^calcCurr: no MOV: yes 250000 C 66.00 cl C 66.00 c2^d2^calccurr: no mov: yes 250000 C 66.00 c3^d3^calccurr: no mov: yes 250000 C 66.00 c4^dl^calccurr: no mov: yes 250000 C 66.00 c5^d2^calccurr: no mov: yes 250000 C 66.00 c6^d3^calccurr: no mov: yes 250000 .END LUMPED .BEGIN LINES .BEGIN LINE-0 phases: 3 Zc: 621.9 275.3 290.9 delay: 0.5e-3 0.3e-3 0.3e-3 nodes: dl no el no d2 no e2 no d3 no e3 no q-matrix: 0.58702696 -0.40302458 0.70710678 0.55427582 0.82086139 0.00000000 0.58702696 -0.40302458 -0.70710678 .END LINE-0 .BEGIN LINE-1 phases: 6 Zc: 987.9 328.4 275.9 222.6 237.2 244.1 delay: 1.4e-3 0.9e-3 0.9e-3 0.8e-3 0.8e-3 0.8e-3 nodes: al no bl no a2 no b2 no a3 no b3 no al no b4 no a2 no b5 no a3 no b6 no q-matrix: 0.51146427 -0.48902472 -0.55148454 0.23244529 -0.41893693 -0.28289203 0.33293163 0.01379915 -0.39499073 -0.48191931 0.26900888 0.58057410 0.35712111 0.51054438 -0.16496383 0.45421967 0.48894408 -0.28793145 0.35712111 0.51054438 0.16496383 -0.45421967 -0.48894408 -0.28793145 0.33293163 0.01379915 0.39499073 0.48191931 -0.26900888 0.58057410  61  0.51146427 -0.48902472 0.55148454 -0.23244529 0.41893693 -0.28289203  .END LINE-1 .BEGIN LINE-2 phases: 6 Zc: 987.9 328.4 275.9 222.6 237.2 244.1 delay: 0.8e-3 0.5e-3 0.5e-3 0.5e-3 0.5e-3 0.5e-3 nodes: bl no cl no b2 no c2 no b3 no c3 no b4 no c4 no b5 no c5 no b6 no c6 no q-matrix: 0.51146427 0.33293163 0.35712111 0.35712111 0.33293163 0.51146427  -0.48902472 -0.55148454 0.23244529 -0.41893693 -0.28289203 0.01379915 -0.39499073 -0.48191931 0.26900888 0.58057410 0.51054438 -0.16496383 0.45421967 0.48894408 -0.28793145 0.51054438 0.16496383 -0.45421967 -0.48894408 -0.28793145 0.01379915 0.39499073 0.48191931 -0.26900888 0.58057410 -0.48902472 0.55148454 -0.23244529 0.41893693 -0.28289203  .END LINE-2 .END LINES .BEGIN SOURCES 408248^10^lefl 408248 130^left 408248 -110^lef3 408248^10^rigl 408248 130^rig2 408248 -110^rig3 .END SOURCES .BEGIN SWITCHES total: 0 .END SWITCHES .BEGIN OUTPUT b2 c2 d2 .END OUTPUT .END FILE  62  APPENDIX M TEST CASE B. EMTP INPUT FILE.  63  ^  *  .^. Case identification card • •^•^•^•^• IFFF-1: Test Case B. Master Thesis Report. L.Linares *  * *  . Time card 100e-6^100e-3 1^  1  . Lumped RLC branch .^ • •^• lefl^al^ 31.11 lef2^a2^ 31.11 lef3^a3^ 31.11 rigl^el^6.5 345.0 rig2^e2^6.5 345.0 rig3^e3^6.5 345.0 66.0 cl^dl^ 66.0 c2^d2^ 66.0 c3^d3^ 66.0 c4^dl^ 66.0 c5^d2^ 66.0 c6^d3^ bl^ le-20 C Transmission line 1 (between bus A and fault) C R' in ohms/km, Zc in ohms, v in km/s, Length in km 9.879E+02 1.400E-03 2.500E+02 2 0 6 al bl -1 3.284E+02 0.900E-03 2.500E+02 2 0 6 b2 -2 a2 2.759E+02 0.900E-03 2.500E+02 2 0 6 b3 -3 a3 2.226E+02 0.800E-03 2.500E+02 2 0 6 al b4 -4 2.372E+02 0.800E-03 2.500E+02 2 0 6 b5 -5 a2 2.441E+02 0.800E-03 2.500E+02 2 0 6 -6 a3 b6 0.51146427 -0.48902472 -0.55148454 0.23244529 -0.41893693 -0.28289203 0.33293163 0.01379915 -0.39499073 -0.48191931 0.26900888 0.58057410 0.35712111 0.51054438 -0.16496383 0.45421967 0.48894408 -0.28793145 0.35712111 0.51054438 0.16496383 -0.45421967 -0.48894408 -0.28793145 0.33293163 0.01379915 0.39499073 0.48191931 -0.26900888 0.58057410 0.51146427 -0.48902472 0.55148454 -0.23244529 0.41893693 -0.28289203 C Transmission line 2 (between fault and bus C) C R' in ohms/km, Zc in ohms, v in km/s, Length in km 9.879E+02 0.800E-03 1.500E+02 2 0 6 -1 bl cl 3.284E+02 0.500E-03 1.500E+02 2 0 6 -2 b2 c2 2.759E+02 0.500E-03 1.500E+02 2 0 6 b3 -3 c3 2.226E+02 0.500E-03 1.500E+02 2 0 6 c4 -4 b4 2.372E+02 0.500E-03 1.500E+02 2 0 6 c5 -5 b5 2.441E+02 0.500E-03 1.500E+02 2 0 6 b6 c6 -6 0.51146427 -0.48902472 -0.55148454 0.23244529 -0.41893693 -0.28289203 0.33293163 0.01379915 -0.39499073 -0.48191931 0.26900888 0.58057410 0.35712111 0.51054438 -0.16496383 0.45421967 0.48894408 -0.28793145 0.35712111 0.51054438 0.16496383 -0.45421967 -0.48894408 -0.28793145 0.33293163 0.01379915 0.39499073 0.48191931 -0.26900888 0.58057410 0.51146427 -0.48902472 0.55148454 -0.23244529 0.41893693 -0.28289203 C Line 3 (between bus D and the external system) C R' in ohms/km, Zc in ohms, v in km/s, Length in km 6.219E+02 0.500E-03 1.000E+02 2 0 3 -1^dl el 2.753E+02 0.300E-03 1.000E+02 2 0 3 -2^d2 e2 2.909E+02 0.300E-03 1.000E+02 2 0 3 e3 -3^d3 0.58702696 -0.40302458 0.70710678 0.55427582 0.82086139 0.00000000 0.58702696 -0.40302458 -0.70710678 *  *  64  1 1 1 1 1 1  1 1 1 1 1 1  1 1 1  * 14 14 14 14 14 14  .^. lefl left lef3 rigl rig2 rig3 b2  .^.^. 408248.0 408248.0 408248.0 408248.0 408248.0 408248.0  . Voltage or current sources 60 10.0 60 130.0 60 250.0 60 10.0 60 130.0 60 250.0  


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