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Testing for floating gates defects in CMOS circuits Rafiq, Sumbal 1998-12-31

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Testing for Floating Gates Defects in CMOS Circuits By Sumbal Rafiq  B.E., University of Engineering and Technology, Lahore, Pakistan, 1994  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF T H E REQUIREMENT FOR T H E DEGREE OF MASTER OF APPLIED SCIENCE in T H E FACULTY OF GRADUATE STUDIES ELECTRICAL AND COMPUTER ENGINEERING  We accept this thesis as conforming to the required standard  T H E UNIVERSITY OF BRITISH COLUMBIA July 1998 © Sumbal Rafiq, 1998  In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, 1 agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department  or  by his or  her representatives.  It  is understood  that copying or  publication of this thesis for financial gain shall not be allowed without my written permission.  EhcPulcA  Department of  The University of British Columbia Vancouver, Canada Date  DE-6 (2/88)  A  A  W  T  1\,  f^ff-  I Pfimpnfo^ £ ^ 3 f W ^ J  Abstract  Abstract This thesis studies the detectability of MOS floating gate transistor faults considering classical Static Voltage, Dynamic Voltage and Static Current testing strategies. The behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters. A floating gate fault can induce abnormal logic values, additional delays, or increased power supply current. Consequently, classical test strategies can only detect floating gate faults for a given range of the unpredictable parameter. Here, a new test scheme is proposed, which allows a considerable current to flow in the faulty logic gate in stable state, making the circuit with a floating gate IDDQ testable. It is shown that a combination of voltage and current testing can ensure complete detection of the floating gate defects, i.e., regardless of the unpredictable parameters. Analysis with increasing initial charge on the floating gate transistor shows how the detectability intervals become smaller for the voltage testing strategies and increase for the static current strategy.  Keywords: Floating gate testing, I DQ testing, gate opens, floating gate defect model. D  The University of British Columbia  ii  Table of Contents  Table of Contents  Abstract  ...ii  List of Tables  vi  List of Figures  vw  Acknowledgements  ix  1 Introduction  1  1.1 The Need for Testing  1  1.2 What is Testing ?  3  1.3 Faults and Errors  4  1.4 Fault Models  5  1.4.1 Stuck-at Fault Model  5  1.4.2 Short-Circuit and Open Circuit Fault Models  7  1.4.3 Bridging Fault Model  9  1.4.4 Delay Fault Model  9  1.5 Test Strategies  10  1.5.1 Static Voltage Strategy (SV Strategy)  11  1.5.2 Dynamic Voltage Strategy (DV Strategy)  11  1.5.3 Static Current Strategy (SC Strategy)  11  1.6 Fault Coverage  The University of British Columbia  12  iii  Table of Contents  1.7 Thesis Motivation  13  1.8 Scope of the Thesis  17  2 Electrical Analysis of a Floating Gate Transistor  20  2.1  The Floating Gate Transistor Fault  21  2.2  Electrical Analysis of a Floating Gate Fault  22  3 Floating Gate Fault Detection  3.1  Introduction  3.2  Detection of a Floating Gate Fault  28  28 29  3.2.1  Static Voltage (SV) Testing Strategy  32  3.2.2  Dynamic Voltage (DV) Testing Strategy  34  3.2.3  Static Current (SC) Testing Strategy  36  4 Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  4.1  Introduction  4.2  Test Strategy Sensitivity to Floating Gate Fault Parameter  4.3  Effect of the FGT Initial Charge on the Detectability Intervals  42 43 45  4.3.1  The Source of Residual Charge  45  4.3.2  Detectability Intervals with an Initial Charge on the FGT  47  4.4  42  Effect of the Metal-Poly Capacitance C  mp  and Metal Potential V on the m  Detectability Intervals  51  4.4.1  Electrical Analysis of the Floating Gate Transistor for C  4.4.2  Dependence of V on the Detectability Intervals m  The University of British Columbia  mp  and V  m  52 56  iv  Table of Contents  4.4.3  Dependence of the Detectability Intervals on C  m p  60  4.4.3.1 Detactability Intervals for SV and DV Test Strategies  60  4.4.3.2  64  Detactability Intervals for SC Test Strategy  5 Conclusions and Future Work  68  5.1  Conclusions  68  5.2  Future Work  70  6 References  71  Appendix A: Model Parameters for the Transistors Used in Simulations Appendix B: Hspice Netlist  The University of British Columbia  76 78  v  List of Tables  List of Tables  Table 1.1 Truth table for the NAND gate Table 4.1 Summary of the results for V and C m  The University of British Columbia  7 m p  67  vi  List of Figures  List of Figures  Figure 1.1 Testing of a device  3  Figure 1.2 A two-input CMOS N A N D gate  6  Figure 2.1. A floating gate transistor (FGT)  21  Figure 2.2. Floating gate n-MOS transistor model  23  Figure 2.3. Equivalent model of a floating gate transistor with V = Vss and V = V , m  m  respectively  d  25  Figure 3.1. An interconnect open in a N O R gate  29  Figure 3.2: Faulty behavior of the NOR gate  30  Figure 3.3: Static Voltage behavior of a floating gate transistor  33  Figure 3.4: Dynamic behavior of an FGT  36  Figure 3.5 (a): A faulty N O R gate circuit  37  Figure 3.5 (b): Current testing (SC) for FGT N O R gate  38  Figure 3.6: Change in the floating gate voltage and current by sweeping C t,; C =250aF p  mp  40 Figure 3.7: Current versus C b characteristics of an FGT  41  Figure 4.1: FGT Fault Detectability Intervals  44  P  Figure 4.2: Change in the output voltage of the N O R gate with an increased initial charge Q  47  0  Figure 4.3: Detectability intervals for Static Voltage strategy with V =0.4V o  The University of British Columbia  48  vii  List of Figures  Figure 4.4: Detectability intervals for Dynamic Voltage strategy with V =0.4V  48  o  Figure 4.5: Change in IDDQ current by an increase in initial charge on the floating gate..49 Figure 4.6: Change in the detectability interval for Static Current Strategy with V =0.4V o  :  50  Figure 4.7: Change in the fault detectability intervals by trapped charges Q on the FGT. Q  51 Figure 4.8: Electrical equivalent circuit of the n-MOS FGT of a faulty NOR gate  52  Figure 4.9: Input vectors for the faulty N O R gate  56  Figure 4.10: Vfi i and Vf plots with the application of V at different instances na  g  m  Figure 4.11: Increase in the detectability intervals by controlling V to Vss volts m  Figure 4.12: Vf, ] variation of a faulty NOR gate for different values of C na  Figure 4.13: V f i versus C ma  Figure 4.14: V and f g  Figure 4.15:  IDDQ  m p  and C b for faulty NOR gate ( V = VDD) P  m  simulation results for different C  IDDQ versus C b P  for varying C  The University of British Columbia  m p  m p  values  of a faulty NOR gate  m p  58 60  (C b =5fF) 61 P  63 64 66  viii  Acknowledgements  Acknowledgements No work is a product of the sole effort of the author. My thesis work could not have been completed without the considerable knowledge and deep understanding of both theoretical and practical issues of my professor / supervisor Dr. Andre Ivanov. I am greatly indebted to him for his guidance to get this ceaseless encouragement and moral support. He has been generous and unstinting in his advice and suggestions - his critique kind, but firm. I am most grateful for his time and patience. In addition to technical critique, he exercised an unerring eye for misleading phraseology and made excellent constructive suggestions for rewording.  In writing the thesis, I have also had the benefit and privilege of stimulating discussions and penetrating criticism of my co-supervisor Dr. Michell Renovell of Universite De Montpellier, France. I am particularly eager to acknowledge my indebtedness to him. It would be hard to overestimate his contributions to this thesis. I have learnt from him in multifarious ways. His comments helped sharpen my thinking and played a central role in developing this thesis.  I also gratefully acknowledge the intellectual contribution of Dr. Naveed A. Sherwani of Intel Corporation. His perceptive comments enhanced my understanding. He offered encouragement and useful comments on the manuscript in its various stages. He also introduced me to the field of physical design and has been my unofficial mentor  The University of British Columbia  ix  Acknowledgements  eversince. I thank him for his guidance, support, and patience. His enthusiasm in working with ideas has helped clarify my thinking in innumerable ways.  I would also like to extend my heartfelt gratitude to Professor Dr. Michael S. Davies for his continued support and help.  In addition, I thank Mr. Sassan Tabatabaei for his help and assistance. His contributions for the designed chips are especially acknowledged. I would also like to thank Mr. Roozbeh Mehrabadi for his help in suggesting and providing solutions to my VLSI tool problems.  I  would  like  to acknowledge  Micronet,  NSERC,  and Canadian  Microelectronics Corporation for providing partial financial support for this research.  I also owe a great debt to my family, particularly my parents, for their relentless support, which added to my peace of mind and productivity as I worked on this study.  Sumbal Rafiq  The University of British Columbia  x  C h a p t e r  1  I n t r o d u c t i o n  1.1  The Need for Testing  Very Large Scale Integration (VLSI) has enabled us to implement very complex circuits on a single chip. Complementary Metal Oxide Semiconductor (CMOS) technology has played a dominant role in allowing this to happen. The advantages of VLSI circuits are obvious. However, they do pose a problem. The problem is how do we test VLSI chips to ensure that they function as they are supposed to. With chips containing million or more transistors, testing has become an increasing part of the time it takes from conception to marketing of a chip. The problem can only become severe in the future.  The yield of a particular IC is the number of good die divided by the total number of die per wafer [38]. Due to the complexity of the manufacturing process not all die on the wafer correctly operate. Small imperfections in starting material, processing steps, or in  The University of British Columbia  1  Chapter 1 Introduction  photomasking may result in bridged connections or missing features. It is the aim of a test procedure to determine which die are good and should be used in end systems. Testing a die (chip) can occur: •  at the wafer level  •  at the packaged-chip level  •  at the board level  •  at the system level  •  in the field.  If the faults can be detected at the wafer level, the cost of manufacturing is kept the lowest. In some circumstances, the cost to develop adequate tests at the wafer level, mixed-signal requirements, or speed considerations may require that further testing be done at the packaged-chip level or the board level. A component vendor can only test at the wafer or chip level. Special systems, such as satellite-borne electronics, might be tested exhaustively at the system level.  IC tests may fall into two main categories. The first set of tests verifies that the chip performs its intended function; e.g., that it performs a digital filter function, acts as a microprocessor, or communicates using a particular protocol. In other words, these tests assert that all the gates in the chip, acting in concert, achieve a desired function. These tests are usually used early in the design cycle to verify the functionality of the circuit. These are called the functionality tests. They may be lumped into the verification activity.  The University of British Columbia  2  Chapter 1 Introduction  The second set of tests verifies that every gate and the register in the chip functions correctly. These test are used after the chip is manufactured to verify that the silicon is intact. They are called manufacturing tests. In many cases these two set of tests may be one and the same, although the natural flow of design usually has a designer considering function before manufacturing concerns.  CMOS has been the dominant technology for the last few years and is expected to remain dominant for many years to come. However, CMOS poses many new challenges in the area of testing. Overcoming these challenges is essential to the well-being of the semiconductor industry [39].  1.2 What is Testing ? Testing in the context of digital systems is defined to be the process by which a defect in the system can be exposed. The defect can occur at the time of manufacture or when the system is in the field. In Figure 1.1 a device under test (DUT) is shown to which test vectors are applied. The resulting response from the device is monitored. If the correct response is known then we can determine if the DUT has a defect or not by comparing the responses. Test Vectors  w  DUT  •-  w  Response  Figure 1.1 Testing of a device  The University of British Columbia  3  Chapter 1 Introduction  Of course, it is assumed that one of the test vectors exposes the defect. For this assumption to be reasonable, the set of test vectors should include vectors for most, if not all, of the defects that are likely to occur.  1.3 Faults and Errors  A fault is an actual defect that occurs in the device. When a vector is applied to the faulty device which produces an incorrect response, an error is said to have occurred. For example, if a line in a chip breaks, a fault has occurred. When this fault is exposed at the circuit outputs by some input vector, an error results. In this case the error is manifested as an incorrect logic value at one or more of the circuit outputs [32]. However, monitoring the logic values is not the only way to determine if an error has occurred. There may be faults which cause the circuit to draw excessively large current when a particular vector is applied, but they may not result in an incorrect logic value at the outputs. In this case the error is manifested as a drastic change in the value of the current [10].  A fault which can change the logic value on a line in the circuit from logic 0 to logic 1 or vice versa is called a logical fault. On the other hand if the fault causes some parameters of the circuit to change, such as the current drawn by the circuit, then it is termed parametric [19].  The University of British Columbia  4  Chapter 1 Introduction  A fault can also be categorized on the basis of duration for which it lasts. The three broad categories are (a) transient, (b) intermittent, and (c) permanent. A fault is called transient if it is only present for a small duration. A fault is intermittent if it appears regularly but is not present continuously. If a fault is present continuously, it is called permanent.  1.4 Fault Models  In order to deal with the existence of good and bad ICs it is necessary to propose a fault model, i.e., a model for how faults occur and their impact on circuits. If we try to derive test vectors for every possible physical failure in a V L S I chip, the problem would soon become unmanageable. To successfully tackle the problem, we represent the physical failures in a chip at a higher level with the help of a fault model.  Any one fault from the fault model may represent many physical failures. Thus, the use of fault models speeds up the test generation process. The fault models most commonly used for CMOS circuits are (a) Stuck-at fault model, and (b) Short-Circuit and Opencircuit fault model [39]. Another fault model which is increasingly being paid attention is the delay fault model [7].  1.4.1 Stuck-at Fault Model  The fault model which has found the most widespread use in the industry is the stuck-at fault model [2]. In this model it is assumed that the fault causes a line in the circuit to  The University of British Columbia  5  Chapter 1 Introduction  behave as if it is permanently at logic 0 or logic 1. If the line is permanently at logic 0, it is said to be stuck-at 0 (s-a-0), otherwise if it is permanently at logic 1 it is said to be stuck-at 1 (s-a-1).  Consider the two-input static CMOS N A N D gate in Figure 1.2.  1  'DD  -x-  *2  Ol  Si  * VSS  Figure 1.2 A two-input CMOS N A N D gate  Let us first examine the short denoted si. This short forces the line fed by input X2 to behave in a s-a-0 fashion. Similarly, the short denoted by S2 forces the line fed by input xi to behave in a s-a-1 fashion. In Table 1.1 the fault-free output is denoted as f whereas the outputs in the presence of shorts si and S2 are denoted as fi and f2 respectively. From this table one can see that the vectors (xi, X2) = 11 detects short Si and the vector (xi, X2) = 01 detects short S2.  The University of British Columbia  6  Chapter 1 Introduction  X2  f  0  0  1  1  0  1  1  1  1  0  1  1  1  1  0  fl  1  f  2  1 0 1 0  Table 1.1 Truth table for the N A N D gate  1.4.2 Short-Circuit and Open Circuit Fault Models  Other fault models include "stuck-open" or "shorted" models [38, 39]. If a fault causes a transistor to conduct continuously, the transistor is said to be "stuck-on". When a transistor is rendered non-conducting by a fault, it is said to be "stuck-open". Consider the break denoted by oi in Figure 1.2. This break prevents transistor 4 from conducting. Thus, it results in a stuck-open fault in transistor 4. Suppose that the vectors shown in Table 1.1 are applied in the order shown. Even when Oi is present the resultant output will still be the same as fault-free output f. This can be verified as follows. When 00 and 01 are applied, transistor 3 conducts, resulting in f = 1. When the third vector 10 is applied, neither the p-MOS network nor the n-MOS network can conduct. Therefore, the previous logic value is retained at the output node. Finally, when 11 is applied, the nMOS network conducts and f becomes 0.  The University of British Columbia  7  Chapter 1 Introduction  A stuck-open fault may cause even a combinational circuit to behave in a sequential fashion [20, 23]. Thus, in order to detect a stuck-open fault, a sequence of vectors is required. The reason the stuck-open fault in transistor 4 did not get detected above is that the proper sequence of vectors was not fed to the circuit. It usually requires a sequence of two vectors to detect a stuck-open fault. The first vector is called an initialization vector and the second vector is called the test vector. The sequence of these two vectors is referred to as the two-pattern test [16]. The two-pattern test for the stuck-open fault in transistor 4 is <11,10>. The vector 11 initializes the output node to 0. When 10 is applied next, the output node remains at 0 and the fault is detected.  It should be mentioned that the two-pattern tests should be applied at a rate higher than that associated with the leakage current time constants. Otherwise, a correct transition may be observed at the output even in the presence of the fault [23]. Opens such as oi in Fig. 1.2, do not make the transistor permanently non-conducting. Due to the leakage currents, the node f may eventually charge to logic 1. However, the more important point is that i f the two-pattern test is applied rapidly, the open oj will still be detected. So it is not necessary to assume that the transistor is permanently non-conducting for the success of two-pattern testing.  The University of British Columbia  8  Chapter I Introduction  1.4.3 Bridging Fault Model  A bridging fault is generally defined to be a short among two or more signal lines in the circuit [11, 32, 33]. Such a short could occur, for example, due to defective masking or etching, aluminum migration, breakdown of insulators, etc. A bridging fault can be broadly classified as either (a) feedback bridging fault, or (b) non-feedback bridging fault. If a bridging fault creates one or more feedback loops, it is referred to as a feedback bridging fault, otherwise it is referred to as a non-feedback bridging fault.  1.4.4 Delay Fault Model  Even if a circuit is free of structural defects, it may not propagate a signal in the time allowed. This gives rise to a delay fault [39]. The voltage on the faulty line could either be slow-to-rise (STR) or slow-to-fall (STF). Two types of delay fault models are generally used: (a) gate delay model, and (b) path delay model. The gate delay model models defects at the inputs or the outputs of a gate. On the other hand, the path delay model models those defects which cause cumulative propagation delays along a circuit path to exceed the specified value. Each model has its own advantages and disadvantages. The path delay model requires the enumeration of circuit paths from all primary inputs to all circuit outputs. This causes an explosion in the number of paths that have to be considered, thereby increasing the number of tests and the test generation time.  The University of British Columbia  9  Chapter 1 Introduction  The gate delay model does not have this problem. However, it can not model delay defects which are not necessarily localized to single gates.  1.5 Test Strategies  With today's manufacturing technology, it is not possible to eliminate all defects and ensure that every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to the customer. Most companies adopt individual approaches since there is not yet general agreement on an optimal (low defect level) test strategy that can be quantified and accepted by both customer and supplier. Most companies use some but not all of the following three test strategies [6]:  1. Static Voltage Strategy (SV strategy) 2. Dynamic Voltage Strategy (DV strategy) 3. Static Current Strategy (SC strategy)  The decision to use some of these three strategies is usually done according to the classical cost / efficiency trade-off.  The University of British Columbia  10  Chapter I Introduction  1.5.1 Static Voltage Strategy (SV Strategy)  The Static Voltage strategy (SV strategy) refers to any test using voltage sensing for verifying logic functionality regardless of clock frequency. S V tests provide boolean controllability (a measure of the ease of  setting the node to a 1 or 0 state) and  observability (the degree to which one can observe that node at the outputs of an integrated circuit) of the considered fault.  1.5.2 Dynamic Voltage Strategy (DV Strategy)  The Dynamic Voltage or Delay strategy (DV strategy) refers to any test using voltage sensing but taking into account the clock frequency. The D V technique works on a gate level description and uses two vector pairs to measure circuit propagation delays. The first vector (initialization vector) sets the logic output and the second one (state change vector) provides controllability and observability for the targeted path or gate.  1.5.3 Static Current Strategy (SC Strategy)  The Static Current Strategy (SC strategy) measures the quiescent VDD power supply current of the IC. This relies on the fact that when a complementary CMOS logic gate is not switching, it draws no D C current (except for leakage) [1]. When a fault such as a short occurs, for some combination of input conditions a measurable D C IDD will flow.  The University of British Columbia  11  Chapter 1 Introduction  Testing consists of applying the normal vectors, allowing the signals to settle, and then measuring IDD- TO be effective any circuits that draw D C power such as pseudo-nMOS gates or analog circuits have to be disabled. Because many circuits now require SLEEP modes to reduce power, this may not be a substantial overhead [1, 10, 16].  Because current measuring is slow, the test must be run slower than normal, thus increasing test time. However, this technique gives a form of indirect massive observability at little circuit overhead. The SC test, therefore, just has to provide the boolean controllability of the considered fault because observability is inherently guaranteed.  1.6 Fault Coverage  A measure of goodness of a test program is the amount of fault coverage it achieves; that is, for the vectors applied, what percentage of the chip's internal nodes were checked. Conceptually, the way in which the stuck fault coverage is calculated is as follows. Each circuit node is taken in sequence and held to 0 (s-a-0), and the circuit is simulated, comparing the chip outputs with a known "good machine" - a circuit with nodes artificially set to 0 (or 1). When a discrepancy is detected between the "faulty machine" and the good machine, the fault is marked as detected and the simulation is stopped [38, 39]. This is repeated for setting the node to 1 (s-a-1). In turn, every node is thus stuck at 1 and 0, sequentially. The total number of nodes that, when set to 0 or 1, do result in the  The University of British Columbia  12  Chapter I Introduction  detection of the fault, divided by the total number of nodes in the circuit, is called the percentage-fault  coverage. This method of fault analysis is called sequential fault  grading.  1.7 Thesis Motivation  The quality of a test set largely depends on the "realistic" characteristics of the fault model. It was found that a test with 100% fault coverage will only provide as little as 10% fault coverage i f another fault model is used [5]. In the last decade, it became clear that the knowledge of the electrical and physical mechanisms that cause faults must be taken into account on establishing accurate fault models [32], while the traditional stuckat fault models are not sufficient to model behavior of faults in MOS circuits [3,8,12,17,33].  The fault models with the insight into the physics of processing defects and mask layouts sometimes are referred to as Realistic Fault Models [34]. Currently, there are a few methods and systems available which can be used to analyze the realistic faults for a given layout. Most of the effort has been put into the study of shorts / bridging faults. However, it seems that the analysis of realistic opens attracts less attention. The importance of the opens should be recognized, however, by the following facts:  The University of British Columbia  13  Chapter 1 Introduction  1. Although opens are not as frequent as bridges [28], the probability of the occurrence of opens can be large [8, 17, 19]. For instance, missing contacts causing opens are one of the most likely defect mechanisms.  2. The random defects cause opens more likely than bridges in one products than in other products [29, 30] or in one period of time than in rest of the time [2]. It is reported experimentally that chips passed single stuck-at (SSA), IDDQ or even delay test pattern sets still not function correctly. One of the reasons is opens on the conducting paths [2, 31].  Furthermore, the type of defects and failure mechanisms in CMOS ICs are dependent on the design, layout, and process technology and therefore can vary not only from vendor to vendor but from wafer lot to wafer lot. Hence for one process, bridge defects may dominate while, for a different process, open circuits may prevail.  In general, the type of an open fault in terms of a transistor may be one of (a) floating gate, (b) open source, and (c) open drain. Many research works showed that the floating gate fault is the most complex and hard-to-detect fault in IC test [5, 7, 12]. Although single transistor stuck-on and stuck-open fault models have been introduced at the switch level, the models are still not sufficient to describe the floating gate behavior. In fact, as will be described later, the behavior of a transistor with floating gate transistor depends on the exact site of the occurrence of the open. It is not possible to model a floating gate  The University of British Columbia  14  Chapter I Introduction  transistor without the information of the open site, since the same floating gate transistor may act completely different if the open sites are different. The floating gate acquires a voltage that depends on the coupling capacitances of the transistor device and on the surrounding circuitry [5, 14, 16]. Gate oxide trapped charges may play an important role in the floating gate transistor (FGT) as well [17].  The significance of the floating gate fault has been investigated by defect simulation by several workers. Shen et al. [19] used a procedure called Inductive Fault Analysis (IFA) to investigate the susceptibility of the layout of a logic cell to photolithography defects. In IFA, random defects are generated on the cell layout and their effect was automatically assessed. They found that 25 % of defects generated for an n-MOS logic cell produce floating gate faults.  Similar results have been obtained by Johnson [17], in defect simulations of CMOS cells. Photolithography defect simulations were performed on a selection of hand-crafted and semi-custom cells. Other forms of defects, such as incomplete contact etching were not included in their calculation. To maintain generality in their results, defect distributions from specific process lines were not used. A generally accepted distribution was used for the defect diameter [35], and equal distributions of extra and missing material resulting from photolithography defects were used in the simulations. In these simulations, a total of 16100 defects were scattered over three typical CMOS cells and the effects of the defects were analyzed. The defects produced 930 faults and 27% of these were floating  The University of British Columbia  15  Chapter 1 Introduction  gates. The floating gate is clearly a significant form of fault that can arise from photolithography defects in CMOS circuits.  Hua et al. [8], performed the probability analysis for CMOS floating gate faults on ISCAS '85 benchmark layouts. The defect with size 5 micron was chosen to analyze the open faults and their critical areas. The results clearly showed that the probability of the occurrence of the floating gate fault is the highest one among the various open faults. The percentage of the floating gate faults in terms of the number of faults was 73 % on average, out of the total number of possible open faults. On the other hand, in terms of the critical area (defined as the area in which the center of a defect must fall to cause a fault), which is proportional to the probability of the occurrence of the fault, the percentage of the floating gate fault reached as high as 91 % out of the total number of possible open faults.  In addition to photolithography defects, poor contact or via processing is likely to be an increasing cause of floating gate faults. The use of stacked vias in submicron, three or more layer metal processes results in via and contact holes which are difficult to etch. This can result in high resistance or open circuit contacts and hence floating gate faults.  The University of British Columbia  16  Chapter 1 Introduction  1.8  Scope of the Thesis  Recognizing the complexity and high probability of occurrence of the floating gate faults, this dissertation analyses the detectability of FGTs using the three conventional test strategies, viz.,  1. The Static Voltage strategy (SV strategy) 2. The Dynamic Voltage or Delay strategy (DV strategy) 3. The Static Current (IDDQ) strategy (SC strategy)  It is shown that the behavior of the floating gate defect depends on two classes of parameters, i.e., the predictable and the unpredictable parameters. Predictable parameters include both technological information from the process and topological information from the layout [5]. The unpredictable parameters include the random information coming from the size, location, and nature of the fault. It is shown that the metal-poly capacitance C  m p  , and the metal potential V , together with the unpredictable poly-bulk  capacitance C  p D  and Q , play an extremely important role in determining the final output  m  0  voltage and the steady state current of a logic gate subject to a floating gate defect.  Chapter 2 is devoted to the analysis of the electrical behavior of a floating gate transistor. It is mentioned that the equivalent gate potential V  g s  of the faulty transistor depends on its  own drain to source voltage V , the influence of an overlapping metal track V , and d s  The University of British Columbia  m  17  Chapter 1 Introduction  different technological and topological parameters [5, 14, 16]. It is shown that the induced voltage on the defective transistor decreases for higher values o f the poly-bulk capacitance C b and increases for the lower values of the same. A strong relationship P  between the crossing-metal potential V capacitance value C  m p  m  together with the corresponding metal-poly  , and the induced voltage on the gate is also presented in detail.  Using these relationships, Chapter 3 analyses the detectability o f the floating gate fault using the three classical test strategies. Detectability is discussed according to the unpredictable polysilicon-to-bulk capacitance C b . A new testing technique for the Static P  Current strategy is proposed based on the induction of voltage on the gate of the faulty transistor, through a crossing metal wire. It is shown that i f the voltage at the floating gate of an n - M O S transistor in a logic gate assumes a value between VJN and V  D  D  (VPT and  Vss for a p - M O S transistor), a quiescent current path in the logic gate can be created. This current can easily be sensed by the static current strategy. Complete analysis is given by considering an example of a two input N O R gate.  Chapter 4 compares the detectability intervals for the three test strategies S V , D V and S C . It is shown that the range is larger for the Dynamic Voltage technique than for the Static Voltage technique. The Static Current strategy exhibits a complementary interval with respect to both the S V and D V strategies. A combination o f either one o f the voltage strategies and the Static Current strategy using the proposed technique, can ensure complete coverage o f the floating gate faults.  The University of British Columbia  18  Chapter 1 Introduction  Finally, it is analyzed how the detectability intervals change with the amount of initial charges trapped on the floating gate transistor. It is shown that a greater value of initial trapped charges decreases the detectability interval for the SV and DV strategies, whereas the interval increases for the Static Current strategy. Similarly, the effect of the overlapping metal potential and the corresponding metal-poly capacitance is also presented in detail.  The University of British Columbia  19  Chapter 2 Electrical Analysis of a Floating Gate Transistor  It is widely assumed that an open gate fault in a MOS transistor is equivalent to a stuck-at fault. In this chapter we demonstrate that a floating gate transistor (FGT) is influenced by its topological environment. It is shown that the equivalent gate potential V of the faulty gs  transistor depends on its own drain to source voltage V , the influence of an overlapping ds  metal track V , and different technological and topological parameters. It is shown that m  the induced voltage on the defective transistor decreases for higher values of the polybulk capacitance C b and increases for the lower values of the same. A strong relationship P  between the crossing-metal potential V  m  together with the corresponding metal-poly  capacitance value C , and the induced voltage on the gate is also presented in detail. mp  The University of British Columbia  20  Chapter 2  2.1  Electrical Analysis of a Floating Gate Transistor  The Floating Gate Transistor Fault  A floating gate fault will occur when the connection between the gate terminal of a MOS transistor and the driving source is open circuited. In such a configuration, a voltage is induced at its gate with values depending on the coupling capacitances of the transistor and of the surrounding circuitry, and by the gate oxide trapped charges. Consider the ntransistor shown in Figure 2.1.  •  Polysilicon Gate  Break in Gate Connection Crossing Metal Line  /  Source  Drain  Figure 2.1. A floating gate transistor (FGT).  The gate connection of the transistor is open, i.e., not connected to the gate control node through a "good" ohmic connection, i.e., low resistance; hence the potential of the gate is floating.  The University of British Columbia  21  Chapter 2  Electrical Analysis of a Floating Gate Transistor  A floating gate transistor fault can result from one of the following probable causes:  i)  Layout design errors  ii)  Photolithography defects  iii)  Poor contact / via processing  iv)  Migration phenomena in tracks or contacts  v)  Corrosion.  One of the most probable causes of those listed above is the photolithographic defect [17]. Defects in any of the interconnect or contact layers, which result in missing material, can also produce floating gate faults. As will be discussed later in this chapter, the location of a defect in the circuit layout will have a significant effect on the fault behavior produced.  2.2  Electrical Analysis of a Floating Gate Fault  The electrical environment of an FGT consists of potentials and capacitances [5, 14]. The different potentials are the source potential (V ), bulk potential (Vb), and the drain s  potential (V ). In addition, we assume that a metal track crosses the gate. The d  corresponding potential is V . Finally, we assume that charges Qo can be trapped in the m  silicon dioxide. Many well-known origins such as hot electrons, photons, and technological processes can induce charges in the silicon dioxide [17]. The different capacitances are as follows:  The University of British Columbia  22  Chapter 2  Electrical Analysis of a Floating Gate Transistor  •  the gate to source capacitance C  •  gate to bulk capacitance C b  •  gate to drain capacitance C d  •  gate to source overlap capacitance C  •  gate to drain overlap capacitance C d  •  metal to gate overlap capacitance C , and  •  polysilicon on thick oxide to bulk capacitance C b  gs  g  g  g  gso  0  mp  P  The question is how this electrical environment (V , V j , V , Q ) will affect the potential s  m  0  Vf of the floating gate. The resulting electrical equivalent circuit for an n-MOS transistor g  is given in Figure 2.2 (a).  t CgfJ  0  C  c  Q°  Qo  (a)  (b)  (c)  Figure 2.2. Floating gate n-MOS transistor model.  The University of British Columbia  23  Chapter 2  Electrical Analysis of a Floating Gate Transistor  Of course, the source and the drain terminals are physically symmetrical. For the nchannel MOS the bulk is grounded and the terminal labels are assigned so that drain-tosource voltage Vds is normally positive. For the sake of convenience, the source is considered to be grounded and used as a reference. The resulting equivalent circuit of Figure 2.2 (a) is given in Figure 2.2 (b).  In Figure 2.2 (b), capacitances C j and C d are in parallel. Similarly, C , C g  g  0  G S  G S O  and C b are P  in parallel as well. It is to be recalled that when capacitors are connected in parallel, the effective plate area increases, and the total capacitance is the sum of the individual capacitances, i.e., capacitors add in parallel. In Figure 2.2 (c), CA and CB represent the equivalent capacitance of the floating gate transistor model of Figure 2.2 (b) and are equal to CA = C g  do  + C  and CB = C b + C  g d  P  g s o  + C . The capacitance C gs  CA or CB, as it depends on the potential V . If V = Vd, C m  the other hand, if V = V s, C ra  S  m p  m  m p  m p  is not added in  comes in parallel to CA- On  comes in parallel to C . B  Figures 2.3 (a) and (b) show different situations with V = V s and V = V respectively. m  In Figure 2.3 (a) C\ = C and C2 = CB + C A  m p  S  m  d  ; whereas in Figure 2.3 (b), C\ = CA + C  m p  and C = C . 2  B  The University of British Columbia  24  Chapter 2  Electrical Analysis of a Floating Gate Transistor  C A — Cgd + Cgd 0  CB  — Cgd + Cgfj 0  Cp|j + Cgso "t"Cg  =  S  Ci - C  A  I  Cg  I  - Cgd + Cgd 0  Ci - C  C = C B + *-mp C, 2  B  :  Cpb + Cgso +Cg  =  T  Cpb + Cg  S0  +Cg + C p S  A  + C p m  Cgdc-  =  Cg(J + C p m  C2 — Cg — Cpb + C  m  v =v  v =vss  m  ra  (a)  S  g s o  +C  g s  d  (b)  Figure 2.3. Equivalent model of a floating gate transistor with V = V m  s s  and V = V , m  d  respectively.  A series connection of the charged capacitors acts as a voltage divider. The voltage across each capacitor in series is inversely proportional to its capacitance (V = QIC). Since the charge on any capacitor in series is the same as the total charge (in a series circuit the current must be the same at all points, and since current is the rate of flow of charge, the amount of charge stored by each capacitor is equal to the total charge), hence:  Qjotal = Q\ C V =C V Q 2  fg  Tolal  d+  C  where, C  0  Tolal  =•  \ 1 C  C +C 2  y  _  V  =  C Total ^d  C,  •  The University of British Columbia  2  _|_ Qo  Q  V + —  (2.1)  25  Chapter 2  Electrical Analysis of a Floating Gate Transistor  Where C j — Cgdo C  2  = Cpb + Cgso +C  + C  gs  mp  for  V =V m  ss  and Cj — Cgdo + Cgd + C p m  C2 = Cpb + Cgso +C  for  gs  V =V m  d  From equation (2.1) it is clear that the behavior of a transistor is strongly dependent on the drain voltage. Champac et. al. [16] made experimental measurements from fabricated n-MOS transistors with floating gate defects. The experimental data showed that the defective transistors might still work in the saturation region for high drain voltages. The induced voltage at the floating gate V f decreases as the drain voltage decreases. For a g  certain drain voltage, the transistor begins to work in cut-off ( V f  g  =VTN)- Then, the  floating gate transistor is not completely turned off but rather works in the sub-threshold region, low current levels flow through the defective transistor and the transistor can be considered as  slightly  ON.  From equation (2.1), it is also clear that the induced voltage on the defective transistor decreases for higher values of C b and increases for lower values of the same. Similarly, P  with V of C  m p  m  =V  D D  , the induced voltage at the gate of a transistor increases for higher values  and decreases with a lower value. With V  The University of British Columbia  m  = 0, the induced voltage at the gate  26  Chapter 2  decreases for a higher value of C relationships of C  m p  m p  Electrical Analysis of a Floating Gate Transistor  and increases with a lower value. Similar  and C b were observed by Champac and Figueras [15]. P  The metal-polysilicon capacitance C  m p  is an overlap capacitance whose value depends on  the gate capacitor area and the metal-to-poly capacitance per unit area [3, 5, 14, 16]. The area can be extracted from the circuit layout and the value per area unit is a known technological parameter. Consequently, the C  m p  value for a given defect can be predicted.  In the same way, by using the layout and the technological parameters, the C j and C g(  g s  capacitances can be computed. A l l the capacitances of the interconnect open defect appear being predictable except the polysilicon on thick oxide capacitance C b. Indeed, P  the value per area unit is perfectly known, but the same depends on the location of the open on the line, which is purely random. So, for the interconnect open, the C  p b  capacitance must be viewed as an unpredictable parameter. The quantity of the trapped charges Q on an FGT is a technological specificity that is not commonly given [6]. The 0  effect of Q on the behavior of an FGT will be studied later in chapter 4. 0  The above analysis has been centered on an n-MOS transistor. A similar analysis can be carried out for a p-MOS transistor.  The University of British Columbia  27  Chapter 3 Floating Gate Fault Detection  3.1  Introduction  In this chapter we analyze the detectability of the floating gate faults using the three classical test strategies viz., Static Voltage (SV), Dynamic Voltage (DV), and Static Current (SC) testing strategies. Detectability is discussed according to the unpredictable polysilicon-to-bulk capacitance C t,. A new testing technique for the Static Current p  strategy is proposed based on the induction of voltage on gate of the faulty transistor, through a crossing metal wire. We show later that if the voltage at the floating gate of an n-MOS transistor in a logic gate assumes a value between VTN and VDD (VPT and Vss for a p-MOS transistor), a quiescent current path in the logic gate can be created. This current can easily be sensed by the Static Current testing strategy. Complete analysis is given by considering an example of a two input NOR gate.  The University of British Columbia  28  Chapter 3  3.2  Floating Gate Fault Detection  Detection of a Floating Gate Fault  The circuit in Figure 3.1, composed of a NOR gate and an inverter illustrates an interconnect open. In the NOR gate, the gate of the n-MOS transistor on input V i is i n  disconnected. Hence this transistor is a floating gate transistor. In this Section we examine the behavior of the floating gate fault with respect to the Static Voltage, Dynamic Voltage, and Static Current test strategies. In each case, it is demonstrated that the detection depends on the unpredictable parameter C t,. p  3.3V  f OV  0  v  in2  = ov  J V,m  Figure 3.1. An interconnect open in a NOR gate.  The University of British Columbia  29  Chapter 3  Floating Gate Fault Detection  Figure 3.2 gives the Cadence Spectre simulation results of the NOR gate of Figure 3.1 using a standard 0.5 micron, 3.3V technology. It is assumed for these simulations that there is no initial charge Q on the floating gate transistor. The behavior of the circuit 0  with initial charge consideration will be discussed later in Chapter 4. The first NOR gate input V i performs a rising transition from 0 to 3.3V, while the second NOR gate input in  Vi„2  is equal to 0V. In the fault-free circuit, the output of the NOR gate obviously  switches from 3.3V to 0V. The behavior of the faulty NOR gate output V R is given in N O  Figure 3.2 for different C b values. P  tim« ( s )  Figure 3.2: Faulty behavior of the NOR gate  To analyze the plots in Figure 3.2, we have to detail the behavior of the floating gate transistor. The charges trapped in the gate oxide, plus the influence of the crossing metal  The University of British Columbia  30  Chapter 3  Floating Gate Fault Detection  line and the influence of the drain voltage create an induced voltage on the floating gate in such a way that the faulty transistor is in a so-called 'slightly' ON state [3, 5, 14].  When  Vjni = O V ,  the p-MOS transistor is O N and the faulty n-MOS transistor is slightly  ON. In this situation, we have two fighting conducting transistors. Due to the very different conduction of these two transistors, the output of the NOR gate is  V OR=3.3V, N  which is the correct value. It is important to note that the difference of degree of conduction is so large that the output is equal to 3 . 3 V whatever the parameters of the defect: C Vi  n v  m g 0  = OV.  , Cpb, C d, etc. The inverter controlled by a high output produces a low output g  The current flowing through the p and n-transistor is negligible due to the low  degree of conduction of the floating n-MOS transistor.  When the input rises to  V  i n  i = 3.3V,  the p-MOS transistor is turned off, and the faulty n-  MOS transistor remains slightly ON. In this situation, we no longer have two fighting transistors but only one slightly conducting n-MOS transistor. Consequently, the floating n-MOS transistor starts to slowly discharge the output node VNOR- The output voltage V OR N  slowly decreases as illustrated in Figure  gate depends on the drain voltage, which is gate decreases as  VNOR  3.2.  But the voltage induced on the floating  VNOR- SO  decreases. For a certain  the voltage induced on the floating  V OR = V f N  i n a  i,  this floating gate voltage is  equal to threshold voltage VJN and the transistor is turned OFF as described by Champac and Figueras [ 1 4 ] . In this new situation we have two OFF transistors, the NOR gate output is in a high impedance state and the final voltage V f i  The University of British Columbia  n a  i  is memorized on the output.  31  Chapter 3  It is now important to note that the final voltage  Vf  i n a )  Floating Gate Fault Detection  strongly depends on the defect  parameters including the unpredictable parameter C b as illustrated in Figure 3.2. p  3.2.1  Static Voltage (SV) Testing Strategy  Considering a Static Voltage strategy, it clearly appears in Figure 3.2 that the circuit operates correctly when the input V i=OV (the effect of the crossing metal potential in in  this situation, will be discussed in Chapter 4). When output voltage is V  f i n a  i . If V  f i n a  Vi i n  = 3.3V, the final N O R gate  i is greater than the logic threshold V t h  inv  of the inverter,  this voltage is recognized as a faulty logic ' 1 ' and a faulty value can be propagated through the circuit, to a primary output.  Vfmai  depends on the transistors' technological and topological parameters: C , V r , u, , o x  IV W , W , L n , L p , C n  p  m p  n  , Cg , including the trapped charges Q [6]. But it is of prime d  0  importance to remark that this voltage also depends on the unpredictable poly-to-bulk capacitance value: C b. Due to the presence of the unpredictable capacitance value, it is P  not possible to predict the V f i in case of a fault. Consequently, the static voltage ma  strategy is not able to unconditionally detect floating gate faults.  However, it is useful to study the variations of the faulty behavior according to the values of the unpredictable parameter. From circuit simulations, we can plot the Static Voltage Vfinai  versus C b characteristics as illustrated in Figure 3.3. In this Figure, P  The University of British Columbia  Vfj i n a  32  Chapter 3  Floating Gate Fault Detection  Figure 3.3: Static Voltage behavior of a floating gate transistor.  The University of British Columbia  33  Chapter 3  increases when C  p b  increases. V  fina  Floating Gate Fault Detection  i is greater than the logic threshold voltage VthiNv of  the driven gate if the unpredictable parameter C b is greater than a critical capacitance P  C  s v c  . This small example illustrates that a critical value of the unpredictable parameter  can be defined for the FGT fault. A n FGT fault can be detected using a Static Voltage test if the unpredictable parameter C  p b  falls into the interval [ C  s v c  , «>]•  m  this  c a s e  > the logic  fault model associated to the interconnect open corresponds to what is commonly called a 'Stuck-Open' transistor fault [2].  3.2.2  Dynamic Voltage (DV) Testing Strategy  When Vim rises from 0 to 3.3V, the faulty NOR gate output falls from 3.3V to V  f m a  i . It  can be noted that this falling transition is delayed due to the low degree of conduction of the floating gate transistor. If this delay D is greater than the slack time SL of the node, a faulty value will be captured on the circuit output. It is clear that the resulting delay D depends on transistor technological and topological parameters and on the poly-bulk capacitance C b. As for the static voltage detection, due to the presence of the P  unpredictable poly-bulk capacitance value, it is not possible to compute a priori the delay D. Consequently, the Dynamic Voltage strategy is not able to unconditionally predict the detection of a floating gate fault.  Here again, we can study the variation of the faulty behavior according to the values of the unpredictable parameter C b. Using Spectre simulations, Figure 3.4 gives the delay p  The University of British Columbia  34  Chapter 3  versus C  pD  Floating Gate Fault Detection  characteristics where the delay increases when C b increases. The delay D is P  greater than the slack time SL if the unpredictable parameter C b is greater than a critical P  capacitance C  DV C  . It is interesting to note that the delay D becomes infinite when Vf i ina  becomes greater than the logic threshold VthiNv of the inverter. Indeed, in this case there is no switching and the delay fault behaves as a stuck-open fault which may be viewed as a particular case of a delay fault. Consequently, this faulty dynamic behavior includes the faulty static behavior and we have C  DV C  <C  s v c  . This small example illustrates that a FGT  fault can be detected using a Dynamic Voltage test if the unpredictable parameter C falls into the interval [C  DV C  pb  ,°°].  4.0 3.0 Cpb = 5fF  >  2.0 L 1.0  E.  Cpb = 4fF V+hlMV  Cpb = 3fF Cpb = 2fF  D  Cpb= IfF  Fault-Free 1.011  2 0n time f s )  3.0n  4 0n  Figure 3.4 (a). Dynamic behavior of an FGT  The University of British Columbia  35  Chapter 3  Floating Gate Fault Detection  D  Detectable values of C using DV strategy pb  I  1  1  ^  2  3  4  C (fF) pb  (b) Figure 3.4: Dynamic behavior of an FGT.  3.2.3  Static Current (SC) Testing Strategy  Due to the low degree of conduction of the floating gate transistor (slightly ON state), the current in the NOR gate is negligible. No current detection of the floating gate is possible by giving a rising transition on V i keeping m  V 2 i n  = 0 while only considering the current  flowing in the N O R gate. This detection might become possible if we consider the current flowing in the driven inverter gate. That is, when Vi„i = OV, the output of the NOR gate is equal to Vfi i which is an intermediate voltage between V and V na  T  D D  - V . In T  such conditions, the two transistors of the driven inverter are ' O N ' (with different degrees of conduction) and a current I Q flows in the inverter from V D D  D D  to G N D during the  steady state [6,9,11,16]. But generally, this is not a valid test strategy for IDDQ, as the  The University of British Columbia  36  Chapter 3  Floating Gate Fault Detection  situation might become entirely different if instead of an inverter, a complex gate was driven by the output of the faulty NOR gate.  The following details a proposed technique which makes floating gates IDDQ testable independently of current in the driven gate, by controlling the potential V , of a crossing m  metal wire. The behavior of the circuit with different metal-poly capacitance is described first, followed by the analysis for behavior with the unpredictable parameter C b. P  DD  L IDDQ  O  V i n l =0V  -#  •  Vin2 = 0V  _* Output  ADDQ  -b P  V  S S  Figure 3.5 (a): A faulty NOR gate circuit.  From Fig. 3.5 (a), when Vi„i = OV and V 2 = OV, a high impedance path from the power in  supply to ground through the defective transistor is created (as the defective n-MOS  The University  of British  Columbia  37  Chapter 3  Floating Gate Fault Detection  transistor is slightly O N ) . If the voltage at the floating n - M O S gate assumes a value between V N and VDD. an increased quiescent current IDDQ flows through the N O R gate. T  This increase in the quiescent current can be used to detect the floating gate defect by IDDQ testing, independent of the current in the driven gate. A s mentioned in Chapter 2, for V  M  = V D> the induced voltage at the gate of the transistor is directly proportional to C D  while for V  M  = 0, the induced voltage at the gate becomes inversely proportional to C  m p  ,  m p  .  Using this relationship, it is clear that by increasing the voltage at V , we can increase M  the voltage at the gate of the transistor. Several Spectre simulations were conducted with Vni = V  I N 2  = OV, by giving a rising transition at V  M  from 0 to 3.3V for the N O R gate in  Figure 3.5 (b).  VDD  t  4"  •  V  S S  Figure 3.5 (b): Current testing (SC) for F G T N O R gate.  The University of British Columbia  38  Chapter 3  Floating Gate Fault Detection  When V i = Vj 2 = OV and V = OV, both p-MOS transistors conduct. Assuming the i n  n  m  extreme case, i.e., when there are no trapped charges on the floating gate transistor, the floating gate acquires a voltage depending only on its electrical environment from the drain voltage V , through capacitances C , C , C , C d  on the C b and C P  g d  m p  G S  P B  M P  . This voltage strongly depends  values [11]. As stated in Chapter 2, when V = OV, the value of C m  added to C b (C2 = C b + C P  P  g s o  +C + C gs  m p  m p  is  ; capacitors in parallel). In that case, the induced  voltage on the gate of the defective transistor (V ) decreases for higher values of C b, the fg  P  floating gate acquires a smaller value with V = OV. However, when the voltage V rises m  m  to 3.3 volts, the effective value of C2 ( C = C B = C 2  effective value of d  (Ci = C + C A  m p  = C  + C  g d o  g d  p b  + C  g s o  +C ) decreases and the gs  + C ) increases. As a result, the m p  voltage on the floating gate also increases. If the values of capacitors are such that V  f g  rises above the threshold voltage V ^ of the transistor, the transistor starts conducting and allows a quiescent current to flow through it making the faulty gate IDDQ testable.  Figure 3.6 shows plots obtained by sweeping C b, with C p  m p  = 250aF. A NOR cell with an  n-MOS floating gate transistor on V i , was laid out using a standard 0.5 micron i n  technology, with the n-MOS transistors of dimension 0.6 (i by 2|i, and p-transistors of dimension 0.6|X by 3|i. A crossing metal wire of length 110|1 in metal 2 gave C 422aF. A value of 250aF for C  m p  m p  =  is therefore a reasonable value to plot the current versus  Cpb characteristics. Similarly, to get a critical value for I DQ testing, a circuit of 10,000 D  gates was laid out using the same 0.5-micron technology. A n IDDQ current of 0.34 (iA was observed for these 10,000 gates. Allowing for a margin of one order of magnitude yields  The University of British Columbia  39  Chapter 3  Floating Gate Fault Detection  3.4 |iA as a critical current for I DQ testing. The plots indicate that by increasing C , the pb  D  floating gate acquires a smaller voltage and consequently the current in the faulty gate decreases.  4.0n  2,0n time ( s )  (a) iDDQ  60u 50u  Cpb=1fF  40u Cpb=2fF 20U  t  Cpb=3fF Cpb=4fF  10U  Cpb=5tF  0.0  1.0n  2.0n  time ( s )  3.0n  4.0n  (b) Figure 3.6: Change in the floating gate voltage and current by sweeping C ; C =250aF pb  The University of British Columbia  mp  40  Chapter 3  Floating Gate Fault Detection  Figure 3.7 gives the current versus C b characteristics where the current decreases when P  Cpb increases. So, the current is greater than the minimum required if the unpredictable parameter C  p b  is smaller than a critical capacitance C  c  . A floating gate transistor fault  can be detected using Static Current test if the unpredictable parameter C b falls into the P  interval [0, C  s c c  ].  'Cpb (fF) Detectable values of C  p b  for SC strategy  <  •!  Figure 3.7: Current versus C b characteristics of an FGT. P  The University of British Columbia  41  Chapter 4 : Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  4.1  Introduction  This chapter compares the detectability intervals for the three test strategies SV, D V and SC. It is shown that the range is larger for the Dynamic Voltage technique than for the Static Voltage technique. The Static Current strategy exhibits a complementary interval with respect to both S V and D V strategies. A combination of either one of the voltage strategies and the Static Current strategy using the proposed technique, can ensure complete coverage of the floating gate faults. Moreover, we analyze how the detectability intervals change with the amount of initial charges trapped on the floating gate transistor. It is shown that a greater value of initial trapped charges decreases the detectability interval for the S V and D V strategies, whereas the interval increases for the Static  The University of British Columbia  42  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  Current strategy. This again suggests a combination of both the current and voltage testing strategies to ensure a complete coverage of the floating gate faults. The effect of metal-poly capacitance C  m p  , and metal potential V on the detectability intervals is also m  studied in detail.  4.2  Test Strategy Sensitivity to Floating Gate Fault Parameter  In the Chapter 3, the detection of floating gate faults has been analyzed using three different test strategies, viz., Static Voltage, Dynamic Voltage and Static Current. This analysis can now be used to clarify the relationships between these test strategies.  First , the main remark coming from the previous study is that the behavior of a defect clearly depends on unpredictable parameters. Second, for a given test strategy, the detection of a floating gate defect can never be guaranteed due to the presence of the associated unpredictable parameter. However, the defect can be detected by a given test strategy if its unpredictable parameter falls within a specific interval. More formally, each couple (Defect, Test Strategy) is associated with a given interval.  As indicated above, a defect cannot be simply unconditionally declared as detected or undetected. So the efficiency of a test strategy cannot be evaluated using the oversimplified concept of detection or non-detection. Consequently, the unpredictable parameter interval represents a reasonable criterion that can be used to evaluate the efficiency of a Test  The University of British Columbia  43  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  Strategy as well as to compare the efficiency (the global ability to detect realistic defects rather than faults) of different test strategies. Figure 4.1 shows the detectability intervals for Static Voltage, Dynamic Voltage and Static Current strategies for FGT faults.  Static Voltage  Dynamic Voltage  Static Current  Zn 1  Zn 2  Zn 3  Zn4  Figure 4.1: FGT Fault Detectability Intervals.  The global consideration of Figure 4.1 shows that all three test strategies are able to detect the considered defect. In each case, we observe a non-empty interval. Using the oversimplified 'detection' versus 'non-detection' concept, the three test strategies appear as equivalent. Of course, this is not the case when considering the size of the interval. Indeed, it seems clear that larger interval means a higher probability of defect detection, and so a higher efficiency. The Static Voltage strategy presents an interval smaller than the Dynamic Voltage since C  s v c  is always greater than C  D V C  . Consequently, we can say  that D V ( zone 2,3,4 ) is more efficient than S V testing ( zone 3, 4 ). The Static Current Strategy presents a complementary interval with respect to the Static and Dynamic  The University of British Columbia  44  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  Voltage strategies ( zone 1, 2, 3 ), but overlaps with both Static Voltage and Dynamic Voltage test strategies. It is evident that a combination of either one of the voltage strategies and the Static Current strategy can ensure complete coverage of the floating gate fault.  4.3  Effect of the FGT Initial Charge on the Detectability Intervals  A l l the simulation results in chapter 3 were generated by considering the extreme case scenario, with no initial charge on the faulty transistor. In this sub-section we will explain how the detectability intervals change with the amount of charge Q trapped on the 0  floating gate transistor.  4.3.1  The Source of Residual Charge  Potential residual charge is most likely to result from the processing of the ICs as the devices had been stored unpowered before testing. Johnson [17] suggests that one possible source of charge is the plasmas that are used in IC fabrication for the etching of various layers and resists. Consider, for example, the patterning of polysilicon by reactive ion etching. The ions at the surface of the sample are positive as the sample is placed on the cathode of the etching system. Interaction of the plasma with the polysilicon as it etches the layer will therefore result in the transfer of charge into the material. At this point the charge density will be roughly uniform within the sheet. Completion of the etch will result in a set of isolated polysilicon tracks and gates which all contain positive  The University of British  Columbia  45  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  charge. It is probable that the photoresist layer would then be removed by a further dry etching process during which the isolated polysilicon tracks are exposed to further positive charge. Subsequent exposure of the wafer to oxygen or nitrogen atmospheres will produce a silicon dioxide or a silicon nitride coating on all polysilicon surfaces which will trap the residual charge [17]. Later stages of the processing will connect all fault free polysilicon tracks to metal tracks providing a conducting path for the tracks to be discharged. Polysilicon gates that remain isolated will retain their positive charge, and this is seen as the unbiased floating gate potential when devices are used.  The analysis presented so far suggests that the charge density will be approximately uniform throughout the polysilicon tracks. Johnson [17], however, made experimental measurements of the floating gate potential in which this is not seen to be the case. A possible cause for this variation can be seen by considering further stages of processing. The first stage of the charge deposition during the reactive ion etch of the polysilicon should result in a uniform charge distribution. The polysilicon layer is a single conducting sheet until the etch is complete, and so for most of the etch a uniform charge distribution will occur. The situation is different during the removal of photoresist. For most of this process, each isolated polysilicon track is exposed to the plasma only along its perimeter. One might therefore assume that the amount of charge accumulating on each track should be determined by the length of the track perimeter. This would result in higher values of residual charge for longer or wider tracks or devices.  The University of British Columbia  46  Chapter 4  4.3.2  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  Detectability Intervals with an Initial Charge on the FGT  Figure 4.2 shows the behavior of the NOR gate output voltage  Vf  i n a ]  ,  when the initial  charge Q on the floating gate increases. It is evident that as the initial charge on the 0  floating gate increases, the voltage at the output of the faulty gate decreases. Hence the detectability intervals for Static Voltage and Dynamic Voltage strategies decrease too.  4  VNOR  3  0 time ( s )  Figure 4.2: Change in the output voltage of the NOR gate with an increased initial charge Q . 0  Figures 4.3 and 4.4 show the detectability intervals for the Static Voltage and Dynamic Voltage strategies with an increased initial floating gate voltage of V =0.4V (V =QO/CA). 0  The critical capacitances C  S V C  and C  D V C  0  for both the strategies increase, giving a lower  range of detectability intervals.  The University of British Columbia  47  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  Figure 4.4: Detectability intervals for Dynamic Voltage strategy with V =0.4V o  The University of British Columbia  48  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  As for the Static Current strategy, a higher Vf means a higher current through the faulty g  transistor. Figure 4.5 shows the change in current through the floating gate transistor when the value of initial charge on the floating gate Q increases for C b = 5 fF. With V 0  p  0  = OV, Cpb = 5 fF gave a current value of 3.1uA, which was below the critical current of 3.4 uA. However, with a slight increase in the initial charge (V =0.1V), the current 0  increases above the threshold current bringing C  p b  = 5 fF in the SC strategy's detectable  range. IDDQ 30u V. =  Q„  Vo=0.5V' Cpb=5fF  20u  Vo=0.4V Vo=0.2V  10j  Vo=0 1V  L  0.0  0,0  1.0n  I. O  v=ov  , 0  3,0n  ,  4.0n  Figure 4.5: Change in IDDQ current by an increase in initial charge on the floating gate.  The detectability behavior for the Static Current strategy with an increased initial floating gate voltage of V = 0.4V is shown in Figure 4.6. 0  The University of British Columbia  49  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  (uA)  1fF Detectability  V =0V  Intervals for SC strategy  v =0.4V  3fF  5fF  7fF  9fF  11fF  C,Pb  o  o  Figure 4.6: Change in the detectability interval for Static Current Strategy with V =0.4V o  Figure 4.7 shows the changed detectability intervals for the three test strategies. It is evident that with the increase in the initial charge on the floating gate, the detectability interval of Static Current strategy changes more than for the voltage strategies. Hence the overlap between current and voltage strategies increases with the increase in the initial charge at the floating gate. However, it is important to note that the detectability interval for the voltage techniques decreases, hence conducting only the voltage test (even Dynamic Voltage) does not ensure a complete coverage of the floating gate fault. Therefore, it is necessary to conduct both current and either of the voltage strategies for guaranteed detection of the floating gate fault.  The University of British Columbia  50  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  Figure 4.7: Change in the fault detectability intervals by trapped charges Q on the FGT. 0  4.4  Effect of the Metal-Poly Capacitance C  m p  and Metal Potential V on the m  Detectability Intervals In this section, we will analyze how a crossing metal wire over a floating gate transistor affects the detectability intervals for the different test strategies. Two parameters are of prime importance while considering the effect of the metal, viz., (a) the value of the capacitance C  m p  , and (b) the corresponding metal potential V . Electrical analysis of the  The University of British Columbia  ra  51  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  floating gate transistor with respect to V and C , will be presented first followed by the m  m p  study of influence of V and C , on the detectability intervals. m  4.4.1  m p  Electrical Analysis of the Floating Gate Transistor for C  To study the influence of C V  fina  m p  and V  m  m p  and V  m  on the FGT, we need to deduce an expression for  i that will give a relationship between Vfi i and C na  m p  / V . Consider the electrical m  equivalent circuit for the floating gate n-MOS transistor of the faulty NOR gate of Figure 3.1 as follows:  v =v d  1  V = V  N0R  d  N 0 R  t  For V = VSS m  C i = Cgdo + Cgd  -gdo  C2  =  Cpb + Cgso "'"Cgs + Cmp  r  ^-mp  For V = VDD  Vfg  Qo  m  R i—  'R  Ci  =  C2  =  Cgdo  Cgd + C p m  C p + Cgso "'"Cgs 0  c —1  z- V S S (a)  (b)  Figure 4.8: Electrical equivalent circuit of the n-MOS FGT of a faulty NOR gate  In the NOR gate of Figure 3.1, when V i = V i n  I N 2  = 0 V , the drain voltage V of the FGT is D  at V D , which is the correct value as discussed in section 3.1. When V i rises to V D , the D  m  D  p-MOS transistor is turned off, and the faulty n-MOS transistor remains slightly ON. In  The University of British Columbia  52  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  this situation, we have one slightly conducting n - M O S transistor. Consequently, this floating transistor starts to slowly discharge the output node V O R . But the voltage N  induced on the floating gate depends on the drain voltage, which is V R . SO, the voltage N O  induced on the floating gate decreases as V O R decreases. For a certain V N  voltage is equal to threshold voltage V  T N  N O  R  = Vf i, this ma  of the FGT, and the transistor is turned O F F . In  this new situation we have two O F F transistors, the N O R gate output is in a high impedance state and the final voltage Vf i is memorized on the output. In Figure 4.8 (b) ina  with Vfg > VTN , the drain voltage of the n - M O S transistor V (=VNORX can be written as: d  VNOR = V  D  e  D  -t/T  where  T  = R,  C  '  C  l  C +C {  2  Taking a first order approximation V Q R can be written as follows: N  V y  =V  NOR  y  DD  [  1—  (4.1)  /?.(C,C )/(C,+C ) 2  2  Assuming no initial charge on the floating gate, the voltage at the gate of the n-MOS transistor is  c V -'2  K  V  V  =C fg  Total NOR  The University of British Columbia  where  C  To[al  =  C C C2  "T"  53  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  C xr  V Total NOR  _  V  -i  =  c  18  l +  V  c  (4.2) N0R  2  By inserting the value of V Q R from Equation 4.1 into Equation 4.2, we get N  V  -i  = C  g  V  C  ] +  1-D D  R.(C C )/(C C ) x  2  2  l+  j  2  Vfmai will be reached when Vf .= VTN- Hence, g  V  = TN  DD  c,+c  {  2  OFF  1-  R.(C C )/(C +C ) X  2  X  j  2  Re-arranging the above equation ^V  c +c  V  ^  •1=  c  'Off  /c.(C,C )/(C,+C ) 2  2  (4.3) 1  T  ^  2  ' DD  At tQFF, V ai = V R . Hence fin  N O  V y  =V final  y  DD  {  1—  OFF  (4.4)  R.(C C )/(C +C ) l  2  l  2  Inserting the value of toFF from Equation 4.3 into Equation 4.4 yields  The University of British Columbia  54  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  V  =V final  y  (4.5)  \  TN -I  v  As described in Chapter 2, for V = V*ss M  C; — Cgd + Cgd 0  C2 — Cpb + Cg  SO  whereas for V = V M  D  +Cg  S  +  Cp m  D  Ci  =  Cgd + Cgd +  C2  =  Cpb + Cgso ~^~Cg  0  Cp m  S  Writing equation 4.5 for the two cases, i.e., with V = V s , and V = V D , we have S  M  M  C.ao+C^+C^+C^+C^+C^ y  final  Y  c  TN  ^r  V y  = V*TN 1  final  y  i  ^-gdo  T  v  v  - g d  +  m  * - p b  ^ ^ g s o  c  +c  *-gdo  ^ ^ g d  ss  - g d  +r +c +c +  for V = V  +c  ^gdo  D  +c ^'"gs  +c  ^  for V = V D  ^ ^ m p  M  D  mp  From the above two equations, we can see that for both V  m  = Vss and V  m  = VQD, the  numerator remains the same. However, the value of the denominator increases in the case when V = VDD- Hence, we can make the following inferences: m  The University of British Columbia  55  Chapter 4  a)  Keeping C  m p  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  constant, the value of V  f i n a  compared to the value when V = V m  denominator when V = V m  D D  D D  i is higher for the case when V = V s , as m  . This is due to an additional term in the  .  b)  When V = V s, Vf i is directly proportional to C  c)  When V = V  4.4.2  m  m  S  D D  ina  m p  , V ai is inversely proportional to C  Dependence of V  fin  m  S  .  m p  .  on the Detectability Intervals  In the previous analysis for the two voltage strategies, a two vector set sequence was applied to the NOR gate circuit with an FGT in order to excite the fault. The first input vector was an initialization vector (00) that sets the output of the N O R gate to a correct logic T . The second input vector (10) tries to set the output of the N O R gate to a logic '0' but an intermediate voltage V f i is achieved in case a floating gate transistor is ma  present. In the previous analysis in Chapter 3, it was assumed that the crossing metal wire also receives a rising transition, i.e., a logic level ' 1 ' , at the same time the second vector is applied to the NOR gate.  0  0  0  Figure 4.9: Input vectors for the faulty NOR gate  The University of British Columbia  56  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  In this sub-section we will analyze four different situations for V , viz., m  a) V is '0' at the application of first vector, and remains '0' at the application of second m  vector. b) V is '0' at the application of the first vector, and becomes ' 1' for the second vector. m  c) V is ' 1' at the application of first vector, and remains ' 1' at the application of the m  second vector. d) V is ' 1' at the application of first vector, and changes to '0' for the second vector. m  Figure 4.10 shows the plots for the four cases described above for a poly-bulk capacitance of 5 fF.  In Figure 4.10 (a), V = Vss when the first vector 00 is applied at the inputs. The floating m  gate voltage is such that a correct value of 3.3 V is observed at the output. At the application of the second vector '10', V remains 0V, and the increase in voltage at the m  floating gate is not sufficient to turn the faulty transistor ON. Hence, the output voltage does not discharge and an increased V f i is stored at the output. In Figure 4.10 (b), V ma  m  changes to 3.3V at the application of the second vector. The floating gate acquires a voltage greater than the transistor threshold and the output node discharges to V  fina  i . This  is precisely in accordance to the analysis presented earlier.  The University of British Columbia  57  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  4.0  Vfinai  r  3.0  (d)  Vinl  3.3  2.0  V  OV  1.0  3.3  Vtg  0.0  -4  V •OV  -1.0 5.0n  0.0 time ( s )  Figure 4.10: Vf i and V plots with the application of V at different instances ina  The University of British Columbia  f g  m  58  Chapter 4  In Figure 4.10 (c), V  m  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  = V D D at the application of first vector. This value remains the  same when the second vector is applied. The floating gate acquires a voltage greater than its threshold and the output discharges to a lower V  fina  i . In Figure 4.10 (d), V  m  drops to  V s- Consequently the value of V f decreases and the output node does not discharge. S  g  Hence, from the simulations in Figure 4.10 we can infer the following: Figure 4.10 (a) and (d) indicate that with V = V s, at the application of the second vector, i.e., when V i m  transitions from zero volts to V of the output  Vfmai  that a higher V  f g  smaller value of  S  D D  in  , a lower V f is achieved. Consequently the final value  > acquires a higher value. Whereas, Figure 4.10 (b) and (c) indicate  is achieved if V = V m  Vf  g  i n a  i.  D D  , when the second vector is applied. This gives a  Therefore, we can say that for given values of C  pD  and C , the mp  detectability range for the Static Voltage and Dynamic Voltage techniques increases by keeping the metal potential equal to Vss as compared to the case when V = V m  D D  .  Figure 4.11 shows the increased detectability intervals for the voltage techniques by controlling the metal potential and maintaining it at Vss- The interval for the Static Current technique is not considered, as the testing strategy for the same depends on providing a rising transition at V . m  The University of British Columbia  59  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  Static Voltage  0  Dynamic Voltage  0  Zn 1  Zn2  Zn3  v =v,DD m  v =vss m  Figure 4.11: Increase in the detectability intervals by controlling V to Vss volts. m  4.4.3  Dependence of the Detectability Intervals on C  m p  The detectability intervals for the voltage and current testing strategies will be considered separately in the following analysis.  4.4.3.1 Detectability Intervals for SV and DV Test Strategies  Consider the following equations  Vfinal  The University of British Columbia  for V = V m  ss  60  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  and (r V y  =V final  y  ,  +C  *~gdo ^ ^ g d  +C  +C +C  ^^gso  ^^gs  r  TN -|  v  V y  +C ^^pb  final  T  ^gd  T  for V M  TN '  V  DD  ^ m p  1 + c p b +c g s o + c g s  =V y  +c  +C  -gdo  ^  ^^mp  for V = VDD M  c , +c +c A  ^gdo  ^gd  ^mp  j  From the above equations, it is clear that when V = Vss, Vf, i is directly proportional to m  C , whereas when V = V D , V mp  m  D  fina  na  i is inversely proportional to C . Figure 4.12 shows mp  the simulation results for NOR gate of Fig. 3.1 with C b = 5fF and different values of C P  when V = V m  D D  m p  .  0.0  1.0n  2.0n  3.0n  time ( s )  4.0n  5.0n  Figure 4.12: Vf i variation of a faulty NOR gate for different values of C ina  The University of British Columbia  m p  ( C =5fF) pb  61  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  From Figure 4.12, it is evident that a small variation in C the output voltage value of  Vfmai  Vf  m a  i,  m p  has a considerable effect on  of the NOR gate. For higher metal-poly capacitances, a lower  is achieved and vice versa. A lower  Vf  m a  i  means a lower detectability  interval for both SV and DV testing strategies. Hence, with V = V m  C  m p  D D  , as the value of  increases, the detectability intervals for the voltage strategies decrease. Figure 4.13  illustrates the C  m p  and C  pD  relationship curves with Vfi i ( V = V D ) . for the Static na  m  D  Voltage technique.  The case is, however, different when V proportional to C  m p  m  = V s. In this case, Vfi i is inversely S  and an increased value of C  m p  na  means increased detectability intervals  for SV and DV strategies. Therefore, an ideal case to achieve maximum coverage for the Voltage strategies would be a high value of C  The University of British Columbia  m p  with V = Vssm  62  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  The University of British Columbia  63  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  4.4.3.2 Detectability Intervals for S C Test Strategy  For the Static Current testing technique from simulations, by controlling the metal potential and by giving a rising transition at V , a greater C m  m p  ensures a greater voltage  induced on the floating gate. Consequently, the conduction of the transistor increases and an increased current flows through the faulty logic gate. Hence the detectability interval increases with an increase in C . mp  C =950aF  1,20  mp  1.00 800m >  C =150aF  600m  C =150aF  mD  mp  400m  C =950aF mp  200m 0.00  0,0  1.0n  2.0n time ( s )  3,0n  4.0n  (a)  In no C =950aF  100u  mp  C =650aF mp  ^  C =300aF  50u  mp  C =150aF mp  C =150aF mp  0.0  0.0  1,0n  2,0n  timo ( s )  3.0n  4.0n  (b) Figure 4.14: Vf and IDDQ simulation results for different C g  The University of British Columbia  m p  values.  64  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  Figure 4.14 (a) shows the voltage acquired by the floating gate for the circuit presented in Fig. 3.5. It clearly appears that when V C =150aF as compared to C mp  C  m p  m p  m  = Vss, Vf acquires a larger value with g  = 300aF, 650aF, 950aF, etc., i.e., the higher the value of  the lower the value of Vf ( refer to the first half of the simulation). When V rises to g  m  VDD (the second half of the simulation), the voltage on the floating gate also increases, i.e., the higher the C , the higher the V . m p  fg  Figure 4.14 (b) shows the IDDQ current flowing through the floating gate transistor. The plots indicate that when V = V s , the current is inversely proportional to C m  S  because the floating gate acquires a larger voltage with a smaller C  m p  . This is  when V = Vss- But  when V jumps to VDD, the current becomes directly proportional to C m  m p  m  m p  . Hence, for the  proposed technique for SC test strategy (by giving a rising transition at V , as per section m  3.2.3), the detectability interval increases with an increase in C  Figure 4.15 depicts that as C  m p  m p  .  is increased, an increased C b value is required to maintain p  the same amount of IDDQ current. Hence, a higher detectability interval is achieved for the Static Current testing technique when C  The University of British Columbia  m p  is increased.  65  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  35  Cpb  Detectable values of for SC strategy  C =250a mp  C =500a mp  C =750a mp  C =lf mp  C =1.25f mp  Figure 4.15:  IDDQ  versus C  The University of British Columbia  p D  for varying C  m p  of a faulty NOR gate.  66  Chapter 4  Test Strategy Detectability Intervals for the Floating Gate Transistor Fault  The analysis for the effects of V and C m  m p  can be summarized as follows. For V , we can m  infer that by keeping the metal potential V  m  at Vss increases the fault detectability  intervals for the Static Voltage and Dynamic Voltage test strategies (section 4.4.2). As for the Static Current strategy, applying a rising transition at V monitor the  IDDQ  m  provides a method to  current in the faulty transistor (described in section 3.3).  For the capacitance C  m p  , Section 4.4.3 suggests that with V = V m  D D  , an increase in C  m p  decreases the detectability intervals for the D V and S V testing techniques, while the intervals increase for the same with an increase in C  m p  when V = V s- As for the Static m  S  Current technique, a higher detectability interval is achieved for the Static Current testing technique when C C  m D  m p  is increased with a rising transition at V . The results for V m  Detectability  Test Strategy  D D  t  I  S S  t  T  D D  t  i  Vss  T  T  V  D D  T  t  S S  t  i  V Static Voltage V V 2.  3.  and  are summarized in table 4.1.  No.  1.  m  Dynamic Voltage  Static Current V  Table 4.1 Summary of the results for V and C, m  The University of British Columbia  67  Chapter 5 Conclusions and Future Work  5.1  Conclusions  In this thesis, the detection of floating gate faults is studied using Static Voltage, Dynamic Voltage and Static Current strategies. It is shown that the behavior of the defect depends on two classes of parameters, i.e., the predictable and the unpredictable parameters. Predictable parameters include both technological information from the process and topological information from layout. The unpredictable parameters include the random information coming from the size, location and nature of the fault. Furthermore, it is shown that the metal-poly capacitance C  m p  and the metal potential V  m  together with the unpredictable poly-bulk capacitance C b, play an extremely important P  role in determining the final output voltage and the steady state current of a faulty gate.  The University of British Columbia  68  Chapter 5  Conclusions and Future Work  We demonstrated that the three test techniques (namely, the SV, D V and SC testing strategies) are each able to detect floating gate faults for a given range of the unpredictable parameter. The Static Current strategy presents a complementary interval with respect to Static and Dynamic Voltage strategies. It is shown that a combination of a voltage and current test strategies can ensure 100% detection of the floating gate defect.  The effect of initial charge on the floating gate was also analyzed. It is shown that with an increase in the initial charge at the floating gate, the detectability intervals for the voltage strategies decrease, while the detectability interval for the current strategy increases. This again suggests a combination of both the current and voltage testing strategies to ensure a complete coverage of the floating gate faults.  Similarly, the effect of the overlapping metal potential and the corresponding metal-poly capacitance is also presented in detail. It is shown that keeping the metal potential at Vss increases the fault detectability intervals for the Static Voltage and Dynamic Voltage testing strategies. For the metal-poly capacitance, an increase in the same decreases the detectability intervals for the D V and S V testing strategies when V = V m  D D  , while the  intervals increase for the SC strategy (using the proposed technique) with an increase in C . It can be therefore, concluded that to achieve complete coverage of the floating gate m p  fault, it is mandatory to conduct both current and either of the voltage testing strategies.  The University of British Columbia  69  Chapter 5  5.2  Conclusions and Future Work  Future Work  The results in this dissertation strongly suggest that the detectability intervals are adversely affected by the initial charge on the floating gate transistor. Though it has been shown that no matter how much initial charge is present at the FGT, a combination of both the current and voltage strategies provides 100% fault coverage. However, for the cases when it is not possible to conduct both the tests due to the classical cost / efficiency trade off, the amount of initial charge on the gate becomes an extremely important factor in determining the detectability interval of the floating gate defect coverage. Further work needs to be done in this regard to determine the initial charge on the gate.  A new technique for IDDQ current monitoring was presented in this thesis assuming that the potential of the crossing metal wire is controllable. However, it was not shown how could that be achieved. Obviously, this is another design area that needs more investigation.  The University of British Columbia  70  References  6. [1]  References J.M. Soden, C.F.Hawkins, R.K. Gulati and W.Mao,  "I DQ D  Testing: A review", J.  Electron. Test: Theory andApplic, vol. 3, no.4, pp. 291-303, Dec. 1992.  [2]  T.Storey, W. Maly, J. Andrews and M . Miske, "Stuck fault and Current Testing comparison using CMOS chip test", Proc. Int. Test Conf., pp. 311-318, Oct. 1991.  [3]  V . H . Champac, R. Rodriguez-Montanes, J.A. Segura, J. Figueras and J.A. Rubio, "Fault Modeling of Gate Oxide Short, Floating Gate and Bridge Failures in CMOS Circuits", Proc. European Test Conf., pp. 143-148, April. 1991.  [4]  M.Renovell and G . Cambon, "Topology Dependence of Floating Gate faults in MOS Circuits", IEE Electron. Letters, vol. 22, no. 3, pp. 152-153, Jan. 1986.  [5]  M.Renovell and G. Cambon, "Electrical Analysis and Modeling of Floating Gate Faults", IEEE Trans. On Comp. Aided Des., pp. 1450-1458, Nov. 1992.  [6]  M . Renovell and G . Cambon, "Test Methodologies Sensitivity to Defect Parameters", Proc. Int. Test Conf., pp. 607-616, Nov. 1997.  [7]  C L . Henderson, J . M . Soden, C.F. Hawkins, "The Behavior and Testing Implications of CMOS IC Gate Open Circuits", Proc. Int. Test Conf., pp. 302-310, Oct. 1991.  [8]  H.Xue, C. D i and J.A.G Jess, "Probability Analysis for CMOS Floating gate Faults", Proc. European Des. Test Conf, pp. 443-448, Feb. 1994.  The University of British Columbia  71  References  [9]  C.F. Hawkins, J.M. Soden, A.W. Righter and F.J. Ferguson, "Defect Classes - A n Overdue Paradigm for CMOS IC Testing", Proc. Int. Test Conf., pp. 413-425, Oct. 1994.  [10]  A.D.Singh, H . Rasheed and W.W. Weber,  "IDDQ  Testing of CMOS Opens: A n  Experimental Study", Proc. Int. Test Conf., pp. 479-489, 1995.  [11] R. Rodriguez-Montanes, J.A. Segura, V . H . Champac, J. Figueras and J.A. Rubio, "Current Vs. Logic testing of Gate Oxide Short, Floating Gate and Bridging Failures in C M O S " , Proc. Int. Test Conf., pp. 510-519, Oct. 1991.  [12] W . Maly, P.K. Nag and P. Nigh, "Testing Oriented Analysis of CMOS ICs with Opens", Proc. Int. Conf. Comp. Aid. Des. (ICCAD), pp. 334-347, Nov. 1988.  [13]  V . H . Champac, J.A. Rubio and J. Figueras, "Analysis of the Floating Gate Defect in C M O S " , Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 101108, Venice, Italy, Oct. 1993.  [14] V . H . Champac, J.A. Rubio and J. Figueras* "Electrical Model of the Floating Gate Defect in C M O S ICs: Implication on IDDQ Testing", IEEE Trans. On Comp. Aided Des., Vol. 13, no. 3, pp. 359-369, Mar. 1994.  [15] V . H . Champac and J. Figueras, "Testability of Floating Gate Defects in Sequential Circuits", 13 IEEE VLSI Test Symposium, pp. 202-207, Apr. 1995. th  [16]  V . H . Champac and J. Figueras,  "IDDQ  Testing of Single Floating Gate Defects using  a Two-Pattern Vector", IEE Electron. Letters, vol. 32, no. 17, pp. 1572-1574, Aug. 1996.  The University of British Columbia  72  References  [17]  S. Johnson, "Residual Charge on the Faulty Floating gate MOS Transistor", Proc. Int. Test Conf., pp. 555-561, Oct. 1994.  [18] H . Konuk and F. J. Ferguson, "An unexpected Factor in Testing for CMOS Opens: The Die Surface", Proc. 14 IEEE VLSI Test Symposium, pp. 422-429, 1996. th  [19]  Shen J.P., Maly, W., Ferguson F.J., "Inductive Fault Analysis of MOS Integrated Circuits" IEEE Design and Test ofComp., Dec. 1985, pp. 13-26.  [20] H . Konuk, "Testing for opens in Digital CMOS Circuits", Ph D. Thesis, University of California, Santa Cruz, Dec. 1996.  [21] C. D i and J.A.G Jess, "On Accurate Modeling and Efficient Simulation of CMOS Opens", Proc. of International Test Conf, Oct. 1993, pp. 875-882.  [22] H . Konuk, F.J. Ferguson, and T. Larrabee, "Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks", Proc. of Design Automation Conf, June 1995, pp. 345 - 351.  [23] Henderson, C.L., Soden, J . M . , Hawkins, C.F., "The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits", Proc. Int. Test Conf, 1991, pp. 302-310.  [24] Johnson, S., " The Detection of Floating Gate Faults and Their Effect on Circuit Reliability", Proc. 6 Int. Conf. On Quality in Electronic Components, 1993, pp. th  595-597.  [25] Al-Arian, S.A., Agrawal, D.P., "Physical Failures and Fault Models of CMOS Circuits", IEEE Trans. Circ. Systems, Vol. CAS-34, No. 3, Mar. 1987, pp. 269-279.  The University of British Columbia  73  References  [26]  Elleuch, M . Renovell, J. Lassale and G . Cambon, "Layout Dependent Fault Modeling Methodology: Floating Gate Transistor", ICM'88 First Int. Conf. on Microelectronics, Nov. 1988.  [27]  K . Baker and B . Verhelst, " I Q Testing because zero defect isn't enough", Int. D D  Test Conf., Sept. 1990, pp. 253-254.  [28]  F.J. Ferguson, and J.P. Shen, " A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Trans. Computer Aided Design, vol. CAD-7, no. 11, pp. 11811194, Nov. 1988. •  [29]  C C . Tornic and W.R. Scott, "Simulation of Stuck-Open Faults in CMOS Integrated Circuits", Proc. Int. Symp. Test and Failure Analysis, pp. 53-56, 1981.  [30]  B.W. Woodhall, B.D. Newman and A . G . Sammuli, "Empirical Results on Undetected CMOS Stuck-open Failures", Proc. Int. Test Conf, pp. 166-170, 1987.  [31]  P . C Maxwell, R.C. Aitken, V . Johansen, and I. Chiang, "The effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverage Do We Need?", Proc. Int. Test. Conf., pp. 168-177, 1992.  [32]  F. Fantini, and C. Morandi, "Failure Modes and Mechanisms for V L S I ICs - a Review", IEE Proceedings, Vol. 132, No. 3, pp. 74-81, June, 1985.  [33]  J.M. Acken, "Testing for Bridging Faults (shorts) in CMOS Circuits", Proc. Design Automation Conf, pp. 717-718, 1983.  The University of British Columbia  74  References  [34]  W. Maly, "Realistic Fault Modeling for V L S I Testing", Proc. IEEE Design Automation Conf., pp. 173-180, 1987.  [35]  Stapper, C.H., "Modeling of Integrated Circuit Defect Sensitivities", IBM J. Res. Dev., Vol. 27, 1983, pp. 549-557.  [36]  S. Rafiq, A . Ivanov, M . Renovell and S. Tabatabaei, " Testing for Floating Gate Defects in C M O S Circuits", submitted for publication at The Seventh Asian Test Symposium (ATS'98), Dec. 1998.  [37]  Spectre Reference Manual, Cadence Design Systems, Inc., March 1997.  [38]  N . Weste and K . Eshragian, "Principles of CMOS VLSI Design, A Systems Perspective, 2 ed. Addison-Wesley, 1993. n d  [39]  N . K . Jha, S. Kundu, " Testing and Reliable Design of C M O S Circuits", Kluwer Academic Publishers, 1990.  The University of British Columbia  75  Appendix A  Appendix A: Model Parameters for the Transistors Used in Simulations  # OPT("/I7/M0"," ??'  i d s = -861.1e-15  vgs = -3.3  vbs = -1.193e-9  v t h = -863.8e-3  v d s a t = -2.001  gm = 245.4e-15  gmbs = 51.09e-15  gameff = 390.6e-3  b e t a e f f = 87e-6  cbd = 2.091e-15  cgs = 1.624e-15  cgd = 1.624e-15  cgb = 199.1e-18  r o n = 1.385e3  i b u l k = 11.34e-21  pwr = 1.027e-21  gmoverid = -285e-3  isub = 0  age = 0  he_vdsat = 0  vds = -1.193e-9 gds = 212e-6 cbs = 2.091e-15 i d = -861.1e-15 stress = 0  # OPT("/I7/M2","??") i d s = -25.19e-18  vgs = -1.193e-9  vbs = -1.193e-9  v t h = -830.8e-3  v d s a t = -35.13e-3  gm = 635.4e-18  gmbs = 202.4e-18  gameff = 390.6e-3  b e t a e f f = 124.4e-6  c b d = 1.526e-15  cgs = 325.9e-18  c g d = 325.9e-18  cgb = 1.48e-15  r o n = 35.19el5  i b u l k = 10e-15  pwr = 8.885e-15  gmoverid = -25.23  isub = 0  age = 0  he v d s a t = 0  vds = -886.3e-3 gds = 23.78e-18 cbs = 2.091e-15 i d = -10.03e-15 stress = 0  # 0PT("/I7/M1","??")  The University of British Columbia  76  Appendix A  i d s = 2.442e-12  vgs = 0  vbs = 0  v t h = 446.3e-3  v d s a t = 34.67e-3  gm = 59.17e-12  gmbs = 21.99e-12  gameff = 512.9e-3  b e t a e f f = 465.5e-6  cbd = 319.5e-18  cgs = 369.5e-18  cgd = 369.5e-18  cgb = 1.03e-15  ron = 988.6e9  i b u l k = -10e-15  pwr = 5.918e-12  gmoverid = 24.23  isub = 0  age = 0  he_vdsat = 0  vds = 2.414 gds = 3.861e-12 cbs = 629.6e-18 i d = 2.452e-12 stress = 0  # OPT ( " / 1 7 / f l o a t i n g , .nmos", "??") i d s =280.3e-9  vgs = 480.8e-3  vbs = 0  v t h = 446.3e-3  v d s a t = 34.67e-3  gm = 6.793e-6  gmbs = 2.021e-6  gameff = 512.9e-3  b e t a e f f = 465.5e-6  cbd = 319.5e-18  cgs = 369.5e-18  cgd = 369.5e-18  cgb = 826.7e-18  ron = 8.61e6  i b u l k = -10.02e-15  pwr = 676.6e-9  gmoverid = 24.23  isub = 0  age = 0  he_vdsat = 0  The University of British Columbia  vds = 2.414 gds = 443.3e-9 cbs = 629.6e-18 i d = 280.3e-9 stress = 0  77  Appendix B  Appendix B: Hspice Netlist The Hspice netlist for the Faulty NOR gate in Figure 3.1:  * # FILE NAME: /NFS/ABAN/INT16/HOME2/SUMBALR/CAD/CDS/CMOSIS 5/SIMULATION/ *  FG_nr2_layout_sim_org2/spectres/schematic/netlist/  *  FG_nr2_layout_sim_org2.C.raw  * N e t l i s t output  f o r spectres.  * Generated on May 11 22:54:07 1998  * g l o b a l net d e f i n i t i o n s .GLOBAL vdd\! v s s \ !  s i m u l a t o r lang= s p e c t r e * F i l e name: floating_Gate_simualtion_FG_nr2_layout_sim_org2_schematic.s. * Subcircuit f o r c e l l :  FG_nr2_layout_sim_org2.  * Generated f o r : s p e c t r e s . * Generated on May 11 22:54:09 1998.  * vpwl Instance V5 = s p e c t r e s d e v i c e v5 v5  ( i p l vss\!)  vsource  type= pwl wave=  [ 400e-12 3.3 500e-12  0.0 1.5e-9 0.0 +1.6e-9 3.3  ]  * vpwl Instance V4 = s p e c t r e s d e v i c e v4 v4  (netlO vss\!)  vsource  type= pwl wave=  [ 400e-12 0.0 500e-12  0.0 1.5e-9  The University of British Columbia  78  Appendix B  +0.0  1.6e-9 3.3  * hnr2_type2  ]  Instance 17 = s p e c t r e s d e v i c e x i 7  * Instance o f L i b : F l o a t i n g G a t e s ,  C e l l : hnr2_type2,  View:  schematic xi7  (vdd\! v s s \ ! v f g i p l in2 output)  * tiedown  Instance 14 = s p e c t r e s d e v i c e x i 4  * Instance of L i b : cmosis5, xi4  hnr2_type2_gl  Cell:  tiedown,  View:  schematic  (vss\!) tiedown_g2  * vdc Instance Vin2 = s p e c t r e s d e v i c e vin2 vin2  (in2 vss\!)  vsource  type= dc dc=0.0  * vdc Instance VI = s p e c t r e s d e v i c e v l vl  (vdd\! vss\!)  vsource  type= dc dc=+3.30000000E+00  * cap Instance C l l = s p e c t r e s d e v i c e e l l ell  (vfg netlO)  c a p a c i t o r c=750e-18 m=l.0  * cap Instance Cgd = s p e c t r e s d e v i c e cgd cgd  (output v f g )  c a p a c i t o r c=100e-18 m=1.0  * cap Instance Cpb = s p e c t r e s d e v i c e cpb cpb  (vfg vss\!)  c a p a c i t o r c=+5.00000000E-15 m=1.0  ic=+0.00000000E+00  s i m u l a t o r lang=  spice  The University of British Columbia  79  Appendix B  s i m u l a t o r lang=  spectre  s i m u l a t o r lang= s p i c e  *Model d e f i n i t i o n s  * F i l e name: cmosis5_tiedown_schematic.s. * Subcircuit f o rc e l l :  tiedown.  * Generated f o r : s p e c t r e s . * Generated on May 11 22:54:09 1998. s i m u l a t o r lang=  spectre  * t e r m i n a l mapping: gndPoint = gndpoint subckt tiedown_g2 gndpoint  * r e s i s t o r Instance R3 = s p e c t r e s d e v i c e r3 r3  (0 gndpoint)  r e s i s t o r r=1.0 m=1.0  s i m u l a t o r lang= s p i c e  s i m u l a t o r lang=  spectre  * End o f s u b c i r c u i t  definition,  ends tiedown_g2 s i m u l a t o r lang= s p i c e  * F i l e name: F l o a t i n g G a t e s _ h n r 2 _ t y p e 2 _ s c h e m a t i c . S . * Subcircuit f o rc e l l :  hnr2_type2.  * Generated f o r : s p e c t r e s .  The University of British Columbia  80  Appendix B  * Generated on May 11 22:54:08 1998.  s i m u l a t o r lang= s p e c t r e * t e r m i n a l mapping: VDD! = vdd\! *  VSS! = v s s \ !  *  fin = fin  *  ipl =ipl  *  ip2 = ip2  *  op = op  subckt hnr2_type2_gl  * n f e t 3 Instance mfloating_nmos  vdd\! v s s \ ! f i n i p l ip2 op  floating_nmos  = s p e c t r e s d e v i c e mfloating_nmos  (op f i n v s s \ ! vss\!)  CMOSN  region=  triode  w=800e-9 l=600e-9 +as=+8.00000000E-13 ad=+8.00000000E-13 ps=+3.60000000E-06 pd=+3.60000000E-06 +nrd=+l.25000000E+00 nrs=+l.25000000E+00 m=1.0  * n f e t 3 Instance Ml = s p e c t r e s d e v i c e ml ml  (op ip2 v s s \ ! vss\!)  CMOSN  region=  t r i o d e w=800e-9 l=600e-9  +as=+8.00000000E-13 ad=+8.00000000E-13 ps=+3.60000000E-06 pd=+3.60000000E-06 +nrd=+1.25000000E+00 nrs=+l.25000000E+00 m=1.0  * p f e t 3 Instance M2 = s p e c t r e s d e v i c e m2 m2 (op i p l n e t l 4 vdd\!)  CMOSP  region=  t r i o d e w=le-6 l=600e-9  +as=+l.00000000E-12 ad=+l.00000000E-12 ps=+4.00000000E-06 pd=+4.00000000E-06 +nrd=+l.00000000E+00 nrs=+l.00000000E+00 m=1.0  The University of British Columbia  81  Appendix B  * p f e t 3 Instance MO = s p e c t r e s d e v i c e mO mO  (netl4 ip2 vdd\! vdd\!)  CMOSP  region= t r i o d e w=le-6 l=600e-  9 +as=+l.00000000E-12 ad=+l.00000000E-12  ps=+4.00000000E-06  pd=+4.00000000E-06 +nrd=+l.00000000E+00 nrs=+l.00000000E+00 m=l.0 s i m u l a t o r lang= s p i c e  s i m u l a t o r lang=  spectre  * End of s u b c i r c u i t  definition,  ends h n r 2 _ t y p e 2 _ g l s i m u l a t o r lang= s p i c e  s i m u l a t o r lang=  spectre  s i m u l a t o r lang= s p i c e  * Include  files  save  xi7.m45:vth  save  xi7.m47:vth  save  xi7.m43:vth  save  xi7.m41:vth  save xi7.mfloating_nmos:cbs save xi7.mfloating_nmos:cgs save xi7.mfloating_nmos:cgd save  xi7.mfloating_nmos:cgb  The University of British Columbia  82  Appendix B  save  xi7.mfloating_nmos:cbd  save  xi7.mfloating_nmos:vth  save  xnmosvinl:vth  *Only one l i b r a r y can be s e l e c t e d i n a time. *  * *#define a n y D e s i r e d L i b r a r y * n5bo b e i n g the d e f a u l t  #define n5bo  *#include  anyDesiredModelFile  * There a r e cmosis5.Ievel3 and cmosis5.bsiml * cmosis5.Ievel3 b e i n g the d e f a u l t #include  "cmosis5.Ievel3"  * #unde f theUs edL i b r a r y  #undef n5bo  s i m u l a t o r lang= s p e c t r e  * End of N e t l i s t * simulator simOptions *  lang=spectre options  rawfmt=psfbin r a w f i l e = " % C : h / . . / p s f "  The University of British Columbia  83  Appendix B  +  currents=all  +  gmin=  +  reltol=  1.00000000E-03  +  scale=  1.0000000  +  scalem=  1.0000000  +  vabstol=  1.00000000E-06  +  iabstol=  1.00000000E-12  +  temp=  27  +  tnom=  27  +  rforce=  +  maxwarns =  +  digits=  +  cols=  +  pivrel=  +  c k p t c l o c k = 1800  +  save=allpub  modelParameter element  1.00000000E-15  1.0000000 5 5 80 1.00000000E-03  info  what=models where=rawfile  i n f o what=inst  where=rawfile  outputParameter i n f o what=output where=rawfile timeSweep t r a n  stop= 5.00000E-09  +  write="spectre.ic"  +  writefinal="spectre.fc"  +  annotate=status  +  compression=no  +  maxiters=  5  finalTimeOP i n f o what=oppoint  The University of British Columbia  where=rawfile  84  

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