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Built-in jitter test schemes for mixed-signal integrated circuits Dalmia, Kamal 1996-12-31

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Built-in Jitter Test Schemes for Mixed-Signal Integrated Circuits By Kamal Dalmia B . E . , University of Delhi, Delhi, India, 1993.  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in  THE FACULTY OF GRADUATE STUDIES ELECTRICAL ENGINEERING  We accept this thesis as conforming to the required standard  THE UNIVERSITY OF BRITISH COLUMBIA April  1996  © K a m a l Dalmia,  1996  In  presenting  degree freely  this  at the  thesis  in  partial  fulfilment  University  of  British  Columbia,  available for reference  copying  of  department publication  this or of  thesis by  this  for  his thesis  and study. scholarly  or for  her  of  I further  purposes  may  gain shall  fJLclf'i  The University of British Columbia Vancouver, Canada  Date  DE-6 (2/88)  n  Ay*  that  agree  It  permission  is  understood be  ^  for  allowed  an  advanced  Library shall make  granted  not  rxc*-*'  that  the  be  permission.  Department of  requirements  I agree  representatives.  financial  the  by  for  the that  without  it  extensive  head  of  my  copying  or  my  written  Abstract  ii  Abstract Recent years have seen an unparalleled growth i n the speed and complexity of V L S I circuits.  Analog and mixed-signal circuits are going through a resurgence and continue  to pose new challenges to V L S I test engineers.  The state-of-the-art i n the mixed-signal  and analog test domain is to use application-specific test methodologies to tackle individual problems.  The same is true for testing the high-speed clock signals used i n present day  integrated circuits (ICs) for their analog attributes. Jitter is one of the ways of quantifying the accuracy of a clock signal. Present day digital automatic test equipment (ATE) does not possess enough resolution to be suitable for jitter tests of high-speed clock signals such as S O N E T ' s (Synchronous Optical Network) 155.52 M H z and 622.08 M H z . In this thesis, the jitter test problem of high-speed clocks is approached with a built-in self-test (BIST) perspective.  A B I S T scheme is presented for the jitter tolerance test of clock and data  recovery units typically found i n data transceiver ICs. A cost-effective scheme based on the utilization of existing components for test purposes is presented. Some possible variations of the presented scheme are discussed. A second B I S T scheme, focused on jitter testing of clock signals i n a sampling-based digital signal processing (DSP) environment, is presented. Again, the focus is on the re-use of typically existing blocks on such ICs.  Table of Contents  III  Table of Contents Abstract  ii  List of Tables  vi  List of Figures  vii  Acknowledgments 1 Introduction 1.1 Scope of Thesis 2 Jitter  x 1 5 8  2.1 Definitions  8  2.2 Effects of Jitter  9  2.3 Sources of Jitter  10  2.3.1 Telecom Systems  10  2.3.2 Sampling Systems  11  2.4 Jitter Characterization  11  2.5 Jitter Specifications  12  2.5.1 Jitter Tolerance  13  3 A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  19  3.1 A S O N E T Node  19  3.2 Theory of Jitter Tolerance  21  Table of Contents  iv  3.3 Conventional Jitter Tolerance Test Schemes  28  3.4 The B I S T Scheme  30  3.4.1 Simulation  39  3.4.2 Hardware Verification  44  3.5 Variations of the B I S T Scheme  50  3.5.1 A Reduced-Set Jitter Tolerance Test  50  3.5.2 L o c k - i n Range Test  55  3.5.3 Conclusions  56  4 A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs . . . . 57 4.1 Jitter Characterization 4.1.1 The Basis of the B I S T Scheme  58 61  4.2 The B I S T Scheme  63  4.2.1 Simulation  67  4.2.2 Hardware Verification  69  5 Conclusions and Future Work  73  5.1 Conclusions  73  5.2 Future Work  74  References  76  Appendix A List of Acronyms  80  Appendix B Schematics  82  Appendix C Simulation Results  89  Appendix D HDL Codes Appendix E M A T L A B Code  . . . 98 103  Table of Contents  Appendix F SONET Jitter Specifications  v  107  F . l Jitter Transfer :  107  F.2 Output Jitter :  108  Appendix G Frequency Test  109  List of Tables  vi  List of Tables Table 2.5.1  Jitter tolerance Specification [Syn94]  13  Table 3.4.1  Simulation and theoretical results  42  Table 3.4.2  Jitter generation comparing predicted and measured values for f  m  = 5  47  MHz Table 3.4.3  Jitter generation comparing predicted and measured values for f  m  = 2  MHz Table 3.4.4  48  Jitter generation comparing predicted and measured values for fm = 1 MHz  48  Table 3.5.5  Calculation of the maximum frequency deviation  52  Table 4.2.1  Experimental results  71  Table F . l . l  Jitter transfer specification [Syn94]  107  List of Figures  vii  List of Figures Figure 1.1  The B I S T methodology  2  Figure 2.1.1  Illustration of jitter i n the time domain  8  Figure 2.5.2  Input jitter tolerance specification [Syn94]  13  Figure 2.5.3  Phase Modulation  16  Figure 2.5.4  Relation between P M and F M  17  Figure 3.1.1  A typical S O N E T node  20  Figure 3.2.2  B l o c k diagram of a P L L  21  Figure 3.2.3  Linear ac model of a P L L [Wol91]  22  Figure 3.2.4  Loop Filter  24  Figure 3.2.5  Frequency response of the loop  Figure 3.2.6  Multiplier type phase detector  25  Figure 3.2.7  Phase detector characteristics  26  Figure 3.2.8  Closed-loop response of the P L L  27  Figure 3.2.9  Open-loop response of the P L L  27  Figure 3.2.10  Jitter tolerance of the P L L  28  Figure 3.4.11  Jitter tolerance B I S T scheme  31  Figure 3.4.12  Generation of jittered clock  32  Figure 3.4.13  A C coupling  34  Figure 3.4.14  Conversion of N R Z data to R Z - l i k e data.... . :  41  Figure 3.4.15  Simulated and theoretical jitter tolerance  43  filter  25  List of Figures  viii  Figure 3.4.16  Experimental vs. theoretical results (5 M H z )  49  Figure 3.4.17  Experimental vs. theoretical results (2 M H z )  49  Figure 3.4.18  Experimental vs. theoretical results (1 M H z )  50  Figure 3.5.19  Phase error response of the P L L  54  Figure 4.1  A DSP-based mixed-signal IC  58  Figure 4.1.2  Illustration of jitter on the m * sampling edge  60  Figure 4.2.3  The block diagram for B I S T  64  Figure 4.2.4  The simulation block diagram  68  Figure 4.2.5  Jitter spectrum with A H D L simulation  69  Figure 4.2.6  Experimental setup for the B I S T scheme  70  Figure 4.2.7  Theoretical vs. experimental results  72  Figure 4.2.8  F F T plot of the sampled sinusoid  72  Figure B . l  L o w pass filter for C S U  83  Figure B . 2  Phase detector used i n C R U and C S U  84  Figure B.3  The C l o c k and data recovery unit ( C R U )  85  Figure B.4  The C l o c k synthesis unit ( C S U )  86  Figure B.5  B I S T scheme for DSP-based ICs.  87  Figure B . 6  B I S T scheme for jitter tolerance test  88  Figure C . l  N o bit i n error, data transition density = 100 %  89  Figure C.2  Various wavefroms with data transition density = 100 %  90  Figure C.3  Bits i n error with data transition density = 100 %  91  Figure C.4  Bits i n error with pseudo-random data  92  List of Figures  ix  Figure C.5  Various waveforms with pseudo-random data  93  Figure C.6  Jitter generation with sinusoidal input  94  Figure C.7  Jitter generation with triangular input  95  Figure C.8  Jitter generation with square wave input  96  Figure C.9  Jitter generation with square wave input added to V C O control net.  Figure F . l . l  Jitter transfer specification [Syn94]  107  Figure G . l  Frequency test  109  . 97  Acknowledgment  x  Acknowledgments I wish to express m y sincere gratitude to m y advisor Professor Andre Ivanov, for his guidance, support and advice. I am deeply indebted to M r . Brian Gerson, M r . Manop and M r . Curtis Lapadat of PMC-Sierra, Inc. for their insightful guidance and invaluable discussions. In addition, I thank the other members of my dissertation committee, Professor H . M . Alnuweiri and Professor D . Pulfrey for their precious time. I also thank M r . Sassan Tabatabaei for his comments and discussions. I would like to acknowledge Micronet, P M C Sierra, Inc., C M C and N S E R C for providing financial support for this research.  Special  thanks to Maneesha Agarwal for her love, patience and encouragement throughout this thesis. Lastly, even though words cannot fully explain, I attempt to express m y deep gratitude and indebtness to m y parents and family for their love, encouragement, support and understanding at every stop of the way.  K a m a l Dalmia  Chapter 1 Introduction  Testing for manufacturing defects and fault diagnosis are vital for the quality assurance of electronic components.  W i t h the rapid advancement i n integrated circuit technology,  these aspects have become critical i n determining the overall cost of the components and systems.  Over the years, testing has become a major factor i n determining the time to  market for Very Large Scale Integration (VLSI) circuits. Historically, the focus of the test community has been biased towards digital circuits due to their sheer abundance. However, this scenario is changing rapidly with the increasing integration of analog and digital functions on single integrated circuits. The class of integrated circuits (ICs) with both analog and digital components is commonly referred to as mixed-signal. This integration of analog and digital components is posing new challenges to V L S I test engineers. The primary reason for this is the fact that the automatic test equipment (ATE) that has been traditionally employed and designed for testing purely digital circuits is incapable of meeting the stringent demands of mixed-signal testing [Meh93]. In recent years, some A T E vendors have introduced test equipment with mixed-signal test capabilities. However, most of these testers are either incapable of meeting the application-specific requirements of analog components, or are too expensive to be cost-effective i n a volume-production environment [Ton93]. Other factors that render mixed-signal testing a difficult task are the limited pin counts of chips and the restricted controllability and observability of internal nodes. The recognition of these  1  I. Introduction  2  difficulties has caused I C designers to more seriously consider test issues and adopt designfor-testability techniques [Bar87]. Built-in self-test (BIST) is a well known design for testability technique [Ton93] [Ter93]. B I S T techniques alleviate some of the problems associated with internal testing. A typical B I S T methodology involves the generation of test stimuli and the evaluation of test responses by adding special circuitry to the basic IC. F i g . 1.1 depicts the basic methodology of a B I S T scheme.  ic  Test Stimulus Generator  ;  Device Under Test  DUT  Test Response Evaluator  Figure 1.1 The BIST methodology.  The test stimulus and the test response evaluator are often realized using linear feedback shift registers ( L F S R ) [Bar87]. B I S T techniques for testing digital circuits have reached a level of sufficient maturity.  However, analog and mixed-signal B I S T research is still  i n its infancy. Present day B I S T techniques for analog and mixed-signal ICs are essentially application specific, i.e., the test circuitry is designed for testing a specific category of circuits and cannot be employed for other circuits i n general. The significant advantages of a B I S T scheme over the conventional A T E based schemes are the following :  I. Introduction  a.  3  L o w cost : If a B I S T scheme is carefully designed with optimum area overhead, the result is substantial savings i n the overall cost of the testing. The savings i n the total cost, in turn, result from the savings i n the external test equipment and the overall test time.  b.  Test time : In general, the external test equipment requires a longer setup time than the circuitry present on the I C . In the case of a B I S T scheme, the test circuitry is present on the I C itself and hence results i n a shorter test time.  c.  Cable parasitics : In high-speed testing, the cables that run from the tester to the D U T can cause significant parasitics to alter the results of a test. It is always desirable to keep the cable lengths to a minimum. The B I S T technique alleviates this problem to a significant extent as the high-speed paths are usually on the chip itself.  d.  Upgrade with technology : A s the speed of the ICs advances, faster testers are required to meet the demands of newer generation of ICs. In a B I S T scheme, the technology and the speed of the test circuitry advances with that of the D U T , resulting i n savings i n the capital expenditure of tester upgrades. Though the popularity of the B I S T methodology is growing at a fast rate, test engineers  often have to tackle the limitations of the B I S T methodology. The significant limitations of the B I S T scheme are the following : a.  Area-overhead : The test circuitry added to the basic circuit is duplicated on every I C for a B I S T scheme. If the test area overhead is excessive, the product yield may drop resulting i n higher overall cost of the I C .  b.  Performance degradation : In some cases such as high-speed digital circuits and analog circuits, added circuitry may introduce noise into the high-speed paths resulting i n an  1. Introduction  4  overall performance degradation, c.  Limited test capabilities : Due to the limitation of the test resources that may be added to an IC, in most BIST cases, only a limited set of tests may be performed as compared to the tests possible with ATEs. Clocking is an integral part of all synchronous circuits. Clock accuracy is crucial in  many computer, telecommunication, and signal processing applications. The clock accuracy, in particular with respect to the occurrence time of clock edges, is becoming increasingly difficult to achieve with increasingly fast clock rates. The timing precision required for the clocks in the range of megahertz is of the order of picoseconds.  Various attributes  such as frequency stability and skew are used to quantify the accuracy of clock signals. One of the standard ways of quantifying the accuracy of a clock signal is through jitter specifications. Jitter is defined as the short-term variations of the significant instants of a digital signal from their ideal position in time [Syn94]. Like other noise forms, jitter can affect system performance, e.g., by introducing bit errors in a digital telecommunication application or by degrading the signal to noise ratio (SNR) in a sampling-based system. With the advent of high-speed information-based systems, there is increasing interest in the systematic measurement of jitter. With digital systems operating at a speed of hundreds of megahertz, commonly available ATEs prove to be incapable of being effectively utilized for testing telecommunication ICs as they are limited to 100-200 MHz clock speeds [Hot92]. Another jitter related problem, mainly associated with clock and data recovery applications, is the production-stage testing for jitter tolerance of clock recovery units (CRU). Common applications which find widespread use of CRUs are data telecommunication ICs,  1. Introduction  5  disk drive storage systems, compact disk players and satellite link communications [Ram94] [Wol91]. Jitter tolerance is a receiver's ability to recover data without errors i n the presence of jitter. In general, a typical digital A T E is incapable of generating jittered data with the required precision (picosecond range for S O N E T / S D H [Syn94]). Hence, dedicated jitter generators and analyzers are used for jitter tolerance tests. Most dedicated jitter generators are designed for characterization tests and are expensive and unsuitable for production-stage testing due to long setup and operational delays. Hence, neither A T E s nor dedicated characterization test equipment provide for l o w cost and efficient volume-production testing. Moreover, there is no published B I S T technique for jitter tolerance testing.  1.1 Scope of Thesis Recognizing the limitations of generic digital A T E ' s with respect to the measurement of analog signals in general and the clock attributes i n particular, this thesis approaches the jitter test problem from a B I S T perspective. Most digital integrated circuit designers are familiar with the time domain representation of jitter. The time domain measurements are usually easier and faster than the frequency domain measurements. However, time domain treatment is often insufficient for phase locked loops (PLLs).  P L L s are the most commonly used  components i n clock generation and clock recovery applications. For P L L s , some particular frequencies may be more offensive than others. Due to this, the study of the spectral content of clock signals is important. Hence, a frequency domain approach has been adopted i n this thesis to tackle the problem. A s a first step towards the attempt to solve the jitter test problem, a comprehensive overview of jitter is provided i n Chapter 2. The formal definition of jitter is presented,  1. Introduction  6  followed by a discussion on the sources and effects of jitter i n sampling-based environments and high-speed data transceiver ICs. Since modern high-speed data telecom equipment must comply with international standards and specifications to ensure compatibility between the equipment manufactured by different vendors and subsequent successful implementation of networks, I C manufacturers must test their components against a variety of applicable jitter specifications. Test engineers dealing with jitter must have a thorough understanding of the specifications. Recognizing this, an overview of Synchronous Optical Networks ( S O N E T ) specifications is also presented i n this chapter. Chapter 3 describes a novel B I S T scheme for the jitter tolerance test of clock and data recovery units (CRUs) commonly found i n the receiver section of high-speed data transceiver ICs. The B I S T scheme is designed to test a C R U against S O N E T jitter tolerance specifications. A n overview of typical S O N E T nodes is presented. Following this, conventional jitter tolerance test schemes are discussed. The requirement that a C R U be tested for jitter tolerance i n the presence of a broad range of jitter amplitudes and frequencies make the "traditional" jitter tolerance test very time-consuming and cumbersome. The presented B I S T scheme effectively tackles the problem. The flexibility of the methodology leads to some variations i n implementation which are discussed at the end of the chapter. With ever-increasing clock speeds, the jitter constraints become increasingly stringent. To measure l o w amounts of jitter the test equipment must have superior resolution. A direct implication of this requirement is high cost. Chapter 4 presents a B I S T scheme for jitter measurement of clock signals i n a sampling based I C . The presented scheme is applicable to the class of circuits which constitute a sampling circuit such as an analog-to-digital converter  1. Introduction  7  ( A D C ) and a digital signal processing (DSP) core capable of performing Discrete Fourier Transforms (DFT). Mathematical analysis leading to the concept underlying the B I S T scheme is also presented. The B I S T schemes presented i n this thesis are a step towards increasing the awareness and recognition of the feasibility of the 'self-test' philosophy i n those applications which are traditionally considered unsuitable for a self-test approach. This thesis addresses various aspects of jitter testing, such as, jitter measurement and the jitter tolerance test, but the problem is by no means completely solved.  Some possible variations of the presented  scheme are mentioned for future work, along with conclusions, i n Chapter 5.  Chapter 2 Jitter  2.1 Definitions Jitter is defined as the short term variation of the significant instants of a digital signal from their ideal position i n time [Syn94]. In other words, jitter is the short term variation of the significant edges of a digital signal from an ideal clock running at an average rate equal to that of the signal itself [You94]. Jitter is also defined as undesired phase variation of the signal, or i n other words, as the phase noise [You94]. F i g . 2.1.1 illustrates the concept of jitter i n the time domain.  Ideal Signal  2T  3T  4T  5T  6T  7T  Jittered Signal »B°  2T  3T  4T  5T  6T  Time Figure 2.1.1 Illustration of jitter in thetimedomain. 8  7T  2.  Jitter  9  In F i g . 2.1.1, ' A ' represents an ideal pulse stream and ' B ' represents the jittered version of signal ' A ' . Significant edges of the signal ' A ' are ideally spaced i n time while the edges of signal ' B ' are shifted from their ideal position and hence said to be jittered.  2.2 Effects of Jitter  L i k e other forms of noise, jitter is undesirable due to its negative effect on a system's performance.  In a typical digital telecommunication system, bit streams are transmitted  serially. Most often, it is not practical to transmit a reference clock along with the data. Hence, a receiver is required to recover the clock from the received data and re-time the data using the recovered clock. In real systems, the received data is jittered due to various stages of regeneration and the non-ideal behavior of network components. The jitter on the received data may lead to bit-errors during the recovery. If the number of the bits i n error is beyond the capabilities of error detection and correction circuits, the data becomes useless. In a sampling-based system which deploys the conversion of continuous time analog signals into discrete time signals, jitter on the sampling clock leads to the addition of random noise to the discretised signal. Such noise degrades the signal-to-noise ratio of the signal. The major factors which limit the accuracy and speed of analog-to-digital convenors are jitter, harmonic distortion, and non-linearity [Shi90]. However, some other factors such as temperature may be important i n some particular applications. Hence, the control and measurement of jitter is extremely important i n such systems.  2.  Jitter  10  2.3 Sources of Jitter 2.3.1 Telecom Systems The primary sources of jitter i n a digital telecommunication system are regenerators and multiplexors [Tri89]. In a typical data transceiver, a 'clean' clock signal is synthesized by the transmitter section. This clock signal is used to transmit the data i n a bit-serial manner. The transmitted data, on its way to the receiver, passes through various regenerators and multiplexors which introduce jitter into the signal. Commonly available regenerators use clock extraction and re-transmission using the extracted clock [Tri89]. The process of clock extraction and re-transmission is rather imperfect and involves timing non-idealities. Due to cascading of regenerators i n most systems, jitter accumulation takes place and results i n a higher net jitter faced by the receiver. In the preceding discussion it was mentioned that the signal at the output of a transmitter is a 'clean' signal. However, this does not imply that the transmitted signal is jitter-free. Instead, it means that the signal contains acceptably l o w amounts of jitter. Standards such as A N S I T l . 105.03-1994 [Syn94] specify the limits of acceptable jitter at the output of transmitters.  Typically, transmitters use some form of clock multiplier or synthesizer that  generates a line rate clock using a phase-locked loop ( P L L ) and a crystal reference. P L L clock synthesizers are prone to introduce their internal phase noise to the generated clock signal i n the form of jitter. This property is often referred to as 'jitter generation'. Primary sources of a P L L ' s internal phase noise are the input phase noise and the voltage controlled oscillator ( V C O ) phase noise. found i n [Wol91].  A comprehensive treatment of P L L internal noise can be  2.  Jitter  11  2.3.2 Sampling Systems A sampling system typically comprises an analog-to-digital convenor, an analog signal source, and a digital signal processing circuit. Most analog-to-digital convenors can be thought of as a combination of a sampling circuit, a quantization circuit, and a digitization circuit. In such a sampling system, the primary sources of timing jitter are - (a) the sampling clock jitter, (b) the sampling circuit jitter and (c) the input signal jitter [Shi90]. A s described earlier, when a clock is synthesized using a P L L , it constitutes the internal phase noise of the P L L in the form of jitter. When such a clock is used i n a sampling system, it is viewed as the sampling clock jitter ((a) above). With a jittered sampling clock, the analog signal is sampled at non-ideal time instants. This leads to unintended amplitudes of the analog signal being recorded and hence results i n amplitude noise being added to the signal. Thermal noise in the sampling circuit also leads to inaccuracy i n timing and subsequendy to further jitter being added to the signal. This form of noise is referred to as the sampling circuit jitter ((b) above). Normally, the signal being sampled has its own jitter and is reffered to as the input signal jitter ((c) above). Though band-limiting is inherent i n sampling and it reduces the signal generator jitter (input signal jitter), substantial jitter can be contributed to the overall jitter by this component. Shinagawa et al. [Shi90] present a method for separately estimating the three forms of jitter i n a sampling system.  2.4 Jitter Characterization Jitter is a form of noise and is generally random i n nature. Some forms of jitter such as pattern dependent jitter [Wol91] i n clock recovery applications are input specific. However,  2.  Jitter  12  since a typical input to such systems is often random or pseudo-random serial data, pattern dependent jitter can also be classified as random jitter. Similar to many noise forms, the Gaussian distribution function is the most commonly used function to represent jitter for analytical purposes [Shi90][Wag91][Wag90]. The jitter tolerance specification for S O N E T network elements is an exception to the practice of using a Guassian distribution function.  S O N E T jitter tolerance specifications  require that the clock signal be modulated by a sequence of single frequency sinusoids be used for testing as opposed to a signal containing broadband noise.  The jitter tolerance  specifications for S O N E T are discussed i n detail i n the next section.  2.5 Jitter Specifications S O N E T is a digital hierarchy interface based on a basic unit of 51.84 Mbps as the transmission rate. S O N E T was initially deployed i n North America. Later on, Synchronous Digital Hierarchy (SDH) was introduced as an international version of S O N E T . S D H is designed to support the European digital data networks. S D H provides for traffic interfaces which are vendor-independent.  The basic rate of 51.84 Mbps is known as O C - 1 or STS-1  (Optical Carrier at level 1 or Synchronous Transport Signal at L e v e l 1). Subsequently, the higher rates are known as O C - N or S T S - N [Fer94] [Hot92]. A t 155.52 Mbps (OC/STS-3), the jitter specifications are defined for optical and electrical interfaces. For higher rates, they are defined for optical interfaces only. The following is an overview of S O N E T / S D H jitter specifications for a network element.  2.  Jitter  13  2.5.1 Jitter Tolerance Input jitter tolerance is the peak-to-peak (p-p) amplitude of sinusoidal jitter applied on the input of an O C - N equipment interface that causes an equivalent 1 d B optical or electrical power penalty [Syn94].  f1  f2  f3  ft  Frequency Figure 2.5.2 Input jitter tolerance specification [Syn94].  Table 2.5.1  Jitter tolerance Specification [Syn94].  OC/STS  fo  fl  f2  f3  ft  A l (UI  A 2 (UI  A 3 (UI  level  (Hz)  (Hz)  (Hz)  (kHz)  (kHz)  P-P)  P-P)  P-P)  1  10  30  300  2  20  0.15  1.5  15  3  10  30  300  6.5  65  0.15  1.5  15  12  10  30  300  25  250  0.15  1.5  15  For practical purposes, the jitter tolerance template specifies the minimum jitter that a network element must be able to sustain without producing any bit errors. Jitter tolerance  2.  Jitter  14  applies specifically to clock and data recovery units. A n interesting feature of this jitter tolerance specification is that it requires C R U s to be able to recover clock and data satisfactorily from a modulated bit stream which has been modulated using a sequence of sinusoids of single frequency and constant amplitude. The range of frequency-amplitude pairs over which the procedure must be repeated is given by the template shown i n F i g . 2.5.2. The jitter amplitudes and frequencies are specified i n Table 2.5.1. In reality, a jittered data stream is seldom modulated by an individual sinusoid. Almost always, i n real systems, the jitter present on a data stream is random i n nature with a broadband jitter spectrum [Bla95]. The requirement of sinusoidal modulation has both advantages and disadvantages. O n one hand, it makes the testing procedure deterministic and repeatable. O n the other hand, it requires long test times as the test must be repeated a number of times for various amplitude-frequency pairs specified i n the template. Theoretically, the number of points is infinite. However, for practical purposes a reasonable spacing between the frequency points is chosen by the test engineer depending on the time, accuracy, and cost requirements. A reasonable number of points can be between 10 to 20. Since jitter tolerance specifications require that the jitter for the test purposes be sinusoidal, next, we investigate the jitter parameters i n terms of conventional angle-modulation parameters.  Jitter as a Case of Angle Modulation  Phase modulation ( P M ) is a form of angle modu-  lation i n which the angle of the carrier is varied linearly with the modulating signal [Hyk92]. Let  x (t), given by c  x (t) = c  cos(uj t), c  (2.1)  2. Jitter  15  denote an unmodulated carrier whose angular frequency is u . The zero crossing instances c  of this signal are assumed to be the time instances corresponding to the clock signal edges under test. Let x (t), given by m  x (t) m  = A cos(2'Kf t), m  (2.2)  m  be the modulating signal used to phase-modulate the carrier x (t). f c  A  m  m  is the frequency and  is the amplitude of the modulating signal. Then, the P M wave is given by  x (t) pm  = cos{u> t + k x (t)}, c  p  (2.3)  m  where k is the phase sensitivity of the modulator. If the angle of the unmodulated carrier is p  considered to be the reference, the angle of the modulated signal, 0 (t), varies proportionally o  with the amplitude of the modulating signal, i.e., 6 (t) = k x (t). 0  p  m  The phase deviation  resulting from the modulation is the jitter. A phase-modulated signal is shown i n F i g . 2.5.3. Due to the modulation, there is a difference i n the time instants at which the edges of the unmodulated and modulated signals happen. The case shown here is the case of sinusoidal jitter.  2.  16  Jitter  Figure 2.5.3 Phase Modulation.  Jitter can also be considered a case of frequency modulation ( F M ) , as frequency and phase modulation are closely related. A frequency modulated wave corresponding to the phase modulated wave i n Eq.2.3 is given by  Xf (t) = cos{u> (t) + kfsin(2irf t)} m  c  m  where kf is frequency modulation index given by k/= Af/f . m  deviation due to F M and f  m  (2.4)  A / i s the maximum frequency  is the modulating signal frequency. F i g . 2.5.4 [Hyk92] depicts  the relationship between P M and F M . P M and F M blocks shown i n the figure denote a phase modulator and a frequency modulator, respectively.  2.  Jitter  17  Modulating Signal  ^.  FM wave  PM  Integrator  Carrier  Modulating. Signal  Differentiator  FM  •  PM wavfi  fc  Carrier  Figure 2.5.4  Relation between P M and F M .  In the physical sense, kf represents the phase deviation of the wave i n Eq.2.4. If the maximum values of the deviations i n angle for F M and P M are considered, then, \{k  p  x cos(u; i)}| m  7  |{A///  x sin(w t)}|,  m  m  (2.5)  U I (unit interval) is a standard way of jitter representation i n terms of the part of the total bit interval. If J  p p  is the peak to peak jitter i n U I , then, its angle equivalent is equal to J  p p  x,27T. However, due to the cosine function i n the angle argument of the angle modulated wave, we replace A / / / by J m  p p  x 7r and not by J  p p  x 2ir, as the excursions of a sinusoid are  from - 1 to + 1. Hence, the jitter i n U I is related to the modulation index as given by  Jpp X 7T = A / / / . m  Eq.  (2.6)  2.6 is the relation between the frequency modulation parameters and the jitter. This  equation is used to translate input jitter tolerance template specifications to frequency deviations. However, the above relations hold for low values of angle modulation indices (<0.8) as the higher modulation indices result i n wideband angle modulation [Hyk92].  2.  Jitter  18  A numeric example provides better insight into the specifications. Consider one of the points on the template, say, 0.15 U I maximum jitter at 250 k H z for an O C - 1 2 (622.08 M H z ) network element. These two numbers provide a complete specification of jitter at the given frequency. 0.15 U I maximum jitter at 250 k H z means that the edges of the jittered signal are shifting away from their corresponding edges of the non-jittered signal at a rate of 250 k H z . Since the modulating signal is assumed sinusoidal, the jitter reaches a maximum at -K/2. A t this point the corresponding edges are apart by 0.15 U I . In the time domain this means that the edges are apart by 241 ps (0.15 x 1.6075 ns), as the time period of a 622 M H z clock is 1.6075 ns. In the frequency domain, this implies that the instantaneous frequency at this point is (622.08+0.1178) M H z (using E q . 2.6). Clearly, the control and measurement of time i n the order of picoseconds is difficult and cumbersome especially at high frequencies. There are other jitter specifications that are not relevant to the clock and data recovery units.  Since, they do not relate to C R U s , they are not discussed i n detail i n this thesis.  However, a brief overview is provided i n Appendix F for the sake of completeness.  Chapter 3 A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  This chapter deals with the jitter tolerance test of the C R U s found i n data transceiver ICs. A S O N E T clock and data recovery unit is adopted as an example. First, an overview of a typical S O N E T node is presented. Following this, the theory of jitter tolerance of a generic P L L is presented. This is followed by a discussion of present-day industry standard methods of performing jitter tolerance tests. A novel B I S T scheme is presented along with simulation and experimental results. Finally, some possible variations of the presented B I S T scheme are discussed.  3.1 A SONET Node The requirement of higher bit rates than the existing integrated services digital network (ISDN) [Onv94], for supporting applications such as interactive multimedia and interconnection of local area networks, has led to the introduction of broadband I S D N (B-ISDN). Asynchronous Transfer Mode ( A T M ) is a transport mode of choice for future B - I S D N . A transfer mode defines how information supplied by network users is eventually mapped onto the physical network [Onv94]. S O N E T has been chosen as the preferred physical medium for A T M networks [Bla95]. 19  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 20  S O N E T is an interface that provides a physical envelope through a framing structure to transport A T M cells. F i g . 3.1.1 shows a typical S O N E T network element. The clock and data recovery unit ( C R U ) i n the receiver section of this S O N E T node recovers the clock signal from the received serial data. The data is recovered with the help of the recovered clock. The recovered data is stored on the I C i n the form of bytes. Hence, a serial-to-parallel conversion is performed using the serial-to-parallel block. The parallel data is processed for section, line, and path overhead by the O H P (overhead processor) block. Error checking and delineation is also performed on the cells by this block. The legitimate cells are then written to a first-in first-out (FIFO) buffer. The switching section processes the frames and routes the data. The clock synthesis unit ( C S U ) i n the transmitter section synthesizes a line rate clock using a local reference. Prior to the transmission, the parallel data stored i n the F I F O is appended with line and section overhead by the O H P . Then, the parallel data is converted into a serial bit stream by the parallel-to-serial converter.  The S O N E T / S D H frames are  finally transmitted v i a a serial data stream at the line rate.  Receiver section  Rxdata  CRU  Serial-toParallel  OHP  FIFO  SWITCH Tx data  CSU  ParalleltoSerial  OHP  FIFO  Transmitter section  Figure 3.1.1  A typical S O N E T node.  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 21  The present day level of system integration has made it possible to integrate C R U , C S U , serial-to-parallel, parallel-to-serial, O H P , and FIFOs blocks on a single I C . A n example of such an I C is P M 5 3 4 6 [Sun95]. The receiver section of such an I C typically constitutes a clock and data recovery unit ( C R U ) based on a P L L . The transmitter section also contains a PLL-based clock synthesizer.  3.2 Theory of Jitter Tolerance A P L L is a feedback control loop whose frequency is locked onto some frequency component of an input signal. The basic architecture of a P L L is illustrated i n F i g . 3.2.2. A phase detector (PD) is used to compare the phase difference between the input signal and the signal generated by a voltage controlled oscillator ( V C O ) . The phase-difference signal at the output of the phase detector is filtered by a low-pass filter to generate the control voltage for the V C O . Thus, through negative feedback, the phase and the frequency of the V C O are "locked" to the phase and frequency of the input signal. Example references on P L L s are [Wol91], [Ega81] and [Gar79].  r Reference input  Figure 3.2.2  Block diagram of a P L L .  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 22  To study the jitter tolerance of a PLL, a linear ac model of the PLL is used. The linear ac model shown in Fig. 3.2.3 [Wol91] represents a generic phase-locked loop comprising of an active loop filter. The ac model of the PLL is used, as opposed to the complete linear model with dc parameters, since the jitter tolerance is directly related to the dynamic behavior (frequency response) of a PLL. G(s)  k  F(s)  1/s  0  Figure 3.2.3 Linear ac model of a PLL [Wol91]  In Fig. 3.2.3, F(s) is the frequency response of the loop filter, kd is the gain factor of the phase detector, and k is the VCO gain. Let @i(s) be the phase of the input signal, 0  ® (s) 0  be the phase of the signal generated by the VCO, and Q (s) be the error signal or e  the phase difference between the input signal and the VCO output. The forward gain of the PLL, G(s), is then given by e {s)  k k F( )  0  d  0  s  (3.1)  From the ac model shown in Fig. 3.2.3, Q (s) = @i(s) - 0 (s), e  o  (3.2)  and ® (s) 0  = 0 (s) e  x G(s)  (3.3)  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 23  Hence, on replacing Q (s) i n E q . 3.2 with its value from E q . 3.3 , we obtain 0  e (s) = Qi(s) - Q (s)G(s) e  (3.4)  e  or, Qi(s) The term  (3.5)  1 + G(s)  is known as the phase error response H (s) [Wol91]. In a general sense, the e  jitter tolerance of a P L L is its ability to maintain lock. A n implication of this statement is that the phase error remains within the linear (useful) range of the phase detector. Hence, the jitter tolerance response, J(s), of a P L L is the inverse of the phase error response H (s), i.e., e  <*> = HZ)  '  J  (3 6)  Next, we investigate the various response functions discussed i n this section i.e., H ( s ) , e  J(s), F(s), and G(s), for an example P L L . The P L L under consideration is based on an active loop filter and a multiplier type P D . The details of the P L L are as follows.  Loop Filter :  The loop filter is shown i n Fig. 3.2.4. The filter is an active R C filter with  poles at 0 and uj, and a zero at w%. The filter uses passive elements used for a P L L i n [Sun95]. The transfer function of the filter is given by  F(s)  =  h-j^n S(s/U>  3  where, kh = jft, u>2 = •  R i = 53.2 k  n  +  (3J)  1)  and u>3 = ^ ^ r . The passive components used for the filter are  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 24  •  R = 200  n  •  C = 0.47  fiF  •  C = 13.5 pF  2  3  Hence, the frequencies of interest are  = 2TT  x 1.693 kHz  •  u  •  u> = 2TT x 886.41 kHz  •  k = 0.003759  2  3  h  R2  From PD  R1/2  C  R1/2  O-  To VCO O C3  Figure 3.2.4 Loop Filter.  The frequency response of thefilterplotted using MATLAB [Mat94] is shown in Fig. 3.2.5.  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 25  F(s)  I  frequency(Hz)—>  |  Figure 3.2.5 Frequency response of the loop filter.  Phase Detector : The phase detector used for the PLL is a multiplier-type phase detector [Wol91]. The block diagram of the phase detector is shown in Fig. 3.2.6. The phase detector comprises a four-quadrant multiplier and a limiter. Such a phase detector features a triangular characteristics as shown in Fig. 3.2.7. For a multiplier-type phase detector, the  Vi  Ve  Figure 3.2.6 Multiplier type phase detector  gain is given by [Wol91]  (3.8)  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  26  In our case, Vdm is chosen to be 2.5 V. Hence, kd = 0.398 V/rad. Vd  Vdm  n/2  Figure 3.2.7  Voltage Controlled Oscillator :  it  9e  Phase detector characteristics.  The VCO model chosen for the PLL is assumed to be  linear with the gain k = 100 MHz/V. 0  From the ac model of the PLL, the closed loop transfer function H(s) is given by  H(s)  =  &o(s)  G(s)  i+  e (s) l  (3.9)  G{ y s  For the PLL under consideration, the open loop transfer function, or, the forward loop gain is  G(s) = k  S (S/LO 2  3  +  (3.10)  1)  where k is referred to as the PLL bandwidth [Wol91] and is given by k = khk kd. Hence, 0  the closed-loop transfer function is given by ks + ku>2 s /u>3 + s 3  2  + ks + ku>2  (3.11)  MATLAB plots of functions H(s) and G(s) are shown in Fig. 3.2.8 and 3.2.9 respectively.  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 27  Figure 3.2.8  Closed-loop response of the P L L .  G(s)  100 A I  lm  50  CD  3  §> - 5 0 co  E  -100 10  10'  10  10  n  frequency(Hz)—>  Figure 3.2.9  10  Open-loop response of the P L L .  The jitter tolerance function J(s) is given by  J(s) = l + k  S (S/UJ 2  3  +  1)'  J(s) for the PLL under consideration is plotted in Fig. 3.2.10.  (3.12)  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 28  J(s)  1001 A  .  1  i  •  r-  !  frequency(Hz)—> Figure 3.2.10 Jitter tolerance of the P L L .  The above plots are used to observe the correlation between the PLL parameters and the theoretical jitter tolerance of the PLL. The jitter tolerance is the inverse of the phase error response and is essentially a function of the PLL's open-loop and closed-loop response. This provides a design guideline for a PLL with required jitter tolerance. The calculated jitter tolerance (theoretical) of the PLL, obtained in this section, is used as a comparative measure for the simulations in section 3.4.1.  3.3 Conventional Jitter Tolerance Test Schemes A conventional method of performing a jitter tolerance test is to use dedicated expensive test equipment that can impose a given jitter on a data stream generated by a data generator. The jittered stream produced by the jitter generator is supplied to the DUT. The bits recovered by the DUT from the jittered data stream are fed to a bit-error rate tester (BERT). The nonjittered data stream is also fed to the BERT. The BERT generates an output indicating the bit error rate of the DUT. The magnitude of jitter at which the bit-error rate (BER) exceeds the  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 29  pre-defined bound specified in the jitter tolerance specifications determines the jitter tolerance of the DUT. An example of an instrument capable of being used for a jitter tolerance test is the industry-standard Microwave Logic SONET/SDH SJ-300 Jitter and Wander Analyzer [Mic95]. A non-SONET-specific example of a jitter tolerance test equipment can be found in [Bla95]. The methodology is based on the generation of jittered data using a jitter source created using precision delay lines. The recovered clock is analyzed by plotting its eyediagram on an oscilloscope. The jitter tolerance methodology is aimed at jitter tolerance tests of fibre channel equipment and does not specify the spectral content of the clock generated by the jitter source. Since SONET jitter tolerance tests must be carried out in the presence of sinusoidal jitter, the above method is not suitable for SONET tests. Another example of a jitter clock source based on direct digital synthesis waveform theory has been proposed in [LaM89]. The presented jitter clock source is capable of generating a clock signal with a wide range of jitter amplitudes and frequencies. However, the method requires a very high frequency clock signal for the synthesis of a programmable low frequency signal. This is due to the fact that the method is based on discrete time approximation. For SONET frequencies (MHz range), the method will require a base frequency in the range of GHz for generating a clock with required jitter characteristics. Since such a high frequency clock signal (GHz) is not available in normal circumstances, this method is also not appropriate for jitter tolerance test at SONET frequencies in the range of MHz or higher. The above methods of performing jitter tolerance tests are either unsuitable for SONET frequencies (hundreds of MHz or higher), or are only applicable for either characterization  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  3 0  tests or volume production-stage tests of expensive parts that can tolerate long test times, using dedicated expensive test equipment that can generate data streams with controlled amounts of jitter. Hence, the major drawbacks of the aforementioned jitter tolerance test methodologies are : (a) high cost - the requirement for expensive test equipment that must have the same or superior speed and accuracy specifications as the CRU under test. (b) long test times - normally, the setup and operational time of dedicated equipment is very long and results in overall long test times. The setup time is a applicable once, while the operational delays are recurrent. (c) frequency limitations - most apparatus of applying jitter to the clock are limited to 1 to 5 MHz jitter frequency and cannot source enough jitter to make the parts fail the test. With the rapidly increasing speeds of clock rates resulting from the advances in the IC technology, these drawbacks become increasingly significant, especially for performing volume-production stage testing of CRU jitter tolerance.  3.4 The BIST Scheme  Recognizing the demerits of conventional jitter tolerance test methodologies and the need for more efficient techniques, this section presents a BIST scheme for the jitter tolerance test of the CRUs found on high speed data transceivers that belong to the class of ICs described in the beginning of this chapter. In particular, the availability of a PLL-based clock synthesizer is assumed which is normal for the types of ICs considered.  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  Fig.  3.4.11 shows a block diagram that illustrates the concept underlying the novel  C R U test method. C R U is the block under test. The data generator, C l o c k Synthesis Unit (CSU), bit-error rate tester, signal generator, and the coupling capacitor together constitute the circuitry required for realizing the C R U tests. The following describes the functionality of these blocks and how it is used towards the realization of the novel test method. It is desirable to have all the blocks integrated on the same I C , and thereby provide for a complete and true B I S T scheme. However, the C R U frequency and jitter tolerance tests can still be realized i f any one or more of the blocks i n F i g . 3.4.11 reside externally (off-chip) to the C R U under test. Frequency Modulation  (Jittered) Clock Clock Synthesis Unit (CSU)  Data Generator  (Jittered) Data  Clock Recovery Unit (CRU)  BER TESTER  Figure 3.4.11 Jitter tolerance BIST scheme.  The requirement for a C R U jitter tolerance test is to verify that the C R U can correctly recover the data from an arbitrary (pseudorandom) data stream that is itself generated from  31  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 32  a specifically jittered clock. The test method here performs just that through the following steps: (1) a jittered clock is generated, (2) the jittered clock is used to generate a test data stream, (3) the test data stream is fed to the C R U under test, (4) the bit error rate tester determines the number of bit errors that arise i n the C R U ' s recovered data stream, thereby establishing the C R U ' s jitter tolerance or lack of. The following describes the steps of the B I S T scheme i n detail. STEP I : Frequency modulation is performed to impose a jitter of known characteristics (amplitude and frequency) on the clock signal generated by the C S U . In the normal mode of operation, the C S U on typical data transceiver ICs is used to synthesize a line rate clock from a local reference. F i g . 3.4.12 shows the structure of a typical phase-locked loop (PLL)-based C S U and the arrangement for performing such frequency modulation. CSU PLL  To Data Generator  Figure 3.4.12 Generation of jittered clock.  Let kf be the gain of the voltage controlled oscillator ( V C O ) i n the C S U P L L and A„  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 33  be the amplitude of the modulating signal. The deviation i n output frequency of the V C O is given by  Af = k xA . f  (3.13)  m  Then, the amplitude of the modulating signal required to impose a jitter of value J  p p  on the  clock is obtained using Eqs. 3.13 and 2.6, and is given by J =  f  PP  7T X  Thus, a sinusoid with a frequency of f  m  U I at frequency f  m  ,  •  f  (3.14)  m  and amplitude A  m  w i l l impose a desired jitter of J  p p  on a carrier given by E q . 2.1.  Since the C S U used i n this test method has a normal mode of operation and purpose other than testing the C R U , it is crucial that the test circuitry added to it for the C R U test purposes not have any significant negative performance impact on the C S U ' s normal mode of operation. A s the normal mode of operation of the C S U results i n the V C O input to be (when in-lock) a dc or very low-frequency signal, it is generally acceptable to add capacitance to this node without incurring any significant negative performance impact. Therefore, as the normal V C O input is a dc signal, an effective way of generating a frequency modulated signal at the C S U output is to provide a modulating signal of specific amplitude and frequency to the V C O - i n p u t (node A ) . In turn, a simple way of superimposing a relatively high frequency ( M H z range) ac-signal (modulating signal) onto a dc signal is through ac-coupling, i.e., coupling the modulating signal source to the V C O - control input through a capacitor. Often the output of the loop filter is a low impedance node and the input of the V C O is a high impedance node. If a signal is ac-coupled into such a node, the relative impedances  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 34  and their impact on the effective control voltage to the V C O must be taken into account. Fig. 3.4.13 depicts the approximate scenario at the control input node of the V C O . Zo Veff  Zi  Vo  +  + Vm  VCO input  LPF output  Modulating signal  Figure 3.4.13 A C coupling.  Z i is the high input impedance of the V C O ( M  range), Z  Q  is the output impedance  of the L P F and V represents the voltage at the output of the L P F . V 0  m  and C represent the  modulating source and the coupling capacitor, respectively. The impedance of the capacitor is given by Z = 1/sC. Then, the effective voltage, V ff, at the control input of the V C O e  is given by  Vo If IZil » I Z I and IZil » 0  +  (3.15)  IZI, then V f f is given by e  Vo  V  e  e f f  w  (Z /Z 0  + 1)  Vrr, +  (Z/Zo  + 1)  (3.16)  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  In order to make V compared to R o .  m  the determining factor for  V ff, e  the ac impedance Z must be small  If I Z I « IZ I, then from E q . 3.15, 0  V  e  f  f  »  (3.17)  V m .  In some cases, the condition I Z I « I Z I may imply a large capacitor which may be unaccept0  able. However, i f the P L L is designed such that V  0  is approximately equal to 0 V i n the  'locked' condition, a smaller capacitor can be used. In that case, V f f is given by e  (3.18) The amplitude of the modulating signal should be determined taking E q . 3.18 into account. If the capacitor scenario is found unsuitable for a particular application, the capacitor can be replaced by an adder (eg., op-amp based adder) or a simple resistor. When an adder is used instead of a capacitor to add the modulating signal to the V C O input, it provides better control over the modulation as the magnitude of the coupled signal is not dependent on the frequency of the modulating signal. However, the price to be paid is the added cost of the adder. If a resistor is used instead of the capacitor it w i l l also make the magnitude of the coupled signal independent of the frequency of the modulating signal. The sinusoidal modulating signal is provided by a sinusoidal signal generator.  This  sinusoidal signal generator can be realized on the same I C as the C R U under test. Examples of such integrable signal generators can be found i n [Ton93][Lu94]. Some jitter specifications may require that the source generate a sinusoid of precise amplitude and frequency.  The  precise amplitude requirement may not allow an on-chip signal source i n most current cases  35  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 36  due to the relatively large area that would be required to realize such a source. A s such sources are not necessarily found on the types of ICs such as transceiver ICs where C R U s are found, the required area for integrating the signal source may not be easily justified. In that case, one would resort to an external signal source. Though the external signal source scenario does not comply with the requirements of a true B I S T scheme, it provides an economical solution as compared to the one provided by mixed-signal A T E s . Another advantage of the external signal source is that, i n general, it is more precise than the on-chip generator. For  example, to impose 0.15 U I jitter on a 622.08 M H z clock signal, frequency  modulation is performed with a sinusoid of 250 k H z frequency.  The amplitude of the  sinusoid is determined by the maximum value of angle deviation. The corresponding value of maximum angle deviation is 0.15 x ir = 0.4712 rad. This corresponds to Af/f . Hence, m  the value of A / i s 117.8 k H z . Assume that the gain of the V C O is 100 M H z / V . The required amplitude of the sinusoid is then obtained from E q . 2.6. In this case, the amplitude w i l l be 1.178 m V . The amplitude of the sinusoid can be directly obtained from E q . 3.14 also. Hence, a sinusoid with a frequency of 250 k H z and amplitude 1.178 m V w i l l impose a desired jitter of 250 k H z and 0.15 U I on a 622.08 M H z clock signal. In such cases, due to the noise factors, the amplitude i n the order of m V may require an external generator. STEP H : The realization of Step (II) of the B I S T , requires that the jittered clock signal from the C S U be fed to the data stream generator block that i n turn generates the data stream against which the C R U is tested for clock recovery and tolerance to jitter. Such a data generator is usually chosen to be a digital pseudo-random data generator realized as a digital finite state machine with feedback.  A well-known example of a pseudo-random  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  37  data generator is a Linear Feedback Shift Register ( L F S R ) [Bar87]. However, this does not preclude the clock being fed to other data sources, such as digital logic producing specific protocol data formats, like S O N E T frames.  S O N E T interface ICs like P M 5346 [Sun95]  normally include such digital circuitry to produce protocol specific data. Thus, supplying the jittered clock obtained through Step (I) to the data generator results i n a data stream that has same jitter characteristics as the clock. STEP HI : The data stream with imposed jitter, obtained through Step (II) is then fed as a test input stream to the C R U . The C R U recovers the clock and data from the input data stream typically using a P L L . STEP TV : The recovered data from C R U is fed to a bit-error rate detection circuit (e.g., B E R T ) . The error detector circuit checks the recovered data stream for B E R . The output of this block is an indication of the number of bits i n error. Several realizations of such error detectors can be found i n practice [Pal95]. In our case (IC PM5346), the transmitter section of the IC contains resources to generate pseudo-random data i n one of its normal modes of operation. A l s o , the receiver section is capable of processing the data for bit errors. Hence, a test-dedicated data generator and a bit error detector were not needed, rendering the implementation more economical. The output of the error detector circuit is used to generate a pass/fail signal for the C R U block. The total area overhead of the B I S T scheme is minimal. The scheme requires essentially four blocks, i.e., a C S U , a data generator, a B E R T , and a modulating signal generator. In addition to this, a coupling capacitor is also required. A s mentioned earlier, the C S U is normally present on the I C . A s for the data generator and B E R T , these simple circuits can  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 38  easily be implemented using known techniques [Bar87, Pal95], and thus do not constitute overhead per se. Regarding the signal generator, i f the integration of the latter is judged excessive, the scheme can still be implemented using a readily available external generator. O n the basis of the block diagram level description of the scheme, the control required for implementing the B I S T scheme is likely to be simple and is not likely to incur any significant overhead.  Another major advantage of the B I S T scheme is high speed of operation as  compared to the conventional test methods. The exact cost of the B I S T is highly dependent on the implementation. Since the implementation of the B I S T is not done on a transistor level, the exact overhead of the scheme is not known. However, based on the other similar implementations found i n literature, such as the B I S T scheme presented i n [Ton93], it can be stated that the area overhead and hence the overall cost is not likely to be excessive.  A potential drawback i n the presented scheme is that it relies on the knowledge of the V C O gain for control over the jitter amplitude being supplied to the D U T . Typically, when an I C is designed and fabricated, a thorough characterization is performed on the sample parts. Through characterization, various parameters and their variations are determined. For the B I S T scheme, the V C O gain needs to be determined.  Because of process variations  and other factors such as temperature and transistor size mismatching, the V C O gain may vary from its nominal value.  Hence, a careful characterization of V C O gain margins is  required prior to the production stage deployment of the methodology. Precise knowledge of other parameters affecting the modulation such as the impedances associated with the control input node of the V C O is not as critical as the V C O gain as long as the conditions on the size of the coupling capacitor, as described earlier, are satisfied. The test guard bands  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 39  must be determined using the variation limits determined through characterization. If the parametric variation of the V C O gain is found to be excessive, the B I S T scheme cannot be used effectively for production stage testing. However, an excessive variation itself would call for the modification of the basic design.  3.4.1 Simulation The presented scheme was simulated i n "Cadence Analog-Artist" environment [Ana94]. The block diagram shown i n F i g . 3.4.11 was implemented using both digital and analog components. The simulations were performed using a mixed-mode simulator 'SpectreVerilog' [Spr94] [Ver90]. The C S U and C R U were implemented using macromodels of P L L s . Two models of the P L L s were made using building blocks from the 'Functional' library for the C R U and the C S U separately.  These building blocks have been realized using controlled  sources. The schematic for the overall B I S T scheme is shown i n Fig. B . 6 (Appendix B ) . The P L L macromodel used for the C S U is shown i n Fig. B . 4 . The P L L uses a passive loop filter and a multiplier type phase detector. The V C O from the library was used along with a comparator to obtain a square-wave V C O . The phase detector was realized using an analog multiplier and a comparator. A n attempt was made to imitate the scenario that would be seen i n an actual circuit, with respect to the impedances. F o r example, the control input net of the V C O , which is a critical node from the point of view of the B I S T scheme, was carefully modeled by putting an extra op-amp based unity gain buffer to simulate a high input impedance. Similarly, the output impedance of the L P F was modeled by the output of another op-amp based unity gain buffer.  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 40  The following is a list of parameters defined for the various components of the C S U P L L . The parameters chosen here are of the order used for S O N E T O C - 3 C M O S ICs such as the IC P M 5346.  •  V C O gain = 100 M H z / V ;  •  Phase detector gain = 5/TT V/rad;  •  Loop filter  a.  kh = 0.34;  b.  Cut-off frequency = 120 k H z .  The P L L macromodel for the C R U is shown i n F i g . B . 3 (Appendix B ) . The loop filter used for this P L L is an active filter implemented using an op-amp macro from the library and the passive components. The V C O used for this filter is exactly the same as the V C O for the C S U P L L . The basic phase detector used for this P L L is also the same as the P D of the C S U . However, a module to convert non-return to zero ( N R Z ) data generated by the data generator into a return to zero (RZ) type format [Wol91] is added before the P D to simplify the design and performance of the basic P L L . The functionality of the N R Z to R Z type convenor is depicted i n Fig. 3.4.14. B y virtue of this conversion, a frequency component is created i n the R Z - l i k e data which helps i n clock recovery. The module consists of a delay element and an X O R gate. The delay element shown i n the schematic i n F i g . B . 6 is written i n the 'Verilog' hardware description language ( H D L ) [Ver90]. The code for this module is given i n Appendix D .  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 41  RZ-like signal N R Z data  A 4_  Tb  B 4_  C4  Time —> Figure 3.4.14 Conversion of N R Z data to RZ-like data.  The two P L L s ( C S U and C R U ) were designed for generating clocks with -2.5 and 2.5 V as low and high amplitudes respectively. This simplifies the design without any impact on performance or functionality. In this particular case, the time instants of the clock and data signals are of importance as opposed to the amplitude levels of the signals. Hence, no performance impact occurs due to the chosen amplitudes.  Moreover, since the clock  generated by the C S U has a swing of -2.5 to 2.5 V , those levels are shifted 'up' using a level shifter from the library before feeding it to the data generator which accepts signals between the 0 and 5 V rails. A delay of one quarter of the time period of the C S U clock (i.e. T /2) D  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 42  is supplied to the recovered clock to compensate for the inherent phase characteristics of the multiplier type phase detector. The data generator description was also written i n Verilog. A n arbitrary data sequence was chosen for the data from the generator. The simulations were divided into two parts. In Part I of the simulations the functionality of the B I S T scheme was simulated. In Part II of the simulations, the behavior of the example P L L was investigated in the presence of various modulating signals. Part I : The B I S T scheme was simulated for Part I of the simulations. The schematic used for the simulations is shown i n Fig. B . 6 . The aim of the simulations was to determine the jitter tolerance of the P L L described i n Section 3.2. The jitter tolerance of the C R U P L L was determined by gradually increasing the jitter (by increasing the amplitude of the modulating signal) until any bit error was observed. The occurrence of bit errors was checked by observing the phase relation between the input data and the output clock. Detailed results are shown i n Appendix C . The simulation results are summarized i n Table 3.4.1. Table 3.4.1  V (V) m  Veff (mV)  The  Simulation and theoretical results.  fm  Jpp (simulation)  Jpp (theoretical)  (UI)  (UI)  32.706  4.115  10 k H z  13.100  14.1894  2.252  2.83  100 k H z  0.901  0.9246  2.466  31.00  1MHz  0.987  1  2.477  62.27  2MHz  0.991  1  2.482  155.98  5MHz  0.993  1  simulation results are obtained using E q 3.14 at the amplitudes of the modulating signal at which bit errors are observed. The theoretical results are obtained using the M A T L A B  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 43  code given i n Appendix E . The theoretical and simulated jitter tolerance curves are shown in F i g . 3.4.15.  10  1  10  10  2  3  Frequency (kHz)  10  4  >  Figure 3.4.15 Simulated and theoretical jitter tolerance.  Part n : In part II of the simulations, only the stimulus part of the scheme was simulated with the aim of investigating the capability of a P L L to provide a jittered clock i n the presence of different modulating signals like a triangular wave, a square wave and a step input signal. Different signals were ac-coupled into the V C O input node of the C S U P L L and the outputs of V C O and loop filter were observed. 1.  Sine wave input - When sine waves are coupled into the V C O input,  frequency  modulation takes place. The output frequency is directly proportional to the amplitude  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 44  of the coupled signal as given by E q . 3.13 (Fig. C.6). 2.  Triangular input - W h e n a triangular signal is supplied to the V C O through the coupling capacitor, the waveform at the filter output is as shown i n F i g . C . 7 . The P L L lock behavior depends on the slope and amplitude of the ramp signal.  3.  Square-wave input - A square wave applied to the coupling capacitor throws the P L L out of the lock. This simulates a random jitter scenario. (Fig. C.8).  4.  Step input - The basic coupling scheme is altered to supply the step input to the P L L . A n adder is required to add the L P F output and coupled signal. The output of the adder is connected to the V C O input. The P L L response is as expected.  The P L L is first  thrown out of lock and then the lock is achieved at a different frequency. This frequency corresponds to the new amplitude of input to the V C O . The waveforms are shown i n Fig. C.9.  3.4.2 Hardware Verification It was not feasible to design a circuit on the transistor level and get it fabricated for the verification of the concept underlying the B I S T scheme. Nevertheless, we verified the concept by using an existing I C P M 5346 [Sun95] provided by P M C - S i e r r a , Inc. The hardware verification was done on a S/UNI-Lite Optical Reference Design ( S O R D ) board [Sor95]. Since, the I C P M 5346 is not designed with the intent of the implementation of the particular B I S T scheme, only the most critical aspect of the scheme, i.e., the generation of the jittered clock could be verified. The underlying assumption is that the digital components required for the B I S T scheme can be easily implemented using well-known digital design techniques. The I C P M 5346 has an architecture very similar to the S O N E T node shown i n  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 45  Fig. 3.1.1, with the exception of the switch. The IC does not include a switching section. This did not affect the experiment as the switch is not used for the B I S T scheme. Moreover, only the jittered clock generation part of the scheme was verified which does not require the use of other digital circuitry present on the I C . The C S U on the I C is designed such that the C S U - P L L cannot be put i n a free running mode with the V C O input being accessible. This means that the C S U - P L L could not be used for the modulation. Due to this restriction, it was decided to use the C R U - P L L for performing the jitter modulation. In the mode of operation of the I C that was used for the experiment, the C R U - P L L is locked to an external 19.44 M H z reference clock signal generated by a crystal source. The P L L generates a 155.52 M H z clock using the reference clock signal. However, the synthesized 155.52 M H z clock signal is not available at an external pin for analysis. Instead, a 'divide-by-8' of the synthesized clock is available at an external pin. A sinusoidal signal was ac-coupled into the VCO-control input node of C R U - P L L using a Marconi - 2022D signal generator and an external 0.47 fxF capacitor. The spectrum of the 'divide-by-8' clock was observed on a spectrum analyzer. The spectrum of a narrow band F M wave consists of a peak at the carrier frequency f . The two side bands are present c  at f  c  +/- fm- It was observed that the modulation sidebands and the carrier signal were  prominently distinguishable. The experimental value of jitter was obtained as follows. If V is the amplitude of the sideband and V is the amplitude of the carrier, it is known from n  the theory of angle modulation [Hyk92] that the relation between modulation index and the amplitudes is given by  V /V n  = Af/f . m  (3.19)  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 46  From E q . 2.6 we know that V r  = A/// . m  '  (3.20)  Hence,  Vn V  Jpp* = 7 7 -  (3-21)  Since, the readings on the spectrum analyzer were taken i n the form of a difference between the amplitudes of the carrier and the sideband ( A ) i n d B , A is given by A = 201og  1 0  ^  (3.22)  or,  V  n  y  A  = 10^0.  (3.23)  Replacing V / V i n E q . 3.23 with E q . 3.19, yields n  J  A  = 1050  p p i r  (3.24)  Since, the observed signal is the 'divide-by-8' of the original clock signal, E q . 3.24 must be modified as  =  (  3.  2 5 )  to obtain the jitter on the original clock signal [Ega81]. E q . 3.25 gives the experimental value of jitter i n the p-p form directly from the spectrum analyzer reading of A . For the verification of the jitter generation concept, the experimental readings obtained from E q . 3.25 are compared against the theoretical value obtained using E q . 3.14, i.e., f  x  7T  X  _ k  Jpp —  7—• f m  (3.26)  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  47  Tables 3.4.2, 3.4.3, and 3.4.4 summarize the modulation results at jitter frequencies 5, 2 and 1 M H z respectively. The difference i n the theoretical and experimental results can be attributed to the approximations involved i n the calculation. F o r example, it has been assumed that the impedance of the coupling capacitor is very small compared to the output impedance of the L P F , and hence, there is a negligible voltage drop across the capacitor. Since, the output impedance of the L P F is not known precisely, the assumptions leads to some error. The average error i n this case is 4.6 %. In a production stage deployment of the scheme, the test limits need to be determined using the results obtained i n this section.  Table 3.4.2  Jitter generation comparing predicted and measured values f o r /  Modulating Sine Wave  A (dB)  Amplitude (rms) (mV)  Experimental J  p p  m  = 5 MHz.  Theoretical J  (UI)  (UI)  10  -27.37  0.109  0.113  11  -26.39  0.122  0.123  12  -25.58  0.134  0.135  13  -25.25  0.139  0.146  14  -24.48  0.152  0.157  15  -23.98  0.161  0.169  16  -23.36  0.173  0.180  p p  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 48  Table 3.4.3  Jitter generation comparing predicted and measured values foif  m  Modulating Sine Wave  A (dB)  Amplitude (rms) (mV)  Experimental J  = 2 MHz.  Theoretical J  p p  (UI)  (UI)  1  -39.80  0.026  0.028  2  -33.96  0.051  0.056  -30.16  0.079  0.084  4  -27.29  0.110  0.113  5  -25.38  0.137  0.140  -24.48  0.152  0.169  -22.63  0.188  0.197  3  6  )  ,  7  Table 3.4.4  Jitter generation comparing predicted and measured values for f  Modulating Sine Wave  m  A (dB)  amplitude (rms) (mV)  Experimental J  p p  p p  = 1 MHz.  Theoritical J  (UI)  (UI)  1  -33.47  0.054  0.0562  2  -27.00  0.113  0.1125  3  -24.48  0.152  0.1688  p p  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 49  0.25,  0.2 h  0.05r  rjl 10  i 11  i  i  i  12 13 14 Amplitude of t h e coupled sine w a v e ( r m s - m V )  i  I  15  16  >  Figure 3.4.16 Experimental vs. theoretical results (5 M H z ) .  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 50  0.251  gl  1  1  1  1  1  1  1  1  1  r  i  i  i  I  I  i  i  i  i  1.2  1.4  1.6  1.8  2  2.2  2.4  2.6  2.8  Amplitude of the coupled sine wave (rms-mV) Figure 3.4.18 Experimental vs.  theoretical results (1  I  3  > MHz).  3.5 Variations of the BIST Scheme The proposed scheme can be varied to suit the implementation needs. Some possible variations of the scheme are described below. Another variation of the scheme i n the form of a frequency test is presented i n Appendix G .  3.5.1 A Reduced-Set Jitter Tolerance Test The basic B I S T scheme presented so far i n this chapter is designed to mimic the natural and straight-forward test flow that would be carried out with the external test equipment. The major difference between the testing using external test equipment and the B I S T scheme is not i n the basic procedure, but i n the location of test components and the speed of overall operation. Even with the presented B I S T scheme, one is required to test the D U T for the complete range of frequencies and jitter amplitudes specified i n the S O N E T template. This  3.  A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 51  may still be unacceptable due to long test times implied by the l o w jitter frequencies. F o r example, a single test at a frequency of 100 H z requires a minimum of 10 ms (1 period) plus the setup time of the test equipment. In this section, we develop an algorithm to decrease the number of test sets for a complete jitter tolerance test. First of all, we observe that a P L L is able to maintain lock i n the presence of sinusoidal modulation at its input as long as the maximum frequency deviation {Aui)  at  the input does not exceed the lock-in range of the P L L [Wol91], i.e.,  Aui  <u . L  (3.27)  For a multiplier type P D , the relation between the lock-in range and the bandwidth k is given by  COL =  (3.28)  Aui = jfc|.  (3.29)  Hence, E q . 3.27 can be rewritten as  E q . 3.29 implies that the P L L w i l l be able to track any frequency modulation producing a maximum frequency deviation less than or equal to kir/2. For jitter tolerance tests, jitter on the clock is essentially angle modulation. Hence, i f a test were performed at a certain jitter amplitude and frequency that produced a given frequency deviation A w , the particular test would cover all the jitter amplitude-frequency pairs which produce a deviation less than A w .  3.  A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 52  Next, we calculate the frequency deviations at various points i n the jitter tolerance template for S O N E T O C - 3 . The obtained values are shown i n Table 3.5.5.  Table 3.5.5 Calculation of the maximum frequency deviation.  Jitter amplitude (UI-pp)  Jitter frequency  A f (AU>/2TT)  15  10 H z  471 H z  15  30 H z  1413.7 H z  1.5  300 H z  1413.7 H z  1.5  6.5 k H z  30.63 k H z  0.15  65 k H z  30.63 k H z  0.15  1MHz  471 k H z  0.15  5MHz  2.356 M H z  It is observed that the jitter amplitude-frequency pair of 1.5 U I at 6.5 k H z produces a frequency deviation of 30.63 k H z . The jitter amplitude-frequency pair of 0.15 U I at 65 k H z also produces a frequency deviation of 30.63 k H z . A t frequencies lower than 65 k H z , all the amplitude-frequency pairs produce a maximum frequency deviation of less than or equal to 30.63 k H z . This suggests that the test at the amplitude-frequency pair of 65 k H z and 0.15 U I jitter w i l l cover all the frequencies lower than 65 k H z . It can be noted that the frequency amplitude pair at 5 M H z and 0.15 U I jitter produces the maximum frequency deviation among the values considered i n Table 3.5.5 but it is not chosen as the test point that can cover all frequencies lower than 5 M H z due to the reason explained below.  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit  Most practical P L L s designed for clock recovery applications at the clock speeds under consideration are narrow-band P L L s and do not have the bandwidth i n the order of M H z [Wol91]. This essentially means that they w i l l not track the modulation at frequencies i n the M H z range for the amplitudes specified i n the template. However, this does not cause any bit errors as the P L L is not required to track the modulation i n order to achieve zero bit errors as long as the jitter amplitude is less than 1 U I . In the case of jitter amplitude less than 1 U I , the bit error depends on the useful range of the phase-detector.  The concept is  better understood by observing the error response of the P L L , which is given by  | M  =  (.)  l-  =  ft  f f  (.).  r T  L - . j  J  (3.30)  The phase error function, H (s), is plotted for the P L L under consideration i n Fig. 3.5.19. e  It is observed that the magnitude of H (s) is approximately equal to 1 for all frequencies e  higher than the P L L bandwidth. This means that, for these frequencies,  | O | ~ |0,-|. c  (3.31)  A n interpretation of E q . 3.31 is that the P L L is not able to decrease the phase error by tracking the input phase and all of the input phase is appearing as the phase error at the output of phase detector.  There w i l l be no bit errors as long as the phase error does not  exceed the linear range of the phase detector. Hence, from a P L L ' s point of view, a given jitter amplitude at all frequencies greater than the P L L bandwidth displays the same behavior, i.e., the behavior of the P L L is given by E q . 3.31. This, i n turn, indicates that a test at any frequency much higher than the P L L bandwidth w i l l cover all the frequencies i n that  53  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 54  range. This is the most likely reason behind the fact that the jitter tolerance template does not specify the highest frequency at which the tests should be carried out.  I  S  1/(1 +G(s))  (  1001  •  1  •  1  •  1  •  1  i7r  Figure 3.5.19 Phase error response of the P L L .  Thus, by choosing two points on the template, one at jitter amplitudes greater than 1 U I and producing the highest frequency deviation i n that range, and another point at an arbitrary frequency higher than the P L L bandwidth, the complete template can be covered. In the particular case of O C - 3 , the highest frequency deviations for the jitter amplitude-frequency pair of 1.5 U I at 6.5 k H z and 0.15 U I at 65 k H z happen to produce the same maximum frequency deviation (30.63 k H z from Table 3.5.5). Hence, instead of choosing the first point in the amplitude range > 1 U I , the 65 k H z point can be chosen as the first point. This w i l l result i n a faster test as the time required for a test at 65 k H z is lesser than the time required for a 6.5 k H z test due to the longer time period of a 6.5 k H z signal. The preceding discussion holds for overdamped and critically damped P L L s [Wol91] [Gar79] and may hold for some P L L s with a low degree of underdamping.  If the P L L  is highly underdamped, the peaking behavior [Wol91] of the closed-loop system becomes prominent and causes the P L L to be less tolerant to jitter i n the vicinity of the peaking  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 55  frequency as compared to the jitter at neighboring frequencies. If a test is not performed in the vicinity of the peaking frequency, the results of the overall test may be misleading. Hence, the above methodology may not hold for some P L L s . A discussion on the damping behavior of P L L s can be found i n [Wol91], [Gar79] and [Bes84].  3.5.2 Lock-in Range Test A s mentioned i n the previous subsection, a P L L can maintain lock i n the presence of a sinusoidal F M i f the condition i n E q . 3.27 is satisfied [Wol91], i.e.,  Aui <u  L  (3.32)  where Au;,- is the input frequency deviation due to modulation, and U>L is the lock-in range of the P L L . Hence, i f the lock-in range of the P L L is known, the maximum frequency deviation that the P L L can sustain can be determined. The maximum frequency deviation can, i n turn, be used to calculate the jitter tolerance of the P L L for jitter amplitudes higher than 1 U l , as explained i n Section 3.5.1. A complete jitter tolerance test can be performed by performing a test that determines the lock-in range of the P L L (and the jitter tolerance for jitter > 1UI) and a second test same as the high frequency test explained i n the previous subsection. The lock-in range test can be easily performed by supplying the C R U with data at a higher rate than the nominal frequency and observing the bit-errors at its output. The highest frequency at which the P L L acquires lock without bit-errors is its lock-in range. The data at a higher frequency than the nominal frequency can be obtained by adding a dc signal to the V C O input of a C S U P L L . However, the capacitive coupling used for the B I S T scheme cannot be used for adding the dc signal to the V C O input as a capacitor blocks  3. A BIST Scheme For the Jitter Tolerance Test of a Clock and Data Recovery Unit 56  the dc signal. The dc signal can be added to the V C O by using an op-amp based adder. The cost of the adder can be justified by the fact that now only dc signals are required as opposed to the sinusoidal signal at l o w frequencies.  3.5.3 Conclusions The following summarizes the relative hardware requirements and the merits and demerits associated with the basic B I S T scheme and its variations. (a) The basic B I S T scheme : The basic B I S T scheme requires the longest test time and the largest area overhead among the presented schemes.  However, the basic scheme  meets the formal requirements of a jitter tolerance test ( S O N E T jitter tolerance test as specified by  [Syn94]).  (b) The reduced-set B I S T scheme : The reduced-set jitter tolerance scheme requires the same amount of hardware overhead as the basic scheme, but a significant reduction i n the overall test time is achieved. The scheme is not the formal jitter tolerance test. However, it can be used as a production stage jitter tolerance test and is a promising alternative to the basic B I S T scheme. (c) The lock-in range test : The lock-in range test requires the overhead of an adder and a variable dc voltage source. The area overhead for this test is slightly less than previous two schemes and this also is not the formal jitter tolerance test.  Chapter 4 A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  The majority of mixed-signal systems being integrated onto single ICs are digital signal processing (DSP) based systems [Meh93]. Examples of such mixed-signal DSP-core ICs are coder-decoders ( C O D E C s ) and single chip modulator-demodulators ( M O D E M s ) [Ter93]. With the increasing integration and emergence of new challenges for test engineers, the attention of researchers has been drawn towards the development of test methodologies for this class of circuits [Ton93] [Meh93] [Ter93]. Teroaka et al. [Ter93] presented a B I S T scheme for testing analog-to-digital convenors ( A D C s ) found i n a C O D E C I C consisting of a 24-bit floating point DSP-core, a 13-bit A D C , a 13-bit D A C (digital-to analog convenor), a 6K-word read only memory ( R O M ) and a 3.5K-word random access memory ( R A M ) . Toner et al. [Ton93] presented a B I S T scheme for the S N R test of a generic mixed-signal I C with a DSP-core. F i g . 4.1 shows a generic mixed-signal DSP-core I C . Typically, over 60% of the total IC area i n such ICs is occupied by digital circuits [Meh93]. The major analog and mixed-signal components on these ICs tend to be analog-to-digital and digital-to-analog convenors, P L L s , op-amps and filters. Sampling is an integral and important part of these systems. The sampling accuracy plays a major role i n the functionality of these ICs, and, is in turn, highly dependent on the accuracy of the sampling clock. 57  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  58  Issues such as frequency stability and accuracy of the clock signal determine the quality of measurements i n DSP-based systems [Meh93]. Hence, testing for clock accuracy is critical for such systems. This chapter presents a B I S T scheme for measuring the jitter of clock signals i n DSP-core mixed-signal ICs. First, a review of the prevalent methods of the analysis of jitter i n sampling-based systems is presented.  Following this, the concept  underlying the proposed B I S T scheme is established. Finally, the B I S T scheme is described, along with simulation and hardware experiment results.  Analog Output DAC  RAM DSP CORE  r  4 Analog Input ADC  ROM  I  !  Digital Interface  f Figure 4.1  PLL and timing  Digital Signals A DSP-based mixed-signal IC.  4.1 Jitter Characterization Most of the recent efforts towards the analytical characterization of jitter i n a samplingbased system are based on the time domain representation of jitter. These efforts can be  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  59  broadly classified into two categories: jitter represented as a case of (i) uniform, and (ii) non-uniform sampling. Jenq [Jenl88, Jen288 and Jen90] treats the analysis of jitter as a case of non-uniform sampling. Wagdy et al. [Wag90], and Souders et al. [Sou90] treat jitter as a case of uniform sampling. Wagdy et al. [Wag91] presented a comparison of jitter characterization using uniform and non-uniform sampling approaches.  Both of these  approaches are based on characterizing jitter by an arbitrary probability distribution function. In most cases, jitter has been assumed to be a random variable with a symmetrical distribution. Next, we present a brief review of these two methods of jitter analysis. A s the names suggest, the two methods of analysis of jitter primarily differ i n their representation of the sampling and the sampled signals. Non-uniform sampling is a more intuitive approach for representing jitter as a jittered clock essentially has non-uniform time periods. Jenq [Jenl88] presents a comprehensive analysis of jitter using the non-uniform sampling representation. H e presents a generic expression for the spectral representation of non-uniformally sampled signals. From the spectral representation, he derives expressions for the S N R of the sampled signal. If r signal with a frequency f  s  where t  is the jitter on the m  sampling edge of a sampling  th  m  or a nominal time period T, then r  m  A tm  mT — t.m  T  T  i n U l is given by  is the actual time instant corresponding to the significant edge of the m  (4.1)  th  m  time  interval [Jenl88 & Jen90]. F i g . 4.1.2 illustrates the representation for the case of random jitter.  4. A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  60  Ideal Signal "A"  Jittered Signal  2T  3T (m-l)T Time  mT  (m+l)T  (m+2)T  ^.  Figure 4.1.2 Illustration of jitter on the 10 sampling edge. th  For the treatment of jitter as a case of uniform sampling, the jittered clock is treated as though it were ideal and the jitter is added to the phase component of the sampled signal. If the sampled signal is a sinusoid, then the n  sample of the signal, v„, is given by  th  2irn  v = sin{  —  n  M  +  —  (4.2)  J  n  where J is the jitter on the n h sample and M is the number of samples per cycle [Wag91]. n  t  For the particular case of a sinusoid  [ e P  W  o  t  —  e  _  J  W  o  <  ) / 2  being the sampled signal, where  UJ  0  is the angular frequency of the sinusoid, it has been shown by Wagdy et al. [Wag91] that for a jitter / „ with zero mean and symmetrical distribution, the S N R is given by  SNR  N (N-2)a  2  (4.3)  where N is the number of samples i n the F F T and a is the standard deviation of the jitter.  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  61  It has been further shown by Wagdy et al. [Wag91] that for the same sinusoid, the nonuniform sampling representation as described earlier also results i n the S N R given by E q . 4.3. The two approaches discussed above, i.e., the uniform and the non-uniform sampling approach, have been used to calculate the S N R and the variation of the jitter from the calculated S N R . In the cases where peak-to-peak jitter measurement is desired, the above approaches cannot be used directly.  4.1.1 The Basis of the BIST Scheme Recognizing the drawbacks of the above mentioned approaches for the measurement of peak-to-peak jitter, we analyze the sampling clock jitter i n terms of the angle modulation. Let a sinusoid given by V f(t) re  = AefCOS  faf ft) re  (4.4)  where A f is the amplitude and f f is the frequency, be sampled using a jittered clock. Let re  K  the nominal frequency of the jittered clock be f  s  and the nominal time period be T. Let the  clock be jittered by a sinusoid such that the n * sampling time instant, n T , be given by nT  = nT + k cos (2TTfjiiT)  (4.5)  where fj is the jitter frequency and k is a constant. When the jittered clock represented by E q . 4.5 is used to sample the sinusoid i n E q . 4.4, the n * sample of the sinusoid is given by v  (nT  r e f  ) = A  ref  cos {2% frefnT  )  (4.6)  Replacing the value of nT from E q . 4.5 into E q . 4.6, we get vf re  (nT^j  = Af re  cos (27r f fnT re  + k2irf f re  cos (27T fjnT))  (4.7)  4. A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  If the constant  is represented by another constant  k.2-K.f f re  k',  62  then the Eq. 4.7 can be  rewritten as ref  v  (j*-T ^ = A f re  c o s (2Trf fnT re  + k cos  (27rfjnT)J  (4.8)  Now, let us consider another angle modulated sinusoid ref' CO = ref  V  A  c o s fa f ft Tt  + k COS 2Trfjt) a  (4.9)  with a frequency f f and the modulating frequency fj. k is the phase modulation index. If K  a  the signal in Eq. 4.9 is sampled using an ideal clock with a nominal time period T, then the n sample of the signal is given by m  v j-i(nT) re  = Af re  c o s (2irf fnT re  + k c o s (2TTfjnT)). a  (4.10)  From Eqs. 4.8 and 4.10, it is evident that they both represent an angle modulated signal sampled with an ideal clock. This indicates that when a pure sinusoid is sampled with an angle modulated clock, the sampled version of the sinusoid represents an angle modulated sinusoid sampled with an ideal clock. However, the relation between the constants determines the amplitude of the jitter on the sampled signal. Thus, if the relation between the angle modulation constants is known, the modulation of the clock signal can be calculated from the modulation information of the sampled signal. In a sampling process, frequency division is inherent [Ega81]. Since the phase of the modulated sampling signal is transferred to the output only at sampling instants, similar to the process of frequency division, the low frequency modulation is transferred to the sampled signal. Hence, if the sampling clock is modulated with a low frequency signal, the sampled signal gets modulated by the signal of  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  63  the same frequency. Due to the inherent frequency division, the modulation index of the sampled signal is decreased by a factor equal to the ratio of the sampled frequency to the sampling frequency [Ega81]. Hence, by measuring the frequency modulation parameters of the sampled sinusoid, the modulation of the clock can be calculated. The BIST scheme presented next relies on this principle.  4.2 The BIST Scheme  A BIST scheme proposed in [Ton93] makes use of an on-chip analog stimulus generator and on-chip DSP resources to perform the SNR test of an ADC. An on-chip stimulus generator is used to obtain a known signal which is sampled using an ADC and a system clock. A Fast Fourier Transform (FFT) is performed on the sampled signal to obtain the SNR. This SNR serves as afigureof merit for the ADC. In such an SNR calculation, the jitter information is lost due to the summation of frequency contents other than the signal frequency. Our BIST scheme is based on analysis of the FFT results from the point of view of angle modulation and thus yields jitter information. The BIST is conducted through the following steps - (I) the digital circuitry of the IC is tested using conventional digital BIST or tester-based techniques, (U) a low frequency signal is generated using a stimulus generator, (Ul) the low frequency signal is sampled by an ADC, (IV) an FFT is performed on the sampled signal, (V) a peak search is performed on the FFT results to identify signal and highest jitter components, (VI) p-p value of jitter is calculated. The block diagram of the BIST scheme is shown in Fig. 4.2.3.  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  FFT  ADC audio frequency ( *~ generator  elk  Peak search  64  Calculation of Jpp  clock signal under test  Figure 4.2.3  The block diagram for BIST.  The following describes the steps involved i n the B I S T i n detail. STEP I : The digital circuitry on the IC is tested before the actual jitter test is performed. This is necessary as the B I S T scheme makes use of the digital components of the I C . The digital circuitry can be tested using a number of well established techniques such as scan and digital BISTs using pseudo-random test patterns [Wil82]. The digital circuitry can also be tested using A T E s commonly found i n the industry. STEP II : A sinusoid of known amplitude and frequency is generated on chip. The generation of such stimulus is now possible on the chip itself with the introduction of architectures focused on testing. A n example of such a generator can be found i n [Lu94]. L u et al. have presented a signal generator designed specifically for mixed-signal testing. STEP III : The stimulus (sinusoid) generated by the on-chip generator is supplied to the analog input of the A D C . The sampling clock of the A D C is chosen to be the clock signal under test. The samples of the sampled sinusoid are stored i n the on-chip R A M . A s mentioned earlier, a R A M is normally found on the class of ICs being considered.  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  65  STEP IV : A n F F T is performed on the sampled waveform stored i n the R A M i n Step I E . Again, most programmable D S P based ICs are capable of performing an F F T [Ter93]. The results of the F F T are stored i n the R A M . STEP V : A peak search is performed on the results of the F F T stored i n the R A M (from Step I V ) . The highest magnitude among the stored results normally corresponds to the frequency of the sampled signal. The next highest magnitude corresponds to the peak jitter frequency. These two magnitudes are recorded i n the memory. The sampled waveform record and the other magnitudes obtained as a result of the F F T are discarded. STEP VI : The peak jitter on the sampling clock is calculated from the amplitudes recorded i n Step V as follows. Let the sampled sinusoid be the reference sinusoid with a frequency f f re  amplitude. From Chapter 3, for a case of sinusoidal jitter, J  and a unity  , the p-p jitter on the reference  ppTef  signal (sampled signal) i n U l (unit interval), is given by  where Af f is the peak frequency deviation of the carrier (sampled signal) and fj is the jitter K  frequency. E q . 4.11 can be used to obtain the magnitude of jitter on the sampled signal i n the peak-to-peak form. A l s o , it is known from the theory of angle modulation that, for small values (<0.8) of f3 (modulation index), the relation between f3 and the amplitudes of the sidebands is given by [Hyk92]  4.  66  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  where V is the amplitude of the sideband and V is the amplitude of the carrier frequency p  component. From Eqs. 4.11 and 4.12, we obtain  •W  = 7^-  (4-13)  E q . 4.13 is used to obtain the amplitude of jitter on the reference signal, from the results of the F F T . To obtain the jitter parameters for the clock signal under test, the process of frequency division must be taken into account, as explained i n the previous section. Hence, to account for the frequency division, multiplying the jitter i n E q . 4.13 by fjf f re  gives the  jitter on the sampling clock, i.e.,  Jpp  =  Jppref  (4.14)  X ~Z  Jref  or,  J??  = r i ? x "j—-•  (4-15)  The experimental peak-to-peak jitter is calculated from E q . 4.15. V and V are obtained p  from the results of the F F T by performing a peak search (Step V above). f and f f are known s  K  constants. Since, the scheme is targeted towards the measurement of the peak value of jitter, only the highest jitter amplitude is considered and other frequency (jitter) components are not considered. The overhead required for the B I S T scheme includes the signal generator, the control circuitry, and the R O M area for storing the test routine. The overhead of the signal generator  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  67  can be justified by the recognition of the fact that the generator can be shared by other tests such as the signal-to-noise ratio (SNR) test presented i n [Ton93]. required for the B I S T is not likely to be excessive.  The control circuitry  The R O M area for storing the test  routine can be justified i f the F F T routine is considered a part of normal functionality of the IC. If this is the case, the peak search routine w i l l be the R O M overhead. The peak search routine is normally simple and does not require unacceptable overhead.  The total  overhead is specific to the implementation and depends on the size of the basic IC. With the above restrictions, the presented scheme can be used as a production stage B I S T . However, the presented B I S T scheme does not apply to the cases which include excessive noise from other sources such as amplitude noise and quantization noise. In such cases, the noise from other sources may be mistaken for jitter.  4.2.1 Simulation To verify the scheme, a relatively new method of simulation was chosen. The circuit shown i n F i g . 4.2.4, comprised of two types of models, was used to simulate the scheme. The A D C block was written i n an analog hardware description language ( A H D L ) [Spt94]. The voltage-controlled oscillator ( V C O ) and sinusoidal generators were taken from the "Functional" library i n Cadence [Ana94]. These blocks have been realized using controlled sources.  The circuit was simulated using the Spectre simulator [Spr94].  The F F T was  performed using the built-in Discrete Fourier Transform (DFT) capability of the Analog Artist simulation interface [Ana94]. Frequency modulation was performed using the V C O to simulate a clock with known jitter. The modulating signal was supplied as the control voltage to the V C O . The detailed  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  68  circuit diagram is given i n Appendix B , F i g . B . 5 .  FFT  ADC audio _JL frequency( ^ ) generator v^^/ elk  VCO  multitone generator  Figure 4.2.4  The simulation block diagram.  Fig. 4.2.5 shows an F F T plot of the reference signal sampled by the jittered clock. In this case, the frequency of the reference sinusoid is 10 M H z . The jitter frequency was chosen to be 200 k H z . The clock frequency was chosen to be 100 M H z . It is observed that the jitter components at 10.2 and 9.8 M H z are discernible. The V C O gain was 10 M H z / V and the length of the F F T was 1024. The amplitudes of 200 k H z signal was chosen to be 10 m V . The corresponding B is 0.5.  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  69  dfUYTC'Vout") 0 2 s - 2 5 1 2 2 4 )  iii  HI m HI Ml Ml I  IM|I  I  ,111111 1111)1  DIM  I I  J  ,  jugiu^u,.ni,, ,ii  J  I  I  I  I  I  l _ l  I  I  I l _ l _  10.  J  I  I  L  20.  J  I  I  L  X10  1  30.  Frequency (Hz) — > Figure 4.2.5  Jitter spectrum with A H D L simulation.  4.2.2 Hardware Verification y  The experimental verification of the B I S T scheme was done on HP75000 D 2 0 system using the V E E T E S T mixed-signal test environment [Vee95, D2092]. Fig.4.2.6 shows the setup used to perform the experiment. The A D C used was the H P a l 4 3 0 [Adc94] module. The reference signal was supplied by the H P E1445a function generator which is a part of the HP75000 D 2 0 system. The frequency modulated clock signal was obtained directly from an H P 33120a function generator. A separate F F T block was not required for this case  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  70  as the spectrum display block includes the F F T processing. The external generator is not shown i n F i g . 4.2.6.  j - Reset j  ^ I n i t i a t e ) : Abort  | DACSource  :  ! function  L..ii?.?=°il  Internal  \j j n i t s I  Volts  Panel  } F r e q Mode LJ.i.*?.<L!'.?.<:S.. j  ! Amplitude  L....-.9.9.°.?.?.L.  1'Offset f # Cycles  jO'.'OOOOOj Auto  1  Set-up  j  5  i  tfrig  Sour  iFrequency  -Frequency  1  j  : """2*0*0 "k"  JRes'et ] j  Main  ]  Input Range Input  Couple  Blocksize  [100k :  1024  jtoto'scale"! 1  ~1 Freq  |  300k j  20k/  Center Freq Span Zoom Mode iAUTO RANGE  :AUTO ZERO  •Si Figure 4.2.6  Experimental setup for the BIST scheme.  A sinusoid of unity amplitude and a frequency of 200 k H z was sampled using the system's A D C with a jittered clock signal. A frequency modulated clock signal was supplied to the A D C as a jittered clock. The unmodulated clock frequency was 10 M H z . The modulation of the clock signal was performed using a sinusoid of 10 k H z frequency for various values of A / . The experimental jitter amplitude is obtained from E q . 4.15 and is compared with the theoretical amplitude calculated using E q . 3.14, i.e., kf x pp  7T X  A  m  /„  (4.16)  4.  A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  71  The experimental and theoretical amounts of jitter are summarized i n Table 4.2.1.  Table 4.2.1  It is  Experimental results  fc  Af  fm  V  Vp  calculated  experimental  (MHz)  (kHz)  (kHz)  (mV)  (mV)  Jpp (UI)  Jpp (UI)  10  10  10  998  18.9  0.318  0.301  10  15  10  998  30.1  0.477  0.480  10  20  10  998  39.6  0.636  0.631  10  25  10  998  47.9  0.796  0.763  10  30  10  998  54.7  0.955  0.872  observed that the theoretical and experimental results are i n close agreement.  It is also  observed that at higher jitter amplitudes, the amount of error is more than the lower amplitudes. This is due to the fact that the calculations presented i n this chapter are not valid for the high values of angle-modulation index (>0.8) due to the side bands that result at higher modulation indices [Hyk92]. The results are plotted i n F i g . 4.2.7. The F F T plot obtained by sampling the sinusoid with a frequency modulated clock signal is shown i n F i g . 4.2.8. The modulation sidebands are easily separable from the rest of noise. In the case shown here, the reference frequency was 200 k H z , the modulation frequency was 10 k H z and frequency deviation was 30 k H z .  4. A BIST Scheme for Jitter Measurement in DSP-Based Mixed-Signal ICs  1.5r  Jpp experimental (o) Jpp theoretical (x)  0.5 \  10  Figure 4.2.7  Figure 4.2.8  15  20 Af (k Hz)  Theoretical vs.  >  25  experimental results.  F F T plot of the sampled sinusoid.  30  72  Chapter 5 Conclusions and Future Work  5.1 Conclusions In this thesis, the problems and issues that beset clock jitter testing of ICs have been outlined. A l o n g with an overview of jitter, two non-traditional and novel B I S T schemes have been presented. The thesis focuses on developing test schemes to overcome the limitations of A T E s . A novel method of performing a jitter tolerance test of clock and data recovery units is presented. The scheme uses l o w overhead. The approach is to use the pre-existing blocks on an I C for the test purposes. Specifically, it has been demonstrated that the clock synthesis units, i n conjunction with a pseudo-random data source, can be used as an effective source of jittered data. The method provides easy control over the jitter supplied to the C R U . In a specific case, it has been shown that the scheme can be implemented with the overhead of a signal generator and a capacitor. The results obtained through theoretical calculations and simulations of the B I S T scheme have been found to be i n close agreement with each other, thus providing a proof of concept. The most critical aspect of the presented scheme, i.e., the generation of the jittered clock, was verified i n hardware. The results demonstrate the effectiveness of the method for generating jittered clock signals. Variations of the principal method i n the forms of the reduced-set jitter tolerance test, the lock-in range test and the frequency test (Appendix G ) have also 73  5.  74  Conclusions and Future Work  been presented.  The mathematical analysis and a numeric example have been used to  substantiate the viability of the lock-in range test. However, a separate mathematical analysis or simulation was not performed to support the frequency test variation. A second B I S T scheme for the jitter measurement of the clock signal i n DSP-based mixed-signal ICs has been presented. The B I S T is designed to measure the peak-to-peak jitter on the sampling clock used i n DSP-based ICs.  It has been shown that the B I S T  scheme is suitable for the specific class of ICs considered. Further, the presented scheme is suitable for the cases where jitter is the prominent source of the overall noise. Simulation and experimental results have been provided i n support of the presented scheme. The feasibility of both the B I S T schemes presented i n this thesis rely on the availability of a number of components as parts of normal functionality of the ICs being tested. This makes the B I S T schemes essentially application-specific. Nevertheless, it has been demonstrated that the B I S T for jitter testing is feasible for the applications that have been traditionally considered unsuitable for B I S T techniques.  5.2 Future Work It is by no means claimed that the jitter test problem has been completely solved i n this thesis. Since this work is a first step towards the B I S T techniques for jitter tests, there is certainly room for improvement and further development of the presented ideas.  The  variations of the B I S T for C R U s should be explored further as they have the potential to reduce the test overhead without compromising the quality.  In particular, a generic  test algorithm for reduced-set jitter-tolerance test for generic P L L s should be explored as  5.  Conclusions and Future Work  75  the methodology presented i n this thesis is applicable only to critically and overdamped P L L s . More work is needed to extend the methodology to the under-damped P L L s . Use of various waveforms other than sinusoidal waveforms should also be studied i n a more detailed manner. In addition to this, since optical-to-electrical and electrical-to-optical conversions are always involved i n typical S O N E T / S D H networks, the jitter allocation to the conversions must be taken into account to determine the test parameters. This w i l l depend on the jitter characteristics of the individual convertors used and is specific to the application. The B I S T scheme for the jitter measurement of DSP-based ICs is suitable for applications where jitter is the dominating source of noise as compared to other noise sources.  The  improvement of the presented methodology should be sought to take other noise sources into account. A l s o , the analysis leading to the concept underlying the B I S T scheme is inductive. A more formal proof of concept is desirable. The B I S T scheme for the C R U exploits a P L L ' s capability of performing angle modulation. This capability has been used to generate a jittered clock. Noting that a P L L can be used to demodulate an angle-modulated signal, possibilities of using a P L L for jitter measurement i n B I S T schemes should be sought. It is generally required to measure the jitter on the clock signal generated by a C S U on data transceiver ICs. If the C R U P L L is used to measure jitter by demodulation, the resulting scheme would result i n a l o w overhead B I S T scheme.  References  [Adc94] H P E 1 4 3 0 A V X I A D C Operator's Guide, Hewlett Packard Company, 1994. [Ana94] Analog Artist Mixed-Signal Reference, Cadence Design Systems, Inc. March 1994. [Bar87] P . H . Bardell, W . M c A n n e y and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques. 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[Spt94] SpectreHDL Reference Manual, Cadence Design Systems, Inc. Sept. 1994. [Spr94] Spectre Reference Manual, Cadence Design Systems, Inc. M a r c h 1994. [Sun95] S U N I - 1 5 5 - L I T E , P M 5346; S A T U R N User Network Interface:  PMC-Sierra,  Inc., 1995. [Syn94] "Synchronous Optical Network ( S O N E T ) - Jitter at Network Interfaces," Tech. Rep. A N S I T l . 105.03-1994, American National Standard for Telecommunications. [Ter93]  E . Teraoka, T. Kengaku, I. Yasui, K . Ishikawa, T. Matsuo, H . Wakada, N . Sakashita, Y . Shimazu and T. Tokuda, " A Built-in Self-test for A D C and D A C i n a Single Chip Speech Codec," i n Proceedings of International Test Conference, pp. 791-796, 1993.  [Ton93] M . F . Toner and G . Roberts, " A B I S T Scheme for an S N R Test of a Sigma-Delta A D C , " i n Proceedings of International Test Conference, pp. 805-814, 1993. [Tri89] P. R. Trischitta and E . L . Varma, Jitter in Digital Transmission Systems. Artech House: Norwood, Mass., 1989, Chapter 1.  References  79  [Vee95] H P V E E , Reference Manual, Hewlett Packard Company, Jannuary 1995. [Ver90] Verilog X L Reference Manual, Volume 1, Version 1.2b, Cadence Design Systems, Inc. N o v .  1990.  [Wag90] F . Wagdy and S. Awad, "Effects of Sampling Jitter on Some Sine Wave Measurements," i n IEEE Transactions on Instrumentation and Measurement, vol.  39, pp. 86-89, 1990.  [Wag91] F . Wagdy and S. Awad, "More on Jitter Effects on Sinewave Measurements," i n IEEE Transactions on Instrumentation and Measurement, v o l . 40, pp. 549-552, 1991. [Wes85] N . Weste and K . Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective, 2nd ed. Addison-Wesley, Reading Mass., 1985, Chapter 3. [Wil82] T. W . Williams and K . P . Parker, "Design for Testability - A Survey," i n IEEE Transactions, v o l . 31, pp. 2 - 1 5 , 1982. [Wol91] D . Wolaver, Phase-Locked Loop Circuit Design, Prentice H a l l , Englewood Cliffs, N.J.,. 1991. [You94] J. Young, "Jitter Considerations i n H i g h B i t Rate Digital Video Signals," i n IEEE Transactions on Broadcasting, v o l . 40, pp. 82-90, 1994.  Appendix A. List of Acronyms  Appendix A. List of Acronyms  ac  Alternating Current  ADC  Analog-to-digital Converter  AHDL  Analog Hardware Description Language  ANSI  American National Standards Institute  ASIC  Applications Specific Integrated Circuit  ATE  Automatic Test Equipment  ATM  Asynchronous Transfer Mode  BER  B i t Error Rate  BERT  B i t Error Rate Tester  B-ISDN  Broadband Integrated Services Digital Network  BIST  Built-in Self-test  CMOS  Complimentry Metal Oxide Semiconductor  CRU  C l o c k Recovery Unit  CSU  Clock Synthesis Unit  DAC  Digital-to-analog Convenor  DC  Direct Current  dB  decibel  DFT  Discrete Fourier Transform  DSP  Digital Signal Processing  DUT  Device Under Test  FFT  Fast Fourier Transform  FIFO  First In First Out  FM  Frequency Modulation  GHz  G i g a Hertz  GPIB  General Purpose Interface Bus  80  Appendix A. List of Acronyms  170  Input/Output  ISDN  Integrated Services Digital Network  kHz  K i l o Hertz  LFSR  Linear Feedback Shift Register  LPF  L o w Pass Filter  Mbps  Mega bits per second  MHz  Mega Hertz  NE  Network Element  nS  nanoSecond  OC-N  Optical Carrier at level N  PD  Phase Detector  PLL  Phase Locked L o o p  PM  Phase Modulation  P-P  peak-to-peak  pS  picoSecond  rms  root mean square  SDH  Synchronous Digital Hierarchy  SNR  Signal to Noise Ratio  SONET  Synchronous Optical Network  SORD  Synchronous Optical Reference Design  STS-N  Synchronous Transport Signal at level N  Ul  Unit Interval  VCO  Voltage Controlled Oscillator  VLSI  Very Large Scale Integration  81  Appendix B. Schematics  82  Appendix B. Schematics  Appendix B. Schematics  83  4 Figure B . l Low pass filter for CSV.  Appendix B. Schematics  84  en-  o Qq. u  o m  o  CD  CD.  CN  c  Figure B.2  Phase detector used in C R U and C S U .  Appendix B. Schematics  85  m  CO  cn  LO  Figure B.3 The Clock and data recovery unit (CRU).  Appendix B. Schematics  86  Figure B.4 The Clock synthesis unit (CSU).  Figure B.5 BIST scheme for DSP-based ICs.  Appendix B. Schematics  88  o o m in Z> 2  .1  jj  111  ii ID  cn CJ)  00 If)  tib JJ10~03A  m  • mo  8  UOD~D}Dp )no~D)Dp  Figure B.6 BIST scheme for jitter tolerance test.  n  I  Appendix  C. Simulation  Results  89  Appendix C. Simulation Results  Data in  — i  /net41 | ] _ _ Aec_clk H_ .ii — i i 5.0  i  r -i i—i r i I U_l il_ _  Transient Response i— l —I i I — r ~ iii r - | r -| r ~ iI r - | I r ~ i I u J I  1  — i  r -  i  i  i—i  l  /'net iu . - RZ-like clock  i—i  I  l  i—i  i_U  i  l  i—i  L_  I—I  1  n  L  1  1  1  1 1  I  I  3.0 E  1.0 \  1  I  I !  11  I  -I.0L  _i  1 1 1  i_  _i  1 1 1 1 1 1 1 1 1 1 1 1  LI  i_  _i  1 1 1 1  i_  _i  1 1 1  i_  / r e U e - VCO OUTPUT (Non shitted)  n n  E  -5.2&L 2.47  _i—J  1—1 1—1 1—1 1—1 1—1 1—1 1—1 L_I 1—1 1—1 1—1 1—1 1—1  2.49  2.51  2.53  2.55  Figure C . l No bit in error, data transition density = 100 %.  2.5.7 time  Appendix C. Simulation Results  90  Appendix C. Simulation Results  Figure C.3 Bits in error with data transition density = 100 %.  91  Appendix C. Simulation Results  Data in  92  Transient Response  /sHi/nd£Lr L_rL_rL_rLhLrLr~! __  rLri  i LI  L_n_r~~L_rL_  A c c elk PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP L J J J J J J J J J J J J J J J d J J J J J J J J J J J J J J J J J J J J J J J J J J J J J J i J J J J J J J J J J J J J J J u  /rec_cm  i:  yg  /lpf_cut  Bits in error-  s' t  5.01 ic 4.0 C c  "I  t 2.0 _ h  F  1.0 f  C  0.0: C  -1.0t h  C  -34 t -4.0:  1-  c  -7.0L  2.8  F i g u r e C.4 B i t s i n error w i t h pseudo-random data  3.0  time  Appendix C. Simulation Results  93  Appendix C. Simulation Results  94  Sinusoidal modulation input response  — 20.Q_1 I I I I I I I I I I I I I I I I I I I  '  i  I I  time Figure C.6 Jitter generation with sinusoidal input.  Appendix C. Simulation Results  Figure C.7 Jitter generation with triangular input.  95  Appendix C. Simulation Results  Figure C.8 Jitter generation with square wave input.  96  Appendix C.  Simulation Results  97  Transient Response *10 20.  — 20.1  o • /r,e 57 +  L_J  III  L  Modulating signal  J__l  I  I  III  I  L  I  I L_J L_  I  I  1} VCO input  40.  10.  -20i 0.0 _L_J  III  I  L  J_l  4.0  l_l  I  I I  I  L_J  8.0  I I  III  I  L_l  I  12.  I  I  II  Figure C.9 Jitter generation with square wave input added to V C O control net.  II  x10" 16. time  l_  Appendix D. HDL Codes  98  Appendix D. HDL Codes 1. The Verilog code for the data generator. / / Verilog HDL for "data_gen" "_functional"  'timescale 1 ps/lps  module data_gen (elk,data_out)  ;  input elk; output data_out; reg mem[0:1090]; reg data_out;  i n i t i a l $readmernb ( "prbs23 .data", mem) ;  integer i ;  initial begin i = 0; end  Appendix D. HDL Codes  always ©(posedge e l k ) begin data_out=mem[i]; end  always @(negedge e l k )  begin  if  (i==1090)  begin i = 0; end else begin i=i+l; end end endmodule  99  Appendix D. HDL Codes  100  2. The Verilog code for the delay element. // The V e r i l o g code f o r the Delay element  // V e r i l o g HDL f o r "common", "delayx"  'timescale 1 ps/1 ps  module delayx  (in,out) ;  input i n ; output out; reg out;  always @(in) begin out = #3215 i n ; end endmodule  "_functional"  Appendix D. HDL Codes  101  3. The A H D L code for the analog-to-digital convertor.  module a_to_d (d7, d6, d5, d4, d3, d2, d l , dO, i n , elk) ( r i s e t i m e ,  falltime)  node [V, I ] d7, d6, d5, d4, d3, d2, d l , dO, i n , e l k ; parameter r e a l r i s e t i m e = O.Oln from  (0:inf);  parameter r e a l f a l l t i m e = O.Oln from  (0:inf);  { r e a l x; const r e a l h a l f r e f  = 0.5;  r e a l out7, out6, out5, out4, out3, out2, o u t l ,  analog { if  ($threshold(V(clk)-2.5, out7 = 0; out6 = 0; out5 = 0; out4 = 0; out3 = 0; out2 = 0; o u t l = 0; outO = 0; x = V(in);  1.0)){  outO;  Appendix D. HDL Codes  102  if  (x > h a l f r e f )  { O U t 7 ==  5. 0;  X  -= h a l f r e f ; } x * = 2 .0  if  (x > h a l f r e f )  { out6 -= 5. 0;  X  -= h a l f r e f ; } x * = 2 .0  if  (x > h a l f r e f )  { out5 == 5. 0;  X  -= h a l f r e f ; } x * = 2 .0  if  (x > h a l f r e f )  { out4 == 5. 0;  X  -= h a l f r e f ; } x * = 2 .0  if  (x > h a l f r e f )  { out3 == 5. 0;  X  -= h a l f r e f ; } x * = 2 .0  if  (x > h a l f r e f )  { out2 == 5. 0;  X  -= h a l f r e f ; } x * = 2 .0  if  (x > h a l f r e f )  { o u t l == 5. 0;  X  -= h a l f r e f ; } x * = 2 .0  if  (x > h a l f r e f )  { outO == 5. 0; }  } V(d7) <- $ t r a n s i t i o n (  out7, 0, r i s e t i m e ,  falltime  / i  V(d6) < - $ t r a n s i t i o n (  out6, 0, r i s e t i m e ,  falltime  i i  $ t r a n s i t i o n ( out5, 0, r i s e t i m e ,  falltime  i i  V(d4) < - $ t r a n s i t i o n ( out4, 0, r i s e t i m e ,  falltime  } i  V(d3) <-  $ t r a n s i t i o n ( out3, 0, r i s e t i m e ,  falltime  ) r  V(d2) <-  $ t r a n s i t i o n ( out2, 0, r i s e t i m e ,  falltime  1 r  V(dl)  $ t r a n s i t i o n ( o u t l , 0, r i s e t i m e ,  falltime  1 r  V(d0) <- $ t r a n s i t i o n ( outO, 0, r i s e t i m e ,  falltime  1 i  V(d5) <-  } }  <-  Appendix E. MATLAB Code  103  Appendix E . M A T L A B Code The M A T L A B code for plotting various P L L parameters, clear; f=l  : 500 :  4*10e6;  Rl=2*26.6*1000; R2=200; C3=13.5*10e-12; C=0.47*10e-6; %%%%%%%%%%%%%%%%% L P F , V C O a n d PD p a r a m e t e r s kd=5/(pi); ko=100*2*pi*10e6; kh=R2/Rl; %%%%%%%%%%%%%%%%%%%%%% w=2*pi*f; w2=l/(R2*C); w3=4/(R1*C3); %%%%%%%%%%%%%%%%%%%%%%% Fs=kh.*((j*w+w2)./((j*w).*(j*w/w3 Gs=ko*kh*Fs./(j*w); Js=l+Gs; Hs=Gs./(1+Gs);  +1)));  Appendix E. MATLAB Code  104  %%%%%%%%%%%%%%%%%%%%%%% magHs=abs(Hs);magGs=abs(Gs); magJs=abs(Js); magFs=abs(Fs); %%%%%%%%%%%%%%%%%%%%%%  plots  log_Hs=10*logl0(magHs); subplot(3,1,1) semilogx(f,log_Hs); grid; title('H(s)'); xlabel('frequency(Hz)-->'); ylabel('magnitude[H(s)] print  (dB)—>');  log_hs  figure(2) ; log_Gs=10*logl0(magGs); subplot(3,1,1)  semilogx(f,log_Gs); grid; title('G(s) ' ) ; xlabel('frequency(Hz)-->');  Appendix E. MATLAB Code  ylabel('magnitude[G(s)] print  105  (dB)-->');  log_gs  figure(3);  log_Js=10*logl0(magJs);subplot(3,1,1)  semilogx(f,log_Js); grid; title('J(s)'); xlabel('frequency(Hz)-->'); ylabel('magnitude[J(s)] print  log_js  figure(4);  log_Fs=10*logl0(magFs); subplot(3,1,1)  semilogx(f,log_Fs); grid; title('F(s)');  (dB)-->');  Appendix E. MATLAB Code  106  xlabel('frequency(Hz)-->'); ylabel('magnitude[F(s)] print  log_fs  (dB)—>');  Appendix F. SONET Jitter Specifications  107  Appendix F. SONET Jitter Specifications F . l Jitter Transfer : Jitter transfer is the ratio of jitter on the output of an O C - N / S T S - N signal to the jitter applied on the input of an O C - N / S T S - N signal versus frequency. F i g . F . l . l and Table F . l . l show the jitter transfer curve applicable to O C - N network interfaces. In general, jitter transfer does not apply to transmitters and receivers. It mainly applies to regenerators [Syn94].  Frequency (Hz) Figure F . l . l Jitter transfer specification [Syn94].  Table F . l . l Jitter transfer specification [Syn94].  O C / S T S level  fc (kHz)  P (dB)  1  40  0.1  3  130  0.1  12  500  0.1  Appendix F. SONET Jitter Specifications  108  F.2 Output Jitter : Jitter generation or "output jitter" specifies the acceptable phase noise level from a S O N E T transmitter.  Current requirements for a S O N E T network element is that the  maximum jitter be less than 0.01 U l rms (root mean square) and 0.1 U l p-p when measured with a high pass filter having a cut-off of 12 k H z and a l o w pass having a minimum cut-off of 5 M H z [Syn94][Cor94].  Appendix G. Frequency Test  109  Appendix G. Frequency Test The basic B I S T scheme for jitter tolerance test and the variations of the scheme discussed in Chapter 3 use some kind of function generator to supply a signal to the V C O input. If none of the discussed variations is feasible, then, a plain frequency test can be performed without the need of a function generator. This can be done by a simple loop-back operation of the C R U and C S U . The C S U can be used to generate a line rate clock signal. This clock is then used i n conjunction with a data generator to feed data to the C R U . The recovered data from C R U is checked for bit-errors. This is a functional test of both the C R U and the C S U . This test does not take jitter into account. The block diagram is shown i n F i g . G . l .  Unit under test (Jittered) Clock  Clock Synthesis Unit (CSU)  t Data Generator  (Jittered) Data  Clock Recovery Unit (CRU)  Figure G . l Frequency test.  1  ^  BER TESTER  

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