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Simulation of transient phenomena in high voltage direct-current converter systems Bhattacharya, Subroto 1987

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Simulation of Transient Phenomena in High Voltage Direct-Current Converter Systems by Subroto Bhattacharya B.Tech.. K.R.E. College, Mangalore, INDIA, 1981 M.Tech., Indian Institute of Technology, Kan pur. 1983 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY in THE FACULTY OF GRADUATE STUDIES Department of Electrical Engineering We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA March, 1987 © Subroto Bhattacharya, 1987 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 DE-6(3/81) Abstract In this thesis models for the simulation of transient phenomena in high voltage direct-current systems are developed. The new converter model is versatile and the solution algorithm is free from numerical oscillations. A new generic inverter control described in this thesis is based on a predictive approach. Steady-state and transient simulations of two-terminal and multi-terminal (i.e., a parallel converter system) high voltage direct-current systems are carried out using the new converter system model. Comparison between the two-terminal transient simulation results and the high voltage direct-current simulator outputs shows good agreement. An alternating-current/direct-current initialization procedure for the Electro-magnetic Transients Program (EMTP) has been investigated and a novel initial-ization algorithm has been suggested in this thesis. i i Contents A B S T R A C T ii ACKNOWLEDGEMENTS vi 1 INTRODUCTION 1 2 CONVERTER MODELS IN ELECTROMAGNETIC TRANSIENTS PROGRAMS 3 2.1 Introduction 3 2.2 Review of Existing Converter Models 3 2.2.1 Converter Models for Digital Simulation 4 2.2.2 Converter Models in the E M T P 5 2.3 New Converter Model 7 2.3.1 Transformer Model 8 2.3.2 Converter Model 10 2.3.3 Series Connection of Bridges 13 2.3.4 Solution Algorithm and Interface with the E M T P 16 2.3.5 Parallel Converter Representation 21 3 HVDC CONTROL REPRESENTATION 25 3.1 Hierarchy in H V D C Control Systems 25 3.2 Converter Firing Control (CFC) 27 iii iv 3.2.1 Alpha Minimum Firing 30 3.2.2 Commutation Margin Control Limiter 30 3.2.3 Emergency Triggering 30 3.3 Current Control Loop 31 3.3.1 Voltage-Dependent Current Order Limiter (VDCOL) 31 3.3.2 Current Control Amplifier 35 3.4 Commutation Margin Control Loop 37 3.4.1 Review 37 3.4.2 A New Generic Model 39 3.5 Solution Method for Control System Equations 48 3.6 Case Study 49 4 CASE STUDIES ON A TWO-TERMINAL HVDC LINK 52 4.1 Test System 52 4.2 Simulation for Steady-State Conditions 54 4.3 Simulation of Transient Conditions 54 4.3.1 Remote Three-Phase-to-Ground Fault 54 4.3.2 Single-Phase-to-Ground Fault 67 4.3.3 Three-Phase-to-Ground Fault 86 5 MULTI-TERMINAL CONVERTER SIMULATION 96 5.1 Multi-terminal dc Control System 97 5.1.1 Current Coordination Control 99 5.2 Simulation Results 99 5.2.1 Parallel Converter System 99 5.2.2 Three-terminal Converter System 107 6 A C / D C INITIALIZATION IN T H E E M T P 122 V 6.1 Introduction 122 6.2 AC/DC Initialization Procedure 124 6.2.1 Relationship between ac/dc parameters 124 6.2.2 Algorithm 126 6.3 Numerical Example 128 7 CONCLUSIONS 129 7.1 Simulation of Transient 129 7.1.1 Converter Model 129 7.1.2 Control Model 130 7.1.3 Simulation 130 7.2 AC/DC Initialization 131 7.3 Scope for Future Work 131 BIBLIOGRAPHY 133 A TOPICS RELATED TO CHAPTER 2 140 A.1 Numerical Oscillation with Implicit Trapezoidal Rule 140 A.2 Open Bridge L~5 Matrix for Three-Phase Transformer Banks . . . . 142 A.3 Relation between the Internal and the External Nodes 143 B A TWO-TERMINAL HVDC SYSTEM DATA 145 C MULTI-TERMINAL HVDC SYSTEM DATA 149 C.1 Parallel Converter System Data 149 C.2 Three-Terminal System Data 149 D A C / D C INITIALIZATION ALGORITHM 151 List of Tables 6.1 Results of the steady-state solution for the ac/dc system of Figure 5.9127 v i List of Figures 2.1 Circuit representation of valve by Woodford 6 2.2 A single-phase two-winding transformer 9 2.3 A single-bridge system 11 2.4 A series converter system 14 2.5 Reallocation of converter nodes in G matrix 19 2.6 Block diagram of the interface between the converter model and the EMTP 23 2.7 A parallel converter system 24 3.1 Two-terminal HVDC control characteristics without the influence of a voltage-dependent current order limiter [29,30j 26 3.2 Block diagram of converter firing control 29 3.3 Block diagram of current and commutation margin controller 32 3.4 Characteristic of voltage-dependent current order limiter[29] 33 3.5 Two-terminal HVDC characteristic with VDCOLJ29J 33 3.6 Block diagram of voltage-dependent current order limiter 34 3.7 Block diagram of the current control amplifier 36 3.8 Commutation voltage waveform of a valve 38 3.9 Block diagram describing the fault detection method 42 3.10 Relationship between average Udio and the gamma order 44 3.11 Result of fault simulation: without change of gain 45 vii viii 3.12 Result of fault simulation: with change of gain 46 3.13 Transient response of a dc system due to a step change in the current (from l .Op.u. to 0.75p.u.), using the E P C scheme at the rectifier and Hingorani's extinction angle control at the inverter[42j 50 3.14 Transient response of a dc system due to a step change in the current (from l .Op.u. to 0.75p.u.), using the E P C scheme at the rectifier and the new generic model at the inverter 51 4.1 A test system showing a two-terminal H V D C system 53 4.2 Steady-state dc voltages and current at the rectifier and at the in-verter terminals 55 4.3 Steady-state voltages across converters at the rectifier side. . . . . . . 56 4.4 Steady-state voltages across converters at the inverter side 57 4.5 Steady-state voltages across converter valves at the rectifier and at the inverter end 58 4.6 Steady-state control outputs and U<n0 outputs at the rectifier and at the inverter ends 59 4.7 Remote three-phase-to-ground fault at the rectifier end: dc terminal voltages and currents 61 4.8 Remote three-phase-to-ground fault at the rectifier end: dc controls and Udio outputs 62 4.9 Remote three-phase-to-ground fault at the inverter end: dc terminal voltages and currents 63 4.10 Remote three-phase-to-ground fault at the inverter end: dc controls and Udio outputs 64 4.11 Remote three-phase-to-ground fault at the inverter end: dc terminal voltage before the smoothing reactor 65 4.12 Remote three-phase-to-ground fault at the inverter end: voltages across the converters and dc link current 66 ix 4.13 Single-phase-to-ground fault at the rectifier end: dc terminal volt-ages and currents 68 4.14 Single-phase-to-ground fault at the rectifier end: control and c7dl0 outputs 69 4.15 Single-phase-to-ground fault at the rectifier end: rectifier ac bus voltages 70 4.16 Single-phase-to-ground fault at the rectifier end: transformer inrush current at the rectifier side 71 4.17 Single-phase-to-ground fault at the rectifier end: inverter ac bus voltages 72 4.18 Single-phase-to-ground fault at the rectifier end: transformer inrush current at the inverter side 73 4.19 Single-line-to-ground fault at the rectifier end: dc voltage and cur-rent waveforms at the inverter side (HVDC simulator results[45]). . 74 4.20 Single-line-to-ground fault at the rectifier end: control and Udio waveforms (HVDC simulator results [45]) 75 4.21 Single-phase-to-ground fault at the inverter end: dc terminal volt-ages and currents 77 4.22 Single-phase-to-ground fault at the inverter end: control and Udio outputs 78 4.23 Single-phase-to-ground fault at the inverter end: rectifier ac bus voltages 79 4.24 Single-phase-to-ground fault at the inverter end: transformer inrush current at the rectifier side 80 4.25 Single-phase-to-ground fault at the inverter end: inverter ac bus voltages 81 4.26 Single-phase-to-ground fault at the inverter end: transformer inrush current at the inverter side 82 X 4.27 Single-line-to-ground fault at the inverter end: dc voltage and cur-rent waveforms at the inverter side (HVDC simulator results[45]). . 84 4.28 Single-line-to-ground fault at the inverter end: control and Udio waveforms (HVDC simulator results[45]) 85 4.29 Three-phase-to-ground fault at the rectifier end: dc terminal volt-ages and currents 87 4.30 Three-phase-to-ground fault at the rectifier end: control and Udio outputs 88 4.31 Three-phase-to-ground fault at the rectifier end: rectifier ac bus voltages 89 4.32 Three-phase-to-ground fault at the rectifier end: transformer inrush current at the rectifier side 90 4.33 Three-phase-to-ground fault at the rectifier end: inverter ac bus voltages 91 4.34 Three-phase-to-ground fault at the rectifier end: transformer inrush current at the inverter side 92 4.35 Three-line-to-ground fault at the rectifier end: dc voltage and cur-rent waveforms at the inverter side (HVDC simulator results[45]). . 93 4.36 Three-line-to-ground fault at the rectifier end: control and Ua0 waveforms (HVDC simulator results[45j) 94 5.1 A block diagram of a current balancer. For a rectifier: X = 1, Y = -1; For an inverter: X =-1, Y =1 98 5.2 Steady-state simulation of the parallel converter system: ac bus volt-ages at the rectifier and the inverter ends 100 5.3 Steady-state simulation of the parallel converter system: dc bus volt-ages and line current 101 5.4 Steady-state simulation of the parallel converter system: dc terminal voltages before the smoothing reactor 102 xi 5.5 Current order change in the parallel converter system: current order of each arm 103 5.6 Current order change in the parallel converter system: dc current through each arm 104 5.7 Current order change in the parallel converter system: dc terminal voltages 105 5.8 Current order change in the parallel converter system: firing angle of each arm 106 5.9 A three-terminal system 108 5.10 Remote three-phase fault at the second inverter of the three-terminal system: current order of each arm 109 5.11 Remote three-phase fault at the second inverter of the three-terminal system: dc current through each arm 110 5.12 Remote three-phase fault at the second inverter of the three-terminal system: dc terminal voltages I l l 5.13 Remote three-phase fault at the second inverter of the three-terminal system: firing angle of each arm 112 5.14 Remote three-phase fault at the second inverter of the three-terminal system: ac voltages at rectifier 113 5.15 Remote three-phase fault at the second inverter of the three-terminal system: ac voltages at the second inverter 114 5.16 Remote three-phase fault at the rectifier of the three-terminal sys-tem: current order of each arm 115 5.17 Remote three-phase fault at the rectifier of the three-terminal sys-tem: dc current through each arm 116 5.18 Remote three-phase fault at the rectifier of the three-terminal sys-tem: dc terminal voltages 117 5.19 Remote three-phase fault at the rectifier of the three-terminal sys-tem: firing angle of each arm 118 xii 5.20 Remote three-phase fault at the rectifier of the three-terminal sys-tem: ac voltages at the rectifier 119 5.21 Remote three-phase fault at the rectifier of the three-terminal sys-tem: ac voltages at the second inverter 120 6.1 Generation of harmonics in filter currents 123 A . l A simple inductor diode circuit 140 A. 2 Current and voltage variation in the inductor circuit 141 B. 1 Filter system configuration 147 xiii Acknowledgements I wish to express my gratitude to my parents, who inspired me to undertake this venture. My heartfelt thanks to Messrs. M. Eitzmann, D. Osborn, M. Barhman and M. Hyttinen of ASEA Power System Center, New Berlin, Wisconsin, for their tech-nical advice and to Prof. W.F. Long, University of Wisconsin, Madison, Wisconsin for his technical support and encouragement. I am thankful to Prof. W.F. Long and Mr. H. Martensson for providing the opportunity for me to pursue my thesis at ASEA Power System Center, New Berlin for five months in 1985. This added a new dimension to my knowledge of HVDC. I am also grateful to them for allowing me to use the results obtained on the HVDC Simulator. I am grateful to my friend Sudhakar for providing many helpful criticisms and suggestions during my Ph.D. and to my friend Dinobandhu for his help during the last phase of my thesis writing. I am indebted to Dr. Jose Marti and Mrs. Mae Marti for their assistance in proofreading my thesis. I am thankful to my colleagues for making my stay at UBC memorable. The financial assistance of the Natural Sciences and Engineering Research Council of Canada and of the British Columbia Hydro and Power Authority is gratefully acknowledged. Last but not the least, to my teacher and supervisor, Prof. Hermann Dommel, who always helped me at the cost of his busy schedule, I offer nothing but an inadequate acknowledgement of my appreciation. Nomenclatures a firing angle 1 extinction angle u commutation angle ud dc bus voltage an ideal no load rectified dc voltage UdioN nominal E / d l 0 Overlap commutation angle, overlap angle peak value of the commutation voltage udt0 average value of Udi0 At time step Id dc current IdN rated dc current Al current margin XV Dedicated to Ski Ski kAMAKklSHMA PAkAMMAMSA Chapter 1 I N T R O D U C T I O N High Voltage Direct-Current (HVDC) power transmission systems have been in operation in many places all over the world, after the Gotland dc link (Sweden) went into operation in 1954 as the first commercial dc system. The first H V D C scheme used mercury arc valves. Schemes built after 1973 use thyristor technology. Traditionally, the economics of direct-current transmission have been based on break-even, distances beyond which overhead or submarine cable dc transmission becomes cheaper than ac transmission. Presently, there are many dc transmission schemes in North America and elsewhere that have been built because the power utilities, in examining different transmission strategies, have looked at other aspects as well, such as controllability, modulation for higher stability limits on parallel ac lines, and asynchronous power transfers between large power systems. An H V D C system also delivers more power for existing rights of way, and has lower radio and audible noise levels. An H V D C system has more major components than a comparable ac system. The primary H V D C components are the converter bridges, converter transformers, converter controls, ac and dc filters, and smoothing reactors. The design of H V D C systems requires the coordination of the performance characteristics of a large number of components. This coordination must be done in such a way that the overall system response will meet the technical specifi-cations of availability, reliability, and other factors during normal operation and during disturbances. To fulfill these objectives, a number of system studies are done. To carry out system studies, sophisticated tools are required. These tools 1 2 are HVDC simulators (i.e., hardware tools) and digital computer programs (i.e., software tools). HVDC simulators were used first, but digital computer programs are also used nowadays to complement the HVDC simulator. An HVDC simulator contains scaled-down models of transformers, converters, and 7r-circuit representations for transmission lines, as well as actual control cir-cuitry. Therefore, the studies can be performed in real time. The drawbacks of using a dc simulator are (i) narrow bandwidth of the frequency response and (ii) limited capability to represent ac/dc networks in detail. Various types of digital computer programs are used for system studies. Tran-sient stability programs are used to study the impact of dc links on the stability of an integrated ac/dc system. For fast transient disturbance studies, electromagnetic transients programs are used, such as the E M T P 1 . The converter model described in this thesis has been developed for the simulation of fast transients, and has been incorporated into the EMTP. The objectives of this thesis are: • to report on a new converter model for electromagnetic transients programs, that can represent series and parallel converter systems and that can also handle all possible converter transformer connections; • to describe a new approach for extinction angle control; • to simulate series and parallel converter systems under both steady-state and transient conditions and to analyze overvoltage problems; and • to develop an ac/dc initialization technique in the EMTP. 1The Electromagnetic Transients Program (EMTP) was originally written by Prof. H.W. Dom-mel in 1969 and later modified by many researchers. Chapter 2 C O N V E R T E R M O D E L S IN E L E C T R O M A G N E T I C TRANSIENTS P R O G R A M S 2.1 In t roduct ion A typical H V D C system consists of (i) a feeding ac network with its filters, (ii) a converter system with its valves, converter transformers, smoothing reactors, and converter controls, and (iii) a dc system with its dc transmission lines and dc filters. All the components of this system can be modelled in the Electromagnetic Transients Program (EMTP) , except for the valves, ln the past, the valves have been modelled indirectly as switches with the control system being simulated with the program TACS (Transient analysis of control systems [l]). This thesis discusses a new converter representation in the E M T P , which has the capability of modelling any transformer connection, and series and parallel connected converters. The formulation of the converter equations is achieved with Network Collapsing and Overlapping algorithms. Section 2.2 reviews the existing converter models. The new converter model, together with the solution algorithm, is described in Section 2.3. 2.2 Rev iew of Ex i s t i ng Conver ter Mode l s The major problem in the digital simulation of H V D C systems is the modelling of the converter. This problem is due to the time-varying topology that is caused by 3 4 the firing and extinction of the converter's valves. Hence, it is difficult to represent the converter in a simple way over a wide range of frequencies both for normal and abnormal operating conditions. At any instant of time, the number of conducting valves in a converter bridge may be two, three, or four. These conditions are referred to as two-, three-, and four-valve modes. For each of these modes, there exist six sets of possible valve conduction patterns, each limited to consecutive valve numbers. For example, for the two-valve mode, each set consists of one valve of the upper row and one valve of the lower row conducting (Figure 2.3). The transfer of current from one valve to another in the same row is called commutation. Since the ac source, with the converter transformer included, has an inductance, the current cannot change instantaneously. Therefore, a finite time is required for commutation. This time is known as commutation time or overlap time and is measured in electrical degrees called overlap angle. This angle is a function both of the ac source inductance and of the dc current. Under normal operating conditions, the overlap angle is less than 60°. In that case, three valves conduct si-multaneously during commutation, and two valves conduct between commutation. Abnormal operating conditions occur if the overlap angle becomes greater than 60°. When this occurs, the conduction pattern alternates between a three-valve mode and a four-valve mode. 2 . 2 . 1 C o n v e r t e r M o d e l s f o r D i g i t a l S i m u l a t i o n The simulation of the time-varying topology of the converter can be approached in two ways. The first method is based on tensor analysis. For a given conduction pattern of the converter, a matrix is constructed and then used to generate the con-verter state equations. Hingorani et al. [2] applied this approach on a two-terminal dc link. Later, Hay et al. [3] applied it to a multi-converter system. Williams et al. [4] formed the matrix by reducing the loop impedance matrix of the converter net-work, which is first built by assuming that all valves are conducting. Later, Vovus et al. [5] extended Williams's method to simulate a twelve-pulse, two-terminal H V D C system. Padiyar and Sachchidanand [6] used a graph-theoretical approach, 5 assuming the dc current to be continuous. This method provide less flexibility for network connections than the E M T P and the converter model described in the thesis. For example, the models of [2] to [6] would have to be changed to handle all types of transformer connections whereas the new model has no such limitations. The second method is based on defining and storing the sets of differentia] equations that describe the different modes of converter conduction patterns. De-pending on the conduction state, the appropriate set of equations is chosen and solved until the next change occurs [7,8,9,10,11]. El-Serafi [7] gave a set of five general equations describing the normal modes of converter operation. In [8], one set of equations is selected using Boolean algebra and is used from the instant a valve is fired to the firing of the next valve. Similar procedures are used in [10,11]. This method of predefined equations is suitable for normal modes of converter op-eration. Typically, for a three-phase bridge, up to 25 sets of equations are required for a full description of the converter system[9]. A detailed ac system representa-tion is difficult with this method because the set of predefined equations becomes prohibitively large. There are also limitations with respect to the transformer connections in [7,8,9,10,111. There is also an alternative approach whereby the converter is represented by a network with fixed topology but time-varying impedance[l2j. A conducting valve is represented as a branch with very low impedance and an open valve is a branch with very high impedance. This method, though simple, requires a very small integration step size to maintain numerical stability. 2.2.2 Converter Models in the E M T P The E M T P was originally developed for the simulation of electromagnetic tran-sients in ac networks. When the need arose to study overvoltages on the H V D C Pacific Intertie dc transmission line, the converter stations were modelled as simple current-controlled dc voltage sources [13,14]. The simulation results obtained with this simple model came reasonably close to field test results[l3,14]. The major drawback of this model, however, is its inability to simulate the transient behavior of the ac network which feeds the dc system. Its usefulness is therefore limited to 6 F i g u r e 2.1: C i r c u i t representation of valve by Woodford. overvoltage studies on the dc lines. l n a more detailed converter model, each valve is represented as a switch. T h i s r e p r e s e n t a t i o n has been used for detailed s i m u l a t i o n s of H V D C systems[lo,16,17]. C h i u 118] s i m u l a t e d the op e r a t i o n of the valves by m o d i f y i n g the diode s w i t c h i n U B C ; s E M T P so t h a t it conducts whenever the voltages across it is p o s i t i v e , p r o v i d e d a firing signal is present at the same time. T h e pro b l e m of numerical o s c i l l a t i o n s r e p o r t e d for the simple model [19] appeared here as well. A s i n [19], the i n c l u s i o n of the snubber c i r c u i t s (R-C branches across the valves) e l i m i n a t e d t h i s problem. W o o d f o r d et al . [20; also modelled the valve as a switch w-ith a p a r a l l e l snubber c i r c u i t i n a computer p r o g r a m E M T D C , w h i c h uses more or less the same algo-r i t h m as the E M T P . T h i s c i r c u i t is represented by an equivalent resistance w i t h a p a r a l l e l current source ( F i g u r e 2.1). T h i s source is as a result of the use of the i m p l i c i t t r a p e z o i d a l rule of in t e g r a t i o n on the R-C branch. W hen the sw i t c h is not c o n d u c t i n g , the equivalent resistor Rv is t h a t of an R-C branch (snubber c i r c u i t ) 7 [201: At Rv — Rd -\- 2Cd W h e n the switch is c o n d u c t i n g , a low value of 1 o h m is used for the resistance. T h e equivalent current source I(t — At) at t ime t is k n o w n f r o m the vol tages and cur rents at the preceding t ime step at (t — At). T o make the input of a converter m o d e l easier, W'oodford et. al cons idered a s ix -pu lse converter as one d a t a set. E a c h valve of the six-pulse converter is m o d -el led internal ly by the c ircui t of F i g u r e 2.1. In def ining the six-pulse conver ter , the conver ter t ransformer is represented as a del ta connect ion of c o m m u t a t i n g reac-tances , w i t h the vol tage sources derived f r o m the ac bus voltages. O n e l im i ta t ion of this representat ion is that not all the t ransformer connect ions can be s imu la ted . T h i s m e t h o d cannot be used direct ly to s imulate g r o u n d faults w i t h i n a s ix-pulse conver ter because its terminals may be at a potent ia l wh ich is different f r o m the g r o u n d potent ia l . 2.3 N e w C o n v e r t e r M o d e l T o s imula te the behav io r of a converter accurate ly , a converter m o d e l must be c a p a b l e of • represent ing the firing a n d ex t inc t ion of each valve , preferably i n c l u d i n g their t u r n - o n and turn-of f t imes; • represent ing b o t h n o r m a l and a b n o r m a l modes of operat ions; a n d • represent ing all possible converter t ransformer connect ions . T h e valve in a converter is usual ly represented by a single swi tch w i t h or w i th -out a para l le l R - C s n u b b e r c i rcu i t , a l t h o u g h in reality, a thyr is tor valve consists of a bank of thyr is tors connected in series a n d para l le l . T h i s s ingle-switch represen-t a t i o n is accurate e n o u g h , unless details of uneven internal vol tage d is t r ibut ions have to be s tud ied . T h e p r i m a r y task of the snubber c i rcu i t is to reduce the vol tage osci l lat ions a n d the steepness of the vol tage rise across the offgoing valve. It also improves 8 transient voltage distribution among series-connected thyristors and among two and more series-connected bridges. The voltage oscillations across the offgoing valve are caused by the interaction between the stray capacitance across the valve and the transformer inductance. Spurious voltage oscillations have been observed across an inductor when the current through the inductor changes abruptly during the E M T P network simula-tion [21,22,23]. These voltage oscillations are caused when the implicit trapezoidal rule, which the E M T P uses for integration, is used for numerical differentiation [21,22,23]. Section A.1 of Appendix A explains the application of the implicit trapezoidal rule as a numerical integrator and differentiator. It has been stated earlier in Section 2.2.2 that to eliminate the spurious voltage oscillations an additional R-C branch across a valve is used. An elegant way to solve this problem would be to eliminate the nodes that create such oscillations from the system of equations. The new converter model adopts this method. It eliminates the nodes (later termed as internal nodes) from the converter equations where the voltage oscillations occur, before it solves for the ac and dc bus currents. Figures 4.3 to 4.5 show that the spurious voltage oscillations are not present. These voltage waveforms of the converter and the valve are simulated using the new model. 2.3.1 Transformer Model In the derivation of the transformer model, the effects of stray capacitances and of saturation are first ignored. Stray capacitances need only be considered for frequencies above 2 to 5 kHz, which is above the frequency range of transients discussed in this thesis. Saturation effects are discussed later in this section. Two approaches for modelling transformers are considered here: the admittance matrix and the impedance matrix approach. Only single-phase transformers are discussed here, since converter transformer banks usually consist of single trans-former units. The methods can be extended to three-phase transformers [24]. A single-phase two-winding transformer (Figure 2.2) can be represented as two inductively coupled branches having a branch impedance matrix Zbranch = Branch + 9 11-2 13-4 V i - 2 V 3 - 4 Figure 2.2: A single-phase two-winding transformer. julibranch- For transient condition, the transformer branch equations are ~Vbranch — [ R f c r a n e h " f" ^branch^branch• at (2.1) The branch impedance matrix Z b r a n c n becomes infinite if the exciting current of the transformer is ignored [24], but its inverse, Ybranch = [ R 6 r a n c h + i w L i r o n c h ] _ 1 , still exists. By ignoring the resistance of the transformer, equation (2.1) can then be rewritten as (2.2) dt If the short-circuit inductance of the transformer as seen from the side 1-2 (Fig-ure 2.2) is L and the transformer turns ratio is t, then the L ^ n c h - m a t r i x of the transformer is T _ 1 ^branch ( 1 V T I J By expressing the branch voltages as the difference of the node voltages vx — and t>3 — v4, and by introducing node currents i] = —12 = i i _ 2 and i 3 = —14 = 13-4, the branch equations (2.2) are transformed into the following node equations: dt ( l -1 -t t \ L L L L *2 -1 1 i -t — L L L L H -t t t2 -1-L L L L t -t t 2 J V L L L L \v4J 10 The above matrix is singular because the exciting current (or magnetizing admit-tance) is ignored. The basic approach for the single-phase two-winding transformer is extended to the three-phase converter transformer banks in Section A.2 of Appendix A. The principle used for modelling single-phase two-winding transformers can be applied to single-phase three-winding transformers as well[24]. The extended delta type of converter transformer, which has recently been proposed, is just a special case of a three-winding transformer. The saturation effect of a transformer is modelled using two-slope piecewise linear inductance. This saturation model is reasonably accurate [24]. Generally, the inductance of the saturated region is twice the short-circuit inductance of a transformer and the inductance of the unsaturated region is typically 400 times the inductance of the saturated region. The location of the connection for a piecewise linear inductance branch a transformer model affects the simulation results. For a two-winding transformer, the best simulation result is obtained if this branch is connected across the winding which is closest to the core of the transformer [24]. In this transformer model, the piecewise linear inductance branch is connected across the primary winding of the transformer because the E M T P can be used to model this branch. 2.3.2 Converter Mode l Figure 2.3 shows a three-phase transformer bank feeding a six-pulse bridge. The valves of the six-pulse bridge are modelled as ideal switches (that is, when the valve is conducting, the voltage across it is zero, and when it is not conducting, the current through it is zero). For simplicity, transformer winding resistances are ignored in this discussion. The transformer is then described by an open-bridge L _ 1 matrix for nodes A, B, C, a, b, c, with the assumption that all valves are not conducting. The derivation of this open-bridge L _ 1 matrix is discussed in Section A.2 of Appendix A. . For example, the open bridge L~Matrix of the system (Figure 2.3) is shown Transformer •A 3 i s i DC Bus 4 ? • Converter (N) Negative Figure 2.3: A single-bridge system. 12 below: P n a b c ne A B C Ne p 'o 0 0 0 0 0 0 0 0 o" n 0 0 0 0 0 0 0 0 0 0 a 0 0 l L 0 0 - l L - l L 0 0 1 L b 0 0 0 1 L 0 - 1 I 0 I L 0 1 L ne 0 0 - ] L - ] L - i L O ».> L 1 I 1 L 1 L -3 L A 0 0 - 1 L 0 0 ] 1 1 z. 0 0 -1 L B 0 0 0 ] L 0 1 L 0 ] z. 0 - 1 I C 0 0 0 0 - 1 L 1 L 0 0 - ] L - 1 L Ne 1° 0 1 L 1 L 1 L -3 L -] L - l L - 1 L 3 L J where ne and JVe are the nodes of the neutrals on the valve and ac sides, respec-tively. Here the wye-wye transformer connection is considered. It is assumed that the short-circuit inductance L for all the phases of the transformer are equal and the turns ratio is unity. Since the converter topology varies with time, the open-bridge L_1matrix must be modified to form a converter L _ 1 matrix for nodes A, B, C, p, and n that describes the network with the proper converter topology at a given time. To form the converter L-1matrix, the Network Collapsing algorithm of [25], which is simple and straightforward, is used. To explain this algorithm, assume that valves 1 and 2 are conducting: that is, the switches representing valves 1 and 2 are closed. Node a, then 1, merges (becomes identical) with node p, and node c merges with node n. The converter L _ 1 matrix is therefore formed by the following operations: • In the open-bridge matrix, the rows and the columns corresponding to nodes a and c are added to the rows and the columns corresponding to nodes p and n, respectively; • The rows and the columns corresponding to nodes a and c are then deleted. The converter L - 1 matrix for this example, with a wye-wye connection of three 13 single phase units, would be P n b ne A B C Ne p n b ne A B C TVe 1 L 0 0 - l L - 1 L 0 0 l L 0 I L 0 - i L 0 0 1 1 L 0 0 1 L - 1 L 0 I L 0 1 L - 1 - 1 - 1 3 1 1 1 -3 L L L L L Z. L L - 1 0 0 1 1 0 1 - 1 L L i I L 0 1 L 0 1 L 0 ] L 0 - 1 L 0 0 - 1 L 1 L 0 0 - 1 L - 1 L 1 1 1 -3 - 1 - 1 - 1 3 L L L L L L I L It should be noted that the converter L Matrix changes as a function of time with the change in the converter conduction pattern. 2.3.3 Series Connection of Bridges Generally, a dc bus (pole) is created by two or three six-pulse bridges in series. The pole L _ 1 matrix, which describes the series connection of converters, is formed from the individual converter L_1matrices and from the smoothing reactor L _ 1 matrix using the Network Overlapping algorithm of [25]. The L~'matrix of the smoothing reactor is where Ld is the inductance of the smoothing reactor. To illustrate the procedure of network overlapping, consider three six-pulse bridges in series (Figure 2.4). Each six-pulse bridge has two terminal nodes p and n, where the voltage in node p is positive with respect to the node voltage in n. Figure 2.4 shows that node p of converter 1 is one end of the smoothing reactor. Node n of converter 1 and node p of converter 2 merge to form a new node Pi. Similarly, node P2 is formed by merging nodes n and p of converters 2 and 3, respectively. Node n of converter 3 is renamed as the negative node N. The system matrix for nodes D, Pi, P2, and Nand for the nodes on the ac side is formed by the following operations: 14 Figure 2 . 4 : A series converter system. 15 • Rename the nodes of the converter L~ 1 matr ices and the smoothing reactor L _ 1 - m a t r i x , start ing from the converter connected to the smoothing reactor; that is, for converter 1 rename node p as P and node n as Pi. • A d d the rows and the columns of the nodes of all the converter and smoothing reactor L - 1 m a t r i c e s bearing the same node name. (2.3) The resultant matr ix is the pole L 1 matrix of the converter system. A pole L _ 1 m a t r i x of a single-bridge system is basically the same as the con-verter L _ 1 m a t r i x except that nodes p and n are renamed as nodes P and A r, and a smoothing reactor has been added. The pole L _ 1 m a t r i x of the system of Figure 2.3 is shown below for the case where valves 1 and 2 are conducting. D 0 0 0 0 0 0 0 J_ Li J Representation of a twelve-pulse converter is a special case of the series connec-t ion discussed above. A twelve-pulse converter consists of two six-pulse converters in series, with a 30° phase shift in their ac sources. Th is shift is achieved by feeding one converter through a wye-wye transformer and the other through a delta-wye or a wye-delta transformer. As there is no l imitat ion with respect to transformer connections in the formation of the open-bridge L _ 1 m a t r i x of a six-pulse converter, the representation of a twelve-pulse converter is automatical ly covered. The representation of a series converter system for the positive pole has been discussed. The representation of the series converter system for the negative pole is analogous. Bipolar H V D C systems can therefore be simulated as well . p b ne N A B c iVe p fx L + A 0 - l L 0 - 1 L 0 0 I L b 0 1 L - l L 0 0 I L 0 1 L ne L - 1 L 3 L -1 L ] L 1 L 1 L -3 L N 0 0 - 1 L 1 L 0 0 - 1 L 1 L A - 1 L 0 1 L 0 1 L 0 1 L - 1 L B 0 0 1 L 0 0 1 L 0 -] L C 0 - 1 L 1 L - 1 L 0 0 - 1 L - 1 L Ne 1 L 1 L -3 L 1 L - 1 L - 1 L - 1 L 3 L D V - 1 hi 0 0 0 0 0 0 0 16 2 . 3 . 4 S o l u t i o n A l g o r i t h m a n d I n t e r f a c e w i t h t h e E M T P Before describing the solution algorithm and the interface with the E M T P , it is necessary to identify the input quantities and the desired output quantities. The inputs are the bus voltages on the primary side of the transformers feeding the six-pulse bridges and the dc bus voltages. The output quantities consist of dc bus currents, ac phase currents, voltages across the valves, and the voltages across the six-pulse converters. The external nodes are the dc buses and the ac buses on the primary side of the transformers. All the remaining nodes are termed as internal nodes. When the pole IT 'matrix of the system is set up, the internal and the external nodes are arranged sequentially. For example, the nodes N, D, A, B, C, and Ne are the external nodes and the nodes P, 6, and ne are the internal nodes of the matrix shown in the expression (2.3). The partitioned pole L _ 1 matrix of the system then has the form shown below. Internal / P P A External y~PE] P E E The spurious voltage oscillations (Section 2.3) occur at the node, which is connected to the transformer secondary nodes, of an outgoing valve [18]. This is because sudden changes in the current through an inductor introduce spurious voltage oscillations in the trapezoidal method of network simulation (refer to Section A.1 of Appendix A). Furthermore, turning on and turning off the thyristor valves cause sudden jumps (these jumps are different from spurious oscillations) at the node voltages of all the internal nodes of the system. For example, when the valves 1 and 2 are conducting (refer to Figure 2.3) node b follows the instantaneous value of the phase B voltage et,. When valve 3 is switched on, a jump in the node b voltage is observed. The node b voltage jumps from et, to -ec/2, where ec is the instantaneous value of the phase C voltage. Therefore, the solution algorithm has to be chosen so that the spurious voltage oscillations across an outgoing valve are not present and the sudden jumps in the internal node voltages do not affect the solution of the system of equations. 17 The converter equations are formulated so that the current injections into the internal nodes are known to be zero. Therefore, the unknown quantities in the system of equations are the internal and the external node voltages and the current injections in the external nodes. As the internal node currents are zero and the internal node voltages have sudden jumps, these nodes are eliminated from the system of equations. The Gauss Elimination method is employed for eliminating the internal nodes. The reduced system matrix is shown below. Internal External V o ( P « ) ; where the submatrix P } ; is an upper triangular matrix and the other submatrices are full matrices. The reduced system of equations in matrix form is given by jlE = PEEVE, (2.4) where V# is the vector containing the voltages of the external nodes; I E is the vector containing the currents of the external nodes; P E £ is the reduced system matrix. To solve equation (2.4), the implicit trapezoidal rule of integration 1 is employed. Applying the trapezoidal rule to equation (2.4), equation (2.5) is obtained I £ ( n ) - I £ ( n - 1 ) V s ( n ) s + V £ ( n - 1 ) , , At E E 2 ' where the subscript E denotes the external nodes and the letter n in parenthesis denotes the time step. The equation (2.5) has to be solved simultaneously with the EMTP-Converter interface equation, which will be discussed now. The converter equation in (2.5) can be rewritten as rEEVE(n) = lE{n) - UE(n - 1), (2.6) 1 There are many different methods for the numerical solution of differential equations. For general-purpose programs, the trapezoidal rule has become the preferred method, for a variety of reasons, both in power system analysis[26j and the analysis of integrated circuits(e.g., with SPICE[27]). 18 where HE{TI— 1) is a vector of history terms. The system of equations of the EMTP can be written as GV(n) = I(n) - H(n - 1), (2.7) where G is the nodal admittance matrix, V(n) is the node voltage vector at nth time step, I(n) is the node current vector at nth time step, and H(n— l) is a vector of history terms. There are two approaches for interfacing equations (2.6) and (2.7). ln the first approach, the nodal admittance matrix G is updated with PREE using the network overlapping algorithm. The right-hand side of equation (2.7) is also modified with H#(n — 1). For example, if the nodes 7 to 9 are the ac nodes and nodes 1 and 2 are the dc nodes, then for a single converter with grounded neutral in the primary side, the interface equation is GmV(n) = lm{n) where G m = 1 01,1 + P6,6 01,2 + P6,5 02,1 + P5,6 02,2 + P5,5 07,1 + Pl,6 07,2 + Pl,5 08,1 + P2,6 08,2 + P2,5 09,1 + P3,6 09,2 + P3,5 n V 0n,l and 0n,2 V(n) 7 8 9 01,7 + P6,l 01,8 + P6,2 01,9 + P6,3 02,7 + P5,l 02,8 + P5,2 02,9 + P5,3 07,7 + Pl,l 07,8 + Pl,2 07,9 + Pi,3 08,7 + P2,l 08,8 + P2,2 08,9 + P2.3 09,7 + P3,l 09,8 + P3,2 09,9 + P3,3 0n,7 V$ \vnJ 0n,8 (hl + h\\ h* + h* h7 + K h*-rh* h9 + h9e \ hn J 0n,9 n 01, n 02, n 07, n 08, * 09, n 9n,n) 19 Nodes connected to HVDC systems Figure 2.5: Reallocation of converter nodes in G matrix. where fffJ- is an element of the matrix G , is an element of the matrix P ^ , h\ is an element of the vector H/j;(n — 1), and h% is an element of the vector H ( n — 1). The problem with this formulation is that the updated matrix Gm has to be retriangularized each time PEE changes. The process of retriangularization of the whole updated matrix involves immense of computational effort. To minimize this effort the following procedure can be adopted: • relocate the nodes associated with the converters to the bottom of G matrix; • retriangularize G matrix as shown in Figure 2.5; • any change in PrEE would involve modifications in the submatrix Gcnv (Fig-ure 2.5) and triangularization of this submatrix. This approach is efficient and is thus suitable for a production-type of program. The second approach is simple and requires rrunimum programming effort. There-fore, the second approach is used in this thesis and it is described in the following paragraphs. The block diagram in Figure 2.6 shows the converter interface with the E M T P . In the E M T P , the effects of a converter are represented by a three-phase instan-taneous current source on the ac nodes and by instantaneous dc current sources 20 on the dc nodes of the network. In the converter subroutine, the ac/dc network is represented by a Thevenin equivalent circuit equation V £ (n) denotes the instantaneous voltage of the Thevenin equivalent circuit at the nth time step; IjE(n) denotes the current out of the Thevenin equivalent circuit at the nth time step (computed in the converter subroutine and passed back to the EMTP); E£(n) denotes the open-circuit voltage of the Thevenin equivalent circuit at the nth time step; R.E denotes the Thevenin equivalent circuit resistance matrix. Equation (2.8) is obtained by solving the network in the EMTP with the implicit trapezoidal method and by reducing the resulting system of nodal equations to the external nodes [24]. Substituting equation (2.8) into equation (2.5) produces the expression of VE{n) = E £ (n) - RElE{n) (2.8) where I£(n) = D- 1 G r [E £ ; (n) + V £(n)] + Hist, (2.9) where D = U + G r R £ G r = EE Hist = D " I I £ ( n - l ) At — step size U is the identity matrix At every time step, IE is solved from equation (2.9) and is computed from equation (2.8). The current l E ( n ) is returned to the EMTP, which finds the final solution for the network at the time step n by superimposing the currents I^. 21 Once the external node quantities are known, the voltages of the internal nodes are easily computed using backsubstitution. The internal node voltages come out with proper jumps and without any spurious oscillation (refer to Figures 4.3 to 4.5). This is because the voltages on the internal nodes are found from an alge-braic relationship between the internal and the external nodes rather than from differentiation. Details are given in Section A.3 of Appendix A. Knowing the internal node voltages, the branch voltages such as the voltages across the six-pulse bridges and the voltages across the non-conducting valves, can then be computed. The phase currents of each transformer are recovered from the branch equation of the transformers. Using the secondary phase currents of the transformers and the external node currents, the currents through the conducting valves can be found. 2.3.5 Parallel Converter Representation Figure 2.7 shows a parallel converter configuration. It is assumed that each parallel arm has its own smoothing reactor, though in practice, this may not always be true. Both arms are fed from the same ac and dc buses. Parallel converter modelling is an extension of series connected bridges (Sec-tion 2.3.3). The algorithm described in Sections 2.3.3 and 2.3.4 can be used to formulate the reduced system of equations for each arm of a parallel converter con-figuration. For the system shown in Figure 2.7, the reduced system of equations for the arm 1 is where PEE a r j d PREE a r e ^ n e reduced system matrices for the arms 1 and 2, re-spectively. 1^  and I\ are the currents in the external nodes for the arms 1 and 2, respectively. Combining equations (2.10) and (2.11), the system of equations (2.12) for the parallel converter configuration shown in Figure 2.7 can be found: (2.10) and for the arm 2 is (2.11) G C V (2.12) where 22 I* = I* I2 T>r2 * EE Since equations (2.12) and (2.4) are similar in nature, the solution of the equation (2.12) can be obtained using the algorithm presented in Section 2.3.4. 23 Electromagnetic Transients Program AC and DC Bus Voltages AC and DC Bus C u r r e n t s Converter Subroutines Figure 2.6: Block diagram of the interface between the converter model and the E M T P . 24 DC B u s Second Arm Figure 2.7: A parallel converter system. Chapter 3 H V D C C O N T R O L R E P R E S E N T A T I O N In this chapter the HVDC control system is discussed. The HVDC control systems vary widely in design and in implementation, but the basic control philosophy is more or less the same. An HVDC control system consists of rectifier and inverter controls which are usually identical, but work at different operating points. Be-tween these two controls, the inverter control is more critical than the rectifier control. The behaviour of the control system must be included in the simulation of HVDC transients. It is impossible to include all the details of a real control system in a digital simulation. What is needed is a generic model that adequately describes the influence of the control system on the transients in the dc and ac networks. Such a generic model is described here. 3.1 Hierarchy in H V D C Control Systems The major advantage of HVDC systems is the controllability of the power being transmitted. The control of power is achieved by organizing the entire control system under various levels of control hierarchy, with different control functions at each level. The lowest level of control is the valve control. The purpose of this control is to gate the individual thyristors of a valve when a triggering pulse from the converter firing control is received. Since the valve is represented by a switch in the model, this level of control need not be modelled. The next level of control is the converter firing control (CFC). The CFC deter-25 26 U d Rectifier a-b: Min. Alpha Characteristic b-c: Const. Current Characteristic a Current Margin Id Inverter 1-2: Min. Alpha Characteristic 2- 3: Const. Current Characteristic 3- 4: Positive Slope Characteristic 4 - 5: Const. Gamma Characteristic Figure 3.1: Two-terminal H V D C control characteristics without the influence of a voltage-dependent current order limiter [29,30]. mines the instant of firing and the sequential valve firing order in a six or a twelve pulse converter. The input to the C F C block is the alpha order. This informa-tion is supplied by the next higher level of control, the pole control system. The philosophy behind C F C is explained in Section 3.2. The pole control system consists of a current control and a commutation margin control. Each pole of an H V D C station is equipped with a pole control system. The output of the pole control is the alpha order. The primary inputs to the pole control system are current order, current response (dc link current), and various voltages from the ac and dc side. 27 Normally, in a two-terminal system, the rectifier controls the current and the inverter controls the voltage of the system. The two-terminal operating characteris-tics for the rectifier and inverter are shown in Figure 3.1. The inverter characteristic (shown in dotted lines in Figure 3.1) is similar to that of the rectifier. The basic in-verter characteristic (vertical and almost horizontal lines) is modified in two ways. First, the minimum alpha is limited to 105°. This restriction prevents the inverter from feeding a dc line fault and also protects against sudden power reversals during transients. Second, a positive slope is introduced (from point 3-4) in order to • ensure that the inverter characteristic always intersects the rectifier charac-teristic. • give a smoother transition from the commutation margin control to the cur-rent control, and • enhance the overall stability of the current control system. The converter firing control system is described first. The current control loop and the commutation margin control loop are described next. 3.2 Converter Firing Control (CFC) There are various ways of implementing converter firing controls, but they can all be classified under two concepts: the individual phase control and the equidistant pulse control. The individual phase control system was the first control scheme to be used in H V D C transmission. The scheme is well-documented [31,32,33]. An advantage of the individual phase control is its capability to transmit more power than equidistant pulse control during unsymmetrical fault conditions. A drawback of this scheme, however, is its inherent instability problem in connection with high impedance (low short circuit ratio) ac networks. This instability is caused by the voltage feedback loop from the converter ac bus voltage. One way of avoiding the instability due to the voltage feedback loop is to use a voltage-controlled pulse oscillator. The frequency of this oscillator is determined from the control error. When the control error is zero, the frequency is equal to 28 6f or 12f, depending on whether the operation is six- or a twelve-pulse, with / being the nominal frequency of the ac network. This control scheme is commonly known as the equidistant pulse control because the firing pulses are equispaced if the control error is zero. Various control strategies have been proposed based on this concept [31,34,35,36]. The control system described here is based on [34], with a few modifications. The converter firing control scheme has three tasks. Its first task is to compute delta alpha (alpha order minus measured alpha) and its limits. Second, it must measure the last firing angle. Its third task is to generate the firing pulses for the valves. Both the current control and the commutation margin control loops output an alpha order; the minimum of the two is then chosen as the actual alpha order. This is fed as an input to the converter firing control block. The difference between alpha order and measured alpha is delta alpha. Delta alpha is passed through a limiter block, whose limits are continuously computed in a way that depends on the measured alpha and the operative mode (i.e. the rectifier or the inverter mode). The block diagram in Figure 3.2 shows the converter firing control scheme. The constant slope ramp function is generated, starting from zero at each firing instant. The ramp function is compared with the control signal, which is the sum of the delta alpha signal (i.e., change in firing angle) and the bias signal. The pulse TRIGG is initiated at the instant of equality. The bias signal is equal to T/6 in the case of a six-pulse operation and T/12 in the case of a twelve-pulse operation, where T is the time period of the ac voltage. If the delta alpha signal is zero, which corresponds to a steady - state operation, the firing pulses will be generated at every 60° for a six-pulse operation and 30° for a twelve-pulse operation. The pulse TRIGG is logically anded with the pulse TRIGV to produce the firing pulse TRIGF. The pulse TRIGV is high if the voltage across the valve is greater than or equal to a threshold voltage. The firing pulse TRIGF is fed to the ring counter logic, which selects the proper six-pulse units and the valve. Emergency Constant Alpha Order TRIGV AND Ring Counter TRIGF Valves T is Time Period of AC System x= 6 for 6 pulse converter x = 12 for 12 pulse converter Figure 3.2: Block diagram of converter firing control. to 30 3.2.1 A l p h a M i n i m u m Fir ing If the ac bus voltage of the converter decreases, the firing angle (alpha) decreases to maintain a constant dc link current. Theoretically, this process of decreasing the firing angle can only go on until the firing angle becomes zero. In practice, the firing angle must be larger than zero because the voltage across a valve must reach a certain value to ensure successful firing. To obtain this in the control system, the firing pulse is delayed until the voltage across the valve to be fired reaches a threshold level. This mode of operation is known as alpha minimum firing. The alpha minimum firing is not equidistant if the ac system is unsymmetric. Therefore, to make the alpha minimum firing equidistant, a special function needs to be incorporated. This function is known as the symmetrizer. If any one valve undergoes alpha minimum firing, then the symmetrizer forces the next eleven valves (or five for six-pulse converters) to fire with 30° intervals. The symmetrizer is disabled if an increase in firing angle is required. 3.2.2 Commutat ion Marg in Control L imiter This function operates only in the inverter mode. The principle behind this function is as follows. Let the firing angle ordered by the commutation margin controller at time tx be a\. If, due to any reason, at time t2 [t2 > ti), the commutation margin controller orders a firing angle a2 (ct2 < at), then this function forces the next eleven valves to be fired with the firing angle a2. This process is known as symmetrizing. When an inverter is undergoing symmetrizing, any firing angle greater than the current firing angle (i.e., a2) is ignored. Any firing angle less than a2 resets the function, and the valve is then fired with the lower firing angle. 3.2.3 Emergency Triggering The emergency triggering function unconditionally makes the pulse T R I G F high. This function is used when the normal triggering condition is not fulfilled. The normal triggering pulse is issued if • the pulse T R I G G is present and 31 • the pulse T R I G V is present. The condition for issuing the emergency trigger is: RAMP function > Control Signal -f Emergency Constant . The value of Emergency Constant depends on the connected ac system. 3.3 Current Control Loop The current control loop consists of a voltage-dependent current order limiter (VD-COL) and current control amplifier. Figure 3.3 shows the block diagram of the current control loop. 3.3.1 Voltage-Dependent Current Order Limiter ( V D C O L ) The purpose of a V D C O L is to limit the current order to lie between a minimum current limit and a voltage-dependent maximum current limit. The maximum current limit must not exceed the absolute maximum. The voltage-dependent maximum current limit decreases as the dc voltage decreases. Figure 3.4 shows the V D C O L characteristic. A complete two-terminal H V D C characteristic shown in Figure 3.5 is obtained by combining the V D C O L and the modified two-terminal H V D C characteristic. The detailed block diagram of the V D C O L is shown in Figure 3.6. The dc bus voltage £/ d is one of the two inputs to V D C O L . Ud is filtered through two filter circuits having different time constants [37]. The filter with the smaller time constant (also known as down time constant Tdn) is needed when the dc voltage is decreasing. The other filter, with the larger time constant (also known as up time constant Tup), is in series with the previous filter and is needed when the dc voltage is increasing. The filter with the small down time constant allows a quick reduction of current order during faults in the ac system. The filter with the large up time constant ensures that the dc voltage is restored before the rated dc current is ordered. Current Control Loop > dio Gamma Order Selector 180 101 Delta Gamma Increase Commutation Margin Control Loop Id Minimum Alpha Alpha Order Overlap Figure 3.3: Block diagram of current and commutation margin controller. CO to Io Maximum Current Order J Minimum Current Order I 1 1 - U d U db U dN Kb = 1/Udb Udb = B r e a k - i n dc Voltage UdN = Nominal dc voltage Figure 3.4: Characteristic of voltage-dependent current order limiter[29j. Rectifier Figure 3.5: Two-terminal H V D C characteristic with VDCOL[29j. Io Minimum Selector Zero Crossing Detector Figure 3.6: Block diagram of voltage-dependent current order limiter. 35 Reference [37] mentions that two filters with different time constants are re-quired in the V D C O L , but does not mention how the filter with the larger time constant is switched in or switched out of the V D C O L circuit. Therefore, to per-form the switching operation, an auxiliary circuit is used. The block diagram in Figure 3.6 is briefly described in the following paragraphs. The dc voltage is continuously filtered through a filter with a small time con-stant. Following this, the auxiliary circuit continuously monitors the rate of change of the dc voltage and issues a control signal if the dc voltage is increasing. This control signal then switches in the second filter circuit with a large time constant, which stays in as long as the signal is present. The second input to V D C O L is the steady-state current order. Depending on the filtered dc voltage, a changed current order is calculated from the equation Ioc = 10 * Udf * Kb , (3.1) where Ioc is the changed current order, I0 is the steady-state current order, Udf is the filtered dc voltage, and Kb is the dc voltage break-in factor (see Figure 3.4). The output of V D C O L is the modified current order J o 1 , which is the minimum of either the changed current order Ioc or the steady-state current order 10. This modified current order becomes the reference signal of the current controller. 3.3.2 Current Control Amplifier A proportional-integral type of controller is generally used for current control. Figure 3.7 shows the block diagram of a commonly used current controller. There are three inputs to the current controller: the modified current order I0i, the current margin Al. and the dc link current Jd. The current margin signal is not present in the rectifier current controller. In the case of an inverter, the current margin signal is added to the error input signal of the integral part of the controller. The output of the current controller is an alpha order. 36 Id K 1 + ST; r sTz J Alpha Order Current Margin Figure 3.7: Block diagram of the current control amplifier. The transfer function of the proportional part is of the form GJs) = — without limits. The transfer function of the integral part is of the form K Gt(s) = (3.2) (3.3) with a non-windup limiter (38]. In normal inverter operation, the output of the proportional part is zero because its input is zero. The integrator output is then at its upper limit because its error is non-zero. The current margin added to the error input of the integrator makes the current controller inoperative in normal operation. The non-windup limiter on the integral part allows the output to leave its limit as soon as the derivative of the input changes sign. The windup limiter [38] on the alpha order is used to implement minimum and maximum alpha limits on the rectifier and the inverter. The minimum alpha limit for a rectifier is typically 5° and for an inverter, typically 105°. The maximum alpha limit for both rectifier and inverter is typically 160°. 37 3.4 Commutation Margin Control Loop 3.4.1 Review For an inverter operation, it is desirable to operate with a firing angle a as close to 180° as possible in order to reduce reactive power consumption. In practice, the firing angle a is limited in the range of 140° to 165°. This limit ensures that a valve gets adequate deionization time, with an additional safety margin to prevent commutation failure for minor ac system transients. The deionization time with its safety margin, in electrical degrees, is the extinction angle 7. A typical value of the minimum extinction angle is 17°. The relation between the firing angle a and the extinction angle 7 is given by where u is the commutation angle. Thus, the purpose of the commutation margin is to operate the inverter with as high a firing angle as possible, while saving the inverter from commutation failures during minor ac system disturbances. This control function is achieved in one of two ways, either by using a predictive type of control [33,34] or by using a gamma feedback control]35,36]. Each of these control approaches has its advantages and disadvantages. The predictive control is less prone to commutation failures but causes harmonic instabilities [35]. The gamma feedback control, with equidistant firing control [35,36], is theoretically prone to commutation failure but is claimed to be free from harmonic instability. Both are briefly discussed next. The predictive type of control as proposed by Hingorani [33] is based on the integration of the commutation voltage waveform of each valve. This control prin-ciple is based on the equation a = 180° - (7 + u) , (3.4) J (3.5) where is the commutation voltage for the valve j, is the commutating reactance, and is the dc link current. 38 t 1 t 2 t 3 Figure 3.8: Commutation voltage waveform of a valve. The valve is fired as soon as J > 0. Ekstrom and Liss[34j approached the predictive type of commutation margin control in a slightly different way. Figure 3.8 shows the commutation voltage waveform of a valve to be fired. The three areas marked in the figure are the total commutation voltage time area A(t), the overlap area Aj, and the commutation margin area Am. Area A(t) is continuously computed using triangular approxima-tion. The area Aj is set to be proportional to the dc link current. The predicted area Ap(t) is then computed as Ap(t) = A(t) - A, . (3.6) Ap(t) is the commutation voltage-time area margin if firing should occur at the arbitrary time t. Ap(t) is compared with a reference value Amref, which is propor-tional to the extinction angle. The valve is fired when Ap(t) is less than or equal to Amref. The above prediction process has an error of AA = Ap - Am , (3.7) 39 where Ap is the value at the instant of firing. This error is added to Amrej as a correction for subsequent firings. This predictive firing scheme works in conjunction with the equidistant converter firing control. The method of gamma feedback control [35,36] uses a sampled time measure-ment of 7. The 7-measuring circuit measures 7 of each valve. The measured 7 is fed back and compared with a reference 7 to generate an error signal. This error signal is used to correct the firing angle for subsequent valve firings. 3.4.2 A New Generic Model The full details of inverter control schemes in operation are not released by the manufacturers, due to competition. Hence, it is necessary to develop a generic control scheme for digital simulation purposes. The generic model described here includes all the basic principles of inverter controls and has the modified inverter characteristic of Figure 3.1, as discussed in the following paragraphs. The commutation margin control loop is shown in Figure 3.3. The gamma order is strictly defined by the minimum extinction angle required for a valve for a certain value of an ideal no load rectified dc voltage(t/(i,0). The inverter control described here is a pseudo-open-loop control. It is simple and said to be pseudo-open-loop because gamma is not measured directly and the error in gamma is not processed through a controller. Instead, gamma is found indirectly from a curve of C'dio versus gamma. The alpha order, which is the output of the commutation margin loop, is computed using the following expression Alpha Order = 180° - (Gamma Order) - (Overlap) - (A7). 1 (3.8) The gamma order calculation, the overlap calculation, and the A7 increase are described next. G a m m a Order Calculation If a valve is fired at time fj, and if at time t2 the current through the commutating valve goes to zero, then the time (t2 - <i) is the overlap period (refer to Figure 3.8). 1A~i achieves the positive slope of the inverter characteristic. 40 The comrnutating valve must turn off within the time (t3 — t2) if there must not be a commutation failure. The time (t3 -1 2 ) in electrical degrees is the extinction angle 7 . Let K\ be the minimal instantaneous value of the commutation voltage at the end of the overlap period for a successful commutation. A relationship between the extinction angle and the peak value Em of the commutation voltage can be found by assuming that the instantaneous voltage is constant (and equal to K\) at the end of the commutation period, with Ki = £ m s i n 7 . (3.9) It is difficult to determine accurately the peak value of the commutation voltage, especially if it contains harmonics. The problem can be resolved by rewriting equation (3.9) in terms of l/J10(average value of Ua0). The relationship between Udioa.nd Em for a six-pulse converter is E*> = i T f • <310> Thus, the relationship between t/^and the extinction angle 7 is obtained by sub-stituting equation (3.10) into equation (3.9), 7 = sin"V , (3.11) where 3*r l v/3 <p = —777- , and 0.25 < 4> < 1. This imposed limitation on <f> ensures that gamma order lies between 15° and 90°. The constant K\ in the above expression is computed with the nominal values of U,n0 and of 7 for normal operation. The determination of the gamma order depends on the measurement of Ud,0 ,which is obtained by rectifying the three-phase ac bus voltages through a six- or twelve-pulse bridge rectifier with diodes. Udl0 will then contain harmonic ripples of order 6n or 12n, with n=l,2,3... In order to get a steady gamma, the ripples are filtered out by computing the average value of Udio over k samples V«0[k) = l E ^ ( 0 , (3-12) K 1=1 41 where Udio(k) and Udi0(i) are the average and the instantaneous values of Udto, respectively. The equation (3.12) can be rewritten in a recursive form as [39] U«0(k) = U^ik - 1) + l\Udl0(k) - Udl0(k - 1)] . (3.13) In equation (3.13), as k increases, the influence of the most recent instantaneous values of Udio on the average value diminishes. The term (l//c) in equation (3.13) can be considered as a diminishing gain. A more general gain can be used if equation (3.13) is replaced by U d M = U;t0(k - 1) + G(k)[Udl0(k) - V'd%0(k - l)j , (3.14) where G(k) is the gain defined by ^ = 1 ^ 0 7 ) ' <315» and wrhere X (0 < A < l) is known as a forgetting factor. The gain G(k) tends to zero when the average value of Udio(k) converges to the true average value. The average value of Udio will change during ac system faults. It will take some time to converge to a new average value of Udio with equations (3.14) and (3.15) (refer to Figure 3.11). To reach the new value faster, the gain in equation (3.14) must be modified during fault conditions with a method that can detect faults without knowing their exact nature and which is immune to false alarms. The variable forgetting factor method is the simplest method for changing the gain, but it is not effective for large parameter variations (e.g., as they occur during ac system faults) [39,40]. A method suggested by Hagglund [40] is tailor-made for large parameter changes. It works in two stages. The first stage detects the large parameter changes. The second stage increases the gain by adding a suitable nonnegative number. Hagglund's method, however, is unsuitable for slow parameter variations. As mentioned earlier, the instantaneous value of Udi0 depends on the ac bus voltages, which vary little (±2%) during normal operation. Large changes in the ac bus voltages are observed at the instant of fault initiation and recovery. To cope with both small changes during normal operation and large changes during faults, Udio(k) 1 - aq w(k-l) D(k B(k + 1) q is a backward shift operator Figure 3.9: Block diagram describing the fault detection method. t o 43 a combination of the variable forgetting factor method with Hagglund's method is an appropriate choice for this application. The block diagram of the combined fault detection scheme is shown if Figure 3.9. In the first stage, product D(k) between w(k — l) (Figure 3.9) and the difference between two successive estimations of Udio is used to detect changes in Udio. D(k) is then replaced by a variable S(k) to make the detection insensitive to noise [40], with [ 1 if D[k) > 0 S[k) = | 0 if D(k) = 0 { -1 if D(k) < 0 The idea of using the sign of the difference between successive estimates as a convergence criterion for the estimates has been proposed earlier[40]. To make the decision based on the recent values of S[k), a variable r(k) is introduced and defined as r(ifc) = b*r{k-l) + {l-b)*S{k) , where 0 < b < 1. During normal operation, that is, when U~dio is close to the nominal average value, the variable r(k) has a mean close to zero. During faulted conditions, r(k) would have a positive mean, which is used as an indicator for the need for a change of gain in equation (3.14). In the second stage, the gain in equation (3.14) is modified with G<*> = Afc(tV*W- <3'16> where B(k) is a nonnegative number. During normal operation the forgetting factor A is 1 and B(k) is zero. The gain can be increased either by decreasing the forgetting factor or by using a positive non-zero value for B(k). To distinguish between large and small parameter changes, two threshold values, r$ and r 3 are used. If the variable r(k — 1) exceeds a certain threshold r i , then it may be concluded that large changes in the ac bus voltages have occurred. In this case, the forgetting factor is set to 1 and B(k) is set to the value B ( f c ) = M ( i b ) | f l " r i r ( _ f c i " 1 ) } , (3.17) where A 44 Figure 3.10: Relationship between average Udio and the gamma order. 45 3 1.2 0.8 rvwwvwvwv\A 0 .4 1.2 3 d o O.B M (0 > < 0.4 i W W W W W W W W W W V Y V V V V V V V V V V V V V V Y V V V V V V V V V V V V V V V V V V 0 . 0 0 0 0 . 0 2 5 0 . 0 5 0 0 . 0 7 5 Time in Seconds 0.100 Figure 3.11: Result of fault simulation: without change of gain. If, on the other hand, the variable r(k - l) is greater than r 0 but less than r\ then the variations in the ac bus voltages are small. During this period the variable B[k) is set to zero and the forgetting factor A is varied from 1.0 to 0.9 as a linear function of r(k - 1). Using these threshold criteria, the gain G(k) is increased to emphasize the latest instantaneous values of Udlc, for a better estimate of U'dic. The curve in Figure 3.10 shows the relationship between the gamma order and per unit Udio. This gamma order changes with the change in Udio. To illustrate the computation of the average value Udio, a three-phase remote fault is simulated. During the fault, the converter bus voltage decreases to 70% of its pre-fault value. The parameters of the fault detecting system were: a=0.85, b=0.98, r0=0.4, and rj=0.55. The fault was initiated at 0.02 s and cleared at 0.07 s. Figures 3.11 and 3.12 show the result of the simulation. It can be seen that the fault detection scheme detected the fault at 21.1 ms (refer to Figure 3.12). 1.2 3 fvwwrvwvvwi 0.8-T3 — 0.75 (0 O *YVVVWVW/VWvVVVWV\ vvvvvvvwwwvvwvvvvvvvvvwvwvvvv 0.000 0.025 0.050 0.075 Time in Seconds -J A 0.100 Figure 3.12: Result of fault simulation: with change of gain. 47 Overlap Calculation The commutation voltage-time integral (i.e., the voltage drop across the commu-tating reactance during commutation) is directly proportional to the dc current[30j. The overlap angle is a function of the ac bus voltages, the firing angle, the commu-tating inductance and the dc current. However, if it is assumed that the overlap angle is less than 60°, then the overlap angle (Overlap) can be approximated as being proportional to the dc current: Overlap = K0{-^-\ . (3-18) l. IdN > where Ko is the Overlap for the rated dc current 1^ and Id is the dc link current . The error in the prediction of the overlap angle with equation (3.18)lies between 0% and +20%. The value of KQ in the above expression is a constant. The value of KQ is computed using [30]: KQ — cos - 1 | d — c d N | — Gamma (nominal) , (3.19) where Ud is the nominal dc terminal voltage , UdioN is the nominal f/d,0 , Xc is the commutating reactance. Delta Gamma Calculation The positive slope characteristic of the inverter characteristic is realized by increas-ing the gamma order. The equation is A-y = KP\I01 - Id}] , (3.20) where KP is the gradient of the slope in deg./p.u. current , Joi is the modified current order , Idf is the filtered dc current . 48 The measured dc current is filtered to get 1$ The transfer function of the filter block is G{*) = — ^ • K ' l + Ts 3.5 Solution Method for Control System Equa-tions Transfer functions of the current controller and various other filter blocks in the H V D C control system are represented in the Laplace domain. The algebraic differ-ence equations in time domain of these transfer function blocks can be written using the implicit trapezoidal rule[lj. For example, the algebraic difference equation in time domain for the transfer function in equation (3.2) is f IT 1 f IT \ + 1 j x{t) = Ku(t) + j ^ - - 1 j x[t - At) + Ku(t - At) , (3.21) where x is the output and u is the input to the transfer function and At is the step size. The generalized form of equation (3.21) is c0x{t) = d0u(t) + Hist(t - At) , (3.22) where Hist(t — At) are the known past history terms of u and x, and c 0 and do are the coefficients of x and u, respectively. The history terms are updated in each time step after the solution has been found at instant t. To impose limits on the various transfer function blocks of an H V D C control system, limiters are used. There are two types of limiters: windup (soft) and non-windup (hard) limiters [38]. The soft limiter can be visualized as a measuring instrument in which the needle (position = output signal) can only be seen within a limited window, but the needle is allowed to move freely (wind up) outside the window. In the hard limiter, the needle is restrained from moving outside the window [41]. The soft limit is easy to simulate with an equation; that is, x m i n if Ku < x x = { Ku if x m i n < x < x m a x if Ku > x. max The non-windup limiter on a transfer function with zeros is difficult to simulate because the limits on the derivatives of the input are unknown. On other hand, for 49 a transfer function with multiple poles, a non-windup limiter may be simulated by forcing the first-and higher order derivatives to zero and by clamping the output to its limits. The transfer functions used for the control system described in the previous sections neither have zeros nor have multiple poles. A non-windup limiter on such transfer functions is easy to simulate. The simulation can be achieved by not updating the history terms of the output variable when the output violates any limits. For example, consider equation (3.21). If at time t, x(t) violates a limit (say, the lower limit), then the history term x(t — At) is not updated at time t and x(t) is set to the lower limit. 3.6 Case Study The case of the two-terminal system described in [42] is simulated to validate the new generic model for the extinction angle control. The results are then compared with the results presented in [42]. The two-terminal H V D C system has a detailed ac system representation only at the inverter terminal. The details are given in Appendices A and C of [42]. As a disturbance, a step change in the current order setting is used to observe the effect of the control system on the electric system response. The current order is changed from l.Op.u. to 0.75p.u. Figure 3.13 shows the results obtained in [42], with the equidistant, pulse control (EPC) for the rectifier and Hingorani's extinction angle control for the inverter. Figure 3.14 shows the results obtained for the same system with E P C at the rectifier and the new generic model at the inverter. With the new generic inverter control, the system settles with least oscillations after the disturbance. The new generic inverter control is a predictive inverter control which performs better than the predictive inverter control suggested by Hingorani[33]. 50 3 a 3 O > c CD ; o ~ o r\l I I I I I I I I I I I I I I I I I I I 1 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 3 a. o > > c CD CD H O i i I I | i I I i | i i I I | i i i i | I I 1 1 | i i i i | i i i i | i i i i | i i i i | i i I I | i i i i 11 11 i 3 O. u 3 O 6 a> CD ; o CM I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I 3 a o > ci CD O I I I | I I I I | I I I I [ I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I | I I I I I " " I I 1 1 " I 0 . 0 .1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 Time in Seconds Figure 3.13: Transient response of a dc system due to a step change in the current (from l.Op.u. to 0.75p.u.), using the E P C scheme at the rectifier and Hingorani's extinction angle control at the inverter[42;. 51 8 8 c 3 O > c 8 8 3 i-H O > c S 8 8 c 3 O o & 8 8 3 •—I O >• • o & 8 V IT" . . . . . . 0.00 0.10 0.20 0.80 0.40 0.50 0.80 Time in Seconds Figure 3.14: Transient response of a dc system due to a step change in the current (from l.Op.u. to 0.75p.u.), using the EPC scheme at the rectifier and the new generic model at the inverter. Chapter 4 C A S E STUDIES ON A T W O - T E R M I N A L H V D C LINK 4.1 Test System In order to validate the mathematical description of the converter and control system, and to check the accuracy and numerical stability of the numerical solution algorithm, the behaviour of a two-terminal H V D C system under steady-state and transient conditions is simulated. The simulation results are compared with results from a hardware simulator with actual H V D C controls. The test system chosen is shown in Figure 4.1. Its parameters are given in Appendix B. All case studies assume a twelve-pulse operation. Both the rectifier and the inverter terminals are represented. The ac systems and the ac filters are modelled with lumped R, L , and C elements, and the magnetizing inductances of the converter transformers are modelled as piecewise linear inductances on the ac side. The three-phase short-circuit power at the rectifier and inverter terminals is 1770 M V A and 4825 M V A , respectively. The dc system is a two-terminal bipolar twelve-pulse scheme. In the simulator study used here for comparison purposes, the bipolar dc line was represented as an equivalent monopolar line to simplify the simulations. In the conversion from a bipolar to a monopolar equivalent, the ground current is assumed to be zero. Therefore, faults on the dc side which give rise to ground currents cannot be sim-ulated. All types of ac faults can be simulated, however. To make the electrical network in the digital simulations similar to that of the simulator study, the equiv-52 Rectifier End A / V R 2 L C - / T C r v L C A/V R 2 L . . C Filters X Filters X Filters X Y / Y h-00—I Y / A Tir>- DC Line > DC Filter! The diagram of the inverter side is identical with that of the rectifier side, but the parameters are different. Figure 4.1: A test system showing two-terminal HVDC system 5 4 alent monopolar dc line representation is adopted as well. The dc line is modelled as a single-phase-distributed-parameter line. The twelfth harmonic dc filters at the rectifier and at the inverter terminals are modelled with lumped R, L, and C elements. The dc link power rating is 800 MW and the dc voltage rating is 500 kV. The short-circuit-ratio (which is the ratio of the three-phase short-circuit power at the converter ac bus to the rated dc link power) of the rectifier and inverter is 2.21 and 6.03, respectively. 4.2 Simulation for Steady-State Conditions Starting from the approximate initial conditions described in Section 6.2, simula-tions were performed over a time span of 0.8 s, with At=40 ps. Since there was no disturbance in the system (except for small errors in the initial conditions), the simulation must therefore reproduce the steady-state behaviour of the HVDC link. This is a useful check for the accuracy of the model, since the steady-state behaviour is usually well-known and is a useful test for numerical stability. The results of the simulation are shown in Figures 4.2 to 4.6. There is no sign of nu-merical instability in any of the curves, in spite of the 20,000 steps to the end of the simulation time span. 4.3 Simulation of Transient Conditions Transient phenomena caused by three types of faults were simulated. These faults were a remote-three-phase fault, a single-phase-to-ground fault, and a three-phase-to-ground fault. 4.3.1 Remote Three-Phase-to-Ground Fault A remote three-phase-to-ground fault was simulated by grounding the converter ac bus through lOOfl resistances. This resistance fault reduced the converter bus voltage by 25% of the pre-fault value. This effect is similar to that of a remote 55 CM CD O o > o I I I I I I I I I I I I I    I I I I I I I I I I I I I I I I I I I I I I I I" "I I I I I I I I I I I I I I I o • _ > o > > c P 3 . I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I" 1 11 1 1 " I ' " '1 1 1 1 'I O J hi 9 -I o O i i i i i i i i i I i i 0. i 1 1 1 1 1 111111111111111 i " " i . . . . i 11111111111 0.14 0.28 0.42 0.56 Time in Seconds 0.7 0.84 Figure 4.2: Steady-state dc voltages and current at the rectifier and at the inverter terminals. Figure 4.5: Steady-state voltages across converter valves at the rectifier and at the inverter end. Cn 00 59 . o o > C 8 l 5 A > c u c u ID o o . o 7. 7.17 7.34 ^ 7.51 7.88 7.85 8 .02 Time i n Seconds MIO-1 Figure 4.6: Steady-state control outputs and Udio outputs at the rectifier and at the inverter ends. 60 fault. The duration of the fault was 200 ms (12 cycles), from t=40 ms to t=240 ms. The total time of the simulation was 500 ms. This fault was applied to both the rectifier and the inverter. At the Rectifier The results of the simulation are shown in Figures 4.7 and 4.8. Observations: • No overvoltages were observed. • The increase of harmonic contents was insignificant. • Nearly 60% of the pre-fault dc power was transmitted during the fault. • After fault clearing the dc terminal voltages recovered up smoothly. • The maximum dc current in the post-fault period was 0.65 p.u. • The inverter was controlling the current during the fault. When the fault was cleared, the current control was transferred from the inverter to the rectifier. It demonstrated that the control model was capable of transferring current control mode from the rectifier to the inverter and restoring it back to the rectifier. At the Inverter The results of the simulation are shown in Figures 4.9 to 4.12. Observations: • During the fault, no significant increase of harmonic contents was observed. • There was no sign of temporary overvoltages. • During the fault, the dc system transmitted 78% of the pre-fault power. • When the fault was cleared, the dc system voltages recovered up smoothly. 61 P OJ a r~ r ^ -J o > > c I" " I" " I " I " 1 1 1 1 1 1 1 1 1 1 1 1 1 p a u P U > c V 6 ' 3 OJ "o > I ' 11 1 I ' i i i i i i i i i i i i i i i i , i ! i i , I 1 1 1 1 I 1 1 ' I I I I I I I I I I I I I I , I I I I.... I p a m j P u c 0. ' I " 1 ' I " " I ' " 1 I 1 " 1 | 1 " 1 | 1 " 1 | 1 1 • • | " 0.084 _0.168 0.252 0.336 Time in Seconds 11 1 1 "I " " i 0.42 0.504 Figure 4.7: Remote three-phase-to-ground fault at the rectifier end: dc terminal voltages and currents. 62 13 > c 3 a o Cv d ' . , . . ( . , i i | i i i i j i , , , j 1 . . . . . . . . . , i i n | i i i i | n i l | . , r-T 1 ' ' ' ' 1 1 " 1 ' " ' 1 1 ' " I r 1 1 1 1 1 1 1 1 1 1 " 1111111111 n 111 111 1 1111111, w —. be CO S H a < H o Di I 1 1 1 1 I 1 1 1 1 I 1 1 1 1 I 1 ' ' 1 ) I I ' I I ' I I ' [ I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 0 . 0.084 0.168 0.252 0.336 0.4 2 0.504 Time in Seconds Figure 4.8: Remote three-phase-to-ground fault at the rectifier end: dc controls and Udio outputs. 63 IT) as I ' ' ] I ' 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 j 11111111111111 j 1111 j 1111111111 0. 0.084 0.168 0.252 0.336 0.42 0.504 Time i n Seconds Figure 4.9: Remote three-phase-to-ground fault at the inverter end: dc terminal voltages and currents. 64 0) a: . _ © j i i i i | i i i i | i i i i | i i i i | i i i i | i i i i | i i i i | i i i i | i i i i | i i i i | i i i i | i i i i | 0. 0.084 0.168 0.252 0.336 0.42 0.504 Time i n Seconds Figure 4.10: Remote three-phase-to-ground fault at the inverter end: dc controls and Udio outputs " Au°D o M CO — 1 i i . i r-j . i ri-j , r i . . i . T t f t-r-j-T i r-r-p i t-r-j-t t r-j , , i r-p . i T-J t i i i-f f t r-r-p . . f-f f t i T-f i . .•«-]• i i t tf T i t .-f-r . t f-| t i i-.-y-t . t-r-j 0 3 0.4? 0.54 0.66 0.78 0.9 1.02 1.14 1.28 1.3B 1.5 Time in Seconds K I O - 1 Figure 4.12: Remote three-phase-to-ground fault at the inverter end: voltages across the converters and dc link current. 67 • The maximum dc current at the time of fault initiation was 0.87 p.u. at the rectifier and 1.38 p.u. at the inverter. • After fault initiation, a commutation failure occurred in one of the six-pulse converters of the inverter. This six-pulse converter recovered from the com-mutation failure. The dc system stabilized at a lower dc link current as determined by the V D C O L . The V D C O L reduced the current order because the dc system voltage was low. 4.3.2 Single-Phase-to-Ground Fault A solid single-phase-to-ground fault was applied to phase A of the converter ac bus for a duration of 200 ms (12 cycles), between t=40 ms and t=240 ms. The total time of simulation was 500 ms. This fault was applied to both the rectifier and the inverter. The results of the simulations have been compared with the H V D C simulator outputs and are presented below. At the Rectifier The results of the simulation are shown in Figures 4.13 to 4.18. Observations: • After fault initiation, transient overvoltages up to a maximum of 2.3 p.u. were observed in the unfaulted phases B and C at the rectifier. • After fault initiation, high magnetizing currents were drawn by the converter transformers at the rectifier in phases B and C due to high transient overvolt-ages in those phases. During the post-fault period, the converter transformers at the rectifier end in all three phases were going in and out of saturation, which might be due to poor damping in the ac network. • Following fault clearing, the periodic saturation of converter transformers caused relatively low temporary overvoltages up to a maximum of 1.1 p.u. in all the phases. Similar observations were made earlier [43,44]. These 68 W j I I I I j I ! I I j I I I I j I I I I | I I M j I I I I | I I I I | I I [ I | I I I | j | | | | J | | | | j | | | | j 0. 0.084 0.168 0.252 0.336 0.42 0.504 Time in Seconds Figure 4.13: Single-phase-to-ground fault at the rectifier end: dc terminal voltages and currents. 69 3 O. D > c XI eo in' O OS TUirMi 1111111111111111111111111 j 1111 j 1111111111111111111 j 1111111111 o. 0.084 0.168 0.252 0.336 0.42 Time in Seconds 0.504 Figure 4.14: Single-phase-to-ground fault at the rectifier end: control and Udio outputs. 70 Figure 4.15: Single-phase-to-ground fault at the rectifier end: rectifier ac bus volt-ages. 71 -I < u u I CL . i 1 " 1 1 1 ' 1 1 ' ' ' • | ' ' 111111111111 [ 11111 < u o ' 3 U CO I 1 1 • i 1 ' I ' 11 i 11111 i 1111 i 11 11 u o J 3 o JUUUiAJdLUUULLLL CL f J 0. 1 I ' " 1 I 1  '.| 1 " 1 | 1 " 1 | 1  " | 1 ' ' 1 0.084 0.168 0.252 0.336 Time in Seconds " I " " i " 1 1 1 1 " 11 0.42 0.504 Figure 4.16: Single-phase-to-ground fault at the rectifier end: transformer inrush current at the rectifier side. 72 ©_, N — * —I > > u I JS o 1 i" 1 1 1 i 1111111111111111111 N 2-• —i > o > CD I JS o * 7- I j I I I I I I I I I I I I I I I I I I I I I I 1 I I I I I I I I I 'I I I' I'I 1 1 ' 1 I' 1 I I I 0. I I I j I I I I I I I I I I I I I I I I 0.08 11 i i 111 i i 111 i i 111 i i 111 i i 111 i i 11 0.16 0.24 0.32 0.4 T ime i n Seconds 0.48 Figure 4.17: Single-phase-to-ground fault at the rectifier end: inverter ac bus volt-ages. 73 Figure 4.18: Single-phase-to-ground fault at the rectifier end: transformer inrush current at the inverter side. 74 9 a > in c4 s a O 0.1 0.2 0.3 T i m e (Sec) 0.4 0.5 Figure 4.19: Single-line-toground fault at the rectifier end: dc voltage and current waveforms at the inverter side (HVDC simulator results[45]). periodic saturations of converter transformers also distorted the voltages of the unfaulted phases. • On an average, 20% of the pre-fault power was transmitted during the fault. • After the fault was cleared, the dc voltages recovered slowly. • During this simulation, the maximum dc current at the rectifier was 1.1 p.u. and 0.86 p.u. at the inverter (refer to page 76). • During this fault, in all the phases of the inverter, transient overvoltages of 1.25 p.u. were observed. Comparison with the H V D C Simulator Results: 75 Figure 4.20: Single-line-to-ground fault at the rectifier end: control and Udio wave-forms (HVDC simulator results [45]). 76 For an identical fault, the results from the HVDC simulator are presented in Figures 4.19 and 4.20 [45]. The overall behaviour in the digital simulation and in the HVDC simulator study was comparable. The differences can be explained as follows: • The HVDC simulator used actual HVDC controls but in the digital simu-lation, a simple current controller and a new generic commutation margin control were used. This might be the reason for the differences in the control outputs (i.e., in alpha and in gamma). • The digital simulation results showed the presence of higher harmonics in the dc system (Figure 4.13). This might be due to the difference in the sampling frequencies. The sampling frequency in the digital simulation was 7.5kHz, as compared to the 2kHz in the HVDC simulator. • The maximum transient dc current at the inverter side for the digital simula-tion was 0.86 p.u., and for the HVDC simulator, it was 0.78 p.u. This slight mismatch might result from the differences in the inverter control schemes. A t the Inverter The results of the simulation are shown in Figures 4.21 to 4.26. Observations: • During the fault, transient overvoltages up to a maximum of 1.92 p.u. were observed on the unfaulted phases B and C at the inverter. The maximum transient overvoltage was 1.72 p.u. during the post-fault period. • These transient overvoltages led to a periodic saturation of the converter transformers at the inverter, during the fault. This periodic saturation caused harmonics in the voltages of the unfaulted phases B and C. The inrush cur-rent decayed fast after fault clearing because the inverter network had high damping[43,44]. • At the rectifier, transient overvoltages up to a maximum of 1.79 p.u. were observed. These overvoltages at the rectifier caused a periodic converter 77 0. 0.084 0.168 0.252 0.336 0.42 0.504 Time in Seconds Figure 4 . 2 1 : Single-phase-to-ground fault at the inverter end: dc terminal voltages and currents. 78 Figure 4.22: Single-phase-to-ground fault at the inverter end: control and Ua0 outputs. 79 Figure 4.23: Single-phase-to-ground fault at the inverter end: rectifier ac bus volt-ages. 80 CO < J* 3 o I i j I I I I j I I I I j I I I I j I I M j I I I I j I I I I | I I I I j I I I I j I I M j I I I I j I I I I j < u U CO I JS c co . o . eo i ' AJJLUII Jl lUUUJUJLJULiJLIll T T T T ' T 1 1 1 r ' l -1 | I I I I \ 1 I I I | I I I I j ! I 1 I "T 1 T 1 1" V 1 1 I ! I I I i i i 111 i i 11 i i i 11 i i i i i i i i i 11 i i 11' i i 111 i i i i i i i 11 i i i 11 11 i 11 i i i i I    11 0. 0.084 0.168 0.252 0.336 0.42 0.504 Time in Seconds Figure 4.24: Single-phase-to-ground fault at the inverter end: transformer inrush current at the rectifier side. 81 Figure 4.25: Single-phase-to-ground fault at the inverter end: inverter ac bus volt-ages. 82 OJ < i- o~T" 3 O u I X. 0. CN) ft i A ft > 1 i i i i I i i i i I i i i i i i i i i i i "I 1 " 1 I 1 1 1 11 1 1 " I CO . < Jit 3 u CQ I JC Cu O . CO JL I 1 " 1 I " 1 1 I " " I i i i i i i i i i i i i i i i i i i i i i i i i i i i i i j i i i i j i i i i u o j 3 u < I a. OJ _ 0. i i i i i i i i i i • I " " I " " I • " • I • • • • I " " I 0.084 0.168 0.252 0.336 Time in Seconds 1 1 1 " I " 1 1 1 " 1 1 1 0.42 0.504 Figure 4.26: Single-phase-to-ground fault at the inverter end: transformer inrush current at the inverter side. 83 transformer saturation during the fault. In the post-fault period, this satu-ration phenomenon persisted in the transformer connected to phase B. This saturation gave rise to temporary overvoltages of 1.25 p.u. during the fault [43,44] and also generated harmonics in the voltages on the ac side during and after fault clearing. • Approximately 8% of the pre-fault power was transmitted in the fault dura-tion. • After fault clearing, the dc terminal voltages were restored after several at-tempts by the control. • During the fault, the maximum dc currents at the rectifier was 1.18 p.u. and at the inverter was 1.93 p.u. (see page 83). The maximum dc voltages at the rectifier was 1.58 p.u. and at the inverter was 1.18 p.u. Comparison with the H V D C Simulator Results: For an identical fault, the results from the H V D C simulator are presented in Figures 4.27 and 4.28 [451. The noticeable differences between the results presented in Figures 4.21 and 4.27 and Figures 4.22 and 4.28 can be explained as follows: • Differences in the controller outputs were present especially in the waveform showing the gamma variations (see page 76 for the discussion). • At the instant of fault, the rate of rise of the firing angle a (see Figures 4.22 and 4.28) in case of the digital simulation was 7.5°/ms and in case of the H V D C simulator was 4 ° / m s . From these rates of rise of alpha, it was apparent that, in the digital simulation, the rectifier was forced to go into inverter mode rapidly causing fast load rejection at the rectifier. This led to high transient overvoltages, unlike the low level of voltages observed in the H V D C simulator output. • The parameters of the fault detection method in the new generic inverter control were not optimized. As a result, in the digital simulation of the inverter, a high dc fault current of 1.93 p.u. was observed which was due 0 0 1 0.2 0.3 0.4 0.5 Time (Sec) Figure 4.27: Single-line-to-ground fault at the inverter end: dc voltage and current waveforms at the inverter side (HVDC simulator results[45]). 85 Figure 4.28: Single-line-to-ground fault at the inverter end: control and Udio wave-forms (HVDC simulator results[45]). 8 6 to the slow change in the value of gamma (see Figure 4.22 for the gamma variation). In contrast, the dc fault current at the inverter was 1.78 p.u. for the H V D C simulator. 4.3.3 Three-Phase-to-Ground Fault A solid three-phase-to-ground fault was applied to the converter ac bus for a du-ration of 66.67 ms (4 cycles), between t=40 ms and t—106.67 ms. The total time of simulation was 500 ms. This fault was applied at the rectifier end only. The results of the simulation have been compared with the H V D C simulator outputs. The simulation results are shown in Figures 4.29 to 4.34. Observations: • After fault clearance, the maximum transient overvoltage was 2.72 p.u. at the rectifier. • In the post-fault period, the magnetizing currents drawn by the converter transformers were damped in phases A and B, but remained undamped in the phase C during the entire simulation. The magnetizing currents caused harmonics in the ac voltages. • There was a significant increase of harmonics in the dc line at the rectifier. There could be many reasons for these harmonics, such as over-sensitive current controller parameters, poor damping in the network, etc. • In the post-fault period, the dc terminal voltages recovered slowly. • The maximum dc line current during the time of recovery was 0.96 p.u. at the rectifier and 0.83 at the inverter. The maximum dc line voltage was 1.41 p.u. at the rectifier and 1.37 p.u. at the inverter. Comparison with the H V D C Simulator Results: For an identical fault, the results from the H V D C simulator are presented in Figures 4.35 and 4.36 [45]. The noticeable differences in the results presented in Figures 4.29 and 4.35 and Figures 4.30 and 4.36 can be explained as follows: 87 OS . I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I j I I I I I I I I I I I I I I I 0. 0.084 0.168 0.252 0.336 0.42 0.504 Time in Seconds Figure 4.29: Three-phase-to-ground fault at the rectifier end: dc terminal voltages and currents. 88 c o l 9 T3 P H r " 1 1 1111111111111111111111111 [ 111111111111111 111111111111111 j 1111 [ 111111111 j 111111111111111111111111 j 11111 O 0.084 0.168 0.252 0.336 0.42 0.504 Time in Seconds Figure 4.30: Three-phase-to-ground fault at the rectifier end: control and Udio 89 Figure 4.31: Three-phase-to-ground fault at the rectifier end: rectifier ac bus volt-ages. 90 U © 3 I TrnriTTTTTTTTTTTinrTTm 11111111111111111111 [ 11111111111111 j 111111111 [ 1111111111 u o O 111 1111 1111 11 1111111111 i [ i 111 j i 111 j 111111111 j 11111111 1111' 11 h © ^ I us i J L _ L _ » _ i i • i i i i • — • — i — i — * _ 111 i 11 i i i i j i i i i I i i i 11 i i i i I i i i i 11 i i i 11 i i i | i i i i 11 i i i [ i 11 11 i i i 11 0. 0.OB4 0.168 0.252 0.336 0.42 0.504 Time in Seconds Figure 4.32: Three-phase-to-ground fault at the rectifier end: transformer inrush current at the rectifier side. 91 Figure 4.33: Three-phase-to-ground fault at the rectifier end: inverter ac bus volt-ages. 92 Figure 4.34: Three-phase-to-ground fault at the rectifier end: transformer inrush current at the inverter side. 9 3 > c 1/5 3 o 0.1 0.2 0.3 Time (Sec) 0.4 0.5 Figure 4 . 3 5 : Three-line-to-ground fault at the rectifier end: dc voltage and current waveforms at the inverter side (HVDC simulator results[45]). 94 Figure 4.36: Three-line-to-ground fault at the rectifier end: control and Udi0 wave-forms (HVDC simulator results[45]). 9 5 • In the HVDC simulator study, the dc transmission line was modelled with six cascaded 7r-circuits, but the digital simulation used a distributed-parameter line model. The higher transients in dc voltages and currents, which were present only in the digital simulation results, might be due to the travelling wave effects. • Following the fault clearance, the oscillations in the voltage and current wave-forms in the digital simulation could be attributed to poor damping in the network. This poor damping could result because the hysteresis of trans-former cores and filter inductances were neglected. • Differences in the controller outputs were present especially in the waveform showing the firing angle a variation (see page 76 for the discussion). Chapter 5 M U L T I - T E R M I N A L C O N V E R T E R SIMULATION In past years, the HVDC transmissions (two-terminal and back-to-back systems) have gained popularity among the North American utilities because the HVDC technology has proven itself to be reliable and is found to be ideal for intercon-necting different ac systems. Despite this popularity, the mesh-type and the radial-type of multi-terminal HVDC schemes, are still not in operation. The Nelson River HVDC Bipoles 1 and 2 have been operated in a four-terminal mode occasionaly[46], although the system is not truely a multi-terminal scheme. It has been reported by Long et al [47] that a third terminal of the Italy-Corsica-Sardinia 200MW/200kV dc link was expected to be commissioned in 1986. The third terminal at Corsica rated 50MW would be in parallel with the main converters at Italy and Sardinia. Recently, a contract has been awarded in December 1986 to build a five-terminal converter system between Quebec (Canada) and New England (USA), with two conventional converter stations at the two ends, and three tap converter stations in between. Another multi-terminal scheme in progress is the HVDC Pacific Intertie, which is a special case of the radial-type multi-terminal configurations. The exist-ing Pacific intertie is being upgraded in its current rating by paralleling a converter to the ones already in operation. Multi-terminal HVDC systems made a humble beginning with the paralleling and deparalleling tests on Nelson River HVDC Bipoles 1 and 2. To simulate these systems, techniques have to be developed. This chapter will show that the simu-lation methods developed in Chapters 2 and 3 can also be used for multi-terminal 96 97 converter systems. The control philosophy of multi-terminal systems is discussed first, followed by the simulation results for parallel and three-terminal converter systems. 5.1 Multi-terminal dc Control System For the last 15 years, many researchers have studied multi-terminal dc transmission systems and their controls [48,49]. Four basic control schemes have evolved. They are (i) current margin (or current coordination) control [50], (ii) voltage margin control [51], (iii) limiting voltage control [52], and (iv) two-current regulator control [53]. Among these control schemes, the current margin control method is the pre-ferred one. It is an extension of the conventional two-terminal dc control. A fast communication link between the terminals is required to coordinate the current orders of each terminal continuously. If the communication link fails, the loss of any one rectifier or inverter may result in instability of the dc system. An improved current margin control scheme has been proposed in [54], which is less dependent on communication during restart. A limitation of the method, however, is that the system has to restart even for small disturbances on the system. A voltage margin control scheme has the same problem. The concept of operating the sending end terminal with a voltage below rated voltage, typically 5%, was first used in the Gotland transmission system as a backup control whenever the communication link broke down. A similar idea has been suggested for controlling multi-terminal H V D C systems. This is known as the limiting voltage control method that can be operated without the communication link. However, the operating characteristics of this scheme are not good enough in practice because the dc fault current or the commutation failure current can become very high while the communication link is inoperative. The control with two-current regulators depends on dc circuit breakers and does not need a fast communication link, even under fault condition. Once the set orders of the converters are relayed to the stations, a stable operating point can be obtained automatically under any contingencies. An additional voltage margin 98 Figure 5.1: A block diagram of a current balancer. For a rectifier: X = 1, Y = -1; For an inverter: X =-1, Y =1. is imposed on each inverter to reduce the risk of overloading it in the event of a communication link failure. This extra voltage margin increases the consumption of reactive power. DC circuit breakers have only become commercially available in the last few years, and no H V D C system has used them yet. This may be the main reason why a two-current regulator control is not used at this time. A two-terminal parallel converter system is a special case of a multi-terminal system. Therefore, the control schemes for multi-terminal systems can also be used for parallel converter systems. In this thesis, the current margin control scheme is used because it seems to be the preferred method in industry. It is briefly described next. 99 5.1.1 Current Coordination Control The current coordination control is achieved by balancing the current orders of all the terminals. These current orders are proportional to the power orders of each terminal (assuming a constant voltage system). The current balancer tries to maintain the sum of all currents injected into a dc system at zero. In the summation, the current order of a rectifier is considered to be positive and that of an inverter, to be negative. Figure 5.1 shows the block diagram of a current balancer. The inputs of the current balancer are the preset current orders of all the terminals. The outputs of the current balancer are the reference current orders for all the terminals. These reference current orders are relayed to their respective terminals. If the sum of all the reference current orders is non-zero, then a controlled distri-bution of this non-zero quantity is done among all the terminals. The distribution is controlled by a distribution factor Kj, where subscript j is the terminal num-ber. The sum of the distribution factors should be one. The distributed amount is added to the preset current order if the terminal is a rectifier and is subtracted if the terminal is an inverter. Limits are imposed on the balancer to safeguard against overcurrents. 5.2 Simulation Results Simulations were performed with a two-terminal parallel converter system and a three-terminal converter system. 5.2.1 Parallel Converter System This system is similar to the two-terminal dc system described in C H A P T E R 4, except that each twelve-pulse converter has been replaced by two twelve-pulse converters connected in parallel. The detailed system parameters are given in Appendix B, and the operating conditions of the system are tabulated in Appendix C. o CM > O > CJ a > c O J Cvj 1 V V V 1 1 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I     I I I I I I I I I I I I C\> »T5 4 o * -I cv 4 > - « 1 = : c v i U CO CJ to r V V 1 1 1 " ' I" 1 1 1" 1 I I I I I I I I I I I I I 1 I I I I I 1 I I I I I I I I I I I I I I I I I I I I I 0.08 0.16 0.24 0.32 Time in Seconds 0.4 0.48 Figure 5.2: Steady-state simulation of the parallel converter system: ac at the rectifier and the inverter ends. 101 CM (O o >* o > CJ > c CO . I I I I I I I I I © o > O V OS c*3 i i i i i i i i i i i i i i i i i i I I i i i 11 i i i i 0. 0.08 0.16 0.24 0.32 Time in Seconds 0.4 0.48 Figure 5 . 3 : Steady-state simulation of the parallel converter system: dc bus volt-ages and line current. Figure 5.4: Steady-state simulation of the parallel converter system: dc terminal voltages before the smoothing reactor. 103 9 d " 9 0) o o Inverter Arm 2 i i i i i i i i i I i i i 111 i i 11 i i i i I i i i i 11 i ' i I' ' i ' I 9 CA? 5 O l h O h 9 Inverter Arm 1 ' I I I I I j I I I I | I I I I | I I I I | I I I I | I I I I | T I I I | I I I I | I I T I j I I I I | I I I I j 3 a in d J 5 o r f O 9 Rectifier Arm 2 i i 11 i i i 11 i i i 111 i i 111 i ' i [ ' ' | • i i i 1 1 i i i | i i i i | i i i 1 1 i i i 1 1 i i i I   i 11  i i 11 d " 9 CD O * J Rectifier Arm 1 I i i i i I i i i i j i 11 111 i i i [ i i i i 11 i i i 11 i i i | i i i i j 111 11 i i i 11 i i i 11 0.08 0.16 0.24 0.32 Time in Seconds 0.4 0.48 Figure 5.5: Current order change in the parallel converter system: current order of each arm. 104 3 a. G V u k 3 U in 11111111111 Inverter Arm 2 C k 3 U o . Inverter Arm 1 i i 11 i i i i j i i i i j i i i 11 i i i 111 i i i j i i 11 j i i i i | i i i 11 i i i 11 i i i i 2 * c 0) 3 Rectifier Arm 2 i i i 1111 i 111 i i 11 i i i 11 i i i i i i i i i 11 i i ' 11 " 1 I " " I " " I 1 1 " I " " I 2 c 0) 3 Rectifier Arm 1 | i i i i j i i i i I i i i i l i i T i | i i i i | i i i i j i i i i | i i i i | i i i i j i i i i j i i r i j i i i i j 0. 0.08 0.16 0.24 0.32 0.4 0.48 Time in Seconds Figure 5.6: Current order change in the parallel converter system: dc current through each arm. 105 cu © 0) CO Inverter Arm 2 o > i i 11 i i i 11 i i i 11 i i i 11 i i i i I i i i i 11 i i i I i i i i I i i i i j i m a o 4) M m Inverter Arm 1 o > o 1111 j 1111111111111111111 [ 11111111111111 j 1111 j 1111 j 1111111111 m Bx O 0) M CD • J > Rectifier Arm 2 i i 1111 i 111 11 i j i 11 i j i i i i j i i i i 11 i i i 11 i i 1111 i i j i i i i j i i i i j i i i i j ft. o 0) 60 CO > Rectifier Arm 1 11 i i 11 i i i 11 i i i i j i i i i j i i i i | i i i i j i i i i 11 i i 111 i i 111 i i 11 i i i i j i i i i | 0. 0.08 0.16 0.24 0.32 0.4 Time in Seconds 0.48 Figure 5.7: Current order change in the parallel converter system: dc terminal voltages. 106 CO _ , be ^ — CB < CM. "V-Inverter Arm 2 i i i 11 i i i 11 i i i 11 i i i 11 i i i i 11 i i 111 i i i i i i i i i i i i 11 i i i 11 11 i 11 i i i  11 1111   11 o M 2-eg J3 < CM. Inverter Arm 1 i i i 11 i i i 11 i i i i j i i i i j i i i i 11 i i i j i i i i j i i i i j i i i i j i i i 11 i i i i j i i i 11 Jm a Recti f i e r Arm 2 i i 11 i i i 11 i i i i j i i i 111 i i i | i i i 111 i i i j i i i i j i i i i j 11 i i j 11 i 11 i i i 11 bo tf2 • X I JS a. R e c t i f i e r Arm 1 j i i i 111 i i 11 i i i i [ i i i 11 i i i i 11 i i i j i i i i j i i i i [ i i 1111 i i 111 i i i j i i i ' | 0.08 0.16 0.24 0.32 Time in Seconds 0.4 0.48 Figure 5.8: Current order change in the parallel converter system: firing angle of each arm. 107 Steady-State Response The steady-state waveforms are shown in Figures 5.2 to 5.4. They resulted from a transient simulation over a period of 500 ms, with At=45 us, and with the to-tal number of time step being 11111. This simulation confirms that the solution method is numerically stable and does not run away. Transient Response due to Change in the Current Order Settings The initial current order setting of all four converters is 0.25 p.u. The current orders for arm 1 of the rectifier and arm 1 of the inverter are changed from 0.25 p.u. to 0.35 p.u. in two equal steps, at 40 ms. and at 50 ms., and then reset to their original value at 300 ms. (Fig. 5.5). The transient responses to 500 ms. are plotted in Figs. 5.5 to 5.8. At the instant of the current order change, the currents through each arm begin to change to their new current order values. A transient overshoot occurs primarily on the inverter side. The disturbances in the dc voltages are insignificant. The increase in currents is achieved through a decrease in the ignition angle of arm 1 at both ends. The maximum transient dc current through arm 1 of the inverter is 0.4 p.u. 5.2.2 Three-terminal Converter System This system has three-terminals: one rectifier and two inverters (Figure 5.9). The rectifier is a twelve-pulse parallel converter system; each of the two inverters is a single twelve-pulse converter. The dc system contains two monopolar lines and dc filters. The ac systems at the rectifier and at the second inverter are identical to the ac systems at the rectifier and inverter of the system discussed in Section 5.2.1. The ac system of the first inverter is represented by a voltage source with a zero internal impedance. The system details and the operating conditions are given in Appendix C. 108 AC Network AC Filters Rectifier o DC Filter Inverter 1 T o o 3 AC Network AC Filters Inverter 2 Figure 5.9: A three-terminal system. 109 Figure 5.10: Remote three-phase fault at the second inverter of the three-terminal system: current order of each arm. 110 in Figure 5.11: Remote three-phase fault at the second inverter of the three-terminal system: dc current through each arm. I l l o > in OJ bo ed m . Inverter 2 ' | ' i i ' | ' ' i ' j i 'I ' | ' i ' i | i i i i | i i i i 11 i i i | i i i i [ i i i i j i i i i j i i i 11 l l l l Inverter 1 I I I | T I I I | I I I I | I I I I | I I | | j | | | | j | | | | j R e c t i f i e r Arm 2 11 1 i i j i i i i j i i i i j i 1 1 i j i i i i | i i i 1 1 1 i 1 1 j i i 1 1 | i i i 11 i i i i j i i i i j o > in OJ 03 in 7' R e c t i f i e r Arm 1 I " 111 " 1 1 I 1 1 111 ' " ' I 1 1 1 1 I 1 1 1 1 I 1 1 1 1 I''" I 1 1 ' ). 0.08 0.16 0.24 0.32 Time in Seconds i " " i " " i I M , i 0.4 0.48 Figure 5.12: Remote three-phase fault at the second inverter of the three-terminal system: dc terminal voltages. 112 Figure 5.13: Remote three-phase fault at the second inverter of the three-terminal system: firing angle of each arm. 113 O © Time i n Seconds Figure 5.14: Remote three-phase fault at the second inverter of the three-terminal system: ac voltages at rectifier. 114 Figure 5.15: Remote three-phase fault at the second inverter of the three-terminal system: ac voltages at the second inverter. 115 to CM o. 5 co -v © u o Inverter 2 i i i i i i 11 i i i 11 i i i 11 i i i i 11 i i i j i i i i 11 i 1 1 j i i i i j i i i 11 i i i i j i i i i I i i i i j i i i 11 i i i 11 i i i i 11 i i i j i i i i j i i 11 11 i i i j i i i i j i i i 11 i i i 11 R e c t i f i e r Arm 1 i i i i i i i i i i i i i i | i i i i j i i i i i i 1 1 1 I " " ! 1 11111 j 111111111111111111111111 j 0.08 0.16 0.24 0.32 Time in Seconds 0.4 0.48 Figure 5.16: Remote three-phase fault at the rectifier of the three-terminal system: current order of each arm. 116 6-q Time in Seconds Figure 5.17: Remote three-phase fault at the rectifier of the three-terminal system: dc current through each arm. 117 a V Ml « O > CM Inverter 2 I " ' I i I | I I I I | i i i i j i i i i j Inverter 1 3 a w CD > CM . R e c t i f i e r Arm 2 1 1 1 1 1 1 1 1 j 1 1 1 1 1 1 1 1 1 1 1 1 1 1 j 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ^ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 j 1 1 1 1 1 CM 3 a bo C0 > R e c t i f i e r Arm 1 11 i i 1 1 1 i i 11 i i i 1 1 1 i i 11 i i i i 11 i ' i 11 i i i 11 i i i | i i i 11 i i i 11 i i i i j i i i 11 0. O.OB 0.16 0.24 0.32 0.4 0.48 Time in Seconds Figure 5.18: Remote three-phase fault at the rectifier of the three-terminal system: dc terminal voltages. 118 co_. Figure 5.19: Remote three-phase fault at the rectifier of the three-terminal s y s t e m : firing angle of each arm. 119 N l f ) " D O i °- *? " i ' " ' ! " " ! " " ! ""I " " | " " | " " | " " | © j 0. 0.08 0.16 0.24 0.32 0.4 0.48 Time in Seconds Figure 5.20: Remote three-phase fault at the rectifier of the three-terminal system: ac voltages at the rectifier. Figure 5.21: Remote three-phase fault at the rectifier of the three-terminal system-ac voltages at the second inverter. 1.21 Three phase Inverter F;nilt A remote three-phase fault on the ac system of the second inverter is simulated by connecting a resistance of 75f) to the ac bus of the second inverter. The simulation results are shown in Figures 5.10 to 5.15. The maximum dc fault, currents are 0.4 p.u. (rectifier), 0.3 p.u. (first inverter), and 1.312 p.u. (second inverter). From Figure 5.14. it can be seen that an inverter fault can distort the rectifier ac bus voltage if the rectifier system is weak. The transient overvoltages on the ac system are 1.289 p.u. at the rectifier and 1.287 p.u. at the second inverter. Three-phase Rectifier Fault An identical fault is simulated on the ac system of the rectifier side. The simulation results are shown in Figure 5.16 to 5.21. The maximum dc fault currents through all converters is less than 0.4 p.u. There are no overvoltages in any of the ac systems. Chapter 6 A C / D C INITIALIZATION IN T H E E M T P 6.1 Introduction Transient phenomena in power systems are described by differentia] equations, and their solution, therefore, depends on the initial conditions (or operating points). For a linear ac system with voltage and current sources, the initial conditions can be found, from a steady-state phasor solution, with the system of linear equations Y ^ V ^ = - YABVB , (6.1) where A refers to the subset of nodes without voltage sources and B refers to nodes with voltage sources. and Y ^ , are the nodal admittance matrices, with the rows for subset B excluded. Vector 1,4 contains the current sources connected to the nodes of A. The E M T P uses this formulation to obtain the initial conditions v(t = 0) = 3t{V} , and i(t = 0) = 9c{I} , where V and I are the peak (not RMS) phase values obtained from the solution of equation (6.1) with Gauss elimination. If active and reactive power, or active power and voltage magnitude, are spec-ified at some nodes, then equation (6.1) can be solved repeatedly by iteratively adjusting the vector 1^ . The network may also contain nonlinear elements, such as 122 123 evil •< -1 1 1 1 1 1 1 1 1 1 j 1 1 1 1 1 1 1 1 1 1 1 1 1 1 j 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 j 1 1 1 1 1 1 1 1 1 j 0. 0.05 0.1 0.15 0.2 0-25 0.3 Time in Seconds M O - 1 Figure 6 . 1 : Generation of harmonics in filter currents saturable shunt reactors, nonlinear magnetizing inductances in transformers, etc. These nonlinearities produce harmonics. To include these harmonics in the steady-state solution is not simple, but iterative procedures have recently been suggested [55] which produce solutions at fundamental frequency as well as at the important harmonics. In ac/dc systems, the steady-state behaviour can be described with ac phasors at fundamental frequency on the ac side and with dc quantities on the dc side. In addition, there are harmonics on both sides. Experience has shown that the harmonics can be ignored in the initialization if the transient simulation is allowed to proceed over a few cycles from the approximate initialization without harmonics. 124 Figure 6.1 shows that within 30ms, the ac filter currents settled down to steady-state conditions with harmonics. If harmonics are ignored, then the steady-state solution of ac/dc systems can be found with well-known ac/dc load flow algorithms. Different solution techniques for an ac load flow are summarized in [56]. The ac/dc load flow is an extension of the ac load flow. Two approaches are used: (i) sequential solution and (ii) simultaneous solution. In the sequential solution [57,58,59,60,61,62], the ac system and the dc system are solved separately, and the interface variables are then adjusted iteratively to fulfill the steady-state converter equations and control equations. In the second approach [62,63,64,65,66], the equa-tions of both ac/dc systems are solved simultaneously. The sequential solution is simpler to implement in the existing steady-state solution module in the EMTP, and since convergence was good, it was chosen for this thesis project. The ac/dc initialization procedure is described first, followed by a numerical example. 6.2 A C / D C Initialization Procedure 6.2.1 Relationship between ac/dc parameters The ac and dc systems are coupled through the converter. To get the coupling equations, the effects of the converter on both systems have to be considered. The converter is represented as a balanced three-phase load (impedance or current source) in the ac system (whose value depends on what happens on the dc side) and as a voltage source in the dc system (whose value depends on what happens on the ac side). To derive the relationship between the ac and dc parameters, two assumptions are made here: • the harmonics in both systems can be neglected and • losses in the converters are neglected. The equation for the voltage source representing a converter is [30]: Ud=[atKELncos$ + {~l)xRcId}nb (6.2) 125 where Ud is the dc bus voltage of the converter , ELn is the RMS voltage of the ac bus of the converter (line-to-ground) , Id is the dc current of the converter , as is the transformer tap ratio from ac side to dc side(l : as) , Rc is the equivalent commutating resistance of one bridge , rib is the number of bridges of the converter , K 0 is the ignition angle a (rectifier) or (3 (inverter) , 3 ^ 7T 1 for rectifier or 2 for inverter The equation for the active power on both the ac and dc side is Pac = Pdc = -{-ifUdh • (6.3) While the active power is negative for an inverter and positive for a rectifier, the reactive power is negative for both rectifier and inverter. The approximate expression for the reactive power is Qac = -1 Pac I tan ^ , (6.4) cos V> ^  T F ¥ - = cos 6 + — . 6.5) The balanced three-phase load Pac — jQac can be represented in equation ( 6.1) either as a balanced three-phase voltage-dependent current source, or as a balanced three-phase voltage-dependent impedance, or as a combination of a fixed impedance and a voltage-dependent current source. The third option was chosen here because experience from stability studies has shown that this representation gives the fastest convergence [67]. The expression for the fixed impedance is 3E 2 " - P^JQZ ' (6-6) and the expression for the voltage-dependent current source is . = (Pac-jQac)-3IzjVL ,6 ? ] , K - l 126 where V^n is the phasor value of the line-to-ground voltage on the ac side and Izj is the phasor value of the current flowing through the fixed impedance Zj. The superscript * denotes the conjugate complex value of the phasor. 6 . 2 . 2 Algorithm During steady-state conditions, a converter may operate either on constant current control, on constant power control, or on constant extinction angle control (i.e. voltage control). All three control modes must be represented properly in the steady-state solution. For many cases, it is impossible to find the steady-state solution directly, and thus, an iterative solution scheme becomes the viable alternative. In this algorithm, the iteration scheme used is based on a direct solution of equation (6.1) for *V A by Gauss elimination with iterative corrections on 1^ . The active and reactive power in equations (6.3) and (6.4) are represented by three single-phase fixed impedances Zj from equation (6.6), which will enter into the diagonal elements of Y^A in equation (6.1) and a balanced three-phase voltage-dependent current source / , from equation (6.7). which will enter in 1^  in equation (6.1). The current source is computed by using the voltage VLn obtained from the previous iteration step. The method usually converges in six iterations. If the short-circuit impedance of the ac system is relatively high, then representing part of the load as a fixed impedance does not speed up convergence and a voltage-dependent current source would work equally well. While computing a steady-state solution, the algorithm may change the control modes of the converters, but the original control modes of the converters are re-stored for transient studies. If the control modes are altered during a steady-state solution, then the desired operating conditions may have been modified to allow the steady-state solution. The strategy of the algorithm is as follows: 1. Find the steady-state solution for the dc system, with one converter repre-sented as a voltage source and the other converters represented as the current sources. 127 DC System Solution **Initial Guess** Terminal Control D C Power Ref. Voltage Current Power Rectifier Current 0.000 0.000 1.600 0.000 Inverter-1 Power -400.000 0.000 -0.800 0.000 Inverter-2 Voltage 0.000 500.000 0.000 0.000 **Final So ution** Rectifier Current 0.000 503.861 1.600 806.177 Inverter-1 Power -400.000 500.994 -0.798 -400.000 Inverter-2 Voltage 0.000 500.000 -0.802 -400.794 D C Solution Converged in 3 Iterations A C System Solution * "Initial Guess** Terminal Tap Ignition J A C Bus Voltage A C Bus Voltage Angle ! Magnitude Phase Real Reactive Rectifier 1.0000 15.00 195.873 0.00 806.177 -312.360 Inverter-1 1.0000 22.71 281.626 0.00 -400.000 -145.999 Inverter-2 1.0000 22.74 281.097 0.00 -400.794 -146.420 **Final So ution** Rectifier 0.9399 15.00 208.408 -25.60 806.177 -312.360 Inverter-1 0.9756 22.71 288.675 0.00 -400.000 -145.999 Inverter-2 1.0432 22.74 269.459 5.490 -400.794 -146.420 A C Solution Converged in 27 Iterations Maximum voltage error = 0.0000765 Table 6.1: Results of the steady-state solution for the ac/dc system of Figure 5.9 2. Solve equation (6.1) iteratively for the ac side, with the active and reactive power specified for the converters (within transformer tap limits). 3. Check for violations of the transformer tap limits. 4. Repeat steps 1 to 3 if there is a mismatch between the ac and dc quantities in the coupling equations of the converters. The detailed description of the algorithm can be found in Appendix D. 128 6.3 Numerical Example The algorithm has been tested on the three-terminal ac/dc system described in Chapter 5 (Figure 5.9). This system is a monopolar dc system and the ac systems are not interconnected. The first converter is a parallel converter system operating in rectifier mode. The second and third converters are operating in inverter mode. These three converters are working on constant current control, constant power control and, constant voltage control, respectively. At each of these terminals, the transformer tap is allowed to vary continuously within ± 1 0 % of its nominal tap. The minimum and the maximum limits on the ignition angle for the rectifier are set to 13° and 17°, respectively. The algorithm computes the minimum limit on the ignition angle of all the inverters using a minimum extinction angle of 17°. The maximum limit on the ignition angle for all current-controlled and power-controlled inverters are arbitrarily set to 15° above the minimum limit of their ignition angle. The nominal ignition angle for the rectifier is set to 15°. For the inverters, the nominal ignition angles are set to their respective minimum ignition angles. Table 6.1 shows the results of the steady-state solution. The convergence of the solution is assumed if the maximum voltage error (i.e., the absolute value of the largest difference in the node voltages between two successive iteration steps) is less than 10 - 4 . The algorithm took 27 iterations for the ac solution to converge, ln contrast, an algorithm based on the Newton-Raphson method would typically require four to five iterations. Chapter 7 CONCLUSIONS This thesis investigates methods for the simulation of the transient phenomena in ac/dc systems. Methods for ac/dc steady-state initialization are discussed as well. Sections 7.1 and 7.2 review the major contributions in this thesis and Section 7.3 discusses the scope for future work. 7.1 Simulation of Transient The simulation of transient in an ac/dc system requires simple but practical mod-els of converters, converter transformers, and H V D C control systems. With this in view, the models of these components have been developed. These models were used in conjunction with the U B C - E M T P . The U B C - E M T P is capable of simulat-ing ac and dc networks including their filters, as well as nonlinear inductances of transformer magnetizing branches. The contributions made in this respect include a new converter model and a new generic inverter control. The highlights of these models are given in the following subsections. 7.1.1 Converter Model The converter model includes the representation of the converter and its trans-formers. The merits of the new converter model are: • it can handle all possible transformer connections; • it is capable of including or excluding snubber circuits; 129 130 • it is capable of simulating series and parallel converter configurations; • the time-varying topology of the converter is represented using network col-lapsing and overlapping algorithms [25]; • a converter, with its transformer, is represented using nodal equations that are relatively easy to program and are suitable for further generalization; • the solution algorithm is free of numerical oscillations [21,22,23]. 7.1.2 Control Model H V D C control systems in operation vary widely in design and implementation. It is impossible to include all the details of the actual control systems in a digital simulation. A generic model is needed which adequately describes the influence of the control system on the transients in the ac and dc networks. Such a generic model will contain a current control loop, a commutation margin control loop, and a converter firing control. The current control loop has been adequately described in [31,30]; however, the commutation margin control loop has not been discussed in detail in the literature. The new generic inverter control described in this thesis is a pseudo-open-loop control because the extinction angle 7 is not measured directly, but found indirectly from the relation between 7 and Udio- The firing angle a is computed from the relation between a, 7 , and commutation angle u. The determination of 7 depends solely on the measurement of Udi0. The pro-cedure for the measurement of Udio involves: • rectifying the converter ac bus voltage to get Ud,0', • filtering out the ripples in Udi0 by averaging; • employing a recursive fault detection method to speed up the averaging pro-cess. 7.1.3 Simulation The results of transient simulations of two-and multi-terminal systems (parallel converter systems) are presented in Chapters 4 and 5 to validate the new converter 131 and control models. The two-terminal results are compared with those obtained from the H V D C simulator [45] and the agreement is reasonably good. The results for the multi-terminal system (i.e., parallel converter systems) could not be com-pared with other simulation results because the simulation of parallel converter systems has not yet been reported in the literature. These transient simulations were carried out on the V A X 11/750 system, which required 8 s to 12 s (depending on the system details) of C P U time for 1ms of simulation. The computation time can be reduced further with optimized programming. 7.2 A C / D C Initialization The ac/dc initialization is a prerequisite for any ac/dc transient simulation. There is no proper ac/dc initialization technique available in the E M T P now. Thus, suitable algorithms for initialization were investigated. The algorithm presented in Chapter 6 is based on a sequential solution of the ac and dc systems. The steady-state solution of the ac or the dc system is obtained by an iterative scheme. This scheme is based on a direct solution of the nodal equations describing the ac or the dc network. The advantages of this algorithm are: • it can be easily implemented in the existing steady-state solution method of the E M T P ; • it has good convergence, and • the algorithm is fast. The simulations in Chapters 4 and 5 show that the ac/dc initialization is accurate enough. 7.3 Scope for Future Work The following are some of the interesting topics for future research. • There is a growing interest in multi-terminal systems, especially for small dc taps on existing dc lines. It is most likely that these taps will be connected 132 to weak (low short-circuit ratio) ac systems. Investigation of new control strategies to operate these dc taps will be of great interest. • The design of system parameters (i.e., the coordination of various actions depending on firing angles, transformer tap changers, filters, etc.) for an H V D C system becomes complex if the ac system is weak. The knowledge of frequency-dependent ac system impedance helps in the design. Also, this information will give a better understanding of the interaction between ac and dc systems. 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[43j Povh, D. and Schultz, W., Analysis of Overvoltage caused by Transformer Inrush Currents, I E E E Transaction on Power Apparatus and Systems, Vol. 97, July/Aug. 1978, pp. 1355-1365. [44] Bowles, J.P., Overvoltages in HVDC Transmission Systems caused by Trans-former Magnetizing Inrush Currents, IEEE Transaction on Power Apparatus and Systems, Vol. 97, Jan./Feb., 1974. [45] Persona] communication with Mats Hyttinen of A SEA Power System Center, New Berlin, Wisconsin. June, 1985. [46] Brandt, D., McKay, I.H., Rashwan, M . M . and Ranade, T.S., Paralleling and Deparalleling Tests on Nelson River Bipoles 1 and 2, I E E E Transaction on Power Apparatus and Systems, Vol. 103, April 1984, pp. 762-770. [47] Long, W.F. , Reeve, J . , McNichol, J.R., Harrison, R . E . and Bowles, J.P., Con-siderations for Implementing Multiterminal DC Systems, I E E E Transaction on Power Apparatus and Systems, Vol. 104, September 1985, pp. 2521-2530. [48] Reeve, J . , Multiterminal HVDC Power Systems, I E E E Transaction on Power Apparatus and Systems, Vol. 99, March/April, 1980, pp. 729-737. 138 [49] Jotten, R., Bowles, J.P., Liss, G. , Martin, C.J.B. , and Rumpf, E . , Control in HVDC Systems; The State of art Part II: Multiterminal Systems, CIGRE 14-07, 1980. [50] Lamm, U., Uhlmann, E . , and Danfors, P., Some Aspects of Taping of HVDC Transmission Systems, Direct Current, May 1963, pp. 124-129. [51] Ishikawa, I., Machida, T . , Watanabe, A . , Konishi. H. , and Murai, K. , Devel-opement of Centralized Control System for Multiterminal HVDC Transmission Systems, IEEE Winter Meeting, 1978, Conference paper No. A78 122-4. [52] Forest, R., Heyner, G. , Kanngiesser, K.W. , and Waldmann, H . , Multitermi-nal Operation of HVDC Converter Stations, IEEE Transaction on Power Apparatus and Systems, Vol. 88, July, 1969, pp. 1042-1052. [53] Sakuari, T . , Goto, K . , Irokawa, S., Imai,K., and Sakai, T . , A new control method for multiterminal HVDC transmission without fast communication sys-tems, IEEE Transaction on Power Apparatus and Systems, Vol. 102, May, 1983, pp. 1140-1150. [54] Nozari, F. , Grund, C . E . , and Hauth, R.L. , Current Order Coordination in Mul-titerminal DC System, IEEE Transaction on Power Apparatus and Systems, Vol. 100, Nov., 1981, pp. 4628-4635. [55] Dommel, H.W., Yan, A. , and Wei, S., Harmonics from Transformer Satura-tion, IEEE Transaction on Power Delivery, April 1986, pp. 209-215. [56] Stott, B., Review of Load Flow Calculation Methods, Proceedings of IEEE, Vol. 62, 1974, pp. 916-929. [57] Reeve, J . , Fahmy, G. and Stott, B., Versatile load flow method for multiter-minal HVDC systems, I E E E Transaction on Power Apparatus and Systems, Vol. 6, May/June 1977, pp. 925-932. [58] Arrillaga, J. and Sato, H . , Improved load flow technique for integrated ac/dc systems, Proceedings of IEE, No. 116, 1969, pp. 525-532. 139 [59] Ong. C M . , and Hamzei-nejad, A. , A general-purpose multiterminal dc load flow, I E E E Transaction on Power Apparatus and Systems, Vol. 100., July 1981, pp. 3166-3174. [60] Padiyar, K.R. and Sachchidanand, Load flow analysis of multiterminal HVDC/AC systems, IFAC Theory and Application of Digital Control, New Delhi, 1982, pp. 595-599. [61] Mahseredjian, J . , Lefebvre, S., and Mukhedkar, D., A multiterminal HVDC load flow with flexible control specification, I E E E Transaction on Power Apparatus and Systems, summer power meeting, 1985. [62] Arrillaga, J . , Arnold, C P . , and Harker, B.J . , Computer Modelling of Electric Power Systems, John Wiley, 1983. [63] Arrillaga, J . and Bodger, P., Integration of HVDC links with fast decoupled load flow solution, Proceedings of IEE, 1977, pp. 463-468. [64] Sheble, G.B and Heydt, G .T . , Power flow studies for systems with HVDC transmission, PICA Conference, 1975, pp. 223-228. [65] Braungel, D.A., Kraft, L . A . and Whysong, J .L . , Inclusion of DC converter and transmission equations directly in a Newton power flow, IEEE Transaction on Power Apparatus and Systems, Vol. 95, 1976, pp. 76-88. [66] Mathur, R . M . , and El-Marasafaway, M . M . , A new fast technique for load flow solution of integrated multiterminal dc/ac system, IEEE Transaction on Power Apparatus and Systems, Vol. 99, 1980, pp. 246-255. [67] Dommel, H.W., and Sato, N., Fast transient Stability Solutions, IEEE Trans-action on Power Apparatus and Systems, Vol. 91, 1972, pp. 1643-1650. Appendix A TOPICS R E L A T E D TO C H A P T E R 2 A . l Numerical Oscillation with Implicit Trape-zoidal Rule Consider a function y = J F{x)dx. (A.l) The equation of the implicit second-order trapezoidal rule, which is obtained from a first-order Taylor series, for the above function is [28] Vn+i = Vn + \\F{xn+1) + F(xn)) , (A.2) where h is the step size. Now consider a simple circuit with an inductance, as shown in Figure A . l . The diode in the circuit is modelled as an ideal switch, which opens when the current through it is going negative. When the diode is conducting, the expression for L 0 S Figure A . l : A simple inductor diode circuit. 140 141 n + 1 n+2 ^ n -1 / \ t / \ Figure A.2: Current and voltage variation in the inductor circuit, current i, using equation (A.2) would be t'n+l = in + ^ K + l + Vn] (A.3) Let the current (Figure A.2) through the inductance be zero at the nth step (i.e., in — 0 but vn ^ 0;) The diode opens after the nth step, causing the current to be at zero at the (n - f 1) step. To satisfy equation (A.3) under this condition, it follows that vn+1 = -vn Hence, the voltage oscillates around its true value of zero. The oscillations occur because the voltage jumps at the n-th step, and the function is not differentiable at that point. The backward Euler method, which uses only the latest value of the function, does not have this oscillation, but it has inherent damping. The best way to avoid numerical oscillations with the trapezoidal rule would be to detect when such discontinuities occur and reinitialize the variables of the equation appropriately. The reinitialization process, however, may not always be simple. In the case of a converter system, reinitialization is not a limitation. The solution algorithm of the new converter model automatically reinitializes the node voltages whenever such a discontinuity is encountered. 142 A.2 Open Bridge L 1 Matrix for Three-Phase Transformer Banks The open bridge L _ 1 matrix is formed by taking into account the transformer connection. The rows and columns of the open bridge L _ 1 matrix are partitioned into three sets. The first set contains the nodes p and n (shown in Figure 2.3). The second and third sets contain the nodes of the secondary and the primary of the converter transformer, respectively. The neutral node is included either in the primary set or in the secondary set or in both, depending on the type of transformer connection. The partitioned open bridge L" 1 matrix is shown below. B12 £13 B21 B 2 2 B 2 3 £31 B 3 2 B33 The partitioned matrices B22, B23, B32, and B33 altogether form the L _ 1 matrix of a three-phase transformer. Let the pth phase of the secondary winding of the transformer be connected to the nodes i and j. Similarly, let the pth phase of the primary winding of the transformer be connected to the nodes k and /. Therefore, the elements of the partitioned matrices B22, B23, B32, and B33 for the pth phase are formed as follows: = B22 = - t2 h = Bjj = B22 t2 Lp — nlk r>33 - Bkl 1 TP r>33 Bkk — R33 - Bu R 3 3 = Bkk • I Tp = B32 R 2 3 — t TP Bf3 = Bf D23 = BH t Tp = B32 E)23 = Bkj + t 143 D23 _ R 3 2 _ D23 ' °n - B,i - Bn - Y ' where Lv is the short-circuit inductance of the pth phase, t is the turns ratio, and B\\, B\\, 5*2, and denote the elements of the partitioned matrices B22, B23, B32, and B33, respectively. There is a total of sixteen entries for any pth phase. Superposition of these entries of all the phases gives the desired open bridge L _ 1 matrix. The partitioned matrices B11, B12, B2i, B13 and B31, respectively, are null matrices, as all the valves are not conducting. A . 3 Relation between the Internal and the Ex-ternal Nodes The new converter model computes the internal node voltages by using an algebraic relation between the internal and the external nodes. The relation between them can be obtained from the triangularized system matrix shown in Section 2.3.4. The relation is P//V; = -P;£V£ . (A.4) ~Prj] is an upper triangular matrix and V; is the internal node voltage vector. Therefore, V 7 can be computed by using backsubstitution. Two examples are used to illustrate the process of computing the internal node voltages. Consider the system shown in Figure 2.3. In the first example, let the transformer connection be wye-wye. For simplicity, it has been assumed that the short-circuit inductance of all phases of the transformer are equal to unity and the turns ratio is unity. The inductance of the smoothing reactor is unity. If valves 1 and 2 are conducting, then the matrices Py7, Pr]E would be P b ne P (1.0 0.0 -0 .5 > Pr7 = b 0.0 1.0 -1.0 , ne \ 0.0 1.0 , 144 and P P / E = b ne The expression for the node b voltage is N A B C Ne D 0.0 -0.5 0.0 0.0 0.5 -0.5 0.0 0.0 -1.0 0.0 1.0 0.0 -0.67 0.33 0.0 0.67 -1.0 -0.33 vB -f vne - vNe . (A.5) For the second example, a wye-delta connected transformer will be considered and the rest of the conditions unaltered as in example one. The matrices P J 7 , ~PrIE would be and P / * = P b N A B C Ne -0.33 -0.33 0.0 0.33 0.0 -0.80 0.40 -0.60 0.20 0.0 The expression for the node b voltage is vb = 0.8vN - 0AvA + 0.6rB - 0.2vc + 0AvD (A.6) From equations (A.5) and (A.6), it can be deduced that voltage oscillations cannot be present at the internal node voltages unless voltage oscillations are present at the externa] node voltages. Appendix B A T W O - T E R M I N A L H V D C S Y S T E M D A T A DC System Parameters A monopolar representation of a bipolar dc line is used for the test simulation. The monopolar dc line is modelled by using a single-phase distributed parameter line model. D C line parameters Resistance (D/mile) 0.0062 Inductance (mH/mile) 0.70789 Capacitance (/iF/mile) 0.04183 Length of the line (miles) 489 The value of the smoothing reactor used is 300 mH on both the terminals. D C Filter: A 3/12th harmonic filter is used both at the rectifier and at the inverter sides. The filter configuration is of type A. D C filter parameters R (fl) 15.0 U (mH) 0.084 L 2 (mH) 246.5 C , (/zF) 0.801 C 2 (/xF) 2.31 145 146 The rectifier and the inverter have the same ac system configuration, as shown in Figure 4.1. A C system parameters Parameters Rectifier Inverter L (mH) 172.00 128.80 R i (n) 3.97 1.30 R i (n) 2917.60 687.50 C (MF) 1.36 3.45 R N (17) 2.83 3.87 L N (mH) 34.00 25.00 A C filter parameters At rectifier Filter L (mH) R (n) Ci (/xF) C 2 (/xF) MVar Type 11th Tuned 47.27 9801 1.23 55.2 D 13th Tuned 32.27 6325 1.29 57.9 D High Pass-1 7.986 358.80 1.551 69.6 D High Pass-2 4.506 180.90 1.239 55.2 D Low Pass (3/5/7) 657.80 1300 1.299 10.70 58.3 C At Inverter 11th Tuned ' 70.83 0.70498 0.82093 68.8 B 13th Tuned 48.33 0.56852 0.86136 77.2 B High Pass 7.5 411.66 1.5932 164 D Refer to Figure B .1 for filter system configurations. Converter transformer parameters Rectifier Inverter Leakage inductance (mH) 15.72 15.72 Winding resistance (fl) 0.025 0.025 Nominal voltage ratio 345kV/206.2kV 500kV/202.4kV Magnetizing inductance (mH) 252" 544* Saturation voltage (kV) 263 s 3806 Value for saturated region (very large in unsaturated region). 6 ac side voltage (line-to-ground). J-c , A: Double Tuned B: Single Tuned C: Damped C Type nd c2: L D: 2 Order Damped Figure B.1: Filter system configuration. Control System Parameters Current controller Ti (ms) 0.78 0.78 T2 (ms) 23.4 23.4 K (deg/p.u. current) 85 85 V D C O L settings Tup (ms) 30 40 Tdn 0.08 0.08 0.66 0.66 Fault detection settings a 0.85 0.85 b 0.98 0.98 r0 0.40 0.40 r\ 0.55 0.55 A C / D C operating conditions Rectifier Inverter Nominal converter bus voltage (kV) 200" 289" Converter bus Magn. (kV) 204.81* 290.42' voltage Phase (deg) 0.29 0.37 Infinite bus Magn. (kV) 219.65 290.00 voltage Phase (deg) 24.26 -9.15 Reactive power required by converter (MVar) 320 320 Reactive power supplied by ac filters (MVar) 409 310 Short-circuit M V A (MVA) 1770 4825 Open circuit D C voltage (kV) 268.68 268.85 Nominal D C terminal voltage (kV) 500 500 DC terminal voltage (kV) 510 505.15 DC link current (kA) 1.6 1.6 Nomina] DC current (kA) 3.2 3.2 Ignition angle (deg) 15 157.3 Extinction ang' e (deg) 17 17 "ac side voltage (line-to-ground) Appendix C M U L T I - T E R M I N A L H V D C S Y S T E M D A T A C . l Parallel Converter System Data A C / D C operating conditions Rectifier Inverter Arm 1 j Arm 2 Arm 1 Arm 2 Converter bus voltage Magn. (kV) 204.81' 204.81' 288.67" 288.67' Phase (deg) -23.26 -23.26 9.82 9.82 Infinite bus voltage Magn. (kV) 220.0* 220.0' 290.0* 290.0" Phase (deg) 0.0 0.0 0.0 0.0 Open circuit D C voltage (kV) 268.49 268.49 268.66 266.66 Nominal D C terminal voltage (kV) 500 500 500 500 D C terminal voltage (kV) 509.63 509.63 504.78 504.78 D C link current (kA) 0.8 0.8 0.8 0.8 Ignition angle (deg) 15 15 157.3 157.3 Extinction angle (deg) 17 17 17 17 'ac side voltage(line-to-ground) C.2 Three-Terminal System Data The rectifier station described in Figure 5.9 is identical to the rectifier system in Figure 4.1. The second inverter station of Figure 5.9 is indentical to the inverter station described in the two-terminal case of Chapter 4. System parameters of these stations are given in Appendix B. The ac system of the first inverter station of Figure 5.9 has infinite short-circuit M V A (i.e., zero internal impedance). Both the inverter stations in Figure 5.9 have the same converter transformer parameters. 149 150 Control system parameters are taken from the two-terminal case (Chapter 4). D C filter parameters used in this case are taken from the two-terminal case. The dc line parameters and the ac/dc operating conditions are given below. D C line parameters Resistance (fi/mile) 0.0062 Inductance (mH/mile) 0.70789 Capacitance (/xF/mile) 0.04183 1 Length of the line (miles) rectifier to inverter-1 289 inverter-1 to inverter-2 200 A C / D C operating conditions Rectifier Inverter arm 1 arm 2 station 1 station 2 Converter bus j Magn. (kV) 208.41' 208.41' 288.67' 269.46' voltage • Phase (deg) -25.6 ; -25.6 0.0 5.49 Infinite bus Magn. (kV) 164.54' i 164.54* i 235.70' 228.63' voltage Phase (deg) 0.0 | 0.0 0.0 0.0 Open circuit D C voltage (kV) 265.50 265.50 266.66 266.16 Nominal DC terminal voltage (kV) 500 500 500 500 D C terminal voltage (kV) 503.86 503.86 500.99 500 DC link current (kA) 0.8 0.8 0.798 0.802 Ignition angle (deg) 15 15 157.3 157.3 Extinction angle (deg) 17 17 17 17 ac side voltage(line-to-ground) Appendix D A C / D C INITIALIZATION A L G O R I T H M The detailed description of the ac/dc initialization algorithm is as follows: S T E P I 1. Read ac/dc system parameters. 2. Form the nodal admittance matrices of the ac and dc systems. 3. Select the converter station which will control the dc voltage as a constant voltage node (user specified). 4. Initialize iteration counter to one. 5. Compute the current drawn by the voltage-controlled converter from the summation of current orders of all current controlled converters: 6. Let the nominal active power of the voltage-controlled converter be Pdc. Com-pute the initial guess of the node voltage at the dc terminal of the voltage-control converter: » r Pdcv ldV S T E P II 1. Represent the voltage-controlled converter as a voltage source with magnitude 151 152 2. Represent all other dc converters as dc current sources. The current sources are flowing into the nodes if the converters are rectifiers and flowing out of the nodes if they are inverters. 3. IF the converter is on current control T H E N the magnitude of the current source = current order E L S E the magnitude of the current source = Porder/Ud (initial guess may be the current order) E N D IF 4. Solve for the voltages at the nodes of the current-controlled converters and the current injection at the node of the voltage-controlled converter. 5. Compute the dc power for all the converters under power control. 6. For the converters on power control, check : IF \Porder ~ Pdc\ < C T H E N proceed to S T E P III E L S E Repeat STEP II END IF STEP III 1. Compute dc coupling parameter for all the converters IF rectifier T H E N E L S E K — ^ d i Tf T •T'-couplinq i ^c-^d nb K - £i - P T coupling — J^c-'d E N D IF 2. Compute the dc power of the converters using equation (6.2). 153 3. Compute the ignition angles of all inverters using the expression 4. Check the ignition angle limits for all converters: IF rectifier T H E N 13° > 6 > 17° E L S E IF current controlled inverter T H E N {&min + 15°) > 9 > 6 min E L S E IF voltage controlled inverter T H E N E N D IF 5. Initialize 6 for all converters: IF rectifier T H E N 6 = 15° E L S E 0 = Omin E N D IF 6. Set transformer tap af to nominal tap (only in first iteration). 7. Predict the magnitude of line-to-ground voltage of the ac bus of all converters (prediction for angles can be zero) and calculate cos Tfm i n Eln — •coupling asK cos 6 STEP rv 1. Compute the reactive power of all converters from equation (6.3). 2. IF this is the FIRST iteration T H E N • Compute the fixed impedance using expression (6.5) • Set the voltage-dependent current source to zero. E L S E Compute the variable current source using the expression (6.7) END IF 3. Update the ac bus voltage history of all converters. 4. Solve for the node voltages with equation (6.1). 5. Check for convergence with the following criteria for all converters: IF \ELn(old) - ELn(new)\ < e and \4>Ln{old) - 4>in(new)\ < t T H E N Proceed to S T E P IX Increment the iteration counter by one. IF maximum number of iteration limit is exceeded T H E N Proceed to S T E P VIII END IF STEP V 1. Modify the transformer tap using ^coupling ~ KELn cos0 2. IF af is not within ±10% of nominal tap settings T H E N IF converter is on voltage control T H E N Proceed to S T E P IV E L S E 6. 7. (a) Set a, equal to the limit which has been violated. (b) Modify the ignition angle using 9 = cos"1 { k c o u p l i n g ) \ asKELn J (c) IF control angle is outside the limits T H E N • Set 6 equal the limit which has been violated • Proceed to S T E P VI END IF END IF 3. Repeat STEP IV 5 VI 1. IF Upper and Lower limits of taps are violated T H E N Proceed to S T E P VII 2. Identify the converter with the largest tap violation (let the converter be the kth converter). 3. Compute As for the kth converter: A„ = or as as 4. IF kth converter is on voltage control T H E N • Modify Vc using Vc(new) = Vc(old)A! • Proceed to S T E P II E L S E • Modify dc bus voltage of the kth converter: Udk{new) = Udk{old)A$ 156 • Replace the current source at the dc bus of the kth converter by a voltage source of magnitude [/^(new). • Replace the voltage source at the dc bus of the voltage-controlled con-verter by a current source of magnitude Idv-• Solve for voltages at the nodes where current sources are connected. • Compute taps of all the converters using the latest dc bus voltages, nominal ignition angles, and known Ein and Id for all the converters. • IF recomputed taps exceed limits T H E N (a) Print Error Message: Control Allocation is not allowed (b) Stop END IF • Replace Vc by the latest value of the dc bus voltage of the voltage-controlled converter. • Proceed to S T E P III END IF S T E P V I I 1. Print Error Message: Both Upper and Lower limits of transformer taps are violated 2. Stop S T E P VIII 1. Print Error Message: Number of iteration exceeded the set limit 2. Stop S T E P LX 1. Update the ac bus voltages, the transformer taps, and ignition angles of all converters. 2. Return 

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