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UBC Theses and Dissertations

Design of a CMOS colour palette integrated circuit for a Telidon graphics display Cheng, Gordon 1983

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Design of a CMOS Colour P a l e t t e Integrated C i r c u i t f o r a T e l i d o n Graphics D i s p l a y by Gordon Cheng B.A.Sc, The U n i v e r s i t y of B r i t i s h Columbia, 1981 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES Department of E l e c t r i c a l E n g i n e e r i n g We accept t h i s t h e s i s as conforming to the r e q u i r e d standard THE UNIVERSITY OF BRITISH COLUMBIA August 1983 (c) Gordon Cheng, 1983 In presenting t h i s thesis i n p a r t i a l f u l f i l m e n t of the requirements for an advanced degree at the University of B r i t i s h Columbia, I agree that the Library s h a l l make i t f r e e l y available for reference and study. I further agree that permission for extensive copying of t h i s thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. I t i s understood that copying or publication of t h i s thesis for f i n a n c i a l gain s h a l l not be allowed without my written permission. Department of E l e c t r i c a l E n g i n e e r i n g The University of B r i t i s h Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date A u g u s t 5 , 1983 DE-6 (3/81) ABSTRACT i i The p r a c t i c a l i t y of a s i m p l i f i e d design method and a l g o r i t h m i c design t o o l s i n s u p p o r t i n g l a r g e s c a l e i n t e g r a t e d c i r c u i t d e s ign was e v a l u a t e d through the design of a custom CMOS i n t e g r a t e d c i r c u i t ( I C ) . The custom IC contained the c o l o u r map and d i g i t a l - t o - a n a l o g (DAC) c o n v e r s i o n f u n c t i o n s f o r a T e l i d o n graphics d i s p l a y t e r m i n a l . The d i g i t a l data i n the c o l o u r map determined the c o l o u r of the g r a p h i c s d i s p l a y and was converted to analog s i g n a l s to c o n t r o l the i n t e n s i t y of CRT e l e c t r o n guns. A s c a l e d down prototype was designed, f a b r i c a t e d and t e s t e d . The prototype was f u n c t i o n a l except f o r a small number of e r r o r s i n the l a y o u t . Subsequently a f u l l s c a l e prototype was designed. S i m u l a t i o n with the c i r c u i t s i m u l a t o r SPICE showed the c i r c u i t performance to be w e l l w i t h i n s p e c i f i c a t i o n . The s i m p l i f i e d design method and the a l g o r i t h m i c layout t o o l s p r o v i d e d an a f f o r d a b l e and workable means t o design ICs. Moderately l a r g e s c a l e i n t e g r a t e d c i r c u i t s c o u l d be designed f o l l o w i n g t h i s approach. The advantages of a l g o r i t h m i c layout c o u l d be combined with i n t e r a c t i v e g r a p h i c s on microcomputers to provide a g r e a t l y enhanced IC design support at a f f o r d a b l e c o s t s in the immediate f u t u r e . TABLE OF CONTENTS ABSTRACT ±± TABLE OF CONTENTS i i i LIST OF FIGURES v LIST OF TABLES v l ACKNOWLEDGEMENTS v i i 1.0 INTRODUCTION 1 1.1 S i m p l i f i e d Custom IC Design 5 1.2 A l g o r i t h m i c Design T o o l s 6 1.3 The Colour P a l e t t e IC Design P r o j e c t 11 1 .4 T h e s i s Work 14 2.0 THE TEL I DON TERMINAL 15 2.1 T e l i d o n Terminal Hsrdware and Operation Overview .... 15 2.2 D e s c r i p t i o n f o r The Colour P a l e t t e IC 17 2.3 The Colour P a l e t t e IC Development Plan 19 3.0 DESIGN OF THE COLOUR PALETTE SCALED PROTOTYPE 20 3.1 A r c h i t e c t u r e 20 3.2 The Colour P a l e t t e Prototype 22 3.3 C i r c u i t Operation 23 3.4 The Memory C e l l 29 3.5 Memory P e r i p h e r a l C i r c u i t s 32 3.6 Video Output C i r c u i t s '. 34 3.7 The M u l t i - P r o j e c t T e s t C hip 36 3.8 Test R e s u l t s 37 4.0 THE FULL SCALE COLOUR PALETTE IC DESIGN 40 4.1 The S t a t i c D i g i t a l - t o - A n a l o g Converter 41 5.0 REFINEMENT FOR THE MEMORY CIRCUIT 42 i v 5.1 Memory C e l l Design A l t e r n a t i v e s 42 5.2 The CMOS S t a t i c RAM C e l l C i r c u i t .44 5.3 Basic C i r c u i t Operation 46 5.4 Memory C i r c u i t S t a b i l i t y 48 5.4.1 Problems R e l a t e d to P r o c e s s i n g 48 5.4.2 Problems Re l a t e d to Sense Current 50 5.4.3 I n s t a b i l i t y R e l a t e d to C a p a c i t i v e C r o s s - c o u p l i n g .. 52 5.5 S i m u l a t i o n of Read Access S t a b i l i t y 53 5.6 A n a l y s i s of S i m u l a t i o n Data 55 5.6.1 D e r i v a t i o n of a Sense Current Discharge Model 56 5.6.2 Nominal C i r c u i t Area 61 5.6.3 The Memory C i r c u i t Design Chart 61 5.6.4 Memory C i r c u i t S e l e c t i o n 62 5.7 Design of a Dual Por t S t a t i c Memory C i r c u i t 65 5.8 Layout f o r the S i n g l e Port Memory C i r c u i t 67 6.0 CONCLUSION 71 BIBLIOGRAPHY 75 LIST OF FIGURES 1.1 The Custom IC Design Procedure 3 1.2 Custom IC Design Procedure With UBC PLAP 8 1.3 L e v e l s of C i r c u i t R e p r e s e n t a t i o n 9 1.4 The S t r u c t u r e of the PLAP Software 10 2.1 Major C i r c u i t F u n c t i o n s of a T e l i d o n Terminal 15 3.1 The A r c h i t e c t u r e of the Colour P a l e t t e C i r c u i t 21 3.2 The A r c h i t e c t u r e of the Colour P a l e t t e Prototype 24 3.3 Symbolic Logic Diagram f o r the Prototype 25 3.4 Processor to Memory Access Timing Diagram 26 3.5 CRT to Memory Access Timing Diagram 27 3.6 The S i x - t r a n s i s t o r SRAM C i r c u i t 31 3.7 The Q u a s i - s t a t i c Memroy C i r c u i t 3 1 3.8 The Colour P a l e t t e M u l t i - p r o j e c t Chip 3 7 5.1 The S i x - t r a n s i s t o r CMOS S t a t i c Memory C i r c u i t 45 5.2 The D.C. T r a n s f e r C h a r a c t e r i s t i c s of an I n v e r t e r 50 5.3 Memory C e l l P a r a s i t i c Coupling Capacitances 52 5.4 S i m u l a t i o n of the F i v e - t r a n s i s t o r C e l l 54 5.5 Sense Current Discharge Model 56 5.6 R e s i s t a n c e Model of Sense Current Discharge 58 5.7 P l o t of I n t e r n a l Read Time v s. (W/L)EFF and (W/L)NOM f o r the F i v e - t r a n s i s t o r C e l l 59 5.8 The U n i f i e d Memory C e l l Design Chart 60 5.9 P l o t of I n t e r n a l Read Time v s . (W/L)EFF and (W/L)NOM f o r the S i x - t r a n s i s t o r C e l l 63 5.10 The Dual-port Memory C e l l C i r c u i t 65 5.11 Layout of a S i n g l e Port CMOS S t a t i c Memory C e l l LIST OF TABLES v i 5.1 Access Time And C i r c u i t Area Of Some S i x - t r a n s i s t o r Memory C e l l s 65 5.2 Modes Of Operation For The Dual Port Memory C e l l 66 9 v i i ACKNOWLEDGEMENT I wish to thank P r o f e s s o r s L. Young, G. Schrack and P. Lawrence f o r t h e i r guidance and support i n my s t u d i e s . I owe s p e c i a l thanks to Pr o f . Young f o r a r r a n g i n g some very i n s i g h t f u l v i s i t s to major m i c r o e l e c t r o n i c s companies, as w e l l as to Dr. Colt o n of Northern Telecom and Mr. D. K l e t t of M i t e l f o r t h e i r h o s p i t a l i t y d u r i n g these v i s i t s . I am g r a t e f u l f o r the ideas and c o o p e r a t i o n of my c o l l e a g u e R. M i e l c a r s k i both i n the t h e s i s p r o j e c t and f o r h i s support as a p e r s o n a l f r i e n d without whom the t i m e l y completion of the t h e s i s p r o j e c t would have been im p o s s i b l e . I wish to express thanks to Mr. P. T h i e l of M i c r o t e l P a c i f i c Research f o r t a k i n g the major steps to secure my s c h o l a r s h i p funding, and a l s o f o r p r o v i d i n g me with the op p o r t u n i t y to l e a r n at MPR. I wish to thank Messrs. G. Schmiing and M. Pejskar f o r t h e i r kindness i n p r o v i d i n g much t e c h n i c a l h e l p i n the IC p r o j e c t . F i n a l l y , I would l i k e to thank the Research S e c r e t a r i a t of B.C. f o r my s c h o l a r s h i p award and the U n i v e r s i t y of B r i t i s h Columbia f o r p r o v i d i n g a tea c h i n g a s s i s t a n t s h i p to support my s t u d i e s i n t h i s program. 1 1.0 INTRODUCTION Custom i n t e g r a t i o n of e l e c t r o n i c c i r c u i t f u n c t i o n s on i n t e g r a t e d c i r c u i t s (IC) has f o r many years been p r a c t i s e d by manufacturers of high-volume, s p e c i a l i z e d e l e c t r o n i c s products to reduce p r o d u c t i o n c o s t and to achieve a c o m p e t i t i v e p o s i t i o n beyond that p o s s i b l e by using o f f - t h e - s h e l f ICs. Most e l e c t r o n i c s product manufacturers cannot e x p l o i t l a r g e s c a l e i n t e g r a t i o n (LSI) technology f o r two main reasons: the c o s t of IC design and f a b r i c a t i o n . The c o s t to a c q u i r e a l a r g e s c a l e i n t e g r a t e d c i r c u i t f a b r i c a t i o n technology and f a c i l i t y , estimated today at about $25 m i l l i o n US d o l l a r s , i s p r o h i b i t i v e l y high f o r most companies. A l t e r n a t i v e l y the use of commercial IC manufacturing f a c i l i t i e s are a v a i l a b l e but has t r a d i t i o n a l l y been d i f f i c u l t to arrange due to reasons of p r o p r i e t y and c o s t . In a d d i t i o n the f a b r i c a t i o n technology of commercial IC houses d i f f e r s u b s t a n t i a l l y such that an IC designed f o r a p a r t i c u l a r p r o c e s s i n g f a c i l i t y i s i n g e n e r a l not p o r t a b l e , hence the custom IC i s i n e f f e c t s i n g l e - s o u r c e d . The s i n g l e - s o u r c i n g of the c h i p which i s u s u a l l y a c r i t i c a l component of the product i s econ o m i c a l l y and l o g i s t i c a l l y unacceptable. The a v a i l a b i l i t y of custom ICs to the common e l e c t r o n i c f i r m improved g r e a t l y i n 1979 when Mead and Conway [Mead80] in t r o d u c e d the " s i l i c o n foundry" concept [Hon79], a job-shop type f a b r i c a t i o n f a c i l i t y f o r custom ICs. The process technology o f f e r e d i s s t a n d a r d i z e d as i s the i n t e r f a c e to the f o u n d r i e s . P r o c e s s i n g cost f o r each IC "run" i s reduced by the " m u l t i -p r o j e c t c h i p " concept where s e v e r a l IC designs are i n c o r p o r a t e d 2 on one d i e to share the mask making and f a b r i c a t i o n c o s t s . Fu r t h e r c o s t d i s t r i b u t i o n i s p o s s i b l e by i n c l u d i n g s e v e r a l d i e s on each wafer. Today IC prototypes can be f a b r i c a t e d at a c o s t of s e v e r a l thousand d o l l a r s i n s m a l l q u a n t i t i e s . The second major problem to the small company i s i n IC c i r c u i t d e s i g n . Although the p r o c e s s i n g c o s t of custom ICs i s w i t h i n reach, IC design c o s t s t i l l remains a major o b s t a c l e to f u l l y e x p l o i t i n g custom i n t e g r a t i o n . S e v e r a l problems are encountered i n custom IC d e s i g n . The f i r s t problem i s that the IC designer must l e a r n to b u i l d e l e c t r o n i c d e v i c e s such as t r a n s i s t o r s and l o g i c gates d i r e c t l y i n the new medium as p r o v i d e d by the f a b r i c a t i o n technology. A b a s i c understanding of d i g i t a l s o l i d s t a t e c i r c u i t and IC f a b r i c a t i o n technology i s e s s e n t i a l f o r most d i g i t a l l o g i c IC designs and i s q u i t e e a s i l y l e a r n e d . In c o n t r a s t to the ease i n g a i n i n g a workable knowledge of the process and c i r c u i t s , managing c i r c u i t complexity i s the major design problem [Spec83, Mead80]. Custom ICs u s u a l l y encapsulate a s i g n i f i c a n t amount of c i r c u i t s and system f u n c t i o n s on c h i p to maximize the c o s t e f f e c t i v e n e s s of the custom IC. As such the IC c o n t a i n s a l a r g e number of c i r c u i t elements ranging from thousands to hundred thousands of t r a n s i s t o r s . The IC design process i s f u r t h e r c o m p licated by the f a c t that IC design r e q u i r e s more steps than f o r d i g i t a l design with o f f - t h e - s h e l f components. A complete IC design procedure and the corresponding software and hardware support i s shown in F i g u r e 1.1. Note the many design steps as w e l l as the many t o o l s needed. The l a s t step in the IC design where the c i r c u i t d e s i g n s p e c i f i c a -t i o n f u n c t i o n p a r t i t i o n IT t e s t a b i -l i t y c h e c k u l o g i c d e s i g n l o g i c c h e c k u e l e c t r i c a l d e s i g n e l e c t r i c a l c h e c k c i r c u i t l a y o u t d e s i g n r u l e c h e c k c i r c u i t e x t r a c t i o n ! mask g e n e r a t i o n F i g u r e 1 . 1 C u s t o m I C d e s i g n p r o c e d u r e 4 elements are " l a i d out" g e o m e t r i c a l l y to b u i l d the p h y s i c a l d e v i c e s i s the most error-prone and most time consuming design step. S o p h i s t i c a t e d and expensive computer-aided design (CAD) t o o l s are e s s e n t i a l to a s s i s t with the l o g i c , e l e c t r i c a l and geometric layout steps i n IC d e s i g n . The c o s t of commercial software c i r c u i t s i m u l a t o r s i s t y p i c a l l y $50,000 to $500,000 US d o l l a r s . Although software s i m u l a t o r s and geometric design r u l e checking programs h e l p to e l i m i n a t e most design e r r o r s , s e v e r a l i t e r a t i o n s of design refinement and f a b r i c a t i o n are commonly needed to o b t a i n a useable IC. The a v a i l a b i l i t y of good IC design t o o l s to support e f f i c i e n t and c o r r e c t design i s c r i t i c a l to custom i n t e g r a t i o n c o n s i d e r i n g the c o s t of each design and the turn-around time of f a b r i c a t i o n . The CAD t o o l s used i n d e d i c a t e d IC design houses are capable of s u p p o r t i n g IC design extremely w e l l such that very complicated ICs can be c o r r e c t l y designed with r e l a t i v e l y l i t t l e e f f o r t . However the cost of such a s o p h i s c a t e d IC design s t a t i o n ranges from $30,000 to $500,000 US d o l l a r s and i s u s u a l l y too expensive f o r the sma l l e r company. Semicustom IC design p r o v i d e s a s o l u t i o n to the design complexity problem by p r o v i d i n g pre-designed c i r c u i t s that the IC designer can connect together on a s i n g l e c h i p to r e a l i z e the d e s i r e d c i r c u i t f u n c t i o n . The mainstream semicustom design approaches are the gate-array and the l i b r a r y c e l l approaches. The semicustom IC design c o n t r a c t i n g work i s c u r r e n t l y a very c o m p e t i t i v e business; as a r e s u l t e x c e l l e n t CAD and c i r c u i t d esign c o n s u l t a t i o n support are a v a i l a b l e to the c l i e n t . 5 1.1 S i m p l i f i e d Custom IC Design While i t i s p o s s i b l e to c o n t r a c t custom IC design, the economics of t o t a l dependence on f u l l custom or semicustom design houses may be unacceptable to the manufacturer who competes i n f a s t e v o l v i n g products such as o f f i c e automation or communication equipment. For the e l e c t r o n i c product manufacturer who wishes to a c q u i r e in-house custom or semicustom IC design support and e x p e r t i s e i n reasonable time and c o s t , the s o - c a l l e d s i m p l i f i e d design approach appears to be a v i a b l e a l t e r n a t i v e . The s i m p l i f i e d design approach was proposed by Mead i n 1979 [Mead80]. In essence the s i m p l i f i e d design approach a p p l i e s s i m p l i f i c a t i o n s and r e s t r i c t i o n s to IC e l e c t r i c a l and layout design r u l e s such that d i g i t a l IC design c o u l d be l e a r n e d q u i c k l y . Some c i r c u i t d e n s i t y i s s a c r i f i c e d i n making the s i m p l i f i c a t i o n s , but the IC d e s i g n e r ' s p r o d u c t i v i t y would be g r e a t l y i n c r e a s e d to allow f u n c t i o n a l , although u s u a l l y sub-optimal ICs to be designed q u i c k l y by d e s i g n e r s with l i t t l e e x p e r t i s e i n IC desi g n . I t i s p r o j e c t e d that the continuous advances i n p r o c e s s i n g technology would encourage l a r g e s c a l e i n t e g r a t i o n of complex and d i v e r s i f y i n g c i r c u i t f u n c t i o n s on ICs needed i n low to medium volume f o r h i g h l y s p e c i a l i z e d a p p l i c a t i o n s . In view of the design c o s t of custom LSI c i r c u i t s , i t would be w e l l j u s t i f i e d to make small s a c r i f i c e s i n c i r c u i t d e n s i t y to reduce design c o s t . F o l l o w i n g a s i m p l i f i e d design approach, system d e s i g n e r s may be i n v o l v e d d i r e c t l y i n system p l a n n i n g as w e l l as i n IC design thus reducing the time and the p o s s i b i l i t y of e r r o r i n i n t e r f a c i n g with s p e c i a l IC design groups. 6 The p r o p o s a l of s i m p l i f i e d IC design i s s i m i l a r to the d e f i n i t i o n of a programming language where the p r i m i t i v e statements are a p p r o p r i a t e l y d e f i n e d to f a c i l i t a t e data p r o c e s s i n g , and that s l i g h t s a c r i f i c e s i n code e f f i c i e n c y i s accepted i n r e t u r n f o r g r e a t e r i n c r e a s e i n programming p r o d u c t i v i t y . In the case of s i m p l i f i e d IC design, the p r i m i t i v e s are s i m p l i f i e d layout r u l e s and e l e c t r i c a l r u l e s f o r c i r c u i t design and l a y o u t . 1.2 A l g o r i t h m i c Design T o o l s In a d d i t i o n to d e f i n i n g the p r i m i t i v e s , i t was s t i l l necessary to decide how best to design and l a y out the i n t e g r a t e d c i r c u i t . To t h i s end Mead proposed that d i g i t a l LSI c i r c u i t s and systems should be designed with an a l g o r i t h m i c approach. The a l g o r i t h m i c approach extends the ideas of program s t r u c t u r e and a l g o r i t h m to IC d e s i g n . The idea of s t r u c t u r e i n IC design means that the design of a complex system such as an LSI c i r c u i t should proceed i n a h i e r a r c h i c a l manner. Although much p r a c t i s e d i n other areas of e n g i n e e r i n g , s t r u c t u r e d design was not e x p l i c i t l y or r i g o r o u s l y advocated i n LSI layout and design u n t i l Mead's work i n 1979. In s t r u c t u r e d design c i r c u i t f u n c t i o n s are modularized such that complex c i r c u i t s c o u l d be c o n s t r u c t e d h i e r a r c h i c a l l y from succ e e d i n g l y simpler c i r c u i t s . The idea of a l g o r i t h m i n v o l v e s the a p p l i c a t i o n of software programming concepts to IC l a y o u t by w r i t i n g programs to p l a c e the geometric f i g u r e s of the l a y o u t . Furthermore, programs can be w r i t t e n to a u t o m a t i c a l l y generate c e r t a i n c l a s s e s of c i r c u i t s 7 s u b j e c t to the a p p l i c a t i o n . A programmed l o g i c a r r a y generator i s a t y p i c a l example of a l g o r i t h m i c IC d e s i g n . A l g o r i t h m i c design i s f a c i l i t a t e d n a t u r a l l y by embedding i n a h i g h - l e v e l programming language the layout p r i m i t i v e s such as polygons and wires to combine the geometric and the a l g o r i t h m i c a s p e c t s of a l g o r i t h m i c IC d e s i g n . The program flow c o n t r o l and p r o c e d u r a l f e a t u r e s of a s t r u c t u r e d , h i g h - l e v e l programming language would f u r t h e r enhance a l g o r i t h m i c IC d e s i g n . A f u r t h e r advantage in embedding a l g o r i t h m i c l a y o u t i n a h i g h - l e v e l programming language was that an inexpensive but workable IC l a y o u t system c o u l d be obtained with a minimum of hardware r e q u i r e d beyond c o n v e n t i o n a l program development t o o l s except f o r the a d d i t i o n of a c o l o u r p l o t t e r to generate check p l o t s . The UBC PLAP software package i s such an a l g o r i t h m i c design t o o l s that the author programmed to support s i m p l i f i e d IC design at UBC. The package c o n s i s t s of a l a y o u t program PLAP and a p l o t t i n g program CIFP. The IC design procedure using PLAP f o r l a y o u t and SPICE f o r c i r c u i t s i m u l a t i o n i s shown i n F i g u r e 1.2. A t y p i c a l design begins with a t r a n s i s t o r l e v e l c i r c u i t schematic shown i n F i g u r e 1.3a. From the schematic the layout topology i s e x p l o r e d by drawing a " s t i c k " diagram as shown i n F i g u r e 1.3b. The s t i c k diagram preserves the t o p o l o g i c a l and p h y s i c a l p r o c e s s i n g i n f o r m a t i o n but e l i m i n a t e s geometric and design r u l e i n f o r m a t i o n to allow c o n c e n t r a t i o n upon g l o b a l and t o p o l o g i c a l layout p l a n n i n g . From the s t i c k diagram, a g r i d l a y o u t of the c i r c u i t such as that shown i n F i g u r e 1.3c i s drawn to s p e c i f y the geometric f e a t u r e s of the layout e x a c t l y . A f t e r the g r i d layout i s checked f o r layout design r u l e v i o l a t i o n s , f u n c t i o n p a r t i t i o n l o g i c d e s i g n e l e c t r i c a l d e s i g n S P I C E s i m u l a t i o n ! s t i c k d i a g r a m g r i d l a y o u t P L A P PLAP p r o g r a m d e s i g n s p i c i f i c a t ' n F i g u r e 1 . 2 C u s t o m I C d e s i g n p r o c e d u r e w i t h UBC PLAP 9 F i g u r e 1 . 3 a T r a n s i s t o r l e v e l s c h e m a t i c d i a g r a m F i g u r e 1 . 3 c L a y o u t o n g r i d p a p e r D e f c ( ' s h i f t r e g ' ) ; T e c h n o l o g y ( c m o s ) ; L a y e r ( m e t a l ) ; w i r e ( 2 , x O , y < 3 ) ; x ( x l ) ; B o x ( 2 0 , 3 0 , 6 8 , 1 1 4 ) ; E n d d e f ; F i g u r e 1 . 3 d R e p r e s e n t a t i o n i n a P L A P p r o g r a m F i g u r e 1 . 3 b S t i c k d i a g r a m 10 the designer w r i t e s a PLAP program to d e s c r i b e the layout as shown i n F i g u r e 1.3d. The PLAP program i s then compiled as a PASCAL program and executed to generate a r e p r e s e n t a t i o n of the c i r c u i t i n the C a l t e c h Intermediate Form (CIF) f o r storage [Mead80, Hon79]. The IC i s designed h i e r a r c h i c a l l y : simple c i r c u i t s ( c e l l s ) are f i r s t l a i d out, then more complicated c i r c u i t modules are c o n s t r u c t e d from p r e v i o u s l y designed c e l l s u n t i l the e n t i r e IC i s obt a i n e d . The CIF code f o r each c e l l may be p l o t t e d u s ing CIFP to check f o r layout r u l e v i o l a t i o n s and fo r documentation. I f e r r o r s are d i s c o v e r e d then the o r i g i n a l PLAP program i s mo d i f i e d , recompiled and executed to produce a new CIF f i l e f o r the updated c e l l . When the e n t i r e c h i p i s designed the CIF database i s sent to a mask house f o r mask making, and f a b r i c a t i o n of the IC then f o l l o w s . The s t r u c t u r e of the PLAP package i s shown i n F i g u r e 1.4. PLAP c o n s i s t s of four e x t e r n a l modules b u i l t on the PASCAL programming language system. P L A P p r i m i t i v e s P L A P l i b r a r y PLAP p r o g r a m s u s e r l i b r a r y PASCAL F i g u r e 1 . 4 The s t r u c t u r e o f t h e P L A P s o f t w a r e The PLAP p r i m i t i v e module c o n t a i n s a l l p r i m i t i v e geometric f e a t u r e s such as wires and polygons commonly used i n IC l a y o u t . 11 The PLAP l i b r a r y c o n t a i n s pre-designed c e l l s such as the inp u t -output pad d r i v e r and the programmed l o g i c a rray needed commonly in a l l IC designs. The PLAP source module c o n t a i n s the PLAP source codes to d e s c r i b e the layout which, when executed, causes the CIF code of the c e l l s to be generated. The user l i b r a r y c o n t a i n s c e l l s designed f o r a s p e c i f i c design p r o j e c t . C u r r e n t l y many companies and u n i v e r s i t i e s are experimenting with a l g o r i t h m i c design t o o l s . 1.3 The Colour P a l e t t e IC Design P r o j e c t The p r a c t i c a l i t y of the s i m p l i f i e d design approach and a l g o r i t h m i c layout t o o l s are i n v e s t i g a t e d through the design of the c o l o u r p a l e t t e c h i p , a custom i n t e g r a t e d c i r c u i t f o r T e l i d o n g r a p h i c s d i s p l a y . The design of the c o l o u r p a l e t t e c h i p may be viewed - as a t y p i c a l example f o r e s t a b l i s h i n g in-house IC design e x p e r t i s e to design LSI c i r c u i t s . The sponsor company i s i n v o l v e d i n the R/D of communication systems and o f f i c e automation products. The p o t e n t i a l consumer market f o r T e l i d o n t e r m i n a l s aroused i n t e r e s t s u f f i c i e n t l y to i n i t i a t e a R/D program i n t h i s a r e a . I t was rec o g n i z e d that custom i n t e g r a t i o n of g r a p h i c s d i s p l a y c o n t r o l f u n c t i o n was c r i t i c a l to making the product c o m p e t i t i v e i n the market of low-cost g r a p h i c s d i s p l a y hardware. Work began i n 1981 to e s t a b l i s h in-house design e x p e r t i s e and design support. The s i l i c o n foundry and m u l t i -p r o j e c t c h i p concepts provided immense he l p to t h i s end and access to an ISO-CMOS f a b r i c a t i o n process was arranged. Design support was e q u a l l y q u i c k l y e s t a b l i s h e d by i n s t a l l i n g the CMOS 1 2 Design System (CDS), a set of BASIC-based a l g o r i t h m i c design t o o l which was used f o r a l l MPC p r o j e c t d e s i g n s w i t h i n the company. The design of the c o l o u r p a l e t t e c h i p spearheaded the development of a p r o p r i e t a r y g r a p h i c s c o n t r o l l e r c h i p set f o r g r a p h i c s d i s p l a y . T h i s p r o j e c t i s motivated by the implementation of new communication i n f o r m a t i o n and database systems to communicate t e x t u a l and g r a p h i c a l data p o p u l a r l y a v a i l a b l e to the p u b l i c . The d e f i n i t i o n of Videotex, a t e r m i n a l -t o - t e r m i n a l t e x t / g r a p h i c s communication s e r v i c e was the f i r s t major step taken to e s t a b l i s h a p u b l i c d atabase/information network. In Videotex, a network of host computers are l i n k e d through telephone l i n e s to alphanumeric/graphics t e r m i n a l s . The T e l i d o n system i s a Canadian implementation of Videotex intended to support s o p h i s t i c a t e d t e x t and g r a p h i c a l i n f o r m a t i o n d i s p l a y . The success of T e l i d o n depends in p a r t upon the a v a i l a b i l i t y of low-cost network t e r m i n a l s . However, the development of these t e r m i n a l s has been slowed by the l a c k of a c l e a r i n t e r f a c e and p r o t o c o l standard thus c r e a t i n g problems i n i n t e r f a c i n g equipment from d i f f e r e n t manufacturers. The North American P r e s e n t a t i o n L e v e l P r o t o c o l Syntax (NAPLPS) d e f i n e d i n 1982 [NAPL81,Flem83] attempts to s o l v e the i n t e r f a c e problem by p r o v i d i n g a standard f o r the interchange of t e x t and g r a p h i c a l data f o r T e l i d o n - l i k e systems. O r i g i n a l equipment manufacturers now has a c l e a r g u i d e l i n e f o r the development of g r a p h i c s t e r m i n a l s s u i t a b l e f o r use i n T e l i d o n - l i k e systems. The r a s t e r g r a p h i c s data t e r m i n a l p r o v i d e s the most convenient and c o s t - e f f e c t i v e means to d i s p l a y t e x t and 13 g r a p h i c a l data. G r a p h i c a l data can be output q u i c k l y by s t o r i n g the p i c t u r e image in a d i g i t a l memory c a l l e d the " b i t map", and then output by scanning, thus r a s t e r g r a p h i c s i s o f t e n synonymous with bit-mapped g r a p h i c s . The memory r e q u i r e d i n good r e s o l u t i o n bit-mapped g r a p h i c s i s l a r g e , u s u a l l y on the order of megabytes. The amount of memory, however, does not determine p r o d u c t i o n c o s t s because high d e n s i t y memory i s a v a i l a b l e at very reasonable c o s t s . The product cost determinant i s the component count of the g r a p h i c s c o n t r o l f u n c t i o n c i r c u i t r y and t h i s count must be minimized to lower production c o s t . C i r c u i t s may be i n t e g r a t d on h y b r i d c a r r i e r s or on s i l i c o n ICs to reduce component count. C u r r e n t l y only a few g r a p h i c s c o n t r o l l e r ICs are commercially a v a i l a b l e . The NEC 7220 and the I n t e l 82720 are best known. In a d d i t i o n , s e v e r a l g r a p h i c s c o n t r o l l e r c h i p s e t s have been announced by AMD and Texas Instruments but these components are e i t h e r too expensive or w i l l not be a v a i l a b l e i n time. D i s p l a y c o n t r o l f u n c t i o n and h i g h speed d i g i t a l - t o - a n a l o g c o n v e r t e r s i n t e g r a t e d on t h i c k f i l m h y brids are c u r r e n t l y a v a i l a b l e but the cost of approximately $100 per u n i t i s not a c c e p t a b l e f o r the development of a h i g h volume, low-cost i n t e l l i g e n t g r a p h i c s data t e r m i n a l s u i t a b l e f o r use i n the market f o r T e l i d o n or other consumer g r a p h i c s t e r m i n a l s . Thus i t was d e c i d e d to custom d e s i g n the IC c h i p set to meet the need for T e l i d o n t e r m i n a l p r o d u c t i o n and a l s o to serve as a v e h i c l e to gain e x p e r t i s e i n d e s i g n i n g LSI w i t h i n the company. 14 1.4 T h e s i s Work The c o l o u r p a l e t t e f u n c i o n of a bit-mapped g r a p h i c s •displayer was i n t e g r a t e d on an ISO-CMOS s i l i c o n i n t e g r a t e d c i r c u i t . The c o l o u r p a l e t t e i n c l u d e s a d i g i t a l memory f o r d i s p l a y c o l o u r c o n t r o l and a d i g i t a l - t o - a n a l o g c o n v e r t e r to transform the c o l o u r code to analog s i g n a l s to c o n t r o l the CRT e l e c t r o n gun i n t e n s i t i e s at video r a t e . The design f o l l o w e d the s i m p l i f i e d design method and was supported by a set of a l g o r i t h m i c layout t o o l s . Te q u a l i t y of the d e s i g n , c i r c u i t performance, as w e l l as a d d i t i o n a l c i r c u i t refinement was ev a l u a t e d . F i n a l l y , the p r a c t i c a l i t y of the s i m p l i f i e d design method and the a l g o r i t h m i c layout t o o l s was eva l u a t e d based on the experience gained i n the c o l o u r p a l e t t e IC design and i n IC design work done at UBC us i n g the PLAP software. 1 5 2.0 TOE TELIDON TERMINAL The T e l i d o n t e r m i n a l hardware may be p a r t i t i o n e d i n t o f i v e major subsystems as shown i n F i g u r e 2.1. The major modules are the t e r m i n a l p r o c e s s o r , the communication module, the CRT c o n t r o l l e r , the frame b u f f e r , and the c o l o u r p a l e t t e module. An overview of system hardware and system o p e r a t i o n i s presented i n S e c t i o n 2. CRT c o n t r o l l e r 7K V t e r m i n a l p r o c e s s o r s c r e e n b u f f e r c o l o u r p a l e t t e c o m m u m c a t n m o d u l e F i g u r e 2 . 1 M a j o r c o n t r o l f u n c t i o n s o f a T e l i d o n t e r m i n a l 2.1 T e l i d o n Terminal Hardware and Operation Overview The t e r m i n a l i s l i n k e d t o the T e l i d o n network v i a a phone l i n e and communicates t e x t , g r a p h i c a l data and c o n t r o l s i g n a l s - f o l l o w i n g the NAPLPS standard [Flem83, NAPL81]. The t e r m i n a l p r o c e s s o r i n i t i a l i z e s the system, decodes NAPLPS p r o t o c o l , communicates with t e r m i n a l computer, and executes the T e l i d o n data p r o c e s s i n g f u n c t i o n s . The communication module p r o v i d e s a standard i n t e r f a c e 16 between the T e l i d o n t e r m i n a l and the network. The communication module i s a l s o r e s p o n s i b l e f o r port d r i v i n g and data co n v e r s i o n to support s e r i a l or p a r a l l e l busing of i n t e r n a l or e x t e r n a l s i g n a l s . The CRT c o n t r o l l e r s u p e r v i s e s the gen e r a t i o n of s i g n a l s to c o n t r o l the p o s i t i o n and i n t e n s i t y of the CRT e l e c t r o n guns i n order to d i s p l a y g r a p h i c a l data and t e x t . H o r i z o n t a l :and v e r t i c a l sweep i s generated by d i v i d i n g the master c l o c k s i g n a l . In a d d i t i o n , c e r t a i n video d i s p l a y f u n c t i o n s such as reverse v i d e o , b l i n k i n g , and v a r i o u s c u r s o r types are a l s o generated by the CRTC. The c o l o u r of each p i x e l on the CRT screen i s s t o r e d i n a d i g i t a l memory c a l l e d the screen b u f f e r . A p i x e l may be composed of s e v e r a l phosphor dots on the screen depending on the r e s o l u t i o n of the grap h i c s d i s p l a y and of the CRT. The c o l o u r of a p i x e l i s s t o r e d as a p o i n t e r to a word i n the c o l o u r p a l e t t e which c o n t a i n s the d i g i t a l code to c o n t r o l the CRT guns' i n t e n s i t y . The t e r m i n a l processor may modify the content of the screen b u f f e r i n accordance with the data to be d i s p l a y e d . The readi n g of the screen b u f f e r to generate video output i s c o n t r o l l e d by the CRTC. Each c o l o u r word i n the p a l e t t e has thr e e f i e l d s t o code the i n t e n s i t y of the red, green, and blue e l e c t r o n guns. In the T e l i d o n c o l o u r p a l e t t e , each primary c o l o u r has 16 i n t e n s i t y l e v e l s . A 4 - b i t b i n a r y code i s chosen to s t o r e the i n t e n s i t y code. For 16 c o l o u r s to be d i s p l a y e d , 16 c o l o u r words are needed. Thus a 16 by 12 b i t d i g i t a l memory needs to be b u i l t which allows any 16 of 4096 d i f f e r e n t c o l o u r s to be d i s p l a y e d simultaneously on the CRT. 17 2.2 F u n c t i o n a l D e s c r i p t i o n f o r the Colour  P a l e t t e I n t e g r a t e d C i r c u i t The c o l o u r p a l e t t e i n t e g r a t e d c i r c u i t combines the c o l o u r map and the d i g i t a l - t o - a n a l o g f u n c t i o n s of the T e l i d o n t e r m i n a l . The c o l o u r p a l e t t e i s a d u a l - p o r t r e g i s t e r f i l e of s i z e 16 x 12 b i t s , and i s accessed by both the t e r m i n a l p r o c e s s o r and the CRT c o n t r o l l e r . The t e r m i n a l processor has read and w r i t e access to the p a l e t t e v i a a 6-bit address bus and an 8 - b i t data bus. When the t e r m i n a l processor r e c e i v e s a NAPLPS s e l e c t c o l o u r command, i t w r i t e s the a p p r o p r i a t e c o l o u r word i n t o the c o l o u r p a l e t t e . Read access i s r e q u i r e d to determined system s t a t u s and f o r s e l f - t e s t i n g . A c o l o u r word i s w r i t t e n or read n i b b l e - w i s e as a 4- b i t p i x e l f i e l d . Data must be v a l i d w i t h i n 150 ns at maximum. When a c o l o u r word s t o r e d i n the p a l e t t e i s read f o r d i s p l a y , each of the three 4 - b i t i n t e n s i t y codes i s converted to an analog s i g n a l . Three d i g i t a l - t o - a n a l o g c o n v e r t e r s are needed to perform t h i s f u n c t i o n i n p a r a l l e l . A p i x e l data r a t e of 186 ns (about 5.38 MHz) i s r e q u i r e d . The read access time of the c o l o u r p a l e t t e r e g i s t e r f i l e i s expected to be approximately 50 to 100 ns. The c o l o u r word read out and co n v e r s i o n are p i p e l i n e d together by l a t c h i n g the data i n t o a p i p e l i n e r e g i s t e r f o r d i g i t a l - t o - a n a l o g c o n v e r s i o n while the next c o l o u r word read access proceeds. The PCLK s i g n a l c o n t r o l s the l a t c h i n g of data i n t o the p i p e l i n e r e g i s t e r . The PCLK s i g n a l , generated e i t h e r by the CRTC or by d i v i d i n g the master c l o c k d i r e c t l y , i s synchronized both to the video address and to the h o r i z o n t a l and v e r t i c a l sweep s i g n a l s . The speed of the d i g i t a l - t o - a n a l o g c o n v e r s i o n c r i t i c a l l y 18 determines the d i s p l a y r e s o l u t i o n . In order to a v o i d b l u r r i n g d u r i n g t r a n s i t i o n between p i x e l boundaries, the DAC should s e t t l e i n about 20 ns. High speed DACs are t r a d i t i o n a l l y f a b r i c a t e d i n b i p o l a r technology. Recently MOS technology gained p o p u l a r i t y f o r the i n t e g r a t i o n of low power, medium speed d i g i t a l and analog c i r c u i t f u n c t i o n s . In p a r t i c u l a r , D/As and A/Ds with 8 - b i t s or higher r e s o l u t i o n have been i n t e g r a t e d on many communication c o n t r o l l e r and f i l t e r - c o d e c c h i p s [ D 0 0 I 8 O ] , thus i t i s r e l a t i v e l y easy to design a 4 - b i t r e s o l u t i o n DAC with a l i n e a r i t y of +-(l/2) LSB. 19 2.3 The Colour P a l e t t e I n t e g r a t e d C i r c u i t Development Plan It was d e c i d e d to develop the c o l o u r p a l e t t e IC i n three phases: (1) design of a s c a l e d p r o t o t y p e ; (2) design of a f u l l s i z e p r o t o t y p e ; and (3) production refinements. The s c a l e d protoytpe was intended as a v e h i c l e to t e s t the b a s i c c i r c u i t s needed to b u i l d the c o l o u r p a l e t t e IC. C i r c u i t f u n c t i o n a l i t y and performance would be v a l i d a t e d to p rovide a c o l l e c t i o n of b u i l d i n g b l o c k s f o r the design i n phase two. The f u l l - s c a l e prototype b u i l d s on the r e s u l t s of phase one. Phase two had two o b j e c t i v e s . The f i r s t o b j e c t i v e was to t e s t the c i r c u i t performance of a f u l l s c a l e p a l e t t e IC b u i l t mostly from the c e l l l i b r a r y designed i n phase one. The second o b j e c t i v e i s t o t e s t the performance of the IC i n s i t u of the T e l i d o n t e r m i n a l hardware. In phase three the c o l o u r p a l e t t e IC would be p e r f e c t e d f o r p r o d u c t i o n . In p a r t i c u l a r , the IC's f u n c t i o n a l i t y , performance, and r e l i a b i l i t y w i l l be c h a r a c t e r i z e d before the IC would be r e l e a s e d f o r p r o d u c t i o n . At the time of w r i t i n g of t h i s t h e s i s the s c a l e d p rototype was designed, f a b r i c a t e d and t e s t e d with e x c e l l e n t r e s u l t s . The f u l l s c a l e p r o t o t y p e had a l s o been designed and was being f a b r i c a t e d . The a r c h i t e c t u r e , l o g i c , c i r c u i t designs and layout of the s c a l e d p rototype and the f u l l s c a l e c o l o u r p a l e t t e are be d e s c r i b e d i n S e c t i o n s 4 and 5 r e s p e c t i v e l y . 2 0 3.0 DESIGN OF THE COLOUR PALETTE SCALED PROTOTYPE The c o l o u r p a l e t t e prototype was f a b r i c a t e d through a m u l t i - p r o j e c t c h i p v e h i c l e . The area a l l o t e d to each design was 1500 by 1500 lambdas with lambda equal 2.5 urn. The main o b j e c t i v e of phase one was to design and t e s t a l l c i r c u i t f u n c t i o n s of the c o l o u r p a l e t t e . In order to stay w i t h i n the area al l o t m e n t and a l s o to reduce the work, a s c a l e d down v e r s i o n of the e n t i r e c i r c u i t was designed which co n t a i n e d a l l major c i r c u i t f u n c t i o n s of the f i n a l c o l o u r p a l e t t e . 3.1 A r c h i t e c t u r e The a r c h i t e c t u r e of the f u l l 12 b i t by 16 word c o l o u r p a l e t t e i s shown i n F i g u r e 3.1. The c i r c u i t can be p a r t i t i o n e d i n t o modules which perform data path f u n c t i o n s and c o n t r o l f u n c t i o n s . Data path modules perform a l l data storage, b u f f e r i n g and data ~ c o n v e r s i o n f u n c t i o n s . The c o l o u r p a l e t t e data path r e g i s t e r f i l e c o n s i s t s of three i d e n t i c a l 4 - b i t wide data paths, each of which c o n t a i n s the f o l l o w i n g c i r c u i t s : (1) d i g i t a l t o analog c o n v e r t e r (2) f o u r - b i t p i p e l i n e r e g i s t e r (3) f o u r - b i t by 16-word memory a r r a y (4) b i d i r e c t i o n a l b u f f e r f o r processor to memory access The c o n t r o l modules generate the s i g n a l s needed t o c o n t r o l memory a c c e s s . These i n c l u d e the f o u r - b i t wide and w r i t e s i g n a l s f o r p r o c e s s o r to memory access , and the t w e l v e - b i t (word) wide read s i g n a l s f o r the video c o l o u r read-out. 21 v i d e o a d d r e s s r p r o c e s s o r a d d r e s s C S ' R / W E a d d r e s s d e c o d e r c o n t r o l s i g n a l g e n 3 16 x 4 RAM 3 16 x 4 RAM 16 x 4 RAM F T b i d i r e c t i o n a l d a t a b u s t r i -s t a t e b u f f e r c P P L REG r e d D/A P P L REG D/A P P L REG D/A > > g r e e n . b l u e F i g u r e 3 . 1 T h e a r c h i t e c t u r e o f t h e c o l o u r p a l e t t e I C 22 The c o n t r o l modules a r e : (1 ) video y-decoder (2) processor y-decoder (3) processor x-decoder (4) c o n t r o l s i g n a l generator The o p e r a t i o n , c i r c u i t and layout of each of the major modules are d e s c r i b e d i n the succeeding s e c t i o n s . 3.2 The Colour P a l e t t e Prototype The c o l o u r p a l e t t e p rototype i n c l u d e d a l l c i r c u i t f u n c t i o n s necessary f o r the f u l l s c a l e p a l e t t e c h i p . The c i r c u i t s i n c l u d e d were a 4 - b i t by 4-word memory a r r a y , a y-decoder f o r four words, and an x-decoder f o r processor a c c e s s . A l s o i n c l u d e d were the vide o c i r c u i t s which c o n t a i n e d a 4 - b i t r e s o l u t i o n d i g i t a l - t o -analog c o n v e r t e r and p i p e l i n e r e g i s t e r . A c o n t r o l s i g n a l generator was i n c l u d e d as w e l l to generate s i g n a l s to c o n t r o l memory read/write or st o r a g e . The a r c h i t e c t u r e of the c o l o u r p a l e t t e prototype i s shown in F i g u r e 3.2. The c o l l e c t i o n of f u n c t i o n s in the c o l o u r p a l e t t e p r o t o t y p e i s e x a c t l y the c i r c u i t r y needed to c o n t r o l the i n t e n s i t y of one CRT e l e c t r o n gun, hence i t i s p o s s i b l e to t e s t the dynamic o p e r a t i o n of the system. To design f u l l - s c a l e c o l o u r p a l e t t e , the s i n g l e c o l o u r c i r c u i t s three times with the memory depth expanded to s i x t e e n words. A l l c e l l i n the c o l o u r p a l e t t e prototype were designed to d r i v e l o a d to be found i n the f u l l c o l o u r p a l e t t e c h i p , hence 23 these c e l l s can be used d i r e c t l y i n the design of the f u l l s c a l e c o l o u r p a l e t t e c h i p . T h i s approach minimizes the e r r o r s i n proceeding from phase one to phase two d e s i g n . 3.3 C i r c u i t Operation The symbolic l o g i c diagram of the prototype i s found i n F i g u r e 3.3. Chip s e l e c t CS, c h i p enable E and pr o c e s s o r to memory access mode R/W perform c o n v e n t i o n a l c o n t r o l f u n c t i o n s . The p r o c e s s o r p r o v i d e s s i x address b i t s A5 to AO. Address b i t s A5,A4 choose one of four n i b b l e s from each c o l o u r word, and b i t s A3 to AO choose one of s i x t e e n c o l o u r words. Only one n i b b l e per word and four words are designed f o r the pro t o t y p e . Word s e l e c t i s performed by the y-decoder while n i b b l e s e l e c t i o n i s the the task of the x-decoder. A l l address b i t s are b u f f e r e d to generate the t r u e and complement s i g n a l s needed to d r i v e true complementary gates. The c h i p c o n t r o l s i g n a l s l i k e w i s e are b u f f e r e d and bussed to the c o n t r o l s i g n a l generator. An i n t e r n a l read s i g n a l R and w r i t e s i g n a l W are generated to c o n t r o l memory read, w r i t e and storage f o r each n i b b l e . The R and W s i g n a l a l s o c o n t r o l s the d i r e c t i o n of data propagation through the b i d i r e c t i o n a l b u f f e r between the memory a r r a y and the output pads. The processor to memory access t i m i n g i s shown i n F i g u r e 3.4. The E s i g n a l i n i t i a t e s the execution of the memory access o p e r a t i o n a f t e r the c h i p i s s e l e c t e d and a f t e r the access mode i s set p r o p e r l y . Although only one c o l o u r p a l e t t e i s expected to be used i n the T e l i d o n t e r m i n a l , CS i s i n c l u d e d to a n t i c i p a t e 24 v i d e o a d d r e s s 4 y' ] v i d e o Y d e c o d e r p r o c e s s o r a d d r e s s -f H p r o c Y 7n I A d e c o d e r i n t e n s i t y c o n t r o l ( a n a l o g ) b i d i r e c t i o n a l d a t a b u s F i g u r e 3 . 2 T h e a r c h i t e c t u r e o f t h e c o l o u r p a l e t t e p r o t o t y p e a d d r e s s A5 A 5 ' A5 A4 A4 "A4 1 S 1 = ( C S + R / W ' ) ' = C S ' . R / W ' S 2 = ( C S + R / W , + E , ) , = C S ' . R / W . E S 2 ' S2 C S ' R/W E CS' R/W S2 ( w r i t e ) SI ( r e a d ) SI "ST F i g u r e 3 . 3 C o l o u r p a l e t t e s y m b o l i c l o g i c d i a g r a m w o r d s e l e c t YP=(A3+A2+A1+A0)' = A 3 ' . A 2 ' . A l * . A 0 1 memory c e l l DP ( d a t a ) R,W DATA READ DATA WRITE x x x x x x x * IK 3 -m i n max n o . t i m e ( n s ) ( n s ) 1 A d d r e s s d e c o d i n g 2 I n t e r n a l memory r e a d t i m e 3 Memory a c c e s s t i m e f r o m E v a l i d 0 150 4 R e a d d a t a v a l i d t i m e 100 5 R e a d d a t a h o l d t i m e 2 0 50 6 Memory w r i t e d a t a d e l a y f r o m E v a l i d —— 7 W r i t e d a t a s e t - u p t i m e 20 8 W r i t e d a t a h o l d t i m e 20 50 9 A d d r e s s m R / W ' , CS h o l d t i m e 20 50 10 E c l o c k c y c l e t i m e 5 0 0 5 0 0 F i g u r e 3 . 4 P r o c e s s o r - t o - c o l o u r p a l e t t e memory a c c e s s t i m i n g d i a g r a m VIDEO WORD SELECT MEMORY DATA t i m e m i n max n o . ( n s ) ( n s ) i V i d e o a d d r e s s d e l a y a f t e r P C L K . . . 20 2 V i d e o a d d r e s s d e c o d i n g d e l a y 3 Memory d a t a r e a d a c c e s s t i m e ( i n t e r n a l ) — -4 Memory d a t a v a l i d t i m e ( i n t e r n a l ) 6 V i d e o d a t a r e a d a c c e s s t i m e f r o m P C L K v a l i d 120 5 Memory d a t a h o l d t i m e ( i n t e r n a l ) 2 0 7 P C L K c y c l e t i m e 186 186 F i g u r e 3 . 5 CRT c o n t r o l l e r ( v i d e o ) - t o - c o l o u r p a l e t t e a c c e s s t i m i n g d i a g r a m 28 the p o s s i b i l i t y of bank s w i t c h i n g to allow f a s t exchanges of p a l e t t e s f o r f u t u r e g r a p h i c s c a p a b i l i t y enhancements. Address decoding begins immediately a f t e r a l l inputs CS,E,R/W become v a l i d . The y- and x-decode o p e r a t i o n proceed i n p a r a l l e l . Once a memory c e l l i s s e l e c t e d , data can be read out or w r i t t e n i n t o memory. The w r i t e and read access are r e l a t i v e l y f a s t i n comparison to the address decode d e l a y . The address decode and word s e l e c t delay i s expected to dominate the memory access time because of the l o a d presented by many memory c e l l s to the address decode c i r c u i t s . The time that the memory output data i s h e l d a f t e r the address and c o n t r o l s i g n a l s become i n v a l i d i s obtained i n d i r e c t l y from the delay a r i s i n g from address decode s i n c e no change i n the output i s p o s s i b l e u n t i l the new values of CS, R/W and E have propagated through the c o n t r o l s i g n a l generator to change the i n t e r n a l R and W s i g n a l s . T h i s delay i s i d e n t i c a l to the address decode and s e l e c t d e l a y , which i s expected t o be at l e a s t 20 ns. In the o p e r a t i o n of the video s e c t i o n , the video addresses P3 to PO are decoded by the video y-decoder to s e l e c t the c o l o u r word to output to the d i g i t a l - t o - a n a l o g c o n v e r s i o n c i r c u i t . The c o l o u r word i s l a t c h e d i n t o the p i p e l i n e r e g i s t e r by the PCLK s i g n a l . The data i s h e l d i n the p i p e l i n e r e g i s t e r f o r the d i g i t a l - t o - a n a l o g c o n v e r t e r f o r a f u l l PCLK c y c l e . N o t i c e that the a memory access c o n f l i c t can a r i s e when a processor w r i t e s i n t o a memory c e l l s i m u l t aneously as the c e l l i s read by the video c i r c u i t . T h i s c o n f l i c t cannot be avoided because the PCLK and the t e r m i n a l processor c l o c k s are not 29 synchronized and no handshaking i s used to c o o r d i n a t e t h e i r memory a c c e s s e s . F o r t u n a t e l y such a c o n f l i c t w i l l occurs only r a r e l y because processor w r i t e s occur seldomly once the p a l e t t e c o l o u r s are s e t . I f a c o n f l i c t does occur, a screen p i x e l w i l l d i s p l a y an u n p r e d i c t a b l e c o l o u r f o r the d u r a t i o n of one PCLK c y c l e of 186 ns. T h i s c o n f l i c t t h e r e f o r e does not s e r i o u s l y a f f e c t the q u a l i t y of the g r a p h i c s d i s p l a y . 3.4 The Memory C e l l The memory c e l l s t o r e s one b i t of in f o r m a t i o n to code the i n t e n s i t y of the CRT e l e c t r o n gun. The memory c o u l d be designed i n s t a t i c or dynamic c i r c u i t s [Elma8l, Howe82]. The s t a t i c memory c e l l i s b a s i c a l l y a b i s t a b l e c i r c u i t . The advantages of the s t a t i c memory are i n i t s low stand-by power consumption and in the s i m p l i c i t y of c i r c u i t design [ K l e i 6 9 ] . The disadvantage of s t a t i c memory i s the l a r g e c i r c u i t area r e l a t i v e to dynamic memory. The dynamic memory s t o r e s i n f o r m a t i o n as a small charge on MOS c a p a c i t o r s . Extremely h i g h c i r c u i t d e n s i t y i s achieved by the use of very small c a p a c i t o r s f o r data storage [Abot73]. The charge s t o r e d on the MOS c a p a c i t o r i s not permanent, however, because charge i s l o s t through t r a n s i s t o r leakage. Data l o s s i s avoided by p e r i o d i c a l l y r e p l e n i s h i n g the charge s t o r e d on the MOS c a p a c i t o r . T h i s o p e r a t i o n , c a l l e d memory r e f r e s h , r e q i r e s a d d i t i o n a l o f f - c h i p memory support c i r c u i t r y . The so c a l l e d " p s e u d o - s t a t i c " RAMs i n t e g r a t e the r e f r e s h s i g n a l generator onto the memory c h i p to r e l i e v e the user of the r e f r e s h task. On-chip r e f r e s h g e n e r a t i o n , though convenient to the user, adds 30 complexity to the IC de s i g n . In view of our modest IC design experience i n ISO-CMOS and of time c o n s t r a i n t , i t was decided t o implement the c o l o u r p a l e t t e memory ar r a y as a s t a t i c memory. Two kinds of s t a t i c c i r c u i t s , completely s t a t i c or " q u a s i - s t a t i c " c i r c u i t s may be used to r e l i z e the s t a t i c memory c e l l . The most common s t a t i c memory c e l l i s the s i x - t r a n s i s t o r c e l l shown i n F i g u r e 3.6. The memory element i s a b i s t a b l e c i r c u i t b u i l t by a c r o s s - c o u p l e d i n v e r t e r p a i r . The output nodes to the data buses are gated by a p a i r of t r a n s m i s s i o n gates. Data i s loaded i n t o the memory c e l l simply by e n a b l i n g the t r a n s m i s s i o n gates and then f o r c i n g the b i s t a b l e i n t o the d e s i r e d s t a t e . Data read-out may be e i t h e r i n the s i n g l e - e n d e d or the complementary mode. Des p i t e i t s apparent s i m p l i c i t y , the design of the completely s t a t i c memory c e l l r e q u i r e s c a r e f u l c o n s i d e r a t i o n of the noise i n j e c t e d i n t o the c e l l d u r i n g data read by the data bus sense c u r r e n t and of the data l i n e t r a n s i e n t n o i s e coupled i n t o c e l l s s h a r i n g the same data l i n e . The presence of t h i s noise c o u l d cause' p a r a s i t i c s t a t e change i n the memory and cause s o f t e r r o r s . A d e t a i l e d d i s c u s s i o n of the s t a t i c memory c e l l i s given i n S e c t i o n 5. The q u a s i - s t a t i c memory c e l l , shown i n F i g u r e 3.7 pr o v i d e s a compromise between s i m p l i c i t y in the memory c e l l c i r c u i t and in memory access c o n t r o l . The q u a s i - s t a t i c memory c e l l needs no r e f r e s h i n the continuous storage mode, but the b i s t a b l e i n v e r t e r p a i r c r o s s - c o u p l i n g i s switched d u r i n g memory w r i t e . B i s t a b l e c r o s s - c o u p l i n g s w i t c h i n g adds c i r c u i t t o the c o n v e n t i o n a l memory c e l l where only the t r a n s m i s s i o n gates are switched d u r i n g memory ac c e s s . VDD SELECT SELECT DATA L _ _ 5 -I 1 DATA VSS F i g u r e 3 . 6 T h e 6 - t r a n s i s t o r CMOS s t a t i c memory c e l l WRITE WRITE WRITE DATA F i g u r e 3 . 7 T h e q u a s i - s t a t i c memory c e l l 32 The c o l o u r p a l e t t e memory c e l l design b a s i c a l l y followed the c i r c u i t of F i g u r e 3.7. The gated i n v e r t e r combines the CMOS complementary t r a n s m i s s i o n gate and the CMOS i n v e r t e r to reduce c i r c u i t area [Susu73]. A d d i t i o n a l i n v e r t e r s are i n s e r t e d to b u f f e r the data output such that sense a m p l i f i e r s w i l l not be needed. In the lay o u t of the memory c e l l and memory a r r a y , data l i n e s were wired i n the metal l a y e r and c o n t r o l l i n e s were wired in the p o l y s i l i c o n l a y e r to minimize propagation delay i n the data path. The power busses were a l l wired i n the metal l a y e r fo r s i m p l i c i t y although the d i f f u s i o n l a y e r c o u l d be used [ I s o b 8 l , Howe8l]. 3.5 Memory P e r i p h e r a l C i r c u i t s Memory p e r i p h e r a l c i r c u i t s are the address decoders and data read out c i r c u i t r y . Address decoding can be dynamic or" s t a t i c . S t a t i c memory decoding i s achieved by us i n g s t a t i c CMOS l o g i c gates. The s i m p l i c i t y i n s t a t i c decoding i s obtained at the cost of c i r c u i t area because a f u l l y symmetric CMOS l o g i c gate r e q u i r e s that both N and P channel t r a n s i s t o r s to have equal c u r r e n t s o u r c i n g / s i n k i n g c a p a b i l i t y to ensure equal r i s e and f a l l times. In the case of address s e l e c t s , equal s e l e c t r i s e and f a l l times are necessary to minimize the i n t e r a c t i o n between the s e l e c t e d and u n s e l e c t e d memory c e l l s s h a ring the same b i t l i n e s [ F r i e 6 8 ] . The s t a t i c CMOS l o g i c gate consumes much f o r two reasons. F i r s t , the P t r a n s i s t o r channel width-to-l e n g t h r a t i o must be 2 to 2.5 times that of the N t r a n s i s t o r 33 because the process parameter f o r the.P channel t r a n s i s t o r i s smaller than that of the n channel t r a n s i s t o r by the same f a c t o r [Burn64, Cher69]. Second, both the true and the complement of a l l c o n t r o l s i g n a l s are needed f o r the o p e r a t i o n of t r u e l y complementary c i r c u i t s . In terms of c i r c u i t area, the t r u e CMOS s t a t i c address decoder i s p r a c t i c a l only f o r decoding a small number of address i n p u t s . Dynamic decoding i s used i n LSI memory where a l a r g e number of address inputs are decoded. By t r a d i n g c i r c u i t complexity f o r layout area, the dynamic decoder consumes l e s s c i r c u i t area r e l a t i v e to the s t a t i c decoder. A precharge technique i s used to charge up the output node dynamically thereby making lo a d d e v i c e s unnecessary. Precharging saves more than h a l f the c i r c u i t area because the P channel p u l l u p s which occupy about twice the N channel t r a n s i s t o r area are now unnecessary. Complementary input s i g n a l s are s t i l l needed of course. The disadvantage i n dynamic decoding i s that the precharge c o n t r o l must be generated from an e x t e r n a l l y s u p p l i e d s i g n a l to c o n t r o l the precharge o p e r a t i o n . Obviously the precharge c o n t r o l s i g n a l cannot be d e r i v e d from the CS,E, or R/W inputs because a c h i p may be c o n t i n u o u s l y p l a c e d i n the read or w r i t e mode while addresses change. A l t e r n a t i v e l y , the precharge c o n t r o l can be generated on c h i p by d e t e c t i n g an address change [Stew77]. For the c o l o u r p a l e t t e , only four b i t s need to be decoded to s e l e c t one of s i x t e e n c o l o u r words. Since the number of address i n p u t s was manageably s m a l l , the s t a t i c decoder was the most s u i t a b l e decoding method. In the layout of the x and y-decoders, the complementary address s i g n a l s were bussed between 34 the N and P channel t r a n s i s t o r s forming a c r o s s - p o i n t g r i d with the N to P channel b r i d g e s . The decoder l o g i c i s programmed simply by p l a c i n g c o n t a c t s at a p p r o p r i a t e c r o s s - p o i n t s . 3.6 Video Output C i r c u i t s The video output s e c t i o n c o n s i s t e d of the d i g i t a l - t o - a n a l o g c o n v e r t e r and the p i p e l i n e r e g i s t e r . The p i p e l i n e r e g i s t e r was a q u a s i - s t a t i c master sl a v e r e g i s t e r c i r c u i t c o n t a i n i n g two q u a s i -s t a t i c r e g i s t e r s such as that d e s c r i b e d i n S e c t i o n 3.4. The p i p e l i n e r e g i s t e r was c l o c k e d by the video read c l o c k PCLK to perform the sample and hold f u n c t i o n s i n order that the c o l o u r word data presented to the d i g i t a l - t o - a n a l o g converter was v a l i d at a l l times except f o r a b r i e f i n s t a n t when new data was l a t c h e d i n t o the p i p e l i n e r e g i s t e r s l a v e stage. In the sampling i n t e r v a l , data was c l o c k e d i n t o the master r e g i s t e r on PCLK'. T h i s data was passed to the sla v e r e g i s t e r on PCLK and h e l d f o r the d i g i t a l - t o - a n a l o g c o n v e r t e r , hence the p i p e l i n e r e g i s t e r output was v a l i d f o r almost a l l of the PCLK p e r i o d . The d i g i t a l - t o - a n a l o g c o n v e r t e r transforms a f o u r - b i t c o l o u r i n t e n s i t y code to an analog s i g n a l to c o n t r o l the CRT e l e c t r o n guns. The primary requirements of the DAC are high speed and low r e s o l u t i o n . The two c o n v e n t i o n a l approaches [Greb72] to b u i l d DACs are vo l t a g e and c u r r e n t s w i t c h i n g c i r c u i t s . The c u r r e n t s w i t c h i n g DAC c o n s i s t s of a c o l l e c t i o n of b i n a r y weighted c u r r e n t sources. The c u r r e n t sources are e i t h e r switched to ground or to a c u r r e n t summer depending on the data input which c o n t r o l the 35 s w i t c h i n g network. The cu r r e n t sources are switched on at a l l times to minimize s i g n a l t r a n s i e n t s when a c u r r e n t source i s switched i n to the summing node. In the c o n v e n t i o n a l v o l t a g e s w i t c h i n g DAC, b i n a r y weighted r e s i s t a n c e s are d r i v e n by a r e f e r e n c e v o l t a g e to generate a bina r y weighted set of c u r r e n t s . The c u r r e n t s are then switched and summed as i n the c u r r e n t switched DAC. The R-2R r e s i s t o r ladder i s the most common approach to generate b i n a r y weighted c u r r e n t sources. The e n t i r e range of bi n a r y weighted c u r r e n t s can be generated by us i n g only two values of r e s i s t a n c e s by using a s i n g l e v o l t a g e source or a s i n g l e c u r r e n t source as r e f e r e n c e . The con v e r s i o n accuracy f o r a R-2R DAC i s s u p e r i o r to the b i n a r y c u r r e n t source or b i n a r y r e s i s t a n c e DAC because the e r r o r s a s s o c i a t e d with a wide range of source value or r e s i s t a n c e v a l u e s are absent. F u r t h e r , the c i r c u i t area i s reduced s i n c e the l a r g e r e s i s t a n c e s (and l a r g e area) needed to b u i l d high r e s o l u t i o n DACs are not needed. The DAC used i n the c o l o u r p a l e t t e protoytpe, a v a i l a b l e as an MPR l i b r a r y c e l l , was a s i m p l i f i c a t i o n of the v o l t a g e switched R-2R DAC. The c o l o u r p a l e t t e DAC c i r c u i t uses a r e s i s t o r ladder of s i x t e e n equal value d i f f u s e d r e s i s t o r s c o n s t r u c t e d by i n s e r t i n g taps at equal d i s t a n c e along the l e n g t h of a d i f f u s i o n s t r i p . The s i x t e e n taps provide s i x t e e n analog v o l t a g e l e v e l s . The taps were switched to the output p o i n t by a pass t r a n s i s t o r c o n t r o l l e d by a b i n a r y decoding network which s e l e c t e d one of s i x t e e n analog v o l t a g e taps to output depending on the f o u r - b i t c o l o u r i n t e n s i t y code. The D A C s accuracy i s maintained i f no c u r r e n t i s d i v e r t e d from the r e s i s t o r ladder 36 i n t o the output l o a d . The output node t h e r e f o r e must be terminated by a high-impedance v o l t a g e f o l l o w e r with a s u f f i c i e n t l y wide bandwidth to t r a c k the output s i g n a l at a vide o data r a t e of 5.4 MHz. An output v o l t a g e swing of 1 V was needed to c o n t r o l the e l e c t r o n gun i n t e n s i t y c i r c u i t . S i x t e e n d i f f u s e d r e s i s t o r s of 66 ohms each were d r i v e n by an e x t e r n a l l y s u p p l i e d 1 v o l t v o l t a g e r e f e r e n c e to give a s t a t i c d i s s i p a t i o n c u r r e n t of about 1.5 mA. 3.7 The M u l t i - P r o j e c t Test Chip The c o l o u r p a l e t t e p r o t o t y p e , along with a c o l l e c t i o n of t e s t c e l l s were f a b r i c a t e d on a m u l t i - p r o j e c t c h i p . S t a t i c t e s t i n g only was p o s s i b l e with the t e s t c e l l s because l i m i t e d area d i d not allow the i n c l u s i o n of output pads to a p p r o p r i a t e l y d r i v e the o f f - c h i p l o a d . Nonetheless, these i n d i v i d u a l t e s t c e l l s all-owed the p a l e t t e IC to be t e s t e d i n a modular way such that problems i n c i r c u i t f u n c t i o n c o u l d be i s o l a t e d and v e r i f i e d e a s i l y . The t e s t c e l l s i n c l u d e d on c h i p were a memory c e l l , an x-decoder, a y-decoder, a b i d i r e c t i o n a l b u f f e r , a p i p e l i n e r e g i s t e r , a c o n t r o l s i g n a l generator and a simple process monitor. A p l o t of the c o l o u r p a l e t t e c h i p i s shown i n F i g u r e 3.8. 3.8 Test R e s u l t s The MPC d i e was bonded and retu r n e d f o r t e s t i n g i n January, 1983. S t a t i c t e s t i n g v e r i f i e d that a l l t e s t a b l e t e s t modules F i g u r e 3 . 8 L a y o u t o f t h e c o l o u r p a l e t t e p r o t o t y p e I C 38 worked p r o p e r l y . The dynamic t e s t i n g of the c o l o u r p a l e t t e prototype r e v e a l e d s e v e r a l design e r r o r s : (1) The power l i n e s of the processor to memory access output pads were connected backward. The power l i n e r e v e r s a l forward-biased a l l d e v i c e - t o - s u b s t r a t e j u n c t i o n s and caused c u r r e n t on the order of s e v e r a l hundred m i l l i a m p s t o be drawn. The high c u r r e n t rendered the p a l e t t e IC u n t e s t a b l e f o r f e a r of damaging the IC. The problem was so l v e d by c u t t i n g the power l i n e s to the output pads by the use of an u l t r a s o u n d e x c i t e d probe. The c u t , however, d i s a b l e d the processor output c i r c u i t such that dynamic t e s t i n g of processor read (where memory data output must be d r i v e n by the output pads) i s no longer p o s s i b l e . (2) The P-well of the processor input pad t r a n s m i s s i o n gate was not connected to VDD. Consequently, charge accumulated i n the P-well due to s u b s t r a t e leakage c u r r e n t . Since the charged P-well, now probably at or near VDD, was the s u b s t r a t e f o r N channel t r a n s i s t o r s , the input pad N channel t r a n s i s t o r t h r e s h o l d v o l t a g e was r a i s e d t o above 3 V. As a r e s u l t , the N channel t r a n s i s t o r d i d not turn f u l l y on, and i t was impossible to di s c h a r g e the i n t e r n a l data bus. Since the i n t e r n a l data bus must be p u l l e d to VSS to w r i t e a l o g i c '0' i n t o memory, i t was impossible to w r i t e i n a l o g i c '0'. F o r t u n a t e l y the memory was i n i t i a l i z e d to the l o g i c '0' s t a t e upon power up, so that 39 at l e a s t a p a r t i a l dynamic check of memory w r i t e and storage was s t i l l p o s s i b l e . (3) A metal to metal spacing v i o l a t i o n at the y-decoder s p o r a d i c a l l y shorted the AO bus to Gnd. As a r e s u l t , only even numbered memory l o c a t i o n s was read r e l i a b l y . (4) The l a c k of proper b u f f e r i n g between the d i g i t a l and analog c i r c u i t of the DAC allowed n o i s e to be coupled to the analog output. As a r e s u l t the analog output was co r r u p t e d by high frequency g l i t c h e s a r i s i n g from the dynamic i n t e n s i t y decoding, and a l s o by a DC o f f s e t which exceeded the one-half LSB l e v e l (63 mV i n t h i s c a s e ) . Once the proper steps were taken to a v o i d the above problems, dynamic t e s t i n g of the video data path gave very encouraging r e s u l t s . Data was loaded i n t o memory and read out s u c c e s s f u l l y . The memory addresses were generated by a c y c l i c s i x t e e n s t a t e counter i n s y n c h r o n i z a t i o n with the p i p e l i n e r e g i s t e r c l o c k PCLK. Four d i f f e r e n t b i t p a t t e r n s were loaded i n t o the four c o l o u r words and the memory words were read out c y c l i c a l l y . The output of analog s i g n a l s was v a l i d up to at l e a s t 13 MHz. The analog output showed that f o r a l o a d of 15pF, the DAC s e t t l e s i n l e s s t h a t 3 ns. The t e s t r e s u l t s v e r i f i e d the f u n c t i o n a l i t y and performance Of most major c i r c u i t modules of the c o l o u r p a l e t t e c h i p and pro v i d e d d i r e c t i o n s f o r improvement i n the phase two desi g n . 40 4.0 THE FULL SCALE COLOUR PALETTE INTEGRATED CIRCUIT DESIGN Phase two of the f u l l s c a l e c o l o u r p a l e t t e d e s i g n began on A p r i l 25, 1983. In the phase two d e s i g n , the c o l o u r p a l e t t e was expanded to i n c l u d e the c i r c u i t f o r the red, green and blue e l e c t r o n guns. Layout mistakes made i n the phase one design were c o r r e c t e d . A new d i g i t a l - t o - a n a l o g c o n v e r t e r was designed to minimize the n o i s e i n the analog v i d e o output. The dynamic DAC used i n the prototype was a l s o i n c l u d e d on the c h i p to ensure that D/A c o n v e r s i o n was p o s s i b l e i n a n t i c i p a t i o n of c i r c u i t e r r o r s i n the new DAC. Separate t e s t c i r c u i t s such as those i n c l u d e d on the phase one MPC c h i p were not i n c l u d e d f o r the l a c k of area. S e l e c t e d c r i t i c a l paths of the f u l l s c a l e c o l o u r p a l e t t e were simulated on SPICE. S i m u l a t i o n r e s u l t s p r e d i c t e d that the IC performance would be w e l l w i t h i n s p e c i f i c a t i o n . An e r r o r margin as high as 50% c o u l d be t o l e r a t e d . The f u l l c o l o u r p a l e t t e design was completed on May 13, 1983, consuming nine man-weeks of work. The same design t o o l s as those used f o r phase one design were used: the MPR CDS software package running on the HP9826 or HP9836 desk top computer. Check p l o t s are output v i a the HP7220 e i g h t pen p l o t t e r . S e c t i o n p l o t s which windowed i n t o p a r t s of the l a y o u t were generated on the VAX 750 and output v i a the HP7220 to allow c a r e f u l checking of the l a y o u t f o r design r u l e e r r o r s . A great deal of time was saved by using the s e c t i o n p l o t t e r because only the p o r t i o n of l a y o u t of i n t e r e s t needed to be p l o t t e d . The r e s o l u t i o n of the output was a l s o much improved s i n c e the output i s s c a l e d to f i l l the maximum p l a t e n area of the p l o t t e r . 41 The f u l l s c a l e c o l o u r p a l e t t e c h i p c o n t a i n e d approximately 6000 t r a n s i s t o r s and measured 0.4 cm by 0.6 cm i n s i z e . The c i r c u i t was being f a b r i c a t e d at the time of w r i t i n g of t h i s t h e s i s . 4.1 The S t a t i c D i q i t a l - t o - A n a l o q Converter The s t a t i c d i g i t a l - t o - a n a l o g c o n v e r t e r was the only new c i r c u i t i n c l u d e d on the f u l l s c a l e c o l o u r p a l e t t e c h i p . The dynamic decoding c i r c u i t was r e p l a c e d by a s t a t i c decoder. The NOR gate loads were implemented by c o n t i n u o u s l y switched-on P channel d e v i c e s . The high frequency n o i s e caused by the dynamic precharge o p e r a t i o n found i n the dynamic DAC was thus removed. A d d i t i o n a l b u f f e r i n g between the d i g i t a l and the analog c i r c u i t r y was provided by p l a c i n g l a r g e power and ground busses between the two s i d e s . Separate grounds f o r the d i g i t a l and the analog c i r c u i t r y a l s o helped to reduce n o i s e . The t r a n s m i s s i o n gates which switched the s e l e c t e d tap vo l t a g e to the output node were mo d i f i e d to f u l l y complementary t r a n s m i s s i o n gates to i n c r e a s e the output v o l t a g e swing to about 4 V. The s t a t i c DC o f f s e t found i n the dynamic DAC may now be reduced by p r o p e r l y s e t t i n g the gain of the o f f - c h i p b u f f e r to s c a l e the video output down to 1 v o l t v o l t a g e swing. The re f e r e n c e v o l t a g e was 5V. The r e s i s t o r ladder r e s i s t a n c e was in c r e a s e d a p p r o p r i a t e l y to maintain a 1 mA maximum d i s s i p a t i o n c u r r e n t . 42 5.0 MEMORY CELL CIRCUIT REFINEMENT The c i r c u i t area of the f u l l - s c a l e c o l o u r p a l e t t e c h i p , as shown i n F i g u r e 3.8, was dominated by the s t a t i c r e g i s t e r f i l e . Not w i t h s t a n d i ng the r e d u c t i o n i n the number of c h i p s that can be manufactured per wafer, the l a r g e d i e s i z e c o u l d l e a d to low y i e l d and i n c r e a s e d packaging c o s t . Therefore the f u l l s c a l e c o l o u r p a l e t t e c h i p area should be reduced through some a d d i t i o n a l refinement. Since the memory a r r a y consumed most of the d i e area, and si n c e i t was not optimal i n design, the memory c i r c u i t i s the f i r s t candidate to be redesigned. The memory u n i t c e l l i n turn must be opti m i z e d because i t was repeated many times i n c o n s t r u c t i n g the memory a r r a y . Changes i n the memory c e l l design would n e c e s s i t a t e the r e d e s i g n i n g of data read-out c i r c u i t s . A design refinement of the memory c e l l c i r c u i t i s presented i n S e c t i o n 5. 5.1 Memory C e l l Design A l t e r n a t i v e s The prime o b j e c t i v e i n the r e d e s i g n i n g of the memory c e l l was to reduce the memory a r r a y layout a r e a . To t h i s end commercial random access memories (RAM) ICs pro v i d e d e x c e l l e n t g u i d e l i n e s [ H o l l 7 8 , Brig78, Akiy79, I s o b 8 l , Abot73,. Elma80]. C a r e f u l c o n s i d e r a t i o n was given to the two mainstream d i g i t a l memory c i r c u i t techniques to determine whether the c o l o u r p a l e t t e memory a r r a y should be r e a l i z e d as a s t a t i c or a dynamic RAM. Dynamic RAMs (DRAM) are i d e a l f o r very l a r g e s c a l e i n t e g r a t i o n . DRAM ch i p s c u r r e n t l y i n the market have a memory 43 c a p a c i t y of up to 128K b i t s . The DRAM s t o r e s the in f o r m a t i o n b i t as a charge on a very small MOS c a p a c i t o r to allow high d e n s i t y i n t e g r a t i o n of memory elements. The c a p a c i t o r charge i s r e p l e n i s h e d p e r i o d i c a l l y , t y p i c a l l y once every one to two m i l l i s e c o n d s to re p l a c e the charge leaked through the o x i d e - t o -s u b s t r a t e i s o l a t i o n and through the non-conducting channel of O F F - t r a n s i s t o r s . The r e f r e s h c i r c u i t r y i n t e g r a t e d on c h i p requires- a d d i t i o n a l r e f r e s h s i g n a l generation support c i r c u i t s o f f - c h i p . Hence extremely high d e n s i t y memory i s achieved at the expense of c i r c u i t complexity. S t a t i c RAMs (SRAM) r e l y on b i s t a b l e c i r c u i t s to s t o r e the in f o r m a t i o n and thus are l e s s dense than dynamic RAMs. Because the i n f o r m a t i o n i s s t o r e d i n a b i s t a b l e c i r c u i t , no r e f r e s h o p e r a t i o n i s necessary and the memory c i r c u i t i s s i m p l i f i e d at the expense of memory d e n s i t y . SRAMs are a v a i l a b l e i n both the NMOS and the CMOS technology. R e l a t i v e to the NMOS SRAM, the CMOS SRAM had the advantage of low stand-by power d i s s i p a t i o n . However, the CMOS memory r e q u i r e s about twice the c i r c u i t area of NMOS SRAMs. A t y p i c a l SRAM memory c a p a c i t y i s about 2K to 4K b i t s . The c o l o u r p a l e t t e r e q u i r e s only a 192 b i t memory or g a n i z e d i n a word-wide c o n f i g u r a t i o n of 12-bits by 16-words. The modest memory s i z e i s thus best implemented as a SRAM to a v o i d the DRAM c i r c u i t complexity. The memory a r r a y i s c o n s t r u c t e d by a new dual port CMOS s t a t i c memory c e l l . I t was decided to design the dual port memory c e l l i n two st e p s . F i r s t the b a s i c s i x -t r a n s i s t o r s i n g l e port CMOS s t a t i c RAM c e l l was i n v e s t i g a t e d to obt a i n an understanding of the c i r c u i t design problems. In the 4 4 second step, the r e s u l t s from step one were extended to f i n a l i z e the c i r c u i t and lay o u t of the dua l p o r t s t a t i c memory c e l l . 5.2 The CMOS S t a t i c RAM C e l l C i r c u i t A survey of the l i t e r a t u r e and the IC market showed that a 5 - t r a n s i s t o r and a 6 - t r a n s i s t o r v a r i a t i o n of the b a s i c c r o s s -coupled i n v e r t e r p a i r b i s t a b l e c i r c u i t are used i n SRAM c e l l d esign as shown i n F i g u r e 5.1. The 6 - t r a n s i s t o r c e l l was the f i r s t b i s t a b l e used f o r high d e n s i t y memory element a p p l i c a t i o n [Hodg68]. The 5 - t r a n s i s t o r c e l l was d e r i v e d from the 6-t r a n s i s t o r c e l l when i t was n o t i c e d that only one read path was needed to access the b i s t a b l e c i r c u i t ; hence the opp o s i t e t r a n s f e r gate was removed. The 5 - t r a n s i s t o r c e l l consumes approximately 30 percent l e s s area than the 6 - t r a n s i s t o r c e l l [ B r i g 7 8 ] , However the 5 - t r a n s i s t o r c e l l was more sus c e p t a b l e than the 6 - t r a n s i s t o r c e l l t o s t a t e r e v e r s a l caused by noise i n j e c t e d i n t o the memory c e l l d u r i n g read access [ H o l l 7 8 , B r i g 7 8 ] . E x t r a p r e c a u t i o n would be needed i n the 5-t r a n s i s t o r c e l l design to prevent s o f t e r r o r s caused by d e s t r u c t i v e readout. In the l i t e r a t u r e , much debate i s d i r e c t e d t o whether the memory c e l l t r a n s f e r gate (G1,G2 i n F i g u r e 5.2) are best implemented by an N-channel, a P-channel t r a n s i s t o r or a complementary t r a n s m i s s i o n gate [Akiy79, I s o b 8 l ] . In the i n t e r e s t of high c i r c u i t d e s i t y , the t r a n s f e r gate i s commonly r e a l i z e d by a s i n g l e channel gate i n s t e a d of a complementary gate. There i s much c o n t r o v e r s y i n the ch o i c e of the s i n g l e VDD SELECT SELECT DATA 5 - t r a n s i s t o r memory c e l l J 6 - t r a n s i s t o r memory c e l l F i g u r e 5 . 1 The f i v e - a n d s i x - t r a n s i s t o r CMOS s t a t i c memory c e l l 46 channel t r a n s f e r gate between the N and P channel pass t r a n s i s t o r . Both the N channel t r a n s f e r gate [Akiya79] and the P channel t r a n s f e r gate are used i n commercial memory products. The exact c h o i c e of the t r a n s f e r gate type i s made a f t e r c o n s i d e r a t i o n of c i r c u i t o p e r a t i o n and c i r c u i t s t a b i l i t y . I t was decided that the ease of design and the grea t e r s t a b i l i t y of the 6 - t r a n s i s t o r c e l l more than compensated f o r the 30 percent area p e n a l t y f o r the small c o l o u r p a l e t t e memory. 5.3 Ba s i c C i r c u i t Operation The b a s i c CMOS s t a t i c 6 - t r a n s i s t o r SRAM c e l l i s shown i n F i g u r e 5.1. The b i s t a b l e storage element i s made up by two i n v e r t e r s which are c r o s s - c o u p l e d . The data are s t o r e d as gate charges on the i n t e r n a l nodes (1) and ( 3 ) . In the s t a b l e s t a t e , the i n t e r n a l node v o l t a g e i s e i t h e r VSS or VDD and the v o l t a g e l e v e l of the i n t e r n a l nodes are complementary. The s t o r e d datum and i t s complement are gated t o the output nodes (2) and (4) v i a t r a n s f e r gates G1 and G2 as c o n t r o l l e d by the SELECT s i g n a l . The output node ca p a c i t a n c e lumps the sense a m p l i f i e r input c a p a c i t a n c e , the in t e r c o n n e c t c a p a c i t a n c e , the b u s - l i n e - t o -s u b s t r a t e c a p a c i t a n c e and other s t r a y c a p a c i t a n c e s . The b i s t a b l e i n v e r t e r c o n s i s t s of the P-channel p u l l u p t r a n s i s t o r and the N-channel pulldown t r a n s i s t o r . The s u b s t r a t e s are a p p r o p r i a t e l y b i a s e d to set the s o u r c e - t o - s u b s t r a t e v o l t a g e to z e r o . In the storage or the standby mode, the t r a n s f e r gates are non-conducting and i s o l a t e the b i s t a b l e storage nodes from the 4 7 b i t l i n e s . The i n v e r t e r s are i n complementary s t a t e s . For each i n v e r t e r e i t h e r the p u l l u p or the pulldown t r a n s i s t o r i s ON and the other t r a n s i s t o r i s OFF, thus the i n t e r n a l nodes are e i t h e r p u l l e d up to VDD or p u l l e d down to VSS. Since the t r a n s f e r gates are OFF i n the standby mode, only a very small c u r r e n t t y p i c a l l y on the order of s e v e r a l picoamperes i s drawn through the ON t r a n s i s t o r to r e p l e n i s h the storage node charge l o s t v i a oxide i n s u l a t i o n leakage and reverse s a t u r a t i o n leakage through the channel of the OFF t r a n s f e r gates. During a read access the t r a n s f e r gates are turned on. The b i t l i n e s , precharged to VDD or VSS, appear to the memory c e l l as a p a s s i v e c a p a c i t a n c e . The b i t l i n e c a p a c i t a n c e s are then d i s c h a r g e d through the i n t e r n a l node connect to the opposite power supply or remain unchanged i f the i n t e r n a l node i s at the same v o l t a g e l e v e l as the precharged' b i t l i n e . The c u r r e n t from the d i s c h a r g e of the b i t l i n e c a p a c i t a n c e , shown i n F i g u r e 5.1 as Isense, i s a m p l i f i e d by a data sensing c i r c u i t f o r output. In a memory w r i t e o p e r a t i o n , the b i t l i n e s are connected to a c t i v e complementary sources and the t r a n s f e r gates are turned on. The e x t e r n a l sources charges or d i s c h a r g e s the i n t e r n a l nodes v i a the t r a n s f e r gates thus f o r c i n g the b i s t a b l e c i r c u i t i n t o the d e s i r e d s t a t e . In g e n e r a l , the p u l l u p t r a n s i s t o r i s the s m a l l e s t , that i s , i t s d.c. transconductance i s lower than that of the pulldown or the t r a n s f e r gate s i n c e i t need to supply only the leakage c u r r e n t f o r the storage node of the opposite i n v e r t e r . The pulldown i s the l a r g e s t in order to sink the sense c u r r e n t adequately to p r o v i d e f a s t data read out. The t r a n s f e r gate s i z e 48 i s i n ge n e r a l smaller than the pulldown to l i m i t the sense c u r r e n t i n order to av o i d s t a t e r e v e r s a l d u r i n g read access. The t o p i c of memory c e l l s t a b i l t y i s d i s c u s s e d i n S e c t i o n 5.4. 5.4 Memory C e l l I n s t a b i l i t y The memory c e l l can f a i l to operate r e l i a b l y f o r many reasons some of which are d i s c u s s e d i n t h i s s e c t i o n . 5.4.1 Problems Re l a t e d to P r o c e s s i n g The n a t i v e t h r e s h o l d v o l t a g e of the N and P channel t r a n s i s t o r should i d e a l l y be matched, that i s , be equal i n magnitude [Burn64]. The l o g i c t h r e s h o l d and the noise margin of the t r a n s i s t o r c i r c u i t depends d i r e c t l y on the t h r e s h o l d matching t h e r e f o r e the n o i s e s u s c e p t a b i 1 i t y of the memory i s d i r e c t l y a f f e c t e d [ K l e i 6 9 , E l m a 8 l ] . D r i f t of the n a t i v e t h r e s h o l d v o l t a g e of 30 percent i s not uncommon due to p r o c e s s i n g v a r i a t i o n s . A c o n s i d e r a t i o n of worst case n a t i v e t h r e s h o l d v o l t a g e s would t h e r e f o r e be necessary to ensure that the c i r c u i t i s s t a b l e and meets speed s p e c i f i c a t i o n . During c i r c u i t o p e r a t i o n , the t r a n s i s t o r t h r e s h o l d v o l t a g e o f t e n s h i f t s due to the back gate b i a s e f f e c t [Cher69, Cobb70], T h i s phenomenon c o u l d be viewed as an e q u i v a l e n t r e d u c t i o n i n the w i d t h - t o - l e n g t h (W/L) r a t i o of the gate of the t r a n s i s t o r . In the o p e r a t i o n of the memory c e l l when the sense c u r r e n t s i n k s to ground through the pulldown t r a n s i s t o r T1, the vo l t a g e of the i n t e r n a l node (1) r i s e s and causes the t r a n s f e r gate t h r e s h o l d 49 v o l t a g e to r i s e thus reducing the sense c u r r e n t and slowing down data read out. The back gate b i a s e f f e c t i s more severe f o r the K-channel t r a n s f e r gate than f o r the P-channel t r a n s f e r gate because the bulk t h r e s h o l d c o e f f i c i e n t Gamma i s p r o p o r t i o n a l to the root of the s u b s t r a t e doping c o n c e n t r a t i o n . For a P-well CMOS process, the N-channel t r a n s i s t o r s are b u i l t i n the P-well. In order to c o n t r o l the n a t i v e t h r e s h o l d v o l t a g e s of the N-channel and the P-channel t r a n s i s t o r s , the P-w e l l doping c o n c e n t r a t i o n i s t y p i c a l l y one order of magnitude high e r than the N-substrate doping c o n c e n t r a t i o n . Hence the magnitude of Gamma f o r N-channel t r a n s i s t o r s i s about 3 times g r e a t e r than f o r P-channel t r a n s i s t o r s . A k i y a [Akiy79] s e l e c t e d the P-channel t r a n s f e r gate over the N-channel gate t o reduce t h r e s h o l d v o l t a g e s h i f t . However the use of P-channel t r a n s f e r gates consumes more c i r c u i t area because the ho l e m o b i l i t y i s about h a l f the e l e c t r o n m o b i l i t y i n bulk s i l i c o n . In the design of the c o l o u r p a l e t t e SRAM c e l l , the N-channel t r a n s f e r gate i s chosen i n order to minimize c i r c u i t a r e a . The speed and s t a b i l i t y of the memory c i r c u i t was sim u l a t e d by SPICE to guarantee that the memory met design s p e c i f i c a t i o n . |vTi = IVTOI + r[JWB + VS-SUB - f&P] c ox 50 5.4.2 Problems R e l a t e d to Sense Current The time to d i s c h a r g e a c a p a c i t o r through an N-channel t r a n s i s t o r i s much s h o r t e r than f o r charg i n g due to back gate b i a s e f f e c t [Craw67, Cobb70], hence i n order t o reduce read access time the b i t l i n e i s u s u a l l y precharged f o r a memory read. I f the memory c e l l storage node was at VSS, then the b i t l i n e c a p a c i t a n c e d i s c h a r g e s through the t r a n s f e r gate, through the i n t e r n a l node and then through the pulldown t r a n s i s t o r to ground. The d i s c h a r g e c u r r e n t , c a l l e d the sense c u r r e n t , i s d e t e c t e d by the sense a m p l i f i e r and r e l a y e d t o the output d r i v e r s t o forward the data t o the e x t e r n a l world. The danger i n a precharged read occurs when the sense c u r r e n t i s l a r g e enough t o r a i s e the i n t e r n a l node v o l t a g e (which i s the gate v o l t a g e of the other i n v e r t e r i n the c r o s s -coupled f l i p f l o p ) near to the p o i n t when the f l i p f l o p c o u l d r e v e r s e s t a t e [Hodg68, F r i e 6 8 ] . The s t a t e r e v e r s a l occurs when the i n v e r t e r s are b i a s e d past the u n i t y gain p o i n t i n t o the high gain r e g i o n shown i n F i g u r e 5.2. V o u t F i g u r e 5 . 2 The D . C . t r a n s f e r c h a r a c t e r i s t i c s o f a n i n v e r t e r 51 The i n t e r n a l node v o l t a g e r i s e i s caused by (1) the VDS of the pulldown t r a n s i s t o r which s i n k s the sense c u r r e n t , and (2) the chargi n g of Cg2 shown i n F i g u r e 5.1 by p a r t of the sense c u r r e n t . Because the b i t l i n e l o a d c a p a c i t a n c e i s t y p i c a l l y two orders of magnitude g r e a t e r than the storage node c a p a c i t a n c e s Cg1, Cg2, the read out " n o i s e " i n j e c t e d i n t o the memory c e l l by the sense c u r r e n t presents a s e r i o u s d e s t a b i l i z i n g e f f e c t . The read out n o i s e tends t o p u l l the memory c e l l t o the opp o s i t e b i n a r y s t a t e , thus causing a s o f t e r r o r . The e f f e c t of read out noise i s e s p e c i a l l y pronounced f o r the "single-ended" read out of the 5 - t r a n s i s t o r [ H o l l 7 8 ] c e l l because the neg a t i v e feedback s u p p l i e d by the complementary b i t l i n e i s absent. The e f f e c t of sense c u r r e n t toward s o f t e r r o r was d i s c u s s e d by many authors [Hodg68, F r i e 6 8 , H o l l 7 8 , A k i y 7 9 ] . The s o l u t i o n i s to a d j u s t the transconductance of the t r a n s f e r gate r e l a t i v e to the pulldown such that the VDS of the pulldown t r a n s i s t o r does not exceed the i n v e r t e r u n i t y g a i n p o i n t . The gate of the c r o s s - c o u p l e d i n v e r t e r i s thus maintained at a s u f f i c i e n t l y p o s i t i v e v o l t a g e to prevent the i n i t i a t i o n of p o s i t i v e feedback i n the b i s t a b l e c i r c u i t which e x p e d i t e s the p a r a s i t i c s t a t e r e v e r s a l . A design c o n f l i c t a r i s e s at t h i s p o i n t because r e d u c t i o n of the t r a n s f e r gate gain w i l l i n c r e a s e the memory read and w r i t e time, while i n c r e a s e of the pulldown g a i n i n c r e a s e s memory c e l l a r e a. 52 5.4.3 I n s t a b i l i t y Related t o C a p a c i t i v e C r o s s - c o u p l i n g Noise due to c a p a c i t i v e c r o s s - c o u p l i n g , or c r o s s t a l k , i s i n j e c t e d i n t o the memory c e l l through the p a r a s i t i c c o u p l i n g c a p a c i t a n c e s Cgn, Cgb, and Cbn shown i n F i g u r e 5.3 [ F r i e 6 8 , S h i c 6 8 ] . SELECT DATA L I N E INTERNAL NODE P a r a s i t i c c o u p l i n g c a p a c i t a n c e s f r o m t h e d a t a l i n e a n d t h e s e l e c t l i n e t o t h e i n t e r n a l n o d e The memory c e l l i n t h i s case i s not accessed and remains d e s e l e c t e d . When another c e l l i n the same column which shares the same b i t l i n e s i s read or when the b i t l i n e i s precharged, however, the b i t l i n e v o l t a g e t r a n s i e n t i s coupled i n t o the gate of the t r a n s f e r gate and a l s o i n t o the i n t e r n a l storage node. I f the s i g n a l s propagating on the b i t l i n e s are op p o s i t e to those s t o r e d on the i n t e r n a l nodes, then both i n t e r n a l nodes w i l l e x perience a " p u l l " t o re v e r s e s t a t e . To worsen matters, the c r o s s t a l k may p a r t i a l l y t urn on the t r a n s f e r gates to f u r t h e r expose the i n t e r n a l nodes t o b i t l i n e t r a n s i e n t v o l t a g e changes. Care must be taken i n c i r c u i t l ayout t o reduce the s t r a y c a p a c i t a n c e between the s e l e c t l i n e s , the b i t l i n e s and the 53 i n t e r n a l storage nodes. 5.5 S i m u l a t i o n of Read Access S t a b i l i t y Read access s t a b i l i t y was simulated to i n v e s t i g a t e the e f f e c t that sense c u r r e n t i n j e c t i o n had toward p a r a s i t i c s t a t e r e v e r s a l [Vlad80a, Vlad80b, S h i c 6 8 ] . The 5 - t r a n s i s t o r memory c e l l was simulated to h e l p i s o l a t e the e f f e c t of the sense c u r r e n t without the negative feedback of the complementary read path. An N-channel t r a n s f e r gate was used. The b i t l i n e was modeled by a 0.4pF load c a p a c i t a n c e and was precharged to VDD to supply the sense c u r r e n t . Because the b i t l i n e was u s u a l l y l a i d out i n metal, b i t l i n e r e s i s t a n c e was s m a l l i n comparison to the t r a n s f e r gate ON-resistance which was t y p i c a l l y 10K ohms and thus was n e g l e c t e d i n the s i m u l a t i o n . In the s i m u l a t i o n , the i n t e r n a l read time of the memory c e l l was d e f i n e d as the time which i t r e q u i r e s f o r the precharged b i t l i n e to di s c h a r g e from VDD to h a l f VDD. A l l t r a n s i s t o r channel lengths were set to the minimum value or 5 microns f o r the ISO-CMOS process used. T r a n s i s t o r transconductance was set by v a r y i n g the gate width. Several p r a c t i c a l combinations of transconductance values f o r the p u l l u p , pulldown and the t r a n s f e r gate were simulated. S t a t e r e v e r s a l occurs f o r a l l cases simulated where the t r a n s f e r gate g r e a t l y exceeds the gain of the pulldown t r a n s i s t o r . The c i r c u i t s imulated i s shown i n F i g u r e 5.4a. The c i r c u i t waveforms f o r a s t a b l e read and a s t a t e r e v e r s a l are shown i n F i g u r e s 5.4b and 5.4c r e s p e c t i v e l y . The exact r a t i o s of 54 F i g u r e 5.4 S t a b i l i t y s i m u l a t i o n s f o r t h e 5 - t r a n s i s t o r memory c e l l 55 t r a n s f e r gate gain to pulldown gain which causes s t a t e r e v e r s a l i s a f u n c t i o n of the gain of the pulldown. The maximum noise v o l t a g e f o r a l l cases was approximately at the i n v e r t e r u n i t y gain p o i n t of about 1.8 v o l t s f o r VDD of 5 v o l t s and f o r symmetric P and N-channel t r a n s i s t o r n a t i v e t h r e s h o l d v o l t a g e s of magnitude of 0.5 v o l t . I n t e r n a l read access times of l e s s than 10 ns were p r e d i c t e d i n a l l the c i r c u i t s s i m u l a t e d . Increases i n the gain of the pulldown reduced the i n t e r n a l node n o i s e v o l t a g e r i s e caused by the sense c u r r e n t as expected, the read time was a l s o decreased. A n a l y s i s of the s i m u l a t i o n data presented i n S e c t i o n 5.7 showed that t r a n s f e r gate transconductance s l i g h t l y s maller than the pulldown transconductance y i e l d e d an adequate s a f e t y margin f o r read out noise and yet maintains near minimum c i r c u i t a r e a . 5.6 A n a l y s i s of Memory C e l l " S i m u l a t i o n The SPICE s i m u l a t i o n data i n d i c a t e d i n gen e r a l that read out n o i s e s u s c e p t i b i l i t y decreased with i n c r e a s i n g area of the pulldown t r a n s i s t o r . In order to choose the optimal c i r c u i t , the s i m u l a t i o n data was analysed to determine the i n t e r r e l a t i o n between the c i r c u i t area, access speed and nois e s u s c e p t i b i l i t y . The a n a l y s i s proceeded i n four s t e p s . F i r s t the sense c u r r e n t d i s c h a r g e c i r c u i t which c o n s i s t e d of the t r a n s f e r gate and pulldown was modeled by a s i n g l e t r a n s i s t o r c i r c u i t to the f i r s t approximation using the Shichman and Hodges [Shic68, Vlad80a] model to summarize the combinations of transconductances needed to achieve c i r c u i t s t a b i l i t y . Second, 5 6 the memory c e l l nominal c i r c u i t area was approximated by a f u n c t i o n of the pulldown and t r a n s f e r gate area with the assumption that the p u l l u p t r a n s i s t o r occupied only a n e g l i g i b l y small f r a c t i o n of the s t a t i c memory c e l l a r e a . T h i r d , - a graph was c o n s t r u c t e d to u n i f y the s t a b i l i t y s i m u l a t i o n data and the a n a l y s i s r e s u l t r e l a t i n g i n t e r n a l read time and nominal c i r c u i t a r e a . F o u r t h , the optimal memory c e l l t r a n s i s t o r gains were s e l e c t e d to minimize the nominal c i r c u i t area s u b j e c t to a given i n t e r n a l read time. 5.6.1 D e r i v a t i o n of a Sense Current Discharge Model The sense c u r r e n t d i s c h a r g e c i r c u i t i s represented by the c i r c u i t of F i g u r e 5.5b. I t i s d e s i r e d t o f i n d the e f f e c t i v e s i n g l e t r a n s i s t o r gate r a t i o (W/L)EFF which g i v e s the same i n t e r n a l d i s c h a r g e time as the c i r c u i t of F i g u r e 5.5a. Using the Shichman and Hodges model, the dis c h a r g e time was s o l v e d i n terms of the s i n g l e t r a n s i s t o r (W/L)EFF. The (W/L)EFF f o r each t r a n s f e r gate and pulldown combination was then computed by s u b s t i t u t i n g the simulated i n t e r n a l read access time. F i g u r e 5.5a Fi g u r e 5.5b Sense c u r r e n t d i s c h a r g e E q u i v a l e n t c i r c u i t c i r c u i t 5 7 The t o t a l time T t o t f o r v ( t ) to d i s c h a r g e from VDD to 0.5*VDD i s T t o t = T s a t + T t r i o d e Tsat i s the time when the t r a n s i s t o r i s i n s a t u r a t i o n Tsat = 1* L i + r(v<;s-VT)j 4r r ( v « - v T y ZL-\old where V i s the back gate b i a s c o e f f i c i e n t , /3 the transconductance, Vr the n a t i v e t h r e s h o l d v o l t a g e and V&s the gate- t o - s o u r c e v o l t a g e . T t r i o d e i s the time when the t r a n s i s t o r i s d i s c h a r g i n g i n the t r i o d e r e g i o n " I t r i o d e - Cb*d l „ [ 2 ( V G 5 - V T ) - ^ z Thus (W/L)EFF i s (yy/pEFF, C\O66 Xn Ttot K' (v« -V T) z(V 6 S-Vr)+% VPP r i + rvpp Ll-rr(s4s-Vr)J T « r ( v 6 S - v r ) s The d i s c h a r g e time T t o t i s dominated by the time t o di s c h a r g e the b i t l i n e c a p a c i t a n c e when the t r a n s f e r gate i s i n the t r i o d e r e g i o n . The c r e d i b i l i t y of the (W/L)EFF value was checked by r e p r e s e n t i n g the t r a n s f e r and pulldown t r a n s i s t o r s by a naive model c o n s i s t i n g of the t r a n s i s t o r ON-resistances connected i n s e r i e s as shown i n F i g u r e 5.6. 58 t r a n s f e r g a t e d r a i n r e s i s t a n c e • V W c u r r e n t s e n s e p u l l d o w n d r a i n r e s i s t a n c e F i g u r e 5 . 6 A r e s i s t a n c e m o d e l f o r s e n s e c u r r e n t d i s c h a r g e A nominal (W/L)NOM value was d e f i n e d as: p u l l d o w n t r a n s f e r (W/L)NOM = (W/L) * (W/L) p u l l d o w n t r a n s f e r (W/L) + (W/L) The nominal (W/L)NOM value represented the apparent c u r r e n t s i n k i n g c a p a b i l i t y of the t r a n s f e r gate and pulldown combination based only upon t h e i r r e s p e c t i v e t r a n s i s t o r s i z e . The e f f e c t i v e value (W/L)EFF i n c o n t r a s t represented the e f f e c t i v e , t h a t i s a c t u a l c u r r e n t s i n k i n g c a p a b i l i t y of the c i r c u i t . The (W/L)EFF i s s l i g h t l y s m a l l e r than the (W/L)NOM value f o r the same c i r c u i t because the nominal value d i d not account f o r the e f f e c t that sense c u r r e n t i n j e c t i o n had on the memory c i r c u i t . A p l o t of (W/L)EFF and (W/L)NOM versus the i n t e r n a l read time i s shown i n F i g u r e 5.7. Note that the (W/L)NOM value d e v i a t e s from the (W/L)EFF values and the decrease of read access time bottoms out due to.the e f f e c t of the sense c u r r e n t which tends to cause the c e l l to p u l l t o the op p o s i t e s t a t e . In f a c t , the i n c r e a s e i n read access time of a simulated c i r c u i t a f t e r the bottoming out p o i n t i n d i c a t e s t h at the c e l l was approaching a s t a t e r e v e r s a l . 59 * , (W/L) E F F f r o m m o d e l (W/L)NOM f r o m s i m u l a t i o n X X A A " • • " 2 . 0 _ 1 . 0 _ 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 ( W / L ) E F F a n d (W/L)N0M F i g u r e 5 . 7 P l o t o f i n t e r n a l r e a d t i m e v s . (W/L)EFF a n d (W/L)N0M , 60 Wpulldown=15um S o 0) u •H 3 a S-J •H U C •H s o S3 1 0 . ( H W p u l l d o w n = l O u m W p u l l d o w n = 5 u m l o c u s o f a p p r o x i m a t e s t a b i l i t y l i m i t l o c u s o f m i n i m u m n o m i n a l a r e a t o r e a l i z e a g i v e n i n t e r n a l r e a d t i m e 0 . 0 1 . 0 2 . 0 3 . 0 R = R a t i o o f t r a n s f e r g a t e a r e a t o p u l l d o w n t r a n s i s t o r g a t e a r e a F i g u r e 5 . 8 T h e u n i f i e d d e s i g n c h a r t f o r memory c e l l d e s i g n 61 5.6.2 D e f i n i t i o n of Nominal Memory C i r c u i t Area Since the p u l l u p t r a n s i s t o r needs to supply only the leakage c u r r e n t f o r the i n t e r n a l node d u r i n g storage, the p u l l u p i s small compared to the t r a n s f e r gate or the pulldown. The memory c e l l c i r c u i t area Anom i s expressed as a f u n c t i o n of the pulldown and the t r a n s f e r gate t r a n s i s t o r s i z e using the assumption that the area consumption of the pulldown i s n e g l i g i b l e . A f u r t h e r s i m p l i f i c a t i o n of the c i r c u i t area i s achieved by c o n s i d e r i n g the lay o u t area to be d i r e c t l y p r o p o r t i o n a l to the t r a n s i s t o r gate a r e a . The nominal memory c e l l c i r c u i t area Anom i s then d e f i n e d as a f u n c t i o n of the t r a n s f e r gate and the pulldown gate s i z e to o b t a i n a nominal estimate of the memory c e l l c i r c u i t area needed to achieve a given i n t e r n a l read access time. A p d * (1+R) p u l l d o w n g a t e a r e a m i n i m u m g a t e a r e a ( 5 u m x 5um) t r a n s f e r g a t e a r e a p u l l d o w n g a t e a r e a 5.6.3 Memory C i r c u i t Design Chart In the c h a r t of F i g u r e 5.8, the r e s u l t s of the di s c h a r g e model a n a l y s i s , simulated c i r c u i t s t a b i l i t y , the i n t e r n a l read time, and the nominal c i r c u i t area of the s i n g l e p o r t 6-t r a n s i s t o r memory c i r c u i t are combined. The f a m i l y of curves parametrized by the i n t e r n a l read time was obtained by Anom = w h e r e A p d = 62 i n t e r p o l a t i o n of the SPICE s i m u l a t i o n data. The black data p o i n t s o btained from s i m u l a t i o n u s i n g pulldown t r a n s i s t o r gate width of 5 urn and gate widths of 5, 10, and 15 urn were connected by t h i n black l i n e s . I t i s seen that the pulldown gate s i z e must be i n c r e a s e d i n order to achieve short i n t e r n a l read times. Of course the nominal c i r c u i t area i n c r e a s e d with the s i z e of the pulldown and the s i z e of the t r a n s f e r gate. The s t a b i l i t y l i m i t s were e s t a b l i s h e d from s i m u l a t i o n data. In terms of nominal c i r c u i t area, the most c o s t e f f e c t i v e c i r c u i t was obtained when the t r a n s f e r gate gain i s s l i g h t l y l e s s than the pulldown t r a n s i s t o r gate gain as shown by the dashed l i n e s connecting the l o c u s of minimum area f o r each i n t e r n a l read time curve. 5.6.4 Memory C i r c u i t S e l e c t i o n The 6 - t r a n s i s t o r c e l l i n t e r n a l read access time was simulated to ensure that the r e s u l t s o b tained f o r the 5-t r a n s i s t o r c e l l was a p p l i c a b l e to the 6 - t r a n s i s t o r c e l l . Bulk t h r e s h o l d c o e f f i c i e n t s of 1.63 and 0.52 were used f o r the N and P-channel t r a n s i s t o r s to r e f l e c t the ISO-CMOS proc e s s . A s l i g h t i n c r e a s e i n i n t e r n a l read time was observed due to the i n c r e a s e d bulk t h r e s h o l d e f f e c t s on the t r a n s f e r gate, but on the whole the r e s u l t s were c l o s e to those obtained f o r the 5 - t r a n s i s t o r c e l l . The data read out f o r the 6 - t r a n s i s t o r c e l l was much more s t a b l e due to the presence of the second t r a n s f e r gate and b i t l i n e which p r o v i d e d negative feedback to counter to d e s t a b i l i z i n g e f f e c t s of the sense c u r r e n t . The w r i t e o p e r a t i o n of the 6 - t r a n s i s t o r memory c e l l was 63 F i g u r e 5 . 9 P l o t o f t h e i n t e r n a l r e a d t i m e v s . (W/L)EFF a n d (W/L)NOM f o r t h e 6 - t r a n s i s t o r memory c e l l 64 simulated by a p p l y i n g v o l t a g e sources d i r e c t l y to the b i t l i n e e x t e r n a l nodes. The memory c e l l was f i r s t p l a c e d i n t o a s t a b l e s t a t e and then the worst case i n t e r n a l w r i t e time was simulated by f o r c i n g the memory c e l l i n t o the opposite l o g i c s t a t e . C i r c u i t s with pulldown t r a n s i s t o r gate widths of 5, 10, and 15 urn with gate l e n g t h f i x e d at 5 urn were simulated. The t r a n s f e r gate s i z e s were maintained to be the same s i z e as the pulldown to minimize the c i r c u i t a r e a . The i n t e r n a l w r i t e time was d e f i n e d as the time r e q u i r e d f o r both i n t e r n a l nodes of the b i s t a b l e c i r c u i t to s e t t l e to w i t h i n 10 percent of the asymptotic v o l t a g e l e v e l . S i m u l a t i o n showed that the i n t e r n a l w r i t e o p e r a t i o n was completed w i t h i n 3 ns f o r a l l three c i r c u i t s s i m u lated. As expected, the i n t e r n a l w r i t e time was c o n s t r a i n e d by the time i t r e q u i r e d f o r the i n t e r n a l node to charge from VSS up to VDD. In g e n e r a l i t i s d e s i r a b l e to design the memory c e l l such that the i n t e r n a l read and w r i t e times are approximately e q u a l . To t h i s end, the c i r c u i t s with pulldown and t r a n s f e r gate widths of 10 to 15 microns were p r e f e r e d . I t was now p o s s i b l e to s e l e c t the optimal c i r c u i t f o r a 6-t r a n s i s t o r memory c i r c u i t . Although the i n t e r n a l read time and w r i t e times d i d not n e c e s s a r i l y r e f l e c t the e x t e r n a l read or wr i t e times, the very short i n t e r n a l access times of approximately 10 ns f o r c i r c u i t s (2) and (3) i n Table 5.1 l e f t a wide s a f e t y margin between the i n t e r n a l memory access times and the maximum e x t e r n a l access times of about 100 ns f o r the video read out o p e r a t i o n . 65 p u l l d o w n p u l l u p t r a n s f e r i n t e r n a l i n t e r n a l n o m i n a l c k t g a t e W g a t e W g a t e W r e a d t i m e w r i t e t i m e c k t a r e a 1 5 um 5 um 5 um 1 1 . 0 n s 2 . 7 n s 2 . 0 2 10 um 5 um 10 um 5 . 5 n s 2 . 2 n s 4 . 0 3 15 um 5 um 15 um 3 . 7 n s 2 . 1 n s 6 . 0 T a b l e 5 . 1 A c c e s s t i m e s a n d n o m i n a l c i r c u i t a r e a o f some p r a c t i c a l 6 - t r a n s i s t o r memory c e l l s 5.7 Design of the Dual Port S t a t i c Memory C i r c u i t The dual p o r t CMOS SRAM c i r c u i t r e q u i r e d f o r the c o l o u r p a l e t t e IC was obt a i n e d by making some minor m o d i f i c a t i o n s to the o p t i m a l s i n g l e port 6 - t r a n s i s t o r SRAM memory c i r c u i t . The ba s i c c i r c u i t of the dual port memory c e l l i s shown i n Fi g u r e 5.10. VDD PROCESSOR SEL VIDEO SEL PROCESSOR SEL F i g u r e 5 . 1 0 T h e d u a l p o r t memory c e l l c i r c u i t 6 6 The dual port memory c e l l was obtained simply by adding an e x t r a p a i r of t r a n s f e r gates to implement the second p o r t . The optimal t r a n s i s t o r s i z e s computed f o r the s i n g l e p o r t 6 - t r a n s i s t o r c e l l c o u l d not be used d i r e c t l y i n the dual p o r t memory c e l l without c o n s i d e r i n g the i n t e r a c t i o n between the two p o r t s . In the o p e r a t i o n of the c o l o u r p a l e t t e , the proc e s s o r had both read and w r i t e access to the memory a r r a y while the video c i r c u i t has only read access to the memory. F u r t h e r , s i n c e the v i d e o and processor-to-memory accesses occur asynchronously, a c o n f l i c t may a r i s e when the processor w r i t e s to a memory l o c a t i o n which i s s i m u l t aneously read by the video c i r c u i t . Table 5.2 shows the p o s s i b l e modes of o p e r a t i o n f o r the dual p o r t memory c e l l . p r o c e s s o r p r o c e s s o r v i d e o mode w r i t e r e a d r e a d comment 1 no no no n o o p e r a t i o n 2 no n o y e s v i d e o r e a d o n l y 3 no y e s n o p r o c e s s o r r e a d o n l y 4 n o y e s y e s d u a l p o r t r e a d 5 y e s no n o p r o e s s o r w r i t e o n l y 6 y e s no y e s d u a l p o r t w r i t e a n d r e a d 7 y e s y e s n o i m p o s s i b l e 8 y e s y e s y e s i m p o s s i b l e T a b l e 5 . 2 M o d e s o f o p e r a t i o n f o r t h e d u a l p o r t memory c e l l The boundary c o n d i t i o n s f o r the dual port memory c e l l c i r c u i t o ccurs when (1) the proc e s s o r read and video read access o v e r l a p ; and (2) when the proc e s s o r w r i t e and video read 6 7 accesses o v e r l a p . In case ( 1 ), the combined sense c u r r e n t f l o w i n g i n t o the VSS i n t e r n a l node must be c o n s i d e r e d to ensure memory read s t a b i l i t y . In case ( 2 ) , the e x t r a l o a d i n g presented by r e l a t i v e l y l a r g e video b i t l i n e c a p a c i t a n c e must be co n s i d e r e d t o avoid an incomplete s t a t e r e v e r s a l d u r i n g a memory w r i t e . E x t e n s i o n of the s i n g l e p o r t memory c e l l r e s u l t i n d i c a t e d t h at given a pulldown s i z e , the s i z e of the t r a n s f e r gates of the two p o r t s should s a t i s f y EFF EFF (W/L)EFF = (W/L) + (W/L) P0RT1 PORT2 Dual p o r t memory c i r c u i t s with v a r i o u s combinations pulldown, processor p o r t t r a n s f e r gate and video port t r a n s f e r gate s i z e were simulated. The P-channel p u l l u p was f i x e d at minimum gate s i z e of 5 um by 5 um. The combined video and proce s s o r t r a n s f e r gate gain was set equal to the pulldown gain to maintain good s t a b i l i t y and optimal c i r c u i t . The s i n g l e read a c c e s s , s i n g l e w r i t e access, the dual read access and simultaneous read and w r i t e access times were i n the neighborhood of 10 to 30 ns. 5.9 Layout f o r the S i n g l e Port Memory C i r c u i t The l a y o u t of a s i n g l e port 6 - t r a n s i s t o r SRAM c e l l i s shown in F i g u r e 5.11. The power g r i d and data ( b i t ) l i n e s are l a i d out i n metal and are run v e r t i c a l l y t o minimize v o l t a g e drop and propagation delay along the l e n g t h of the memory a r r a y . The word s e l e c t i s wired i n p o l y s i l i c o n and runs orthogonal to the data l i n e s t o minimize the c o u p l i n g c a p a c i t a n c e between the two 68 buses. A l s o s i n c e the s e l e c t l i n e gates the memory c e l l t r a n s f e r gate t h e r e f o r e the s e l e c t l i n e s are best l a i d out i n p o l y s i l i c o n . For a b u l d CMOS process, t y p i c a l metal and p o l y s i l i c o n - t o - b u l k c a p a c i t a n c e s are 2.5e-5 and 3.5e-4 pF/sq.um. T y p i c a l sheet r e s i s t a n c e s f o r metal and p o l y s i l i c o n are 0.03 and 30.0 Ohms/square. The c a p a c i t a n c e of metal and p o l y s i l i c o n with r e s p e c t to s u b s t r a t e were comparable, however the sheet r e s i s t a n c e of p o l y s i l i c o n i s s e v e r a l o r d e r s of magnitude g r e a t e r than that of metal. If the propagation delay along a bus l i n e were represented by a lumped RC model, then the time constant of p o l y s i l i c o n i s about 4 orders of magnitude g r e a t e r than that of metal. The l a r g e p o l y s i l i c o n RC time constant c o u l d cause s i g n a l skew in high speed c i r c u i t s where long p o l y s i l i c o n i n t e r c o n n e c t s are used. In the i n t e r e s t of reducing the p o l y s i l i c o n s e l e c t s i g n a l bus l e n g t h , the memory c e l l should have a l a r g e height to width r a t i o . In order to reduce s t r a y c a p a c i t a n c e , a h e i g h t - t o - w i d t h r a t i o of 1 to 2 i s more a p p r o p r i a t e . In the l a y o u t of the s i n g l e port memory c e l l shown i n F i g u r e 5.11, the P-channel p u l l u p t r a n s i s t o r i s 5 by 5 urn; the pulldown and the t r a n s f e r gate both has channel a width of 15 urn and a gate l e n g t h of 5 urn. The s i n g l e port memory c e l l shown i n F i g u r e 5.11 has a c i r c u i t area of 972 square lambdas, with lambda equal 2.5 micron. In comparison, the dual p o r t memory c e l l used i n the c o l o u r p a l e t t e prototype consumed 8580 square lambdas per b i t of s t o r a g e . Assuming that the new dual p o r t memory c e l l c i r c u i t area was twice that of the s i n g l e port memory c e l l , that i s having a c i r c u i t area of approximately 2000 square lambdas, the 69 VSS DATA VDD © A T A VSS a c t i v e p w e l l p p o l y s i l i c o n c o n t a c t n m e t a l L a y o u t o f F i g u r e 5 . 1 1 a s i n g l e p o r t CMOS s t a t i c RAM c e l l 70 memory a r r a y c i r c u i t area would be reduced by about 75 percent. The f u l l s c a l e c o l o u r p a l e t t e c h i p d i e s i z e would then be reduced by about 50 percent. 7 1 6.0 CONCLUSION The p r a c t i c a l i t y of the s i m p l i f i e d design method and a l g o r i t h m i c layout t o o l s to support custom LSI design was eva l u a t e d i n l i g h t of the complexity of the IC designed, the c a p a b i l i t y of the hardware and software design t o o l s , and the work r e q u i r e d to complete the des i g n s . Two prototypes of the c o l o u r p a l e t t e custom IC were designed. The s c a l e d down prototype c o n t a i n e d almost a l l the f u n c t i o n a l c i r c u i t modules of the f u l l s c a l e c o l o u r p a l e t t e . The prototype contained approximately 800 t r a n s i s t o r s . The f u l l s c a l e prototype made use of most of the pre-designed c e l l s and had a t r a n s i s t o r count of approximately 6000 and d i e s i z e of 0.4 by 0.6 cm. S i m p l i f i e d e l e c t r i c a l and layout design r u l e s , as we l l as speed and and l o a d i n g e s t i m a t i o n r u l e s were f o l l o w e d i n the design work. With the exception the dynamic DAC used i n the prot o t y p e , a l l c i r c u i t s were s t a t i c and complementary. The cho i c e of s t a t i c and complementary c i r c u i t s s i m p l i f i e d the design task at the expense of layout a r e a . In l i g h t of our modest IC design experience and the time a v a i l a b l e , t h i s s i m p l i f i c a t i o n was necessary to maximize the p r o b a b i l i t y of o b t a i n i n g a f u n c t i o n a l IC. As a r e s u l t , the prototype c i r c u i t s were indeed f u n c t i o n a l but they consumed la y o u t area e x t r a v a g a n t l y . The c i r c u i t s , e s p e c i a l l y those which c r i t i c a l l y determine the o v e r a l l p r o c e s s i n g speed of the IC should be designed c a r e f u l l y with the h e l p of c i r c u i t s i m u l a t i o n to achieve a c c u r a t e performance c h a r a c t e r i s t i c s and minimal c i r c u i t a r e a . The c o l o u r map memory c e l l was redesigned which was p r o j e c t e d to reduce the IC area by about 50 percent. 7 2 The set of M i c r o t e l P a c i f i c Research a l g o r i t h m i c layout t o o l s used i n the design provided the b a s i c geometric p r i m i t i v e s f o r l a y o u t work. C e l l i n s t a n t i a t i o n , node naming and node f i n d i n g f u n c t i o n s were provided to a s s i s t with the h i e r a r c h i c a l c o n s t r u c t i o n of the IC. The a l g o r i t h m i c layout t o o l s were programmed in HP-BASIC and executed on the HP9826 and HP9836 desk-top computers. Check p l o t s were obtained through low r e s o l u t i o n B/W screen d i s p l a y s as w e l l as from the HP7220 e i g h t c o l o u r pen p l o t t e r . SPICE was used to simulate c r i t i c a l paths in the c i r c u i t but no automatic design r u l e checking program or any other v e r i f i c a t i o n t o o l s were a v a i l a b l e . The c o l o u r p a l e t t e prototype r e q u i r e d two man-months to design and the f u l l s c a l e prototype about 2.5 man-months. Indeed i t was p o s s i b l e to design f a i r l y c o m p l i cated ICs with r e l a t i v e l y ' l i t t l e e f f o r t . I t was found that the a l g o r i t h m i c l a y o u t t o o l s were very u s e f u l f o r the design of s m a l l " l e a f " c e l l s . L i t t l e time was spent i n generating a c e l l once i t s c i r c u i t was l a i d out i n d e t a i l on g r i d paper. The IC and i t s l a y o u t , t h e r e f o r e , must be planned c a r e f u l l y so that the c i r c u i t can be c o n s t r u c t e d by a small c o l l e c t i o n of simple c e l l s i n a h i e r a r c h i c a l manner, and such that the layout of complicated c i r c u i t s on unmanageably l a r g e sheets of paper i s avoided. A h i e r a r c h i c a l design approach helped g r e a t l y to reduce design r u l e e r r o r s . T h i s design s t r a t e g y i s s i m i l a r to the concept of s t r u c t u r e d or modular computer programming. The analogy, however, i s incomplete because u n l i k e the l o g i c a l i n t e g r a t i o n of program procedures, the assembly of c e l l s of an IC l a y o u t r e q u i r e d the i n t e r c o n n e c t i o n of c e l l s g l o b a l l y over a l a r g e c i r c u i t a r e a . No 73 p r o v i s i o n i s a v a i l a b l e i n the t o o l s used to a s s i s t i n c e l l placement and r o u t i n g to minimize layout area and layout r u l e v i o l a t i o n s , which are both important toward i n c r e a s i n g the c o s t -e f f e c t i v e n e s s of the IC. More than h a l f the t o t a l design e f f o r t was put toward g l o b a l placement and i n t e r c o n n e c t i o n as the r e s u l t of the lack of such t o o l s . Despite i t s shortcomings, the set of a l g o r i t h m i c l a y o u t programs d i d provide a f f o r d a b l e and workable t o o l s i n the design of the c o l o u r p a l e t t e p r o t o t y p e . I t may be concluded from t h i s work that l a r g e s c a l e i n t e g r a t e d c i r c u i t s may be e f f i c i e n t l y designed f o l l o w i n g a s i m p l i f i e d and a l g o r i t h m i c design approach. There i s , however, some p o s s i b i l i t y of improvement i n design t o o l s . The r a p i d i n c r e a s e i n c o s t - e f f e c t i v e n e s s of microcomputers and h i g h r e s o l u t i o n c o l o u r g r a p h i c s d i s p l a y system today opens the p o s s i b i l i t y of i n t e g r a t i n g both a l g o r i t h m i c and i n t e r a c t i v e g r a p h i c s on microcomputer-based workstations f o r IC d e s i g n . F u r t h e r , the i n c r e a s i n g l y s o p h i s t i c a t e d microcomputer o p e r a t i n g systems c o u l d be used to m u l t i - t a s k c i r c i t d e s i gn, l a y o u t , v e r i f i c a t i o n and documentation simult a n e o u s l y . N u m e r i c a l l y i n t e n s i v e s i m u l a t i o n s c o u l d be o f f - l o a d e d to a mainframe computer to a v o i d compute-bounding the response of the microcomputer. IC design can thus be supported e f f e c t i v e l y by a mainframe computer s e r v i n g a network of s a t e l l i t e workstations each with some s i g n i f i c a n t l o c a l p r o c e s s i n g c a p a b i l i t y . The problem of how best to combine the advantages of a l g o r i t h m i c and i n t e r a c t i v e g r a p h i c s f o r IC design s t i l l e x i s t s . From a t e c h n i c a l standpoint, t h i s i s a problem i n user and de v i c e i n t e r f a c e . A l t e r n a t i v e l y , from a conceptual standpoint, the 7 4 i n t e r f a c e of the gra p h i c s and a l g o r i t h m i c design approach p o i n t s to the many l e v e l s of data r e p r e s e n t a t i o n and t r a n s l a t i o n i n v o l v e d i n IC desi g n . T h i s c o m p l i c a t i o n touches upon s p a t i a l and l o g i c a l data p r o c e s s i n g i n p a r t i c u l a r , and upon i n f o r m a t i o n r e p r e s e n t a t i o n and manipulation i n g e n e r a l . 75 B i b l i o g r a p h y [Abot73] R.A. Abbott, W.A. R e g i t z , and J.A. Karp, A 4K MOS dynamic random-access memory, IEEE J o u r n a l of S o l i d State C i r c u i t s , SC-8, October 1973, 292-310. [Akiy79] M. Aki y a , and M. Ohara, New input/output designs f o r high-speed s t a t i c CMOS RAM, IEEE J o u r n a l of S o l i d State C i r c u i t s , SC-14, October 1979, 823-828. [B01173] H.J. B o l l , and W.T. Lynch, Design of a hig h performance 1024-bit switched c a p a c i t o r p-channel IGFET memory c h i p , IEEE J o u r n a l of S o l i d State C i r c u i t s , SC-8, October 1973, 310-318. [Brig78] G.R. Br i g g s , et a l . , 40-MHz CMOS-on-sapphire microprocessor, IEEE T r a n s a c t i o n s on E l e c t r o n Devices, ED-25, August 1978, 952-958. [Burn64] J.R. Burns, Switching response of complementary-symmetric MOS t r a n s i s t o r l o g i c c i r c u i t s , RCA Review, 25, December 1964, 627-661. [Carr72] W.N. Car r , and J.P. Mize, MOS/LSI Design and A p p l i c a t i o n , New York, McGraw-Hill Co., 1972. [Chat79] P.K. C h a t t e r j e e , G.W. T a y l o r , A.F. Tasch,Jr., and H.S. F r i , Leakage s t u d i e s i n h i g h - d e n s i t y dynamic MOS memory d e v i c e s , IEEE E l e c t r o n Devices, ED-26, A p r i l 1979, 564-575. [Cher69] G. C h e r o f f , D.L. C r i t c h l o w , R.H. Dennard, and L.M. Terman, IGFET c i r c u i t performance - n-channel versus p-channel, IEEE J o u r n a l of S o l i d State C i r c u i t s , SC-4, October 1969, 267-271. 76 [Cobb70] [Craw67] [ D 0 0 I 8 O ] [ E l m a 8 l ] [Flem83] [ F r i e 6 8 ] [ G a r r 8 l ] [Greb72] [Hodg68] [Holl78] [Hon79] R.S.C. Cobbold, Theory and A p p l i c a t i o n of F i e l d - E f f e c t T r a n s i s t o r s , New York, W i l e y - I n t e r s c i e n c e , 1970. R.H. Crawford, MOSFET in C i r c u i t Design, New York, McGraw-Hill Co., 1967. D.J. Dooley, Ed., Data Conversion I n t e g r a t e d C i r c u i t s , New York, IEEE Press, 1980. M.I. Elmasry, Ed., D i g i t a l MOS I n t e g r a t e d C i r c u i t s , New York, IEEE Press, 1981. J . Flemming, and W. F r e z z a , NAPLPS: a new standard f o r tex t and g r a p h i c s , BYTE, 8, February 1983, 203-254. J.H. F r i e d r i c h , A c o i n c i d e n t - s e l e c t MOS storage a r r a y , IEEE J o u r n a l of S o l i d S tate C i r c u i t s , SC-3, September, 1968, 280-285. P.H. G a r r e t t , Analog I/O Desgin - A c q u i s i t i o n , Conversion, Recovery, New York, Reston P u b l i s h i n g Company, 1981. A.B. Grebene, Analog In t e g r a t e d C i r c u i t Design, New York, Van Nostrand Reihhold Co., 1972. D.A. Hodges, Large c a p a c i t y semiconductor memory, Proc. IEEE, 56, J u l y 1968, 1148-1162. R.J. H o l l i n g s w o r t h , A.C. I p r i , and C S . Kim, A CMOS/SOS 4K s t a t i c RAM, IEEE J o u r n a l of S o l i d S t a t e C i r c u i t s , SC-13, October 1978, 664-668. R.W. Hon, and C H . Sequin, A Guide to LSI Implementation, Tech. Rep., SSL-79-7, Xerox Palo A l t o Research Centre, 1979. 77 [Howe8l] [ l s o b 8 l ] [ K l e i 6 9 ] [Mead80] [NAPL81 ] [Shic68] [Spec83] [Stew77] [Susu73] [Taru69] M.J. Howes, and D.V. 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Hodges, Modeling and s i m u l a t i o n of i n s u l a t e d - g a t e f i e l d - e f f e c t t r a n s i s t o r s s w i t c h i n g c r c u i t s , IEEE J o u r n a l of S o l i d S t a t e C i r c u i t s , SC-3, September 1968, 285-289. S p e c i a l Issue on VLSI Design: Problems and T o o l s , Proceedings of the IEEE, 71, January 1983. R. Stewart, High d e n s i t y CMOS ROM, IEEE J o u r n a l of S o l i d S t a t e C i r c u i t s , SC-12, October 1977, 503-506. Y. Susuki, K. Odagawa, and T. Abe, Clocked CMOS c a l c u l a t o r c i r c u i t r y , IEEE J o u r n a l of S o l i d S t a t e C i r c u i t s , SC-8, December 1973, 462-469. Y. T a r u i , et a l . , A 40-ns 144-bit n-channel MOS-LSI memory, IEEE J o u r n a l of S o l i d S tate C i r c u i t s , SC-4, October 1969, 271-279. [T o r i 7 8 ] Y. Torimaru, K. Miyano, and H. Tokeuchi, DSA 4K s t a t i c RAM, IEEE J o u r n a l of S o l i d S tate C i r c u i t s , SC-13, October 1978, 647-650. [Vlad80a] A. V l a d i m i r e s c u , and S. L i u , The s i m u l a t i o n of MOS i n t e g r a t e d c i r c u i t s u s ing SPICE2, Tech.Rep., UCB/ERL M80/7, Department of E l e c t r i c a l E n g i n e e r i n g , U n i v e r s i t y of C a l i f o r n i a at Berkeley, February 1980. [Vlad80b] A. Vladimirescu,-A.R. Newton, and P.O. Paderson, SPICE V e r s i o n 2G.1 User's Guide, Department of E l e c t r i c a l E n g i n e e r i n g , U n i v e r s i t y of C a l i f o r n i a at Berkeley, October 1980. 

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