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An investigation of defects in gallium arsenide using the DLTS technique Shi, Yi 1989

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A N I N V E S T I G A T I O N O F D E F E C T S IN G A L L I U M A R S E N I D E USING T H E DLTS  TECHNIQUE  by Y i SHI B . Sc., East C h i n a N o r m a l University, C h i n a , 1982 M . Sc., University of M a n i t o b a , C a n a d a , 1986 A THESIS S U B M I T T E D IN PARTIAL F U L F I L L M E N T O F T H E REQUIREMENTS F O RT H E D E G R E E O F M a s t e r of A p p l i e d Science in T H E F A C U L T Y O F G R A D U A T E STUDIES (Department of E l e c t r i c a l Engineering) We accept this thesis as conforming to the required standard  T H E UNIVERSITY OF BRITISH COLUMBIA A p r i l 1989 ©  Y i S H I , 1989  In  presenting  degree at the  this  thesis  in  University of  partial  fulfilment  of  of  department  this thesis for or  by  his  or  requirements  British Columbia, I agree that the  freely available for reference and study. 1 further copying  the  representatives.  an advanced  Library shall make it  agree that permission for extensive  scholarly purposes may be her  for  It  is  granted  by the  understood  that  head of copying  my or  publication of this thesis for financial gain shall not be allowed without my written permission.  Department The University of British Columbia Vancouver, Canada  DE-6 (2/88)  ABSTRACT  A well-known technique—Deep level Transient Spectroscopy ( D L T S ) — w a s used for investigating deep levels i n G a l l i u m Arsenide ( G a A s ) semiconductor material. E i g h t deep levels, among t h e m the most i m p o r t a n t deep level EL2,  were found in  L i q u i d - E n c a p s u l a t e d C z o c h r a l s k i ( L E C ) grown semi-insulating G a A s substrates. T w o of these deep levels, one electron deep level and one hole deep level, were observed for the first t i m e i n D L T S studies. B o t h have large t h e r m a l a c t i v a t i o n energy. A study in understanding the f o r m a t i o n of deep levels i n the G a A s substrate was actively undertaken. T h e cause of four deep levels present i n the L E C - g r o w n G a A s substrate were identified. T h e chief effects on electronic devices a n d integrated circuits due,to the presence of these deep levels i n the G a A s substrate were p a r t i a l l y characterized. O t h e r contributions include: firstly, a computer-assisted m e t h o d was used to profile the spatial d i s t r i b u t i o n of deep traps. Deep traps act as free carrier traps w h e n deep levels are present i n semiconductor bulk m a t e r i a l . Secondly, the author, through experiments, made clear that the increasing capacitance of a S c h o t t k y diode increasing w i t h temperature was due to the S c h o t t k y diode's barrier height decreasing w i t h rising temperature. T h i r d l y , the author, by experimental results, supported the point that shallow donor w i t h very high concentration i n the bulk m a t e r i a l is the major cause of a n n i h i l a t i o n of EL2 deep traps.  ii  TABLE OF CONTENTS  ABSTRACT  ii  LIST OF T A B L E S  v  LIST OF FIGURES  vi  ACKNOWLEDGMENTS  viii  C h a p t e r 1: I N T R O D U C T I O N  1  1.1 GaAs Devices  1  1.2 Defects and Deep Levels  2  1.3 Deep Level Transient Spectroscopy  4  1.4 Author's Contributions To D L T S Research  6  1.5 Thesis Layout  7  C h a p t e r 2: D L T S T H E O R Y  8  2.1 Transition Equation of Deep Level and Fermi Function  8  2.2 Thermal Capture Cross Section and Thermal Activation Energy For Deep Level  18  2.3 Deriving the Formula Used To Calculate Spatial Distribution of Deep Traps  20 C h a p t e r 3: E X P E R I M E N T A L I N S T R U M E N T S and S A M P L E S  26  3.1 Experimental Instruments  26  3.1.1 M M R Refrigerator  28  3.1.2 Boonton Model 72BD Capacitance Meter  32  3.1.3 Boxcar Averager and Gated Integrator  33  iii  3.2 Samples and Their Fabrication  37  3.2.1 Mask  37  -.  3.2.2 Fabrication Procedures  38  Chapter 4: DATA ANALYSIS AND EXPERIMENTAL RESULTS  45  4.1 Data Analysis Using Conventional DLTS Technique  45  4.1.1 The Determination of Maximum Rate Window For Conventional DLTS Scans  45  4.1.2 Non-Exponential Transient Capacitance  51  4.1.3 Mathematical Treatment To Data Obtained From DLTS Scans  53  4.2 Results of DLTS Scans  55  4.2.1 Description of the Shift of Peak Position In Doping Concentration  55  4.2.2 Description of the Identification of Deep Levels  57  4.2.3 Identification of Deep Level EL2  62  4.2.4 Concentration of EL2 Deep Traps  65  4.2.5 Investigation On the Annihilation of EL2 Deep Traps  65  4.2.6 Variation of Capacitance With Temperature  70  Chapter 5: CONCLUSIONS AND SUGGESTIONS FOR FURTHER RESEARCH  77  REFERENCES  79  Appendix: FABRICATION PROCEDURES OF MESFETs USED FOR DLTS SCANS  83  iv  LIST O F T A B L E S Table 4.1: Properties of deep levels found from LEC-grown GaAs.  LIST O F F I G U R E S Fig. 2.1: Energy band diagram of a semiconductor with a single deep level  9  Fig. 2.2: Schematic of Schottky diode under a bias waveform  12  Fig. 2.3: Schematic of Schottky diode under a bias waveform and its transient capacitance  19  Fig. 2.4: The thermodynamical process of emitting electrons of a deep level  22  F i g . 3.1: Block diagram of configuration of the DLTS system  27  F i g . 3.2: Sample mounting surface assembly.  29  Fig. 3.3: Exploded view of MMR probe stage  31  Fig. 3.4: The signal processing of the Boxcar system  34  Fig. 3.5: Exponential averaging as a function of time in the channel A and the channel B  36  F i g . 3.6: Tilt and rotation angle of the GaAs wafers  39  F i g . 3.8: Fabrication sequence for patterning sample 686/70CP  41  F i g . 3.9: Fabrication sequence for patterning sample 686/70NC  43  F i g . 4.1: A typical spectrum of DLTS scan  47  Fig. 4.2: Variation of peak position with change of maximum rate window. 49 F i g . 4.3: Arrhenius Plot for deep levels found from LEC-grown GaAs substrates  50 F i g . 4.4: Transient capacitance of one experimental sample at  vi  T = 300 °K  52  Fig. 4.5: Effect of smoothing average routine on DLTS signal  56  F i g . 4.6: Doping concentration of sample 686/70CP and of sample 686/70NC  58  Fig. 4.7: EL2 configuration  63  F i g . 4.8: Concentration of the EL2 deep traps  66  F i g . 4.9: Electric field versus the emission rate of the EL2 deep traps  67  Fig. 4.10: Barrier height of Schottky diode versus leakage current density  69  F i g . 4.11: Doping concentration of various samples  71  Fig. 4.12: C — V plots of Schottky diode at T = 290 °K and T = 400 °K  73  F i g . 4.13: Barrier height of Schottky diode versus temperature  vii  74  ACKNOWLEDGMENTS I a m deeply grateful to m y supervisor, D r . Lawrence Y o u n g , for his technical guidance and generous financial support. His many intellectually s t i m u l a t i n g suggestions p r o v i d e d me i m p o r t a n t access to the research leading to this thesis. I c o u l d not have accomplished the research w i t h o u t technical and emotional support from a l l staff and m y fellow graduate students i n the solid-state group of this department.  A m o n g them, M r .  P . M a t z is specifically thanked for his help  i n fabricating experimental specimens.  M r . N . Jaeger, M r . H . K a t o and M r . D .  Sutherland are also t o be thanked for discussions and suggestions. I a m v e r y indebted to M r .  D . H u i for f a m i l i a r i z i n g me w i t h experimental  instruments a n d for fixing facilities used for m y experiments. In a d d i t i o n , I appreciate his suggestions i n the explanation of many experimental phenomena.  viii  Chapter 1  I N T R O D U C T I O N  In evaluating the quality of semiconductor materials as well as i m p r o v i n g performance of electrical devices a n d integrated circuits, it is essential for the material manufacturer and the electronics designer to assess the defects in semiconductor mater i a l , a n d their effects on the performance of electronic devices and integrated circuits. A powerful technique—Deep Level Transient Spectroscopy ( D L T S ) — i s widely used to accomplish this. In this thesis, the D L T S technique was employed to conduct an i n vestigation to find defects in L i q u i d - E n c a p s u l a t e d C z o c h r a l s k i ( L E C ) g r o w n G a l l i u m Arsenide ( G a A s ) substrates. T h e results of the D L T S study show that two new deep levels are observed for the first time. D L T S technique is also modified to profile spatial d i s t r i b u t i o n of deep traps. A study related to a n n i h i l a t i o n of the ELI deep traps and an investigation of the S c h o t t k y diode's capacitance variation w i t h temperature are included in this thesis as well.  1.1  G a A s Devices  G a l l i u m A r s e n i d e , being a semiconductor material i n the III-V compound family, has h i g h m o b i l i t y , h i g h t h e r m a l c o n d u c t i v i t y , h i g h efficiency i n opto-electronic conversion a n d broad R F b a n d w i d t h compared to silicon and g e r m a n i u m . Therefore,  1  G a A s is an ideal candidate for developing high speed transistors for telecommunicat i o n , logic a n d digital integrated circuits. M e t a l - S e m i c o n d u c t o r F i e l d Effect T r a n sistors ( M E S F E T s ) fabricated o n G a A s substrates have demonstrated unparalleled performance as microwave devices w o r k i n g at u l t r a - h i g h frequency. Moreover, G a A s appears very p r o m i s i n g for high speed s w i t c h i n g device. Electronic devices a n d integrated circuits after fabricated o n G a A s substrate sometimes do not work as expected. T h e existence of defects in the G a A s substrate is a major reason for electronic devices and integrated circuits to fail their n o r m a l performance. Defects are omnipresent i n bulk m a t e r i a l , at the surface, a n d the interface between the active layer a n d the semi-insulating substrate. F o r this reason, an active field of research has developed i n the identification a n d characterization of defects i n semiconductor materials as well as i n the discovery of the materials' electronic and t h e r m o d y n a m i c properties.  1.2  Defects a n d D e e p Levels  Defects are generally categorized into t w o kinds:  (i) the intrinsic or native  defects a n d , (ii) i m p u r i t y defects. F o r m a t i o n of the first k i n d is caused b y structural damage of the lattice, such as point defects, dislocations a n d m a t e r i a l inhomogeneity. C r y s t a l l i n e vacancies, interstitials and antisites are the three major types of point defects i n semiconductor crystals. Intrinsic defects include point dislocation and line dislocation. Defects of the second k i n d are caused by foreign atoms substituting for atoms w h i c h n o r m a l l y constitute the lattice of semiconductor. T h e chief effect of defects i n G a A s is that a number of specific energy levels  2  are present i n the forbidden zone, i.e. i n the energy bandgap between the b o t t o m of the c o n d u c t i o n b a n d a n d the top of the valence b a n d . These specific energy levels w i t h a t h e r m a l activation energy greater t h a n 8 0 m e V below the b o t t o m of the cond u c t i o n b a n d or above the top of the valence b a n d are called deep levels [l]. T h e most i m p o r t a n t deep level EL2 has a t h e r m a l activation energy 0.82eV below the b o t t o m of the c o n d u c t i o n b a n d . Since the bandgap for G a A s is 1.424eV at r o o m temperature, the deep level EL2 is often referred to mid-gap deep level. O n the other h a n d , the characteristic of a shallow donor or acceptor is that it is fully ionized at room temperature. T r a p s , recombination a n d scattering centers are the three c o m m o n formations of the defects. Deep traps w h i c h capture electrons or holes a n d , then t h e r m a l l y emit electrons or holes to the conduction band or valence b a n d , are defined as electron deep traps a n d hole deep traps, respectively. In most semiconductor materials the presence of defects is undesirable. E v e n w i t h defect concentration very s m a l l compared to the free carrier concentration, devices, w h i c h are usually fabricated on a t h i n active layer on the top of semi-insulating m a t e r i a l or embedded i n bulk semiconductor m a t e r i a l , are s t i l l so sensitive to different types of defects that they fail n o r m a l i m p l e m e n t a t i o n . Effects on devices due to the presence of defects are: I - V characteristic looping, low b r e a k d o w n voltage i n power field effect transistors, large microwave noise figure, variations i n transconductance versus frequency, a b n o r m a l light sensitivity, low saturation current. In a d d i t i o n , leakage current is induced by defects between the a c t i v a t i o n layer a n d the passivation layer. A n o t h e r k i n d of defect—surface state defects p r o d u c e d b y dangling bonds on the wafer surface near the edge of the gate electrode—gives rise to a n artificial increase  3  of the gate length leading to decrease of gain with frequency [2]. Inhomogeneous distribution of clusters containing defects in bulk material makes the transistor's threshold voltage unstable. As a result, effects of defects in semiconductor materials become increasingly important as the scale of device is reduced and as multi-layer devices are introduced. Defects in the GaAs, however, can be used for improving devices' characteristics. Some impurity defects can increase switching speed of transistors, because those sorts of defects are able to reduce the minority carrier lifetime. Some impurity defects can be used to increase resistivity of the substrate in which devices are fabricated [3]. One well-known example is that deep acceptors in GaAs produced by impurities (chromium) can compensate the shallow donors so that semi-insulating material is produced. Liquid-Encapsulated Czochralski (LEC) GaAs demonstrates an unequaled property of being a semi-insulating material. This is attributed to compensation of shallow acceptors (carbon) in the bulk material by the deep level EL2 [4-6]. The carbon present in LEC-grown GaAs substrate results from GaAs being contaminated by carbon heating elements during its crystal growth. This property has been widely used in the fabrication processes of monolithic microwave circuits, and fast digital and logic integrated circuits.  1.3  Deep Level Transient Spectroscopy  For the manufacturers of semiconductor materials as well as for the users of the materials, it is crucial to know an effective way to eliminate those undesirable defects in the bulk material. Deep Level Transient Spectroscopy (DLTS) is a powerful  4  technique for users to detect deep levels sensitively, rapidly and directly [7]. Moreover, the DLTS technique can also provide important information relevant to the deep traps' concentration, thermal activation energy and thermal capture cross section. A capacitance transient results from the fact that free carriers are gradually released by deep traps and thermally emitted to the conduction band or valence band. When electrons are captured by electron deep traps, the depletion depth of the Schottky diode becomes larger. As a result, the capacitance of the Schottky diode becomes smaller. When electrons escape from electron deep traps after they acquire enough thermal energy, the depletion depth of the Schottky diode becomes smaller. The capacitance of the Schottky diode then becomes larger after electrons are released by deep traps and thermally emitted to conduction band. This converse process is called detrapping. The emission rate of the deep traps is directly related to the temperature. Therefore, the capacitance transient is strongly temperature dependent. In DLTS signals, different deep levels are spectroscopically resolved from one another. Each peak in the DLTS spectrum (temperature versus amplitude from subtraction of transient capacitance sampled at two particularly selected times) shows a deep level. The peaks are uniquely determined by the thermal emission properties of the deep traps. If one peak in the DLTS spectrum is positive (the amplitude greater than zero), the positive peak represents a hole deep level. On the contrary, a negative peak (the amplitude smaller than zero) in the DLTS spectrum represents an electron deep level.  5  1.4  A u t h o r ' s C o n t r i b u t i o n s T o D L T S Research  D L T S research was conducted o n L E C - g r o w n G a A s substrates.  Results of  investigation show eight deep levels are present i n L E C - g r o w n G a A s . A m o n g them, two are hole deep levels, the rest are electron deep levels. T h e most i m p o r t a n t electron deep level, EL2, was observed. Its t h e r m a l activation energy below the b o t t o m of the c o n d u c t i o n b a n d (E  c  — ET) and capture cross section (a ) n  E c  are:  and  E  T  =  0.82eV,  a„  =  3.34 x 1 0 - 1 3 c m _ 2  (1.1)  A m e t h o d , namely the " M o d i f i e d D L T S T e c h n i q u e " , w h i c h is developed from D L T S technique, is employed to profile the concentration of deep traps [8,9].  The  author's research shows that EL2 i n L E C - g r o w n G a A s substrate has a peak concent r a t i o n as h i g h as 2 x 1 0 1 5 c m ~ 3 . T h e author found the deep level EL2 only i n one S c h o t t k y diode, though it is widely believed that EL2 exists universally i n G a A s substrate so that one should be able to find EL2 f r o m every sample used for D L T S scans. A f t e r careful investigation, the author agrees that a large p o r t i o n of EL2's deep traps has been annihilated by shallow donor w i t h considerably high concentration (above 2 x 1 0 1 7 c m ~ 3 )  [2].  A n o t h e r interesting phenomenon observed is that capacitance always varies w i t h changing temperature whether or not a reverse bias is applied to the Schottky diode's gate. T h e phenomenon is a t t r i b u t e d to the v a r i a t i o n of Schottky barrier height w i t h temperature [10].  6  1.5  Thesis L a y o u t  Chapter 2 explains the theory of the DLTS, and the Modified DLTS Technique as well as the capacitance transient.  A detailed description of experimental  instruments and fabrication processes of experimental samples is given in Chapter 3. Chapter 4 includes a list of deep levels and their intrinsic characteristics as well as data analysis. Conclusions of this research and suggestions for further DLTS studies are included in Chapter 5. References and appendix finally follow the Chapter 5.  7  Chapter 2  DLTS  THEORY  Three major parameters required to generally characterize a deep level are: thermal activation energy, thermal capture cross section, and concentration of the deep traps. The thermal activation energy is the effective free energy required to excite free carriers from a deep level to energy band edge. The thermal capture cross section represents the probability for a free carrier to be trapped in a deep trap. The concentration is determined by the spatial distribution of the deep traps in the substrate.  2.1  T r a n s i t i o n E q u a t i o n of D e e p L e v e l a n d F e r m i F u n c t i o n  To aid discussion of the transition process of deep levels, the energy band diagram of a semiconductor with a single electron deep level is drawn in Fig. 2.1. In Fig. 2.1, NC and NV are the effective density of state in the conduction band and in the valence band, respectively. NT(X) is the total concentration of deep traps. Shallow donor and acceptor concentrations, when they are completely ionized, are denoted by  N£(x)  and  N^(x).  The capture rate and the emission rate of the deep  traps are denoted by c n and e„, respectively, while n is the concentration of free n  carrier. 8  EC  cn  e,•n  n  1.  EV  F i g u r e 2.1: E n e r g y b a n d d i a g r a m of a semiconductor w i t h a single deep level. EE and EV denote the b o t t o m of the conduction b a n d and the top of the valence band while ED a n d EA s t a n d for energy levels of shallow donor and acceptor, respectively. The effective free energy of the electron deep level is denoted by ETW h e n a shallow donor loses an electron, i t is ionized. However, shallow donor a n d acceptor w i l l be deionized when they are at low temperature. Therefore, a n d N^(x) are replaced b y  ND{X)  and  (x)  respectively. In the process of deion-  NA(X),  i z a t i o n , a shallow donor captures a n electron while a shallow acceptor captures a hole. T h e t r a n s i t i o n process illustrated in F i g . 2.1 can be formulated b y the rate equations of charge carrier p o p u l a t i o n at the deep level as  rfnr(x, t) dt  = c n\N {x) - n {x,t)) n  T  T  9  e n {x,t) n  T  (2.1)  where n (x,t) T  is the concentration for those deep traps in which electrons filled, and  x is the distance in the substrate from the metal-semiconductor interface. The general solution of the above ordinary differential equation is given by  n {x,t)  =  T  e-^ ^  -  n+e  {N {x)—" cn + e T  n  n  xe " »I' +Const.} [e  (2.2)  n+e  By applying the initial condition, t=0, n (x,0)  = N (x)——— cn  T  T  n  -f-  en  + Const.  (2.3)  and the final condition, t=oo,  n (i,oo) = N {x) T  T  C n  "  (2.4)  The Const, in Eq.(2.2) then becomes  Const. = n-r(x,0) — nx(x,oo)  (2-5)  Therefore, Eq.(2.2) reduces to [11]  n (x,t) T  = n r (x,oo) + [n (x,0) T  - nT(x,oo)] • [exp(—)} T  where r is defined as the rate window or the time constant 10  (2.6)  Fig. 2.2 gives the band diagram of a Schottky diode under a bias waveform, the Fermi function at T - 0 °K, and T > 0 °K, and the bias waveform. Fig. 2.2, solid lines indicate energy bands when a reverse bias (VR) of the bias waveform is applied to the Schottky diode, while VH is the barrier height, x is defined as the distance in the substrate from the metal-semiconductor interface.  XR denotes the depth of  the depletion region while xR — X„(t) is the distance from the metal-semiconductor interface to the crossing point where the deep level intersects the Fermi-level. Bands start becoming fiat after x is greater than XR.  A„(<) indicates the length of the  depletion region in which the thermal energy of the deep traps is less than the Fermi level. The deep traps in this particular region are fully filled with electrons, and hence their electronic charge state is neutral. This particular region is called as the neutral region. On the other hand, deep traps above the Fermi level, due to their thermal energy greater than the Fermi level, emit their electrons. The deep traps in the region from the metal-semiconductor interface to the crossing point are empty, because their thermal energy is greater than the Fermi level. Their electronic charge state is positive. The region with a depth of XR — A„(£) is named the ionization region, because the deep traps are empty in this region. The deep trap concentration in the ionization region is denoted by N}(x,t), denoted by  NT{X).  while the total deep trap concentration is  The mathematical correlation of the deep trap concentration in  the ionization region and the total deep trap concentration is according to [12]  11  METAL  n-TYPE SEMICONDUCTOR  F i g u r e 2.2: Schematic of the Schottky diode under a bias waveform. ( A ) b a n d diagram, (B) the F e r m i function, a n d (C) the bias waveform w h i c h is applied to the Schottky diode.  12  N}(x,t)  = NT{x)[l  - exp—}  (2.8)  T  When a filling bias of the bias waveform ( V? in Fig. 2.2) is applied to the Schottky diode, energy bands in Fig. 2.2 are drawn by dashed lines. The depth of depletion zone is now denoted by xp, while the length of the neutral region is denoted by  XF{t).  The electron Fermi function, / „ , is defined as a ratio of the concentration of electron filled deep traps to the total deep trap concentration [11]. Due to the nonuniformity of the deep trap concentration in GaAs active layer, non-equilibrium electron Fermi function / „ is a function of x and t, and is expressed as  According to Eqs.(2.1) and (2.9), the probability equation of finding an electron in a deep level per unit time is given  dfn{x,t)  =  d\nT{x,t)/NT{x)}  dt  dt  =  -[cnn + en)fn(x,t)  + c„n  (2.10)  When a reverse bias is applied to the Schottky diode for a long enough time, i.e. t = oo, thermodynamical process of the Schottky diode reaches a steady state. Therefore,  13  nT(x,t)  = nT{x,oo)  (2-11)  From Eq.(2.4), we can derive the steady state Fermi function in h-type active layer as  f  /  fn[X,  s  nT(x,oo)  cnn  NT(X)  cnn + en  OO) = ——r-r- - — — —  (2.12)  As stated previously, the deep level is separated into two region, the ionization region and the neutral region. If thermal electron excitation between the two regions is neglected, the Fermi function in the neutral region, due to all electron energy levels being entirely filled with electrons, is equal to unity. The Fermi function in the ionization region, due to all electron energy levels being entirely empty with electrons, is equal to zero. Therefore, the neutral region in the steady state has a length of Xn(t =  oo) while the ionization region in the steady state has a length of W{x, oo) — Xn(t = oo). The steady state Fermi functin is expressed as [13]  , / (x,oo) = { e"+e> 1 n  0 < x < Wit = oo) - XJt = oo) W{t = oo) - Xn(t = oo) < x < W(t = oo)  (2.13)  where x originates from the metal-semiconductor interface and W{t = oo) denotes the depth of the depletion zone. ep is the emission rate for hole deep traps. From Eq.(2.6), we can directly formulate an expression for the transition of occupied electron energy levels from an initial distribution to the final equilibrium as  14  / » ( * , 0 = fn(x, oo) + [f {x, 0) - / „ ( * , oo)]exp(—) n  (2.14)  where the rate window r = [c„n + e „ ] _ 1 . In order to easily approach the solution, an assumption that doping concentration and deep trap concentration in the active layer is homogeneous is made. By double integration of Poisson's equation, we can obtain a mathematical expression for variation of depletion depth with time [13]  8W{t) dt  _  N (x)  f _df {x,t) w  T  W(t =  n  oo)N {x) d  where N [x) is the doping concentration which is equal to shallow donor concentration d  in the n-type semiconductor.  NT{X)  is supposed to be much smaller than N (x). d  W{t = oo) is the depth of  the depletion zone of the Schottky diode when it is in the steady state. If capacitance (C(t)) is inversely proportional to W (t), Eq.(2.15) can be deduced to  AC{t) C(t = 00)  _  AW{t)  ~  W(t = 00)  where AC{t) is called DLTS signal. If the Schottky diode under a reverse bias is completely in darkness, we can assume that the deep traps in the depletion region emit much more electrons than 15  capture them, i.e. c n <C e . Thus, the rate window is replaced by n  n  r = -  .  (2.17)  According to Eq.(2.14), the Fermi function can be expressed as  f {x,t)  = / „ ( x , o o ) + [/„(x,0) - /n(x,oo)]exp(-enf)  n  (2.18)  Using the expression of the Fermi function in Eq.(2.18), AC(t) can be deduced to  AC(i)  t{nH3  JVWx) = -W>[t  =  w{t=oo)  ,  f  Lm,)Jo  ,  „  #  ,  A U ^ ) - U ^ o o ) ] e x  P  { - e  n  t )  d  (2.19)  x  As previously mentined, the ionization region is restricted into 0 < x < W(t = oo) — X (t = oo), where n  / ( i , 0 ) = 1,/n(x,oo) = n  —  (  2  .  2  0  )  and the neutral region is in W(t = oo) — X (t = oo) < x < iy(f = oo), where n  / „ ( x , 0 ) = 1 and /n(x,oo) = 1, because deep traps in the neutral region are filled with electrons all the time. Thus, Eq.(2.19) becomes: 16  (2.21)  AC{t)  _  C(* = oo)  ~  NT{x) ~W {t  = oo)Nd{x)  2  rW(t=oo)-\ (t=oo) n  { /  x[/n(x,0) - / „ ( x , oo)]exp{-ent)dx  Jo  rW(t=oo)  +  /  x[/„(x,0) -  fn(x,oo)}exp(-ent)dx}  ./W(t=oo)-A„(t=oo)  - n r+^ e]p J > W 2 (* = oo)7Vd(x):l2Ul l i e N  t  {  x  )  {[W 2 (« = 0 0 ) - X 2n{t = 00)] + 0}exp(-erif) N  T  {  X  h  2/Vd(x)1  l - 3 ^2 ) ( T ^ , l) * M - e  W (f = oo) e n + ep  n  t )  (2.22)  Observing Eq.(2.22), we can write  N  T  {  X  27Yd(x)L  H - B ^ H t ^ - ) > 0  )  (2.23)  W 2(t = oo) e + e, Jv  n  since An(f = 00) is always smaller than W(t = 00) Thus,  NT[X)  r  27Yd(x)1  A 2 (i = 00) ..  e„  .  ,  1^2(< = oo) J v e n + e)  Therefore,  Since ep <C e„ in n-type semiconductor, we can simply let  17  e  e  " e be unity. i'  It can easily be concluded that AC[t) increases exponentially with time, since AC(oo) equates to zero. If one chooses AC(t) = C(t) — C(ti),  one can obtain a  transient capacitance {C(t)) expression as  C(t) = C{h)[l  - exp{-ent)\  (2.26)  where C(ti) is equal to  C ( <  =  2^R(l-^(t  TO)  = oo)1  ( 2  "27)  This transient capacitance (C(t)) is shown in the Fig. 2.3(c).  2.2  T h e r m a l C a p t u r e Cross Section a n d T h e r m a l A c t i v a t i o n E n e r g y F o r Deep Level  Arrhenius plots are frequently employed to obtain the thermal activation energy and thermal capture cross section of deep levels. All data points in Arrhenius plots are basically derived from the following equation as given by Martin et al. and Mitonneau  et al. [14,15]  en = 7 o~ r ejp(— ^ ° ^ ) n  n  2  e = lpOpT 2exp(  u r  T  p  KJ.  18  for electron deep level  (2.28)  ") for hole deep level  (2.29)  S  G  n-TYPE ACTIVE LAYER  W(t = o-) )W(t  D  = oo)l  w{t=o r +  (A)  SEMI-INSULATING GaAs SUBSTRATE  Figure 2.3: Schematic of a Schottky diode under a bias waveform and its transient capacitance. (A) depletion depth of a Schottky diode under the bias waveform, (B) the bias waveform, (C) transient capacitance under the bias waveform. 19  where  EC — ET = thermal activation energy of the electron deep level ET — EV = thermal activation energy of the hole deep level en = thermal electron emission rate e = thermal hole emission rate p  on = thermal capture cross section for electrons a = thermal capture cross section for holes in n-type material p  7„ = 2.3 x 1020 cm- K~ s2  2  7 P = 1.7 x 1021 cm~ K~ s~ 2  (for electron)  1  2  l  (for hole in n-type material)  k — Boltzmann constant  2.3  D e r i v i n g the F o r m u l a U s e d T o C a l c u l a t e S p a t i a l D i s t r i b u t i o n of the Deep Traps  The Modified DLTS Technique has high resolution to detect a minute amount of deep traps and their spatial distribution in semiconductor materials. The mathematical relation between the depletion width and capacitance is according to [16]  20  where e is the permittivity of semiconductor, A is the area of the Schottky diode and s  W(t = oo) is the depletion width. Double integration of Poisson equation from the point where Fermi level crosses the deep level to the boundary of the depletion zone yields  (2.31)  For a uniform distribution of shallow donor, \ (t n  = oo) is easily derived by  taking N (now a constant) out of the integral as [17] d  (2.32)  Nevertheless, Eq.(2.31) is difficult to solve if the shallow donor is non-uniformly distributed (N = N (x)). d  d  To obtain X (t = oo) in Eq.(2.3l), a computer-assisted n  method must be developed. In this Modified DLTS Technique, a large reverse bias whose voltage level is held constant and a filling bias (usually a small reverse bias) whose voltage level changes from run to run are alternately applied to the Schottky diode to measure the concentration of deep traps versus distance in the substrate from the metal-semiconductor interface. During the period that the reverse bias is applied to the Schottky diode, the deep traps whose thermal energy is now above the Fermi level start emitting electrons. The thermodynamical process of emitting electrons is depicted in Fig. 2.4. In Fig. 2.4, 21  METAL  n-TYPE A C T I V E LAYER  the distance from crossing point of the Fermi level with deep level to the boundary of the depletion region is denoted by Xn(t = oo). The depth of depletion layer is denoted by W0 when the large reverse bias is applied on the Schottky diode, where x P l , and xP2 represents the depth of depletion region when two filling biases with different voltage levels are applied to Schottky diode, respectively. The rationale of the technique is that deep traps in the substrate are laminally detected.  Since deep traps outside the depletion zone are always filled with  electrons, they will not be involved in the thermodynamical process of emitting electrons. Therefore, only those deep traps which reside inside the depletion zone undergo thermal interaction with free carriers. The boundary of the depletion zone is determined by the voltage level of the large reverse bias applied to the Schottky diode. A magnitude, |x P 2 -x P l | which is determined by depth of the depletion region of the Schottky diode under filling bias VP2 minus that of Schottky diode under filling bias V P l , is called a window as depicted in Fig. 2.4. If the voltage level of the filling biases Vp is slightly different from that of the filling biases VPl, the window is very small. 2  Therefore, one is able to locally detect deep traps through measuring DLTS signals, and to spatially profile the deep traps concentration. After a double integration of Poisson's equation in the renge from metalsemiconductor interface to the boundary of depletion region for the Schottky diode under a reverse bias, we obtain [18]  +  xNT{x)[l  - exp{-ent)]u{x  23  - [W(t = oo) - Xn(t = oo)}}dx  (2.33)  where VBI is the built-in potential of the Schottky diode, VR is the large reverse bias voltage level. The function u{z} has the form as .0  u{z}  for z < 0  1  for z > 0  At the end of the large reverse bias, a filling bias (a small reverse bias) is applied on the Schottky diode in order that deep traps are filled with electrons. Again, through integrating Poisson's equation twice, we have  VBI + VP  =  / ee Jo  +  xNT(x)[l  xNd{x)dx - exp(-ent)}u{x  - [xp(t = oo) - X'n(t = oo)]}dx  (2.34)  where xp(t = oo) is the boundary of the depletion zone under the small reverse bias,  X'n(t = oo) is the distance from the crossing point of the deep level with the Fermi level to the boundary of the depletion zone under the small reverse bias, VP. By making the voltage level of the reverse bias VR is slightly different from the voltage level of the filling bias VP, one can let xp(t = oo) ~ W(t = oo). Subtracting Eq.(2.33) from Eq.(2.34), we obtain  Vr-Vp  =  -{/ €  t  +  xNd{x)dx Jx (t=c l>V '-°°) v  W(«=oo)-A^(«=oo)  24  XNT{X)\1  —  exp(—ent)]dx}  (2.35)  Assuming that the large reverse bias is held constant and the small reverse bias is varied from run to run, we can derive the relation for two small reverse biases with different voltage level, V  P2  P,- VP>  =  V  and V P l , by using Eq.(2.35) as  xNd{x)dx-  - ( /  xNd{x)dx]  £„ Jx (t=oo)  Jx (t=oo)  Pl  P2  /•W(t=oo)-A„1(t=oo)  Q  + f[l-exp(-ent)}  xNT(x)dx  (2.36)  The primary solution of Eq.(2.36) was acquired through a hard and tedious integration and was given by [9]  JVr|x - W{t = oo)] -  W  !  (  ( =  o o )  _A;  i ( (  =  o c ) ] C » F ( ( = oo)]  ( 2  ;37»  However, Eq.(2.37) is modified in attempting to improve accuracy when it is experimentally used. In practice, the formula actually used in calculating the spatial distribution of the deep traps is [8]  NT[x  - W(t - oo)] _  {  x  l  {  t=  _  =  ^  =  (2.38)  where A C j is the amplitude from subtraction of the transient capacitance sampled at two particularly selected times when a filling bias voltage level V and a large reverse pi  bias voltage level V are alternately applied on the Schottky diode. A C 2 has the same r  meaning as A C i except that the filling bias voltage level V filling bias voltage level V . P2  25  pi  is replaced by another  Chapter 3  E X P E R I M E N T A L I N S T R U M E N T S and S A M P L E S  3.1  E x p e r i m e n t a l Instruments  The block diagram of the DLTS system in which data are stored and analyzed is shown in Fig. 3.1. The HP9816 Personal Computer with a 1MB R A M acts as a heart of the DLTS system. After receiving a command from the computer, the MicroMiniature Refrigerator (MMR) K-20 Programmable Temperature Controller (MMR Controller) immediately responds to the computer and then sets up the right power of the resistor heater in the sample mounting surface of the refrigerator in order to keep a constant temperature to either the sample mounting surface or the sample. MMR Controller is able to send signals from any voltage source (maximum voltage level is 1.25 volts) through two channels in its Analog Output Port, in which signals are converted into digital form, to the computer. One of the two channels is connected to the output of the Boxcar Averager. Therefore, the signal from the output of the Boxcar Averager is read and digitally recorded in the memory of the computer. After one DLTS scan is done, all data are transferred by computer to a 5-1/4-inch floppy disc. Each floppy disc is able to store data from 15-20 scans. The Pulse Generator sends a bias waveform to Capacitance Meter. When the  26  HP  202A  Tektronix 5441  Pulse Generator  Storage Oscilloscope  EG. & G 165 Gated Integrators EG  & G 162  Boxcar Averager  Boonton 72BD Capacitance Meter  HP  9816  Personal Computer  MMR K-20 Programmable Temperature Controller  - a — MMR  Refrigerator  Figure 3.1: Block diagram of DLTS system configuration.  27  bias waveform, such as one in Fig. 2.3 (B), is applied to Schottky diode, a transient capacitance is produced. The signal of the transient capacitance (in voltage level) from the analog output of the capacitance meter is transferred to the input of the Gated Integrators which are internally connected to the Boxcar Averager, and is monitored by the Storage Oscilloscope. There are two identical Gated Integrators in the Boxcar system, namely channel A and channel B. Both can be used to sample transient capacitance The delay time to open the aperture of the channel A or the channel B can be arbitrarily selected. If the signal processing option of the Boxcar Averager is chosed as the signal in channel A minus the signal in channel B, the signal in the output of the Boxcar Averager is, therefore, XC(ti)  — XC(t2),  where X is the  amplification factor.  3.1.1  M M R Refrigerator  Through the IEEE488 bus the computer is directly connected with the MMR Controller.  The M M R Controller programmably manipulates a resistor heater in  the MMR Refrigerator, and reads the signal from the silicon diode temperature sensor so that the temperature in the sample mounting surface of the refrigerator is held constant. The highest temperature in the sample mounting surface theoretically corresponds to the highest power of the resistor heater,  1  provided that the solders  connecting the cathode and anode of the silicon diode sensor to the electrical lead connections which are embedded in the quartz supporter (see Fig. 3.2) do not melt. The sample mounting surface locates in the head of the quartz supporter. The solders are usually made of indium alloy which has a melting point about 1  The highest temperature recommended by manufacture is not to exceed 450 °K.  28  Figure 3.2: Sample m o u n t i n g surface assembly. Courtesy of i n s t r u c t i o n a l m a n u a l of the M M R Technological, Inc. 209 °C.  T h e reason that i n d i u m alloy is used i n soldering electrical connections is that  it has a very low resistivity, because one ohm added resistance i n the connections w i l l induce a —0.01 °K temperature error. T h e lowest temperature the sample m o u n t i n g surface is able to reach is restricted by the liquifying temperature of the nitrogen gas w h i c h is used to cool down temperature of the refrigerator. F i g . 3.2 shows a draft of the sample m o u n t i n g surface assembly. A n exploded view of the M M R probe stage is given i n F i g . 3.3. The  M M R K-20 P r o g r a m m a b l e Temperature Controller does not have front  panel controls other t h a n a R E S E T , since it is expected that controller w i l l be connected to a computer w h i c h w i l l act essentially as the front panel. A simple c o m m a n d w h i c h is implemented by the microprocessor i n the M M R Controller leads to an accurate change of temperature in the sample m o u n t i n g surface w h i c h directly touches the 29  specimen so that both have the same temperature after a sufficiently long period of time. Change of the temperature of the refrigerator is accomplished through turning on or off the power of the resistor heater. During cooling, the power of the resistor heater is off. The MMR refrigerator utilizes the Joule-Thomson effect. When a gas such as nitrogen is allowed to expand through a porous plug or fine capillary tube at high pressure, the gas cools. This is known as the Joule-Thomson effect. The magnitude of the effect is small, being about 0.1  °K/atm  for nitrogen at ambient temperature.  This figure can be magnified by allowing the expanded, cooled gas to pass through a counter current heat exchanger, precooling the incoming high pressure gas. This regenerative cooling continues until the gas liquifies. The M M R Controller has a built-in vacuum measurement system that can indicate vacuum of the main vacuum chamber to user. The sample mounting surface is designed to locate almost in the middle of the main vacuum chamber. A conventional vacuum gauge due to its size is not suitable. The vacuum gauge which is small enough to be installed in the miniature refrigerator is Pirani gauge. The resolution of the Pirani gauge is limited to integers from 1 to 500 militorrs, however, this is more than adequate for indicating whether the vacuum is good enough for proper refrigerator operation. In addition, the MMR Controller is able to monitor the supplied power to the resistor heater. This indicates the load margin. The power monitor can also be used to measure the power dissipation of the user's device which is mounted on the refrigerator.  By subtracting energy measured from two different situations, (i)  30  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20  Refri gerator Main Vacuum Chamber Manipulator Assembly Base Plate Filter Window Assembly 0-Rings Rubber Feet SMA Connector Cold End Assembly Vacuum Pump Out Port Gas Inlet Gas Exhaust Probe Tip Lateral Adjust Height Adjust Longitudinal Adjust Ground Receptacle Removal Holes Electrical Harness Connector  Figure 3.3: Exploded view of the MMR probe stage. Courtesy of instructional manual of the MMR Technological, Inc.  31  mounting a device and (ii) without mounting a device on the sample mounting surface within a certain temperature range, we can obtain the power dissipation of the device. The accuracy in indicating power dissipation of a device is ± 5 % when averaged over at least 10 readings. Each refrigerator is supplied by the manufacturer with a PROM which is calibrated to the refrigerator's silicon diode sensor and Pirani vacuum gauge. This PROM is mounted on a PROM board which can be plugged into the PROM port on the back panel of the MMR Controller. The manufacturer used to provide a PROM which had been properly calibrated to one refrigerator.  3.1.2  B o o n t o n M o d e l 7 2 B D Capacitance M e t e r  A Boonton Electronics Corporation's Model 72BD Digital Capacitance Meter was employed to sample transient capacitance.  The great advantage in using the  Model 72BD Capacitance Meter is that its rising time in each measurement is very small, usually less than 50 microseconds. The required rising time in measuring the test capacitor's capacitance in the DLTS scans should be less than 1 millisecond in order to allow transient capacitance to be immediately sampled.  Large rise time  will induce timing inaccuracy in sampling transient capacitance. In particular, the beginning part of transient capacitance will be distorted and even chopped by the capacitance meter. Transient capacitance starts when bias which is applied to the Schottky diode pulses fromthe filling bias voltage level to the reverse bias voltage level. Some deep traps have the property that they are thoroughly ionized at low temperature. They usually have fast time response to the change of bias at or above room temperature. In order to sample transient capacitance of these deep traps, it is 32  imperative that we employ a capacitance meter with fast measurement in the DLTS scans. The other distinguishing feature in the meter is that it contains an-independent crystal-controlled test signal source. This source provides a stable, low noise figure A C signal with a constant frequency of 1MHz and voltage level of lOOmV R.M.S. which is superimposed on the DC bias voltage level. The small AC signal contributes a stable and reliable measurement to the magnitude of capacitance of the Schottky diode. This magnitude of capacitance will not be dependent upon the DC bias voltage level and polarity, nor upon selection of the meter's measurement scale.  3.1.3  B o x c a r A v e r a g e r a n d G a t e d Integrator  The model 162 Boxcar Averager can be combined with two Model 165 Gated Integrators to form a gated signal-recovery system with exceptional versatility. This system synchronously samples the input signal with an aperture in Gated Integrator, which can be set to open at any time. A signal passing through the aperture is applied to a variable time constant integrator, the output of which is the result of exponential average of some numbers of repetitions of the signal over the aperture duration. Because the average magnitude of noise over a large number of repetitions is zero, an improvement in signal-to-noise ratio occurs. If the aperture is fixed on a single point of the input signal, the output of the Gated Integrator rises asymptotically towards the average value of the input signal at the sampled point. Fig. 3.4 depicts concisely how the Boxcar system works. In Fig. 3.4, (A) represents the transient capacitance which is transferred to the channel A and the channel  33  Figure 3.4: The signal processing of Boxcar system. (A) the input signal in the Gated Integrator, (B) triggering and the aperture delay time of the channel A and B, (C) the amplified signal in the output of the channel A and the channel B, and (D) the signal in the output of Boxcar Averager.  34  B, (B) gives aperture delay time of the channel A and the channel B, (C) shows the amplified signal in the output of the channel A and the channel B, and (D) illustrates the output signal in the Boxcar Averager. The significant feature in using Boxcar system is that it uses exponential averaging to reduce the noise-to-signal ratio. Exponentially averaging signal in channel A can be formulated as  = £  Cne A^ n~ 1^  (3.1)  n=l  where C „ is the amplitude of each sample, A is a constant with positive value, and T represents the period of triggering. When n goes to infinite, the term, e l A  <1_  ^  n_1  ' l in T  the summation of Eq.(3.1), goes rapidly to zero, n is currently decided by the Time Constant in the Gated Integrator. White noise participating in input signals has been reduced greatly after signal is amplified and exponentially averaged in the Gated Integrator. Fig. 3.5 shows the channel A and the channel B's output in response to a function of time for mode of exponential averaging. The system has a limitation in the maximum number (500) of repetitions. Suppose that the required resolution is 1/AS, and that an aperture duration of 1/is is used. We want to utilize exponential averaging, so we should be at the steady state value after 500 repetitions. However, we can roughly set a useful repetition number,  N, equal to 100. This means that the output will reach 63% of steady value after 100 repetitions, and 99.3% of steady state value after 500 repetitions. With an Aperture  35  T  IT  3T  4T  St  Figure 3.5: Exponential averaging as a function of time in the channel A and the channel B. Coutesy of instructional manual of the E G & G PRINCETON APPLIED RESEARCH. Duration of lfis and 100 repetitions, we, therefore, need a Time Constant setting of IOOJUS.  The signal-to-noise-improvement ratio (SNIR) at the steady state will be given  to be  SNIR =  V AD  = (2/V)1/2 = (2 x 100)1/2 = 14.1  (3.2)  where T O is the Time Constant and AD the Aperture Duration. From Eq.(3.2), it is obvious that SNIR can be upgraded by increasing T O or decreasing AD or doing both.  36  3.2  Samples a n d T h e i r F a b r i c a t i o n  Samples used in the DLTS scans are Metal Semiconductor Field Effect Transistors (MESFETs). It is inevitable that some kinds of defects be produced in the fabrication processes. In order to investigate the deep levels produced by fabrication process, two types of samples with slight differences were fabricated. One sample's n-type active layer is formed by implanting 29Si +  ions into LEC-grown GaAs sub-  strate through a S13N4 cap which is built by depositing a layer of S13/V4 on the wafer surface. The n-type active layer of another sample is, however, formed by implanted 2 9  £ t + ions into LEC-grown GaAs without a S13N4 cap. But, a Si N 3  4  cap is deposited  on the latter before annealing, because dissociation of GaAs starts at a temperature of 650 °C. Therefore, a layer of protection on the wafer surface is necessary when the GaAs wafer undergoes annealing at temperature 850 °C.  The region of GaAs  wafer after being implanted with ions is damaged. This region of the wafer becomes amorphous material or amorphous and crystalline mixed material. An annealing to eliminate the damaged region of the wafer is needed. Therefore, GaAs wafer after annealing returns to the crystalline material of III-V compound semiconductor.  3.2.1  Mask  In order to reduce the effect of surface state defects which scatter at the edge of the gate electrode, we are supposed to design our samples with small gap between gate electrode and drain pad or gate electrode and source pad. Bell-Northern Research test masks are used to fabricate samples. This set of masks can produce a number of MESFETs with different shapes in which one is chosen for our DLTS scans. The  37  distance between the edge of the gate electrode and edge of the source pad or the drain pad of this M E S F E T is only 2fim. As an approximation by neglecting fringe effect on edge of the gate electrode, the area of the gate electrode is determined by the length of sides of the gate electrode. The area of our samples' gate electrode is 225//m x 405/zm = 9.11 x 10 fj,m 4  2  =  9.11 x 10 _ 4 cra 2 .  However, a small gap between the gate electrode and the drain pad or the source pad makes it more difficult to align masks during fabrication precesses. The breakdown voltage is also considerably reduced. The author found that some of our samples with a fat gate electrode started breakdown when a bias of —7 volts was applied between the gate and the drain-source connection. The asymmetry of capacitance measured between the gate and the source and between the gate and the drain is also of concern. This is due to the asymmetry of drain pad with source pad on two sides of the gate electrodes. Besides, leakage current is somewhat large in comparison with the M E S F E T which has small area of the gate electrode. This is attributed to leakage current induced by high electric field in the gap between the gate electrode and the drain pad or the source pad.  3.2.2  Fabrication Procedures  One piece of LEC-grown GaAs wafer was labelled 686/70. This piece of wafer was cut into 4 quarter pieces. Sample fabricated on one quarter wafer was labelled 686/70CP. The n-type active layer of sample 686/70CP was formed by implanting 29  S t + ions through a  S13N4  cap with a thickness of 400A. A sample fabricated  on another quarter wafer was labelled 686/70NC. The n-type active layer of sample 686/70NC was formed by implanting 29Si + 38  ions without through a Si3N4  cap.  Figure 3.6: Tilt and rotation angle of the GaAs wafers. During the GaAs wafer ion-implant process, axial and planar channeling cannot be eliminated while the implanted ions undergo hundreds of collisions before they totally come to rest. But, channeling will be minimized by rotating and tilting the GaAs wafer. When an ion is deflected into a channel, it has more chance to keep moving. Therefore, less fraction of ions came to rest even at much deeper depth than they are found in the implantation towards amorphous material. Fig. 3.6 shows a planar diagram of the rotation angle and tilt angle of the wafer. In making n-type active layer, the LEC-grown GaAs wafers are implanted with  Si +  29  ions at a dose of 3 x 1012 ions/cm2 and energy 125/ceV. Rotation and tile angle are achieved by rotating wafers about their axes parallel and perpendicular to the wafers' face as depicted in Fig. 3.6. At 0tiu = 0°, the wafers' face is perpendicular to the beam axis. Thus, ion has maximum channeling down the < 100 > axis of the lattice. At  BTot = 0 ° , the wafers' flat is aligned with (Oil) plane, so ions moving along the wafers'  39  flat have maximum channeling, too. According to Rosenblatt's viewpoint, axial and planar channeling gives doping profile broadening [19].  The broader doping profile is due to longer projection of  implanted ions in crystal. The shortest projection of implanted ions appears when wafers are tilted 13° to the axis parallel to the ion-implanting beam line, and rotation 45° to the axis perpendicular to wafer's fiat. In our studies, we found that planar channeling is minimized when the axis perpendicular to the wafers' flat is set to 22°. However, we are in agreement with the point that axial channeling is minimized when wafers are tilted 13° to the axis parallel to ion-implanting beam line. All procedures in fabricating sample 686/70CP and sample 686/70NC except ion implantation are exactly identical. A graphic depiction of patterning sample 686/70CP is given in Fig. 3.7, and of patterning sample 686/70NC is given in Fig. 3.8. Details of every procedure in fabricating processes of sample 686/70CP and sample 686/70NC are listed in appendix which follows the Chapter 5.  40  S.l. GaAs  (A) Wafer pre—cleaning. registration  mark Si 3 M4 cap  S.l. GaAs S i 3 N 4 cap (9)  S i 3 N 4 capping & registration mark etch. 2 9  Si+  II  2 9  Si+  ^photoresist' SijM» cop  In"  !n4 S.l. GaAs S i ^  cap  (C) Pattern ing n * mask for Ion implantation. Figure 3.7: Fabrication sequence for patterning sample 686/70CP. 41  S.I. GaAs Si 3 N4 cap (D) Patterning n~ mask for ion implantation,.  AuGe  AuGe  AuGe  S.I. GaAs (E) Removing Si 3 Mt c a p and patterning ohrnic contacts. A!  .A! .Ai n  %/$&'////  S.I. GaAs (F) Patterning-Schottky  Fig. 3.7: Continued.  42  contact.  S.I.  GGAS  (A) Wafer .pre~c!ecning.. . registration mark LT  S.I. GaAs (3) Registration mark etch.  S.L GaAs (C) Patterning n  +  mask for ion implantation.  Figure 3.8: Fabrication sequence for patterning sample 686/70NC. 43  1 i i_  -ii -  i  r  S.I. GaAs (D) Patterning n~ mask for ion implantation. AuGe  AuGe  AuGe  n S.I. GcAs (E) Removing S i N cap and patterning ohmic contacts. 3  4  S.I. GaAs (F) Patterning Schottky contact. Fig. 3.8: Continued. 44  Chapter 4  DATA ANALYSIS A N D EXPERIMENTAL  4.1  4.1.1  RESULTS  D a t a A n a l y s i s U s i n g C o n v e n t i o n a l D L T S Technique  T h e D e t e r m i n a t i o n of M a x i m u m R a t e W i n d o w F o r C o n v e n t i o n a l D L T S Scans  The conventional DLTS Technique using Gated Integrator and Boxcar Averager for investigating deep levels in GaAs semiconductor material was first introduced by D.V. Lang in 1974 [7]. Later, researchers who are interested infindingdeep levels in semiconductor substrates have widely used this technique. This technique has become a powerful tool in evaluating the quality of semiconductor material, and providing most important information relevant to semiconductor material to manufacturers as well as electronic device designers. In this conventional DLTS technique, two channels which have different aperture delay times ti and £ 2 , respectively, and a Boxcar Averager are employed to sample transient capacitance at two different points of time. Meanwhile, the specimen's temperature is scanned, usually heating from low to high temperature. The amplitude of  C(ti)  — C(t 2 ), which corresponds to  XC(ii)  — XC(«2)  at the output of Boxcar Averager as described in Chapter 3, varies with temperature. As a result, we can obtain a DLTS spectrum which plots variation of the amplitude 45  of C(ti) — C(t ) versus temperature. The DLTS spectrum consists of positive peaks 2  {C(ti) — C(t ) > 0) and negative peaks (C(ti) — C(t ) < 0). Each peak in the spec2  2  trum represents the "signature" of a deep level. The temperature which matches the peak amplitude of C{t\) — C{t ) is defined as the peak temperature. A typical DLTS 2  spectrum is shown in Fig. 4.1. When a peak amplitude of C(ti) — C{t ) appears in the DLTS spectrum at 2  one temperature, the rate window inversely equates to the emission rate of the deep traps. This rate window is called maximum rate window, and is denoted as r  max  in  this thesis. By combining Eq.(2.28) and Eq.(2.29), we have  en = ^nonT  exp(  ——) (for electron deep level)  (4.1)  and  1  _, / = ep = 7 <7 r exp(  'max  — E  2  p  p  v  ") (for hole deep level)  2  (4.2)  KJ-  Therefore, rate window has a physical meaning as selecting emission rate. In DLTS study, the maximum rate window is expressed as  where ti and t are the aperture delay time of the channel A and the channel B of the 2  Boxcar system, respectively.  46  DLTS  SPECTRUM  (Raw  data)  However, one must be aware that l/rmax  = e„  iP  in Eq.(4.1) and Eq.(4.2) ap-  pears only when the amplitude of C(ti) — C(t2) reaches its peak amplitude in DLTS spectrum,  l/rmax  is generally not equal to e n p .  In the DLTS signal, the peak position of the amplitude of C{t{) — C(t2) in temperature correlates to the maximum rate window. Therefore, the maximum rate window  Tmax  is the variable of the peak position in temperature. Change of aperture  delay times ti and t2 leads to a shift of peak position in temperature. Since smaller  rmax means larger en and e , according to Eq.(4.1) and Eq.(4.2), a smaller maximum p  rate window brings about a shift in the peak position in DLTS spectrum to a higher temperature. Fig. 4.2 is depicted as such variation of the peak position in temperature with the change of maximum rate window. Through a series of DLTS scans for which different maximum rate windows are selected, we are able to obtain a number of peak temperatures in the DLTS spectra. Plotting en<p/T 2  versus lOOO/T, where e „ p is inversely equal to the maximum rate  window and T is the peak temperature in the DLTS spectrum, for each maximum rate window, we obtain a straight line. The thermal activation energy and the thermal capture cross section of a deep level can be obtained from the slope of the straight line and the intersection of the straight line with y-axis  (e n p /r 2 ), respectively.  A graph  plotting a number of such straight lines is entitled an Arrhenius plot, and is given in Fig. 4.3. Each datum point in the Arrhenius plot represents a peak temperature in the DLTS spectrum. In Fig. 4.3, electron deep levels are labelled EL2, El, E2, E3,  E4 and E, while hole deep levels are labelled Hi and H2. One condition for each Gated Integrator is that its aperture duration must  48  DLTS  Plotted  SPECTRUM  (Raw  data)  on 2 D«o 1988  -I -l 1 1  1  1 r-  3 rC 3  >. c H  1 r~  &. +• ^» .& 1.  V  Peak Peak  _1_  Z5C  230  330  370  J  418  i  l u. •*5E  Temparsturs CK)  Figure 4.2: Variation of peak position in temperature with change of maximum rate window.  49  ARRHENIUS PLOT O.Ol ^  Qoooo pi ? * * * * * E2 t i i ± * E3  o  t±±±+ E4  w  0.001  C4  c  0)0.0001  0.00001  4  |n 2.50  1111  mill mi mill n 2.70 2.90  11111111  3.10  rn i u , i M 3.30  1000/T  M , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,  3.50  3.70  3.90  (1/°K)  ARRHENIUS PLOT 0.01 -a * * * * * H1 t t * t t H2  ooooo E5  e m  0.001  CM C  0.0001 -i  0.00001  _  . •  2.50  1  11"  2.70  i' "  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n 1 1 1 1 1 1 1 1 1 I I 1 1 1 1 1 in  2.90  3.10  1000/T  3.30  3.50  11111n  3.70  i H  M  N  3.90  (1/°K)  Figure 4.3: (Top) Arrhenius Plot for deep levels found from LEC-grown GaAs substrates, (bottom) continued. 50  be very much smaller than  1/Tmax.  If the aperture duration has the same order of  magnitude as maximum rate window, the expression of  1/ T m a x  needs being modified for  increasing correction. According to D.S. Day et al., the maximum rate window should take the following form if the aperture duration has the same order of magnitude as maximum rate window [20]  M)  W = (<i-«»)[MJ|^^)] where W is the aperture duration of the Gated Integrator.  However, the aperture duration used in the conventional DLTS technique is very much smaller than  Tmax.  Typical numbers of W and  Tmax  are 5 microseconds and  5-50 milliseconds, respectively. Consequently, the unmodified formula (Eq.(4.3)) is good enough to maintain high precision in DLTS analysis.  4.1.2  Non-Exponential Transient Capacitance  DLTS used in investigating defects involves a capacitance transient thermal scanning technique. The underlying theory of DLTS technique, that a capacitance transient for a Schottky diode starts exponentially increasing just when the bias applied on its gate pulses from filling bias voltage level to reverse bias voltage level, is based on the assumption that only one deep level is involved in the capacitance transient. Since a single deep level tends not to be isolated from other deep levels in the DLTS technique, capacitance transient neither increases exponentially nor follows any simple mathematical model. In reality, more than two deep levels are often simultaneously involved in contribution to the capacitance transient. 51  mm  fl  F i g u r e 4.4: Transient capacitance of one experimental sample at T = 300 ° A ' . A photo below displays an observed capacitance transient. However, one can find t h a t transient capacitance in this photo increases almost exponentially w i t h time. T h i s is a t t r i b u t e d t o the situation that one deep level w h i c h has relatively high deep trap concentration dominates the thermal emission process of the free carriers. Therefore, this deep level makes the major c o n t r i b u t i o n to the signal of the transient capacitance. A n o t h e r effect w i t h respect to non-exponential transient capacitance is that the electron emission rate of deep traps depends u p o n the electrical field established by the voltage w h i c h is applied between the gate electrode and the source or the d r a i n pad [28].  52  4.1.3  M a t h e m a t i c a l T r e a t m e n t of D a t a O b t a i n e d F r o m D L T S Scans  In principle, white noise from the input signal has been exponentially averaged out by the Gated Integrators of the Boxcar system. The Boxcar Averager should theoretically provide a relatively noise-free DLTS signal. However, noise still comes out in the output of the Boxcar Averager. This noise may be possibly produced by electronic components in the equipment of the DLTS system, particularly the noise from the Boonton Capacitance Meter. The noise makes a powerful influence on the output signal in the Boxcar Averager so that the noise appears in the DLTS spectrum. Mechanical vibration of probes which touch the gate electrode and, the source pad and the drain pad is also a source of noise. This noise signal through internal electronic components of the capacitance meter and Boxcar system superimposes on the output signal of the Boxcar Averager. Therefore, it is essential that a method which reduces noise signal be employed. In this thesis, a Numerical Smoothing Average Routine was used to improve signal-to-noise ratio [11]. A more precise determination of each datum is accomplished in this method. As we know, data in the DLTS spectrum are plotted by the amplitude of  C(ti)  — C(t ) versus temperature. Smoothing average routine takes each datum in 2  DLTS signal to be averaged over by its several adjacent data. Thus, noise signal level superimposed on the DLTS signal is significantly reduced. This is algorithmically expressed as  AC'(li) = \t\C{Ti 4  - 1) + ^ACiTi) I  + -AC^ 4  + 1)  where AC = C{ti) — C(t2) is the DLTS signal and TJ is temperature. 53  (4.5)  Eq.(4.5) takes the form  Ac'cn) -  ^Acrro + -AC{T )  .  2  4  (4.6)  4  to average the first datum in the DLTS signal, and the form  AC'{T ) N  = ^ A C ( T „ ) + ^ A C ( T n - 1)  (4.7)  to average the last datum in the DLTS signal. The algorithm in Eq.(4.5) only takes three points for smoothing average routine. If one wants to increase accuracy, one can expand to five data point smoothing average routine, called 5 iterations, which has the equivalent form as Eq.(4.5), except that two more successive data are taken for routine. The mathematical form for 5 iterations is  AC(Ti)  =  ^AC(T, - 2) + \AC{Ti o o  - 1) +  \&C{Ti)  6  +  ^(7(7/, + 1) + ^ A C ( T i + 2) o o (4.8)  But,  two-end data points are averaged over only three data as if next datum  had the same values, i.e.  AC'(Ti) =  -ACfTi) + -AC(7\ + 1) + -ACfc 2 4 4  and  54  + 2)  (4.9)  AC"(T n ) =  ±AC{T ) n  + ±AC(T  n  - 1) +  ^AC(T  n  - 2)  (4.10)  Although the smoothing average routine decreases the fluctuation of the DLTS signal, it still conserves the peak position of the DLTS signal in its original peak temperature. Fig. 4.5 shows the results of the smoothing average routine. Curve (a) displays the raw data of one of the DLTS scan, curve (b) and (c) are the 3 iterations and 10 iterations, respectively. The effect of the smoothing average routine on raw data is obvious. As seen, the great advantage in using smoothing average routine is that fluctuation in the magnitude of raw data (curve (a)) is suppressed in a considerable extent, particularly when number of iterations goes large (curve (c)). In order that three curves are distinctly separated from each other in one plot, the magnitude of the data in curve (b) is slightly reduced while the magnitude of the data in curve (c) is slightly amplified.  4.2  4.2.1  Results of D L T S Scans  Description of the Shift of Peak Position In Doping Concentration  As mentioned in Chapter 3, the n-type active layer of sample 686/70NC was formed by implanting without a S13N4 cap, and the active layer of sample 686/70CP was formed by implanting through a  S13N4  cap. Doping concentration of both samples  is given in Fig. 4.6. It is obvious that the peak position of the doping concentration of the sample 686/70NC (0.104/xm) is deeper than that of the sample 686/70CP (0.079^m).  55  DLTS  SPECTRUM  292  330  3?0  410  Tanparttura CK)  Figure 4.5: Effect of smoothing average routine on DLTS signal.  56  The shift of peak position in doping concentration is due to loss of the ions' energy when they are implanted into the GaAs wafer through a Si3N4  cap. Their  projected range is comparatively smaller. Therefore, only those recoiled lattice atoms which locate closer to the wafer surface where the gate electrode is built scatter spatially from their equivalent vacant lattice sites. Sample 686/70CP, therefore, shows a shift of the peak position of doping concentration towards the metal-semiconductor interface. Since lattice atoms are physically displaced from their original sites when they collide with foreign atoms ( 2 9 5 t + ) , displaced lattice atoms concomitantly generate vacancies in the crystal. The displaced lattice atoms and vacancies are spatially well separated in the lattice, they are thought to form different complex defects depending upon the local conditions of non-stoichiometry. These complex defects are believed to cause damage-related deep levels in bulk material, and are similarly found in electronirradiated GaAs substrate. Some of these complex defects can be removed by annealed [9].  4.2.2  D e s c r i p t i o n of the Identification of D e e p Levels  The most important information, such as thermal activation energy, thermal capture cross section, is provided by the Arrhenius plot given in Fig. 4.3. Details of the thermal activation energy, the thermal capture cross section, approximate ratio of peak deep trap concentration to doping concentration, and peak temperature of each deep level found in DLTS scans are listed in Table. 4.1. In Table 4.1, electron deep level El is also labelled as EB3 by Martin [14] or F3  57  ; PEAK DEPTH  0  -1  0797MICRONS  -2  .3  .4  .S  DEPTH (MICRONS)  DEPTH  (MICRONS)  Figure 4.6: Doping concentration of sample 686/70CP (top) and of sample 686/70NC (bottom). 58  Label of deep level EL2 El E2 EA HI  H2 El  £3 E5  Alternative label in reference  Energy from band edge (eV)  Thermal capture cross section (cm 2)  NT Nd  Deep levels found from uncapped sam])les — EL2 0.82 3.38 x 10- 13 11 0.92 3.69 x 10EB3 by Martin or 0.0506 F3 by Allsopp EF1 by Martin or 0.69 5.54 x 10-14 0.0316 F2 by Allsopp — 1.19 7.43 x 10-7 0.062* HA1 by Auret or 0.70 2.75 x 10~14 0.0256 HB2 by Bourgoin or HL2 by Mitonneau — 1.00 9.51 x 10~9 — Deep levels found from capped samp es EB3 by Martin or 0.92 3.69 x 10-11 0.050" F3 by Allsopp F4 by Allsopp 0.72 4.69 x 10- 12 0.0096 EL16 by Martin 0.42 3.69 x 10" 18 0.0506  DLTS peak temperature ( °K)  384.60a 364.00° 354.14a 353.17° 338.87°  315.21" 364.00° 306.23" 363.64°  ° Peak temperature corresponds to DLTS maximum rate window rmax = 4.97 x 10 seconds. b Nd is the peak doping concentration around 2 — 3 x 10 17 cm~ 3 . Table 4.1: Properties of deep levels found from LEC-grown GaAs.  59  3  by Allsopp [22]. Since this electron deep level is observed from both sample 68C/70CP and sample 686/70NC, the author concluded that the formation of this deep level was not related to the SizN4 atoms which were knocked into the GaAs substrate during the ion implantation. Therefore, deep levels in our GaAs substrate are not produced by ion-implant process. Instead of having a sharp line, each peak in DLTS signal has an envelope. The envelope in the DLTS signal of sample 686/70CP is very much broader than that of sample 686/70NC. Broadening envelope in DLTS signal is due to the broader spatial distribution of deep traps in the bulk material. The author suggested that the broader envelope in the DLTS signal occuring in the sample 686/70CP be induced by the implanted ions' initial scattering angle when ions reach wafer surface, and the shorter projected range in the substrate. As described by Allsopp, the structural damage of crystal is the cause to form this deep level. When host atoms (Ga and As) are collided by foreign atoms {Si), host atoms displace from their original positions to form a vacancy, and recoil back to form an interstitial. Therefore, a complex containing an interstitial and a vacancy is created. This complex interacts electrically and thermally with free carriers, mainly acts as a deep trap.  The complex is always stable, once it is formed, unless the  concentration of local vacancy is extremely high. A very high concentration of local vacancies removes the local stoichiometric balance. However, the concentration of the complex can be controlled by annealing, because the vacancy during annealing diffuses into a deeper position in the bulk material so that annealing makes the region in the substrate closer to the metal-semiconductor interface free of the deep traps.  60  Since Allsopp found the deep level El in 78Se +  implanted GaAs substrate, he  concluded that the formation of this deep level was very unlikely to relate to impurities, such as implanted foreign atoms [22].  But, there was still a small possibility for  combined residual impurities with interstitial As or Ga participating in the formation of this deep level. In Table 4.1, electron deep level E2 (also labelled E F l by Martin [14] or F2 by Allsopp [22]) and E3 (also labelled F4 by Allsopp [22]) arise from the distribution of recoiled As or Ga atoms in the GaAs substrate. The formation of the deep levels E2 and E3 is similar to that of deep level El. From the distribution of the deep traps, the formation of those deep levels seems to relate to ion-implanted non-stoichiometry of the crystal. This non-stoichiometry results from displacement of the host lattice atoms and concomitant vacancies which take place when host lattice atoms are hit by foreign ions. Therefore, electron deep levels E2 and E& are also the lattice structural damagerelated deep levels, and are commonly observed in ion-implanted GaAs substrates. Electron deep level Eb (also labelled EL16 by Martin [14]) given in Table 4.1 has a comparatively small thermal activation energy and thermal capture cross section. According to its small thermal activation energy, E5 is a shallow donor-like deep level. However, the source of this deep level is unknown. As described in other studies, this deep level is responsible for generating low frequency noise in electronic devices, and decreasing the devices' gain with frequency [14]. As shown in Table 4.1, the hole deep level HI (also labelled HB2 by Bourgoin [2] or HL2 by Mitonneau [15] or HA1 by Auret [23] or B by Lang [24]) has been reported in publications. According to Lang, [24] this deep level might be "due to a  61  native defect or to unavoidable chemical impurities." The electron deep level EA and hole deep level H2 in Table 4.1 appear to be reported for the first time. Both deep levels have large thermal activation energy (Ec - 1.19eV for FA and Ev + l.OeV for  4.2.3  #2).  Identification of D e e p L e v e l EL2  It is commonly recognized that the electron deep level EL2 is present in every growing bulk GaAs material. Since it is a native or intrinsic defect, [2] it cannot be eliminated by annealing [9] or chemical methods. EL2 was found along with the discovery of the unusual behavior of the material, namely persistent quenching of the photoconductivity at low temperature, [25,26] because this unusual behavior is caused by the existence of EL2 in the bulk material. EL2 is responsible for the fact that LECgrown GaAs is semi-insulating. It has been extensively studied, and its electrical as well as its thermodynamic al characteristics have been carefully investigated. Although some of its properties and identifications have been clarified, a lot of new discoveries relevant to its intrinsic characteristics and thermodynamics are still being reported. Presently, the microscopic structure of EL2 is drawn as a complex which includes an arsenic antisite (AsGa)  plus an arsenic interstitial (Ast) [27-29]. The arsenic interstitial  can dissociate and migrate [30]. The thermal behavior of EL2 is determined by this arsenic interstitial.  EL2 complex has a stable state and a metastable state. These states are associated with the position of the arsenic interstitial in £X2's configuration, depending  62  o£  €  A  S  0 o  +  Figure 4.7: EL2 configuration. Ref. 2. upon the distance of this arsenic interstitial with arsenic antisite. The arsenic interstitial locates at a [111] tetrahedral site. (See Fig. 4.7 below.) According to Bourgoin, [2] the stable state of the EL2 configuration is composed of an arsenic antisite (As ) Ga  with an arsenic interstitial (Asi) which is a singly posi-  tively charged state (Asj + *). The metastable state of EL2 configuration has the same composition as EL2 stable state, but, the arsenic interstitial is a neutrally charged state (i4sj°')) and its location is closer to the site of arsenic antisite. The mechanism involved in the transformation of the stable state to a metastable state is due to, as suggested, an internal transition of an electron from  As^J — As\ ^ +  to As l~ G  As\°^ by an  excitation, [31] such as optical excitation. This process is demonstrated by the characteristic photoquenching effect of the complex EL2 through an optical transition from the stable state, EL2° Therefore, Asoa  {AsG~a ] - As\ +))  to the metastable state, EL2* {AsQ -  As\° ]).  of EL2 complex loses an electron during transition. The metastable  state can be recovered back to the stable state. This reverse transition occurs when sample is under optical irradiation in the 70 — 140 °K range [32-34]. But, the details  63  of the process of the thermal transition in optical absorption is not easily generalized. Suezawa and Sumino favor the model that EL2 complex is composed of one As  Ga  and two V , which is in agreement with the model proposed by Vechten [35,36]. Ga  The correlation between the EL2 complexes and the crystal stoichiometry is essential for material manufacturers. Since it allows concentration of the EL2 complexes to be controlled by controlling the growth condition, and Ga vacancies are essential constituents for EL2 complexes, increasing As pressure during material growing or annealing might be an effective method to increase numbers of EL2 complexes [4,37,38]. The concentration of EL2 complexes is usually dependent upon the As/Ga increases with increasing As/Ga  ratio, and  ratio. This strongly suggests that the concentra-  tion of EL2 complexes is related to the intrinsic nature of LEC-grown GaAs, and determined by the numbers of Ga vacancies, As interstitials and As antisites. The electrical property of LEC-grown GaAs, being a semi-insulating material, is based upon the model which assumes free carrier in stoichiometric semi-insulating material to interact between the EL2 deep traps and the residual shallow donor and acceptor impurities. EL2 concentration  [NELI)  is compensated by the concentration of  the shallow acceptor impurities. In terms of compensation, the Fermi level is pinned by the mid-gap deep level EL2 around the vicinity of the Fermi level. However, this point is true in reality only if the concentration of shallow acceptor impurities {NA) is quantitatively closer to the EL2 concentration  64  NELZ-  4.2.4  C o n c e n t r a t i o n of the EL2 D e e p T r a p s  T h e " M o d i f i e d D L T S Technique" is used t o profile the spatial d i s t r i b u t i o n of EL2 deep traps [8,9,18]. T h e theory of this technique has been already described i n C h a p t e r 2. T h e spatial d i s t r i b u t i o n of EL2 deep traps as a function of depth i n bulk m a t e r i a l is p l o t t e d i n F i g . 4.8. In a p p l y i n g this technique, one must pay more attention to t h e specimen's temperature as well as to the selection of the aperture delay times  t\ a n d t2.  These parameters c a n be obtained f r o m the m a x i m u m rate w i n d o w used  for the D L T S scan a n d the peak position i n temperature i n the D L T S spectrum. If one peak i n the D L T S s p e c t r u m appears at one particular temperature w i t h a p a r t i c u l a r m a x i m u m rate w i n d o w , this particular temperature is used for the specimen's temperature, while the particular m a x i m u m rate window is used as the reference to determine the aperture delay time ti of the channel A and the aperture delay time  t2 o f the channel B . I n F i g . 4.8, a straight dashed line indicates the position of the peak doping c o n c e n t r a t i o n i n b u l k m a t e r i a l . T h e peak concentration of the EL2 deep traps i n L E C G a A s substrate is given i n publications around 1 x 1 0 1 6 — 1 x 1 0 1 6 c m ~ 3 [2,22,23]. In F i g . 4.8, the peak concentration of  NEL2  is 3 X 1 0 1 5 c r o - 3 w h i c h is i n good agreement  w i t h the published results.  4.2.5  Investigation O n the A n n i h i l a t i o n of EL2 D e e p T r a p s  I n this thesis, EL2 was detected from only one M E S F E T . However, EL2 is believed t o be present everywhere i n the L E C - g r o w n G a A s .  65  Temperature=367.5°K 2 c  Peak position of the doping concentration  OQ" >-t  <T>  OO  a  O  o  CJ o  10  (T>  3 1-1 9>  <3>  5'  18 _ 4-  g  o Si*  S a* CD  CD  r-  2:  10,4^=  O  z: o o  10  1 S  'TT"r  0.00  r  • ' , l  1  » • I ' • ' » • i i »i 1 « • ! i »'i • II 11 III i l l i i i i i i i i II i r i II i i v i TITI  0.20  0.40  0.60  0.80  DISTANCE (Micrometer) Flg.4.8: Concentration of the EL2 deep traps.  1.00  1.20  ELECTRIC FIELD FdO" VcrrT ) 5  1  Figure 4.9: Electric field versus the emission rate of the EL2 deep traps. Ref. 41. There are three major explanations regarding the apparent annihilation of the  EL2 deep traps.  1.  At low electric field strength ( below 3 x 106 V/cm), i.e. a small voltage applied on the Schottky diode, the electron emission rate of EL2 deep traps is not enhanced, and remains unchanged [39]. But, this point contradicted the results which were reported by Makram-Ebeid [40,41]. In Makram-Ebeid's publications, the emission rate of deep traps increases with increasing electric field even if the electric field is very small (3 x 10"5 V/cm). The influence of electric field on electron emission rate is suggested by the phonon-assisted tunneling effect [41,42]. A graphic illustration is given in Fig. 4.9.  2.  Ma et al. pointed out that the EL2 signal in the DLTS spectrum decreases 67  with decreasing barrier height [43]. This mechanism is attributed to variation of the occupancy of EL2, which is determined by the reverse bias saturation current density. The author measured I — V characteristic on two samples. One sample, called sample A , was observed the deep level EL2.  The other sample, called  sample B, was not detected the deep level EL2. For a reverse bias voltage V = —2V, the leakage current of sample A was |/|eofc| = 21/xA, while the leakage r  current of sample B was \Iu k\ — a  0.48/J.A.  Using the relation of barrier height versus reverse current density given in Fig. 4.10, we have: barrier height for the sample A is 0.66eV at T" = 400 °K, barrier height for the sample B is 0.84eV at T = 400 °K. It is apparent that the barrier height of sample A is smaller than that of sample B. However, deep level EL2 signature does not show up in DLTS scans of sample B. 3.  EL2 deep trap concentration sharply decreases with large shallow donor concentration [2,44]. This point suggests that EL2 deep traps are annihilated by shallow donors, the group IV impurities (here the  2 9  S i + ions).  During annihilation, the ionized state of EL2 deep trap complex is suppressed by excessive free carriers. Here, it is presumed that one shallow donor contributes only one free carrier so that both doping concentration and free carrier concentration are equal. Nevertheless, this suppression only happens at a temperature much lower than the crystal's melting point, because at the melting point GaAs displays the behavior of a intrinsic semiconductor, and its intrinsic 68  0.5  06  07  08  0.9  10  BARRIER HEIGHT (eV)  Figure 4.10: Barrier height of Schottky diode versus leakage current density. Ref. 43.  69  carrier concentration to be Nt = 5 x 1018cm 3 , which greatly exceeds the shallow donor concentration (1 x 1017cm~3). According to Lagowski, [44] the crucial figure of the shallow donor concentration to annihilate EL2 deep traps is 2 x 10 17 cm~ 3 . The author profiled the doping concentration for various samples used for DLTS scans. The results of the doping profiles were shown in Fig. 4.11. In Fig. 4.11, only one sample whose doping concentration is less than 2 x 10 1 7 cm - 3 is observed the deep level EL2.  It is assumed that the annihilation of EL2 deep traps takes place when an arsenic interstitial (referring to the EL2 configuration in Fig. 4.7) captures an electron. Thus, the stable state (As^J — As\ +^)  of EL2 configuration transforms to the  metastable state (.As^"] — .<4.s^). This process only occurs when shallow donor concentration is fairly high, at least above 2 x 10 1 7 cm - 3 . It is proposed by the author that the possibility for arsenic interstitial capturing an electron sharply increases, and the space charge effect, which is more significant when excessive free carriers appear in the bulk material, makes arsenic interstitial easily migrate to the position closer to arsenic antisite.  4.2.6  "Variation of C a p a c i t a n c e W i t h  Temperature  As mentioned in Chapter 1, it was found in the present studies that the capacitance always increases with increasing temperature, regardless of the level of the reverse bias applied to the Schottky diode. Fig. 4.12 gives two curves which represent the relation of capacitance versus voltage level of the reverse bias (C — V plot) at T = 290 °K and T = 400 °K.  If we select C{t = oo,T = 400 °K) and 70  DOPING  PROFILE  Plotted on 8 Dec 1986 I  • •  1-  1  -j  1  ,  r  1  1  1  .  1  1  1  1  1  1  .  m < E  V. \  2.  O  *-* t-  2 v  «'CENT  *  1  0  i 7  "" EL2  \  • • . .  •  >- . . . r-—  " • •  -  d o  .  i.E+1?  .0?  1  .  1  ,  -1  1  u.  .E8  .09 DEPTH (MICRONS)  Figure 4.11: Doping concentration of various samples.  71  .1  C(t  = oo,T = 290 °K) at 0V bias voltage level from both C — V plots, we can  directly obtain  C(t  = oo,T = 400°K)  - C(t = oo,T = 290° K)  C(t = oo,r = 290-JT)  = 5-  3 %  ( 4  -  U )  On the other hand, capacitance can be calculated by employing Eq.(2.30). The expression of depletion width is given by [16]  / 2f  kT  The built-in potential in Eq.(4.12), Vj,,, is calculated by the expression of the barrier height, qVgH which can be directly obtained from Fig. 4.13, [10] as  qV H B  where Ee - EF = kTln{Ne/ND),  = qVbi + {Ec - EF)  (4.13)  ND = 1.5 x 10 cm- for reverse bias Vr = 0V. 17  3  Using Eq.(4.13) and computing qVH at T = 400 °K and T = 290 °K, then putting qVbi into Eq.(4.12), we have W{t  = oo,T = 400 °K) = 0.0600/Ltm  and  W{t = oo,T = 290 °K) = 0.0748//m Inserting above results into Eq.(2.30), we get 72  C-V  PLOT  Btu  Figure 4.12: C-V  Voltaga  (V)  plots of Schottky diode at T = 290 °K and T = 400 °K.  73  Figure 4.13: Barrier height of Schottky diode versus temperature. Ref. 10.  74  C(t = oo,T = 400 °K) -C(t  —  = oo,T = 290 °K)  C(* = oo,T = 290  Q.  =6  A  %  ( 4 , 1 4 )  Therefore, this shows that the experimental result (5.3%) is in good agreement with the calculated result (6.4%). Consequently, reduction of barrier height with rising temperature is the dominant contribution to increase of capacitance with rising temperature. In addition, the model that the increase of capacitance with rising temperature is due to the increase of GaAs permittivity with rising temperature is unsuccessful. From the expression of GaAs permittivity with temperature given as[45]  6,(T) =c 0 x 12.737(1 + 1.2 x 10~ 4-T)  (4.15)  We derive two values  es{T = 4 0 0 ° K ) = 13.35e  0  and  £.(T = 290 °K) = 13.18e  0  Inserting above values into Eq.(4.12) and Eq.(2.30), and setting qVbi as a constant, we have  C(t = oo,T = 400 °K) - C(t = oo,T = 290 °K)  C(* = oo,r = 290 °A-)  =  L  3  %  (  4  1  6  )  Obviously, this ratio (1.3%) is insufficient to match the experimental result 75  (5.3%).  76  Chapter 5  CONCLUSIONS A N D SUGGESTIONS F O R F U R T H E R R E S E A R C H  Several conclusions emerge from the DLTS study. The first, two new deep levels which were not previously reported were found in LEC-grown GaAs substrate. One is an electron deep level EA with very large thermal activation energy, EC -  ET = 1.19eV. The other is a hole deep level which has also large thermal activation energy, ET — EV — l.OOeV'. The second, the fact that the deep level El was detected from both samples can be used to conclude that the cause of this deep level did not correlate to the  S13N4  atoms which were knocked into the GaAs substrate during ion-  implantation. The third, the experimental results were used to support the point that extremely high shallow donor concentration led to annihilation of EL2 deep traps. The fourth, it was shown that the reduction of barrier height of the Schottky diode with rising temperature was the major effect causing increase of capacitance with rising temperature. Finally, the author suggested a number of interesting works for the DLTS research. Further investigation in finding nature of the formation of deep level EA and  H2 seems to be needed. The author considers that the formation of the hole deep level H2 is associated with shallow acceptor impurity, since most hole deep levels in the n-type layer of GaAs have been reported to relate to various impurities. In order  77  to detect deep levels in GaAs substrate produced by one kind of impurity, we can compare result of DLTS scans obtained from a sample fabricated on the GaAs substrate which had been doped this kind of impurity with that obtained from a sample which was fabricated on undoped GaAs substrate. The annihilation of EL2 deep traps by shallow donor with very high concentration can be experimentally studied by fabricating samples with low dose of implanting ions ( 29Si +).  If the implanted dose on the  wafer is one order of magnitude less than the present dose, one is expected to find the  EL2 signature from DLTS scans of all samples which are fabricated on the wafer. To increase the speed in finding deep level signature from DLTS scans, two different methods can be used. One is the "Digitally Recorded Capacitance Transient Spectroscopy" [46]. The other is the "Paired Temperature Spectroscopy" [47-49]. Both methods are basically developed from the conventional DLTS technique and are computer-assisted systems. However, they can handle an instant default to produce the Arrhenius Plot. But, both methods need a programmable pulse generator which helps computer to well-timingly sample transient capacitance at various points of time.  78  REFERENCES  1. M . Bugajski, K.H. Ko, J. Lagowski, and H.C. Gatos, J. Appl. Phys., 65, 596 (1989). 2. J.C. Bourgoin, H.J. von Bardeleben, and D. Stievenard, J. Appl. Phys., 64, R65 (1988). 3. M . Henini, B. Tuck and C.T. Paull, Solid-State Electronics, 29, 483 (1986). 4. S. Chichibu, N. Ohkubo, and S. Matsumoto, J. Appl. Phys., 64, 3987 (1988). 5. C M . Martin, J.P. Farges, G. Jacob, an J.P. Hallais, J. Appl. Phys., 51, 2840 (1980). 6. S. Chichibu, S. Matsumoto, and T. Obokata, J. Appl. Phys., 62, 4316 (198T). 7. D.V. Lang, J. Appl. Phys., 45, 3023 (1974). 8. D. Allsopp, A.R. Peaker, E.J. Thrush, an G. Wale-Evans, J. of Crystal Growth, 68, 295 (1984). 9. K.L. Wang, G.P. Li, P.M. Asbeck, and C.G. Kirkpatrick, in: Defects in Semiconductors, Eds.  J. Narayan and T.Y. Tan (North-Holland, Amsterdam,  1981), p. 487. 10. G.P. Li, K.L. Wang, Inst. Phys. Conf. Ser. No. 63, 317 (1982). Paper presented at: Int. Synp. G a A s and Related Compounds, Japan 1981. 11. G.N. Maracas, Ph.D. Thesis, Cornell University (1982). 12. M . Bleicher an E. Lange, Solid-State Electronics, 16, 375 (1973). 13. G.M. Martin, A. Mitonneau, D. Pons, A Mircea, and D.W. Woodard, J. Phys. C: Solid St. Phys., 13, 3855 (1980). 14. G.M Martin, A Mitonneau, and A. Mircea, Electronics Letters, 13, 191 (1977). 79  15. A. Mitonneau, G.M. Martin, and A. Mircea, Electronics Letters, 13, 666 (1977). 16. S.M. Sze, Physics of Semiconductor Devices, (2nd Edition, John Wiley and Sons, 1981), p. 248. 17. Y. Zohta an M.O. Watanabe, J. Appl. Phys., 53, 1809 (1982). 18. H. Lefevre and M . Schulz, Appl. Phys., 12, 45 (1977). 19. D.H. Rosenblatt, W.R. Hitchens, R.E. Anholt, and T.W. Sigmon, IEEE Electron Devices Letters, 9, 139 (1988). 20. D.S. Day, M.Y. Tsai, B.G. Streetman, and D.V. Lang, J. Appl. Phys., 50, 8 (1979). 21. B. Olejmkova, Phys. Stat. Sol., (a) 84, 621 (1984). 22. D. Allsopp, Semicond. Sci. Technol., 2, 129 (1987). 23. F.D. Auret, A.W.R. Leitch, and J.S. Vermaak, J. Appl. Phys., 59, 158 (1986). 24. D.V. Lang and R.A. Logan, J. of Electronic Materials, 4, 1053 (1975). 25. A.L. Lin, E. Omekanovski, and R.H. Bube, J. Appl. Phys., 47, 1852 (1976). 26. A.L. Lin and R.H. Bube, J. Appl. Phys., 47, 1859 (1976). 27. B.K. Meyer, D.M. Hofmann, J.R. Niklas, an J.M. Spaeth, Phys. Rev., B36, 1332 (1987). 28. G.A. Baraff an M . Schliiter, Phys. Rev. Lett., 55, 2340 (1985). 29. Y. Mochizuki and T. Ikoma, in Defects in Semiconductor, Material Science Forum, edited by H.J. von Bardeleben (Trans. Tech, Aedermannsdorf, Switzerland, 1986), 10-12, p. 323. 30. M . Levinson and T.A. Kafalas, Phys. Rev., B35, 9383 (1987).  80  31. D. Stievenard, H.J. von Bardeleben, J.C. Bourgoin, an A. Huber, in Defects in Semiconductor, Material Science Forum, edited by H.J. von Bardeleben (Trans. Tech, Aedermannsdorf, Switzerland, 1986), 10-12, p. 305. 32. S. Nojima, J. Appl. Phys., 57, 620 (1985). 33. Y. Mochizuki and T. Ikoma, Jpn. J. Appl. Phys., 24, L895 (1985). 34. J.C. Parker and R. Bray, in Defects in Semiconductor, Material Science Forum, edited by H.J. von Bardeleben (Trans. Tech, Aedermannsdorf, Switzerland, 1986), 10-12, p. 347. 35. M . Suezawa an K. Sumino, Jpn. J. Appl. Phys., 27, L18 (1988). 36. J.A. van Vechten , J. Electrochem. Soc, 122, 423 (1975). 37. J. Nishizawa, H. Otsuka, S. Yamakoshi, and K. Ishida, Jpn. J. Appl. Phys., 13, 46 (1974). 38. H. Otsuka, K. Ishida, and J. Nishizawa, Jpn. J. Appl. Phys., 8, 632 (1969). 39. G.P. Li and K.L. Wang, Appl. Phys. Lett., 42, 838 (1983). 40. S. Makram-Ebeid, Appl. Phys. Lett., 37, 464 (1980). 41. S. Makram-Ebeid, Phys. Rev., B25, 6406 (1982). 42. G. Vincent, A. Chantre, and D. Bois, J. Appl. Phys., 50, 5484 (1979). 43. Q.Y. Ma, M.T. Schmidt, X. Wu, H.J. Evans, and E.S. Yang, J. Appl. Phys., 64, 2469 (1988). 44. J. Lagowski, H.C. Gatos, J.M. Parsey, K. Wada, M. Kaminska, and W. Walakiewicz, Appl. Phys. Lett., 40, 342 (1982). 45. W. Platen, H.-J. Schmutzler, and D. Kohl, J. Appl. Phys., 64, 218 (1988).  81  46. H.K. Kim, T . E . Schlesinger, and A . G . Milnes, J. of Electronic Materials, 17, 187 (1987). 47. R.K. Singh, V . A . Singh, J.W. Corbett, and A. Das, J. Phys. C: Solid State Phys., 19, 2177 (1986). 48. R.K. Singh, V.A. Singh, J.W. Corbett, Semicond. Sci. Technol., 2, 716 (1987). 49. R.K. Singh, V.A. Singh, J.W. Corbett, an R. Magnos, Semicond. Sci. Technol., 2, 726 (1987).  82  APPENDIX FABRICATION P R O C E D U R E S OF MESFETs USED F O R DLTS SCANS  1. Scribe wafer into 4 pieces of quarter-wafers. Wafer pre-cleaning  2. Degrease quarter-wafers in boiling acetone 5 minutes. 3. Immerse two quarter-wafers in H S0 2  : H0  4  2  2  : H 0 ( 8 : 1 : 1 ) for 2 minutes and 2  45 seconds at room temperature. A thickness of about 3^xm on both surfaces of a quarter-wafer is etched. 4. A silicon nitride cap with a thickness of 400A is deposited on one quarter-wafer which is labelled as 686/70CP. The other quarter-wafer without a silicon nitride cap is then labelled 686/70NC. P a t t e r n i n g for registration m a r k s  5. Spin Shipley 1400-30 photoresist (P.R.) on 686/70CP and 686/70NC at 4700 r.p.m. for 35 seconds. 6. Soft bake at 95 °C for 25 minutes. 7. Expose under registration mask to ultraviolet light for 36 seconds. 8. Post exposure bake at 95 °C for 36 seconds. 9. Soak 686/70CP and 686/70NC in developer solution (developer is always 50% MF312 and 50% H 0) for 55 seconds to etch out P.R. from regis2  tration mark area. 10. Rinse 686/70CP and 686/70NC in D.I. Water for 1 minute and blow dry in N2 gas. 83  11. Soak 686/70CP in BHF for 40 seconds to etch Si3N4  out in the position of  registration marks. 12. Etch 686/70CP and 686/70NC registration marks with 5 : 2 : 240/NH4OH  H202  :  : H20 for 50 seconds.  13. Rinse in D.I. Water for 5 minutes and blow dry with N2 gas. 14. Remove P.R. —5 min microstrip 95 °C —5 min D.I. Water rinse —5 min boiling acetone —5 min boiling isopropy P a t t e r n i n g area i m p l a n t e d n + for ohmic contacts  15. Spin Shipley 1400-30 photoresist on 686/70CP and 686/70NC at 4700 r.p.m. for 35 seconds. 16. Soft bake at 95 °C for 25 minutes. 17. Expose under n + mask to ultraviolet light for 36 seconds. 18. Post exposure bake at 95 °C for 20 minutes. 19. Immerse in developer solution for 55 seconds to remove P.R. from ohmic contact area. 20. Rinse in D.I. Water for 1 minute, then blow dry in N2 gas. 21. Remove surface oxides from 686/70NC by etching in 10% NH4OH. on 686/70CP is still  {Si3N4  cap  in-situ.)  22. Immediately load 686/70CP and 686/70NC into implanter. Implanting energy and dose are set 150KeV  and 1 x 1013 ions/cm2, respectively. 84  23. Remove P.R. (the same routine as step 14). Patterning area implanted n~ for n-type active channel 24. Spin Shipley 1400-30 photoresist on 686/70CP and 686/70NC at 4700 r.p.m. for 35 seconds. 25. Soft bake at 95 ° C for 25 minutes. 26. Expose under n~ mask to ultraviolet light for 36 seconds. 27. Post exposure bake at 95 °C for 20 minutes. 28. Immerse in developer solution for 55 seconds to remove P.R. from Schottky contact area. 29. Rinse in D.I. Water for 1 minute, then blow dry in N2 gas. 30. Remove surface oxides from 686/70NC by etching in 10% NH4OH.  {Si3N4  cap  on 686/70CP is still in-situ). 31. Immediately load 686/70CP and 686/70NC into implanter. Implanting energy and dose are set \2hKeV  and 3 x 1012 ions/cm2, respectively.  32. Remove P.R. (the same routine as step 14). 33. Deposit Si3N4  cap onto 686/70NC.  Annealing 686/70CP and 686/70NC 34. Put in furnace at 850 °C for 25 minutes. 35. Remove Si3N4  cap from 686/70CP and 686/70NC. Soak in BIIF for 15 - 20  minutes, then rinse in D.I. Water for 10 minutes. Sometimes, plasma etching after chemical etching is required to thoroughly remove residual Si3N4 Patterning for ohmic contacts  85  cap.  36. Spin Shipley 1400-30 photoresist on 686/70CP and 686/70NC at 4700 r.p.m. for 35 seconds. 37. Soft bake at 70 °C for 25 minutes. 38. Soak in chlorobenzene for 7 minutes. 39. Expose under ohmic mask to ultraviolet light for 36 seconds. 40. Immerse in developer solution for 55 seconds to etch out P.R. from ohmic contact area. 41. Post exposure bake at 95 °C for 20 minutes. 42. Immerse in BHF for 30 seconds to remove residual thin layer of P.R. on the ohmic contact area. 43. Rinse in D.I. Water for 10 minutes. 44. Soak in 10% NH OH 4  to remove oxides on the GaAs, then blow dry in N gas. 2  45. Immediately load 686/70CP and 686/70NC into CHA to evaporate AuGe to form ohmic contacts. 46. Remove P.R. (the same routine as step 14). After liftoff of P.R., GaAs wafer undergoes a bake in furnace at 425 °C for 2 minutes to make a metal-semiconductor sinter. This causes the AuGe to diffuse into the GaAs to make ohmic contacts. P a t t e r n i n g for S c h o t t k y contact on the n-type active channel  47. Spin Shipley 1400-30 photoresist on 686/70CP and 686/70NC at 4700 r.p.m. for 35 seconds. 48. Soft bake at 70 °C for 25 minutes. 49. Soak in chlorobenzene for 7 minutes. 86  50. Expose under Schottky mask to ultraviolet light for 36 seconds. 51. Immerse in developer solution for 55 seconds to remove P.R. from Schottky contact area. 52. Post exposure bake at 95 °C for 20 minutes. 53. Immerse into BHF for 30 seconds to remove residual thin layer of P.R. on the Schottky contact area. 54. Rinse in D.I. Water for 10 minutes. 55. Soak in 10% NH4OH  to remove oxides on the GaAs, then blow dry in iV2 gas.  56. Immediately load 686/70CP and 686/70NC into CHA to evaporate Al to form Schottky contact. 57. Remove P.R. (the same routine as step 14). Samples are ready for D L T S scans  Sometimes, a thicker and harder Schottky contact is needed through increasing its thickness by patterning a second Schottky contact on gate area in order to prevent it from being easily scratched out. This can be achieved by repeating procedure steps 47-57, but using another Schottky mask instead of the mask used in step 50.  87  

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