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Design-rule independent layout generation of PLA and gate matrix layouts for CMOS technologies Gagne, David A. 1989

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D E S I G N - R U L E I N D E P E N D E N T L A Y O U T G E N E R A T I O N O F P L A A N D G A T E M A T R I X L A Y O U T S F O R C M O S T E C H N O L O G I E S David A . Gagne B . A . S c . (Electrical Engineering) University of Br i t i sh Columbia A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF T H E REQUIREMENTS FOR T H E D E G R E E OF M A S T E R OF AP P L I E D SCIENCE in T H E FACULTY OF GRADUATE STUDIES DEPARTMENT OF E L E C T R I C A L ENGINEERING We accept this thesis as conforming to the required standard T H E UNIVERSITY OF BRITISH COLUMBIA June 1989 © David A . Gagne, June 1989 In presenting this thesis i n partial fulfillment of the requirements for an advanced degree at the University of Br i t i sh Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of Electrical Engineering The University of Br i t i sh Columbia 1956 M a i n M a l l Vancouver, Canada Date: A b s t r a c t Automat ic layout generation techniques can be used to generate layouts in arbitrary tech-nologies i f sufficient information describing the technology is available, and i f sufficient constraints can be applied to device placement and routing. Two approaches can be taken to the automatic generation of layouts: the coordinate-free, or relative coordinate approach, and the origin-based, or absolute coordinate approach. Each of these methods was used to implement design-rule independent layout generators, the coordinate-free method on a P L A generator, and the origin-based method on a gate matr ix generator. It was determined that the origin-based approach was more suitable to mask-level layout generation than was the coordinate-free system. i i T a b l e o f C o n t e n t s A b s t r a c t i i L i s t o f F i g u r e s v i A c k n o w l e d g e m e n t v i i i 1 I n t r o d u c t i o n 1 2 Design-Rule Independence 3 2.1 T i l ing Generators 3 2.1.1 Gate Array Chip Generation 4 2.1.2 Standard Ce l l Chip Generation 5 2.1.3 Other T i l ing Generators 7 2.2 Technology Independence 7 2.2.1 Layer Functions 8 2.2.2 Design Rules 9 2.2.3 Device Construction 10 2.2.4 Generation of a transistor in C M O S 3 11 2.2.5 Split Contacts . 12 2.3 Layout Assembly Methods 13 2.3.1 Coordinate Free Layout Database 13 2.3.2 Origin Based Layout Database 15 2.3.3 Comparison of Coordinate Free and Origin Based Techniques . . . 18 i i i 3 P L A G e n e r a t o r 20 3.1 P L A Construction 20 3.1.1 Fu l l C M O S P L A s 21 3.1.2 Pseudo-NMOS N O R - N O R P L A s 22 3.2 Folding P L A s 26 3.2.1 A Folding Program: p leasure 30 3.3 T i l ing Generators 31 3.3.1 A Ti l ing Generator: mpla 31 3.3.2 A Ti l ing Generator for Folded P L A s : mpanda 33 3.3.3 Advantages of T i l ing Generators 34 3.3.4 Disadvantages of T i l ing Generators 34 3.4 Mask Level P L A Generation 34 3.4.1 Basic Structure of a P L A 35 3.4.2 Pre-processing Step 36 3.4.3 Subcell Generation 37 3.4.4 Row and Column Generation 40 3.4.5 F ina l Assembly 40 3.5 Simulations 42 3.5.1 F u l l C M O S P L A 43 3.5.2 Pseudo-NMOS P L A 43 3.5.3 Pseudo-NMOS P L A with Buffers Between Planes 43 3.5.4 Comparison of Simulations 45 4 A G a t e M a t r i x G e n e r a t o r 47 4.1 Structure and Description of the Gate Ma t r i x 47 4.2 The Intermediate Format 48 iv 4.2.1 Deficiencies in the Standard Format 50 4.3 Issues i n Producing a Gate M a t r i x 51 4.4 Applications of the Gate Ma t r i x 52 4.5 T i l ing Generation vs. Mask Level Generation 53 4.6 Gate Mat r ix Layout Generator 54 4.6.1 Preprocessing Step 54 4.6.2 Row and Column Generation ; . . ; . 55 4.6.3 Substrate and Doping Regions 57 4.6.4 Output 58 5 C o n c l u s i o n s 61 5.1 Future Work 62 Refe rences 63 A T e c h n o l o g y F i l e F o r m a t 65 v L i s t o f F i g u r e s 2.1 A Typica l Unconnected Gate Array Layout 5 2.2 A Typica l Standard Cel l Layout 6 2.3 Gate Information Required for Device Construction 10 2.4 A C M O S 3 Split Contact 12 2.5 Symbol Hierarchy for Origin Based Layout Database 16 2.6 Structure of a SYMBOL element 17 2.7 Structure of a CALL element 17 2.8 Structure of a LAYER element 18 3.9 N A N D Type Structure 22 3.10 A F u l l C M O S P L A Generated by P L A m a t e 23 3.11 Pseudo N M O S N O R Type Structure 24 3.12 A Simple Pseudo-NMOS P L A 25 3.13 A Simple Pseudo-NMOS P L A with Buffers Between Planes 27 3.14 P L A Before Row and Column Rearranging 28 3.15 P L A After Row and Column Rearranging 28 3.16 P L A after Simple Column Folding 29 3.17 P L A After Mul t ip le Column Folding 29 3.18 P L A After Row Folding 30 3.19 Tiles for mpla Program 32 3.20 A Simple Truth Table Description of a P L A 32 3.21 Input File for a Folded P L A 33 vi 3.22 Transistor Pairs i n the A N D Plane 35 3.23 Input Format for P L A Generator. '." 36 3.24 Folding a P L A in the A N D Plane 38 3.25 Stretching the P L A to accommodate conflicts i n A N D Plane 38 3.26 Exploded View of P L A section . . : 41 3.27 F ina l Layout of P L A . 42 3.28 Schematic of a Simple P I network 43 3.29 Schematic used for Simulations of Fu l l C M O S P L A s . 44 3.30 Schematic used for Simulations of Pseudo N M O S P L A s . 45 3.31 Comparison of P L A Speeds 46 3.32 Comparison of P L A Areas 46 4.33 Input Format for the Gate M a t r i x Generator 48 4.34 Half-adder circuit 50 4.35 Extended Input Format for the Gate Ma t r i x Generator . 52 4.36 Structure of a Gate M a t r i x Row or Column Descriptor. 55 4.37 Gate Ma t r i x Layout of Half-Adder 58 4.38 Comparison of Layouts Generated by Various Methods 60 vi i A c k n o w l e d g e m e n t I would like to thank my supervisor Dr . Dan Camporese for his support, input and patience during this project. Also , the equipment and software made available to the V L S I lab by the Canadian Microelectronics Corporation was invaluable in this work. Mike Bolotski was a good buddy and assisted in the editing of the final draft of this thesis, and Rod Barman was a big help i n keeping the computers running smoothly. Thanks, guys. vm Chapter 1 Introduction One of the most time consuming parts of VLSI design is the generation of the mask layout of a chip. Considerable effort has been expended in attempts to automate the layout process. Gate array [Hollis87] and standard cell layout generators have become very common and many large designs have been constructed using these methods. Gate array and standard cell chip generators are inherently area inefficient because they are based on methods which require the use of simplified placement and routing constraints. At a slightly lower level than gate arrays and standard cell based chip generators are various types of tiling generators. These programs generate layouts of a particular type using a set of pre-compiled tiles. Fully design-rule independent layout generators will not need any pre-designed cells or tiles, but will be able to generate mask-level layouts based solely on information gleaned from the design rules, which can be inputed in a simple text file. Two basic approaches to mask-level layout generation can be identified. The first method is based on relative coordinates. All objects added to a design are added using relative coordinates: they are placed relative to some object which currently exists in the design database. The CFL [Beck86] design package implements a design environ-ment based on relative coordinates. This method was used to implement a design-rule independent PLA generator. The second method utilizes absolute coordinates to specify objects in the design. A 1 Chapter 1. Introduction 2 design environment based on absolute coordinates was implemented in the C program-ming language, and was used to implement a design-rule independent mask-level gate matrix generator. During the course of the development of the above two layout generators, it was discovered to be very awkward to generate mask level layouts using a relative coordinate based system, which seem to be more suited to tile assembly than absolute coordinate methods. Chapter 2 Design-Rule Independence Layout generation programs can appear to be design-rule-independent superficially, while not actually being so. Many programs require a library of pre-designed cells to be present for any technology that they are to be used with. It is usually possible to use the same program, with the same input data, to generate a layout in any of the technologies for which there is a cell library. At this level the generator can appear to be design rule independent, but is not in the general case. Programs which require a cell library to be defined cannot be used to produce a layout in a new technology until a cell library for that technology is assembled. A truly design-rule-independent generator is one which will generate a mask level layout based on a set of design rules describing the technology. There should be no need for any pre-designed cells, although it should be possible to integrate custom designed and optimized cells into a generated layout. 2.1 Ti l ing Generators A tiling generator is a program which creates a layout from a set of pre-designed blocks. In general, these blocks are created manually. If the generation program is intended for commercial use, then the cell must be designed by experienced design engineers who are familiar with the particular technology. For generators which generate full IC layouts, such as gate arrays, there may be a large number of cells to be designed; this process can consume a significant amount of time. Chapter 2. Design-Rule Independence 4 The tiling method is used by gate array and standard cell chip generators, as well as most high level silicon compilers. A library of layout cells is required for each supported technology. A tiling generator can be described as design rule independent in the sense that the same input file can be used to generate layouts in several different technologies. However, a tiling generator is not truly design rule independent because it cannot create layouts in a technology for which there is no cell library. Assembly of a chip using a tiling generator can be divided into two phases: placement and routing. In the placement phase, the various primitive cells are assigned physical locations on the chip, and in the routing phase, wiring is added to connect the cells. 2.1.1 Gate Array Chip Generation A gate array layout is based on a structurally constrained format. Layouts are created on wafers on which transistors have already been placed, meaning that all transistor placement is been fixed. A gate array generator is required to place subcells which consist of metal interconnect patterns, and then to connect routing wires between the various cells. Routing wires are generally constrained to horizontal and vertical routing channels, often with a different conducting layer used to route in each direction. A typical gate array layout is shown in Figure 2.1, demonstrating the regular placement of the transistors, and the routing channels. For a given technology, a gate array chip generator requires a very simple technology database. The database needs only to list the routing layers for the technology, and describe contact structures which connect the routing layers. No information about transistor construction is necessary, as the transistors already exist on the wafer. While the various cells which make up a gate array cell library are quite simple, consisting simply of metal interconnects and contacts between these interconnects, many cells are required to make up a useful cell library. All of these cells must be created Chapter 2. Design-Rule Independence 5 Routing Channe l p r o Routing Channel N J J Figure 2.1: A Typical Unconnected Gate Array Layout manually, and must be modified for each new technology. One of the advantages of a gate array type generator is that the library cells are quite simple, so that updating a library to a new technology is less complicated than updating layout cells containing all the layers in a technology. 2.1.2 Standard Cell Chip Generation Standard cell chip layouts are assembled in much the same way as gate array chips. For each technology, a complete cell library is required, and chips cannot be generated for technologies without these libraries. Standard cell libraries differ from those of gate arrays in that cells consist of full physical layouts, not simple interconnect patterns. The cells Chapter 2. Design-Rule Independence 6 in the library are usually designed with parallel power and ground lines which abut in adjacent cells. Routing connections between cells are made in routing channels between rows of standard cells. The place and route system uses two or more routing layers and only needs to know where the input and output connections are located in each cell in the library, no information is required about internal geometries. If a standard cell library exists for a technology it can often be integrated into the place and route system of a particular standard cell chip generator by specifying which layers are to be used as routing layers and how those layers are connected. Figure 2.2: A Typical Standard Cell Layout In general a standard cell library is only valid for a single technology. Updating a standard cell library to a new technology is more difficult than updating a gate array Chapter 2. Design-Rule Independence 7 cell library, because the cells in a standard cell l ibrary are more complex. However, there are fewer restrictions on transistor placement and sizing in a standard cell design, so it should be possible to create designs which are more area efficient and operate at higher speed. 2.1.3 Other Til ing Generators Ti l ing generators exist for many structures which are more regular than gate array or standard cell chips. Structures like P L A s , R O M s , R A M s , and even A L U s can be assem-bled using tiling generators. In each case, however, a cell l ibrary must be created before the generation program can be used with a new technology. A n example of a P L A tiling generator is mpla which wi l l be discussed in Section 3.3.1. 2.2 Technology Independence The term "technology independence" implies any type of technology: C M O S , N M O S , B I P O L A R and others. However, transistor construction is very different in most tech-nologies, so only M O S technologies with an emphasis on C M O S wi l l be considered here. N M O S technologies use many constructs which are similar to those used in C M O S , so most of the ideas developed here wi l l apply to N M O S as well as to C M O S . In order to generate mask level layouts independent of technology, certain universal guidelines need to be established. It is necessary to identify features and constructs which are common to C M O S designs in general, rather than to specific C M O S technologies. A l l of the information that is required to describe a technology sufficiently for mask level generation is stored in a technology file. This file contains information on those layers which are used in device construction and wiring, as well as information describing the construction of each device (transistor) which is allowed. The technology file format is Chapter 2. Design-Rule Independence 8 discussed in Appendix A, which uses Northern Telecom's CM0S3 process as an example. Along with Northern Telecom's CM0S3 process, the MOSIS Scalable CMOS (SC-MOS) process, and an old version of the ISOCMOS used by Microtel Pacific Research were used to test the technology independence of the layout generators to be described in this thesis. 2.2.1 Layer Functions When dealing with layout generation, it is conceptually simpler to refer to layers and masks as though they were synonymous. In fact many of the "layers" are not physical layers, but regions of diffused or doped substrate. In the discussion which follows the terms "layers" and "masks" both refer to the layer masks used in the device fabrication process. Every CMOS technology has a certain set of layers, which have fairly specific func-tions. Different technologies will refer to these layers by different names, but the func-tionality will be the same. For example, in the CMOS3 process, the layer used to form device channels is called the "device well" layer, while in the ISOCMOS process, the layer is referred to as the "active layer". Despite the different names, the layer serves the same purpose. It is important to recognize that it is the function of the layer which must be used to identify it, rather than the name. There are a set of primary layers which must be identified for a new technology. Every CMOS technology has a gate layer, which is used to form transistor gates; this layer is generally polysilicon. Also, the channel layer must be identified, and the primary routing layer, which is usually a metal layer. In some cases it may be useful to identify a secondary routing layer as well. Connections between the above primary layers is accomplished by a set of contact layers. After the primary and contact layers have been specified, other layers can be categorized more generally as substrate or well layers and doping layers. Chapter 2. Design-Rule Independence 9 Additional layers, such as the overglass layer, may exist in the design process, but are not relevant to circuit construction. These layers are classified as other layers. 2.2.2 Design Rules Identification of the primary layers is a necessary initial step. It is also useful to identify design rule constraints at the same time, so that a layout which is free of design rule violations can be generated. Design rules exist in a number of areas, each of which is discussed below. The first design rule constraint is that of the minimum dimension of a mask layer. This rule indicates how small the geometry on a given layer can be. Among other things this sets the minimum size of a transistor in the given technology. Under normal circumstances, the minimum dimension is used when creating geometry on a particular layer. On occasion, features larger than the minimum size will be constructed. Long power and ground will often be built on metal layers which are larger than minimum size to accommodate larger currents. Transistors can also be created in differing sizes depending on how much drive is required of them. After the dimension rules are the spacing or separation rules. These specify how much space must lie between unconnected structures on different layers. This information sets the spacing between adjacent devices or parallel routing wires. The other major design rules focus on device construction. Information on the doping and substrate for a device come from the enclosure rules, which specify parameters such the minimum enclosure of an active region by a well or doping region. The gate overhang rules deal directly with the devices in the current technology, and is discussed further in the next section. Chapter 2. Design-Rule Independence 10 2.2.3 D e v i c e C o n s t r u c t i o n A l l C M O S transistors consist of basically the same structure: a gate crossing over a channel. The gate and channel layers are identified i n the technology file. The generator also needs to know the min imum gate/channel overlap, and the min imum extent of the channel beyond the gate on either side. In the technology file, the layers forming the device are specified starting with the channel layer, then the gate layer, and finally the various doping/substrate layers. From this information, and the rules relating to enclosures of one layer by another, it is possible to construct the transistor. Figure 2.3 graphically shows the parameters required by the generation algorithm. Channel Extension \ / Channel Gale Overhang Channel Extension Gate Figure 2.3: Gate Information Required for Device Construction Construction of a transistor begins with the placement of the gate and channel layers. The other layers in the device description are processed one at a time, checking for enclosure rules wi th each other layer in the device description, and with the special layer gate. In this way the required layer geometries are determined, and the layers surrounding the gate are sized and placed correctly. These layers are referred to as the surrounding Chapter 2. Design-Rule Independence 11 layers, because they physically surround the gate. In practice, it is not feasible to construct each device individually, since it is common for several devices of the same type to be placed adjacent to each other. Constructing devices one at a time could possibly result in design rule violations dealing with layer spacing, particularly wi th the surrounding layers. To avoid this problem, transistors of the same type are grouped into regions, the boundaries of which are calculated. Then the surrounding layers are placed around the entire region rather than around an individual device. 2.2.4 G e n e r a t i o n o f a t r a n s i s t o r i n C M O S 3 As an example of device construction, the steps in building an n-channel transistor in Northern Telecom's C M 0 S 3 process wi l l be described. A l l the required information is contained in the technology file included in Appendix A . 1. Identify the gate and channel layers. For C M O S 3 they are "polysil icon" and "de-vwel l" respectively. 2. Generate a transistor by placing the gate layer over the channel. The type of the transistor is established by the type of doping, and the substrate in which the transistor is placed. 3. Place wells and doping layers. The technology file for C M O S 3 indicates in the . d e v i c e entry for an "n-channel" device, that the layers composing the transistor are: "devwell," "polysil icon," "p-well ," "p-guard," and "n-well ." The first two layers have already been placed, but the other three are st i l l needed. These three layers are well or doping layers, as indicated in their respective . l a y e r entries. They wi l l be passed to a routine that generates the layers surrounding the transistor. Chapter 2. Design-Rule Independence 12 Each surrounding layer is indexed against al l other layers in the technology file to determine minimum allowable dimensions of that layer around the device. After these dimensions are calculated, the surrounding layers are placed. 2.2.5 S p l i t C o n t a c t s A split contact is a structure which combines a contact to power or ground with a substrate contact, and is a convenient space-saving construct. Split contacts are valid structures in many C M O S technologies, and it is often desirable to make use of them. However, they also tend to violate a number of design rules, and are therefore more difficult to describe. A C M 0 S 3 split contact, layout is shown in Figure 2.4. Figure 2.4: A C M 0 S 3 Split Contact. A split contact consists of two portions: a contact to a power or ground line, and a contact to the device substrate. The two sections of the contact must be doped differently, and this is where design rule violations come in . In most cases diffusion regions must be completely enclosed by a doping mask, whereas the doping masks in a split contact wi l l Chapter 2. Design-Rule Independence 13 cut across the diffusion region. For these reasons, split contacts are not currently handled by any of the layout gen-erators described in this work. 2.3 L a y o u t A s s e m b l y M e t h o d s There are a number of possible methods for assembling a layout. In general, the layout is held in some internal database unt i l completed, and then the database wi l l be written to a file in some common layout format. Whi le the layout is being generated, new objects are added to the database using subroutine calls for this purpose. Objects can be added to the database using two different positioning methods: relative to other elements, or relative to the origin of the entire layout being generated. Both methods are useful under certain circumstances, and both were studied in separate mask-level layout generators. 2.3.1 C o o r d i n a t e F r e e L a y o u t D a t a b a s e A typical coordinate-free layout database is implemented i n the C F L subroutine package from the University of Washington. The package supplies a number of routines for placing structures into a layout database. Da ta is organized into SYMBOLS which can contain boxes of valid mask layers for the current technology, or other SYMBOLS to allow for hierarchy in the design. Items must be created by specific subroutine calls, and then may be combined with existing symbols. The package is intended to be coordinate free, so that designers can use relative coordinates when placing components, rather than keeping track of absolute coordinates. This approach allows a sub-block of the design to be placed relative to another block without knowledge of the absolute or true coordinates of the latter block. C F L provides Chapter 2. Design-Rule Independence 14 functions to accommodate alignment of blocks at edges through layers or user defined points crossing or touching the bounding box of the block. Placing objects using relative coordinates can be useful in some cases, while being very awkward at other times. In general, it is more useful to use-relative coordinates when dealing with fully designed layout blocks, such as those used in tiling generation programs, or in standard cell chip generators. In cases where overlaps between adjacent cells are required, and where many objects are to be placed close together and may overlap each other, relative coordinates become very difficult to use. The reason for the difficulty is that all overlap offsets need to be calculated, and these calculations can become quite involved in regions where several objects mutually overlap. During the generation of mask-level layouts, multiple objects frequently overlap, rendering the relative coordinate approach unsuitable. Because the PLA generator was conceived as a number of abutting components, it was implemented using a relative coordinate system using the CFL package. During development of the software it became obvious that even though much of the layout generation could be done using relative coordinates, there were areas in which relative coordinates were inadequate. With layout components which are replicated many times, as is the case for input and output buffers, it is much easier to create a layout block for that component, and add it to the database at the points where it is needed. Symbol alignment is difficult in CFL, because CFL routines generally only accept two blocks in alignment operators, and often many more blocks must be mutually aligned. Also, alignment can only occur on block boundaries, and it is often much more efficient to align connected wires at some point internal to a block. Another difficulty in doing mask level layout generation occurs if there is no easy access to database structures. When transistors are being formed, for example, it is nec-essary to determine the boundary of the region containing all the active devices in order Chapter 2. Design-Rule Independence 15 to determine the sizing and placement of substrate/well regions. The layout database needs to allow such information to be extracted, and C F L does not provide this type of access. 2.3.2 O r i g i n B a s e d L a y o u t D a t a b a s e The absolute coordinate approach lacks some of the useful features associated with the coordinate free method, but a number of tasks can be handled wi th considerably less effort. The primary drawback of absolute coordinates is the difficulty encountered in the alignment of complex structures, such as input buffers for the P L A with input columns. Alignment utilities can be added, to augment the system. These utilities should be more general than the ones offered by C F L i n that they access alignment structures which may be contained within a symbol structure. The alignment operators would return absolute coordinates of the alignment points, and then the structures could be placed into the design database. The approach taken i n this work is to create the low level structures such as rectan-gular boxes of a particular mask layer, and then to insert these structures into the larger design database. The implementation of this is based on the hierarchal symbol database shown in Figure 2.5. A t the top of the hierarchy is a DESIGN structure. The DESIGN contains a list of SYMBOLS which compose the whole design. The basic design unit is the SYMBOL. A SYMBOL is equivalent to a C I F [MeCo80] symbol, or a G D S II [Rubin87] structure. The structure of a SYMBOL is fully displayed i n Figure 2.6. It contains the elements next and prev which are used to form a list of symbols active in the current design. Also included are the call field (see below) which defines a list of sub-symbol calls. The layers field is a list of layers which are used in the current symbol. It is possible for a symbol to consist solely of mask geometries Chapter 2. Design-Rule Independence 16 Figure 2.5: Symbol Hierarchy for Origin Based Layout Database (layers) and have no sub-symbol calls or vice versa. In the case where there are no calls, then the calls field is N U L L (zero). Bo th the calls and layers fields refer to structures similar to the SYMBOL structure. In addition to the fields mentioned above, the SYMBOL structure contains miscellaneous information which identifies the symbol, and provides housekeeping information to the database system. The C A L L structure is shown in Figure 2.7. As with the SYMBOL structure, there is a next field which is used to link a list of calls referenced by a SYMBOL which contains the call . This provides for the hierarchy in the database.. The CALL also contains a symbol and a number field which identifies the symbol being referenced. The tx and T fields provide transformation information in two forms. The transformation is used to place Chapter 2. Design-Rule Independence 17 V a r i a b l e D e s c r i p t i o n next Next symbol in list prev Previous symbol in list name Name of the symbol number Number of the symbol a, b A / B type scaling factors scale Floating point scaling factor calls List of sub-symbol calls layers List of layers used in symbol X-min 5 Ymin Lower left corner of bounding box ^maxi Ymax Lower left corner of bounding box bbox T R U E if bounding box is current defined T R U E if symbol has been defined written T R U E i f symbol has been written to output Figure 2.6: Structure of a SYMBOL element. and orient the SYMBOL being referenced. V a r i a b l e D e s c r i p t i o n next Next call in list symbol Symbol which is being called number Number of the called symbol tx List of applied transformations T 3 x 3 transformation matr ix accum T R U E if transformation matrix is current Figure 2.7: Structure of a CALL element. The other important element in the SYMBOL structure is the layer field. It contains information which identifies the layer being referenced, and provides links with other Chapter 2. Design-Rule Independence 18 layers used in a symbol. There are two fields for including geometry on the layer: the wires and the polygons fields. A polygon is composed of a list of vertices which form a closed figure. The wire description consists of a series of points forming a path, and a width for the wire. It is possible to describe a wire as a polygon, or a polygon as a wire, but it is often more convenient to have both structures. V a r i a b l e D e s c r i p t i o n next Next layer in list name Name of this layer number Number of this layers polygons List of polygons for this mask wires list of wires for this mask X m i n j Ymin Lower left corner of bounding box X-maxi Ymax Lower left corner of bounding box bbox T R U E if bounding box is current Figure 2.8: Structure of a L A Y E R element. The database interface provides routines to add objects at any level. For example, wires can be added to layers or to symbols directly, or calls can be added to symbols. This interface is also useful in that it is possible to read pre-designed blocks into the database from C I F or Ca lma G D S II Stream Format, and use these blocks as sub-blocks i n layout generation. 2.3.3 C o m p a r i s o n o f C o o r d i n a t e F ree a n d O r i g i n B a s e d T e c h n i q u e s B o t h the coordinate free and the absolute coordinate layout techniques were used to implement design rule independent layout generators. The coordinate free method was used to write a P L A generator and the origin based method was used to design a gate Chapter 2. Design-Rule Independence 19 matr ix layout generator. The coordinate free method is most efficient for assembling layouts from a set of sub-blocks which can be butted together. This makes the method very useful for tile-based layout generators like m p l a . However, when complex structures are to be built at the mask level, there is a great deal of overlap between geometries on different layers. Over-laps occur when transistors are being constructed, when wires on different layers cross over each other, and when substrate and doping regions are being added. These problems do not occur in ti l ing generators, because all of the geometry required i n a layout block has been fully specified when the library of required blocks was created. Overlaps can be handled by a coordinate-free system through the use of offset parameters. However, attempting to calculate offsets for overlapping structures is contrary to the goals of a coordinate-free system. The calculation essentially duplicates internal coordinate han-dling used by the package to hide coordinates from users. In addition, offset calculations require that positions of those layers already in the database be known, in order that the positions of new layers can be calculated. Since coordinate free systems do not retain this information in an easily usable form, it is necessary to search through the list of layers currently residing in the database for the cell being assembled to find the relative positions of those layers which wi l l be involved in the overlap. A system which uses absolute coordinates is more complicated to use, since it is nec-essary to retain a set of (x,y) coordinates while the layout is being assembled. However, the task of adding objects into the layout database at an arbitrary location is greatly simplified. The extra complexity added by the need for retaining coordinates is easily offset by the elimination of the offset calculations needed i n a coordinate free method. Objects can be added to the database at a calculated position, which may create an overlap wi th existing objects. It is also easy to add objects to the interior of a layout block, a procedure which is extremely difficult in a coordinate free system. Chapter 3 PLA Generator PLAs are useful in many applications. Instruction decoders in microprocessors (especially RISC microprocessors) are often constructed using a PLA or a series of PLAs. Finite state machines can be built using a PLA with the appropriate feedback circuitry. PLAs are simple structures which have a highly regular architecture. This simple architecture makes them easy to design, thus reducing design time, and making it feasible to generate layouts automatically. Because PLAs are fairly simple to construct, they are a good starting point for the study of mask level layout generation. Some of the basic ideas of design rule independent generation can be tested in simple PLA layout generation, and more complex problems can be addressed when folded PLAs are considered. Most previous work on PLA generation has concentrated on tiling oriented generators. Tiling generators provide an alternative layout generation methodology against which the performance of a mask-level design rule independent generator can be compared. 3.1 PLA Construction A basic PLA consists of two planes, the AND and the OR planes. This structure allows the implementation of any sum-of-products combinational logic expression. Sequential logic is more difficult, but can be realized using a PLA with external feedback circuitry as part of a finite state machine. The planes of the PLA can be constructed in with several different methods each of which aim to optimize a different parameter, such as layout area or power dissipation. The choice of method depends on which factor is considered 20 Chapter 3. PLA Generator 21 most important. 3.1.1 F u l l C M O S P L A s In a full C M O S P L A , each N-channel device has a corresponding P-channel device. The primary advantage of a C M O S P L A is the low power consumption of full C M O S designs. Because N and P channel devices require different substrates, layout area can be reduced by collecting devices of a similar type into large regions of one substrate. The area gain is a result of the reduction in the number of area-intensive P- to N-substrate transitions. Unfortunately, this approach separates N and P channel transistor pairs by significant distances, requiring long connection wires. The physical consequence of the resulting long connecting wires is a large R C delay which results in much slower P L A s . In C M O S , N A N D and N O R gates are more easily implemented than A N D and O R structures, and can be made functionally equivalent by the addition of an inverter on the gate output. The choice of architecture for a C M O S P L A is between a N A N D based system and a N O R based system. In either number of devices must be connected i n series, which wi l l result in increased delays. The more transistors which are connected i n series, the slower the circuit wi l l be. In general, the N A N D structure is preferable, because N-channel devices are usually faster than P-channel devices. A full C M O S N A N D type structure is shown in Figure 3.9. Since each input to the P L A connects to several of the N A N D gates, P L A s wi th a large number of inputs must be constructed wi th N A N D gates wi th many transistors i n series. The program P L A m a t e [Leask87] from the University of Waterloo generates a full C M O S P L A in Northern Telecom's C M 0 S 1 B technology by default. A n example of a full C M O S P L A generated by this program is shown in Figure 3.10. P L A m a t e claims to be technology independent, but requires a dedicated program to act as a module generator for each different technology. This is in contrast with other generators such as Chapter 3. PLA Generator 22 L> E> [] [] CD [] 63-• [] - B - <3-CD \7 Figure 3.9: N A N D Type Structure. m p l a which require cell libraries for each supported technology, but require no additional programming when a new technology is introduced. Some of the problems with a full C M O S P L A are evident in Figure 3.10. In order to connect the N and P channel transistor pairs, long busses are required. If the lines are i n polysilicon, as they are with P L A m a t e , then the R C delay characteristics are significant. In addition, the wire busses occupy a great deal of area. 3.1.2 P s e u d o - N M O S N O R - N O R P L A s Pseudo N M O S is based on N M O S type designs, in which there is a single pullup transistor for several pulldown transistors. Each row in a P L A corresponds to one " A N D " gate in Chapter 3. PLA Generator 23 AND Plane OR Plane Inputs Outputs Figure 3.10: A F u l l C M O S P L A Generated by P L A m a t e . the A N D plane, and each column in the O R plane corresponds to one " O R " gate. Since each gate in a pseudo-NMOS design requires one pullup transistor, and each row and each column correspond to one " A N D " or one " O R " gate respectively, one pullup transistor is required for each row and column. The pullup transistor is a P-channel connected as a static pullup, wi th its gate connected to ground so that it wi l l always be on. The pseudo-N M O S architecture is designed to reduce the area occupied by the P L A by eliminating most of the P-channel devices. Pseudo-NMOS P L A s can be implemented with a N A N D structure which differs from the schematic of Figure 3.9 in that only one P-channel device is used. Unfortunately, this configuration sti l l suffers from the speed problem of series connected N-channel devices. Chapter 3. PLA Generator 24 A n alternative to the N A N D structure is the pseudo-NMOS N O R structure. Among the advantages of the N O R structure is the fact that there are no transistors in series, so the circuit is faster than the corresponding N A N D structure. It too can be made functionally equivalent to an A N D function by supplying inverted inputs to the N O R gate, and inverting the output. This logical equivalence is demonstrated with DeMorgan's theorem in Equation 3.1. Figure 3.11 shows this structure as it is implemented in the P L A generator. A + B A B A B (3.1) L> L> -B—\ « LJ \ 7 - B - C [J CJ \ 7 -e-LJ «3-[J [J X7 -E> Figure 3.11: Pseudo N M O S N O R Type Structure. The A N D / O R architecture of the full C M O S P L A is replaced by an equivalent N O R / N O R structure. The P L A is st i l l divided into two planes, and the planes are Chapter 3. PLA Generator 25 sti l l referred to as the A N D and O R planes, since they are functionally identical to A N D and O R planes i n a full C M O S P L A . In Figure 3.12 pseudo-NMOS is used to bui ld a simple 4-input, 3-output P L A . In this sort of structure, each " A N D " gate i n the A N D plane has a maximum fan-in equal to the number of inputs to the P L A , and each " O R " gate in the O R plane has a fan-in equal to the number of product terms (rows) in the P L A . Figure 3.12: A Simple Pseudo-NMOS P L A . The constraint of one pullup per row (one pullup per column) applies only to simple P L A s such as the one i n Figure 3.12. In the case of a folded P L A , where multiple logical rows may be combined into a single physical row, placement of pullup transistors is more complicated. It may be possible to find empty space in a P L A row into which a pullup may be inserted [Lurs88]. Whi le this solution may seem elegant, it is definitely not consistent. There is no guarantee that it wi l l be possible to fit the pullups into spaces Chapter 3. PLA Generator 26 inside the rows, and in those cases where it is possible, an extra area overhead is involved in changing from a P- to an N-substrate, and in connecting to the pullup. A much more generally useful solution is to place pullups at an inter-plane transition. If buffers are to be placed between the planes, then the row pullups may be integrated as a part of the buffer structure. Using this scheme, a P L A layout generator must make a simple test to be sure that only one pullup is placed on rows which may span more than one inter-plane transition. Modifications to this general structure are possible. One common addition is the inclusion of buffers between the planes of the P L A . The intention here is to split the long product term (pterm) wires which form the rows of the P L A and are usually constructed on the gate layer, typically polysilicon. Polysil icon tends to have high resistance and capacitance characteristics, which results in significant R C delays for longer wires. The buffers reduce the total length of a wire, and give additional drive to a signal propagating on the wire. The configuration can be seen in Figure 3.13. The pseudo-NMOS P L A architecture is much more common in P L A designs for rea-sons discussed above, and was the architecture chosen for the design-rule-independent P L A generator work. 3.2 Folding PLAs Folding is a concept introduced to reduce the overall area of a P L A by taking advantage of sparsity in a P L A matrix. It is possible to rearrange the order of pterm rows, and of input /output columns i n such a way that one or more rows (columns) may be combined into a single row (column). Simple folding involves the combination of two rows or columns, and multiple folding refers to the combination of more than two rows or columns. Column folding is the most effective method of P L A folding because there is little or Chapter 3. PLA Generator 27 i t j f i f 5" Y V Y Figure 3.13: A Simple Pseudo-NMOS P L A with Buffers Between Planes. no area overhead involved. To perform a column fold, the pterm rows in a P L A need to be reordered so that transistor sites i n the columns to be combined do not overlap i n rows. Figure 3.14 shows a simple case where several columns are to be combined. The in i t ia l array seems to offer l i t t le opportunity for folding, but after rows have been re-arranged as in Figure 3.15, it is possible to see where folding can occur. The array i n Figure 3.15 can be folded using simple or multiple folding in the O R plane. These two cases are show i n Figure 3.16 for simple folding, and Figure 3.17 for multiple folding. W i t h simple folding all inputs and outputs appear on the top or bottom of the array, while wi th multiple folding, some inputs or outputs must be placed on the sides of the array. A simple column fold reduces the total number of physical columns in a P L A by one, while a multiple column fold reduces the number of physical columns by more than one, depending on the number of columns which are combined. Chapter 3. PLA Generator 28 O R A N D Figure 3.14: P L A Before Row and Column Rearranging. A N D O R p. p7 p, p. p, p3 p. p. i. i, i , i= i, i, o, 0, 0, 0, 0, Figure 3.15: P L A After Row and Column Rearranging. Row folding is also possible by combining two or more rows into a single row. W i t h each row fold, another plane is created. A simple row fold wi l l thus create an A N D -O R - A N D ( A O A ) structure or a O A O structure. Because an additional plane is created, there is some extra overhead involved. The inter-plane connection consists of at least a contact structure connecting the gate wire in the O R plane wi th the routing wire in Chapter 3. PLA Generator 29 A N D O R B ; ) : S 5 E ) 7\ ! ' 1 Figure 3.16: P L A after Simple Column Folding. A N D O R - % ; i « 3 0, Figure 3.17: P L A After Mul t ip le Column Folding. the A N D plane (usually polysilicon and metal respectively). In some cases, it is useful to have buffers between the planes to break up long polysilicon lines. If this scheme is used along wi th row folding, the overhead of an additional plane may actually result, in Chapter 3. PLA Generator 30 an increase in area. Figure 3.18 shows how row folding affects the structure of a P L A . OR A N D OR p, . p, Pi , p. p. p. 0 3 0, 0 , I, I, Ia I, 1, I3 0, 0, Figure 3.18: P L A After Row Folding. The problem of P L A folding is N P complete, so this means that some heuristic is required to do the folding in a manner which is as close to optimal as possible. There are many algorithms and programs available for solving this problem. 3.2.1 A F o l d i n g P r o g r a m : p leasure The folding program which is used by the design-rule-independent P L A generator is p l ea su re [Sangio83]. It accepts input in the form of a t ruth table as in Figure 3.20, and produces output in the form read by m p a n d a [VLSI86], a t i l ing generator for folded P L A s . The output format produced by p leasure is typified by the P L A in Figure 3.21. As previously discussed, P L A s can be folded in several ways. The program p leasure is capable of handling several of these forms, and is designed to give the designer as much control over the topology of the final P L A as is possible. The folding performed by p l easu re can be in the form of simple row or column folding. To provide more flexibility, and to allow a designer to fit the P L A into a larger design more easily, p l easu re also allows certain constraints to be applied to the final placement of inputs and outputs. This Chapter 3. PLA Generator 31 is called constrained PLA folding. Constrained folding can be used with either simple or multiple folding. Constraints can be applied to force inputs or outputs of the folded P L A to appear on a particular side of the P L A , to group a certain set of columns or rows and to preserve their order, or to specify the architecture of the folded P L A ( A N D - O R - A N D or O R - A N D - O R ) . It is often easier to fit a macro cell into a chip design if certain inputs and outputs of the block can be placed in a certain location on the block, and pleasure allows these constraints to be applied to the folded P L A . 3.3 Ti l ing Generators 3.3.1 A Ti l ing Generator: mpla A simple method of generating a P L A layout is to use a t i l ing generator such as mpla. This program wi l l generate simple, unfolded P L A s by assembling a series of tiles or cells into an array. A large number of cells are required i n the generation of a P L A , as shown in Figure 3.19. mpla takes a simple truth table in the form of Figure 3.20 as input, mpla places the tiles, based on the placement of transistors specified i n the truth table. Each element in the truth table corresponds to one or more cells in the database for the current technology. Tiles are simply butted together to form the final layout. There are fairly strict guidelines on tile specifications to ensure that adjacent tiles wi l l form correct connections. Most parameters, such as transistor gate size, are fixed by the tile cells, but it is possible to have mpla insert additional ground lines, and to stretch ground or power lines to allow for larger currents. Chapter 3. PLA Generator 32 ul—and top-and lop—mid leftu-and 1-and r-and midd leftd-and midu HGleft-and HGI-and HGr-and | HG-mid~ U-and bot-and bot-mid Figure 3.19: Tiles for mpla Program. . i 6 .o 8 .p 10 HOOxx 10100010 xOlOxx 11000001 OxlOxx 10000000 xOOlxx 10001000 OxOlxx 10000000 xxllxx 00100000 lx l lxx 00000010 l l l l x x 10000000 lxx l lx 00010001 lxOllx 00010000 . e Figure 3.20: A Simple Truth Table Description of a P L A . Chapter 3. PLA Generator 33 3.3.2 A Ti l ing Generator for Folded P L A s : mpanda A program which is capable of generating the layout of a folded P L A is mpanda de-veloped at the University of California at Berkeley. A more complex input format is required to describe a folded P L A , and mpanda uses a number of special characters to indicate splits and folds i n a P L A array. A n example of a mpanda input file is shown in Figure 3.21. Because of the extra complexity introduced by folding, mpanda requires considerably more tiles than is required by mpla. . t op i n l out4 out3 ou t6 . .bot tom i n 2 o u t l out2 out7 out5 out8 i n 3 i n 3 . and 2 9 4 . row 6 * X +++XX++XX X X * * X - ; l - — •1— -;-x X l _ - 1 ~ I ~ ~ ~ I I ~ ~ 1- •1;- — X X l - 1 - 1 I I I 1- > — X X l - 1 - I ~ | I ~ - l - X X_—1 ~ ~ ~ I ~ I I I ~ — 1, - — X X - l , - I~~H 1- 1—X * * +++++XX++ * * X X . end Figure 3.21: Input Fi le for a Folded P L A . In Figure 3.21, a ";" symbol indicates that a transistor is present, along with a split in the row. This means that the horizontal wire (pterm wire) is terminated at that point due to a fold in the row. The symbol "1" indicates a transistor in the A N D plane, and a " I " is a transistor in the O R plane. The "," symbol indicates a split in the row, with no transistor present. Chapter 3. PLA Generator 34 3.3.3 Advantages of Ti l ing Generators The primary advantage of a t i l ing generator like mpla is due to its use of a cell library. The layout is generated from a set of pre-constructed tiles, so there is no need to generate much of the layout at the mask level. As a result, the layout generator is faster than a mask level generator. 3.3.4 Disadvantages of Ti l ing Generators Ti l ing generators require a complete set of tiles for each technology wi th which they are to be used. These tiles must be created individually by an experienced designer, and must be modified or replaced whenever the current technology changes, or a new technology is introduced. Another l imitat ion imposed by t i l ing generators is that control can not be exerted over the layout on a transistor by transistor basis. Transistor characteristics such as gate width are fixed in the tiles, and not alterable. A mask level generator can size transistors individually, based on netlist data, load factors or other schemes. 3.4 Mask Level P L A Generation In the P L A generation method described in this thesis, the layout is constructed row by row, and then column by column. As each row is constructed, it is placed relative to those rows which were built before i t , based on pre-calculated spacings. After the columns have been similarly constructed and placed, the rows and columns are combined into the final array. A more detailed explanation of the generation algorithm follows. Chapter 3. PLA Generator 35 3.4.1 B a s i c S t r u c t u r e o f a P L A The basic structure used in the P L A generator is depicted in Figure 3.22, which is based on work described in [Jinks85]. It shows how rows and columns are arranged so that two adjacent device rows or columns (pterm rows, input and output columns) share a ground row or (column). In addition, adjacent transistors connected to the same device row (or column) may share a contact to that row (or column). This technique is designed to minimize layout area. M 1 $$ SSI 1 1 HI, G r o u n d G r o u n d T r u e Comp lement T r u e Comp lement Figure 3.22: Transistor Pairs in the A N D Plane. In folded P L A s , some modification to the basic structure is required. The modifica-tions are needed to handle cases where a fold occurs, requiring a split i n the wire. The modifications generally involve local changes in row or column spacing. Chapter 3. PLA Generator 36 3.4.2 P r e - p r o c e s s i n g S t e p The first step converts the P L A into a format recognized by the main generation en-gine. Since both truth table and p a n d a [VLSI86] input styles are supported, a certain amount of processing is required. The main input format for the generator is a modified p a n d a format, with all internal spaces removed, and plane to plane contacts marked. A n example of this format is shown in Figure 3.23 * X +++XX++XX X X * * X- ; 1-CI~ I — I C — 1 — ;-X X1_-1C~I~~~II~~C1-1; X XI- l - C IIIIC1 ; — X X l - l - G I~|I~C 1-X X_—1C~~~I~III~C— 1, X X - l . - C I~~IIC1-;~1—X * * +++++XX++ * * X X Figure 3.23: Input Format for P L A Generator. Converting from the standard p a n d a format to the modified format consists of re-moving unnecessary spaces, and inserting the plane to plane contact marker. Converting a t ruth table requires basically the same processing. After the input file has been con-verted, it is scanned row by row, and column by column. The scanning is intended to locate possible conflicts in transistor placement, especially where a split or a fold occur. A conflict occurs where adjacent unconnected transistors may be placed too close together, and violate some of the design rules. During the scanning, splits and folds are flagged, along with the presence of adjacent transistors. A t a point where a split or fold occurs, adjacent transistors can no longer share a contact to a pterm wire and extra space must be added. The flags are used when the rows and columns of the P L A are assembled. Chapter 3. PLA Generator 37 3.4.3 Subcell Generation After the P L A has been put into a format usable by the generator, a number of sub-cells need to be created. These cells are used by the generator to assemble the rows and columns of the P L A . In order to ensure that all possible folding situations can be handled, many cells are needed. The cells consist of small pieces of wire or diffusion which are abutted during row/column generation. Cells are needed for contacts between the channel and routing layers, and between the gate and routing layers. A number of cells are needed for each type of row and column, such as cells which form the channel of a transistor, and cells which consist solely of a connecting wire. Once spacing requirements have been determined, the process of assembling the P L A begins. Rows and columns are assembled by stepping through the list of elements com-posing the row/column, and placing a series of subcells depending on the type of the element. Since transistors are arranged in pairs as shown i n Figure 3.22, adjacent tran-sistors may overlap in two places: the contact to the pterm wires, and the contact to the G N D wires. This suggests that transistors may be split into three parts: the contact to the pterm wire, the body of the transistor and the contact to the ground wire. Each element in the truth table corresponds to a transistor position. In that position, there may or may not be a transistor. In addition, for folded P L A s , there may be a fold, meaning that there wi l l be no connection between adjacent elements. Figure 3.24 shows such a situation in the A N D plane. Thus for each transistor position there are three cases to be handled: 1. Transistor is present, 2. Transistor not present; pterm wire connecting to the next element, 3. Transistor not present; no connection (there is a fold). Chapter 3. PLA Generator 38 i m m m M Complement True Complement Figure 3.24: Folding a P L A in the A N D Plane. Three separate cells are required in each of the above cases, one corresponding to each part of a transistor. In addition, separator cells are required i n those cases where the P L A must be stretched to accommodate conflicts between adjacent transistors. This case is shown in Figure 3.25. 1 W SK%< 1 i 1 m 1 1— r " |— p -M m m 1— —i i i i Split _i 1 Figure 3.25: Stretching the P L A to accommodate conflicts i n A N D Plane. Chapter 3. PLA Generator 39 A row fold wi l l produce an area reduction of: AArow = A r o w - J2 [{*)(A.ep) + AAO] (3.2) A n d a column fold wi l l produce an area reduction of: AAcoi = Acoi E K * ) ( ^ P ) ] i=J where: A si-row = Area of an unfolded row. Acol = Area of an unfolded column. NfoU, = Number of folds i n the row/column. X = True( l ) if extra spacing is required, or False(O) i f not (Figure 3.25). A = E x t r a area required to separate transistors. AAo = Area of an A N D to O R plane transition. (3.3) Chapter 3. PLA Generator 40 Another problem which must be considered is whether a cell containing several sep-arate layers, such as a contact cell, must extend any of its layers to the edge of the cell. Depending on the design rules for a particular technology, it may be possible that the min imum enclosure rules for some layers wi l l result in cells in which all the connection type layers do not extend to the edge of the cell. This could occur in a polysilicon to metal contact, for example, if the metal enclosure of a contact cut was different than the polysilicon enclosure for the same contact. In this case, both metal and poly would not have to extend to the edge of the contact cell, and special care must be taken to ensure that this situation is handled correctly. 3.4.4 Row and Column Generation After the cells have been generated, the rows and columns are assembled. The assembly follows the format of the specified P L A . Each element in the input file corresponds to one or more of the primitive blocks described earlier. The procedure is to step through the elements of a particular row, decide on whether or not a transistor is to be placed, and whether or not a connection is to continue through the element to the succeeding element. This is done for each row and column separately, wi th no reference to any of the other rows or columns i n the P L A other than the spacing parameters determined earlier. A t this time, checks are also made to determine whether extra space must be added to eliminate conflicts caused by splits in a row or column. If a conflict exists, a spacing cell is added to the layout. 3.4.5 Final Assembly When separate cells exist for rows and columns, those cells are combined into a single cell which contains all the rows and columns. Then the bounding boxes of the regions con-taining al l the diffusion blocks of each doping type are determined, and the well/substrate Chapter 3. PLA Generator 41 regions are placed into the layout. A t this stage, the entire A N D / O R plane structure is assembled. A n exploded view of the upper left portion of the example i n Figure 3.23 is shown i n Figure 3.26. The exploded view includes two rows of the P L A in the first A N D plane section. Also included are the A N D to O R plane connector, and the first column in the O R plane. - ; l - c • • l.'i [....:• Ill |:'J Q [J. 1 ' m r[np rrj~i I D U D • • • • • O L T r i L r j n a c L T i y n rS: n D :  •3D • • • e g ] • ] • i — i j o O [) [• .X3-• • r-i • ] c 1 c Figure 3.26: Exploded View of P L A section. The final layout of the example shown in Figures 3.21 and 3.23 can be seen in F ig -ure 3.27. In this layout, the various well and guard layers have been removed to improve readability. Layouts were also generated in the S C M O S and the I S O C M O S processes. A complete design rule checker rule file exists for C M 0 S 3 , and it was used to verify the correctness of the C M 0 S 3 layout. The S C M O S and I S O C M O S designs were checked by hand and determined to be correct Chapter 3. PLA Generator 42 @4 ft 3 .ipj. f e LRl y TO p jy y at i s typA -m. dai= 4Sf "13 Figure 3.27: F ina l Layout of P L A . 3.5 Simulations In order to verify that pseudo-NMOS P L A s are more area and speed efficient than full C M O S P L A s , a series of S P I C E simulations was performed on a set of P L A s of varying size. In addit ion, approximate P L A areas were calculated for the same set of example P L A s . Comparisons were made for three P L A styles: full C M O S P L A s , pseudo-NMOS P L A s and pseudo-NMOS P L A s with buffers between A N D and O R planes. In each case, a P L A size was arbitrarily chosen i n terms of the three major dimensions of a P L A : number of inputs, number of outputs, and number of product terms (rows). Resistance and capacitance values were calculated based on the size of a simple P L A unit , as in Figure 3.22, in the A N D plane, and a corresponding structure in the O R plane. Using this basic unit, wire areas were calculated to obtain load capacitances, and resistances were calculated based on the wire length and width. Using an estimate of one transistor gate per three pterm wires, one gate per three inputs, and one gate per three outputs, the total number of gates on a wire was determined, and the total gate capacitance added to the wire capacitance. For those wire segments to which transistor drains were connected, a similar scheme was used in calculating total drain capacitance. Chapter 3. PLA Generator 43 The calculated resistance and capacitance values were generated using a simple C program which can generate values for arbitrary sized P L A s . The R C delay effects were modeled by a simple P I network of the type in Figure 3.28. A l l resistance and capacitance values were based on the C M 0 S 3 process. O — ^ V V V - Q 9 B - V V V 0 — O \ 7 Figure 3.28: Schematic of a Simple P I network. 3.5.1 Full C M O S P L A The R C calculations for the full C M O S P L A simulations were based on the structure of the full C M O S P L A generated by P L A m a t e and depicted in Figure 3.10. The schematic corresponding to this type of circuit is shown in Figure 3.29. The circuit contains tran-sistors, and R C type delay elements. 3.5.2 P s e u d o - N M O S P L A This is the type of structure generated by the design-rule-independent P L A generator. The schematic used for simulations is shown in Figure 3.30. 3.5.3 P s e u d o - N M O S P L A with Buffers Between Planes For the purposes of comparison wi th a simple pseudo-NMOS P L A , simulations were performed on a P L A circuit of the form of Figure 3.13. Chapter 3. PLA Generator 44 CO o 0 A A & Inputs Plerm Wire V V 3 a, o Outputs Figure 3.29: Schematic used for Simulations of Fu l l C M O S P L A s . Buffers were constructed of one min imum size inverter, followed by a larger driver inverter. Several values were used for the size of the driver buffer to determine the effects of larger sized buffers. The schematic used for simulations was identical to the schematic of Figure 3.30, wi th the addition of two inverters between the delay element representing the long wires in the A N D and O R planes. Chapter 3. PLA Generator 45 AND Plane OR Plane HL7Z>-Pterm Wire f 3 a fl 3 a .*-) 3 O a Input Output <b Figure 3.30: Schematic used for Simulations of Pseudo N M O S P L A s . 3.5.4 C o m p a r i s o n o f S i m u l a t i o n s The full C M O S P L A was demonstrated to be significantly slower than a pseudo-NMOS P L A , even for small arrays. The results of the S P I C E simulations is presented in Fig-ure 3.31. From the table, it is obvious that the cycle delay in a full C M O S P L A becomes totally unmanageable for larger P L A s , and the delay is significantly greater even for relatively small P L A s . Inserting buffers between planes is only useful when very large P L A s are being gen-erated. For smaller arrays, the effect of buffers is not significant, and the incurred area overhead is not justified. Chapter 3. PLA Generator P L A Cycle Dimensions Delay number number number Fu l l C M O S Pseudo-NMOS Pseudo-NMOS of of of wi th Buffers inputs outputs pterms (ns) (ns) (ns) 10 10 10 29.4 20.6 21.6 10 32 24 96.3 55.5 53.2 32 32 64 307.6 136.7 126.0 40 40 128 4100.0 320.7 286.4 Figure 3.31: Comparison of P L A Speeds. P L A P L A Dimensions Area number number number Fu l l C M O S Pseudo-NMOS Pseudo-NMOS of of of wi th Buffers inputs outputs pterms (mm2) (mm2) (mm2) 10 10 10 0.326 0.147 0.186 10 32 24 1.380 0.596 0.690 32 32 64 7.380 3.010 3.200 40 40 128 20.300 7.540 8.040 Figure 3.32: Comparison of P L A Areas. Chapter 4 A Gate Matr ix Generator Although P L A s provide a good starting point for a study of layout generation techniques, their practical applications are l imited due to inefficient use of area, long delay for large arrays, and the difficulty of handling multi-level and sequential logic structures. The gate matr ix structure [Lopez80] does not suffer from the problems listed above and can be generated using many of the same techniques described in the previous chap-ter. 4.1 Structure and Description of the Gate Matr ix A gate matr ix is a two-dimensional grid-based structure, like a P L A , and which can be used to implement multi-level logic functions. Columns of the grid are formed by placing transistors wi th common gate connections in a single column, with the gate wire running vertically over them. Routing is done vertically using short metal wires and short runs of diffusion in one type of routing column, and polysilicon in another. Horizontal routing is done using the primary routing layer. Because gate matr ix structures are subject to fairly strict transistor placement and routing constraints, they are a logical next step in design-rule-independent layout algo-rithms. Also , like P L A s they can be easily described in a simple input format. This input format maps directly to a layout, and thus it is possible to write a design-rule-independent layout generator similar to that for P L A s . In fact, the layout format lor a gate matrix is in many ways simpler than that for a P L A , since there are no special 47 Chapter 4. A Gate Matrix Generator 48 cases like those which occur during folding, where extra space needs to be inserted in the layout. Also , al l connections and transistors are explicitly specified in a gate matrix input file. 4.2 The Intermediate Format The gate matr ix is described in text form as a two-dimensional array of characters as shown in Figure 4.33. D S D S D S D S D S D S D S D S + + i - + i - + i - + i * i + i - + i - + - -i 1 1 1 1 1 * * 1 N 1 1 1 N 1 N * 1 * D = D i f f u s i o n column. N 1 1 1 1 1 I S = P o l y s i l i c o n column. * N * + - + * N * * 1 I 1 = P o l y s i l i c o n runner, : 1 1 1 1 1 1 I or N - d i f f u s i o n runner + + * N * + * N * + - * | i = P - d i f f u s i o n runner. 1 1 1 1 1 1 I : = Metal v e r t i c a l l y . * N N * + - * 1 1 I - = Metal h o r i z o n t a l l y . 1 1 1 1 1 1 I + = Crossover. + + - + - + - * 1 1 | * = contact. 1 1 1 1 1 1 | N = N-channel device. 1 1 * * 1 1 * + - P = P-channel device. 1 P 1 ! 1 1 1 I * P 1 + P I * 1 1 i P 1 * i P 1 + P 1 * j ! i 1 P 1 1 P I * l + 1 l P 1 + I 1 + 1 - l * 1 1 * 1 + I + I 1 + i -l + 1 * l P 1 + i 1 * I l 1 1 1 _ 1 + * 1 + 1 + + * 1 + 1 + + _ _ Figure 4.33: Input Format for the Gate M a t r i x Generator Each character i n the array represents a particular structure in the layout. Val id structures are N and P channel devices, metal, polysilicon, and diffusion routing, and Chapter 4. A Gate Matrix Generator 49 contacts between the various routing and device layers. In some cases the detailed struc-ture of an element must be partially inferred from elements surrounding i t . This is the case when one or more layers cross. A crossover point is indicated by a '+ ' character. To determine which layers are involved in the crossover, it is necessary to look at the ele-ments immediately above or below, and to the sides of the crossover element. Crossovers between metal and polysilicon, and between metal and diffusion are possible. A crossover of polysilicon over diffusion is a transistor gate, and is marked explicitly as ' N ' for an N-channel device or ' P ' for a P-channel device. Each column in a gate matr ix array can be classed as a diffusion column or as a polysilicon column. Diffusion columns may contain diffusion runners or metal routing wires. Polysi l icon columns are used to form the gates of the transistors, or as vertical routing columns. The type of a column must be explicitly known before it can be con-verted to a mask level layout, so each column includes a marker to indicate the type of that column. These are the ' S ' and ' D ' labels on the columns. The circuit of Figure 4.33 is a half adder circuit. The schematic for the half adder is shown i n Figure 4.34. A fully automated system for gate matr ix layout would include a system for creating the intermediate format from a netlist. This would allow the designer to enter a schematic using a schematic capture system, extract a netlist from the schematic, and generate the intermediate format for the gate matrix. A layout could then be generated in an arbitrary technology. The generation of the intermediate format is beyond the scope of this thesis, and is not considered in detail here. Chapter 4. A Gate Matrix Generator 50 c HI A B H E H E H E H E H E H E H E HI HI H E H E H E HE Figure 4.34: Half-adder circuit 4.2.1 Deficiencies in the Standard Format The gate matrix format described earlier can fully specify a gate matrix layout, but there are a number of omissions which should be recognized. All of the deficiencies described below are relatively minor, and can be eliminated by some slight extensions to the standard format. It is often desirable to design a layout so that the power and ground lines are of greater width than other wires in the layout. If this capability is desired in a gate matrix the format must be extended to allow nagging wires as being power rails. This can be done quite simply by adding a single character to the input file, such as a ' V to mark a Vdd line, or a 'G' to mark a ground line. It may even be desirable to use the full names: Chapter 4. A Gate Matrix Generator 51 ' V D D ' and ' G N D ' as the markers. Once the power and ground wires have been identified, then they can be generated with a width greater than the minimum width used for other wires. Whether or not branches of power and ground wires should also be of greater length could also be set as an option. There is no provision for the inclusion of either substrate contacts, or of split contacts in the standard gate matr ix format. Both of these type of contacts can be placed by a smart algorithm if the power and ground lines are marked as described above. Without this information, it is not possible to locate the power and ground wires and so substrate and split contacts cannot be placed. Alternatively, these contacts could be explicitly located by creating new symbols for them. The '<§•' symbol could be used to mark a substrate contact, and a could be used to mark a split contact. However, split contacts may require special consideration when doping regions are determined, possibly forcing the doping region away from a simple rectangular box. The problems in creating a split contact are discussed in Section 2.4 The layout of Figure 4.33 would be modified to that of Figure 4.35 when the extensions are added. 4.3 Issues i n P r o d u c i n g a G a t e M a t r i x The goal of minimizing layout area is one of the most important design constraints in the generation of a physical layout. Gate matrices are designed in such a way that transistors wi th common inputs lie i n the same column. Source and drain connections, along with other routing wires generally run horizontally. Since transistors are constrained to a par-ticular column of the array, the optimization problem becomes one of placing transistors so to minimize the number of rows in the layout. The gate matr ix layout, problem is then one of converting from a netlist to a near optimal intermediate description of the layout. One system for converting netlists to the gate matrix format is the Oct Tools approach Chapter 4. A Gate Matrix Generator 52 GND -D S D s D S D S D S D S D S D S + + i + 1 - + i - + i & i + i - + I + - -i 1 1 1 1 1 * * 1 N 1 1 1 N 1 N * 1 * D = Diffusion column. N  1 1 1 1 I S = Polysilicon column. * N * + - + * N * * 1 I 1 = Polysilicon runner, : 1 1 1 1 1 1 I or N-diffusion runner + + * N * + * N * + - * I ! = P-diffusion runner. 1 1 1 1 1 1 1 = Metal v e r t i c a l l y . * N N * + - * 1 1 1 - = Metal horizontally. 1 1 1 1 1 1 I + — Crossover. + + - + - + - * 1 1 I * = contact. 1 1 1 1 1 1 I N = N-channel device. 1 1 * * 1 1 * + - P = P-channel device. 1 P 1 ! 1 1 ! 1 I @ = Substrate contact. * P 1 + P 1 * 1 1 i P 1 * i P 1 + P 1 * 1 & = Split contact. i i 1 P 1 l P 1 * I + 1 * l P 1 + i l + 1 - l * 1 1 * + I + i 1 + 1 - 1 + 1 * 1 P 1 + i 1 * I 1 1 I 1 1 + & 1 + 1 + 1 + & 1 + 1 + 0 + - -Figure 4.35: Extended Input Format for the Gate Matrix Generator [Oct88]. The program gem calls a number of other tools which can read netlist or functional descriptions of circuits, minimize them, and produce output in a form which can be mapped to a gate matrix intermediate format. There are also a variety of graph-theoretic based approaches for the netlist to gate matrix problem as in [Wing85], [Deo87]. A dynamic netlist approach to the layout problem is taken in [Lakh89]. 4.4 Applications of the Gate Matrix A gate matrix is a more widely applicable architecture in the sense that it is possible to create general multi-level logic structures. Logic circuits implementable by a P L A are limited in complexity as a P L A allows only AND-OR logic. More complex circuits can Chapter 4. A Gate Matrix Generator 53 often be converted to this representation, but certain classes of circuits, notably those with feedback paths (sequential logic circuits), cannot be implemented with a P L A . Gate matrix layouts are significantly easier to construct than full custom layouts, even if they are produced manually. As a result, total layout time is reduced. In addition, there is no theoretical limit on the maximum size of chip that can be created using gate matrix methods. Researchers have used gate matrices to design significant portions of chips as large as 32 bit microprocessors [Kang83]. Also, since the intermediate format of a gate matrix is design rule independent, a minimal amount of work is required to convert a gate matrix based design to a new technology. 4.5 Tiling Generation vs. Mask Level Generation The gate matrix layout generator described in this thesis is a mask level generator, and does not build a layout using a library of layout cells. An alternative approach would be to implement the gate matrix layout generator as a tiling generator, an approach which has some advantages, but also a number of serious drawbacks. A tile-based gate matrix generator requires a library of primitive cells for each sup-ported technology, and those cells must be designed to handle every possible layout configuration. It is necessary to design row cells with a fixed height, and column cells with a fixed width. The fixed dimensions are necessary to allow cells to form correct connections between cells when they are butted together. The height and width of the cells are calculated based on worst case configurations, and must be able to contain the largest structure which may be present in the row or column. Spacing cells are needed to fill spaces between rows and columns, and to form connections between rows and columns. The widths and heights of spacing cells must be great enough to avoid any possible conflict between structures in adjacent rows or columns. The tiling method Chapter 4. A Gate Matrix Generator 54 will generate correct layouts, but where there are no conflicts, or large elements are not present in each row or column, then in general space will be wasted. A mask-level layout generator does not suffer from these problems, because all row and column dimensions and spacings can be calculated based on the structures which are actually present. The ability of a mask level generator to dynamically size elements of the layout means that it can generate more compact layouts in the general case. Another disadvantage of a tile based generator is that transistor sizes are fixed in the cells. If multiple transistor sizes are to be supported, a separate cell is needed for each supported size. Again, a mask level generator can size transistors on an individual basis. 4.6 Gate Matrix Layout Generator Using the origin-based layout database described in section 2.3.2, a design-rule indepen-dent gate matrix generator was implemented in the C language. 4.6.1 Preprocessing Step The initial step in the generation process is to read the input file, compress out extra spaces in the input array, and then calculate positions of each row and column. This step uses the spacing and dimension information from the technology file, and scans the input file for potential spacing conflicts between objects in adjacent rows and columns. When a conflict is detected, sufficient space is inserted in the array to eliminate the violation. At the end of this process, all major spacing and position values are known. As a side effect, the final size of the gate matrix layout is known before the layout is generated. A set of layer contact cells are also generated at this point. The cells are used to connect the various routing layers in the layout. Rules for contact cells are described in the . contact rule in the technology file. Chapter 4. A Gate Matrix Generator 55 Each row and column in the array contains the information described in Figure 4.36. Starting at position (x,y) = (0,0), the position of each row is calculated. Positions of successive rows are based on the width of each previous row, and the spacing between each adjacent row. Widths of rows are calculated so that the largest element which can occur in that row will fit within the boundaries of the row. Spacings are calculated based on possible conflicts between all combinations of elements which may be contained in adjacent rows. Variable Description width Width of the Row/Column position Relative Position of the Row/Column elements Elements contained in the Row/Column Figure 4.36: Structure of a Gate Matrix Row or Column Descriptor. 4.6^2 Row and Column Generation Rows and columns are not generated separately in the gate matrix generator. The input file is scanned sequentially, and each element is handled separately. The layout generation is not cell-based other than the previously mentioned contact cells. Objects are added directly to the database in their most primitive form, which is usually a polygon on a particular mask layer. The rows of the gate matrix are all scanned in turn. Each character in the input file corresponds to a particular action to be performed by the generator. Unlike the PLA generator which places a specific cell corresponding to the element, in the input, description, the gate matrix generator calculates the size of the needed element as it Chapter 4. A Gate Matrix Generator 56 occurs. Elements in the input file are converted to polygons on the appropriate layer. The dimensions of the polygon are determined by the minimum dimension of the layer and the spacing of adjacent rows and columns as calculated above. This step sometimes involves adding a wire which stretches over several rows or columns. There are two cases where a wire may span a number of rows or columns. The first case occurs when several wire segments lie in adjacent elements in the input file. The generator may combine these elements into a single wire, rather than representing them as a series of smaller segments. The second case occurs when a connection must be inferred. This situation can result when two adjacent transistors have a merged source or drain. The merged region may not explicitly appear in the input file, and the connection must be inferred. An example of this situation appears in the example input file in Figure 4.33. An operation like this is not difficult, because the coordinates of each row/column and the spacing between adjacent rows/columns are already calculated. The only potential difficulty is that the width of a row or column is calculated based on the size of the largest component which can be placed in the row or column. In those cases where a smaller object is to be placed in the row/column, connections to that element require extensions of the element to the boundaries of the row/column. Contact cells are inserted into the database as required, and may require additional connecting polygons to connect the contact cell with adjacent wire segments. The con-necting polygons may overlap the cell slightly if the connection layer in the contact does not extend to the border of the contact cell. The gate matrix generator does not use a large set of primitive cells, but adds polygons into the layout database as they are needed. This makes the generation less complex in some ways, since there is no need to decide which of many cells must be added to the database at a given point, it is just necessary to add a polygon whose size is easily calculated. Chapter 4. A Gate Matrix Generator 57 4.6.3 Substrate and Doping Regions The substrate regions for different transistor types are constructed in two steps. The first step runs concurrently with the row and column generation. As each element containing device-well geometry is added to the database, a region describing the bounding box of the substrate layer is updated based on the type of the device-well. In other words, if a P channel device is added to the design, the P-channel substrate region is extended if necessary to enclose the new transistor. Under certain circumstances, it will not be clear to which substrate region a device-well polygon belongs. One instance where this occurs is when a metal to device-well contact cell is added. These contact cells are described using the same symbol for N-channel and P-channel device-well connections. In this case, it is necessary to trace the device-well connection to the point where the diffusion type is non-ambiguous, such as a transistor gate. After the row and column generation step, the substrate regions are known, and the substrates can be generated. This involves the information contained in the substrate field in the .device sections of the technology file. Generation of the substrate regions involves scanning each layer in the substrate for a device, initializing them to the size of the substrate region, then expanding each required layer based on enclosure rules with each other layer in the substrate, with transistor gates, and with device-well regions. The substrate region is created as a S Y M B O L , and placed into the database over the corresponding substrate region. Chapter 4. A Gate Matrix Generator 58 4.6.4 Output The final design can be printed to a C I F file or a G D S II file. The physical layout of Figure 4.34 using the C M 0 S 3 process is shown in Figure 4.37. Layouts were also generated in the S C M O S and the I S O C M O S processes. A full design rule check was run on the C M O S 3 designs using a comprehensive design-rule set. The S C M O S and I S O C M O S designs were checked by hand and determined to be correct. A B C S I"  Figure 4.37: Gate M a t r i x Layout of Half-Adder It is instructive to compare the layout generated by the gate matr ix method with layouts created using other methods. In Figure 4.38 layouts generated by hand (full Chapter 4. A Gate Matrix Generator 59 custom), by a typical standard cell method, and by the gate matrix method are compared. It should be noted that the full custom layout was created by a relatively inexperienced designer, and that in general a full custom design should be more area efficient than a gate matrix design. However, for inexperienced designers, and when standard cells are an alternative, the gate matrix is clearly a reasonable approach. Chapter 4. A Gate Matrix Generator 60 S t a n d a r d Cel l s A B C Gate M a t r i x Figure 4.38: Comparison of Layouts Generated by Various Methods. Chapter 5 Conclusions The use of layout generators greatly speeds up design time i n a IC design project, avoiding the need for designers to spend large amounts of time on the tedious task of physical lay-out. The design rule independent nature of the generators simplify the task of converting a layout to a new technology. In order to generate design-rule independent layouts at the mask-level, a relatively simple technology description is required. The technology description must contain infor-mation which specifies the functions of the major layers defined for the technology, defines various design rules for the technology, and indicates how valid devices are constructed. Two methods, absolute coordinate based and relative coordinate based systems were compared wi th respect to mask-level layout generation. A P L A generator was imple-mented based on the coordinate free system implemented by the Coordinate Free Lap design package. A system based on absolute coordinates was implemented and used in the design of a gate matrix layout generator. The P L A generator used a system of subcells to bui ld a P L A row by row, and column by column, placing the cells relative to each other. The P L A generator was written in about 7,800 lines of C code, and makes use of the C F L subroutine package. The gate matr ix generator, in contrast, places blocks at the mask level into an internal database using absolute coordinates. A layout generated at the mask level is more area efficient than one generated by a t i l ing generator, because the mask level generator can size rows and columns, and calculate row and column separations on an individual basis. 61 Chapter 5. Conclusions 62 A ti l ing generator must use fixed sized rows and columns, with fixed separations in order to be able to handle all possible configurations. The gate matrix generator program was written wi th about 3,200 lines of C code, while the layout database support routines required over 7,600 lines of code. In comparing the two layout generation techniques, it has been determined that an absolute coordinate or origin-based approach is more suitable to a mask-level generator. It is simpler to construct objects containing many overlapping layers by placing objects at known, absolute locations than it is to calculate offset position relative to the borders of a compound object. The layout generators were tested using three different technologies: Northern Tele-com's C M O S 3 process, which was the primary technology, the Mosis Scalable C M O S process ( S C M O S ) , and a version of the I S O C M O S process used by Microte l Pacific Re-search. In each case, correct circuits were generated. Since each of these technologies is a 3 micron process, there is l i t t le difference i n appearance i n the layouts generated, so no size comparisons were done between the three technologies. 5.1 F u t u r e W o r k It would be useful to convert the P L A generator to the absolute coordinate layout system, since that method has proven more applicable to mask-level layout generation. More flexibility should be provided in terms of pullup and pulldown sizing. The gate matr ix generator would benefit from more complex row and column spacing and width calculations, to eliminate unneccesary space in the matrix. In addition, a netlist to gate matr ix program should be developed to make fuller use of the power of the layout generator. References [Beck86] [VLSI86] [MeCo80] [Rubin87] [Hollis87] [Sangio83] [Jinks85] [Steb83] W . Beckett, " C F L Reference manual" VLSI Design Tools Reference Manual, N W Laboratory for Integrated Systems, Dept. of Computer Science, University of Washington, Feb. 1987. W . S. Scott, R . N . Mayo , G . H . Hamachi and J . K . Ousterhout, ed 1986 VLSI Tools: Still More Works by the Original Artists., Computer Science Divis ion, University of California, Berkeley, Dec. 1985 C . A . Mead and L . A . Conway, Introduction to VLSI Systems, Reading, M A : Addison-Wesley, 1980. S. Rub in , Computer Aids for VLSI Design Reading, M A : Addison-Wesley, 1987. E . E . Holl is , Design of VLSI Gate Array ICs Englewood Cliffs, N J : Prentice-Hall , Inc., 1987. G . De Michel i and A . Sangiovanni-Vincentelli " P L E A S U R E : A Com-puter Program For Simple /Mul t ip le Constrained/Unconstrained Fold-ing of Proammable Logic Arrays" 20th Design Automation Conference, 1983. B . W . Jinks, W . S. Snyder and D . L . Pulfrey, "The Algori thmic Gener-ation of R O M Macrocells," Proc. 2nd. Int. Symposium on VLSI Tech-nology, Systems and Applications, Taiwan, 1985 pp. 190-193. M . W . Stebnisky, M . J . McGis s in , J . C Werbickas, R . N . Putatunda and A . Feller " A P S S : A n Automatic P L A Synthesis System" 20th Design Automation Conference, 1983. 63 References 64 [DeMan83] H . De M a n , L . Reynders, M . Bartholomeus and J . Cornelissen " P L A S C O : A Silicon Compiler for n M O S and C M O S P L A s " VLSI '83, 1983. [Liu83] W . L i u "Bounds on the Saved Area Rat io Due to P L A Folding" 20th Design Automation Conference, 1983. [Chuq83] S. Chuquil lanqui "Internal Connection Problem in Large Optimized P L A s " 20th Design Automation Conference, 1983. [Lurs88] C . Lursinsap and D . D . Gajski " A Technique for Pu l l -Up Transistor Folding" IEEE Transactions on CAD, A u g , 1988. [Leask87] J . Leask, P. Gaboury and M . I . Elmasry, " P L A m a t e : A C M O S P L A / F S M Compiler User's Guide" [Lopez80] A . D . Lopez, " A Dense Gate M a t r i x Layout Method for M O S V L S I " IEEE Journal of Solid-State Circuits, August , 1980. [Kang83] S. M . Kang , R . H . Krambeck, H . S. Law and A . D . Lopez, "Gate M a t r i x Layout of Random Control Logic in a 32-bit C M O S C P U Chip Adapt-able to Evolv ing Logic Design" IEEE Transactions on CAD, Jan, 1983. [Oct88] Rick Spicklemier, ed "Oct Tools Distr ibution 2.1" Electronics Research Laboratory, University of California, Berkeley, M a r , 1988. [Wing85] 0 . W i n g , S. Huang and R . Wang, "Gate Ma t r i x Layout" IEEE Trans-actions on CAD, J u l , 1985. [Deo87] N . Deo, M . S. Krishnamoorthy and M . A . Langston, "Exact and A p -proximate Solutions for the Gate M a t r i x Layout Problem" IEEE Trans-actions on CAD, Jan, 1987. [Lakh89] G . Lakhani and S. Ra.thinaswa.mi, "Par t i t ion Based Heuristics lor Gate M a t r i x Layout," 1989 IEEE International Symposium on Circuits and Systems, Jan, 1987. Appendix A Technology File Format The technology file format may contain a number of different commands. Commands are a single text string prefixed by a period. Following is the syntax for each command in the technology file: .tech .layer •device .contact .separation techname ; layername shortname shortname cifname cifname ] devicename type type } overhang integer] width integer ] length integer ] layers layerJist : ] substrate layerJist layertype layertype layerl ] contact-layer ] layer2 ] layerl ] layer2 ] separation ] 65 Appendix A. Technology File Format 66 •enclosure [ inner layername ] [ outer layername ] [ value integer ] Appendix A. Technology File Format As an example, here is the technology file for C M 0 S 3 /* * Technology f i l e for CM0S3. */ .tech cmos3; /* * Layer declarations: */ layer contact shortname cc cifname CC function CONTACT gds# 9 gdstype 0 dimension 5 /* Layer name. */ /* short name. */ /* CIF name. */ /* function. */ /* GDS II layer no. */ /* GDS II layer type. */ /* min. dimension. */ .layer via shortname v cifname CV gds# 18 gdstype 0 function CONTACT dimension 5 layer polysilicon shortname poly cifname CP gds# 12 gdstype 0 function GATE dimension 5 .layer shortname devwell d Appendix A. Technology File Format cifname gds# gdstype f u n c t i o n dimension .layer shortname cifname f u n c t i o n dimension .layer shortname cifname f u n c t i o n dimension l a y e r shortname cifname gds# gdstype f u n c t i o n dimension .layer shortname cifname gds# gdstype f u n c t i o n dimension .layer shortname cifname CF 2 0 CHANNEL 5 devwelldd d CF CHANNEL_DD 5 devwellds d CF CHANNEL_DS 5 p-plus PP CPP 8 0 DOPING 5 n-plus np CNP 7 0 DOPING 5 metall ml CM Appendix A. Technology File Format gds# = 10 gdstype = 0 function = ROUTING1 dimension = 5 layer shortname cifname gds# gdstype function dimension metal2 m2 CM2 19 0 R0UTING2 5 layer p-well shortname pw cifname CPW gds# 1 gdstype 0 function WELL dimension 10 layer p-guard shortname pg cifname CPG gds# 3 gdstype 0 function GUARD dimension 10 .layer n-well shortname ng cifname CNG gds# 4 gdstype 0 function GUARD dimension 10 Appendix A. Technology File Format 70 /* * Dev i ce D e c l a r a t i o n s : */ . d e v i c e n-channel t ype PULL-DOWN overhang 5 w i d t h 5 l e n g t h 5 l a y e r s d e v w e l l , p o l y s i l i c o n , p - w e l l , p-guard, n-we l l : s u b s t r a t e c o n t a c t , d e v w e l l , m e t a l l , p-p lu s , n-plus : » . d e v i c e p-channel t ype PULL-UP overhang 5 w i d t h 5 l e n g t h 5 s u b s t r a t e c o n t a c t , m e t a l l , devwe l l : l a y e r s d e v w e l l , p o l y s i l i c o n , p-p lu s , n-plus : /* * Contact D e c l a r a t i o n s : */ con tac t GATE R0UTING1 p o l y s i l i c o n con ta c t m e t a l l . c on t a c t R0UTING1 DIFFUSION m e t a l l con tac t d e v w e l l ; . c on t a c t R0UTING2 R0UTING1 meta l2 v i a m e t a l l Appendix A. Technology File Format /* * Separations. */ .separation polysilicon devwell 4; separation polysilicon poly 5; separation metall metall 5; separation metal2 metal2 5; separation devwell devwell 7; separation devwell devwelldd 8; separation devwell devwellds 9; separation devwelldd devwellds 14 /* * Enclosures. */ /* contact cuts: */ .enclosure of contact by metall 2 ; .enclosure by devwell of contact 2; enclosure inner contact outer polysilicon value 2 enclosure inner via outer metall value 3 enclosure inner v i a outer metal2 value 3 /* N-channel transistors: */ Appendix A. Technology File Format enclosure inner gate outer p-well value 7 enclosure inner devwell outer p-well value 3 enclosure inner p-well outer p-guard value 5 .enclosure inner p-guard outer n-well value 3 /* P-channel devices: */ .enclosure inner devwell outer p-plus value 4 .enclosure inner devwell outer n-plus value 4 . end 


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