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Design, implementation and testing of a flexible, intelligent modem architecture for power line communications Buternowsky, Barry 1992

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Design, Implementation and Testing ofa Flexible, Intelligent Modem Architecturefor Power Line CommunicationsbyBarry ButernowskyB. Sc. Computer Eng., University of Manitoba, 1989.A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinTHE FACULTY OF GRADUATE STUDIESDEPARTMENT OF ELECTRICAL ENGINEERINGWe accept this thesis as conformingto the required standardTHE UNIVERSITY OF BRITISH COLUMBIAJanuary 1992© Barry Buternowsky, 1992.In presenting this thesis in partial fulfilment of the requirements for an advanceddegree at the University of British Columbia, I agree that the Library shall make itfreely available for reference and study. I further agree that permission for extensivecopying of this thesis for scholarly purposes may be granted by the head of mydepartment or by his or her representatives. It is understood that copying orpublication of this thesis for financial gain shall not be allowed without my writtenpermission.Department of Electrical EngineeringThe University of British ColumbiaVancouver, CanadaDateDE-6 (2/88)AbstractIntrabuilding electric power distribution lines provide easy access and universalcoverage for data communications. However, power line communication channels exhibitunpredictable levels of impedance, attenuation and noise. To enable effectivecommunications requires appropriate modulation schemes and communication protocols.This thesis describes the design, implementation and testing of a modular, flexible,intelligent modem architecture, based on binary phase-shift keying (BPSK). The modemoperates at user selectable baud rates of 2.4, 4.8, 9.6 and 19.2 kbps. Most of the design isdigital, to facilitate eventual implementation using VLSI. A microcontroller resident on themodem enables judicious allocation of data link layer functions between modem and hostmicrocomputer. Data link functions performed by the microcontroller include byte andpacket synchronization, and control of host-modem communications. The overall data linkprotocol design results in a flexible, user specified packet format and length, whichaccommodates to different data rates. The modem architecture is designed for use withvarious medium access protocols including CSMA, polling or token passing. Addition offorward error correction capability in the form of on-board hardware is also feasible.Evaluation of the modem architecture was performed in a four-storey industrialbuilding which contains good, fair and poor quality communication links. Results forsame phase and cross phase transmissions were collected and analyzed for two differenttest environments: (1) short length links of approximately 30 meters within the same roomlocation; and, (2) moderate to very long links (greater than 60 meters) among differentfloors. Results from tests (1) indicate that same phase transmission is in generaladvantageous over cross phase transmission. This advantage for BERs less than 10 -3 fortransmission at 19.2 kbps can be large as 27 dBmV. Evaluation of results from tests (2)indicate that power line channel communication characteristics are directly related to thechannel's length. The BER was found to be in a range from 10 -1 to 10 -3 for transmissionat 19.2 kbps . Comparison of channel throughput for continuous one-way transmissionwithout forward error correction indicates 2.4 kbps would be appropriate for long distance,4.8 and 9.6 kbps for medium distances, and 19.2 kbps for relatively short distances.iiTable of ContentspageAbstract^List of Figures^List of Tables.Acknowledgements ^ ^ii ^vi ^ix1 Introduction    11.1 MOTIVATION^ 11.2 BACKGROUND 11.3 OVERALL MODEM DESIGN CONSIDERATIONS^ 31.4 OUTLINE OF THESIS^ 42 Power Line Channels^ 62.1 ELECTRICAL POWER DISTRIBUTION^ 62.1.1^Power Systems Topology 62.1.2^Building Wiring Plans 62.2 ATTENUATION^ 82.2.1^Attenuation in Industrial Buildings^ 82.2.2^Attenuation in Residential Buildings 112.3 NOISE 132.4 SIGNAL FADING^ 162.5 POWER LINE LOADING^ 163 Hardware Architecture—Design and Implementation^ 193.1 OVERVIEW OF MODEM HARDWARE ARCHITECTURE ^ 193.2 TRANSMITTER AND RECEIVER SUPPORT COMPONENTS 193.2.1^Power Supply^ 193.2.2^The Clock Generator 203.2.3^A Description of the Microcontroller Control Pins^ 203.2.4 The Host/ Modem Interface^ 223.3 MODEM TRANSMITTER HARDWARE 223.3.1^BPSK Modulator^ 223.3.2^The Transmit Low Pass Filter^ 243.3.3^The Power Amplifier 25iii45Table of Contents (Contd)3.4 MODEM RECEIVER HARDWARE^3.4.1^Line Coupling Network3.4.2^Receive Band Pass Filter3.4.3^The Costas Loop^3.4.4^Bit Synchronization Circuit^3.4.5^Integrate-and-Dump Filter and Host Interface^Firmware Design and Implementation ^4.1 OVERVIEW OF MODEM FIRMWARE ORGANIZATION^4.2 MODEM INITIALIZATION MODULE^4.3 MODEM TRANSMIT MODULE4.3.1^Transmitted Packet Format: Preamble and Data^4.3.2 Host-Modem Communication^4.3.3 XON/XOFF Host-Modem Flow Control^4.3.4 Synchronous Handshaking for AsynchronousCommunication^4.4 MODEM RECEIVE MODULE^4.4.1^Data Link Layer4.4.2^Discussion of Data Link Layer Parameters^4.4.3^Carrier Detection^Test Results in Different Environments5.1 DISCUSSION OF TEST PARAMETERS^5.2 TEST RESULTS UNDER WHITE NOISE CONDITIONS^5.3 TEST ENVIRONMENT AND PROCEDURE^5.4 SAME PHASE AND CROSS PHASE TESTS ON LAB SYSTEM ...5.5 TESTS ON GENERAL IN-BUILDING ELECTRICALDISTRIBUTION SYSTEM^5.5.1^Bit^Error^Rate5.5.2^Block Error Rate5.5.3^Percent of Lost Packets5.5.4 Summary5.6 TESTS FOR TRANSMISSIONS FROM LAB TO^GENERAL SYSTEM^5.6.1^Bit^Error^Rate5.6.2^Block Error Rate5.6.3^Percent of Lost Packets^5.6.4^Error-free^Throughput5.6.5 Summary 36page2525262632353638383940424344454750.54545758606870707171727272737374ivTable of Contents (Contd)^ page6 Conclusions   ^756.1 CONCLUDING REMARKS^ 756.2 SUGGESTIONS FOR FURTHER WORK^ 76References  78A Hardware Schematics^ 83B Firmware Listing 94vList of FigurespageFigure 2.1 Residential electrical power distribution^ 7Figure 2.2 Commercial/Industrial three-phase electrical power distribution ^ 9Figure 2.3 Attenuation during the work day in an industrial building [1]^ 11Figure 2.4 Attenuation in an industrial building at night [1] ^ 11Figure 2.5 Attenuation for residential in-building power linewith resistive load [1]^ 12Figure 2.6 Attenuation across phases in residential power lines [1] ^ 13Figure 2.7 Residential power line bandwidth [1]^ 14Figure 2.8 Distribution network load profile during one day [50]^ 17Figure 2.9 Distribution network load profile during one week [50] 18Figure 3.1 Output of shift register 74HCT164 in modulator circuit^ 23Figure 3.2 Synthesized sinusoidal carrier^ 24Figure 3.3 Second order butterworth LPF 24Figure 3.4 Second Order Butterworth Band Pass Filter^ 26Figure 3.5 BPSK Costas loop demodulator^ 28Figure 3.6 Digital Costas loop^ 28Figure 3.7 Spectrum of square wave c(t) 29Figure 3.8 Block diagram of loop filter chip^ 30Figure 3.9 Inserted and deleted pulses of the loop filter chip^ 30Figure 3.10 BER vs loop filter bandwidth 31Figure 3.11 Percent lost packets vs loop filter bandwidth 31Figure 3.12 Bit synchronization circuit^ 33Figure 3.13 Non-synchronized bit stream 33Figure 3.14 Perfectly synchronized bit stream 34Figure 3.15 Bit Sync waveforms for different up/down values^ 34Figure 3.16 Noisy bit stream^ 34Figure 3.17 Integrate and dump matched filter^ 35Figure 4.1 Overall view of modem firmware 37viList of Figures (Contd)^ pageFigure 4.2 OSI reference model 37Figure 4.3 Commands sent to the modem by the host duringinitialization^ 38Figure 4.4 Transmit module data link layer functions^ 39Figure 4.5 Transmit module physical layer functions 39Figure 4.6 Transmit module block diagram^ 41Figure 4.7 Transmitted packet format 41Figure 4.8 Circular transmit buffer 42Figure 4.9 Receive module physical layer functions^ 44Figure 4.10 Receive module data link layer functions 45Figure 4.11 Data link layer flow chart 46Figure 4.12 Packet Sent to Host ^0 ^ 47Figure 4.13 Performance of data link layer 48Figure 4.14 Correlation of SYNC word 49Figure 4.15 High and low confidence bits^ 51Figure 4.16 Time taken for new _confidence to fall belowconfidence threshold^ 53Figure 4.17 Bits to terminate lock state for cur _conf of 0, 1, & 2^ 53Figure 5.1 Packet format for Bit Error Rate Tester 54Figure 5.2 Noisy and quiet periods on a channel^ 56Figure 5.3 Modem performance in white noise: BER and BLKER^ 58Figure 5.4 BLKER and percent lost packets vs BER for white noise 58Figure 5.5 Three phases of a power line^ 59Figure 5.6 BER for lab system^ 61Figure 5.7 BLKER for lab system 62Figure 5.8 BER vs BLKER for lab system^ 63Figure 5.9 Percent lost packets for lab system 64Figure 5.10 Variation in BER as plotter location is varied^ 65Figure 5.11 Frequency spectrum of output of bandpass filter^ 66Figure 5.12 Waveforms of output of demodulator and bandpass filter^ 67Figure 5.13 BER and BLKER vs time for x to y channel at 63 dBmV 68viiList of Figures (Contd)^ pageElectrical engineering building^ 69BER for 70 dBmV data signal on General System^ 70BLKER for 70 dBmV data signal on General System 71Percent lost packets for 70 dBmV data signal on general system ^ 71BER for 70 dBmV data signal on Lab to General System^ 72BLKER for 70 dBmV data signal on Lab to General System^ 73Percent lost packets for 70 dBmV data signal on labto general system^ 73Error-free throughput for 70 dBmV data signal on labto general system 74Figure 5.14Figure 5.15Figure 5.16Figure 5.17Figure 5.18Figure 5.19Figure 5.20Figure 5.21vulList of TablespageTable 2.1 Error free lengths for 38.4 kbps, industrial building^14Table 2.2 Error free lengths for 19.2 kbps, industrial building 14Table 2.3 Error free lengths for 4.8 and 19.2 kbps, industrial building^14Table 2.4 Summary of Tables 2.1-2.3 with single bit errors^ 15Table 3.1 Shift register waveforms: unweighted and weighted 23Table 4.1 Mean time between false preambles^ 50Table 4.2 new confidence values for different current confidence values^52Table 5.1 Sub-buses in General and Lab Systems 69Table 5.2 Phases of Power Lines at Test Locations^ 69ixAcknowledgementsI would like to express my sincere gratitude to my supervisor Dr. R. W. Donaldsonfor his support and guidance during the course of this thesis.A special thank-you is extended to my family for their endless supply of love andencouragement throughout this thesis. I would also like to thank Mr. William Cheung formaking available the software tools that were used during this research.Partial funding for this thesis was provided by the Natural Sciences andEngineering Council of Canada in the form of an academic scholarship for which I amgrateful.1 Introduction1 Introduction1.1 MOTIVATIONThe use of intrabuilding communications involving computers and other terminalequipment has increased rapidly over the past few years. The need for interofficecommunications, local area networks, security control, and energy use management inbuildings is creating a demand for faster, cheaper, and more reliable systems andservices. Conventional wireline communications media including twisted pair andcoaxial cable are suitable for carrying baseband and broadband communications. Forwide area networks, media include fibre optic, microwave, and satellite links whichsupport broadband communications [8].The driving cost, in networking, after computer and other terminal equipment, isthe installation of cables [8]. These installation costs can be substantial even forrelatively simple networks. Although a network may have been functioning for anextended period of time, as it expands so do the expenses of installing new lines.Power line communication takes advantage of existing copper lines within thebuilding walls. A natural interface between power lines and the communications deviceexists in the form of a standard wall plug. There are no extra costs for expanding thenetwork, save the cost of additional modem and terminal devices. In addition, thephysical location of terminals can be changed at will, thus creating a network which isflexible in response to terminal locations and user needs.Power lines are not designed for use as communication channels. They exhibitunpredictable and varying levels of impedance, noise, and attenuation. Theseimpairments must be overcome to enable effective communications.1.2 BACKGROUNDElectric power distribution lines have been used by the power industry fordistribution automation including remote meter reading, load management, and other11 Introductionapplications [6]. Because of various degradative factors including large amounts of noisegenerated by electrical equipment, most of these systems have data rates below 100 bps.Recent developments in local area networks (LANs) and independentmicroprocessor controlled equipment enhances the benefits of using power lines as acommunication medium for local networking inside buildings. By communicating overpower lines one has potentially access to a network which encompasses an entirebuilding. With sufficient bandwidth, transmission of digital voice as well as data isfeasible. Automated home control is one possibility. Previous home bus systems havebeen developed [37-43] which use dedicated twisted pair and coaxial cable forcommunicating at 9600 bps. The features provided by the home bus can be extended toindustrial buildings which, because of their considerable size, are excellent candidates forpower line communications.Several commercial intrabuilding power line communication systems have beendeveloped during the last few years. These include modems from Signetics, NONWIRE,BSR, ExpertNet, and National Semiconductor [6,12]. These products have data ratesranging from 120 bps to 1.2 kbps and operate at carrier frequencies from 30 kHz to 150kHz. The modulation schemes include amplitude shift keying and noncoherent frequencyshift keying. These schemes are simple to implement, and inexpensive to manufacture.However, their performance capabilities are severely limited. In addition to thesecommercial products, several research systems have been reported. A pseudonoisespread spectrum modem that operated at 60 bps used the AC crossings of the 60 Hzpower signal for synchronization [4]. A spread spectrum minimum shift keyed modemwith fixed maximum baud rate of 19.2 kbps was documented in [1].Channel impairments severely limit the data transmission speed and accuracyachievable on power line networks. At low data rates, power line impulse noise isrelatively small, energy per data bit is high, and reliable performance is achievable atrelatively low transmitter power levels. As the transmitted bit period decreases (whentransmission speed increases), the detrimental effects of impulse noise and fadingincrease. At moderate to high transmission speeds (9.6 kbps and higher), impulse noisebecomes the dominant factor, on some links, in determining the performance of thecommunication channel.Increasing interest in powerline communications as a cost effective alternative forLAN implementation motivates extensive testing of possible future LAN sites. This21 Introductiontesting will provide valuable information concerning the overall potential of the site, andwill also provide important information which must be considered in the design of thenetwork. This knowledge is important if future commercial developments are to berealized.A power line LAN must be commercially competitive with other network media.Dedicated wireline or optical communication networks have a very high transmissioncapacity and reliability. It is therefore necessary that the cost of power line LANfacilities be kept as low as possible, while maintaining adequate reliability andthroughput, and low message delay. Although several modems have been developed andtested, there remains an absence of a low-cost, reliable modem architecture andassociated data link control protocol with adequate performance capabilities for medium-speed, in-building applications.In this thesis, a unique microprocessor-based power line modem was developedand tested. This modem uses BPSK (binary phase shift keying) modulation which issuperior to DPSK (differential PSK) by 1 dB in additive white Gaussian noise, and issuperior to coherent OOK (On-Off shift keying) and coherent FSK (frequency shiftkeying) by 3 dB [10]. A data link layer protocol which resides on the modem performsbyte and packet synchronization. Optimization of channel throughput is providedthrough variability of packet size and baud transmission rate. Baud rates from 2.4 kbps to19.2 kbps are dynamically selected through software. An industrial building was selectedas the test site. Performance results were recorded for short and long transmissiondistances and for good and for very poor quality channels.1.3 OVERALL MODEM DESIGN CONSIDERATIONSFigure A.1 in Appendix A is a block diagram of the modem design. Shown in thisschematic are the signals passed to each modem component and the clearinterdependence among the components. An important block is the control circuitrywhich contains a microcontroller. The microcontroller's program is stored in an externalEPROM which allows the microcontroller to supervise all aspects of the modemfunctioning. In part, the modem's maximum baud rate is limited by instruction executionspeed. The other overriding restriction in developing high speed modems is hardwarecomplexity which if allowed to proceed unchecked would produce an impractically costlyproduct.3I IntroductionThe design philosophy of microcontroller-based modems is derived from severalmotivations. These include flexibility, modem intelligence, and chip count (or cost). Amicrocontroller-based modem's functionality often can be modified by simply rewritingthe microcontroller's firmware. Functions can be added, operational problems resolved,and options expanded with minimal modem service time. As processors become smallerand faster, microcontroller-based systems become smarter. Tasks otherwise performed inhost computers are implemented within the modem itself. Because the microcontrollerreplaces many elementary chips, the overall chip count and physical size are reduced. Asmaller number of chips generally results in a less expensive and more reliable system.Some subsystems of the modem developed in this thesis were tested earlier, inpreliminary form at 9.6 kbps transmission rate [21]. These subsystems include someparts of the modulator, demodulator, and carrier detector. The modem described herein,goes well beyond earlier work, and is thoroughly tested on various links in a harshoperating environment. Several changes in design philosophy and implementation haveenabled an increase in the transmission rate to 19.2 kbps. Appropriate data link controlfunctions are also developed, judiciously partitioned for implementation on the modem orwithin the PC host.The purpose of this thesis is to design, implement and evaluate a cost-effectivepower line modem which operates with a high degree of reliability under variable channelconditions, at data rates up to 19.2 kbps. Design simplicity is emphasized. Generally,overly complex schemes are more expensive and less reliable than simpler schemes.Where possible, techniques which lend themselves to all-digital VLSI implementation, orfailing that, mixed digital/analog application specific integrated circuits — ASICs, areused. Two very important design criteria are high data rates and baud rate selectivity.The modem must have the ability to change baud rates as needed. Modem architectureshould be modular and amenable to the future addition of on-board medium accessprotocols including CSMA, polling, or both. It is useful to accommodate user-definedpacket format and length as dictated by application and channel quality. Testing of themodem on a wide variety of actual power line communication channels is essential.1.4 OUTLINE OF THESISThe remainder of this thesis comprises five additional chapters and twoappendices. Chapter 2 contains a description of the power line communications channel.This description includes a summary of some previous work by others and provides the41 Introductionnecessary background for understanding power line channel impairments. Signalattenuation and noise characteristics for both industrial and residential buildings areanalyzed. These are the two major channel impairments.Chapter 3 describes the overall modem hardware design approach and architectureas well as hardware circuitry within the modem. This description includes analysisconcerning choice of parameters for low pass and band pass filters, and the design of adigitally realized modulator and demodulator. Design and analysis of an all-digitalsymbol synchronization means is also included. Coupling circuitry to enable interfacingof the modem to the power line is described.Chapter 4 describes the design and implementation of the data link layer functionsstored in firmware and executed on the modem's microcontroller. The data link layerperforms byte and packet synchronization. The firmware also includes a user interfacewhich allows various parameters such as modem baud rate to be changed dynamically.The distribution of data link functions between the modem and the host is designed toenable maximum application flexibility.Chapter 5 describes the results from numerous performance tests based onmeasurements within an industrial building. These tests determine operating parametersfor the power line modem as packets are sent from a transmitting host (IBM-PCcompatible 386) to a receiving host. Several different parameters are tabulated includingbit error rate, block error rate, percent of lost packets, and throughput. The tests wereperformed over different times of the day, and different powerline communicationchannels, at various transmitter power levels.Chapter 6 contains a summary of the thesis work and performance results, andprovides suggestions for further research.The appendices provide detailed modem circuitry and firmware listings.52 Power Line Channels2 Power Line ChannelsIn this chapter, details of the dominant properties of power lines — attenuation,noise levels, and fading — are described for industrial and residential sites. Theinformation concerning these two factors is derived from various sources including [1] and[6]. In order to understand the characteristics and behavior of intrabuilding power linecommunication, it is necessary to first understand the way electrical power is distributedwithin a building.2.1 ELECTRICAL POWER DISTRIBUTION2.1.1 Power Systems TopologyThree phase electrical power is distributed from generating plants to consumersover large and complex networks. High voltage transmission lines transmit power fromgenerating plants to electrical substations. The transmission lines vary in length from tensto hundreds of kilometers. Next, a distribution network delivers electrical power fromsubstations to a number of distribution transformers [4]. The distribution network varies insize as well. It is small for villages and extensive for metropolitan areas. The secondary(load) side of a distribution transformer connects to the circuit panels in a building. Asingle distribution transformer may provide electrical power for many buildings inresidential districts, or for single buildings in industrial sectors.2.1.2 Building Wiring PlansIn residential housing or apartment units, the secondary side of the distributiontransformer delivers split-single-phase power to circuit panels by two 120V (180° out ofphase) 60 Hz lines and a neutral conductor as shown in Figure 2.1. The neutral conductoris normally connected to the grounded circuit panel. Electrical power is distributedthroughout the building on general purpose branch circuits which usually consist of twistedpair copper wiring. One wire of the twisted pair is connected to a 120V line, and the otheris connected to neutral. Small loads are interfaced to the branch circuits using standard wallplug-in receptacles.625 Kv POWER LINEDISTRIBUTIONTRANSFORMERTO RESIDENCE B120V litNEUTRAL °120V L20RESIDENCE Ai•-ME TER . J ...r.....■-SERVICE  PANELSWITCHES1 ■ r• 4II ■ • wLOADSWATER HEATER^f\Ar---BRANCH CIRCUITSr11IrLCIRCUITBREAKERS010.9.00 Q.,2 Power Line ChannelsFigure 2.1 Residential electrical power distribution72 Power Line ChannelsElectrical power is supplied to large appliances on special individual dedicatedbranches. Washing machines, refrigerators, dishwashers, and freezers all have their own120V branch circuit. Appliances with large heating elements such as electric ranges, waterheaters and clothes dryers usually require a 240V branch circuit. These appliances areconnected to both 120V lines, and the neutral. The heating element within these appliancesis connected directly across the two 120V lines while the motor (in the clothes dryer) isconnected to a single 120V line and neutral.Commercial and industrial buildings are typically supplied with three-phaseelectrical power as indicated in Figure 2.2. In very large buildings, each floor may besupplied by separate three-phase transformers. Standard branch circuits consisting of a120V line and a neutral line supply small loads. Larger loads are supplied by circuits thatdeliver either single-phase or polyphase power.2.2 ATTENUATIONAttenuation is the amount by which a signal decreases in amplitude duringtransmission. Many resistive loads are normally attached to power lines in buildings; as aresult the amount of attenuation will depend on number, types and location of loads. It isexpected that industrial buildings will have higher attenuation than residential ones, and asthe next two sections show, this is in fact the case.2.2.1 Attenuation in Industrial BuildingsThere have been a number of measurements regarding the attenuation characteristicsof power lines [1,5,61 A brief synopsis of the measurements will be given here and onlythe major observations will be noted.It is agreed that the power line transmission characteristics resemble those of a lowpass filter. The cut off frequency is typically located somewhere between 70 kHz and 150kHz. Where it lies at any particular time is dependent on the loading profile of the line.83 0POWER LINES/METERI/CIRCUIT PANEL1-1i(\\■.-^  BRANCH CIRCUITS2 Power Line ChannelsDISTRIBUTION TRANSFORMERFigure 2.2 Commercial/Industrial three-phase electrical power distribution92 Power Line ChannelsA set of transmission curves was obtained in [1] for the electrical engineeringbuilding at the University of British Columbia, which is classified as an industrial building.Several attenuation curves appear in Figures 2.3 and 2.4 where the symbol "L" means"local", the symbol "R" means "remote", the symbol "0" means phase, and the symbols"A,B,C" denote the three phases of a three phase power line. The measurements forFigure 2.3 were taken during working hours from 8:30-4:00, and the measurements forFigure 2.4 were taken after 6:00 PM. The term "local" refers to the power lines physicallywrapped in the same cable, whereas "remote" refers to the power lines not connected to the"local" power cable directly.For each test in Figures 2.3 and 2.4 the receiver was connected to "local" phase Bwhile the transmitter was moved to "local" and "remote" phase locations as indicated inFigures 2.3 and 2.4. There are several interesting observations based on Figures 2.3 and2.4: (1) There is 5-7 dB attenuation from 30 to 70 kHz on "local" phase B; (2) There is15-30 dB attenuation on "local" phases A and C; (3) All of the remote phases producesimilar attenuation curves except for an underlying attenuation of approximately 25 to 30dB; (4) There are no strictly narrow band dropouts in any of the curves; and (5) There isno frequency above 30 kHz where all of the power lines exhibit minimal attenuation of 5-7dB.Overall, the graphs are consistent with expectations and can be segregated into threegroups. The power line with the least attenuation is local phase B. Next in terms ofattenuation are the local power lines, A and C. The highest attenuation levels are on remoteA, B, and C lines.An explanation provided in [1] for the equality of the attenuation for the three"remote" phases A, B, and C is that such equality is due to signal leak-throughs fromelectrical equipment connected to different phases, and from capacitive coupling ontransformer windings. This statement is supported by [43] which states that the impedanceof power lines is determined by two parameters, the loads connected to the network and theimpedance of the distribution transformer.102 Power Line Channels10 1^102^103frequency (kHz)Figure 2.3 Attenuation during the work day in an industrial building [1]-50,^ ••^•^•^•^=^= • 1^ ,^•^.^.^. . •10 1 102 103frequency (kHz)Figure 2.4 Attenuation in an industrial building at night [1]2.2.2 Attenuation in Residential BuildingsA residential building is powered by a 110 V split single phase circuit. Because thetwo circuits are 180 degrees out of phase, one can be denoted as "phase 0," and the otheras "phase 180." In the following three figures (Figures 2.5-2.7) the symbol "0 0" denotesa test condition where the receiver and the transmitter are both connected to the "phase 0"power line. Also, the symbol "0 180" denotes a test condition where the receiver is112 Power Line Channelsconnected to the "phase 0" power line, and the transmitter is connected to the "phase 180"power line.Attenuation measurements for a residential building are shown in Figure 2.5. Thisfigure shows that the cross-phase "0 180" test resulted in higher attenuation than the same-phase "0 0" test. Figure 2.5 also shows a same phase test with a resistive load attached tothe power line. This test is denoted by the symbol "0 0 R Load." As expected, theattenuation is larger in the "0 0 R Load" test than in the "0 0" test. The change inattenuation is approximately 4 dB.10 1^102^103frequency (kHz)Figure 2.5 Attenuation for residential in-building power line with resistive load [1]Results for cross-phase transmission in a residential building are shown in Figure2.6. The symbol "0 180 R Path" denotes the cross-phase test with a resistive pathconnected between the "phase 0" and the "phase 180" power lines. As shown in Figure2.6 there is a notable improvement of 3-5 dB in signal transmission capability when thisresistive path is present.Figure 2.7 shows attenuation results in a residential building for same-phase "00" and cross-phase "0 180" tests over an extended frequency range to 600 kHz. The rolloff for the "0 0" test occurs at about 400 kHz and at about 200 kHz for the "0 180" test.122 Power Line Channels10 1^102^1 03frequency (kHz)Figure 2.6 Attenuation across phases in residential power lines [1]A notable difference between the industrial and residential attenuation graphs is thatboth the same-phase and cross-phase attenuations have larger bandwidths in a residencethan in an industrial building. The residential power lines have less attenuation because theelectrical loads draw less power than those in an industrial building.2.3 NOISEThe results of a study of the error characteristics in an industrial setting aresummarized in [5] for bit rates from 1.2 kbps to 38.4 kbps using a carrier of 115 kHz.Tables 2.1-2.3 contain statistics on error free lengths using a PSK modem [5].To interpret Tables 2.1-2.3 consider Table 2.3. This table contains data for 4.8 and1.2 kbps tests. Under the "1.2 kbps" heading of Table 2.3 are two tests that produced biterror rates of 9.6E-04 and 3.0E-03. The entries under the "9.6E-04" column yield thefollowing conclusions: (1) — 25% of the error free lengths were of lengths at most 550bits long; (2) — 25% of the error free lengths were of lengths 2000 bits and over; and (3)— 50% of the error free lengths were of lengths between 550 and 2000 bits.132 Power Line Channels102^103frequency (kHz)Figure 2.7 Residential power line bandwidth [11Error Free Length in BitsPer- 38.4 Same Phase 38.4 Cross PhaseGentile 6.60E-04 1.30E-03 5.20E-03 3.50E-04 1.20E-03 5.30E-03 BER25% 1100 500 200 2000 900 12050% 1900 1200 300 3000 1500 27075% 3000 2000 500 5000 2100 400Table 2.1 Error Free Lengths for 38.4 kbps, Industrial BuildingError Free Length in BitsPer- 19.2 Same Phase 19.2 Cross PhaseGentile 4.9E-04 1.2E-03 2.3E-03 4.8E-03 4.0E-04 1.2E-03 2.8E-03 4.8E-03 BER25% 1000 600 300 170 1200 650 300 170.50% 2000 1000 600 300 2100 1000 500 30075% 3500 1700 900 500 4000 1900 800 500Table 2.2 Error free lengths for 19.2 kbps, industrial buildingError Free Length in BitsPer- 4.8 kbps 1.2 kbpscentile 4.2E-04 1.4E-03 3.0E-03 4.1E-03 9.6E-04 3.0E-03 BER25% 600 370 220 230 550 25050% 1300 600 400 300 1100 40075% 3100 1100 610 500 2000 700Table 2.3 Error free lengths for 4.8 and 19.2 kbps, industrial buildingTo further interpret this information, Table 2.4 was constructed. It contains all theinformation from Tables 2.1-2.3 but lists the data in order of bit error rate (BER). It also142 Power Line Channelsincludes a column for the percentage of single bit errors (ie. of all the errors that occur:single, double, triple, etc., what percent are single). Note that a single bit error is onewhich is immediately preceded and followed by at least one correctly received bit.Error Free Lengths and Single Bit ErrorsPercentile Percent of TestBER 25 50 75 Single Bit Err Condition3.5E-04 2000 3000 5000 98 38.4 cross4.0E-04 1200 2100 4000 96 19.2 cross4.2E-04 600 1300 3100 96 4.84.9E-04 1000 2000 3500 99 19.2 same6.6E-04 1100 1900 3000 95 38.4 same9.6E-04 550 1100 2000 70 1.21.2E-03 600 1000 1700 96 19.2 same1.2E-03 650 1000 1900 94 19.2 same1.2E-03 900 1500 2100 93 38.4 same1.3E-03 500 1200 2000 90 38.4 same1.4E-03 370 600 1100 91 4.82.3E-03 300 600 900 94 19.2 same2.8E-03 300 500 800 86 19.2 cross3.0E-03 220 400 610 84 4.83.0E-03 250 400 700 55 1.24.1E-03 230 300 500 83 4.84.8E-03 170 300 500 78 19.2 same4.8E-03 170 300 500 76 19.2 cross5.2E-03 200 300 500 65 38.4 same5.3E-03 120 270 400 70 38.4 crossTable 2.4 Summary of Tables 2.1-2.3 with single bit errorsFrom Table 2.4 it should be noted that the error free lengths for the 25, 50, and 75percentiles decrease as the BER increases. This is as expected since the larger BER willcause more errors in the data. This larger number of errors implies that any two errors willbe separated by a smaller number of bits.The predominant type of error is the single bit error. In some cases single bit errorscomprise 98 percent of all errors. In Table 2.4 it is interesting to compare entries 5 and 6.The former (38.4 kbps, BER of 6.6 x 10 -4) has a single bit error percentage approaching95% and the latter (1.2 kbps, BER of 9.6 x 10 -4) has only 70% of single bit errors. Thissuggests that noise impulses must be of sufficient duration to corrupt the shorter 38.4 kbpsbit but not the longer 1.2 kbps bit.152 Power Line ChannelsMany different types of appliances produce noise. Relatively low noise levelsresult from induction motors, florescent lighting, and other appliances at the frequencyrange up to 100 kHz when compared to the noise levels of light dimmers [6,43] anduniversal motors. Television receivers produce a significant amount of noise at harmonicsof the 15734 Hz horizontal line rate [26].A solid state light dimmer can be used with up to 100 watts of incandescent lightingto provide continuously variable lamp brightness. The dimmer is wired in series with theincandescent lights and controls lamp brightness by switching on and off rapidly throughthe use of triacs. Universal motors are found in vacuum cleaners, mixers, blenders,sewing machines, sanders, drills, and saws. Universal motors contain brushes, and theirperformance is similar to that of do motors: when a load is placed on the motor, the speeddecreases; and when the voltage to the motor is increased, the speed increases. The noisegenerated by motors with brushes has a random amplitude and frequency and can causeradio interference. The noise spectrum of the light dimmer is approximately 25 dB greaterthan the universal motor at 100 kHz [26,43].It has been shown that forward error correction is an effective means to combaterrors on power line communication channels [23].2.4 SIGNAL FADINGAt times, periodic 120 kHz signal fading is observed on power line channels [6].Fading occurs on same-phase and cross-phase channels, with cross-phase channelsoccasionally producing severe fading. One cause of fading is rectifier circuits within powersupplies. When a rectifier turns on, either once or twice during a 60 Hz cycle, it places alarge capacitance directly across the power circuit. This causes the impedance seen by apower line coupled transmitter or receiver to change at a 60 or 120 Hz rate. Since thesignal voltage is developed across this time varying impedance, the signal becomesamplitude modulated at a 60 or 120 Hz rate [43].2.5 POWER LINE LOADINGThe number of appliances connected to an electrical power distribution networkconstantly changes. Streetlights, air conditioning, electric public transport, and electricsteel mills all contribute to the distribution network's loading characteristics. Figure 2.8shows the loading profile of a distribution network during a typical day [50]. This figurecontains curves for industrial, commercial, domestic, and total system electric power16IndustrialCommercial2 Power Line Channelsloading. This figure shows periods of increased system power consumption at 12:00 pm,3:00 pm, and 6:00 pm. Minimum power system power consumption occurs during thenight from 2:00 am to 7:00 am.Figure 2.8 Distribution network load profile during one day [50]Figure 2.8 indicates commercial power loading increases to its maximum at 10:00am and remains constant until 5:00 pm when it decreases to its minimum. Typicalcommercial customers include retail businesses, financial institutions, and commercialoffice real-estate. Industrial customers tend to use the most power at 8:00 am. Theindustrial load also increases at 12:00 pm and 4:00 pm. Domestic users consume thelargest overall amount of power. Figure 2.8 shows increases of load for domestic users at8:00 am, 12:00 pm, and 6:00 pm which is when it attains its maximum.A daily load profile [50] for Saturday through Friday for a distribution system iscontained in Figure 2.9. This figure shows the hourly trends in Figure 2.8 occurconsistently throughout the work-week. Power consumption is much less during week-end periods than during Monday to Friday.17Tu Th FrweSME - storage7;^A^4^4^A-:^i^A^■N.^.^.^■^■Y 9I 1Hydro -pumped-storagea.25ta tSo^Su^Mo12 Power Line ChannelsFigure 2.9 Distribution network load profile during one week [50]The amount of noise and attenuation on a power line is generally related to thenumber and types of loads connected to the power line. An increase in loading will tend toincrease the noise level and attenuation [43]. Although Figures 2.8 and 2.9 are loadingprofiles for entire distribution networks, the loading profiles of individual buildings can beexpected to be similar in profile.183 Hardware Architecture3 Hardware Architecture—Design andImplementation3.1 OVERVIEW OF MODEM HARDWARE ARCHITECTUREThe microcontroller-based modem designed, implemented and tested as part of thisthesis work is conveniently sectioned into two major parts: the receiver and the transmitter.Neither of these two parts can function alone. Each part needs the essential signalssupplied by other common components. These support components are described inSection 3.2 and include the power supply, clock generator, control circuitry, and hostinterface. All schematics are found in Appendix A. The transmitter and receiver hardwaredesign and implementation are described in Sections 3.3 and 3.4, respectively.The modem was designed to facilitate digital implementation and eventualrealization using VLSI technology. A modular architecture was developed, to enableselection or variation of important modem parameters, with minimal impact on mostcomponents and subsystems. Many operational changes are realizable by changingmicrocontroller software.The following modem subsystems, described in detail below, are realized digitally:clock generator, microcontroller, host-modem interface, BPSK modulator (exclusive of theoperational amplifier), Costas loop, bit synchronizer and integrate and dump detector.Analog subsystems include the line-coupling network, transmit power amplifier, transmitlowpass filter, receive bandpass filter and power supply. Some of these analogsubsystems could be realized using ASIC technology.3.2 TRANSMITTER AND RECEIVER SUPPORT COMPONENTS3.2.1 Power SupplyThe power supply shown in Figure A.9 uses a bridge rectifier to convert the powerline AC 110 V to its positive and negative DC components. Three regulators convert theseDC values to +5, +12, & -12 V which are appropriate modem power supply voltages.193 Hardware Architecture3.2.2 The Clock GeneratorThe clock generator is shown in Figure A.4. Two signals are generated by theclock generator: Tx Data Clk and Baud*24. The Tx Data Clk signal is used by themicrocontroller to clock the transmit bit into the transmit latch of the modulator. TheBaud*24 signal is used as a sampling signal by the integrate-and-dump filter circuitry(Figure 3.17). The clock generator generates the Baud*24 signal by dividing the 14.7456MHz signal three times: 14.7456 MHz + 16 + 6 (1, 2, 4, or 8). The 74HCT164,74HCT92, and 74HCT393 function as the three dividers.3.2.3 A Description of the Microcontroller Control PinsThe purpose of this section is to provide an explanation of the control signals whichinterface to the microcontroller in the control unit. The control unit is shown in Figure A.2and consists of three chips: an Intel 8-bit microcontroller 80C31BH-1; an 8-bit addresslatch 74HCT374; and a 128 kbit (16 kbyte) ultra-violet light erasable electricallyprogrammable read only memory, 27128A EPROM. The microcontroller fetchesinstructions from the EPROM and executes them. The EPROM contains themicrocontroller's firmware. The microcontroller is clocked by a 14.7456 MHz oscillator.Hence, the machine cycle of the microcontroller is 14.7456 MHz s 12 = 1.2288 MHzbecause 12 clock cycles are required for the inner functioning of the microcontrollerinstruction cycle which involves fetch, decode and execute operations.The microcontroller uses 18 pins to interface with the address latch and EPROM.These pins are:Pins 39-32 (ADO-AD7): contain the lower order byte of the addresssent to the EPROM. These 8 lines also function as themicrocontroller's data bus. Pins 39-32 are known as port 0of the microcontroller.Pins 21-28 (A8-A15): contain the higher order byte of the addresssent to the EPROM.Pin 30 (ALE/ P ): contains the address line enable signal for theaddress latch. The address latch will output an address tothe EPROM when this signal is high.Pin 29 (PSEN): contains the program store enable. The EPROMwill output data onto the data bus when this signal is low.203 Hardware ArchitectureThe microcontroller uses 12 pins for controlling the modem hardware. These pinsPins 2 & 8 (BaudO & Baudl ): control the baud rate. These twopins are connected to the multiplexor, 74HCT153, in theclock generator circuit (Figure A.4). BaudO & Baudl canselect one of four baud rates: 19.2, 9.6, 4.8, or 2.4 kbps.Pin 1 (Tx Bits): sends the current bit to the modulator.Pin 4 (RxITx*): controls the relay in the coupling network. If thesignal is high/low the transmitter is not connected/connectedto the channel. In other words if the Rx/Tx* signal ishigh/low the modem is in receive/transmit mode.Pin 7 (DCD): is set high when the microcontroller detects the BPSKdata carrier. (Aside: In our modem the carrier signal is115.2 kHz.) The DCD signal is sent to the host via the hostinterface. Thus, the host may implement carrier detection inits communication protocols.Pin 3 (Sync Detect): is set high whenever the microcontrollerdetects a synchronization sequence. The synchronizationsequence is sent at the beginning of every packet as shownin Figure 4.7 in Section 4.3.1. The Sync Detect signal isused for debugging and performance testing purposes.Pin 12 (Rx Bits): receives the demodulated signal from the bitsynchronization circuitry.Pin 14 (Baud*24): receives the baud x 24 signal from the clockgenerator circuitry. The Baud*24 signal is used to samplethe Rx Bits signal as shown in Figure 3.17.Pin 13 (Bit Sync): receives the bit synchronization signal from thebit synchronization circuitry. The Bit Sync signal is used tocontrol the integrate and dump filter described in Section3.4.4.Pin 15 (Tx Data C1k or TxC (DTE)): receives the transmit clockfrom the clock generator circuitry. This signal provides thebit timing for the modem transmitter.Pin 5 (RTS): is reserved for Request To Send information and iscurrently unused.213 Hardware ArchitecturePin 6 (CTS): is used to send Clear to Send information to the host.The use of the CTS signal is described in Section 4.3.4.The microcontroller uses 2 pins for communications with the host. These pins are:Pin 11 (TxD): is used for transmitting data (bytes) to the host inasynchronous format.Pin 10 (RxD): is used for receiving data (bytes) from the host inasynchronous format.3.2.4 The Host/ Modem InterfaceThe host and modem are interfaced to each other via a standard RS232 connection.The interface is depicted in Figure A.10. Two microelectronic chips are used to make theTTL-RS232 signal conversion; the 1488 chip converts TTL to RS232, and the 1489 chipconverts RS232 to TTL. A DB25 connector is used for external access to the RS232signals.3.3 MODEM TRANSMITTER HARDWAREThe transmitter consists of several parts, including modulator, transmit lowpassfilter, and power amplifier.3.3.1 BPSK ModulatorThe modulator, shown in Figure A.4, gets its clocking signal Tx Data Clk from theclock generator, its data Tx Bits from the microcontroller, and the control signal Rx/Tx*from the microcontroller. The modulator sends its output Tx Signal to the transmit lowpass filter.The 115.2 kHz BPSK carrier is generated as a staircase sine wave. The serial-inparallel-out shift register chip 74HCT164 receives a 1.8432 MHz clock signal and dividesthe signal by 16 to produce a set of 8 parallel waveforms. The waveforms are depicted inFigure 3.1. Each of these 115.2 kHz waveforms is passed through a resistor. As shownin Figure A.4 the outputs of the 8 resistors are summed. The output signal of the summingcircuit is an approximation to a sine wave.22IL__3 Hardware ArchitectureA waveformsa 1b —IcdeIghI^I^I^I^I^I^1^I^I^I^I^I^I^I^I- II0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15n (time)Figure 3.1 Output of shift register 74HCT164 in modulator circuitTo select the values of the resistors to generate the sine wave carrier, consider Table3.1. This table lists in its second column the sum of the unweighted 8 parallel waveformsdenoted as sum(a,b,...,h)=a[n]+b[n]+dni -i-dftd+e[n]+f[n]+g[n]+kni. We notice thatsum(a,b,...,h) increases for n=0,...,8 and decreases for n=8,...,15. The third column ofTable 3.1 lists the values of a cosine signal: -cos(360n/16) + 1. This cosine signal has abehavior similar to sum(a,b,...,h). The cosine signal increases for n=0,...,8 and decreasesfor n=8,...,15 . If we assign a weight to each of the 8 parallel waveforms a-h, we canequate columns two and three of Table 3.1. The appropriate equation is shown below,where A -H are the weights assigned to waveforms a-h in Figure 3.1.Aainl+Bb[n]+Cdni+Dd[n]+Ee[n]+Ff[n]+Gg[n]+Hh[n] = -cos(360n116)+1n sum(a,b,...,h) -cos(360n116) + 10 0 0.0001,15 1 0.0762,14 2 0.2933,13 3 0.617 ^4,12 4 1.0005,11 5 1.383^J6,10 6 1.7077,98781.9242.000Table 3.1 Shift register waveforms: unweighted and weighted23ideal. _ _ synthesized3 Hardware ArchitectureSolving for the weights A-H yields: A=H=0.07612, B=G=0 216, C=F=0 3244 ,and D=E=0.3827. The values for the resistors Ra,...,Rg in Figure A.4 in terms of Rh areas follows: R a =Rh; Rb=R g =AIB=0 .3 5 1Rh; R e =Rf=AIC=0.234Rh; andRd=R e=AID=0.199Rh. The resistor Rh is set to 100 Ica Figure 3.2 shows thesynthesized sinusoidal waveform.10 30 50 70 90 110 130 150 170 190 210 230 250nFigure 3.2 Synthesized sinusoidal carrier3.3.2 The Transmit Low Pass FilterFigure 3.3 shows an active second order Butterworth low pass filter which is alsoreferred to as a Sallen-Key circuit [9]. The method used to calculate the values for thecapacitors and resistors is described below.Figure 3.3 Second order Butterworth LPF10-1243 Hardware ArchitectureFor a second order filter Ra and Rb must satisfy the equation Q — 2RRac!Rb ' forQ=0.71. A solution to this equation is Ra = 8250 a and Rb = 4870 D. The capacitors Cland C2 are set to 100 pf. The resistors RI and R2 are frequency scaled to yield the desiredcut-off frequency fo using the following relationships:Rnew = km RoldCold = km kf Cnewkf = 2xfowhere Cold = Rold = 1, fo = 139 kHz, Cnew=100pf. Thus, km = 11842 and Ri=R2=Rnew= 11.8 kQ. The notation "old" in Cold and Rold denotes the values that the resistors andcapacitors have before the above frequency scaling, and the notation "new" denotes thevalues of the components after frequency scaling. Figure A.7 shows the low pass filterwith the above calculated values.3.3.3 The Power AmplifierThe power amplifier circuit shown in Figure A.8 is taken from the application notesfor the power amplifier LM384 [13]. The amplifier circuit has a variable resistor forchanging the gain of the amplifier for performance tests described in Chapter 5. Theamplified signal is sent from the amplifier first through the relay, then through the 1:1transformer, and finally onto the power line. The relay is closed by the Rx/Tx* signal fromthe microcontroller. Because the relay must be activated by a high current, the Rx/Tx*signal is passed through the 7406 high-current driver chip shown in Figure A.B.3.4 MODEM RECEIVER HARDWAREThe receiver consists of several sections which are described in the order which thesignal flows through them from the power line channel. This order is the line couplingnetwork, receive bandpass filter, Costas loop demodulator, bit synchronizer, and modemcontrol unit.3.4.1 Line Coupling NetworkThe line coupling network is shown in Figure A.B. The received signal enters themodem though the AC plug. The signal passes through the 1:1 transformer to the receiveband pass filter in Figure A.6.253 Hardware Architecture3.4.2 Receive Band Pass FilterThe fourth order Butterworth filter [9] shown in Figure A.6 consists of twocascaded second order filters. A second order Butterworth filter is shown in Figure 3.4.Figure 3.4 Second order Butterworth band pass filterThe two criteria used to select the resistor and capacitor values in the second orderfilter are bandwidth BW=56 kHz and centre frequency fo=115 2 kHz. The capacitors areconveniently fixed at 1 nf. Using the bandwidth and centre frequency criteria, the valuesR2=5.6 kS2 and R1 =31752 can be found from the following equations:1 2^1 ^2 BW — 27r R2C 2 ir R2 10 - 9f. ^1^1 "— 27r CV-Iri R2 2n 10 -9 -Nil?, R2The resistors Ra and Rb are connected to the front of the second order BPF andR a Rb implement a voltage divider such that Ra Rb = R1 or R1 = Ra Rb . The choices Ra =2700 D and Rb = 36012 are convenient and satisfy this equation.3.4.3 The Costas LoopThe Costas loop shown in Figure 3.5 is a well-known method of retrieving aBPSK carrier and demodulating the signal simultaneously. Because there is no carriercomponent in the BPSK signal on which to lock, a conventional phase lock loop cannot beused. The frequency spectrum of the BPSK waveform is symmetric about its carrierfrequencyfc and this property is used to synchronize the locally generated carrier [10,25].The BPSK carrier may also be recovered using a squaring loop [34]. With such aloop the received BPSK signal must be multiplied with the local carrier signal and filteredto obtain the baseband information signal.263 Hardware ArchitectureThe Costas loop has several variations. One variation involves the use of a hardlimiter in the bandpass filter preceding the loop. This hard limiter replaces automatic gaincontrol (AGC) circuits which are used to maintain a constant signal level into the receiver'sfront end so that linearity of receiver operation is maintained [49]. Another variationinvolves the use of a hard limiter in the in-phase channel of the Costas loop [47]. This hardlimiter allows the designer to replace the third multiplier (shown in Figure 3.5) with achopper. The variation that was implemented in our modem uses hard limiters in both in-phase and quadrature-phase channels of the Costas loop. Before this variation isexplained, the workings of the general Costas loop is described briefly.As illustrated in Figure 3.5, quadrature components of the local carrier multiply thereceived signal which is then passed through a low pass filter to remove the frequencycomponent at 2fc. The resulting quadrature signals are multiplied together to isolate theerror signal Oe— Sin(0e). The voltage controlled oscillator (VCO) uses this error signal toadjust the local carrier phase.An aberration of BPSK signalling is that there is a 180° phase ambiguity in therecovered carrier. Because of this uncertainty we cannot be sure whether we are receivingm(t) or -m(t) from the Costas loop. There are two ways of removing this ambiguity [10].The first way is to send a known test sequence over the channel before the informationpacket so that a sense of the transmitted signal's polarity can be determined. The secondmethod is to use differential coding and decoding. The BER of differentially encodedBPSK is approximately 1dB worse than uncoded BPSK. Our modem uses a test sequence(or preamble) to determine data polarity and is discussed in Section 4.4.1.The Costas loop demodulator can also be implemented digitally (Figure 3.6), with adigital loop filter chip replacing the LPF and VCO, and with choppers replacing the twomultipliers labelled 1 and 2 in Figure 3.5. Multiplier 3 in Figure 3.5 is replaced with anXOR gate as illustrated in Figure 3.6. Figure 3.6 can be termed a digital Costas loop [11].Figure A.5 contains the fmal implementation of the demodulator.27s(t) = m(t) cos(wc t)IA o sin(wc t + Oe )2^v2 (t) = 1 A c A0 m(t) sin(Oe t)Figure 3.5 BPSK Costas loop demodulatorFigure 3.6 Digital Costas loopvl (t) =-f A c A„ m(t) cos(Oe t)3 Hardware ArchitectureIn Figure 3.6, we replaced multipliers 1 and 2 with two choppers. It will be shownnext that for practical considerations this replacement is valid .A chopper with an input s(t) that is triggered by a square wave c(t) produces anoutput which is identical to multiplying the signal s(t) by c(t) [101 The square wave c(t) isperiodic with period To, and is represented as follows during the time interval [(k-1)To,kTo], where k is any integer:A, (k-1) To < (k-iff) Toc(t) =-A, (k-2)^< k ToFunction c(t) has Fourier transformnr--00C(f) = ECn 6(f-nfo)283 Hardware ArchitecturewherePi= co.A./"Cn = o ,n=oddn otherwiseThe magnitude /C(/)/ = DC n1 8(f-nfo) is shown in Figure 3.7.n=0A2A2A2A3-rr 2A7;fo 310^S.fo^7.f0Figure 3.7 Spectrum of square wave c(t)Because the received signal has a bandwidth less than fo, the spectrum W(f) of the outputw(t) of the chopper is^w(t) = c(t) s(t) •=,1V(f) = C(f)*S0 =^n 8(f-nfo) *It follows thatW(f) = CIS(ffo) + C3S(f 3f0) + C5S(f-5f0) +The first term C/S(flo) is exactly that which occurs when multiplying s(t) by thecarrier signal of frequency fo using an analog multiplier. The higher order components areremoved by the LPF. Therefore, replacing multipliers 1 and 2 in Figure 3.5 with the twochoppers is a valid replacement.The loop filter chip 74HCT297 is the heart of the carrier tracking loop. Thefunctionality of the chip is shown in Figure 3.8. The modulo counter (random walk filter[33]) is triggered by the clock signal and is controlled by the up/ down signal. If thecounter overflows, then the ins line is set. If the counter underflows, the del line is set.The insert/delete circuit is triggered by the clock signal. This circuit outputs pulses at a rateof clock ÷ 2. When the ins line goes high the insert/delete circuit inserts an extra pulse in293 Hardware Architectureits output. When the del line goes high the insert/delete circuit deletes a pulse from itsoutput. Figure 3.9 shows the clock/2 pulses signal with an inserted and a deleted pulse.clock/2pulses insert/deletemodulocounterup/downfrom I armfrom Q armdelclock^clockFigure 3.8 Block diagram of loop filter chipclockclock/2pulsesdeleted insertedpulse pulseFigure 3.9 Inserted and deleted pulses of the loop filter chipThe bandwidth of the loop filter chip is set by the four input control lines of thecounter. These lines are able to set the modulus m of the counter to values between 23 and2 17. Because the clock=14.7456 MHz, the maximum number of inserted and deletedpulses is14.7456 x 106 — extra pulsesIsecond.mTherefore the range of pulses generated isclock^ 14.7456 x 106 14.7456 x 106 2 ± extra pulses/second —^2^±Since the output of the the loop filter chip is divided by 64 (Figure A.5), the local carriersquare wave will have a frequency range of2115.2 • (1 ±—m IcHzThus, the bandwidth can be chosen within the range of 1.75 Hz to 28.8 kHz. Asmall (or narrow) bandwidth will track the carrier very closely producing a small phasejitter, and performs well under low SNR conditions. Conversely, a large bandwidth willproduce a local carrier with a large amount of phase jitter. There is one disadvantage to a30706050k^40 -3020 -10 -• If^• • IV ••^.^•^• II • • V I^•^• •••••1100 10 1 102 103Bandwidth0 If^• •^• • •Iri^•^• •^If • UN104 1053 Hardware Architecturevery narrow bandwidth; a carrier recovery loop with a very narrow bandwidth will take along time to lock onto the signal. To choose the best bandwidth one must compromisebetween phase jitter and lock (or acquisition) time. The amount of phase jitter can beestimated by recording the modem's BER performance under noisy conditions. TheseBER results are shown in Figure 3.10. Similarly, the length of acquisition time can beestimated by tabulating the percentage of packets which are lost (see Section 5.1) as shownin Figure 3.11.10010 -110-2 1010 -10 -610-7 • •^•^• 01 WI^•^• If • 0-1-11 VI^•^II -•^05'1^r^-0- • 11 • II 11,11^•^• • • If • •111100 10 1 102 103 105Bandwidth (Hz)Figure 3.10 BER vs loop filter bandwidthFigure 3.11 Percent lost packets vs loop filter bandwidth313 Hardware ArchitectureFigure 3.10 shows that BER stays fairly constant at 8 x 10 -4 until the loopbandwidth is increased above 7200 Hz, at which point the BER increases rapidly withfurther bandwidth increase. Figure 3.11 shows that bandwidth values between 1800 and7200 Hz produce minimal lost packet percentages. Based on these two ,results, abandwidth of 1800 Hz was selected.As shown in Figure 3.5, the in-phase arm of the IQ demodulator will produce thedemodulated bit stream. This bit stream (Rx Bits signal) is used as an input to the bitsynchronization circuit.3.4.4 Bit Synchronization CircuitIt is assumed in addition to carrier phase and frequency knowledge that thereceiver has accurate knowledge of when an incoming symbol started and when it isfinished. This knowledge is required in order to know the proper symbol integrationinterval. Clearly if the receiver integrates over an interval of an inappropriate length, orover an interval that spans two symbols, the ability to make accurate symbol decisions willbe degraded [25].Timing information is usually derived from the data signal itself and based on somemeaningful optimization criterion which determines the steady-state location of the timinginstants. A distinction can be made between three different kinds of methods [27]. Thefirst class of synchronizers is transition based. The threshold crossings of the receivedbaseband signal are compared with the sampling phase. A correction of the sampling phaseis initiated as a result of this comparison. The mean location of the crossings is estimatedand the optimum sampling instant and maximum eye opening are assumed to be halfwaybetween these crossings. These synchronizers are also called early-late or split-gatesynchronizers [23].The second class of synchronizers uses a signal derivative at the samplinginstances. This derivative, or at least its sign, is usually correlated with the estimated datato produce the updating information required for the timing loop. These synchronizersinclude data-directed and decision feedback loopsA third class of symbol synchronizers uses nonlinear processing to generate andfilter out a spectral line at the clock frequency. The nonlinearity is generally supplied by asquare law device.323 Hardware ArchitectureThe early-late gate is one of the most popular symbol synchronizers because of itssimplicity and is the synchronizer of choice here. The all-digital bit synchronization circuitappears in block diagram form in Figure 3.12 and is detailed in Figure A.3. Often asequential filter (also known as a random walk filter) is inserted between the phase detectorand counter [28,33] to narrow the synchronizer's bandwidth.4. Baud*24Rx Bits ---110Bit Sync 1.--01'PhaseDetectoruP^ counterdown111 Figure 3.12 Bit synchronization circuitFigure 3.13 contains the waveforms of Figure 3.12 when the Rx Bits and Bit Syncsignals are not synchronized. The vertical dashed lines denote the local bit boundaries setby the falling edges of the Bit Sync signal. The bit synchronization circuit synchronizesthese bit boundaries with transitions in the Rx Bits signal. The left half of Figure 3.13shows a received bit of the Rx Bits signal that is "early." The bit synchronization circuitwill respond to the "early" bit by setting the up signal. When the up signal is high thecounter outputs the Bit Sync signal at a slightly higher frequency. Thus, the Bit Syncsignal will "move" to the left until the Bit Sync's boundaries match the boundaries of thereceived bits in the Rx Bits signal. The right half of Figure 3.13 depicts the reversesituation whereby the received bit is "late."Bit SyncRx Bits _.Jupdownearly late^71_Figure 3.13 Non-synchronized bit streamA perfectly synchronized Bit Sync signal is shown in Figure 3.14.333 Hardware ArchitectureBit Sync^ :i^Rx Bits _I bit L____updownFigure 3.14 Perfectly synchronized bit streamThe bit synchronization circuit adjusts the Bit Sync signal by stretching or shrinkingthe high part of the Bit Sync signal. The Bit Sync signal can be one of the waveformsshown in Figure 3.15 (the numbers 11, 12, & 13 represent the number of cycles of theBaud*24 signal shown in Figure 3.12). The Bit Sync signal can be either 23, 24 or 25cycles of the baud*24 signal which implies that the synchronizer's bandwidth isapproximately 0.08 times the bit rate. Thus, the Bit Sync signal will be perfectlysynchronized within 12 transitions of the Rx Bits signal.12 12 12 up=down12 1213 up=0, down=112 11 12 up=1, down=0Figure 3.15 Bit Sync waveforms for different up/down valuesBecause the Bit Sync signal can be synchronized even under noisy conditions asshown in Figure 3.16, the recovered bit clock should not appreciably degrade theperformance of the receiver.Bit SyncnoisyRx BitsFigure 3.16 Noisy bit streamThe Rx Bits and the Bit Sync signal are processed by the receiver's final stagewhich is the integrate-and-dump filter.34Integratorresetbit streamorRx BitsSample "received" values& Holdt Bit Sync3 Hardware Architecture3.4.5 Integrate-and-Dump Filter and Host InterfaceThe digital integrate-and-dump filter [10] is located inside the microcontroller and isshown in Figure 3.17.Figure 3.17 Integrate and dump matched filterThis filter is all-digital and is implemented via hardware and firmware using thethree input signals: Rx Bits, Baud*24, and Bit Sync. The first two signals are connectedto Timer O. (Two hardware timers are located in the microcontroller: Timer 0 and Timer1.) Timer 0 is set to a mode for measuring the length of pulses [18]. This mode causesTimer 0 to be clocked by Baud*24 whenever the Rx Bits signal is high. Timer 0 is readand reset to zero by the firmware on the falling edge of the Bit Sync signal. The effect ofthis procedure is to sample the Rx Bits signal 24 times per bit interval. Section 4.4describes the method used to determine whether the "received" value read from Timer 0 is a1 or O.The microcontroller buffers up eight "received" bits and sends them to the host onthe TxD line shown in Figure A.2. The bits are sent at a baud rate of 38.4 kbps usingasynchronous serial communication.354 Firmware Design4 Firmware Design and Implementation4.1 OVERVIEW OF MODEM FIRMWARE ORGANIZATIONUse of a microcontroller provides flexibility needed to easily vary important modemparameters, without alterations to hardware. Such parameter changes are realizable usingsoftware resident in a host microcomputer interfaced to our modem.An important design consideration is the allocation of data link layer functionsbetween the host and microcontroller. Our division of tasks maximizes the flexibility of thepacket structure, while keeping communication-related tasks performed by the host to aminimum. Packet flexibility is useful, to enable service of different communicationapplications.The microcontroller uses random access memory (RAM) and read only memory(ROM). This RAM consists of 128 bytes located on the microcontroller. Themicrocontroller stores its program variables in this RAM. The ROM, located on theEPROM, consists of 16 kbytes. The microcontroller reads instructions from the EPROMand executes them. These instructions comprise the modem's firmware.The firmware code is separated into the initialization module, the transmit module,and the receive module. The initialization module initializes the modem's parameters, thetransmit module sends bits to the modulator, and the receive module receives bits from thedemodulator. This chapter describes these three modules in detail. The term "mode" isused to describe the fact that the microcontroller is executing instructions found in a certainmodule. Figure 4.1 illustrates the three modes in the firmware.The phrases "data is sent up to the host" and "data is sent down from the host" areused throughout this chapter. The phrases originate from the Open SystemsInterconnection (OSI) reference model (see Figure 4.2) within which the modem occupiesthe lowest layer and the host occupies the higher layers [10]. When the host wants totransmit a packet it sends the packet "down" to the modem. The modem receives thispacket and transmits it over the power line. Similarly, when the modem receives a packetfrom the power line, the modem sends the packet "up" to the host.364 Firmware Design((encleodem inive mode <received two chars)from the hostnotwo chars = "DLE I" ?modem in^modem insmit mode initialization mode)Figure 4.1 Overall view of modem firmwareLayerHOST A logicalconnectionsHOST B Layer7 Application Application 76 Presentation -41111- -1111B- Presentation 65 Session .4111- - -Ow Session 54 Transport Transport 43 Network Network 32 Data link +10- - Data link 2Physical Physical 1physical channel 1.44--Figure 4.2 OSI reference modelChannel communication between transmitter and receiver can be one of three types,asynchronous, synchronous, and intermittent synchronous [24]. An asynchronous bit pipeis one in which individual characters are framed (start, stop bits). This asynchronoustechnique is not useful for very high data rates. A synchronous bit pipe is one where bitswithin a character are sent at a fixed rate but successive characters can be separated byvariable delays. Dummy bits are sent during idle time. This synchronous technique isuseful when high data rates are not important. An intermittent bit pipe is one where the datalink layer of the data terminal equipment (DTE) supplies bits synchronously to the modemwhen it has data to send, but supplies nothing when it has no data. Thus the modem must374 Firmware Designdistinguish between 0, 1, and idle. The capability to transmit nothing is very important formulti-access channels [24].4.2 MODEM INITIALIZATION MODULEThe modem contains many parameters which may be initialized from the hostcomputer. This initialization must be performed at the beginning of a communicationsession. To initialize the modem, the host sends the modem a data link escape characterfollowed by an "I". These two characters are represented as "DLE r. When the modemreceives "DLE r it enters the initialization mode. In this mode commands shown in Figure4.3 are sent between the modem and its host. The command "B", sent from the host,changes the baud rate at which bits are transmitted over the power line by the modem. Therates available are 19.2, 9.6, 4.8, and 2.4 kbps. The parameters accessed by thecommands "C", "S", and "K", sent from the host, are explained in later sections of thischapter. The commands "?", "Q", "P", and "V" send information from the modem to thehost. When the modem receives the "R" command from the host, the modem leaves theinitialization mode and returns to the receive mode.? -- print help informationC -- set data carrier detection thresholdS -- set synchronization wordL -- set data link escape characterQ -- print user selectable parametersK -- set the start of packet indicatorB -- set the baud rateP -- print the baud rate^ -- print the firmware version numberZ -- reset the modemR -- leave the initialization mode and go to receive modeFigure 4.3 Commands sent to the modem by the host during initialization4.3 MODEM TRANSMIT MODULEFigure 4.1 showed that the modem makes a decision when it receives twocharacters from the host. If the two received characters are "DLE I", the modem switchesto initialization mode. If the two received characters are not "DLE I" the modem switchesto transmit mode.38bytes tophysical layer attachpreambletransmitbufferpackets from hostbit stream tomodulator byte to bitserializationbytes fromdata link layer4 Firmware DesignThe transmit module performs physical layer as well as data link layer functions.The physical layer functions are performed by manipulating hardware signals. The datalink layer functions are performed entirely within the microcontroller. Figure 4.4 showsthe data link layer functions which the microcontroller performs. Figure 4.5 illustrates thetransmit module's physical layer functions. Because the data link functions are much morecomplex than the physical layer functions, discussion of the transmit module willconcentrate on the data link layer.bytesFigure 4.4 Transmit module data link layer functionsFigure 4.5 Transmit module physical layer functionsA block diagram of the transmit module is shown in Figure 4.6. As seen in thisfigure the first function performed by the modem is to reset the RxITx* pin to the low logiclevel. When the Rx/Tx* pin is low the modem's hardware transmit power amplifier isconnected to the power line. The next function performed by the modem is to transmit apreamble data sequence over the power line. While the modem is transmitting the preamblethe host sends data bytes down to the modem . These bytes are received by the modem andare stored in its transmit buffer. When the modem finishes transmitting the preamble, ittransmits the data stored in its transmit buffer. As shown in Figure 4.4, the host continuesto send down bytes to the modem while the modem is transmitting data from the transmitbuffer.4.3.1 Transmitted Packet Format: Preamble and DataThe preamble is modulated onto the powerline with the data following immediatelythereafter. A byte is defined to be 8 bits long, and a word is defined to be 16 bits long. Inthe present version,V2.17, of the firmware, 9 bytes of preamble are sent. These bytesconsist of three and one-half synchronization words (SYNC) and one start of packetindicator word (STRT) as shown in Figure 4.7. A word contains two bytes, a mostsignificant (ms) and least significant (ls) byte. The "one-half SYNC word" is the least394 Firmware Designsignificant (1s) byte of SYNC. Section 4.4.2 includes more discussion of preamble lengthand SYNC and STRT sequences. The data field of Figure 4.7 can be any number of bytesin length.The modem does not implement higher data link operations such as CRC,addressing, flags, packet length indicators, and character (or bit) stuffing. These functionsare implemented in the host. The data field in Figure 4.7 will contain the packet formatimplemented by the host. The modem is almost completely transparent to the host. Theonly restriction of the data field content (Figure 4.7) is the first two bytes. These twobytes are described in Section 4.2. Because of this high degree of transparency, themodem can transmit and receive any type of data including text and binary formats.Transparency is important because the higher the order of transparency the lower theamount of additional overhead on a packet due to character and bit stuffing.4.3.2 Host-Modem CommunicationFrom Figure 4.4 it was seen that the host sends data down to the modem while themodem transmits data over the power line. The modem buffers the data in its transmitbuffer and will transmit this data at a later time. The modem is capable of transmitting dataover the power line at rates of 2.4, 4.8 ,9.6, and 19.2 kbps. The host sends data down tothe modem at 38.4 kbps using an asynchronous serial communication format. This formatconsists of one start bit, eight data bits, and one stop bit. Taking this format overhead intoconsideration, the maximum throughput of the host-modem link is reduced to 30.27 kbps.As was mentioned earlier, the modem contains only 128 bytes of RAM. Of this128 bytes only 40 are used for the transmit buffer. This buffer is used in a circular fashionas shown in Figure 4.8. The "buffer occupied" portion of the buffer contains bytes that areyet to be transmitted over the power line. The arrow labelled "1" in Figure 4.8 indicates thedirection that the "start of data" arrow moves as data is removed from the circular buffer.The arrow labelled "2" in Figure 4.8 shows the direction that the "end of data" arrowmoves as data enters the buffer.404 Firmware Designreset RxITx pi)V[transmit preambleover power line andbuffer data received fromhost in transmit bufferremove byte from transmit bufferC7et bit count =.4.22‹^1144r^received byte from host?iyes (buffer byte received from host in)V' \ -transmit buffersend bit to modulator on low edgeof Tx Data Cikecrement bit countno < is transmit buffer empty? >*yes (set RxITx* pi.)Figure 4.6 Transmit module block diagramIs byte word word word word 1 or more bytesSYNC I SYNC' SYNCI SYNC' STRT  I^DATA^1PREAMBLEFigure 4.7 Transmitted packet formatIf<is bit count = 0? >no*yes41start ofdata buffer notoccupiedend ofdata4 Firmware DesignFigure 4.8 Circular transmit bufferWhen the circular transmit buffer becomes full, two options are possible. The firstoption is for the modem to stop placing data in the transmit buffer, and to ignore any databytes sent down by the host. The second option is for the host to stop sending data bytesdown to the modem. Of the two options, the second is preferred. To implement thissecond option the modem must inform the host whenever the transmit buffer becomes full.This capability called handshaking is discussed in the next section. A useful generalizationof this capability results when the modem has complete control over the host-modem link.This generalization is discussed in Section 4.3.4.4.3.3 XON/XOFF Host-Modem Flow ControlThe XON/XOFF protocol is a common method of implementing host-modemhandshaking. Two control bytes XON and XOFF are sent up to the host by the modem.XON means "transmission ON," and XOFF means "transmission OFF." When themodem's transmit buffer becomes full, the modem sends XOFF up to the host Similarly,when the modem's transmit becomes empty, the modem sends XON up to the host.This protocol has two important disadvantages. The first disadvantage is that theprotocol malfunctions whenever the XON/XOFF bytes are not received by the host. Thesecond is that the protocol is not able to alter the transfer rate of the host-modem link. Thefirst disadvantage became evident during testing when it was noticed that the host personalcomputer did not always receive the XON/XOFF control bytes. A missing XON bytecaused the modem's transmit buffer to empty prematurely, and a missing XOFF bytecaused the modem's transmit buffer to overflow. The second XON/XOFF protocoldisadvantage became evident when the modem was tested at 2400 bps. At 2400 bps themodem missed some of the data bytes sent down from the host. This problem occursbecause the host sends data bytes down to the modem faster than the modem can buffer424 Firmware Designthem. The modem is capable of buffering at a rate of 2400 bytes per second. In Section4.3.2, the host-modem link was calculated to be 30.27 kbps which is equal to 3784 bytesper second. Since the host sends data bytes down to the modem at 3784 bytes per second,and since the modem buffers these bytes at 2400 bytes per second, data bytes are lost andthe packet is corrupted.To overcome the XON/XOFF protocol impairments, a new handshaking protocolwas developed. This new protocol is described in the next section.4.3.4 Synchronous Handshaking for Asynchronous CommunicationThe two disadvantages of the XON/XOFF protocol discussed in Section 4.1.3 areresolved by using a hardwired handshaking protocol. The CTS line was chosen toimplement this protocol.In the host computer, there is an indicator bit called Delta Clear to Send (DCTS).This indicator bit is located in the Modem Status Register (MSR) of the host's serial port.The DCTS bit is set whenever the CTS line changes state. The bit is reset whenever thehost computer reads the Modem Status Register.There are two rules in the protocol to which the host and modem adhere. Themodem toggles the CTS line whenever it is able to receive a data byte from the host. Thehost must only send a data byte down to the modem if its DCTS bit is set.The hardwired handshaking protocol is able to avoid the two disadvantages of theXON/XOFF protocol. The modem's transmit buffer will never overflow because the hostwill only send data bytes whenever the CTS line is toggled. Whenever the modem's bufferbecomes full, the modem stops toggling the CTS line. The second disadvantage of theXON/XOFF protocol is solved because the modem is able to control the rate at which datais sent down from the host. The modem toggles the CTS line at the same rate at which it isable to buffer data bytes sent down from the host.There are two possible problems which could cause the hardwired protocol to fail.The first problem is a failure by the host of detecting one or more toggles. This is in factnot a problem for the following reason. Whenever the host detects a toggle, the host willsend a byte of data down to the modem. If the host does not detect a toggle the host willnot send down a data byte. The modem will not notice this lack of data because themodem's buffer already contains several bytes of data which must be transmitted. A43received signalfrom demodulator valuesbit stream todata link layerIntegrate and TableDump Matched Filter Look-Up No-confidence todata link layerFigure 4.9 Receive module physical layer functions4 Firmware Designsecond potential problem is the detection by the host of a spurious toggle. This is a moreserious problem because the host may send down a byte of data to the modem before thethe modem is able to accept it. Thus it is possible for a data byte to be lost on a spurioustoggle. The chance of a spurious toggle occurring is very remote and will occur only if themodem/host hardware malfunctions. Neither of these two problems have been detected intesting.The above approach to host-modem communication is advantageous over purelysynchronous communication because the timing is not rigid. As long as the host sends datato the modem at a rate high enough to prevent the modem's transmit buffer from emptying,the protocol will work as required. Another advantage is the fact that the host-modemcommunication rate is much higher than the power line baud rate. For purely synchronouscommunication the host-modem communication rate is equal to the power line baud rate.This difference in host-modem communication rates would translate into time saved by thehost. This time could be used by the host to perform other processing tasks.4.4 MODEM RECEIVE MODULEAs shown in Figure 4.1, the receive module is the default module. This means thatafter the modem finishes transmitting or initializing, the modem returns to receive mode.Like the transmit mode, the receive module performs physical and data link layerfunctions. Figure 4.9 shows the receive module's physical layer functions. Figure 4.10illustrates the data link layer functions performed by the receive module.444 Firmware Designbit stream fromphysical layer bytesynchronizationbytes strippreamblebytes attach packetdelimiterspackets to hostconfidence from tphysical layerFigure 4.10 Receive module data link layer functionsThe physical layer performs two functions shown in Figure 4.9. The integrate-and-dumpmatched filter was described from a hardware perspective in Section 3.3.4. In firmwareterms, a counter acts as an integrator. The dumping action of the filter is realized by"reading" and subsequently zeroing it. The table look-up function implements thresholdingrequired to translate dump values from the integrate and dump matched filter into "received"bits. The thresholding procedure isbit =where value is in the range 0 to 25.4.4.1 Data Link Layerf 1 ,value >1210, value _1 12As shown in Figure 4.10, the data link layer receives a bit stream from the physicallayer. The bit stream is analyzed in order that bytes and packets can be extracted and sentto the host. To perform these extractions the data link layer was designed as a real-timefinite state automata containing four states. The four states are Sync_Search, Sync_Verify,Sync/Strt, and Lock shown in Figure 4.11. Item SR in Figure 4.11 is a 16-bit shiftregister that contains 16 bits from the received bit stream. The items SYNC and STRT areexplained in Section 4.3.1.The complexity of the automata is limited by two microcontroller restrictions.These include microcontroller instruction operand width and instruction execution speed.The microcontroller is only able to process operands which are a byte wide. Thus, anyword-wide operations must be converted to byte-wide operations. The microcontroller hasan instruction frequency of 1.2288 MHz. When the modem is operating at 19.2 kbps, themicrocontroller can execute a maximum of 64 1-cycle instructions. Thus, the automatamust perform its functions within 64 instruction cycles.45(get bit(put in SR )no ^* 4—<SR=SYNC>*yes(get 16 bits)no<S^R=SYNC>* yes (set or reset)inversion( get 16 bits )invertnecessaryes ^* SR=SYNC"›nono+yes^Vg t^t sinvert ifnecessary<)carrier detected?4( yes^(send byte)to hostSR=STRT?no4 Firmware DesignSYNC SEARCH SYNC VERIFY SYNC/STRT^LOCKFigure 4.11 Data link layer flow chartThe first state of the automata in Figure 4.11 is Sync_Search. In this state themicrocontroller continuously searches for the 16-bit synchronization word SYNC in the bitstream. When SYNC is detected with three or fewer bit errors, the microcontrollerswitches to state Sync_Verify. In this state the microcontroller buffers 16 bits in shiftregister SR and compares SR with SYNC. This comparison is to verify that themicrocontroller has correctly synchronized itself to the synchronization pattern in thepreamble. A single bit error is allowed in this verifying comparison. This state alsodetermines whether the bits are inverted and sets an inversion flag to this effect. Bits maybe inverted because of the 180° phase ambiguity discussed in Section 3.4.3. Uponsuccessful SYNC verification, the microcontroller switches to Sync/Strt state. As shownin Figure 4.11 the microcontroller buffers 16 bits in SR. SR is compared against SYNCand STRT while allowing one bit error. If SR contains SYNC the microcontroller stays inSync/Strt, but if SR contains STRT the microcontroller switches to the Lock state.Upon entering the Lock state, the microcontroller has accomplished the first twofunctions of Figure 4.10: byte synchronization and preamble stripping. The Lock stateperforms the final function of packet delimiting. Figure 4.12 shows the received data andits delimiters all of which are sent up to the host. SOP and EOP are the Start of Packet andEnd of Packet delimiters, respectively, as detailed later in Section 4.4.2. The flow chart ofFigure 4.11 does not show the delimiting action of the Lock state. The SOP delimiter isattached when the state switches from Sync/Strt to Lock, and the EOP delimiter is attachedwhen the state switches from Lock to Sync_Search. Otherwise, the functioning of the464 Firmware DesignLock state is as shown in Figure 4.11. The microcontroller buffers 8 bits in the the lowerhalf of the shift register SR_LOW and sends SR_LOW to the host if the data carrier isdetected.I SOP I^DATA^I EOP Iword^1 or more bytes^wordFigure 4.12 Packet sent to host4.4.2 Discussion of Data Link Layer ParametersThe description of the receive module's data link layer in Section 4.2.1 containsmany parameters that were fixed when the finite state automata was being designed. Theparameters in the automata were selected such that the functions of the data link layer are aspowerful as possible within the limits imposed in Section 4.2.1.The length of the preamble was selected after consideration of several factors. Thefirst consideration is packet overhead. To reduce packet overhead, it is necessary that thepreamble contain as few bits as possible. The second consideration is reliable data linklayer performance. The data link layer must be able to recognize a high percentage ofincoming packets, facilitate byte and packet synchronization, and properly strip thepreambles. Any faulty behavior of the data link layer will result in packet corruption andloss of channel throughput. A third consideration is host processing time. The host isbusy performing a variety of tasks, of which only one is communication with its modem.The data link layer of the modem must monitor the bit stream coming from the physicallayer and must pass only valid packets up to the host. Any random bits in the bit streamwhich have the appearance of valid data must be deleted. The host will then spend aminimum amount of time processing data arriving from its modem, and will be able todedicate itself to other tasks.The first consideration in the above paragraph identifies the need for a shortpreamble. The finite state automata discussed in Section 4.2.1 requires that the preamblecontain a minimum of two SYNC words followed by a single STRT word. The data linklayer was tested with preambles containing two SYNC words plus incremental numbers ofadditional bits from 0 to 48. These additional bits are segments of the SYNC words (ie. 4additional bits means the least significant nibble of the SYNC word is transmitted). Adirect relationship was found between the number of additional SYNC bits in the preambleand the probability that the automata is able to synchronize to the preamble as shown in474 Firmware DesignFigure 4.13. Since there is little improvement in the performance of the automata forpreambles containing more than 24 additional bits, the preamble as shown in Figure 4.7was chosen to contain three and a half SYNC words.0^10^20^30^40^50Number of Additional Bits in PreambleFigure 4.13 Performance of data link layerConsiderations two and three motivated the use of 16-bit SYNC and STRTidentities. Sixteen-bit words are processed as two separate bytes by the microcontrollerbecause of the byte-wide operand restriction discussed in Section 4.2.1. The SYNC wordwas chosen to be Ox3ca9, where Ox denotes hexadecimal, and the STRT word was chosento be Ox3c56. The binary representation of SYNC is 0011110010101001 and the binaryrepresentation of STRT is 0011110001010110. The SYNC word contains patterns ofalternating ones and zeroes which is desirable for demodulator and hardwaresynchronization circuits. The STRT word has the beneficial property that eight error bitsare required to turn STRT into SYNC. The SYNC word was also chosen because of itsdesirable correlation feature. A good synchronization codeword is one that has theproperty that the absolute value of its "correlation sidelobes" is small. A correlationsidelobe is the value of the correlation of a codeword with a time-shifted version of itself[23,25]. This correlation is shown in Figure 4.14. The word Ox3ca9 was identified via anexhaustive computer search that selected 16-bit words based on correlation and number of1-0 and 0-1 transitions.4818161412.210 -8 8640 8^16^24# of bits SYNC word is shifted324 Firmware DesignFigure 4.14 Correlation of SYNC wordConsiderations two and three were used to decide on the number of bit errorsallowed for a preamble word in each state of the automata. Sync_Search allows three biterrors, Sync_Verify allows 1 bit error, and Sync/Strt allows 1 bit error.Two probabilities characterize the performance of a system using a synchronizationword. These are the probability of a missed detection and the probability of false alarm[25]. Clearly, the system designer would wish both probabilities to be as small aspossible. These are conflicting objectives. In order to decrease the probability of a miss,the system designer may allow less than perfect correlation of an incoming synchronizationword. That is, a word may be accepted even if it contains a small number of errors. This,however, enlarges the number of symbol patterns that will be accepted and therebyincreases the probability of a false alarm.We can evaluate the data link layer performance using these considerations. Toperform this evaluation, we determine the rate at which the automata falsely triggers on arandomly noisy bit stream. To find this rate we first calculate the total number Ni ofrandom bit error patterns of length 16 bits which can successfully pass through theindividual states of the data link layer, as follows:2 [( 3 )+( 2 )+( 16)4 0 )]= 1394 for Sync_Search StateN2= 2 [(115 )4106 n= 34 for Sync_Verify State494 Firmware DesignN3= [C16 ) +Cit ll= 17 for Sync/Strt StateThe total number of patterns which will match the preamble is (1394)(34)(17) = 8 x 10 5 .The total number of patterns possible are (216)(216)(216) =2.8 x 1014. Therefore, theprobability of a random bit sequence matching the preamble is 2.84 x 10 -9. Thus, onaverage the data link layer would detect a false preamble once in 3.5 x 108 random bits.The mean time between false preambles for different baud rates is tabulated in Table 4.1.This table shows that a modem operating at 19.2 kbps will produce false preambles every 5hours, on average. This mean time is large enough to fulfill the reliability requirementsdescribed as consideration two above.baud rate (kbps) seconds minutes hours19.2 18229.2 303.8 5.19.6 36458.3 607.6 10.14.8 72916.7 1215.3 20.32.4 145833.3 2430.6 40.5Table 4.1 Mean time between false alarmsFigure 4.12 shows that two delimiters SOP and EOP are sent up to the host. Thehost uses the delimiters to identify packets within its own buffers. SOP and EOP wereeach chosen to be 16 bits long. Because a packet contains random data, it is better in termsof probability of spurious delimiter occurrence to use a 16 bit delimiter instead of an eightbit delimiter. The probability that 16 bits of random data is a delimiter is 246 = 0.000015whereas the probability that 8 bits of random data is a delimiter is 2-8 = 0.0039. The SOPand EOP were arbitrarily chosen to be 0x3738 and Oxa3a4, respectively. Because SOP andEOP are generated by the modem and are not transmitted over the power line, theprobability that a delimiter contains a bit error is very small. In fact, the probability of adelimiter bit error is equal to the probability of a bit error in RS232 communication.4.4.3 Carrier DetectionAs shown in Figure 4.11 the finite state automata switches from Lock state toSync_Search state if a data carrier is not detected. Carrier detection is performed within theLock state. This detection is based on a computed value called confidence. Whenconfidence is high the modem is "confident" that a carrier signal is present on the powerline. The DCD (Data Carrier Detect) pin is set high whenever confidence is high. The504 Firmware DesignDCD signal is connected to the host to enable the host to use protocols that require carrierdetection.Figure 4.9 shows that the physical layer produces a confidence value for every bitsent to the data link layer. A bit's confidence value is calculated from the dump valuesproduced by the integrate and dump matched filter as shown in Figure 4.9. Therelationship between confidence and dump values is confidence =112-dumpl. Figure 4.15shows a bit which has a high confidence value and a bit which has a low confidence value.The confidence value of the high confidence bit in Figure 4.15 is 11=112-231, and theconfidence value of the low confidence bit is 1=112-131.high confidence bitlow confidence bit111111111111111111111111111^1^ 24bit sample numberFigure 4.15 High and low confidence bitsA low confidence value terminates the Lock state. Because the power line is noisythe packets will contain incorrectly detected bits. These errored bits often have lowconfidence values. Reception of a single noisy bit may result in termination of the Lockstate and consequently in truncation of the packet being sent up to the host. In someapplications, it may be advantageous to send some noisy packets up to the host, since someerrors may be acceptable. Often, an error correction procedure may be available. Analternative method of terminating the Lock state is to utilize confidence values from manybits. One such formula isnew confidence = ROUND (2-1 old confidence) + current confidence22 –where function ROUND(X) denotes the closest integer to X. current confidence is theconfidence value of the current bit and has a range of 0 to 12. new confidence is the valuewhich is used for deciding on termination of the Lock state. new_confidence has a range514 Firmware Designof 0 to 254. old confidence was the calculated new_confidence for the previous bit. Thevalue for new confidence is calculated for every bit.Previously it was said that the DCD signal is set whenever confidence is "high."The term "high" is subjective. confidence is said to be "high enough" whenevernew_confidence exceeds the quantity confidence_threshold. The value forconfidence_threshold must be low enough that the Lock state will tolerate some bit errors,and high enough that the Lock state will terminate at the end of a received data packet.To determine a value for confidence_threshold it is useful to calculate the values ofnew_confidence for different values of current_confidence. Table 4.2 tabulates thesecalculations. If we subjectively rate the current_confidence values as poor, marginal,good, and excellent as shown in Table 4.2, a selection for the value ofconfidence_threshold can be made. The value chosen for confidence_threshold is 192which falls under the "good" category.category current confidence new confidencepoor 0 0• OOTsoor1111111111111111111111111234•oor 1111111111.1111.1 56WM 4 78marginalood:oodlIllrnllIlliIllIllMll11189IIIIIIIIIIIIIIII•188foodexcellent12 254excellentTable 4.2 new_confidence values for different current confidence valuesAs mentioned above, the Lock state is terminated whenever the new_confidencevalue falls below confidence_threshold. The time between the end of a packet and theinstant that the Lock state is terminated is the transition time. Bits that are sent up to thehost during the transition time are transition bits, illustrated in Figure 4.16.52new_confidenceLock stateterminationconfidence thresholdtransition time^NW'4 Firmware Designend of packetpacket^ noiseRx Bits timebits sent^0^1^0^0^1up to host^data bits transition bitsFigure 4.16 Time taken for new_confidence to fall below confidence thresholdThe number of transition bits depends on the value of new_confidence at the end ofthe packet and on the values of current_confidence during the transition time. Figure 4.17illustrates this dependence for current_confidence values of 0, 1, and 2. Figure 4.17shows that the number of transition bits produced is at most eight. As mentioned inSection 4.4.1 the microcontroller sends data up to the host in bytes. Therefore the modemwill send a maximum of 1 byte to the host during the transition time.9az 8o 7654.,o 432111111111111111.1Legend— current confidence=0— current confidence=1- - - current confidence=2\ lel^I^111.111250^240^230^220^210^200new_confidenceFigure 4.17 Bits to terminate lock state for cur conf of 0, 1, & 2535 Test Results...5 Test Results in Different EnvironmentsThe 19.2 kbps modem was used to perform many tests in various, actual operatingenvironments. The purpose of the tests was to obtain various communicationperformance parameters, including bit error rate, block error rate, and percent of lostpackets. These tests were carried out in the Electrical Engineering building at theUniversity of British Columbia. This building is known to provide a harsh operatingenvironment for power line communications.Before the modem was tested on power line channels various statistics regardingits operation were collected for tests under white noise conditions. These statistics aredescribed in Section 5.2 and verify the modem's correct operation.5.1 DISCUSSION OF TEST PARAMETERSTo test modem performance, packets (blocks) are sent from the transmitting hostto the receiving host. The receiving host analyzes received packets in real-time andgenerates results discussed later in this section. The software used to analyze the receivedpackets is called A Bit Error Rate Tester for Power Line Modems [20]. The packets havea format shown in Figure 5.1.I SOB TYPE SEQ ACK NFR DATA TYPE LEN STX CRC1 CRC2 I TEST PATTERN ETX•^data^I trailerFigure 5.1 Packet format for Bit Error Rate TesterThe packet in Figure 5.1 indicates that a packet has three parts, a header, a datafield, and a trailer. The header and trailer identify the beginning and end of a packet,respectively. The header is terminated by a cyclic redundancy check (CRC) number.The receiving host calculates its own CRC number for the header. If the transmitted CRCand the locally calculated CRC are identical then the header contains no detected errorsand the packet is forwarded for analysis. The analysis is performed on a test patternwithin the packet's data field.header545 Test Results...The test pattern in the data field consists of 125 characters: "AAAAAAAAAABBBBBBBBBBCCCCC MMMMM". A bit error occurs whenever a bit within thedata field is in error. A block error occurs when one or more bit errors occur within thedata field of the packet. Throughput is determined by the following formula.number of packets received^number of data bytes/packetthroughput = bit rate • ( number of packets transmitted) . (total number of bytes/packetThe number of data bytes/packet is the number of bytes within the data field which is125. The total number of bytes/packet includes all the bytes in Figure 5.1 as well as thepreamble. This total comes to 145 bytes. The above formula for throughput is based oncontinuous single-direction transmission of packets and does not include idle timebetween packets. Idle time was placed between transmitted packets in order to allow timefor the receiver's synchronization circuits to fall into a random state. This is done tosimulate actual channel traffic. Also, the calculation for throughput does not take intoconsideration packets with errors. This can be done by multiplying throughput by (1-BLKER).Because of the functionality of the modem's data link layer described in Chapter4, and the method used to obtain "operating" data, packets can be lost. These lostpackets are the reason number of received packets 5 number of transmitted packets.Packets are lost in two ways. If there are many errors within a transmitted preamble(Figure 4.7), the modem's data link layer will not recognize the start of a packet.Although the rest of the packet may not contain any errors, the modem will not send anypart of the packet up to the host. Thus, the modem itself loses a packet when it cannotrecognize a packet's preamble. A second way in which a packet may be lost is when apacket is discarded by the receiving host. If the packet header contains an error (which iscaught by the CRC) the packet is not analyzed. The Bit Error Rate Tester discards thepacket and looks for the next packet. Packet discards occur because the Tester does nothave any method for determining whether any part of the header is correct. Therefore inboth cases, a "lost packet" is a packet whose beginning can not be identified. Theparameter percent lost packets is calculated aspercent lost packets = 1 - number of packets received^100)( number of packets transmittedNormally, "raw" statistical value is obtained by analyzing all data received froma modem. This can be achieved by using a device called a Data Error Analyzer. An555 Test Results..."operating" value is calculated by analyzing data after minimal processing of the rawdata. This processing is necessary for generating statistics when using packetized data.Errors tend to occur in bursts on power lines [19]. Figure 5.2 shows an illustrationof noisy and quiet periods on a power line. The probability of a packet being lost is highif the preamble or header is transmitted during a noisy period. The nature of burstychannels is that a noisy period is followed by a fairly low noise or quiet period. Within aquiet period random errors occur. Depending on the relationship between the lengths ofnoisy and quiet periods, the data field of a packet which is not lost may fall more often inquiet periods or in noisy periods. If a quiet period is much larger than a noisy period, thedata field will fall more often within a quiet period. Therefore, "operating" data is datawhich is obtained from packets whose preamble and header have a low probability ofbeing in a noisy period. Statistics from tests that produce a small percentage of lostpackets can be assumed to not suffer from this noisy-quiet period phenomena.quiet periodnoisy period^noisy periodFigure 5.2 Noisy and quiet periods on a channelBER is calculated for a single packet using the following formula.BER — number of bits in error in data fieldtotal number of bits in data fieldThe total number of bits in data field is equal to 1000. Because BER is a statisticalnumber, its value is most accurate when it is based on a very large number of samples.This can either be achieved by transmitting one extremely long packet or many shorterpackets. The solution is to send packets of moderate length (125 data bytes) and calculatethe BER based on the total number of data bits for all the received packets.The block error rate (BLKER) is calculated as shown in the following equation.BLKER — number of received packets with error in the data fieldtotal number of packets receivedA block is considered to be in error if any of the bits in its data field is in error.565 Test Results...5.2 TEST RESULTS UNDER WHITE NOISE CONDITIONSFigures 5.3 and 5.4 contain performance curves for the modem for additive whitegaussian noise. Figure 5.3 (a) contains BER results for the modem under white noiseconditions. In such a case, bit errors are independent under optimum reception. Themethod for determining Eb/No is described in [1]. This figure shows that the modem isoperating properly and the deviation from theory is approximately 1-2 dB. This deviationcan be attributed to carrier and symbol recovery error [25]. The graph in Figure 5.4 (a)shows the relationship between BLKER and BER. The theoretical curve is calculatedusing the following equation [24].BLKER = I - (1-BER) 1where I is the number of bits in a packet (here it is the number of bits in the data field)which is 1000 bits. The graph in Figure 5.4 (b) shows percent lost packets vs BER. Thetheoretical curve is calculated by determining the probability that the synchronizationsequence will contain too many errors and thus will not be recognized by the finite stateautomata in the data link layer (Chapter 4). The probability of an errored preamble isfound by the relationship P(incorrect preamble) = 1 - P(correct preamble). P(correctpreamble) can be determined from the following relationship,P(correct preamble) = P( correct SYNC 1) P(correct SYNC 2) P(correct STRT)It was stated in Chapter 4 that SYNC 1 can be inverted and have at most 3 errors,SYNC 2 can be inverted and have at most 1 error, and STRT cannot be inverted and canhave at most one error. Using these conditions the three probabilities can be calculated.As an example P(correct SYNC 2) is given next where p is the probability of a bit error.P(correct SYNC 2) = g 06 )0_0466 p_py5p1 + C5)(1..p)ipt5+ 60p16.1Figure 5.4 (b) also contains a "not synced" and a "not analyzed" curve. The not analyzedcurve represents the packets not available for analysis by the software (ie. host level).The not synced curve represents the packets lost at the modem level. The differencebetween the not analyzed and not synced curve represent packets which were passed up tothe host by the modem but were discarded by the host because of errors in the packetheader detected by the CRC.57•^1-15^6^7^8^9^10 11 12Eb/No (dB)(b)100-10 1-10 2 "ce 10-3Lla-41010 5-10 6 1^10-7 ".^•^•^•^0^2^4^6^8Eb/No (dB)(a)10^12ieon" theory"*" AWGN102 .^Wa10 1 ".010080-0" theory-"P' not analyzed"4- not synced200^• 11..-1 INI5 Test Results...Figure 5.3 Modem performance in white noise: BER and BLKER10-7 10-6 10 -5 10-4 10-3 10-2 10-1 100^10-7 10-6 10-5 10-4 10-3 10-2 10-1 100BER^ BER(a) (b)Figure 5.4 BLKER and percent lost packets vs BER for white noise5.3 TEST ENVIRONMENT AND PROCEDUREWithin the Electrical Engineering building, electrical power is delivered throughtwo systems. One system provides three phase power to all laboratories and machineshops. The other system provides three phase power to wall outlets and lighting fixtures585 Test Results...in hallways, classrooms, and offices. The first system is called a Lab System and thesecond system is called a General System (my terminology). Each of these systems has a1600 amp bus in the Switch Room in the basement (first floor) from which power isdistributed. The flow of electrical power consists of a path from the three phase4160V/120V transformer to the General System bus, across a copper bus bar or "link",and onto the Lab System bus [22]. Sometime in the future, this link may be replaced by areactor. The reactor would limit the current flowing from the General System bus to theLab System bus. This current limiting feature would protect the three phase transformerfrom high current flow whenever a short circuit fault appeared on the Lab System. Thethree phases of a power line are denoted as Ox, Ø y, and Oz . The relationship between thethree phases are shown in Figure 5.5.Volts120Figure 5.5 Three phases of a power lineThree types of tests were performed on these systems. The first test is composedof same and cross phase tests within the Lab System. A second test is composed of sameand cross phase tests within the General System. A third test is same and cross phase testsperformed across the link between the Lab System and the General System. Thetransmitter RMS output voltage VT is used as a parameter in the tests. This parameter ismeasured at the output of the transmitter's power amplifier and is tabulated in terms ofdBmV. This decibel measure is defined as follows [10] where VT is in volts:dBmV = 20 log ( 10-3The data signal that appears on the power line channel at the output of the modem isapproximately 2 dBmV lower than the signal at the output of the power amplifier. Thisattenuation is caused by the transformer in the line-coupling network.The length of each test in terms of bits and blocks was selected such that thenumber of bits in error exceeded 100 and the number of received packets was at least595 Test Results...1000. For tests that produced BER values better than 1 x 10 -5 , the test was terminatedafter 10000 packets (1 x 107 bits) were received.5.4 SAME PHASE AND CROSS PHASE TESTS ON LAB SYSTEMThe location of the tests is a communications laboratory which containsapproximately 20 computers (or workstations) and other test equipment. The transmitterand receiver are separated by approximately 100 feet of power line. Tests are performedon all three phases of the power line producing nine different channels. Three of thechannels are same phase and six of the channels are cross phase. Figure 5.6 shows theBER results for the nine channels.Figure 5.6 (a) shows that channel x to z has an approximate 22 dBmV advantageover x to x and that channel x to y has an approximate 20 dBmV advantage over x to x.Figure 5.6 (b) shows that channel y to z is 6.6 dBmV worse than y to y and channel y to xis 10 dBmV worse than y to y. Figure 5.6 (c) shows that z to x and z to y are 15 dBmVand 27 dBmV worse, respectively, than z to z.Comparing same phase channels only, y to y performs best producing a BER of1 x 10-5 at 41 dBmV. For cross phase channels only, y to z performs the best with a BERof 2 x 10-6 at 46 dBmV.Figure 5.7 shows BLKER results for the nine channels. The BLKER results areconsistent with the BER results in Figure 5.6. A more useful method of determining thecharacteristics of the nine channels is to look at the BER vs BLKER curves in Figure 5.8.Figure 5.8 compares the BER vs BLKER curves of the nine channels against acurve for random (equiprobable) errors. The random curve was discussed in Section 5.2.Figure 5.8 (a) shows that the x to y channel has characteristics similar to a random noisechannel. This figure also shows that channel x to z behaves like a random noise channelfor BER<10 -5 . Channel x to x does not behave like a random noise channel. Figure 5.8(b) shows that channel y to x behaves like a random noise channel for BER<10-6 .Channel y to y behaves similar to a random noise channel. Channel y to z does notbehave like a random noise channel but its shape suggests it will at low BER (<10 -7).Figure 5.8 (c) shows that channel z to y behaves like a random noise channel (with smalldeviation) for BER<10 -5 . Channel z to x behaves like a random noise channel forBER<10 -7 . Channel z to z does not behave like a random noise channel but the curvesuggests it might at approximately BER<10 -8 .6075I^ITransmitter Voltage (dBmV)(a) (b)-0- y to x-•- y to y—I— y to z1 001^1^1^1^.25^35^45^55^65Transmitter Voltage (dBmV)•^I^'25^35^45^55^65 -10010-10-ct 10-was1010-10-10-77510410-2cd 10-3was10-410-510-610-75 Test Results...25^35^45^55^65^75^85Transmitter Voltage (dBmV)(c)Figure 5.6 BER for lab systemThe results in Figures 5.6-5.8 clearly indicate that different communication linkshave large differences in BER at any given voltage level.615 Test Results...102 10210-2 10-225^35^45^55^65^75^25^35^45^55^65^75Transmitter Voltage (dBmV) Transmitter Voltage (dBmV)(a) (b)25^35^45^55^65^75^85Transmitter Voltage (dBmV)(c)Figure 5.7 BLKER for lab system62-0- z to x-0- z to yz to z-4  Random5 Test Results...102 102CO111 10-0 irasa10-7 10-6 10-5 104 10-3 10-2 10-1 10°BER(b)7Hi 10 6 10-5 10-4 10-3BERy to x•-•-• y to yy to z-4- Random(a)101 010-2 -^1^I^" .".7 • '• 11.10-7 10-6 10-5 104 10-3 10-2 10-1 100BER(c)Figure 5.8 BER vs BLKER for lab systemFigure 5.9 shows results for percent lost packets vs transmitter output voltage.These results are consistent with the results in Figure 5.6.63-0- y to xy to yy to z ..1 • 1 . 1•1•10.1a 10 1a.•102 ^•5 Test Results...102a,. 10 1 1es •1:18 100 •0. -0- x to xx to yx to z10-1 _^^•^I^•^•^I25^35^45^55^65^75^25^35^45^55^65^75Transmitter Voltage (dBmV) Transmitter Voltage (dBmV)(a) (b)1\1 \\\\Z tO ZZ to X"4" Z to y10.1 I^•^1^I^I^•25^35^45^55^65^75Transmitter Voltage (dBmV)(c)Figure 5.9 Percent lost packets for lab systemIn addition to the above tests a Tektronix plotter was connected to the z to zchannel, and the BER was measured and is shown in Figure 5.10. The plotter wasconnected at the receiver, midway between transmitter and receiver, and at thetransmitter. It was stated previously that the distance between transmitter and receiver isapproximately 100 feet (30 meters). This figure shows a degradation of approximately 20dBmV for BER<10 -3 in the normal channel (plotter not attached). Figure 5.11 (a) and5.11 (b) show the frequency spectrum at the output of the receiver bandpass filter before645 Test Results...the plotter was connected and after it was connected, respectively. Figure 5.11 (b) showsthe distortion of the received signal spectrum caused by the connection of the plotter.Figure 5.12 (a) and 5.12 (b) show two receiver time domain waveforms. The bottomtrace is the output of the bandpass filter and the upper trace is the output of thedemodulator. Figure 5.12 (b) shows severe fading in the bottom trace which results in asmaller (in amplitude) signal from the demodulator (upper trace). The plotter was chosenfor this test because of its clear and drastic effect on the transmitted signal. This effectshould not be construed as being indicative of the effects of all electrical equipment. Theamount of noise, attenuation, and fading produced by electrical equipment varies over awide range. The characteristics of the power line and the effects of electrical equipmenton the power line are described in Chapter 2 and the references referred to therein.1 00 ^10410-g 10-3‘,10-10-10-7 ^25^35 45^55-0- z to z normal-4- plotter at Rx-+- plotter at mid-0- plotter at Tx65^75^85^95Transmitter Voltage (dBmV)Figure 5.10 Variation in BER as plotter location is varied655 Test Results...TEKLEVEL^ FREQUEACT^ SPAN/DIVREF^-3008i4 CEN^115KHZ 20KHZ^DOHmom^-6.408^meet 36.2KHZ^ -so497P-40—50——00——70—SO— .111 liff fill III.,_—9°_—100—110——1111 fill flit fillr........o.,1008/^ODB^0-1.8^INT^30HZ^OKHZVERTICAL RF FRED REF VIDEO RESOLUTIONDISPLAY^ATTENUATION^RANGE^DSC^FILTER^BANDWIDTH(a)iTEK497PLEVELREF^-3008M^comem^-14.408 MICRf •115KHZ^SPAN/DIV20KHZ^am35.8KHZ -so—40..---. -so-soL —70—00—90—100—110...,—.... .I I I  I I II III WIlilt fill liffrip ...-..—......1008/^008VERT ICAL IIFDISPLAY^ATTENUATION0-1.8^INTFRED REFRANGE^DSC30HZ^OKHZVIDEO RESOLUTIONFILTER^BANDWIDTH(b)Figure 5.11 Frequency spectrum of output of bandpass filter: (a) without,and (b) with plotter connected665 Test Results...TEKTRONIX 2232AU1=Al.)2..-- 014.8U2`i8l)Y&T= 4 .925kHzSAU::_-\...r,..,^, t^i,'t ,ii^,^1. 0ICI' II,I^tI l' I^Ibi...Y0.1msI,Iili^II1=0.51M51^■II^II0.1n5lili , 11llaU 0.2U SAMPLE(a)TEKTRONIX^22326,U1=AV2--,-- 0ii.0U6V1/&,-=4.925kSAL-7z,----„_, — —i I.,I 01 ,^I, I i^s •i^114 di^i III ■^■^.^i/I.01M5a .irns10U 0.2V SAMPLEDL (T) > = 00.1 ms(b)Figure 5.12 Waveforms of output of demodulator (upper trace) and bandpass filter(lower trace): (a) without , and (b) with plotter connected675 Test Results...Figure 5.13 shows the variation of BER and BLKER during a work day. Figure5.13 (a) shows increases in bit errors at 12:00 pm and at 6:00 pm. Figure 5.13 (b) showsblock errors approximately double at 6:00 pm. The results in Figure 5.13 are consistentwith the trends suggested by Figure 2.6 in Chapter 2.aoa1'1'1 'I' 1•1'11'1•1'02 4 6 8 10 12 14 16 18 20 22 24time (hours)(a)02 4 6 8 10 12 14 16 18 20 22 24time (hours)(b)Figure 5.13 BER and BLKER vs time for x to y channel at 63 dBmV5.5 TESTS ON GENERAL IN-BUILDING ELECTRICALDISTRIBUTION SYSTEMThis test determines the modem's performance parameters across a building. Atransmitting modem is connected to a wall outlet in Room 458, the communicationslaboratory. The receiving modem is moved to different locations throughout the building.The dimensions of the building are shown in Figure 5.14 [22]. The physical distancebetween two modems is not directly proportional to the length of the connecting powerline wire. Because wiring is distributed from a circuit breaker panel on each floor, it ispossible for wall outlets that are within a few feet of each other to be separated by 200feet (60 meters) or more of wiring. Also, because the circuit breaker panel distributessingle phase power from a three phase power source, wall outlets may be supplied fromany one of three phases. The circuit breaker panel on each floor is connected directly tothe General System bus (Section 5.3) via a sub-bus. Table 5.1 contains the names of allthe General and Lab System sub-buses. This nomenclature follows from [22]. Becausephysically adjacent floors do not have the shortest powerline communication path,685 Test Results...transmission among adjacent floors will not necessarily be advantageous over non-adjacent floor transmission. For example, a signal transmitted from the fourth floor to thethird floor would have the following circuitous route: the signal would travel to thefourth floor circuit panel (panel D); propagate down sub-bus D to the basement; travelacross the General System bus to sub-bus C; propagate up sub-bus C to the third floorcircuit panel (panel C); and finally, travel on the third floor to reach the receiver.Floor General System Lab System1 A 12 B 13 C 2,34 D 4Table 5.1 Sub-buses in General and Lab Systems231.2 feetheight=50 feet^BIM^Eapanel C ElMN^Al21feet121.8tf21 Receiver• TransmitterLegendA Room 113B Room 214C Third Floor North Wing StairwellD Fourth Floor East Wing Stairwell'IF 59.4 ll""^E Room 402feet F Room 458 Communications LabWS^NE459.4 feetFigure 5.14 Electrical engineering buildingThe phases for the locations indicated in Figure 5.14 are listed in Table 5.2. It isseen in Table 5.2 that different locations are served by different power phases. Thus,tests encompass both same phase and cross phase conditions.Location Phase.._...^Room 113 ZRoom 214 Y3rd Floor E. Wing Stairwell X4th Floor N. Wing Stairwell X ^Room 402 f—Room 458^. XTable 5.2 Phases of power lines at test locations695 Test Results...5.5.1 Bit Error RateFigure 5.15 shows BER results for a transmitted signal of 10.5 dBmV. Receptionin rooms 113 and 214 produce very similar BER values. BER for 19.2 kbps is 3 x 10 -3and BER for 9.6 kbps is 9 x 10 -4. Reception on the third floor test produces BER valuesslightly better than the lower two floors. The BERs for the third floor stairwell are1 x 10 -3 for 19.2 kbps and 5 x 10 -5 for 9.6 kbps. BER for Room 458 which is the sameroom as the transmitter and on the same circuit breaker (from panel D) produces BERsfor all baud rates less than 10-6 . BERs for baud rates of 4.8 kbps and 2.4 kbps are lessthan 10-6 at all locations.I a^I^I^1:1^I^4^Cl^I^I^0Room Room^Third Floor^Room113^214 North Wing^458StairwellFigure 5.15 BER for 70 dBmV data signal on General System5.5.2 Block Error RateFigure 5.16 shows BLKER results for a 70 dBmV transmitted signal. Almost100% of the blocks for 19.2 kbps received in Rooms 113 and 214 contained errors.BLKER for 9.6 kbps is 32% for Room 113, 53% for Room 214, and below 5% for thethird floor stairwell. BLKER is 0 for baud rates of 2.4 and 4.8 kbps at all locations tested.Figures 5.15 and 5.16 show that the third floor test location has lower error rates thanboth the first and second floor locations. An explanation for this observation is that theThird Floor Stairwell is connected to the same phase (phase X) as the transmitter. Rooms113 and 214 are connected to phases Z and Y, respectively.1.E-021.E-03g 1.E-04as1.E-051.E-061.E-07 O 41 - 2.4 kbps43' 4.8 kbps••- 9.6 kbps4>- 19.2 kbps705 Test Results...^100 ^90 —80 —"IR 7060 —50 —^•^•co 40 —30 — •20 —10 —0 CI I I Q 1 l el I IRoom^Room^Third Floor^Room113 214 North Wing 458Stairwell •■- 2.4 kbpsCI- 4.8 kbps'"- 9.6 kbps*- 192 kbpsFigure 5.16 BLKER for 70 dBmV data signal on General System5.5.3 Percent of Lost PacketsFigure 5.17 shows the percent of lost packets for a 70 dBmV transmitted signal.The percent of lost packets for 2.4 kbps varied from 0 to 5%, and the percent of lostpackets for 19.2 kbps varied from 0 to 42%. Figure 5.17 suggests that same phase andcross phase considerations are important.50^■ 2.4 kbps30 —^ D 4.8 kbps20 —^■^ • 9.6 kbps10— •^•^ * 192 kbps^0Room^Room^Third Floor^Room113 214^North Wing^458StairwellFigure 5.17 Percent lost packets for 70 dBmV data signal on general system5.5.4 SummaryThe results show that baud rates of 2.4 and 4.8 kbps should be used for longdistance communication within a building in the absence of forward error correctioncoding. The baud rate of 19.2 kbps is appropriate for short distance communication, and9.6 kbps should be used for medium distance communication. The results also show thatthe baud rate of 2.4 kbps is the least affected of the four baud rates by cross phase71O0•■ ■•5 Test Results...impairments. The results indicate the need for a modem with some form of baud rateflexibility.5.6 TESTS FOR TRANSMISSIONS FROM LAB TO GENERAL SYSTEMThe transmitter is connected to Oy power line of the Lab System as described inSection 5.4. The receiver is connected to various locations in the General System asdescribed in Section 5.5.5.6.1 Bit Error RateFigure 5.18 shows BER results for a transmitted signal of 70 dBmV. Rooms 113and 402 produced the best and worst BER values, respectively. The BER value for 2.4kbps in Room 402 is significantly higher than values produced from other locations. Itcan be implied from this high BER at low data rates that the power line channel betweenRoom 402 and Room 458 is extremely poor.•■• 2.4 kbps.a 4.8 kbps9.6 kbps-0- 19.2 kbpsRoom Room Third Floor Room Fourth Floor113^214^North Wing 402^East WingStairwell^StairwellFigure 5.18 BER for 70 dBmV data signal on Lab to General System5.6.2 Block Error RateFigure 5.19 shows BLKER results for a transmitted signal of 70 dBmV. TheBLKER values for 9.6 and 19.2 kbps are very high, and exceed 80%. The lowestBLKER for 4.8 kbps is 20% in Room 113. All BLKER values for 2.4 kbps are below 1%except for Room 402 which produced a BLKER of 35%.72LE+00LE-011.E-02g 1.E-03Aa LE-041.E-05LE-06LE-07100907006050^ a403020100Room Room Third Floor^Room Fourth Floor113^214^North Wing^402^East WingStairwell Stairwell•a5 Test Results...-•• 2.4 kbps0 4.8 kbps-•• 9.6 kbps+ 19.2 kbpsFigure 5.19 BLKER for 70 dBmV data signal on Lab to General System5.6.3 Percent of Lost PacketsFigure 5.20 shows the percent of lost packets for a 70 dBmV transmitted signal.At 19.2 kbps, packet loss ranges from 45% to 95%. At 2.4 kbps packet loss is below20%. Figure 5.20 does not show any advantage in same phase transmission relative tocross phase transmission.1004 90IAasa,-g.,80706050400^0•••••••0-•-2.4 kbps4.8 kbps9.6 kbpskiLi3020• a 0. 19.2 kbps10 0 4 00 1---4-11!^I I!I I^fRoom Room^Third Floor Room Fourth Floor113 214^North Wing 402 East WingStairwell StairwellFigure 5.20 Percent lost packets for 70 dBmV data signal on lab to general system5.6.4 Error-free ThroughputFigure 5.21 shows the error-free throughput (as defined in Section 5.1) for a 70dBmV transmitted signal. This figure shows that low baud rates produce higherthroughput values than higher baud rates. Transmitting at 2.4 kbps produces the highestthroughput at receiving locations in Room 113, Room 402, and the fourth floor stairwell.The baud rate of 4.8 kbps produces the highest throughput at receiving sites in Room 214and the third floor stairwell.73S Test Results...30002500 —• 2000 ■^■s. 1500_ 0^01000o^•^ ■5000■-6- 2.4 kbps43- 4.8 kbps9.6 kbps•4 19.2 kbpsI^I^I $1 I^I 1 IRoom^Room Third Floor Room Fourth Floor113 214^North Wing 402^East WingStairwell^StairwellFigure 5.21 Error-free throughput for 70 dBmV data signal on lab to general system5.6.5 SummaryThe results in this section clearly reflect the observations stated in Section 5.5concerning the architecture of the test site's power distribution system. Figure 5.18showed that the BER increased as the physical location of the receiver neared that of thetransmitter. This trend in Figure 5.18 is explained by the fact that the "link" between theGeneral and Lab Systems is located on the first floor. The transmitted signal originateson the fourth floor in Room 458, and propagates over the Lab System to the first floorwhere it crosses the link. The signal continues to propagate from the link throughout theGeneral System towards the fourth floor. Therefore Room 113 is closest to thetransmitter, and the Fourth Floor Stairwell is farthest. The Fourth Floor Stairwellalthough being the closest physically, is in fact the farthest through the power linechannel, and its BER, BLKER, and percent of lost packets results are among the highest(and worst) in the building.746 Conclusions6 Conclusions6.1 CONCLUDING REMARKSThis thesis has pursued the development of an intelligent modem architecture foruse on interbuilding power lines. Modem functionality and cost have been primary designand evaluation considerations.The basic task of any modem is to provide a means of communicating over actual,non-ideal channels. The transmitting part of a modem accepts information from its host,and modulates this information for transmission over a channel. The receiving part of amodem recovers transmitted information from a channel, and sends this information up toits host. This basic limited functionality is insufficient when the modem is used as a"transeiver" under actual network conditions. In an actual network a host is constantlyutilizing the modem's abilities to send and receive data among a number of other hostcomputers. All of the hosts are potentially busy with other tasks, and should spendminimal time in communicating with their modems. An intelligent modem which doesmuch of the processing otherwise done by a host is advantageous over a non-intelligentmodem.The power line modem developed in this thesis is microcontroller-based. Severalimportant revisions and innovations to the earlier preliminary design enabled operation attransmission rates up to 19.2 kbps. A data link layer is provided, to enable extensiveprocessing by the modem itself. This processing includes byte and packet synchronizationand recognition. Judicious division of data link layer functions between modem and hostfacilitate choice of packet length and format, and enable accommodation to a variety ofapplications.Many test results obtained using an industrial building as a test site are documentedin this thesis. The building contains two different systems of three phase powerdistribution. One system distributes electrical power to many laboratory and machine shoprooms. The other system distributes electrical power to lighting fixtures and wall outlets.The purpose of the tests was to determine the modem's performance under actual756 Conclusionsoperational conditions. The tests were used to obtain extensive data to estimate bit errorrate, block error rate, percentage of lost packets, and throughput.To facilitate comparisons an initial test was performed in an isolated location in theLab System. The results indicated that performance on some channels differed fromperformance using the best channel by as much as 30 dBmV.Another test was performed using different locations within the industrial building.The results show that nearness of the receiver to transmitter can be a dominating factor inthe number of transmission errors. Baud rates of 9.6 kbps and 19.2 kbps resulted inrelatively high BER performance for long transmission distances. These two baud ratesproduced bit error rates in the range of 10 -3 and block error rates above 30%. On the otherhand, baud rates of 2.4 kbps and 4.8 kbps produced bit error rates below 10 -6 and blockerror rates below 1%.The test results give an indication of the conditions under which each baud ratewould be appropriate. Rates of 2.4 kbps and 4.8 kbps are relatively slow but provide lowBER and BLKER values even under long transmission paths. Rates of 19.2 kbps and 9.6kbps produce relatively high through rates and acceptable BER and BLKER on shorttransmission paths.The test results also indicate that performance at 19.2 kbps is very sensitive topower line noise. The BLKER may change by as much as 30% over a two hour period.The lower baud rates, especially 2.4 kbps, are not as sensitive as 19.2 kbps to channelimpairments, in our test environment.6.2 SUGGESTIONS FOR FURTHER WORKThere are several potential enhancements to the 19.2 kbps modem. The firstenhancement would double the bit rate of the modem to 38.4 kbps. This rate increasecould be accomplished in one of two ways. The first approach is to replace the currentmicrocontroller with one which operates at twice the speed. In order to operate at 38.4kbps, the modem's clock circuitry would need adjustment. Using the current modulatingcarrier, such adjustment would result in three carrier periods per data bit. The secondapproach is to change the data carrier modulation from BPSK to QPSK. This alternativewould maintain the symbol rate at 19200 symbols per second while doubling the bit rate to38.4 kbps. In order to change the modulation scheme to QPSK major changes would berequired to the modulator and demodulator circuitry. Also, the modem's firmware would766 Conclusionsneed slight alteration. Such enhancements would be appropriate in relatively noise-freeenvironments, for those applications which require high bit rates.Another enhancement which could be made to the modem is to replace themicrocontroller with a digital signal processing (DSP) chip. With this DSP chip thereceived signal could be demodulated using DSP techniques, and the Costas loop would beeliminated. Familiarity with the required DSP chip would be needed in order to determinewhether bit rates above 9.6 kbps can be obtained.A third possible modem enhancement is to implement a forward error correction(FEC) algorithm. The addition of this function could greatly improve the modem's BERand BLKER parameters on noisy links [48].A further enhancement would involve the incorporation of medium access controlas a part of the modem circuitry. Such control is needed, to enable orderly access to anetwork, by otherwise unsynchronized access arrangements. A modified version ofCSMA is an appropriate access control scheme [44]. Polling may be useful for someapplications. An implementation which allows either CSMA or polling could be useful.Preliminary work indicates that the modem described in this thesis can be readily modifiedto accept medium access control circuitry on the modem circuit board.A very large scale integration (VLSI) implementation of the modem would provideseveral advantages. The power consumption would be reduced substantially. The modemwould be smaller and cheaper to produce. Digital components are more reliable than analogcomponents and hence an all-digital BPSK modem would have this added reliability,relatively, over a digital-analog modem.The power line modem could be implemented as an internal personal computer (PC)card. The modem would take its power from the PC backplane and packets could be sentto and from the modem by the host PC using direct memory access (DMA). This approachis very reliable but is somewhat complicated as it requires a thorough understanding of thetechniques needed to design an integrated PC card. Connection to the power line channelwould be accomplished via an external connector.77ReferencesReferences[1] Frank Kwok King Chiu, Intrabuilding Polyphase Power Line Networks, Departmentof Electrical Engineering, University of British Columbia, M.A.Sc. Thesis, Dec. 1985.[2] R. C. Dixon, Spread Spectrum Systems. New York: John Wiley & Sons, 1976.[3] Dimitri N. Chorafas, The Handbook of Data Communication and ComputerNetworks. Princeton, New Jersey: Petrocelli Books, 1985.[4] Peter K. Van Der Gracht and Robert W. Donaldson, "Communication UsingPseudonoise Modulation on Electric Power Distribution Circuits," IEEE Trans. onCommunications, Vol. COM-33, No. 9 pp. 964-974, Sept. 1985.[5] Morgan Hing-Lap Chan and Robert W. Donaldson, "Attenuation of CommunicationSignals on Residential and Commercial Intrabuilding Power-Distribution Circuits," IEEETrans. on Electromagnetic Compatibitility, Vol. EMC-28, No. 4, pp. 220-230, Nov.1986.[6] Morgan Hing-Lap Chan and Robert W. Donaldson, "Amplitude, Width, andInterarrival Distributions for Noise Impulses on Intrabuilding Power Line CommunicationNetworks," IEEE Trans. on Electromagnetic Compatibitility, Vol. EMC-31, No. 3, pp.320-323, Aug. 1989.[7] Paul E. Green, Jr., Computer Network Architectures and Protocols. New York:Plenum Press, 1982.[8] Dimitri N. Chorafas, Designing and Implementing Local Area Networks. New York:McGraw-Hill Book Company, 1984.[9] M. E. Van Valkenburg, Analog Filter Design. Toronto, Ont: Holt, Reinhart &Winston, 1982.[10] Leon W. Couch II, Digital and Analog Communication Systems. New York:Macmillan Publishing Co, Inc., 1987.78References[11] Roland E. Best, Phase-Locked Loops: Theory, Design, and Application. New York:McGraw-Hill, 1984.[12] IEEE Spectrum, Line Upon Line, pp 25, September, 1985.[13] National Semiconductor, Special Purpose Linear Devices, Data Book, LM384, pp 1-26, 1989.[14] Herman J. Blinchikoff, Filtering in the Time and Frequency Domains. New York:John Wiley & Sons, 1976.[15] P. Bowron and F. W. Stephenson, Active Filters for Communications andInstrumentation. New York: McGraw Hill , 1979.[16] William F. Egan, Frequency Synthesis by Phase Lock. New York: John Wiley &Sons, 1981.[17] Vadim Manassewitsch, Frequency Synthesizers. New York: John Wiley & Sons,1987.[18] 8 -Bit Embedded Controllers Handbook, Intel Corporation, 1989, Literature Sales,P.O. Box 7641, Mt. Prospect, IL, 60056-7641.[19] John Ogutu Onunga and Robert W. Donaldson, "Personal ComputerCommunications on Intrabuilding Power Line LAN's Using CSMA with PriorityAcknowledgements," IEEE Journal on Selected Areas in Communications, Vol. 7, No. 2,pp. 180-191, Feb. 1989.[20] William Cheung, "Design and Test of A Bit Error Rate Tester for Power LineModems," Unpublished In-House Document, University of British Columbia, ElectricalEngineering, July 1991.[21] Ron Jeffery, "Hardware Documentation for 9600 BPS Intra-Building Power LineModem," Unpublished In-House Document, University of British Columbia, ElectricalEngineering, Jan. 1990.[22] Simpson and McGregor, "Electrical Plans," Structural, Electrical, Plumbing, andHeating Plans for the Electrical Engineering Building at the University of British Columbia,Thomson, Berwick, and Pratt Architects, May 1962.79References[23] J. J. Stiffler, Theory of Synchronous Communication. Englewood Cliffs, NJ:Prentice-Hall, 1971.[24] Dimitri Bertsekas and Robert Gallager, Data Networks. Englewood Cliffs, NJ:Prentice-Hall, 1987.[25] Bernard Sklar, Digital Communications: Fundamentals and Applications. EnglewoodCliffs, NJ: Prentice-Hall, 1988.[26] Roger M. Vines, H. Joel Trussell, Lois J. Gale, and J. Ben O'Neal, Jr., "Noise onResidential Power Distribution Circuits," IEEE Trans. on Electromagnetic Compatibility,Vol. EMC-26, No. 4, pp. 161-167, Nov. 1984.[27] Kurt H. Mueller and Markus Milner, "Timing Recovery in Digital Synchronous DataReceivers," IEEE Trans. on Communications, Vol. COM-24, No. 5, pp. 516-531, May1976.[28] Jerry J. Ransom and Someshwar C. Gupta, "Performance of a Finite Phase State Bit-Synchronization Loop with and Without Sequential Filters," IEEE Trans. onCommunications, Vol. COM-23, No. 11, pp. 1198-1206, Nov. 1975.[29] Marvin K. Simon, "Optimization of the Performance of a Digital-Data-TransitionTracking Loop," IEEE Trans. on Communication Technology, Vol. COM-18, No. 5, pp.686-689, Oct. 1970.[30] William J. Hurd and Tage 0. Anderson, "Digital Transition Tracking SymbolSynchronizer for LOW SNR Coded Systems," IEEE Trans. on CommunicationTechnology, Vol. COM-18, No. 2, pp. 141-147, April 1970.[31] Marvin K. Simon, "Nonlinear Analysis of an Absolute Value Type of an Early-LateGate Bit Synchronizer," IEEE Trans. on Communication Technology, Vol. COM-18, No.5, pp. 589-596, Oct. 1970.[32] A. Erbil Payzin, "Analysis of a Digital Bit Synchronizer," IEEE Trans. onCommunications, Vol. COM-31, No. 4, pp. 554-560, April 1983.[33] Hisao Yamamoto and Shinsaku Mori, "Performance of a Binary Quantized All DigitalPhase-Locked Loop with a New Class of Sequential Filter," IEEE Trans. onCommunications, Vol. COM-26, No. 1, pp. 35-45, Jan. 1978.80References[34] W. C. Lindsey, "Phase-Shift-Keyed Signal Detection with Noisy ReferenceSignals," IEEE Trans. on Aerospace and Electronic Systems, Vol. AES-2, No. 4, July1966.[35] V. K. Prabhu, "PSK Performance With Imperfect Carrier Phase Recovery," IEEETrans. on Aerospace and Electronic Systems, Vol. AES-12, No. 2, March 1976.[36] V.K. Prabhu, "Imperfect Carrier Recovery Effect on Filtered PSK Signals," IEEETrans. on Aerospace and Electronic Systems, Vol. AES-14, No. 4, July 1978.[37] Brian Markwalter and Christopher Russell, "Consumer Electronics Bus, A RobustCommunications System," IEEE International Conference on Consumer Electronics.Digest of Technical Papers, pp. 42-43, June 8-10, 1988.[38] Ryuji Hamabe, Masashi Murata, Toshinhiko Namekawa, "A Protocol Example onSuper Home Bus System (S-HBS)," IEEE International Conference on ConsumerElectronics. Digest of Technical Papers, pp. 44-45, June 8-10, 1988.[39] J. A. Tritton, "Interactive Home Systems (IHS) - Principles and Applications," IEEEInternational Conference on Consumer Electronics. Digest of Technical Papers, pp. 46-47,June 8-10, 1988.[40] Ryuhi Hamabe, Seiji Hatano, Kenzo Tatematsu, and Kenji Tida, "Comformance TestConcept for the Home Bus System, IEEE International Conference on ConsumerElectronics. Digest of Technical Papers, pp. 48-49, June 8-10, 1988.[41] D. Fezzolo, "Characterization of the Power Line Carrier CommunicationsEnvironment of the American Home," IEEE International Conference on ConsumerElectronics. Digest of Technical Papers, pp. 50-51, June 8-10, 1988.[42] Tetsushi Sakaguchi and Hiromasa Nakatsu, "HBS's Communication Function andRouting Management in Various Network," IEEE International Conference on ConsumerElectronics. Digest of Technical Papers, pp. 52-53, June 8-10, 1988.[43] J. B. O'Neal, "The Residential Power Circuit as a Communication Medium," IEEETrans. on Consumer Electronics, Vol. CE-32, No. 8, pp. 567-577, Aug. 1986.[44] John O. Onunga and Robert W. Donaldson, "Performance Analysis of CSMA withPriority Acknowledgements (CSMA/PA) on Noisy Data Networks with Finite User81ReferencesPopulation," IEEE Trans. on Communications, Vol. COM-39, No. 7, pp. 1088-1096,July 1991.[45] Robert Matyas and Peter J. McLane, "Decision-Aided Tracking Loops for Channelswith Phase Jitter and Intersymbol Interference," IEEE Trans. on Communications, Vol.COM-22, No. 8, pp. 1014-1023, Aug. 1974.[46] William C. Lindsey and Marvin K. Simon, "Data-Aided Carrier Tracking Loops,"IEEE Trans. on Communication Technology, Vol. COM-19, No. 2, pp. 157-168, April1971.[47] Marvin K. Simon, "Tracking Performance of Costas Loops with Hard-Limited In-Phase Channel," IEEE Trans. on Communications, Vol. COM-26, No. 4, pp. 420-432,April 1978.[48] Morgan Hing-Lap Chan, Channel Characterization and Forward Error CorrectionCoding for Data Communications on Intrabuilding Electric Power Lines, Ph. D. Thesis,Department of Electrical Engineering, University of British Columbia, Canada, April 1989.[49] William C. Lindsey and Marvin K. Simon, "Optimum Design and Performance ofCostas Receivers Containing Soft Bandpass Limiters," IEEE Trans. on Communications,Vol. COM-25, No. 8, pp. 822-831, Aug. 1977.[50] United Nations Economic Comision for Europe (UNECE), Electrical Load-CurveCoverage. New York: Pergamon Press, 1979.82A. Hardware SchematicsAppendix AHardware SchematicsThe following schematics detail PSK modem hardware.A .1 MODEM OVERVIEWA.2 CONTROL UNITA.3 BIT SYCHRONIZATIONA .4 MODULATORA.5 COSTAS LOOP DEMODULATORA.6 RECEIVE BAND PASS FILTERA.7 TRANSMIT LOW PASS FILTERA.8 LINE COUPLING, RELAY, AND POWER AMPA.9 POWER SUPPLYA .10 TERMINAL INTERFACE83I taac•0K•aaCd 0 0<QQW••♦• y0•^•K q•K0tt•84cv000000000,c,mv,0N 000000000 0000I-A00xcc VOCl)Cl)etCD CDCl)CO0cv Cl)00ICO CO00000000aaaaaaaaOrN0/00N MWZM0066N60i66N00.0.0.0A0.1^cL-1OrNM MOrNMetOON00rrrr r<<<4<<<<4<<<<< <■■■■■■■ ■///,///rNMVIGON4<<<<<<<0J000N000rrrr\-1711771\OrNMetOWN00000000<<<<<<<<cocr) tt)CON001/7/////OrNMetOCl)OcoCl)OQQNNcoCl)orr IlNI0100rrNM\\\\\\\\0000000(<4<(<4<rNMOON00OrNMetM o N000000 0 0OrNMo,NmItmoncom, ,,, Mr100.4<<<<<<<4<<<<< 1000.>Cl)rNI200"+o— —°ZLLO zco^oOrMZ000,ck,z00orOlq(:)0.ND ICU XIIInp MN0 0^V—.Or ..NO I2^co^A^In 0ri-II-D Nr'^0 ^ mN etD v- XXO0j 0).Z A )^IS'L./co co 0^01 VVV0XVVVVWc,f),t00ClXxV0 CD NN^0-^0700 ,0t10.N.0^f-1-taciaLlatI0O>^0t11 Nr0^Er coDei^ 8ZE J^Nw 0UJ^CCZ^l—z0^15zw u^01 .a< 0)O w^oo 0 occ 0^i oI—^JC.)^2^t rw W k.o J^Z .0^etJ WN^0 EZ^LI'CC 3^(I)0 0 W z^cD.cr -- i^%o "0O Ili^t Ez 1..2^oD a 02 <^002 I 0i0 w E^oo 0^N < 01-•^0^085UIN CCr)^11)^J000000 00.-evr)v0m000000 O001.-O 0^0It^I N If) V fl^aNO r 0 00)C)C4'acoI-C0NC0C0tOthi42zC200N0To08I0I0Mr)O 000PScsiital 10^tI)Ni N00 NI- 1-NINcv^I mo el). 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N/•••••■N N„.■—■N N/*....--..Nrs',...--Ne;:s7-..... ■N\ N0 0^N CI^r N^V II)^M 0^N M^r N^V 01- 1- 1- r T. rA A A• (11N0< <1-^I-x^< ^>I-^0^co7x(C)>cC INto+C)+tN +Din• OfD0 , NCt) OrNe)0000 0000NNNN0 0< NIA0I8788CFe^31Hip5 51616^"7—Ego ^C .14-1(^.Z5 !^5!R°—I(^ 1E-1.5as 5!r1-1(^ 1E-C.5 ■ti1(---I*5^1E-,1" kHI41600^I.1 e- I4IC CVS2r. •44+-'-114sasz agdsziathalsN1•1wlN0N0•.40VI04.1•0.0 Z.-•1^Z6-1 0•0U^-. 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Firmware ListingAppendix BFirmware ListingFollowing is a listing of firmware source code in the modem microcontroller.94ok.a^tis^. 1^tP.• •a^ i 3^-a^.. 4^4:^. gilgagi^1 04.^gii^••1^ t^;164 1' • eV'^g^A^ig V.^.1 Vo^woo°^M/4.1441qt ^2^A^-^t^a44^.4..000^.444JO oAA0^a 4^^2 ^5^V^g^2^.....^0%^.6^0%^O.^*ft^Oft^*ft^..^..^ea^Oa^Oft^O. g• !^V^1 . ...,*4 0^.1P441^\\10^.40+ 1 ^ . tig^0 enII^+^44^V^0^4.^.1 V..z, ....^.. ..^..^Oa Oft^0*0NMWNIVN^00N .....^NO NH: . ^;^r. ;^441.1 p; ,.; 4; ,.; ,.; ,.; ri 1410N ,1 w . r. 0.z ee^il ^.80i^, 1^1ga q^ao Io I^i .--r4 ^edg^4, ..^t.. 20m •5^%^1.5..' ^.4..1^.. .6"^ A•.^1 .i.i.^U^nE^O0..,.. ..z^EEEN. ul^2 4'^a^t gl^il^1 IO/ V1^ICI I^0 I^54^00^I8 ^1 OV^01"1414: I • •^ 1 t^2t8b^h g^I2Mgra^g^ligg2g012 ^3.EI^40100^0^0^NWM^NWM^0^gaix.^.4..0^0^H^0..........44^.............^.^Mtn Ili= 101 . illii : ii a : aii :•• a lin ■nael iF t ;I0-^•^I^...^....^..^.•2N...^•1.44^'^0^iPONWg :1 H^z^.....,..^111^ii^I'•^I^I 70^... 44^00 A^.. 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