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A DC-DC converter suitable for controlling a photovoltaic powered pumping system Passmore, William A. 1989

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A DC-DC CONVERTER SUITABLE FOR CONTROLLING A PHOTOVOLTAIC POWERED PUMPING SYSTEM William A. Passmore B.A.Sc. (Electrical Engineering) University of British Columbia A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ELECTRICAL ENGINEERING We accept this thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA March 1989 © William A. Passmore, 1989 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, 1 agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department The University of British Columbia Vancouver, Canada Date DE-6 (2/88) Abstract A photovoltaic powered pumping system offers an attractive means of supplying fresh water in remote areas not serviced by a utility grid. In order to extract the maximum amount of energy from the solar panels, it is necessary to match the characteristics of the photovoltaic array to the DC motor which drives a pump. A one quadrant DC-DC converter is capable of adjusting the effective load impedance for maximum power transfer under most lighting conditions. Three styles of DC-DC converters used to control the pumping system are de scribed and compared. The voltage tracking style of converter fixes the array voltage at a level considered optimum. The power tracking converter measures, and attempts to maximize, the output power of the photovoltaic array. The microprocessor based power tracking, voltage tracking converter toggles between the two methods of control. Experimental results are included. ii Table of Contents Abstract ii List of Tables v List of Figures v Acknowledgement vi 1 Introduction 1 1.1 System components 2 1.1.1 Photovoltaic Array1.2 Thesis 6 2 Power Converter 7 2.1 Component Matching2.2 Component Ratings 8 2.2.1 Filter Capacitor 9 2.2.2 Power Mosfets 11 2.2.3 Diode 4 2.2.4 Power Supply 5 2.2.5 Heatsink 16 3 Voltage Tracking Converter 18 3.1 Specifications 1iii 3.2 Circuit Description 18 3.2.1 Basic Operation 20 3.2.2 Gate Drive 1 3.2.3 Overcurrent Protection 23.2.4 Thermal Protection '. 21 3.2.5 Protection 22 3.3 Testing and Results 3 3.3.1 Waveforms3.3.2 Efficiency 29 4 Maximum Power Tracking Converter 31 4.1 The Logic Circuit 34.2 Results 4 4.3 Constant Voltage vs. Maximum Power Tracking 38 5 Microprocessor Based Hybrid Control 40 5.1 Logic Circuit 41 5.1.1 MC68HC11 Single Chip Microprocessor 45.1.2 Current Sensing 44 5.1.3 Overcurrent Protection 5 5.1.4 Voltage Sensing 6 5.1.5 Pulse Width Modulation 45.1.6 Gate Drive 50 5.2 Program5.2.1 Maximum Power Tracking . 50 5.2.2 Voltage Tracking 51 5.2.3 Interrupts 5 iv 5.2.4 Changing the Duty Cycle 57 5.3 Results 55.3.1 Voltage Waveform 58 5.3.2 Current and Voltage Measurements 55.3.3 Maximum Power Point 65 6 Conclusions 72 A Assembly Language Program 74 A.l Main Program 76 A.2 A/D Converter Set-Up 8 A.3 Timer Set-Up 9 A.4 Overcurrent Initialization 81 A.5 Read Input Data 2 A.6 Adjust the Pulse Width 84 A.7 Real Time Timer 90 A.7.1 Time of Day Interrupt Service 91 A.7.2 Increment The Time of Day . . 2 A.7.3 Add Time 93 A.7.4 Compare Time 4 A.8 Clear Timer Node 6 A.9 Maximum Power Tracking 97 A.9.1 Change Search Direction 104 A. 10 Current Adjustment 105 A.11 Voltage Tracking RoutineA. 11.1 Adjustment to the Duty Cycle 107 A.12 Read Open Circuit Voltage and Current 109 v A. 13 Calculate Load Voltage and Current 110 A. 14 Change the Duty Cycle in Small Increments 113 A.15 Overcurrent 116 A. 15.1 Overcurrent Interrupt 117 A.16 Output Compare One Interrupt 9 A. 17 Output Compare Two Interrupt 11Bibliography 121 vi List of Tables 2.1 IRF730 Device Specifications: ,- 13 3.2 Voltage Tracking Converter Specifications 20 3.3 Converter Efficiency 35.4 Power Tracking Results 71 vii List of Figures 1.1 Voltage vs Current Curves of a Photovoltaic Array 4 1.2 Current and Voltage vs Power at a Set Insolation Level 5 2.3 DC to DC Converter 9 2.4 Converter Voltage and Current Waveforms 10 3.5 Circuit Diagram of the Voltage Tracking Converter . 19 3.6 Drain-to-Source Voltage 24 3.7 Drain-to-Source Voltage at Turn-off 25 3.8 Gate-to-Source Voltage with the Drain-to-Source Voltage 26 3.9 Current Signal 28 3.10 Experimental Set-up 9 4.11 Block Diagram of Maximum Power Point Tracking Circuit 32 4.12 Array Power vs. Solar Radiation Level 35 4.13 Converter Efficiency 36 4.14 Motor Efficiency 7 5.15 External Logic Circuit 42 5.16 Pulse Width Modulated Waveforms 49 5.17 Simplified Power Circuit 53 5.18 Equivalent Power Circuit5.19 Drain-to-Source Voltage Waveform 59 5.20 Drain-to-Source Voltage Waveform at Turn-off 60 viii 5.21 Drain-to-Source Voltage Waveform at Turn-on 61 5.22 HEXSense Current Waveform 62 5.23 Filtered HEXSense Current Waveform 63 5.24 Current Waveform with Active Overcurrent Protection 64 5.25 Microprocessor Current Measurements vs Metered Current Measure ments 66 5.26 Microprocessor Voltage Measurements vs Metered Voltage Measurements 67 5.27 Calculated Power vs Metered Power 68 5.28 Power, Load Current, and Load Voltage vs Duty Cycle 69 ix Acknowledgement The author would like to express his appreciation to his supervisor, Dr. W. G. Dunford, for guidance and assistance during this project, and to Dr. M. D. Wvong, for assuming the role of acting supervisor during the final stages of this project. The author also wishes to express his gratitude to his father, Mr. C. E. Passmore, for his help and assistance, and to his wife, Carol, for her understanding and support. Gratitude is also expressed to colleagues Nick Jaeger, Ben Giudici, and C.E. Sudhakar for their help. Appreciation is also expressed to the staff of Electrical Engineering, UBC, for their helpful assistance, particularly to Alan Prince and Lloyd Welder. Appreciation is also expressed to Guang Liu for making available data on the photovoltaic array. x Chapter 1 Introduction A photovoltaic-powered pumping system offers an attractive means of supplying water from medium head wells in locations not serviced by a utility grid. The capital cost of a system is higher than a diesel-powered pumping station but the photovoltaic system utilizes a free and inexhaustible energy source, requires very little maintenance, and can be completely automated. Therefore the long term cost and reliability of the system compares favorably with that of a diesel powered station [l]. The regions that could benefit most from such a pumping system can generally least afford it. However, industrialized countries such as Canada are willing to fund such projects. They recognize the benefits that quantities of clean drinking water would allow in the areas serviced by these pumping stations. The Canadian International Development Agency, CIDA, is currently installing test pumping stations in Morroco and is considering many more sites in various locations throughout the world. Dry tropical countries offer particularly attractive sites because of their great need of water, consistently long hours of sunshine, and lack of alternate energy sources. However, there are areas within Canada, such as the prairies or the interior of B.C. which could benefit from such a pumping system. During dry spells, water is urgently needed to feed livestock. Where ground water is present and mains power is not, a photovoltaic-powered pumping system could supply the needed water. 1 Chapter 1. Introduction 2 1.1 System components The photovoltaic-powered pumping system consists of an array of solar panels, a power converter, a motor, and a pump. The photovoltaic array produces a DC voltage and current, therefore, a DC motor and a DC to DC converter are the logical component choices. Some systems do employ an AC motor requiring a DC to AC converter, but for a small or medium sized system the inherent extra complexity and reduced efficiency rule it out. A permanent-magnet DC motor is preferable to a separately-excited or compound-wound machine. The increased efficiency and reduced heating of the permanent mag net machine will justify the higher cost. A l.lkW permanent-magnet BROT motor equipped with samarium cobalt magnets and interpole windings is used for many of the tests described in this report. This motor achieved measured efficiencies as high as 87% and has a long brush life to minimize maintenance. The Mono progressive cavity pump is the pump of choice for this application. It is efficient over a large range of speeds and well depths [2] and is well known at many of the target sites. The pump itself is submersed at the bottom of the well and driven by a shaft running up the length of the well and connected to a motor at the top. This gives the dual advantage of having a dry, easily accessible electric motor and a submersed pump, capable of efficiently delivering water from depths of up to 150m. 1.1.1 Photovoltaic Array The photovoltaic array is the most expensive system component. It is therefore wise to maximize its effectiveness by extracting the maximum amount of energy from its' panels. Chapter 1. Introduction 3 The voltage-current curves displayed in Figure 1.1 were obtained from measure ments performed on the photovoltaic array located on the roof of the Hector MacLeod building at UBC. This array is made up of two parallel strings of five series panels rated at 16V and 35w each. The curves show that the current delivered by the panels increases significantly with the insolation level as compared to the open circuit volt age which increases only a small amount. Consistent with theory [3], the open circuit voltage decreases as the temperature increases, creating intersecting curves. A curve displaying how the power output of the array varies with the array voltage at a particular insolation level is shown in Figure 1.2. Its jagged appearance is due to the limited eight-bit resolution of the measurement equipment. Nevertheless the general shape of the curve is clear. The peak of the power curve occurs on the knee of the corresponding voltage-current curve. The locus of maximum power points for different insolation levels is shown in Figure 1.1 and is approximately a constant voltage, variable current curve. It is apparent that a reasonable approximation to a maximum power tracking converter would be a voltage tracking converter. Such a converter would fix the array voltage at a level considered to be optimum. The voltage-current curve tends to flatten out as the panels age, shifting the opti mum operating voltage. Add to this effect the shift in the open circuit voltage with temperature and a case could be made for using a converter which can adapt to chang ing conditions. More practically, an adaptive converter would be able to automatically locate the best operating point regardless of the array configuration. The need for careful on-site measurements and adjustments would then be eliminated. Chapter 1. Introduction Array Current vs Array Voltage 4.0 Moderate temperature operation — — Higher temperature operation x x x x x Maximum power points 3.0 -CL E < 2.0 -c o 1.0 0.0 0 -I—I—I—I—I—I—I—I—I—I—I—1—I—I—I—I—I—I I I I 1 I I I 40 80 Voltage (Volts) Figure 1.1: Voltage vs Current Curves of a Photovoltaic Array Chapter 1. Introduction 5 Array Current and Power vs Array Voltage 20 40 60 80 100 Voltage (Volts) Figure 1.2: Current and Voltage vs Power at a Set Insolation Level Chapter 1. Introduction 6 1.2 Thesis This thesis covers the design and testing of three different styles of converters. The basic design of the power circuit is common to all three converters and is described in Chapter 2. The device specifications, thermal and RMS ripple current calculations, and heatsink sizing are presented in this chapter. The voltage tracking style of converter is described in Chapter 3. It was built as a prototype for Optima Design Ltd. to be considered for use in Morroco. The control is simple, yet it is a rugged reliable device. The array voltage is set on site by means of a potentiometer which is accessible through the front of the converter. Chapter 4 discusses an analogue maximum power tracking style of converter. It continuously searches for the maximum power point of the array and it does not require any field adjustments, however, the logic circuit is more complicated. A hybrid maximum power tracking, voltage tracking style of converter is presented in Chapter 5. In the maximum power tracking mode it searches for the optimum operating point. Once this point has been found the array voltage is maintained at its optimum level in the voltage tracking mode. Periodically the power tracking mode is reentered to make minor adjustments to the operating voltage. The MC68HC11 makes it possible to use this more sophisticated algorithm without increasing the circuit complexity. It is able to perform the A/D conversions, execute the control algorithms, keep track of timing, and output a series of pulse width modulated output waveforms. Only a few external chips are required to assist the MC68HC11 in controlling the converter. Chapter 2 Power Converter 2.1 Component Matching It is necessary to match the motor, pump, and photovoltaic array characteristics. Matching the D.C. motor to the Mono progressive cavity pump is relatively straight forward. Their torque-speed characteristics must be matched with possibly the aid of a mechanical gearing system. Matching the photovoltaic array to the DC motor-pump combination is more challenging. A large starting current of at least twice the rated value of the machine may be necessary to overcome the static friction of the Mono pump. Once rotating, the motor will draw an almost constant current over most of its speed range for a fixed head. The DC-DC converter illustrated in Figure 2.3, is well suited to matching the pho tovoltaic and motor characteristics. It is capable of increasing the impedance of the load as seen by the source so that it is possible to extract the maximum power from the source for most lighting conditions. This power conditioning is achieved by adjusting the ratio of the on-time to off-time, i.e. the duty cycle, of the power mosfets. During their on state the full source voltage, Vs, appears across the load while the load current, //,, is supplied by the source and the filter capacitor. During the off state the load voltage, VL, drops to zero while the current, maintained by the load inductance, flows through the freewheeling diode. The 7 Chapter 2. Power Converter 8 average load voltage, Vj,, is therefore: VL = t-f-.Vs = d.Vs (2.1) where tojv is the on time, T is the period and d is the duty cycle. If the chopping fre quency and load inductance are high enough the load current remains almost constant with a small ripple component. Figure 2.4 displays the voltage and current waveforms of the load, source, and filter capacitor. In the steady state the average capacitor current is zero, which implies: Is = /L~ = h-d (2.2) The resistance of the load as seen by the source is: Vs Vs R IN — Is h-d VL _ 1 w (2-3) The chopper is in effect a transformer with turns ratio equal to the duty cycle for the purpose of transforming the voltage, current and effective resistance from one side to another. The chopper can therefore increase the load resistance by the factor of d~2 to capture all maximum power points lying above the base load line. 2.2 Component Ratings The reliability and efficiency of the system will depend to a large degree upon the choice of suitable components. Reliability is essential, as in most practical applications the system will be located in remote areas. Efficiency is important, as the photovoltaic panels are expensive. An increase in converter efficiency will usually result in an even greater increase in overall efficiency, as the pump and motor are generally more efficient at higher speeds. Chapter 2. Power Converter 9 Array Connect ion Lo mm. Ro - h DC Mach i ne Figure 2.3: DC to DC Converter 2.2.1 Filter Capacitor The DC-DC input capacitor is essential to fix the array voltage. It accepts current from the array during the off state of the mosfets and delivers current to the load while the mosfets are switched on. The value of capacitance will be determined by the allowable input voltage ripple. Consider an example where a 0.5^ ripple is acceptable with the array delivering 5A of current. The worst case will occur when the switch is either open or closed for almost all of the switching period. If the switching frequency is 20kHz, then a capacitor of at least (2.4) „ q 50/zs x 5A c = 7 = = 500*F' would be required. The capacitor chosen must satisfy the RMS current requirements and withstand the peak open-circuit array voltage. From the current waveforms of Figure 2.4 and assuming a constant load current IL the capacitor RMS current can be Chapter 2. Power Converter 10 £ 200 -+-' "o > o o 0 -ON T •L 5.0 Motor Current 0.0 Supply Current c CD L. D O o ' 'o o CL o o o 0.0 -5.0 "i—i—i—i—i—i—i—i—i—i—i—i—i—i—r 0 50 -\—i—i—i—i—i—i—i—i—i—i—i—i—i 100 150 Time (LLS) Figure 2.4: Converter Voltage and Current Waveforms Chapter 2. Power Converter 11 calculated: rms (2.5) Substituting equation 2.2 for the source current yields: — In*ON i _ *ON rms \ L rp *• rp (2.6) Which has a maximum when: r toN — — (2.7) Therefore: Irms{max) h (2.8) 2 The maximum continuous load current is usually a known quantity, so that the maxi mum continuous RMS capacitor current rating can be easily calculated. 2.2.2 Power Mosfets The logical choice of a switching device for the converter is the power mosfet. They are easily driven by either CMOS or TTL logic chips, switch rapidly, and do not require a commutation circuit. They are robust and are readily available at the current and voltage levels typically encountered in this application. They also can easily be driven at a high enough frequency to ensure a continuous motor current. Although the power mosfet is rugged, the designer must ensure that it is operated within its specified ratings. The ratings of concern are the maximum gate-to-source and drain-to-source voltage levels and the maximum junction operating temperature. In this application it is not difficult to adhere to the maximum voltage ratings. A zener diode inserted between the gate and source prevents the gate voltage from rising Chapter 2. Power Converter 12 beyond its limit. The drain-to-source voltage rating is maintained by choosing a device rated high enough to withstand the open-circuit voltage together with the voltage spike generated as the device is switched off. This spike is minimized by paying careful atten tion to circuit layout and by the use of a free-wheeling diode. For further protection a zener diode may be inserted between the drain and source, or third generation devices used that have a built-in zener diode. The current ratings listed in the device specifications are misleading as they assume a junction operating temperature of 25°C which is impractical. Realistically current ratings of the device are derived from the maximum operating junction temperature of the mosfet. It is safe to force current through the device as long as the junction temperature remains below 150°C. If the device is operated above 150°C premature failure can occur. To arrive at an operating junction temperature for a specified current the on resis tance must be known together with the junction to case, case to heatsink, and heatsink to ambient thermal resistances. As an example consider the IRF730 mosfet chosen for the voltage tracking converter described in Chapter 3. Six parallel devices are used and must be capable of supplying a continuous load current of 12A and a peak current of 22A. The maximum ambient temperature is assumed to be 55° C and a heatsink will be chosen to operate at a maximum of 30°C above ambient, under rated conditions. Table 2.1 summarizes the operating conditions and device ratings. Consider the mosfets turned fully on and delivering 12A of load current. Assume the heatsink temperature is 85°C and the junction temperature is 115°C. The calculated junction operating temperature is: ^ = TH + d*{^)2*RoN(t)*{Tjc + TCH) Chapter 2. Power Converter 13 Table 2.1: IRF730 Device Specifications: Description Symbol Value Ambient temperature TA 55° C Heatsink temperature TH 85°C Junction to case thermal resistance TJC 1.5° C/W Case to heatsink thermal resistance with an electrically insulating silica pad-TCH l.VCjW On resistance at a junction temperature, of 25° C RON{2S°) l.on On resistance at a junction temperature of 115°C RoN{n5°) i.9n = 85°C + (2.CL4)2 * 1.90 * [1.5°C/W + 1.7°C/W) - 109.3°C (2.9) where n is the number of parallel mosfets. This temperature is below the assumed value of 115°C used to determine the on resistance of the mosfets. It is also well within the safe operating temperature of 150°C. The power that must be dissipated by the heatsink due to losses within the mosfets for the above operating conditions is: Pics = 6 * (2.(L4)2 * 1.9f] = 45.6W (2.10) Consider now the converter providing peak load current, 24A, at a duty cycle of 25%. The same assumptions are made as above. The junction operating temperature would then be: = 85°C + 0.25 * (4.04)2 * 1.9H * (1.5°C/W + l.VC/W) = 109.3°C (2.11) Chapter 2. Power Converter 14 with a loss of: Ploss = 0.25 * 6 * (4.0.4)2 * 1.9H = 45.6W (2.12) The mosfets are operating at a safe temperature. The array current would be 6A for these conditions and it is unlikely the duty cycle would exceed 25% as most array configurations would not be able to deliver such a large current. The load current is prevented from exceeding 24A by the current limit. Note that for these conditions there are also losses in the diode to consider. 2.2.3 Diode A freewheeling diode is essential when switching inductive loads such as a DC motor. Even a resistive load will usually contain enough stray inductance to produce an exces sive voltage spike as the mosfets are switched off if the freewheeling diode is removed from the circuit. A fast or ultra fast recovery diode is necessary to cope with the fast switching speed of the mosfets. If a slow diode is used a large reverse recovery current spike will be generated as the converter is switched on, which may damage the mosfets. This current spike also creates noise which may interfere with the operation of the logic circuits. Even when a fast recovery diode is used, it is often wise to slow down the mosfets turn-on time in order to reduce noise levels. The converter will need to supply maximum current at a low duty cycle when the DC machine is being turned on to overcome starting torque. The diode, therefore, must be able to handle the maximum current on a continuous basis. For example, for the converter described in Chapter 3, a current rating of 30A should be adequate. The diode should also be rated at 400V to be compatible with the mosfets. The MUR3040PT ultra fast recovery diode in a T0-218AC package is the device of choice. This device is Chapter 2. Power Converter 15 made up of two parallel 15A, 400V diodes in the same package, with a recovery time of 50ns. The diodes are matched and thermally coupled, enabling parallel operation of the two diodes. If the diode is operated under the same conditions used in equation (2.11) the power loss and operating junction temperature would be: Pi0„ = {l-d)*IL* VON = 0.75 * 2AA * 0.75F = IZ.SW (2.13) m _ Ploss /rr, „, , Tj = TH + *{TCH + TjC) n 13 5W = 85°C + — * (1.7°C/W + l.5°C/W) = 106.6°C (2.14) 2.2.4 Power Supply The logic circuit requires its own power supply. The most practical way to derive this supply is directly from the photovoltaic array. The array voltage will vary at different installations and under different operating conditions while the logic voltage must remain constant. The current requirements of the logic supply are modest, approximately 100mA, so that a simple supply is adequate. The simplest supply would consist of a resistor charging an output filter capacitor whose voltage is set by a reference zener diode. At higher input voltages excess current would be drained through the zener diode. The power supply loss increases with the square of the input voltage over its operating range. This loss is high but may be acceptable for certain applications. The supply can be made more efficient by replacing the dropping resistor with a mosfet. The effective resistance of the mosfet is automatically adjusted to maintain a constant output voltage as the input voltage varies. The output voltage level is Chapter 2. Power Converter 16 maintained by the mosfet three volts below the value set by a reference zener diode attached to the gate. Only as much current as is necessary to maintain the source voltage is supplied resulting in a net loss which is directly proportional to the input voltage. This form of supply is used by the converter described in Chapter 3 and is shown in detail in Figure 3.5. The power loss in the logic supply when the array is operating at 250V is: P,0„ = 250V x lOOm.4 = 251V (2.15) A more sophisticated and efficient switched mode power supply could be used. However the extra circuit complexity would not justify the power savings achieved as only a small logic current is required. The added complexity would reduce the overall circuit reliability as well as increase costs. Once a steady output voltage is established a single, dual or triple supply can be derived. For example the analogue maximum power tracking circuit of Chapter 4 requires a 15V, 5V and —7V supply. A linear voltage regulator is used to provide the 15V and 5V supplies from the 18V supply. The negative supply is derived with the aid of a switching regulator and a few external components. 2.2.5 Heatsink Proper sizing of the heatsink is essential for reliable operation. The heatsink must be able to maintain the temperature of the active devices within their safe operating region over a large range of ambient temperatures. To calculate the heatsink size the power being dissipated must be known along with the temperature rise above ambient which can be tolerated. It is assumed the device is operated in the shade and with its fins positioned vertically. From the power losses calculated in equations (2.10) and (2.15) it is determined the Chapter 2. Power Converter 17 heatsink used in the sample converter may have to dissipate up to 70W under normal circumstances. From equations (2.11), (2.12) and (2.15) it can be seen that the losses under peak current conditions can reach as high as 84W. However, this is abnormal and peak current should only be delivered on a temporary basis. If peak current is supplied for a prolonged period, it could be expected the heatsink would warm up causing a thermal cutout to shut down the converter. It was decided while making thermal calculations that a 30°C temperature rise between the heatsink and the environment could be tolerated. This implies a heatsink with a thermal coefficient of 0.43°C/W is required. There are many shapes and sizes of heatsinks available. A suitable heatsink for this application is heatsink #2001 from AHAM TOR INC., California. Chapter 3 Voltage Tracking Converter 3.1 Specifications A DC-DC converter is to be designed for use with photovoltaic arrays of up to two kilowatts. The converter attempts to maximize the power output of the array by optimizing the operating voltage. The converter is built to be both efficient and reliable. The power mosfets are derated to ensure a long life and reduce overall losses. A high chopping frequency minimizes the ripple voltage, ripple current and harmonic motor losses. An over-temperature cut out is built into the converter to turn it off if the motor remains stalled for a prolonged period of time. Table 3.1 summarizes the device specifications. 3.2 Circuit Description The voltage tracking converter approximates a maximum power tracking converter by fixing the array voltage at a point considered optimum. This design is based on a circuit developed and tested by Dr. W.G. Dunford and Dr. P. Ward. The logic adjusts the duty cycle of the power mosfets according to the value of the array voltage. If the voltage is too high the duty cycle is increased to bring the voltage down and vice versa. The circuit diagram is detailed in Figure 3.5. 18 Chapter 3. Voltage Tracking Converter 19 CY LJ 'CY Lu L> 21 O O CJ o o CJ o i— CO z: o u (Y O l— O C y z: ! + A CS ISJ — CY CY Figure 3.5: Circuit Diagram of the Voltage Tracking Converter Chapter 3. Voltage Tracking Converter 20 Table 3.2: Voltage Tracking Converter Specifications. Electrical Specifications: Power Rating 2.0kW Efficiency @ 2kW 0.90 Input Operating Voltage 75V - 250V Input Current up to 12A Output Voltage 30V - 240V Continuous Output Current 14A Peak Output Current 24Chopping Frequency 20kIIz Operating ambient temperature —10°C to +55°C Relative humidity 0 to 100% Automatic thermal shutdown External shutdown through a normally open switch contact 3.2.1 Basic Operation The logic senses the array voltage via an adjustable resistive voltage divider. This signal is inverted via an LM358 inverting operational amplifier which pivots around a 3.1V reference with a gain of minus one. The resultant signal is amplified by the internal opamp of the NE5561 PWM with a gain of minus 100 to form the reference voltage which determines the duty cycle. One volt corresponds to a 0% duty cycle while 5V corresponds to a 98% duty cycle. The chopping frequency is set by the RC oscillator of the NE5561 to approximately 20kIIz. The chopped output of the NE5561 PWM is buffered and then used as the gate drive signal. Chapter 3. Voltage Tracking Converter 21 3.2.2 Gate Drive A 4041 buffer is placed between the 5561 PWM chip and the gate drive. The comple mentary NFET-PFET pair which forms the gate drive requires a little more switching current than the PWM can provide. Also the extra buffer helps to isolate the PWM from the power supply. A resistor is placed in series with the positive supply of the complementary NFET-PFET pair to limit the amount of gate current which can be supplied. This slows down the switching speed of the mosfets and limits the reverse recovery current through the devices. The series resistor should be between 290 and 470 to be effective. There is no problem switching the mosfets off as fast as possible, so it is not necessary to place resistance in the ground line of the complementary FET pair. 3.2.3 Overcurrent Protection Cycle by cycle overcurrent protection is provided by feeding a voltage signal propor tional to the current through the mosfets to pin 6 of the NE5561. If this voltage rises above 0.6V the NE5561 output is forced high and turns off the mosfets for the remain der of the cycle. This current signal is derived from the voltage across the mosfets. A resistive voltage divider feeds a portion of the mosfets on-state voltage to the NE5561. The high off-state voltage is ignored by switching on an NPN transistor, effectively shorting the segment of the voltage divider that provides the current signal. 3.2.4 Thermal Protection The internal temperature of the converter is monitored with the aid of a thermistor. If the temperature rises beyond the limit as indicated by the 6.2V reference zener diode the converter will be shut down. Hysteresis is built around the operational amplifier, Chapter 3. Voltage Tracking Converter 22 acting as a comparator, to give the converter time to cool down before the converter is restarted. Resistance values for the NTCl, Rll, R15, and R22 are chosen such that the converter is shut down at 85°C and restarted at 65°C. The sealed box which encloses the converter forms part of the heatsink so that in the steady state the internal temperature will approximately equal the temperature of the heatsinks. Also resistors and integrated circuits mounted on the printed circuit board itself produce heat that should raise the operating temperature slightly above the heatsink temperature. All electronic components must be rated to operate in an ambient temperature of up to 85°C. The mosfets, diode and capacitor are rated to operate at this high temperature. However, all the integrated circuits used in the prototype were not. The LM358 operational amplifier should be replaced with an LM258 opamp and the NE5561 PWM should be replaced with the SE5561 PWM. These devices are rated for use over a wider temperature range and are only moderately more expensive. 3.2.5 Protection Some extra components have been added to the circuit to protect the power devices: • Two pairs of two zener diodes in series have been placed in parallel with the power mosfets to protect against overvoltages caused by any stray circuit inductance. Two pairs are used instead of one to maintain circuit symmetry. Two zeners are placed in series in each branch to form a high enough voltage rating. • A O.lf! resistor is placed between source and ground of each power mosfet. This small resistance enhances the current sharing capabilities of the mosfets during switching thereby minimizing the effects of varying device current gains. Chapter 3. Voltage Tracking Converter 23 • A 16V zener diode is placed across the power supply. If the resistors provide more logic current than required, then the excess current is is bled off by the zener diode. 3.3 Testing and Results To simulate a solar array source a variable DC source was used in series with a variable resistance. This would produce a linear voltage, current curve rather than the humped curve of Figure 1.1. This setup is however adequate to demonstrate the operation of the converter. 3.3.1 Waveforms The converter was first tested with a load made up of a 11.5mH inductor in series with a variable resistance. The converter was run at various input voltages ranging between 50V and 250V and with input currents between OA and 12A. Output voltages ranged between 0V to 200V and output currents between OA to 24A. The drain to source voltage waveform is displayed in Figure 3.6. A voltage spike is evident during turn off. This is due to stray circuit inductance which is impossible to completely eliminate. The magnitude of the spike is approximately 70V and can easily be tolerated as the mosfets are rated 150V higher than the maximum input voltage. A magnified view of this spike is shown in Figure 3.7. It is seen here as a damped sinusoid with a natural frequency of 40MHz. The mosfets are protected with zener diodes which should clamp the voltage appearing across them at 350V. Even at conditions of maximum input voltage and peak output current the voltage spike across the mosfets did not approach the 350V limit. The voltage across the mosfets drops very rapidly, even though the rise of the gate Chapter 3. Voltage Tracking Converter 24 Figure 3.6: Drain-to-Source Voltage \1N : 200V VOUT : 123V 50V/div. I,„ : 7.7A lour • 12.1A 10.0/is/div. Chapter 3. Voltage Tracking Converter 25 VIN : 202V IiN : 7.52A YOVT • 125V IOUT : 11.95A 50V/div. 0.05/iis/div. Chapter 3. Voltage Tracking Converter 26 Figure 3.8: Gate-to-Source Voltage with the Drain-to-Source Voltage Top trace Gate to source voltage: 5V/div 2.0^s/div. Bottom trace.... Drain to source voltage: 50V/div 2.0/is/div. WIN • 200V WOVT : 35V I/* : 1.7A lour : 9.3A voltage is limited by a series resistor . The drain to source voltage together with the gate voltage is shown in Figure 3.8. The gate voltage takes approximately 0.5/xs to rise to near its' peak value, however the drain to source voltage falls so rapidly that it appears instantaneous. There is a delay of about 0.15/us from the instant that the gate voltage starts to rise and the drain to source voltage falls. This is because the drain to source voltage is constrained to remain high until the mosfets are conducting the full load current. The rate at which current through the FET can rise is limited by the current gain of the device during switching. Limiting the gate current therefore limits the rate of rise of the current through the mosfet. This slows down the switching process and limits the peak recovery current through the device. Chapter 3. Voltage Tracking Converter 27 The signal used by the PWM to measure the current through the mosfets is shown in Figure 3.9. The displayed signal is turning off the mosfets on a cycle by cycle basis as the voltage exceeds the threshold level. The level at which the overcurrent protection engages is determined by the relative resistance values of R32, R33, and R34 in the voltage divider of Figure 3.5. The PWM only samples the current signal when the mosfets are turned on. The signal voltage during the mosfets off-state is ignored even though it may be higher than the cutoff threshold value. Also during the switching intervals a considerable amount of noise is present in the current signal. However, the operation of the overcurrent detector is not adversely effected. Figure 3.9 shows the current signal dipping down when the mosfets are first turned on. The signal grows as stray circuit capacitance is charged up through the resistive divider network. When the voltage builds up to the internal reference level of the NE5561, the mosfets are shut off creating the noise spikes visible on the waveform. The shorting transistor, Q2, is turned on when the mosfets are turned off preventing the current signal from going excessively high. The over-temperature protection was tested by operating the device with a peak load current for a prolonged period of time. The converter shut itself off when the internal temperature reached approximately 85DC and automatically restarted when the temperature cooled to 65"C. The slow-start circuitry on the NE5561 and the overcurrent protection prevented excessive current from flowing through the converter as it was restarted. Chapter 3. Voltage Tracking Converter 28 Figure 3.9: Current Signal VJN : 223V VOVT • 84V 20mV/div. lIN : 7.1A lour • 18.5A lO^s/div. Chapter 3. Voltage Tracking Converter 29 Figure 3.10: Experimental Set-up 3.3.2 Efficiency The converter was also tested by driving a 2.5hp DC motor which in turn drove an induction machine operating as a generator. The generator supplied power to a resistive three-phase load. The generator load could be adjusted in order to vary the loading of the DC machine. Figure 3.10 shows the experimental set up. No problems were experienced by the converter driving the DC machine. The overcurrent protection operated successfully during machine start up and the starting torque was easily overcome. Measurements made to determine the converter efficiency are displayed in Table 3.3. The peak efficiency of the converter is about 96% which exceeds the design specifications. Chapter 3. Voltage Tracking Converter 30 Table 3.3: Converter Efficiency Duty Input Input Input Output Output Output Efficiency. Cycle Voltage Current Power Voltage Current Power n Resistive and inductive load: 0% 15mA 180V 2.7W OA 0V OW 0 14% 198.5V 1.4A 278W 30.0 V 6.8A 204 W 0.734 28% 199.8V 3.55A 709.3W 55V 12.2A 671W 0.946 40% 201.5V 7.3A 1471W 80V 18A 1440W 0.978 9.3% 200.2V 0.22A 44W 18.3V 1.9A 34.8W 0.789 25% 200.5V 1.3A 261W 49V 5.1A 250W 0.958 47% 201.5V 4.57 A 921W 93.5V 9.5A 888W 0.964 66% 204V 8.95A 1826W 133V 13.25A 1762W 0.965 71% 205V 10.0A 2050W 141V 14.0A 1974W 0.963 76% 206.5V 4.44A 917W 155V 5.7A 883W 0.963 90% 208V 6.4A 1331W 187V 6.97A 1303W 0.979 95% 209V 7.4A 1547W 202V 7.53A 1521W 0.983 Speed Input Input Input Output Output Output Efficiency r/min Voltage Current PoWer Voltage Current PoWer DC Motor load: 1000 141V 4.45A 627W 98.5V 6.1A 601W 0.958 1000 141V 5.18A 730W 99V 7.1A 703W 0.962 1000 141.5V 7.59A 1074W 98V 10.5A 1029W 0.958 1500 190.8V 2.14A 408W 137V 2.74A 375W 0.920 1500 191.2V 3.60 A 688W 138V 4.75A 655W 0.952 1500 192.1V 5.89 A 1131W 142V 7.68A 1090W 0.964 1500 200V 9.1A 1820W 145V 11.86A 1720W 0.945 2000 215.6V 2.45A 528W 188V 2.18A 410W 0.776 2000 216V 3.21A 693W 187V 3.6A 673W 0.971 2000 242.8V 4.1A 995 W 185V 5.0A 925W 0.929 2000 246V 6.85A 1685W 186 V 8.42A 1566W 0.929 2000 248.6V 9.46A 2352W 187V 12.1A 2262W 0.962 Chapter 4 Maximum Power Tracking Converter A true maximum power point controller that will automatically adjust to different input conditions is described in this chapter. This converter is designed to operate at power levels of up to one kilowatt and was tested using the facilities at B.C. Hydro-Research, Surrey, B.C. 4.1 The Logic Circuit The control circuit illustrated in the block diagram of Figure 4.11 provides true max imum power point tracking. The controller adjusts the conversion ratio to maximize the array voltage and current product. The array voltage is sampled directly using a resistive voltage divider. The array current, however, is derived from the voltage across the mosfet. During its on state, the mosfet appears as a resistive element. The average on state voltage is proportional to the current through the device which is in turn proportional to the steady state array current. Changes in the mosfet resistance with temperature are unimportant as only relative changes in the current signal are of interest and not its absolute value. The average array current and voltage signals are multiplied using an analog mul tiplier to produce an output power signal. A low frequency (3 Hz.) clock latches the power level into the sample and hold unit. The controller then changes the conversion ratio of the DC to DC converter. At the end of the cycle the instantaneous power level is compared with the sampled power level. 31 er 4. Maximum Power Tracking Converter Mosfet ««s Got i ng SIgnoI Pulse Vidth Modulo t or Ronp Generotor Flip Flop Mu11 i pIier Sonple ond Hold Conporotor Low Frequency Clock Figure 4.11: Block Diagram of Maximum Power Point Tracking Circuit Chapter 4. Maximum Power Tracking Converter 33 If the power level has increased, another change is made to the conversion ratio in the same direction. If the power level has decreased, the change in the conversion ratio is made in the opposite direction. When the converter is first switched on, the conversion ratio is set to its minimum value and climbs the hill to the value corresponding to the maximum power point. In the steady state, the duty cycle toggles around this optimum value. Two sets of low frequency timing pulses are required to synchronize the controller. Both pulses are very short, approximately 10/xs, with the second pulse immediately following the first. The first pulse is logically anded with the power level comparator output and then used as the clock input to a JK flip-flop. When the power level is decreasing, the comparator output goes high, allowing the timing pulse to propagate through to the flip-flop, causing its outputs to toggle. The complementary flip-flop outputs are each logically anded with the second timing pulse. One of the resulting signals has its polarity reversed. Once every cycle, there is either a positive or negative pulse generated, depending on the state of the flip flop outputs. These positive and negative pulses are then integrated and scaled to form the input of a pulse width modulator. As the pulses are narrow, the duty cycle is changed quickly at the beginning of each cycle. For the rest of the cycle the duty cycle is held constant while the motor and control circuit transients decay. The instantaneous power signal then represents a steady state value and a true comparison can be made with the last sampled power level. Some additional features include over-current protection which is provided on a cycle by cycle basis. If the measured current signal rises above a threshold level, a flip flop is set, turning off the power mosfet. The next gating signal resets the flip flop Chapter 4. Maximum Power Tracking Converter 34 allowing the power mosfet to be turned on again. The converter is also capable of being shut down if the motor overheats. The temperature signal provided by the DC motor can disable the gating signal as it switches from an open to a short circuit, or vice versa. 4.2 Results The hydraulic test equipment consisted of a 200-litre storage tank in which various Mono progressive cavity pumps could be inserted. The pump is discharged into a pressure tank regulated by a back pressure sustaining valve. By adjusting the pressure, well depths ranging between 10 to 65 meters can be simulated. Water from the pressure tank is discharged back into the storage tank. The power output of the pump is calculated by multiplying the water flow rate with the back pressure. The electrical system consisted of the panels, converter and motor. The photovoltaic array consisted of two parallel strings of 11 panels, producing a maximum power of 770 watts and nominal voltage of 165 V. The array was kindly supplied by British Columbia Hydro and Power Authority, Research and Development Division, which also provided laboratory space. Power from the array was routed through the DC - DC converter to a Brot 1.1 kW permanent magnet DC motor which directly coupled to the Mono pump. The system was tested at various insolation levels and well depths. The greatest system losses occur during the conversion of sunlight to electricity, which proceeds at an efficiency of 0.083. A large loss is inevitable due to the physics of the conversion process. The converter successfully altered the conversion ratio to track the maximum power point of the array for most light conditions. Figure 4.12 displays the power developed Chapter 4. Maximum Power Tracking Converter BOO 35 i i i i i i i i I i i i i i i i i i | i i i i i i i i i | i i i i i i i i i 300 500 700 900 1100 Solar radiation (watts/m2) Figure 4.12: Array Power vs. Solar Radiation Level by the array for various levels of solar radiation. The converter was also able to deliver enough current to develop the required starting torque at all simulated well depths. The efficiency of the converter, as calculated by the output converter power divided by input array power (as shown in Figure 4.13), ranged from 0.75 to 0.91 with an average of 0.84. Losses were incurred in the power mosfets, the freewheeling diode and the logic power supply. The voltage tracking converter of Chapter 3 turned out to be slightly more efficient because it used six parallel power mosfets of a similar rating to the two used here. Also the voltage tracking converter used a more efficient power supply. The Brot permanent magnet DC motor operated with an average efficiency of 0.82. The efficiency ranged from 0.78 to 0.87 and tended to increase with motor speed as shown in Figure 4.14. Harmonic motor losses were small as the ripple current was kept Chapter 4. Maximum Power Tracking Converter 36 100 c O i_ d> Q. 90 • • o c |o <D i_ d) i_ > c o o 80 LXHD350 kPa head CO00O450 kPa head HXMKK 545 kPa head 70 60 | i i i i i i i i i | i i i i i i i i i | i i—r 500 1000 1500 Motor speed (r/min) n—i—i—i—r 2000 Figure 4.13: Converter Efficiency Chapter 4. Maximum Power Tracking Converter 37 100 v_ O 90 c 0) o a o 80 c 'o 70 + i l I I I I 350 kPa head COD00 450 kPa head x x x x x 545 kPa head DE 60 I i i i i i i i i ' I ' ' 1 ' 1 1 ' ' 1 ' ' ' 500 1000 1500 Motor speed (r/min) i i i 2000 Figure 4.14: Motor Efficiency Chapter 4. Maximum Power Tracking Converter 38 below 0.1A at the 20kHz chopping frequency. The efficiency of the Mono pump also increased with speed up to approximately 1600 r/min as shown in Figure 4.14. Both the increased mechanical vibrations in the driveshaft and the increased hydraulic resistance at larger flow rates reduce the pump efficiency at higher speeds. 4.3 Constant Voltage vs. Maximum Power Tracking A simpler constant voltage tracking converter could perform many of the same func tions as the maximum power tracking converter described in this chapter. It does not, however, provide the flexibility of the maximum power tracking system. The volt age tracking converter must be carefully adjusted at each individual installation while the maximum power tracking circuit automatically determines the optimum operating point. It also tracks the changes to this optimum operating point as the ambient tem perature and insolation levels change with the time of day and the seasons. A small increase in the power extracted from the array (possibly 5%) is multiplied to form an even greater overall efficiency as the power converter, motor and pump all operate with a greater efficiency at higher speeds and power levels. The maximum power tracking system may, however, have difficulty tracking fast changes in the insolation level. The converter assumes a constant or slowly varying insolation level. Changes in the observed power levels are assumed to be the result of a change to the conversion ratio, and not the result of a change in the insolation level. Normally, insolation levels change slowly and the converter is able to accurately track the maximum power point. However, occasionally weather conditions will cause rapid transitions in the light levels. It senses the changing power levels and attributes it to the last conversion ratio change. The conversion ratio then drifts away from the Chapter 4. Maximum Power Tracking Converter optimum value until the insolation level stabilizes. Chapter 5 Microprocessor Based Hybrid Control There are certain merits to using either a voltage tracking or a maximum power tracking control scheme. A voltage tracker has a simple control algorithm that is not affected by fast variations in insolation levels. A power tracker is self adjusting and can optimize the output of the array as the characteristics of the photovoltaic panels change with temperature and time. A hybrid power tracking, voltage tracking converter retains the advantages of both control schemes. When the converter is first turned on, it enters the power tracking mode. The voltage corresponding to the maximum power point is located and retained. The converter then switches to the voltage tracking mode where the array voltage is held constant. Periodically the power tracking mode is reentered to make fine adjustments to the optimum operating voltage. An analogue control circuit which could perform all of these functions would be quite complex. However, a digital implementation of this control scheme using a single chip microprocessor is feasible. Most of the logic functions can be implemented in software resulting in a low chip count. The system is flexible and additional functions can be incorporated to handle faults or special conditions as more sophisticated software is developed. 40 Chapter 5. Microprocessor Based Hybrid Control 41 5.1 Logic Circuit The majority of the control logic is handled by the Motorola MC68HC11 single chip microcomputer. It reads the photovoltaic array voltage and current signals, keeps track of timing, regulates the duty cycle and outputs a pulse-width-modulated waveform. Some external logic is required to support the MC68HC11 and to drive the power mosfets. Figure 5.15 displays the circuit diagram of the external logic and gate drive chips. 5.1.1 MC68HC11 Single Chip Microprocessor The MC68IIC11 incorporates the following features which make it possible to perform these multiple tasks: • An 8-bit central processing unit, CPU, containing two internal 16-bit index reg isters, X and Y, one 16-bit stack pointer, S, a 16-bit program counter, two 8-bit accumulators,A and B, and a condition code register, CC. The two 8-bit accumu lators can be concatenated into one 16-bit register, D. The CPU can be operated with a full 64K bytes of external memory or in the single chip mode. In this application the single chip mode of operation is selected. • There are 8K bytes of read only memory, ROM, available to store the resident program and also 512 bytes of EPROM and 256 bytes of RAM to store variables and constants. • A 16-bit free-running timer is available for use by the program. The external lines associated with the timer are attached to port A. Some timer features used in this application include: er 5. Microprocessor Based Hybrid Control VA cc A PA6 PBI 0C2 ON A A 0C3 0C4 PA5 PA4 of? NOS PBC ^CC NCS A NCS ' 15V Vcc CLR2 D2 CIKZ PR2 OJ 05 7474 DUAL D nIP-FLOP CLR1 01 CLkl PR I 0) 5T I T PE2 A/D 0 luf SENSE PIN<-KELVIN GN0<-CAIE SIGNAL G Vcc = 5V PAO. PA6: MC68HC!1 I/O Port Pins NQS: Noma I 1 y Dpen Switch PBO PB6: MC68HC11 I/D Port Pins NCS: Noma 1 1 y C losed Switch PEO. . PE3: MC68HC1I A/D Input Pins Figure 5.15: External Logic Circuit er 5. Microprocessor Based Hybrid Control 43 — Five output compare registers attached to external pins PA3 through PA7. The voltage levels on these pins can be forced high or low, when the free-running timer count equals the number stored in the corresponding compare register. Interrupt requests can be optionally generated upon a successful output compare. — A periodic real time interrupt can be generated at various rates. This inter rupt can be used to update a real time clock. — Some other features include a pulse accumulator, which can count external events or be used as the external timer clock, and an input capture register which can hold the timer count when a transition is sensed on an external pin. There are two eight-bit general purpose ports, B and C, available. Port C can be used for input or output while port B is strictly an output port. Ports A, D, and E, which are set aside for the timer, A/D converter, and communications interface can also be used as general purpose I/O ports when the special functions attached to these ports are not being used. A Serial Peripheral Interface, SPI, and Serial Communications Interface, SCI, are built into the chip and connected to port D. These interfaces are used to communicate with peripheral devices or external systems and have various modes of operation. An eight-bit analogue-to-digital, A/D, converter is included with four, or in some packages eight, input channels and connected to port E. The input channels can be individually selected or all four channels can be read consecutively. The conversions can take place continuously or under program control. Chapter 5. Microprocessor Based Hybrid Control 44 • Two non-maskable and fifteen maskable interrupt sources are possible. The inter rupts obey a fixed hardware priority structure to resolve simultaneous requests. However, the priority of a maskable interrupt source can be raised under program control. Maskable interrupts are disabled by setting the Enable bit of the CC register. Internally generated interrupt requests also have a local mask. Each in terrupt source has a corresponding interrupt vector containing the address of the interrupt routine. The CPU responds to an active request by saving the register state on the stack, setting the enable bit, and jumping to the address indicated by the interrupt vector. The power requirements of the MC68IIC11 are modest making it attractive for high efficiency, low power applications. It requires 20mA at 5V in the run mode, and even less in the special wait or stop modes. 5.1.2 Current Sensing A current signal is derived with the aid of a current sensing power mosfet. This device has identical characteristics to the regular power mosfets, except the source of a few transistor cells are isolated and connected to a separate external pin. Under ideal con ditions, the current diverted to the current sense pin would be the ratio of the number of isolated cells to the total number of parallel cells in the power device. A separate Kelvin source pin is provided to increase the accuracy of the current measurement. This pin is internally connected to the source of the power device and does not share the metalization, bonding wire, and pin resistance with the external source pin. A virtual earth sensing circuit is used to amplify the current signal. This method is superior to a resistor sensing circuit in terms of speed, accuracy and noise immunity. However, the resultant signal is inverted and a second operational amplifier is required Chapter 5. Microprocessor Based Hybrid Control 45 to produce a signal of the correct sign. This current signal is suitable to be used as a reference for the cycle by cycle overcurrent protection. The current waveform is filtered to provide the A/D input pin, PE2, with a signal proportional to the average current through the power mosfets. In the steady state this signal is also proportional to the current provided by the supply. 5.1.3 Overcurrent Protection Cycle by cycle overcurrent protection is necessary when using a chopper to drive a variable impedance load such as a DC motor. During start up the motor may draw large currents to overcome static friction and inertia. The protection must respond quickly to be effective. The protection operates by comparing the instantaneous current signal to a refer ence voltage level. If the current signal exceeds the reference, the LM311 comparator output toggles low, which in turn asynchronously latches the output of a D flip-flop low. When low, this flip-flop output turns off the power mosfets. At the start of the next cycle, the flip-flop clock input is strobed, resetting the output, which enables the power mosfets to be turned on once more. If the current signal again exceeds the reference, the power mosfets are switched off and the process is repeated. During an overcurrent fault the duty cycle of the chopper is governed by the over-current hardware and not the main logic program. The microprocessor therefore needs to be flagged when an overcurrent condition occurs. This is achieved with the aid of a second D flip-flop. The overcurrent signal is attached to the clear pin of this flip-flop to latch the output low. This output forces the STRA pin low, which in turn, is capable of generating an interrupt request. The output also forces bit 0 of port C low, which can be polled to determine if the overcurrent condition persists. The flip-flop clock line, bit 2 of port B, must be strobed to reset the flip-flop. Chapter 5. Microprocessor Based Hybrid Control 46 5.1.4 Voltage Sensing A portion of the input voltage to the chopper is sampled by the A/D converter via a resistive voltage divider. A potentiometer adjusts the sampled voltage to just be low 5 V under open circuit conditions to utilize the full scale of the A/D converter. This manually adjusted potentiometer could be replaced with a digitally controlled potentiometer, such as the Xicor X9MME, for complete automation of the adjustment process. 5.1.5 Pulse Width Modulation The conventional means of creating a pulse-width-modulated waveform is with a PWM IC such as the NE5561. The frequency is fixed by an R,C oscillator while the pulse width is dependent on the input voltage level. When a digital controller is used, a D/A conversion is necessary to arrive at an analogue input voltage to the PWM. Yet the gating signal is basically a digital waveform. The D/A conversion is necessary because the digital processor is limited. It cannot toggle an output port bit fast or accurately enough to create a pulse-width-modulated waveform at a useful frequency. It may be possible, however, to create the waveform with the aid of external timers. The logic circuit would then become more complex and costly. What is gained by eliminating the D/A converter and PWM chip is offset by the additional timers. The MC68HC11 however has an on-board timer. A pulse-width-modulated wave form can be created with the aid of only limited additional hardware in the following manner: The timer is free running and counts from 0 through to FFFF continuously. At tached to the timer are five output compare registers OCl through OC5. Registers Chapter 5. Microprocessor Based Hybrid Control 47 0C2 through 0C5 are attached to the output port bits PA6 through PA3 respectively. Register OC1 can be attached to PA7 and it can also affect the output state of PA6 through PA 3. When a number loaded into one of the compare registers equals the timer count, a specified action will occur. For example, when the timer count equals the number contained in the OC2 register, PA6 can be forced high, or low, or be made to toggle, depending on the control register settings. An interrupt request can also be generated upon a successful compare. Compare register OCl is special. It can affect all output port bits associated with the compare registers simultaneously. The change called for by OCl will override a change called for by any other output compare register in the event of a conflict. A pulse-width-modulated waveform can be created at the output of pin PA6 by using OCl to set the pin high and by using OC2 to reset the pin low. The compare registers would be updated each cycle by responding to an interrupt request generated by an OCl successful compare. The processor would add a number representing the period to each compare register within the interrupt routine. The number contained in register OC2 would be offset from the number in OCl by the on time. In this scheme the on time must be long enough for the processor to respond to the interrupt request and update register OC2 ruling out the use of a small duty cycle. It is possible to use a full range of duty cycles by switching interrupt sources. When the duty cycle is greater than 50% OCl could generate interrupt requests as already explained. When the duty cycle is less than 50% interrupt requests could be generated by successful OC2 comparisons. Switching interrupt sources must be done with care to ensure a smooth transition. The maximum frequency of the generated waveform is limited by the speed of the CPU. Before it can respond to an interrupt request the CPU must complete the present Chapter 5. Microprocessor Based Hybrid Control 48 instruction, save the register state, and load the address of the interrupt routine into the program counter. Once in the interrupt routine, the CPU must update the next compare register before the timer count runs past it. These processes may take up to 37 machine cycles or 18.5/xs and must be completed within one half of a period of the pulse width modulated waveform. Updating the next compare register, clearing the interrupt request and returning to the interrupted task will take another 35 machine cycles. The maximum frequency is therefore limited to about 25kIIz. At an operating frequency of 25kIIz there would be very little free time for the CPU to service other procedures. Only one or two instructions could be executed between interrupt requests. Also the adjustment to the pulse width would be coarse. The minimum adjustment to the pulse width is a 0.5/LJS step, so at 25kHz there are only 80 steps between a 0% and 100% duty cycle. It is possible to free up CPU time and effectively decrease the step size by creating three output waveforms instead of one. These waveforms are combined in a set of external NAND gates to produce a single waveform at twice the frequency. A set of these waveforms are displayed in Figure 5.16. The waveforms produced at pins PA5 and PA4 are NANDED together. The output is then NANDED together with the waveform produced at pin PA6 to produce the resultant waveform shown in Figure 5.16. The waveform at pin PA5 remains at a 50% duty cycle while the waveforms at PA6 and PA4 are adjustable. By adjusting the waveforms at PA6 and PA4 separately the duty cycle resolution is effectively doubled. For example if the period is 50/xs and the on time of the first pulse stream is 18.0/us while the on time of the second pulse stream is 18.5/Lts the effective duty cycle is 36.5%. The duty cycle is adjustable in 0.5% steps instead of 1.0% steps, which would be the limit with a single pulse stream. With some additional NAND gates a full range of duty cycles from 0% to 100% is Chapter 5. Microprocessor Based Hybrid Control 5.0 -CN O O 0.0 5.0 -O O 0.0 H* 5.0 o o 0.0 5.0 Z) Q_ I— ZD O 0C4 0C4 0.0 —i i i i i i i i i—i i i i i i i i i—i i i i i i i i i—i i i i i i i i i 0 50 100 Time (LIS) 150 200 Figure 5.16: Pulse Width Modulated Waveforms Chapter 5. Microprocessor Based Hybrid Control 50 possible, unlike conventional PWM chips, which are capable only of duty cycles between 0% and 98%. Bit one of port A is wired to the input of one NAND gate and dedicated to turning the converter fully off when low, while bit two is wired to the input of a second NAND gate and dedicated to turning the converter on. Figure 5.15 shows the detailed circuit diagram. Addition NAND gate inputs are used to externally switch the converter off. When turned fully off or on the pulse width modulation continues at a minimum or maximum duty cycle. This simplifies the restart process as timer synchronization within the program is never lost. 5.1.6 Gate Drive The gates of the three parallel power mosfets are driven by a DS0026 dual inverting buffer. This device can deliver a large peak current, 1.5A, to rapidly switch the power mosfets. A series resistance of 33fi is inserted between each power mosfet and the gate to limit the switching speed and prevent oscillations between parallel devices. 5.2 Program The main function of the logic program is to alternate between the maximum power and voltage tracking modes of operation. Various sub-tasks must be coordinated for the main program to successfully operate. 5.2.1 Maximum Power Tracking The program begins in the maximum power tracking mode and periodically reenters it. In this mode a search is made for the optimum operating point and the voltage corresponding to this point is recorded. Chapter 5. Microprocessor Based Hybrid Control 51 Initially the converter is turned fully off. The open circuit voltage is read together with the DC offset, if any, in the current measurement hardware. The duty cycle is then slowly increased in steps of approximately 5%. After each change to the duty cycle a delay of two seconds is introduced to allow system transients to decay. The voltage and current signals are sampled at each step and the operating power calculated. A record of the last three power and operating voltage levels are kept for future reference. The present power level is compared with previous power levels. If the measured power is increasing the duty cycle is again changed in the same direction. If, however, the power level has twice decreased, the direction of the search is reversed. The direc tion of the search will also reverse if the converter reaches the limit of being turned either fully on or fully off. Each time the direction of the search is changed, the maxi mum recorded operating power and corresponding voltage level of the latest sweep are recorded in an array. Also, the amount the on time is changed between samples is reduced for a finer gradient search. Once enough sweeps past the maximum power point have been made, presently 12, the power tracking mode is discontinued. A search is made for the highest recorded six power levels. The voltages corresponding to these power levels is then averaged and passed on to the voltage tracking routine. After a period of time, half an hour, the power tracking mode is reentered. The principle of sweeping past the maximum power point is maintained. This time, however, the search for the maximum power point originates at the present duty cycle rather than starting from a fully off position. 5.2.2 Voltage Tracking The controller enters the voltage tracking mode after the power tracking routine has de termined the optimum operating voltage. The voltage is held constant by periodically, Chapter 5. Microprocessor Based Hybrid Control 52 ten times a second, comparing the operating voltage to the reference. An adjustment to the duty cycle is made to compensate for the difference between the optimum and measured voltage, AV. To calculate the magnitude of the change in the on time, AtoN, a simplified model will be used. The photovoltaic array will be modeled by a voltage source, Vs, with an internal resistance, Rs- The DC machine will be represented by a resistor and an inductor. The converter, by altering the duty cycle, adjusts the effective resistance of the load, REFF> as seen by the source. This system with a simple resistive and inductive load is shown in Figure 5.17 and Figure 5.18. The voltage at the terminals of the source, VA, is: VA = Vs - RSIS (5.16) where Is is the source current. Substituting Is = h • *-f (5.17) into Equation 5.16, where II is the load current and T is the period yields: VA = VS- Rsh— (5-18) Assume the converter is operating near the maximum power point. Then it can be shown for the simple resistive and inductive load modeled here that £.Iu = 0. Also if one considers the constant torque Mono pump as the load, then Ii is constant for most operating conditions. In any case, for the purpose of approximating the derivative of Equation 5.18 near the maximum power point, II shall be considered constant. Therefore: Chapter 5. Microprocessor Based Hybrid Control Source Res i s t once © Idea I Vo 1 tage Source -Q-Ar ray Connect ion Lo JTTTI DC Mach i ne Figure 5.17: Simplified Power Circuit Source Res Is t ance ©Idea I VoIt age Source EFFective / Load /R Res is tonce / EFF Array Connect ion Figure 5.18: Equivalent Power Circuit Chapter 5. Microprocessor Based Hybrid Control 54 AVA = Rsh AtON T AVAT AW = ~-^r (5.19) From the maximum power transfer theorem, it is known that R$ = REFF at the maximum power point. Therefore: Rs = REFF = ^r- (5.20) is Substituting Equations 5.20 and 5.17 into Equation 5.19 yields: AtON = -^ON. (5.21) All the quantities on the right hand side of Equation 5.21 are either known, can be measured, or can be easily calculated. The magnitude of the change in the on time, Alow, is therefore easily determined. Some of the assumptions made in the above equations may be either crude or do not hold true away from the maximum power point. The actual system contains a non linear source impedance, and the usual equivalent circuit of a DC machine includes a back electromotive force, EMF, which is proportional to the machine speed. However, it is standard practice to linearize a non-linear system around an operating point. Also it is valid to lump the back EMF of the DC machine into an equivalent resistance, if the current through the machine is constant. In any case, there are no strict constraints on the performance of the control system. All that is necessary is that the operating voltage be held constant and that the system remain stable. These criteria are easily met by this control scheme. Chapter 5. Microprocessor Based Hybrid Control 55 5.2.3 Interrupts The hardware arbitrated priority structure of the MC68HC11 assists in coordinating the various tasks. At any time three interrupt requests are active. One to service the pulse width modulation routine, one to service the real time clock, and one to service the overcurrent routine. The main program receives the lowest priority and can be interrupted at any time. Timing within the main program is coarse, and not critical, so that interrupt requests can be easily serviced without interfering with the logical flow of the program. • Pulse Width Modulation The routine servicing the pulse width modulation interrupt receives the highest priority. This is achieved by appropriately setting the HPRIO, highest priority I interrupt register. It is critical that the output compare registers be updated before the timer count exceeds the updated compare register count. Otherwise gate voltage transitions will be lost and the power mosfets will be turned either, off or on for a prolonged period of time. An interrupt routine can only be serviced after the CPU has completed the present instruction. To reduce the maximum response time to an interrupt request, a wait instruction, WAI, is placed before each instruction which requires a long time to complete. The wait instruction saves the register state and halts the program execution until an interrupt request is received. In this way the longer instructions, such as divide, FDIV, and multiply, MUL, are executed just after the interrupt routine has been serviced and it is very unlikely that another interrupt request would be generated while these instructions are being executed. • Overcurrent Protection Chapter 5. Microprocessor Based Hybrid Control 56 The routine which services the overcurrent interrupt request receives the next highest priority. Response time to this routine is not critical as the hardware detector protects the power mosfets. This routine serves the purpose of clearing the fault and acknowledging its receipt. First the routine calls for a delay and then checks to see if the fault persists. If the fault persists the duty cycle is reduced, another delay is called for, and the overcurrent input line is read. This procedure continues until the fault is at last cleared. Before returning to the main program a flag bit is set to signal that an overcurrent fault has occurred. This flag bit is checked each time an increase in the duty cycle is called for. If the flag bit is set, an overcurrent counter is incremented before clearing the flag and increasing the duty cycle. If the overcurrent counter indicates a persistent fault, ie. more than six faults have occurred in a given period, then the converter is shut down for a period of half an hour. • Real Time Clock It is convenient to use a real time clock to synchronize events within the program. Delays ranging from a fraction of a second to several days can be handled with the aid of a real time clock. The clock is derived from the free running timer. As the timer overflows an interrupt request is generated. The interrupt service routine is then able to update the time of day node by a fraction of a second. The second, minute, hour and day counters are appropriately updated as required. More details as to the updating process are given in the program listing. To create a delay, the program must first access a timer node. The delay is added Chapter 5. Microprocessor Based Hybrid Control 57 to the time of day and the result is placed in the timer node. The timer node is periodically compared with the time of day until they match. The delayed procedure is then executed. Several delays can be handled simultaneously. Timer nodes may be sequentially tested until a match is found. The procedure associated with the matched node is then executed and the timer node released. This timer coordination is handled by the program. To handle a more complex coordination problem a special operating system could be written. However this is beyond the scope of this project. 5.2.4 Changing the Duty Cycle Although it is possible to make large, sudden changes to the duty cycle, it is more desirable to make changes slowly and smoothly. In this way large transient currents, due to the filter capacitor discharging, are avoided. In any case the motor together with the pump have a large inertia and cannot change speed quickly. The subroutine CHANGE ramps up or down the duty cycle in small steps. A minimal change, 0.5/tts, is made to one of the two sets of pulse streams in each step. The pulse width modulation process then continues for several cycles before the next small change is made. The pulse width is changed again until either the desired value is reached or the converter is turned fully on or off. 5.3 Results The program is able to handle the multiple simultaneous tasks well. The pulse width modulation process continues without interruption, the maximum power point is lo cated within 1% of the optimum value, and the voltage tracking routine is both accurate and stable. Chapter 5. Microprocessor Based Hybrid Control 58 5.3.1 Voltage Waveform The drain-to-source voltage waveform is displayed in Figure 5.19. There is some ringing evident as the power mosfets switched off, but this is not important as the peak voltage is not very high. A magnified view of the drain-to-source voltage as the converter is switched off is displayed in Figure 5.20 while the drain-to-source voltage during turn-on is displayed in Figure 5.21. In both cases the switching is fast and the peak voltage is not significantly higher than the input terminal voltage. 5.3.2 Current and Voltage Measurements The accuracy of the power tracking routine is only as accurate as the voltage and current measurements made by the microprocessor, as the power level is calculated from this voltage-current product. The load current and voltage are also calculated from the supply current and voltage . The accuracy of the current, voltage and power measurements are verified by com paring the values obtained by the microprocessor with actual measurements. Each measurement is taken with a fixed duty cycle, supply voltage, and load impedance. To obtain several data points the duty cycle is varied, while the other variables are held constant. Measurements made by the microprocessor are compared with the measure ments obtained from the voltage and current meters. The signal read by the microprocessor is not calibrated, but in this application this is not important as only the relative current signal is of interest. All that is required is that an increase in the supply current be accompanied by a proportionate increase in the measured current. However, if it were required, it would not be difficult to calibrate the current and voltage signals. The instantaneous current signal through the power mosfets is shown in Figure 5.22. Chapter 5. Microprocessor Based Hybrid Control 59 Figure 5.19: Drain-to-Source Voltage Waveform VIN : 145V VOUT • HIV 20V/div. lIN : 4.9A IOVT • 6.1A lO.Oms/div. Apart from the ringing as the devices are first switched on the signal is an accurate representation of the current. The ringing, induced by the drain-to-source capacitance of the isolated current sensing cells, is removed by a low pass filter. The signal, shown in Figure 5.23, is then suitable to be used for the cycle-by-cycle overcurrent protection. Figure 5.24 displays the filtered current signal when the overcurrent protection is active. The supply current measured by the A/D converter is compared with the meter-measured current in Figure 5.25. The linear relationship between the two methods of measuring current is evident, even though the temperature of the power mosfets is changing as the current through the device increases. The load current is derived by the microprocessor by dividing the supply current by the duty cycle. The measured load current is compared with the derived load current Chapter 5. Microprocessor Based Hybrid Control 60 Figure 5.20: Drain-to-Source Voltage Waveform at Turn-off YIN • 145V YOUT : 111V 20V/div. I/A, : 4.9A lOUT : 6.1A 0.02/its/div. Chapter 5. Microprocessor Based Hybrid Control 61 Figure 5.21: Drain-to-Source Voltage Waveform at Turn-on V/JV : 145V VOUT • HIV 20V/div. lIN : 4.9A IQVT • 6.1A 0.02/is/div. Chapter 5. Microprocessor Based Hybrid Control 62 Figure 5.22: HEXSense Current Waveform V/JV : 145V VQUT • 90.7V lV/div. I/JV : 6.37A Iot/r : 9.4A lO.Oms/div. Chapter 5. Microprocessor Based Hybrid Control 63 Figure 5.23: Filtered HEXSense Current Waveform VJJV : 145V VOVT • 90.7V lV/div. 1IN : 6.37A lour • 9.4A lO.Oms/div. Chapter 5. Microprocessor Based Hybrid Control 64 Figure 5.24: Current Waveform with Active Overcurrent Protection V/JV : 232V I/Tv : 2.6A V0UT : 52.9V lour • 10.4A lV/div. lO.Oms/div. Chapter 5. Microprocessor Based Hybrid Control 65 in Figure 5.25. The calculated load current is accurate within a few percent except when the duty cycle is very small. The point on the load current curve of Figure 5.25 with a significant error is calculated at a 2% duty cycle, where a quantization error in the supply current is magnified 50 times when the load is calculated. The supply voltage measured by the microprocessor is compared with the supply voltage read from a voltmeter in Figure 5.26. The calculated and measured load volt ages are also displayed. It is evident that both the calculated load voltage and the supply voltage measurements obtained by the microprocessor are accurate. The bump that is observed in the region between the load and supply voltage measurements is due to losses in the converter which are unaccounted for in the computation of the load voltage. Other small discrepancies are due to fluctuations in the supply voltage. The power calculated by the microprocessor is compared with the measured input and output power in Figure 5.27. The measured power is the product of the measured voltage and current. There is a good correspondence between the two methods of measuring the power. There is a slight difference between the input power and the power delivered to the load. The difference between these two curves is the converter losses. There are also inaccuracies in the measurements due to the meters and variations in the supply voltage. 5.3.3 Maximum Power Point The controller attempts to maximize the power delivered to the load. To test the accu racy of the power tracker the following test circuit was constructed: A stiff, adjustable DC source was derived from the rectified output of a three-phase variac. The source impedance of the photovoltaic array is simulated by an adjustable power resistor. The source resistance remains fixed for any given set of measurements. The load is made Chapter 5. Microprocessor Based Hybrid Control 66 Measured Current (Amps) Figure 5.25: Microprocessor Current Measurements vs Metered Current Measurements Chapter 5. Microprocessor Based Hybrid Control •67 Figure 5.26: Microprocessor Voltage Measurements vs Metered Voltage Measurements Chapter 5. Microprocessor Based Hybrid Control 68 co 'E Z5 o c CD $ O Q_ X) CD i_ 13 CO D CD O CO CO CD U O Q_ O u 15000 10000 5000 0 Load power xxxxx Array power X » XX X * X X • » w x < X » X • X X X • X • X • X * X * X • X « X * X • X « xx.# ~i i i i i i i i iI ii i i|miiiiiiiIr 0 100 200 300 400 500 Measured Power (Watts) Figure 5.27: Calculated Power vs Metered Power Chapter 5. Microprocessor Based Hybrid Control 69 600 -i 400 H 200 Input Power xxxxx Load Voltage ***** Load Current 60 50 h-40 h30 20 10 r 10 co > Cn O "o > O O 0 | i i—i—i—i—i—i—i—i—|—i—i—i—i—i—i—i i i | r~i i 0 0 40 80 8 co Q. 6 E < h-4 c cu CJ "a o o L0 Duty Cycle (percent) Figure 5.28: Power, Load Current, and Load Voltage vs Duty Cycle Chapter 5. Microprocessor Based Hybrid Control 70 up of a 11.5mH inductor in series with an adjustable power resistor which also remains fixed for a given set of measurements. From the maximum power transfer theorem it is known that the load and source resistance should be equal at the maximum power point. Note that the effective load appears resistive to the source as both the voltage and current into the chopper are DC. The voltage at the terminals of the chopper will be half the source voltage when the effective load resistance equals the source resistance. The accuracy of the power tracking system is therefore tested by running the test circuit with various loads and open circuit voltages. These conditions are recorded and if the power tracker is accurate the voltage level at the terminals of the chopper will settle to one half the source voltage. The test results are summarized in Table 5.3.3. The maximum power point is located within 1.0% in all cases and within 0.5% in most cases. The operating voltage which the converter settles upon is located within a few volts of the optimum value. Near the maximum power point the power delivered to the load changes only slightly as the operating voltage is varied. Figure 5.28 displays how the input power, load voltage and load current change as the duty cycle is varied from 2% to 98%. The load current and load voltage curves are quite flat near the peak, which occurs at the same point as the peak on the power curve. As a final test the converter is set up to run a DC machine which in turn drives an induction generator. The same stiff DC source together with a series power resistor is used to simulate a photovoltaic array. The test results were encouraging. The starting torque is easily overcome, the maximum power point is located within 1.0% and the voltage tracking is stable and accurate. The converter meets all requirements. Chapter 5. Microprocessor Based Hybrid Control 71 Table 5.4: Power Tracking Results Open Maximum Power Circuit Operating Input Load Output Efficiency Input Tracking Voltage Voltage Power Voltage Power n Power Error 120 V 55.7V 202 W 42.3V 192W 95% 203 W 0.49% 120 V 57.8V 202 W 29.8V 186W 92.1% 202W 0.0 150V 71.4V 307W 52.3V 294 W 95.8% 310W 0.97% 151V 71.5V 309W 42.8V 290W 93.9% 311W 0.64% 175V 88.7V 257W 65.9V 247W 96.1% 258W 0.39% 175.8V 91V 406W 60.3 V 386W 95.1% 410W 0.98% 175.8V 88.1V 410W 49.3V 384W 93.6% 410W 0.0 201V 101V 530W 62.1V 500W 94.3% 530W 0.0 201V 98.6V 335W 75.4V 323W 96.4% 335W 0.0 201V 96V 532W 69.1V 505W 94.9% 532W 0.0 225V 109.7V 659W 76.4V 640W 97.1% 660W 0.15% 225.6V 104V 414W 60.6 V 386W 93.2% 415W 0.24% 225V 109.7V 659W 76.4V 640 W 97.1% 660W 0.15% 250V 117V 511W 93.5V 492W 96.3% 512W 0.20% 251V 123V 518W 72.7 V 492 W 95.0% 520W 0.38% 250.6V 125V 512W 66.0V 475W 92.8% 512W 0.0 300V 144V 731W 112.4V 710W 97.1% 735W 0.54% 304V 144V 940W 127.7V 910W 96.8% 942 W 0.21% 301V 146V 925W 90.9V 870W 94.0% 930W 0.54% Chapter 6 Conclusions The amount of water delivered by a photovoltaic powered pumping system can be maximized with the aid of a one quadrant DC to DC converter. The converter is capable of matching the combined motor-pump characteristics to the characteristics of the photovoltaic array for maximum power transfer under most lighting conditions. Three schemes of controlling the DC to DC converter are presented. The simplest control scheme involves fixing the photovoltaic array voltage at some manually set reference level. Close to maximum power is delivered to the load under most insolation levels and the control scheme is stable, even under fluctuating lighting conditions. Only a simple analogue circuit is required. A true power tracking control scheme can also be used to maximize the power output of the DC to DC converter. This controller finds and maintains the best operating point automatically at the expense of a more complex logic circuit. Maximum power output will be maintained, even if the photovoltaic array characteristics drift with temperature and age. Maximizing the output is important because the photovoltaic panels are expensive. A small increase in the power delivered to the load will result in an even greater increase in overall efficiency, as both the pump and DC motor operate more efficiently at higher speeds and power levels. One drawback is that the controller can temporarily drift away from the optimum operating point if the insolation levels are fluctuating. To maintain the advantages of both the power tracking and the voltage tracking 72 Chapter 6. Conclusions 73 control schemes a microprocessor based hybrid scheme is developed. A single chip mi crocomputer provides most of the logic functions of the controller when used with only a few external chips. During the power tracking mode, the optimum operating point is automatically located and adjusted. Many data points are sampled and averaged to increase the accuracy of the search. The majority of the time is spent in the voltage tracking mode. In this mode the array voltage is held constant even as the insolation levels fluctuate. These basic functions have been implemented and tested. But perhaps the most important advantage of the microprocessor based control scheme is its flexibility. More sophisticated features can be added with little or no increase in the complexity of the hardware. For instance, it should be possible to identify a dry well and quickly shut down the converter preventing a catastrophic failure. This feature, although easily implemented, was not incorporated due to inadequate test facilities. Another possibility is that the microprocessor based system could act as a data logger, keeping a record of the power level, motor voltage and current, ambient tem perature, etc., for future reference and study. This information, along with any fault alarms, could conceivably be transmitted to a central location to be recorded and speed the detection and repair of faulty equipment. The extra cost involved in developing and manufacturing the microprocessor based system would be justified by the extra flexibility and protection the system would provide. Appendix A Assembly Language Program ORG $00 ******************************************* * * Hybrid Power Tracking, Voltage Tracking Controller * *************************************************************************** * * This assembly language program is targeted for the Motorola * MC68HC11A8 HCMOS single-chip microcomputer. J^t 5^ SJ^ t^fi ^ l(C 5^ iff ^ 5^ )|c J^S 3J£ 3f* 5JC 5fc ik )|i *^ ^ 5k- *^ 3J< ^ #Jc J^C 5f< ^Jc 3^ )|c 5jc 3^ 3^ 5J< S^C 3|C5|C-^5fc5|is(c5^^t5^3|i5^ * This program controls the pulse width of the gating pulses applied to the gates of a set of parallel power mosfets. The controller has two modes of operation. In the power tracking mode the duty cycle is slowly increased from its minimum value in a search for the maximum power point. Once this point has been found the voltage tracking mode is entered. In this mode the operating is held steady at the value corresponding to the maximum power point. * * Label some memory locations to hold useful variables PERIOD RMB 2 0NCNT1 RMB 2 0FCNT1 RMB 2 0NCNT2 RMB 2 0FCNT2 RMB 2 STEP RMB 1 FLG RMB 1 MAXCUR RMB 1 OPEN RMB 1 Memory location to hold the period. Memory location to hold the ON count one. Memory location to hold the OFF count one. Memory location to hold the ON count two. Memory location to hold the OFF count two. Define a user flag register. Register to hold the short circuit current. Register to hold the open circuit voltage. 74 Appendix A. Assembly Language Program 75 CURR RMB 1 Register to hold the operating current. MOTCUR RMB 2 Register to hold the load current. VOLT RMB 1 Register to hold the operating voltage. MOTVLT RMB 1 Register to hold the average load voltage. POWER RMB 2 Register to hold the operating power. PWRMAX RMB 2 Register to hold the maximum operating power. OFFSET RMB 1 Register to hold the current offset. CORECT RMB 1 Register to hold the current correction factor. MAXVLT RMB 1 Maximum power voltage. COUNT RMB 1 Reserve a space for a counter. TEMP RMB 2 Define a space for a temporary variable. TEMP 2 RMB 1 TMPVT1 RMB 1 TMPVT2 * RMB 1 * * Label memory locations to hold the timer variables. T-FRCSEC RMB 2 Holds the fraction of a second count. SECOND RMB 1 The second counter. MINUTE RMB 1 The minute counter. HOUR RMB 1 The hour counter. DAY RMB 1 The day counter. TMENOD RMB 6 A 6 byte timer node. TMN0D2 RMB 6 A 6 byte timer node. * The last item is memory reserved for an array. * Although there is only one byte reserved the array ARRAY RMB 1 can grow as far as the stack boundary. MSKOC1 EQU $80 Mask for the 0C1 flag and mask registers. MSK0C2 EQU $40 Mask for the 0C2 flag and mask registers. * Define the software flag register bits. STRTUP EQU 1 ONGR EQU 2 UP EQU 4 DECRS EQU 8 FRST EQU $10 Bit one signals pulse width modulation start-up. When set, signals the ON time is greater than the OFF time. When set, indicates an increasing pulse width. When set, indicates a decreasing power level. Bit to indicate the initiation of the maximum power Appendix A. Assembly Language Program 76 * tracking routine. OVRCUR •J-EQU $20 Over-current flag bit. Def ine some other useful constants. RDCURR EQU 1 RDVLT EQU 2 OFF EQU $01 ON EQU $02 RUN EQU $03 CLRCUR EQU $04 MIN EQU $2 DLAY EQU 1 One second delay. DELAY EQU $0600 Fraction of a second delay. * Define the I/O port locations PORTA EQU $1000 I/O port A PORTB EQU $1004 I/O port B PORTC EQU $1003 I/O port C PRTCL EQU $1005 Alternate latched port C. DDRC EQU $1007 Data direction for port C. PIOC EQU $1002 Parallel I/O Control Register PORTD EQU $1008 I/O port D A.l Main Program ORG $E000 BEGIN SEI LDS #$00FF * LDY #PORTB BCLR ,Y OFF BSET ,Y ON LDD #$0064 Inhibit interrupt requests. Turn the power MOSFETS off. Load a number representing the period. Appendix A. Assembly Language Program STD LSRD LSRD PERIOD Divide down the period to form the initial step size to perturb the pulse width. * * LOOP * L0P1 LSRD STAB STEP LSRD ADDB STEP STAB STEP Set up the overcurrent detector. JSR OCRSET CLRB STD PWRMAX Initialize the A/D converter. BSR ADSET Initialize the timer. BSR TIMER CLI Enable the interrupt system. Determine the open circuit voltage and offset current. JSR ADJOPN Find the maximum power point. JSR MAXPWR Place the converter in the voltage tracking mode. CLR COUNT Clear the counter which records the number overcurrent incidents. LDX #TMEN0D Clear the timer node. JSR CLRTME LDAB #30 Add 30 minutes to the time. STAB JSR 3.X ADDTME Appendix A. Assembly Language Program 78 L0P2 * L0P2A L0P2B L0P3 JSR VLTRAK Call the voltage tracking routine. Test for overcurrent and branch if clear. BRCLR FLG OVRCUR L0P2B This section is entered if an overcurrent fault has been detected LDAA COUNT INCA Increment the overcurrent counter. BCLR FLG OVRCUR Clear the overcurrent flag. CMPA #7 BNE L0P2A JMP OVRDLY Exit if the number of overcurrent occurrences STAA COUNT PSHX Save the timer node address. LDX #TMN0D2 JSR CLRTME Clear the new timer node. LDD #DELAY Add a fraction of a second to the time STD .X of day and place the result in the timer node JSR ADDTME JSR CMPTME Compare the timer node to the current time. TSTA BNE L0P3 Loop if time is not up. PULX Restore the first timer node address. JSR CMPTME Compare to the current time. TSTA BNE L0P2 Loop again if time is not up. Adjust the maximum power tracking voltage. LDD PERIOD LSRD LSRD Redefine the step size. LSRD STAB STEP BRA LOOP Find the maximum power point again. = 7. A.2 A/D Converter Set-Up Appendix A. Assembly Language Program * *********************************************** * * SUBROUTINE ADSET * * Subroutine ADSET sets up the A/D converter to read in data * from all four data lines under program control. * * INPUT and OUTPUT: NONE * * REGISTERS EFFECTED: The CC and A register. **************************************************************** * * * Define some memory locations associated with the A/D * converter. * ADCTL EQU $1030 A/D Control/Status register. OPTION EQU $1039 Configuration options register. ADR1 EQU $1031 A/D Result register 1. ADR2 EQU $1032 A/D Result register 2. ADR3 EQU $1033 A/D Result register 3. ADR4 EQU $1034 A/D Result register 4. ADDAT EQU $10 A data byte to configure the ADCTL to read all * four channels under program control. ADSET LDAA OPTION ORAA #$80 Set the A/D power up bit in the options reg. STAA OPTION LDAA #ADDAT Configure the A/D converter to read lines one STAA ADCTL through four under program control. RTS A.3 Timer Set-Up * * **************************************************************** * * SUBROUTINE TIMER * * Subroutine TIMER sets up the free running timer. Appendix A. Assembly Language Program 80 * from all four data lines under program control. * * INPUT and OUTPUT: NONE * * REGISTERS EFFECTED: The CC and A register. * Define some memory locations associated with the timer. * TIME EQU $100E REG0C1 EQU $1016 REG0C2 EQU $1018 REG0C3 EQU $101A REG0C4 EQU $101C TMSK1 EQU $1022 TCTL1 EQU $1020 0C1M EQU $100C 0C1D EQU $100D CFORC EQU $100B TMSK2 EQU $1024 TFLG2 EQU $1025 TFLG1 EQU $1023 TIMER LDAA #$F8 STAA TCTL1 LDAA #$FF STAA 0C1M LDAA #$10 STAA 0C1D LDAA #$F8 STAA CFORC * * Set the timer registers to zero. * LDX #FRCSEC JSR CLRTME LDAA TFLG2 Clear any pending overflow interrupts. STAA TFLG2 LDAA #$80 Enable the overflow interrupt request by setting STAA TMSK2 timer mask register bit. 16 bit free running timer address. Output compare register one. Output compare register two. Output compare register three. Output compare register four. Main timer interrupt mask register 1. Timer control register 1 address. Output compare 1 mask register address. Output compare 1 data register address. Timer compare force register. Timer interrupt mask register 2. Timer interrupt flag register 2. Timer interrupt flag register 1. Specify the timers' mode of operation. Set the timer control register to force 0C2 and 0C3 high, and 0C4 low after a successful compare Specify A3-A7 to be effected by a successful 0C1 compare in the output compare mask register. Set the compare 1 data register to force 0C2.0C3 low and 0C4 high after a successful 0C1 compare. Set the timer compare force register to force A3-A7 low. Appendix A. Assembly Language Program 81 LDAA #0 Set the FLG register to indicate a start up condition. STAA FLG RTS A.4 Overcurrent Initialization * * SUBROUTINE OCRSET * * * INPUT and OUTPUT: NONE * * REGISTERS EFFECTED: CC. Subroutine OCURST sets up the overcurrent detector. Both flip flop clocks are strobed to place the detector in a known state. Also internal registers are set to receive an overcurrent interrupt request. OCRSET PSHX Strobe the output of PORTA to ensure overcurrent flip flop one latches to a high value. PSHA LDAA PIOC LDAA PRTCL Clear any pending interrupt flags. LDX #P0RTA BCLR ,X $40 BSET .X $40 BCLR ,X $40 LDX #P0RTB BSET ,X 4 Strobe the clock of overcurrent flip flop 2, BCLR ,X 4 BSET ,X 4 BCLR .X 4 Appendix A. Assembly Language Program LDAA #0 STAA DDRC LDX #PI0C BCLR ,X $2 BSET .X $40 PULA PULX RTS Set up port C as an input port. Activate an interrupt request upon a falling edge of STBA. Set the interrupt enable mask. A.5 Read Input Data ****************************************** * * SUBROUTINE READ * * Subroutine READ reads in the data from a single channel * of the A/D converter. The data is read in four times and * averaged. * * INPUT: Register A is input with the number of the * A/D line to be read. * none * * OUTPUT: Register A is returned with a value of: * 0: Successful read. * -1: Illegal input data. * * Register B is returned with the average * of four A/D conversions. * * REGISTERS EFFECTED: A.B and CC registers. **************************************************************** * READ PSHX CMPA #3 Test for illegal input data. BHI ERR1 PSHA LQ2 STAA ADCTL Initiate an A/D conversion process. Appendix A. Assembly Language Program LQ3 LQ3B Lq3C LQ3D Lq4 LQ5 LQ6 LQ7 LDX #ADR1 LDAA ADCTL BPL LQ3 Wait for valid data. Test the data to ensure the four readings do not vary more than one bit. LDAB ,X SUBB l.X BHS LQ3C NEGB CMPB #1 BLS LQ3D TSX LDAA .X BRA LQ2 INX CMPX #ADR4 BNE LQ3B Compare two readings. Form the absolute vale of the difference, If the readings vary more than one bit. Fetch another set of readings. Else the two readings vary less than one bit. All for readings tested? If not, test the next pair. Add the four A/D conversion results and average them. Average the four readings. PULA CLRA STAA TEMP2 LDAB ADR1 ADDB ADR2 BCC LQ4 INCA ADDB ADR3 BCC LQ5 INCA ADDB ADR4 BCC LQ6 INCA LSRD BCC LQ7 INC TEMP2 LSRD BCC LQ8 INC TEMP2 Divide the result by two. Divide by two again. Appendix A. Assembly Language Program 84 LQ8 LDAA #1 Check if both discarded bits from the averaging SUBA TEMP2 process were set. BCC LQ9 If so increment the result. INCB LQ9 CLRA Signal a successful A/D conversion. PULX RTS ERR1 LDAA #$FF Signal illegal input data. CLRB PULX RTS A.6 Adjust the Pulse Width * SUBROUTINE ADJST * * Subroutine ADJST adjusts the pulse width of the modulated * output voltage waveform. The waveform is updated two pulses * at a time and the width of each of these two pulses can be * separately adjusted. * * ASSUMPTION: * The ON times input for the two pulse trains is valid and * strictly less than the period. * * INPUT: * 1) The FLG register is set to indicate which * compare line activates an interrupt request. * a) FLG bit 0 = zero implies the waveform * has not yet been started. * b) FLG bit 1=1 implies the ON time is * greater than the OFF time and OCl is currently * generating interrupt requests upon a successful * compare. * c) FLG bit 1=0 implies the OFF time is * greater than the ON time and 0C2 is currently * generating interrupt requests upon a successful * compare. Appendix A. Assembly Language Program 85 * * 2) The ON time of the first pulse is input via * the D register. * 3) The ON time of the second pulse is input via * the X register. * 4) The period of the waveform is contained in the * memory location PERIOD. * * OUTPUT: * The pulse width suitably modified and the FLG register * suitably set. * REGISTERS EFFECTED: CC * .J- si. sT. sL. si. vL- sl> sis si* *X* *ls st* \l* \t* sL> »X* st* sly >L> sL> xl* ^ ^ ^ ^ ^ ^ ^ ^ ^ & ^ \L» \1» J/ ^ ^ ^ ^ ^ ^ ^ ^ ^ Jtf ^ ^ it ^ ^ ^ ^ i Jtf J*Jtf^^^fcJ*Jtfj£*kj£jtfJ^ ^ JfC Jfs JJ^ yyx ^ •ji ^ ^ 7ft ^ •p. 'T' *T" 'T* *T* 'T* "T* *T" *^ "T* 'T' *T* *T* *T* *T* ^ *r" -T" 'Ts 'T* "T* "T^ *T* *T* 'T* 'T* 'T^ *T* 'T' 'T^ ^ ^T1 "T" 'T* *T* 'T' *T* "T" *1* vr* *T* "T* *T* "T^ *T* *r* * * Define some constants. Highest priority I interrupt register address. Data byte used to set 0C1 as the highest priority. Data byte used to set 0C2 as the highest priority. Save the ON time for pulse two. Save the ON time for pulse one. Branch if the pulse train has not yet been started. BRCLR FLG 1 START Test bit 2 of FLG to see if the ON time is greater * Branch if OFF > ON. BRCLR FLG 2 OFFGR HPRIO EQU $103C HP0C1 EQU $8 HP0C2 EQU $9 ADJST PSHY PSHX PSHB PSHA This program section is entered when the FLG register indicates that the ON time was previously greater than the OFF time. Determine whether the new on or off time is greater. * If the on time is larger, there is no need to change the interrupt source. If the off time is now larger the interrupt source * must be changed to 0C2. Appendix A. Assembly Language Program 86 XGDX Place the ON time for pulse two in D reg. TSX ADDD ,X Add the ON time for pulse one. SUBD PERIOD Branch if the sum of the ON times is less than BCS 0C2SEL the period. LDD PERIOD SUBD ,X Calculate the new OFF time for pulse one. XGDY Save the OFF time in the Y register. LDD PERIOD Calculate the OFF time for pulse two. SUBD 2,X WAI SEI Disable interrupts while updating the ON and STY 0FCNT1 OFF registers. STD 0FCNT2 LDD ,X STD 0NCNT1 Save the ON time for pulse one. LDD 2.X STD 0NCNT2 Save the ON time for pulse two. CLI Enable interrupts PULA PULB Restore the register state. PULX PULY RTS * * This program section is entered if the current ON time is greater * than the OFF time and the new OFF time is greater than the new * ON time. * LDD PERIOD SUBD .X Calculate the new OFF time for pulse one. XGDY Save the OFF time in the Y register. LDD PERIOD Calculate the OFF time for pulse two. SUBD 2.X PULX Load the ON time for pulse 1. WAI SEI Disable interrupts while updating the ON and STY 0FCNT1 OFF registers. STD 0FCNT2 STX 0NCNT1 Save the ON time for pulse one. PULX STX 0NCNT2 Save the ON time for pulse two. Appendix A. Assembly Language Program 87 LDD REG0C1 Prepare to change the 0C2 compare register to account ADDD 0NCNT1 for the new pulse width. LDX #TFLG1 LQ10 BRCLR ,X MSK0C2 LQ10 Mark time until 0C2 changes. STD REG0C2 Set the 0C2 bit of the timer interrupt mask register to select an interrupt request upon a successful 0C2 compare. Raise 0C2 to the highest priority interrupt request. LDAA #MSK0C2 STAA TMSK1 LDAA #HP0C2 STAA HPRIO LDAA TFLG1 STAA TFLG1 CLI Clear any pending interrupt requests Enable interrupts Set the FLG register to show the OFF time is BCLR FLG ONGR greater than the ON time. LDD LDX PULY RTS 0NCNT1 0NCNT2 Restore the register state START BRA STRT This program section is entered when the FLG register indicates that the OFF time was previously greater than the ON time. Determine whether the new on or off time is greater. If the off time is larger, there is no need to change the interrupt source. If the on time is now larger the interrupt source must be changed to OCl. XGDX Place the ON time for pulse two in D reg. TSX ADDD ,x Add the ON time for pulse one. SUBD PERIOD Branch if the sum of the ON times is less than BCC 0C1SEL the period. LDD PERIOD SUBD .X Calculate the new OFF time for pulse one. XGDY Save the OFF time in the Y register. LDD PERIOD Calculate the OFF time for pulse two SUBD 2,X Appendix A. Assembly Language Program 88 WAI SEI Disable interrupts while updating STY 0FCNT1 OFF registers. STD 0FCNT2 LDD .X STD 0NCNT1 Save the ON time for pulse one. LDD 2,X STD 0NCNT2 Save the ON time for pulse two. CLI Enable interrupts PULA PULB Restore the register state. PULX PULY RTS * * 0C1SEL TSX LDD SUBD XGDY LDD This program section is entered if the current OFF time is greater than the ON time and the new ON time is greater than the new OFF time. PERIOD .X PERIOD SUBD 2,X WAI SEI STY STD LDD STD LDD STD 0FCNT1 0FCNT2 .X 0NCNT1 2.X 0NCNT2 Calculate the new OFF time for pulse one, Save the OFF time in the Y register. Calculate the OFF time for pulse two. Disable interrupts while updating the ON and OFF registers. Save the ON time for pulse one. Save the ON time for pulse two. LDAA #MSK0C1 Set the 0C1 bit of the timer interrupt mask register STAA TMSK1 to select an interrupt request upon a successful 0C1 compare. LDAA TFLG1 Clear any pending interrupt requests. STAA TFLG1 LDAA #HP0C1 Raise 0C1 to the highest priority interrupt request. STAA HPRIO CLI Enable interrupts BSET FLG ONGR Set the FLG register to show the ON time is Appendix A. Assembly Language Program 89 PULA greater than the off time. PULB Restore the register state. PULX PULY RTS * * This next program section is entered only during start up. STRT LDD PERIOD Calculate and store the ON and OFF times. TSX SUBD .X STD 0FCNT1 LDD ,x STD 0NCNT1 INX INX LDD PERIOD SUBD .X STD 0FCNT2 LDD *x STD 0NCNT2 * * Determine whether the on or off time is greater. * If the on time is larger select 0C1 to generate interrupt * requests and initialize the compare registers in the appropriate * order. * Otherwise select 0C2 successful comparisons to generate * interrupt requests and choose the appropriate order to * initialize the compare registers. ADDD 0NCNT1 Add the two ON times together. SUBD PERIOD BCS SEL0C2 Branch if the OFF time is greater than the ON time. LDAA #MSK0C1 Set the 0C1 bit of the timer interrupt mask register STAA TMSK1 to select an interrupt request upon a successful * 0C1 compare. BSET FLG ONGR Set the FLG register to show the ON time is * greater than the OFF time. LDD 0NCNT1 STD REG0C2 Store the on time in the output compare 2 register. ADDD 0FCNT1 STD REG0C3 Store the result in the output compare 3 register. Appendix A. Assembly Language Program 90 ADDD STD ADDD STD * LDAA STAA BRA SEL0C2 LDAA STAA 0NCNT2 REG0C4 0FCNT2 REG0C1 #HP0C1 HPRIO ENABLE #MSK0C2 TMSK1 Store the double period in the output compare 1 reg. Raise OCl to the highest priority interrupt. Set the 0C2 bit of the timer interrupt mask register to select an interrupt request upon a successful 0C2 compare. BCLR FLG ONGR Set the FLG register to show the OFF time is greater than the ON time. Start up the timer sequence. Store the number in the compare register 3. Store the result in the compare register 4. Store the number used by the compare reg. 1. Store the number used by the compare reg. 2. Raise 0C2 to receive the highest priority. LDD 0FCNT1 STD REG0C3 ADDD 0NCNT2 STD REG0C4 ADDD 0FCNT2 STD REG0C1 ADDD 0NCNT1 STD REG0C2 LDAA #HP0C2 STAA HPRIO ENABLE CLI BSET PULA PULB PULX PULY RTS Enable the interrupt system. FLG STRTUP Set the FLG register to show startup has occurred. Restore the register state. A.7 Real Time Timer ****************************************** * * REAL TIME TIMER * ************************************************************************* * Appendix A. Assembly Language Program 91 on The real time timer will monitor the time in days, hours, minutes seconds, and fractions of a second. Tasks can then be scheduled according to the time of day or delayed for some specified time period as required. The timer will be driven by the "overflow" interrupt request which is assigned a lower priority than the "output compare" interrupt request. An overflow occurs once every 2 to the power of 16 clock cycles, the clock rate being two megahertz. Each time the processor is interrupted the 16 bit "fraction of a second" register is updated. This register is then compared to a number representing one second. If the fraction of a second register is large enough The number representing one second is subtracted from it and the "second" register incremented. If 60 seconds have elapsed the "minute" register is incremented and so In binary 2,000,000 is 0001 1110 1000 0100 1000 000. This is the number which should be subtracted from the fraction of a second register once it is large enough. It is however unnecessary to keep a record of the last seven zeros. Shifted seven places the number becomes 0011 1101 0000 1001 and once every interrupt period 0000 0010 0000 0000 will be added to this 16 bit fraction of a second register. Declare some constants MAXSM MAXHR CNTSEC INCFRC EQU 60 The maximum number of seconds or minutes. EQU 24 The maximum number of hours. EQU $3D09 The number representing one second. EQU $0200 The number added to the fraction of a second register each interrupt period. A.7.1 Time of Day Interrupt Service TIME OF DAY INTERRUPT SERVICE TMINTR LDAA TFLG2 Clear the interrupt request. Appendix A. Assembly Language Program 92 STAA TFLG2 CLI LDD FRCSEC ADDD #INCFRC CPD #CNTSEC BCC INCSEC STD FRCSEC RTI SUBD #CNTSEC STD FRCSEC BSR INCTME RTI Enable the interrupt system. Increment the count by one time period. Subtract the count representing one second. Save the fraction of a second count. Add back the count representing one second. Save the fraction of a second count. A.7.2 Increment The Time of Day ************************************************************************** * SUBROUTINE INCTME *************************************** * * Subroutine INCTME increments the time of day counter * by one second. * * The time of day is divided into days, hours, minutes and seconds. * INCTME INC SECOND LDAA SECOND SUBA #MAXSM BEQ INCMIN RTS INCMIN STAA SECOND INC MINUTE LDAA MINUTE SUBA #MAXSM BEQ INCHR RTS INCHR STAA MINUTE INC HOUR LDAA HOUR Increment the hour counter. Appendix A. Assembly Language Program 93 SUBA #MAXHR Check if the count has reached 24. BEQ INCDAY RTS INCDAY STAA HOUR Reset the hour counter to zero. INC DAY RTS A.7.3 Add Time ****************************************** * * SUBROUTINE ADDTME ************************************************************************* * This subroutine adds a time increment to the current time as specified in the time of day register. INPUT: A pointer to the node containing the time increment OUTPUT: The time increment added to the time of day in the time node pointed to by the X register. REGISTERS EFFECTED: D.CC ************************************************************************ * Disable the time of day interrupt. ADDTME CLRA STAA TMSK2 LDD ,X ADDD FRCSEC LP1 LP2 * Fetch the fraction of a second increment. Add the fraction of a second portion of the time of day. SUBD #CNTSEC Determine if there is an overflow and the second counter needs to be updated. BCC LP1 If yes, branch. ADDD #CNTSEC Restore the fraction of a second count. BRA LP2 Increment the second counter. Save the fraction of a second portion of the result. Load the seconds portion of the time increment, Add the seconds portion of the time of day. INC 2.X STD .X LDAB 2.X ADDB SECOND Appendix A. Assembly Language Program 94 LP3 LP4 LP5 LP6 LP7 LP8 SUBB #MAXSM BCC LP3 ADDB #MAXSM BRA INC BRA INC BRA INC LP4 3.X STAB 2.X LDAB 3.X ADDB MINUTE SUBB #MAXSM BCC LP5 ADDB #MAXSM LP6 4.X STAB 3.X LDAB 4.X ADDB HOUR SUBB #MAXHR BCC LP7 ADDB #MAXHR LP8 5.X STAB 4.X LDAB 5.X ADDB DAY STAB 5.X LDAB #$80 STAB TMSK2 RTS Determine if there is an overflow and the minute counter needs to be updated. If yes. branch. Restore the second counter. Increment the minute counter. Save the second portion of the result. Load the minute portion of the time increment. Add the minute portion of the time of day. Determine if there is an overflow in the minute counter. If yes, branch. Restore the minute counter. Increment the hour counter. Save the minute portion of the result. Load the hour portion of the time increment. Add the hour portion of the time of day. Determine if there is an overflow in the hour counter. If yes, branch. Restore the hour counter. Increment the day counter. Save the hour portion of the result. Load the day portion of the time increment. Add the day portion of the time of day. Save the day portion of the result. An overflow in the day counter is not accounted for as this counter cycles back to zero when full, Enable the time of day interrupt. A.7.4 Compare Time *|c ifj J^C ^ ^ 3^C )fc ^* *|C ^ 3JC sfc -^C ^ jjc 3^ 3fc ^Jc *t*5JC*^5|*4*4CD|C3^* 3|C S^C 5^ *^ ^ ^* ^ *^ ^'t*'^ ^3k^5^^£3fl3JC2|C3$C5$C * SUBROUTINE CMPTME ****************************************** * Appendix A. Assembly Language Program 95 * * * This subroutine compares the pending time contained in a timer node to the time of day. ASSUMPTION: This routine is called often enough so that that the day and hour registers of the pending time will equal the day and hour time of day registers for a successful match. INPUT: A pointer to the node containing the pending time. OUTPUT: Register A is returned with a value of: 0: The time of day is greater than or equal to the pending time. 1: The pending time is greater than the time of day. REGISTERS EFFECTED: D.CC time CLRA Disable the time of day interrupt. STAA TMSK2 LDAB DAY Load the current day. CMPB 5.X Compare the pending day. BNE RTN1 Return if the day registers don't match. LDAB HOUR Load the current hour. CMPB 4.X Return if the hour registers don't match. BNE RTN1 LDAB MINUTE Load the minute portion of the time. CMPB 3.X Compare to the pending time. BLO RTN1 Return if the current time less than the pending BHI RTNO LDAB SECOND Load the second portion of the time. CMPB 2.X Compare to the pending time. BLO RTN1 Return if the current time less than the pending time, BHI RTNO LDD FRCSEC CPD ,X BLO RTN1 Load the fraction of a second portion of the time Compare to the pending time. Return if the current time less than the pending Appendix A. Assembly Language Program 96 time. RTNO RTN1 LDAA #$80 STAA TMSK2 CLRA RTS LDAA #$80 STAA TMSK2 LDAA #1 RTS Enable the time of day interrupts. The time of day is greater than or equal to the pending time so return with A set to zero. Enable the time of day interrupts. The time of day is less than the pending time so return with register A set to one. A.8 Clear Timer Node sfi s(c sfi 5(c s(c i(c 5|c s(c J4« sjc sfr !^ >(c sfj >(c jf; sft s|c 5}c sjc s(c sfi sjc sfc s(c s^c sfi 5(1 jjc s(c s|c sfi sjc 3^c sfc )}c 3(t ijt s(Jc sff s^Jc s(c J(C s|c s|c sjc )(t 't- 'i- 4* 't' 'r' 4- ^4* 'f' ^ ^ ^ 5^ 5^ ^ ^ ^ ^ * SUBROUTINE CLRTME * This subroutine sets to zero the timer node pointed to by the * address contained in the X register. * * INPUT: The address of the timer node in the X register. * OUTPUT: None. * * REGISTERS EFFECTED: D.CC * CLRTME LDD #0 STD ,X Clear the fraction of a second register. STD 2,X Clear the second and minute registers. STD 4,X Clear the hour and day registers. RTS Appendix A. Assembly Language Program A.9 Maximum Power Tracking 97 * SUBROUTINE MAXPWR * * This subroutine attempts to maximize the power delivered to the load * by adjusting the duty cycle of the pulse width modulated output. * The routine starts by calculating the power level at the present pulse * width setting. The pulse width is perturbed and the power level * recalculated. If the power level decreases twice the direction of the * pulse width perturbation is reversed. The peak power level and its' * associated voltage level is recorded for further reference. * A number of peak power levels and their associated voltage levels * are recorded. The maximum power tracking voltage is then calculated * by averaging the voltages corresponding to the top few of the peak * power levels. * * ASSUMPTIONS: * 1) The current signal is tied to AN1 and the array voltage * signal to line AN2. * 2) The load current is approximately continuous throughout * the ON and OFF converter states, ie. the load is * inductive. * * INPUT: The initial step size by which the pulse width is to * be initially perturbed in STEP. * * OUTPUT: * 1) The duty cycle is adjusted for maximum power output. * 2) The voltage corresponding to the maximum power level * is placed in MAXVLT. * 3) The offset current is returned in OFFSET and the open * circuit voltage in OPEN. * 4) The value of the maximum power level is returned * in MAXPWR and the maximum current reading in MAXCUR. * * REGISTERS EFFECTED: CC * Appendix A. Assembly Language Program 98 **************************************************** * NMBR EQU 6 ARYMAX EQU 12*3+ARRAY MAXPWR PSHA PSHB PSHX PSHY CLR * LDD STD STD STD STAB LDY LDX BSET BSET * BCLR * * Enter * power * MAXLP1 PSHX * MLP1 Save the register state. COUNT Clear the counter which records the number of overcurrent incidents. #0 POWER Clear the variables used. TEMP TMPVT1 MAXVLT #PORTB #ARRAY Load the base Array address. FLG FRST Set the bit to indicate the first pass. FLG UP Set the bit to increase the pulse width. Clear the bit signalling a decreasing power level. FLG DECRS the loop which perturbs the pulse width and records peak levels along with their operating voltage levels. Save the array address. Call for a delay. Load the address of a timer node. LDX #TMEN0D JSR CLRTME LDAB #DLAY STAB 2.X JSR ADDTME JSR CMPTME TSTA BNE MLP1 LDAA #RDVLT JSR READ STAB VOLT JSR CURNT STAB CURR LDAA VOLT Read in the array voltage. Read in the corrected current value Calculate the power output. Appendix A. Assembly Language Program 99 WAI MUL PULX Retrieve the array address. * BRCLR FLG FRST MLP2 If not the first power reading, branch. BCLR FLG FRST Clear the flag bit indicating a first pass. STD POWER Save the power reading. LDAB VOLT STAB TMPVT1 Save the operating voltage. BRA MLP4 * MLP2 CPD POWER Check if the power level is increasing. BLS MLP3 If NO, branch. * * This program section is entered when the * power level is increasing. * * If the converter is turned fully ON, branch. BRCLR ,Y ON CHDIR1 * BCLR FLG DECRS Clear the decreasing power level flag. JSR PRUPD Update the power levels. BRSET ,Y OFF MLP4 * If the converter is turned fully off an error JMP BEGIN has been detected, so start again. * * This program section is entered when the power level * is decreasing. * * If the power has twice decreased, branch. MLP3 BRSET FLG DECRS CHDIR2 BRCLR ,Y ON CHDIR3 If converter turned fully ON, branch. BRCLR ,Y OFF CHDIR3 If the converter is turned fully OFF, branch. BSET FLG DECRS Set the decrease flag. JSR PRUPD Update power levels. * * Change the pulse width * MLP4 LDAB STEP LDAA #1 Indicate an increase in the pulse width. * Branch if the pulse width is to be Appendix A. Assembly Language Program 100 MLP4B BRSET FLG UP MLP4B CLRA JSR CHANGE increased. Else indicate a negative change. Change the duty cycle. MLP4C * MLP4D CHDIR1 Test for overcurrent and branch if clear. BRCLR FLG OVRCUR MLP4D This section is entered if an overcurrent fault has been detected. LDAA COUNT INCA Increment the overcurrent counter. BCLR FLG OVRCUR Clear the overcurrent flag. CMPA #7 BNE MLP4C JMP OVRDLY Exit if the number of overcurrent occurrences = 7 STAA COUNT JMP MAXLP1 Enter the power tracking loop again. CHDIR is local to the maximum power routine. CHDIR reverses the direction of the maximum power search. It also places the last peak power value and its' associated operating voltage in the array pointed to by the X register. The array pointer is updated and the power search is ended after enough data points have been collected. CHDIR1 is called when the power level is increasing and the converter is turned fully ON. PSHA PSHB STD STD ,X POWER LDAB VOLT STAB 2.X Save the power reading in the array. Save the associated voltage reading. BRA CHDIR4 * CHDIR2 is called when the power has decreased twice. CHDIR2 PSHA Appendix A. Assembly Language Program 101 PSHB LDD TEMP STD ,X Save the power reading in the array. LDAB TMPVT2 STAB 2,X Save the associated voltage reading. BRA CHDIR4 * * CHDIR3 is called when the power level has decreased * once and the converter is turned fully ON. * CHDIR3 PSHA PSHB LDD POWER Save the last power reading in the STD ,X maxpower array. LDAB TMPVT1 STAB 2.X Save the associated voltage reading. * * This program section is common to all three subroutines * which change the direction of the maximum power search. * CHDIR4 PULB Retrieve the last power reading. PULA STD POWER Save the last power reading. LDAB VOLT STAB TMPVT1 Save the last voltage reading. CLR TEMP CLR TEMP+1 CLR TMPVT2 INX Update the array pointer. INX INX CPX #ARYMAX IF enough data points have been collected. BHS EXITL1 EXIT the maximum power searching loop. Toggle the direction of the maximum power search. LDAB FLG COMB ANDB #UP BEQ CHDIR5 BSET FLG UP Set the flag to increase the pulse width. BRA CHDIR6 Appendix A. Assembly Language Program 102 CHDIR5 CHDIR6 CHDIR7 EXITL1 MAXLP2 MAXLP3 MLP5 BCLR FLG UP Clear the flag so that the pulse width will be decreased. BCLR FLG DECRS Clear the flag which signals one power decrease. Reduce the step size. LDAB STEP LSRB Divide the step by two. CMPB #2 Compare the step to a minimum value. BHS CHDIR7 LDAB #2 STAB STEP Save the new step value. BRA MLP4 This program section is entered when enough data points have been collected and it is time to exit the power search loop. CLRA CLRB PSHB Set a counter to zero. STD POWER Clear memory locations. STD TEMP STD TMPVT1 LDX #ARRAY load the array base address. PSHX LDD .X Load the power level of array item(i). CPD POWER BLO MLP5 If power level is the highest yet found, STD POWER Save the value of the power level and a pointer INS to its' place in the array. INS PSHX INX Update the array pointer. INX INX CPX #ARYMAX If the end of the array has not been found, BLO MAXLP3 loop again. The maximum power value has been located. Appendix A. Assembly Language Program 103 MLP6 MLP7 PULX LDD BNE LDD CPD BLS STD CLRA LDAB STD TMPVT1 MLP7 POWER PWRMAX MLP6 PWRMAX 2,X TMPVT1 PULB INCB PSHB CLRA LDAB 2.X ADDD TMPVT1 STD TMPVT1 LDD #0 STD POWER STD ,X PULB INCB PSHB CMPB #NMBR BLO MAXLP2 Load the pointer to the highest power level. If not the first value, branch. If this is the highest power level yet obtained, save it. Load the associated voltage level. Save it to add extra weight to the voltage level associated with the highest power level. Increment the counter. Set the power level of the value just processed to zero. Have the desired number of data points been processed? No, collect another data point. Divide the sum of the voltage levels by the number of samples PULB CLRA LDX TMPVT1 XGDX WAI IDIV LSLD SUBD #NMBR MLP8 BLO INX XGDX TSTA MLP8 Fetch the number of data samples. Fetch the accumulated voltage sum. Round off the result Increment the quotient, Appendix A. Assembly Language Program 104 BEQ MLP9 * An error has been detected so restart the program. * JMP BEGIN * MLP9 STAB MAXVLT Store the voltage level to track which corresponds PULY to the maximum power point. PULX PULB PULA RTS A.9.1 Change Search Direction ^ 3^ )|c -t* ^  ^ *^ 4* ^ ^ ^r* ^ ^1* 4c*^^i5(l*^*^5|C5(c 5JC 5|c T^C^fc^^^Sfc^^ 5^ 3^* 3(/i 3JC 5JC *(c ^ }(c -^C S^CSjcsksf^I'lc^.^?^^^?^ This subroutine which can be considered local to the maximum power routine updates the power levels. INPUT: 1) Current power level in D register. 2) Operating voltage level in VOLT. OUTPUT: 1) Current power level is placed in POWER. 2) Last power level is placed in TEMP 3) Current voltage level is placed in TMPVT1 4) Last voltage level is placed in TMPVT2 * PRUPD PSHA Save the operating power level. PSHB LDD POWER Move the last power level to TEMP. STD TEMP LDAB TMPVT1 Move the last voltage reading to TMPVT2. STAB TMPVT2 LDAB VOLT Move the current voltage reading to TMPVT1 STAB TMPVT1 PULB PULA Store the current power level in POWER. STD POWER RTS Appendix A. Assembly Language Program 105 A. 10 Current Adjustment ***************************************** * * SUBROUTINE CURNT ************************************************************************* * * * This subroutine reads and adjusts the value of the current being * read by the A/D converter. An adjustment may be necessary if the current * signal has a DC offset. * * ASSUMPTIONS: 1) The current has settled to a steady state value. * 2) The offset current has been recorded. * * INPUT: None. * * OUTPUT: The adjusted current value in the B register. * * REGISTERS EFFECTED: B.CC. *• * CURNT PSHA LDAA #RDCURR Read in the current from the A/D. JSR READ SUBB OFFSET Subtract the DC offset. BHS CUR1 Did the result overflow? CLRB Yes? Set the result to zero. CUR1 PULA Else continue. RTS A.11 Voltage Tracking Routine * * * SUBROUTINE VLTRAK * Appendix A. Assembly Language Program 106 * This subroutine maintains the array voltage at the level specified * in the memory location MAXVLT. The array voltage is adjusted by * varying the duty cycle of the power MOSFETS. * * ASSUMPTIONS: * 1) The timers are initialized and running. * 2) The voltage corresponding to the maximum power point * has been determined. * * INPUT: The reference array voltage in MAXVLT. * * OUTPUT: * 1) The duty cycle is adjusted to track the reference * voltage. * 2) The operating array current, load current, array * voltage and power output levels are updated. * REGISTERS EFFECTED: CC * VLTRAK PSHA Save the state of the A and B registers. PSHB JSR CURNT Read the current. STAB CURR LDAA #RDVLT Read in the operating voltage. JSR READ PSHB * Take two sets of readings and average them. LDAA #RDVLT JSR READ PULA ABA Add the first and second readings. RORA Divide the result by two. TAB Place the result in the B register. STAB VOLT * * Calculate the error voltage, delta V. SUBB MAXVLT BEQ VLTRTN Appendix A. Assembly Language Program 107 BHI INCRSE INCRSE VLTRTN If this program section is entered the array is operating at less than its' optimum voltage. Therefore decrease the MOSFETS' ON time. NEGB BSR LDAA JSR BRA DELTA #1 CHANGE VLTRTN Form the absolute value of the error voltage. Calculate the change in the ON time required. Delta ON will be returned in the B register. Indicate a decrease in the pulse width. Ramp down the duty cycle. If this program section is entered the array voltage is higher than its' optimum value. Therefore increase the MOSFETS' ON time. BSR DELTA CLRA JSR JSR PULB PULA RTS CHANGE LOAD Calculate the change in the ON time required. Delta ON will be returned in the B register. Indicate an increase in the pulse width. Ramp up the duty cycle. Determine the load current and voltage. Restore the A and B registers. A.11.1 Adjustment to the Duty Cycle * * SUBROUTINE DELTA * * This subroutine calculates the change to the ON time of the pulse * width modulated waveform according to the formula: * * delta ON = delta V * ON / Varray * * Where ON is the last ON time, delta V is the error voltage and * Varray is the operating array voltage. Appendix A. Assembly Language Program 108 delta ON = delta V * ON / Varray ASSUMPTION: The timers are initialized and running. INPUT: 1) The error voltage in the B register. 2) The operating voltage in VOLT. 3) The current on time in ON. OUTPUT: 1) The change in the ON time in the B register. REGISTERS EFFECTED: B.CC sly *L» sly *1* *1* *L» sly *1* sly Jy »ly sL. sly sly sL- sL- sly si. si' si* sly sly si- d'^^^X^st^' sly s^ s^ s^ sL> sL< ^ ^ «k s^ ^ ^u^s^sL*LsVsUs^^'sVs^s^ >V ^ ^ *^ >k ^ >^ ^ *^ *^ *V *1* sUslysUslysLysksl»sL. y^y^y^y^y^y^y^y^yT.y^y^yT.yT^^^^^^^^^^^^ * DELTA PSHA Save the contents of the A and X registers. PSHX LDAA 0NCNT1+1 Multiply the ON time by the error voltage. WAI MUL XGDX LDAB VOLT CLRA XGDX WAI IDIV Store the result in the X register. Load the operating voltage. Wait for an interrupt to complete as the next instruction takes 41 cycles, (delta V * ON) / Varray. Check the remainder to see if the result should be incremented. LSLD Multiply the remainder by two. TSTA If the reminder spills into the A register BNE DLP1 the result should be incremented. DLP1 DLP2 CMPB VOLT BLO DLP2 INX XGDX TSTA If 2 * remainder < VOLT do nothing Else increment the result. Appendix A. Assembly Language Program 109 DLP3 DLP4 ERROR BNE ERROR TSTB BNE DLP3 INCB CMPB #1 BEQ DLP4 LSLB PULX PULA RTS JMP BEGIN If A is not equal to zero an error has occurred. Set the change to one if the result was zero. Multiply the result by two. Restore the X and A registers Restart the whole process. A. 12 Read Open Circuit Voltage and Current * SUBROUTINE ADJOPN * This subroutine reads in the open circuit voltage and current * offset upon start-up. * * ASSUMPTION: Timers are initialized. * * INPUT: None. * * OUTPUT: 1) The open circuit voltage in OPEN. * 2) The offset current in OFFET. * 3) The portion of the current signal created by noise in CORECT * * REGISTERS EFFECTED: CC. ADJOPN PSHA Save registers used by the routine. Appendix A. Assembly Language Program 110 ADLP1 PSHB PSHX PSHY LDY #P0RTB Turn the converter off. BCLR ,Y ON BCLR FLG 1 Signal the start up of the pulse width modulation process. LDX #TMENOD Load the address of a timer node. JSR CLRTME Clear the timer node. LDAA #DLAY Call for a delay. STAA 2.X JSR ADDTME JSR CMPTME Wait TSTA BNE ADLP1 LDAA #RDVLT Read in the open circuit voltage. JSR READ STAB OPEN Save the value of the open circuit voltage LDAA #RDCURR Read in the offset current. JSR READ STAB OFFSET Save the value of the offset current. Start the pulse width modulation process LDD #1 LDX #1 JSR ADJST PULY PULX Restore the machine registers. PULB PULA RTS A.13 Calculate Load Voltage and Current ****** ***************************************** * * SUBROUTINE LOAD ************************************************************************* Appendix A. Assembly Language Program 111 This subroutine calculates the average load voltage and current knowing the average supply voltage and current and the duty cycle. ASSUMPTIONS: 1) The count representing the period is less than 256. INPUT: 1) The supply voltage in VOLT. 2) The supply current in CURR 3) A number representing the on time in ONCNT. 4) A number representing the period in PERIOD. OUTPUT: 1) The load voltage in MOTVLT. 2) The load current in MOTCUR. REGISTER EFFECTED: CC. LOAD PSHA PSHB PSHX LDAA PORTB COMA ANDA #0FF BNE LDOFF LDAA PORTB COMA ANDA #0N BNE LDON Check if the converter is turned fully OFF. Branch if the converter is turned off Check if the converter is turned fully ON. Branch if the converter is turned fully ON Calculate the average load voltage. LDD 0NCNT1 ADDD 0NCNT2 LSRD LDAA VOLT WAI MUL LDX PERIOD WAI IDIV Average the two ON counts Load voltage = supply voltage * ONCNT / PERIOD. Appendix A. Assembly Language Program 112 LD1 LD2 LDON LSLD Round off the quotient by inspecting the CPD PERIOD remainder. BLO LD1 Increment the quotient if 2 * remainder is INX greater than the divisor. XGDX TSTA If A .NE. 0 an error has occurred. BNE LDERR STAB MOTVLT Record the load voltage. Calculate the average load current. 0NCNT1 0NCNT1 LD2 MOTCUR Fetch the current reading. Load current = supply current * PERIOD / ONCNT. Round off the quotient by inspecting the remainder. Increment the quotient if 2 * remainder is greater than the divisor. Record the load current as a 16 bit data item. LDD PERIOD LDAA CURR WAI MUL LDX WAI IDIV LSLD CPD BLO INX XGDX STD PULX PULB PULA RTS This program section is executed if the converter is turned fully ON. LDAB CURR CLRA STD MOTCUR Load current = supply current. LDAB VOLT STAB MOTVLT Load voltage = supply voltage. PULX PULB PULA RTS Appendix A. Assembly Language Program 113 * This program section is executed if the converter is turned * fully OFF. * LDOFF CLR MOTVLT Load voltage = 0. CLR MOTCUR CLR MOTCUR+1 Load current = 0. PULX PULB PULA RTS * LDERR JMP BEGIN An error has been detected so start again. A.14 Change the Duty Cycle in Small Increments 'i^- sfr* •'t^ 4^ 4^ 4^ sfc sf^ -5^c S'fc sfc sfc 'f1* s|c s^c sfc ^J^- sfc ^{c * SUBROUTINE CHANGE * Subroutine change ramps up or down the duty cycle from its present * value to its' desired value in one step increments. * * ASSUMPTIONS: 1) The count representing the period is less than 256. * * INPUT: 1) An integer which indicates the direction of the * change in the A register. * 0: Increase the pulse width. * 1: Decrease the pulse width. * 2) An unsigned integer representing the change in the ON * count in the B register. * 3) The current on time in 0NCNT1 and 0NCNT2. * 4) The period in PERIOD. * * OUTPUT: 1) The duty cycle is ramped up or down. * REGISTERS EFFECTED: B.CC. Appendix A. Assembly Language Program 114 ******************************************** CHANGE PSHY PSHX PSHA PSHB LDY LDX * * * CHLP1 * * * CHNXT #PORTB 0NCNT2 CMPA #1 BHI CHERR BEQ TSTB BEQ NEGCHG CHRTN Check if the duty cycle is to be increased or decreased. Branch if the parameter is illegal. Branch if the duty cycle is to be decreased. If change = 0 return. If an overcurrent condition is encountered, return. BRSET FLG OVRCUR CHRTN Increase the duty cycle in one count increments. PSHB LDD CPD BHI INCB CPD BHS CPX BNE 0NCNT1 0NCNT2 CHLP2 PERIOD CHON #0 CHNXT XGDX PULB DECB PSHB XGDX LDX INX JSR WAI BSET ,Y RUN PULB #0NCNT2 ADJST Branch if 0NCNT2 < 0NCNT1 Increment the ON time. If ONCNT = PERIOD turn the converter fully ON. Make sure 0NCNT2 does not equal zero. If 0NCNT2 = 0, increment it. Decrement the step counter. Increment 0NCNT2 Adjust the duty cycle. Appendix A. Assembly Language Program 115 CHLP2 DECB BLS BRA INX CPX BEQ JSR WAI BSET PULB DECB BEQ BRA CHRTN CHLP1 PERIOD CHON ADJST ,Y RUN CHRTN CHLP1 Return if the adjustment of the duty cycle is complete. Adjust the duty cycle. Return if the adjustment of the duty cycle is complete. Decrease the duty cycle in one step increments. NEGCHG PSHB LDD CPD BLO DECB BEQ JSR WAI BSET PULB DECB BEQ BRA CHLP3 DEX BEQ JSR PULB DECB BLS BRA CHRTN PULB PULA PULX PULY RTS 0NCNT1 0NCNT2 CHLP3 CHOFF ADJST ,Y RUN CHRTN NEGCHG CHOFF ADJST CHRTN NEGCHG Branch if 0NCNT2 > 0NCNT1 Decrement the ON time. Adjust the duty cycle, Return if the adjustment of the duty cycle is complete. If the ON count = 0 turn the converter fully OFF. Adjust the duty cycle. Return if the adjustment of the duty cycle is complete. Appendix A. Assembly Language Program 116 CHERR * CHON CHOFF Start again if an error in the input parameter indicating the sign of the change is detected. JMP BEGIN Turn the converter fully ON. BCLR ,Y ON BSET ,Y OFF INS PULB PULA PULX PULY RTS Turn the converter fully OFF. BCLR .Y OFF BSET ,Y ON INS PULB PULA PULX PULY RTS Restore the register state, Restore the register state A.15 Overcurrent * OVRDLY * * Control will be passed to this routine if the overcurrent * interrupt has been repeatedly activated. * * This routine turns off the Mosfets, introduces a half hour XSI * *ipeq.s eiiq. uo apou jerarq. e aq.eaJO * •sq.sanbaj q.dnjjaq.UT ajeduioo q.ndq.no exqeug no •sq.dnaj8q.UT q.uajjnDJ8AO x^uoT^TPP18 9Icl1S8Ta 0fr$ X4 H109 ooid# xai yyoHAO * sl* sly sly si* sly si* sly sly si* si* sL* si* si* sly sly si* sly sly si* ij> sly sly sly si* sly sly sly sly si* sly sly sly sly si* sty sly si* si* sly sly sly sly sly sly sly si* sly sL* si* sly sly sly st* si* «A* sly sly >±» sL* sL- sly vL. sL* >X- *X" »L* st* sL- -sL- "sly *^*^*'J(y^y](y^y^y|t*,|(yf*. yjt ^ Jfi y]t yfk y^ y^ yf( yf( J|k yj^ yf* JJ^ y^ y^ y^ y]tyfky|tj|s<y^y^y^y^ **fh y^ y^ y^ y^ y^ y^ y^ ^ ^ *^ y^ y^ y|^ yp ^ *^ #^ yp *J» y^y^**^y^ *js 'T" "T* *T* *T* 'T* *P 1* *l* •ipoio doxj dtxj au;q. se sqoe U;OTU;M giHOd 10 2 q.iq 2ujqojq.s * iCq qasaj ST. OIHOd 10 ojsz q.Tq 'paonpaj ST X9AST q.U8Jjno axiq. ueuji * * • 3ATQ.DB ST uoTQ.oaq.ojd q.uajjnoJ8AO aiiq. USXJM MOX Q-as OSXB ST DIHOd 10 * ojez q.Tg •auxq.noj q.dnjJ8q.UT STiiq. saq.BTq.TUT VHiS J° s9ps SuiTI181 V * • aAtq.De ST ejBMpjeu; uorq.D8q.OJd * qusjjnDjeAO aiiq. IT uoTq.Das raej9ojd STirq. oq. passed aq XTTW Xo:t:l-uoO * ********************************* * •UTB9B q.jeq.g mvis dwr •dn qou sx amrq. IT dooq SAIOAO 3N3 V1S1 eraTq. quajjno aiiq. oq. apou jemiq. aiiq. ajedmoo 3WIdWD ysr awiaav use x'e avis •sraTq. aiiq. oq. saqxiUTin 0£ PPV oe# aval 3WIH10 HSf •apou jainTq. aiiq. Jeaxo a0N3WI# xen 3DNVH0 usr T# wai •anx^A SINDNO aaav mnfflxuTTii sq.x oq. joq.exnpora u.q.piM asxnd aiiq. aonpay .TINDN0 aai NO A' i3sa • }}o SI3JS0W Jswod aiiq. ujnx JJO A' moa aiHOd# Adl ************************************************************************** * •raejSojd aqq. sq.jeq.S8J uaqq. 'A"exap * ill UIVJSOJJ aSvnSuvq A~[qwdssy y xipuaddy Appendix A. Assembly Language Program 118 0VR1 0VR2 CLEAR Subtract six bytes from the stack base address. Place the new address on the stack. The X register now contains an address with six free bytes available for a timer node. Clear the timer node. Add a second to the time of day and place the result in the timer node. Compare the timer node to the current time. Loop if time is not up. Strobe the clock of overcurrent flip flop 2 in an attempt to clear the interrupt request. XGDX SUBD #6 XGDX TXS JSR CLRTME LDAB #DLAY STAB 2,X JSR ADDTME JSR CMPTME TSTA BNE 0VR2 LDY #P0RTB BSET ,Y 4 BCLR ,Y 4 BSET ,Y 4 BCLR ,Y 4 Branch if the overcurrent condition has been cleared. LDY #P0RTC BRSET ,Y 1 CLEAR The overcurrent condition persists so reduce the pulse width. LDAB #2 Reduce the pulse width. LDAA #1 JSR CHANGE BRA 0VR1 Attempt to clear the fault again. The overcurrent condition has been cleared so return to the interrupted routine. LDAB #6 Restore the stack to its original condition. ABX TXS Set the overcurrent flag bit. BSET FLG OVRCUR LDAA PIOC LDAA PRTCL Clear the interrupt flag. Appendix A. Assembly Language Program 119 LDX #PIOC WAI SEI Inhibit interrupt requests. BSET ,X $40 Enable additional overcurrent interrupts. RTI A. 16 Output Compare One Interrupt ****************************************** * * Control will be passed to this program section in the event of * a successful compare of 0C1 if the interrupt is enabled. ************************************************************************ * Clear the interrupt request and enable the next interrupt. Load the contents of the output compare 1 reg. which caused an interrupt. LDAA TFLG1 STAA TFLG1 LDD REG0C1 ADDD 0NCNT1 STD REG0C2 ADDD 0FCNT1 STD REG0C3 ADDD 0NCNT2 STD REG0C4 ADDD 0FCNT2 STD REG0C1 RTI A.17 Output Compare Two Interrupt * * * * INTR2 LDAA TFLG1 STAA TFLG1 LDD REG0C2 ADDD 0FCNT1 STD REG0C3 ADDD 0NCNT2 Control will be passed to this program section in the event of a successful compare of 0C2 if the interrupt is enabled. Clear the interrupt and enable the next interrupt request. Load the contents of compare register 2 which just caused an interrupt. Update the output compare 3 register. Appendix A. Assembly Language Program 120 STD REG0C4 Update the output compare 4 register. ADDD 0FCNT2 STD REG0C1 Update the output compare 1 register. ADDD 0NCNT1 STD REG0C2 Update the output compare 2 register. RTI * Place the interrupt vectors in memory. * ORG $FFDE FDB TMINTR ORG $FFE6 FDB INTR2 Insert the interrupt vectors in memory. FDB INTR1 ORG $FFF2 FDB OVRCRR END Bibliography [1] J.A. Roger, Water and Photovoltaics in Developing Countries, Solar Cells (Switzerland), vol. 6, no. 3, Aug. 1982, pp.295-308. [2] P.R.B. Ward, W.G. Dunford and D.L. Pulfrey, Performance of Small Pumps with Solar Power, Proc. Canadian Society of Civil Engineering, 7th Canadian Hy-drotechnical Conference, Saskatoon, pp.249-258, 1984. [3] M.A. Green Solar Cells: Operating Principals, Technology and System Applica tions, Prentice-Hall series in solid state physical electronics, 1982. [4] D. L. Pulfrey, P.R.B. Ward and W.G. Dunford, A Photovoltaic-powered system for medium head pumping Solar Energy, vol. 38, no. 4, 1987, pp255-256. [5] M.B.Aylward and B. McNeils, Small scaled solar pumping systems - present status and future prospects, Int. Jour, of Ambient Energy, vol 5, no. 3, July 1984, ppl47-158. 121 

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