T H E MULTI-SAMPLING DIGITAL TANLOCK LOOP FOR TRACKING SUPPRESSED-CARRIER M A R Y PSK SIGNALS Joel A. Bisson B.A.Sc . Univers i ty of Waterloo, 1987 A THESIS S U B M I T T E D I N PARTIAL F U L F I L L M E N T OF T H E R E Q U I R E M E N T S F O R T H E D E G R E E OF M A S T E R OF A P P L I E D S C I E N C E in T H E F A C U L T Y OF GRADUATE STUDIES D E P A R T M E N T OF E L E C T R I C A L E N G I N E E R I N G We accept this thesis as conforming to the required standard T H E UNIVERSITY OF BRITISH C O L U M B I A September 1989 ©Joel A. Bisson, 1989 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. The University of British Columbia Vancouver, Canada DE-6 (2/88) Abstract A Multi-Sampling Digital Tanlock Loop ( M D T L ) is proposed for t racking suppressed-carrier M-ary Phase-Shift Keyed signals. U n l i k e the conventional Digital Phase-Locked Loop ( D P L L ) which possesses a sinusoidal phase characteristic, the M D T L has a l inear phase characteristic wi th a period of 2-K/M. Consequently, the M D T L can be characterized by a l inear difference equation which eliminates the approximations of nonlinearity seen i n the conventional D P L L . The linear difference equation also provides many attractive features over the conventional D P L L . These include locking conditions which are insensitive to variations i n signal power, enhanced noise immuni ty , wider lock range and reduced steady-state mean phase error for the first order loop when the received signal has a frequency offset. A first-order M D T L is analyzed i n the noiseless case. Closed-form expressions were derived for the steady-state mean phase error, the region of stability, the lock range and the acquisition time. It is shown that the use of mult i -sampling improves the performance of the M D T L over the conventional Dig i ta l Tanlock Loop by increasing the region of stability and consequently, the lock range, and by decreasing the steady-state mean phase error and the acquisition time. In the presence of noise, the task of modell ing the M D T L is parti t ioned into a software testbed and a hardware testbed. Both the software and hardware testbed simulate the M D T L i n the presence of noise. The hardware testbed, however, also includes other important impairments such as quantization effects and loop delay. The software testbed represents the reference model against which the hardware testbed can be compared and measured. The phase error, the acquisition time and the hold-in time are the three performance measures used to characterize the performance of the M D T L i n the presence of noise. It is shown that mul t i -sampl ing can be used as an acquisition aid without increasing the standard deviation of the phase error distribution. For binary phase-shift keying, four bits of sampler quantization and 64 levels of numerically-controlled oscillator resolution are needed to provide negligible performance degradation compared to the infinite quantization case at a received signal-to-noise ratio of zero d B . The M D T L design is simple. Dig i ta l implementation of the M D T L provides an opportunity for enhanced system integration us ing Very Large Scale Integration techniques for high speed applications or Digital Signal Processing microprocessor techniques for slower speed applications. i i Table of Contents Abstract i i List of Tables v i List of Figures v i i Acknowledgements x 1 Introduction 1 1.1 Synchronization i n Dig i t a l Communicat ion Systems 1 1.1.1 Hierarchica l Synchronization i n a Communicat ion System 1 1.1.2 Car r ie r Synchronization for Suppressed-Carrier M-a ry P S K Signals 3 1.1.2.1 Conventional Techniques 4 1.1.2.2 Dig i ta l Techniques 5 1.2 Scope of the Thesis 5 1.3 Organizat ion of the Thesis 6 2 Review of Previous Work 7 2.1 Phase-Locked Loops 7 2.2 D ig i t a l Phase-Locked Loops 8 2.2.1 The Zero Crossing D P L L 10 2.2.2 The Dig i t a l Tanlock Loop 13 2.2.2.1 The D T L for Tracking Suppressed-Carrier P S K Signals 14 2.2.2.2 The D T L wi th Mul t i -Sampl ing 14 3 Characterization of the MDTL 15 3.1 Assumptions 15 3.2 Description of the M D T L 16 3.2.1 The Ana log Front E n d 16 3.2.2 The Numerical ly-Control led Oscillator 19 3.2.3 The Phase Detector 20 i i i 3.2.4 The Dig i t a l Loop F i l t e r 25 3.3 System Equations of the M D T L 26 3.3.1 The Baseband Model 26 3.3.2 The Phase Er ro r Difference Equat ion 28 3.3.2.1 The Steady-State M e a n Phase E r r o r i n the Absence of Noise 29 3.3.2.2 Locking Conditions 29 3.3.2.3 Lock Range 33 3.3.2.4 Acquis i t ion Statistics i n the Absence of Noise 36 3.3.3 Comparison of the M D T L wi th Loops Employ ing the Tanlock Principle . . . . 39 4 Testing Environment of the MDTL 43 4.1 Software Platform of the M D T L 44 4.1.1 S imula t ion Requirements 44 4.1.2 Test Configuration 45 4.1.3 Calcula t ing the Input S N R 47 4.2 Hardware Platform of the M D T L 49 4.2.1 Funct ional Description of the Loop Components 49 4.2.1.1 The Analog Front E n d 50 4.2.1.2 The Phase Detector / Da ta Extractor 52 4.2.1.3 The Dig i ta l Loop Fi l te r 55 4.2.1.4 The Numerical ly-Control led Oscillator 57 4.2.1.5 The Sequencer 60 4.2.2 Test Configuration 61 4.2.3 Calcula t ing the Input S N R 62 5 Performance Evaluation 65 5.1 Phase Er ro r Statistics 65 5.1.1 Defining the Test Procedure 66 5.1.2 Phase Er ro r Results 68 5.2 Acquis i t ion Statistics 73 5.2.1 Defining the Test Procedure 74 5.2.2 Acquis i t ion Results 75 iv 5.3 Hold-In Statistics 79 5.3.1 Defining the Test Procedure 79 5.3.2 Hold-In Results 83 6 Conclusions 85 6.1 Summary of Research Results 85 6.2 Suggestions for Future Work 87 References 89 A Mathematical Derivations 94 B Topology Files of the Simulated MDTL 100 C Details of the Hardware Design 105 v List of Tables 4.1 Actions Performed by the F S M 61 5.1 Standard Deviat ion <rq (in Radians) of the Reduced Phase E r r o r Process as a Function of A, B and Eb/N0 69 C.l Features Incorporated into the Transmitter 107 C .2 T M S Port Assignments 109 v i List of Figures 1.1 Example of a Communicat ion System 3 2.1 Block Diagram of the Phased-Locked Loop 7 2.2 Simplif ied Block Diagram of the D P L L 8 2.3 Block Diagram of the F F - D P L L Phase Detector 9 2.4 Block Diagram of the L L - D P L L Phase Detector 10 2.5 Block Diagram of the Z C - D P L L Phase Detector 10 2.6 G i l l and Gupta's D P L L (a) Block Diagram (b) the D P L L ' s Sampl ing Process wi th Respect to the Incoming Signal x (t) 11 2.7 Block Diagram of the D T L 13 3.1 Block Diagram of the Mul t i -Sampl ing Dig i ta l Tanlock Loop 17 3.2 Modulo 27r L imi t e r for the t a n - 1 Function 22 3.3 Phase E r r o r Est imate for the Case M = 2 i n the Absence of Noise 24 3.4 The Baseband Model for the M D T L i n z Operator Notat ion 27 3.5 Discrete Phase Plane Plot for Different Values of A 0 and K' 31 3.6 Discrete Phase Plane Plot wi th Conditions LI and L2 True, (a) <p0 — —TT/3 Converges (b) cp0 = — 47r/5 does not Converge 31 3.7 (a) Lock ing Region of the M D T L for A = B = M = 1 (b) Discrete Phase Plane Plot for A 0 = 7r/5 and K' = 8/5 (c) Sampl ing Process w i th Respect to the Inphase Signal x (t). 33 3.8 Lock ing Region for Various Values of A, B and M 34 3.9 Lock ing Region i n Terms of the Normal ized Dig i ta l Loop Coefficient and the Frequency Offset Rat io 36 3.10 Normal ized Acquis i t ion Times versus Ini t ia l Phase Er ro r for K' = 1/5, A„ = n/10, (pc = 7 r / 3 2 M and Various Values of A,B and M 40 3.11 Probabil i ty of Acqu i r ing Lock versus the Normal ized Total Elapsed Time for K' — 1/5, A0 = TT/10, and <pe = TT/32M (a) M = 1 (b) M = 2 41 4.1 Block Diagram of the M D T L Test Configuration 46 4.2 S imula t ion of the Transmit ted B P S K Waveform with/without A W G N . (a) Sample Time-Domain Representation (b) Power Spectral Est imat ion. 48 v i i 4.3 Block Diagram of a Hardware Implemented MDTL 49 4.4 Block Diagram of the AFE 50 4.5 Block Diagram of the PD/DE 52 4.6 Mapping From / and Q Samples to the Phase Angle Estimate 54 4.7 Block Diagram of the Digital Filter 55 4.8 Block Diagram of the NCO 58 4.9 State Diagram of the FSM 60 4.10 The Hardware Test Environment 62 4.11 Photograph of the Hardware Implementation 63 5.1 PDF of an Unbounded Phase Error Process 65 5.2 Sample PDFs of the Reduced Phase Error for a BPSK Signal 67 5.3 PDFs of the Reduced Phase Error qk Obtained from the Software Simulation 68 5.4 PMFs of the Reduced Phase Error qk Obtained from the Hardware Implementation. 70 5.5 Standard Deviation aq as a Function of the Number of Sampler Quantization Bits and the NCO Resolution 72 5.6 Cumulative Distributions of the Acquisition Time Obtained from the Software Simulation for Different SNRs and Values of A 76 5.7 Cumulative Distributions of the Acquisition Time Obtained from the Hardware Implementation for Different SNRs and Values of A 78 5.8 Cumulative Distributions of the Acquisition Time in the Absence of AWGN 79 5.9 Discrete Phase Plane Plot of the MDTL in the Presence of Noise 80 5.10 Reduced Discrete Phase Plane Plot of the MDTL in the Presence of Noise 81 5.11 Cumulative Distribution of the Hold-In Time Obtained from the Hardware Implementation for Eb/N0 - 0 dB and A = B = 1 83 C l Block Diagram of the Transmitter 106 C.2 Block Diagram of the Noise Channel 107 C.3 Block Diagram of the TMS Interface 109 C.4 Photograph of the Test Configuration 110 C.5 Sampled I and Q Waveforms for BPSK Signalling I l l viii C.6 Spectrum of the A F E (a) I and Q Noise Samples (b) Spectral Est imate of the Inphase A r m 112 C.7 Unmodula ted Sinusoid (a) / versus Q Samples (b) Spectral Est imate of the Sine A r m 112 C.8 Sampler Degradation (a) - (c) / versus Q Samples of an Unmodulated Sinusoid wi th Different S ignal Strengths (d) - (f) Spectral Estimates 114 C.9 Sampled B P S K / and Q Waveforms wi th Windowing 114 C.10 Power Spectral Estimates of Various Modulated Signals 116 C.l l Schematic of the Analog Front E n d 117 C.12 Schematic of the Phase Detector/Data Extractor 118 C.13 Schematic of the Dig i ta l Loop F i l t e r 119 C.14 Schematic of the Numerical ly-Control led Oscillator 120 C.15 Schematic of the Sequencer 121 C.16 Schematic of the Transmitter 122 C.17 Schematic of the T M S 320C25 Interface 123 C.18 Schematic of the T M S Read Ports 124 C.19 Schematic of the T M S Write Ports 125 C.20 Schematic of Miscellaneous Circui ts 126 ix Acknowledgements I would l ike to thank Dr . R. W. Donaldson for his suggestions and supervision dur ing this project. In addition, I would l ike to thank R. A . Jeffery, M . M i l l e r and E . Casas for their discussions and invaluable suggestions and D. Sapach and N . Robidoux for their work on the hardware implementat ion of the M D T L . Special thanks to my companion, Brigi t te Vachon, for her constant support and encouragement. F inanc ia l support dur ing this work was provided by the Na tu ra l Sciences and Engineer ing Research Counci l . x Chapter 1 Introduction Synchronization plays a major role i n the fields of communications, digital data transmission, radar, sonar, and navigation. In modern communications systems, several different layers of synchronization are needed. These synchronization schemes range from frequency and phase estimation of an incoming carrier to the sequencing of packets, typically found i n higher levels of communication protocols. The demand for more efficient and robust communication systems coupled wi th the continuing advances i n digi ta l technology have motivated researchers to investigate alternatives to existing systems. Research i n synchronization and its related areas remains active, i n order to support the needs of increasing system demands and to exploit the many benefits that newer technologies provide. 1.1 Synchronization in Digital Communication Systems Two sequences of events are said to be synchronous i f corresponding events i n the two sequences occur simultaneously. Synchronization is defined as the process of br inging about, and retaining, a synchronous situation [1]. In the context of digital communication systems, the blocks which make up the receiver must synchronize to the corresponding transmitter blocks whose signals are deterministic. Hence, the synchronization problem can, i n general, be l imi ted to receiver design. 1.1.1 Hierarchical Synchronization in a Communication System A s previously mentioned, several layers of synchronization exist wi th in a communication system. Commonly used schemes are [2]: • carrier synchronization; • symbol (or clock) synchronization; 1 Chapter 1: Introduction • word synchronization; • frame synchronization; • network synchronization; and • higher-level application-dependent synchronization. Coherent demodulation of a received signal requires the use of carrier, or subcarrier, synchro-nizat ion. Car r ie r synchronization deals wi th the estimation of both the frequency and phase of the received signal. Symbol synchronization consists of detecting the boundaries between each symbol transmitted. The term clock synchronization can also be used to denote symbol synchronization since the synchronization process involves the extraction of the clock wi th in the bit/symbol se-quence. If the data source is block encoded, word synchronization groups the appropriate symbols into their respective blocks. Frame synchronization is based on the reconstruction of the data i n terms of their or iginal time samples. A n example of this is a f raming bit for synchronization of t ime-multiplexed samples. Network synchronization is required i f data is t ransmit ted to and received from mult iples sources. F ina l ly , higher levels of synchronization may be required de-pending on the application. A feature which distinguishes higher level synchronization schemes from those of carrier and symbol synchronization is that higher level schemes are usual ly solved by message format design, which involves the repetitive insertion of bits or words into the data sequence solely for synchronization purposes [3]. A s an i l lustrat ive example of a communication system using synchronization techniques, consider the system shown i n Figure 1.1. The mainframe, at point A , wishes to broadcast information to the Local Area Network ( L A N ) at point B , through a series of communications devices. The information is encoded and modulated onto a carrier signal for transmission v ia the satellite communication network. A t the receiver, carrier and symbol synchronization are performed to extract r aw bit sequences which are regrouped into packets once higher levels of synchronization are accomplished, such as framing and word alignment. The received data is then t ransmit ted onto the L A N . The overall effect is the proper recovery of the information at the destination node(s). 2 Chapter 1: Introduction Figure 1.1: Example of a Communication System. The lower level synchronization schemes, such as carrier or symbol synchronization, have rarely used digi ta l technology, pr imar i ly due to the l imitat ions i n speed of the digi ta l circuit elements themselves. Dig i ta l circuits, wi th a l l their inherent advantages, have only recently been considered as a viable alternative to existing analog systems. Hence an investigation into the use of newer, more economical digi tal technologies at the lower levels of synchronization is required. 1.1.2 Carrier Synchronization for Suppressed-Carrier M-ary PSK Signals Phase-Shift Keyed (PSK) signal l ing consists of modulat ing a carrier, typical ly a sinusoid, wi th a discrete phase value representing the data signal. M-ary P S K signal l ing has M discrete phase values available for modulation. O f interest is the case where the carrier is suppressed, i n which case a l l of the power is allocated to the modulated signal sidebands. For coherent demodulation, nonlinear methods are required to regenerate the carrier. These nonlinear techniques typically employ the phaselock principle. 3 Chapter 1: Introduction 1.1.2.1 Conventional Techniques Conventional techniques to regenerate the carrier from a suppressed-carrier M - a r y P S K signals are: • the squaring loop for Binary P S K ( B P S K ) and its derivatives for higher-order constella-tions; • the Costas loop for B P S K and its derivatives for higher-order constellations; • the decision-directed feedback loop, the data aided loop [4]; and • application-dependent hybr id loops. The purpose of the loops previously mentioned is to generate a discrete carrier component whose frequency and phase agrees closely wi th that of the suppressed-carrier frequency. The squaring loop obtains a discrete spectral component by squaring the signal [2, 5]. This discrete component is then tracked by a Phase-Locked Loop ( P L L ) . For t racking multiphase signals a s imi lar loop, the iVth Power loop, generates a discrete spectral component by ra i s ing the incoming signal to the Nth power. The Costas loop 1 [6, 71, is shown to be equivalent to the squaring loop under certain reasonable assumptions [81 but its implementation is quite different. The iV-phase Costas loop is used for higher-order phase constellations. Other loops, such as the decision-directed loop or the data aided loop, t ry to eliminate the effects of modulation i n order to track the carrier frequency [2]. One common problem exists among these loops. The analog circuit elements which make up these loops suffer from component aging and temperature drifts. These conditions can have detrimental effects on the system. A typical example is the dc voltage drift on a Voltage-Controlled Oscillator (VCO). A properly biased dc input voltage causes the V C O to oscillate at its free-running frequency. Th i s frequency is typically set to the expected carrier frequency. Component aging and temperature drifts can offset this voltage hence changing the free-running frequency. A solution to this problem is the use of digi tal components whose performance does not degrade over time. In 1 The Costas loop is also called the I-Q loop when the lowpass arm filters are replaced with integrate-arid-dump arm filters. 4 Chapter 1: Introduction addition, the use of digital technology would provide a greater flexibility in the design of carrier tracking loops. 1.1.2.2 Digital Techniques Since the early 1960's, digital techniques have been applied to carrier tracking loops to eliminate the shortcomings of analog circuit elements. Among the loops which have been investigated are: • hybrid analog/digital loops; • sampled squaring and Costas loops; • non-uniform sampling loops; and • software loops. Initially, efforts were made to replace analog loop components with their digital counterparts [9]. In the late 1960's, emphasis was placed on all-digital loops. Intuitive schemes such as the sampled Costas loop were first considered [101. Non-uniform sampling loops were later considered due to their simplicity in design and their enhanced performance [11, 12, 13, 14]. Today, due to the advancement of microprocessor technology, software loops are being de-signed for practical demodulation at carrier frequencies below 100 kHz [15, 16, 171. 1.2 Scope of the Thesis This thesis: • proposes a new loop for tracking suppressed-carrier M-ary PSK signals, the Multi-sampling Digital Tanlock Loop (MDTL), based on an extension of an existing non-uniform sampling Digital Phase-Locked Loop (DPLL); • provides an analysis of a first-order MDTL in the absence of noise; • describes the design criteria and testing environment for a software simulation and a hardware implementation; and 5 Chapter 1: Introduction • defines the performance measures and evaluates the results obtained for phase error, acquisit ion and hold-in measurements. 1.3 Organization of the Thesis Chapter Two reviews the most important work previously done on P L L s and D P L L s . This review includes research on both discrete- and suppressed-carrier loops wi th an emphasis on non-uniform sampling D P L L s . In addition, a brief outline of the Dig i ta l Tanlock Loop is presented. Chapter Three describes the functional loop components which make up the M D T L . A phase error difference equation which governs the behaviour of the M D T L is derived. F rom this difference equation, closed-form expressions of the steady-state mean phase error, the region of stabili ty, the lock range and the acquisition time are presented for a first-order M D T L i n the absence of noise. Chapter Four presents a brief overview on the design of a software simulation and a hardware implementat ion required to measure the performance of the M D T L i n the presence of noise. The test specifications for both the software and hardware testbed are given. Chapter Five defines the test procedures for the phase error, acquisition and hold-in mea-surements. Results of these measurements, conducted on both the hardware implementation and the software s imulat ion are given. Chapter S ix concludes the thesis wi th a summary of the results and suggestions for future areas of research. 6 Chapter 2 Review of Previous Work 2.1 Phase-Locked Loops A P L L consists of three functional units, the phase detector, the loop filter and the V C O . The block diagram of the P L L is shown i n Figure 2.1. Input Signal Phase Detector Reference Signal Phase E r r o r Voltage Controlled Oscillator Filtered Phase E r r o r Figure 2.1: Block Diagram of the Phased-Locked Loop. The P L L operates as follows. The phase detector generates a signal whose value represents an estimate of the phase error. Phase Error is defined as the instantaneous phase difference between the incoming signal and the reference signal generated by the V C O . This phase error estimate is filtered and the resul t ing error signal is fed back into the V C O i n order to reduce the overall phase difference. U n l i k e the conventional feedback systems, the P L L is a nonlinear system which makes i t difficult to analyze. The first known paper on the P L L was published in 1922 [18]. A thorough survey on the more recent status of the P L L can be found i n [2, 19, 20]. 7 Chapter 2: Review of Previous Work 2.2 Digital Phase-Locked Loops 2 The general DPLL structure is derived from the Maximum A Posteriori (MAP) estimation of an unknown phase for a sampled sinusoidal carrier embedded in Additive White Gaussian Noise (AWGN) [21]. Figure 2.2 shows a block diagram of the DPLL resulting from the closed loop MAP phase estimate. y(t) =y2Pcos(<o 0t+9(t)) cos(co„ t k + 9 k ) f(ek) Figure 2.2: Simplified Block Diagram of the DPLL. With the exception of the sampler, the DPLL is similar in form and in operation to the general PLL shown in Figure 2.1. The sampler, however, allows the replacement of analog circuit elements with equivalent digital elements. The introduction of digital technology provides several benefits. First, it eliminates the problems of component aging and temperature drifts. Second, digital technology allows greater flexibility in design and testing. Finally, digital implementation provides an opportunity for greater system integration using Very Large Scale Integration (VLSI) techniques. The MAP estimate of the generalized DPLL does not take into account the sampling process. The times at which the observables j/*, k = 0,...,N — 1, are sampled are not specified. Hence, several different types of DPLLs have evolved as the result of the variability of the sampling 2 The term Digital Phase-Locked Loop has created a great deal of confusion in publications as to its precise definition. Since virtually all PLLs contain digital components, in this thesis the term Digital Phase-Locked Loop will be reserved for PLLs in which all components are digital. 8 Chapter 2: Review of Previous Work process. Lindsey [21] classifies the various types of D P L L s into four categories depending on the type of phase detector used. These four categories are: • the Nyquist Rate D P L L ( N R - D P L L ) ; • the Flip-Flop D P L L ( F F - D P L L ) ; • the Lead I Lag D P L L ( L L - D P L L ) ; and • the Zero Crossing D P L L ( Z C - D P L L ) . The N R - D P L L evolved pr imar i ly from analog P L L s whereby a sampler is placed before the loop and the received signal is sampled at the Nyquis t rate. A number of researchers have investigated the N R - D P L L [10, 22, 23, 24, 25, 26, 27, 28]. Figure 2.2 is an example of the N R -D P L L when sampl ing occurs at a uniform rate. Due to the uniform sampling nature of the N R - D P L L , however, the samplers do not eliminate the need for a phase detector. Addi t iona l circuit elements are needed for this scheme. The F F - D P L L was the first D P L L developed which employs a non-uniform sampling method, hence e l iminat ing the need for a conventional phase detector [29, 30, 31, 32]. The phase error is derived from the duration between the set and reset times of a F l ip -F lop triggered by the zero crossings of the input signal and a local reference clock. A block diagram of a phase detector typical ly used i n the F F - D P L L is shown i n Figure 2.3. Signal Positive Zero Crossing Detector r Set FlipFlop 1 Reference Reset Clock Signal Positive Zero Crossing Detector \ Digital Phase E r r o r Counter Figure 2.3: Block Diagram of the F F - D P L L Phase Detector. 9 Chapter 2: Review of Previous Work In the L L - D P L L , the phase detector decides at every cycle whether the input signal is leading or lagging the reference signal by means of an integrate-and-dump circuit followed by a threshold detector [33, 34]. A block diagram of a phase detector used i n the L L - D P L L is shown i n Figure 2.4. Due to the coarse quantization of the phase detector output, the L L - D P L L uses a nonlinear digital loop filter, such as a sequential filter, to smooth the error value. Yamamoto [35] has extended the L L - D P L L to include a second-order sequential filter w i t h memory. The L L - D P L L has been very successful w i th digi tal signals and is available commercially i n both T T L and C M O S technologies. input Signal Integrate and Dump - • Lead L a g Reference | Binary Phase Detector Signal Figure 2.4: Block Diagram of the L L - D P L L Phase Detector. The Z C - D P L L tracks the positive zero crossings of the received signal us ing a sampler as the phase detector [36]. The sampling instants are derived from a Numerically-Controlled Oscillator (NCO) which replaces the conventional V C O . A block diagram of the Z C - D P L L phase detector is shown i n Figure 2.5. The Z C - D P L L w i l l be the subject of the remainder of this chapter. Input Signal Sampling instants controlled by a local reference signal Figure 2.5: Block Diagram of the ZC-DPLL Phase Detector. 2.2.1 The Zero Crossing D P L L The purpose of the Z C - D P L L is to track the positive zero crossings of the sinusoidal carrier corrupted by A W G N . N a t a l i [37] was the first to propose such a structure i n 1968. G i l l and Gupta 10 Chapter 2: Review of Previous Work [36, 38] were the first to systematically analyze the first- and second-order Z C - D P L L s . A s a result of their analysis, the Z C - D P L L is often referred to as Gill and Gupta's DPLL. The loop consists of a sampler, a digi ta l loop filter and a N C O . A block diagram of the Z C - D P L L along wi th an i l lus t ra t ion of the sampling process is shown i n Figure 2.6. X(t) Tk = tk - tk-i = TQ - Ck-i D(z) NCO ck (a) sampling A / instant t (sec) (b) Figure 2.6: Gill and Gupta's DPLL (a) Block Diagram (b) the DPLL's Sampling Process with Respect to the Incoming Signal x{i). The N C O allows the sampler to act as a phase detector, therefore e l iminat ing the need for a conventional mul t ip l ie r phase detector and providing a conceptually simpler system. The N C O determines the next sampling interval Tk given Tk = T0 — Ck~\ (2.1) 11 Chapter 2: Review of Previous Work which states that the next sampling interval is the difference between the nominal sampling period of the input signal T0 and the previous correction value Ck-\ given by the digi ta l loop filter. In the example shown i n Figure 2.6 (b), the sampling instant tk-i lags the positive zero crossing. A s a result, the sampling interval Tk should be smaller than the nominal sampling period by an amount which is proportional to the value of the sample acquired at time tk-i- When the sampling instants eventually sample at the positive zero crossing, Tk w i l l assume the value of the nominal sampling period and the loop attains a steady-state. A n y sampling deviation from the positive zero crossing w i l l force the N C O to adjust the sampling interval to consequently, offset the effects of the deviation. The simplici ty and practicality of the Z C - D P L L have motivated a considerable amount of research. The following is a brief outline on the areas of research which have been investigated on the Z C - D P L L . • Stability: D 'Andrea and Russo [39, 40, 41] analyzed the stabili ty of Z C - D P L L using graph-ica l techniques for various levels of quantization. Osborne [12, 13] provided analytical results for the stabili ty of a Nth Power Z C - D P L L for first-, second- and third-order loops. • Statistical Analysis: Weinberg and L i u [42, 43] provided semi-numerical techniques for the statistical analysis of the Z C - D P L L using the Chapman-Kolgomorov equation. Chie [44] extended the analysis and compared the results to analog P L L s . Lindsey [45] used the Chapman-Kolgomorov equation to determine the acquisition behaviour of the Z C - D P L L . • Quantization: Reddy and Gupta [46, 47] analyzed the effects of quantization wi th and without A W G N . Pomalaza-Raez [48] extended the analysis by studying both clock and sampler quantization. M c C a i n [49] investigated the use of robust estimators for various non-Gaussian noise processes. • Variations and Extensions: Holmes and Tegnelia [50, 51, 52] have modified the Z C - D P L L to track a square-wave subcarrier. The i r results are also applicable to arbi trary subcarriers that are odd symmetric about the transit ion region. Ko izumi [53] analyzed the Z C - D P L L when subjected to a time delay. Rocha [54] investigated the performance of the Z C - D P L L wi th t ime-varying digi tal loop filter coefficients. Majumdar [55] and Cernuschi-Frias [56] 12 Chapter 2: Review of Previous Work have improved the performance of the Z C - D P L L when the loop tracks both the positive and negative zero crossings of the received signal. Sandoz [57] analyzed a binary quantized Z C - D P L L using a sequential filter and an aided-acquisition technique. • Applications: G i l l [36] suggested the use of the Z C - D P L L for the demodulation of angle-modulated signals. Reddy [58] applied the Z C - D P L L for the demodulation of F M signals and N a t a l i [11] designed a Z C - D P L L to coherently demodulate B P S K signals at data rates below 1 Mbps. 2.2.2 The Digital Tanlock Loop Lee and U n [59] developed the Digital Tanlock Loop (DTL) which is a Z C - D P L L whose main feature is the tan" 1 phase detector. Figure 2.7 shows the block diagram the D T L which consists of two samplers, the tan" 1 phase detector, the digi tal loop filter and a N C O . The loop is preceded by a 90° phase shifter i n order to generate the quadrature arm. The inphase and quadrature samples are required indiv idual ly i n order to determine a phase error estimate i n the interval between — T and n. NCO D(z) ly(k)\ Figure 2.7: Block Diagram of the DTL. U n l i k e the conventional Z C - D P L L which possesses a sinusoidal phase characteristic, the D T L has a l inear phase characteristic which is due to the tan" 1 operator. As a result, the D T L can be characterized by a l inear difference equation which eliminates the approximations of nonlinearity 13 Chapter 2: Review of Previous Work which are seen i n the conventional Z C - D P L L . The l inear difference equation also provides many attractive features which include locking conditions which are insensitive to variations i n signal power, enhanced noise immuni ty , wider lock range and a reduced steady-state mean phase error for a first-order loop given a received signal hav ing a frequency offset. 2.2.2.1 The D T L for Tracking Suppressed-Carrier PSK Signals K i m and U n [141 developed a D T L for t racking suppressed-carrier M - a r y P S K signals by making simple modifications to the phase detector. The D T L is an ideal candidate for this application since both the inphase and quadrature arms are readily available. The 90° phase shifter i n Figure 2.7 was replaced by an inphase and quadrature mixer whose purpose is to beat the received signal down to a carrier frequency which is suitable for digital technology and to generate both the inphase and quadrature arms. 2.2.2.2 The D T L with Multi-Sampling Cho and U n [60] proposed mul t i -sampling methods for the conventional D T L to extend lock range and to reduce steady-state mean phase error and variance. Hag iwara and Nakagawa [61] have successfully applied the D T L wi th mult i -sampling to demodulate the pilot tones of both stereophonic and monophonic F M . 14 Chapter 3 Characterization of the MDTL 3.1 Assumptions Let r(t) be the received signal whose components consists of a Af-ary PSK signal s(t), and a AWGN signal n(t). Hence r{t) = s (t) + n{t). (3.1) The information-bearing signal s (t), can be written as « (t) = y/2Pc sin [uct + 9(t) + \ (t)] (3.2) where Pc is the signal power, u>c is the nominal carrier radian frequency, 6 (t) is the instantaneous phase disturbance, and A (f) is the modulating data signal. The instantaneous phase disturbance 6 (/), consists of a frequency offset as well as a phase offset and can be expressed as 6 (t) = Aut + 90 (3.3) where Aw = LJ — coc represents a frequency detuning with w being the actual carrier radian frequency, and 90 is a phase offset which is uniformly distributed between [—n, 7r). The data signal X(t), for the case of Non Return-to-Zero-Level (NRZ-L) coding, can be ex-pressed as OO A(t) = A8- .[u(t- tT.) -u(t-(i+ 1)Ts)} (3.4) i — — oo where u(t) is the unit step function, Ts is the symbol period, and A, represents a uniformly distributed data phase whose value is Inm/M (m = 0,1,2, . . . ,M - 1) at the zth symbol interval. The double-sided spectral density of the noise process n (t), is assumed to be N0/2 Watts/Hz. 1 5 Chapter 3: Characterization of the MDTL 3.2 Description of the MDTL The purpose of the MDTL is to lock onto the mixed-down suppressed-carrier frequency, and to track the instantaneous phase disturbance caused by the effects of the channel and the Analog Front End (AFE). The MDTL can also perform data extraction but is beyond the scope of this thesis and will not be considered. Figure 3.1 shows the functional block diagram of the MDTL. The MDTL consists of a phase detector, a digital loop filter, an NCO, and is preceded by an AFE. 3.2.1 The Analog Front E nd The purpose of the AFE is to beat the incoming signal down to a frequency level suitable for digital signal processing and to generate bandlimited inphase and quadrature arms for the tan"1 phase detector. The incoming signal is multiplied by a local oscillator signal and by a 90° phase-shifted version of the local oscillator signal. The frequency of the local oscillator ulo, is the difference between the nominal carrier frequency and the desired mixed-down frequency w0I that is wio = w c — w0. (3.5) The multiplied signals are then bandpass filtered with filters having a center frequency equal to the mixed-down frequency. The value chosen for the mixed-down frequency will be discussed in Chapter Four. The resulting inphase arm x (t), can be expressed as x (t) = [2r (t) cos (u>i0t)] <g> h (t) (3.6) where the symbol ® denotes convolution and h (t) is the impulse response of the bandpass filter H (/). A factor of 2 has been introduced for mathematical convenience in subsequent analysis. Similarly, the quadrature arm y{t), can be expressed as y (t) = [2r (t) sin (u,0t)] ®h(t) (3.7) Due to the bandpass filtering, the mixed-down signals suffer both phase and envelope distortion [14]. For simplicity, the envelope distortion can be represented as a signal power reduction. Hence, the approximated inphase and quadrature arms may be written, respectively, as 16 Analog Front End Numerically-Controlled Digital Loop Filter Phase Detector Oscillator Figure 3.1: Block Diagram of the Multi-Sampling Digital Tanlock Loop. Chapter 3: Characterization of the MDTL x (t) = y/2p~Pcsm [u0t + e(t)+Z (*)] + V (t) (3.8) y(t) = y/2pKcos [u0t + e(t)+^(t)] + fi(t) where p is the signal power reduction factor due to filtering, £ (t) represents the data signal A (t) w i th distortion due to filtering, 77 (t) is approximately narrowband A W G N wi th double-sided spectral density N0/2 and bandwidth Bot and fj(t) is the process rj(t) phase-shifted by 90° . The signal power reduction factor p can be expressed as the ratio between the total power of the filtered baseband data signal and the total power of the unfiltered signal, that is 00 / Sm(f)\Ht(f)\2df C O / Sm(f)df P = ^ (3-9) where Hi (/) represents the low-pass version of the bandpass filter H (/) and Sm (/) is the power spectral density of the baseband data signal. For N R Z - L coding, Sm (/) can be wri t ten as [14] Sm(f) = TsS^^l. ' (3.10) If the bandwidth B0 of H (/) is made sufficiently large so that the fi l tering affects can be neglected, £ (t) would be the modulat ing data signal itself, that is £(t) = \ (t) (3.11) but the noise power due to A W G N would increase i n direct proportion to B0. Hence, for a bandl imited signal, the phase distortion i n £ (t) cannot be ignored and is denned as modulation distortion. Exc lud ing quantization effects, the noise i n the M D T L consists of channel noise and modulation distortion. The Phase Error Disturbance is defined as the cumulative effect of these two sources of impairment. F ina l ly , the A F E may be preceded by either a bandpass filter or a bandpass l imi ter whose purpose is to eliminate unwanted noise i n the frequency bands wi th negligible signal power. In addition, the bandpass l imi ter l imits the signal range i n order to protect the remain ing circuit 18 Chapter 3: Characterization of the MDTL elements. If the incoming carrier frequency is sufficiently low that no mix ing is required then a simple 90° phase shifter can be substituted for the A F E to generate the quadrature arm. The l imi ta t ion of this design, however, is the accuracy at which a realizable Hi lber t Transform can be designed to implement the 90° phase shift for a bandwidth to center frequency ratio greater than 0.1. 3.2.2 The Numerically-Controlled Oscillator The N C O is the circuit element required to control the sampling process of the loop. Un l ike a conventional V C O where the frequency of the reference signal is controlled, the N C O operates i n the t ime domain where the sampling interval is controlled. The sampling interval Tk, is denned as the time between adjacent sampling instants, tk and tj,_i, that is where k represents a time index. In a non-uniform sampling D P L L , Tk is a function of the previous output sample from the digital loop filter, ct-i. In the case of the M D T L , the sampling interval equation can be wri t ten as where T0 — 2TT/U>0 is the nominal sampling period of the N C O , A is an integer denoting the nominal number of samples per input period, and B is a factor used to reduce the loop control gain. The introduction of A enables the M D T L to acquire a greater number of samples per data symbol which is desirable i n the case where bi t detection is performed using a digi tal summation and dumping process. F r o m E q . (3.12), an expression for the total elapsed time tk up to the kth. sampling instant can be wri t ten as Tk — tk — tk-l (3.12) rr, T0 T k = -A~ C f c - l B (3.13) k tk—to+y^.Tj (3.14) Subst i tut ing E q . (3.13) for Tj, we obtain 19 Chapter 3: Characterization of the MDTL (3.15) where t0 is assumed to be zero without loss of generality [38]. Equat ion (3.15) describes the behaviour of the N C O and provides the necessary information to derive a suitable expression for the phase detector and consequently, a difference equation for the phase error process. 3.2.3 The Phase Detector The phase detector consists of the samplers followed by the tan" 1 operator, and the elements which precede the digi tal loop filter, D (z). The purpose of the phase detector is to give a reasonable estimate of the phase error. In the case of the M D T L , the samples xk and yk are fed into the tan" 1 block whose output zk, contains the wanted phase error term and two unwanted terms due to the mul t i -sampl ing and the modulat ing data signal. The blocks which immediately follow the tan ' 1 function eliminate these unwanted terms. The phase detector can be analyzed as follows. The inphase and quadrature samples can be wri t ten, respectively, as where xk = x[tk], yk = y[tk], 6k = 0[tk], tk = t[tk], rjk = v[tk], and rfk = fj[tk]. Subst i tut ing E q . (3.15) for the total elapsed time into the sampled inphase arm, we obtain = x/2pPc sin [u0tk + 9k+ £k] + Vk (3.16) yk = \JlpP0 cos [u>0tk + 9k+ tk] + rjk % I + °k+^ +vk (3.17) Z7TK \/2pPc sin — + <pk + tk +f)k where the phase error, <pk, is denned as (3.18) 20 Chapter 3: Characterization of the MDTL and fc—1 * = ^ 2 ^ ' (3.19) The loop phase estimate 9k is given as the product of the nominal input carrier frequency and the sum of the correction values weighted by 1/B. In a s imilar fashion, the quadrature arm can be wri t ten as Vk t = \/2pPc cos 2irk — + <Pk + <k (3.20) The output of the tan" 1 operator zk, is defined as A + - i zk = tan Vk (3.21) where zk lies wi th in the range — ir < zk < TT. Note that both xk and yk must both be given i n order to determine the correct phase quadrant. In the absence of any phase error disturbance, that is Vk = Vk = 0, £fc = Aj; = 2irm/M for m = 0,1,..., M — I, zk may be rewrit ten as 2irk 2irm (3.22) where the function /[•] is defined as / [p] — ~ l r + {(u + 7 r) modulo 2ir} (3.23) and is shown i n Figure 3.2. A s a result of this function, the phase angle is l imi ted to — ir < zk < ir and reflects the 27r phase ambiguity seen i n the tan ' 1 function and i n a l l phase detectors. F r o m E q . (3.22), i t is noted that the tan" 1 function retains the phase information and eliminates a l l amplitude information, that is the signal levels between the inphase and quadrature samples cancel. Th i s cancellation justifies our earlier assumption of a constant signal power reduction i n § 3.2.1. In addition, the insensit ivi ty to variations i n signal power eliminates the need for an accurate Automatic Gain Control (AGC) circuit commonly seen i n conventional D P L L s . 21 Chapter 3: Characterization of the MDTL f[V] -K--Figure 3.2: Modulo 2w Limiter for the tan 1 Function. For the purpose of synchronization, an estimate of the phase error ipk is required. Interest-ingly, E q . (3.23) represents the response of the ideal phase detector, i f y, is replaced by <pk, and is called a sawtooth phase detector. Since E q . (3.23) occurs natural ly wi th in the tan" 1 function, i t is possible to realize the ideal phase detector i f the unwanted terms wi th in zk are eliminated. These unwanted terms are: • Ink I A, the result of mult i -sampling since sampling no longer occurs only at the positive zero-crossings, and • 2-irm/M, the result of the modulat ing data signal. In order to properly derive the phase error estimate, i t is necessary to use the following properties which are shown i n Appendix A . l . Given the real numbers a\, a2, an integer M, and the function / [•] which is given by E q . (3.23), then where op is one of the operators + , - or x . W i t h these two properties, the phase error estimate ek becomes / [ai op a2] = f[f [ai] op f [a2] ] (3.24) f[Mai} = f[Mf[ai}} (3.25) 22 Chapter 3: Characterization of the MDTL To prove E q . (3.25), we expand the Right Hand Side (R.H.S.) and make use of E q . (3.24) to obtain M [zk - / 2irk A = f Mf Mf Mf Zk~ f 2irk A 2irk 2irm v>k + 2itm ~M~ = f [Mipk + 27rm] = f[M<pk]. -f 2irk A Q.E.D. o (3.26) Equat ion (3.25) states that i n the absence of noise we are able to obtain an ideal phase error estimate which is l inear modulo 2ir/M. The introduction of the gain factor M eliminates the effects of modulation but contracts the ideal phase detector curve by an equivalent amount. As an example, Figure 3.3 shows the phase error estimate i n the absence of noise for the case where M is equal to 2. Note that from the range —TT < <pk < ir, stable lockpoints exist, that is <pk — 0, at — 7 r and at zero. In general, there exists M stable lockpoints located at 2-KJ M M-l 1 ' M 2 1) M even ^fl) M odd. (3.27) Simi la r ly , there exists M unstable lockpoints equally spaced between stable lockpoints. This M-fo ld ambiguity occurs i n a Mth-order Costas loop as well . The advantage of this system, however, is that to change from one M - a r y P S K format to another, M is the only parameter that needs to be modified i n the M D T L whereas i n the Mth-order Costas loop, different circuit configurations are needed for various M - a r y P S K formats [1] (pp. 245-246). Since both M and / f 2 ^ ] are known, the R . H . S . of E q . (3.25) can be emulated wi th the blocks which follow the tan" 1 function and precede the digital loop filter in Figure 3.1. Note that the nonlinear functions i n E q . (3.25) can be easily created i n a digital system whereas i t may be extremely difficult to bui ld an equivalent analog circuit. 23 Chapter 3: Characterization of the MDTL / [ M < p J 71-- M = 2 •7C F i g u r e 3.3: Phase Error Estimate for the Case M = 2 in the Absence of Noise. In the presence of noise, it is necessary to classify the sampled noise process which is the result of sampling both the inphase and quadrature arms. Both r) (t) and T) (t) are approximately narrowband AWGN with zero-mean, double-sided spectral density N0/2 and bandwidth equal to the noise equivalent bandwidth of AFE which is B0 [62]. The bandwidth of the bandpass filter H (/) is equal or larger than the nominal sampling rate of the NCO and hence the sampled noise process rj (k) can be approximated as a sequence of independent and identically distributed Gaussian random variables having zero mean and variance a2 (rf) — B0N0 [44]. The same approximation applies for fj(k). In addition, both n(t) and fj(t) are always uncorrected at sampling instant tk, hence where E [•] is the expected value operator. When considering the Maximum A Posteriori (MAP) criterion, the assumptions for the pro-posed loop differ from conventional suppressed-carrier tracking loops. The derivation of the Costas loop, for example, is based on the idea that the phase error estimate is derived from an infinite number of observables for use in the MAP estimate [7]. Since the Costas loop is closed-form, the solution to the MAP estimate is performed iteratively. The phase detector of the MDTL, how-ever, is based on the simpler assumption that the phase error estimate is based on the present pair of input samples, xk and yk- If the phase angle within the inphase and quadrature sam-E [m • m] = 0 (3.28) 24 Chapter 3: Characterization of the MDTL pies is uniformly distributed, p[zk] = 1/2-K (—IT < zk < TT), i t is shown i n Appendix A .2 that the M A P estimate of the phase angle is the tan" 1 function. In the case of the M D T L , the modulat ing data signal is not uniformly distributed and hence the above assumption does not apply. The Maximum-Likelihood estimator, however, suggests that the tan" 1 function provides the most un-biased estimate of the phase angle [63]. A s a result of the phase error disturbance, the actual phase error estimate consists of the term / [ M ^ ] and an additive non-Gaussian random variable (k, hence ek = f[M<pk] + Ck. (3-29) Refer to Appendix A.3 for a description on the statistical characteristics of the phase detector i n the presence of noise. 3.2.4 The Digital Loop Filter The phase error estimate ek, is filtered by a digi tal loop filter resul t ing i n a correction value ck, which is then used by the N C O to determine the following sampling interval . A n nth-order digital loop filter can be represented by a difference equation of the same order, that is n n Ck = ^2 aiek-i - ^2 bjCk-j (3.30) »' = 0 j = l The filter may also be described i n a more convenient form which is the z operator notat ion 3 . It is denoted by D (z), which is a ratio of two polynomials i n z. The nth-order digital loop filter may be wri t ten as 3 The symbol z is used as an operator on any function / (fc) which is defined in the domain of non-negative integers. The operator has the following properties: U(k)] = f(k + n) z-n[f(k)] = f(k-n). It should be noted that the z operator notation is not the z transform. 25 Chapter 3: Characterization of the MDTL D (z) = C0 (;+PiH' + P2)-"('+Pn) (3.32) V ° (z + qi)(z + q2)---(z + qn) where C0 is the constant gain. Given D(z), the correction value may be wri t ten as ck = D(z)ek. (3.33) In most practical applications, the digital loop filter is usual ly zero- or first-order. The zero-order filter is simply an attenuator whereas the first-order filter is either modelled as an RC lowpass filter, a phase-lag filter or a perfect integrator. The choice of filter depends on the specifications of the application. 3.3 System Equations of the MDTL Given the details of the indiv idual components of the M D T L , i t is possible to analyze the general loop behaviour. The analysis is based on a baseband model of the loop which characterizes the phase error process. 3.3.1 The Baseband Model The baseband model is derived from the expression for the loop phase estimate, i n E q . (3.19). The difference between adjacent samples is given as ek~+1 -ek = ^ L (3.34) Subst i tu t ing E q . (3.29) and E q . (3.33) for ck we get Ok+i - Ok = {/ [M<pk] + C*} (3.35) or i n z operator notation h = 4^ I T {/ \ - M ^ + ^ > • ( 3 ' 3 6 ) z — 1 a 26 Chapter 3: Characterization of the MDTL Equation (3.36) leads directly to the baseband model which is shown in Figure 3.4. Note that this model is independent of the carrier frequency and the multi-sampling, and depends only on the phase process of the input signal. The baseband model is different from the conventional DPLL where the nonlinear term sin [<pk] is replaced with / [Mipk] and Gaussian noise by the non-Gaussian noise process Ck- Despite the removal of the sine nonlinearity, the model in Figure 3.4 remains nonlinear due to the coupling between the input phase 6k and the loop phase estimate 9k- This coupling is the result of the sampling process ik where (3.37) Figure 3.4: The Baseband Model for the M D T L in z Operator Notation. When the MDTL is tracking the input phase process, however, the correction values ct are small and the sampling intervals are assumed to be constant. With this approximation, the coupling between 6k and 9k no longer exists and the baseband model is characterized by a piecewise linear stochastic difference equation. Linearization simplifies the analysis of the phase error process whose difference equation will be derived in the following section. 27 Chapter 3: Characterization of the MDTL 3.3.2 The Phase Error Difference Equation The phase error difference equation can be derived from Eq. (3.35). Substituting 9k = 9k - ipk, we get <Pk+i -<Pk = Ok+i - h - {/[M<pk] + <k] (3.38) Using 9k+1 - 9k = AwTjfc+i and replacing Tk+i with Eq. (3.13) yields u>inD(z) f , T . . , , . , , AuiT0 Vfc+i-Vfc^ {f[Mipk] + Ck} + —— (3- 39) where u>in =u0 + Aw is the actual mixed-down frequency. Using the same assumptions as denned in § 3.3.1, Eq. (3.39) represents a piecewise linear stochastic difference equation. When M — 1, Eq. (3.39) reduces to Cho's DTL [601 which is a multi-sampling DTL for a continuous sinusoidal signal. In addition, when A = B = 1, Eq. (3.39) reduces to Kim's DTL [14] which is a DTL for M-ary PSK signals. Finally, setting M = A = B - 1 reduces Eq. (3.39) to Lee's conventional DTL [59]. In the absence of noise, several important properties can be derived from the loop including the steady-state mean phase error, the region of stability, the lock range and the acquisition time. Although the techniques used in the following sections could be applied to derive loop equations for higher-order loops, the analysis for the remainder of this thesis will be limited to a first-order MDTL. First-order analysis is relatively simple and provides good insight on the effects of the individual loop parameters. Hence D{z) = Gx. (3.40) In addition, Lee [59] has shown that the DTL outperforms the conventional ZC-DPLL and hence it is sufficient to compare the performance of the MDTL with loops which employ the Tanlock principle [14, 59, 60]. As a result, the notations used in thesis are the same as those used by Lee. 28 Chapter 3: Characterization of the MDTL 3.3.2.1 The Steady-State Mean Phase Error in the Absence of Noise In the absence of any phase error disturbance, that is (k = 0, and considering the interval <Ph € hif, if), Eq. (3.39) can simplified to /, K'M\ A0 ,0 <Pk+i= [ 1 - — B ~ ) ( p k + ~A where K'=winG1: A0 = AuT0. (3.42) The steady-state mean phase error < p s s must satisfy (3.41) given fk+i — <fk = <P>s- Accordingly, i p s s is given by If the ratio B/AM is less than unity, the steady-state mean phase error decreases. The reduction can be accomplished by increasing the multi-sampling rate A while keeping B constant. 3.3.2.2 Locking Conditions We wish to determine the values of K' and A 0 for which a steady lockpoint exists. Equation (3.41) is considered first. Afterwards, the discrete phase plane method is used to derive stricter locking conditions. The first locking condition which is denoted by LI, is the restriction on i p „ which must lie between the interval if). Hence, using Eq. (3.43), LI becomes (LI) |A„| < (3.44) The solution to Eq. (3.41) is stable if all the roots of its characteristic equation have absolute value less than one [64]. For a first-order characteristic equation x(n + 1) - ax(n) = 0 (3.45) 29 Chapter 3: Characterization of the MDTL the absolute value of the root a must be less than one. W h e n applied to E q . (3.41), the second locking condition L 2 , becomes 1 - £ £ < 1 (3.46) B or 9 Fl (L2) 0 < K' < =£. (3.47) M To i l lustrate the conditions needed for the M D T L to achieve a stable lockpoint, the discrete phase plane method is used. The discrete phase plane method gives a graphical interpretation of the phase error trajectory and is used extensively for nonlinear sampled-data systems. The horizontal axis represents the present state of the phase error <pk, and the vert ical axis represents the next state of the phase error ipk+i-The phase error <pk is projected vert ical ly onto the characteristic curve which yields <pk+i-The characteristic curve i n our case is the phase error difference equation (3.39), wi th set to zero. This next state is projected horizontally onto the transformation line <pk+\ = <pk and the process repeats itself. The result is a series of vertical and horizontal projections whose end points represent the trajectory of the phase error process. Given an in i t i a l phase error bounded by [— fj, JJ), a l l projections i n a stable system should lie inside a square box centered about the origin and whose half-width is TT/M. Figure 3.5 shows the trajectories of two phase error signals for A — B — M = 1 when the locking conditions are not met. The dotted lines show the trajectory of the phase error signals. Clear ly , the phase error samples do not converge since i n Figure 3.5 (a), A 0 = 37r/5 and K' = 2/5 and hence L I is not met. In Figure 3.5 (b), A 0 = 27r/5 and K' = 11/5 and hence L 2 is not met. Equations (3.44) and (3.47) are necessary but not sufficient conditions. Given A 0 and K' whose values meet both lock conditions, there exists i n i t i a l phase errors for which the phase error samples do not converge. Figure 3.6 shows the discrete phase plane plot whereby both lock 30 Chapter 3: Characterization of the MDTL (a) (b) Figure 3.5: Discrete Phase Plane Plot for Different Values of A Q and K'. / I (a) (b) Figure 3.6: Discrete Phase Plane Plot with Conditions L l and L2 True, (a) <p0 = —x/3 Converges (b) ip0 = —47r/5 does not Converge. conditions are met, A0 — Zir/b and K' = 8/5, however for a given i n i t i a l phase error tp0 the phase error samples do not converge. -47r/5, Both locking conditions were derived from the simplified l inear equation given by (3.41). F rom the discrete phase plane plot, however, one can see that an additional restriction is needed. This restriction states that for any phase error value <pk between [-jj, jj), (fk+i should also be bounded 31 Chapter 3: Characterization of the MDTL by [—jf, jj). Graphical ly , the restriction is equivalent to bounding the straight line i n the range of [—jr, jj) inside the square box. As a result, i t is necessary to simply evaluate the endpoints of the l ine. Hence, for <pk = ±ff, < jj which leads to the th i rd locking condition L3 (L3) | A ( , | < ^ ^ - § ) (3.48) Figure 3.7 shows the locking region of the M D T L given by Eqs. (3.44), (3.47) and (3.48) for A = B — M = 1. The shaded area i n Figure 3.7 (a) represents the locking region i n which the M D T L can lock regardless of the in i t i a l phase error. The x inside the shaded area is a coordinate chosen to i l lustrate the locking process i n Figure 3.7 (b). The sampling process of (b) wi th respect to the inphase signal x (t) is shown i n Figure 3.7 (c). The three locking conditions are sufficient to determine the locking region when A = 1. When mul t i -sampl ing is present, however, certain values of A0 and K' w i th in the locking region correspond to an unrealizable loop. For the loop to be realizable, the sampling interval must be greater than zero. Therefore, T fc = - ^ > 0. (3.49) This leads to the fourth locking condition L4, which is (L4) A0 > 7r - . (3.50) The effect of the fourth condition is a truncation of the diamond-shaped locking region. Figure 3.8 shows the regions of convergence for various values of A, B and M. Note that as the ratio B/A decreases, the diamond-shaped region expands, while as M increases, the reverse is true. Hence, when considering stability, the use of mul t i -sampling offsets the adverse effects that higher-order modulation formats create. It should be mentioned that, unl ike the sinusoidal D P L L , the locking conditions are inde-pendent of signal power. In the sinusoidal D P L L , given the opt imum value of K' for fastest convergence, the system can become unstable as signal power increases. A s the signal power de-32 Chapter 3: Characterization of the MDTL A 0 o -6 L2 L I j / 0.5 1 1.5 K' 2.5 (a) (b) t (sec) Figure 3.7: (a) Locking Region of the MDTL for A = B = M = 1 (b) Discrete Phase Plane Plot for A 0 = TT/5 and A" = 8/5 (c) Sampling Process with Respect to the Inphase Signal i (t). creases, its acquisition time increases [12]. Hence, to operate the D P L L properly at an optimum signal level, an accurate A G C circuit is required. This is not the case for the M D T L . 3.3.2.3 Lock Range Lock Range is defined as the frequency range for which the M D T L can achieve lock given the digital loop filter coefficient G\, and the values A, B and M. We can therefore reexamine the four locking conditions i n terms of the normalized digi tal loop filter coefficient K and the frequency offset ratio w 0 / c j ! r a where 33 Chapter 3: Characterization of the MDTL K = LJ0GX (3.51) and 34 Chapter 3: Characterization of the MDTL Win \27T (3.52) W i t h equations (3.51) and (3.52), and the locking conditions given by (3.44), (3.47), (3.48), and (3.50), the lock range is bounded by (LI) K > 25 A Win (L2) K < 25 M Wo_ Win (L3) K < 25 A (A W0 \M ' Win 1 - ^ 2 -Win (L4) K < 25 A ' (3.53) (3.54) (3.55) (3.56) Figure 3.9 shows the locking regions i n terms of K and w0/win for various values of A, B and M . The shaded areas represent the acceptable frequency range for the M D T L to achieve lock regardless of i n i t i a l phase error given. In Figure 3.9 (a), the fourth locking condition, Tk > 0, does not apply since this restriction is not needed when mul t i -sampl ing is not present. In Figure 3.9 (b), when the mul t i -sampl ing rate is increased, the lock range widens at the expense of the range i n K. Th is l imi ta t ion, however, is not a serious drawback, since i n most practical systems, the value of K is generally much less than one. In Figure 3.9 (c), as M is increased, the lock range, for values of w0/win less than one, is decreased. F ina l ly , the more restrictive th i rd locking condition eliminates the need for the second condition. The second locking condition, however, is shown i n Figure 3.9 for sake of completeness. The lock range can be determined for given values of A,B,M and K. F rom Figure 3.9, two ranges exists depending on the value of K and its boundary is the intersection between the first and the th i rd locking condition. Hence, the lock range is given as 25 Win 25 + AK < w0 K 25 25 - AK K€[0, 25 1 2M + A (3.57) and 25 win 2B (M±A) 2B + AK w0 2B+AK 25 25 2M+A' A (3.58) 35 Chapter 3: Characterization of the MDTL 3.3.2.4 Acquisition Statistics in the Absence of Noise The piecewise l inear difference equation of the phase error process can be used to determine the performance of the M D T L dur ing its acquisition period. The Acquisition Time is defined as the time required for the first phase error sample to fal l wi th in a given level tpc, of the steady-36 Chapter 3: Characterization of the MDTL state mean phase error given by (3.43). Hence, the acquisition process is terminated at the k t h sampl ing instant when \<Pk — Vas| < (3.59) In the absence of noise, the acquisition t ime can be explicitly stated for a given in i t i a l phase error and first-order loop configuration. The values of K ' and A 0 are assumed to be wi th in the locking region. The derivation consists of f inding the m i n i m u m value of k which satisfies E q . (3.59) and solving the equation for the total elapsed time given the m i n i m u m value of k. To determine k, we define a new variable <p'k = i p k — <pss to be the difference between the phase error sample at the the k t h sampling instant and the steady-state mean phase error. Subst i tut ing this expression into (3.41) results i n ? ; + i = ( l - ^ p ) ? ' f c . (3.60) Equat ion (3.60) can be rewrit ten recursively to obtain an expression i n terms of tp'0, which is the in i t i a l phase error difference from i p S 3 . Therefore, K ' M X k <Pk = (1 - — j Vo- (3-61) Subst i tut ing this expression into the definition of acquisition time, E q . (3.59), and solving for k yields , . log (yQ - log (\<Po\) ,„ «™ * " l o g ( H - ^ | ) • ( 3 ' 6 2 ) The value of k, however, must be restricted to the set of non-negative integers. W h e n the R . H . S . of E q . (3.62) is negative, which is the case where the in i t i a l phase error is wi th in the given level <pe, the acquisition time, and consequently k, is zero. For values of k which are positive, the cei l ing function when applied to the R . H . S . of E q . (3.62), gives the m i n i m u m integer value required. Hence, log ( < p e ) - log Q'0[) log k > 0. (3.63) 37 Chapter 3: Characterization of the MDTL The term 1 — determines the rate of convergence for the phase error process and should be as close to zero as possible for fast acquisition. In fact, i f is unity, the m a x i m u m value that k can assume is one, which indicates that the acquisition process w i l l always terminate after one sampl ing period. For a given B and M, this leads to K' = (3.64) M or consequently, i n terms of the normalized digital loop coefficient K = ^-.^-. (3.65) H a v i n g obtained k, the total elapsed time can be wri t ten as A ^ B 3=0 °U 27T (3.66) The loop phase estimate Ok, can be expressed i n terms of the in i t i a l phase error and the steady-state mean phase error and hence, the acquisition time Tacq, normalized to mixed-down carrier cycles is given by = * - 7 f r o - y „ ) ( 3 i 6 7 ) H DM. _ l _ 1 where i - ( i - ^ y T = n • (3-68) Thus , for a given loop configuration and an i n i t i a l phase error, the acquisition t ime can be given explicit ly. In addition, a good approximation for Tacq can be 38 Chapter 3: Characterization of the MDTL T ± 0 acq k_ A (3.69) when the frequency offset ratio w0/w,-„ is close to unity, that is A0 sw 0. A s an i l lustrat ive example, Figure 3.10 shows the acquisition times versus in i t i a l phase error for a given loop configuration and various values of A, B and M. The acquisition l imi t (pc = 7r / 3 2 M , is a function of M since the range of values for which the in i t i a l phase error can assume is a function of 1 / M . Note that when the in i t i a l phase error is wi th in cpe, the acquisition time is zero. A s the distance between the in i t i a l phase error and the steady-state mean phase error increases, the acquisition time increases. B y increasing the mult i -sampling rate, however, the acquisition t ime is reduced. In this part icular example, increasing M also decreases the acquisition time since the term approaches unity. F ina l ly , note that the acquisition time increases at finite values of tpQ. This step increase is due to the discrete values for which k can assume. If the distr ibution of the in i t i a l phase error is known, then i t is possible to determine the cumulative density function of the acquisition time. F r o m Baye's' rule, the probabili ty of acquiring lock w i th in [0,nk), denoted as Prob [Tacq < nk] can be written as [651 where nk is the time expressed i n mixed-down carrier cycles. The in i t i a l phase error is assumed to be uniformly distributed p[<po] = M/2-ir, (p0 G [jtf-,jf) so that E q . (3.70) can be evaluated numerically. Figure 3.11 shows the probability of acquir ing lock for the acquisition times shown i n Figure 3.10 given a uniformly distributed in i t i a l phase error. In Figure 3.11 (a), M = 1 whereas i n Figure 3.11 (b), M = 2. 3.3.3 Comparison of the MDTL with Loops Employing the Tanlock Principle The M D T L is an extension of the D T L s proposed by Lee, K i m and Cho [59,14, 60]. Consequently, the phase error difference equation which governs the behaviour of the M D T L can also predict the performance of the loops which employ the Tanlock principle. The following is a brief comparison between the M D T L and the loops previously mentioned i n terms of the steady-state mean phase 7T/M (3.70) -n/M 39 Chapter 3: Characterization of the MDTL 20 17.5 15 12.5 7.5 5 2.5 0 A =1 B=l M-l -ic -3it/4 -it/2 -it/4 0 it/4 n/2 3ic/4 ic (a) 5" 12 10.5 9 7.5 6 4.5 3 1.5 0 I A = 4 B = 2 M-l -it -3ic/4 -it/2 -it/4 0 it/4 TC/2 3ic/4 it (b) 8 7 6 5 4 3 2 1 0 -ic/2 -3JC/8 -it/2 -7C/8 0 7t/8 ic/4 3ic/8 TC/2 (c) I A = 4 B = 2 M = 2 8" 6 5.25 4.5 3.75 3 2.25 1.5 0.75 0 A = 9 B = 3 M = 2 -TC/2 -3ic/8 -TC/2 -7C/8 0 it/8 it/4 3it/8 ic/2 (d) Figure 3.10: Normalized Acquisition Times versus Initial Phase Error for K' = 1/5, A Q = ir/10, ipe = i r / 3 2 M and Various Values of A,B and M. error, the region of stability, the lock range and the acquisition time. The comparisons assume the absence of any phase error disturbance. Case 1: Lee's DTL The D T L proposed by Lee tracks the positive zero-crossings of an unmodulated carrier frequency. The phase error difference equation for Lee's loop is given by 40 Chapter 3: Characterization of the MDTL = 1.B = / 1 1 A = 4,B-. = 2 12 16 20 24 28 32 (a) 0.875 0.75 0.625 8" 0.5 1 1 o 0.375 0.25 0.125 I I i 1 1 1 1 1 1 1 1 1 t i i i f 1 1 1 / J -; A - A tt --1 I : / _ _ A no 3 -1 1 1 ' ' ' • 1 1 i i i 1 1 1 1 1 1 I I I 0.75 1.5 2.25 3 (b) 3.75 4.5 5.25 6 Figure 3.11: Probability of Acquiring Lock versus the Normalized Total Elapsed Time for K' = 1/5, A c = TT/10, and <pe = n/32M (a) M = 1 (b) M = 2. (3.39) when A = B = M = 1. If the M D T L is t racking an unmodulated carrier frequency wi th the ratio B/A less than unity, the steady-state mean phase error and the acquisition time decreases, and the region of stability and the lock range increases. A s an example, the lock range i n Figure 3.9 (a) represents the lock range of Lee's loop whereas Figure 3.9 (b) represents the lock range of the M D T L . For a given K the M D T L has a wider lock range than the conventional D T L or alternatively, for a given lock range, the M D T L can have a smaller value of K than the conventional D T L , and thus the M D T L has more immuni ty for additive noise. Case 2: Kim's DTL The D T L proposed by K i m tracks the positive zero-crossings of a suppressed-carrier M - a r y P S K signal, A = B = 1. For the same value of M and given a ratio B/A less than unity, the steady-state mean phase error and the acquisition time of the M D T L decreases, and the region of stability and the lock range increases. The M D T L , however, requires a greater number of functional elements than Kim ' s D T L . 41 Chapter 3: Characterization, of the MDTL Case 3: Cho's D T L The D T L proposed by Cho tracks an unmodulated carrier frequency wi th the mul t i -sampling scheme, M = 1. For given values of A and B, the M D T L when t racking an unmodulated carrier frequency represents Cho's D T L and consequently, the performance of both loops is identical . The M D T L , however, can be configured to track suppressed-carrier M - a r y P S K signals as wel l . In a l l three cases, the M D T L offers distinct advantages over the compared loops at the expense of addit ional system elements. In addition, the M D T L can be made to emulate any one of the previous loops by vary ing the values of A, B and M . 42 Chapter 4 Testing Environment of the MDTL The analysis of the M D T L i n the absence of noise, has led to closed-formed expressions for the steady-state mean phase error, the region of stability, the lock range and the acquisition time. In the presence of noise, however, the behaviour of the M D T L is more difficult to analyze. A s mentioned i n Chapter Two, several researchers have successfully characterized D P L L s i n the presence of noise us ing the Chapman-Kolgomorov equation [66]. In the phase error difference equation (3.39), <pk is a discrete-time, continuous variable M a r k o v process, and consequently, the probability density function of <pk also satisfies the Chapman-Kolgomorov equation. The phase error disturbance £ fc i n (3.39), however, is difficult to model accurately since the pdf of the distorted data phase £ k is only an approximation when modulation is present 4 . A s a result, the solution to the Chapman-Kolgomorov equation becomes an approximation. In addition, the effects of quantization and mult i -sampling are not accurately reflected i n this solution and the computational complexity and the time required to obtain an approximate solution does not fully justify the use of this technique. For these reasons, the baseband model of the M D T L is not used to obtain performance results i n the presence of noise. Instead, the M D T L shown i n Figure 3.1 is used to model the loop's performance i n the presence of noise. The task of model l ing the M D T L is divided into two separate testing platforms. The first platform is a software testbed where the effects of A W G N are present. The software platform simulates the system i n the presence of noise and acts as a reference model. The second platform is a hardware testbed where a l l other secondary impairments such as quantization and loop delay are present. The hardware platform represents the implementable case which accurately reflects the performance degradation from the reference model. This chapter w i l l deal wi th the design, implementation and problems of both these systems, while Chapter F ive w i l l present the performance results obtained. 4 Refer to Appendix A.3 for a detailed description on the statistical characteristics of the phase detector in the presence of noise. 43 Chapter 4: Testing Environment of the MDTL 4.1 Software Platform of the MDTL The purpose of the software testbed is to simulate the M D T L and to obtain performance results i n the ideal case for a received Signal-to-Noise Ratio (SNR). In order to accomplish this task, i t is necessary to first enumerate the simulation requirements to determine a test environment, and then design a structure which effectively models the M D T L and which is suitable for data gathering and analysis. 4.1.1 Simulation Requirements The M D T L is highly structured wi th every block being wel l defined. The simulat ion program should reflect this structured environment since the use of blocks forces the system designer to minimize the amount information passed between blocks. This approach eliminates the need for complex interface units. The simulation program must be able to work wi th sampled-data signals so that commonly-used Digital Signal Processing (DSP) techniques can be applied. F ina l ly , the simulat ion program must be flexible so that the blocks which make up the M D T L can be integrated into the simulat ion program wi th l i t t le difficulty. The program chosen for the software simulation is a general purpose t ime-driven simulation program for sampled-data systems called BLOck SIMulator ( B L O S I M ) [67]. B L O S I M is a ' C language discrete-time simulator which provides a h ighly structured environment for simulation. B L O S I M is very natural to use for system designers since i t encourages the division of the system into smal l interconnected blocks i n the same way that a system is parti t ioned for implementation. The user must provide a simulation program for each of these blocks, and a specification of the topology for block interconnection. B L O S I M includes as features: • Hierarchical Specification of Blocks: New blocks can be defined which are made up of specified interconnections of other blocks. For example, the complete topology of the system is called the universe. The universe is made up of ind iv idua l blocks called stars and groups of interconnected blocks called galaxies. The nesting of stars and galaxies wi th in galaxies is unl imited. Hence, i t is possible to design a system without knowing the implementat ion details of the fundamental units which make up this system. 44 Chapter 4: Testing Environment of the MDTL • Interconnection of Blocks by Random Access Buffers: Blocks are interconnected v i a random access buffers. The output data samples from one block are passed through a buffer before reaching the input of the destination block. Buffer management is transparent to the user who must only specify the interconnection between blocks. The use of random access buffers allows the user to access past samples thereby e l iminat ing program complexity. • Passing of Parameters to Blocks: Parameters which are specified i n the topology file are passed to the ind iv idua l blocks at run-time. The type of parameters which can be passed are integer and floating point numbers, arrays, files and functions. • Multiple Instances of Blocks: The same block can appear many times wi th in a simulation. The functionality of the block can be specialized by passing i t different parameter values. For example, an IIR bi-quadratic filter block was created for the A F E . This block is used eight times wi th in the simulation and is configured for different bandwidths and center frequencies. • Consistency Checks and Narrative Mode: B L O S I M makes consistency checks during topology definition and execution, a l lowing i t to detect user programming errors. In addition, B L O S I M has a narrative mode which lists the actions taken by the program. This narrative feature allows the user to verify the topology definitions and the execution of the ind iv idua l blocks. • Automatic Scheduling on the Order of Block Execution: The order i n which the blocks are executed is automatically scheduled at run-time for efficiency. B L O S I M ' s ma in disadvantage is that the user must be knowledgeable i n ' C . Once the blocks have been created, however, they may be accumulated to form a l ibrary of routines which may be used afterwards. B L O S I M is public-domain and is available from the Univers i ty of California at Berkeley. 4.1.2 Test Configuration The phase error process, the acquisition process and the hold-in process are the three performance measures used to characterize the performance of the M D T L i n the presence of noise. A l l three 45 Chapter 4: Testing Environment of the MDTL measures, which are denned i n Chapter Five, require an exact expression of the phase error at every sampling instant. The simulation must be able to generate this phase error information. Figure 4.1 shows the block diagram of the M D T L test configuration which is needed to acquire a l l three performance measures. This method of acquiring data resembles the one used by Charles [68]. AFE MDTL Channel i i | PRBS F i g u r e 4 .1 : Block Diagram of t h e MDTL T e s t Configuration. The top branch of Figure 4.1 consists of the M D T L and the blocks needed to exercise the loop. The transmitter consists of a Pseudo-Random Bit Sequence (PRBS) generator and a B P S K modulator. The modulated signal is corrupted by A W G N i n the Channel block. F ina l ly , the received signal is passed to the A F E whose outputs represent the inphase and quadrature signals used for the loop under test. The bottom branch shows the blocks needed to extract the phase error information for the test results. The Z E R O block outputs a stream of zeros which, when passed through the B P S K modulator, generates an unmodulated carrier frequency. This carrier signal is synchronized to the modulated carrier s ignal and is fed directly into an A F E which is identical to the A F E being tested. A s a result, the lower inphase and quadrature arms do not suffer from any phase error disturbance. The sampling process from the loop under test is used to sample the noise-free signals to obtain an exact phase error expression. F ina l ly , the test block, which is configured for the part icular performance measure, acquires the samples for subsequent analysis. In the acquisition and hold-in tests, the test block must also be able to communicate w i th the loop under 46 Chapter 4: Testing Environment of the MDTL test. Chapter Five discusses the algorithms used to obtain each measure i n greater detail. The topology files which define the three performance tests are listed i n Appendix B . In order to generate comparable results from both test platforms, both the simulation program and the hardware implementation must conform to the following specifications: • Car r ie r frequency: 115.2 k H z ; • D a t a Rate: 9600 bps; • Mixed-down Carr ie r Frequency: 19.2 k H z ; • Mul t i - sampl ing Rate: A = 1,2,4,8; • Loop G a i n Value: B = 1,4; • Modula t ion Format: M = 2 for B P S K ; and • Normal ized Dig i ta l Loop Coefficient: K = 2 _ n , n = 0, • • •, 5. In addition, the filters used i n the A F E are identical to those of the hardware implementation. The filter specifications are given i n § 4.2.1.1. F ina l ly , the sampling frequency used for the simulat ion is fs — 1.152 M H z which is ten times the rate of the carrier frequency. 4.1.3 Calculating the Input SNR To calculate the receiver input S N R , i n the form of Eb/N0, we note that the variance of the noise samples added by the channel block is given by [62] Given (4.1) and the ratio between the bi t period and the sampling period, the input S N R can be wri t ten as where / j — 9600 bps. In E q . (4.2) Eb, N0/2 and Pc denote, respectively, the received energy per bit, the power spectral density of the received noise, and the received average power of the B P S K signal. Pc, c r 2 , fs and fb are parameters which are set by the user and placed i n the topology file. To verify E q . (4.2), a trace routine was connected to the output of the Channe l block. The (4.1) N0 N0 2o-2 X f6 Eb PcTb Pc f, (4.2) 47 Chapter 4: Testing Environment of the MDTL trace routine obtains a time domain representation and a power spectral density estimate of its input signal. Given Pc = 0.5, G\ = 1 and the ratio between the bi t period and the sampling period, E q . (4.2) yields an S N R of 14.77 dB. Figure 4.2 shows the received t ime and frequency domain waveforms. A spectral estimate of the simulated B P S K waveform, shown i n Figure 4.2 (b), reveals an S N R of approximately 15 dB . 0 115.2 230.4 345.6 460.8 fs/2 Frequency (kHz) (b) Figure 4.2: Simulation of the Transmitted BPSK Waveform with/without AWGN. (a) Sample Time-Domain Representation (b) Power Spectral Estimation. 48 Chapter 4: Testing Environment of the MDTL 4.2 Hardware Platform of the MDTL A hardware implementation of the M D T L was designed, bui l t and tested. The experimental uni t tracks an incoming 115.2 k H z modulated carrier. The modulation formats can be either B P S K , Q P S K or 8 - P S K w i t h a selectable data rate ranging from 600 to 28 800 bps. The purpose of the hardware model is to: • study the feasibility of implementing the M D T L using a standard T T L / C M O S technology; • determine the problems typically associated wi th coherent demodulation at the hardware abstraction level; • develop techniques required to overcome these problems; and • study the effects of quantization on the performance of the loop and to compare results w i th those obtained from the software simulat ion. 4.2.1 Functional Description of the Loop Components Figure 4.3 shows a simplified block diagram of the M D T L . These blocks are the A F E , the phase detector / data extractor, the digital loop filter, the N C O and the sequencer. To separate the different signals wi th in the system, N-b i t wide digital data paths are represented by a shaded arrow whereas analog signals or digi tal control signals are represented by thinner arrows. Incoming Signal Analog Front End Inphase Arm Quadrature Arm Phase Detector/ Data Extractor Sequencer \ Control Signals Phase Error Data Samples •i.u...MM...ii.li.um»v Figure 4.3: Block Diagram of a Hardware Implemented M D T L . 49 Chapter 4: Testing Environment of the MDTL 4.2.1.1 The Analog Front End Figure 4.4 shows the components which make up the A F E . The A F E consists of a bandpass filter centered about the carrier frequency, two mul t ip l ier units, a local oscillator, two bandpass niters centered about the mixed-down frequency and two signal level estimators. fs= 19.2 kHz Figure 4.4: Block Diagram of the A F E . Two second-order bandpass niters, wi th center frequencies of 115.2 k H z and Q of 2.0, are cascaded to form a fourth-order bandpass filter. This filter eliminates unwanted noise i n the out-of-band region. The bandpass filter may be replaced by a bandpass l imi ter to protect the remain ing components from excessive signal levels i n the incoming signal [2]. Various circuits can be used to make up the mul t ip l ier units. The part icular arrangement chosen depends heavi ly on the frequency range of interest. The analog mixer is ideally suited to R F applications, whereas analog mult ipl iers or chopper circuits are better suited to lower frequency ranges. For the experimental unit , chopper circuits are chosen over analog mult ipl iers since choppers simplify design, and provide better stability. A local oscillator of 96 k H z is needed to beat the 115.2 k H z signal down to 19.2 k H z . When chopper circuits are used, the local oscillator is a digi tal clock which controls the analog switches. The 90° phase-shifted clock for use i n the quadrature a rm is generated us ing two Fl ip-Flops . It is important to note that a tradeoff exists when choosing the mixed-down carrier frequency. A s the mixed-down carrier frequency decreases, the response time of the system decreases and 50 Chapter 4: Testing Environment of the MDTL al ias ing occurs, that is the spectral terms overlap around 0 H z . Conversely, as the carrier frequency increases, the cost of the technology needed to run at higher speeds increases. One reasonable compromise is to choose the mixed-down carrier frequency to be a mult iple of the data rate. For the experimental unit, the mixed-down carrier frequency chosen is twice the data rate. A disadvantage of the chopper circuit is the creation unwanted harmonics at 96 k H z intervals. A s a result , a bandpass filter wi th a steep rolloff is desired. Two second-order bandpass filters, each wi th a center frequency of 19.2 k H z and a variable bandwidth, are cascaded to form the fourth-order bandpass filter required. The Analog to Digital Converters (ADCs) require that the incoming signals be centered about 2.5 Vdc. The necessary circuitry needed to add this offset is incorporated into the bandpass niters. The A F E would normally have an A G C circuit i n order to keep the signal at a constant level. Ideally, the M D T L does not require an A G C circuit since the ratio between the inphase and quadrature arms eliminates any amplitude information. In practice, however, this is not the case. Quantizat ion mismatch introduces noise, i n the form of granular noise or overload distortion, and can severely degrade the S N R of the signal. For a properly designed system, the signal-to-quantization noise ratio is roughly + K dB , where N represents the number of bits of quantization and K is a constant which is dependent on the signal [69]. A n alternative approach to an A G C , and one which is used i n the experimental unit , is the level estimator for adaptive quantization [69]. Signal level estimators are used to estimate the signal range of the inphase a rm and this estimate is passed to the (ADC) to dynamically change the step size of the quantizer. The quantizer step size is defined as (V+ — V~)/N where V+ represents the m a x i m u m signal estimate and V~ represents the m i n i m u m signal estimate. The quantity, N, represents the number of quantization levels. The reasons for choosing this latter A G C circuit are twofold. Fi rs t , the signal level estimator can be set to adapt either quickly or slowly to changing input conditions, depending on the application. In our case, a time-constant of 1.0 msec is used for an increase i n signal amplitude and 19.6 msec for a decrease i n signal amplitude. Second, the circuit is simple and stable. The major disadvantage is the circuit 's poor performance for very weak signals, below 50 m V peak-to-peak. This is due to the l imitat ions of the A D C chosen. 51 Chapter 4: Testing Environment of the MDTL Fina l ly , a relay switch and a variable gain amplifier are placed i n front of the A F E . The relay allows the user to switch from a remote signal to a locally generated signal, enabling integrity loopback testing for diagnostic purposes. The variable gain amplifier sets the received signal to a workable level, approximately 5.0 V peak-to-peak. The schematic layout of the A F E is shown is Figure C . l l i n Appendix C. 4.2.1.2 The Phase Detector / Data Extractor The Phase Detector I Data Extractor (PD/DE) provides an estimate of the phase error between the received signal and the sampling pulse of the N C O . Provisions were also added for the data extraction function, although at present, the function i tself is undefined. The blocks which form the P D / D E are the / (inphase) and Q (quadrature) A D C s , the lookup tables for the tan" 1, data extraction, and phase error functions, and the switch programmable resolution selectors. Figure 4.5 shows the block diagram of the P D / D E . Inphase Arm ADC +ve Peak -ve Peak Quadrature Arm ADC A n n Sampling Pulse t a n 1 ' x k 1 . y " J >> Lookup N-bit Resolution Selectors U n d e f i n e d Lookup Lookup Data Samples Phase Error Figure 4.5: Block Diagram of the PD/DE. The A D C s sample and quantize both the / and Q arms of the received signal to give two eight-bit unsigned values, 0 represents the m i n i m u m value and 255 represents the max imum value. The A D C s are configured as mid-riser quantizers and use the signal level estimates from 52 Chapter 4: Testing Environment of the MDTL the A F E to adapt the quantizer step size. Sampl ing is controlled by the sequencer. The part icular A D C chosen uses a half-flash technique to achieve a conversion time of approximately 1.34 /isec, thus e l iminat ing the need for an external sample-and-hold circuit. In addition, the A D C s have bui l t - in latches which hold the eight bit values for the tan" 1 lookup table. Resolution selectors are used after the A D C s and the various lookup tables to allow the performance of the M D T L to be evaluated for a given number of quantization levels. The number of quantization levels is reduced by zeroing the selected least significant bits of the eight-bit input sample. The number of quantization levels for each resolution selector is controlled by a D I P switch which can vary the number of sampling bits from one to eight bits. Programmable Array Logic (PAL) Integrated Circuits (ICs) are used to implement this function. The I and Q samples of the received signal are combined to create the phase angle estimate us ing the tan" 1 function. Several methods exist to generate this function. One scheme would be to calculate a power series expansion for the tan" 1 function. This method, however, consumes a great deal of t ime. The method chosen for the experimental un i t is the use of a lookup table which contains precalculated values for a l l possible signal inputs. A lookup table is conceptually simple, can be implemented us ing a standard Programmable Read-Only Memory ( P R O M ) and has considerable flexibility. The inphase sample forms the most significant byte address and the quadrature sample forms the least significant byte address. The output of the P R O M is an eight bi t two's complement number representing the phase angle estimate of the received signal. As an i l lustrat ive example, consider two three-bit unsigned I and Q samples mapped into a two's complement four-bit phase angle shown i n Figure 4.6. The circular dots represent/ , Q pairs. The lines which radiate outward from the origin define the decision regions for the phase angle. The triangles encircling the constellation represent the phase angle estimates which, i n this case, are given i n two's complement notation. A s an example, consider the coordinate (1,6) where xk = 6 is sample from the / a rm and yk = 1 is the sample from the Q arm. This coordinate falls wi th in the shaded decision region and hence would generate a two's complement value zk = 6 from the lookup table. Note that a l l amplitude information is lost i n this estimate. If amplitude-dependent modulation formats are used, another lookup table us ing could be used to generate the necessary amplitude information. 53 Chapter 4: Testing Environment of the MDTL ' k I ( X K ) -4 Figure 4.6: Mapping From / and Q Samples to the Phase Angle Estimate. The phase angle estimate contains unwanted information due to modulation and mul t i -sampling. To obtain a workable phase error estimate for synchronization, the phase error function is implemented us ing a P R O M and a resolution selector. The P R O M lookup table contains a quantized form of E q . (3.25) defined i n Chapter Three. The table index consists of the output value from the tan" 1 lookup table, the modulation index M and a count value k = 0,...,A - 1 generated by the sequencer. The value of A is controlled us ing a D I P switch and the access time of the P R O M is approximately 50 nanoseconds. I f speed is less cri t ical , the phase error function could be implemented i n a microprocessor. The circular mapping from modulo arithmetic to two's complement ari thmetic makes this latter alternative attractive. F ina l ly , provisions have been allocated for the data extraction function. A bipolar P R O M along wi th a resolution selector are needed to perform this function. The table index is identical to that of the phase error function. This allows considerable freedom as to the type of algorithm used. A s of yet, the lookup table is undefined. Figure C.12 i n Appendix C shows the schematic layout of the P D / D E . 54 Chapter 4: Testing Environment of the MDTL 4.2.1.3 The Digital Loop Filter The behaviour of the M D T L depends largely on the transfer characteristics of the digi tal loop filter. This filter processes the phase error estimate resul t ing from the output of the phase detector. A discrete filter design was chosen to minimize the delay through the loop. Figure 4.7 shows the block diagram of the first-order digital loop filter. Figure 4.7: Block Diagram of the Digital Filter. The digital equivalent of the analog integrating element, such as a RC filter, is an accumu-lator [21]. In our case, the digi tal loop filter uses a resource shar ing mechanism whereby the mul t ip ly ing element, that is the barrel shifter, and the adder, are used twice to implement a second-order filter. To see this, consider the Proportional-Integral (PI) output characteristic of the digi tal loop filter denoted by the relation k Ck = Giek + G2^2ej (4.3) j = 0 where, ej, j = 0,...,k represents the incoming phase error samples, G\ and G2 represent the digi tal loop filter coefficients and ck represents the correction factor at time k for use by the N C O . To implement the resource sharing mechanism, we assume that the accumulator Acc, maintains 55 Chapter 4: Testing Environment of the MDTL k-l a weighted, runn ing sum of the past samples, that is Acck-i = G2 ej. O n that assumption, 3 = 0 E q . (4.3) can be wri t ten as ck = Giek + G2ek + Acck-i (4.4) We see immediately from E q . (4.4) that ck is the result of two multiplications of the input signal by the filter coefficients and two additions. In order to main ta in the weighted, runn ing sum of the past samples, the accumulator is updated us ing the following expression. Acck = G2ek + Acck_i (4.5) The following l is t specifies the order of operations needed to implement the P I controller. • M u l t i p l y the incoming signal ek by the filter coefficient G2 and add i t to the current value of the accumulator Acck-i-• Store this value into the accumulator, that is the accumulator holds the value Acck. • M u l t i p l y the incoming signal ek by the filter coefficient G\ and add i t to the current value of the accumulator Acck. • Store this value, ck into the output register. A t this point, the correction factor is sent to the N C O and the digi ta l loop filter is ready for the next sample. To facilitate the design of the filter and to decrease the execution time, a barre l shifter was chosen for the mult ip l ier . Shift ing an input sample to the r ight by n bits is equivalent to a divide by 2™ operation. The coefficients G\ and G2 are four bi t values which represent the shift amounts where 0000, i n binary, represents no shift, that is 1 x 2°, and 1111, i n binary, represents a r ight shift of 15 positions, 1 x 2 - 1 5. For a two's complement notation, the higher-order bits of the output sample are sign extended. Note that the coefficients i n this experimental uni t are normalized to the mixed-down carrier frequency. Hence, ck w i l l differ sl ightly from the correction value i n Chapter Three. A scaling by l/w0 is needed to convert ck into a workable time value and this scaling operation takes place i n the N C O . 56 Chapter 4: Testing Environment of the MDTL In terms of functionality, a barrel shifter is identical to a conventional shift register. U n l i k e conventional shift registers, the desired number of positions to be shifted is determined by an input decoder, hence e l iminat ing the need for a clock. The speed of the shift operation is restricted only by in ternal propagation delay and this delay is the same regardless of the number of positions to be shifted. The net effect is a high-speed shifter wi th a propagation delay of approximately 30 nanoseconds. The 16-bit accumulator and the 16-bi t output register are implemented us ing four P A L s . These P A L s perform the necessary la tching of information and overflow management. Overflow is detected when the carry bits of the two most significant digits from the adder output are different. If overflow occurs the output values from the P A L s are set to the max imum, or m i n i m u m value depending on the sign bi t of the input sample. In addition, the accumulator may be held at zero, us ing a D I P switch, to change the order of the filter, between first- and zero-order. Fo r the purpose of testing, the digi tal loop filter is configured as a zero-order filter. If problems associated wi th rounding or truncation are present, the designer has the option of us ing a floating-point digi tal signal processor. The advantages of this option are flexibility, ease of design and integration. The disadvantages are price and execution time. A s a comparison, the digital loop filter implemented can deliver an output sample every 150 nanoseconds whereas a T M S 3 2 0 C 3 0 runn ing at 40 M H z w i l l execute one P I controller step i n approximately one psec. Figure C.13 i n Appendix C shows the schematic layout of the digi tal loop filter. 4.2.1.4 T h e N u m e r i c a l l y - C o n t r o l l e d O s c i l l a t o r Quant iz ing the correction value forces the designer to quantize the N C O operation. In addition, N C O (or clock) quantization is necessary since, i n practice, i t is very difficult to design an N C O whose sampling interval Tk is continuously variable. The circuit used to perform the N C O operation wi th clock quantization is shown i n Figure 4.8. The N C O consists of a down counter, a h igh frequency oscillator and a lookup table. The frequency of the oscillator fosc is a mult iple of the mixed-down carrier frequency f0, that is f0,c = Nf, (4.6) 57 Chapter 4: Testing Environment of the MDTL 11 10-a n 2 -2 c Lookup Switch Values for ' a ' and ' n ' 19.6608 MHz 11. 5 5 g 5 ^ 3 B L o a d Pulse osc 11-Bit Down Counter Sampling Pulse • Figure 4.8: Block Diagram of the NCO. where N is denned as the N C O resolution and i n this case is equal to 2 1 0 . N gives the number of phase states possible wi th in 2TT, hence 7T A = ^ = N 512 (4.7) where A is the separation between phase states. In this part icular implementation of the N C O , A is programmable which allows the effects of clock quantization on the loop's performance to be determined. The circuit arrangement i n Figure 4.8 is equivalent to a programmable divide-by-P circuit. The lookup table converts the correction factor ck, into a count value which is then loaded into the counter. The counter is decremented and when the count value reaches zero, the A D C s are sampled. B y va ry ing the load value, the period of the N C O can be controlled. To derive an expression for the load value, we rewrite the equation for the sampling interval as T Tk = - C • Ck-i (4.8) where C is a constant to be denned later and Ck-i is the output of the digital filter. Equat ion (4.8) differs sl ightly from the sampling interval equation (3.13) derived i n Chapter Three since the normalized digi ta l loop filter coefficient, i n this experimental unit , incorporates the loop gain 58 Chapter 4: Testing Environment of the MDTL factor B. In addition, as previously mentioned, ck-i is not scaled by l / w 0 . Hence, C is used to perform this scaling and can be expressed as c = £ = £ ( 4- 9 ) where A / w 0 defines the time resolution of the sampling interval . The mul t i -sampl ing value A is a mult iple of 2, and can be represented as A = 2a, a = 0,... ,3. Subst i tut ing the expressions for A and C into (4.8) and factoring the oscillator period i n our experimental unit , we get r * = p r [ 2 1 0 - f l - c t _ i ] (4.10) wi th the restriction that ck-i < 2 1 0 _ a. Equat ion (4.10) states that the sampling interval can be represented as a mult iple of the oscillator period. To vary the amount of clock quantization a s imi lar expression can be wri t ten, where = ^ [ 2 1 0 — ( 4 ' n ) where T o/2 1 0 _ n, n = 0, •••,7 represents the oscillator period, and ck-i is restricted to ck-i < 2 1 0 _ n _ a. In order to use a constant oscillator frequency for a l l values of clock quantization, we mul t ip ly both the numerator and denominator of (4.11) by 2n to obtain Tk = | | [210-° - 2nci_1] (4.12) Hence, decreasing the number of phase states is equivalent to reducing the resolution of CA_I. The expression w i th in the square brackets is stored wi th in the lookup table and the values of a and n are selectable v i a D I P switches. In addition, the values wi th in the lookup table take into account the time offset given by the loop delay. A n eight segment display is controlled by the unused memory i n the lookup table. The display gives an indication of whether the M D T L is i n lock by comparing at each sampling instant the load value wi th the nominal load value. If the load value is wi th in 10% of the nominal value, an L is displayed which indicates that the loop is t racking. S imi la r ly , i f the load value deviates from the nominal value by more than 25%, an A is displayed which indicates that the loop is acquiring. 59 Chapter 4: Testing Environment of the MDTL The display is left b lank dur ing the transi t ion period between the acquisition process and the t racking process. It should be noted that the display acts as a v isua l aid when configuring the loop and is not used for accurate measurement of lock. Figure C.14 i n Appendix C shows the schematic diagram of the N C O . 4.2.1.5 The Sequencer The sequencer coordinates the activities of the various loop components. The sequencer consists of a 64-state Finite State Machine ( F S M ) P A L and a Da ta Controller P A L . The F S M performs the operations needed to control the A D C s , the flow of data, the digital loop filter, and the N C O . The inputs to the F S M are the sampling pulse generated by the N C O and a reset signal. The state diagram of the F S M is shown i n Figure 4.9. 11 [Tj Start Sequence of Events 11 riT| Sampling Pulse Negated fi~] Sampling Pulse Asserted fx] Don't Care Figure 4.9: State Diagram of the FSM. The m i n i m u m time required to complete a cycle through the loop is 64 clock cycles and is referred to as loop delay. The operation of the M D T L is not affected by the loop delay i f the sampling interval exceeds this delay. Otherwise, the sampling interval assumes the value of the loop delay which, unfortunately, introduces a nonlinearity. This nonlineari ty is negligible i f the loop delay is much smaller than the nominal sampling interval . K o i z u m i has suggested methods to eliminate the nonlinearities created by loop delay i f loop delay is comparable to the sampling interval [53]. For the experimental unit , these methods were not necessary. The operation of the F S M is as follows. The F S M remains i n its idle state (63) un t i l a sampling pulse from the N C O triggers a new sequence. The F S M signals the A D C s to acquire a new sample while the a control signal is sent to the data controller to increment the k count which is then 60 Chapter 4: Testing Environment of the MDTL passed to the phase error function lookup tables. The F S M increments unconditionally through the various states while asserting the appropriate signals at the proper times. When the F S M returns to its idle state, i t is ready to receive a new sampling pulse from the N C O . In addition, the reset signal, when asserted, overrides the sampling pulse and halts the execution of the loop. The F S M immediately goes into its idle state and remains there un t i l the reset signal is negated. Table 4.1 enumerates the actions performed by the F S M at the given states. These state values were determined by the propagation delays of the various components. S t a t e N o . A c t i o n s P e r f o r m e d 0 Signal data controller to increment 'k' count. Assert sampling signal to the A D C . 13 Negate sampling signal. 40 La tch data from A D C into the resolution selector. 50 La t ch data into the accumulator. S ignal data controller to output filter coefficient G2. 53 L a t c h data into the loop filter output register. S ignal data controller to output filter coefficient G l . 59 Asser t load signals to the N C O down counter. 61 Negate load signals. Table 4.1: Actions Performed by the F S M . The data controller must cycle through the various values of k depending on the value of A. The data controller also multiplexes the digi tal loop coefficients for the barre l shifter. These outputs are triggered by the F S M at the appropriate time. In addition, a user-selectable signal is passed to the data controller to allow the user to select between a zero- or first-order digital loop filter. Figure C.15 i n Appendix C shows the schematic layout of the sequencer. In addition, the software listings for a l l P A L and P R O M designs required for implementation of the M D T L are listed i n Appendix C. 4.2.2 Test C o n f i g u r a t i o n A controlled test environment, s imilar to the test configuration i n Figure 4.1, was developed to test 61 Chapter 4: Testing Environment of the MDTL the functionality of the M D T L , and to evaluate its performance. Figure 4.10 shows the functional block diagram of the M D T L along wi th the supporting blocks needed to exercise the M D T L and to gather data. The test configuration consists of a data source, a transmitter, a noise channel, the M D T L , the phase error reference circuit, a data acquisition unit, and finally, a personal computer to capture and analyze the data. The H P 1 6 4 5 A data error analyzer is a commercial uni t capable of generating fixed and pseudo-random bi t sequences at moderate data rates. The generated bit sequence is modulated onto a 115.2 k H z carrier. The modulated carrier is corrupted by A W G N , and is passed to the A F E . S imi la r ly , an unmodulated carrier which is synchronized to the modulated carrier is passed the to reference circuit i n order to obtain the exact value of the phase error. F ina l ly , a data acquisition un i t extracts the necessary information for subsequent analysis by the personal computer. Voltmeter Figure 4.10: The Hardware Test Environment. Appendix C describes i n greater detail the design of the supporting hardware and evaluates the hardware implementation. A photograph of the hardware implementation is shown i n Figure 4.11. 4.2.3 Calculating the Input SNR To calculate the receiver input S N R , i n the form of Ei/N0, a true rms voltmeter was used to measure the power components of the modulated signal and the noise signal separately. The received energy per bi t is given by 62 Chapter 4: Testing Environment of the MDTL Figure 4.11: Photograph of the Hardware Implementation. V2 Eh = PcTb = (4.13) Jb where VSrmt represents the measured rms voltage of the modulated signal and / j is the b i t rate. S imi la r ly for the noise component, we have V2 N0 = (4.14) In where Vnrm, represents the measured rms voltage of the noise signal and / „ is the noise equivalent bandwidth. Combining equations (4.13) and (4.14) we obtain N0 V2 fh 63 Chapter 4: Testing Environment of the MDTL A Krohn-Hi te (Model 3202) filter was configured as an 8th-order bandpass filter and was used to bandl imi t the noise spectrum. Consequently, the noise equivalent bandwidth was ap-proximately equal to the 3 dB bandwidth of the filter [70]. 64 Chapter 5 Performance Evaluation Three M D T L performance measures are presented i n this chapter which include phase error distributions, acquisition times and hold-in times. For a l l three cases, a test procedure is defined and results from the software simulation and the hardware implementation are presented. 5.1 Phase E r r o r Statistics To obtain v a l i d phase error statistics, i t is necessary to identify the two types of error components encountered dur ing the t racking process. The first error component is phase error j i t ter due to channel noise or modulation distortion. The second error component is the Cycle Slip which is a phase jump by mult iples of 2ir/M. Cycle slips are due to either excessive levels of noise or channel interruptions, both of which typically cause catastrophic failure. A s a result of these two error components, the phase error process i n the M D T L undergoes diffusion and its variance becomes infinite i n the steady-state. A n i l lus t ra t ion of a Probability Density Function (PDF) for an unbounded phase error process is shown i n Figure 5.1. Pl<P j M = l -An -2TC 271 An Figure 5.1: PDF of an Unbounded Phase Error Process. To overcome the problem of an unbounded P D F , the phase error process is reduced by applying the / [•] operator given by E q . (3.23). This modulo 2ir reduction results i n a phase error process which is stationary and possesses a bounded variance. Reducing the phase error modulo 2n is 65 Chapter 5: Performance Evaluation analogous to reading the phase error process off a phase meter. The net effect is a phase error process which undergoes diffusion over a bounded closed interval . The amount of phase error j i t ter determines the accuracy i n which the recovered signal is formed. In carrier recovery, the reduced phase error process is typically characterized by its first and second moments [711. A n example on the application of moments is i n the calculation of the probabil i ty of bi t error for a suppressed-carrier B P S K signal. I f the phase error varies rapidly over the symbol interval , the average bi t error probability Pe, can be approximated by applying [2] i e r f c (cos ip) (5.1) where erfc [•] is the complementary error function. Consequently, imperfect synchronization in this case causes an S N R degradation of (cosy) 2 . In the results that follow, the mean value and the standard deviation of the reduced phase error process are measured. 5.1.1 Defining the Test Procedure The test procedure consists of obtaining an exact value of the reduced phase error and calculating its first two moments. The sampling process from the loop under test is used to sample undistorted inphase and quadrature signals from the reference circuit. The sampled references signals can be expressed as xrefk = y/2Pcsm 2-nk (5.2) yrefk 'IP,, cos 2irk A The reduced phase error is extracted by passing xrefk and yrefk to a tan" 1 operator followed by a modulo operator to eliminate the effects of mult i-sampling. Hence f[fk] = f tan" xrefk . yrefk 2TI-A: A (5.3) A s mentioned i n Chapter Three, an M - f o l d ambiguity exists whenever the carrier is to be recovered directly from modulation. Examples of the phase error ambiguity while t racking a 66 Chapter 5: Performance Evaluation B P S K signal is shown i n Figure 5.2. This figure was obtained by applying E q . (A.27) i n Appendix A.3 and serves only as an i l lustrat ive example. 0.8 I i i i I i i i I i i i I i i i I i i i I i i i I i i i I i i i r—, 0.7 -7t -371/4 -71/2 -7C/4 0 7C/4 Tt/2 371/4 71 f[%] Figure 5.2: Sample PDFs of the Reduced Phase Error for a BPSK Signal. The P D F s of / [<pk] show that the loop can track, w i th equal probability, to either the incoming signal wi th a zero phase offset or a phase offset of ±TT. Several techniques exist to eliminate this ambiguity, inc luding differential encoding techniques. Note, however, that the P D F s i n Figure 5.2 are periodic wi th a period of 2x/M and can be reduced to eliminate the M - f o l d ambiguity. Hence, the reduced phase error sample qk, can be expressed as qk= + + m o d u l ol} (5'4) where qk lies wi th in the interval [-JJ, JY)- The value qk is passed to a statistical routine which creates a histogram of the reduced phase error process. Once a l l the data is received, the sample mean q, and standard deviation aq, are calculated, respectively, from 1 N « = NJ2V (5-5) 67 Chapter 5: Performance Evaluation and N N 9 ) • (5.6) 5.1.2 Phase Error Results The P D F s of the reduced phase error qk obtained by the software simulation are shown i n Figure 5.3. For each phase error measurement, a total of 2 x 10 5 samples have been accumulated i n order to obtained a reasonable estimate of the sample mean and standard deviation of qk. In Figure 5.3 (a), both A and B have been set to one; i n Figure 5.3 (b), A is set to eight times oversampling and B is set to four. Note that i n both cases, the P D F s of qk for a given S N R are roughly equivalent which indicates that the degradation i n bi t error rates due to the phase offset of the recovered carrier would be roughly the same i n both cases. The advantages of oversampling, however, are the increased number of samples for data extraction and a faster acquisition time which w i l l be shown i n § 5.2. o a 6 _o § 5 fa a >, 3 o E„INo=10dB ,B =4 - l _L -it/2 -3TC/8 -ic/4 -7C/8 7C/4 3*8 Jt/2 (a) -Ji/2 Figure 5.3: PDFs of the Reduced Phase Error qk Obtained from the Software Simulation. 68 Chapter 5: Performance Evaluation The standard deviation aq of the reduced phase error process is shown i n Table 5.1. Results have been tabulated for input S N R s of zero, five, and ten dB and for different values of A and B. The case where no channel noise is present, that is Eb/N0 = oo dB, is also given to measure the effects of the modulation distortion which determines the upper bound on the performance of the loop. For each phase error measurement, the resul t ing mean phase error q, was l imited to roughly ± 3 ° , that is |g| < 0.05 rad (5.7) B = 1 B = 4 SNR (dB) A = l A = 2 A = 4 A = 8 0 0.276018 0.326127 0.180351 0.248730 5 0.138774 0.167653 0.113793 0.149561 10 0.075010 0.100710 0.069710 0.089343 infinite 0.015670 0.024599 0.016828 0.037347 Table 5.1: Standard Deviation <rq (in Radians) of the Reduced Phase Error Process as a Function of A, B and Eb/N0. For a l l cases i n Table 5.1, increasing Eb/N0 decreases o-q. Note, however, that increasing A while keeping B constant results i n a slight increase i n aq whi le increasing the loop gain B decreases aq. The increase i n aq, as a result of mult i -sampling, is due to the bandlimited inphase and quadrature arms which causes the phase error samples to become increasingly correlated. Consequently, the amount of useful information available to the loop is reduced. Increasing the bandwidth of the inphase and quadrature arms would reduce the amount of correlation between samples but would increase the amount of noise from the channel. These two conflicting requirements suggests that there exists an optimum bandwidth for a part icular S N R and values of A and B for which aq is minimized. The amount of available bandwidth and constraints which are imposed on the real-time processing of the M D T L , ul t imately l i m i t the amount of mult i -sampling, and provide a practical upper l imi t for A. 69 Chapter 5: Performance Evaluation It is interest ing to compare crq at zero dB for both A = B = 1 (Kim's D T L [14]) wi th the case A = 8, 5 = 4. Our M D T L has a smaller standard deviation than Kim ' s and is able to extract eight times as many samples. A s the S N R increases, our M D T L has a comparable yet bigger standard deviation than K i m ' s D T L which suggests that mul t i -sampling performs better for A W G N than for modulation distortion. The Probability Mass Functions (PMF)s of the reduced phase error qk obtained by the hardware implementation are shown i n Figure 5.4. Fo r each phase error measurement, a total of 1 x 107 samples were accumulated into a 128-bin histogram. The plots shown are for the case A = B = 1. In Figure 5.4 (a) four bits of sampler quantization and an N C O resolution of 256 levels were used. In Figures 5.4 (b) and (c), eight bits of sampler quantization and an N C O resolution of 1024 levels were used. 7 -6 -5 j-4 -3 F-2 0.2 0.175 0.15 0.12S § 0.075 0.05 0.025 0 (a) TTT TTT l|IM|IM|lll|.IL EbINo=0dB _ : -E : ; : : r E : : E I I J I -U_L z 0.2 0.175 0.15 # 0.125 ? 0.075 0.05 0.025 0 TTT TTT TTT T T T j n i | II 1 | 1 ITJTTT EbIN0=5dB -E E -: E : E : ; E E X U . II, I L L (b) 0.2 0.175 0.15 # 0.125 § 0.075 0.05 0.025 (c) TT TT TT 1 II | II 1 | 1 II | II 1 | 1 1 L EbINa=10dB ~ I -: ; : : : 1 : E E E : - i 11 -UJ. J- In I M J_L -nlA 0 it/4 TI/2 Figure 5.4: PMFs of the Reduced Phase Error qk Obtained from the Hardware Implementation. A scale of the P D F shown i n Figure 5.3 is placed alongside the scale of the P M F . The scaling factor needed to convert the P M F to a P D F is the inverse of the wid th of the b in , that is 128/TT, which is approximately 40. Al though the P M F s i n Figure 5.4 resemble those found i n Figure 5.3 (a), two features dist inguish the hardware results from software results. The first feature is the mean phase error which deviates from zero as the S N R decreases or as sampler quantization becomes coarser. The deviation from the mean phase error suggests that a first-order loop filter is needed even i f frequency detuning is absent. The second feature is increased variance between adjacent phase error samples, which seems to indicate that the loop favors certain phase error 70 Chapter 5: Performance Evaluation values more than others. It is unclear at the moment i f this second feature poses any loop performance problems. The standard deviation of the reduced phase error process was measured for various sampling, quantization and N C O resolution values. The results are shown i n Figure 5.5. In a l l four cases, the horizontal l ine above zero indicates the standard deviation obtained from the software simulat ion. Two sources of error were thought to contribute into the increased standard deviation of the reduced phase error i n the hardware implementation. These error sources are truncation and phase error j i t ter introduced by non-orthogonal inphase and quadrature arms. In Figure 5.5 (a), for a part icular N C O resolution, there is no appreciable difference i n aq when either four, six, or eight bits of quantization is used. Decreasing the N C O resolution increases crq dramatically, which suggests that aq is more sensitive to changes i n the N C O resolution. Note that <rq is near zero when the number of sampling bits is two and the N C O resolution is set to 1024 levels. Th is interesting phenomenon can be explained i f we consider the source of impairment which, i n this case is simply modulation distortion. The coarse quantization ignores the discrepancies introduced by the modulation distortion and thus, the sampl ing interval , which has a h igh resolution, remains constant. The results i n Figure 5.5 (b), are s imi lar to those i n Figure 5.5 (a) except that the hardware implementat ion was not able to achieve the same level of aq than the software simulation. The reason for this anomaly is believed to be the l imitat ions of the digital loop filter and the phase j i t ter introduced by the mult i-sampling. The digital loop filter truncates the error samples and hence introduces a nonlinearity. In addition, i t is shown i n Appendix C.2 that the inphase arm lags its true position by approximately 9.5° and consequently, an error is introduced i n the estimation of the phase error. The increase i n aq due to these two sources of impairment , prevented the loop from achieving lock at S N R values of zero and five dB wi th A = 8, B = 4. The problem can be solved by us ing a better filter design which eliminates truncation and by assuring true orthogonal inphase and quadrature arms. Figure 5.5 (c) shows the case where A = B — 1 at Eb/NQ = 0 d B . The horizontal l ine at crq = 0.907 is the standard deviation of a uniformly distributed phase error distribution which indicates the loop's inabi l i ty to achieve lock and can be seen when two bits of sampler quantization 71 Chapter 5: Performance Evaluation 0.2 •-^ 0.15 --B .2 '•3 0.1 --0.05 --(« 0.6 --•o 0.2 --0.15 --0 '•5 a OS 0.1 •--••B~. 0.05 •-e R = Q -+ 4-2 4 6 8 Sampler Quantization (Bits) (a) NCO Resolution N = 16 N = 64 M = 256 N = 1024 0.6 •-c« 0.6 •-C 2 '•3 a « b 0.2 --2 4 6 8 Sampler Quantization (Bits) (c) Q - _ ^ Eb/N0 = oo dB A = 8,B=4 V- -O Q O- _ -e---f-2 4 6 8 Sampler Quantization (Bits) (b) Eb/No=0dB A = 2,B = 1 -4-2 4 6 Sampler Quantization (Bits) (d) Figure 5.5: Standard Deviation aq as a Function of the Number of Sampler Quantization Bits and the NCO Resolution. were used. The measured results which yie ld the lowest aq occur when four bits of sampler quantization along wi th an N C O resolution of 64 levels are used. It should be noted that in 72 Chapter 5: Performance Evaluation some cases the measured standard deviation was lower than the results obtained i n the software simulat ion. Th i s is due to the measurement of the S N R whose accuracy is l imi ted to ± 1 dB. In Figure 5.5 (d), increasing A from one to two provides s imilar results as those found i n Figure 5.5 (c) wi th the exception of an increase i n the m i n i m u m standard deviation obtainable. This again may be due to the phase j i t ter introduced by the non-orthogonality between the inphase and quadrature arms. 5.2 Acquisition Statistics A closed-form expression for the acquisition t ime was developed i n Chapter Three. The acquisition time was derived from the phase error difference equation i n the absence of any phase error disturbance. In the presence of noise, the acquisition time becomes a random variable and at present, no known theory exists to predict its behaviour. For any acquisit ion t r ia l , one of three events occur. The first event results when lock conditions are not met and loop never locks. The second event is when the loop false locks, which results i n the phase detector output becoming periodic for a l l t ime. The th i rd event is when lock conditions are met after some time interval . The statistical properties of the th i rd event are investigated i n this section. In the results that follow, the Cumulative Density Function (CDF) of acquisition t ime for a part icular loop configuration is used to characterize the behaviour of the loop i n the acquisition mode. F r o m this distr ibution, the mean time to acquire lock and its standard deviation can be calculated. In current engineering practice, the time required to obtain lock wi th an acquisition probabili ty of 0.9, for example, is used as a specification of loop performance. This information can also be acquired from the C D F . In addition to the results from software simulation and hardware implementation, results from the closed-form expression for the acquisition time are presented. Our purpose is to verify the val id i ty of the closed-form expression wi th the results obtained from the software simulation and hardware implementation, and to identify the effects of modulation distortion on acquisition time. 73 Chapter 5: Performance Evaluation 5.2.1 Defining the Test Procedure The test procedure consists of start ing the execution of the loop at some random time and obtaining the acquisition time for that part icular t r ia l . The test is repeated un t i l a sufficient number of acquisition trials have been accumulated. A s denned i n Chapter Three, the acquisition process is terminated at the fcth sampling instant when where <pss is the steady-state mean phase error and ipc is the acquisition l imi t . The instantaneous phase disturbance 6 ( t ) is simply a phase offset which is uniformly distributed between [—ic, ic). Frequency detuning is not present since the incoming 115.2 k H z carrier frequency is mixed down precisely to 19.2 k H z and consequently, f s , equals zero. The reduced phase error i p k is obtained using equations (5.2) and (5.3) and is further reduced due to the M-fo ld ambiguity us ing E q . (5.4). Hence, the acquisition process is terminated at the fcth sampling instant i f where the acquisit ion l imi t (pc is set to 7r / 3 2 M which corresponds to an acquisition l i m i t of approximately ± 3 ° . The following algori thm was used to perform the acquisition test. The loop under test and the test procedure were grouped into one executable block. The inputs to the block are the inphase and quadrature samples from the A F E under test and the inphase and quadrature samples from the reference circuit. The outputs of the block are the sampling interval and the acquisition time normalized to the mixed-down carrier cycle. \fk ~ fss\ < fe (5.8) l?fc| < f e (5.9) Acquisition Test Algorithm While \ Input (xk,yk) and (xrefk,yrefk) \ True Calculate ek = f [M ( t an" 1 [£*•] - / [2ifc])] Calculate / [ f k ] = / [tan" 1 [ f ^ ] - / [ ¥ ] ' Calculate qk = - £ + {(/ [fk] + & ) modulo £ } 74 Chapter 5: Performance Evaluation If {|«*| < f e } then Output Tjt = T0 + Trand Output Tacq Reset Tacq = 0 Else O u t p u t s = ^ - ^ Update Tacq = Tacq + Note that the generation of the uniformly distributed in i t i a l phase error is created by the test algorithm and not by the input signal whose phase offset remains constant. The random time variable Trand which is uniformly distributed between [0,To) creates the i n i t i a l phase error required for every acquisition t r ia l . F ina l ly , the acquisition time Tacq is passed onto a statistical routine which calculates the mean acquisition time Tacq, and the standard deviation aacq. The equations which generate Tacq, and aacq are similar to those used for the phase error statistics. 5.2.2 Acquisition Results The C D F s for the normalized acquisition time Tacq obtained by the software s imulat ion are shown i n Figure 5.6. A total of 1 x 105 acquisition trials were accumulated for every C D F plot. Each graph corresponds to a part icular S N R , where A is set to one, two, or eight times oversampling. In Figure 5.6 (a), the mean time Tacq to acquire lock is 94.7 mixed-down carrier cycles when A = 1. When A = 2, the mean time is roughly halved. Increasing A to eight decreases Tacq by approximately a factor of eight. The standard deviation aacq undergoes the same reduction and is always sl ight ly less than the mean time. The same decrease i n Tacq and aacq appears in Figure 5.6 (b), (c) and (d). Furthermore, as the S N R increases, Tacg decreases except when no channel noise is present (see Figure 5.6 (d)). This exception w i l l be discussed i n greater detail at the end of this section. It should be noted that increasing A while keeping B constant increases aq. As an example, at zero dB, increasing A from one to two introduces a slight increase i n aq as seen i n Table 5.1. 75 Chapter 5: Performance Evaluation 0.125 \ EbINo = 0dB -A = 1,B = 1 Gacq = 78.3 A=2,B = 1 Tacq = 46.2 Gacq = 39.4 A = 8,B = 1 Gacq = 10.1 0.125 1 1 1 1 1 ' 1 ' 1 50 . 100 150 200 250 300 350 400 (a) 25 50 75 100 125 150 175 200 (b) 0 20 40 60 80 100 120 140 160 0 50 100 150 200 250 300 350 400 (c) (d) Figure 5.6: Cumulative Distributions of the Acquisition Time Obtained from the Software Simulation for Different SNRs and Values of A. When A = 8, o-q increases to 0.5912 which is more than double the aq value when A = 1. The increase i n aq is unacceptable and hence adjustment of the loop gain control B is necessary to keep aq at an acceptable level. To complete the example, setting 5 = 4 w i th A = 8 decreases aq (see Table 5.1) while Tacq = 49.7 and aacq — 39.5. Hence, wi th appropriate values for A and B, the M D T L can reduce the phase error j i t ter and decrease the acquisition time. Low acquisition time and low phase error tend to be conflicting requirements. A s a first approximation, the mean 76 Chapter 5: Performance Evaluation t ime required to acquire lock when using mul t i -sampling wi th respect to the mean time without mul t i -sampl ing can be expressed as 1 £ Tacq & Tacq ("'«'> A=B=i) (5.10) The C D F s of the acquisition t ime obtained by the hardware implementat ion are shown i n Figure 5.7. The dashed curves represent the case where eight bits of sampler quantization and an N C O resolution of 1024 levels are used. The dotted curves represent the case where four bits of sampler quantization and an N C O resolution of 64 levels are used. For each hardware plot, a total of 1 x 105 acquisition tr ials were measured. The solid curves represent the results obtained by the software s imulat ion and are used as a reference for the hardware results. In Figure 5.7 (a), where Et,/N0 = 0 dB and A = 1, the hardware plot for eight sampling bits is comparable to the results obtained by the software simulation and the difference can be considered to be negligible. When using four sampling bits, however, an increase i n the acquisition t ime is observed. This increase is the result of an N C O resolution which may be to smal l for the acquisition l i m i t specified. A s imilar affect occurs i n Figure 5.7 (b), (c) and (d). Note that i n Figure 5.7 (c) and (d), the hardware results seem to be better than the software results. The slight discrepancy is thought to be due to the inaccuracy of the S N R measurement. A comparison between the closed-form expression for the acquisition time derived i n Chapter Three and the results obtained from both the software simulation and the hardware implemen-tation for the case where no channel noise is present is shown i n Figure 5.8. In Figure 5.8 (a), w i th A = 1, we see that a l l three graphs agree very closely un t i l nk reaches roughly 45 cycles. A t that point, both the hardware and software results diverge from the theoretical result. This divergence is due to the modulation distortion which is s t i l l present in the loop and which causes hang-up. Hang-up is defined as the phenomenon whereby the phase dwells near the unstable lockpoint of the phase detector characteristic for an extended period of time. Clear ly , hang-up is worst when ip0 = ir/2. A n interesting discussion on the phenomenon of hang-up for a sawtooth phase detector can be found i n [721. The hardware plot i n Figure 5.8 (a) is sl ightly better than the software s imulat ion whereas i n Figure 5.8 (b), hang-up is almost completely eliminated i n the hardware result. It is suspected 77 Chapter 5: Performance Evaluation 1 0.875 0.75 v/ a 6 2 5 ^ 0 , 5 *0 0.375 0.25 0.125 I I I 1 1 1 I i i i i i 1 1 1 1 1 1 - ^ .«••*" - /( - // 64 NCO levels _ : A •/* Tala = 128.0 Cacq = 124.0 - / - -SbUAID - 1014 NCO levels -7 ^ = 99.1 Cacq = 83.5 -J -n -~- / EbINo=0dB A = 1,B = 1 Software Talq=94.7 Cacq = 78.3 1 1 1 i i i i i i 1 1 1 I i I 1 1 1 1 1 1 350 400 (a) 1 0.875 0.75 0.625 V/ 5" O 0.375 0.25 0.125 0 I I I 1 1 1 I I I M L 1 1 1 - : -- i / 64 NCO leveh -/ / TaZ, = 57.3 Cacq = 55.6 -- is _ - --- SbUAID -/• 1024 NCO level! -/• Tacq = 46.3 Cacq = 42.0 -M - / -- i --I EbIN„=0dB A = 2 , B = 1 Software Taa, = 46.2 Cacq = 39.4 : _ 1 1 1 I 1 1 i i i I 1 1 i I I I I I 1 I I 40 80 120 160 (b) 0.875 0.75 C 0.625 V/ 5" * 1 O 0.375 0.25 0.125 I I I ' M l i i i n i l ........... ..(•H" 1 -- // // -- lb' 64 NCO level! _ : it Tacq = 62.8 Cacq = 60.7 - it - -SbUA/D -f 1024 NCO level! _ : j Ta~cq = 49.7 Cacq - 34.6 -$ _ 3/ --E„/N0=5dB A = 1,B = 1 Software 7^ = 52.0 Cacq = 34.0 --, , , i i i 1 • • i i i ' ' ' 1 1 1 1 I I 40 80 120 160 200 240 280 320 ( C ) 0.875 0.75 0.625 V/ a* O 0.375 0.25 0.125 0 I I I M I 7J..X1.^ 1 1 1 1 1 1 1 - / . it : i f 4 bit AID -- il 64 NCO level! -: i-i iff Talq = 25.4 Cacq = 21.9 -- ¥/ f -7 SbUAID -1024 NCO level! -: k Talq = 22.0 Cacq = 15.3 -- * - V " V --- */ E„/N0=5dB A = 2 , B = 1 Software Tacq ' 25.4 Cacq =17.1 _ 1 ' • • 1 1 • 1 1 1 ' 1 1 1 ' 1 1 1 20 40 60 80 100 120 140 160 (d) Figure 5.7: Cumulative Distributions of the Acquisition Time Obtained from the Hardware Implementation for Different SNRs and Values of A. that the increased phase ji t ter introduced by the mult i -sampling eliminates hang-up. In addition, i t seems that hang-up is most severe when no channel noise is present. It is unclear at the moment why channel noise helps to eliminate hang-up. 78 Chapter 5: Performance Evaluation 0.875 0.75 1—1 0.625 V/ 0.5 JO o 0.375 £ 0.25 0.125 I I I • i; i i i i i * 1 1 M l -' St // Theoretical Ta~cq = 39.2 Gacq =11-9 'A : 'I '• '/ \ij i i Hardware Tacq = 57.7 Gacq = 47.2 I i i / E„/N0= oodB A = 1.B = 1 Software 7^=69.4 Gacq — 68.8 _ i i i i i i 1 I I 1 1 1 1 1 1 \ 1 1 1 1 1 1 _ i _ L 40 80 120 160 200 240 280 320 (a) 1 0.875 0.75 0.625 V/ 8" f £ 0.5 *0 0.375 0.25 I I I rr •i >i i i i i I I 1 1 1 1 1 1 : ii :l ? t _ Theoretical fa7q= 19.6 Gacq = 5.95 '- 1 / \ 1/ 1 1 Hardware Ta7q = 20.6 Gacq = 7.72 ~-: I 1 1 B EblN0=oodB A = 2,B = 1 Software Talq = 28.4 Gacq =19.9 i i i i i i 1 I I i i i i i i i i i I I I 20 40 60 80 100 120 140 160 (b) Figure 5.8: Cumulative Distributions of the Acquisition Time in the Absence of AWGN. 5.3 Hold-In Statistics As mentioned i n § 5.1, excessive levels of noise or channel interruptions causes synchronization failures at randoms points in time, which forces the synchronization loop to cycle slip. In physical terms, & Cycle Slip occurs when the N C O eithers adds or drops a sampling pulse relative to the nominal number of sampling instants i n the incoming signal. Hold-In t ime is defined as the interval of time from acquisition to when the first cycle slip occurs. The statistical properties of the hold-in time are investigated below. 5.3.1 Defining the Test Procedure The test procedure consists of recording a number of hold-in times to plot its C D F . The digital loop is assumed in i t i a l ly to be locked onto the phase of the incoming signal, that is tpo = 0. The hold-in time Th0u terminates once the loop crosses a prespecified barrier for the first time. In our case, the prespecified barriers are the unstable nulls which are ±ir/M. In order to measure cycle slips, i t is necessary to understand how a slip occurs at the unstable nu l l . The phase error difference equation given by E q . (3.39) and plotted onto the discrete phase plot i n Figure 5.9, provides a good means of investigating the sl ipping process. 79 Chapter 5: Performance Evaluation lower bound without noise with noise Figure 5.9: Discrete Phase Plane Plot of the MDTL in the Presence of Noise. The solid lines i n Figure 5.9 represent the characteristic curve and the transformation line <Pk+i = <Pk- In the presence of noise, the range of values that (fk+i can have for a part icular value of tpk is denoted by the shaded area. This range can be determined by let t ing the phase error estimate ek equal its max imum and min imum value, that is ek = / [M<pk] + (k = ±ir. S tar t ing at <p0 = 0, Thold terminates once <pk crosses ±ir/M, whose value is denoted by the square box centered about the origin. A magnification of the unstable n u l l reveals that i n the absence of noise, the phase error process w i l l follow the trajectory la id out by the characteristic curve which is seen by the darker phase trajectory. In the presence of noise, the lighter phase trajectory i l lustrates an example of ipk crossing the boundary. Unfortunately, <pk is not available for measurement purposes. A t our disposal, however, is the reduced phase error sample qk which, when plotted onto a reduced 80 Chapter 5: Performance Evaluation discrete phase plane plot, indicates a method i n which the hold-in t ime can be measured. The reduced discrete phase plane plot of the M D T L i n the presence of noise is shown i n Figure 5.10. Figure 5.10: Reduced Discrete Phase Plane Plot of the MDTL in the Presence of Noise. In the case where the loop has not slipped, the difference between the consecutive reduced phase error samples is . . K' it Iff* — < — g ~ (5.1D where K' = K — 1/32 since frequency detuning is not present. When a slip occurs, however, the difference between consecutive reduced phase error samples is greater than (5.11) which is indicated by the arrows i n Figure 5.10. In the hardware implementation, E q . (5.11) may not necessarily be va l id since Figure 5.10 represents the case of infinite quantization. The ratio K'ir/B, however, is never greater than the half-width of the square box, that is w/M. Hence, for the hold-in tests which were performed, the loop has slipped i f and only i f 81 Chapter 5: Performance Evaluation (5.12) The following algori thm was used to perform the hold-in test. The loop under test and the test procedure were grouped into one executable block. The inputs to the block are the inphase and quadrature samples from the A F E under test and the inphase and quadrature samples from the reference circuit. The outputs of the block are the sampling interval and the hold-in time normalized to the mixed-down carrier cycle. Hold-In Test Algorithm Output Thold Reset Thoid = 0 • Set Flag = Acquire Else Update Thold = Thold + a . Calculate ek = f [M (tan'1 [j*] - / [2ai])] Calculate / [9K] = / [tan"1 [ f£f£] - / [ ^ ] ] Calculate q k = + {(/[<pk] + j j ) modulo^} O u t p u t s = Update Thoid = Thoid + % Set Flag = Hold Else 82 Chapter 5: Performance Evaluation 5.3.2 H o l d - I n R e s u l t s Due to the length of t ime required to obtain meaningful results for the hold-in tests, approximately 7500 hours for 1000 trials at zero dB , software results were not obtained. Furthermore, the complexity of the hold-in algorithm l imi ted the hold-in test i n the hardware implementation to the case where A = 1. Figure 5.11 shows the cumulative distr ibution for the hold-in time obtained from the hardware implementation for the case, Ef,/N0 = 0 dB and A = B = 1. Both the mean hold-in time Thoid and the standard deviation Ohou are roughly equal to 3.1 x 105 mixed-down carrier cycles. 103 104 105 106 107 »* Figure 5.11: Cumulative Distribution of the Hold-In Time Obtained from the Hardware Implementation for Eb/N0 = 0 dB and A = B = 1. W h e n four bits of sampler quantization and an N C O resolution of 64 levels are used, the ratio between the mean hold-in time and the mean acquisition time is approximately Th~o7d/TaTq w 2500 (5.13) 83 Chapter 5: Performance Evaluation which roughly states that, on average, for every bi t used i n a block for acquisition, 2500 bits may be sent without a cycle slip occurring. O f course, i n engineering practice, more restrictive specifications are used. Consider for example, a random access protocol where a block or groups of bits, is passed through the channel, at random points i n time. When a block is sent, the time required to obtain lock wi th an acquisition probabili ty of 0.9 may be used. As a further specification, a probabili ty of a cycle slip occurring wi th in the block must be less than 0.02. These specifications and others l imi t the size of the block. It should be noted that these specifications are applicable to systems where acquisition times and block length are important parameters. Such is the case in random access protocols. In other systems where acquisition times are less important, the synchronization loop is usually set to have a very narrow bandwidth and a relatively long acquisition time. Once acquisition is complete, the length of t ime between cycle slips is extremely long. 84 Chapter 6 Conclusions 6.1 Summary of Research Results This thesis has documented the analysis, design and testing of the M D T L for t racking suppressed-carrier M - a r y P S K signals. Higher levels of synchronization i n a communication system, such as word or frame synchronization, lend themselves easily to digital implementation. Carr ier syn-chronization, however, has yet to fully exploit the many benefits of digi tal technology, pr imar i ly due to the awkwardness of implementation and lack of knowledge as to what the system pa-rameters should be. This thesis has characterized the M D T L which was chosen because of its superior performance over conventional D P L L s and because of its potential simplici ty i n hard-ware implementation. Since the early 1960's, digital techniques have been applied to carrier t racking loops to eliminate the shortcomings of analog circuit elements. The benefits of digital technology are rel iabi l i ty , since circuit element performance does not degrade over time, and flexibility. In spite of these advantages, D P L L s have only recently been considered as a viable alternative to conventional analog P L L s , p r imar i ly because of the l imitations i n speed of the digital circuit elements themselves. Today, because of the enhanced processing speeds of newer technologies, i t possible to design a carrier t racking loop for data rates above 100 kbps. The M D T L is an extension of K im ' s D T L for suppressed-carrier recovery, w i th the benefits of mult i -sampling. Based on a non-uniform sampling mechanism and a tan" 1 operator, the M D T L has a phase characteristic which is piecewise linear, unl ike the conventional D P L L whose phase characteristic is sinusoidal. Consequently, the M D T L can be characterized by a l inear difference equation which eliminates the approximations of nonlineari ty seen i n the conventional D P L L . The l inear difference equation also provides many attractive features over the conventional D P L L . These include locking conditions which are insensitive to variations i n signal power, enhanced 85 Chapter 6: Conclusions noise immuni ty , wider lock range and reduced steady-state mean phase error for the first order loop when the received signal has a frequency offset. In the absence of noise, closed-form expressions of the steady-state mean phase error, the region of stability, the lock range and the acquisition t ime were derived for a first-order M D T L It is shown that the use of mult i -sampling improves the performance of the M D T L over the conventional D T L by increasing the region of stability and consequently, the lock range, and by decreasing the steady-state mean phase error and the acquisition time. In order to test the performance of the M D T L i n the presence of noise, both a software testbed and a hardware testbed have been designed and implemented. The software testbed represents the reference model against which the hardware testbed can be compared and measured. The hardware testbed includes other important impairments such as quantization effects and loop delay and represents an implementation which accurately reflects the performance degradation from the reference model. The phase error, acquisition time and hold-in time are the three performance measures used to characterize the performance of the M D T L i n the presence of noise. For each measure, a well-defined test procedure is derived. The software results reveal that at zero dB, the M D T L has a smaller phase error standard deviation than Kim ' s D T L and is able to extract eight times as many samples. As the S N R increases, the M D T L has a comparable yet larger phase error standard deviation than Kim's D T L , which suggests that mul t i -sampling performs better for A W G N than for modulation distortion. Furthermore, the mean acquisition time of the M D T L is roughly one ha l f that of Kim 's D T L . As a first approximation, the decrease i n the mean time required to acquire lock wi th mult i -sampling wi th respect to the mean time without mult i -sampling is approximately a factor of B/A. The results obtained by the hardware implementation reveal that for B P S K , four bits of sam-pler quantization and 64 levels of N C O resolution are needed to provide negligible performance degradation compared to the infinite quantization case at a received S N R of zero dB. Two sources of error were thought to contribute to the increased standard deviation of the reduced phase error i n the hardware implementation. These error sources are truncation of the phase error samples i n the digi tal loop filter and phase error j i t ter introduced by non-orthogonal inphase and quadrature arms. Both these error sources can be minimized by an enhanced hardware design. 86 Chapter 6: Conclusions The MDTL design is simple. Digital implementation of the MDTL provides an opportunity for enhanced system integration using VLSI-ASIC techniques for high speed applications or DSP microprocessor techniques for slower speed applications. 6.2 Suggestions for Future Work The many attractive features which the MDTL possesses make it an ideal candidate for carrier recovery. Further research, however, is needed to exploit fully the possibilities of this system. The following is a list of suggestions for future work on the MDTL. The areas of research which, in the author's opinion, show the most promise are placed at the top of the list. • Design of the Data Extractor — Several forms of data extraction can be applied to the MDTL. Data can be extracted from the inphase arm or from the output of the tan'1 operator. Due to the addition of data extraction, the bandwidths of the bandpass filters have to be adjusted accordingly, and Simon has suggested a method for optimizing these filter bandwidths [73]. • Analysis of Higher-Order Loops — The analysis of higher-order loops, particularly the second-order MDTL, should be investigated to determine its performance when the input signal has a constant or variable frequency offset. Chie, for example, analyzed a second-order DPLL for Doppler rate tracking [74]. In addition, the use of nonlinear loop filters when coarse sampler quantization is used should be investigated. • VLSI Implementation — An interesting area of research is the digital implementation of carrier recovery loops for large scale integration. The problems typically associated with this area of research are the integration of analog and digital circuit elements, process technology, fault tolerance and detection and finally, design for manufacturability. The alternative to VLSI design is the implementation of the MDTL using commercially available microprocessors. Typically, the designer develops suitable carrier tracking algorithms which must meet real-time requirements. • Frequency Discriminators — It may be possible to design frequency/phase detectors that do not suffer from the problem of phase ambiguity. Messerschmitt has applied frequency detectors for PLL acquisition and has obtained good results [75]. 87 Chapter 6: Conclusions • Sub-Optimum Loops — The work on sub-optimum loop design is best applicable when cost constraints are added to system specifications. For example, i t is possible to design a sub-optimum M D T L for t racking suppressed-carrier signals which is based on one A D C sampling four times per mixed-down carrier cycle. • Semi-Numerical Analysis — The solution to the Chapman-Kolgomorov equation for the P D F of the phase error process has l imitat ions as to its applicabili ty. These l imitat ions are due to the increased correlation between noise samples as the sampl ing rate is increased. It may be necessary to develop alternative numerical or semi-numerical methods to determine the effects of correlated noise samples. 88 References [I] J. J. Stiffler, Theory of Synchronous Communications. New Jersey: Prentice-Hall, 1971. [2] W. C. Lindsey and M. K Simon, Telecommunication Systems Engineering. New Jersey: Prentice-Hall, 1973. [3] L. E. Franks, "Carrier and bit synchronization in data communications - A tutorial review," IEEE Trans. Commun., vol. COM-28, pp. 1107-1121, Aug. 1980. [4] J. K Holmes, Coherent Spread Spectrum Systems, pp. 179-184. New York: Wiley, 1982. [5] A. J. Viterbi, Principles of Coherent Communications. New-York: McGraw-Hill, 1966. [6] J. P. Costas, "Synchronous communications," Proc. of the IRE, vol. 44, pp. 1713-1718, Dec. 1956. [71 S. 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(A.2) Proof: We can write ax — 2irkx + rlt a2 = 2irk2 + r2 where kx,k2 are integers and rx, r2 G [-it, TT). For addition, / [ai + a2] = — 7r + {(ai + a 2 + 7r) modulo 27r} = - T T + { ( ( 2 7 T * ! + n) + (2ir^ 2 + r 2) + TT) modulo 2TT} = —7r + {(n + r2 + TT) modulo 27r} (A.3) = / [ r i + r 2 ] = /[/[«i] + /[a2]] Q.E.D. * The same holds true for subtraction. For mult ipl icat ion, / [ai x a2] — —TT + {(ai x a 2 + 7r) modulo 2n} = — 7T + {((2^^! + ri) x (2-rrk2 + r 2) + TT) modulo 2TT} = — 7r + {(27T (27rfc!fc2 + rifc2 4- r 2 k x ) + n r 2 + it) modulo 27r} = —7r + {(ri x r 2 + 7r) modulo 2T} = / [ri x r2] = /[/[ai]x/[a 2]] Q.E.D. o (A.4) Corollary: Le t ax be a real number, M be an integer and / [p] be denned by E q . ( A . l ) then 94 Appendix A: Mathematical Derivations f [Mai] = / [Mf [ai]] CA.5) Proof: We can write ai = 27r&i + ri, then / [Mai] = f [2irMki + Mn] = f [M ri] (A.6) = f[Mf[ai]] Q.E.D. * A.2 MAP Estimate of an Unknown Phase Angle Let xk and yk be defined, respectively, as xk = Asm(zk) + r]k ( A > 7 ) yk = A cos (zk) + rfk where zk is the uniformly distributed phase angle, p[zk] — l/2-ir zk € [-7r,7r), and Tjk,rfk are independent identically distributed Gaussian noise samples wi th zero mean and variance The probability of a correct decision for the phase angle is maximized i f p[zk\xk,yk] (A.8) is maximized for a given inphase and quadrature sample. F r o m Baye's rule w - i - Pix^yk\zk]p[zk] r A P x p[zk\xk,yk\ = p ? (A.a; and since the logari thm is a monotonically increasing function of its positive argument, maximiz-ing E q . (A.9) is equivalent to maximiz ing \n(p[zk\xk,yk]) = \n(p[xk,yk\zk]) + In (p[zk]) - ln (p [xk, yk]). (A.10) The second term i n E q . (A.10) is a constant since zk is assumed to be uniformly distributed, and the th i rd term is not a function of the phase angle. Consequently, max imiz ing E q . (A.9) w i th respect to zk is equivalent to max imiz ing the first term of E q . (A.10) w i th respect to zk. The joint Probability Density Function (PDF) of xk and yk given zk can be rewri t ten as 95 Appendix A: Mathematical Derivations p[xk,Vk\zk] - Pr, [xk ~ Asin(zk) ,yk - A cos (zk) \zk] (A.11) where pv [•, •] is the joint P D F of the noise samples r)k, rjk- m E q . ( A . l l ) , the dependence on zk can be discarded since the noise samples are assumed to be independent of the phase angle. F rom E q . ( A . l l ) , the joint P D F is given by Pr, [xk - A sin (zk), yk - A cos (zk)} CA.12) Subst i tut ing E q . (A.12) into E q . (A.10), differentiating wi th respect to zk and setting the result to zero, we obtain d dzk 1 (xk - Asm {zk)f + (yk - A cos (zk))2^ = 2 [~xk cos (zk) + yk sin (zk)} 0. (A.13) Solving for zk, we get zk — tan - l xk Vk (A.14) Thus, i t has been showned that the optimum M A P estimate of a uniformly distributed phase angle for a given pair of inphase and quadrature samples corrupted by A W G N is the tan" 1 operator. In addition, the max imum likelihood estimator suggests that the most unbiased estimate of the phase angle when its P D F is unknown is given by the t a n 1 operator. A.3 Statistical Characteristics of the Phase Detector in the Presence of Noise We wish to obtain the P D F of the phase detector output ek i n order to ascertain that the phase detector output can be wri t ten as ejb = / [M<pk] + (k (A.15) 96 Appendix A: Mathematical Derivations where / [Mfk] is the phase error estimate i n the absence of noise and 0t is a non-Gaussian noise process. Given the inphase and quadrature samples yk = \/2pPc os 2irk — + fk + f jb 2irk A + fk+€k + Vk + rfk (A-16) i t is assumed that the modulation distortion is independent of the channel noise. In addition, since Vk and rjk are independent zero mean Gaussian random variables, Xk and yk are also mutual ly independent random variables for a given ffc w i th means E [xk] = ^/2p~Fcsm + <Pk+U (lick E bk] = VZpPc cos ( — + <pk + f* (A.17) and variances var [xk] - var [j/*] = a*. (A.18) If the P D F of ft, p [ik] is known, we can write the joint P D F of Xk, yk and ft as P [Efc, yk, ft] = p [xk, y f c |f fc] p [ft] (A.19) where p[xjt,yjblfjt] may be wri t ten us ing Eqs. (A.17) and (A.18) as P [xk, ykIf fc] = —'--exp 27T(Tf1 1 • ^ ( - ^ - \/2p^sin ^ —r- + fk+£k 2rck + {yk - \/2pPc cos ^ j^p -+- Vfc + f*^ 2\ l (A.20) To determine p[^t] which is the output from the tan" 1 function, we define a new random variable R such that xk = Rs'm(zk), yk = Rcos(zk) (A.21) 97 Appendix A: Mathematical Derivations where zk e [ - T . T T ) and R e [0,oo). The joint P D F p [zk, R,£k] is equal to p[zk,R,£k] = p[xk,yk,tk] • R-Therefore, the P D F of zk can be calculated from Eqs. (A.19) - (A.22) as 7T OO P W = J Jp[zk,R,tk] dR - I T Lo IT a f i ( 27T& x exp ( - a sin2 ( zk - - <pk - £k r— i 2irk V2a cos ( zk — <Pk-£k x ( - + erf where a is the input S N R defined as A pPc and erf (*) i - 7 = /e->'/3dy. v ^ J 0 To obtain the P D F of ek, we perform a transformation of variables us ing e* = / Mf Zk~ f '2-irk1 to give 98 Appendix A: Mathematical Derivations Pe [e*] = — P z Mzk + 2irn + exp (A.27) x exp ( {—a sin2 7) x ( - + erf [\Pla cos 7] j dfk where T = 17 [e* + 2 7 r n ~ MVk ~ Milk]. (A.28) Although ek is considered only i n the in terval [—TT, 7T), the function pe [ek] i tself is periodic i n ek w i t h a period of 2T and has peaks occurring at ek = f [Mtpk] + 2irn for a l l integer values of n. Hence, the phase error estimate consists of a noise-free estimate / [Mipk] and a non-Gaussian noise process £ k which lies i n the interval [—TT — f [Mipk] ,ir — f [Mipk]). The above analysis has assumed that the P D F of fit, p[^k] is known. Unfortunately, i t is difficult know the statistics of ft at non-uniform sampling instants. Numer ica l solutions, however, have been obtained by K i m [13]. 99 Appendix B Topology Files of the Simulated MDTL A n example of the topology files used for the s imulat ion of the M D T L is presented. The universe topology file lists the stars and galaxies needed for the simulation and the parameters passed to the star and galaxy routines. The universe topology file is common to a l l three performance measures. E a c h performance measure is l isted as an indiv idual galaxy file. 100 UNIVERSE TOPOLOGY F I L E Author: Joel A. Bisson I n s t i t u t i o n : University of B r i t i s h Columbia Date: Feb 11th, 1989 Filename: UNIVERSE.T Purpose: To simulate the MDTL imbedded i n AWGN. N.B. UNIVERSE.T used for a l l three performance measures. t Specify t e s t measure (one galaxy for each test) i galaxy MDTL mdtlped.t • Phase error d i s t r i b u t i o n s Jgalaxy MDTL mdtlacq.t # Acquisition d i s t r i b u t i o n s •galaxy MDTL mdtlhold.t * Hold-In d i s t r i b u t i o n s t Specify mixed-down 4th-order bandpass f i l t e r s t param f l o a t 1152000.0 t Sampling frequency param f l o a t 19200.0 t Center frequency param f l o a t 19200.0 * Bandwidth star SinMDFA iir_4 t h b p f .s t Inphase arm (Ci r c u i t Under Test) param f l o a t 1152000.0 t Sampling frequency param f l o a t 19200.0 t Center frequency param f l o a t 19200.0 t Bandwidth star CosMDFA iir_4thbpf .s t Quadrature arm (Circuit Under Test) param f l o a t 1152000.0 t Sampling frequency param f l o a t 19200.0 t Center frequency param f l o a t 19200.0 t Bandwidth star SinMDFB i i r 4thbpf.s t Inphase arm (Reference C i r c u i t ) param f l o a t 1152000.0 t Sampling frequency param f l o a t 19200.0 t Center frequency param f l o a t 19200.0 t Bandwidth star COSMDFB iir_4thbpf.s t Quadrature arm (Reference C i r c u i t ) # Specify m u l t i p l i e r s f star star SinMultA CosMultA multiply.s multiply.s # inphase arm (Ci r c u i t Under Test) # Quadrature arm (Circuit Under Test) star star SinMultB CosMultB multiply.s multiply.s # inphase arm (Reference C i r c u i t ) # Quadrature arm (Reference C i r c u i t ) * f Specify phase s h i f t e r s # * param i n t 3 1/4 of 12 sample cycle star DelayA delay.s * Phase s h i f t element (C.U.T.) param i n t 3 * 1/4 of 12 sample cycle star DelayB delay.s # Phase s h i f t element (Reference) Specify l o c a l o s c i l l a t o r s param i n t 12000000 t Total number of samples generated param i n t 2400 t Output 2400 samples per block c a l l param i n t 12 t 12 samples per period param f l o a t 1.4142 i Peak amplitude of the sinusoid star LocalOscA sin c l k . s t Local O s c i l l a t o r (C.U.T.) param i n t 12000000 t Total number of samples generated param i n t 2400 t Output 2400 samples per block c a l l param i n t 12 t 12 samples per period param f l o a t 1.4142 t Peak amplitude of the sinusoid star LocalOscB s i n c l k . s i Local O s c i l l a t o r (Reference) Speci fy forks star Fork-AO fp_fork.s t From bpf to m u l t i p l i e r s (C.U.T.) star Fork-Al fp_fork.s i From l o c a l o s c i l l a t o r to m u l t i p l i e r s star Fork-BO fp_fork.s t From bpf to m u l t i p l i e r s (Reference] star Fork-Bl fp_fork.s i From l o c a l o s c i l l a t o r to mu l t i p l i e r s Specify bandpass f i l t e r s preceding AFE param f i l e 115.2k.coef t C o e f f i c i e n t s for 115.2 kHz cf, Q = 2 star BPF-A0 iir_biquad.s t 1st cascaded f i l t e r (C.U.T.) param f i l e 115.2k.coef t C o e f f i c i e n t s for 115.2 kHz cf, Q •= 2 star BPF-Al iir_biquad.s t 2nd cascaded f i l t e r (C.U.T.) param f i l e 115.2k.coef t C o e f f i c i e n t s for 115.2 kHz cf, Q = 2 star BPF-B0 iir^biquad.s t 1st cascaded f i l t e r (Reference) param f i l e 115.2k.coef t C o e f f i c i e n t s for 115.2 kHz cf, Q = 2 star BPF-Bl iir_biquad. s t 2nd cascaded f i l t e r (Reference) Specify channel being used param function ranl.c t Random no. generator ('C f i l e ) param fl o a t 5.477225575 t Standard deviation of noise (0 dB) param i n t -4764532 t I n i t i a l seed star ChannelA awgn.s t Channel (C.U.T.) # Specify BPSK modulators f param int 10 param default param default param int 12 star ModulatA pskgen.s param int 10 param default param default param int 12 star ModulatB pskgen.s # Specify pseudo bit sequence t No. of samples per cycle f Infinite quantization t Zero phase offset * No. of cyles per bit i BPSK modulator (C.U.T.) i No. of samples per cycle t Infinite quantization * Zero phase offset * No. of cycles per bit * BPSK modulator (Reference) param i n t 100000 * Total no. of b i t s generated param i n t -4231934 * I n i t i a l seed star SourceA prbs.s t PRBS generator (C.U.T.) t # Specify zero bit sequence param int 100000 t Total no. of bits generated star SourceB zero.s * Zero bit sequence (Reference) • Specify interconnection of blocks for the Circuit Under Test t connect SourceA connect ModulatA connect ChannelA connect BPF-A0 connect BPF-A1 connect Fork-AO connect Fork-AO connect LocalOscA connect Fork-Al connect Fork-Al connect DelayA connect SinMultA connect CosMultA connect SinMDFA connect CosMDFA 0 ModulatA 0 0 ChannelA 0 0 BPF-A0 0 0 BPF-A1 0 0 Fork-AO 0 0 SinMultA 0 1 CosMultA 0 0 Fork-Al 0 0 SinMultA 1 1 DelayA 0 0 CosMultA 1 0 SinMDFA 0 0 COSMDFA 0 0 MDTL 0 0 MDTL 1 t t Specify interconnection of blocks for the Reference C i r c u i t t connect SourceB connect ModulatB connect BPF-BO connect BPF-B1 connect Fork-BO connect Fork-BO 0 ModulatB 0 0 BPF-BO 0 0 BPF-B1 0 0 Fork-BO 0 0 SinMultB 0 1 CosMultB 0 connect LocalOscB 0 Fork-Bl 0 connect Fork-Bl 0 SinMultB 1 connect Fork-Bl 1 DelayB 0 connect DelayB 0 CosMultB 1 connect SinMultB 0 SinMDFB 0 connect CosMultB 0 CosMDFB 0 connect SinMDFB 0 MDTL 2 connect CosMDFB 0 MDTL 3 GALAXY TOPOLOGY F I L E FOR PHASE ERROR TESTS f t Author: Joel A. Bisson t Institution: University of British Columbia t Date: Feb 12th, 1989 t t Filename: MDTLPED.T i t t Purpose To generate phase error distributions and statistics. t t * Specify statist ical routines param float -3.1415926535 * Minimum bound param float +3.1415926535 i Maximum bound param int 255 * No. of bins param int 0 * Hide empty bins = OFF param int 1 t Cumulative distribution = ON param int 0 t Normalized distribution = OFF param default t Output f i le is 'stdout' star Statl fp histogram, s t Histogram routine for phase error param float -3.1415926535 t Minimum bound param float +3.1415926535 t Maximum bound param int 255 t No. of bins param int 0 t Hide empty bins = OFF param int 1 t Cumulative distribution = ON param int 0 t Normalized distribution « OFF param default i Output f i le is 'stdout' star StatO fp histogram, s t Histogram routine for error signal t t t Specify MDTL and Test circuit param int 2 t M = 2, BPSK param int 8 t A = 8, multisampling param int 4 t B = 4, loop gain param float 19200.0 t Mixed-down carrier frequency param float 0.03125 t Normalized digital loop f i l te r coef. t star Test ctpeddtl.s t Star File i Specify samplers t O CO param int 64 t No. of reconstruction samples param float 1152000.0 t Sampling frequency param float 19200.0 t Mixed-down carrier frequency star Samplers fastcts ampler. s t Samplers for (C.U.T.) param int 64 i No. of reconstruction samples param float 1152000.0 t Sampling frequency param float 19200.0 i Mixed-down carrier frequency star SamplerB fastctsampler.s i Samplers for (Reference) Specify fork star Fork fp_fork.s i From Test to samplers Specify the interconnections of the blocks connect input 0 SamplerA 0 connect input 1 SamplerA 1 connect input 2 SamplerB 0 connect input 3 SamplerB 1 connect SamplerA 0 Test 0 connect SamplerA 1 Test 1 connect SamplerB 0 Test 2 connect SamplerB 1 Test 3 connect Test 0 Fork 0 connect Fork 0 SamplerA 2 connect Fork 1 SamplerB 2 connect Test 1 StatO 0 connect Test 2 Statl 0 GALAXY TOPOLOGY F I L E FOR ACQUISITION TESTS * t t t t t f t Purpose: * Author: Institution: Date: Filename: Joel A. Bisson University of British Columbia Feb 20th, 1989 MDTLACQ.T To generate acquisition distributions and statistics. • • Specify statistical routines t param int param int 10000 256 t Total no. of entries # No. of bins param star default Stat acummulate.s * Output f i le is 'stdout' # Cummulative routine for acq. time t Specify MDTL and Test circuit t param int 2 * M = 2, BPSK param int 2 t A = 2, multisampling param int 1 t B = 1, loop gain param float 19200.0 i Mixed-down carrier frequency param float 0.03125 t Normalized digital loop f i l te r coef param int -789324 t Init ia l seed for 'k' count param float 0.04908739 t Acquisition limit (2.8125 degrees) star Test ctacqdtl.s • Star File Specify samplers param int 64 f No. of reconstruction samples param float 1152000.0 t Sampling frequency param float 19200.0 t Mixed-down carrier frequency star SamplerA fastcts ampler. s i Samplers for (C.U.T.) param int 64 t No. of reconstruction samples param float 1152000.0 t Sampling frequency param float 19200.0 t Mixed-down carrier frequency star SamplerB fastctsampler.s t Samplers for (Reference) Specify fork star Fork fp_fork.s t From Test to samplers Specify the interconnections of the blocks connect input 0 SamplerA 0 connect input 1 SamplerA 1 connect input 2 SamplerB 0 connect input 3 SamplerB 1 connect SamplerA 0 Test 0 connect SamplerA 1 Test 1 connect SamplerB 0 Test 2 connect SamplerB 1 Test 3 connect Test 0 Fork 0 connect Fork 0 SamplerA 2 connect Fork 1 SamplerB 2 connect Test 1 Stat 0 GALAXY TOPOLOGY F I L E FOR HOLD-IN TESTS t t Author: Joel A. Bisson t Institution: University of British Columbia * Date: Mar 1st, 1989 * Filename: MDTLHOLD.T # t t Purpose: To generate hold-in distributions and statistics. t t t Specify statistical routines 4 param float 0.0 t Minimum bound param float 1000000.0 t Maximum bound param int 100000 t No. of bins param int 1 t Hide empty bins - ON param int 0 * Cumulative distribution « OFF param int 0 t Normalized distribution = OFF param default t Output file is 'stdout' star StatO fp histogram.s t Histogram routine for hold-in t Specify MDTL and Test circuit t param int 1 t M » 2, CW param int 1 f A - 1, multisampling param int 1 * B = 1, loop gain param float 19200.0 i Mixed-down carrier frequency param float 0.03125 * Normalized digital loop filter coef. param float 0.04908739 t Acquisition limit (2.8125 degrees) star Test ctholddtl.s * Star File t t Specify samplers * param int 64 t No. of reconstruction samples param float 1152000.0 t Sampling frequency param float 19200.0 t Mixed-down carrier frequency star SamplerA fastcts ampler s t Samplers for (C.U.T.) param int 64 t No. of reconstruction samples param float 1152000.0 t Sampling frequency param float 19200.0 t Mixed-down carrier frequency star SamplerB fastctsampler s # Samplers for (Reference) Specify fork star Fork fp_fork.s t From Test to samplers * Specify the interconnections of the blocks t connect connect connect connect connect connect connect connect connect connect connect connect input input input input SamplerA SamplerA SamplerB SamplerB Test Fork Fork Test SamplerA SamplerA SamplerB SamplerB Test Test Test Test 0 Fork 0 SamplerA 1 SamplerB 1 Stat •a S PL to Q 3-ft. I 3 Appendix C Details of the Hardware Design In this appendix, • a functional description of the supporting hardware needed for the test configuration is described; • an evaluation on the functionality of the test configuration is provided; and • schematic diagrams of the hardware design and program listings for the programmable devices are given. C.l Functional Description of the Supporting Hardware The supporting hardware for the MDTL consists of a transmitter, a noise channel, a phase error reference circuit and a data acquisition unit. C.l.l The Transmitter The transmitter generates PSK waveforms subject to different data rates, pulse shapes and digital baseband formats. The purpose of this effort is to provide a flexible transmitter circuit in order to ascertain the functionality of the MDTL. To generate these many signals, the transmitter system is based on a stored-waveform mechanism. Figure C.l shows the block diagram of the transmitter. The transmitted signal is generated by an eight-bit lookup table. The output of the lookup table is passed to a Digital-to-Analog Converter (DAC) whose output signal is amplified and then sent directly to the receiver for testing purposes or to the channel via a BNC connector. The lookup table contains a generalized sine wave function, that is sn = {An)sm{6n) (C.l) 105 Appendix C: Details of the Hardware Design Window Functions Lookup Figure C l : Block Diagram of the Transmitter, where An is a seven-bit value representing the amplitude information and 6n is a seven-bit value representing the phase information. B y vary ing the values of A„ and $„, i t is possible to generate the waveforms needed for testing. To create the desired 115.2 k H z carrier frequency, the local oscillator of the transmitter is 2 7 b l t s = 128 times the carrier frequency or 14.7456 M H z . The phase sequence is created by a programmable P A L counter whose in i t i a l count value, at the beginning of every carrier cycle, is loaded from a digital baseband formatter P A L . The formatter converts the incoming pseudo-random N R Z - L bi t sequence from an external data source to the three most significant bits of the i n i t i a l count value. These three bits divide 2TT into eight uniform sections thus creating the necessary phase information. The lower four bits of the in i t i a l count value determines the phase offset and is selectable v i a D I P switches. Several windowing functions have been stored into a P R O M i n order to generate the amplitude sequence. Th i s amplitude information is indexed v i a an amplitude counter and is passed to the upper seven bits of the sine wave lookup table. A divide-by-N P A L determines the period of the amplitude window which is dependent on the data rate. A t present, the pulse shape mechanism is used for B P S K signal l ing only. Table C l lists the features of the transmitter which are D I P switch selectable. Figure C.16 shows the schematic diagram of the transmitter. 106 Appendix C: Details of the Hardware Design Selectable Formats Modulation CW, BPSK, QPSK, 8-PSK Data Rate 600, 1200, 2400, 4800, 9600, 19200, 28800 bps. Baseband Signalling NRZ-L, NRZ-M, NRZ-S, RZ, Biphase-L, Biphase-M, Biphase-S, Delay Mod Pulse Shaping Rectangular, Bartlett, Hamming, Hanning, Blackman, Kaiser 30db, Kaiser 40db, Kaiser 50db Phase Offset 0 to 45 degrees Table C l : Features Incorporated into the Transmitter. Noise ( Source Filter -o o-Signal + Noise z V—o Xmit Signal Filter © -o T O-Figure C2: Block Diagram of the Noise Channel C.1.2 The Noise Channel The noise channel is used to evaluate the MDTL's performance in a controlled environment. The block diagram of the noise channel designed for the experimental unit is shown in Figure C.2. This circuit consists of an high-power noise source, a noise amplifier and a summing amplifier. The noise source generates white Gaussian noise which is bandlimited from 50 Hz to 500 kHz. The noise source is amplified and summed with the PSK signal. BNC connectors are placed in both the transmitter and noise paths to allow the insertion of commercial filters or sources. For example, the user may wish to use an unfiltered BPSK signal originating from the transmitter along with an external noise source. Figure C.20 shows the schematic diagram of the noise channel. 107 Appendix C: Details of the Hardware Design C.1.3 The Phase Error Reference Circuit The phase error reference circuit consists of a sine wave generator, an A F E , inphase and quadra-ture A D C s and lookup tables for the tan ' 1 function and the phase error detector. The sine wave generator creates an unmodulated sinusoidal signal which is synchronized to the modulated car-r ier signal. The sine wave generator uses the local oscillator from the transmitter to synchronize the sine wave. The reference sine wave is passed to an A F E which is identical to the A F E under test. The local oscillator from the A F E under test is used to mix the reference signal down to the 19.2 k H z . The inphase and quadrature arms are then sampled us ing the t iming information generated from the N C O . A phase detector circuit generates a phase error sample which is passed to the data acquisition unit . C.1.4 The Data Acquisition Unit The data acquisition uni t reads and processes information from the various loop components for performance testing at run-time and reads from and writes to the M D T L for diagnostic testing. The data acquisition uni t consists of two separate units. The first uni t is a general-purpose D S P board based on Intel's T M S 3 2 0 C 2 5 Dig i ta l S ignal Processor and resides i n a personal computer. The second uni t consists of an external adaptor and supporting hardware which is used to connect the M D T L to the personal computer. W i t h this configuration, the user instructs the T M S board to execute routines wri t ten i n assembly code for diagnostic testing or for data capture. The received data is then processed us ing a higher level language, i n our case ' C , to eventually obtain meaningful results. The external hardware needed to interface from the T M S board to the M D T L is shown in Figure C.3. The interface uni t consists of interrupt logic, address decoding logic and read/write ports. A n interrupt signal instructs the T M S board to begin an exception processing routine. The par t icular routine depends on the test being performed. Interrupt logic is used to control which interrupt signal enters the priori t ized interrupts pins. A t present, the control signals from the F S M are used as interrupt signals. E igh t 16-bi t read/write ports are placed throughout the 108 Appendix C: Details of the Hardware Design 78 To PC TMS Adaptor Board DO - D15 A 0 - A 2 RAV IS Address Decode 4 Interrupt Logic Figure C.3: Block Diagram of the TMS Interface. Read Port Write Port Port No. MSB LSB MSB LSB 0 Sine Arm Cosine Arm Sine Arm Cosine Arm 1 True Phase Error Phase Angle - Phase Angle 2 Data Extractor Error Estimate Data Extractor Error Estimate 3 Accumulator Accumulator Barrel Shifter Barrel Shifter 4 Loop Filter Loop Filter NCO NCO 5 - - - -6 - - - -7 Status Register Status Register Control Register Control Register Table C . 2 : TMS Port Assignments. MDTL to access the desired data samples. The port addresses are decoded using the address lines A0-A2, along with the read/write and strobe pins. The port assignments are shown in Table C.2. In addition, a wait state generator provides the necessary delay for the TMS board to properly read from and write to these ports. Figures C.17, C.18 and C.19 shows the schematic diagrams of the TMS interface and the read/write ports. A photograph of the complete hardware test configuration is shown in Figure C.4 109 Appendix C: Details of the Hardware Design Figure C.4: Photograph of the Test Configuration. C.2 Evaluation of the Functionality of the Test Configuration A series of tests were conducted to evaluate the functionality of the hardware implementation. The degradation in the receiver as compared to the theoretical circuit in Figure 3.1 was anticipated to lie within the AFE. This degradation is due to the discrepancies in the analog circuit elements which force the behaviour of the AFE to be less predictable than the digital circuit elements. Hence, the tests which were conducted, evaluate the characteristics of the AFE, the transmitter and the noise channel. The digital loop components of the MDTL were individually tested for functionality using the data acquisition unit and performed well. In order to perform the tests, it is necessary to sample the output signals of the AFE at uniform sampling intervals. Hence, the NCO is configured by the data acquisition unit to sample at a constant rate of 153.6 kHz. The samples from the inphase and quadrature arms were gathered 110 Appendix C: Details of the Hardware Design by the data acquisition unit and routines such as an integer power spectral estimate routine were written in TMS320C25 assembly. Figure C.5 illustrates an example of the sampling process of the inphase and quadrature arm for BPSK signalling. The sampling rate in this case is 307.2 kHz. 0 20 40 60 80 100 120 140 160 180 200 Index (n) Figure C.5: Sampled I and Q Waveforms for BPSK Signalling. The first test consisted of passing white Gaussian noise into the receiver in order to estimate the spectrum of the AFE. The eight-bit noise samples obtained from the inphase and quadrature arms are plotted in Figure C.6 (a). The spectral estimate of the inphase arm which is shown in Figure C.6 (b). All graphs which display spectral estimates were obtained by an integer spectral estimation routine written in TMS320 assembly code. The spectral estimate of the inphase arm is compared to the theoretical frequency response of the bandpass niters placed after the multipliers. In this particular example, the bandpass filters have a Q of 2.0. The spectral estimate closely resembles the theoretical response. The center frequency of the inphase spectral estimate, however, is slightly offset due to the inaccuracies the analog circuit elements. In addition, the attenuation of the spectral estimate at higher frequencies is the result of the bandpass filter placed at the receiver's input. Finally, a non-zero dc component is present in the spectral estimate which is the result of the dc bias circuit placed in the final stage of the bandpass filter. This dc component, however, should have negligible effects on the system since it is attenuated by approximately 40 dB. I l l Appendix C: Details of the Hardware Design 0 64 128 192 256 0 9.6 19.2 28.8 38.4 48 57.6 67.2 fs/2 Quadrature Arm (y[k]) Frequency (kHz) (a) (b) Figure C.7: Unmodulated Sinusoid (a) / versus Q Samples (b) Spectral Estimate of the Sine Arm. The second test measured the orthogonality between the inphase and quadrature arms. A graph of the inphase samples versus quadrature samples for an unmodulated sinusoid is shown in Figure C.7 (a). The spectral estimate of the inphase arm is shown in Figure C.7 (b). 112 Appendix C: Details of the Hardware Design The inphase and quadrature samples should form a circle i f they are orthogonal. Figure C.7 (a) shows, however, that the samples are not completely orthogonal resul t ing i n an ell ipt ical function. The dotted curve i n Figure C.7 (a) represents an estimate of the relationship between the inphase and quadrature samples. It is estimated that the inphase arm lags its true position by approximately 9.5° and that the amplitude ratio between the inphase and quadrature arms is approximately 1.03. This anomaly results from us ing unmatched filters. A commercial uni t would have niters matched to each other. In addition, Figure C.7 (a) shows the effects of c l ipping by the signal level estimators. This cl ipping introduces harmonics into the signal as seen i n Figure C.7 (b). The th i rd harmonic (57.6 k H z ) for example, is roughly 35 dB below the first harmonic. It is difficult to ascertain i f this c l ipping w i l l severely affect the performance of the M D T L . As mentioned i n Chapter Four, the major disadvantage of us ing signal level estimators is the circuit's poor performance for very weak signal levels, e.g 50 m V peak-to-peak. This degradation is due to the l imitat ions of the A D C whose performance degrades as the quantizer step size decreases. Hence, the th i rd test consisted of measuring the performance of the A D C for various signal levels. Figure C.8 shows the relationship between inphase and quadrature samples of an unmodulated mixed-down carrier frequency for various signal levels and the spectral estimates of the inphase arms. In Figure C.8 (d), for an inphase signal level of 4.5 V peak-to-peak, the signal-to-quantization noise is roughly 60 dB. In Figure C.8 (e), for a signal level of 2.5 V peak-to-peak, the decrease i n signal-to-quantization noise is negligible. In Figure C.8 (f) however, the decrease is roughly 10 dB and any further decrease i n signal level increases the noise floor dramatically. A s a result, an alternative A G C circuit may have to be considered i f the received power of the signal varies by more than 20 dB. The final test assures the functionality of the transmitter for various data rates, modulation formats, baseband formats and window functions. A n example of a t ransmit ted signal is shown i n Figure C.9. In this example, the inphase and quadrature arms for B P S K signal l ing are windowed using a Ka i se r (50 dB) window. 113 Appendix C: Details of the Hardware Design „ 256 s * 192 128 X a. 1 1 1 | ITI | 1 IT" (4.5 vpp) ; ~i i i i i i i i i i i ) j .i i i 1 i i i 1 i i r 0 64 128 192 256 Quadrature Arm (y[k]) (a) E « w Q 03 0, 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 I I | I I I | I I I | I I I | I I I | I I I | I I I | I I Inphase Ann (4.5 Vpp) — . I . M L M I , , I , , , ! I , , 128 192 256 Quadrature Arm (y[k]) (b) CQ i S a in ft, 0 9.6 19.2 28.8 38.4 48 57.6 67.2 Is/2 Frequency (kHz) (d) o -10 -20 -30 -40 -50 -60 -70 -80 -90 -rrrn 1"!"1!111!1"!1"!1 Inphase Arm (2.5 Vpp) — hM4 M I , , , ! , , , ! , , , ! , , . ! , , , ! , , , ! , £ 192 5 64 B. _i rrrT i i | i i i - ii • n"T| i i i | i i i_ (0.5 vpp) ; I -I-.. ^ I I 1 1 M 1 , I I Ii : 1 : I -Ai , , i 1 , , , 1 , , r 0 64 128 192 256 Quadrature Arm (y[k]) (O ca rt s •B 00 H Q 01 9.6 19.2 28.8 38.4 4B 57.6 67.2 fs/2 Frequency (kHz) (e) o -10 -20 -30 -40 -50 -60 -70 -80 -90 I I | I I I | I I I | I I I | I I I | I I I | I I I | I I L Inphase Ami (0.5 Vpp) ' I 1 1 1 I 1 1 1 I 1 1 1 I 1 1 1 I 1 0 9.6 19.2 28.8 38.4 48 57.6 67.2(5/2 Frequency (kHz) (f) Figure C.8: Sampler Degradation (a) - (c) / versus Q Samples of an Unmodulated Sinusoid with Different Signal Strengths (d) - (f) Spectral Estimates. 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 Index(n) 3 5 0 4 0 0 4 5 0 5 0 0 Figure C.9: Sampled B P S K / and Q Waveforms with Windowing. Figure C I O illustrates spectral estimates for various transmitted signals. The purpose of the test is to ascertain the functionality of the transmitter. To quantify the performance of the 114 Appendix C: Details of the Hardware Design t ransmitter is beyond the scope of this thesis. S c h e m a t i c D i a g r a m s a n d P r o g r a m L i s t i n g s Figures C . l l to C.20 show the schematics diagrams of the hardware implementation. The software listings for the programmable devices are also presented. Conversion routines for the P R O M list ings and test vectors for the P A L listings have been omitted for clarity. 115 Appendix C: Details of the Hardware Design 1 I ' 1 1 I 1 ' 1 I 1 1 1 I 1 1 1 I 1 1 ' I 1 1 2400 bps, NRZ-L, BPSK, Rect (4.5 Vpp) -0 -10 -20 -30 -40 I 1 1 1 I ' ' 1 I 1 1 1 I 1 1 1 I 1 1 ' I 1 1 1 I 1 4800 bps, NRZ-L, BPSK, Rect (4.5 Vpp) 9.6 19.2 28.8 38.4 48 57.6 67.2 fs/2 Frequency (kHz) (a) Frequency (kHz) (b) o -10 (--20 p--30 -40 H -50 -60 | --70 -80 -90 1 I 1 1 1 I 1 1 1 I 1 1 1 I 1 1 1 I 1 1 1 I 1 1 4800 bps, NRZ-L, QPSK. Rect (4.5 Vpp) -I I I | M I | I I I | I I I | I I I | I I I | I I I | I I I 9600 bps, NRZ-L, OPSK, Rect (4.5 Vpp) -19.2 28.8 38.4 48 57.6 67.2 fs/2 Frequency (kHz) (c) 9.6 19.2 28.8 38.4 48 57.6 67.2 fs/2 Frequency (kHz) (d) I i i i | i i i | i i i | i i i | i i i | i i i | 2400 bps, Delay Mod., BPSK, Rect (4.5 Vpp) • I i i i I i i i I i i i I 9.6 19.2 28.8 38.4 48 57.6 67.2 fs/2 Frequency (kHz) (e) 9.6 19.2 28.8 38.4 48 57.6 67.2 fs/2 Frequency (kHz) (f) Figure C.10: Power Spectral Estimates of Various Modulated Signals. 116 Appendix C: Details of the Hardware Design Ul ^ 1 ED l l 3 • Q UJ * t lu * o EC u. ALL ENGI B.C. u a Q * s 3g§ 1 « E * e £ S -J *» 1 a N w ^ Q 5 u. u. a a IV u. a If u u. u 1 1 / II u. a If K u. a If \\ u. a If II u. a j} H u. a \t U Figure C . l l : Schematic of the Analog Front End. 117 Appendix C: Details of the Hardware Design /7777T77 /7 J o o o o o o o o u 777777 ' 0 0 0 0 0 0 0 0 ° - n *t » <n — * ssssssss SSSSSSVi ooooooao ^ * * * « * « * * * t ^ < * * JO oooooooa s v > v > Cc J o s is -* n m « W t- O a. 5 5 5 o 0) « w » t Q U C l u m u u = 3 S 7777 O O O O O O O O |uj|uj s : j ^ H » , k » n , R h „ 0 |0|u *********<«**x*«(<t; C J o o o o o o o o c * * * * SSSSSVA sssss\s\ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ssssssss ssssssss sisisis U * <• o • 2 •n m a. « Z % S J S Hi" I- K t l ** ii 0 0 j « CE CE met U.U, Ul Uj Ul£ o u o S 0 0 ui ui utS Ul lu Ul H U U (J UlUl K *~ Ul * tt i * tt; * * £ >- t» « U> 22 aa 0. O. a a a a a a Q. Q. o. 0. a. a. o o o c i O a a a E p cc cc ut^ c . * k H U K U O Q . t U > U K t t * * 7T( Q U O cn tf) co ti Y77~~~ S P «i *mil a si MM I 0» a * 111111 1 ** Q E& 03 Q) <t ^ F i g u r e C.12: Schematic of the Phase Detector/Data Extractor. 118 Appendix C: Details of the Hardware Design Figure C.13: Schematic of the Digital Loop Filter. 119 Appendix C: Details of the Hardware Design CC 5 t i cc o s * ri o ej VEER! VST Uj o ALL EN Gil B.C.. X O Q " • . u *• * i i* t s 2 S 5 5 ~ i a s 3 *t 1 Ul »- ° > » " £ a c 1 R S 2 a E a Q a 5 * 5 Figure C.14: Schematic of the Numerically-Controlled Oscillator. 120 Appendix C: Details of the Hardware Design 121 Appendix C: Details of the Hardware Design F i g u r e C.16: Schematic of the Transmitter. 122 Appendix C: Details of the Hardware Design Figure C.17: Schematic of the TMS 320C25 Interface. 123 Appendix C: Details of the Hardware Design DQoinnt&tttiB Q Q Q Q & C l C l Q u t x •» «N * * * * * * * * 3QCQC0C0CDCQQ; I ssssssw Q Q Q Q Q Q Q Q Q Q Q Q C i Q _ _ 0. * * * * * * * * I \ \ \ \ \ \ \ \ Q Q O Q O Q Q Q * * * * * * * * I \\\\\\\\ Q Q Q Q Q O Q C l * * * * * * * * O Q Q Q E l Q f i D t Il CO CD H) Q CQ Q Q Q Q Q Q Q Q ssssssss Q Q Q Q Q O Q Q * * * * * * * * * CO CQ CD CO co a a Q O O Q Q Q Q C 1 •Si . u a Figure C.18: Schematic of the TMS Read Ports. 124 Appendix C: Details of the Hardware Design CD I Q Q Q Q Q Q Q Q O O O O O Q O O Q Q Q Q Q D Q t t O U oooooooo \ Q Q C . Q C . C i Q Q O O O O O O O O Q Q Q Q Q Q Q Q • S < -HS Q Q Q Q Q Q Q Q O O O O O O O O a. L Q Q Q Q Q Q Q Q oooooooo eg t Q Q Q Q Q Q Q Q O O O O O O O O Q Q Q Q Q Q Q Q I ssssssss Q Q Q S Q Q Q Q O O O O O O O O Q Q Q a Q Q Q ////// Q Q Q Q Q Q Q Q ** Q Q Q Q Q Q Q O O O O O O O O Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q O O O O O O O O Q Q Q Q Q Q Q Q O U _ Q Q Q _ _ Figure C.19: Schematic of the TMS Write Ports. 125 Appendix C: Details of the Hardware Design I—II-!<J>-—K l(— • - K If-_l( 1(-H( It-o a k 0 0 S B • El El 0. Q • El • • • • i "i i -5 E 3 * * G '5 Figure C.20: Schematic of Miscellaneous Circuits. 126 ARCTAN LOOKUP TABLE * Author: * Institution: * Date: * Filename: * * Purpose: * / Joel A. Bisson University of British Columbia Oct 20th, 1988 ARCTAN.C To generate a phase angle given I and Q arms Jinclude •include •include •include <stdio.h> <stdlib.h> <math. h> "tohex.h" •define •define DecLvl (256) MaxLvl (256) main () { int i, j , k, LI, index; int Quantize (double x, int L, double ex[)); unsigned mask, shift, table[MaxLvl*MaxLvl]; double ex[MaxLvl+1], qy[MaxLvl], qx[MaxLvl], theta; long count; FILE * f l ; / * Read in quantizer coefficients */ scanf ( "%i\n", SL1); for (i = 0; i < L l ; i++) scanf ( "%G %G\n", sqx[i], sqy[i]); scanf ( "%G\n", sqx[Ll]); / * generate decision levels * / for (i = 0; i < DecLvl; i++) ex[i] = 2.*M_PI*i/DecLvl - (DecLvl+1)*M_PI/DecLvl; ex[DecLvl] = M_PI - M_PI/DecLvl; for (index = 0; index < L1*L1; index++) table[index] = OxFFFF; mask = ~(-L1); shift = (unsigned) (log((double)Ll)/log(2.0)); /* Main Loop */ for (j = 0; j < Ll; j++) for (k = 0; k < Ll; k++) { theta = atan2 (qy[j], qy[k]); ^ Quantize (theta, DecLvl, ex) - DecLvl/2; 13 index = ((mask s j) « shift) I (mask s k); g table[index] = ((unsigned) i) s OxOOFF; H' > o f l = fopen ("ARCTAN. HEX", "wt"); for (count = 0; count < L1*L1; count += 32) if ((i = ToHex (fl,Ll*Ll,255,32,count,00,table+count)) = -1) o exit(0); 3-i f ((i = ToHex (fl,Ll*Ll, 255, 0,0L, 01, table)) — -1) J* exit(0); 133 O fclose (fl); &. s 0 1 b int Quantize (double x, int L, double ex[]) { int i; 3 for (i - 1; i < L; i++) if ((ex[i] <= x) ss (x < ex[i+l])) return (i); return (0); ) PHASE ERROR ESTIMATE LOOKUP TABLE * Author: Joel A. Bisson * Institution: University of British Columbia * Date: Oct 22th, 1988 * Filename: MODULO.C Purpose: To generate a phase error estimate */ •include •include •include •include <stdio.h> <stdlib.h> <math.h> "tohex.h" •define •define DecLvl (256) MaxLvl (256) main () { int i , j , k, zk, index; int Quantize (double x, int L, double ex[]); unsigned table[MaxLvl*MaxLvl]; double ex[MaxLvl+l], ey[MaxLvl], M, theta; double Modulo (double x); long count; FILE * f l ; /* generate decision levels */ for (i = 0; i < DecLvl; i++) ex[i] = 2.*M_PI*i/DecLvl - (DecLvl+1)*M_PI/DecLvl; ex [DecLvl] = M_PI - M_PI/DecLvl; /* generate quantized levels */ for (i = 0; i < DecLvl; i++) ey[i] = 2.*M_PI*i/DecLvl - M_PI; for (index = 0; index < MaxLvl*MaxLvl; index++) table[index] = OxFFFF; /* Main Loop */ M = 1.0; for (j = 0; j < 4; j++) ( for (k = 0; k < 8; k++) for (zk = 0; zk < 256; zk++) ( theta = Modulo (M*(ey[zk) - Modulo (2. *M_PI*k/8.))) i = Quantize (theta, DecLvl, ex) - DecLvl/2; index = ( j« l l ) I (k«8) I (OxOOFF £ (zk-DecLvl/2)) table[index] = ((unsigned) i) & OxOOFF; } M *= 2.0; ) f l = fopen ("MODULO.HEX", "wt"); for (count = 0; count < 8192; count += 32) i f ((i = ToHex (fl,8192,255,32,count,00,table+count)) == -1) exit(0); i f ((i - ToHex (fl,8192,255,0,0L,01,table)) 1) exit(0); fclose (fl); 1 i n t Quantize (double x, i n t L, double ex[]) { int i ; for ( i = 1; i < L; i++) i f ((ex[i] <= x) ii (x < ex[i+l])) return ( i ) ; return (0) ; ) double Modulo (double x) { return ( -M_PI + fmod (x + 25.*M_PI, 2.*M_PI) ); ) re a. o 3-re s. s 3 b re CO if?-3 NCO LOOKUP TABLE (MOST SIGNIFICANT BYTE) * Author: * Institution: * Date: * Filename: * Purpose: * */ Joel A. Bisson University of British Columbia Nov 3rd, 1988 NCOHIGH.C To generate load value (high byte) •include •include •include •include •define •define •define •define •define •define •define •define main () { <stdio.h> <stdlib.h> <math.h> "tohex.h" MaxLvl (2048) MaxStat (32) LoopDly (63) Middle (.25) In (.15) Acquire 0x20 Trans 0x38 Lock 0x18 int a, n, i , ck, load, display; unsigned mask, shift, table[MaxStat*MAX_LVL]; long count, index; FILE * f l ; for (index = 0; index < MaxStat*MAX_LVL; index++) table[index] = OxFFFF; shift = (unsigned) floor ((log ((double)MAX_LVL)/log(2. 0)) +.5); /* Main Loop */ for (a = 0; a < 4; b++) for (n =3; n < 11; a++) for (ck = -MAX_LVL/2; ck < MAX_LVL/2; ck++) ( load = (1 « (10 - a)) - (1 « (10 - n)) * (int) floor ((double) ck / (double)(1 « (10 - n))) - ((n = 10) ? 0 : (1 « (9 - n))) ; display = Acquire; i f (load >= (int) floor((1.-Middle) * pow(2.,10.-a) + 0.5) ss load <= (int) floor((l.+Middle) * pow(2.,10.-a) + 0.5)) display = Trans; i f (load >= (int) floor((1.-In) * pow(2.,10.-a) + 0.5) ss load <= (int) floor((l.+In) * pow(2.,10.-a) + 0.5)) display = Lock; load -= LoopDly; i f (load <- 0) load - (n «— 3) ? 128 - LoopDly : 1; index = (a « shift+3) I <(n-3) « shift) I (ck s 0x7FF); table[index] = ((load 4 0x0700) » 8) I display; ( f l = fopen ("NCOHIGH.HEX","wt") ; for (count = 0; count < MaxStat*MAX_LVL; count += 32) i f ((i = ToHex (fl,MaxStat*MAX_LVL,255, 32,count,00,table+count)) == -1) exit(0); i f ((i = ToHex (fl , MAX_LVL*MAX_LVL, 255, 0,0L,01,table)) = -1) exit(0); fclose(fl); ) /* NCO LOOKUP TABLE (LEAST SIGNIFICANT BYTE) * Author: Joel A. Bisson * Institution: University of British Columbia * Date: Nov 3rd, 1988 * Filename: NCOLOW.C Purpose: To generate load value (low byte) */ (include •include •include •include <stdio.h> <stdlib.h> <math.h> "tohex.h" •define •define •define MaxLvl (2048) MaxStat (32) LoopDly (63) main () { int a, n, i , ck, load, display; unsigned mask, shift, table[MaxStat*MAX_LVL]; long count, index; FILE * f l ; for (index = 0; index < MaxStat*MAX_LVL; index++) table[index] = OxFFFF; shift = (unsigned) floor((log((double)MAX_LVL)/log(2.0)) +.5); /* Main Loop */ for (a = 0; a < 4; b++) for (n = 3; n < 11; a++) for (ck = -MAX_LVL/2; ck < MAX_LVL/2; ck++) ( load = (1 « (10 - a)) - (1 « (10 - n)) * (int) floor ((double) ck / (double)(1 « (10 - n))) - ((n = 10) ? 0 : (1 « (9 - n))) ; i f (load <=> 0) load = (n = 3) ? 128 - LoopDly : 1; index = (a « shift+3) | ((n-3) « shift) I (ck s 0x7FF) ; table[index] = load s OxOOFF; ) f l = fopen ("NCOLOW.HEX", "wt") ; for (count = 0; count < MaxStat*MAX_LVL; count += 32) if <<i ToHex (fl,MaxStat*MAX_LVL, 255, 32,count,00,table+count)> ==-1) exit(O); if ((i = ToHex (fl,MAX_LVL*MAX_LVL,255,0,OL,01,table)) — -1) exit(0) ; fclose(fl); ) CLOCKED RESOLUTION SELECTOR co o "Author Joel A. Bisson / D.R.S." " I n s t i t u t i o n University of B r i t i s h Columbia" "Date Nov 29th, 1988" " F i l e RESSEL1.PLD" DEVICE RESOLUTION_SELECT (P22V10) PIN "Definitions" CLK = 1 (CLK_INPUT combinatorial) D[7:0) = 2:9 (INPUT combinatorial) S[2:0] = 10,11,13 (INPUT combinatorial) GND = 12 (GND) Q[7:0] - 23:16 (OUTPUT active_high registered) VCC - 24 (VCO; BEGIN "Logic Equation Section" ENABLE (Q[7:0]) CASE (S[2:0]) BEGIN *B000) BEGIN Q[7] Q[6:0] END; *B001) BEGIN Q[7:6] Q[5:0J END; JB010) BEGIN Q[7:5] Q[4:0] END; *B011) BEGIN 0.17:4] Q[3:0] END; BEGIN Q[7:3] Q[2:0] END; BEGIN Q[7:2] *B100) »B101) D[7]; 0; D[7:6]; 0; D[7:5]; 0; D[7:4); 0; D[7:3]; 0; D[7:2]; Q[1:0] = 0; END; #B110) BEGIN Q[7:l] - D[7: i]; QtO] = 0; END; •Bill) Q[7:0] D[7: 0]; END; END. TEST_VECTORS omitted END. GATED RESOLUTION SELECTOR Title Resolution Selector Pattern RESSEL2.PDS Revision A Author Joel A. Bisson Institution University of British Columbia Date Oct 14th, 1988 CHIP ressel2 PAL20S10 ;PINS 1 2 3 4 5 6 7 8 9 10 11 12 S2 SI SO D7 D6 D5 D4 D3 D2 DI DO GND ;PINS 13 14 15 16 17 18 19 20 21 22 23 24 /OE Q0 Ql Q2 Q3 Q4 Q5 Q6 Q7 NC NC vcc EQUATIONS Q0.TRST = OE Ql.TRST = OE Q2.TRST = OE Q3.TRST = OE Q4.TRST = OE Q5.TRST = OE Q6.TRST = OE Q7.TRST = OE Q7 = D7 * /S2 * /SI * /SO + ;Q7 selected for all S2 SI SO D7 * /S2 * /SI * SO + D7 * /S2 * SI * /SO + D7 * /S2 * SI * SO + D7 * S2 * /SI * /SO + D7 * S2 * /SI * SO + D7 * S2 * SI * /SO + D7 * S2 * SI * so Q6 = GND* /S2 * /SI * /so + ;Q6 selected for all but 000 D6 * /S2 * /SI * so + D6 * /S2 * SI * /so + D6 * /S2 * SI * so + D6 * S2 * /SI * /so + D6 * S2 * /SI * so + D6 * S2 * SI * /so + D6 * S2 * SI * so Q5 = G N D * /S2 * /SI * /so + selected for all but 000 GND* /S2 /SI * so + 001 D5 * /S2 * SI /so + D5 * /S2 * SI * so + D5 * S2 * /SI * /so + D5 * S2 * /SI * so + D5 * S2 * SI * /so + D5 * S2 SI * so Q4 = GND* /S2 * /SI /so + •Q4 selected for all but 000 GND* /S2 * /SI * so + 001 GND* /S2 * SI * /so + 010 D4 * /S2 * SI * so + D4 * S2 * /SI * /so + D4 * S2 * /SI * so + D4 * S2 * SI * /so + D4 * S2 * SI * so Q3 « GND* /S2 * /SI * /so + Q.3 selected for all but 000 GND* /S2 * /SI * so + 001 GND* /S2 * SI * /so + 010 GND* /S2 * SI * so + Oil D3 * S2 * /SI * /so + D3 * S2 * /SI * so + D3 * S2 • SI * /so + D3 * S2 * SI * so Q2 = GND* /S2 * /SI * /so + Q2 selected for all but 000 GND* /S2 * /SI * so + 001 GND* /S2 * SI * /so + 010 GND* /S2 * SI * so + Oil GND* S2 * /SI * /so + 100 D2 * S2 /SI * so + D2 * S2 * SI * /so + D2 * S2 * SI * so Ql - GND* /S2 * /SI * /so + Ql selected for all but 000 GND* /S2 * /SI * so + 001 GND* /S2 • SI * /so + 010 GND* /S2 SI * so + Oil GND* S2 * /SI * /so + 100 GND* S2 * /SI * so + 101 DI * S2 * SI * /so + DI * S2 * SI * so QO = GND* /S2 * /SI * /so + QO selected for all but 000 GND* /E2 * /SI * so + 001 GND* /S2 * SI * /so + 010 GND* /S2 * SI * so + Oil GND* S2 * /SI /so + 100 GND* S2 * /SI * so -f 101 GND* S2 * SI * /so + 110 DO * S2 * SI * so SIMULATION g ft. omitted £[' O ACCUMULATOR (MOST SIGNIFICANT BYTE) "Author Joel A. Bisson / N.R." o "Institution University of British Columbia" "Date Nov 30th, 1988" "File ACCMSB.PLD" J* DEVICE MS 8BIT REG (P22V10) ft. " s PIN "Definitions" ^ CLK = 1 (CLK_INPOT combinatorial) t l D[15:81 = 2:9 (INPUT combinatorial) g A15 - 10 (INPUT combinatorial) <£|' C16 = 11 (INPUT combinatorial) 3 GND - 12 (GND) ZERO = 13 (INPUT combinatorial) OVFLW = 15 (OUTPUT active_high combinatorial) Q[15:8] - 23:16 (OUTPUT active_high registered) VCC = 24 (VCC); BEGIN "Logic Equation Section" ENABLE (Q[15:8],OVFLW); RESET(Q[15:8]) = ZERO; OVFLW = A15 % Q[15] % D[15] % C16 CASE (OVFLW,A15) BEGIN #B00, #B01) Q[15:8] •BIO) Q[15:81 •Bll) Q[15:81 END; - D[15:8]; = #B01111111; = •B10000000; TEST_VECTORS omitted END. ACCUMULATOR (LEAST SIGNIFICANT BYTE) "Author Joel A. Bisson / N.R." " I n s t i t u t i o n University of B r i t i s h Columbia" "Date Nov 23th, 1988" " F i l e ACCLSB.PLD" DEVICE LS_8BIT_REG (P22V10) PIN "D e f i n i t i o n s " CLK 1 (CLK_INPUI combinatorial) D[7:0] = 2:9 (INPUT combinatorial) A15 10 (INPUT combinatorial) OVFLW = 11 (INPUT combinatorial) GND = 12 (GND) ZERO = 13 (INPUT combinatorial) Q[7:0] = 23:16 (OUTPUT active high registered) vcc -24 (VCC); BEGIN "Logic Equation Section" ENABLE (Q[7:0J); RESET(Q[7:0]) = ZERO; CASE (OVFLW,A15) BEGIN • BOO, •B01) Q[7:0] = D[7:0J; •BIO) Q[7:0] = • B l l l l l l l l ; • Bll) Q[7:0] = •B00000000; END; END. TEST_VECTORS omitted E N D . OUTPUT REGISTER (MOST SIGNIFICANT BYTE) "Author Joel A. Bisson / N.R." "I n s t i t u t i o n University of B r i t i s h Columbia" "Date Nov 27th, 1988" " F i l e OUTMSB.PLD" DEVICE MS_OUTPUT_8BIT_REG (P22V10) PIN "Definitions" CLK 1 (CLK INPUT combinatorial) D[15:8J = 2:9 (INPUT combinatorial) A15 10 (INPUT combinatorial) C16 11 (INPUT combinatorial) GND = 12 (GND) B15 = 13 (INPUT combinatorial) OVFLW 15 (OUTPUT active_high combinatorial) Q[15:8] = 23:16 (OUTPUT active high registered) VCC = 24 (VCC); BEGIN "Logic Equation Section" ENABLE (Q[15:8]); ENABLE (OVFLW); OVFLW = A15 % B15 % D[15] % C16; CASE (OVFLW,A15) BEGIN •BOO, •B01) Q[15:8] = D[15:8]; •BIO) Q[15:8] = •B01111111; •B l l ) Q[15:8] = •B10000000; END; END. TEST_VECTORS omitted END. OUTPUT REGISTER (LEAST SIGNIFICANT BYTE) "Author Joel A. Bisson / N.R." " I n s t i t u t i o n University of B r i t i s h Columbia" "Date Nov 27th, 1988" " F i l e OUTLSB.PLD" DEVICE OUTPUT_8BIT_REG (P22V10) PIN "D e f i n i t i o n s " CLK = 1 (CLK_INPUT combinatorial) D[7:0] 2:9 (INPUT combinatorial) A15 10 (INPUT combinatorial) C16 = 11 (INPUT combinatorial) GND = 12 (GND) B15 13 (INPUT combinatorial) D15 = 14 (INPUT combinatorial) OVFLW 15 (OUTPUT active high combinatorial) Q[7:0) = 23:16 (OUTPUT active_high registered) VCC = 24 (VCC); S9 CONT -> S10 S10 • = CONT -> Sll Sll : = CONT -> SI 2 BEGIN "Logic Equation Section" S12 : = CONT -> S13 S13 • = CONT -> S14 ENABLE (Q[7:01); S14 = CONT -> SI 5 ENABLE (OVFLW); S15 = CONT -> SI 6 S16 = CONT -> S17 OVFLW = A15 % B15 % D15 * C16; S17 = CONT -> SI 8 S18 = CONT -> SI 9 CASE (OVFLW,A15) S19 = CONT -> S20 BEGIN S20 = CONT -> S21 *B00, S21 = CONT -> S22 •B01) Q[7:0] = D[7:0]; S22 = CONT -> S23 •BIO) Q[7:01 = •Bllllllll; S23 = CONT -> S24 •Bll) Q[7:0] = •BOOOOOOOO; S24 = CONT -> S25 END; S25 = CONT -> S26 S26 = CONT -> S27 END. S27 = CONT -> S28 S28 CONT -> S29 S29 CONT -> S30 TEST VECTORS S30 = CONT -> S31 S31 = CONT -> S32 omitted S32 = CONT -> S3 3 S33 = CONT -> S3 4 END. S34 = CONT -> S35 S35 = CONT -> S3 6 SEQUENCER (64-STATE FSM) S36 CONT -> S3 7 S37 = CONT -> S38 S38 = CONT -> S3 9 S39 CONT -> S40 Title MDTL Sequencer S40 = CONT -> S41 pattern SEQ1.PDS S41 = CONT -> S42 Revision A S42 = CONT -> S43 Author Joel A. Bisson / D.R.S. S43 = CONT -> S44 Institution University of British Columbia S44 = CONT -> S45 Date Jan 18th, 1989 S45 = CONT -> S46 S46 = CONT -> S47 CHIP SEQUENCER 1 PMS14R21 S47 = CONT -> S48 S48 = CONT -> S49 ; PINS 1 2 3 4 5 6 7 8 9 10 11 12 S49 = CONT -> S50 CLK DCK /SP INI NC NC NC NC NC NC SDI GND S50 = CONT -> S51 S51 = CONT -> S52 13 14 15 16 17 18 19 20 21 22 23 24 S52 = CONT -> S53 /OE SDO ENG ENK LDP OUT ACC PE /SAMP /LDM MOD VCC S53 = CONT -> S54 S54 CONT -> S55 STATE MOORE MACHINE S55 CONT -> S56 S56 = CONT -> S57 OUTPUT ENABLE S57 CONT -> S58 DEFAULT_ BRANCH S63 S58 CONT -> S59 S59 = CONT -> S60 SO CONT -> SI S60 = CONT -> S61 SI CONT -> S2 S61 = CONT -> S62 S2 CONT -> S3 S62 = CONT -> S63 S3 CONT -> S4 S63 = SAMPLE -> SO S4 CONT -> S5 S5 CONT -> S6 POWER UP : = VCC -> S63 S6 CONT -> S7 POWER UP.OUTF /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S7 CONT -> S8 S8 CONT -> S9 S0.OUTF ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP SI.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE 4 SAMP S61.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S2.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP S62.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S3.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT /ACC * /PE * SAMP S63.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S4.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP S5.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP CONDITIONS S6.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP S7.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP SAMPLE = SP * /INI; S8.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP CONT = /INI; S9.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP S10.OUTF : = /ENK /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP SIMULATION Sll.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * SAMP S12.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC /PE * SAMP omitted S13.0UTF : = /ENK • /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S14.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S15.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT + /ACC * /PE * /SAMP DATA CONTROLLER S16.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S17.0UTF : = /ENK * /ENG * /LDM * /LDP /OUT * /ACC * /PE * /SAMP S18.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC /PE * /SAMP S19.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP "Author Joel A. Bisson" S20.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP "I n s t i t u t i o n University of B r i t i s h Columbia" S21.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP "Date Nov 14th, 1988" S22.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP " F i l e SEQ2.PLD" S23.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S24.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S25.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP DEVICE SEQUENCER_2 (P22V10) S26.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S27.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP PIN " D e f i n i t i o n s " S28.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S29.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP CLK = 1 (CLK INPUT combinatorial) S30.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE /SAMP B[1:0] = 2:3 (INPUT combinatorial) S31.0UTF : = /ENK * /ENG • /LDM * /LDP * /OUT * /ACC * /PE * /SAMP Gl[3:0] = 4:7 (INPUT combinatorial) S32.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP G2[3:0] = 8:11 (INPUT combinatorial) S33.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP GND = 12 (GND) S34.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP ZERO - 13 (INPUT combinatorial) S35.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT /ACC * /PE * /SAMP ZEROUT = 14 (OUTPUT active high registered) S36.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP SH[3:0) = 18:15 (OUTPUT active_high registered) S37.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP K[2:0) = 21:19 (OUTPUT active high registered) S38.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP ENG = 22 (INPUT combinatorial) S39.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP ENK = 23 (INPUT combinatorial) S40.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC PE * /SAMP VCC = 24 (VCC); S41.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S42.0UTF :•= /ENK * /ENG * /LDM * /LDP * /OUT * /ACC /PE * /SAMP S43.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP BEGIN "Logic Equation Section" S44.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S45.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP ENABLE (ZEROUT,SH[3:0],K[2:0]); S46.0UTF : =• /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP ZEROUT = ZERO; S47.0UTF : = /ENK * /ENG * /LDM /LDP * /OUT /ACC * /PE * /SAMP S48.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC /PE * /SAMP IF (ENK) THEN S49.OUTF : = /ENK * /ENG /LDM * /LDP * /OUT * /ACC * /PE * /SAMP CASE (B[l:01) S50.OUTF : = /ENK * ENG * /LDM * /LDP * /OUT + ACC * /PE * /SAMP BEGIN S51.0UTF : = /ENK ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP #B00) K[2:0] = *B000; "k={0)" S 52. OUTF : = /ENK * ENG * /LDM * /LDP * /OUT * /ACC /PE * /SAMP *B01) BEGIN "k=(0,4)" S53.OUTF : = /ENK * /ENG * /LDM * /LDP * OUT * /ACC * /PE /SAMP K[2) = /K[2); "count through k" S54.OUTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP K[1:0) = #B00; . S55.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE • /SAMP END; S56.0UTF : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP JB10) BEGIN "k=(0,2,4,6|" S57.OUTF : = /ENK * /ENG /LDM * /LDP * /OUT * /ACC * /PE * /SAMP K[2) = K[2) % K [ l ) ; "count through k" S58.OUTF : = /ENK /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP K[l] = / K [ l ] ; S59.0UTF : = /ENK * /ENG * LDM * LDP * /OUT * /ACC * /PE * /SAMP K[0) = *B0; S60.OUTF : = /ENK * /ENG * LDM * LDP * /OUT * /ACC /PE * /SAMP END; • B l l ) BEGIN "k=(0,l,2,3,4,5,6,7(" K[2] = K[2] % (K[l] * K[01); "count through lc" K[l] = K[l) % K[0J; K[0] = /K[0J; END; END; ELSE K[2:0] = K[2:0] ; IF (ENG) THEN SH[3:0] = Gl[3:0]; ELSE SH[3:0J = G2[3:0]; END. TEST VECTORS omitted END. FREQUENCY DIVIDER (TRANSMITTER) co or "Author Joel A. Bisson" " I n s t i t u t i o n University of B r i t i s h Columbia" "Date Nov 10th, 1988" " F i l e CLKCODE, PLD" DEVICE CLOCK_CODE (P23S8) PIN " D e f i n i t i o n s " CLK = 1 (CLOCK) CLKINP = 2 (INPUT combinatorial) DRSEL[2:0) = 3:5 (INPUT combinatorial) N[1:0] = 6:7 (INPUT combinatorial) GND 10 (GND) OBS = 11 (INPUT combinatorial) QDR1[2:1] = 12: 13 (OUTPUT enable_high active_high reg_feedback) QDR110) = 14 (OUTPUT enable_high active_high registered) QMOD[1:0] = 15: 16 (OUTPUT enable high active high registered) QDRCLK = 17 (OUTPUT enable_high active_high registered) AMPCLK = 18 (OUTPUT enable_high active_high io_feedback) DRCLK 19 (OUTPUT enable high active high i o feedback) VCC = 20 (VCC) /QDR2[4:0] = 23: 26,22(BREG active_low registered),-BEGIN "Logic Equation Section" ENABLE (AMPCLK,DRCLK,QDRCLK,QMOD[l: 0] ,QDR1(2: 0] ) ; IF (OBS) THEN OBSERVE(QDR2[4:0]); QDRCLK = DRCLK; CASE (QDR1[2:0]) BEGIN •B000) BEGIN QDR2[4] - QDR2[4] % (QDR2[3] * QDR2[2] * QDR2[1] * QDR2[0]) QDR2[3) = QDR2[3] % (QDR2[2] * QDR2[1] * QDR2[0]); QDR2[2] = QDR2[2] % (QDR2[1] * QDR2[0]); QDR2[1J = QDR2[1] % (QDR2[0]); QDR2[0] = /QDR2[0J ; QDR1[2:0] = •B011; END; •B010) BEGIN QDR2[4:0] =QDR2[4:0]; QDR1[2:0] = •B101; END; •B001, #B011) BEGIN QDR2[4:0] = QDR2[4:0]; QDR1[2:0) = *B010; END; •B101) BEGIN QDR2[4] = QDR2[4] % (QDR2[3] * QDR2[2] * QDR2[1] * QDR2[01); QDR2[3] = QDR2[3] % (QDR2[2J * QDR2[1) * QDR2[0)); QDR2[2] = QDR2[2) % (QDR2[1] * QDR2[0]); QDR2[1] = QDR2[1] % (QDR2[0)); QDR2[0] = /QDR2[0]; QDR1[2:0] = #B110; END; #B100, #B110) BEGIN QDR2[4:0] = QDR2[4:0]; QDR1[2:0] = • B i l l ; END; • B i l l ) BEGIN QDR2[4:0] =• QDR2[4:0]; QDR1[2:0) = •B000; END; END; CASE (DRSEL[2:0]) BEGIN •B000) DRCLK CLKINP; •B001) DRCLK QDRl[0] •B010) DRCLK = QDRl[l] #B011) DRCLK QDR2[0] •B100) DRCLK = QDR2[1] •B101) DRCLK = QDR2[2] •B110) DRCLK QDR2[3] • B i l l ) DRCLK = QDR2[4] END; CASE (N[1:0)) BEGIN • B00, •B01) AMPCLK = QDRCLK; •B10) IF (DRSEL[2:0) = JB000) THEN AMPCLK = QDRl[0]; ELSE BEGIN IF (DRCLK * /QDRCLK) THEN QMOD[0] = /QMOD[0) ; ELSE QMODfO) = QMOD[0J ; AMPCLK = QMODfO] ; END; • B l l ) IF (DRSEL[2:0] = #B000) THEN AMPCLK = QDR1[1]; ELSE BEGIN IF (DRCLK * /QDRCLK) THEN CASE (QMOD[1:0]) BEGIN *B00) QMOD[1:0] = *B01, #B01) QMOD[1:0] = *B10, *B10) QMOD[1:0] = *B00, #B11) QMOD[1:0] = tBOO END; ELSE QMOD[1:0] =QMOD[1:0]; AMPCLK = QMOD[l] ; END; END; CO TEST_VECTORS omitted END. BASEBAND FORMATTER (TRANSMITTER) "Author Joel A. Bisson" " I n s t i t u t i o n University of B r i t i s h Columbia" "Date Nov 10th, 1988" " F i l e PCMCODE.PLD" DEVICE PCM_CODE_FORMATTING (P23S8) PIN " D e f i n i t i o n s " TXCLKINX2 = 1 (CLOCK) TXCLKIN = 2 (INPUT combinatorial) DATAIN = 3 (INPUT combinatorial) S[2:0] = 4:6 (INPUT combinatorial) N[1:0] = 7:8 (INPUT combinatorial) GND = 10 (GND) OBS = 11 (INPUT combinatorial) Q[1:0J = 13:12 (OUTPUT enable_high active_high reg_feedback) PHB[0] = 14 (OUTPUT enable_high active_high registered) PHA[0] = 15 (OUTPUT enable_high active_high registered) PCMOUT[1:0] = 17 16 (OUTPUT enable high active high registered) PCMOUT[2] 18 (OUTPUT enable_high active_high reg_f eedback) DATAOUT 19 (OUTPUT enable high active high reg feedback) VCC 20 (VCC) /PHB[3:1] 22 24 (BREG active_low registered) /PHA[2:1] 25 26 (BREG active low registered); BEGIN "Logic Equation Section" DATAOUT = DATAIN; ENABLE (PCMOUT [2 :0] ,Q[1:0] ,DATAOUT,PHA[0] ,PHB[0] ) ; IF (OBS) THEN OBSERVE(PHA[2:1],PHB[3:1]); CASE (N[1:0]) BEGIN #B00) BEGIN PCMOUT[2:0] = #B000; Q[1:0] = #B00; END; JB01) BEGIN Q[1:0] - #B00; PCMOUT[1:0] = #B00; IF (TXCLKIN) THEN PCMOUT[2] = PHB[0]; ELSE PCMOUT [2] = PHA[0] ; END; #B10) BEGIN Q[l] = *B0; PCMOUT[0] = #B0; CASE (Q [ 0 ] , TXCLKIN) BEGIN #B00) BEGIN PCMOUT[2:l] =PHAtl:0]; Q[0] = /Q[0]; END; fB10) BEGIN PCMOUT[2:l] =PHB[1:0]; Q[0] = /Q[0]; END; *B01, *B11) BEGIN PCMOUT[2:l] = PCMOUT[2:l]; Q[0] = Q[0]; END; END; END; #B11) CASE (Q[1:0].TXCLKIN) BEGIN }B000) BEGIN PCMOUT[2:0] =PHA[2:0]; Q[1:0] = Q[1:0]; END; #B001) BEGIN PCMOUT[2:01 = PCMOUT[2:0]; Q[1:0] = #B01; END; •B100, •B010) BEGIN PCMODT[2:0] - PCMOUT[2:0J; Q[1:0] = Q[1:0J; END; •B011) BEGIN PCMOUT[2:0] =PHB[3:1); Q[1:0) = •BIO; END; •B101) BEGIN PCMOOT[2:0] = PCMOUT[2:0); Q[1:0] = •BOO; END; •B110, •Bill) BEGIN PCMOUT[2:0] = PCMOUT[2:0]; Q[1:0] = •BIO; END; END; IF (TXCLKIN) THEN BEGIN PHA[1) = PHA[0] ; PHA[2) = PHA[1]; PHB[0] = PHB[0] ; PHB[1] = PHB[1] ; PHB[2) = PHB[2] ; PHB[3] = PHB[3] ; CASE (S[2:0)) BEGIN •B000) •B001) PHA[0) = DATAIN; IF (DATAIN) THEN PHA[0] ELSE PHA[0] /PHB[0]; PHB[0] ; •B010) IF (DATAIN) THEN PHB[0]; •B011) •B100) •B101) •B110) •Bill) PHA[0) ELSE PHA[0] PHA[0] = PHA[0] = PHA[0] = PHAtO] = = /PHB[0]; DATAIN; DATAIN; /PHB[0]; /PHB[0]; IF (DATAIN) THEN PHA[0J = PHB[0); ELSE IF (/DATAOUT) THEN PHA[0] ELSE PHA[0] END; END; ELSE BEGIN PHB[1] = PHB[0] PHB[2) = PHB[1) PHB[3] = PHB[2] PHA[0] = PHA[0] PHA[1] = PHA[1) = /PHB[0); = PHB[0] ; PHA[2] = PHA[2] ; CASE (S[2:0]) BEGIN •B000) PHB[0] = PHA[0]; •B001) PHB[0] = PHA[0); •BOIO) PHB[0] = PHA[0] ; •B011) PHBtO) = 0; •B100) PHB[0] = /PHA[0] •B101) IF (DATAOUT) THEN PHB[0] = /PHA[0J; ELSE PHB[0) = PHA[0]; •B110) IF (DATAOUT) THEN PHB[0] = PHA[0) ; ELSE PHB[0) = /PHA[0]; •Bill) IF (DATAOUT) THEN PHB[0] = /PHA[0]; ELSE PHB[0J = PHA[0]; END; END; END. TEST_VECTORS omitted END. PHASE ANGLE GENERATOR (TRANSMITTER) "Author Joel A. Bisson" "Institution University of British Columbia" "Date Nov 10th, 1988" "File PHASECOD.PLD" DEVICE PHASE_CODE_FORMATTER (P22V10) PIN "Definitions" CLK = 1 (CLK INPUT combinatorial) LOAD = 2 (INPUT combinatorial) PCM[2:0] = 3:5 (INPUT combinatorial) PHOFF[3:0] = 6:9 (INPUT combinatorial) N[1:0] = 10:11 (INPUT combinatorial) GND 12 (GND) ZERO 13 (INPUT combinatorial) Q[6:0] = 19:14 21(OUTPUT active_high registered) LDOUT = 23 (OUTPUT active high registered) VCC = 24 (VCC); BEGIN "Logic Equation Section" ENABLE (LDOUT,Q[6:0]); LDOUT = LOAD; IF (ZERO) THEN RESET (Q[6:0J); IF (/LDOUT * LOAD) THEN BEGIN CASE (N[1:0J) BEGIN *B00) Q[6:4] = *B000; •B01) BEGIN Q[6) = PCM[2] ; Q[5:4] = *B00; END; *B10) BEGIN Q[6] = PCM[2]; Q[5) = PCM[2] % PCM(1]; Q[4] = #B0; END; *B11) BEGIN Q[6] = PCM[21; Q[5] = PCM[2) % Q[4) = PCM[2] % END; END; Q[3:0]= PHOFF[3:0); END; ELSE BEGIN Q[6] PCM[1]; PCM[1] % PCM[0]; Q[5] = Q[5] Q[4] = Q[4] Q[3] = Q[3] Q[2] = Q[2] Q[l] = Q[l) % Q[0J = /Q[0]; END; END. TEST_VECTORS omitted END. Q[6] % (Q[5] * Q[4] * Q[3] * Q[2] * Q[l] (Q[4] * Q[3] * Q[2] * Q[l] * Q[0]) (Q[3] * Q[2] * Q[l] * Q[0]); (Q[2] * Q[l) * Q[0] ); (Q[l] * Q[0]); (Q[0]); fr TO 3 PL o a. s to CO 3
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The Multi-Sampling Digital Tanlock Loop for tracking suppressed-carrier M-ary PSK signals Bisson, Joël A. 1989
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Title | The Multi-Sampling Digital Tanlock Loop for tracking suppressed-carrier M-ary PSK signals |
Creator |
Bisson, Joël A. |
Publisher | University of British Columbia |
Date Issued | 1989 |
Description | A Multi-Sampling Digital Tanlock Loop (MDTL) is proposed for tracking suppressed-carrier M-ary Phase-Shift Keyed signals. Unlike the conventional Digital Phase-Locked Loop (DPLL) which possesses a sinusoidal phase characteristic, the MDTL has a linear phase characteristic with a period of 2π/M. Consequently, the MDTL can be characterized by a linear difference equation which eliminates the approximations of nonlinearity seen in the conventional DPLL. The linear difference equation also provides many attractive features over the conventional DPLL. These include locking conditions which are insensitive to variations in signal power, enhanced noise immunity, wider lock range and reduced steady-state mean phase error for the first order loop when the received signal has a frequency offset. A first-order MDTL is analyzed in the noiseless case. Closed-form expressions were derived for the steady-state mean phase error, the region of stability, the lock range and the acquisition time. It is shown that the use of multi-sampling improves the performance of the MDTL over the conventional Digital Tanlock Loop by increasing the region of stability and consequently, the lock range, and by decreasing the steady-state mean phase error and the acquisition time. In the presence of noise, the task of modelling the MDTL is partitioned into a software testbed and a hardware testbed. Both the software and hardware testbed simulate the MDTL in the presence of noise. The hardware testbed, however, also includes other important impairments such as quantization effects and loop delay. The software testbed represents the reference model against which the hardware testbed can be compared and measured. The phase error, the acquisition time and the hold-in time are the three performance measures used to characterize the performance of the MDTL in the presence of noise. It is shown that multi-sampling can be used as an acquisition aid without increasing the standard deviation of the phase error distribution. For binary phase-shift keying, four bits of sampler quantization and 64 levels of numerically-controlled oscillator resolution are needed to provide negligible performance degradation compared to the infinite quantization case at a received signal-to-noise ratio of zero dB. The MDTL design is simple. Digital implementation of the MDTL provides an opportunity for enhanced system integration using Very Large Scale Integration techniques for high speed applications or Digital Signal Processing microprocessor techniques for slower speed applications. |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2010-08-27 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0064770 |
URI | http://hdl.handle.net/2429/27823 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Campus |
UBCV |
Scholarly Level | Graduate |
AggregatedSourceRepository | DSpace |
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