T H E MULTI-SAMPLING DIGITAL TANLOCK LOOP FOR TRACKING SUPPRESSED-CARRIER M A R Y PSK SIGNALS Joel A. Bisson B . A . S c . U n i v e r s i t y of Waterloo, 1987 A THESIS S U B M I T T E D I N PARTIAL F U L F I L L M E N T O F T H E REQUIREMENTS FOR T H E DEGREE OF M A S T E R OF A P P L I E D SCIENCE in T H E F A C U L T Y O F GRADUATE S T U D I E S DEPARTMENT OF ELECTRICAL E N G I N E E R I N G We accept t h i s thesis as conforming to the r e q u i r e d s t a n d a r d T H E U N I V E R S I T Y O F BRITISH C O L U M B I A September 1989 ©Joel A. Bisson, 1989 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may department or by his or her representatives. be It is understood publication of this thesis for financial gain shall not be permission. The University of British Columbia Vancouver, Canada DE-6 (2/88) granted by the head of that copying allowed without my my or written Abstract A Multi-Sampling Digital Tanlock Loop ( M D T L ) is proposed for t r a c k i n g suppressed-carrier M ary Phase-Shift K e y e d signals. U n l i k e the conventional Digital Phase-Locked Loop ( D P L L ) w h i c h possesses a sinusoidal phase characteristic, the M D T L has a l i n e a r phase characteristic w i t h a period of 2-K/M. Consequently, the M D T L can be characterized by a l i n e a r difference equation w h i c h eliminates the approximations of nonlinearity seen i n the conventional D P L L . T h e linear difference equation also provides m a n y attractive features over the conventional D P L L . These include l o c k i n g conditions w h i c h are insensitive to variations i n signal power, enhanced noise i m m u n i t y , wider lock range and reduced steady-state mean phase error for the first order loop when the received signal has a frequency offset. A first-order M D T L is analyzed i n the noiseless case. Closed-form expressions were derived for the steady-state m e a n phase error, the region of stability, the lock range a n d the acquisition time. It is shown that the use of m u l t i - s a m p l i n g improves the performance of the M D T L over the conventional D i g i t a l Tanlock Loop by increasing the region of stability and consequently, the lock range, a n d by decreasing the steady-state m e a n phase error and the acquisition time. In the presence of noise, the task of m o d e l l i n g the M D T L is partitioned into a software testbed a n d a h a r d w a r e testbed. B o t h the software a n d h a r d w a r e testbed simulate the M D T L i n the presence of noise. T h e hardware testbed, however, also includes other i m p o r t a n t impairments such as quantization effects and loop delay. The software testbed represents the reference model against w h i c h the h a r d w a r e testbed can be compared and measured. T h e phase error, the acquisition time a n d the hold-in time are the three performance measures used to characterize the performance of the M D T L i n the presence of noise. It is shown that m u l t i - s a m p l i n g can be used as an acquisition a i d w i t h o u t increasing the standard deviation of the phase error distribution. F o r b i n a r y phase-shift k e y i n g , four bits of sampler quantization and 64 levels of numerically-controlled oscillator resolution are needed to provide negligible performance degradation compared to the infinite q u a n t i z a t i o n case at a received signal-to-noise ratio of zero d B . T h e M D T L design is simple. D i g i t a l i m p l e m e n t a t i o n of the M D T L provides an opportunity for enhanced system integration u s i n g Very Large Scale Integration techniques for h i g h speed applications or Digital Signal Processing microprocessor techniques for slower speed applications. ii Table of Contents Abstract ii L i s t of Tables vi vii L i s t of F i g u r e s Acknowledgements x 1 1 Introduction 1.1 2 3 Synchronization i n D i g i t a l C o m m u n i c a t i o n Systems 1 1.1.1 H i e r a r c h i c a l Synchronization i n a C o m m u n i c a t i o n System 1 1.1.2 C a r r i e r Synchronization for Suppressed-Carrier M - a r y P S K Signals 3 1.1.2.1 Conventional Techniques 4 1.1.2.2 D i g i t a l Techniques 5 1.2 Scope of the Thesis 5 1.3 O r g a n i z a t i o n of the Thesis 6 7 Review of Previous Work 2.1 Phase-Locked Loops 7 2.2 D i g i t a l Phase-Locked Loops 8 2.2.1 The Zero C r o s s i n g D P L L 10 2.2.2 T h e D i g i t a l Tanlock Loop 13 2.2.2.1 The D T L for T r a c k i n g Suppressed-Carrier P S K Signals 14 2.2.2.2 The D T L w i t h M u l t i - S a m p l i n g 14 15 C h a r a c t e r i z a t i o n of the M D T L 3.1 Assumptions 15 3.2 Description of the M D T L 16 3.2.1 The A n a l o g F r o n t E n d 16 3.2.2 T h e N u m e r i c a l l y - C o n t r o l l e d Oscillator 19 3.2.3 The Phase Detector 20 iii 3.3 3.2.4 The D i g i t a l Loop F i l t e r 25 System Equations of the M D T L 26 3.3.1 The Baseband M o d e l 26 3.3.2 The Phase E r r o r Difference E q u a t i o n 28 3.3.2.1 The Steady-State M e a n Phase E r r o r i n the Absence of Noise 29 3.3.2.2 L o c k i n g Conditions 29 3.3.2.3 Lock Range 33 3.3.2.4 A c q u i s i t i o n Statistics i n the Absence of Noise 36 3.3.3 Comparison of the M D T L w i t h Loops E m p l o y i n g the Tanlock P r i n c i p l e . . . . 4 43 Testing E n v i r o n m e n t of the M D T L 4.1 Software Platform of the M D T L 44 S i m u l a t i o n Requirements 44 4.1.1 4.1.2 Test Configuration 4.1.3 4.2 5 45 C a l c u l a t i n g the Input S N R 47 H a r d w a r e Platform of the M D T L 49 4.2.1 F u n c t i o n a l Description of the Loop Components 49 4.2.1.1 The A n a l o g F r o n t E n d 50 4.2.1.2 T h e Phase Detector / D a t a Extractor 52 4.2.1.3 The D i g i t a l Loop F i l t e r 55 4.2.1.4 The N u m e r i c a l l y - C o n t r o l l e d Oscillator 57 4.2.1.5 T h e Sequencer 60 4.2.2 Test Configuration 61 4.2.3 C a l c u l a t i n g the Input S N R 62 65 Performance E v a l u a t i o n 5.1 5.2 39 P h a s e E r r o r Statistics 65 5.1.1 Defining the Test Procedure 66 5.1.2 Phase E r r o r Results 68 A c q u i s i t i o n Statistics 73 5.2.1 Defining the Test Procedure 74 5.2.2 A c q u i s i t i o n Results 75 iv 5.3 6 H o l d - I n Statistics 79 5.3.1 Defining the Test Procedure 79 5.3.2 H o l d - I n Results 83 Conclusions 85 6.1 S u m m a r y of Research Results 85 6.2 Suggestions for F u t u r e W o r k 87 References 89 A Mathematical Derivations 94 B Topology Files of the Simulated MDTL 100 C Details of the Hardware Design 105 v List of Tables 4.1 Actions Performed by the F S M 61 5.1 S t a n d a r d D e v i a t i o n <r (in Radians) of the Reduced Phase E r r o r Process as a F u n c t i o n of q A, B and E /N b 69 0 C.l Features Incorporated into the T r a n s m i t t e r 107 C.2 T M S Port Assignments 109 vi List of Figures 1.1 E x a m p l e of a C o m m u n i c a t i o n System 3 2.1 B l o c k D i a g r a m of the Phased-Locked Loop 7 2.2 S i m p l i f i e d B l o c k D i a g r a m of the D P L L 8 2.3 B l o c k D i a g r a m of the F F - D P L L Phase Detector 9 2.4 B l o c k D i a g r a m of the L L - D P L L Phase Detector 10 2.5 B l o c k D i a g r a m of the Z C - D P L L Phase Detector 10 2.6 G i l l and Gupta's D P L L (a) Block D i a g r a m (b) the D P L L ' s S a m p l i n g Process w i t h Respect to the Incoming S i g n a l x (t) 11 2.7 B l o c k D i a g r a m of the D T L 13 3.1 B l o c k D i a g r a m of the M u l t i - S a m p l i n g D i g i t a l Tanlock Loop 17 3.2 M o d u l o 27r L i m i t e r for the t a n 22 3.3 Phase E r r o r Estimate for the Case M = 2 i n the Absence of Noise 24 3.4 The Baseband M o d e l for the M D T L i n z Operator Notation 27 3.5 Discrete Phase Plane Plot for Different Values of A and K' 31 3.6 Discrete Phase Plane Plot w i t h Conditions L I a n d L 2 True, (a) <p — —TT/3 Converges (b) cp = — 47r/5 does not Converge 31 - 1 Function 0 0 0 3.7 (a) L o c k i n g Region of the M D T L for A = B = M = 1 (b) Discrete Phase Plane Plot for A = 7r/5 and K' = 8/5 (c) S a m p l i n g Process w i t h Respect to the Inphase S i g n a l x (t). 33 0 3.8 L o c k i n g Region for Various Values of A, B and M 3.9 L o c k i n g Region i n Terms of the N o r m a l i z e d D i g i t a l Loop Coefficient a n d the Offset R a t i o 3.10 N o r m a l i z e d A c q u i s i t i o n Times versus I n i t i a l Phase E r r o r for K' = 1/5, A„ = (p = 7 r / 3 2 M and Various Values of A,B a n d M 34 Frequency 36 n/10, c 3.11 40 Probability of A c q u i r i n g Lock versus the N o r m a l i z e d Total E l a p s e d T i m e for K' — 1/5, A 0 = TT/10, and <p = T T / 3 2 M (a) M e = 1 (b) M = 2 41 4.1 B l o c k D i a g r a m of the M D T L Test Configuration 46 4.2 S i m u l a t i o n of the Transmitted B P S K Waveform with/without A W G N . (a) Sample T i m e - D o m a i n Representation (b) Power Spectral E s t i m a t i o n . 48 vii 4.3 Block Diagram of a Hardware Implemented MDTL 49 4.4 Block Diagram of the AFE 50 4.5 Block Diagram of the PD/DE 52 4.6 Mapping From / and Q Samples to the Phase Angle Estimate 54 4.7 Block Diagram of the Digital Filter 55 4.8 Block Diagram of the NCO 58 4.9 State Diagram of the FSM 60 4.10 The Hardware Test Environment 62 4.11 Photograph of the Hardware Implementation 63 5.1 PDF of an Unbounded Phase Error Process 65 5.2 Sample PDFs of the Reduced Phase Error for a BPSK Signal 67 5.3 PDFs of the Reduced Phase Error q Obtained from the Software Simulation 68 5.4 PMFs of the Reduced Phase Error q Obtained from the Hardware Implementation. 70 5.5 Standard Deviation a as a Function of the Number of Sampler Quantization Bits and the NCO Resolution 72 5.6 Cumulative Distributions of the Acquisition Time Obtained from the Software Simulation for Different SNRs and Values of A 76 Cumulative Distributions of the Acquisition Time Obtained from the Hardware Implementation for Different SNRs and Values of A 78 5.8 Cumulative Distributions of the Acquisition Time in the Absence of AWGN 79 5.9 Discrete Phase Plane Plot of the MDTL in the Presence of Noise 80 5.10 Reduced Discrete Phase Plane Plot of the MDTL in the Presence of Noise 81 5.11 Cumulative Distribution of the Hold-In Time Obtained from the Hardware Implementation for E /N - 0 dB and A = B = 1 83 5.7 k k q b 0 Cl Block Diagram of the Transmitter 106 C.2 Block Diagram of the Noise Channel 107 C.3 Block Diagram of the TMS Interface 109 C.4 Photograph of the Test Configuration 110 C.5 Sampled I and Q Waveforms for BPSK Signalling Ill viii C.6 S p e c t r u m of the A F E (a) I and Q Noise Samples (b) Spectral E s t i m a t e of the Inphase Arm 112 C.7 U n m o d u l a t e d S i n u s o i d (a) / versus Q Samples (b) Spectral E s t i m a t e of the Sine Arm C.8 112 S a m p l e r Degradation (a) - (c) / versus Q Samples of an U n m o d u l a t e d S i n u s o i d w i t h Different S i g n a l Strengths (d) - (f) Spectral Estimates 114 C.9 S a m p l e d B P S K / a n d Q Waveforms w i t h W i n d o w i n g 114 C.10 Power Spectral Estimates of Various M o d u l a t e d Signals 116 C.ll Schematic of the A n a l o g F r o n t E n d 117 C.12 Schematic of the Phase Detector/Data Extractor 118 C.13 Schematic of the D i g i t a l Loop F i l t e r 119 C.14 Schematic of the N u m e r i c a l l y - C o n t r o l l e d Oscillator 120 C.15 Schematic of the Sequencer 121 C.16 Schematic of the T r a n s m i t t e r 122 C.17 Schematic of the T M S 320C25 Interface 123 C.18 Schematic of the T M S R e a d Ports 124 C.19 Schematic of the T M S Write Ports 125 C.20 Schematic of Miscellaneous C i r c u i t s 126 ix Acknowledgements I w o u l d l i k e to t h a n k D r . R. W . Donaldson for his suggestions and supervision d u r i n g this project. In addition, I would l i k e to t h a n k R. A . Jeffery, M . M i l l e r and E . Casas for their discussions a n d invaluable suggestions and D . Sapach and N . Robidoux for their work on the hardware implementation of the M D T L . Special t h a n k s to m y companion, B r i g i t t e Vachon, for her constant support and encouragement. F i n a n c i a l support d u r i n g this work was provided by the N a t u r a l Sciences a n d E n g i n e e r i n g Research Council. x Chapter 1 Introduction Synchronization plays a major role i n the fields of communications, d i g i t a l data transmission, r a d a r , sonar, a n d navigation. I n modern communications systems, several different layers of synchronization are needed. These synchronization schemes range from frequency a n d phase estimation of a n i n c o m i n g carrier to the sequencing of packets, typically found i n higher levels of communication protocols. T h e demand for more efficient and robust communication systems coupled w i t h the continuing advances i n d i g i t a l technology have motivated researchers to investigate alternatives to existing systems. Research i n synchronization a n d its related areas remains active, i n order to support the needs of increasing system demands a n d to exploit the m a n y benefits that newer technologies provide. 1.1 S y n c h r o n i z a t i o n i n D i g i t a l Communication Systems Two sequences of events are said to be synchronous i f corresponding events i n the two sequences occur simultaneously. Synchronization is defined as the process of b r i n g i n g about, a n d retaining, a synchronous situation [1]. I n the context of d i g i t a l communication systems, the blocks w h i c h m a k e up the receiver m u s t synchronize to the corresponding t r a n s m i t t e r blocks whose signals are deterministic. Hence, the synchronization problem can, i n general, be l i m i t e d to receiver design. 1.1.1 H i e r a r c h i c a l Synchronization i n a Communication System A s previously mentioned, several layers of synchronization exist w i t h i n a communication system. C o m m o n l y used schemes are [2]: • carrier synchronization; • symbol (or clock) synchronization; 1 Chapter 1: Introduction • w o r d synchronization; • frame synchronization; • network synchronization; a n d • higher-level application-dependent synchronization. Coherent demodulation of a received signal requires the use of carrier, or subcarrier, synchron i z a t i o n . C a r r i e r synchronization deals w i t h the estimation of both the frequency and phase of the received signal. S y m b o l synchronization consists of detecting the boundaries between each symbol transmitted. T h e t e r m clock synchronization can also be used to denote symbol synchronization since the synchronization process involves the extraction of the clock w i t h i n the bit/symbol sequence. I f the data source is block encoded, word synchronization groups the appropriate symbols into their respective blocks. F r a m e synchronization is based on the reconstruction of the data i n terms of their o r i g i n a l time samples. A n example of this i s a f r a m i n g bit for synchronization of time-multiplexed samples. N e t w o r k synchronization is required i f data is t r a n s m i t t e d to and received from multiples sources. F i n a l l y , higher levels of synchronization m a y be required de- p e n d i n g on the application. A feature w h i c h distinguishes higher level synchronization schemes from those of carrier and symbol synchronization is t h a t higher level schemes are u s u a l l y solved by message format design, w h i c h involves the repetitive insertion of bits or words into the data sequence solely for synchronization purposes [3]. A s a n i l l u s t r a t i v e example of a communication system u s i n g synchronization techniques, consider the system shown i n F i g u r e 1.1. The mainframe, at point A , wishes to broadcast information to the Local Area Network ( L A N ) at point B , through a series of communications devices. The information is encoded a n d modulated onto a carrier signal for transmission v i a the satellite communication network. A t the receiver, carrier and symbol synchronization are performed to extract r a w bit sequences w h i c h are regrouped into packets once higher levels of synchronization are accomplished, such as f r a m i n g a n d word alignment. T h e received data is then t r a n s m i t t e d onto the L A N . The overall effect is the proper recovery of the information at the destination node(s). 2 Chapter 1: Introduction F i g u r e 1.1: Example of a Communication System. T h e lower level synchronization schemes, such as carrier or symbol synchronization, have r a r e l y used d i g i t a l technology, p r i m a r i l y due to the limitations i n speed of the d i g i t a l circuit elements themselves. D i g i t a l circuits, w i t h a l l their inherent advantages, have only recently been considered as a viable alternative to existing analog systems. Hence a n investigation into the use of newer, more economical d i g i t a l technologies at the lower levels of synchronization is required. 1.1.2 Carrier Synchronization for Suppressed-Carrier M-ary PSK Signals Phase-Shift Keyed ( P S K ) s i g n a l l i n g consists of m o d u l a t i n g a carrier, t y p i c a l l y a sinusoid, w i t h a discrete phase value representing the data signal. M-ary P S K s i g n a l l i n g has M discrete phase values available for modulation. O f interest is the case where the carrier is suppressed, i n which case a l l of the power is allocated to the modulated signal sidebands. F o r coherent demodulation, nonlinear methods are required to regenerate the carrier. These nonlinear techniques typically employ the phaselock principle. 3 Chapter 1: Introduction 1.1.2.1 Conventional Techniques Conventional techniques to regenerate the carrier from a suppressed-carrier M - a r y P S K signals are: • the s q u a r i n g loop for Binary P S K ( B P S K ) a n d its derivatives for higher-order constellations; • the Costas loop for B P S K a n d its derivatives for higher-order constellations; • the decision-directed feedback loop, the data aided loop [4]; a n d • application-dependent h y b r i d loops. T h e purpose of the loops previously mentioned is to generate a discrete carrier component whose frequency a n d phase agrees closely w i t h t h a t of the suppressed-carrier frequency. The s q u a r i n g loop obtains a discrete spectral component by s q u a r i n g the signal [2, 5]. T h i s discrete component is then tracked b y a Phase-Locked Loop ( P L L ) . F o r t r a c k i n g m u l t i p h a s e signals a s i m i l a r loop, the i V t h Power loop, generates a discrete spectral component by r a i s i n g the i n c o m i n g signal to the Nth power. T h e Costas loop [6, 71, is shown to be equivalent to the s q u a r i n g loop under certain reasonable 1 assumptions [81 but its implementation is quite different. T h e iV-phase Costas loop is used for higher-order phase constellations. O t h e r loops, such as the decision-directed loop or the data aided loop, t r y to eliminate the effects of modulation i n order to track the carrier frequency [2]. One common problem exists among these loops. T h e analog circuit elements which make up these loops suffer from component aging a n d temperature drifts. These conditions can have d e t r i m e n t a l effects on the system. A t y p i c a l example is the dc voltage drift on a Voltage-Controlled Oscillator ( V C O ) . A properly biased dc i n p u t voltage causes the V C O to oscillate at its free-running frequency. T h i s frequency is typically set to the expected carrier frequency. Component aging a n d temperature drifts can offset this voltage hence changing the free-running frequency. A solution to this problem is the use of d i g i t a l components whose performance does not degrade over time. In 1 The Costas loop is also called the I-Q loop when the lowpass arm filters are replaced with integrate-arid-dump arm filters. 4 Chapter 1: Introduction addition, the use of digital technology would provide a greater flexibility in the design of carrier tracking loops. 1.1.2.2 D i g i t a l Techniques Since the early 1960's, digital techniques have been applied to carrier tracking loops to eliminate the shortcomings of analog circuit elements. Among the loops which have been investigated are: • hybrid analog/digital loops; • sampled squaring and Costas loops; • non-uniform sampling loops; and • software loops. Initially, efforts were made to replace analog loop components with their digital counterparts [9]. In the late 1960's, emphasis was placed on all-digital loops. Intuitive schemes such as the sampled Costas loop were first considered [101. Non-uniform sampling loops were later considered due to their simplicity in design and their enhanced performance [11, 12, 13, 14]. Today, due to the advancement of microprocessor technology, software loops are being designed for practical demodulation at carrier frequencies below 100 kHz [15, 16, 171. 1.2 Scope of the Thesis This thesis: • proposes a new loop for tracking suppressed-carrier M-ary PSK signals, the Multisampling Digital Tanlock Loop (MDTL), based on an extension of an existing non-uniform sampling Digital Phase-Locked Loop (DPLL); • provides an analysis of a first-order MDTL in the absence of noise; • describes the design criteria and testing environment for a software simulation and a hardware implementation; and 5 Chapter 1: Introduction • defines the performance measures a n d evaluates the results obtained for phase error, acquisition a n d hold-in measurements. 1.3 Organization of the Thesis C h a p t e r Two reviews the most i m p o r t a n t work previously done on P L L s a n d D P L L s . T h i s review includes research on both discrete- and suppressed-carrier loops w i t h a n emphasis on non-uniform s a m p l i n g D P L L s . I n addition, a brief outline of the D i g i t a l Tanlock Loop is presented. C h a p t e r Three describes the functional loop components w h i c h m a k e up the M D T L . A phase error difference equation w h i c h governs the behaviour of the M D T L is derived. F r o m this difference equation, closed-form expressions of the steady-state m e a n phase error, the region of stability, the lock range a n d the acquisition time are presented for a first-order M D T L i n the absence of noise. C h a p t e r F o u r presents a brief overview on the design of a software s i m u l a t i o n a n d a hardware i m p l e m e n t a t i o n r e q u i r e d to measure the performance of the M D T L i n the presence of noise. T h e test specifications for both the software a n d hardware testbed are given. C h a p t e r F i v e defines the test procedures for the phase error, acquisition a n d hold-in measurements. Results of these measurements, conducted on both the hardware i m p l e m e n t a t i o n and the software s i m u l a t i o n are given. C h a p t e r S i x concludes the thesis w i t h a s u m m a r y of the results a n d suggestions for future areas of research. 6 Chapter 2 Review of Previous Work 2.1 Phase-Locked Loops A P L L consists of three functional units, the phase detector, the loop filter and the V C O . The block d i a g r a m of the P L L is shown i n F i g u r e 2.1. Input Phase Filtered Phase Signal Error Error Phase Detector Reference Signal Voltage Controlled Oscillator F i g u r e 2.1: Block Diagram of the Phased-Locked Loop. T h e P L L operates as follows. T h e phase detector generates a signal whose value represents an estimate of the phase error. Phase Error is defined as the instantaneous phase difference between the i n c o m i n g signal and the reference signal generated by the V C O . T h i s phase error estimate is filtered and the r e s u l t i n g error signal is fed back into the V C O i n order to reduce the overall phase difference. U n l i k e the conventional feedback systems, the P L L is a nonlinear system w h i c h makes it difficult to analyze. T h e first k n o w n paper on the P L L was published i n 1922 [18]. A thorough survey on the more recent status of the P L L can be found i n [2, 19, 20]. 7 Chapter 2: Review of Previous Work 2.2 D i g i t a l Phase-Locked L o o p s 2 The general DPLL structure is derived from the Maximum A Posteriori (MAP) estimation of an unknown phase for a sampled sinusoidal carrier embedded in Additive White Gaussian Noise (AWGN) [21]. Figure 2.2 shows a block diagram of the DPLL resulting from the closed loop MAP phase estimate. y(t) =y2Pcos(<o t+9(t)) 0 f(e ) cos(co„t + 9 ) k Figure 2.2: k k Simplified Block Diagram of the DPLL. With the exception of the sampler, the DPLL is similar in form and in operation to the general PLL shown in Figure 2.1. The sampler, however, allows the replacement of analog circuit elements with equivalent digital elements. The introduction of digital technology provides several benefits. First, it eliminates the problems of component aging and temperature drifts. Second, digital technology allows greaterflexibilityin design and testing. Finally, digital implementation provides an opportunity for greater system integration using Very Large Scale Integration (VLSI) techniques. The MAP estimate of the generalized DPLL does not take into account the sampling process. The times at which the observables j/*, k = 0,...,N — 1, are sampled are not specified. Hence, several different types of DPLLs have evolved as the result of the variability of the sampling 2 The term Digital Phase-Locked Loop has created a great deal of confusion in publications as to its precise definition. Since virtually all PLLs contain digital components, in this thesis the term Digital Phase-Locked Loop will be reserved for PLLs in which all components are digital. 8 Chapter 2: Review of Previous Work process. L i n d s e y [21] classifies the various types of D P L L s into four categories depending on the type of phase detector used. These four categories are: • the Nyquist Rate D P L L ( N R - D P L L ) ; • the Flip-Flop D P L L ( F F - D P L L ) ; • the Lead I Lag D P L L ( L L - D P L L ) ; a n d • the Zero Crossing D P L L ( Z C - D P L L ) . T h e N R - D P L L evolved p r i m a r i l y from analog P L L s whereby a sampler is placed before the loop and the received signal is sampled at the N y q u i s t rate. A n u m b e r of researchers have investigated the N R - D P L L [10, 22, 23, 24, 25, 26, 27, 28]. F i g u r e 2.2 is a n example of the N R D P L L w h e n s a m p l i n g occurs at a uniform rate. Due to the uniform s a m p l i n g nature of the N R - D P L L , however, the samplers do not eliminate the need for a phase detector. Additional circuit elements are needed for this scheme. T h e F F - D P L L was the first D P L L developed w h i c h employs a non-uniform s a m p l i n g method, hence e l i m i n a t i n g the need for a conventional phase detector [29, 30, 31, 32]. T h e phase error is derived from the duration between the set and reset times of a F l i p - F l o p triggered by the zero crossings of the i n p u t signal a n d a local reference clock. A block d i a g r a m of a phase detector typically used i n the F F - D P L L is shown i n F i g u r e 2.3. Signal Clock Positive Zero Crossing Detector r Digital Phase Set FlipFlop 1 Counter Reset Reference Signal Error Positive Zero Crossing \ Detector F i g u r e 2.3: Block Diagram of the F F - D P L L Phase Detector. 9 Chapter 2: Review of Previous Work In the L L - D P L L , the phase detector decides at every cycle whether the i n p u t signal is leading or lagging the reference signal by means of an integrate-and-dump circuit followed by a threshold detector [33, 34]. A block d i a g r a m of a phase detector used i n the L L - D P L L is shown i n F i g u r e 2.4. Due to the coarse quantization of the phase detector output, the L L - D P L L uses a nonlinear digital loop filter, such as a sequential filter, to smooth the error value. Yamamoto [35] has extended the L L - D P L L to include a second-order sequential filter w i t h memory. T h e L L - D P L L has been very successful w i t h digital signals and is available commercially i n both T T L a n d C M O S technologies. input Signal - • Integrate and Dump Reference | Lead Lag Binary Phase Detector Signal F i g u r e 2.4: Block Diagram of the L L - D P L L Phase Detector. T h e Z C - D P L L tracks the positive zero crossings of the received s i g n a l u s i n g a sampler as the phase detector [36]. T h e s a m p l i n g instants are derived from a Numerically-Controlled Oscillator ( N C O ) w h i c h replaces the conventional V C O . A block diagram of the Z C - D P L L phase detector is shown i n F i g u r e 2.5. T h e Z C - D P L L w i l l be the subject of the remainder of this chapter. Input Signal Sampling instants controlled by a local reference signal F i g u r e 2.5: Block Diagram of the ZC-DPLL Phase Detector. 2.2.1 T h e Zero C r o s s i n g D P L L T h e purpose of the Z C - D P L L is to track the positive zero crossings of the sinusoidal carrier corrupted by A W G N . N a t a l i [37] was the first to propose such a structure i n 1968. G i l l and G u p t a 10 Chapter 2: Review of Previous Work [36, 38] were the first to systematically analyze the first- a n d second-order Z C - D P L L s . A s a result of their analysis, the Z C - D P L L is often referred to as Gill and Gupta's DPLL. The loop consists of a sampler, a d i g i t a l loop filter and a N C O . A block d i a g r a m of the Z C - D P L L along w i t h an i l l u s t r a t i o n of the s a m p l i n g process is shown i n F i g u r e 2.6. X(t) D(z) c k Tk = tk - tk-i = T - Ck-i Q NCO (a) sampling A / instant t (sec) (b) F i g u r e 2.6: Gill and Gupta's DPLL (a) Block Diagram (b) the DPLL's Sampling Process with Respect to the Incoming Signal x{i). The N C O allows the sampler to act as a phase detector, therefore e l i m i n a t i n g the need for a conventional m u l t i p l i e r phase detector and p r o v i d i n g a conceptually simpler system. The N C O determines the next s a m p l i n g i n t e r v a l Tk given Tk = T 0 — 11 Ck~\ (2.1) Chapter 2: Review of Previous Work w h i c h states t h a t the next sampling i n t e r v a l is the difference between the n o m i n a l s a m p l i n g period of the i n p u t signal T a n d the previous correction value Ck-\ given by the d i g i t a l loop filter. 0 In the example shown i n F i g u r e 2.6 (b), the sampling instant tk-i lags the positive zero crossing. A s a result, the s a m p l i n g i n t e r v a l Tk should be smaller than the n o m i n a l s a m p l i n g period by an a m o u n t w h i c h is proportional to the value of the sample acquired at time tk-i- W h e n the s a m p l i n g instants eventually sample at the positive zero crossing, Tk w i l l assume the value of the n o m i n a l s a m p l i n g period and the loop attains a steady-state. A n y s a m p l i n g deviation from the positive zero crossing w i l l force the N C O to adjust the s a m p l i n g i n t e r v a l to consequently, offset the effects of the deviation. The simplicity and practicality of the Z C - D P L L have motivated a considerable amount of research. T h e following is a b r i e f outline on the areas of research w h i c h have been investigated on the Z C - D P L L . • Stability: D ' A n d r e a a n d Russo [39, 40, 41] analyzed the stability of Z C - D P L L u s i n g graphi c a l techniques for various levels of quantization. Osborne [12, 13] provided analytical results for the stability of a Nth Power Z C - D P L L for first-, second- a n d third-order loops. • Statistical Analysis: Weinberg a n d L i u [42, 43] provided semi-numerical techniques for the statistical analysis of the Z C - D P L L u s i n g the C h a p m a n - K o l g o m o r o v equation. Chie [44] extended the analysis and compared the results to analog P L L s . L i n d s e y [45] used the Chapman-Kolgomorov equation to determine the acquisition behaviour of the Z C - D P L L . • Quantization: Reddy a n d G u p t a [46, 47] analyzed the effects of quantization w i t h and without A W G N . Pomalaza-Raez [48] extended the analysis by s t u d y i n g both clock and sampler quantization. M c C a i n [49] investigated the use of robust estimators for various non-Gaussian noise processes. • Variations and Extensions: Holmes a n d Tegnelia [50, 51, 52] have modified the Z C - D P L L to track a square-wave subcarrier. T h e i r results are also applicable to a r b i t r a r y subcarriers t h a t are odd symmetric about the transition region. K o i z u m i [53] analyzed the Z C - D P L L w h e n subjected to a time delay. R o c h a [54] investigated the performance of the Z C - D P L L w i t h t i m e - v a r y i n g d i g i t a l loop filter coefficients. M a j u m d a r [55] and C e r n u s c h i - F r i a s [56] 12 Chapter 2: Review of Previous Work have improved the performance of the Z C - D P L L w h e n the loop tracks both the positive and negative zero crossings of the received signal. Sandoz [57] analyzed a b i n a r y quantized Z C - D P L L u s i n g a sequential filter a n d a n aided-acquisition technique. • Applications: G i l l [36] suggested the use of the Z C - D P L L for the demodulation of anglemodulated signals. Reddy [58] applied the Z C - D P L L for the demodulation of F M signals a n d N a t a l i [11] designed a Z C - D P L L to coherently demodulate B P S K signals at data rates below 1 M b p s . 2.2.2 T h e D i g i t a l T a n l o c k L o o p Lee a n d U n [59] developed the Digital Tanlock Loop ( D T L ) w h i c h is a Z C - D P L L whose m a i n feature is the tan" phase detector. F i g u r e 2.7 shows the block d i a g r a m the D T L w h i c h consists 1 of two samplers, the tan" phase detector, the digital loop filter and a N C O . T h e loop is preceded 1 by a 90° phase shifter i n order to generate the quadrature a r m . T h e inphase a n d quadrature samples are required i n d i v i d u a l l y i n order to determine a phase error estimate i n the i n t e r v a l between — T a n d n. NCO D(z) F i g u r e 2.7: ly(k)\ Block Diagram of the D T L . U n l i k e the conventional Z C - D P L L w h i c h possesses a sinusoidal phase characteristic, the D T L has a l i n e a r phase characteristic w h i c h is due to the tan" operator. A s a result, the D T L can be 1 characterized by a l i n e a r difference equation w h i c h eliminates the approximations of nonlinearity 13 Chapter 2: Review of Previous Work w h i c h are seen i n the conventional Z C - D P L L . T h e l i n e a r difference equation also provides many attractive features w h i c h include locking conditions w h i c h are insensitive to variations i n signal power, enhanced noise i m m u n i t y , wider lock range a n d a reduced steady-state mean phase error for a first-order loop given a received signal h a v i n g a frequency offset. 2.2.2.1 T h e D T L f o r T r a c k i n g Suppressed-Carrier P S K Signals K i m and U n [141 developed a D T L for t r a c k i n g suppressed-carrier M - a r y P S K signals by m a k i n g simple modifications to the phase detector. T h e D T L is an ideal candidate for this application since both the inphase a n d quadrature arms are r e a d i l y available. T h e 90° phase shifter i n F i g u r e 2.7 was replaced by a n inphase and quadrature m i x e r whose purpose is to beat the received signal down to a carrier frequency w h i c h is suitable for digital technology and to generate both the inphase a n d quadrature arms. 2.2.2.2 T h e D T L with Multi-Sampling Cho a n d U n [60] proposed m u l t i - s a m p l i n g methods for the conventional D T L to extend lock range a n d to reduce steady-state m e a n phase error and variance. Hagiwara and Nakagawa [61] have successfully applied the D T L w i t h m u l t i - s a m p l i n g to demodulate the pilot tones of both stereophonic a n d monophonic F M . 14 Chapter 3 Characterization of the MDTL 3.1 Assumptions Let r(t) be the received signal whose components consists of a Af-ary PSK signal s(t), and a AWGN signal n(t). Hence r{t) = s (t) + n{t). (3.1) The information-bearing signal s (t), can be written as « (t) = y/2P c sin [u t + 9(t) + \ (t)] (3.2) c where P is the signal power, u> is the nominal carrier radian frequency, 6 (t) is the instantaneous c c phase disturbance, and A (f) is the modulating data signal. The instantaneous phase disturbance 6 (/), consists of a frequency offset as well as a phase offset and can be expressed as 6 (t) = Aut + 9 (3.3) 0 where Aw = LJ — co represents a frequency detuning with w being the actual carrier radian c frequency, and 9 is a phase offset which is uniformly distributed between [—n, 7r). 0 The data signal X(t), for the case of Non Return-to-Zero-Level (NRZ-L) coding, can be expressed as OO A(t) = A- .[u(t- tT.) -u(t-(i+ 8 1)T )} (3.4) s i — — oo where u(t) is the unit step function, T is the symbol period, and A, represents a uniformly s distributed data phase whose value is Inm/M (m = 0 , 1 , 2 , ...,M - 1) at the zth symbol interval. The double-sided spectral density of the noise process n (t), is assumed to be N /2 Watts/Hz. 0 15 Chapter 3: Characterization of the MDTL 3.2 D e s c r i p t i o n of the M D T L The purpose of the MDTL is to lock onto the mixed-down suppressed-carrier frequency, and to track the instantaneous phase disturbance caused by the effects of the channel and the Analog Front End (AFE). The MDTL can also perform data extraction but is beyond the scope of this thesis and will not be considered. Figure 3.1 shows the functional block diagram of the MDTL. The MDTL consists of a phase detector, a digital loop filter, an NCO, and is preceded by an AFE. 3.2.1 T h e A n a l o g F r o n t E n d The purpose of the AFE is to beat the incoming signal down to a frequency level suitable for digital signal processing and to generate bandlimited inphase and quadrature arms for the tan" phase 1 detector. The incoming signal is multiplied by a local oscillator signal and by a 90° phase-shifted version of the local oscillator signal. The frequency of the local oscillator u , is the difference lo between the nominal carrier frequency and the desired mixed-down frequency w that is 0I wio = w — c w . 0 (3.5) The multiplied signals are then bandpass filtered with filters having a center frequency equal to the mixed-down frequency. The value chosen for the mixed-down frequency will be discussed in Chapter Four. The resulting inphase arm x (t), can be expressed as x (t) = [2r (t) cos (u>i t)] <g> h (t) 0 (3.6) where the symbol ® denotes convolution and h (t) is the impulse response of the bandpass filter H (/). A factor of 2 has been introduced for mathematical convenience in subsequent analysis. Similarly, the quadrature arm y{t), can be expressed as y (t) = [2r (t) sin (u, t)] ®h(t) 0 (3.7) Due to the bandpass filtering, the mixed-down signals suffer both phase and envelope distortion [14]. For simplicity, the envelope distortion can be represented as a signal power reduction. Hence, the approximated inphase and quadrature arms may be written, respectively, as 16 Analog Front End Numerically-Controlled Oscillator Digital Loop Filter Figure 3.1: Block Diagram of the Multi-Sampling Digital Tanlock Loop. Phase Detector Chapter 3: Characterization of the MDTL x (t) = y/2p~P sm [u t + e(t)+Z (*)] + V (t) c 0 (3.8) y(t) = y/2pKcos [u t + e(t)+^(t)] + fi(t) 0 where p is the signal power reduction factor due to filtering, £ (t) represents the data signal A (t) w i t h distortion due to filtering, 77 (t) is approximately n a r r o w b a n d A W G N w i t h double-sided spectral density N /2 a n d b a n d w i d t h B a n d fj(t) is the process rj(t) phase-shifted b y 9 0 ° . ot 0 The signal power reduction factor p can be expressed as the ratio between the total power of the filtered baseband data signal a n d the total power of the unfiltered signal, t h a t is 00 / P = ^ S (f)\H (f)\ df 2 m t (3-9) CO / S (f)df m where Hi (/) represents the low-pass version of the bandpass filter H (/) a n d S spectral density of the baseband data signal. F o r N R Z - L coding, S m Sm(f) = T ^^l. S s (/) is the power m (/) can be w r i t t e n as [14] ' (3.10) If the b a n d w i d t h B of H (/) is made sufficiently large so t h a t the filtering affects can be 0 neglected, £ (t) would be the m o d u l a t i n g data signal itself, t h a t is £(t) = \ (t) (3.11) but the noise power due to A W G N would increase i n direct proportion to B . 0 Hence, for a b a n d l i m i t e d signal, the phase distortion i n £ (t) cannot be ignored a n d is denned as modulation distortion. E x c l u d i n g quantization effects, the noise i n the M D T L consists of channel noise a n d modulation distortion. T h e Phase Error Disturbance is defined as the cumulative effect of these two sources of i m p a i r m e n t . F i n a l l y , the A F E m a y be preceded by either a bandpass filter or a bandpass l i m i t e r whose purpose is to eliminate u n w a n t e d noise i n the frequency bands w i t h negligible signal power. I n addition, the bandpass l i m i t e r l i m i t s the signal range i n order to protect the r e m a i n i n g circuit 18 Chapter 3: Characterization of the MDTL elements. I f the i n c o m i n g carrier frequency is sufficiently low t h a t no m i x i n g is required then a simple 90° phase shifter can be substituted for the A F E to generate the quadrature a r m . T h e l i m i t a t i o n of this design, however, is the accuracy at w h i c h a realizable H i l b e r t Transform can be designed to i m p l e m e n t the 90° phase shift for a b a n d w i d t h to center frequency ratio greater t h a n 0.1. 3.2.2 T h e Numerically-Controlled Oscillator The N C O is the circuit element required to control the s a m p l i n g process of the loop. U n l i k e a conventional V C O where the frequency of the reference signal is controlled, the N C O operates i n the time domain where the s a m p l i n g i n t e r v a l is controlled. T h e s a m p l i n g i n t e r v a l Tk, is denned as the time between adjacent s a m p l i n g instants, tk and tj,_i, that is (3.12) Tk — tk — tk-l where k represents a time index. I n a non-uniform s a m p l i n g D P L L , Tk is a function of the previous output sample from the digital loop filter, ct-i. I n the case of the M D T L , the s a m p l i n g i n t e r v a l equation can be w r i t t e n as rr, T k T = -A~ 0 Cfc-l (3.13) B where T — 2TT/U> is the n o m i n a l s a m p l i n g period of the N C O , A is a n integer denoting the 0 0 n o m i n a l number of samples per i n p u t period, a n d B is a factor used to reduce the loop control gain. T h e introduction of A enables the M D T L to acquire a greater number of samples per data symbol w h i c h is desirable i n the case where b i t detection is performed u s i n g a digital summation a n d d u m p i n g process. F r o m E q . (3.12), a n expression for the total elapsed time t k up to the kth. s a m p l i n g instant can be w r i t t e n as k tk—to+y^.Tj S u b s t i t u t i n g E q . (3.13) for Tj, we obtain 19 (3.14) Chapter 3: Characterization of the MDTL (3.15) where t i s assumed to be zero without loss of generality [38]. E q u a t i o n (3.15) describes the 0 behaviour of the N C O a n d provides the necessary information to derive a suitable expression for the phase detector a n d consequently, a difference equation for the phase error process. 3.2.3 T h e Phase Detector The phase detector consists of the samplers followed by the tan" operator, and the elements which 1 precede the digital loop filter, D (z). T h e purpose of the phase detector i s to give a reasonable estimate of the phase error. I n the case of the M D T L , the samples x a n d y are fed into the k k tan" block whose output z , contains the wanted phase error term a n d two u n w a n t e d terms due 1 k to the m u l t i - s a m p l i n g a n d the m o d u l a t i n g data signal. T h e blocks w h i c h i m m e d i a t e l y follow the tan' 1 function eliminate these u n w a n t e d terms. The phase detector can be analyzed as follows. The inphase a n d quadrature samples can be w r i t t e n , respectively, as = x/2pPc sin [u t + 9 + £ ] + Vk 0 k k k (3.16) y = \JlpP cos [u> t + 9 + tk] + rjk k 0 where x = x[t ], y = y[t ], 6 = 0[t ], t k k k k k k 0 k k k = t[t ], rj = v[t ], a n d rf = fj[t ]. S u b s t i t u t i n g E q . k k k k k (3.15) for the total elapsed time into the sampled inphase a r m , we obtain % I + °k+^ +vk (3.17) Z7TK \/2pP c sin — + <p + tk k +f)k where the phase error, <pk, i s denned as (3.18) 20 Chapter 3: Characterization of the MDTL and fc—1 (3.19) *= ^ 2 ^ ' T h e loop phase estimate 9 is given as the product of the n o m i n a l i n p u t carrier frequency k and the s u m of the correction values weighted b y 1/B. I n a s i m i l a r fashion, the quadrature a r m can be w r i t t e n as 2irk t = \/2pP cos — + <Pk + <k Vk (3.20) c T h e output of the tan" operator z , is defined as 1 k + -i z = tan A k (3.21) Vk where z lies w i t h i n the range — ir < z < TT. Note that both x a n d y m u s t both be given i n order k k k k to determine the correct phase quadrant. I n the absence of any phase error disturbance, that is Vk = Vk = 0, £fc = Aj; = 2irm/M for m = 0,1,..., M — I, z m a y be r e w r i t t e n as k 2irk 2irm (3.22) where the function /[•] is defined as / [p] — ~ l r + {( u + 7r ) m o d u l o 2ir} (3.23) and is shown i n F i g u r e 3.2. A s a result of this function, the phase angle is l i m i t e d to — ir < z < ir k and reflects the 27r phase ambiguity seen i n the t a n ' function a n d i n a l l phase detectors. 1 F r o m E q . (3.22), i t is noted t h a t the tan" function retains the phase information a n d 1 eliminates a l l amplitude information, that is the signal levels between the inphase a n d quadrature samples cancel. T h i s cancellation justifies our earlier assumption of a constant signal power reduction i n § 3.2.1. I n addition, the insensitivity to variations i n signal power eliminates the need for a n accurate Automatic Gain Control ( A G C ) circuit commonly seen i n conventional D P L L s . 21 Chapter 3: Characterization of the MDTL f[V] -K-- Figure 3.2: Modulo 2w Limiter for the tan Function. 1 F o r the purpose of synchronization, an estimate of the phase error ip is required. Interestk ingly, E q . (3.23) represents the response of the ideal phase detector, i f y, is replaced by <p , and k is called a sawtooth phase detector. Since E q . (3.23) occurs n a t u r a l l y w i t h i n the tan" function, 1 i t is possible to realize the ideal phase detector i f the u n w a n t e d terms w i t h i n z are eliminated. k These u n w a n t e d terms are: • Ink IA, the r e s u l t of m u l t i - s a m p l i n g since s a m p l i n g no longer occurs only at the positive zero-crossings, and • 2-irm/M, the result of the m o d u l a t i n g data signal. In order to properly derive the phase error estimate, i t is necessary to use the following properties w h i c h are shown i n A p p e n d i x A . l . G i v e n the r e a l numbers a\, a , an integer M, and 2 the function / [•] which is given by E q . (3.23), then / [ai op a ] = f[f 2 [ai] op f [a ] ] 2 (3.24) f[M } ai = f[Mf[ }} ai where op is one of the operators + , - or x . W i t h these two properties, the phase error estimate e k becomes (3.25) 22 Chapter 3: Characterization of the MDTL To prove E q . (3.25), we expand the Right Hand Side (R.H.S.) a n d m a k e use of E q . (3.24) to obtain M [z - / k 2irk A = f Mf 2irk f Zk~ A 2irk Mf 2irm -f 2irk A (3.26) 2itm Mf v>k + ~M~ = f [Mipk + 27rm] Q.E.D. = f[M<p ]. k o E q u a t i o n (3.25) states that i n the absence of noise we are able to obtain a n i d e a l phase error estimate w h i c h is l i n e a r modulo 2ir/M. T h e introduction of the g a i n factor M eliminates the effects of modulation b u t contracts the ideal phase detector curve by a n equivalent amount. A s a n example, F i g u r e 3.3 shows the phase error estimate i n the absence of noise for the case where M is equal to 2. Note that from the range —TT < <p < ir, stable lockpoints exist, that is <p — 0, at k k — 7 r a n d at zero. I n general, there exists M stable lockpoints located at 2-KJ M M M-l 1 ' 2 1) ^fl) M even M odd. (3.27) S i m i l a r l y , there exists M unstable lockpoints equally spaced between stable lockpoints. T h i s M - f o l d ambiguity occurs i n a M t h - o r d e r Costas loop as well. T h e advantage of this system, however, is t h a t to change from one M - a r y P S K format to another, M is the only parameter t h a t needs to be modified i n the M D T L whereas i n the M t h - o r d e r Costas loop, different circuit configurations are needed for various M - a r y P S K formats [1] (pp. 245-246). Since both M a n d / f ^ ] are k n o w n , the R . H . S . of E q . (3.25) can be emulated w i t h the blocks 2 w h i c h follow the tan" function a n d precede the digital loop filter i n F i g u r e 3.1. Note t h a t the 1 nonlinear functions i n E q . (3.25) can be easily created i n a digital system whereas i t m a y be extremely difficult to b u i l d a n equivalent analog circuit. 23 Chapter 3: Characterization of the MDTL /[M<pJ M 71-- 2 = •7C F i g u r e 3.3: Phase Error Estimate for the Case M = 2 in the Absence of Noise. In the presence of noise, it is necessary to classify the sampled noise process which is the result of sampling both the inphase and quadrature arms. Both r) (t) and T) (t) are approximately narrowband AWGN with zero-mean, double-sided spectral density N /2 0 and bandwidth equal to the noise equivalent bandwidth of AFE which is B [62]. The bandwidth of the bandpass filter 0 H (/) is equal or larger than the nominal sampling rate of the NCO and hence the sampled noise process rj (k) can be approximated as a sequence of independent and identically distributed Gaussian random variables having zero mean and variance a (rf) — B N 2 0 0 [44]. The same approximation applies for fj(k). In addition, both n(t) and fj(t) are always uncorrected at sampling instant tk, hence E [m • m] = 0 (3.28) where E [•] is the expected value operator. When considering the Maximum A Posteriori (MAP) criterion, the assumptions for the proposed loop differ from conventional suppressed-carrier tracking loops. The derivation of the Costas loop, for example, is based on the idea that the phase error estimate is derived from an infinite number of observables for use in the MAP solution to the MAP estimate [7]. Since the Costas loop is closed-form, the estimate is performed iteratively. The phase detector of the MDTL, how- ever, is based on the simpler assumption that the phase error estimate is based on the present pair of input samples, x and yk- If the phase angle k 24 within the inphase and quadrature sam- Chapter 3: Characterization of the MDTL pies is u n i f o r m l y distributed, p[zk] = 1/2-K (—IT < z < TT), i t is shown i n A p p e n d i x A . 2 that the k M A P estimate of the phase angle is the tan" function. I n the case of the M D T L , the m o d u l a t i n g 1 d a t a signal is not uniformly distributed and hence the above assumption does not apply. T h e Maximum-Likelihood estimator, however, suggests t h a t the tan" function provides the most un1 biased estimate of the phase angle [63]. A s a result of the phase error disturbance, the actual phase error estimate consists of the term / [ M ^ ] and an additive non-Gaussian r a n d o m variable (k, hence ek = f[M<p ] + Ck. (3-29) k Refer to A p p e n d i x A . 3 for a description on the statistical characteristics of the phase detector i n the presence of noise. 3.2.4 T h e D i g i t a l L o o p F i l t e r T h e phase error estimate e , is filtered by a digital loop filter r e s u l t i n g i n a correction value c , k k w h i c h is then used by the N C O to determine the following s a m p l i n g i n t e r v a l . A n nth-order digital loop filter can be represented by a difference equation of the same order, t h a t is n Ck = n ^2 aie -i k - ^2 bjC -j k (3.30) j=l »' = 0 T h e filter m a y also be described i n a more convenient form w h i c h is the z operator n o t a t i o n . 3 It is denoted by D (z), w h i c h is a ratio of two polynomials i n z. T h e nth-order digital loop filter m a y be w r i t t e n as 3 The symbol z is used as an operator on any function / (fc) which is defined in the domain of non-negative integers. The operator has the following properties: U(k)] = f(k + n) z- [f(k)] = f(k-n). n It should be noted that the z operator notation is not the z transform. 25 Chapter 3: Characterization of the MDTL D (z) = C (;+PiH' ° (z + )(z 0 V qi + P2)-"('+Pn) + q )---(z + q ) 2 (3.32) n where C i s the constant gain. G i v e n D(z), the correction value m a y be w r i t t e n as 0 c = D(z)e . k (3.33) k I n most p r a c t i c a l applications, the digital loop filter is u s u a l l y zero- or first-order. The zeroorder filter is s i m p l y a n attenuator whereas the first-order filter is either modelled as a n RC lowpass filter, a phase-lag filter or a perfect integrator. T h e choice of filter depends on the specifications of the application. 3.3 System Equations of the MDTL G i v e n the details of the i n d i v i d u a l components of the M D T L , i t is possible to analyze the general loop behaviour. T h e analysis is based on a baseband model of the loop w h i c h characterizes the phase error process. 3.3.1 The Baseband Model T h e baseband model is derived from the expression for the loop phase estimate, i n E q . (3.19). T h e difference between adjacent samples is given as e ~ -e = ^ L k +1 ( k 3.34) S u b s t i t u t i n g E q . (3.29) a n d E q . (3.33) for c we get k {/ [M<p ] + C*} Ok+i - Ok = (3.35) k or i n z operator notation h = ^4 z — 1I T a {/ \ - 26 M ^ + ^ > • ( 3 ' 3 6 ) Chapter 3: Characterization of the MDTL Equation (3.36) leads directly to the baseband model which is shown in Figure 3.4. Note that this model is independent of the carrier frequency and the multi-sampling, and depends only on the phase process of the input signal. The baseband model is different from the conventional DPLL where the nonlinear term sin [<pk] is replaced with / [Mipk] and Gaussian noise by the nonGaussian noise process Ck- Despite the removal of the sine nonlinearity, the model in Figure 3.4 remains nonlinear due to the coupling between the input phase 6k and the loop phase estimate 9k- This coupling is the result of the sampling process ik where (3.37) Figure 3.4: The Baseband Model for the M D T L in z Operator Notation. When the MDTL is tracking the input phase process, however, the correction values ct are small and the sampling intervals are assumed to be constant. With this approximation, the coupling between 6k and 9 no longer exists and the baseband model is characterized by a k piecewise linear stochastic difference equation. Linearization simplifies the analysis of the phase error process whose difference equation will be derived in the following section. 27 Chapter 3: Characterization of the MDTL 3.3.2 The Phase Error Difference Equation The phase error difference equation can be derived from Eq. (3.35). Substituting 9 = 9 - ip , k k k we get {/[M<pk] + < ] <Pk+i -<Pk = Ok+i - h - Using 9 k (3.38) - 9 = AwTjfc+i and replacing T +i with Eq. (3.13) yields k+1 k k Vfc+i-Vfc^ u> D(z) , . . , , . , , AuiT {f[Mip ] + Ck} + —— in f T 0 k - (3 39) where u> =u + Aw is the actual mixed-downfrequency.Using the same assumptions as denned in 0 in § 3.3.1, Eq. (3.39) represents a piecewise linear stochastic difference equation. When M — 1, Eq. (3.39) reduces to Cho's DTL [601 which is a multi-sampling DTL for a continuous sinusoidal signal. In addition, when A = B = 1, Eq. (3.39) reduces to Kim's DTL [14] which is a DTL for M-ary PSK signals. Finally, setting M = A = B - 1 reduces Eq. (3.39) to Lee's conventional DTL [59]. In the absence of noise, several important properties can be derived from the loop including the steady-state mean phase error, the region of stability, the lock range and the acquisition time. Although the techniques used in the following sections could be applied to derive loop equations for higher-order loops, the analysis for the remainder of this thesis will be limited to a first-order MDTL. First-order analysis is relatively simple and provides good insight on the effects of the individual loop parameters. Hence D{z) = G . x (3.40) In addition, Lee [59] has shown that the DTL outperforms the conventional ZC-DPLL and hence it is sufficient to compare the performance of the MDTL with loops which employ the Tanlock principle [14, 59, 60]. As a result, the notations used in thesis are the same as those used by Lee. 28 Chapter 3: Characterization of the MDTL 3.3.2.1 T h e Steady-State M e a n Phase E r r o r i n the Absence of Noise In the absence of any phase error disturbance, that is (k = 0, and considering the interval <Ph € hif, if), Eq. (3.39) can simplified to /, <Pk+i= [ 1 K'M\ - — B ~ ) A , 0 ( p k + 0 ~A where K'=w G in A = AuT . 1: 0 The steady-state mean phase error < p must satisfy (3.41) given fk+i s s ip s s (3.42) 0 — <fk = <P>s- Accordingly, is given by If the ratio B/AM is less than unity, the steady-state mean phase error decreases. The reduction can be accomplished by increasing the multi-sampling rate A while keeping B constant. 3.3.2.2 L o c k i n g Conditions We wish to determine the values of K' and A for which a steady lockpoint exists. Equation 0 (3.41) is considered first. Afterwards, the discrete phase plane method is used to derive stricter locking conditions. The first locking condition which is denoted by LI, is the restriction on i p „ which must lie between the interval if). Hence, using Eq. (3.43), L I becomes (LI) |A„| < (3.44) The solution to Eq. (3.41) is stable if all the roots of its characteristic equation have absolute value less than one [64]. For afirst-ordercharacteristic equation x(n + 1) - ax(n) = 0 29 (3.45) Chapter 3: Characterization of the MDTL the absolute value of the root a must be less t h a n one. W h e n applied to E q . (3.41), the second l o c k i n g condition L 2 , becomes 1 - £ £ < 1 (3.46) B or (L2) 9 Fl 0 < K' < =£. (3.47) M To i l l u s t r a t e the conditions needed for the M D T L to achieve a stable lockpoint, the discrete phase plane method is used. T h e discrete phase plane method gives a graphical interpretation of the phase error trajectory a n d is used extensively for nonlinear sampled-data systems. T h e h o r i z o n t a l axis represents the present state of the phase error <p , a n d the v e r t i c a l axis represents k the next state of the phase error ip +ik The phase error <p is projected vertically onto the characteristic curve w h i c h yields <p +ik k The characteristic curve i n our case is the phase error difference equation (3.39), w i t h set to zero. T h i s next state is projected horizontally onto the transformation line <p +\ = <pk a n d the k process repeats itself. T h e r e s u l t is a series of vertical a n d h o r i z o n t a l projections whose end points represent the trajectory of the phase error process. G i v e n a n i n i t i a l phase error bounded by [— fj, JJ), a l l projections i n a stable system should l i e inside a square box centered about the origin a n d whose half-width is TT/M. F i g u r e 3.5 shows the trajectories of two phase error signals for A — B — M = 1 w h e n the l o c k i n g conditions are not met. T h e dotted lines show the trajectory of the phase error signals. C l e a r l y , the phase error samples do not converge since i n F i g u r e 3.5 (a), A = 37r/5 a n d K' = 2/5 0 and hence L I is not met. I n F i g u r e 3.5 (b), A = 27r/5 a n d K' = 11/5 a n d hence L 2 is not met. 0 E q u a t i o n s (3.44) a n d (3.47) are necessary b u t not sufficient conditions. G i v e n A 0 a n d K' whose values meet both lock conditions, there exists i n i t i a l phase errors for w h i c h the phase error samples do not converge. F i g u r e 3.6 shows the discrete phase plane plot whereby both lock 30 Chapter 3: Characterization of the MDTL (a) (b) Discrete Phase Plane Plot for Different Values of A and K'. F i g u r e 3.5: Q / I (a) (b) F i g u r e 3.6: Discrete Phase Plane Plot with Conditions L l and L 2 True, (a) <p = —x/3 Converges (b) ip = —47r/5 does not Converge. 0 0 conditions are met, A — Zir/b a n d K' = 8/5, however for a given i n i t i a l phase error tp 0 0 -47r/5, the phase error samples do not converge. B o t h l o c k i n g conditions were derived from the simplified l i n e a r equation given by (3.41). F r o m the discrete phase plane plot, however, one can see t h a t a n additional restriction is needed. T h i s restriction states t h a t for any phase error value <pk between [-jj, jj), (fk+i should also be bounded 31 Chapter 3: Characterization of the MDTL by [—jf, jj). G r a p h i c a l l y , the restriction is equivalent to bounding the straight line i n the range of [—jr, jj) inside the square box. A s a result, i t is necessary to simply evaluate the endpoints of the l i n e . Hence, for <p = ±ff, < jj w h i c h leads to the t h i r d l o c k i n g condition L 3 k (L3) | A ( , | < ^ ^ - § ) (3.48) F i g u r e 3.7 shows the l o c k i n g region of the M D T L given b y E q s . (3.44), (3.47) a n d (3.48) for A = B — M = 1. The shaded area i n F i g u r e 3.7 (a) represents the l o c k i n g region i n w h i c h the M D T L can lock regardless of the i n i t i a l phase error. The x inside the shaded area is a coordinate chosen to illustrate the l o c k i n g process i n F i g u r e 3.7 (b). The s a m p l i n g process of (b) w i t h respect to the inphase signal x (t) is shown i n F i g u r e 3.7 (c). The three l o c k i n g conditions are sufficient to determine the l o c k i n g region w h e n A = 1. W h e n m u l t i - s a m p l i n g is present, however, certain values of A and K' w i t h i n the l o c k i n g region 0 correspond to a n unrealizable loop. F o r the loop to be realizable, the s a m p l i n g i n t e r v a l must be greater t h a n zero. Therefore, T = - ^ fc > 0. (3.49) T h i s leads to the fourth l o c k i n g condition L4, w h i c h is (L4) A > 7r 0 - . (3.50) The effect of the fourth condition is a truncation of the diamond-shaped l o c k i n g region. Figure 3.8 shows the regions of convergence for various values of A, B a n d M. Note t h a t as the ratio B/A decreases, the diamond-shaped region expands, w h i l e as M increases, the reverse is true. Hence, when considering stability, the use of m u l t i - s a m p l i n g offsets the adverse effects t h a t higher-order modulation formats create. It should be mentioned that, u n l i k e the sinusoidal D P L L , the l o c k i n g conditions are independent of signal power. In the sinusoidal D P L L , given the o p t i m u m value of K' for fastest convergence, the system can become unstable as signal power increases. A s the signal power de- 32 Chapter 3: Characterization of the MDTL L2 LIj/ A 0 o -6 1 0.5 1.5 2.5 K' (b) (a) t (sec) Figure 3.7: (a) Locking Region of the MDTL for A = B = M = 1 (b) Discrete Phase Plane Plot for A = TT/5 and A" = 8/5 (c) Sampling Process with Respect to the Inphase Signal i (t). 0 creases, its acquisition time increases [12]. Hence, to operate the D P L L properly at a n optimum signal level, a n accurate A G C circuit is required. T h i s is not the case for the M D T L . 3.3.2.3 L o c k R a n g e Lock Range is defined as the frequency range for w h i c h the M D T L can achieve lock given the digital loop filter coefficient G\, a n d the values A, B and M. We can therefore reexamine the four l o c k i n g conditions i n terms of the normalized d i g i t a l loop filter coefficient K a n d the frequency offset ratio w /cj 0 ! r a where 33 Chapter 3: Characterization of the MDTL K = LJ G 0 X (3.51) and 34 Chapter 3: Characterization of the MDTL Win (3.52) \27T W i t h equations (3.51) a n d (3.52), and the locking conditions given by (3.44), (3.47), (3.48), and (3.50), the lock range i s bounded by K> (LI) (L2) K< (L3) K < K < (L4) 25 (3.53) A 25 M Win Wo_ (3.54) Win 25 (A A \M W ' 0 Win 1-^2- 25 (3.56) A' F i g u r e 3.9 shows the locking regions i n terms of K and w /w 0 M. (3.55) Win for various values of A, B and in T h e shaded areas represent the acceptable frequency range for the M D T L to achieve lock regardless of i n i t i a l phase error given. In F i g u r e 3.9 (a), the fourth locking condition, T > 0, does not apply since this restriction is k not needed w h e n m u l t i - s a m p l i n g is not present. In F i g u r e 3.9 (b), w h e n the m u l t i - s a m p l i n g rate is increased, the lock range widens a t the expense of the range i n K. T h i s l i m i t a t i o n , however, is not a serious drawback, since i n most practical systems, the value of K is generally m u c h less t h a n one. I n F i g u r e 3.9 (c), as M is increased, the lock range, for values of w /w 0 in less t h a n one, is decreased. F i n a l l y , the more restrictive t h i r d locking condition eliminates the need for the second condition. T h e second locking condition, however, is shown i n F i g u r e 3.9 for sake of completeness. T h e lock range can be determined for given values of A,B,M a n d K. F r o m F i g u r e 3.9, two ranges exists depending on the value of K a n d its boundary is the intersection between the first and the t h i r d l o c k i n g condition. Hence, the lock range i s given as 25 25 + AK Win < w 0 K 25 25 - AK K€[0, 25 1 2M + A (3.57) and 25 w 2B + AK w in 0 2B (M±A) 2B+AK 35 25 25 2M+A' A (3.58) Chapter 3: Characterization of the MDTL 3.3.2.4 A c q u i s i t i o n Statistics i n the Absence of Noise The piecewise l i n e a r difference equation of the phase error process can be used to determine the performance of the M D T L d u r i n g its acquisition period. T h e Acquisition Time is defined as the time r e q u i r e d for the first phase error sample to fall w i t h i n a given level tp , of the steadyc 36 Chapter 3: Characterization of the MDTL state mean phase error given by (3.43). Hence, the acquisition process is terminated at the k t h s a m p l i n g instant w h e n \<Pk — Vas| < (3.59) I n the absence of noise, the acquisition t i m e can be explicitly stated for a given i n i t i a l phase error and first-order loop configuration. T h e values of K ' a n d A 0 are assumed to be w i t h i n the l o c k i n g region. T h e derivation consists of finding the m i n i m u m value of k w h i c h satisfies E q . (3.59) and solving the equation for the total elapsed time given the m i n i m u m value of k. determine k, we define a new variable <p' = i p — <p k k ss To to be the difference between the phase error sample at the the k t h s a m p l i n g instant a n d the steady-state mean phase error. S u b s t i t u t i n g this expression into (3.41) results i n ?;+i= (l-^p)?' f c . (3.60) E q u a t i o n (3.60) can be r e w r i t t e n recursively to obtain an expression i n terms of tp' , w h i c h is the 0 i n i t i a l phase error difference from i p . Therefore, S 3 K ' M X k <Pk = (1 - — j Vo- (3-61) S u b s t i t u t i n g this expression into the definition of acquisition time, E q . (3.59), and solving for k yields , . log (yQ - log (\<Po\) ,„ «™ *" ( 3 log(H-^|) • ' 6 2 ) T h e value of k, however, m u s t be restricted to the set of non-negative integers. W h e n the R . H . S . of E q . (3.62) is negative, w h i c h is the case where the i n i t i a l phase error is w i t h i n the given level <p , the acquisition time, and consequently k, is zero. F o r values of k w h i c h are positive, e the ceiling function when applied to the R . H . S . of E q . (3.62), gives the m i n i m u m integer value required. Hence, log (<p ) e - log Q' [) 0 log 37 k > 0. (3.63) Chapter 3: Characterization of the MDTL The t e r m 1 — determines the rate of convergence for the phase error process a n d should be as close to zero as possible for fast acquisition. In fact, i f is unity, the m a x i m u m value t h a t k can assume is one, w h i c h indicates that the acquisition process w i l l always terminate after one s a m p l i n g period. F o r a given B and M, this leads to K' = (3.64) M or consequently, i n terms of the normalized digital loop coefficient K = ^-.^-. (3.65) H a v i n g obtained k, the total elapsed time can be w r i t t e n as A ^ B 3=0 (3.66) °U 27T The loop phase estimate Ok, can be expressed i n terms of the i n i t i a l phase error and the steadystate mean phase error a n d hence, the acquisition time T , normalized to mixed-down carrier acq cycles i s given by = H *-7fro-y„) DM. _l_ ( 3 i 6 7 ) 1 where T= i - ( i - ^ y n • (3-68) T h u s , for a given loop configuration and an i n i t i a l phase error, the acquisition time can be given explicitly. In addition, a good approximation for T acq 38 can be Chapter 3: Characterization of the MDTL Tacq ± 0 k_ A (3.69) when the frequency offset ratio w /w,-„ is close to unity, t h a t is A sw 0. 0 0 A s a n i l l u s t r a t i v e example, F i g u r e 3.10 shows the acquisition times versus i n i t i a l phase error for a given loop configuration and various values of A, B a n d M. T h e acquisition l i m i t (p = 7 r / 3 2 M , c is a function of M since the range of values for w h i c h the i n i t i a l phase error c a n assume is a function of 1 / M . Note t h a t when the i n i t i a l phase error is w i t h i n cp , the acquisition time is zero. e A s the distance between the i n i t i a l phase error and the steady-state m e a n phase error increases, the acquisition time increases. B y increasing the m u l t i - s a m p l i n g rate, however, the acquisition time is reduced. I n this particular example, increasing M also decreases the acquisition time since the t e r m approaches unity. F i n a l l y , note that the acquisition time increases at finite values of tp . T h i s step increase is due to the discrete values for w h i c h k can assume. Q If the distribution of the i n i t i a l phase error is k n o w n , then i t is possible to determine the cumulative density function of the acquisition time. F r o m Baye's' r u l e , the probability of a c q u i r i n g lock w i t h i n [0,n ), denoted as Prob [T k acq < n ] c a n be written as [651 k 7T/M (3.70) -n/M where n is the time expressed i n mixed-down carrier cycles. T h e i n i t i a l phase error is assumed k to be uniformly distributed p[<po] = M/2-ir, (p G [jtf-,jf) so that E q . (3.70) can be evaluated 0 numerically. F i g u r e 3.11 shows the probability of a c q u i r i n g lock for the acquisition times shown i n F i g u r e 3.10 given a uniformly distributed i n i t i a l phase error. I n F i g u r e 3.11 (a), M = 1 whereas i n F i g u r e 3.11 (b), M = 2. 3.3.3 Comparison of the MDTL with Loops Employing the Tanlock Principle T h e M D T L is a n extension of the D T L s proposed by Lee, K i m a n d C h o [59,14, 60]. Consequently, the phase error difference equation w h i c h governs the behaviour of the M D T L can also predict the performance of the loops w h i c h employ the Tanlock principle. The following is a b r i e f comparison between the M D T L a n d the loops previously mentioned i n terms of the steady-state mean phase 39 Chapter 3: Characterization of the MDTL 20 12 A =1 B=l M-l 17.5 15 I A=4 B=2 M-l 10.5 9 12.5 7.5 5" 6 7.5 4.5 5 3 2.5 1.5 0 -ic -3it/4 -it/2 -it/4 0 it/4 0 n/2 3ic/4 ic -it -3ic/4 -it/2 -it/4 (a) 8 TC/2 3ic/4 it 6 A=4 B=2 M=2 6 it/4 (b) I 7 0 A=9 B=3 M=2 5.25 4.5 5 3.75 8" 4 3 3 2.25 2 1.5 1 0.75 0 0 -TC/2 -3ic/8 -TC/2 -7C/8 -ic/2 -3JC/8 -it/2 -7C/8 0 7t/8 ic/4 3ic/8 0 it/8 it/4 3it/8 ic/2 TC/2 (d) Figure 3.10: for K' = 1/5, (c) A Q Normalized Acquisition Times versus Initial Phase Error = ir/10, ip = i r / 3 2 M and Various Values of A,B and M. e error, the region of stability, the lock range a n d the acquisition time. T h e comparisons assume the absence of a n y phase error disturbance. Case 1: Lee's D T L The D T L proposed by Lee tracks the positive zero-crossings of a n u n m o d u l a t e d carrier frequency. T h e phase error difference equation for Lee's loop is given by 40 Chapter 3: Characterization of the MDTL I I i 1 1 1 1 1 1 1 1 1 i i i t / 0.875 0.75 J f 1 1 1 - 0.625 8" 1 = 1.B ==/ 1 o 1 A = 4,B-.= 2 0.5 1 0.375 0.25 ; : - / A _ _ A - A tt -1 - I no 3 0.125 1 1 1 12 16 20 24 28 32 (a) ''' • 0.75 1.5 1 1 i 2.25 i i 1 3 1 1 1 1 1 3.75 I 4.5 I I 5.25 (b) F i g u r e 3.11: Probability of Acquiring Lock versus the Normalized Total Elapsed Time for K' = 1/5, A = TT/10, and <p = n/32M (a) M = 1 (b) M = 2. c e (3.39) when A = B = M = 1. I f the M D T L is t r a c k i n g a n unmodulated carrier frequency w i t h the ratio B/A less than u n i t y , the steady-state m e a n phase error a n d the acquisition time decreases, a n d the region of stability a n d the lock range increases. A s a n example, the lock range i n F i g u r e 3.9 (a) represents the lock range of Lee's loop whereas F i g u r e 3.9 (b) represents the lock range of the M D T L . F o r a given K the M D T L has a wider lock range than the conventional D T L or alternatively, for a given lock range, the M D T L can have a smaller value of K t h a n the conventional D T L , a n d thus the M D T L has more i m m u n i t y for additive noise. Case 2: Kim's DTL T h e D T L proposed by K i m tracks the positive zero-crossings of a suppressedcarrier M - a r y P S K signal, A = B = 1. F o r the same value of M a n d given a ratio B/A less t h a n unity, the steady-state mean phase error and the acquisition time of the M D T L decreases, a n d the region of stability a n d the lock range increases. T h e M D T L , however, requires a greater number of functional elements t h a n K i m ' s DTL. 41 6 Chapter 3: Characterization, of the MDTL Case 3: Cho's D T L T h e D T L proposed by Cho tracks an unmodulated carrier frequency w i t h the m u l t i s a m p l i n g scheme, M = 1. F o r given values of A and B, the M D T L w h e n t r a c k i n g a n u n m o d u l a t e d carrier frequency represents Cho's D T L and consequently, the performance of both loops is identical. T h e M D T L , however, can be configured to track suppressed-carrier M - a r y P S K signals as w e l l . In a l l three cases, the M D T L offers distinct advantages over the compared loops at the expense of a d d i t i o n a l system elements. I n addition, the M D T L can be made to emulate any one of the previous loops by v a r y i n g the values of A, B and M . 42 Chapter 4 Testing Environment of the MDTL The analysis of the M D T L i n the absence of noise, has led to closed-formed expressions for the steady-state mean phase error, the region of stability, the lock range and the acquisition time. In the presence of noise, however, the behaviour of the M D T L is more difficult to analyze. A s mentioned i n C h a p t e r Two, several researchers have successfully characterized D P L L s i n the presence of noise u s i n g the Chapman-Kolgomorov equation [66]. I n the phase error difference equation (3.39), <p is a discrete-time, continuous variable M a r k o v process, a n d consequently, k the probability density function of <p also satisfies the C h a p m a n - K o l g o m o r o v equation. k phase error disturbance £ fc The i n (3.39), however, is difficult to model accurately since the pdf of the distorted data phase £ is only an approximation when modulation is present . A s a result, 4 k the solution to the Chapman-Kolgomorov equation becomes a n approximation. In addition, the effects of quantization and m u l t i - s a m p l i n g are not accurately reflected i n this solution and the computational complexity and the time required to obtain a n approximate solution does not fully justify the use of this technique. F o r these reasons, the baseband model of the M D T L is not used to obtain performance results i n the presence of noise. Instead, the M D T L shown i n F i g u r e 3.1 is used to model the loop's performance i n the presence of noise. The task of m o d e l l i n g the M D T L is divided into two separate testing platforms. T h e first platform is a software testbed where the effects of A W G N are present. T h e software platform simulates the system i n the presence of noise and acts as a reference model. T h e second platform is a h a r d w a r e testbed where a l l other secondary i m p a i r m e n t s such as quantization and loop delay are present. T h e h a r d w a r e platform represents the implementable case w h i c h accurately reflects the performance degradation from the reference model. T h i s chapter w i l l deal w i t h the design, implementation a n d problems of both these systems, while C h a p t e r F i v e w i l l present the performance results obtained. 4 Refer to Appendix A.3 for a detailed description on the statistical characteristics of the phase detector in the presence of noise. 43 Chapter 4: Testing Environment of the MDTL 4.1 Software Platform of the MDTL The purpose of the software testbed is to simulate the M D T L a n d to obtain performance results i n the i d e a l case for a received Signal-to-Noise Ratio ( S N R ) . I n order to accomplish this task, it is necessary to first enumerate the simulation requirements to determine a test environment, and then design a structure w h i c h effectively models the M D T L a n d w h i c h is suitable for data g a t h e r i n g a n d analysis. 4.1.1 Simulation Requirements The M D T L is h i g h l y structured w i t h every block being well defined. T h e s i m u l a t i o n program should reflect this structured environment since the use of blocks forces the system designer to m i n i m i z e the amount information passed between blocks. T h i s approach eliminates the need for complex interface units. T h e s i m u l a t i o n program m u s t be able to work w i t h sampled-data signals so that commonly-used Digital Signal Processing (DSP) techniques can be applied. F i n a l l y , the s i m u l a t i o n p r o g r a m m u s t be flexible so that the blocks w h i c h m a k e up the M D T L can be integrated into the s i m u l a t i o n program w i t h little difficulty. The p r o g r a m chosen for the software simulation is a general purpose time-driven simulation program for sampled-data systems called BLOck SIMulator ( B L O S I M ) [67]. B L O S I M is a ' C language discrete-time simulator w h i c h provides a h i g h l y structured environment for s i m u l a t i o n . B L O S I M is very n a t u r a l to use for system designers since i t encourages the division of the system into s m a l l interconnected blocks i n the same way t h a t a system i s partitioned for implementation. The user m u s t provide a s i m u l a t i o n program for each of these blocks, a n d a specification of the topology for block interconnection. B L O S I M includes as features: • Hierarchical Specification of Blocks: N e w blocks can be defined w h i c h are made up of specified interconnections of other blocks. F o r example, the complete topology of the system i s called the universe. T h e universe is made up of i n d i v i d u a l blocks called stars a n d groups of interconnected blocks called galaxies. T h e nesting of stars a n d galaxies w i t h i n galaxies is u n l i m i t e d . Hence, i t is possible to design a system without k n o w i n g the i m p l e m e n t a t i o n details of the fundamental units w h i c h m a k e up this system. 44 Chapter 4: Testing Environment of the MDTL • Interconnection of Blocks by Random Access Buffers: Blocks are interconnected v i a r a n d o m access buffers. T h e output data samples from one block are passed through a buffer before r e a c h i n g the i n p u t of the destination block. Buffer management is transparent to the user who m u s t only specify the interconnection between blocks. T h e use of r a n d o m access buffers allows the user to access past samples thereby e l i m i n a t i n g program complexity. • Passing of Parameters to Blocks: Parameters w h i c h are specified i n the topology file are passed to the i n d i v i d u a l blocks at run-time. T h e type of parameters w h i c h can be passed are integer a n d floating point numbers, arrays, files and functions. • Multiple Instances of Blocks: T h e same block can appear m a n y times w i t h i n a simulation. The functionality of the block can be specialized by passing it different parameter values. F o r example, an IIR bi-quadratic filter block was created for the A F E . T h i s block is used eight times w i t h i n the s i m u l a t i o n and is configured for different b a n d w i d t h s and center frequencies. • Consistency Checks and Narrative Mode: B L O S I M makes consistency checks d u r i n g topology definition a n d execution, a l l o w i n g i t to detect user p r o g r a m m i n g errors. In addition, B L O S I M has a n a r r a t i v e mode w h i c h lists the actions t a k e n by the program. T h i s narrative feature allows the user to verify the topology definitions and the execution of the i n d i v i d u a l blocks. • Automatic Scheduling on the Order of Block Execution: T h e order i n w h i c h the blocks are executed is automatically scheduled at run-time for efficiency. B L O S I M ' s m a i n disadvantage is t h a t the user m u s t be knowledgeable i n ' C . Once the blocks have been created, however, they m a y be accumulated to form a l i b r a r y of routines w h i c h may be used afterwards. B L O S I M is public-domain and is available from the U n i v e r s i t y of California at B e r k e l e y . 4.1.2 Test Configuration The phase error process, the acquisition process and the hold-in process are the three performance measures used to characterize the performance of the M D T L i n the presence of noise. A l l three 45 Chapter 4: Testing Environment of the MDTL measures, w h i c h are denned i n C h a p t e r Five, require a n exact expression of the phase error at every s a m p l i n g instant. T h e s i m u l a t i o n m u s t be able to generate this phase error information. F i g u r e 4.1 shows the block diagram of the M D T L test configuration w h i c h is needed to acquire a l l three performance measures. T h i s method of a c q u i r i n g data resembles the one used by Charles [68]. AFE i Channel i MDTL | PRBS Figure 4.1: Block Diagram of the MDTL Test Configuration. T h e top b r a n c h of F i g u r e 4.1 consists of the M D T L and the blocks needed to exercise the loop. T h e t r a n s m i t t e r consists of a Pseudo-Random Bit Sequence ( P R B S ) generator and a B P S K modulator. T h e modulated signal is corrupted by A W G N i n the C h a n n e l block. F i n a l l y , the received signal is passed to the A F E whose outputs represent the inphase a n d quadrature signals used for the loop u n d e r test. T h e bottom b r a n c h shows the blocks needed to extract the phase error information for the test results. T h e Z E R O block outputs a stream of zeros w h i c h , w h e n passed t h r o u g h the B P S K modulator, generates an unmodulated carrier frequency. T h i s carrier signal is synchronized to the modulated carrier s i g n a l and is fed directly into a n A F E w h i c h is i d e n t i c a l to the A F E being tested. A s a result, the lower inphase and quadrature arms do not suffer from any phase error disturbance. T h e s a m p l i n g process from the loop u n d e r test is used to sample the noise-free signals to obtain a n exact phase error expression. F i n a l l y , the test block, w h i c h is configured for the p a r t i c u l a r performance measure, acquires the samples for subsequent analysis. In the acquisition a n d hold-in tests, the test block m u s t also be able to communicate w i t h the loop under 46 Chapter 4: Testing Environment of the MDTL test. C h a p t e r F i v e discusses the algorithms used to obtain each measure i n greater detail. T h e topology files w h i c h define the three performance tests are listed i n A p p e n d i x B . In order to generate comparable results from both test platforms, both the s i m u l a t i o n program and the h a r d w a r e i m p l e m e n t a t i o n m u s t conform to the following specifications: • C a r r i e r frequency: 115.2 k H z ; • D a t a Rate: 9600 bps; • M i x e d - d o w n C a r r i e r Frequency: 19.2 k H z ; • M u l t i - s a m p l i n g Rate: A = 1,2,4,8; • Loop G a i n Value: B = 1,4; • M o d u l a t i o n F o r m a t : M = 2 for B P S K ; a n d • N o r m a l i z e d D i g i t a l Loop Coefficient: K = 2 _ n , n = 0, • • •, 5. In addition, the filters used i n the A F E are identical to those of the h a r d w a r e implementation. T h e filter specifications are given i n § 4.2.1.1. F i n a l l y , the s a m p l i n g frequency used for the s i m u l a t i o n is f — 1.152 M H z w h i c h is ten times the rate of the carrier frequency. s 4.1.3 C a l c u l a t i n g the Input S N R To calculate the receiver i n p u t S N R , i n the form of E /N , b we note that the variance of the noise 0 samples added by the channel block is given b y [62] (4.1) G i v e n (4.1) a n d the ratio between the b i t period a n d the s a m p l i n g period, the i n p u t S N R can be w r i t t e n as E N PT N b c 0 P b 0 f, c 2o-2 X f (4.2) 6 where / j — 9600 bps. I n E q . (4.2) E , N /2 a n d P denote, respectively, the received energy per b 0 c bit, the power spectral density of the received noise, a n d the received average power of the B P S K signal. file. P , cr , f 2 c s and f b are parameters w h i c h are set by the user a n d placed i n the topology To verify E q . (4.2), a trace routine was connected to the output of the C h a n n e l block. T h e 47 Chapter 4: Testing Environment of the MDTL trace routine obtains a time domain representation a n d a power spectral density estimate of its i n p u t signal. G i v e n P = 0.5, G\ = 1 a n d the ratio between the b i t period a n d the s a m p l i n g c period, E q . (4.2) yields a n S N R of 14.77 d B . F i g u r e 4.2 shows the received time a n d frequency domain waveforms. A spectral estimate of the simulated B P S K waveform, shown i n F i g u r e 4.2 (b), reveals a n S N R of approximately 15 d B . 0 115.2 230.4 345.6 460.8 fs/2 Frequency (kHz) (b) F i g u r e 4.2: Simulation of the Transmitted BPSK Waveform with/without AWGN. (a) Sample Time-Domain Representation (b) Power Spectral Estimation. 48 Chapter 4: Testing Environment of the MDTL 4.2 H a r d w a r e P l a t f o r m of the M D T L A h a r d w a r e implementation of the M D T L was designed, b u i l t and tested. T h e experimental u n i t tracks a n i n c o m i n g 115.2 k H z modulated carrier. T h e modulation formats can be either B P S K , Q P S K or 8 - P S K w i t h a selectable data rate r a n g i n g from 600 to 28 800 bps. T h e purpose of the h a r d w a r e model is to: • study the feasibility of i m p l e m e n t i n g the M D T L u s i n g a standard T T L / C M O S technology; • determine the problems typically associated w i t h coherent demodulation at the hardware abstraction level; • develop techniques r e q u i r e d to overcome these problems; a n d • study the effects of quantization on the performance of the loop a n d to compare results w i t h those obtained from the software s i m u l a t i o n . 4.2.1 F u n c t i o n a l D e s c r i p t i o n o f the L o o p Components F i g u r e 4.3 shows a simplified block diagram of the M D T L . These blocks are the A F E , the phase detector / data extractor, the digital loop filter, the N C O and the sequencer. To separate the different signals w i t h i n the system, N - b i t wide digital data paths are represented by a shaded arrow whereas analog signals or digital control signals are represented by t h i n n e r arrows. Incoming Signal Inphase Arm Analog Front End Data Samples Phase Detector/ •iu....MM...ii.iu.m»v Data Extractor l Quadrature Arm \ Sequencer F i g u r e 4.3: Control Signals Phase Error Block Diagram of a Hardware Implemented M D T L . 49 Chapter 4: Testing Environment of the MDTL 4.2.1.1 T h e A n a l o g F r o n t E n d F i g u r e 4.4 shows the components w h i c h m a k e up the A F E . T h e A F E consists of a bandpass filter centered about the carrier frequency, two m u l t i p l i e r units, a local oscillator, two bandpass niters centered about the mixed-down frequency a n d two signal level estimators. f = 19.2 kHz s F i g u r e 4.4: Block Diagram of the A F E . Two second-order bandpass niters, w i t h center frequencies of 115.2 k H z a n d Q of 2.0, are cascaded to form a fourth-order bandpass filter. T h i s filter eliminates u n w a n t e d noise i n the out-of-band region. T h e bandpass filter may be replaced by a bandpass l i m i t e r to protect the r e m a i n i n g components from excessive signal levels i n the i n c o m i n g signal [2]. Various circuits can be used to make up the m u l t i p l i e r units. T h e p a r t i c u l a r chosen depends h e a v i l y on the frequency range of interest. arrangement T h e analog m i x e r is ideally suited to R F applications, whereas analog m u l t i p l i e r s or chopper circuits are better suited to lower frequency ranges. F o r the experimental unit, chopper circuits are chosen over analog m u l t i p l i e r s since choppers simplify design, and provide better stability. A local oscillator of 96 k H z is needed to beat the 115.2 k H z signal down to 19.2 k H z . W h e n chopper circuits are used, the local oscillator is a digital clock w h i c h controls the analog switches. T h e 90° phase-shifted clock for use i n the quadrature a r m is generated u s i n g two F l i p - F l o p s . It is i m p o r t a n t to note that a tradeoff exists w h e n choosing the mixed-down carrier frequency. A s the mixed-down carrier frequency decreases, the response time of the system decreases and 50 Chapter 4: Testing Environment of the MDTL a l i a s i n g occurs, t h a t is the spectral terms overlap around 0 H z . Conversely, as the carrier frequency increases, the cost of the technology needed to r u n at higher speeds increases. One reasonable compromise is to choose the mixed-down carrier frequency to be a m u l t i p l e of the data rate. F o r the experimental unit, the mixed-down carrier frequency chosen is twice the data rate. A disadvantage of the chopper circuit is the creation u n w a n t e d harmonics at 96 k H z intervals. A s a result, a bandpass filter w i t h a steep rolloff is desired. Two second-order bandpass filters, each w i t h a center frequency of 19.2 k H z a n d a variable b a n d w i d t h , are cascaded to form the fourth-order bandpass filter required. T h e Analog to Digital Converters ( A D C s ) require that the i n c o m i n g signals be centered about 2.5 V d c . T h e necessary circuitry needed to a d d this offset is incorporated into the bandpass niters. T h e A F E would n o r m a l l y have a n A G C circuit i n order to keep the signal at a constant level. Ideally, the M D T L does not require a n A G C circuit since the ratio between the inphase and quadrature arms eliminates any amplitude information. I n practice, however, this is not the case. Q u a n t i z a t i o n m i s m a t c h introduces noise, i n the form of g r a n u l a r noise or overload distortion, a n d can severely degrade the S N R of the signal. F o r a properly designed system, the signal-to-quantization noise ratio is roughly + K d B , where N represents the number of bits of quantization a n d K i s a constant w h i c h is dependent on the signal [69]. A n alternative approach to a n A G C , a n d one which is used i n the experimental u n i t , is the level estimator for adaptive quantization [69]. S i g n a l level estimators are used to estimate the signal range of the inphase a r m a n d this estimate is passed to the ( A D C ) to d y n a m i c a l l y change the step size of the quantizer. T h e quantizer step size is defined as (V + — V~)/N where V + represents the m a x i m u m signal estimate a n d V~ represents the m i n i m u m signal estimate. T h e quantity, N, represents the number of quantization levels. T h e reasons for choosing this latter A G C circuit are twofold. F i r s t , the signal level estimator can be set to adapt either quickly or slowly to changing i n p u t conditions, depending on the application. I n our case, a time-constant of 1.0 msec is used for a n increase i n signal amplitude and 19.6 msec for a decrease i n signal amplitude. Second, the circuit is simple a n d stable. T h e major disadvantage is the circuit's poor performance for very weak signals, below 50 m V peakto-peak. T h i s is due to the limitations of the A D C chosen. 51 Chapter 4: Testing Environment of the MDTL F i n a l l y , a r e l a y switch and a variable gain amplifier are placed i n front of the A F E . T h e relay allows the user to switch from a remote signal to a locally generated signal, enabling integrity loopback testing for diagnostic purposes. The variable gain amplifier sets the received signal to a workable level, approximately 5.0 V peak-to-peak. T h e schematic layout of the A F E is shown is F i g u r e C . l l i n A p p e n d i x C . 4.2.1.2 T h e Phase Detector / D a t a E x t r a c t o r T h e Phase Detector I Data Extractor ( P D / D E ) provides an estimate of the phase error between the received signal and the s a m p l i n g pulse of the N C O . Provisions were also added for the data extraction function, although at present, the function itself is undefined. T h e blocks w h i c h form the P D / D E are the / (inphase) a n d Q (quadrature) A D C s , the lookup tables for the tan" , data 1 extraction, a n d phase error functions, a n d the switch programmable resolution selectors. F i g u r e 4.5 shows the block d i a g r a m of the P D / D E . Undefined ADC Lookup Inphase Arm tan 1 1 . " J ' x k Data Samples y n n >> Lookup +ve Peak -ve Peak ADC Quadrature Arm Sampling Pulse Lookup A Phase Error N-bit Resolution Selectors F i g u r e 4.5: Block Diagram of the PD/DE. T h e A D C s sample a n d quantize both the / and Q arms of the received signal to give two eight-bit unsigned values, 0 represents the m i n i m u m value a n d 255 represents the m a x i m u m value. T h e A D C s are configured as mid-riser quantizers a n d use the signal level estimates from 52 Chapter 4: Testing Environment of the MDTL the A F E to adapt the quantizer step size. S a m p l i n g is controlled b y the sequencer. The p a r t i c u l a r A D C chosen uses a half-flash technique to achieve a conversion time of approximately 1.34 /isec, thus e l i m i n a t i n g the need for an external sample-and-hold circuit. In addition, the A D C s have b u i l t - i n latches w h i c h hold the eight bit values for the tan" lookup table. 1 Resolution selectors are used after the A D C s and the various lookup tables to allow the performance of the M D T L to be evaluated for a given n u m b e r of q u a n t i z a t i o n levels. T h e number of q u a n t i z a t i o n levels is reduced by zeroing the selected least significant bits of the eight-bit i n p u t sample. T h e number of quantization levels for each resolution selector is controlled by a D I P switch w h i c h can v a r y the n u m b e r of s a m p l i n g bits from one to eight bits. Programmable Array Logic ( P A L ) Integrated Circuits (ICs) are used to implement this function. T h e I and Q samples of the received signal are combined to create the phase angle estimate u s i n g the tan" function. S e v e r a l methods exist to generate this function. One scheme w o u l d be 1 to calculate a power series expansion for the tan" function. T h i s method, however, consumes 1 a great deal of time. T h e method chosen for the experimental u n i t is the use of a lookup table w h i c h contains precalculated values for a l l possible signal inputs. A lookup table is conceptually simple, can be implemented u s i n g a standard Programmable Read-Only Memory ( P R O M ) and has considerable flexibility. T h e inphase sample forms the most significant byte address and the quadrature sample forms the least significant byte address. T h e output of the P R O M is a n eight b i t two's complement n u m b e r representing the phase angle estimate of the received signal. A s an i l l u s t r a t i v e example, consider two three-bit unsigned I and Q samples mapped into a two's complement four-bit phase angle shown i n F i g u r e 4.6. T h e c i r c u l a r dots r e p r e s e n t / , Q pairs. T h e lines w h i c h radiate o u t w a r d from the origin define the decision regions for the phase angle. T h e triangles encircling the constellation represent the phase angle estimates w h i c h , i n this case, are given i n two's complement notation. A s a n example, consider the coordinate (1,6) where x = 6 is sample from the / a r m a n d y = 1 is the sample from k k the Q a r m . T h i s coordinate falls w i t h i n the shaded decision region and hence would generate a two's complement value z k = 6 from the lookup table. Note that a l l amplitude information is lost i n this estimate. I f amplitude-dependent modulation formats are used, another lookup table u s i n g could be used to generate the necessary amplitude information. 53 Chapter 4: Testing Environment of the MDTL 'kI(X ) K -4 F i g u r e 4.6: Mapping From / and Q Samples to the Phase Angle Estimate. T h e phase angle estimate contains u n w a n t e d information due to modulation a n d m u l t i sampling. To obtain a workable phase error estimate for synchronization, the phase error function is implemented u s i n g a P R O M a n d a resolution selector. T h e P R O M lookup table contains a quantized form of E q . (3.25) defined i n C h a p t e r Three. T h e table index consists of the output value from the tan" lookup table, the modulation index M a n d a count value k = 0,...,A - 1 1 generated b y the sequencer. T h e value of A is controlled u s i n g a D I P switch a n d the access time of the P R O M is approximately 50 nanoseconds. I f speed i s less critical, the phase error function could be implemented i n a microprocessor. T h e circular m a p p i n g from modulo arithmetic to two's complement arithmetic makes this latter alternative attractive. F i n a l l y , provisions have been allocated for the data extraction function. A bipolar P R O M along w i t h a resolution selector are needed to perform this function. T h e table index is identical to t h a t of the phase error function. T h i s allows considerable freedom as to the type of algorithm used. A s of yet, the lookup table is undefined. Figure C.12 i n A p p e n d i x C shows the schematic layout of the P D / D E . 54 Chapter 4: Testing Environment of the MDTL 4.2.1.3 The Digital Loop Filter T h e behaviour of the M D T L depends largely on the transfer characteristics of the digital loop filter. T h i s filter processes the phase error estimate r e s u l t i n g from the output of the phase detector. A discrete filter design was chosen to m i n i m i z e the delay through the loop. F i g u r e 4.7 shows the block d i a g r a m of the first-order digital loop filter. F i g u r e 4.7: Block Diagram of the Digital Filter. T h e digital equivalent of the analog integrating element, such as a RC filter, is a n accumulator [21]. I n our case, the digital loop filter uses a resource s h a r i n g m e c h a n i s m whereby the m u l t i p l y i n g element, t h a t is the b a r r e l shifter, a n d the adder, are used twice to implement a second-order filter. To see this, consider the Proportional-Integral (PI) output characteristic of the digital loop filter denoted by the relation k Ck = Gie + G ^2ej j=0 k (4.3) 2 where, ej, j = 0,...,k represents the i n c o m i n g phase error samples, G\ a n d G2 represent the digital loop filter coefficients a n d c represents the correction factor at time k for use b y the N C O . k To i m p l e m e n t the resource s h a r i n g mechanism, we assume that the accumulator A , cc 55 maintains Chapter 4: Testing Environment of the MDTL a weighted, r u n n i n g s u m of the past samples, t h a t is Acck-i = G Eq. (4.3) can be w r i t t e n as k-l 2 ej. O n t h a t assumption, 3=0 ck = Gie + G e + Acc -i k 2 k (4.4) k We see immediately from E q . (4.4) t h a t c is the result of two multiplications of the i n p u t k signal b y the filter coefficients a n d two additions. I n order to m a i n t a i n the weighted, r u n n i n g s u m of the past samples, the accumulator is updated u s i n g the following expression. Acc = G e + Acc _i k 2 k (4.5) k T h e following list specifies the order of operations needed to implement the P I controller. • M u l t i p l y the i n c o m i n g signal e b y the filter coefficient G a n d a d d i t to the current value k of the accumulator 2 Acc -ik • Store this value into the accumulator, t h a t is the accumulator holds the value Acc . • M u l t i p l y the i n c o m i n g signal e b y the filter coefficient G\ a n d add i t to the current value k k of the accumulator Acc . k • Store this value, c into the output register. k A t this point, the correction factor is sent to the N C O a n d the d i g i t a l loop filter is ready for the next sample. To facilitate the design of the filter a n d to decrease the execution time, a b a r r e l shifter was chosen for the m u l t i p l i e r . Shifting a n i n p u t sample to the r i g h t b y n bits is equivalent to a divide b y 2™ operation. T h e coefficients G\ a n d G are four b i t values w h i c h represent the shift 2 amounts where 0000, i n binary, represents no shift, that is 1 x 2°, a n d 1111, i n binary, represents a r i g h t shift of 15 positions, 1 x 2 - 1 5 . F o r a two's complement notation, the higher-order bits of the output sample are sign extended. Note that the coefficients i n this experimental u n i t are normalized to the mixed-down carrier frequency. Hence, c w i l l differ slightly from the correction k value i n Chapter Three. A scaling b y l/w i s needed to convert c into a workable time value a n d 0 k this scaling operation takes place i n the N C O . 56 Chapter 4: Testing Environment of the MDTL In terms of functionality, a b a r r e l shifter i s identical to a conventional shift register. U n l i k e conventional shift registers, the desired number of positions to be shifted is determined by a n i n p u t decoder, hence e l i m i n a t i n g the need for a clock. The speed of the shift operation is restricted only by i n t e r n a l propagation delay a n d this delay is the same regardless of the number of positions to be shifted. T h e net effect is a high-speed shifter w i t h a propagation delay of approximately 30 nanoseconds. T h e 16-bit accumulator a n d the 1 6 - b i t output register are implemented u s i n g four P A L s . These P A L s perform the necessary l a t c h i n g of information and overflow management. Overflow is detected when the carry bits of the two most significant digits from the adder output are different. If overflow occurs the output values from the P A L s are set to the m a x i m u m , or m i n i m u m value depending on the sign b i t of the i n p u t sample. I n addition, the accumulator may be held at zero, u s i n g a D I P switch, to change the order of the filter, between first- and zero-order. F o r the purpose of testing, the d i g i t a l loop filter is configured as a zero-order filter. If problems associated w i t h r o u n d i n g or truncation are present, the designer has the option of u s i n g a floating-point d i g i t a l signal processor. T h e advantages of this option are flexibility, ease of design a n d integration. The disadvantages are price and execution time. A s a comparison, the digital loop filter implemented can deliver a n output sample every 150 nanoseconds whereas a T M S 3 2 0 C 3 0 r u n n i n g at 40 M H z w i l l execute one P I controller step i n approximately one psec. F i g u r e C.13 i n A p p e n d i x C shows the schematic layout of the d i g i t a l loop filter. 4.2.1.4 T h e N u m e r i c a l l y - C o n t r o l l e d O s c i l l a t o r Q u a n t i z i n g the correction value forces the designer to quantize the N C O operation. I n addition, N C O (or clock) quantization is necessary since, i n practice, i t is very difficult to design a n N C O whose s a m p l i n g i n t e r v a l T is continuously variable. k T h e circuit used to perform the N C O operation w i t h clock quantization is shown i n F i g u r e 4.8. T h e N C O consists of a down counter, a h i g h frequency oscillator a n d a lookup table. T h e frequency of the oscillator f osc is a m u l t i p l e of the mixed-down carrier frequency f , t h a t is 0 f ,c = Nf, 0 57 (4.6) Chapter 4: Testing Environment of the MDTL 19.6608 MHz 10-a n 2 osc -2 c Lookup 11 11. 5 5 g 5 11-Bit Sampling • Down Counter ^ 3 Pulse B Switch Values L o a d Pulse for ' a ' and ' n ' F i g u r e 4.8: Block Diagram of the N C O . where N is denned as the N C O resolution and i n this case is equal to 2 . N gives the number 1 0 of phase states possible w i t h i n 2TT, hence 7T A = ^ N = 512 (4.7) where A is the separation between phase states. In this p a r t i c u l a r implementation of the N C O , A is programmable w h i c h allows the effects of clock quantization on the loop's performance to be determined. T h e circuit arrangement i n F i g u r e 4.8 is equivalent to a programmable divide-by-P circuit. T h e lookup table converts the correction factor c , into a count value w h i c h is then loaded into k the counter. T h e counter is decremented a n d when the count value reaches zero, the A D C s are sampled. B y v a r y i n g the load value, the period of the N C O can be controlled. To derive a n expression for the load value, we rewrite the equation for the s a m p l i n g i n t e r v a l as T Tk = - C • Ck-i (4.8) where C is a constant to be denned later and Ck-i is the output of the digital filter. E q u a t i o n (4.8) differs slightly from the s a m p l i n g i n t e r v a l equation (3.13) derived i n C h a p t e r Three since the normalized d i g i t a l loop filter coefficient, i n this experimental unit, incorporates the loop gain 58 Chapter 4: Testing Environment of the MDTL factor B. In addition, as previously mentioned, c -i k is not scaled by l / w . Hence, C is used to 0 perform this scaling and can be expressed as c = £ =£ (4 - 9) where A / w defines the time resolution of the s a m p l i n g i n t e r v a l . T h e m u l t i - s a m p l i n g value A is 0 a m u l t i p l e of 2, and can be represented as A = 2 , a = 0,... ,3. S u b s t i t u t i n g the expressions for a A and C into (4.8) and factoring the oscillator period i n our experimental unit, we get r* = pr[2 - -c _i] 1 0 (4.10) f l t w i t h the restriction t h a t c -i k < 2 10_a . E q u a t i o n (4.10) states that the s a m p l i n g i n t e r v a l can be represented as a m u l t i p l e of the oscillator period. To v a r y the amount of clock quantization a s i m i l a r expression can be written, where = ^ where T / 2 o 2 1 0 _ n _ a 1 0 _ n , [ 2 1 — 0 n = 0, •••,7 represents the oscillator period, and c -i k ( 4 ' n is restricted to c -i k ) < . In order to use a constant oscillator frequency for a l l values of clock quantization, we m u l t i p l y both the numerator a n d denominator of (4.11) by 2 to obtain n T = | | [2 -° - 2 c _ ] 10 k n i 1 (4.12) Hence, decreasing the number of phase states is equivalent to reducing the resolution of CA_I. The expression w i t h i n the square brackets is stored w i t h i n the lookup table and the values of a and n are selectable v i a D I P switches. In addition, the values w i t h i n the lookup table take into account the time offset given by the loop delay. A n eight segment display is controlled by the unused memory i n the lookup table. The display gives an indication of whether the M D T L is i n lock by comparing at each s a m p l i n g instant the load value w i t h the n o m i n a l load value. If the load value is w i t h i n 10% of the n o m i n a l value, an L is displayed w h i c h indicates that the loop is tracking. S i m i l a r l y , i f the load value deviates from the n o m i n a l value by more than 25%, an A is displayed w h i c h indicates t h a t the loop is acquiring. 59 Chapter 4: Testing Environment of the MDTL T h e display is left b l a n k d u r i n g the transition period between the acquisition process a n d the t r a c k i n g process. It should be noted that the display acts as a v i s u a l aid when configuring the loop a n d is not used for accurate measurement of lock. Figure C.14 i n A p p e n d i x C shows the schematic d i a g r a m of the N C O . 4.2.1.5 T h e Sequencer T h e sequencer coordinates the activities of the various loop components. T h e sequencer consists of a 64-state Finite State Machine ( F S M ) P A L and a D a t a Controller P A L . T h e F S M performs t h e operations needed to control the A D C s , the flow of data, the digital loop filter, and the N C O . The inputs to the F S M are the s a m p l i n g pulse generated b y the N C O a n d a reset signal. The state diagram of the F S M i s shown i n F i g u r e 4.9. 11 11 [Tj Start Sequence of Events riT| Sampling Pulse Negated fi~] Sampling Pulse Asserted fx] Don't Care F i g u r e 4.9: State Diagram of the FSM. The m i n i m u m time required to complete a cycle through the loop is 64 clock cycles a n d is referred to as loop delay. T h e operation of the M D T L is not affected b y the loop delay i f the s a m p l i n g i n t e r v a l exceeds this delay. Otherwise, the s a m p l i n g i n t e r v a l assumes the value of the loop delay w h i c h , unfortunately, introduces a nonlinearity. T h i s nonlinearity is negligible i f the loop delay is m u c h smaller t h a n the n o m i n a l sampling interval. K o i z u m i has suggested methods to eliminate the nonlinearities created by loop delay i f loop delay is comparable to the sampling i n t e r v a l [53]. F o r the experimental unit, these methods were not necessary. The operation of the F S M is as follows. The F S M remains i n its idle state (63) u n t i l a sampling pulse from the N C O triggers a new sequence. The F S M signals the A D C s to acquire a new sample w h i l e the a control signal is sent to the data controller to increment the k count w h i c h is then 60 Chapter 4: Testing Environment of the MDTL passed to the phase error function lookup tables. T h e F S M increments unconditionally through the various states while asserting the appropriate signals at the proper times. W h e n the F S M returns to its idle state, i t is ready to receive a new s a m p l i n g pulse from the N C O . I n addition, the reset signal, w h e n asserted, overrides the s a m p l i n g pulse a n d h a l t s the execution of the loop. The F S M i m m e d i a t e l y goes into its idle state a n d remains there u n t i l the reset signal is negated. Table 4.1 enumerates the actions performed by the F S M at the given states. These state values were determined by the propagation delays of the various components. State N o . Actions Performed 0 S i g n a l data controller to increment 'k' count. A s s e r t s a m p l i n g signal to the A D C . 13 Negate s a m p l i n g signal. 40 L a t c h data from A D C into the resolution selector. 50 L a t c h data into the accumulator. S i g n a l data controller to output filter coefficient G 2 . 53 L a t c h data into the loop filter output register. S i g n a l data controller to output filter coefficient G l . 59 A s s e r t load signals to the N C O down counter. 61 Negate load signals. Table 4.1: Actions Performed by the F S M . The data controller m u s t cycle through the various values of k depending on the value of A. T h e data controller also multiplexes the digital loop coefficients for the b a r r e l shifter. These outputs are triggered by the F S M at the appropriate time. In addition, a user-selectable signal is passed to the data controller to allow the user to select between a zero- or first-order digital loop filter. F i g u r e C.15 i n A p p e n d i x C shows the schematic layout of the sequencer. I n addition, the software listings for a l l P A L a n d P R O M designs required for implementation of the M D T L are listed i n A p p e n d i x C . 4.2.2 T e s t C o n f i g u r a t i o n A controlled test environment, s i m i l a r to the test configuration i n F i g u r e 4.1, was developed to test 61 Chapter 4: Testing Environment of the MDTL the functionality of the M D T L , a n d to evaluate its performance. F i g u r e 4.10 shows the functional block diagram of the M D T L along w i t h the supporting blocks needed to exercise the M D T L and to gather data. T h e test configuration consists of a d a t a source, a transmitter, a noise channel, the M D T L , the phase error reference circuit, a data acquisition unit, a n d finally, a personal computer to capture and analyze the data. T h e H P 1 6 4 5 A data error analyzer is a commercial u n i t capable of generating fixed a n d pseudor a n d o m b i t sequences at moderate data rates. T h e generated b i t sequence is modulated onto a 115.2 k H z carrier. T h e modulated carrier is corrupted by A W G N , a n d is passed to the A F E . S i m i l a r l y , a n u n m o d u l a t e d carrier w h i c h is synchronized to the modulated carrier is passed the to reference circuit i n order to obtain the exact value of the phase error. F i n a l l y , a data acquisition u n i t extracts the necessary information for subsequent analysis by the personal computer. Voltmeter F i g u r e 4.10: The Hardware Test Environment. A p p e n d i x C describes i n greater detail the design of the supporting h a r d w a r e a n d evaluates the hardware implementation. A photograph of the hardware i m p l e m e n t a t i o n is shown i n Figure 4.11. 4.2.3 C a l c u l a t i n g the Input S N R To calculate the receiver i n p u t S N R , i n the form of Ei/N , 0 a true r m s voltmeter was used to measure the power components of the modulated signal and the noise signal separately. received energy per b i t is given by 62 The Chapter 4: Testing Environment of the MDTL Figure 4.11: Photograph of the Hardware Implementation. V 2 E =PT = h where V Srmt c (4.13) b Jb represents the measured rms voltage of the modulated signal a n d / j is the b i t rate. S i m i l a r l y for the noise component, we have V 2 N = (4.14) 0 In where V , represents the measured r m s voltage of the noise signal and / „ is the noise equivalent nrm bandwidth. C o m b i n i n g equations (4.13) and (4.14) we obtain N V 2 0 63 f h Chapter 4: Testing Environment of the MDTL A K r o h n - H i t e (Model 3202) filter was configured as a n 8th-order bandpass filter and was used to b a n d l i m i t the noise spectrum. Consequently, the noise equivalent b a n d w i d t h was ap- proximately equal to the 3 d B b a n d w i d t h of the filter [70]. 64 Chapter 5 Performance Evaluation Three M D T L performance measures are presented i n this chapter w h i c h include phase error distributions, acquisition times a n d hold-in times. F o r a l l three cases, a test procedure is defined and results from the software s i m u l a t i o n a n d the h a r d w a r e i m p l e m e n t a t i o n are presented. 5.1 Phase E r r o r Statistics To obtain v a l i d phase error statistics, i t i s necessary to identify the two types of error components encountered d u r i n g the t r a c k i n g process. T h e first error component is phase error j i t t e r due to channel noise or modulation distortion. T h e second error component is the Cycle Slip which is a phase j u m p b y m u l t i p l e s of 2ir/M. Cycle slips are due to either excessive levels of noise or channel interruptions, both of w h i c h typically cause catastrophic failure. A s a r e s u l t of these two error components, the phase error process i n the M D T L undergoes diffusion a n d its variance becomes infinite i n the steady-state. A n i l l u s t r a t i o n of a Probability Density Function ( P D F ) for an unbounded phase error process is shown i n F i g u r e 5.1. Pl<Pj M =l -An -2TC Figure 5.1: 271 An PDF of an Unbounded Phase Error Process. To overcome the problem of a n unbounded P D F , the phase error process is reduced b y applying the / [•] operator given b y E q . (3.23). T h i s modulo 2ir reduction results i n a phase error process w h i c h is stationary a n d possesses a bounded variance. Reducing the phase error modulo 2n is 65 Chapter 5: Performance Evaluation analogous to r e a d i n g the phase error process off a phase meter. T h e net effect is a phase error process w h i c h undergoes diffusion over a bounded closed i n t e r v a l . The amount of phase error jitter determines the accuracy i n w h i c h the recovered signal is formed. I n carrier recovery, the reduced phase error process is typically characterized by i t s first a n d second moments [711. A n example on the application of moments is i n the calculation of the p r o b a b i l i t y of b i t error for a suppressed-carrier B P S K signal. I f the phase error varies r a p i d l y over the symbol i n t e r v a l , the average b i t error probability P , can be approximated b y a p p l y i n g [2] e (5.1) (cos ip) ierfc where erfc [•] i s the complementary error function. Consequently, imperfect synchronization i n t h i s case causes a n S N R degradation of ( c o s y ) . I n the results t h a t follow, the mean value a n d 2 the standard deviation of the reduced phase error process are measured. 5.1.1 Defining the Test Procedure The test procedure consists of obtaining a n exact value of the reduced phase error a n d c a l c u l a t i n g its first two moments. T h e s a m p l i n g process from the loop under test is used to sample undistorted inphase a n d quadrature signals from the reference circuit. T h e sampled references signals can be expressed as xrefk = y/2P sm 2-nk c (5.2) yrefk 2irk 'IP,, cos A The reduced phase error is extracted by passing xrefk a n d yrefk to a tan" operator followed 1 by a modulo operator to eliminate the effects of m u l t i - s a m p l i n g . Hence f[fk] = f tan" xrefk 2TI-A: . yrefk A (5.3) A s mentioned i n C h a p t e r Three, a n M - f o l d ambiguity exists whenever the carrier is to be recovered directly from modulation. E x a m p l e s of the phase error a m b i g u i t y while t r a c k i n g a 66 Chapter 5: Performance Evaluation B P S K signal is shown i n F i g u r e 5.2. T h i s figure was obtained by a p p l y i n g E q . (A.27) i n A p p e n d i x A . 3 a n d serves only as a n i l l u s t r a t i v e example. 0.8 r—, I i i i I i i i I i i i I i i i I i i i I i i i I i i i I i i i 0.7 -7t -371/4 -71/2 -7C/4 0 7C/4 Tt/2 371/4 71 f[%] Figure 5.2: Sample PDFs of the Reduced Phase Error for a BPSK Signal. T h e P D F s of / [<p ] show t h a t the loop can track, w i t h equal probability, to either the i n c o m i n g k signal w i t h a zero phase offset or a phase offset of ±TT. Several techniques exist to eliminate this ambiguity, i n c l u d i n g differential encoding techniques. 5.2 are periodic w i t h a period of 2x/M Note, however, t h a t the P D F s i n F i g u r e a n d can be reduced to eliminate the M - f o l d ambiguity. Hence, the reduced phase error sample q , can be expressed as k = qk + + modulo l} ' (5 4) where q lies w i t h i n the i n t e r v a l [-JJ, JY)- T h e value q is passed to a statistical routine w h i c h k k creates a h i s t o g r a m of the reduced phase error process. Once a l l the data is received, the sample m e a n q, a n d standard deviation a , are calculated, respectively, from q 1 N « = NJ2V 67 (5 - 5) Chapter 5: Performance Evaluation and N 9) N (5.6) • 5.1.2 Phase Error Results T h e P D F s of the reduced phase error q obtained by the software s i m u l a t i o n are shown i n Figure k 5.3. F o r each phase error measurement, a total of 2 x 10 samples have been accumulated i n order 5 to obtained a reasonable estimate of the sample m e a n a n d standard deviation of q . In F i g u r e 5.3 k (a), both A a n d B have been set to one; i n F i g u r e 5.3 (b), A is set to eight times oversampling and B is set to four. Note t h a t i n both cases, the P D F s of q for a given S N R are r o u g h l y equivalent k w h i c h indicates t h a t the degradation i n b i t error rates due to the phase offset of the recovered carrier w o u l d be roughly the same i n both cases. T h e advantages of oversampling, however, are the increased n u m b e r of samples for data extraction a n d a faster acquisition time w h i c h w i l l be shown i n § 5.2. ,B =4 o a _o 6 § fa 5 E„IN =10dB o a 3 >, o -l_L -it/2 -3TC/8 -ic/4 -7C/8 7C/4 3*8 Jt/2 -Ji/2 (a) Figure 5.3: PDFs of the Reduced Phase Error q Obtained from the Software Simulation. k 68 Chapter 5: Performance Evaluation T h e standard deviation a of the reduced phase error process is shown i n Table 5.1. Results q have been tabulated for input S N R s of zero, five, a n d ten d B a n d for different values of A a n d = oo d B , is also given to measure B. T h e case where no channel noise is present, that is E /N b 0 the effects of the modulation distortion which determines the upper bound on the performance of the loop. F o r each phase error measurement, the r e s u l t i n g m e a n phase error q, was l i m i t e d to r o u g h l y ± 3 ° , t h a t i s |g| < 0.05 rad B= 1 (5.7) B= 4 SNR (dB) A =l A =2 A= 4 A =8 0 0.276018 0.326127 0.180351 0.248730 5 0.138774 0.167653 0.113793 0.149561 10 0.075010 0.100710 0.069710 0.089343 infinite 0.015670 0.024599 0.016828 0.037347 Table 5.1: Standard Deviation <r (in Radians) of the Reduced Phase Error Process as a Function of A, B and E /N . q b F o r a l l cases i n Table 5.1, i n c r e a s i n g E /N b 0 0 decreases o- . Note, however, t h a t increasing q A while k e e p i n g B constant results i n a slight increase i n a w h i l e i n c r e a s i n g the loop g a i n B q decreases a . T h e increase i n a , as a r e s u l t of m u l t i - s a m p l i n g , is due to the b a n d l i m i t e d inphase q q and quadrature arms w h i c h causes the phase error samples to become increasingly correlated. Consequently, the amount of useful information available to the loop is reduced. Increasing the b a n d w i d t h of the inphase a n d quadrature arms w o u l d reduce the a m o u n t of correlation between samples b u t w o u l d increase the amount of noise from the channel. These two conflicting requirements suggests t h a t there exists a n o p t i m u m b a n d w i d t h for a p a r t i c u l a r S N R a n d values of A a n d B for w h i c h a is m i n i m i z e d . T h e amount of available b a n d w i d t h a n d constraints w h i c h are q imposed on the real-time processing of the M D T L , u l t i m a t e l y l i m i t the amount of m u l t i - s a m p l i n g , and provide a p r a c t i c a l upper l i m i t for A. 69 Chapter 5: Performance Evaluation It is i n t e r e s t i n g to compare cr at zero d B for both A = B = 1 (Kim's D T L [14]) w i t h the case q A = 8, 5 = 4. O u r M D T L has a smaller standard deviation t h a n K i m ' s a n d is able to extract eight times as m a n y samples. A s the S N R increases, our M D T L h a s a comparable yet bigger standard deviation t h a n K i m ' s D T L w h i c h suggests t h a t m u l t i - s a m p l i n g performs better for A W G N t h a n for m o d u l a t i o n distortion. Probability Mass Functions ( P M F ) s of the reduced phase error q obtained by the The k h a r d w a r e implementation are shown i n F i g u r e 5.4. F o r each phase error measurement, a total of 1 x 10 samples were accumulated into a 128-bin histogram. T h e plots shown are for the case 7 A = B = 1. I n F i g u r e 5.4 (a) four bits of sampler quantization a n d a n N C O resolution of 256 levels were used. I n F i g u r e s 5.4 (b) a n d (c), eight bits of sampler quantization a n d a n N C O resolution of 1024 levels were used. 0.2 7 - 0.175 6 - 0.15 5 j- 0.12S 4 3 2 F- § 0.075 0.05 0.025 0 TTT TTT l|IM|IM|lll|.IL E IN =0dB _ : : : b E ; o : r E : : E II J I U -_L z 0.2 TTT TTT TTT T T T j n i | II 1 | 1 ITJTTT 0.2 0.175 E IN =5dB -E 0.175 0.15 # 0.125 ? 0.075 0.05 0.025 0 E b - : E E : : ; E E 0.15 # 0.125 § 0.075 0.05 0.025 II, XU. ILL TTTTTTTTT 1 (b) II | II 1 | 1 II | II 1 | 1 1 L I : : : - i 11 E IN =10dB ~ b a ; : : 1 E E E : -UJJ.JJ-nlA (a) Figure 5.4: 0 In 0 I M J_L it/4 TI/2 (c) PMFs of the Reduced Phase Error q Obtained from the Hardware Implementation. k A scale of the P D F shown i n F i g u r e 5.3 is placed alongside the scale of the P M F . T h e scaling factor needed to convert the P M F to a P D F i s the inverse of the w i d t h of the b i n , t h a t is 128/TT, w h i c h is approximately 40. A l t h o u g h the P M F s i n F i g u r e 5.4 resemble those found i n F i g u r e 5.3 (a), two features d i s t i n g u i s h the hardware results from software results. T h e first feature is the m e a n phase error w h i c h deviates from zero as the S N R decreases or as sampler quantization becomes coarser. T h e deviation from the m e a n phase error suggests t h a t a first-order loop filter is needed even i f frequency d e t u n i n g is absent. T h e second feature is increased variance between adjacent phase error samples, w h i c h seems to indicate t h a t the loop favors certain phase error 70 Chapter 5: Performance Evaluation values more t h a n others. It is unclear at the moment i f this second feature poses any loop performance problems. T h e standard deviation of the reduced phase error process was measured for various sampling, quantization and N C O resolution values. T h e results are shown i n F i g u r e 5.5. I n a l l four cases, the h o r i z o n t a l line above zero indicates the standard deviation obtained from the software simulation. Two sources of error were thought to contribute into the increased standard deviation of the reduced phase error i n the h a r d w a r e implementation. These error sources are truncation and phase error j i t t e r introduced by non-orthogonal inphase a n d quadrature arms. In F i g u r e 5.5 (a), for a particular N C O resolution, there is no appreciable difference i n a w h e n q either four, six, or eight bits of quantization is used. Decreasing the N C O resolution increases cr d r a m a t i c a l l y , w h i c h suggests t h a t a q q is more sensitive to changes i n the N C O resolution. Note t h a t <r is near zero when the number of s a m p l i n g bits is two a n d the N C O resolution is q set to 1024 levels. T h i s interesting phenomenon can be explained i f we consider the source of i m p a i r m e n t w h i c h , i n this case is simply modulation distortion. T h e coarse quantization ignores the discrepancies introduced by the modulation distortion a n d thus, the s a m p l i n g i n t e r v a l , which has a h i g h resolution, remains constant. T h e results i n F i g u r e 5.5 (b), are s i m i l a r to those i n F i g u r e 5.5 (a) except that the hardware i m p l e m e n t a t i o n was not able to achieve the same level of a q than the software simulation. The reason for this anomaly is believed to be the l i m i t a t i o n s of the digital loop filter a n d the phase j i t t e r introduced b y the m u l t i - s a m p l i n g . The digital loop filter truncates the error samples and hence introduces a nonlinearity. In addition, i t is shown i n A p p e n d i x C.2 that the inphase a r m lags its true position by approximately 9.5° and consequently, an error is introduced i n the estimation of the phase error. T h e increase i n a q due to these two sources of i m p a i r m e n t , prevented the loop from a c h i e v i n g lock at S N R values of zero and five d B w i t h A = 8, B = 4. T h e problem can be solved by u s i n g a better filter design w h i c h eliminates truncation and by assuring true orthogonal inphase a n d quadrature arms. F i g u r e 5.5 (c) shows the case where A = B — 1 at E /N b Q = 0 d B . T h e h o r i z o n t a l line at cr = 0.907 is the standard deviation of a uniformly distributed phase error distribution which q indicates the loop's i n a b i l i t y to achieve lock and can be seen w h e n two bits of sampler quantization 71 Chapter 5: Performance Evaluation Q- ^ 0.2 •- 0.2 -- 0.15 -- 0.15 -- _ ^ E /N = oo dB b 0 A = 8,B=4 V- -O 6 8 B .2 '•3 '•5 a 0.1 -- OS 0 0.1 •Q O- -••B~. 0.05 -- _ -e-- 0.05 •e =Q- R 2 + 4 6 48 2 -f- 4 Sampler Quantization (Bits) Sampler Quantization (Bits) (a) (b) NCO Resolution N = 16 N = 64 M = 256 N = 1024 0.6 •- (« 0.6 -- c« C 0.6 •- 2 '•3 a •o « b 0.2 -- E /N =0dB A = 2,B = 1 b 2 4 6 8 2 Sampler Quantization (Bits) -44 o 6 Sampler Quantization (Bits) (d) (c) F i g u r e 5.5: Standard Deviation a as a Function of the Number of Sampler Quantization Bits and the NCO Resolution. q were used. T h e measured results w h i c h y i e l d the lowest a q occur when four bits of sampler quantization along w i t h a n N C O resolution of 64 levels are used. 72 It should be noted that i n Chapter 5: Performance Evaluation some cases the measured standard deviation was lower t h a n the results obtained i n the software simulation. T h i s is due to the measurement of the S N R whose accuracy is l i m i t e d to ± 1 d B . In F i g u r e 5.5 (d), increasing A from one to two provides s i m i l a r results as those found i n F i g u r e 5.5 (c) w i t h the exception of a n increase i n the m i n i m u m standard deviation obtainable. T h i s again m a y be due to the phase j i t t e r introduced by the non-orthogonality between the inphase and quadrature arms. 5.2 A c q u i s i t i o n Statistics A closed-form expression for the acquisition time was developed i n C h a p t e r Three. T h e acquisition time was derived from the phase error difference equation i n the absence of a n y phase error disturbance. I n the presence of noise, the acquisition time becomes a r a n d o m variable a n d at present, no k n o w n theory exists to predict its behaviour. F o r a n y acquisition t r i a l , one of three events occur. T h e first event results w h e n lock conditions are not m e t a n d loop never locks. T h e second event is w h e n the loop false locks, w h i c h results i n the phase detector output becoming periodic for a l l time. T h e t h i r d event i s w h e n lock conditions are m e t after some time i n t e r v a l . T h e statistical properties of the t h i r d event are investigated i n this section. In the results t h a t follow, the Cumulative Density Function ( C D F ) of acquisition time for a p a r t i c u l a r loop configuration is used to characterize the behaviour of the loop i n the acquisition mode. F r o m this distribution, the mean time to acquire lock a n d i t s standard deviation can be calculated. I n current engineering practice, the time r e q u i r e d to obtain lock w i t h a n acquisition probability of 0.9, for example, is used as a specification of loop performance. T h i s information can also be acquired from the C D F . In addition to the results from software s i m u l a t i o n a n d hardware implementation, results from the closed-form expression for the acquisition time are presented. O u r purpose is to verify the v a l i d i t y of the closed-form expression w i t h the results obtained from the software simulation and h a r d w a r e implementation, a n d to identify the effects of modulation distortion on acquisition time. 73 Chapter 5: Performance Evaluation 5.2.1 Defining the Test Procedure The test procedure consists of s t a r t i n g the execution of the loop at some r a n d o m time a n d obtaining the acquisition time for that p a r t i c u l a r t r i a l . T h e test is repeated u n t i l a sufficient n u m b e r of acquisition trials have been accumulated. A s denned i n C h a p t e r Three, the acquisition process is t e r m i n a t e d at the fcth s a m p l i n g instant w h e n \fk where <p ss (5.8) ~ fss\ < fe is the steady-state mean phase error a n d ip is the acquisition l i m i t . T h e instantaneous c phase disturbance 6 ( t ) is simply a phase offset w h i c h is uniformly distributed between [—ic, ic). Frequency d e t u n i n g i s not present since the i n c o m i n g 115.2 k H z carrier frequency is m i x e d down precisely to 19.2 k H z a n d consequently, f , equals zero. T h e reduced phase error i p s k is obtained u s i n g equations (5.2) a n d (5.3) a n d is further reduced due to the M - f o l d a m b i g u i t y u s i n g E q . (5.4). Hence, the acquisition process i s t e r m i n a t e d at the fcth s a m p l i n g i n s t a n t i f l?fc| < f e (5.9) where the acquisition l i m i t (p is set to 7 r / 3 2 M w h i c h corresponds to a n acquisition l i m i t of c approximately ± 3 ° . The following a l g o r i t h m was used to perform the acquisition test. T h e loop under test a n d the test procedure were grouped into one executable block. T h e inputs to the block are the inphase and quadrature samples from the A F E under test a n d the inphase a n d quadrature samples from the reference circuit. T h e outputs of the block are the s a m p l i n g i n t e r v a l a n d the acquisition time n o r m a l i z e d to the mixed-down carrier cycle. Acquisition Test Algorithm While \ Input (x ,y ) and (xref ,yref ) k k k e = f [M ( t a n " Calculate k k 1 \ True [£*•] - / [2ifc])] Calculate / [ f ] = / [tan" [ f ^ ] - / [ ¥ ] ' 1 k Calculate q = k £ + {(/ [f ] + & ) modulo £ } k 74 Chapter 5: Performance Evaluation If {|«*| < f e } then Output Tjt = T + T 0 Output T Reset T rand acq acq = 0 Else Outputs = Update T ^ - ^ =T acq acq + Note t h a t the generation of the uniformly distributed i n i t i a l phase error is created by the test algorithm and not by the i n p u t signal whose phase offset remains constant. time variable T rand The random w h i c h is uniformly distributed between [0,T ) creates the i n i t i a l phase error o r e q u i r e d for every acquisition t r i a l . F i n a l l y , the acquisition time T acq is passed onto a statistical routine w h i c h calculates the mean acquisition time T , and the standard deviation a . T h e acq equations w h i c h generate T , and a acq acq are s i m i l a r to those used for the phase error statistics. acq 5.2.2 A c q u i s i t i o n Results T h e C D F s for the normalized acquisition time T acq obtained by the software s i m u l a t i o n are shown i n F i g u r e 5.6. A total of 1 x 10 acquisition trials were accumulated for every C D F plot. E a c h 5 g r a p h corresponds to a p a r t i c u l a r S N R , where A is set to one, two, or eight times oversampling. In F i g u r e 5.6 (a), the m e a n time T acq to acquire lock is 94.7 mixed-down carrier cycles when A = 1. W h e n A = 2, the mean time is roughly halved. Increasing A to eight decreases T by approximately a factor of eight. T h e standard deviation a acq acq undergoes the same reduction and is always s l i g h t l y less t h a n the mean time. T h e same decrease i n T acq F i g u r e 5.6 (b), (c) and (d). Furthermore, as the S N R increases, T acg and a acq appears i n decreases except w h e n no channel noise is present (see F i g u r e 5.6 (d)). T h i s exception w i l l be discussed i n greater detail at the end of this section. It should be noted t h a t increasing A while keeping B constant increases a . A s a n example, q at zero d B , i n c r e a s i n g A from one to two introduces a slight increase i n a as seen i n Table 5.1. q 75 Chapter 5: Performance Evaluation \ E IN = 0dB b o A = 1,B = 1 Gacq = 78.3 A=2,B = 1 Tacq = 46.2 Gacq = 39.4 A = 8,B = 1 0.125 0.125 Gacq = 10.1 1 11 1 1 50 . 100 150 200 250 ' 1 300 ' 1 350 400 25 50 75 (a) 0 20 40 60 80 100 125 150 175 200 250 300 350 400 (b) 100 120 140 160 0 50 100 150 (c) 200 (d) F i g u r e 5.6: Cumulative Distributions of the Acquisition Time Obtained from the Software Simulation for Different SNRs and Values of A. W h e n A = 8, o- increases to 0.5912 w h i c h i s more t h a n double the a value w h e n A = 1. T h e q q increase i n a is unacceptable a n d hence adjustment of the loop g a i n control B is necessary to q keep a at a n acceptable level. To complete the example, setting 5 = 4 w i t h A = 8 decreases a q q (see Table 5.1) while T acq = 49.7 a n d a acq — 39.5. Hence, w i t h appropriate values for A a n d B, the M D T L can reduce the phase error j i t t e r a n d decrease the acquisition time. L o w acquisition time a n d low phase error tend to be conflicting requirements. A s a first approximation, the mean 76 Chapter 5: Performance Evaluation time r e q u i r e d to acquire lock when u s i n g m u l t i - s a m p l i n g w i t h respect to the m e a n time without m u l t i - s a m p l i n g can be expressed as 1£ T q ac & Tacq ("'«'> (5.10) A=B=i) T h e C D F s of the acquisition time obtained b y the h a r d w a r e i m p l e m e n t a t i o n are shown i n F i g u r e 5.7. T h e dashed curves represent the case where eight bits of sampler quantization a n d a n N C O resolution of 1024 levels are used. T h e dotted curves represent the case where four bits of sampler quantization a n d a n N C O resolution of 64 levels are used. F o r each h a r d w a r e plot, a total of 1 x 10 acquisition trials were measured. T h e solid curves represent the results obtained 5 by the software s i m u l a t i o n a n d are used as a reference for the h a r d w a r e results. In F i g u r e 5.7 (a), where Et,/N 0 = 0 dB a n d A = 1, the hardware plot for eight s a m p l i n g bits is comparable to the results obtained b y the software simulation a n d the difference can be considered to be negligible. W h e n u s i n g four s a m p l i n g bits, however, a n increase i n the acquisition time is observed. T h i s increase is the result of a n N C O resolution w h i c h m a y be to s m a l l for the acquisition l i m i t specified. A s i m i l a r affect occurs i n F i g u r e 5.7 (b), (c) a n d (d). Note t h a t i n F i g u r e 5.7 (c) a n d (d), the hardware results seem to be better t h a n the software results. T h e slight discrepancy is thought to be due to the inaccuracy of the S N R measurement. A comparison between the closed-form expression for the acquisition time derived i n C h a p t e r Three a n d the results obtained from both the software s i m u l a t i o n a n d the h a r d w a r e implementation for the case where no channel noise is present is shown i n F i g u r e 5.8. I n F i g u r e 5.8 (a), w i t h A = 1, we see that a l l three graphs agree very closely u n t i l n reaches roughly 45 cycles. k A t that point, both the hardware a n d software results diverge from the theoretical result. T h i s divergence is due to the modulation distortion w h i c h is still present i n the loop a n d w h i c h causes hang-up. Hang-up is defined as the phenomenon whereby the phase dwells near the unstable lockpoint of the phase detector characteristic for a n extended period of time. C l e a r l y , hang-up is worst w h e n ip = ir/2. A n interesting discussion on the phenomenon of hang-up for a sawtooth 0 phase detector can be found i n [721. T h e hardware plot i n F i g u r e 5.8 (a) is slightly better than the software s i m u l a t i o n whereas i n F i g u r e 5.8 (b), hang-up is almost completely eliminated i n the h a r d w a r e result. It is suspected 77 Chapter 5: Performance Evaluation 1 0.875 I I I 111 I i i i i i ^ // A a 6 2 5 0.875 64 NCO levels - / Cacq = 124.0 / - 0.75 _ Tala = 128.0 •* V/ - ^ *0 0.375 - O / ~- n E IN =0dB b A 0.125 - Software 0.25 Talq=94.7 = 1 0.125 Cacq = 78.3 i i i 1 1 1 i i i 1 11 // is - I i I 1 1 1 1 1 1 350 0.875 0.75 - 64 NCO level! : 0.625 C V/ f j $ : 0.375 SbUA/D - 1024 NCO level! _ Ta~cq = 49.7 - Cacq - 34.6 _ V/ - = 1,B 7^ = 1 O A = 2 , B I 1 1 1 1 40 : T , , , 40 i i i 80 1 120 = 1 i 80 i i I 1 1 120 160 i I I I I I 1 _ I I 160 200 MI 7J..X1.^ 1 11 240 - - 1 1 k - - Talq - = 25.4 - 7 SbUAID - 1024 NCO level! - Talq = 22.0 - V 320 0 - Cacq = 15.3 - V 0.25 " - */ I I 1 Cacq = 21.9 * Software E„/N =5dB 0 A Tacq = 2 , B = 1 ' 25.4 Cacq =17.1 1 1 64 NCO level! f 0.375 1 1 1 4 bit AID ¥/ 0.125 280 1 : it if il i-i iff 52.0 i i i ' ' ' • • = 46.2 aa = 1 /. - - Cacq = 34.0 -, - Cacq = 39.4 : - 0 A - = 46.3 b a* - Software E„/N =5dB 0.125 0.625 - 3/ 0.25 - SbUAID Software E IN„=0dB : = 62.8 Cacq = 60.7 - 1 O 0.75 _ - 5" * Tacq it it - _ Tacq I I I 0.875 // // lb' Cacq = 55.6 Cacq = 42.0 -I ........... ..(•H" 1 - - - (b) n i l i i i 57.3 = -- (a) I I I' M l - TaZ, - / - i 0 400 64 NCO leveh 1024 NCO level! /• M 0.375 o = 1,B - i/ - /• - J 0.25 1 1 1 : = 99.1 Cacq = 83.5 - I I I M L - - 1014 NCO levels 7^ 0.625 5" SbUAID 0 , 5 I I I 1 1 1 .«••*" /( : v/ 1 1 1 1 - 0.75 1 1 1 ' • • 20 1 • 1 40 1 1 60 1 80 ' 1 1 1 100 ' _ 11 1 120 140 160 (d) (C) F i g u r e 5.7: Cumulative Distributions of the Acquisition Time Obtained from the Hardware Implementation for Different SNRs and Values of A. that the increased phase jitter introduced b y the m u l t i - s a m p l i n g eliminates hang-up. I n addition, it seems t h a t hang-up is most severe w h e n no channel noise is present. moment w h y c h a n n e l noise helps to eliminate hang-up. 78 It is unclear a t the Chapter 5: Performance Evaluation I II • i; i i i 0.875 i * 1M l 1 - Ta~cq = 39.2 : 'I '• '/ \ij 0.5 0.625 Gacq =11-9 i i Hardware I V/ 8" Tacq = 57.7 JO o 0.375 0.25 0 0.125 i i i i i i 40 1 1 1 1 1 1 \ 1 1 1 1 1 1_ i _ L Theoretical t '- 1 / \ 1/ fa7q= 1 1 Hardware I 320 i i b i i 20 i 0 i 40 i i 7.72 1 1 Gacq =19.9 i i i i 60 i i I I I 1 I I 80 100 120 140 160 (b) (a) Figure 5.8: Gacq = Software Talq = 28.4 E lN =oodB A = 2,B = 1 B i 1 I I 80 120 160 200 240 280 19.6 Gacq = 5.95 Ta7q = 20.6 0.5 0.25 Gacq — 68.8 1 _ ? *0 0.375 _ 1 1 1 ii : Software 7^=69.4 E„/N = oodB A = 1.B = 1 / i 1 1 II ~- f£ Gacq = 47.2 i i i i i :l 0.75 Theoretical rr •i >i : 'A 0.625 I I I 0.875 ' St 1—1 £ 1 // 0.75 V/ i Cumulative Distributions of the Acquisition Time i n the Absence of A W G N . 5.3 Hold-In Statistics A s mentioned i n § 5.1, excessive levels of noise or channel interruptions causes synchronization failures at randoms points i n time, w h i c h forces the synchronization loop to cycle slip. I n physical terms, & Cycle Slip occurs w h e n the N C O eithers adds or drops a s a m p l i n g pulse relative to the n o m i n a l n u m b e r of s a m p l i n g instants i n the i n c o m i n g signal. Hold-In time is defined as the i n t e r v a l of time from acquisition to w h e n the first cycle slip occurs. T h e statistical properties of the hold-in time are investigated below. 5.3.1 D e f i n i n g the Test Procedure The test procedure consists of recording a n u m b e r of hold-in times to plot its C D F . T h e digital loop is assumed i n i t i a l l y to be locked onto the phase of the i n c o m i n g signal, that is tpo = 0. T h e hold-in time Th u terminates once the loop crosses a prespecified barrier for the first time. I n our 0 case, the prespecified barriers are the unstable nulls w h i c h are ±ir/M. In order to measure cycle slips, i t is necessary to u n d e r s t a n d h o w a slip occurs at the unstable n u l l . The phase error difference equation given by E q . (3.39) and plotted onto the discrete phase plot i n F i g u r e 5.9, provides a good means of investigating the slipping process. 79 Chapter 5: Performance Evaluation lower bound without noise with noise Figure 5.9: Discrete Phase Plane Plot of the MDTL in the Presence of Noise. T h e solid lines i n F i g u r e 5.9 represent the characteristic curve a n d the transformation line <Pk+i = <Pk- In the presence of noise, the range of values t h a t (fk+i can have for a p a r t i c u l a r value of tp is denoted by the shaded area. T h i s range can be determined by l e t t i n g the phase error k estimate e k equal its m a x i m u m and m i n i m u m value, that is e = / [M<p ] + ( k at <p = 0, T 0 hold terminates once <p crosses ±ir/M, k k k = ±ir. S t a r t i n g whose value is denoted by the square box centered about the origin. A magnification of the unstable n u l l reveals t h a t i n the absence of noise, the phase error process w i l l follow the trajectory l a i d out by the characteristic curve w h i c h is seen by the darker phase trajectory. In the presence of noise, the lighter phase trajectory illustrates an example of ip crossing the boundary. Unfortunately, <p is not available for measurement purposes. A t k k our disposal, however, is the reduced phase error sample q w h i c h , w h e n plotted onto a reduced k 80 Chapter 5: Performance Evaluation discrete phase plane plot, indicates a method i n w h i c h the hold-in time can be measured. The reduced discrete phase plane plot of the M D T L i n the presence of noise is shown i n F i g u r e 5.10. Figure 5.10: Reduced Discrete Phase Plane Plot of the MDTL in the Presence of Noise. In the case where the loop has not slipped, the difference between the consecutive reduced phase error samples is . Iff* — . K' it < —g~ (5.1D where K' = K — 1/32 since frequency detuning is not present. W h e n a slip occurs, however, the difference between consecutive reduced phase error samples is greater t h a n (5.11) which is indicated by the arrows i n F i g u r e 5.10. In the hardware implementation, E q . (5.11) may not necessarily be v a l i d since F i g u r e 5.10 represents the case of infinite quantization. K'ir/B, T h e ratio however, is never greater t h a n the half-width of the square box, t h a t is w/M. Hence, for the hold-in tests w h i c h were performed, the loop has slipped i f and only i f 81 Chapter 5: Performance Evaluation (5.12) The following a l g o r i t h m was used to perform the hold-in test. T h e loop under test and the test procedure were grouped into one executable block. T h e inputs to the block are the inphase and quadrature samples from the A F E under test and the inphase a n d quadrature samples from the reference circuit. T h e outputs of the block are the s a m p l i n g i n t e r v a l a n d the hold-in time normalized to the mixed-down carrier cycle. Hold-In Test Algorithm Calculate e = f [M (tan' [j*] - / [2ai])] 1 k Calculate / [ ] = / [tan" [ f £ f £ ] - / [ ^ ] ] 1 9K Calculate q = + {(/[<p ] + j j ) modulo^} k k Outputs = Update T i ho d = Thoid + % Set Flag = Hold Else Output T hold Reset T i ho d =0 • Set Flag = Acquire Else Update T hold =T hold + a. 82 Chapter 5: Performance Evaluation 5.3.2 H o l d - I n R e s u l t s Due to the length of time r e q u i r e d to obtain meaningful results for the hold-in tests, approximately 7500 hours for 1000 trials at zero d B , software results were not obtained. Furthermore, the complexity of the hold-in algorithm l i m i t e d the hold-in test i n the h a r d w a r e implementation to the case where A = 1. F i g u r e 5.11 shows the cumulative distribution for the hold-in time obtained from the h a r d w a r e implementation for the case, Ef,/N hold-in time Thoid a n d the standard deviation Ohou 0 = 0 dB a n d A = B = 1. B o t h the mean are roughly equal to 3.1 x 10 mixed-down 5 carrier cycles. 10 3 10 10 4 10 5 6 10 7 »* F i g u r e 5.11: Cumulative Distribution of the Hold-In Time Obtained from the Hardware Implementation for Eb/N = 0 dB and A = B = 1. 0 W h e n four bits of sampler quantization a n d a n N C O resolution of 64 levels are used, the ratio between the m e a n hold-in time a n d the mean acquisition time is approximately Th~o7d/TaT q 83 w 2500 (5.13) Chapter 5: Performance Evaluation which roughly states that, on average, for every bit used i n a block for acquisition, 2500 bits m a y be sent without a cycle slip occurring. O f course, i n engineering practice, more restrictive specifications are used. Consider for example, a r a n d o m access protocol where a block or groups of bits, is passed through the channel, at r a n d o m points i n time. W h e n a block is sent, the time required to obtain lock w i t h an acquisition probability of 0.9 m a y be used. A s a further specification, a probability of a cycle slip occurring w i t h i n the block m u s t be less t h a n 0.02. These specifications and others l i m i t the size of the block. It should be noted t h a t these specifications are applicable to systems where acquisition times and block length are important parameters. Such is the case i n r a n d o m access protocols. In other systems where acquisition times are less important, the synchronization loop is usually set to have a very narrow b a n d w i d t h a n d a relatively l o n g acquisition time. Once acquisition is complete, the length of time between cycle slips is extremely long. 84 Chapter 6 Conclusions 6.1 Summary of Research Results T h i s thesis has documented the analysis, design and testing of the M D T L for t r a c k i n g suppressedcarrier M - a r y P S K signals. H i g h e r levels of synchronization i n a communication system, such as word or frame synchronization, l e n d themselves easily to digital implementation. C a r r i e r synchronization, however, has yet to fully exploit the m a n y benefits of digital technology, p r i m a r i l y due to the awkwardness of implementation a n d lack of knowledge as to what the system parameters should be. T h i s thesis has characterized the M D T L w h i c h was chosen because of its superior performance over conventional D P L L s and because of its potential simplicity i n h a r d ware implementation. Since the early 1960's, digital techniques have been applied to carrier t r a c k i n g loops to eliminate the shortcomings of analog circuit elements. T h e benefits of digital technology are reliability, since circuit element performance does not degrade over time, and flexibility. In spite of these advantages, D P L L s have only recently been considered as a viable alternative to conventional analog P L L s , p r i m a r i l y because of the limitations i n speed of the digital circuit elements themselves. Today, because of the enhanced processing speeds of newer technologies, it possible to design a carrier t r a c k i n g loop for data rates above 100 kbps. T h e M D T L is an extension of K i m ' s D T L for suppressed-carrier recovery, w i t h the benefits of m u l t i - s a m p l i n g . B a s e d on a non-uniform s a m p l i n g mechanism and a tan" operator, the M D T L 1 has a phase characteristic w h i c h is piecewise linear, u n l i k e the conventional D P L L whose phase characteristic is sinusoidal. Consequently, the M D T L can be characterized by a l i n e a r difference equation w h i c h eliminates the approximations of nonlinearity seen i n the conventional D P L L . The l i n e a r difference equation also provides m a n y attractive features over the conventional D P L L . These include l o c k i n g conditions w h i c h are insensitive to variations i n signal power, enhanced 85 Chapter 6: Conclusions noise i m m u n i t y , w i d e r lock range a n d reduced steady-state mean phase error for the first order loop w h e n the received signal has a frequency offset. In the absence of noise, closed-form expressions of the steady-state m e a n phase error, the region of stability, the lock range a n d the acquisition time were derived for a first-order M D T L It is shown t h a t the use of m u l t i - s a m p l i n g improves the performance of the M D T L over the conventional D T L by increasing the region of stability and consequently, the lock range, a n d by decreasing the steady-state mean phase error and the acquisition time. In order to test the performance of the M D T L i n the presence of noise, both a software testbed and a h a r d w a r e testbed have been designed and implemented. T h e software testbed represents the reference model against w h i c h the hardware testbed can be compared and measured. The h a r d w a r e testbed includes other important i m p a i r m e n t s such as quantization effects a n d loop delay and represents an implementation w h i c h accurately reflects the performance degradation from the reference model. T h e phase error, acquisition time a n d h o l d - i n time are the three performance measures used to characterize the performance of the M D T L i n the presence of noise. F o r each measure, a well-defined test procedure is derived. The software results reveal that at zero d B , the M D T L has a smaller phase error standard deviation t h a n K i m ' s D T L a n d is able to extract eight times as m a n y samples. A s the S N R increases, the M D T L has a comparable yet larger phase error standard deviation t h a n K i m ' s D T L , w h i c h suggests t h a t m u l t i - s a m p l i n g performs better for A W G N t h a n for m o d u l a t i o n distortion. F u r t h e r m o r e , the m e a n acquisition time of the M D T L is roughly one h a l f t h a t of K i m ' s D T L . A s a first approximation, the decrease i n the m e a n time required to acquire lock w i t h m u l t i - s a m p l i n g w i t h respect to the m e a n time without m u l t i - s a m p l i n g is approximately a factor of B/A. The results obtained by the hardware implementation reveal t h a t for B P S K , four bits of sampler quantization a n d 64 levels of N C O resolution are needed to provide negligible performance degradation compared to the infinite quantization case at a received S N R of zero d B . Two sources of error were thought to contribute to the increased standard deviation of the reduced phase error i n the hardware implementation. These error sources are truncation of the phase error samples i n the digital loop filter and phase error j i t t e r introduced by non-orthogonal inphase and quadrature arms. B o t h these error sources can be m i n i m i z e d by a n enhanced h a r d w a r e design. 86 Chapter 6: Conclusions The MDTL design is simple. Digital implementation of the MDTL provides an opportunity for enhanced system integration using VLSI-ASIC techniques for high speed applications or DSP microprocessor techniques for slower speed applications. 6.2 Suggestions for Future Work The many attractive features which the MDTL possesses make it an ideal candidate for carrier recovery. Further research, however, is needed to exploit fully the possibilities of this system. The following is a list of suggestions for future work on the MDTL. The areas of research which, in the author's opinion, show the most promise are placed at the top of the list. • Design of the Data Extractor — Several forms of data extraction can be applied to the MDTL. Data can be extracted from the inphase arm or from the output of the tan' 1 operator. Due to the addition of data extraction, the bandwidths of the bandpass filters have to be adjusted accordingly, and Simon has suggested a method for optimizing these filter bandwidths [73]. • Analysis of Higher-Order Loops — The analysis of higher-order loops, particularly the second-order MDTL, should be investigated to determine its performance when the input signal has a constant or variable frequency offset. Chie, for example, analyzed a secondorder DPLL for Doppler rate tracking [74]. In addition, the use of nonlinear loop filters when coarse sampler quantization is used should be investigated. • VLSI Implementation — An interesting area of research is the digital implementation of carrier recovery loops for large scale integration. The problems typically associated with this area of research are the integration of analog and digital circuit elements, process technology, fault tolerance and detection and finally, design for manufacturability. The alternative to VLSI design is the implementation of the MDTL using commercially available microprocessors. Typically, the designer develops suitable carrier tracking algorithms which must meet real-time requirements. • Frequency Discriminators — It may be possible to design frequency/phase detectors that do not suffer from the problem of phase ambiguity. Messerschmitt has applied frequency detectors for PLL acquisition and has obtained good results [75]. 87 Chapter 6: Conclusions • Sub-Optimum Loops — T h e work on sub-optimum loop design is best applicable w h e n cost constraints are added to system specifications. F o r example, i t is possible to design a sub-optimum M D T L for t r a c k i n g suppressed-carrier signals w h i c h is based on one A D C s a m p l i n g four times per mixed-down carrier cycle. • Semi-Numerical Analysis — T h e solution to the Chapman-Kolgomorov equation for the P D F of the phase error process has limitations as to its applicability. These l i m i t a t i o n s are due to the increased correlation between noise samples as the s a m p l i n g rate is increased. It m a y be necessary to develop alternative n u m e r i c a l or semi-numerical methods to determine the effects of correlated noise samples. 88 References [I] J. J. Stiffler, Theory of Synchronous Communications. New Jersey: Prentice-Hall, 1971. [2] W. C. Lindsey and M. K Simon, Telecommunication Systems Engineering. New Jersey: Prentice-Hall, 1973. [3] L. E. Franks, "Carrier and bit synchronization in data communications - A tutorial review," IEEE Trans. Commun., vol. COM-28, pp. 1107-1121, Aug. 1980. [4] J. K Holmes, Coherent Spread Spectrum Systems, pp. 179-184. New York: Wiley, 1982. [5] A. J. Viterbi, Principles of Coherent Communications. New-York: McGraw-Hill, 1966. [6] J. P. Costas, "Synchronous communications," Proc. of the IRE, vol. 44, pp. 1713-1718, Dec. 1956. [71 S. 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L i n d s e y , " O p t i m u m performance of suppressed carrier receivers w i t h Costas loop tracking," IEEE Trans. Commun., v o l . C O M - 2 5 , pp. 215-227, Feb. 1977. [74] C . M . Chie, " A second-order frequency-aided digital phase-locked loop for doppling rate t r a c k i n g , " IEEE Trans. Commun., v o l . C O M - 2 8 , pp. 1431-1436, A u g . 1980. [75] D . G . Messerschmitt, "Frequency detectors for P L L acquisition i n t i m i n g a n d carrier recovery," IEEE Trans. Commun., v o l . C O M - 2 7 , pp. 1288-1295, Sept. 1979. 93 Appendix A Mathematical Derivations A.1 M o d u l o A r i t h m e t i c Theorem: L e t a a n d a be r e a l numbers, a n d let op be one of the following operators +, - or x 2 x. I n addition, let f[p] be a modulo function denned b y = -IT + {(fj. + 7r) modulo 2TT} f[p] (A.1) then f [ a o p a ] = f[f[a ] 1 2 opf[a }]. 1 (A.2) 2 Proof: We can w r i t e a — 2irk + r a = 2irk + r where k ,k x x lt 2 2 2 x are integers and r , r G [-it, 2 x 2 TT). For addition, / [ai + a ] = — 7r + {(ai + a + 7r) modulo 27r} 2 2 = + n) + (2ir^ + r ) + TT) modulo -TT + {((27T*! 2 2 2TT} = —7r + {(n + r + TT) modulo 27r} (A.3) 2 = /[ri + r ] 2 Q.E.D. * = /[/[«i] + /[a ]] 2 The same holds true for subtraction. F o r multiplication, / [ai x a ] — —TT + {(ai x a + 7r) modulo 2n} 2 2 = — 7T + {((2^^! + ri) x (2-rrk + r ) + TT) modulo 2TT} 2 2 = — 7r + {(27T (27rfc!fc + rifc 4- r k x ) + n r + it) modulo 27r} 2 2 2 = —7r + {(ri x r + 7r) modulo 2T} 2 (A.4) 2 = / [ri x r ] 2 = /[/[ai]x/[a ]] 2 Corollary: Q.E.D. o L e t a be a r e a l number, M be an integer a n d / [p] be denned by E q . ( A . l ) then x 94 Appendix A: Mathematical Derivations f [Mai] = / [Mf [ ]] CA.5) ai Proof: We c a n write ai = 27r&i + ri, then / [Mai] = f [2irMki + Mn] = f [M ri] (A.6) = f[Mf[ ]] Q.E.D. * ai A.2 M A P Estimate of an U n k n o w n Phase Angle Let x a n d y be defined, respectively, as k k x = Asm(z ) + r]k k k ( A > 7 ) y = A cos (z ) + rfk k where z k k is the uniformly distributed phase angle, p[z ] — l/2-ir z k k € [-7r,7r), a n d Tj ,rfk are k independent identically distributed G a u s s i a n noise samples w i t h zero mean a n d variance The probability of a correct decision for the phase angle is m a x i m i z e d i f p[z \x ,y ] k k (A.8) k is m a x i m i z e d for a given inphase a n d quadrature sample. F r o m Baye's rule w - i - Pi ^yk\zk]p[zk] p[zk\xk,yk\ = p ? x x (A.a; r A P and since the logarithm is a monotonically increasing function of its positive argument, m a x i m i z ing E q . (A.9) is equivalent to m a x i m i z i n g \n(p[z \x ,y ]) k k k = \n(p[x ,y \z ]) k k k + In (p[z ]) - ln (p [x , y ]). k k (A.10) k The second t e r m i n E q . (A.10) is a constant since z is assumed to be uniformly distributed, k and the t h i r d t e r m i s not a function of the phase angle. Consequently, m a x i m i z i n g E q . (A.9) w i t h respect to z is equivalent to m a x i m i z i n g the first term of E q . (A.10) w i t h respect to z . k k The j o i n t Probability Density Function ( P D F ) of x a n d y given z can be r e w r i t t e n as k 95 k k Appendix A: Mathematical Derivations (A.11) p[xk,Vk\zk] - Pr, [xk ~ Asin(zk) ,y - A cos (z ) \z ] k where p [•, •] is the j o i n t P D F of the noise samples r) , rjkv k k E q . ( A . l l ) , the dependence on z can m k k be discarded since the noise samples are assumed to be independent of the phase angle. F r o m Eq. ( A . l l ) , the joint P D F is given by Pr, [x - A sin (z ), yk - A cos (z )} k k k CA.12) S u b s t i t u t i n g E q . (A.12) into E q . (A.10), differentiating w i t h respect to z a n d setting the result k to zero, we obtain 1 d dz (x - Asm {z )f k + (y - A cos (z )) ^ 2 k k k k = (A.13) 2 [~x cos (z ) + y sin (z )} k k k k 0. S o l v i n g for z , we get k z — k tan- l x (A.14) k Vk T h u s , i t has been showned that the o p t i m u m M A P estimate of a uniformly distributed phase angle for a given p a i r of inphase a n d quadrature samples corrupted b y A W G N is the tan" operator. 1 In addition, the m a x i m u m likelihood estimator suggests t h a t the most unbiased estimate of the phase angle w h e n its P D F is u n k n o w n is given by the t a n 1 operator. A.3 Statistical Characteristics of the Phase Detector in the Presence of Noise We w i s h to obtain the P D F of the phase detector output e i n order to ascertain t h a t the phase k detector output can be w r i t t e n as ejb = / [M<p ] + ( k 96 k (A.15) Appendix A: Mathematical Derivations where / [Mfk] is the phase error estimate i n the absence of noise and 0t is a non-Gaussian noise process. G i v e n the inphase a n d quadrature samples 2irk + fk + f jb + Vk — (A-16) 2irk y = \/2pP cos + fk+€k + rfk A k c i t is assumed that the modulation distortion is independent of the channel noise. I n addition, since Vk a n d rjk are independent zero mean G a u s s i a n r a n d o m variables, Xk a n d yk are also m u t u a l l y independent r a n d o m variables for a given f w i t h means fc E [x ] = ^/2p~F sm k + <Pk+U c (A.17) (lick E bk] = VZpPc cos ( — + <p + f* k and variances var [x ] - var [j/*] = a*. (A.18) k If the P D F of f t , p [ik] is k n o w n , we can write the joint P D F of Xk, yk a n d ft as (A.19) P [Efc, yk, ft] = p [xk, y |f ] p [ft] fc fc where p[xjt,yjblfjt] m a y be w r i t t e n u s i n g Eqs. (A.17) a n d (A.18) as P [xk, y If fc] = —'--exp k • 1 2rck ^ ( - ^ - \/2p^sin ^—r- + fk+£k 27T(Tf1 (A.20) 2\ l + {yk - \/2pP cos ^^jp + - Vfc + f*^ c To determine p[^t] which is the output from the tan" function, we define a n e w random 1 variable R such t h a t x = Rs'm(z ), k y = Rcos(z ) k k 97 k (A.21) Appendix A: Mathematical Derivations where z e k [-T.TT) a n d R e [0,oo). T h e joint P D F p [z , R,£ ] is equal to k k p[zk,R,£k] = p[xk,yk,tk] • R- Therefore, the P D F of z can be calculated from E q s . (A.19) - (A.22) as k 7T P W =J -IT OO Jp[zk,R,tk] dR Lo IT i f a ( x exp ( - a sin ( z - - <p - £ 2 k x ( -+ r— erfV2a cos 27T& k i ( z 2irk — k k <Pk-£k where a is the i n p u t S N R defined as A pP c and erf (*) i - 7 = /e->' dy. /3 v^ J 0 To obtain the P D F of e , we perform a transformation of variables u s i n g k '2-irk 1 e* = / Mf Zk~ to give 98 f Appendix A: Mathematical Derivations Pe [e*] = — P z Mz + 2irn + k (A.27) exp x exp ({—a sin 7) x ( - + erf [\Pla cos 7] j df 2 k where T 17 [ * + = e 2 7 r n ~ Vk ~ M (A.28) Milk]. A l t h o u g h e is considered only i n the i n t e r v a l [—TT, 7T), the function p [e ] itself is periodic i n k e k e w i t h a period of 2T a n d has peaks occurring at e = f [Mtp ] k k + 2irn for a l l integer values of n. Hence, the phase error estimate consists of a noise-free estimate / [Mip ] k noise process £ w h i c h lies i n the i n t e r v a l [—TT — f [Mip ] k The k ,ir — f above analysis has assumed t h a t the P D F of fit, p[^ ] k k a n d a non-Gaussian [Mip ]). k is k n o w n . Unfortunately, i t is difficult k n o w the statistics of ft at non-uniform s a m p l i n g instants. N u m e r i c a l solutions, however, have been obtained by K i m [13]. 99 Appendix B Topology Files of the Simulated MDTL A n example of the topology files used for the s i m u l a t i o n of the M D T L is presented. T h e universe topology file lists the stars and galaxies needed for the s i m u l a t i o n a n d the parameters passed to the star and galaxy routines. The universe topology file is common to a l l three performance measures. E a c h performance measure is listed as a n i n d i v i d u a l galaxy file. 100 U N I V E R S E TOPOLOGY Author: Institution: Date: Filename: Purpose: t i Specify galaxy Jgalaxy •galaxy t t J o e l A. B i s s o n University of B r i t i s h Feb 11th, 1989 UNIVERSE.T Columbia To simulate the MDTL imbedded i n AWGN. N.B. UNIVERSE.T used f o r a l l t h r e e performance t e s t measure (one galaxy f o r each MDTL MDTL MDTL mdtlped.t mdtlacq.t mdtlhold.t # FILE measures. param star int DelayA 3 delay.s * param star int DelayB 3 delay.s * 1/4 o f 12 sample c y c l e # Phase s h i f t element (Reference) Specify local param param param param star int int int float LocalOscA 12000000 2400 12 1.4142 sinclk.s param param param param star int int int float LocalOscB 12000000 2400 12 1.4142 sinclk.s oscillators test) • Phase e r r o r d i s t r i b u t i o n s # Acquisition distributions * Hold-In d i s t r i b u t i o n s mixed-down 4th-order bandpass param param param star float float float SinMDFA 1152000.0 19200.0 19200.0 i i r _ 4 t h b p f .s t Sampling frequency t Center frequency star star Fork-AO Fork-Al fp_fork.s fp_fork.s t Fork-BO Fork-Bl fp_fork.s fp_fork.s param param param star float float float CosMDFA 1152000.0 19200.0 19200.0 i i r _ 4 t h b p f .s Specify bandpass param param param star float float float SinMDFB 1152000.0 19200.0 19200.0 i i r 4thbpf.s param star file BPF-A0 115.2k.coef iir_biquad.s param star file BPF-Al 115.2k.coef iir_biquad.s param param param star float float float COSMDFB 1152000.0 19200.0 19200.0 iir_4thbpf.s t Sampling frequency t Center frequency t Bandwidth t Quadrature arm ( C i r c u i t Under Test) t Sampling frequency t Center frequency t Bandwidth t Inphase arm (Reference C i r c u i t ) t Sampling frequency t Center frequency t Bandwidth t Quadrature arm (Reference C i r c u i t ) star star param star file BPF-B0 115.2k.coef iir^biquad.s param star file BPF-Bl 115.2k.coef iir_biquad. s Specify channel b e i n g used param param param star function float int ChannelA # Specify f filters * Bandwidth arm ( C i r c u i t Under Test) star star SinMultA CosMultA multiply.s multiply.s # inphase arm ( C i r c u i t Under Test) # Quadrature arm ( C i r c u i t Under Test) star star SinMultB CosMultB multiply.s multiply.s # inphase arm (Reference C i r c u i t ) # Quadrature arm (Reference C i r c u i t ) f Specify phase s h i f t e r s T o t a l number o f samples generated Output 2400 samples p e r b l o c k c a l l 12 samples p e r p e r i o d Peak amplitude of t h e s i n u s o i d L o c a l O s c i l l a t o r (C.U.T.) t i t i From b p f t o m u l t i p l i e r s (C.U.T.) From l o c a l o s c i l l a t o r t o m u l t i p l i e r s T o t a l number o f samples generated Output 2400 samples p e r b l o c k c a l l 12 samples p e r p e r i o d Peak amplitude of t h e s i n u s o i d L o c a l O s c i l l a t o r (Reference) * From b p f t o m u l t i p l i e r s (Reference] From l o c a l o s c i l l a t o r t o m u l t i p l i e r s f i l t e r s p r e c e d i n g AFE multipliers * t t t i t t t t t i Speci fy forks Specify Inphase 1/4 o f 12 sample c y c l e Phase s h i f t element (C.U.T.) ranl.c 5.477225575 -4764532 awgn.s t t t t t t t t C o e f f i c i e n t s f o r 115.2 kHz c f , Q = 2 1st cascaded f i l t e r (C.U.T.) t t t t Random no. generator ('C f i l e ) Standard d e v i a t i o n of n o i s e (0 dB) I n i t i a l seed Channel (C.U.T.) C o e f f i c i e n t s f o r 115.2 kHz c f , Q •= 2 2nd cascaded f i l t e r (C.U.T.) C o e f f i c i e n t s f o r 115.2 kHz c f , Q = 2 1st cascaded f i l t e r (Reference) C o e f f i c i e n t s f o r 115.2 kHz c f , Q = 2 2nd cascaded f i l t e r (Reference) # Specify BPSK modulators f param param param param star int default default int ModulatA param param param param star int default default int ModulatB 10 12 pskgen.s 10 12 pskgen.s t f t * i No. of samples per cycle Infinite quantization Zero phase offset No. of cyles per b i t BPSK modulator (C.U.T.) i t * * * No. of samples per cycle Infinite quantization Zero phase offset No. of cycles per bit BPSK modulator (Reference) int int SourceA 100000 -4231934 prbs.s * T o t a l no. of b i t s generated * I n i t i a l seed t PRBS generator (C.U.T.) t LocalOscB Fork-Bl Fork-Bl DelayB SinMultB CosMultB SinMDFB CosMDFB 0 0 1 0 0 0 0 0 Fork-Bl SinMultB DelayB CosMultB SinMDFB CosMDFB MDTL MDTL G A L A X Y TOPOLOGY f # Specify pseudo bit sequence param param star connect connect connect connect connect connect connect connect t t t t t i t t Author: Institution: Date: Filename: Purpose 0 1 0 1 0 0 2 3 F I L E FOR P H A S E ERROR TESTS Joel A. Bisson University of British Columbia Feb 12th, 1989 MDTLPED.T To generate phase error distributions and s t a t i s t i c s . # Specify zero bit sequence param star int SourceB 100000 zero.s t Total no. of bits generated * Zero bit sequence (Reference) t t * • Specify interconnection of blocks for the Circuit Under Test t connect connect connect connect connect connect connect connect connect connect connect connect connect connect connect SourceA ModulatA ChannelA BPF-A0 BPF-A1 Fork-AO Fork-AO LocalOscA Fork-Al Fork-Al DelayA SinMultA CosMultA SinMDFA CosMDFA 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 ModulatA ChannelA BPF-A0 BPF-A1 Fork-AO SinMultA CosMultA Fork-Al SinMultA DelayA CosMultA SinMDFA COSMDFA MDTL MDTL 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 t t t t t t S p e c i f y i n t e r c o n n e c t i o n of b l o c k s f o r the Reference C i r c u i t connect connect connect connect connect connect SourceB ModulatB BPF-BO BPF-B1 Fork-BO Fork-BO 0 0 0 0 0 1 ModulatB BPF-BO BPF-B1 Fork-BO SinMultB CosMultB 0 0 0 0 0 0 Specify s t a t i s t i c a l routines param param param param param param param star float float int int int int default Statl -3.1415926535 +3.1415926535 255 0 1 0 param param param param param param param star float float int int int int default StatO -3.1415926535 +3.1415926535 255 0 1 0 fp histogram, s Specify MDTL and Test circuit param param param param param star t fp histogram, s * Minimum bound i Maximum bound * No. of bins * Hide empty bins = OFF t Cumulative distribution = ON t Normalized distribution = OFF t Output f i l e i s 'stdout' t Histogram routine for phase error t Minimum bound t Maximum bound t No. of bins t Hide empty bins = OFF t Cumulative distribution = ON t Normalized distribution « OFF i Output f i l e i s 'stdout' t Histogram routine for error signal int int int float float Test 2 8 4 19200.0 0.03125 ctpeddtl.s t t t t t t M = 2, BPSK A = 8, multisampling B = 4, loop gain Mixed-down carrier frequency Normalized d i g i t a l loop f i l t e r coef. Star File i Specify samplers param star t 64 1152000.0 19200.0 fastctsampler.s t t t t i t i i No. of reconstruction samples Sampling frequency Mixed-down carrier frequency Samplers for (Reference) fp_fork.s i From Test to samplers param param param star int float float Samplers 64 1152000.0 19200.0 fastcts ampler. s param param param star int float float SamplerB No. of reconstruction samples Sampling frequency Mixed-down carrier frequency Samplers for (C.U.T.) Fork O CO input input input input SamplerA SamplerA SamplerB SamplerB Test Fork Fork Test Test 0 1 2 3 0 1 0 1 0 0 1 1 2 SamplerA SamplerA SamplerB SamplerB Test Test Test Test Fork SamplerA SamplerB StatO Statl * Output f i l e i s 'stdout' # Cummulative routine for acq. time t param param param param param param param star int int int float float int float Test 2 2 1 19200.0 0.03125 -789324 0.04908739 ctacqdtl.s * M = 2, BPSK t t i t t t A = 2, multisampling B = 1, loop gain Mixed-down carrier frequency Normalized d i g i t a l loop f i l t e r coef I n i t i a l seed for 'k' count Acquisition limit (2.8125 degrees) • Star File Specify samplers Specify the interconnections of the blocks connect connect connect connect connect connect connect connect connect connect connect connect connect acummulate.s t Specify MDTL and Test circuit Specify fork star default Stat 0 1 0 1 0 1 2 3 0 2 2 0 0 param param param star int float float SamplerA 64 f No. of reconstruction samples 1152000.0 t Sampling frequency 19200.0 t Mixed-down carrier frequency fastcts ampler. s i Samplers for (C.U.T.) param param param star int float float SamplerB 64 1152000.0 19200.0 fastctsampler.s t t t t No. of reconstruction samples Sampling frequency Mixed-down carrier frequency Samplers for (Reference) fp_fork.s t From Test to samplers Specify fork star Fork Specify the interconnections of the blocks GALAXY * t t t t t Author: Institution: Date: Filename: f t Purpose: * TOPOLOGY F I L E FOR ACQUISITION Joel A. Bisson University of British Columbia Feb 20th, 1989 MDTLACQ.T To generate acquisition distributions and statistics. • • Specify s t a t i s t i c a l routines t param param int int 10000 256 t Total no. of entries # No. of bins TESTS connect connect connect connect connect connect connect connect connect connect connect connect input input input input SamplerA SamplerA SamplerB SamplerB Test Fork Fork Test 0 1 2 3 0 1 0 1 0 0 1 1 SamplerA SamplerA SamplerB SamplerB Test Test Test Test Fork SamplerA SamplerB Stat 0 1 0 1 0 1 2 3 0 2 2 0 G A L A X Y TOPOLOGY F I L E FOR HOLD-IN TESTS t t Author: Joel A. Bisson t Institution: University of British Columbia * Date: Mar 1st, 1989 * Filename: MDTLHOLD.T # t t Purpose: To generate hold-in distributions and statistics. t t t Specify statistical routines 4 param param param param param param param star float float int int int int default StatO 0.0 1000000.0 100000 1 0 0 int int int float float float Test * t t fp histogram.s t 1 1 1 19200.0 0.03125 0.04908739 ctholddtl.s Minimum bound Maximum bound No. of bins Hide empty bins - ON Cumulative distribution « OFF Normalized distribution = OFF Output file is 'stdout' Histogram routine for hold-in int float float SamplerA int float float SamplerB t M » 2, CW f A - 1, multisampling * B = 1, loop gain i Mixed-down carrier frequency * Normalized digital loop filter coef. t Acquisition limit (2.8125 degrees) * Star File 64 t No. of reconstruction samples 1152000.0 t Sampling frequency 19200.0 t Mixed-down carrier frequency fastcts ampler s t Samplers for (C.U.T.) 64 t No. of reconstruction samples 1152000.0 t Sampling frequency 19200.0 t Mixed-down carrier frequency fastctsampler s #Samplers for (Reference) Specify fork star Fork fp_fork.s input input input input SamplerA SamplerA SamplerB SamplerB Test Fork Fork Test SamplerA SamplerA SamplerB SamplerB Test Test Test Test 0 Fork 0 SamplerA 1 SamplerB 1 Stat S PL to Q ft. I 3 t t Specify samplers * param param param star param param param star connect connect connect connect connect connect connect connect connect connect connect connect •a 3- t t t t t Specify MDTL and Test circuit t param param param param param param star * Specify the interconnections of the blocks t t From Test to samplers Appendix C Details of the Hardware Design In this appendix, • a functional description of the supporting hardware needed for the test configuration is described; • an evaluation on the functionality of the test configuration is provided; and • schematic diagrams of the hardware design and program listings for the programmable devices are given. C.l Functional Description of the Supporting Hardware The supporting hardware for the MDTL consists of a transmitter, a noise channel, a phase error reference circuit and a data acquisition unit. C.l.l The Transmitter The transmitter generates PSK waveforms subject to different data rates, pulse shapes and digital baseband formats. The purpose of this effort is to provide a flexible transmitter circuit in order to ascertain the functionality of the MDTL. To generate these many signals, the transmitter system is based on a stored-waveform mechanism. Figure C.l shows the block diagram of the transmitter. The transmitted signal is generated by an eight-bit lookup table. The output of the lookup table is passed to a Digital-to-Analog Converter (DAC) whose output signal is amplified and then sent directly to the receiver for testing purposes or to the channel via a BNC connector. The lookup table contains a generalized sine wave function, that is s = {A )sm{6 ) n n 105 n (C.l) Appendix C: Details of the Hardware Design Window Functions Lookup F i g u r e C l : Block Diagram of the Transmitter, where A n is a seven-bit value representing the amplitude information a n d 6 is a seven-bit value n representing the phase information. B y v a r y i n g the values of A„ a n d $„, i t is possible to generate the waveforms needed for testing. To create the desired 115.2 k H z carrier frequency, the local oscillator of the transmitter is 2 7 b l t s = 128 times the carrier frequency or 14.7456 M H z . T h e phase sequence is created by a programmable P A L counter whose i n i t i a l count value, at the b e g i n n i n g of every carrier cycle, is loaded from a digital baseband formatter P A L . T h e formatter converts the i n c o m i n g pseudor a n d o m N R Z - L b i t sequence from a n external data source to the three most significant bits of the i n i t i a l count value. These three bits divide 2TT into eight uniform sections thus creating the necessary phase information. T h e lower four bits of the i n i t i a l count value determines the phase offset a n d is selectable v i a D I P switches. Several w i n d o w i n g functions have been stored into a P R O M i n order to generate the amplitude sequence. T h i s amplitude information is indexed v i a a n amplitude counter a n d is passed to the upper seven bits of the sine wave lookup table. A divide-by-N P A L determines the period of the amplitude window w h i c h is dependent on the data rate. A t present, the pulse shape m e c h a n i s m is used for B P S K s i g n a l l i n g only. Table C l lists the features of the t r a n s m i t t e r w h i c h are D I P switch selectable. F i g u r e C.16 shows the schematic d i a g r a m of the transmitter. 106 Appendix C: Details of the Hardware Design Selectable Formats Modulation CW, BPSK, QPSK, 8-PSK Data Rate 600, 1200, 2400, 4800, 9600, 19200, 28800 bps. Baseband Signalling NRZ-L, NRZ-M, NRZ-S, RZ, Biphase-L, Biphase-M, Biphase-S, Delay Mod Pulse Shaping Rectangular, Bartlett, Hamming, Hanning, Blackman, Kaiser 30db, Kaiser 40db, Kaiser 50db Phase Offset 0 to 45 degrees Table C l : Features Incorporated into the Transmitter. Filter Noise Source o- ( -o ©z V — o Signal + Noise Filter Xmit Signal -o T O- F i g u r e C2: Block Diagram of the Noise Channel C.1.2 The Noise Channel The noise channel is used to evaluate the MDTL's performance in a controlled environment. The block diagram of the noise channel designed for the experimental unit is shown in Figure C.2. This circuit consists of an high-power noise source, a noise amplifier and a summing amplifier. The noise source generates white Gaussian noise which is bandlimited from 50 Hz to 500 kHz. The noise source is amplified and summed with the PSK signal. BNC connectors are placed in both the transmitter and noise paths to allow the insertion of commercial filters or sources. For example, the user may wish to use an unfiltered BPSK signal originating from the transmitter along with an external noise source. Figure C.20 shows the schematic diagram of the noise channel. 107 Appendix C: Details of the Hardware Design C.1.3 The Phase Error Reference Circuit The phase error reference circuit consists of a sine wave generator, a n A F E , inphase and quadrature A D C s a n d lookup tables for the t a n ' function and the phase error detector. T h e sine wave 1 generator creates a n unmodulated sinusoidal signal w h i c h is synchronized to the modulated carr i e r signal. T h e sine wave generator uses the local oscillator from the t r a n s m i t t e r to synchronize the sine wave. The reference sine wave is passed to a n A F E w h i c h is identical to the A F E under test. The local oscillator from the A F E under test is used to m i x the reference signal down to the 19.2 k H z . The inphase and quadrature arms are then sampled u s i n g the t i m i n g information generated from the N C O . A phase detector circuit generates a phase error sample w h i c h is passed to the data acquisition unit. C.1.4 The Data Acquisition Unit The data acquisition u n i t reads and processes information from the various loop components for performance testing at run-time and reads from and writes to the M D T L for diagnostic testing. The d a t a acquisition u n i t consists of two separate units. T h e first u n i t is a general-purpose D S P board based on Intel's T M S 3 2 0 C 2 5 D i g i t a l S i g n a l Processor and resides i n a personal computer. The second u n i t consists of an external adaptor and supporting h a r d w a r e w h i c h is used to connect the M D T L to the personal computer. W i t h this configuration, the user instructs the T M S board to execute routines w r i t t e n i n assembly code for diagnostic testing or for data capture. The received data is then processed u s i n g a h i g h e r level language, i n our case ' C , to eventually obtain meaningful results. The external h a r d w a r e needed to interface from the T M S board to the M D T L is shown i n F i g u r e C . 3 . T h e interface u n i t consists of i n t e r r u p t logic, address decoding logic a n d read/write ports. A n i n t e r r u p t signal instructs the T M S board to begin an exception processing routine. The p a r t i c u l a r routine depends on the test being performed. Interrupt logic is used to control which i n t e r r u p t signal enters the prioritized interrupts pins. A t present, the control signals from the F S M are used as i n t e r r u p t signals. E i g h t 1 6 - b i t read/write ports are placed throughout the 108 Appendix C: Details of the Hardware Design DO - D15 A0-A2 Address 78 To PC TMS RAV Adaptor IS Decode Board 4 Interrupt Logic F i g u r e C.3: Block Diagram of the TMS Interface. Read Port Write Port Port No. MSB LSB MSB LSB 0 Sine Arm Cosine Arm Sine Arm Cosine Arm 1 True Phase Error Phase Angle Phase Angle 2 Data Extractor Error Estimate Data Extractor Error Estimate 3 Accumulator Accumulator Barrel Shifter Barrel Shifter 4 Loop Filter Loop Filter NCO NCO 5 6 - 7 Status Register Status Register Control Register Control Register - Table C . 2 : TMS Port Assignments. MDTL to access the desired data samples. The port addresses are decoded using the address lines A0-A2, along with the read/write and strobe pins. The port assignments are shown in Table C.2. In addition, a wait state generator provides the necessary delay for the TMS board to properly read from and write to these ports. Figures C.17, C.18 and C.19 shows the schematic diagrams of the TMS interface and the read/write ports. A photograph of the complete hardware test configuration is shown in Figure C.4 109 Appendix C: Details of the Hardware Design Figure C.4: Photograph of the Test Configuration. C.2 Evaluation of the Functionality of the Test Configuration A series of tests were conducted to evaluate the functionality of the hardware implementation. The degradation in the receiver as compared to the theoretical circuit in Figure 3.1 was anticipated to lie within the AFE. This degradation is due to the discrepancies in the analog circuit elements which force the behaviour of the AFE to be less predictable than the digital circuit elements. Hence, the tests which were conducted, evaluate the characteristics of the AFE, the transmitter and the noise channel. The digital loop components of the MDTL were individually tested for functionality using the data acquisition unit and performed well. In order to perform the tests, it is necessary to sample the output signals of the AFE at uniform sampling intervals. Hence, the NCO is configured by the data acquisition unit to sample at a constant rate of 153.6 kHz. The samples from the inphase and quadrature arms were gathered 110 Appendix C: Details of the Hardware Design by the data acquisition unit and routines such as an integer power spectral estimate routine were written in TMS320C25 assembly. Figure C.5 illustrates an example of the sampling process of the inphase and quadrature arm for BPSK signalling. The sampling rate in this case is 307.2 kHz. 0 20 40 60 80 100 120 140 160 180 200 Index (n) Figure C.5: Sampled I and Q Waveforms for BPSK Signalling. The first test consisted of passing white Gaussian noise into the receiver in order to estimate the spectrum of the AFE. The eight-bit noise samples obtained from the inphase and quadrature arms are plotted in Figure C.6 (a). The spectral estimate of the inphase arm which is shown in Figure C.6 (b). All graphs which display spectral estimates were obtained by an integer spectral estimation routine written in TMS320 assembly code. The spectral estimate of the inphase arm is compared to the theoretical frequency response of the bandpass niters placed after the multipliers. In this particular example, the bandpass filters have a Q of 2.0. The spectral estimate closely resembles the theoretical response. The center frequency of the inphase spectral estimate, however, is slightly offset due to the inaccuracies the analog circuit elements. In addition, the attenuation of the spectral estimate at higher frequencies is the result of the bandpass filter placed at the receiver's input. Finally, a non-zero dc component is present in the spectral estimate which is the result of the dc bias circuit placed in the final stage of the bandpass filter. This dc component, however, should have negligible effects on the system since it is attenuated by approximately 40 dB. Ill Appendix C: Details of the Hardware Design 0 64 128 192 256 0 9.6 19.2 28.8 38.4 48 57.6 Quadrature Arm (y[k]) Frequency (kHz) (a) (b) 67.2 fs/2 Figure C.7: Unmodulated Sinusoid (a) / versus Q Samples (b) Spectral Estimate of the Sine Arm. The second test measured the orthogonality between the inphase and quadrature arms. A graph of the inphase samples versus quadrature samples for an unmodulated sinusoid is shown in Figure C.7 (a). The spectral estimate of the inphase arm is shown in Figure C.7 (b). 112 Appendix C: Details of the Hardware Design T h e inphase a n d quadrature samples should form a circle i f they are orthogonal. Figure C.7 (a) shows, however, that the samples are not completely orthogonal r e s u l t i n g i n an elliptical function. T h e dotted curve i n F i g u r e C.7 (a) represents an estimate of the relationship between the inphase a n d quadrature samples. It is estimated t h a t the inphase a r m lags its true position by approximately 9.5° and that the amplitude ratio between the inphase and quadrature arms is approximately 1.03. T h i s anomaly results from u s i n g unmatched filters. A commercial u n i t would have niters matched to each other. In addition, F i g u r e C.7 (a) shows the effects of c l i p p i n g by the signal level estimators. T h i s c l i p p i n g introduces harmonics into the signal as seen i n F i g u r e C.7 (b). T h e t h i r d harmonic (57.6 k H z ) for example, is roughly 35 d B below the first harmonic. It is difficult to ascertain i f this c l i p p i n g w i l l severely affect the performance of the M D T L . A s mentioned i n C h a p t e r F o u r , the major disadvantage of u s i n g signal level estimators is the circuit's poor performance for very weak signal levels, e.g 50 m V peak-to-peak. T h i s degradation is due to the l i m i t a t i o n s of the A D C whose performance degrades as the quantizer step size decreases. Hence, the t h i r d test consisted of m e a s u r i n g the performance of the A D C for various signal levels. F i g u r e C.8 shows the relationship between inphase and quadrature samples of an u n m o d u l a t e d mixed-down carrier frequency for various signal levels and the spectral estimates of the inphase arms. In F i g u r e C.8 (d), for a n inphase signal level of 4.5 V peak-to-peak, the signal-to-quantization noise is roughly 60 d B . I n F i g u r e C.8 (e), for a signal level of 2.5 V peak-to-peak, the decrease i n signal-to-quantization noise is negligible. I n F i g u r e C.8 (f) however, the decrease is roughly 10 d B and any further decrease i n signal level increases the noise floor dramatically. A s a result, an alternative A G C circuit m a y have to be considered i f the received power of the signal varies by more than 20 d B . T h e final test assures the functionality of the transmitter for various data rates, modulation formats, baseband formats and w i n d o w functions. A n example of a t r a n s m i t t e d signal is shown i n F i g u r e C.9. I n this example, the inphase and quadrature arms for B P S K s i g n a l l i n g are windowed u s i n g a K a i s e r (50 dB) window. 113 Appendix C: Details of the Hardware Design 1 1 1 | ITI | 1 IT" (4.5 vpp) „ _i rrrT i i | i i i n"T| i i i | i i i_ ; (0.5 vpp) 256 s 192 £ * 192 - ii • 128 ) B. j 0 64 128 192 Ai (a) (b) Q 03 0, CQ i Inphase Arm (2.5 Vpp) -60 0 I,,,! I,, , , r Inphase Ami (0.5 Vpp) -20 hM4Q 00 H M I , , , ! , , , ! , , , ! , , . ! , , , ! , , , ! , II|III|III|III|III|III|II -10 •B -70 -90 9.6 19.2 28.8 38.4 48 57.6 67.2 Is/2 — ca -80 . I . M L M I , , o 1 -30 a -90 1 -40 rt s -50 -50 1 , ,,1 192 256 (O 1 -40 S -80 111 -30 -60 in ft, 1 1 , ,I I, i M 64 128 - Quadrature Arm (y[k]) -20 -50 -70 1 1 1 0 |oI I-rrrn I | I II "!" ! ! "! "! -10 Inphase Ann (4.5 Vpp) — -40 I II 256 Quadrature Arm (y[k]) -30 E 192 Quadrature Arm (y[k]) -20 « w 128 II|III|III|III|III|II -10 1: I ^ 256 - Ii : 64 ~i i i i i i i i i i i .i i i 1 i i i 1 i i r 0 I I-.. 5 X a. ; -60 -70 01 9.6 19.2 28.8 38.4 4B 57.6 67.2 fs/2 -80 -90 'I 0 1 1 1 I 1 1 1 I 1 1 1 I 1 1 1 I 1 9.6 19.2 28.8 38.4 48 57.6 67.2(5/2 Frequency (kHz) Frequency (kHz) Frequency (kHz) (d) (e) (f) Figure C.8: Sampler Degradation (a) - (c) / versus Q Samples of an Unmodulated Sinusoid with Different Signal Strengths (d) - (f) Spectral Estimates. 100 150 200 2 5 0 3 0 0 350 400 450 500 Index(n) Figure C.9: Sampled B P S K / and Q Waveforms with Windowing. F i g u r e C I O illustrates spectral estimates for various t r a n s m i t t e d signals. T h e purpose of the test is to ascertain the functionality of the transmitter. To quantify the performance of the 114 Appendix C: Details of the Hardware Design t r a n s m i t t e r is beyond the scope of this thesis. Schematic Diagrams and Program Listings Figures C . l l to C.20 show the schematics diagrams of the hardware implementation. T h e software listings for the programmable devices are also presented. Conversion routines for the P R O M listings a n d test vectors for the P A L listings have been omitted for clarity. 115 Appendix C: Details of the Hardware Design 1 I' 1 1 I ' I 1 1 I 1 1 1 1 1 I 1 'I 1 1 0 11 2400 bps, NRZ-L, BPSK, Rect (4.5 Vpp) I 1 1 1 -10 - I'' I 1 I 1 1 1 I 1 1 1 1 1 'I I 1 1 1 1 4800 bps, NRZ-L, BPSK, Rect (4.5 Vpp) -20 -30 -40 9.6 19.2 Frequency (kHz) (a) o 1 -10 (- -20 p- I 1 1 1 I 1 1 1 I 1 1 1 I 1 1 1 I 28.8 38.4 48 57.6 67.2 fs/2 Frequency (kHz) (b) I 1 1 1 11 I I 4800 bps, NRZ-L, QPSK. Rect (4.5 Vpp) I | M I | - I I I | I I I | I I I | I I I | I I I | I I I 9600 bps, NRZ-L, OPSK, Rect (4.5 Vpp) - 19.2 fs/2 -30 -40 H -50 -60 |- -70 -80 -90 19.2 28.8 38.4 48 57.6 67.2 fs/2 9.6 Frequency (kHz) (c) 28.8 38.4 48 57.6 67.2 Frequency (kHz) (d) I i i i |iii|ii i |i ii |i ii|i ii | 2400 bps, Delay Mod., BPSK, Rect (4.5 Vpp) • I i ii Ii iiIi ii I 9.6 19.2 28.8 38.4 48 57.6 67.2 fs/2 Frequency (kHz) (e) 9.6 19.2 28.8 38.4 48 Frequency (kHz) (f) Figure C.10: Power Spectral Estimates of Various Modulated Signals. 116 57.6 67.2 fs/2 Appendix C: Details of the Hardware Design Ul 1 ED ll 3 • Q UJ * o EC u. lu * ALL ENGI B.C. t u a 1 E s 3g§ £ S N Q « * a -J * e *» w^ 1 Q 5 u. a u. a IV u u. a u. If u 1 1/ K u. a Figure C . l l : Schematic of the Analog Front E n d . 117 II u. a If \\ u. a If II u. If a u. a j} \t U ^ H Appendix C: Details of the Hardware Design /7777777 /7777T77 J o o o o o o o o ' 0 0 0 0 0 0 0 0 ° u =3S - n *t » <n — * SSSSSSVi ssssssss Cc J o sis* n m« W t- O a. ooooooao 55 5o oooooooa 0) « w » tQUCl ^***«*«***t^<** JO umuu s v > v > I- K ** 00 « 0 0 ui ui utS J OOOOOOOO s : j ^ H » , k » n , R h „ H o o o o o o o o Ul lu Ul U U (J UlUl K *~ Ul *tti U.U, Ul Uj Ul£ o u o S 7777 |uj|uj CE CE tl ii metj *; * * tt £ >- t» « U> 22 c aa aQ. Q.a o.a0.aa.aa. a 0 |0|u *********<«**x*«(<t; 0. O. ooociO aa a OQ.tU>U Ktt* * * * * C SSSSSVA 0 0 0 0 0 0 0 0 0 0 sssss\s\ Ep cc cc ut^ c . * k H U K U 0 0 0 0 0 0 0 0 0 0 * Y77~~~ 7T( QUO cn tf) coStiP *mil 0» ssssssss ssssssss U * <• o • 2 •n m a. a si MM a ** Q E& 03 Q) <t ^ sisisis « Z % SJ «i S Hi" F i g u r e C.12: Schematic of the Phase Detector/Data Extractor. 118 I * 111111 1 Appendix C: Details of the Hardware Design Figure C.13: Schematic of the Digital Loop Filter. 119 Appendix C: Details of the Hardware Design CC cc o 5 ti s * o ej o ALL EN GilVEER! B.C.. VST " ri • Uj Q X O . *Si 5i2~i3 t s*s a5 Ul »- ° *• u 1 a c 1 R S 2 a Ea > *t » " £ Q a Figure C.14: Schematic of the Numerically-Controlled Oscillator. 120 5 * 5 Appendix C: Details of the Hardware Design 121 Appendix C: Details of the Hardware Design F i g u r e C.16: Schematic of the Transmitter. 122 Appendix C: Details of the Hardware Design F i g u r e C.17: Schematic of the T M S 320C25 Interface. 123 Appendix C: Details of the Hardware Design u t t x •» «N •Si ******** DQoinnt&tttiB 3QCQC0C0CDCQQ; QQQQ&ClClQ Il CO CD H) Q CQ QQQQQQQQ 0. I ssssssw ssssssss QQQQQQQQ ******** QQQQCiQ _ _ I \\\\\\\\ QQOQOQQQ ******** I \\\\\\\\ QQQQQOQCl ******** QQQQQOQQ ********* CO CQ CD CO co a a OQQQElQfiD QOOQQQQC1 F i g u r e C.18: Schematic of the TMS Read Ports. 124 . u a Appendix C: Details of the Hardware Design \ I CD QQQQQQQQ QQC.QC.CiQQ OOOOOQOO QQQQQDQtt •S < -HS OOOOOOOO oooooooo OU QQQQQQQQ eg a. QQQQQQQQ OOOOOOOO QQQQQQQQ L t QQQQQQQQ QQQQQQQQ oooooooo QQQQQQQQ OOOOOOOO ** QQQQQQQQ I ssssssss QQQSQQQQ OOOOOOOO Q Q Q Q Q Q Q OOOOOOOO QQQQQQQQ OOOOOOOO QQQQQQQQ Q Q Q a QQ Q QQQQQQQQ OU _ Q Q Q _ _ ////// F i g u r e C.19: Schematic of the TMS Write Ports. 125 Appendix C: Details of the Hardware Design I—II- !<J>- 0 0 S B • oak —K l(— •-K If- El El 0. Q _l( 1(- H( It- El • • • • • i "i i - 5E3 **G Figure C.20: Schematic of Miscellaneous Circuits. 126 '5 ARCTAN LOOKUP * * * * * theta = atan2 (qy[j], qy[k]); Quantize (theta, DecLvl, ex) - DecLvl/2; index = ((mask s j) « shift) I (mask s k); table[index] = ((unsigned) i) s OxOOFF; TABLE for (count = 0; count < L1*L1; count += 32) i f ((i = ToHex (fl,Ll*Ll,255,32,count,00,table+count)) = -1) exit(0); */ Jinclude •include •include •include <stdio.h> <stdlib.h> <math. h> "tohex.h" •define •define DecLvl MaxLvl (256) (256) i f ((i = ToHex (fl,Ll*Ll, 255, 0,0L, 01, table)) — -1) exit(0); 3J* 133 fclose (fl); &. O 0 1 b int Quantize (double x, int L, double ex[]) { int i; i, j , k, LI, index; Quantize (double x, int L, double ex[)); mask, shift, table[MaxLvl*MaxLvl]; ex[MaxLvl+1], qy[MaxLvl], qx[MaxLvl], theta; count; *fl; 3 for (i - 1; i < L; i++) if ((ex[i] <= x) ss (x < ex[i+l])) return (i); return (0); ) /* Read in quantizer coefficients * / scanf ( "%i\n", SL1); for (i = 0; i < L l ; i++) scanf ( "%G %G\n", sqx[i], sqy[i]); scanf ( "%G\n", sqx[Ll]); P H A S E ERROR E S T I M A T E /* generate decision levels * / for (i = 0; i < DecLvl; i++) ex[i] = 2.*M_PI*i/DecLvl - (DecLvl+1)*M_PI/DecLvl; ex[DecLvl] = M_PI - M_PI/DecLvl; for (index = 0; index < L1*L1; index++) table[index] = OxFFFF; mask = ~(-L1); shift = (unsigned) (log((double)Ll)/log(2.0)); /* Main Loop * / for (j = 0; j < Ll; j++) for (k = 0; k < Ll; k++) { o s main () { int int unsigned double long FILE o f l = fopen ("ARCTAN. HEX", "wt"); To generate a phase angle given I and Q arms * Purpose: H' > Joel A. Bisson University of British Columbia Oct 20th, 1988 ARCTAN.C Author: Institution: Date: Filename: ^ 13 g * * * * Author: Institution: Date: Filename: Purpose: Joel A. Bisson University of British Columbia Oct 22th, 1988 MODULO.C To generate a phase error estimate */ •include •include •include •include LOOKUP <stdio.h> <stdlib.h> <math.h> "tohex.h" TABLE •define •define DecLvl MaxLvl (256) (256) i n t Quantize main () { int int unsigned double double long FILE a. int i ; i , j , k, zk, index; Quantize (double x, int L, double ex[]); table[MaxLvl*MaxLvl]; ex[MaxLvl+l], ey[MaxLvl], M, theta; Modulo (double x); count; *fl; for (0) ; ) 3re double Modulo (double x) { return for (i = 0; i < DecLvl; i++) ex[i] = 2.*M_PI*i/DecLvl - (DecLvl+1)*M_PI/DecLvl; ex [DecLvl] = M_PI - M_PI/DecLvl; ( -M_PI + fmod (x + 25.*M_PI, 2.*M_PI) ); NCO /* generate quantized levels */ LOOKUP TABLE (MOST S I G N I F I C A N T Author: Institution: Date: Filename: * Purpose: * M = 1.0; for (j = 0; j < 4; j++) ( for (k = 0; k < 8; k++) for (zk = 0; zk < 256; zk++) ( Joel A. Bisson University of British Columbia Nov 3rd, 1988 NCOHIGH.C To generate load value (high byte) */ = Modulo (M*(ey[zk) - Modulo (2. *M_PI*k/8.))) = Quantize (theta, DecLvl, ex) - DecLvl/2; = ( j « l l ) I (k«8) I (OxOOFF £ (zk-DecLvl/2)) = ((unsigned) i) & OxOOFF; } M *= 2.0; ) f l = fopen ("MODULO.HEX", "wt"); for (count = 0; count < 8192; count += 32) i f ((i = ToHex (fl,8192,255,32,count,00,table+count)) exit(0); 1 if? - * * * * /* Main Loop */ fclose ( f l ) ; BYTE) s 3 b re CO for (index = 0; index < MaxLvl*MaxLvl; index++) table[index] = OxFFFF; ((i - ToHex (fl,8192,255,0,0L,01,table)) exit(0); s. ) for (i = 0; i < DecLvl; i++) ey[i] = 2.*M_PI*i/DecLvl - M_PI; theta i index table[index] o ( i = 1; i < L; i++) i f ( ( e x [ i ] <= x) ii (x < e x [ i + l ] ) ) r e t u r n ( i ) ; return /* generate decision levels */ if re (double x, i n t L, double ex[]) { 1) == -1) •include •include •include •include <stdio.h> <stdlib.h> <math.h> "tohex.h" •define •define •define MaxLvl (2048) MaxStat (32) LoopDly (63) •define •define •define •define •define Middle In Acquire Trans Lock (.25) (.15) 0x20 0x38 0x18 main () { int unsigned long FILE a, n, i , ck, load, display; mask, shift, table[MaxStat*MAX_LVL]; count, index; *fl; for (index = 0; index < MaxStat*MAX_LVL; index++) 3 table[index] = OxFFFF; NCO shift = (unsigned) floor ((log ((double)MAX_LVL)/log(2. 0)) +.5); TABLE (LEAST SIGNIFICANT /* /* Main Loop */ * * * * for (a = 0; a < 4; b++) for (n =3; n < 11; a++) for (ck = -MAX_LVL/2; ck < MAX_LVL/2; ck++) ( load = (1 « (10 - a)) - (1 « (10 - n)) * (int) floor ((double) ck / (double)(1 « - ((n = 10) ? 0 : (1 « (9 - n))) ; LOOKUP (10 - n))) Author: Institution: Date: Filename: Joel A. Bisson University of B r i t i s h Columbia Nov 3rd, 1988 NCOLOW.C Purpose: To generate load value (low byte) */ display = Acquire; i f (load >= (int) floor((1.-Middle) * pow(2.,10.-a) + 0.5) ss load <= (int) floor((l.+Middle) * pow(2.,10.-a) + 0.5)) display = Trans; (include •include •include •include <stdio.h> <stdlib.h> <math.h> "tohex.h" i f (load >= (int) floor((1.-In) * pow(2.,10.-a) + 0.5) ss load <= (int) floor((l.+In) * pow(2.,10.-a) + 0.5)) display = Lock; •define •define •define MaxLvl (2048) MaxStat (32) LoopDly (63) load -= LoopDly; main () { if int unsigned long FILE (load <- 0) load - (n «— 3) ? 128 - LoopDly : 1; index = (a « shift+3) I <(n-3) « shift) I (ck s 0x7FF); table[index] = ((load 4 0x0700) » 8) I display; ( f l = fopen ("NCOHIGH.HEX","wt") ; for (count = 0; count < MaxStat*MAX_LVL; count += 32) i f ((i = ToHex (fl,MaxStat*MAX_LVL,255, 32,count,00,table+count)) == -1) exit(0); if ((i = ToHex ( f l , MAX_LVL*MAX_LVL, 255, 0,0L,01,table)) = -1) exit(0); fclose(fl); ) a, n, i , ck, load, display; mask, s h i f t , table[MaxStat*MAX_LVL]; count, index; *fl; for (index = 0; index < MaxStat*MAX_LVL; index++) table[index] = OxFFFF; shift = (unsigned) floor((log((double)MAX_LVL)/log(2.0)) +.5); /* Main Loop */ for (a = 0; a < 4; b++) for (n = 3; n < 11; a++) for (ck = -MAX_LVL/2; ck < MAX_LVL/2; ck++) ( load = (1 « (10 - a)) - (1 « (10 - n)) * (int) floor ((double) ck / (double)(1 « - ((n = 10) ? 0 : (1 « (9 - n))) ; if (10 - n))) (load <=> 0) load = (n = 3) ? 128 - LoopDly : 1; index = (a « shift+3) | ((n-3) « table[index] = load s OxOOFF; shift) I (ck s 0x7FF) ; ) f l = fopen ("NCOLOW.HEX", "wt") ; for (count = 0; count < MaxStat*MAX_LVL; count += 32) BYTE) if <<i ToHex (fl,MaxStat*MAX_LVL, 255, 32,count,00,table+count)> ==-1) exit(O); if ((i = ToHex (fl,MAX_LVL*MAX_LVL,255,0,OL,01,table)) — -1) exit(0) ; fclose(fl); ) CLOCKED RESOLUTION "Author "Institution "Date "File co o SELECTOR J o e l A. B i s s o n / D.R.S." U n i v e r s i t y of B r i t i s h Columbia" Nov 29th, 1988" RESSEL1.PLD" DEVICE RESOLUTION_SELECT (P22V10) PIN "Definitions" CLK = 1 (CLK_INPUT combinatorial) D[7:0) = 2:9 (INPUT combinatorial) S[2:0] = 10,11,13 (INPUT combinatorial) GND = 12 (GND) Q[7:0] - 23:16 (OUTPUT active_high registered) VCC - 24 (VCO; BEGIN "Logic Equation Section" ENABLE (Q[7:0]) CASE (S[2:0]) BEGIN *B000) BEGIN Q[7] D[7]; Q[6:0] 0; END; *B001) BEGIN Q[7:6] D[7:6]; Q[5:0J 0; END; JB010) BEGIN Q[7:5] D[7:5]; Q[4:0] 0; END; *B011) BEGIN 0.17:4] D[7:4); Q[3:0] 0; END; *B100) BEGIN Q[7:3] D[7:3]; Q[2:0] 0; END; B E GIN »B101) Q[7:2] D[7:2]; Q[1:0] = END; #B110) BEGIN Q[7:l] -= QtO] END; •Bill) Q[7:0] END; END. 0; D[7: i]; 0; D[7: 0]; TEST_VECTORS omitted END. GATED R E S O L U T I O N SELECTOR Resolution Selector Title Pattern RESSEL2.PDS Revision A Author Joel A. Bisson Institution University of British Columbia Date Oct 14th, 1988 CHIP ressel2 PAL20S10 ;PINS 1 2 3 4 5 6 7 8 9 10 11 12 S2 SI SO D7 D6 D5 D4 D3 D2 DI DOGND ;PINS 13 14 15 16 17 18 19 20 21 22 23 24 /OE Q0 Ql Q2 Q3 Q4 Q5 Q6 Q7 NC NCvcc EQUATIONS Q0.TRST = OE Ql.TRST = OE Q2.TRST = OE Q3.TRST = OE Q4.TRST = OE Q5.TRST = OE Q6.TRST = OE Q7.TRST = OE Q7 = D7 */S2 * /SI */SO + ;Q7 selected for all S2 SI SO D7 */S2 * /SI * SO ++ D7 */S2 * SI */SO + D7 */S2 * SI * SO + D7 * S2 * /SI */SO + D7 * S2 * /SI * SO + D7 * S2 * SI */SO D7 * S2 * SI * so Q6 = GND*/S2 * /SI */so + ;Q6 selected for all but 000 D6 */S2 * /SI * so + D6 D6 D6 D6 D6 D6 */S2 * */S2 * * S2 * * S2 * * S2 ** * S2 Q5 = G N D * /S2 * GND* /S2 D5 */S2 * D5 */S2 ** D5 * S2 D5 * S2 * D5 * S2 * D5 * S2 Q4 = GND*/S2 * GND* /S2 * GND* /S2 ** D4 */S2 * D4 * S2 D4 * S2 * D4 * S2 * D4 * S2 * Q3 « GND*/S2 * GND* /S2 ** GND* /S2 * GND* /S2 D3 * S2 ** D3 * S2 D3 * S2 •* D3 * S2 Q2 = GND*/S2 * GND* /S2 ** GND* /S2 * GND* /S2 GND* S2 * D2 * S2 * D2 * S2 D2 * S2 * Ql - GND* /S2 * GND* /S2 * GND* /S2 • GND* /S2 GND* S2 * GND* S2 * DI * S2 * DI * S2 * QO = GND*/S2 * GND* /E2 ** GND* /S2 GND* /S2 ** GND* S2 * GND* S2 GND* S2 ** DO * S2 SI * SI * /SI * /SI * SI ** SI /SI * /SI * SI SI * /SI * /SI * SI * SI * /SI /SI * SI ** SI /SI ** /SI * SI SI * /SI * /SI ** SI * SI /SI ** /SI SI * SI * /SI * /SI ** SI * SI /SI * /SI ** SI SI * /SI * /SI * SI ** SI /SI * /SI ** SI SI * /SI * /SI ** SI SI * /SI * /SI SI ** SI /so ++ so /so ++ so /so + so /so + so + /so ++ so /so ++ so /so + so /so + so ++ /so + so /so ++ so /so + so /so + so + /so ++ so /so ++ so /so + so /so + so ++ /so + so /so ++ so /so + so /so ++ so /so ++ so /so ++ so /so + so /so + so + /so ++ so /so +-f so + /so so SIMULATION g ft. omitted selected for all but 000 001 •Q4 selected for all but 000 001 010 Q.3 selected for all but 000 001 010 Oil Q2 selected for all but 000 001 010 Oil 100 Ql selected for all but 000 001 010 Oil 100 101 O ACCUMULATOR (MOST S I G N I F I C A N T B Y T E ) "Author "Institution "Date Joel A. Bisson / N.R." University of British Columbia" Nov 30th, 1988" o "File ACCMSB.PLD" J* DEVICE MS 8BIT REG (P22V10) ft. " PIN "Definitions" CLK = 1 D[15:81 = 2:9 A15 - 10 C16 = 11 GND - 12 ZERO = 13 OVFLW = 15 Q[15:8] - 23:16 VCC = 24 (CLK_INPOT combinatorial) (INPUT combinatorial) (INPUT combinatorial) (INPUT combinatorial) (GND) (INPUT combinatorial) (OUTPUT active_high combinatorial) (OUTPUT active_high registered) (VCC); BEGIN "Logic Equation Section" ENABLE (Q[15:8],OVFLW); RESET(Q[15:8]) = ZERO; OVFLW = A15 % Q[15] % D[15] % C16 CASE (OVFLW,A15) BEGIN #B00, #B01) Q[15:8] - D[15:8]; •BIO) Q[15:81 = #B01111111; •Bll) Q[15:81 = •B10000000; END; TEST_VECTORS QO selected for all but 000 001 010 Oil 100 101 110 £[' omitted END. s ^ tl g <£|' 3 ACCUMULATOR "Author "Institution "Date "File (P22V10) "Definitions" CLK D[7:0] A15 OVFLW GND ZERO Q[7:0] vcc BYTE) J o e l A. Bisson / N.R." U n i v e r s i t y of B r i t i s h Columbia" Nov 23th, 1988" ACCLSB.PLD" DEVICE LS_8BIT_REG PIN (LEAST SIGNIFICANT = = = = = - = = = = = 1 2:9 10 11 12 13 15 23:16 24 (CLK INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (GND) (INPUT c o m b i n a t o r i a l ) (OUTPUT a c t i v e _ h i g h c o m b i n a t o r i a l ) (OUTPUT a c t i v e h i g h r e g i s t e r e d ) (VCC); BEGIN " L o g i c Equation S e c t i o n " (CLK_INPUI combinatorial) (INPUT combinatorial) (INPUT combinatorial) (INPUT combinatorial) (GND) (INPUT combinatorial) (OUTPUT a c t i v e h i g h registered) (VCC); 1 2:9 10 11 12 13 23:16 24 CLK D[15:8J A15 C16 GND B15 OVFLW Q[15:8] VCC ENABLE ENABLE (Q[15:8]); (OVFLW); OVFLW = A15 % B15 % D[15] % C16; CASE (OVFLW,A15) BEGIN •BOO, •B01) Q[15:8] = D[15:8]; •BIO) Q[15:8] = •B01111111; •Bll) Q[15:8] = •B10000000; END; BEGIN "Logic Equation S e c t i o n " ENABLE (Q[7:0J); RESET(Q[7:0]) = ZERO; END. CASE (OVFLW,A15) BEGIN • BOO, •B01) Q[7:0] = D[7:0J; •BIO) Q[7:0] = • B l l l l l l l l ; • Bll) Q[7:0] = •B00000000; END; TEST_VECTORS omitted END. END. OUTPUT R E G I S T E R (LEAST SIGNIFICANT TEST_VECTORS "Author "Institution "Date "File omitted END. OUTPUT R E G I S T E R "Author "Institution "Date "File J o e l A. Bisson / N.R." U n i v e r s i t y of B r i t i s h Columbia" Nov 27th, 1988" OUTMSB.PLD" DEVICE MS_OUTPUT_8BIT_REG PIN (MOST S I G N I F I C A N T "Definitions" (P22V10) BYTE) J o e l A. B i s s o n / N.R." U n i v e r s i t y of B r i t i s h Columbia" Nov 27th, 1988" OUTLSB.PLD" DEVICE OUTPUT_8BIT_REG PIN (P22V10) "Definitions" CLK D[7:0] A15 C16 GND B15 D15 OVFLW Q[7:0) = = = = = 1 2:9 10 11 12 13 14 15 23:16 (CLK_INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (GND) (INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (OUTPUT a c t i v e h i g h c o m b i n a t o r i a l ) (OUTPUT a c t i v e _ h i g h r e g i s t e r e d ) BYTE) VCC = 24 (VCC); BEGIN "Logic Equation Section" ENABLE (Q[7:01); ENABLE (OVFLW); OVFLW =A15 % B15 % D15 * C16; CASE (OVFLW,A15) BEGIN *B00, •B01) Q[7:0] = D[7:0]; •BIO) Q[7:01 = •Bllllllll; •Bll) Q[7:0] = •BOOOOOOOO; END; END. TEST VECTORS omitted END. SEQUENCER Title pattern Revision Author Institution Date ( 6 4 - S T A T E FSM) MDTL Sequencer SEQ1.PDS A Joel A. Bisson / D.R.S. University of British Columbia Jan 18th, 1989 CHIP SEQUENCER 1 PMS14R21 ; PINS 1 2 3 4 5 6 7 8 9 10 11 12 CLK DCK /SP INI NC NC NC NC NC NC SDI GND 13 14 15 16 17 18 19 20 21 22 23 24 /OE SDO ENG ENK LDP OUT ACC PE /SAMP /LDM MOD VCC STATE MOORE MACHINE OUTPUT ENABLE DEFAULT_ BRANCH S63 SO SI S2 S3 S4 S5 S6 S7 S8 CONT CONT CONT CONT CONT CONT CONT CONT CONT -> -> -> -> -> -> -> -> -> SI S2 S3 S4 S5 S6 S7 S8 S9 S9 S10 Sll S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S3 36 S 7 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 •= := := •= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT C CO ON NT T CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT CONT SAMPLE POWER UP POWER UP.OUTF S0.OUTF -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> -> S10 Sll SI 2 S13 S14 SI 5 SI 6 S17 SI 8 SI 9 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S3 3 S3 4 S35 S3 6 S 37 S38 S3 9 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 SO : = VCC -> S63 /ENK * /ENG * /LDM * /LDP* /OUT * /ACC * /PE * /SAMP ENK * /ENG * /LDM * /LDP * /OUT* /ACC * /PE * SAMP SI.OUTF S2.0UTF S3.OUTF S4.OUTF S5.OUTF S6.OUTF S7.OUTF S8.0UTF S9.OUTF S10.OUTF Sll.OUTF S12.0UTF S13.0UTF S14.0UTF S15.0UTF S16.0UTF S17.0UTF S18.0UTF S19.0UTF S20.OUTF S21.0UTF S22.0UTF S23.0UTF S24.0UTF S25.0UTF S26.0UTF S27.0UTF S28.0UTF S29.0UTF S30.OUTF S31.0UTF S32.0UTF S33.0UTF S34.OUTF S35.0UTF S36.0UTF S37.0UTF S38.0UTF S39.0UTF S40.OUTF S41.OUTF S42.0UTF S43.0UTF S44.0UTF S45.0UTF S46.0UTF S47.0UTF S48.0UTF S49.OUTF S50.OUTF S51.0UTF S 52. OUTF S53.OUTF S54.OUTF S55.0UTF S56.0UTF S57.OUTF S58.OUTF S59.0UTF S60.OUTF : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK :•= /ENK : = /ENK : = /ENK : = /ENK : =•/ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK : = /ENK * * * * * * * * * * * •* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG ENG ENG ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG /ENG * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * •* * * * * * * * * * * * * * * * * * * * * * * * * * * /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM /LDM LDM LDM * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP /LDP LDP LDP * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /OUT * /OUT * /OUT /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT + /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /OUT /OUT * /OUT * /OUT + /OUT * /OUT * OUT * /OUT * /OUT * /OUT * /OUT * /OUT * /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /ACC /OUT* /ACC /OUT * /ACC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE /PE 4 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * •* * * * * SAMP SAMP SAMP SAMP SAMP SAMP SAMP SAMP SAMP SAMP SAMP SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP /SAMP : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP : = /ENK * /ENG * /LDM * /LDP * /OUT * /ACC * /PE * /SAMP S61.0UTF S62.0UTF S63.0UTF CONDITIONS SAMPLE = SP * /INI; CONT = /INI; SIMULATION omitted DATA "Author "Institution "Date "File J o e l A. B i s s o n " U n i v e r s i t y of B r i t i s h Nov 14th, 1988" SEQ2.PLD" DEVICE SEQUENCER_2 PIN CONTROLLER Columbia" (P22V10) "Definitions" CLK B[1:0] Gl[3:0] G2[3:0] GND ZERO ZEROUT SH[3:0) K[2:0) ENG ENK VCC = = = = = = = = = = = 1 2:3 4:7 8:11 12 13 14 18:15 21:19 22 23 24 (CLK INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (GND) (INPUT c o m b i n a t o r i a l ) (OUTPUT a c t i v e h i g h r e g i s t e r e d ) (OUTPUT a c t i v e _ h i g h r e g i s t e r e d ) (OUTPUT a c t i v e h i g h r e g i s t e r e d ) (INPUT c o m b i n a t o r i a l ) (INPUT c o m b i n a t o r i a l ) (VCC); BEGIN " L o g i c Equation Section" ENABLE (ZEROUT,SH[3:0],K[2:0]); ZEROUT = ZERO; IF (ENK) THEN CASE (B[l:01) BEGIN #B00) K[2:0] = *B01) BEGIN K[2) K[1:0) END; JB10) BEGIN K[2) = K[l] = K[0) = END; *B000; = /K[2); = #B00; . K[2) % K [ l ) ; /K[l]; *B0; "k={0)" "k=(0,4)" "count through k" "k=(0,2,4,6|" "count through k" • Bll) BEGIN K[2] K[l] K[0] END; = K[2] % (K[l] * K[01); = K[l) % K[0J; = /K[0J; "k=(0,l,2,3,4,5,6,7(" "count through lc" END; ELSE K[2:0] = K[2:0] ; IF (ENG) THEN SH[3:0] = G l [ 3 : 0 ] ; ELSE SH[3:0J = G2[3:0]; END. TEST VECTORS omitted END. FREQUENCY co or "Author "Institution "Date "File DIVIDER (TRANSMITTER) J o e l A. Bisson" U n i v e r s i t y of B r i t i s h Columbia" Nov 10th, 1988" CLKCODE, PLD" DEVICE CLOCK_CODE (P23S8) PIN "Definitions" CLK CLKINP DRSEL[2:0) N[1:0] GND OBS QDR1[2:1] QDR110) QMOD[1:0] QDRCLK AMPCLK DRCLK VCC /QDR2[4:0] = = = = = = = = = = = = 1 (CLOCK) 2 (INPUT combinatorial) (INPUT combinatorial) 3:5 (INPUT combinatorial) 6:7 (GND) 10 11 (INPUT combinatorial) 12: 13 (OUTPUT enable_high a c t i v e _ h i g h 14 (OUTPUT enable_high a c t i v e _ h i g h 15: 16 (OUTPUT enable high a c t i v e high 17 (OUTPUT enable_high a c t i v e _ h i g h (OUTPUT enable_high a c t i v e _ h i g h 18 (OUTPUT enable h i g h a c t i v e high 19 20 (VCC) 23: 26,22(BREG active_low registered),- BEGIN " L o g i c Equation S e c t i o n " ENABLE IF (AMPCLK,DRCLK,QDRCLK,QMOD[l: 0] ,QDR1(2: 0] ) ; (OBS) THEN OBSERVE(QDR2[4:0]); reg_feedback) registered) registered) registered) io_feedback) i o feedback) QDRCLK = DRCLK; CASE (QDR1[2:0]) BEGIN •B000) BEGIN QDR2[4] QDR2[3) = QDR2[2] = QDR2[1J = QDR2[0] = QDR1[2:0] END; •B010) BEGIN QDR2[4:0] QDR1[2:0] END; •B001, #B011) BEGIN QDR2[4:0] QDR1[2:0) END; •B101) BEGIN QDR2[4] = QDR2[3] = QDR2[2] = QDR2[1] = QDR2[0] = QDR1[2:0] END; #B100, #B110) BEGIN QDR2[4:0] QDR1[2:0] END; • B i l l ) BEGIN QDR2[4:0] QDR1[2:0) END; END; CASE (DRSEL[2:0]) BEGIN •B000) DRCLK •B001) DRCLK •B010) DRCLK = #B011) DRCLK •B100) DRCLK = •B101) DRCLK = •B110) DRCLK • B i l l ) DRCLK = END; QDR2[4] % QDR2[3] % QDR2[2] % QDR2[1] % /QDR2[0J ; = •B011; (QDR2[3] * QDR2[2] * QDR2[1] * QDR2[0]) (QDR2[2] * QDR2[1] * QDR2[0]); (QDR2[1] * QDR2[0]); (QDR2[0]); =QDR2[4:0]; = •B101; = QDR2[4:0]; = *B010; QDR2[4] % QDR2[3] % QDR2[2) % QDR2[1] % /QDR2[0]; = #B110; (QDR2[3] * QDR2[2] * QDR2[1] * QDR2[01); (QDR2[2J * QDR2[1) * QDR2[0)); (QDR2[1] * QDR2[0]); (QDR2[0)); = QDR2[4:0]; = •Bill; =• QDR2[4:0]; = •B000; CLKINP; QDRl[0] QDRl[l] QDR2[0] QDR2[1] QDR2[2] QDR2[3] QDR2[4] CASE (N[1:0)) BEGIN • B00, •B01) AMPCLK = QDRCLK; •B10) IF (DRSEL[2:0) = JB000) THEN AMPCLK = QDRl[0]; ELSE PCMOUT[1:0] PCMOUT[2] DATAOUT VCC /PHB[3:1] /PHA[2:1] BEGIN IF (DRCLK * /QDRCLK) THEN QMOD[0] = /QMOD[0) ; ELSE QMODfO) = QMOD[0J ; AMPCLK = QMODfO] ; END; ENABLE (PCMOUT [2 :0] ,Q[1:0] ,DATAOUT,PHA[0] ,PHB[0] ) ; IF omitted END. "Author "Institution "Date "File (TRANSMITTER) J o e l A. Bisson" U n i v e r s i t y of B r i t i s h Columbia" Nov 10th, 1988" PCMCODE.PLD" DEVICE PCM_CODE_FORMATTING (P23S8) PIN "Definitions" TXCLKINX2 TXCLKIN DATAIN S[2:0] N[1:0] GND OBS Q[1:0J PHB[0] PHA[0] = = = = = = = = = = 1 2 3 4:6 7:8 10 11 13:12 14 15 (CLOCK) (INPUT (INPUT (INPUT (INPUT (GND) (INPUT (OUTPUT (OUTPUT (OUTPUT (OUTPUT enable h i g h a c t i v e h i g h r e g i s t e r e d ) (OUTPUT enable_high a c t i v e _ h i g h r e g _ f eedback) (OUTPUT enable h i g h a c t i v e h i g h r e g feedback) (VCC) (BREG a c t i v e _ l o w r e g i s t e r e d ) (BREG a c t i v e low r e g i s t e r e d ) ; DATAOUT = DATAIN; TEST_VECTORS BASEBAND FORMATTER 17 16 18 19 20 22 24 25 26 BEGIN "Logic Equation S e c t i o n " • B l l ) I F (DRSEL[2:0] = #B000) THEN AMPCLK = QDR1[1]; ELSE BEGIN IF (DRCLK * /QDRCLK) THEN CASE (QMOD[1:0]) BEGIN *B00) QMOD[1:0] = *B01, #B01) QMOD[1:0] = *B10, *B10) QMOD[1:0] = *B00, #B11) QMOD[1:0] = tBOO END; ELSE QMOD[1:0] =QMOD[1:0]; AMPCLK = QMOD[l] ; END; END; CO = combinatorial) combinatorial) combinatorial) combinatorial) combinatorial) enable_high a c t i v e _ h i g h reg_feedback) enable_high a c t i v e _ h i g h r e g i s t e r e d ) enable_high a c t i v e _ h i g h r e g i s t e r e d ) (OBS) THEN OBSERVE(PHA[2:1],PHB[3:1]); CASE (N[1:0]) BEGIN #B00) BEGIN PCMOUT[2:0] = #B000; Q[1:0] = #B00; END; JB01) BEGIN Q[1:0] - #B00; PCMOUT[1:0] = #B00; I F (TXCLKIN) THEN PCMOUT[2] = PHB[0]; ELSE PCMOUT [2] = PHA[0] ; END; #B10) BEGIN Q [ l ] = *B0; PCMOUT[0] = #B0; CASE (Q [ 0 ] , TXCLKIN) BEGIN #B00) BEGIN PCMOUT[2:l] = P H A t l : 0 ] ; Q[0] = /Q[0]; END; fB10) BEGIN PCMOUT[2:l] =PHB[1:0]; Q[0] = /Q[0]; END; *B01, *B11) BEGIN PCMOUT[2:l] = PCMOUT[2:l]; Q[0] = Q[0]; END; END; END; #B11) CASE (Q[1:0].TXCLKIN) BEGIN }B000) BEGIN PCMOUT[2:0] =PHA[2:0]; Q[1:0] = Q[1:0]; END; #B001) BEGIN PCMOUT[2:01 = PCMOUT[2:0]; Q[1:0] = #B01; END; •B100, •B010) BEGIN PCMODT[2:0] - PCMOUT[2:0J; Q[1:0] = Q[1:0J; END; •B011) BEGIN PCMOUT[2:0] =PHB[3:1); Q[1:0) = •BIO; END; •B101) BEGIN PCMOOT[2:0] = PCMOUT[2:0); Q[1:0] = •BOO; END; •B110, •Bill) BEGIN PCMOUT[2:0] = PCMOUT[2:0]; Q[1:0] = •BIO; END; END; IF (TXCLKIN) THEN BEGIN PHA[1) = PHA[0] ; PHA[2) = PHA[1]; PHB[0] = PHB[0] ; PHB[1] = PHB[1] ; PHB[2) = PHB[2] ; PHB[3] = PHB[3] ; CASE (S[2:0)) BEGIN •B000) PHA[0) = DATAIN; •B001) IF (DATAIN) THEN PHA[0] /PHB[0]; ELSE PHA[0] PHB[0] ; •B010) IF (DATAIN) THEN PHA[0) PHB[0]; ELSE PHA[0] = /PHB[0]; •B011) PHA[0] = DATAIN; •B100) PHA[0] = DATAIN; •B101) PHA[0] = /PHB[0]; •B110) PHAtO] = /PHB[0]; •Bill) IF (DATAIN) THEN PHA[0J = PHB[0); ELSE IF (/DATAOUT) THEN PHA[0] = /PHB[0); ELSE PHA[0] = PHB[0] ; END; END; ELSE BEGIN PHB[1] = PHB[0] PHB[2) = PHB[1) PHB[3] = PHB[2] PHA[0] = PHA[0] PHA[1] = PHA[1) PHA[2] = PHA[2] ; CASE (S[2:0]) BEGIN •B000) PHB[0] = PHA[0]; •B001) PHB[0] = PHA[0); •BOIO) PHB[0] = PHA[0] ; •B011) PHBtO) = 0; •B100) PHB[0] = /PHA[0] •B101) IF (DATAOUT) THEN PHB[0] = /PHA[0J; ELSE PHB[0) = PHA[0]; •B110) IF (DATAOUT) THEN PHB[0] = PHA[0) ; ELSE PHB[0) = /PHA[0]; •Bill) IF (DATAOUT) THEN PHB[0] = /PHA[0]; ELSE PHB[0J = PHA[0]; END; END; END. TEST_VECTORS omitted END. PHASE ANGLE "Author "Institution "Date "File GENERATOR (TRANSMITTER) Joel A. Bisson" University of British Columbia" Nov 10th, 1988" PHASECOD.PLD" DEVICE PHASE_CODE_FORMATTER (P22V10) PIN "Definitions" CLK LOAD PCM[2:0] PHOFF[3:0] N[1:0] GND ZERO Q[6:0] LDOUT VCC = = = = = = = = 1 (CLK INPUT combinatorial) 2 (INPUT combinatorial) 3:5 (INPUT combinatorial) 6:9 (INPUT combinatorial) 10:11 (INPUT combinatorial) 12 (GND) 13 (INPUT combinatorial) 19:14 21(OUTPUT active_high registered) 23 (OUTPUT active high registered) 24 (VCC); BEGIN " L o g i c E q u a t i o n S e c t i o n " ENABLE (LDOUT,Q[6:0]); fr TO 3 PL LDOUT IF = LOAD; o (ZERO) THEN RESET (Q[6:0J); IF (/LDOUT * LOAD) THEN BEGIN CASE (N[1:0J) BEGIN *B00) Q[6:4] = *B000; •B01) BEGIN Q[6) = PCM[2] ; Q[5:4] = *B00; END; *B10) BEGIN Q[6] = PCM[2]; Q[5) = PCM[2] % PCM(1]; Q[4] = #B0; END; *B11) BEGIN Q[6] = PCM[21; Q[5] = PCM[2) % PCM[1]; Q[4) = PCM[2] % PCM[1] % PCM[0]; END; END; Q[3:0]= PHOFF[3:0); END; ELSE BEGIN Q[6] Q[6] % (Q[5] * Q[4] * Q[3] * Q[2] * Q [ l ] Q[5] = Q[5] (Q[4] * Q[3] * Q[2] * Q[l] * Q[0]) Q[4] = Q[4] (Q[3] * Q[2] * Q[l] * Q[0]); Q[3] = Q[3] (Q[2] * Q[l) * Q[0] ); Q[2] = Q[2] (Q[l] * Q[0]); Q [ l ] = Q[l) % (Q[0]); Q[0J = /Q[0]; END; END. TEST_VECTORS omitted END. a. s to CO 3
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The Multi-Sampling Digital Tanlock Loop for tracking suppressed-carrier M-ary PSK signals Bisson, Joël A. 1989
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Title | The Multi-Sampling Digital Tanlock Loop for tracking suppressed-carrier M-ary PSK signals |
Creator |
Bisson, Joël A. |
Publisher | University of British Columbia |
Date Issued | 1989 |
Description | A Multi-Sampling Digital Tanlock Loop (MDTL) is proposed for tracking suppressed-carrier M-ary Phase-Shift Keyed signals. Unlike the conventional Digital Phase-Locked Loop (DPLL) which possesses a sinusoidal phase characteristic, the MDTL has a linear phase characteristic with a period of 2π/M. Consequently, the MDTL can be characterized by a linear difference equation which eliminates the approximations of nonlinearity seen in the conventional DPLL. The linear difference equation also provides many attractive features over the conventional DPLL. These include locking conditions which are insensitive to variations in signal power, enhanced noise immunity, wider lock range and reduced steady-state mean phase error for the first order loop when the received signal has a frequency offset. A first-order MDTL is analyzed in the noiseless case. Closed-form expressions were derived for the steady-state mean phase error, the region of stability, the lock range and the acquisition time. It is shown that the use of multi-sampling improves the performance of the MDTL over the conventional Digital Tanlock Loop by increasing the region of stability and consequently, the lock range, and by decreasing the steady-state mean phase error and the acquisition time. In the presence of noise, the task of modelling the MDTL is partitioned into a software testbed and a hardware testbed. Both the software and hardware testbed simulate the MDTL in the presence of noise. The hardware testbed, however, also includes other important impairments such as quantization effects and loop delay. The software testbed represents the reference model against which the hardware testbed can be compared and measured. The phase error, the acquisition time and the hold-in time are the three performance measures used to characterize the performance of the MDTL in the presence of noise. It is shown that multi-sampling can be used as an acquisition aid without increasing the standard deviation of the phase error distribution. For binary phase-shift keying, four bits of sampler quantization and 64 levels of numerically-controlled oscillator resolution are needed to provide negligible performance degradation compared to the infinite quantization case at a received signal-to-noise ratio of zero dB. The MDTL design is simple. Digital implementation of the MDTL provides an opportunity for enhanced system integration using Very Large Scale Integration techniques for high speed applications or Digital Signal Processing microprocessor techniques for slower speed applications. |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2010-08-27 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0064770 |
URI | http://hdl.handle.net/2429/27823 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Campus |
UBCV |
Scholarly Level | Graduate |
Aggregated Source Repository | DSpace |
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