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Electronic systems : a course based on adult education practices 1981

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ELECTRONIC SYSTEMS A COURSE BASED ON ADULT EDUCATION PRACTICES by MIRO ANGELES Diploma (B.Sc.)> National Polytechnic I n s t i t u t e , Mexico, 1958 B. A. Sc., Un i v e r s i t y of B r i t i s h Columbia, 1966 Diploma i n Adult Education, U n i v e r s i t y of B r i t i s h Columbia, 1972 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF EDUCATION i n THE FACULTY OF GRADUATE STUDIES (Department of Adult Education) We accept t h i s thesis as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA August 1981 (c) Teodomiro Angeles-Salgado, 1981 In p r e s e n t i n g t h i s t h e s i s i n p a r t i a l f u l f i l m e n t o f the r e q u i r e m e n t s f o r an advanced degree a t the U n i v e r s i t y o f B r i t i s h C o l u m b i a , I agree t h a t the L i b r a r y s h a l l make i t f r e e l y a v a i l a b l e f o r r e f e r e n c e and s t u d y . I f u r t h e r agree t h a t p e r m i s s i o n f o r e x t e n s i v e c o p y i n g o f t h i s t h e s i s f o r s c h o l a r l y purposes may be g r a n t e d by the head o f my department o r by h i s o r h e r r e p r e s e n t a t i v e s . I t i s u n d e r s t o o d t h a t c o p y i n g o r p u b l i c a t i o n o f t h i s t h e s i s f o r f i n a n c i a l g a i n s h a l l n o t be a l l o w e d w i t h o u t my w r i t t e n p e r m i s s i o n . Department o f EDUCATION The U n i v e r s i t y o f B r i t i s h C o l u m b i a 2075 Wesbrook P l a c e V a n c o u v e r , Canada V6T 1W5 Date SEPTEMBER 28, 1981 DE-6 (2/79) ABSTRACT The causes of low student attendance for continuing education courses in electronics at the Pacific Vocational Institute (PVI) are analyzed. The unsatisfactory student persistence reflected inadequacies in the approaches used to instruct and in the textbooks ut i l i z e d in these courses. This report describes how modern principles of adult education were employed to identify these inadequacies and how the application of these principles was used to develop a new curriculum and a new book (appendix F). The new curriculum and i t s accompanying book not only incorporate the latest developments from the electronics industry, but they also incorporate the continuing application of adult education principles and practices. The c r i t e r i a for the selection of electronic components is discussed. The resulting component selection provides the students with a moderately priced kit that is easy to transport, and whose components find repeated application throughout the various experiments in the course. The students' attendance records provide one index of the success achieved by the new course. These records show that the successful application of adult education principles has renewed the interest and promoted the active participation of continuing education students attending electronics courses. Another indicative index of the success of the course is the result of f i e l d tests performed by other instructors at PVI as well as at other institutions. These results confirm that the new curriculum, the new book and the application of the recommended adult education practices provide the same successful responses as those experienced during the i n i t i a l tests and development of the course. i i TABLE OF CONTENTS ABSTRACT . . . . i i ACKNOWLEDGEMENTS v INTRODUCTION . . . . . . . 1 THE CURRICULUM USED TO TEACH ELECTRONICS 3 STUDENT PERFORMANCE AND PERSISTENCE IN PREVIOUS PROGRAMS . . . 5 Day Program Students 5 Continuing Education Students 6 IDENTIFICATION OF INADEQUACIES OF PREVIOUS APPROACHES . . . . 8 The Old Curriculum 8 The New Curriculum 10 Teaching Practices 12 Textbooks 12 TECHNICAL FACTORS LEADING TO THE DEVELOPMENT OF THE NEW CURRICULUM AND THE NEW TEXTBOOK 18 DEVELOPMENT OF THE NEW CURRICULUM AND THE NEW TEXTBOOK . . . . 21 Pre-requisites for the New Course 21 Ti t l e of the New Book 23 SELECTION CRITERIA FOR LABORATORY COMPONENTS 25 RECOMMENDATIONS FOR THE USE OF THE TEXTBOOK, 28 FIELD TESTING OF THE BOOK AND THE NEW COURSE 29 INSIGHTS ACQUIRED FROM THE FIELD TEST 31 CONCLUSION • 32 i i i APPENDICES A. . CURRICULUM COVERAGE OF THE TEN MONTH DAYTIME PROGRAM . . . 33 Laboratory Materials in use for the Old Curriculum . . . 36 B. THE NEW CURRICULUM 38 Laboratory Materials for the New Curriculum 42 C. COST OF LABORATORY COMPONENTS FOR THE NEW CURRICULUM . . . 43 D. ATTENDANCE RECORDS OF COURSES USING THE NEW CURRICULUM . . 46 E. FIELD TESTING FROM WHITTIER UNION HIGH SCHOOL DISTRICT . . 49 F. ELECTRONIC SYSTEMS BOOK 51 iv ACKNOWLEDGEMENTS My sincere thanks to Dr. William S. G r i f f i t h for his encouragement during the development of the new course and the book (appendix F). His valuable suggestions and guidance w i l l continue to assist me in future tasks. I also acknowledge the late Dr. Coolie Verner who aided my early work in the f i e l d of Adult Education. Miro Angeles University of British Columbia August 1981 v INTRODUCTION In this essay I am discussing the present teaching practices of electronics, in particular at post secondary education institutions. For the past three years I have taught this subject at the Pacific Vocational Institute in Burnaby, B. C , both during the day program and in the evening Continuing Education Program. This experience has brought me into close contact with both Day Program Students and Continuing Education Students. This close contact made me aware that the current practices in teaching this subject in the day program are successful as far as attracting sufficient students to ju s t i f y giving the course and also that a large enough percentage of these students succeed in satisfying the course requirements. However, the same approaches did not seem to provide satisfactory results with the students of continuing education courses, who showed lack of involvement and a declining attendance after a few sessions of their course. In this essay I describe both how I have attempted to identify and correct the basic weaknesses in the practices used to instruct the continuing education students, in accordance with the modern practices of adult education as elaborated in the literature, and the process that I followed in the preparation of a new textbook whose use requires approaches suitable for teaching adults, and which is meant to be used in a revised course. This paper is organized into ten sections as follows : The curriculum used to teach electronics, Student performance and persistence in previous programs, Identification of inadequacies of previous approaches, Factors leading to the development of the new curriculum and the new book, 1 2 Development of the new curriculum and the new textbook, Selection Criteria for laboratory components, Recommendations for the use of the textbook, Field testing of the new book and the new course, Insights acquired from the f i e l d test, Conclusions. In the appendices the following materials are presented in addition to a copy of the new textbook: Curriculum coverage of the ten month daytime program, The new curriculum, Cost of laboratory components for the new curriculum, Attendance records of courses using the new curriculum, Field testing from Whittier Union High School District. THE CURRICULUM USED TO TEACH ELECTRONICS As an electronics instructor in a ten-month program of Electronics taught at the Pacific Vocational Institute, I can describe the traditional curriculum and laboratory materials used for this subject, both during the ten-month day program, and during the four year Continuing Education Program. The ten-month daytime curriculum 1 is a typical example of the organization of content taught in most post secondary electronics training centres throughout British Columbia. While I do not consider i t totally inadequate for those students who can affort the time and are willing to immerse themselves in a course designed to train them in this discipline, I find both the content and the methods used in teaching i t unsuitable for average adult students. I refer to this ten-month curriculum, when applied to continuing education courses, as the OLD CURRICULUM, to differentiate i t from the proposed curriculum discussed in this essay and which i s referred as the PROPOSED or NEW CURRICULUM. The old curriculum is presented to the adult students as an imposed discipline whose planning does not involve their participation. The students confronted with this approach quite often f a i l to recognize how this curriculum w i l l help them to understand, in a short period of time, the operation of modern electronics devices, unless they are prepared to devote a much longer time than they had previously anticipated. This extra time needed is not available to most of these students. The Continuing Education program using this old curriculum also • Appendix A, Curriculum Coverage of the Ten Month Daytime Program. 3 4 u t i l i z e s the same laboratory f a c i l i t i e s and techniques of the ten-month daytime program.2 The continuing education program is offered two evenings per week during the winter sessions and students require four years to complete i t . The same basic material for the ten-month daytime courses is included in the continuing education courses, but under different names. For example, the f i r s t year continuous education courses are called Telecommunications Principles, Practical Mathematics and Engineering Science. The second year continuing education courses are called Telecommunications Principles A, Mathematics A and Computers A. The third and fourth years bear the letters B and C for each course respectively. For the f i r s t year, Telecommunications Priniciples and Practical Mathematics are offered on Tuesdays and Thursdays respectively, from September to the f i r s t weeks in January. Engineering Science i s then available, on the same days of the week, from January to the f i r s t weeks of May. The same schedule is followed for the second year, i.e. Telecommunications Principles A and Mathematics A are offered from September to the f i r s t weeks in January, and Computers A from January to the f i r s t weeks of May. < 2Appendix A, Laboratory Materials in use for the Old Curriculum,p.36. STUDENT PERFORMANCE AND PERSISTENCE IN EXISTING PROGRAMS Day Program Students The enrollment for day programs in electronics is limited to a maximum of twenty students per class. Usually there are more applicants than spaces available for these courses. The selection of successful applicants i s done on the basis of pre-requisites and date of the application for admission. The basic pre-requisites c a l l for a certificate from secondary school, indicating the successful completion of the grade 12 mathematics and physics. Notification of e l i g i b i l i t y to enroll in these courses is on short notice, usually less than a week. A total of 18 students normally register in a starting course. As a point of general observation and previous experience, during the f i r s t week, two to three students decide to withdraw from the course, and another two students quit within the next two weeks. The remaining students, fourteen to sixteen, usually persist to the end of the course. The students who persist are usually very highly motivated. Some are sponsored by the Canadian Employment and Immigration Commission (C.E.I.C.) or other agencies, but in general they do not hold part-time positions. Thus, these students are able to spend full-time working on their studies. They are constantly involved with electronic equipment and appliances and have the opportunity to discuss problems in this area with more advanced students as well as with possible future employers. They often attend seminars offered by the local industry and they participate in f i e l d trips. A l l these contacts and exposure seem to strengthen their motivation, since they appear to be willing to study a l l the basic concepts, even those whose 5 6 usefulness is not apparent. In general they are active participants of the electronics discipline. Continuing Education Students The enrollment practices for continuing education students are similar to those of the day program. Although the academic background of the continuing education student is similar to that of the day program student, his persistence rate in these courses is much lower. As an average, eighteen students have enrolled each September to take the f i r s t year courses, but no more than ten to twelve of them finish their f i r s t year. Of those students who finish the f i r s t year, only five to seven students enroll in second year courses. Students in these courses are usually employed, though their employment may not be related to electronics. The great majority of them are employees of B. C. Telephone Company. Upon successful completion of their f i r s t year, this company revises and upgrades their work position. Therefore, i t is in the students' interest to finish at least the f i r s t year course. Salary increases for second, third and fourth years of education are not as substantial as for the f i r s t year. Other students who do not work for B. C. Telephone Company usually work for other electronics-related companies. They claim to be interested in improving their positions in the work force and in keeping abreast of the changes taking place in this rapidly advancing area. Finally, there are students interested in a general understanding of this subject in order to appreciate the latest products from the electronics industry. In general, these last students are not interested in studying the fudamental theorems in great detail, since electronics i s usually only of 7 general interest to them. These students may work during the day on something that i s unrelated to electronics. They lack contacts and exposure in the electronics industry and quite often do not discuss electronics matters at work. They often admit to being just observers on what is going on in electronics, rather than participants. Some of these students are not willing to spent time studying concepts unless an immediate application i s found. This last group of students does not enroll in more advanced courses because: a) Unless the student satisfies the pre-requisites for more advanced courses, he w i l l not be admitted to them on the basis that the electronic equipment used in advanced laboratories could be hazardous to persons without their knowledge of safe and appropriate procedures. b) Even i f they are accepted into the theory portion of more advanced courses, they would be unable to comprehend the advanced concepts because of their inadequate foundation in this area. c) The school w i l l not run a course i f the number of students is fewer than twelve, and usually there are insufficient applicants for these advanced courses. Accordingly, few eligible continuing education students endure the f i r s t sessions of these courses, because these courses are based on a curriculum that offers no opportunities for their active participation. Instead of involvement, this old curriculum requires the students' acceptance of a coverage which most of them find unrelated to what they want to learn. I D E N T I F I C A T I O N OF INADEQUACIES OF CURRENT APPROACHES The Old Curriculum The old curriculum requires the student to study the basic electrical coverage as i t i s defined from a disciplinary standpoint. Students often have d i f f i c u l t y identifying the purpose of this basic coverage because i n i t i a l l y they do not have the knowledge to enable them to relate that basic coverage to the modern devices they want to assemble and operate. Also typically nobody explains the relationship to them. The coverage of this basic e l e c t r i c a l material takes most of the i n i t i a l time allocated in the old time schedules, a fact which discourages many students who do not have the desire to endure long periods of study in matters that do not seem related to their immediate occupational goals. In these traditional courses the student is held responsible only for the material described by a rigi d curriculum and is required to attend classes in which the instructor delivers canned audiovisual presentations without discussion. These students are not participants in the planning of their studies and they are not given the opportunity to learn how to define their goals or how to achieve them. Most of the students who endure the old curriculum do so in order to achieve an accreditation that eventually might be used to obtain a salary raise from the employers who subsidize part time studies. Regarding the expectation of a raise as a motivating factor we make reference to Malcolm S. Knowles. He considers the objective "being able to make more money" an important incentive to learning but he calls i t an ' Interes t " rather than a "need" and adds: 8 9 Interests are relevant to the adult educator's technology but in relation to his mission we are talking about something different and more fundamental - indeed, about something about which individuals are less conscious than they are of their interests. We are talking about the more ultimate needs and goals of human fulfillment. (1) The fact that most students motivated by the expectation of a salary raise endure only one year of the old curriculum indicates that while their interests are satisfied, their ultimate needs are not being f u l f i l l e d . The old curriculum does not consider the student's ever-changing needs and the contents of this curriculum are presented in a standard way to the student who is expected to accept their validity without question. This situation constitutes a violation of the modern practices of adult education, because, as is pointed out by Knowles: There is a distinct shift in emphasis in andragogy away from the transmittal techniques so prevalent in youth education - the lecture, assigned readings, and canned audio-visual presentation - toward the more participatory experiential techniques. Indeed, "participation" and "ego-involvement" are 1 Malcolm S. Knowles, The Modern Practice of Adult Education, (New York: Association Press, 1977), p. 23. 10 boldfaced words in the lexicon of the adult educator, with the assumption often being made that the more active the learner's role in the process, the more he is probably learning. (2) The aftermath of using a standard curriculum without any consideration of differences among the adult students is that many of them leave the class- room after the f i r s t session and do not return. The New Curriculum The new curriculum relates more closely than the old to the developments that have attracted students to take a course in electronics. It teaches them how modern electronic circuits operate. By outlining the possible interconnections needed to produce the complex devices these students are eager to assemble, i t makes the application of the knowledge readily apparent. A common example is that of students who want to learn electronics so that they can i n s t a l l visual displays in their cars, such as d i g i t a l clocks, speedometers, tachometers or voltmeters. The new curriculum i s designed to teach students as early as possible about the most common modern circuits used to make up those complex devices; how these circuits work; how to connect them; how to look for their corresponding technical specifications; how to evaluate their advantages and limitations; the kind of power supplies needed to operate them; how to select the components needed from technical catalogs; how to evaluate their cost; and how to assemble the devices. 2Malcolm S. Knowles, The Modern Practice of Adult Education, p. 45 11 I set out to develop the new curriculum following the guidelines of superior conditions of learning from Knowles3 which c a l l for a high level of student involvement. Thus, I have allowed the new curriculum to offer the student the opportunity to contribute suggestions regarding the depth of coverage as well as suggestions on special applications that they want to learn. This feature gives the students the opportunity to get involved in their own learning immediately at the beginning of their course. Such involvement at the beginning of previous courses seldom took place, because the contents of previous curricula c a l l for the lengthy coverage of basic material before the students can begin to appreciate how this coverage w i l l satisfy their original interests in particular applications. Students taking courses using this old approach must endure a coverage that in i t s i n i t i a l stages appears unsatisfactory and remote to their f e l t needs, fa i l i n g thus to promote their involvement. The approach and coverage of the new curriculum requires that the instructors find out, during the fir s t , session, what is i t that the students want to learn and the type of applications in this f i e l d that interest them most. Then, based on the students' response, the instructors must set out to determine the necessary depth of coverage and extra materials needed to satisfy those desires in the shortest possible time. This approach is possible because of a new and careful selection of material coverge u t i l i z i n g present technical innovations. When I discussed the new plan and content for the achievement of 3Malcolm S. Knowles, The Modern Practice of Adult Education, p. 52. t h e i r objectives with the students, I found they did not object to the challenge of p a r t i c i p a t i o n , and w i l l i n g l y set out to research and study on t h e i r own. This corroborated Knowles' statement that learning i s i n t e r n a l l y motivated and: The important implication f o r adult-education p r a c t i c e of the fact that learning i s an i n t e r n a l process i s that those methods and techniques which involve the i n d i v i d u a l most deeply i n s e l f - d i r e c t e d i n q u i r y w i l l produce the greatest learning. (*•') Teaching Practices Some i n s t r u c t o r s claim that the old curriculum contents are not sui t a b l e f o r discussion, at le a s t during the i n i t i a l stages of the course They f e e l that new students w i l l require long periods of t r a i n i n g before they can make any worthwhile contribution. Therefore, these i n s t r u c t o r s d e l i v e r t h e i r lectures using a f a c t u a l approach without any discussion. These teaching approaches v i o l a t e the modern practices of adult education because they f a i l to involve the students. Textbooks Most of the texts suggested f o r previous courses i n e l e c t r o n i c s are no more than f a c t u a l presentations of the theory i n t h i s f i e l d . ^Malcolm S. Knowles, The Modern Practice of Adult Education, p. 51. 13 The following i s a l i s t of commonly recommended reference books f o r e l e c t r o n i c s courses at PVI: Herbert W. Jackson, Introduction to E l e c t r i c C i r c u i t s , (New Jersey: P r e n t i c e - H a l l , 1981) Bernard Grob & Milton S. Kiver, Applications of E l e c t r o n i c s , (New York: McGraw-Hill, 1966) Training Publications D i v i s i o n of the Naval Personnel Program Support A c t i v i t y , Washington, D. C , Basic Electronics,(New York: Dover, 1973) Robert L. Shrader, E l e c t r o n i c Communication, (New York: McGraw-Hill/ Gregg D i v i s i o n , 1980) T. A. Lovelace, Engineering P r i n c i p l e s , (Hong Kong: Thomas Nelson and Sons, 1976) R. N. Renton, Telecommunication P r i n c i p l e s , (Bath, Great B r i t a i n : The Pitman Press, 1973) G. L. Danielson & R. S. Walker, Radio and Line Transmission, (London: I l i f f e Books, 1969) The design of the above books antici p a t e s that the approach w i l l be accepted by the students without question regarding t h e i r v a l i d i t y , therefore " t h e i r approach i s not conducive to student involvement and v i o l a t e s fundamental p r i n c i p l e s of adult education. The c i r c u i t schematics presented i n most textbooks are i n general not meant to be assembled. These schematics are meant to i l l u s t r a t e i s o l a t e d t h e o r e t i c a l d e s c r i p t i o n s . Besides being incomplete, these schematics depict c i r c u i t s that often w i l l not work when connected as shown i n these textbooks. This i s why i n most present day books the schematic diagrams are drawn quite small, since the author does not expect the student to attempt t h e i r assembly, therefore neither the author nor the publisher i s concerned about t h e i r l e g i b i l i t y i n a laboratory s e t t i n g . — Only persons with extensive knowledge of e l e c t r o n i c s would f e e l confident enough to even attempt assembling these c i r c u i t s , which require a great deal of knowledge, resources and time. These persons must be w i l l i n g to investigate the many sources of t e c h n i c a l data and be able to read, i n t e r p r e t and understand such sources. They must also possess a working and p r a c t i c a l knowledge of commercially a v a i l a b l e components and be f a m i l i a r with the wide range of expensive laboratory equipment needed to assemble and test prototypes of these c i r c u i t s . In essence,these persons must have a deep understanding of laboratory procedures, component s e l e c t i o n , test procedures and trouble-shooting techniques and must f e e l quite confident i n t h e i r a b i l i t y to assemble p r o j e c t s . These persons are not average students and constitute only a small minority compared with the vast majority who are eager to a t t a i n an adequate l e v e l of expertise. The average student who attends adult education courses becomes quite f r u s t r a t e d i n h i s attempts to assemble a c i r c u i t from the skimpy information provided by ordinary textbooks because he does not have t h i s advanced knowledge. To the average student the task of comprehending t h i s kind of presentation i s not only an immense obstacle i n h i s learning but also i n h i b i t s h i s gaining the necessary confidence to proceed success- f u l l y with studies i n h i s chosen f i e l d . This i s probably one of the reasons many students become despondent i n t h e i r e f f o r t s to learn e l e c t r o n i c s . Students who are determined to continue t h e i r studies using these books quite often f i n d themselves unable to describe the operation of various c i r c u i t s without making constant reference to the text. This i s because these students have not been given the opportunity and guidance to become involved i n the development, the p r a c t i c a l assembly, and the t e s t i n g of those c i r c u i t s . 15 While searching for a suitable textbook to be used with the new proposed curriculum, i t soon became apparent to me that none of the available books contained the desired coverage nor conformed to adult education standards. Many books were found to be out of date, some were too advanced for use in continuing education courses and s t i l l others could only be used as technical reference manuals. The out-of-date books do not address the present needs of the students. Many of these books s t i l l show the use of obsolete devices, such as vacuum tubes, which are no longer commercially available. 5 Most of them do not consider integrated circuits in their coverage. The advanced textbooks expect the learner to be familiar with a l l the basic literature, i . e. they assume that the learner has acquired most of the basic knowledge as well as most of the more advanced concepts (which take many years of intense study to acquire), in order to appreciate much of the material that the authors consider unnecessary to explain. These books are apparently intended for university students or graduates in the sciences and not for the average person who does not possess many of the pre-requisites. 6 5Bernard Grob & Milton S. Kiver, Applications of Electronics,(New York: McGraw-Hill, 1966) Training Publications Division of the Naval Personnel Program Support Activity, Washington, D. C., Basic Electronics, (New York: Dover, 1973) Robert L. Shrader, Electronic Communication, (New York: McGraw-Hill/ Gregg Division, 1980) T. A. Lovelace, Engineering Principles, (Hong Kong: Thomas Nelson and Sons, 1976) R. N. Renton, Telecommunication Principles, (Bath, Great Britain: The Pitman Press, 1973) G. L. Danielson & R. S. Walker, Radio and Line Transmission, (London: I l i f f e Books, 1969) 6Joseph A. Edminister, Electric Circuits, (New York: McGraw-Hill, 1965) T. P. Sifferlen & V. Vartanian, Digital Electronics with Engineering Applications, (Englewood C l i f f s , N. J. : Prentice-Hall, 1970) 16 Another kind of book i s the te c h n i c a l manual published for diverse e l e c t r o n i c s companies. These manuals are meant to be used only for the tr a i n i n g of employees within the p a r t i c u l a r company that issues them. The manuals u s u a l l y contain reference material about the construction and operation of the company's products and equipment. To understand t h e i r contents, and employee must receive i n s t r u c t i o n from a company's t r a i n i n g supervisor, usually i n s p e c i a l i z e d t r a i n i n g centers where the d i f f e r e n t products and equipment are discussed. In general i t i s very d i f f i c u l t to interpret the contents of these manuals without the equipment or the guidance of a person conversant with i t . Therefore, these manuals are unsatisfactory for s e l f - d i r e c t e d studies. They can be c l a s s i f i e d only as reference m a t e r i a l . 7 F i n a l l y there are books of the "cookbook" type which contain a se l e c t i o n of c i r c u i t schematics c o l l e c t e d from a wide range of designers. Many of these books advertise t h e i r projects as: "do-it-yourself e l e c t r o n i c s " and promise that a l l the projects are easy to b u i l d . The presentation of these c i r c u i t s i s not organized i n an educational manner, since no educational outcomes are expected nor planned for the person who purchases the book. The purpose of the books i s generally l i m i t e d to serving as The following are examples of company publications using this approach: IBM Systems Development Division, 1443 NI Printer, (North Carolina: IBM Product Publications, 1968) Olivetti/General Electric, GE 115/2 CR 10 Subsystem, (Italy: General Electric Information Systems Division, 1966) Hewlett Packard, Model 2402A Integrating Digital Voltmeter, (Palo Alto, California: Hewlett Packard Company, 1969) The Decca Navigator Company, Loran C (Long Range Aid to Navigation) Model DL91, (Surrey, England: Decca Technical Publications Department, 1975) 17 •> reference material for experienced technicians who design electronic c i r c u i t r y . 8 The type of presentation used in technical manuals is useful when company trade procedures are to be kept relatively private among the employees of those companies. Unfortunately, many authors make use of similar presentation in their books. One of the immediate results is that these books appeal only to a few selected students. David Hume9 pointed out to me on a conversation held last May 1981, that the above textbook presentations appeal to some instructors, unsure of themselves, who find satisfaction from the admiration and respect that they seem to command when they interpret the content of those books to their students. Mr. Hume indicated also that these instructors generally do not appreciate books with clear presentations because such books eliminate the satisfaction that these instructors derive from interpreting obscure texts. I find that this type of presentation leads to frustration for most students, and misleads them into thinking that the subject is beyond their capabilities unless they receive adequate help. Don Lancaster, TTL Cookbook, (Indiana: Howard W. Sams, 1977) Don Lancaster, CMOS Cookbook, (Indiana: Howard W. Sams, 1978) 'David Hume, Director of Extension Services, British Columbia Institute of Technology, Burnaby, B. C. TECHNICAL FACTORS LEADING TO THE DEVELOPMENT OF THE NEW CURRICULUM AND THE NEW TEXTBOOK Present technical innovations have made possible the development, production and marketing of micro-miniature electronic circuits. These circuits are known as Integrated Circuits (IC's) and are available to the consumer in conveniently sealed packages. Compared with previous conventional circuits they are physically small, inexpensive, require small amounts of power to operate, are very reliable and can be used in many applications. These are the main reasons why they are replacing with an unprecedented rapidity the big, bulky, and expensive circuits that formerly were custom built for each particular application or piece of equipment. Integrated circuits contain thousands of electronic components reduced by photographic means into microscopic sizes. They are then enclosed into small packages and are ready to be used. Their production in large quantities has permitted manufacturers to reduce their price, making their use economically attractive. The electronics equipment that uses integrated circuits is smaller, lighter, requires less power to operate, and i t s repair and maintenance are greatly facilitated by the easy replacement procedures possible only with integrated ci r c u i t s , further reducing the costs of their operation. Integrated circuits are compatible with different electronic configurations, and can be reused repeatedly. This universal acceptability of a common set of circuits is already paving the way to an overall standardization in the electronics industry that w i l l affect a l l the present industrial processes. Examples of this acceptance can be found easily, such 18 19 as i n the c i r c u i t s used to represent voice and t e l e v i s i o n images. These t e l e v i s i o n images are being transmitted from country to country, where d i f f e r e n t and incompatible t e l e v i s i o n systems may be i n use, by decoding and t r a n s l a t i n g d i g i t a l information into t h e i r own t e l e v i s i o n system p r i o r to l o c a l re-broadcasting. Another example i s the use of l a s e r beams to carry telephone conversations, where these conversations are transmitted d i g i t a l l y . Even more recently, d i g i t a l records have made t h e i r appearance i n the consumer's market. The present state of the e l e c t r o n i c s technology o f f e r s the p o s s i b i l i t y of new material coverage i n order to give the student the option for a simpler and shorter approach to h i s learning. The long periods of t r a i n i n g needed using t r a d i t i o n a l approaches discouraged many students from taking the course. Thus the new curriculum c a l l s f o r a change of the t r a d i t i o n a l order of presentation of topics that does not hamper the students' future progress. The development of the new curriculum required the rearrangement of previous materials, the addition of new materials, and the a p p l i c a t i o n of the l a t e s t innovations i n e l e c t r o n i c s . Instead of teaching the fundamental ideas on the components and design procedures that make up an e l e c t r o n i c c i r c u i t , the new curriculum begins by teaching the operation and use of i t s pre-assembled equivalent, which i s what many students are eager to l e a r n . The experience gained by the student while using and operating pre-assembled c i r c u i t s can be used then to f a c i l i t a t e h i s understanding of the basic theorems and mathematical p r i n c i p l e s behind them. Thus the new curriculum provides the students with the basic p r a c t i c a l applications of e l e c t r o n i c c i r c u i t s and f a c i l i t a t e s t h e i r future progress and advancement i n t h i s f i e l d . Many attempts have been made to modify the old curriculum i n order to accelerate the coverage of basic material. This has been done to introduce students much sooner to the applications that they want to learn. However a l l of these attempts have been unsuccessful, since they involve the removal of material from and old curriculum which does not lend i t s e l f to such changes, and the students s t i l l have to learn the removed material at unplanned stages of t h e i r course. The new course and textbook are designed to involve the student, so that he can develop the confidence and a b i l i t i e s exhibited by highly q u a l i f i e d technicians i n the design, assembly, and t e s t i n g of e l e c t r o n i c c i r c u i t s and thus come to understand the procedures and techniques of t h i s f i e l d . DEVELOPMENT OF THE NEW CURRICULUM AND THE NEW BOOK During the development of the new course and book, i t seemed essential that relevant laboratory experiments were needed to follow any theoretical description mentioned in the text so that the student could verify that the theory i s correct and thus proceed confidently to the next stages of his learning, because he now knows that what he is doing is right, not because i t is written in a book but because the student himself has been able to verify i t with actual electronic circuitry. The new course and new book c a l l for the student to verify the theory behind each circuit at a l l levels of his training, from basic circuits to more advanced ones. This verification i s facilitated with laboratory components whose careful selection allows the students to assemble, test, and prove to themselves that the theoretical statements in the book are indeed correct. 1 Pre-requisites for the New Course The pre-requisites for the new course and the understanding of the book do not include university level mathematics or physics. In fact, the knowledge acquired by students who have completed courses such as tenth grade mathematics or physics is often sufficient to enable these students to complete the course successfully. Thus the course and i t s textbook become suitable for a great number of students, i . e. for students with related advanced studies as well as for those students that are newcomers to the f i e l d . 1Appendix F, Electronic Systems Book, p. 8 21 I have found that most of the advanced students generally welcome a thorough review of materials already familiar to them, because a review seems to refresh and reinforce their previously acquired knowledge. They also profit by learning new applications to this knowledge. As for the students with only a basic understanding of mathematics, they find that the material is explained in simple terms with plenty of analogies to which they can relate and understand. The new curriculum and i t s book follow the procedures outlined by Knowles, who asserts: The central dynamic of the learning process is thus perceived to be the experience of the learner, experience being defined as the interaction between an individual and his environment. The quality and amount of learning is therefore clearly influenced by the quality and amount of interactionbetween the learner and his environment and by the educative potency of the environment. The art of teaching is essentially the management of these two key variables in the learning process - environment and interaction - which together define the substance of the basic unit of learning, a "learning experience." The c r i t i c a l function of the teacher, therefore, is to create a rich environment from which students can extract learning and then to guide their interaction with i t so as to maximize their learning from i t . (2) This learning experience is accelerated by the confirming results from relevant laboratory experiments and produces the desired level of 2Malcolm S. Knowles, The Modern Practice of Adult Education, p.51. involvement of students as well as of the instructors who conduct the course. The application of these principles in the text has also permitted advanced students to use i t as a self-study guide. 3 T i t l e of the New Book The t i t l e "ELECTRONIC SYSTEMS" was chosen for the textbook because i t considers the circuits used in the evaluation, analysis and control of measurable physical phenomena. In present day technology, physical phenomena measurements are represented by equivalent values of voltage, known as ANALOG VOLTAGES, prior to their electronic processing. Electronic processing consists in storing, analyzing and comparing analog voltages against standard values that the designer or user may consider as desirable, e. g. the setting of an a±r conditioning d i a l to a desired temperature. Twenty years ago, electronic processing was done using mostly analog devices, however these devices were useful to control only a limited number of physical applications. Now, thanks to the great ve r s a t i l i t y of available d i g i t a l systems, that employ a universal mathematical system, the only restriction placed on analog voltages of any origin is their conversion into a d i g i t a l form. This analog to d i g i t a l conversion (ADC) combines both analog and d i g i t a l techniques. After the above conversion has taken place, the resulting figures are processed d i g i t a l l y and the answers converted back into analog voltage form. These analog results are then used to activate electrical controls that correct the intended physical phenomena. The d i g i t a l to analog conversion (DAC) also makes use of d i g i t a l and analog techniques. This book and the 3Appendix E, Field Testing from Whittier Union High School District. new curriculum are concerned with ADC and DAC procedures, as well as with the basic processes taking place in the d i g i t a l processor, therefore the contents cover both d i g i t a l as well as analog techniques, and justify the t i t l e "ELECTRONIC SYSTEMS". .SELECTION CRITERIA FOR LABORATORY COMPONENTS As previously discussed, the development of integrated circuits offers countless possibilities to improve on previous approaches. Their availability has facili t a t e d the development of this new curriculum, permitting the introduction of advanced circuits at much earlier stages of the students' training than was possible before. In the new coverage i t is no longer necessary to discuss the principles that led to the design of these integrated circuits, nor the operation of each of the components used in their construction, because this i s the primary concern of design engineers. Therefore the new coverage considers only their operation and applications, which is what most students want to learn. If a student were to assemble an equivalent circuit using the regular standard components, he would find that the resulting assembly occupies several hundred times the space of the original integrated c i r c u i t . The student not only would be faced with increased space requirements, but also would have to waive the advantages that integrated circuits have on the previous technology, such as reduced power requirements, low static interference between components due to their close proximity, and above a l l , low costs that result from their production in assembly lines. For example, the purchase of an oscillator circuit in integrated circuit form, such as the 555 and which has been pre-tested to insure i t s proper operation, costs only 38 cents. 1 On the other hand, the assembly of i t s equivalent ci r c u i t using standard components that require an area comparable to that of a 1Appendix C, Cost of Laboratory Components for the New Curriculum. 25 26 standard brief case, costs in the v i c i n i t y of $70.00. Thus the new technology also offers immense possibilities to improve on the cost of the components used in previous teaching approaches. Up to the present, hundreds of dollars have been spent on standard laboratory equipment. If a student wants to purchase these standard laboratory f a c i l i t i e s he would have to be prepared to invest at least $1000.00 in order to purchase power supplies worth up to $300.00, volt-ohmmeters worth up to $200.00, signal generators worth up to $200.00 and a few other pieces of test equipment. This estimate does not include oscilloscopes, since their unit price i s close to $1500.00. Compared with these costs, the use of integrated circuits described in the new curriculum and book amount to $47.20.2 The power supplies consist of inexpensive six volt batteries, that are sufficient to provide the power requirements of most integrated circuits. The components listed for the new curriculum also include the necessary parts to assemble an electronics test probe that i s used as a voltage indicator throughout the course, 3 and the parts needed to assemble a signal generator.1* It should be noted that the laboratory components used in standard laboratories and those proposed in the new curriculum are equally satisfactory in carrying out the experiments of the new curriculum, but not their price as indicated above. The size of the components needed for this course, besides being within the economic reach of the students, f a c i l i t a t e s their transportation. This factor allows students to take them home and carry out experiments there that otherwise would never have been possible using standard f a c i l i t i e s . 2Appendix C, Cost of Laboratory Components for the New Curriculum. 3Appendix F, Electronic Systems Book, Section 1. 4Appendix F, Electronic Systems Book, Section 5. Technical c r i t e r i a for the selection of these components was based on their ease of handling and operation. Some specialized components can be damaged easily at the touch of the hand due to electrostatic charges in a human body. Special procedures are required for their handling. Their use was avoided to eliminate concerns that might distract the students while performing their laboratory experiments. Finally, another c r i t e r i a for the selection of laboratory components was their repeated use in different experimental configurations throughout the course. This consideration was meant to further reduce the cost of the components needed in the course without affecting the coverage of the book. This factor also helps students to realize that the same component can be used in different configurations to perform different functions. RECOMMENDATIONS FOR THE USE OF THE TEXTBOOK The proposed course and textbook are meant _£o provide the students with basic and fundamental coverage as well as with the advanced material required to understand and u t i l i z e the most recent developments in this f i e l d . They also aim to provide the students with the procedures needed to allow them to conduct their own inquiry and plan their own learning in this f i e l d . This is because the new curriculum is based on Knowles' guideline that the greatest learning is produced by methods and techniques that involve the students in their own self-directed inquiry. This does not mean that an instructor using the new curriculum should give up his responsiblility, but that he now has the option to use a process of reasoning and demonstration to convince the students of the u t i l i t y of the objectives that he suggests. Therefore instructors using the new curriculum and book are required to conduct class discussions in order to: consider the students' needs and goals, to help the students relate the new contents with their own goals, and to allow them to undertake reasonable objectives within the length of the course. Students with a sound knowledge and experience on technical matters can be expected to achieve much more in a shorter time than students who lack that kind of background. The new curriculum and book permit students of different backgrounds the opportunity to achieve their individual goals, providing the instructor i s willing to coordinate and lead them in the achievement of their expectations. 28 FIELD TESTING OF THE BOOK AND THE NEW COURSE The f i r s t time the new curriculum was offered to students was during the winter session of 1979-1980 under the name of Electronic Systems Parts I and II. The students enrolled in this f i r s t course included high school teachers, engineers, el e c t r i c a l and electronics technicians as well as people with a general interest in this subject. Their diverse backgrounds provided the opportunity to test the efficacy of the new curriculum and i t s recommended teaching practices. The new curriculum proved effective in involving a l l the students in class without inhibiting the progress of the more advanced students. This involvement was evident by the excellent student attendance recorded from the beginning to the end of the course. 1 During the i n i t i a l winter session, I also carried out minor modifications on the curriculum under test, in order to improve the general continuity of i t s presentation. These changes led to the f i n a l preparation of the present curriculum in the summer of 1980,2 and the completion and subsequent publication of the new book in September 1980.3 This new curriculum was successfully tested once more during the winter session of 1980-1981. The students performance has been assessed on the basis of their a b i l i t y to design and assemble practical electronic devices, and not on a f i n a l exam. At the end of these courses each student has been requested to present projects that work as intended, according to the principles behind their operation. These students have shown a great degree of confidence in Appendix D, Attendance Records of Courses using the New Curriculum. 2Appendix B, The New Curriculum. 3Appendix F, Electronic Systems Book. 29 the selection of electronic components, in the assembly of circuits and in the use of test equipment. These factors corroborate the efficacy of the new curriculum that helps them achieve their desired goals at an earlier stage of their training than the longer periods previously expected from the old curriculum. The same findings have also been reported by other instructors at the Pacific Vocational Institute using this curriculum as well as at high school levels.^ 4Appendix E, Field Testing from Whittier Union High School District -INSIGHTS ACQUIRED FROM THE FIELD TEST The response from other instructors and teachers from PVI as well as from other institutions indicate that most of them have found the new curriculum and the new book most useful in their task. Their results confirm that there i s an increased participation and involvement of students taking this course, and that advanced students have even managed to use the text as a guide to their self-directed study. 1 Some instructors have mentioned that a few of their less advanced students have experienced d i f f i c u l t y understanding some basic mathematical concepts. Since the course calls for a basic knowledge of mathematics and el e c t r i c i t y , I set to investigate the cause of these isolated d i f f i c u l t i e s . My impression is that in the introduction of new mathematical concepts, these instructors do not provide as many analogies as needed by these students so that they can relate the new concepts with their own experience. Therefore, in a second edition of this book more analogies w i l l be included and others suggested to the instructors to further f a c i l i t a t e i t s readability to the largest possible number of interested students. Additional material w i l l include problems, more exercises and examples and the insertion of technical.data as originally intended but withheld pending the permission to reprint from electronics manufacturers. t 1Appendix E, Field Testing from Whittier Union High School Di s t r i c t . 31 CONCLUSION At the Pacific Vocational Institute I observed a problem with continuing education courses in electronics. Students would enroll in beginners' courses but many of them would drop out after a few sessions. This situation seemed inconsistent with their i n i t i a l interest. In my investigation of their reasons for discontinuing their course, i t became apparent that they were discouraged by methods of instruction that failed to involve them and also by a curriculum whose contents did not appear related to the applications that they wanted to learn. To solve this problem I constructed a new curriculum by combining two major developments: the modern principles of adult education as outlined by Knowles;and the most recent innovations that our present electronics technology has to offer, namely pre-assembled circuits. These two developments were put together to produce the new book "ELECTRONIC SYSTEMS"1 which requires adult education principles for i t s use and places great emphasis on the students' involvement. The f i e l d tests done on the use of the new curriculum and the new book have basically confirmed the u t i l i t y of the approach. The successful application of these principles is reflected by the popularity and interest that the course is enjoying, the regular attendance from participating students, the reports of successful f i e l d testing from other instructors and their financial backing in the purchase of books and accompanying electronic components. •'•Appendix F, Electronic Systems Book. 32 APPENDIX A CURRICULUM COVERAGE OF THE TEN MONTH DAYTIME PROGRAM During the f i r s t month of the daytime program, electronics is taught with emphasis on the physical characteristics of the elements and materials used in e l e c t r i c i t y . The present day theories about the atomic nature of el e c t r i c i t y are discussed, as well as the conduction of electric currents through different media, i . e. solids, liquids and gases. The Systeme International (SI) is introduced. To i t s basic three units to measure length, weight and time, a fourth unit is added: the AMPERE. This last unit i s used to measure electrical currents, and together with the previous three units, i t defines the essential aspects of an electrical system. The need to represent quantities numerically is self-evident, because any measurement must be taken in relation or comparison with known values. A few examples of these comparisons are: twice as fast as, half as loud as, three times as heavy as, five times as far as. The student is also taught that electrical quantities have a wide range of values, varying from millionths of a given quantity, to millions and billions.of another quantity. This wide range of values brings the need for special notations, which are presented to the student as "Scientific Notation" or also called "Engineer's Representation of Numbers". In these notations, quantities are represented by a digit, 1 to 9, with or without a decimal, times the base number 10, and this base number may use positive or negative exponents as required, e.g. 7.2 x 10 6. 33 — Besides the above system, the student is introduced to the prefixes used by the electronics industry, such as MEGAhertz ( one million hertz), or NANOsecond (one b i l l i o n t h of a second). The student i s taught to relate the s c i e n t i f i c notation to the industry's jargon. The four basic elements that constitute an electric system are introduced: (1) Power Sources; (2) Conductors; (3) Control Elements, such as switches and fuses; (4) The Work-load, i . e. anything that requires ele c t r i c i t y to do an intended amount of work. During the second month, the student learns what physical characteristics of matter oppose the^flow of electrical currents. The student . gets inititated into the study of one of the three properties of ele c t r i c i t y , i . e. RESISTANCE,which is the property that opposes the flow of electrical currents. During the third, fourth and f i f t h month, the student learns electrostatics and magnetism, studies that lead him into the remaining two other properties of e l e c t r i c i t y , i . e. CAPACITANCE and INDUCTANCE. During this period, the student is also introduced to circuit analysis techniques, that w i l l enable him to predict how a given circuit w i l l react to particular conditions of current and voltage, where the sources of energy for these studies consist of: a) Direct Current (DC), where the currents or voltages do not vary with respect to time. b) Alternating Current (AC), for given frequencies, where the currents or voltages alternate, being positive for one half a cycle and negative for the other half. The student i s taught appropriate mathematical procedures, known as Complex Variable, to help him determine the physical response of a circuit under this type of source, c) Transient Conditions and response to Pulses. At this stage, the student needs to use more advanced mathematical procedures, in order to determine how a circuit w i l l react to any particular pulse. These advanced mathematical procedures include the use of calculus. The circuit analysis techniques are based on physical laws f i r s t defined by earlier scientists and that bear their names. These basic laws used in e l e c t r i c i t y are know as Ohm's Law, Kirchhoff's voltage law, and Kirchhoff's current law. These cir c u i t analysis techniques include: a) Equivalent Circuits, where a circuit gets replaced by a dummy load without any effect on the source under study, and then the total current i s defined, e. g. the loudspeaker in a radio may be replaced by a resistor, and though there is no sound, a l l the circuits continue normal operation. b) Black Box Concept, which considers any circuit as a source together with an el e c t r i c a l component called impedance. Impedance is the name of the combination of one or a l l the three basic properties of e l e c t r i c i t y , i . e. Resistance, Capacitance and Inductance. Through this black box concept, a very complex circuit feeding power into a load, is replaced by a simple pair of elements, and the load w i l l not miss any of i t s original: supply circuits. As an example we can consider AC/DC pocket calculators, which may be plugged into the power outlets or may be used with batteries. The theorems that define the black box concept are known as: Thevenin's Equivalent Circuit and Norton's Equivalent Circuit. c) Loop Analysis Techniques, derived from Kirchhoff's voltage law. d) Node Analysis Techniques, derived from Kirchhoff's current law. In the sixth month, when the above principles and techniques have been mastered by the student, the student is introduced to devices that have the a b i l i t y to amplify electrical signals. These devices are known as active components and include tubes and transistors. The basic physical properties of matter are discussed in order to explain the operation of these devices. During the seventh and eighthmonths, the student begins to study the basic electronic circuits. These basic circuits, common to any electronics application, f a l l under any of the three following groups: (1) Rectifiers; (2) Amplifiers; (3) Oscillators. During the ninth and tenth months, the student begins to study specialized applications, such as: Radio Transmission, Radio Reception, Radar, Television, Microwave and Telephone Communications, Computers, Satellite Communications, Marine and Aircraft Electronics and Control Electronics. Laboratory Materials in use for the Old Curriculum The student is issued a laboratory k i t . The kit contains tools and a set of discrete e l e c t r i c a l components. Some of the tools include: soldering irons, pliers and screw drivers. The e l e c t r i c a l components 37 include: resistors, capacitors, coils and chokes, transformers and connectors. The test equipment is supplied as the experiments c a l l for i t . This equipment consists of Vacuum Tube Voltmeters, Volt-Ohmmeters and Oscilloscopes. The student also receives Power Supplies, Frequency Generators, Transistor and Tube Testers. The student spends about four months on experiments that are s t r i c t l y e l e c t r i c a l in nature. These experiments use discret components of the passive type such as resistors, inductors and capacitors. Another four months are spent in experiments that are electronic in nature. These experiments use active components, such as tubes and semiconductor devices. The semiconductors studied include: Rectifiers, Zener Diodes, Tunnel Diodes, Transistors and their applications to Amplifiers and Oscillators. APPENDIX B .THE NEW CURRICULUM The new curriculum has been covered in a new continuing education course at PVI. This new course has been taught in 32 evening sessions for a period of 16 weeks. Therefore, this appendix l i s t s i t s coverage based on a weekly basis. During the f i r s t week, the student is handed the electronic components used for the course. The student learns to identify them. This task includes the introduction to el e c t r i c a l color codes and the meaning of the physical size in these components. The student also learns to assemble a simple logical indicator, used to identify the presence of voltage. A basic explanation i s given regarding the operation of transistors when used as ordinary switches in this indicator. 1 The second week, the student i s introduced to Boolean Algebra. This is the algebra that defines the response of binary devices, i . e. those devices that have only two possible states like a switch which is either on or off. The student identifies the integrated circuits that w i l l produce the boolean functions defined in class, and proceeds to assemble and verify the accuracy of the mathematical statements that define their operation. 2 The third week, the student learns the laws of binary algebra and proceeds to corroborate their accuracy when the circuits described by this algebra are assembled and their response determined. The most basic form of binary addition i s then introduced. 1Appendix F, Electronic Systems Book, p. 4. ° 2Appendix F, Electronic Systems Book, Section 2 38 39 The fourth week the student learns the different number systems associated with computers to carry out arithmetic operations. He learns to interpret binary results and also to use electronic circuits capable of translating those answers to our decimal system using seven segment displays. The f i f t h week, the student is introduced to graphical methods designed to simplify the boolean algebra expressions. 3 Complex boolean statements as well as their simplified versions are implemented with electronic components and the student verifies that both circuits yield the same response but one is simpler and more economical to build than the other. Now the student is intoduced to the importance of the time element in logical circuitry. He learns the basic forms of memory used by most computers, and relates the storage of information with the application of timing pulses called Clock Pulses (CP's).1* The sixth week, the student learns the operation of more sophisticated units of memory and connects the corresponding integrated circuits to test their performance. He also learns the basic operation of electronic oscillators, plus the role of capacitors in the production of oscillations, and proceeds to assemble several types of o s c i l l a t o r s . 5 The seventh week, the student learns to use integrated circuit oscillators. The student calculates and measures their frequencies of oscillation and applies these frequencies to electronic counting c i r c u i t s . 6 3Appendix F, Electronic Systems Book, Section 3. 4Appendix F, Electronic Systems Book, Section 4. 5Appendix F, Electronic Systems Book, Section 5. 6Appendix F, Electronic Systems Book, Section 6. When an oscilloscope is available, the student is introduced to i t s use, so that he can observe the waveforms taking place in different circuits. Special laboratory exercises have been provided for students that do not have an oscilloscope, so that they can s t i l l observe the behaviour of different frequencies of oscillation. The eighth week the student learns how to produce any given count using electronic c i r c u i t s . 7 Different applications'are found for counters such as: the measurement of time in d i g i t a l clocks; the measure- ment of frequency in speedometers and tachometers; and the production of . light chasing effects used in advertisements. The ninth week the student is introduced to the Shift Register, 8 used to store strings of binary quantities. Their applications include the transmission of information between two separate electronic devices or the internal use within a d i g i t a l system. Visual Displays are covered during the tenth week, to decode the information stored in binary form and then display i t in the more familiar decimal notation. 9 During this same week the student is introduced to the Operational Amplifier 1 0 and i t s applications. The student uses i t to add two or more voltages and also to compare and detect the largest voltage from two different sources. The eleventh week the student learns to use operational amplifiers to shape various waveforms. He uses them to transform triangular waves into square waves.(differentiator-action), and square waves back into triangular waves (integrator-action). Waveshaping circuits find application in television circuits as well as in analogous computers. The student is also introduced 7Appendix F, Electronic Systems Book, Section 7 8Appendix F, Electronic Systems Book, Section 8 9Appendix F, Electronic Systems Book, Section 9 1 0Appendix F, Electronic Systems Book, Section 1 0 41 to the Digital to Analog Converter (DAC), a device that produces an output voltage proportional to the binary quantity stored in a register. The student is introduced to i t s various control applications such as brightness controls for illumination or speed controls for motors. The twelfth week is spent learning the operation of more sophisticated types of Digital to Analog Conversion circuits. The student i s introduced to equivalent ci r c u i t s , such as those described by Thevenin's Theorem.11 During the thirteenth week, the student i s introduced to the Analog to Digital Converter (ADC). This i s the electronic circuit used to convert the analogous voltages from external devices into binary quantities used for di g i t a l displays as well as in computer processing. The student learns different methods to obtain this conversion and assembles and calibrates his own circuits. During the fourteenth week, other ADC methods are studied and their corresponding circuits are assembled and tested. During this week the student i s also introduced to the design of power sources that use transformers and integrated circuits. The fifteenth week, the student learns to interface systems powered by low voltages to external devices that operate at higher voltages. He learns to apply different isolating techniques. The sixteenth week is spent learning computer languages and applying them to solve electrical circuit problems. As an example, the student learns to use the Ohm's Law Matrix, 1 2 to predict the response of electrical circuits to different applied voltages. The procedure described in the book is 1 1Appendix F, Electronic Systems Book, p. 232 1 2Appendix F, Electronic Systems Book, p. 241. 42 easily programmed into a computer and yields answers in fractions of the time needed by other methods. Laboratory Materials for the New Curriculum The laboratory components for the new curriculum are list e d in the hew book. 1 3 They were selected on the basis of their ease of handling and operation as well as of their repeated use in different experiments throughout the course. Their cost is within the economic possibilities of interested students. 1 I + Once the students learn their operation and some of their uses, they usually find many other applications for them, extending thus their usefulness. 1 3Appendix F, Electronic Systems Book, p. 8. 1^Appendix C, Cost of Laboratory Components for the New Curriculum. APPENDIX C COST OF LABORATORY COMPONENTS FOR THE NEW CURRICULUM The following table l i s t s the cost of the components needed f o r the new curriculum. The prices were quoted by the following l o c a l d i s t r i b u t o r s on January 13, 1981. RAE I n d u s t r i a l E l e c t r o n i c s Ltd./3455 Gardner Court/Burnaby, B. C. CAM GARD I n d u s t r i a l Electronics/2055 Boundary Road/ Vancouver, B. C. VARAH Electronics/2077 A l b e r t a Street/Vancouver, B.C. These d i s t r i b u t o r s quoted prices for i n d i v i d u a l items but these prices were based on the purchase of one hundred u n i t s . The lowest p r i c e of each item was chosen as representative of the value of each component, and i s l i s t e d on the l a s t column to the r i g h t . I t i s f e l t that t h i s i s the cost that a c a r e f u l shopper would normally have to pay for these components. ITEM INTEGRATED CIRCUITS 5 5 5 yA741 FND 5 0 7 4 0 6 6 7 4 0 0 7 4 0 2 QTY/KIT 1 2 1 1 2 2 RAE 0.45 0.39 2.04 0.95 0.35 0.35 P R I C E CAMGARD VARAH 0.38 0.46 1.79 0.89 0.36 0.36 0.75 0.51 1.83 1.06 0.46 0.46 LOWEST TOTAL 0.38 0.78 1.79 0.89 0.70 0.70 4 3 44 1 ITEM 7404 7410 7413 7427 7442 7447 7476 7486 7490 74107 74LS190 74LS283 QTY/KIT 1 1 1 1 1 1 2 1 2 2 1 1 RAE 0.44 0.35 0.63 0.62 0.58 1.63 0.50 0.68 0.53 0.77 2.72 0.90 P R I C E CAMGARD VARAH NIL 0.36 NIL 0.42 NIL 0.91 0.43 0.45 0.45 NIL 0.82 NIL 0.49 0.46 0.68 0.49 0.97 1.67 0.52 0.51 0.92 1.25 1.81 2.23 LOWEST TOTAL 0.44 0.35 0.63 0.42 0.58 0.91 0.86 0.45 0.90 1.54 0.82 0.90 SEMICONDUCTORS RED LED GREEN LED DIODE 1N4005 ZENER 1N761 2N2222 5 5 4 1 1 15.50/h 17.50/h 0.46 0.78 31.00/h 23.00/h 0.51 1.15 NIL 5.99/h 0.15 0.24 0.20 0.12 2.81 0.12 0.27 0.18 0.82 0.18 CAPACITORS lOyF (16V) 22yF (16V) 1 1 0.85 1.36 0.13 0.13 0.20 0.20 0.13 0.13 45 P R I C E ITEM QTY/KIT RAE -CAMGARD SARAH LOWEST TOTAL RESISTORS 430 tt h W 7 2.07/h 2.03/h 1.64/h 0.14 3.3 ,k« h W. 2 2,07/h 2.03/h 1.64/h 0.04 4.7 kfi % W 4 2.07/h 2.03/h 1.64/h 0.08 10 kfi. % W 6 2.07/h 2.03/h 1.64/h 0.12 22 kfi % W 2 2.07/h 2.03/h 1.64/h 0.04 39 Ml h W 4 2.07/h 2.03/h 1.64/h 0.08 82 kfi h W 6 2.07/h 2.03/h 1.64/h 0.12 1 Mft Jz; W 1 8.19/h 3.59/h 1.64/h 0.03 2.2 M̂  Jz; W 2 9.27/h 3.59/h 1.64/h 0.07 1 Mfi Potentiometer with thumbwheel 2 0.49 NIL 6.89 0.99 ACCESSORIES BREADBOARD (SK-10) 1 21.50 NIL NIL . 21.50 TRANS-BOX 1 NIL NIL NIL 7.22 TOTAL COST PER KIT $47.20 APPENDIX D ATTENDANCE RECORDS OF COURSES USING THE NEW CURRICULUM The following attendance records were compiled from the Continuing Education Registers at PVI. They correspond to the four times that the new curriculum has been covered in courses offered by this department. These courses were scheduled over a period of two consecutive winter-spring sessions. 1979 - 1980 SESSION (WINTER) Course Name: Electronic Systems Part I Scheduled dates: September 10, 1979 to November 5, 1979 Number of sessions Number of enrolled students Possible attendance (Students x Sessions) Absences Percentage of attendance Course Name: Electronic Systems Part II Scheduled dates: November 7, 1979 to January 21, 1980 Number of sessions Number of enrolled students Possible attendance (Students x Sessions) Absences Percentage of attendance 16 23 368 46 88% 16 10 160 16 90% 46 1979 - 1980 SESSION (SPRING) 47 Course Name: Computers A and Computers B Scheduled' dates: February 5, 1980 to May 13, 1980 Number of sessions 30 Number of enrolled students 8 Possible attendance (Students x Sessions) 240 Absences •. 8 Percentage of attendance 97% 1980 - 1981 SESSION ( WINTER) Course Name: Electronic Systems Part I Scheduled dates: September 15, 1980 to November 10, 1980 Number of sessions 16 Number of enrolled students 20 Possible attendance (Students x Sessions) 320 Absences 18 Percentage of attendance 94% Course Name: Electronic Systems Part II Scheduled dates: November 12, 1980 to January 19, 1981 Number of sessions 16 Number of enrolled students 20 Possible attendance (Students x Sessions) 320 Absences 27 Percentage of attendance 92% 1980 - 1981 SESSION (SPRING) 48 Course Name: Electronic Systems Part I Scheduled dates: January 21, 1981 to March 16, 1981 Number of sessions 16 Number of enrolled students 21 Possible attendance (Students x Sessions) 336 Absences 20 Percentage of attendance 94% Course Name: Electronic Systems Part II Scheduled dates: March 18, 1981 to May 13, 1981 Number of sessions . , 16 Number of enrolled students 15 Possible attendance (Students x Sessions) 240 Absences 37 Percentage of attendance 85% APPENDIX E FIELD TESTING FROM WHITTIER UNION HIGH SCHOOL DISTRICT -49 WHITTIER UNION HIGH SCHOOL DISTRICT 50 Whittier, California 90605 BOARD OF TRUSTEES: Joan Nay. Presidem • SUPERINTENDENT: Norman B. Eisen. Ed.D. Jerry Sarchet, Ph.D., Vice President ASSOC. SUPT.: Earle K. Fisher • Roy Sal as. Qerk • Eve Burnett, Henri Peliissier, Members ASST. SUPTS.: Arthur T. Hobson. Ed.D. • Seabron A. Nolin, Ed.D. March 27, 1981 To Whom It May Concern: Our school district has recently had the pleasure of reviewing and field testing an electronics text Electronic System by Miro Angeles. I personally reviewed the book regarding readability and format and found it to be very appropriate for a high school population. We had our most experienced and respected electronics instructor field test the book in his classroom/lab. He found the book to be very well laid out with the theory clearly presented and followed by lab experiments that the students found very relevant. Some advanced students used the book in an independent study mode and found it to be excellent. If you should have any further questions feel free to call. Sincerely yoiirs, Ronald 3. Rhodes Director, Pupil Personnel Services RJR:pb APPENDIX F ELECTRONIC SYSTEMS BOOK -51 52 53 E I E C f S O N I C S Y S T E M S © •)< MI HO ANGELES ^ 1980 DISTEIBU'l'ED BY: AB DIGTTECH CORP. STATION S, P. 0. BOX 76711 VANCOUVER, B. C. 54 TELL ME AED I WILL FORGET SHOW ME AND I MIGHT REMEMBER INVOLVE ME Aid I SHALL UJHJEESTAND To AMELIA, mother. -u - 5 7 ABOUT THE AUTHOR Mr. Angeles is a graduate in Electronics and Communications Engineering ( 1 9 5 8 ) , from the National Polytechnic Institute (Mexico City). He also holds a B. A. Sc. in Electrical Engineering from U. B. C. (1 9 6 6 ) and a Diploma in Adult Education from U. B. C. ( 1 9 7 2 ) . At present he is working toward a Master of Education Degree at U. B. C. Mr. Angeles is a registered Professional Engineer, in the Province of Ontario, where he has worked in different aspects of the electronics industry. He has extensive experience in computer software (programming) and hardware (circuit design). At the Steel Company of Canada, he worked as a design engineer in computer operated mills. _ Mr. Angeles holds a Professional Certificate from the B. C. Department of Education. He taught Computer Science and Electronics at Hillside-Secondary School and at present is an electronics instructor in a post secondary education institute in Burnaby, B. C. -{it- FOREWORD This book is written for Senior Secondary and Post Secondary Students, as well as for the interested Public in general. The book discusses the use and application of integrated circuits, treating them as building units. This way, the student does not need to learn electronics from the fundamentals, nor have more than grade 10 mathematics. The student learns to read and interpret technical data and soon becomes aware of the latest products available to him from the electronics industry. The student assembles the projects discussed in the text and soon becomes capable of designing and assembling projects of his own, which seldom happens when the student reads a cookbook. The material is presented at a level that is easily understood by the average reader. Many analogies of physical phenomena and electronics procedures have been included, so that the reader can relate them to familiar experiences. For completeness, some important circuit analysis procedures have been included in the appendix. The author wishes to acknowledge the assistance received from Mr. F. C. Bailey, proof reading many sections of this book; Ms. Patricia Cave, collating the pages of this book; and Ms. Elaine Angeles for the Book Cover. i WHITTIER UNION HIGH SCHOOL DISTRICT 5 9 Whittier, California 90605 BOARD OF TRUSTEES: Joan Nay, President • Jerry Sarchet, Ph.D., Vice President • Roy Salas, Clerk » Eve Burnett, Henri Pellissier, M e m b e r s N SUPERINTENDENT: Norman B. Eisen, Ed.D. ASSOC. SUPT.: Earle K. Fisher ASST. SUPTS.: Arthur T. Hobson, Ed.D. • Seabron A. Nolin, Ed.D. March 27, 1981 To Whom It May Concern: Our school district has recently had the pleasure of reviewing and field testing an electronics text Electronic System by Miro Angeles. I personally reviewed the book regarding readability and format and found it to be very appropriate for a high school population.. We had our most experienced and respected electronics instructor field test the book in his classroom/lab. He found the book to be very well laid out with the theory clearly presented and followed by lab experiments that the students found very relevant. Some advanced students used the book in an independent study mode and found it to be excellent. If you should have any further questions feel free to call. Sincerely yours, Ronald J. Rhodes Director, Pupil Personnel Services RJR:pb 60 IMPORTANT NOTE Please notice that the Manufacturer's Specification Sheets have been excluded from this f i r s t edition, pending permission from those manufacturers to reprint their material. The above material may be found in the following technical publications: ANALOG DEVICES Data Acquisition Products Catalog Supplement 1979 CANADIAN GENERAL ELECTRIC CO. LTD. Silicon Controlled Rectifier GE-X1 ELECTRONICS TODAY INTERNATIONAL Toronto Ontario EXAR Timer Data Book May 1979 PAIRCHILD TTL Data Book 1978 PAIRCHILD Voltage Regulator Handbook 1978 GENERAL INSTRUMENTS Catalog of Optoelectronic Products 1980 HAMMOND MEG. CO. LTD. : 166 Series Transformers Channel Bracket Mounting INTERSIL Monolithic MAXCMOS Voltage Converter 1980 LITRONIX BAR LED'S MONSANTO Solid State Optoelectronics Product Selection Guide Jan. 1979 MOTOROLA Linear Integrated Circuits 1979 NATIONAL SEMICONDUCTOR CMOS Data Book 1978 NATIONAL SEMICONDUCTOR Linear Data Book 1976 NATIONAL SEMICONDUCTOR Data Acquisition Handbook POTTER & BRUMPIELD Distributor Stock Relays April 1980 RCA COS/MDS Integrated Circuits 1978 SIGNETICS ANALOG Data Manual 1979 TECCOR ELECTRONICS, INC. Technical Data T-1078 May 1978 TEXAS INSTRUMENTS The TTL Data Book 2nd. Edition TEXAS INSTRUMENTS The Optoelectronics Data Book VARO SEMICONDUCTOR, INC. Rectifier and Bridges June 1977 -v- CONTENTS 62 1 ASSEMBLY OF LOGICAL CIRCUITS 1 Probe to test logic levels (4); Logical Indicator for Integrated Circuits (7); Electronics Components for Course (8). 2 LOGICAL CIRCUITS 9 Introduction (9); Boolean Algebra (9); Fundamental Operations (10);Boolean Algebra Laws (14); Implementation of Gates (16); HAND Gates (23); NOR Gates (24); Pin Lay Out for Integrated Circuits (24); EOR (29); Addition (30); Half Adder (32); Full Adddr (37). 3 SYNTHESIS OF BOOLEAN FUNCTIONS .' 39 Venn Diagrams (42); Karnaugh Maps (46). 4 SEQUENTIAL CIRCUITS 57 Basic Memory Unit (57); RS FF with NOR Gates (58); RS FF with HAND Gates (59); Timing in Systems (63); Clocked RS FF (63); JK MS FF (66). 5 CLOCKS 73 Manual Pulser (73); 60 Hz Clock (74); Schmitt Trigger (76); Ring Oscillator Clocks (77); Astable Multivibrator (79); 555 Timer (82); 555 in Astable Mode (82); 555 in Monostable Mode (90). 6 COUNTERS 92 Asynchronous Counter (92); 0 - 7 Ripple Through Counter (95); 0 - 1 5 Ripple Through Counter (97); 8421 BCD Decade Counter. (98). 7 SYNCHRONOUS COUNTERS 102 Design (102); 0 - 7 3inary Synchronous Counter (103); Modulo 16 Binary Synchronous Counter (109); Count Down Counter (112); Special Synchronous Counters (114); Ring Counter (114); Mobius (117). 8. SHIFT REGISTERS 120 States of a Register (121); State Tables (122).; State Diagrams (124); Design of a Shift Register (129); Example 1, Light Chaser (131); Example 2 (137). 9 VISUAL DISPLAYS HO Binary Weighted LSD Indicators (140); Decimal Weighted Display (141); Roulette Wheel (141); Seven Segment Displays (l44); Common Anode Display (146); Common Cathode Display (147)• 10 OPERATIONAL AMPLIFIERS . 148 General Considerations (150); Basic Circuit (151); Summing Amplifier (153); Comparators (155); Waveshaping Circuits (159); RC Differentiators (162); RC Integrators (164). -vi- 11 DIGITAL TO ANALOG CONVERTERS 168 Factors Affecting DAC's (168); Summing Amplifier for Selected Voltage Sources (169); Summing Amplifier with Weighted Input Voltages (173); Summing Amplifier with Resistive Ladder Attenuator (176); BCD Ladder Network (180). 12 ANALOG TO DIGITAL CONVERTERS 186 Sweep Timing ADC (187); Feedback ADC (190); Tracking ADC (195); Successive Approximation ADC (201); Voltage References (203); Ladder ADC (204). 13 SAMPLE AND HOLD CIRCUITS 205 14 POWER SOURCES FOR DIGITAL CIRCUITS 207 A +5 V Power Supply (208); Transformer (208); Rectifier (209); Filter (210); Voltage Regulators (211); Voltage Converters (214). 15 THE INTERFACE OF ELECTRONIC SYSTEMS 218 Interfacing Digital Circuits to AC 120 V Line (219); Electronic Switching Devices: SCR, Triac (220); Optoisolators (223); Electromechanical Relays (224); Variable Speed Flasher (225). APPENDIX I COLOUR CODE " 226 II PRINTED CIRCUIT BOARDS (CONSTRUCTION) 227 III THEVENIN'S THEOREM 232 IV OHM'S LAW MATRIX 241 -vii- 64 1" ASSEMBLY OF LOGICAL CIRCUITS Several strip bread boards are available in the electronics market, such as: SK-10; BIMBOARDS; SUPER-STRIPS; EX300 and EX600; etc. They provide a convenient and easy way to mount integrated circuits and the accompanying peripheral components. Strip bread boards consist of distribution metal strips. These strips are covered by a perforated plastic surface. The components get inserted in the available plug-in-tie points without the need to solder such connections. Each metal strip looks like a U-shaped miniature trough. Components and integrated circuits get inserted into them. Care must be taken to prevent excessive stress, for example large diameter wires can damage the shape of the strip. The recommended wire gauge is #22. Such wires can f i t firmly without slipping out or deforming the strip* STRIP 66 Matrix arrangement of these strips vary with the manufacturer, but in general, horizontal strips run across the top and also at the bottom of the board, see figure below. JUMPER (OPTIONAL) "HORIZONTAL STRIPS VERTICAL STRIPS Above horizontal strips can be used to supply power to the components on the board. For example, the top strip can be connected to the positive end of a battery and the bottom strip to the negative end. Notice that these strips do not run f u l l y across the board, and i f i t i s desired to use a l l the top for positive voltage supply, one must add jumpers, as shown i n the figure above. To provide power to the different components, a battery holder and four size D batteries may be used. This power supply w i l l be sufficient f o r most of the experiments i n this book. -2- 6 7 Vertical strips are used to hold the pins of integrated circuits. Most integrated circuits are of the DIP type, i . e. Dual-In-Line package* In this configuration, the pins are arranged in two rows, one at the top of the IC and the other at its bottomi Each pin is numbered and the count starts counter-clockwise from a notch at the left side of the integrated circuity 1 NOTCH When the integrated circuit i s mounted at the center of the bread board, each pin gets inserted on a separte vertical strips Each vertical strip provides five tie points. Since one tie point is used for each IC pin, then the four remaining tie points are available for external connections, to or from the pin under consideration, as well as for the direct insertion of other electrical components. See the figure below. - 3 68 PROBE TO TEST LOGIC LEVELS To test the different logic levels and outputs of integrated circuits, the following circuit may be made into a useful probe. 9 + V c c P R O B E As a probe, above circuit produces satisfactory results for the voltage levels used in TTL (Transistor-Transistor-Logic) circuits, which is 0 7 or +5 V. This circuit uses LED1s (Light Emitting Diodes) connected in series with 430 ohm resistors. These resistors limit the current through the LED's, down to the recommended manufacturer's values (about 10 mA), thus protecting the LED's.- Notice that this circuit uses a transistor (2N2222) with high input impedance (3.3 K i l ) . This high impedance limits the loading effect on the integrated circuit. This is a desirable feature, since then the test probe does not draw large currents from the IC connections, yet i t indicates whether the IC pin connection has a HI condition, or a LO condition. - <T - 69 The circuit operates as follows. A HI voltage will bias the KPN transistor in such a way that i t goes into saturation, i . e., i t conducts heavily and turns the LED on. The LED light therefore acts as an indicator of a HI condition at the probe's tip. A LO condition at the probe's tip will not be sufficient to bias the transistor's base and consequently the transistor remains in the cut-off condition, i . e. i t does not conduct. Consequently the LED will not glow. This circuit may be assembled on a small piece of vector board. The parts l i s t and the physical connections are shown below. PARTS LIST QUANTITY DESCRIPTION 1 3.3 K/l Resistor (R^ 1 4 3 0 H Resistor (R2) 1 2N2222 Transistor (NPll) 1 LED Light Emitting Diode 2 Alligator Clips 1 18" #22 Red Wire 1 18" #22 Black Wire 1 i " x 2" Vector Board #169P84-062 (Sylmar, California) 2N2222 Bottom View PICTORIAL DIAGRAM 70 PROBE (PART OF Rl) R| = 3.3KJ2 2N2Z22 R2 = 43011 LED BLACK LEAD h i " " o o<U> o 0 0 6 0 O O jbO O0O .. 2" RED LEAD - 6 - 71 LOGICAL INDICATOR ON IC CIRCUITS The following circuit may be installed on the strip bread board, to indicate HI, LO or both conditions. It i s used on IC's that are not driving other loads or IC's. When a HI condition occurs at the probe tips, LED2 will be driven into conduction by the IC, thus indicating a HI. When a LO condition i s being present, the LED1 will permit current through i t into the IC, i . e. the IC will sink this flow of current, lighting LED1. For most applications, the connection of LED1 will be sufficient to indicate the conditions of an IC or of a Counter. IC OUTPUT - 7 - ELECTRONICS COMPONENTS FOR COURSE 72 The following is a l i s t of the suggested electronics components required for most of the experiments in this book. ITEM RECOMMENDED ITEM RECOMMENDED QUANTITY QUANTITY INTEGRATED CIRCUITS SEMICONDUCTORS 555 1 LED's RED 5 /fA741 2 LED's GREEN 5 Fin) 507 1 DIODE 1N4005 4 FND 500 1(Optional) 1N761/5.4V - 4066 1 Zener Diode 1 7400 2 2N2222 (NPN) 1 7402 2 CAPACITORS 7404 1 10JUF 1 7410 1 22>IF 1 7413 1 RESISTORS 7427 1 430a, i W 7 7442 1 3.3 ka, \ w 2 7447 1 4.7 kft, i W 4 . . 7448 1(Optional) 10 kci, i w 6 7476 2 22 kft, i v; 2 7486 1 39 ka, i w 4 7490 2 82 ka, i \7 6 74107 2 1 Ma, \ w 1 74LS190 1 2.2 MQ, i V/ 2 1 74LS283 1 1 I-SLPotentio- meter 2 STRIP BREAD BOARD 1 NOTE.- Should the reader be interested in purchasing above components in a single package, please address: AB DIGITECH CORP. STATION S, P. 0. BOX 76711 Vancouver, 3. C. - 8 - LOGICAL CIRCUITS INTRODUCTION The basic component in logical c i r c u i t s are switches. A switch i s either "on" or "off", not i n between. Since switches can have either one of two values, we find that there are many components that can satisfy this condition. Those two conditions are referred by different names such as: on/off; hi/lo; true/false; 1/0; set/reset; hole/no-hole; saturated/cut-off; open/closed; etc. In order to deal with a number system consisting of the values "0" or "1 , extensive use i s made of Boolean Algebra. This i s a mathematical, system devised by the Br i t i s h mathematician George Boole (1815-1864). During Boole's lifetime, this algebra did not find substancial practical application, but i n 1938, the Bell Telephone Company found i t very suitable to describe the telephone switching gear. Ten years later, with the advent of the f i r s t commercial computers, such as ENIAC, i t was found that Boolean Algebra not only simplified the concepts involved i n computer design, but became indispensable i n their understanding. BOOLEAN ALGEBRA Boolean Algebra uses two-valued variables called binary variables. These variables are represented by a "1" or a "0". If a variable "A" represents the positions of a switch, then, when the switch i s closed, A = 1 and when the switch i s open, A = 0 There are three fundamental propositions: NOT, AND, and OR. 7 4 The logical circuits divide into two classes: Combinational and Sequential. Combinational circuits are analogous to lock mechanisms, where the tumblers must be pushed the right distance by a key. Sequential circuits are analogous to combination locks, where the right sequence of turns must be used to open them. In the combinational class, time is not important, but as we get into the sequential circuits, we will have to consider time as an important element to determine the sequence of events. FUNDAMENTAL OPERATIONS • NOT The NOT operation negates the condition of a switch. If switch "A" is true, i . e. A = 1, then, by the use of the NOT operation i t becomes A, i . e. a zero. A is read NOT A, or A NOT. When dealing with voltage levels, many computer systems use a +5 V to indicate a true value, and a 0 V to. indicate a false value. Thus, a NOT operation simply inverts the voltage level. The logical graphic symbol for the NOT operation i s : A truth table for this operation is simply the reversal of any ini t i a l condition, and is indicated below: A A 0 1 1 0 -10- 75 AND This operation is a form of multiplication. It indicates that two variables must be true for an output to be true. To perform this operation, two switches will be connected as shown below: * / _ ^ / 0 BATTERY E L@ LAMP L The logical algebraic symbol used for this operation is a dot between variables, or simply no symbol between them, i . e. A«B or AB, and i t is read A AND B. The logical graphic symbol for an"AND operation device or gate is: A B A - B Its corresponding truth table i s : A B A-B 0 0 0 0 1 0 1 0 0 1 1 1 - // - 76 OR This operation is a form of addition and indicates that either one of two variables, or both, must be true for an output to be true. See the switch implementation of this operation: B te The logic algebraic symbol used for this operation is a plus sign between variables, e. g. A + B, and i t is read A OR B. 'When used in logic diagrams, its graphic symbol i s : A + B Its truth table i s the following: A B A+B 0 0 0 0 1 1 1 0 1 1 1 1 The next page depictsthese basic logic symbols and their corresponding truth table. Notice that a s m a l l circle a t the input of a gate means inversion of the input signal. Also, a small circle at the output of a gate means inversion of the output logical function. - / 2 - 77 LOGIC SYMBOLS AND THEIR TRUTH TABLES A N D G A T E S O R G A T E S A B F I i 1 A — A — i 0 0 B — J 8 — r 0 i 0 0 0 o 1 1 0 A — 0 A — E 1 0 0 B — ) 8 — - o L _ y ° 0 i 1 0 0 0 i j 0 A - p A • 0 1 B — 0 J 8 — —) y ° 0 / o 0 0 0 1 1 0 A — — 0 c A — F 1 o 0 & — — 0 ) B — — o 1 0 0 0 ' l 1 / A — — 0 \ c A — —r^> F l o 1 B — 0 f 6 — i o 1 1 - 0 0 I t 1 A \ A — C 1 0 6 — 0 1 r B — —) y r o / 1 o 0 1 1 / 1 A — 0 \ A — I 0 1 B — r 8 — 0 / 0 0 0 1 1 / 0 A — c A — -TV \ 0 / B — r & — 0 / / * 0 o / -12- 78 BOOLEAN ALGEBRA LAWS These laws are useful i n the simplification of Boolean expressions. We can verify them by the use of truth tables or implementing them with switches. 1.- ONE and ZEBO rules Q 3.- Associative laws A + (B + C) ss (A + B) + C A • (B • C) = (A * B.) • C AN EXTRA SWITCH IS NEEDE - 1 4 - 5.- Idempotence laws A + A = A A • A = A 6. - Complementary laws A + A = 1 A • A = 0 7. - Absorption laws A + A #B = A A-(A + B) = A A + A'B = A + B A / A -Or 0 0 0 - A B :A B 8 . - Involution A = A 9.- Inversion laws, also known as DeMorgan's Theorems (A + B) = A B A « B = A + B -IS- 80 Delforgan's theorems are very important in the simplification of logical equations, which in turn results in the use of fewer gates while implementing them. Their proof is done by means of truth tables. A graphical proof is discussed under the section of Venn Diagrams. — • — A B A-B A-B A B A + B A + B A + B A«B 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 0 1 1 V 1 0 0 0 0 1 0 0 IlgLEMENTATION OF GATES . While implementing gates, we should notice that only two fundamental operations are needed, i . e. either NOT and AND, or NOT and OB. This is due to the fact that a given circuit may be an AND for a logic called positive, and an OR for a logic called negative. In positive logic, a HI is defined as a " 1 " and a L 0 as a " 0 " , whereas in negative logic, the opposite is true, i . e. a HI is a " 0 " and a LO is a "1". GATE IMPLEMENTATION USING DIODES The following circuit corresponds to an AND gate for positive logic and for negative logic i t corresponds to an OR gate. - 1 6 - Va OO In order to prove above statements, let us consider the output readings obtained with a voltmeter, regardless of the chosen logic* V and V, can each take on two values, which we designate H a b for high level and L for low level. Assuming ideal diodes, the output VQ can be tabulated in accordance with the input conditions, as shown below. REMARKS V a Vb Vo L L L I i H 1 H L L I T H H Both diodes conducting (short circuit) Both diodes off (open circuit) Using positive logic, an " H " will be a "1" and an "L" will be a "0", therefore above table becomes: A B V 0 0 0 0 0 1 0 1 0 0 1 1 1 - 1 7 - 8 2 From the truth table, i t is easy to see that VQ = A B and that i t satisfies the conditions for an AND gate. If on the other hand, we use negative logic, then we must interpret HH" as a " 0 " and "L" as a " 1 " , in which case the voltage table becomes: A B Vo 1 1 1 1 0 1 0 1 1 0 0 0 Above truth table satisfies the condition V = A + B and o corresponds to an OH"gate. From this example, i t can be seen that the same piece of hardware can be used as an AND gate or an OR gate, depending on our definitions of positive or negative logic. Negative"logic is often used in the transmission of data, where noise in the form of voltage spikes may introduce errors in the transmitted data. When positive logic is used, each spike may be interpreted as a " 1 " , whereas in negative logic, a spike will be interpreted as a zero, and negative spikes do not occur. 0 POSITIVE LOGIC NEGATIVE LOGIC 83 Let us consider above same circuit, except that this time we reverse the bias. The bias reversal makes i t into an OE gate for positive logic and an AND gate for negative logic. O O -V Using a voltmeter, we can tabulate our physical results as shown below. V V a b 0 L L L L H H H L H H H H REMARKS j* Neither diode conducts Diode in series with Vb conducts causing V R across R that makes the output positive. - 1 9 - 84 Using positive logic, the resulting truth table is the one that corresponds to a logical OR gate: A B V 0 0 0 0 0 1 1 1 0 , 1 1 1 1 Applying negative logic, we find that the resulting truth table corresponds to a logical AND gate: A B V 0 1 1 1 1 0 0 0 1 0 0 0 0 Because diodes do not have gain, their use is limited* Therefore, we will consider the use of transistors to implement logical functions. GATE IMPLEMENTATION USING TRANSISTORS Consider the following circuit, we shall prove that for positive logic i t represents a NOR gate (NOT OR), and for negative logic i t represents a IIAND gate (NOT AND). -20- EMITTER"— EMITTER " T" NOTE.- The transistors shown in the circuit above are NPN type, since the arrow in the emitter points out. This type of transistor, in order to conduct, requires a positive voltage at its base. For switching transistors, a positive voltage at their base causes them to conduct heavily, that i s , they become saturated and appear as a virtual short circuit to ground. A negative voltage at their base causes them to cut-off, and they stop conducting, acting as an open circuit. Based on the principle of operation of transistors, we can build a table with the different combinations and output results that a voltmeter would indicate. V V a b 0 L L H L H L H L L H H L -21- The positive logic table where H = "1" and L = "0", shows that above c i r c u i t corresponds to the NOR operation, i . e. to A + B A B V o 0 0 1 0 1 0 1 0 0 1 1 0 The logic graphic symbol f o r a NOR gate i s : The negative logic table, where H = "0" and L = " 1 " , shows that above c i r c u i t corresponds to the NAND operation, i . e. to A B A B V 0 1 1 0 1 0 1 0 1 1 0 0 1 The logic graphic symbol f o r a NAND gate i s : -ix.- 87 UNIVERSALITY OP MED It is advisable, from the economics point of view, to have a piece of hardware that does a l l the work. Thus, we can build a l l the logical functions with HAND gates or with NOR gates. INVERTER USING NAND GATES AND GATE USING NAND'S OR GATE USING HAND'S To implement an OR gate using NAND gates, one can make use of DeMorgan's Theorem: A • B = A + B Therefore: A-B = A+B - 2 3 - 88 AND GATE USING NOR'S To implement an AND gate using NOR gates, one can make use of the second DeMorgan' s Theorem: A + B = A • B Therefore: OR GATE USING NOR'S PIN LAY OUT FOR INTEGRATED CIRCUITS The pin connections for the integrated circuits suggested i n in this ,text are included next. Most of these integrated circuits belong to the TTL family (Transistor Transistor Logic). They require minimum electrostatic charge care while handling. - -24- PHsintitiTiiioimm i? irf^ U l i l L i J I i l l i i l i J l z J 7400 QUAD 2-INPUT NAND GATE POSITIVE LOGIC : Y- A & WliililbuliJlfJlz] 7402 QUAD 2 - I N P U T NOR G A T E POSITIVE L06 IC Y = A * B 89 Vcc liJlilliJIiJIkllijlzj 7404 HEX INVERTER POSITIVE LOGIC Y= A UJ UJ I4J LiJ l±J UJ IzJ 7410 TRIPLE 3 - I N P U T NAND GATE POSITIVE LOGIC: Y = A B C ""I J U i J S KC Jill Iii lgjlillzl iraiBiraimramrsi 0 7413 DUAL 4 INPUT SCHMITT TRIGGER) UJliJIiJIiilkllsJlzJ 7427 TRIPLE 3 - I N P U T NOR GATE POSITIVE LOGIC-. Y s A B C D POSITIVE LOGIC: Y = A+B+C MMEMSMJIBB. I V<x A B C D 9 B 7. 0 I 2 3 4 5 6 ffllO LJlillULiJlilWlzJIsI 7442 FOUR LINE TO TEN UNE DECQPEd 1 Vcc f g a b c d & 81/ B C LT R80 RBI D A 6M0 'LdlilUJLiJliJÎ IillSJ raraiBiinnrgFnRm y , ( ^ a b c J e |6 C a MP RBI ( I - OF - 10) 7447 BCD TO 7-SESIV1EMT OECODER / DRIVER _ H / _ J 6 C LT RBORBI 0 A GNO lZl2j|ilkjl£l|£llZll8J 7448 B C D TO 7- S E G M E N T D E C O D E R ISHi5llHlFSn!?H7ilPo|l9l J CP aits Is. fc>b, K CP J wsmmm 747 6 DUAL J K MASTER/SLAVE FLIP FLOP WITH SEPARATE SETS (r^SETS),aEAeS(PRERESEI5)SCtO0d RI7JI17111771 ISimill UJliJllllaJLgliJLiJ l5irill7IIF7H?51l?IT8l 3>A NC QA QO WO 0, Qc CHSD"O(I)RKI)NC VIC BmRw) 74 90 DECADE COUNTER Ro — RESET - Z E R O INPUTS R, - R E S E T - N W E INPUTS 7486 tfUAO 2 - J N P U T EXCLUSIVE - OR G A T E POSITIVE LOGIC i Y = A $ B __ RoCp K R,C,J ao UJtyiillaJlsjlsJizj' 74107 DUAL 4 K MASTER/SLAVE FLIP-FLOP WITH SEPARATE CLEARS(PRERESET^ AND CLOCKS V « A CP TC S . C D w cot/NT OP wrrti LOW *).COUNT DOWN WITH H I , IfoUMTWHEMLOlU/ I B Q» Q>cii 7b Q<. Opto® 74LSf90 SYNCHRONOUS UP/DOWN DECADE COUNTER WITH PRESET AND RIPPLE CLOCK 90 V« A CP RC TC PL C D S COI/NT UP W(|TH LOW |XcOL'MT OOWN WITH HI6H/ CNA61.CS TO r B Oft Q A « ^ Q< °. GW> 74 LS191 SYNCHRONOUS UP/DOWN BINARY COUNTER WITH PRESET AND RIPPLE CLOCK P5ltaK)P5HaHffiP5im V« B3 « £3 M M 24 04 (+3 TD*I5V) ,FiT f»l R Ifl f̂ l £2 BI M2I Al BI CO GWOl LLJlillUllJ|5||6jlZjli) 74LS283 FOUR BIT BINARY FULL ADDER WITH FAST CARRY GND ^"T™ 1 VOLTAGE Vcc t THRESHOLD 4066 QUAD BILATERAL SWITCH SHOWN IN DIGITAL MODE wo nmnuEr t TRIGGER I RESET OUTPUT t t  R S rpuT 555 TIMER TO /SV OUTMc CONTROL VOLTAGE O.oiyr IforriONAL). 4 8 3 7 555 I 2 100 u. \ 10 ul u 11 §0:1 % '0.01 0001 \ \ \ s . , \ > / \ \ \ \ \ CHARGE TIME (OUTPUT HICK) iO.«3(fc tfe)C DISCHARGE TIME(0oTPUTbw):a693 R&C PERIOD •  0.693(RA+2R^C l.4-q OJHj IHz lOfc 100Hz I KHz lOKfelOOttfe FREE RUNNING FREQUENCY FREQUENCY= DUTY CVCLE * (RA+2R«^C RB RA +2 R 6 555 IN AST ABLE MOOE OUTPUT N t " o c f NULL LIliJLiJLiJ OfRtT INV.A -VCC NUU. INfUT MON-INV INPUT / •A74/M > / ( A74ICN ' o DP lijiillsjbJid F N D 5 0 7 / 5 6 7 COMMON ANODE F N D 5 0 0 / 5 6 0 COMMON CATHODE PIN FND 507/567 FND 500/560 PIN 1 1 SEGMENT E SEGMENT E PIN 2 2 SEGMENT D SEGMENT D PIN 3 3 COMM. ANODE COMM.CATH. PIN 4 4 SEGMENTC SEGMENT C PIN 5 5 DEC.POINT DEC. POINT PIM 6 6 SEGMENT B SEGMENT B PIN 7 7 SEGMENT A SEGMENT A PIN 8 8 COMM. ANODE COMM.CATU. PIN 9 9 SEGMENT F SEGMENT F P IN 10 10 SEGMENT G SEGMENT G PIN 11 PIN 12 PIN 13 PIN 14 T I L 312 COMMON ANODE DP=DEC.PO/NT; L=LEFT ; R= RIGHT CATHODE A CATHODE F ANODE DIGIT 5 DECIMAL OMITTED OMITTED CATHODE LEFT DECIMAL CATHODE E CATHODE 0 CATHODE RIGHT DECIMAL CATHODE C CATHODE G 9 1 QND EJ M A N 3 6 4 0 COMMON CATHODE D.R = DEC IMAL POINT PIN \ ANODE F PIN 2 A N O D E G PIN 3 OMITTED PIN 4 COMMON CATHODE PIN 5 OMITTED PIN G ANODE E PIN 7 ANODE D PIN 8 ANODE C PIN 9 ANODE DECIMAL POINT PIN 10 OMITTED PIN 11 OMITTED PIN 12 COMMON CATHODE PIN 13 A N O D E B PIN 14 ANODE A + 9 2 LABORATORY Using the data provided for the above l i s t of integrated c i r c u i t s , the student can assemble the circuits so f a r discussed. The assembly i s done on a strip bread board. A probe like the one described i n the beginning of this book w i l l enable the student to verify the operation of these ci r c u i t s . This check i s done by comparing the truth tables with the ele c t r i c a l results. The integrated c i r c u i t s needed so far, include: 7400, 7402 and 7404. EXAMPLE.- Test the ABB gate using NAND1s. The logical c i r c u i t and truth tables are given below. F = A B The physical connections are shown below. A B A B 0 0 0 0 / 0 J 0 0 J 1 I A 8 DEPENDING ON THE CONDITION OF DESIRED INPUT£,THE TIP OF WIRES "A"AND "6" ARE INSERTED INTO +Vcc FOR A HI, OR <SND FOR A LO LED USED AS OUTPUT INDICATOR F = A - B 2.8- 9 3 OCCLUSIVE OR An Exlcusive Or i s also lmov.rn as: Half Add, P a r t i a l Add, Selective Complement or Add Modulus-2. It i s defined as the condition where the output i s true i f EITHER ONE 0? THE INPUTS IS TRUE BUT NOT BOTH. This c o n d i t i o n i s found i n the three-way switches used i n stairways and house c o r r i d o r s . One can turn one switch on to turn a l i g h t on, but not both switches. See f i g u r e . LAMP L IS ON WHEN A-B OR A-B LAMP L IS OFF WHEN A-B OR A-B The l o g i c a l algebraic symbol f o r an "exclusive or" i s © and i t s t r u t h table i s the follo w i n g . A B A Q B 0 0 0 0 1 1 1 0 1 1 1 0 There are several equation forms that describe the exclusive or, some of them are l i s t e d below. A © B = A-B + A-B = A~B (A + B) = (I + B)(A + B) = A ( A - ! ) B (A~"B) = A +. B + A + A + B + B A l l forms above can be proven with the use of t r u t h tables or by means of Boolean Algebra manipulation. For example, using DeLforgan's theorem a-b = a + b , we can prove the following: A (A B ) B ( A B ) = A ( A B ) + B (A = A (A B ) + B ( A B ) = A (X + B ) + B (I + B ) = A A + A B + B A + B B = A B + A B ( Q . E. D . ) The truth table of an exclusive or i s also the table f o r the addition of two one-bit binary numbers. Therefore, there are many important applications for this operation. ADDITION OF BINARY NUMBERS The four possible conditions for the addition of two one-bit binary numbers are shown below. 0 + 0 0 + 1 1 1 + 0 1 1 + 1 1 0 u CARRY If variables A and B are used to represent above values, then the following truth table w i l l result. A B S ( S U M ) G (CARRY) 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 -30- 9 5 Comparing the results of the column S (SUM), i n the table above, with the truth table for an "exclusive or", we find that: S = A © B The column for the carry can also be represented by the logical function: C = A-B The logical symbol assigned to an exclusive or i s : A 0 B 8 -H Then, a "half-adder" can be represented by the following logical c i r c u i t : A B S=A©B C = A-B The logical symbol for a "half-adder" i s : B H.A. S= A © B •C* A-B •31- 96 II/IPLEMEIITATIOIT OP A HALF-ADDER a) Using simple AND and OR gates: B S =AB •+• A B C = AB b) Using DeMorgan's Theorem, a half-adder can be simplified further. The equation used i s : A © B = A B (A + B) S = A B fAn-B) It should be noticed that this c i r c u i t uses two gates less than the ci r c u i t i n (a). That i s , the implementation of circuits i s greatly f a c i l i t a t e d by the use of simpler equivalent Boolean expressions. Other methods to reduce complex expressions are discussed under Karnaugh Maps. -32- 97 c) Using NAND gates and the identity: A © B = A*A«B -B-A'B A © B C = A B Although above circuit uses an extra gate compared with the circuit in (b), i t has the advantage of permitting us to implement the circuit with only NAND gates. It will not be necessary to have IC's with different functions on the same strip bread board. At an early stage in the development of Digital Systems, this advantage also resulted in economic savings. d) Implementation using NOR gates. The figure below shows the logic diagram. It can be assembled by using two 7402 IC 1s. The 7402 is a QUAD 2 I/P NOR GATE. QUAD means that there are four NOR gates. Each NOR gate has two inputs. The suggested pin connections for each gate have been indicated on this diagram. It is advisable that the student gets the habit of indicating his pin connections, for i t will help him while testing and troubleshooting his circuits. NOTE.- Anyone of above circuits can be assembled on a strip bread board. The truth tables may be corroborated using LED's or a logic levels probe. I t i s also recommended to tes t the integrated c i r c u i t 7486, that corresponds to a Quad 2-Input Exclusive Or Gate. -33- 98 A©B A + B = A B 74 0 2 A p i c t o r i a l diagram of connections f o r the same half-adder i s shown below. 6 V C=AB * I A M \\$\ [12] fll~| [io] [T| [8 I4I [ii fm IT1 flol [71 IT 1 1 11 I I r——1 L — i i S = A® B - 31- 99 MECHANIZATION OF ADDITION OP BINARY NUMBERS Consider the addition of binary variables A and B below: 9 8 7 6 5" 4 3 2 A = i 0 0 1 0 1 1 0 1 + B = 1 1 0 1 1 0 1 0 0 A + B = 0 1 1 1 0 0 0 0 1 In the process of adding above variables, we find that the sixth column from right to left yields the sum S = 1 • The subscript n refers to the column number, and in this particular, case n = 6..- The sum Sg consists of Ag plus Bg and also a carry C^ that originates in the previous column. The previous column can be referred in general as ^. Sum Sg also produces a carry Cg of its own, referred below as C n. The table below considers a l l the possible combinations of A , B n and Gn_.j, and the resulting S n and C n values. Cn-1 A n B n s n c n . 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 -35- 100 The following boolean expressions represent the values of the previous table. The verification of their equivalency can easily be accomplished by means of truth taoles. S = C , © (A © B ) n n-1 ^ K n n' G =A B + G , ( A © B ) n n n n-1 v n ^ n' As can be seen from above expressions, a f u l l sum S n > corresponding to any column n, consists of two half additions. To implement this operation, i t i s necessary to have two HALF-ADDERS, hence the name. The f u l l adder circuit i s shown below. A Full Adder is represented by the following logical graphic symbol: F.A. -36- IMPLEMEITTATION OF A FULL ADDER FOR POUR BINARY DIGITS (BITS) 1 0 1 To add two vinary variables A and B with four bits each, the following logical circuit may be used. Addition made this way i s known as Parallel Addition, because the quantities are a l l entered at the same time. A4 B4 A3 B3 A2 B l Al B l F.A. RA. F.A. H. A. C3 C2 C l C4 S4 S3 S2 SI TO OVERFLOW Integrated Circuits with a l l the required logic shown above are available. One of such IC's is the 74LS283PC. See the TTL Data Book, 2nd. Edition, published by Texas Instruments. The accompanying technical specifications were taken from this book and were used to assemble and test the circuit below. Notice that in this circuit, CO corresponds to a carry from another IC cascaded to this one. If i t is not required, i t must be connected to ground to prevent an extra digit in the displayed results. C4 may be connected to an Overflow Indicator as shown in the figure. - 3 7 - ELECTRICAL WIRING DIAGRAM 102 Notice that LED's are used to ind i c a t e the state of each output (2. 1 toZ4), as well as the state of the carry (C4). \ 15 If 1 3 1 2 II 1 0 Vcc 8 3 A 3 £ 3 M B 4 £ 4 C 4 SN 74 LS 2.83 Z 2 B 2 A 2 £ 1 A l B l C O G N O nr w w w M30JI >430A >430Jl >430il >430il C 4 £ 4 £3 Z2. £1 In the diagram shown above, the connections f o r A 1 , A^, A^, , Br,i %j -̂ 4 ̂ a v e been l e f t open. They represent the bits that make up the variables A and B . These connection inputs can be made to represent logic 1's or O's, by connecting them to +V or to GND respectively. The bit arrangement for quantities A and B i s : •̂ 4 ^3 ^2 1̂ + B4 B3 B2 B1 Z Z T Z ^4 ^-2 1 For example, to add A = 0101 and B = 0110, A 1 and go to V C C and A 2 and A^ go to GND, for B , B 2 and 3^ go to V c c and B^ and B^ go to GND. The results have LED indicators. - 3 8 - SYNTHESIS OF BOOLEAN FUNCTIONS 1 0 3 3 Synthesis i s the development of boolean expressions from a given truth table. It i s the inverse process to that of analysis, since analysis was the process of testing the truth of a boolean expression by the use of truth tables. Synthesis i s carried out by inspecting the truth table and considering the statements that either make the function true or false. EXAMPLE Find the boolean expression that describes the following table: C B A F ROW 1 0 0 0 1 ROW 2 0 0 1 0 ROW 3 0 1 0 0 ROW 4 1 0 0 1 By inspection, one can see that the function F i s true only in ROW 1 "OR" ROW 4, that i s : F =(R0W 1) + (ROW 4) ROW 1 results when A = 0, B = 0 and C = 0, i . e. when I I C ROW 4 results when A = 0, B = 0 and C = 1, i . e. when A B C Therefore: F = A B C + A B C Simplifying: F = A B ( C " + C ) = A B -39- 104 Above expression describes the results of the previous table. This result i s verified below: c B A A B A B = F 0 0 0 1 . 1 1 0 0 1 0 T 0' 0 1 0 1 0 0 ' 1 0 0 1 1 1 EXAMPLE Given the table f o r the addition of binary numbers, find the boolean expression for S . °n-1 A n B n s n 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 SOLUTION S = A B C~ . + A B C " , + A B C , + A B G . n n n n-1 n n n-1 n n n-1 n n n-1 Factoring: S = C" „ ( A 3 + A B ) + C . (A B + A B ) n n-1 n n n n' n-1 n n n n - 4 0 - Using the definition of EOR: A @ B = A B + . A B , plus the expression that corresponds to i t s inversion: 105 EXAMPLE A @ B = A B + A B the above formula becomes: S n - °n-1 ( A n ® Bn> + °n-1 C^®**) Using the definition for EOR again: S = C .. © (A„ © B ) n n-1 n n' Find the boolean expression that describes the following table: A B p 0 0 1 0 1 1 1 0 1 1 1 0 SOLUTION P s A B + A B + A B Simplifying: F = A (B + B) + A B = A + A B = A + B (a) An alternate procedure can be worked out by considering the case when the function i s not true, i . e., the function i s not true only when A = 1 and B = 1 : F = A B Therefore: P = TB (b) Expressions (a) and (b) represent the same function, f o r they are one of DeMorgan's theorems. - 4 I - 106 VENN DIAGRAMS These diagrams are useful in describing the theory of sets. Their applications to boolean algebra provide us with graphical solutions. Such is the case with the graphical proof to DeMorgan's theorems. Although their use is limited to very few binary variables, these diagrams lead directly to the use of Karnaugh Maps. These latter ones prove to be very useful in the simplification of boolean algebra expressions. A simple Venn diagram is shown below. The rectangle represents a l l the possible conditions in a set, whether true or false, i . e., i t represents the totality of " 1 " . The shaded area "A" represents a l l the true conditions of "A". Therefore, any point that does not belong to "A" will be outside of "A", where i t is marked A. Using above diagram for boolean algebra, i t represents one of the complementary laws: A + A = 1 Where A is a binary variable. - 4 1 - 107 When two v a r i a b l e s i n t e r s e c t each other, the i n t e r s e c t i o n represents the l o g i c a l operation AND. The Venn diagram f o r t h i s operation, A B, i s shown below. The combined area of A and B, A + B, i s represented below. Negations correspond, to the area outside the i n t e r s e c t i n g or combined areas. Por example AB i s the area outside of the i n t e r s e c t i o n AB. - 4 3 - 108 DeMORGAlf'S THEOREMS: a) Consider A and B -separately: When their areas get combined, to obtain A + B , i t should be noticed that the total hatched section i s the same as the area corresponding to AB , therefore: AB = A + B b) The intersection of A and B, i . e. A B , i s given by the cross-hatched area seen below. This area corresponds to A + B, therefore: A B = A + 3 - 4 4 - 1 0 9 Verm diagrams get complicated i s we run into more variables, e. g. the intersection of three variables A B G i s represented by the shaded area: If instead of circles, we use rectangles to represent the variables A, B and C, we obtain the following figure, where the shaded area represents the intersection A B C . A m i c c c Above matrix arrangement i s known as a Karnaugh Map. Karnaugh maps prove very useful in simplifying Boolean Algebra expressions. -45*- 110 KABMUGH MAPS Karnaugh Maps constitute a very useful means of simplifying Boolean Algebra expressions. Although their use i s limited to a maximum of six variables, they are well suited for most practical applications. TV/0 VARIABLE KARNAUGH MAP Consider the following figure. It represents a two variable Karnaugh Map, where the variables are A and B. B In the above map, each variable or i t s negation defines two squares. i . e. Variable A defines the upper l e f t and lower l e f t squares. Variable A defines the upper right and lower right squares. Variable B defines the upper l e f t and upper right squares. Variable B defines the lower l e f t and lower right squares. Prom the above area definitions, i t can be seen that any combination of variables w i l l intersect and identify a single square. Examples: The product A 3 defines the upper l e f t square. The product A B defines the upper right square. - 4 6 - THREE VARIABLE KARNAUGH MAP I l l The following Karnaugh Map may be used to describe the variables A A B B C C C In the above map, each variable defines four squares. Consider the following examples: Variable A defines the four squares to the l e f t of a vertical center l i n e . A / / / / Variable B defines the four squares in the upper horizontal row. B / / / / Variable C defines the two center squares of the top row and the two center squares of the bottom row. / / / / c -47- 1 1 2 Variable C defines the two squares in the l e f t hand ver t i c a l column plus the two squares i n the right hand vertical column. J 1 1 1 c c NOTE.- The region defined by the variable. C may appear at f i r s t as consisting of two separate regions. However, i f we consider wrapping the map around a vertical cylinder, as shown below, then the l e f t hand vertical column comes into contact with the right hand ver t i c a l column, and the apparent two separate regions merge into a single one. The intersection of two variables defines a region made up of two squares. Consider the following examples: The product A C* defines the two squares i n the l e f t hand vertical column. A / / . c - 4 8 - The product A B defines the l e f t two squares in the upper horizontal A B / / The intersection of three variables defines a region made up of a single square. Consider the following example: The product A B C defines the upper right square. A B / C POUR VARIABLE KARNAUGH MAP The following Karnaugh Map may be used to describe the variables A, B, C, and D. A A B 5 D B 5 C C C - 4 9 - 114 In the above map, each v a r i a b l e defines eight squares. Consider the following examples: Variable A defines the eight squares to the l e f t of a v e r t i c a l A / / / / / / / / Variable 3 defines the f o u r squares of the upper row plus the four squares of the second row from the top. B / / / / / / / / Variable C defines the four squares i n the l e f t hand v e r t i c a l column plus the four squares i n the r i g h t hand v e r t i c a l column. These eight squares c o n s t i t u t e a single continuous region, as discussed under the note f o r the Three Variable Karnaugh Hap. / / / / / / / / c c -50- 115 Variable D defines the eight squares i n the h o r i z o n t a l second and t h i r d rows. The i n t e r s e c t i o n of two v a r i a b l e s defines a region made up of f o u r squares. Consider the following examples: The product B D defines the four squares i n the upper h o r i z o n t a l row. B / / The product A C defines the four squares i n the l e f t hand v e r t i c a l column. A / / / / C 51- 116 The intersection of three variables defines a region made up of two squares. Consider the following example: The product A B D defines the l e f t two squares in the upper horizontal row. A / / 0 Finally, the region where the product of four variables intersect i s a single square. Consider the following example. The product A B C D defines the right square in the lower horizontal row. A B / D C -52- 117 NOTE.- The region defined by the variable D, i s similar to that defined by C. Just like region C, the region D also appears as consisting of tv/o separate regions. However, wrapping the Karnaugh Map on a horizontal cylinder, as shown below, u n t i l the top upper row comes into contact with the bottom row, causes the two apparent separate regions to merge into a single one. SII.gLIPICATIOIT 0? BOOLEAN EXPRESSIONS USING THE KARNAUGH MAP The basic steps required to simplify a given boolean expression are the following: 1. - The number of variables in the boolean expression determines the size of the Karnaugh Map. 2. - Draw the Karnaugh Map. 3. - Each term in the Boolean Expression defines a region in the Karnaugh Map. Mark the square or squares defined by each term of the expression with X*s or 1's. Each square needs to be marked only once. When different terms in the boolean expression also c a l l for the same square or squares, the simplification of -53- 118 the original expression becomes apparent, since there i s no need to define any region more than once. 4.- Once a l l the terms of the boolean expression have been marked on the Karnaugh Map, redefine the regions marked with X's or 1 1s. The largest the region, the fewer the number of variables needed to define them, this results i n a boolean expression that i s simpler than the original one. NOTE.- For the cases when this method yields two different simplified expressions, each with the same minimum number of variables, (even though the variables are not the same), then both expressions are considered correct and either can be chosen. EXAMPLE 1.- Simplify the following expression: f = A C + A B + I B + A C Solution: 1.- There are three variables:A, B and C. 2.- The corresponding Karnaugh Map i s : A A B B C c C Each term of the above expression defines the regions shown below: 4 AB -54- 119 4.- The largest regions that can be redefined on the above map are shown below: \ •< B 1 r JJ c 1 c B 1 1 C ( c c Therefore the simplified expression i s : f = B C + C However, equally as accurate, but even better, since i t covers larger regions with less variables, i s the following choice: R A A B - - .0 c c B / j / C C * c The resulting simplified expression becomes: f = B + C" Above two solutions prove one of the absorption laws previously described: 3 C + C = 3 + C How the absorption takes place can be seen clearly when the functions are implemented with switches: -55- 120 EXAMPLE 2 . - Simplify the following expression: f = A B D + A B C + B C D + A B C + A B C D Solution: 1 . - There are four variables: A, B, G and D 2 . - The Karnaugh Map i s : B 3.- A B D Each term i n the above expression defines the regions shown below: B C D ^ B 0 0 Cu D_. D B A B C — / 1 1 ' 1 KJ 1 > C c C ABCD BCD ABC 4. - The largest possible regions that can be defined from above map are shown below: B BC B BO BC Therefore, the simplified expression becomes: f = B D + B C -56- 121 SEQUENTIAL CIRCUITS Up to here, a l l the c i r c u i t s described belong to the Combinational Classification, where time i s not important, and the system responds to input conditions whenever they happen. For example, for the function F = A-B + C , i t s logical configuration i s the following. In the c i r c u i t given above, the function F occurs whenever A, B and C are present. No provision i s made for their sequence of appearance. On the other hand, sequential circuits must respond to a chain of events, consequently, these circuits must keep track or have "memory" of a l l the changes taking place with respect to time. Sequential c i r c u i t s require memory and master oscillators or clocks, in order to keep track of the given sequence of pulses. In above example, C may be preceded only by B and B preceded by A for function F to occur. BASIC MEMORY UNIT The FLIP FLOP (FF) i s a sequential device that stores a binary digit or "bit". It i s represented by a box, and has two outputs called Q and ~Q. Q Q If Q i s a "1" or HI, the f l i p flop i s said to be SET. If i t i s a "0" or LO, the f l i p flop i s said to be RESET. - 5 7 - 122 RS FP USING NOR GATES This f l i p - f l o p has two inputs called S for Set and R for Reset. Feedback lines are used to implement i t , see figure below: The c i r c u i t rests in eitherof tv/o states, thus storing one b i t . a) If S = 1 and R = 0 , the HI input to the lower gate makes Q = 0 . Q then feeds back i t s LO into the input of the upper gate. The input to the upper gate has now two LO's that make Q = 1 (Hi). Q then feeds i t s HI into the input of the lower gate, which now has two Hi's. In this way, the f l i p - f l o p i s locked into the SET condition, even after the i n i t i a l inputs are gone. b) If S = 0 and R = 1, the f l i p - f l o p locks i n the RESET condition ( i . e. Q = 0 ) . c) If S = 0 and R = 0 , as i s the case when no signal i s being applied, the f l i p - f l o p remains unchanged. d) If S = 1 and R = 1, both Q and Q become " 0 " (LO), giving rise to an indeterminate state. The last input to return to LO, determines the f i n a l state of the f l i p - f l o p . -58- R S OPERATION: I 123 I Above indeterminate state is analogous to a coin being held vertically by two persons. Each individual pushes their respective side to win, but the one that wins is the one that holds his coin side the longest. The operation of this flip-flop can be summarized in the following table: s R % Qn+1 1 0 «n 1 0 1 Qn 0 0 0 Qn Qn 1 1 Qn INDETERMINATE (Q = 0; Q = 0) Qn is the state of the flip-flop, either a " 1 " or a "0" before applying S and R. Qn+^ is the state of the flip-flop that results from inputs S and R. RS FF USING NAND GATES These flip-flops are implemented with two NAND GATES. Notice that in the circuit below, inverters have been added to the S and R inputs so that the operation and resulting table become similar to the ones described for the NOR GATE FF. -59- OPERATION: a) Assume a given output as i n i t i a l condition (e.g. Q = 1, Q = 0). b) Mark the corresponding conditions on the feedback lines. c) Add any desired combination of input signals (e. g. S = 0, R = 1). -60- 125 d) Analyze the response of the gates, one gate at a time. For instance, starting from gate "A", its inputs will be: a " 1 " from an inverted S = 0 , and a " 0 " from the feedback of Q. Its output will be " 1 " ( 0 • 1 ) and as a result, Q remains a " 1 " . e) Now, we analyze the response of gate "B". Its inputs are a " 1 " from the feedback of Q (as seen in (d), i t remained a " 1 " ) , and a "0" from the inverted R = 1, therefore its output will become a "1" ( 1 • 0 ) . Q = I f) See i f above step changes the feedback conditions. In our example i t does, inputs to "A" become: a " 1 " from the inverted S = 0 and a " 1 " from the new feedback from Q. Then, the output from "A" will change from a " 1 " to a "0" -6/- 126 g) Through feedback lines, above new condition in the output from gate "A" will modify the input to gate "B". Gate "B" will have two zeroes for inputs, one from the inverted E and another from the feedback from Q. These inputs will keep the output of gate "B" as a " 1 " ( 0 0 ) . f) Thus, the input condition S = 0 and R = 1 will cause the flip-flop to settle at Q = 0 and Q = 1, which conforms to the results of the previous truth table. -62- 127 TIMING IN SYSTEMS Many devices require synchronous operation, some examples are given below: a) Television Systems, where the horizontal and ver t i c a l deflection of the television set must be synchronized to those deflections of the television camera. b) Record players must run at 33$rpm to play 33srpm records. c) Digital computers, where a master oscillator or clock gates the propagation of signals from stage to stage with a sequence of timing pulses. d) Digital instruments such as frequency counters, tachometers, d i g i t a l voltmeters, etc. A synchronous analogy may be drawn by a train of stretched freight cars. When the locomotive moves from a s t i l l position, a l l the cars move at the same time. The asynchronous example i s that of cars waiting at an intersection. When the light turns green, the second car does not move un t i l the f i r s t does, and the third car does not move u n t i l the second car i s in motion, etc. Another synchronous analogy i s that of a group of soldiers waiting for the order to march. V/hen the order arrives, a l l the soldiers move at the same time, i . e. the f i r s t soldier as well as the last one in the formation. The asynchronous counterpart i s that of a queue of people waiting outside a theater. V/hen the gates are opened, only the f i r s t person i n the queue can move, then the second and so on. As a result, a considerable amount of time elapses from the opening of the gates before the last person in the queue can begin to move. CLOCKED RS FP If an RS FF i s to be used in a synchronous manner, i t must be able to accept a synchronizing "clock pulse". This i s easily achieved as shown below: - 6 3 - 128 C P > The absence of a clock pulse (CP) INHIBITS the input gates from accepting incoming signals S and R. When a CP is present, i t ENABLES the input gates, and signals S and R can be fed through into the flip-flop. The truth table for above flip-flop i s : s R «n Qn + 1 0 0 Qn Qn 0 1 ^ 0 1 0 Qn 1 1 1 Qn * * The state of the flip-flop is indeterminate and Q = Q = 1 Note.- Outputs Q and Q are zero i f the CP is zero. In above table. Q refers to the i n i t i a l condition before the n clock pulse, and QJ^-J refers to the output result after the clock pulse. -64- 129 Assemble the following circuit and test the truth tables given above. In the following circuit a 7400 integrated circuit is used. The pin connections are suggested but other pins may be used. 6 r - 1 3 0 Above clocked RS f l i p flop changes state on the leading edge of the clock pulse. H LEADING EDGE T R A I L I N G E D G E CLOCK PULSE Clock pulses may last for a relatively long period of time. During this time, the input gates of the f l i p flops remain enabled and may accept unwanted information from feedback paths. The condition of unwanted feedback loops during the time the gates are enabled i s known as RACE-AROUND. During race-around, the f l i p flops are unstable and means must be provided to eliminate this condition. JK MASTER SLAVE FLIP FLOP' If the f l i p flop i s designed to change state after the clock pulse has disappeared, race-around w i l l be eliminated. • The MASTER SLAVE system i s the most common solution adopted by manufacturers of integrated c i r c u i t s . In the master slave system, two f l i p flops are connected in tandem. The f l i p flop that receives the incoming signal i s called the MASTER. The master has two inputs called J and K. Inputs J and K update the information stored in the master f l i p flop. -66- Updating of information takes place when gates A and B are 121 enabled, see the f i g u r e below: M A S T E R The gates A and B are enabled by: a) the leading edge of a clock pulse plus b) a feedback l i n e from the slave portion, used to prevent indeterminate states when J and K are both HI, as explained f u r t h e r below. While the clock pulse i s on, the i n v e r t e r "C" i n h i b i t s the slave f l i p f l o p from changing state. Once the information has been f u l l y updated, the contents of the master get t r a n s f e r r e d i n t o the slave f l i p f l o p . This t r a n s f e r of data from master to slave takes place only during the t r a i l i n g edge of the c l o c k p u l s e . During the t r a i l i n g edge, the HI to LO t r a n s i t i o n of the clock pulse gets' i n v e r t e d by "0", thus enabling gates 3? and & i n the slave s e c t i o n . In t h i s way, the slave f l i p f l o p now accepts the contents from the master f l i p f l o p . Notice t h a t during t h i s t r a n s f e r , the master f l i p f l o p can not accept any other i n p u t , since i t s gates A and B are i n h i b i t e d by a low clock pulse. - G 7 - 132 The logic symbol for a JK master slave f l i p flop (JK lil/S FF) i s : The bubble on the clock input indicates that the f l i p flop changes state on the t r a i l i n g end of the clock pulse, that i s , during the III to LO transition. The truth table for this c i r c u i t i s : J K Q n Qn + 1 0 0 Q n Q n 0 1 Q n 0 1' 0 Q n 1 1 1 Q n "n When J = 1 and K = 1, the above table, indicates that the state of the f l i p flop w i l l be reversed, i . e. toggled after a clock pulse. This result i s in contrast with that of previous f l i p flops, where the above condition resulted in an indeterminate state. Above toggling action w i l l be described below: -68- a) Assume a given output condition, e. g. Q = 1 ; Q = 0 133 b) Draw J = K = 1 on the l o g i c diagram: The output from gate A i s a 1 (0-1-1 ) The output from gate B i s a 0 (1-1-1 ) Therefore, the output state of the master f l i p f l o p becomes: Output from gate D = 0 Output from gate E = 1 Above i s not an indeterminate state, as seen i n previous f l i p f l o p s . This i s due to the feedback l i n e s from the slave f l i p f l o p . -69- 134 d) After the HI to LO transition of the clock pulse,"L, the inverter G causes a LO to HI which enables the slave input gates P and G. Thus, the slave f l i p flop accepts the transfer of information from the master f l i p flop. and the output from gate G becomes a "0" ( 1-1 ). Therefore Q becomes a "0" where previously i t was a "1", and Q becomes a " 1 " where previously i t was a "0". Thus, the master slave f l i p flop reverses states every time a clock pulse arrives i f and only i f J = K = 1. This toggle switch action i s used extensively in Counter Circuits and Shift Registers. -10- 135 The following JK master slave f l i p flop has two extra inputs called PRESET and PRERESET, labelled and R^ respectively. So R o Inputs Sp and R̂  allow one to preset or prereset the f l i p flop when the clock pulse i s low. This i s so, because a low clock pulse causes a HI out of gate C, thus enabling the input gates P and G to accept pulses S^ or R̂ . By the use of the preset and prereset inputs, when the clock pulse i s LO, one can cause the circuit to act as a simple RSPP. Above mode of operation i s very useful, in particular with counters or shift registers, where an i n i t i a l condition i s often desired prior to i t s operation. Above circuit also allows one to preset and prereset the f l i p flop even when the clock pulse is. a HI. This can be accomplished as follows: a) V/hen the clock pulse i s HI, the only way to preset the f l i p flop i s with S D = 1 and J = 0 -II- 1 3 6 b) When the clock pulse i s H I , the only way to prereset the f l i p flop i s with E~ - 1 and K = 0. I'TOTB.- Conditions (a) and (b) are applicable only to the circuit shown above. In most JK master slave f l i p flops, the preset and the prereset inputs are independent of the clock pulse. Finally, by tying the J and K inputs together in above circ u i t , the f l i p flop w i l l function as a toggle switch, chanring output conditions with every clock pulse, a highly desirable characteristic. JK master slave f l i p flops are available in dual packages, such as the 7476 and the 74107. riot ice that the 74107 has only a prereset input Rp, whereas the 7476 comes with preset as well as prereset R̂  inputs. The technical specifications for these f l i p flops are included. To get familiar with the JK master slave f l i p flop, i t i s recommended to test the information supplied by the manufacturers. This can be accomplished by using a manual pulser as a clack pulse on either the 7476 or the 74107. Then, the conditions l i s t e d on the respective truth tables should be verified, applying the respective voltage levels to inputs J and K and also testing inputs and R̂ . L3D indicators may be connected at the Q and Q outputs. -72- CLOCKS In order to generate clock pulses, any of the following circuits may be used. a) MAV.TJAL PULSER A manually produced signal i s very useful to test c i r c u i t s and verify truth tables, especially i f one wants to do i t at one's own speed, rather than at the speed of a fast electronic switching device. However, the use of ordinary switches, by themselves, i s not satisfactory, since ordinary switches produce spikes when closed or opened due to the mechanical bouncing of their contacts, as well as electrostatic sparks between contacts when they are i n close proximity. ON OFF Above spikes cause misreadings or noise in subsequent ci r c u i t s , and thus they must be removed. A simple method to remove spikes i s by the use of the following manual pulser. In fact, this pulser may replace any manually operated switch in a logical system. -73- MANUAL PULSER WITH CONTACT BOUNCE ELIMINATION OPERATION When the switch moves into position 1, i t applies a LO to the input of the upper gate and a HI to the input of the lower gate. Therefore, the Q output locks into a HI, regardless of subsequent momentary spikes. b) 60 HERTZ CLOCK This clock makes use of the line frequency. 115 V j 12.6 V C T. -YWvW I -www- However, the resulting clock pulses have a 60 Hz harmonic component on their leading and t r a i l i n g edges, as shown in the following figure, where the rise time and the f a l l , time are very slow. Notice that rise time t i s r -74- d e f i n e d a s t h e t i m e r e q u i r e d by t h e d r i v i n g p u l s e t o r i s e f r o m 10$ t o 90$ o f i t s m a x i m u m l e v e l . L i k e w i s e , t h e f a l l t i m e t f i s d e f i n e d a s t h e t i m e 111139 w h i c h t h e s i g n a l d r o p s f r o m 9 0 $ t o 1 0 $ o f i t s m a x i m u m l e v e l . V A 60 Wz ALTERNATION 60 H2 HARMON C COMPONENTS Q OUTPUT CLOCK PULSES I n o r d e r t o d e c r e a s e t h e r i s e t i m e o f t h e l e a d i n g e d g e a n d t h e f a l l t i m e o f t h e t r a i l i n g e d g e , a w a v e s h a p i n g c i r c u i t may be u s e d . A d e v i c e • c o m m o n l y u s e d i n t h e s e a p p l i c a t i o n s i s t h e S c h m i t t T r i g g e r c i r c u i t . T h e f i g u r e b e l o w s h o w s a 6 0 H z c l o c k t h a t u s e s a 7 4 0 0 i n t e g r a t e d c i r c u i t , f o l l o w e d b y a 7413 t h a t c o r r e s p o n d s t o a S c h m i t t t r i g g e r w i t h HAND g a t e i n p u t s . T h e s y m b o l u s e d f o r t h i s S c h m i t t t r i g g e r h a s a h y s t e r e s i s l o o p , t o i n d i c a t e i t s mode o f o p e r a t i o n . T h e r e s u l t i n g w a v e f o r m s , a s s e e n w i t h a n o s c i l l o s c o p e , a r e a l s o s h o w n . V/here p o s s i b l e , t h i s c i r c u i t s h o u l d be a s s e m b l e d a n d t e s t e d . 103V ffr.bvns 140 THE SCHMITT TRIGGER CIRCUIT The Schmitt trigger circuit i s a wave shaping c i r c u i t . When used to produce a square wave from a positive sinusoidal alternation, i t f i r e s at a low voltage level , producing a fast rise time. When the input voltage drops below a level V , see figure below, the Schmitt trigger circuit drops i t s output voltage with a fast f a l l time. In between voltage levels and V q i t maintains a constant output voltage that looks f l a t , and i t thus shapes a positive alternation into a square looking pulse. INPUT TO •SCHMITT TRIGGER OUTPUT FROM SCHMITT TRIGGER Notice that the output wave shape can be improved even further by including a Monostable Circuit to follow the Schmitt trigger. See the 555 timer used i n Monostable mode. -76- 141 c) RING OSCILLATOR CLOCXS These c i r c u i t s consist of s t r i n g s of two or three i n v e r t e r s or a m p l i f i e r s , where feedback loops are used to produce the o s c i l l a t i o n condition. The simplest to assemble and t e s t i s the following. t>4>-4> —o OUTPUT _L I f i t i s desired to gate above c i r c u i t , i . e., to get i t to o s c i l l a t e or to stop o s c i l l a t i n g at a p a r t i c u l a r instant of time, nand gates and a manual pulser can be used as shown below. I — " 1 Another os c i l l a t o r that offers good timing pulses i s shown next. Notice that the output wave shape can be improved even further by the addition of a f l i p flop as shown in the diagram. The numbers by the side of each input or output indicate suggested connections when an integrated c i r c u i t 7400 i s used. C = R = I80.fl The frequency of oscillation can be estimated using the following expression: 3 RC For the component values shown in the circuit above, this frequency becomes: f = 84.3 Hz -78- 143 ASTABLB LfJLTIVIBRATOR This i s a basic oscillator c i r c u i t . Its theory of operation i s outlined below, where two Vly.-1 transistors are used in the configuration. The advent of integrated ci r c u i t s has f a c i l i t a t e d the incorporation of more components to stabilize i t s operation, without complicating i t s use, as i s seen in section (e) for the 555 Timer. Consider the ci r c u i t below, where N P N transistors are used. Mote that an N P N transistor conducts when i t s base receives a positive bias. When power i s applied, either transistor T̂  or w i l l conduct, depending on which i s ready to do so. If Tg conducts more readily than T^, then there i s a voltage drop across R̂  with the polarity shown above. The negative voltage resulting from w i l l be applied to the base of T^, cutting i t off. Since T̂  i s not conducting, the voltage at the collector of T 1 w i l l be +V, and this positive voltage i s applied to the base of T 2 keeping transistor Tg turned " C N " . Above locked condition w i l l remain as long as there i s power, and can be broken by the addition of two RC circuits connected across R., and R, as shown below. -79- R 3 144 When power i s applied to above c i r c u i t , i f we assume that transistor Tg i s the f i r s t to switch on, we w i l l see that the current through R. causes V„.. At this instant of time, the voltage y n„ = V„. as seen in 4 R4 R2 R4 the sketch below, and consequently, a negative voltage gets applied to the base of transistor T 1, mailing sure that i t remains cut off. NE<5ATWE VOLTAGE . TO BASE OP T T R 4 V, Since T 1 i s cut off, the voltage at i t s collector i s +Vecand whun applied to the base of transistor Tg, i t keeps this transistor T 2 switched on. However, as time progresses, the capacitor C 2 charges exponentially to a maximum value of V ^ . Notice that = v ^ + VQ2* VR4 ^-*cz -80- When v„ 0 = +V,,. , this positive voltage, fed to the base o f 145 transistor T1 , w i l l trigger i t to the "ON" condition. ,Vcc POSITIVE VOLTAGE -* TO BASE v « S V W = } = C t Of T, R., I VR4 Once the transistor T.̂  begins to conduct, i t acts as a short cir c u i t to ground, and the current through i t w i l l cause voltage p̂-,. Since = v R 1 + v ^ and v ^ = 0 at this instant of time, then the negative end of R̂  w i l l apply a negative voltage to the base of transistor T^, shutting i t "OFF". The process i s repetitive. To verify above principles of operation, the following circuit may be assembled. Note that the time each lamp i s on i s given approximately by the expression t = 0.7 RG. # 4 7 # 4 7 L A M P O.I5"A @ 6 V 2 N 3 7 0 2 2 N 3 7 0 2 Notice that the biasing in above circuit has been reversed, because the transistors used are PNP. -81- 146 e) 5 5 5 TIMER An astable multivibrator can be built using a 5 5 5 integrated c i r c u i t . This IC i s called a Monolithic Timing Circuit. It i s a very- popular component used extensively in the electronics industry. Its electronic diagram i s the following. The 5 5 5 i s a highly stable device for generating accurate time delays or oscillations. Additional terminals are provided for triggering or resetting i f desired. In the time delay mode of operation, the time i s precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circu i t may be triggered and reset on f a l l i n g waveforms, and the output ci r c u i t can source or sink up to 2 0 0 mA or drive TTL ci r c u i t s . Timing i s from microseconds through hours. OPERATION IN THE ASTABLE MODE In this mode of operation, the capacitor C shown i n the figure below charges between 1/3 V and 2 / 3 V . The charge and discharge times, - 8 2 - 147 as well as the frequency are independent of the supply voltage. tV c e = ( '5rOI5V) o- OUTPUT O CONTROL VOLTAGE O.OtJtF —*— (OPTIONAL) — The following figure shov/s the actual wave forms generated i n this mode of operation. CAPACITOR VOLTAGE 0 OUTPUT VOLTAGE •0 / If the cir c u i t i s connected as shown above, i t w i l l trigger i t s e l f and free run as a multivibrator. The external capacitor charges through R^ and R^ only. Thus the duty cycle may be precisely set by the ratio of these two resistors. The charge time (output Hi) i s given by: t 1 = 0 . 6 9 3 ( R A + 1 ^ ) 0 The discharge time (output LO) i s given by: t 2 = 0.693 (R s) G -83- 148 There fo re , the t o t a l pe r i od i s g i ven by: T = t 1 + t 2 = 0.693 ( R A + 2 R B ) C The frequency of o s c i l l a t i o n i s then: 1 1.44 T (R A + 2 R B ) Above frequency of o s c i l l a t i o n may be e a s i l y found by the use of the f o l l o w i n g nomogram. I0O 10 u. | o , g aoi o.ooi \ \ \ \ > \ > / fa+2R») \ N \ 0.1 H r I Hz. IOHI lOOUi I KHz 10 KHz. MO KHz. FREE RUNNING FREQUENCY CALCULATION EXAMPLES USING ABOVE NOMOGRAM EXAMPLE 1) The f o l l o w i n g c o n f i g u r a t i o n may be used to produce low f requency c l o c k p u l s e s . The one meghom potent iometer i s in tended to prov ide a manual c o n t r o l to determine de s i r ed f requency. oCP - 8 4 - Usirur the above nomogram, the approximate ran e of frequencies 149 can be estimated, e.g. i) If the potentiometer i s set for 1 megohm: R. + 2R.O = 1 Ml2 + 2 - 0 = 1 Mn A B C = 1 0 ^ ? After reading the value of C on the C-axis, one moves to the right u n t i l the 1 Mllline i s intersected. Then one moves downwards u n t i l the frequency axis i s intersected. It reads about 0 . 1 2 Hz. i i ) If the potentiometer i s set for 5 Kfl , then: R̂  + 2 R g = 5 kCi + 0 = 5 kft We repeat the process of reading the value of C on the C-axis and move to the right u n t i l the 5 k l l line i s intersected. Since this line i s not i n the nomogram, i t must be interpolated. This i s done by observing that the scales are logarithmic, therefore, the 5 k-flline w i l l not be at the geometric center of the 1 kHand the 1 0 k i l l i n e s , but rather closer to the 10 k f l l i n e than the 1 k i l l i n e . At the estimated intersection, vie move down to the f-axis and read the frequency to be: f = 35 Hz - 8 5 - 150 Therefore, for potentiometer settings between 5 k f L a n d 1 M_fl, the resulting range of frequencies w i l l be between 1.2 Hz and BO Hz. Above c i r c u i t can be assembled and tested at i t s lower frequency range using a stopwatch. For higher frequencies, a frequency counter or an oscilloscope w i l l be necessary. EXAMPLE 2) Determine the frequency i f = 100 k i l , R^ = 20 kftand C = 10/F. Solution: R̂  + 2Rg = 100 kit + 2 -20 kil= 140 k i l Read C = 10^F on the C-axis and move to the right u n t i l the 140 kA line i s intersected ( i t i s closer to 100 kftthan to 1 Mil). Then, moving downwards, read the frequency on the f-axis. It i s about 10 Hz. EXAMPLE 3) Determine the value of R̂  for Rg = 0 and C = 30/ F, to yi e l d a frequency of 10 Hz. Solution: Read f = 10 Hz on the f-axis and also read C = 30/F on the C-axis. Now find where lines perpendicular to these readings intersect. They intersect above the 10 k i l l i n e . Considering the logarithmic interpolation, we estimate them to be at 8 klL. Therefore: R. + 2R_ = 8 k i l A . ± 3 Since Rg = 0, then RA = 8 kft NOTE.- If RA happens to be a linear potentiometer, i . e. each mechanical angular rotation corresponds to an even change in resistance, this potentiometer w i l l act as a tapered resistor (logarithmic response), due to the nature of the nomogram and the circuit response. - 8 6 - •The charge time, when the output pulse i s HI i s determined by the r e s i s t o r s H ^ , R^ and the c a p a c i t o r 0. I t i s given by the expression: t 1 = 0.693 (R, + ?-) C The discharge time, when the output pulse i s LO, i s determined only by the r e s i s t o r Rg and the c a p a c i t o r C. I t i s given by the expression t 2 = 0.693 (R B ) C Therefore, by c a r e f u l l y s e l e c t i n g the r a t i o R^ to R_,, one can vary the l e n g t h of time when the pulse i s HI w i t h respect to when i t i s LO. This v a r i a t i o n can take place f o r a pulse being HI 50$ of the time, i . e. the symmetric c o n d i t i o n , to pulses being HI up to 99.9$ of the time, i . e. the asymmetric c o n d i t i o n . Notice that the output pulse cannot be HI l e s s than 50$ of the time. A l s o , that the c o n d i t i o n f o r symmetry i s that R^ i s made la r g e with respect to R^. CP ON O F F SYMMETRIC WAVE R B > RFT C P O N ,0ff ASYMMETRIC WAVE R A > R 6 MORATORY E X P E R i r ^ The f o l l o w i n g a s t a b l e m u l t i v i b r a t o r c i r c u i t may be assembled to corroborate the symmetry of the output waves. An o s c i l l o s c o p e may be u s e f u l but i s not i n d i s p e n s a b l e . -87- 152 Vcc O RA R B 3.3Ka I M H Hvvrvwvvvv 10/F CP a) VISUAL SYĴ fflT-HY.- ".men E, = 5 . 3 kXI and Hp i s c l o s e to 5 5 kll , the c o n d i t i o n f o r symmetry i s s a t i s f i e d . Th i s y i e l d s an output f requency c l o s e to 2 Hz. Th i s low frequency i s easy to mon i tor w i t h an JED as an output i n d i c a t o r and a stop watch. The l e n g t h of time tha t the LED i s OH corresponds c l o s e l y to the l eng th of t ime when i t i s OFF, thus v e r i f y i n g symmetry. CP ON OFF J * - 2 6 5 ^ 243 m s — * \ f s , . 9 6 H t However, i f R-L-, i s made to be about 5 0 0 . f l , asymmetry occur s , because Eg i s no l onge r g r e a t e r than R^. Th i s l a s t c o n d i t i o n can no l o n ge r be v e r i f i e d v i s u a l l y , because the f requency r i se s to about 3 3 Hz. - 8 8 - 153 b) VISUAL A S Y I 1 S M . - In the absence of an o s c i l l o s c o p e , the same c i r c u i t , v/ith a s m a l l m o d i f i c a t i o n , can be used to observe the asymmetric c o n d i t i o n . Simply exchange the potent iometer and the f i x e d va lue r e s i s t o r , so that the potent iometer i s now connected between p i n s 7 and 8 of the 555 t ime r , and the 5 . 3 k_fL r e s i s t o r i s connected between p i n s 6 and 7 of the same t i m e r . 3y s e t t i n g the potent iometer (K ; i n t h i s case) to a va lue c l o s e to 200 k i l , asymmetry r e s u l t s s ince P., > R_ where now R_ = 3 . 3 k The r e s u l t i n g f requency i s c l o s e t o 0.7 Hz and the asy?metr ic c o n d i t i o n can be observed v i s u a l l y . The LED w i l l be 01T f o r about 1.43 seconds and then OPF f o r c l o s e to 23 ms. C P h ON OFF 1.43 s 22.9 ms P o r t h i s l a s t c o n f i g u r a t i o n , i f fi, i s set to a low va l ue , say 200.Q. , then Rp y R. and symmetry i s r e - e s t a b l i s h e d aga i n . However, i t can not be monitored v i s u a l l y because the f requency r i s e s to about 21 Hz. - 8 9 - 154 OPERATION IN THE MONOSTABLE MODE In t h i s mode of operation, the timer functions as a one-shot. Referring t the f i g u r e below, the external capacitor i s i n i t i a l l y held discharged by t r a n s i s t o r i n s i d e the timer. + Vc«f5TOl5V) o OUTPUT o =F C CONTROL VOLTAGE 0.01 J*F Upon a p p l i c a t i o n of a negative t r i g g e r pulse to p i n 2, the f l i p f l o p i s set which releases the short c i r c u i t across the external c a p a c i t o r and drives the output high. The voltage across the capacitor, now increases exponentially with the time constantT eR^ C. V/hen the voltage across the capacitor equals 2/3 ^ c c> the comparator resets the f l i p - f l o p which i n turn discharges the capacitor r a p i d l y and drives the output to i t s low state. The a c t u a l wave forms generated i n t h i s mode are shown below. INPUT 0 -3Y o OUTPUT -5"V 1 1 t - -( 1- H h CAPACJTOR VOLTAGE -3V - i — i — i 1 i—i—i—y- -90- 155 The c i r c u i t t r i g g e r s on a negative going input s i g n a l when the l e v e l reaches 1/3 V c c . Once triggered, the c i r c u i t w i l l remain i n t h i s state u n t i l the set time i s elapsed, even i f i t gets triggered again during t h i s i n t e r v a l . The time that the output i s i n the high state i s given by t - 1.1 R A C and can e a s i l y be determined by the nomogram below. Since the charge rate and the threshold l e v e l of the comparator are both d i r e c t l y proportional to supply voltage, the timing i n t e r v a l i s independent of the supply. Applying a negative pulse simultaneously to the reset terminal (pin 4) and the t r i g g e r terminal (pin 2) during the timing cycle discharges the external capacitor and causes the cycle to star t over again. The timing cycle w i l l now commence on the p o s i t i v e edge of the reset pulse. During the time the reset pulse i s applied, the output i s driven to i t s low state. When the reset function i s not i n use, i t i s recommended that i t be connected to V to avoid any p o s s i b i l i t y of f a l s e t r i g g e r i n g . -9/- COUNTERS Counters are arrangements using f l i p flops to store and update a set of i n i t i a l or current conditions, according to a predefined sequence. Their use i s of great importance in electronic d i g i t a l systems. The state of a counter may be displayed in different ways, according to desired use. Digital clocks display the state of a counter. Digital voltmeters indicate the binary count that takes place while comparing voltages. Distance measuring devices count the time a pulse takes to reach a given destination. The sequential change of a counter i s used to give the impression of movement in advertising displays. Their use in computer operation as well as i n the transmission of data makes them indispensable. Counters can be divided into Asynchronous and Synchronous cir c u i t s . THE ASYNCHRONOUS COUNTER This counter i s also known as a Ripple Through Counter because only the f i r s t f l i p flop in the ci r c u i t receives a clock pulse, and i t takes a f i n i t e time for a l l the other f l i p flops to get updated. The f i n a l limit on the number of f l i p flops in a ripple through counter i s the total propagation time, where propagation time i s the time i t takes a signal to go through each f l i p flop. Since each f l i p flop delays the i n i t i a l clock pulse, the total propagation time within the c i r c u i t must be less than the time defined between two consecutive clock pulses. -92- R ipp l e through counters may be assembled u s i ng JK master s lave f l i p f l o p s . These master s lave f l i p f l o p s are used i n the togg le mode, which i s the r e s u l t of the f o l l o w i n g connect ions . cc C P In t h i s mode of o p e r a t i o n , each . ' l i p f l o p w i l l change s t a t e w i t h every HI to LO t r a n s i t i o n on i t s CP i npu t . From the t r u t h t a b l e shown below, one can see t ha t i f J = K = 1, t hen , a f t e r a G? input pu l s e , the output c o n d i t i o n s i n the f l i p f l o p rever se from a c o n d i t i o n Q (a "1" o r a "0"), t o a c o n d i t i o n Q (a "0" o r a "1" r e s p e c t i v e l y ) . J K Q n Qn+1 0 0 Q n Q n 0 1 Q n 0 1 0 Q n 1 1 1 Q n \ Toggle C o n d i t i o n -93- 158 In order to corroborate the toggle action of a JK master slave f l i p flop, the following circuit may be assembled. 4ion If the clock frequency i s kept sufficiently low, one should be able to observe that LEU 2 turns ON or ONE every time that LED 1 goes OFF, i . e., during the HI to LO transition. - 9 4 - 159 0 - 7 l i lPPLB THROUGH COUNTER Th i s c i r c u i t c o n s i s t s of th ree JK master s lave f l i p f l o p s used i n the togg le mode. These f l i p f l o p s are connected i n tandem as shown below C P To ana lyze i t s o p e r a t i o n , we can b u i l d up a t r u t h t a b l e . Due to the togg le mode of the f l i p f l o p s , - PP A w i l l change every t ime a c l o c k pu l se changes from a HI to a LO, i . e. the f l i p f l o p w i l l change s t a te w i t h every c l o c k pu l se from the master c l o c k . - P P B w i l l change s t a t e every t ime t ha t PP A changes from a "1" to a "0". - FP C w i l l change s t a t e every t ime t ha t FP B changes from a "1" t o a "0" Above r e s u l t s are used to b u i l d up the t a b l e below. An i n i t i a l c o n d i t i o n has been assumed, where the s t a te of the f l i p f l o p s A, B and C i s ze ro . From the t a b l e , i t i s c l e a r that a b i na r y count takes p l a c e . Th i s count i s f rom 0 to 7 and r e c y c l e s i t s e l f t o zeroes a f t e r the maximum number i n the count has been reached. -95- COUNT C 3 A J I N A R Y Y/UI CHITS 2 2 . 4 1 2 =2 2°=1 I n i t i a l l y 0 0 0 1 0 0 2 r> 1 " 3 0 4 5 1 0 6 1 7 1 0 0 0 0 -96- 0 - 15 FJPPL-, THROUGH COUNTER 161 The s t a t e t a b l e f o r t h i s counter i s g i ven below. I) c 3 A COUNT BINARY WEIGHTS 2 5 2 2 2 1 2 ° 0 0 0 0 0 . 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 ' 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 The c i r c u i t below has p r o v i s i o n to p re re se t the counter to zeroes. The c i r c u i t i s an ex ten s i on of the 0 - 7 r i p p l e through counter w i t h an added f l i p f l o p . N O T E . - J AND K INPUTS A R E T I E * TO + V C C T Oc D C Y 6 A 1 O CP RESET -97- 162 8421 BCD DECADE COUNTER The 8421 B ina ry Coded Decimal Decade Counter i s a w e l l thought out a p p l i c a t i o n of f eed - fo rward and feed-back l i n e s . De tec t i on i s made of the presence of N-1 where N i s the de s i r ed count. Thus the counter i s r e se t whenever the Nth . pu l se takes p l a c e . The counte r counts from 0 to 9 i n b ina ry weighted f a s h i o n and r e s e t s to 0 to s t a r t the count a l l over a ga i n . FEEDFORWARD LINE C A R R Y _ T O N E K T D E C A D E B O X —cr Qc go K —rr B 5e R „ Kj A QA BO K b — c p M A S T E R 'RESET FEEDBACK L INE • NOTE. - J A N D K INPUTS S H O W N WITHOUT CONNECTION ARE TIED TO +V, cc DESCRIPTION 0? OPERATION A f t e r a Master Reset P u l s e , the counter s t o re s 0000. Under t h i s c i r cumstance, PP D s to res a 0, t h e r e f o r e the J input of PP B w i l l be c o n d i t i o n e d , i . e. J and K i npu t s to PP B are HI. Both i npu t s to PP D v / i l l be i n h i b i t e d : Input J by the AND gate (BC) and input K by the Q output of PP D. - 9a - 163 The set J input to PF B i s conditioned with a HI from so that i t can operate normally with incoming pulses from 1 to 7 . The counter counts i n binary sequency u n t i l a count of 0111 i s reached. At count 0 1 1 1 , the J input to FF D i s conditioned by the AND gate ( B C ) . The eighth input pulse w i l l reset A, B, 0 and FF D w i l l be set to a " 1 " by i t s J input. The nineth input pulse sets A = 1, therefore the count w i l l be 1 0 0 1 . FF B i s i n h i b i t e d by a LO from i n t o i t s J input, therefore i t w i l l not change state during the 9 t h . and 1 0 t h . pulses, otherwise i t would read 1011 f o r a nine and 0 0 1 0 f o r zero. The tenth input pulse causes A to go to zero, and the HI to LO t r a n s i t i o n from FF "A" i s f e d forward to the clock input of FF D. Since input K of FF "D" i s conditioned and input J of FF "D" i s i n h i b i t e d , FF D changes to " 0 " , thus completing the c y c l e . Notice that above l a s t HI to LO t r a n s i t i o n of FF D occurs only once during the whole count, therefore i t can be used to drive another • stage of BCD counters to count from 0. to 9 9 i n , etc. -99- 164 STATE TABLE D c 3 A COUNT BINARY •, EIGHTS 2 3=8 2 1=2 2°=1 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 0 0 0 0 0 -wo- 165 To test the previous table,the following c i r c u i t may be assembled. Notice that i t uses a 555 timer to produce the clock pulses, and a 7490 Decade Counter, to do the count. Technical s p e c i f i c a t i o n sheets are included regarding the 7490 decade counter. The display of the count i s done by the use of l i g h t emitting diodes, where LED D corresponds to the Most Significant B i t (MSB =2 =8) and LED A corresponds to the Least Sig n i f i c a n t B i t (LOE = 2^ = 1 ) . 4 3 0 A ^430H ^ 4 1 0 A $ 4 3 0 1 1 -101- Th i s counte r i s one of the most e x t e n s i v e l y used i n d i g i t a l systems, because of i t s a b i l i t y to accept c l o ck pu l s e s . Synchronous counters a re used to produce b i na r y counts as w e l l as s p e c i a l counts . Among the s p e c i a l counts , we f i n d c i r c u i t s known as r i n g counte r s , mobius counters and many d i f f e r e n t k i nd s of l i g h t chase r s . Above s p e c i a l counts are a p p l i c a t i o n s of a more genera l c i r c u i t known as the s h i f t r e g i s t e r . S h i f t r e g i s t e r s are used to manipulate data i n computer systems as w e l l as i n the t r an sm i s s i o n and r e c e p t i o n of d i g i t a l i n f o r m a t i o n . DESIGN OF SYNCHRONOUS BINARY COUNTERS The b i na r y count from these counters i s read from the s t a t e of b i na r y weighted f l i p f l o p s . I f the count i s from 0 t o 1, the c i r c u i t i s a l s o known as Modulo 2, and r e q u i r e s on l y one f l i p f l o p . I f the count i s f rom 0 t o 3, two f l i p f l o p s are needed. I f the count i s from 0 to 7, t h ree f l i p f l o p s a re r e q u i r e d , e t c . In g e n e r a l , the count and the number of f l i p f l o p s a re r e l a t e d by the exp re s s i on : COUNT = ( 2 n - 1) where n = number of f l i p f l o p s The des ign procedure i s the f o l l o w i n g . a) A t a b l e of the b i na r y count i s made, w i t h the cor respond ing s t a t e f o r each f l i p f l o p . b) A t a b l e of the t r i g g e r i n g f u n c t i o n s needed to step each count i s added to step ( a ) . c) The t a b l e of t r i g g e r i n g f u n c t i o n s i s s yn thes i zed u s i n g Boolean exp re s s i on s . -102- 167 d) Above Boolean express ions are s i m p l i f i e d by means of Karnaugh maps. e) The c i r c u i t gets implemented acco rd ing to the r e s u l t i n g Boolean exp re s s i on s . i'ARY SYNCIihOlIOUS 0QUITTER To b u i l d up t h i s synchronous b ina ry counter: a) IvSake a t a b l e w i th the d e s i r e d count and i t s b inary weighted e q u i v a l e n t . In the t a b l e below, the contents of A, 3 and C w i l l be s to red i n three J K master s lave f l i p f l o p s . COUNT • c A 0 0 0 0 1 0 0 1 2 . 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 0 0 0 0 b) I n ve s t i g a te which t r i g g e r i n g pu laes w i l l change the s ta te of each of the three JIT master s lave f l i p f l o p s i n o rder to r e s u l t i n the next count. Example.- Eor count 0 to 1, we need to change on ly the s ta te of F l i p f l o p A? t h e r e f o r e , the t r i g g e r i n g pu l ses must be: A t = 1 ; E. = 0 and C t = 0 -103- 168 Nor the count 1 to 2 v;e need to change the s t a te of f l i p flops A and B, therefore: A t = 1 ; B t = 1 and G t = 0 In the fashion shown above, the table of triggering pulses i s made and i s placed adjacent to the previous one: COUNT C E A G t B t 0 0 0 0 0 0 1 1 0 0 1 0 1 1 2 0 1 0 0 0 1 3 0 1 1 1 1 1 4 1 0 0 0 0 1 5 1 0 1 0 1 1 6 1 1 0 0 0 1 7 1 1 1 1 1 1 0 0 0 0 Nov/, we can proceed to the synthesis of the triggering pulse table, i . e., A^, B^ and C^ w i l l be expressed as Boolean equations. A^ occurs every time a count i s to be updated, therefore, everytime that a clock pulse arrives:' A^ = CP -/04- is true i n any" of the f o l l o w i n g rows: 2nd. row, when A = 1, 3 = 0 and 0 = 0 , i . e. when A 3 G 4th. row, when A = 1, B = 1 and C = 0 , i . e. when A B C 6th. row, when A = 1, B = 0 and C = 1, i . e. when A B C 8th. row, when A = 1, B = 1 and C = 1, i . e. when A B C Therefore: B t = A B C " + A B C " + A B C + A B C C. i s true on the fourbh row, when A B C , or on the 8th. row, when A B C . Therefore: C. = A B C " + A B C Above expressions can be s i m p l i f i e d best by the use of Karnaugh Maps: F o r A, we know that A, = CP , which i s just a wire connected to CP. A 6 / / B / / C C c Therefore: B, = A For C, : / A B / / B C c C Therefore: C. = A B -105- e) Implementation of the circuit. Draw three JK master slave f l i p flops and wire them in accordance to the previous equations: 170 c = AB C P OPERATION.-Inputs J and K for fl i p flop A are tied to +Vcc, therefore f l i p flop A will change state every time a clock pulse arrives. Elip flop B will change state only every other clock pulse, when its inputs J and K receive a HI from f l i p flop A. At the end of count 3, C =0; B = 1 and A = 1 , therefore: The J and K inputs of G have a HI from A B. The J and K inputs of 3 have a HI from A. The J and K inputs of A have a HI from V cc Y/hen the next clock pulse arrives, i t changes above three states to: C = 1; B = 0 and A = 0 The same J and K input conditions for A, B and C repeat at the end of count 7, when G = 1; B = 1 and A = 1. Therefore, the next clock pulse after the count of 7 will reset the three f l i p flops to: C = 0; B = 0 and A = 0 thus commencing the cycle a l l over again. -106- 171 Th i s c i r c u i t may be assembled u s i n g two dua l master s lave f l i p f l o p s l i k e the 7476 i n t e g r a t e d c i r c u i t and one 7400 as shown below. N o t i c e t ha t LED ' s have been used as i n d i c a t o r s , and that they are i n s t a l l e d at the Q output of each f l i p f l o p . P i n connect ions are suggested but d i f f e r e n t arrangements may be used. C P The s t a t e of each f l i p f l o p versus t ime i s shown below. No t i c e t ha t the r e s u l t i n g vo l t a ge l e v e l s have d i f f e r e n t f requency than tha t of the i n i t i a l c l o c k p u l s e . Th i s r e s u l t a l l ows these c i r c u i t s to be used as f requency d i v i d e r s . D i g i t a l c l o c k s make use of t h i s important a p p l i c a t i o n by s u b d i v i d i n g the master c l o c k f requency i n t o subfrequenc ies t ha t w i l l t r i g g e r the seconds, the minutes and the hours . -107- 172 FREQUENCE OF FF C CP o FREQUENCV OF FF 8 = ^ CP FREQUENCY OF FF A ^ CP CLOCK PULSE STATE OF FLIP FLOPS C O 0 0 o 1 1 1 1 0 B 0 0 1 1 0 0 1 t 0 A 0 / 0 / 0 1 0 1 0 B INARY 0 / 2 3 4 5 6 7 0 COUNT -108- 173 MODULO 16 BINARY SYNCHRONOUS COUNTER This ci r c u i t should count from 0 to 15. The procedure used to develop i t i s the one outlined above. a & b) State table: TRIGGERING FUNCTIONS COUNT D c B A D t °t B t A t 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 2 0 0 1 0 0 0 0 1 3 0 0 1 1 0 1 1 1 4 0 . 1 0 0 0 0 0 1 5 0 1 0 1 0 0 1 1 6 0 1 1 0 0 0 0 . 1 7 0 1 1 1 1 1 1 1 8 1 0 0 0 0 0 0 1 9 1 0 0 1 0 0 1 1 10 1 0 1 0 0 0 0 1 11 1 0 1 1 0 1 1 1 12 1 1. 0 0 0 0 0 1 13 1 1 p 1 0 0 1 1 14 1 1 1 0 0 0 0 1 15 1 1 1 1 1 1 1 1 0 0 0 0 0 -tog- c) Synthesis of triggering functions. The boolean expressions f o r above triggering functions are: A T = CP B T = A S C " D + A B C ~ D + A B G D + A B C D + A B G D + A B C " D + A B C D + A B C D C T = A B C " D + A B C D + A B C " D + A B C D D t = A B C r I + A B C D d) Simplification of above expressions by means of Karnaugh maps: For A ^ : A t =CP For Bt: A A B / / 5 / / D B / / / / D C C C Therefore: = A For C t: A A B / / 5 / / D B 5 C C C Therefore: G = A B 175 For Dt: A A / 5 B / D 8 5 C C C Therefore: = A B C e) Circuit implementation D c A B C 0 9 K H H 0 J C=AB K3t Q K a J Q K U A q K In long counter chains, gates w i l l require a large number of inputs or "FAN-IN", as these inputs are also referred to. A solution to limit this fan-in i s the connection shown below. c p -Mi- The gates i n above cir c u i t have a maximum fan-in of two, i . e. only two inputs. The only restriction i s that i n long counter chains, a l l the gating must have taken place before the HI to LO transition of the clock pulse, otherwise a race condition w i l l affect the results. COUTTT DOWN COUNTER Above counter may be used to count down. This i s achieved by taking the results from the Q outputs, this way, the read out w i l l be that of the inverted values. Above can be easily seen i f we start with the i n i t i a l zero value in the table below, and continue to count up. QD QC Q VA COUNT 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 e t c ' - 1 / 2 - 177 If we now obtain the outputs from the Q lines, instead of the Q lines, the f i r s t row of our count w i l l correspond to the inversion of 0000, i . e. 1111, the second row w i l l correspond to the inversion of 0001, i . e. 1110 and so on, so that our table w i l l look as shown below. QD QC WB QA COUNT 1 1 1 1 15 1 1 1 0 14 1 1 0 1 13 1 1 0 0 12 1 0 1 1 11 etc. Therefore, with above provision, the counter counts down. If i t i s desired to obtain the outputs from the Q lines, a variation of above cir c u i t w i l l be to connect the Q output of a previous stage to the gated inputs of succeeding stages. The ci r c u i t below may be assembled to test i t s operation, and also, i t may be analyzed, by using the procedure outlined in the next s e c x i o n . D \Q K| -I/3- 178 ANALYSIS OF SPECIAL SYNCHRONOUS COUNTERS As mentioned before, some of these special counts are particular applications of the more general Shift Register. Once a counter i s given, we can always analyze i t s operation as shown below. a) Consider the state of the f l i p flops after an i n i t i a l condition, usually determined by a master reset pulse. b) Consider the logic level of the J and K inputs (either HI or LO). c) Add a clock pulse and observe the changes that i t causes on the state of each f l i p flop. d) Tabulate the changes that occur i n each f l i p flop for each clocking pulse. e) Repeat (a) to (d) u n t i l a pattern or return to i n i t i a l conditions occurs. RING COUNTER This circuit i s an electronic distributor, and i s often used i n sign advertising and also in car ignition systems. It receives i t s name for the way i t s f l i p flops are connected, i . e. Q outputs to J inputs and Q outputs to K input's, u n t i l the last f l i p flop gets connected i n this manner to the f i r s t f l i p flop. The i n i t i a l value of the count i s set by a master reset which reaches the preset and prereset gates of the f l i p flops in use. -114- 1 7 9 4 3 0 / 1 ^ 4 3 0 1 1 ^ 4 3 0 i l ^ 4 3 0 f l . >NT W T ^ : o so j D Q 5 B J C Q RD K B 4 Rt K q 5 » J A 5 R 0 K OPERATION a) For the ci r c u i t shown above, the master reset line i s connected to the preset gate of f l i p flop A and to the prereset gates of f l i p flops B, C and D. Consequently, after i n i t i a l i z i n g , the state of the counter w i l l be the following: PULSE D C ' B A MASTER RESET 0 0 0 1 b) Consider the logic level of the J and K inputs as a result of above f l i p flop states: JA = 0 and KA = 1 (since FF D = 0) J B = 1 and K B = 0 (since FF A = l ) J c = 0 and K c = 1 (since FF B - o) J B = 0 and = 1 (since FF C = o) NVTCTER RESET -CP -ns- 180 c) Add the f i r s t clock pulse (CP1) and observe how i t affects the state of the f l i p flops. PP A becomes 0 ( J A = 0, K A = 1) PP B becomes 1 (j = 1, Kg = 0) PP C remains 0 (j = 0, K Q = 1) PP D remains 0 ( j ^ = 0, K^ = 1) d) Record the new state of the f l i p flops after 0P1. PULSE D C B A MASTER RESET 0 0 0 1 GP1 0 0 1 0 e) Repeat the procedure used in (a), (b), (c) and (d), u n t i l the i n i t i a l conditions are repeated. The state table becomes: PULSE D c B A MASTER RESET 0 0 0 1 CP1 0 0 1 0 CP2 0 1 0 0 CP 3 1 0 0 0 CP4 0 0 0 1 Above cir c u i t may be assembled using two dual master slave f l i p flops like the 7476 and a variable frequency clock, so that above results may be verified at low frequencies. As the frequency increases, the light chasing effect w i l l be created. Notice also that the light arrangements can be modified'by reconnecting the master reset differently, for example, i f we want three f l i p flops ON and one f l i p flop OPP, then the master reset could be connected to the preset inputs of f l i p flops 3, C and D and to the prereset input of f l i p flop A, in which case the count sequence w i l l be the following: 1110 / 1101 / 1011 / 0111 -116- 181 SV/ITCHBO TAIL RING- COUNTER This counter i s also known as the Kobius counter, for the similarity of the electric configuration to that of the Mobius Strip, shown below. A CONTINUOUS LINE DRAWN FROM THE OUTSIDE WILL END UP IN THE INSIDE In the Mobius counter, the Q outputs are connected to the J inputs and the Q outputs are connected to the K inputs as i n the ring counter, except for the last f l i p flop where i t s Q output i s connected to the K input of the f i r s t f l i p flop and i t s Q output i s connected to the J input of said f i r s t f l i p flop. This counter i s often used to generate control and test patterns for transmission of data and i s also used to drive the rear turning lights i n some car models. This circuit i s shown next and may easily be assembled and tested, in order to corroborate i t s state table. The analysis procedure i s the same outlined above. -1/7- 182 C l« J l B Q J A Q K C P The state table f o r the Mobius counter i s shown below. PULSE C B A MISTER PULSE 0 0 0 GP1 0 0 1 CP2 0 1 1 C?3 1 1 1 CP4 1 1 0 CP5 1 0 0 CP6 0 0 0 - ; i g - FURTHER EXAMPLE OF SPECIAL COUNTS 1 8 3 a) For the counter shown below, determine the sequence of states that take place after a master reset pulse sets i t to 000. b) What happens i f the counter i s i n i t i a l l y in state 110 or 111 for f l i p flops C, B and A respectively. SOLUTION a) Assuming that a master reset pulse w i l l set A, B and C to zeroes, then the state table becomes the following. Notice that i t i s a binary counter that counts from 0 to 4. PULSE C B A MASTER RESET 0 0 0 CP1 0 0 1 CP2 0 1 0 CP3 0 1 1 CP4 1 0 0 CP 5 0 0 0 b) If the counter i s i n i t i a l l y in state n o or 111, the state tables below show that the cir c u i t w i l l restore i t s e l f to i t s normal counting mode, i . e. the count becomes 010 or 011 respectively, after CP1. PULSE C B A MASTER RESET 1 1 0 CP1 0 1 0 PULSE c B A MASTER RESET 1 1 1 CP1 0 1 1 -//9- S h i f t r e g i s t e r s c o n s i s t of cascaded f l i p f l o p s . C lock pu l se s reach a l l these f l i p f l o p s s imu l taneous l y . Each c l o c k pulse causes the contents of a feedback f u n c t i o n , a "0" o r a " 1 " , t o be t r a n s f e r r e d i n t o the f i r s t f l i p f l o p of the r e g i s t e r ; at the same t ime, the contents of the f i r s t f l i p f l o p are t r a n s f e r r e d to the second f l i p f l o p ; the contents of the second f l i p f l o p are t r a n s f e r r e d to the t h i r d f l i p f l o p ; and so on, u n t i l the l a s t f l i p f l o p s t o re s the contents of i t s p rev ious f l i p f l o p . Between c l o c k pu l s e s , the contents of each f l i p f l o p are combined t o make up the new feedback f u n c t i o n . See the f o l l o w i n g b lock diagram. FEEDBACK FUNCTION N — F F •The above ope r a t i on i s s i m i l a r to s h i f t i n g domino bones on a t a b l e . Con s i de r the f o l l o w i n g analogy f o r a f o u r f l i p f l o p s h i f t r e g i s t e r . Each f l i p f l o p i s ass igned an a rea on the t a b l e marked A, B, C and D. See the next f i g u r e . -120- 185 The state of each f l i p flop i s determined by the single domino bone that occupies i t s area. The domino bones are marked either as a " 0 " or as a "1 The feedback function i s represented by new domino bones that can only be placed in the least significant bit position, i . e. PI? A. Since each f l i p flop area can store only one bone at a time, the new bones must push those already on the table, shifting them one position to the l e f t , as shown in the above figure. This way, the bone in area A w i l l now occupy the area B, that in area B i s shifted to area C, that in area C i s shifted to area D and that i n area D gets removed altogether from the table. The resulting count i s displayed by the remaining bones. POSSIBLE STATES OR COUNTS OF A REGISTER The number of different states or counts that a register may contain at any one time i s dependent on how many f l i p flops are there in the register. Including t r i v i a l cases, i . e. those situations where the shift register becomes locked i n a loop, the number of different states i s given -121- 186 by the f o l l o w i n g expression: 1 =* (Number of d i f f e r e n t states) ^ 2 n In the above expression, n i s the number of f l i p f l o p s i n the s h i f t r e g i s t e r . Examples: a) A s h i f t r e g i s t e r with four f l i p f l o p s has a maximum of 16 d i f f e r e n t states or counts. b) A s h i f t r e g i s t e r with f i v e f l i p f l o p s has a maximum of 32 d i f f e r e n t states or counts. STATE TABLES State tables are used to l i s t a l l the possible counts of a s h i f t r e g i s t e r . As an example, we w i l l show the procedure used to tabulate the states of a four f l i p f l o p s h i f t r e g i s t e r . It must be noted that the feedback functions can only be " 1 " or "0", Assuming that the i n i t i a l count i s zero, i . e. 0000^: a) Adding a feedback function with zero value w i l l not change the state of the count. Repeated use of t h i s zero feedback w i l l keep the s h i f t r e g i s t e r locked i n a t r i v i a l loop. b) Adding a feedback f u n c t i o n with a value of ONE w i l l change the state of the count to a 1, i . e. 0001^, because: PF A becomes 1 (due to the feedback function) FF B remains 0 ( i . e. the previous value of FF A) FF C remains 0 ( i . e. the previous value of PF B) FF D remains 0 ( i . e. the previous value of FF C) TThen the count i s ONE, i . e. 0001 g : a) Adding a feedback function with zero value w i l l change the state of the count to a 2, i . e. 0010^, because: - 1 2 2 - 187 PF A becomes 0 (due to the feedback function) PP B becomes 1 ( i . e. the previous value of PP A) PP C remains 0 ( i . e. the previous value of PP 3) FP D remains 0 ( i . e. the previous value of PF C) b) Adding a feedback function with a value of ONE, w i l l change the state of the count to a 3> i . e. 0011^, because: FF A becomes 1 (due to the feedback function) FP 3 becomes 1 ( i . e. the previous value of FF A) FF 0 remains 0 ( i . e. the previous value of FF B) FF D remains 0 ( i . e. the previous value of FF c ) The remaining states are determined using this procedure. The table below l i s t s a l l the 16 states with the feedback functions that produce them. COUNT 2 3 ~ T 6 5 7 8 12 10 H 9 13 11 15 D 0 0 0 0 0 0 0 0 0 1 1 1 J_ 0 1 0 1 0 1 0 1 B 0 1 1 0 1 0 J_ 0 0 1 1 0 0 1 1 -III- 188 STATE DIAGRAMS F o r a n a l y s i s and des ign purposes, i t i s u s e f u l to know the s e q u e n t i a l o rder of the s t a t e s o r counts i n a s h i f t r e g i s t e r . when the s t a t e sequences are mapped on s p e c i a l graphs, they become known as S ta te Diagrams. Once a S ta te Diagram i s completed, i t becomes a u s e f u l r e fe rence to determine s equen t i a l counts a t any t i m e . STATE DIAGRAM F O R P E S F L I P P L O P A s i n g l e f l i p f l o p has two p o s s i b l e s t a t e s o r counts , i . e. a "0" o r a "1". These two s t a t e s are represented g r a p h i c a l l y by two nodes. © © A feedback f u n c t i o n , f ed du r i ng a c l o c k pu l s e , w i l l produce the f o l l o w i n g r e s u l t s : a) I f the f l i p f l o p i s i n the "0" s t a t e , a ZERO feedback f u n c t i o n w i l l not a l t e r i t s s t a t e . Thus, the f l i p f l o p remains i n the "0" s t a t e . Th i s i s a t r i v i a l case and i s represented by a c l o s ed loop around the node 0. FEEDBACK-0 b) I f the f l i p f l o p i s i n the " 1 " s t a t e , a ZERO feedback f u n c t i o n w i l l change i t i n t o the "0" s t a t e . Th i s t r a n s i t i o n i s represented by an arrow drawn from node 1 to node 0. c) I f the f l i p f l o p i s i n the "0" s t a t e , a ONE feedback f u n c t i o n w i l l set the f l i p f l o p i n t o a " 1 " . Th i s t r a n s i t i o n i s represented by an arrow drawn from node 0 t o node 1. -124- 189 d) If the f l i p flop i s in the " 1 " state, a ONE feedback function w i l l only keep the f l i p flop in the same " 1 " state . This i s another t r i v i a l case and i s represented by a closed loop around the node 1 . ® l ) ) FEEDBACK =J The complete State Diagram i s the composite of the above four cases and i s shown below. STATE DIAGRAM FOR A TWO FLIP ?LOP SHIFT ISGISTBR When a shift register consists of two f l i p flops, A and B, i t has four possible states or counts. Each of these counts i s designated by a node. Node zero represents the count 0 0 ^ ; node 1 represents the count 0 1 0 ; node 2 represents the count 10,, and node 3 represents the count 1 1 _ . Feedback functions modify only the least significant bit of the shift register. Therefore, we w i l l consider the effect of a feedback function when: a) the feedback i s ZERO and b) when the feedback i s ONE. a) "/hen the contents of the register are zero, a ZERO feedback -125- 190 function w i l l not a l t e r the r e s u l t s . This can be seen r e a d i l y when we use the domino analogy: .FEEDBACK COUNT = 0 BEFORE FEEDBACK FUNCTION COUNT = 0 AFTER FEEDBACK FUNCTION When the i n i t i a l contents of. the s h i f t r e g i s t e r have a count of " 1 " , ( 0 1 2 ) , then a Z E R O feedback function w i l l modify them as follows: ^ FEEDBACK COUNT = | ( b i z ) BEFORE FEEDBACK FUNCTION COUNT -2 (\0Z) A F T E R FEEDBACK FUNCTION V/hen the i n i t i a l contents of the s h i f t r e g i s t e r have a count of " 2 " , ( 1 0 9 ) , then a ZEEO feedback f u n c t i o n w i l l modify them as follows: COUNT = 2 ( I00 BEFORE FEEDBACK FUNCTION COUNT = 0 AFTER F E E D B A C K FUNCTION Y/hen the i n i t i a l contents of the s h i f t r e g i s t e r have a count of "3", ( 1 1 2 ) , then a ZEEO feedback function w i l l modify them as follows: COUNT = 3 0 k ) BEFORE FEEDBACK FUNCTION COUNT ^2, (ICO AFTER FEEDBACK FUNCTION -126- 191 .bove f o u r c o n d i t i o n s are summarized g r a p h i c a l l y below: 0 Not i ce t ha t the arrows i n d i c a t e the d i r e c t i o n i n which the t r a n s i t i o n s take p l a c e , when the feedback f u n c t i o n i s ZERO, b) A feedback f u n c t i o n equal to " 1 " w i l l modify the contents of the same s h i f t r e g i s t e r , i n the d i r e c t i o n shown by the arrows i n the f o l l o w i n g f i g u r e . No t i ce t ha t the same domino analogy may be a p p l i e d to any i n d i v i d u a l case . Fo r example, con s i de r the case when the i n i t i a l count i s a " 1 " , (O l g ) , and the feedback f u n c t i o n i s a l s o a " 1 " , then the on ly p o s s i b l e new count i s a "3", t ha t i s : 11 p. See the f i g u r e below: The complete s t a t e diagram i s the composite of the above p a r t i a l diagrams. See the next f i g u r e . COUNT = I (0I2) BEFORE FEEDBACK FUNCTION COUNT = 3 ( H i ) AFTER FEEDBACK FUNCTION -127- 192 STATE DIAGPJUI I?OP. A THPEE FLIP FLOP '^IIFT RSCI5TES. A s h i f t r e g i s t e r with three f l i p f l o p s has e ight p o s s i b l e s t a t e s o r counts . Nodes 0 t o 7 are used to des ignate those counts . The p o s s i b l e t r a n s i t i o n s between counts due to a feedback function are i n d i c a t e d by arrows. The absence of arrows between two nodes i n d i c a t e s tha t no transition i s p o s s i b l e between them. -ize- 193 : ? o u ? . F L I P ? L O ? :.iEim S G I saint A s h i f t r e g i s t e r w i t h f o u r f l i p f l o p s has s i x t e e n p o s s i b l e s t a t e s o r counts . The p o s s i b l e t r a n s i t i o n s , due to feedback f un c t i o n s are shown i n the s t a te diagram below. The above diagram shows nodes of a l l the po s s i b l e counts , and i t a l s o i n d i c a t e s , w i t h arrows, a l l the p o s s i b l e new counts a v a i l a b l e from each of those nodes. The domino analogy ma;/ a l s o be a p p l i e d to any i n d i v i d u a l s t a te shown i n the above diagram. F o r example, c o n s i d e r the case when the i n i t i a l count i s a 3, i . e. 0011^. The two p o s s i b l e new s t a t e s o r counts are dependent on whether the feedback f u n c t i o n i s : (a) Z E E O ; o r (b) O N E . a) v.hen the feedback f u n c t i o n i s a "0", the on ly p o s s i b l e new count i s eaua l to 6 , i . e. 0 1 1 0 „ , see the f i g u r e below: FEEDBACK COUNT = 3 (00ll2) BEFORE FEEDBACK FUNCTION COUNT - 6 (OII0i) AFTER FEEDBACK FUNCTION -IZ9- 194 b) ".Then the feedback f u n c t i o n i s a " 1 " the only p o s s i b l e new count i e equal to 7, i . e. 0111 / V . FEEDBACK I see the f i g u r e below: COUNT =3 ( O D I ^ BEFORE FEEDBACK FUNCTION AFTER FEEDBACK FUNCTION D B S I C - I c O F A S H I F T R E G I S T E R S h i f t r e g i s t e r s are used to transmit i n f o r m a t i o n i n accordance t o s p e c i f i e d sequences. Thus, the d e s i r e d sequence determines the s i z e and c o n f i g u r a t i o n of the s h i f t r e g i s t e r as w e l l as that of i t s feedback l o g i c s . The design procedure, based on a f e a s i b l e count sequence, i s 1. - Use the appr o p r i a t e State Diagram o r any of i t s p o r t i o n s . 2. - Construct a t a b l e w i t h the d e s i r e d count" sequences. Refer to the s t a t e diagram, t o make sure t h a t the count sequences are f e a s i b l e . 3. - F o r each of the counts l i s t e d i n the t a b l e of part (2), determine the value of the feedback f u n c t i o n t h a t w i l l produce the next s t a t e . L i s t those values of feedback f u n c t i o n s i n an e x t r a column. 4. - Synthesize the feedback f u n c t i o n from the values l i s t e d i n the feedback column. 5. - S i m p l i f y the feedback f u n c t i o n , by the use of Karnaugh haps. 6. - Implement the l o g i c a l diagram. summarized below: -130- 195 3XAL'3?LE 1 counts: Design a s h i f t r e g i s t e r to produce the following sequential 0, 1, 2, 4, 8, 1, etc. Notice that the implemented c i r c u i t w i l l have commutating c h a r a c t e r i s t i c s , of the type used i n l i g h t chasing e f f e c t s . SOLUTION 1.- The s h i f t r e g i s t e r must contain f o u r f l i p f l o p s , because the requested maximum count i s an eight, that i s , lOOOg. Notice that the above sequence i s part of the state diagram f o r a four f l i p f l o p s h i f t r e g i s t e r . The p a r t i a l diagram i s shown below. I DESIRED •SEQUENTIAL LOOP 2.- B u i l d up a table containing the desired sequential counts, and assign corresponding values to each of the four f l i p f l o p s . -12,1- 196 COUNT STATES ' D G B A 0 0 0 0 0 •1 0 0 0 1 2 0 0 1 0 4 0 - 1 0 0 8 1 0 0 0 1 0 0 0 1 3.- Li s t the required feedback functions on an extra column. These are the functions that w i l l step any count into i t s following state. COUNT STATES D c B A FEEDBACK FUNCTION 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 0 0 4 0 1 0 0 . 0 8 1 0 0 0 1 1 0 0 0 1 4. - Synthesize the feedback function from i t s corresponding column. The rows where this function i s true are "added" i n the following Boolean Algebra Expression. f = l B f i D + l B C B 5 . - Simplify the above expression, by using Karnaugh maps: -HI- 197 A A B D 0 i B i 1 5 C C C The s i m p l i f i e d feedback function becomes: f = A 3 C" 6.- The implemented l o g i c a l diagram i s the following: f = A B C a 4> B VThen the above c i r c u i t i s f i r s t energized, a random condition may appear on each of i t s f l i p f l o p s . Assuming that the s h i f t r e g i s t e r i s i n i t i a l l y set to OlTE's, i t can be seen that a f t e r a few clock pulses, the sequential count i s eventually restored to i t s intended sequential loop. This i s shown i n the following t r u t h t a b l e , where a master reset pulse produces the i n i t i a l count of 15. Columns A, B and C are used to derive the feedback functions (f-column), which determine the state of the new count, every time a clock pulse i s received. -133- 198 CLOCK PULSE COUNT D c B f, sx A B c f = A B C MASTER RESET 15 1 1 1 1 0 0 0 0 CP 1 14 1 1 1 0 1 0 0 0 CP 2 12 1 1 0 0 1 1 0 0 CP 3 8 1 0 0 0 1 1 1 1 CP 4 1 0 0 0 1 1 1 0 0 ETC. - Notice that the above count follows a portion of the f o u r f l i p f l o p state diagram, as shown below, and then i t restores i t s e l f to the desired sequential loop. I t may also be corroborated, by f o l l o w i n g the above procedure, that t h i s c i r c u i t always restores i t s e l f to i t s intended mode of operation, regardless of the value of the i n i t i a l count (0 to 1 5 ) . Therefore, a master reset pulse i s not required. The above l o g i c a l diagram may be assembled and tested by using the f o l l o w i n g components: Two dual master slave f l i p f l o p s 7476 One t r i p l e 3-input NMD gate to be used as an AND gate as well as an i n v e r t e r . One 555 timer to produce the clock pulses. See the next f i g u r e . 199 X 7 4 1 0 PIN 14 TO Vcc PIN 7 TO GND 430J1 : LED 0 4 J Q 4 1/6 K <? 7 4 7 6 PIN 5 TO V « PIN 13 TO GND Vcc 9 I MA ZZ*£L km 43011: LED 2 430XL : LED3 430X1 LED 4 J Q 4 B i rd it K 4 101 .J L 161 I2i K Q 7 4 7 6 PIN 5 TO Vcc PIN 13 TO GND -I3S- 200 T h e p r e v i o u s c i r c u i t may be m o d i f i e d s o t h a t t h e Q l i n e s f e e d t h e f e e d b a c k f u n c t i o n . T h e " A N D " g a t e i s c h a n g e d f o r a " N A N D " g a t e t o p r e v e n t l o c k i n g t h e s h i f t r e g i s t e r i n t o t h e t r i v i a l m o d u l o 1 s t a t e , i . e . 0 0 0 0 . T h e t a b l e t h a t d e s c r i b e s t h e s t a t e s o f t h e c o u n t i s : P U L S E D c B A MASTER R E S E T 0 0 0 0 GP1 0 0 0 1 C P 2 0 0 1 1 C P 3 0 1 1 1 G P 4 1 1 1 0 C P 5 1 1 0 1 C P 6 1 0 1 1 C P 7 0 1 1 1 T h i s c i r c u i t d o e s n o t r e q u i r e a m a s t e r r e s e t p u l s e . I f t h e Q o u t p u t s g e t c o n n e c t e d t o L E D ' s , i t p r o d u c e s a p a t t e r n w h e r e a n o - l i g h t s e e m s t o c h a s e t h r e e l i g h t s . -136' EXAMPLE 2 Using the shaded portion of the state diagram shown below, design a shift register that w i l l assume a l l those indicated states, that i s : 0, 1, 2, 4, 9, 3, 6, 13, 11, 7, 14, 12, 8, 0 Above count has thirteen different states, i . e. a modulo 13. The cir c u i t therefore must use four f l i p flops. -137- 202 SOLUTION 1 . - The State Diagram has already been provided. 2 Sc 3.- The states of the count and their respective feedback functions are li s t e d below: COUNT STATES D c B A FEEDBACK FUNCTION 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 0 0 4 0 1 0 0 1 9 1 0 0 1 1 3 0 0 1 1 0 6 0 1 1 0 1 13 1 1 0 1 1 11 1 0 1 1 1 7 0 1 1 1 0 14 1 1 1 0 0 12 1 1 0 0 0 8 1 0 0 0 0 0 0 0 0 0 4 . - In terms of Boolean algebra, the feedback function i s synthesized as follows: f = ABC~D + A B C D + ABC~D + A B C D + A B C D + A B C D - I 3 8 - 203 5.- Simplification by means of Karnaugh maps yields: B B 9 D ti Therefore, the feedback function becomes: f = A C D + A B D + A C D + A B D 6.- The implemented cir c u i t i s shown below. -139- VISUAL EISPLAYS Visual displays are commonly used to retrieve information from electronic systems. Electronic d i g i t a l displays are mostly made with incandescent lamps, nixie tubes, neon lamps, light emitting diodes (LED), liq u i d crystal displays (LCD) and cathode ray tube displays (CRT). In this section, only light emitting diodes are considered, since their application mode i s general to a l l the displays l i s t e d above. BINARY WEIGHTED LED INDICATORS (8, 4, 2, 1) As previously mentioned, the lo g i c a l state of a c i r c u i t , HI or LO, can be known by using light emitting diodes as indicators. Eor a BCD decade counter, the following arrangement was used to display the state of the count. These LED indicators are used i n the binary coded weight mode, i . e. 8, 4, 2 and 1. In order to read the count, one must interpret the indicated weights. + Vcc D C B A 2*= 8 2X-A 2'=Z 2°=/ -HO- DEGir.1A,L WEIG-HTED DISPLAY (9, 8, 7, 6, 5, 4, 3, 2, 1, 0) 205 These c i r c u i t s save us the ef f o r t to interpret the binary coded weights. The output consists of 10 l i g h t emitting diodes where each i s weighted i n our f a m i l i a r decimal number system. The t r a n s l a t i o n of results from a binary coded weight system into the decimal number system i s done by using a 4-LINE-TO-10-LINE DECODER, such as the 7442 integrated c i r c u i t , see attached technical s p e c i f i c a t i o n s . The previous c i r c u i t can be modified i f we add a 7442. The required ten l i g h t emitting diodes w i l l be used to indicate the state of the count. Notice that the 7442 integrated c i r c u i t sinks the current from the LED indi c a t o r s , therefore, the l i g h t emitting diodes must be connected i n the common anode configuration to +^ c c» The r e s u l t i n g c i r c u i t may be used as an electronic roulette wheel. OPERATION AS A ROULETTE V/HEEL The frequency of o s c i l l a t i o n i n the clock of t h i s c i r c u i t can be varied by varying the one megohm potentiometer, i . e. R̂ . Notice that the clock pulse i s only indicated i n the next f i g u r e , but i t s o s c i l l a t o r i s the same one used i n the previous display. As the resistance R̂  i s decreased, the frequency of o s c i l l a t i o n increases. See how t h i s takes place graphically, r e f e r r i n g to the nomogram f o r the 555 timer i n the astable multivibrator mode, or simply consider the design equation below, where R~ = 0 and C = 10Mp. -Hi- 206 £ = 1.44 (R A + 2RB)C Notice that i f R̂  becomes less than 1 k f l , then the ci r c u i t reaches an unstable region, as seen i n the nomogram, to the right side of the 1 kfl l i n e . If R̂  i s decreased further, the cir c u i t w i l l stop oscillating. This condition can happen when R i s close to 100 ohms. V/hen the oscillation stops, there are no more clock pulses to trigger the counter. Without triggering pulses, the counter stops, retaining the count from the last clock pulse. The o s c i l l a t i o n stops at any random count, because prior to i t , the osc i l l a t o r i s operating in an unstable region and the frequency i s high enough to make the LED indicators of the count appear as i f they were a l l l i t . Above count may be any number from 0 to 9, and the display w i l l show one light to be l i t out of ten. The display light emitting diodes may be arranged in a circular pattern and light emitting diodes of different colours may be used. -HZ- 207 4 3 0 . 0 - Instead of individual light emitting diodes, a package may be used, where a l l the light emitting diodes are assembled inside of a single unit. An example of these packages i s found in the RBG-/0BG-/GBG-/YBG-1000. The f i r s t l e t t e r indicates the colour of the light emitting diodes i . e. red/orange/green/yellow. The pin identifications are included below. RBG-/OBG-/GBG-/YBG-1000 97 10 TYP 04 , TYP 36 01 TYP m r n m — — . 0 2 -4 U • .0* —^ TYP TYP. I 15 " 1 .25 _. 1 10 ~T -.10 TYP .30 AUXILIARY TOP VIEW JO '» n i? it II M 13 t? II ,0 0 0 0 0 0 0 0 0 0 -ELEMENT «1 ELEMENT «10^ -PRODUCT IDENTIFICATION MARKING Pin Function 1 Anode 1 Anode 2 Anode 3 Anode 4 Anode 5 Anode 6 Anode 7 8 Anode 8 9 Anode 9 10 Anode 10 11 Cathode 10 12 Cathode 9 13 Cathode 8 14 Cathooe 7 15 Cathode 6 16 Cathode 5 17 Cathode 4 18 Cathode 3 19 Cathode 2 20 Cathode 1 -H3- 208 SEVEN SEGMENT DISPLAYS A numerical d i s p l a y i s e a s i e r to read than any of the two previously discussed d i s p l a y s . The output consists of seven l i g h t emitting diodes arranged to look l i k e a number 8 , and each diode i s l a b e l l e d with l e t t e r s "a" to "g" as shown below. d Notice that the display can s t i l l be inte r p r e t e d properly i f segment "d" happens to be disconnected or inoperative. The t r a n s l a t i o n of r e s u l t s from a binary coded weight system i n t o a seven segment system i s done by using a BCD-TO-SEVEN-SEGMENT DECODER/DRIVER, such as the 7 4 4 7 integrated c i r c u i t , or the 7 4 4 8 integrated c i r c u i t , see attached t e c h n i c a l s p e c i f i c a t i o n s . Notice that the 7 4 4 7 "sinks" the current from the elements of the seven segment di s p l a y that need to be energized. This type of decoder/driver requires a COMMON ANODE SEVEN-SEGMENT DISPLAY, such as the TIL 312 from Texas Instruments, or the END 507 from P a i r c h i l d . For the counter discussed above, i t s block diagram using a 7447 and a common anode seven segment display, i s the follo w i n g . F O U R L I N E S I l 4 8 7 S E V E N L I N E S < L o. B C D D E C I M A L C O U N T E R 7 4 9 0 B C D T O S E V E N S E G M E N T D E C O D E R D R I Y E R 7 4 4 7 — — A V W — — b lrtftArL b Kl e l C MAIL 5 F s l e .... e rsl f f Pvl .-1 — M W — — * . S Kl F - J O U T P U T S T O B E D I S P L A Y E D A R E L O J 209 COMMON ANODE e.g. TIL 312 OR FNO 507 A decode r/d r i ve r , such as the 7443 can a l s o be used. I t must be n o t i c e d tha t t h i s 7448 i n t e g r a t e d c i r c u i t " s ou rces " cu r ren t to the elements of the seven segment d i s p l a y tha t need e n e r g i z i n g . There fo re , t h i s type of decode r/d r i ve r r equ i r e s a COMKON CATHODE SEVEN-SEGMENT DISPLAY, such as the MAN 3640 from Monsanto o r the END 500 from P a i r c h i l d . The cor respond ing b lock diagram f o r the counte r i n ques t ion i s the f o l l o w i n g . P 0 U R L I N E S -7 S E V E N L I N E S B C D 1 B C D T O S E V E N D E C I M A L 2. S E G M E N T C O U N T E R 4 • D E C O D E R D R I V E R 8 7 4 90 7 4 4 8 O U T P U T S T O B E D I S P L A Y E D A R E J SPECIAL CHARACTERS COMMON CATHODE ~ e.g. MAN 3640 OR FND 5 0 0 S p e c i a l c h a r a c t e r s i n c l u d e p l u s s i ng s , l e f t dec imal p o i n t , r i g h t dec imal p o i n t , a s t e r i s k s , semicolons and other s needed f o r s p e c i a l type of a p p l i c a t i o n s . These s p e c i a l c h a r a c t e r d i s p l a y s and t h e i r cor respond ing connect ions are supp l i ed by the d i f f e r e n t manufacturers . T h e i r mode of ope ra t i on i s the same as f o r a numeric seven segment d i s p l a y . -MS- DIGITAL COUNTER USING COMMON ANODE DISPLAY 210 The following circuit may be assembled to test the characteristics of a common anode display and i t s driver. 10 9 8 g f Vte a b i n 'EJU PNO 507 d V* c NOTE : PINS 8 AND 3 ARE INTERNALLY CONNECTED R = 430 Jl -146- 211 DIGITAL COUNTER USING GO ".Gi: CATHODE DISPLAY The following c i r c u i t may be assembled to test the characteristics of a common cathode display and i t s driver. -147- THE OPERATIONAL AMPLIFIER The operational amplifier i s one of the most widely used and useful electronic components of control technology. Some of i t s applications are list e d below. a) Summing amplifiers b) Comparators c) Active F i l t e r s d) Waveshaping cir c u i t s e) Audio Amplifiers and Mixers As a summing amplifier, i t permits equivalent voltage levels to be obtained from binary weighted outputs. When binary data from a computer or any other electronic system i s converted into equivalent voltage levels, the resulting control applications are numerous. Some of these applications include switch activation of ovens and temperature regulating systems, speed control of motors, brightness controls i n illumination, direction finders in radio, tracking mechanisms i n satellites and missiles, computer simulation systems, such as aircraft training devices, etc. As a comparator, the operational amplifier makes i t possible to compare two voltages and then to determine which one i s larger. With this feature, the contents of an up or down binary counter may be compared to external voltage sources, so that the state of the count can be stopped whenever a match occurs. This i s the basic principle of Analog to Digital Converters (ADC), of which the di g i t a l voltmeter i s an example. Its application in Real Time Computers, to make decisions while industrial processes are taking place, makes them extremely important. -H8- 213 Operational a m p l i f i e r s are used i n the design of a c t i v e f i l t e r s . A ctive f i l t e r s are used to reproduce sound and video from a set of short duration pulses. This mode of transmission i s known as Fulse Code Modulation (PCM) and i s becoming i n c r e a s i n g l y important due to present t e c h n i c a l innovations, such as the use of f i b e r o p t i c s i n transmission systems. In pulse code modulation, sound information i s sent as a sequence of pulses, each with d i f f e r e n t binary coded value. At the rec e i v e r end, the a c t i v e f i l t e r restores the continuous nature to those s i g n a l s before reproduction takes place on a loudspeaker. Present users of PCM are telephone companies, a i r c r a f t , and systems where a bulky number of cables can be greatly reduced. The operational a m p l i f i e r , used as a waveshaping c i r c u i t , i s b r i e f l y discussed i n t h i s section, although t h i s a p p l i c a t i o n mode i s not d i g i t a l . 7/aveshaping c i r c u i t s are used i n the transmission and reception of TV n o n - d i g i t a l s i g n a l s . These c i r c u i t s were a l s o used i n the now outdated analog computer systems. The operational a m p l i f i e r i s also used as an Audio A m p l i f i e r and Mixer. In t h i s mode i t sums or adds d i f f e r e n t sound tracks and produces a single channel. This operation mode i s not d i g i t a l but shows the great v e r s a t i l i t y of the device. -149- 214 GENERAL CONSIDERATIONS The fundamental requirements f o r an operational a m p l i f i e r are: extremely high open loop voltage gain and also high open loop current gain. Open loop voltage gains can run from 40,000 to 250,000 v o l t s / v o l t depending upon the p r i c e tag of the component, and current gains of 50,000 amps/amp are not uncommon. The magnitude of the output voltage and output current i s u s u a l l y i n the order of - 20 V, and - 25 mA r e s p e c t i v e l y . The f l e x i b i l i t y and usefulness of the a m p l i f i e r comes from the f a c t that by choosing the correct feedback and input components, the a m p l i f i e r can be made to operate with almost any t r a n s f e r function that can be conceived. I t i s from t h i s f a c t that the a m p l i f i e r derives i t s de s c r i p t i v e name of "operational". Most of the a m p l i f i e r s a v a i l a b l e i n industry have two inputs, one i s the i n v e r t i n g input, l a b e l l e d "-" or " I " , which means that the p o l a r i t y of the input voltage i s inverted at the a m p l i f i e r output, and the other, the non-inverting input, l a b e l l e d "+" or "NI", which means that the p o l a r i t y of the input voltage i s not inverted at the output. I t s l o g i c symbol i s shown below. Notice that the inputs may be l a b e l l e d "-" and "+", or " I " and "NI" r e s p e c t i v e l y . ^ INVERTER INPUT I > OUTPUT NON- INVERTER Voltage gain i s designated by the l e t t e r A v, or simply A, and i s given i n v o l t s / v o l t . Current gain i s designated by the l e t t e r A^ and i s given i n amperes/amp. -ISO- 215 EASIC OIIXJUIT CCEFIGURATI02T The c i r c u i t below shows input r e s i s t o r R. and feedback r e s i s t o r m R F B connected to an o p e r a t i o n a l a m p l i f i e r . Vo l tages and c u r r e n t s a re des ignated as f o l l o w s : e^ = i nput vo l t age e ' = v o l t a ge at the i n v e r t i n g input e Q = output vo l t age i . , = i nout cu r rent ±2 = feedback cu r ren t By Ohm1s law, the i npu t cu r ren t becomes: x 1 = R. xn S ince t h i s c i r c u i t i n v e r t s and a m p l i f i e s the input s i g n a l by a f a c t o r A, then the output vo l t age i s : e = - e ' A o By Ohm's lav/, the cu r r en t i n the feedback c i r c u i t w i l l be g i ven by: f b -151- 216 I f we consider the f a c t that the current gain of the a c t u a l a m p l i f i e r i s i n the order of 20,000 to 50,000 amps/amp, then the drain of current into the i n v e r t e r input c an be ignored, therefore: i 1 = i 2 S u b s t i t u t i n g the previous equations f o r i ^ and i ^ , e. - e' e' - e x_ o_ _ . X1 " R. " R „ " X2 xn i b Since the working range of e can be between - 20 V and the a m p l i f i e r may have a voltage gain of 100,000 v o l t s / v o l t , then e' w i l l have the f o l l o w i n g magnitude: e e' = T^" =-iooTooo" = °*2 m V Prom above r e s u l t , i t i s assumed that e' i s approximately zero, that i s , i t i s a virtual ground. This assumption permits us to ignore the value of e 1 from the previous expression, therefore: e. -e l o R. 3* xn f b Above y i e l d s the f i n a l expression: E f b e_ = - e o i R. xn -152- 217 SUMMING AMPLIFIER As a summing amplifier, the operational circuit adds the value of incomming inputs. This i s easily seen from the circuit below and the considerations outlined with i t . If e Q^ denotes the output due to input ê  only, then, using the expression derived for the operational amplifier, 'o1 R o Also, i f e ^ denotes the output due to input e^ only, R. e 'o2 o R„ 6 2 The output voltage e Q i s the sum of above two voltages, therefore: e„ = e o o R R o o e„ + — — e. e1 e 2 1 + e o2 = - ( - R ; e i + -67 e 2 } = - Ro < — + -67 If we now make R . = R „ = R = R , then: 1 2 o e Q = - ( e, + e 2 ) This last expression shows that the amplifier output is the sum of the input voltages, and that the amplifier acts as an adder of voltages. -/53- 218 Notice that i f the input voltages have opposite polarities, e. g. ê  > 0 and eg < 0, then, the output voltage expression becomes: e Q = -(e, - e 2) and the amplifier then acts as a subtractor. The following summing amplifier may be assembled. Its operation may be verified for different values of ê  and e 2» The cir c u i t uses a //A741 operational amplifier. The technical data for this integrated ci r c u i t has been included at the end of this section. -T/WW R,=IOKn I vWWW 1 e 0 = -(e,+ e 1 ) Two 9 V radio batteries provide the supply voltage for the operational amplifier. The magnitude of this supply voltage determines ' the maximum voltage range available for summing actions. This means that the summing amplifier equation: e Q = -(e^ + e 2 ) , w i l l be satisfied only i f the sum of the input voltages does not exceed the value available from the supply, i.e. only i f : |e( -f e j ̂  9 7 In order to use the above circuit as a subtractor, simply invert the polarity of the input that needs to be subtracted. NOTE.- There are no loop currents between input sources, i . e. between branch e 1, and branch e 2, R2, because the input to the operational amplifier (pin 2) i s a vir t u a l ground. 219 COI.gARATORS The basic c i r c u i t configuration of a comparator i s given i n the next f i g u r e . It uses a^*A741 integrated c i r c u i t . The supply voltage was provided with two 9 V b a t t e r i e s , of the type a v a i l a b l e f o r t r a n s i s t o r radios. The pin connections shown are those recommended f o r this- p a r t i c u l a r device, see drawing of pin connections on the r i g h t , as well as the attached t a c h n i c a l data. ( i /p) i o V+ O/p NULL J / A 7 4 / T C TTTT offset L NI V- rRINCIPLE 0? OPERATION I f the input voltage ( i / p ) ^ into the i n v e r t e r section i s greater than the input voltage ( l / p ) 2 into the non-inverter section, then the output i s negative. I f the input voltage ( l / P ) 2 i n t o the non-inverter section i s greater than the input voltage ( l / P ) ^ i n t o the i n v e r t e r section, then the output i s p o s i t i v e . Above can be summarised i n the fo l l o w i n g table: INPUT CONDITION OUTPUT (I / P ) 1 > ( I / P ) 2 _ 9 V ( I / P ) 2 > ( I / P ) 1 + 9 V -ISS- 220 Notice that the available output i s proportional to the supply voltage. According to the included technical specifications for theJ*klK\, the supply voltage may not exceed a maximum of - 18 V. In d i g i t a l c i r c u i t s , the recommended logical voltage levels are in the order of + 5 V. Therefore, above output voltages must be limited in order to conform to d i g i t a l requirements. This i s accomplished below, by connecting a semiconductor zener diode across the output terminals. The zener diode shown below i s a 1N761, and i t limits the output voltage between -0.7 V to a maximum value of + 5.4 V. ( I / P ) , (1/P\ Using above circuit with i t s limiting device, gives a table of values that can be summarized as follows: INPUT CONDITION OUTPUT WITH ZENER (I/P) 1 > (I/P) 2 - 0.7 V (I/P) 2 > (I/P) 1 + 5.2 V NOTE.- A comparator i s a very sensitive circuit and cannot determine a balance condition. Therefore, when connected as shown above, i t w i l l produce a HI or a LO at anyone time. -156- 221 The following readings, measured with a volt-ohmmeter, conform to the previous table. Above circuit may be assembled to corroborate these results. (l/p)1 (I/P) 2 OUTPUT REMARKS - 4 . 5 - 6 - 0.7 - 1 . 5 + 1 .5 - 6 - 6' - 0.7 - 0.7 (I/P) 1 > ( I / P ) 2 + 4 . 5 - 6 - 0.7 - 6.0 - 3.0 0 0 + 5 . 2 + 5 . 2 (I/P) 2 >(I/P) 1 + 1 .5 + 4 . 5 0 0 - 0.7 - 0.7 (I/P) 1 > ( I / P ) 2 - 4 . 5 + 6 + 5 . 2 - 1 . 5 + 1 . 5 + 6 + 6 + 5 . 2 + 5 . 2 (I/P) 2 >(I/P) 1 + 4 . 5 + 6 + 5 . 2 GRAPHIC INTERPRETATION The values used to draw the following graph were measured in a similar fashion to those from the previous table. While drawing the graph, i t was assumed that those readings occurred at regular time intervals and i n a staircase arrangement. This last step i s done to familiarize the reader with staircase waveforms, commonly generated from binary counter ci r c u i t s , as i t w i l l be shown in the section of Digital to Analog Conversion. In this graph, ( l / p ) 2 i s kept at - 6 V and i s used as a reference voltage, whereas ( l / P ) 1 i s varied between + 4 . 5 V and - 9 V. -/57- 222 Notice a l s o , that a l o g i c LO l e v e l occurs i f ( l / P ) 1 > ( l / P ) 2 , but a l o g i c HI l e v e l occurs whenever ( l / P ) 2 > ( i / P ) ^ . INPUT A 4 , s 3.0 I.S -J.S -3.0 • MS - 6 . 0 -7.S -3.0 R E F E R E N C E C t / P X R E F E R E N C E (1/P) S.2 o -o.T LO LEVEL HI LEVEL LO LEVEL ( 1 / P ) , > fi/p)t (I/p) z > (I/P), (i/p), > a/p)2 These c i r c u i t s have predetermined t r a n s f e r functions that transform input s i g n a l s into s p e c i f i c a l l y shaped outputs. RC '.VAVESHAPING- CIRCUIT The c i r c u i t shown below c o n s i s t s of a square wave si g n a l generator and a load. The load i s made up of a r e s i s t o r and a capacitor connected i n s e r i e s . - c r o - When a square wave s i g n a l i s applied, the r e s u l t i n g waveforms, which appear across the r e s i s t o r and across the capacitor, w i l l not have the same shape as the input square wave. The next f i g u r e shows the differences between the o r i g i n a l square v/ave and the waves across the capacitor and the r e s i s t o r . -159- INPUT SIGNAL A FISURE (a) 0 Vc FIGURE ( b ) F I G U R E ( C ) 0 i • i i • CAPACITOR CHARGING TO tVs I I I I I 'CAPACITOR CHARGING TO - V s CURRENT DROPS TO ZERO WHEN Vc s 1 % r — — — _ — t F T t ' C U R R E N T D R O P S T O Z E R O W H E N T T e = -1TS 224 Figure (a) shows the input voltage versus time, i . e. the square wave signal from the generator. Figure (b) shows that the voltage v̂ , across the capacitor does not change instantaneously with new voltage levels. New voltage levels take place exponentially i n the same way that a tank with a floater controlled faucet f i l l s up with water, i . e. fast when the tank i s empty, because the floater i s f u l l y down and the faucet i s f u l l y open, and not so fast as the tank f i l l s up with water and the water level l i f t s the floater, closing the faucet more and more. Figure (c) shows the change of magnitude and direction of the capacitor current i ^ . If the capacitor needs to charge from -v^ to +v^, •/60- a very large current w i l l circulate-in the c i r c u i t , but this current 225 becomes smaller, in an exponential fashion, as the voltage in the capacitor approaches the new value v . This i s similar to what happens s to the tank with the floater controlled faucet. 7/hen the tank i s empty, the floater i s f u l l y down and the faucet i s f u l l y open, then a large flow of water starts to f i l l the tank. However, this flow of water becomes smaller as the tank f i l l s up with water and the water level l i f t s the floater, closing the faucet more and more. Similar action takes place when the capacitor needs to charge from +v to -v , except that the current w i l l be in the opposite s s direction. The waveshapes shown above can easily be seen on an oscilloscope Although oscilloscopes display voltage waveforms, they do not directly display current waveforms. Therefore, to observe the current waveforms due to i ^ , , i t must be noticed that: a) The capacitor and the resistor are connected i n series, therefore: i ^ = i R . b) By Ohm's law, the current i ^ , w i l l produce a voltage drop across the resistor, which i s directly proportional to i n , because the resistance i s constant. Therefore ±n <x v„. Thus, by connecting the oscilloscope across R, the resulting waveforwVp w i l l be proportional to the current waveform f o r i n . 226 R G D I ? ? E ? J S : ; T I A T O R S An RC waveshaping cir c u i t yields two different output signals, depending on the output connections. When the output connections are placed across the resistor R, as shown below, the output waveshape i s roughly the differentiated input signal. The term "differentiated" refers to the mathematical operation that describes the changes in shape undergone by an input signal, when i t reaches the output of this configuration. In our case, the output shapes are the current variations that take place in a resistive capacitive c i r c u i t , since v p o < i . C •o •o - 1 6 2 - 227 The output responses to different input waveforms are shown below: NEGATIVE; R A M P CONSTANT 1/« DUE TO CONTINUOUS FLOW OF CURRENT t CONSTANT ~Vn D U E TO CONTINUOUS FLOW OF CURRENT When v i s a ramp, the capacitor charges at a constant rate, s Because the voltage across R i s proportional to this charging current, then the voltage v^ i s constant. This i s equivalent to a tank with a floater controlled faucet. If the tank volume i s increased at a constant rate, the floater would never be l i f t e d up and the current would flow continuously. The simple EG c i r c u i t has two major disadvantages, i t loads other c i r c u i t s , and also attenuates the input signal, since i t i s made up of passive components. These disadvantages can be overcome, by the use of operational amplifiers. A differentiating c i r c u i t , using one of these operational amplifiers i s shown below. -163- R = 2KfL vW 228 o- C- I .O/F o> o RC INTEGRATORS When the output connections of a resistive capacitive c i r c u i t are placed across the capacitor C, as shown below, the output waveshape i s roughly the "integrated" input signal. The term "integrated" refers to the mathematical operation that describes the changes i n shape undergone by an input signal, when i t reaches the output of this configuration. The output shapes, for this c i r c u i t , are those corresponding to the voltage variations across the capacitor C. SQUARE WAVE / OR ( TRIANGULAR WAVE •O -164- 229 The output responses to d i f f e r e n t input waveforms are shown below: NOTE-A POSITIVE OR NEGATIVE RAMP WITH SLOPE m OR - m RESULTS IN THE MORE Notice that i n t e g r a t i o n i s the inverse process from d i f f e r e n t i a t i o n . Therefore square voltage l e v e l s r e s u l t i n increasing or decreasing outuput ramps. This i s so, because the capacit o r t r i e s to charge up to those new voltage l e v e l s . Although capacitors charge exponentially, i f the change of voltage l e v e l s occurs f a s t e r than the capacitor takes to charge to those new l e v e l s , then the rate of charge of the ca p a c i t o r w i l l look almost l i k e a l i n e a r ramp. Compensated c i r c u i t s , using operational a m p l i f i e r s , produce f a i r l y l i n e a r ramps out of square voltage l e v e l v a r i a t i o n s . One of these c i r c u i t s i s shown below. -165- 230 R r = lOMft N A A A - C= O . O I / F The connect ion of an i n t e g r a t o r f o l l o w e d by a d i f f e r e n t i a t o r , causes a square input s i g n a l t o become a t r i a n g u l a r waveshape at the output of the i n t e g r a t o r , then the d i f f e r e n t i a t o r r e s t o r e s t h i s t r i a n g u l a r waveshape back i n t o a square wave. Th i s arrangement may be assembled to show tha t i n t e g r a t i o n and d i f f e r e n t i a t i o n are i n ve r se f u n c t i o n s . IJot ice t ha t a 555 t i m e r connected i n the a s t a b l e m u l t i v i b r a t o r mode w i l l produce the r equ i r ed square waves f o r t h i s exper iment. A l s o , t h i s c l o c k c i r c u i t can supply f a i r l y good t r i a n g u l a r waveshapes. These are the waveshapes t ha t appear ac ro s s the e x t e r n a l c a p a c i t o r du r i ng the ope r a t i on of the c l o c k . These waveshapes can be used by connec t ing a set of output l ead s between the p i n number two of the 555 t i m e r and ground. -i(,b- 231 i INTEGRATOR DIFFERENTIATOR _0 OUTPUT -\<ol- DIGITAL TO ANALOG CONVSII'TERS The results from a binary count are i n binary form. The state of a count may be used to control the brightness level of an outside lamp. We may want the results of a low count to produce a low voltage on the lamp, and the results of a higher count to produce a higher voltage on the same lamp. These output voltages may be stepped up i n discrete quantities, as a function of an upwards binary count. The process of converting binary data into specific voltage levels i s known as Digital to Analog Conversion (DAC). This process i s the fundamental form of communication between a computer system and the external systems under i t s control. FACTORS AFFECTING DAC For the counters so f a r discussed, binary coded weights have been assigned to the output lines of each f l i p flop. These weights are based on powers of two. For a 0 to 15 counter, their distribution by f l i p flop position i s shown in the table below. FF WEIGHT REMARKS A 2° = 1 LSB B 21 =2 C 2 2 = 4 D 3 2J = 8 IrhO-U If the count i s 1 5 , i . e. i f the four f l i p flops A to D are set, then their outputs w i l l be QA = Q B = Qc = Q D = V c c . If each output line i s fed individually and directly to an external lamp, the external lamp would produce the same brightness with the LSB line as with the PISE line, because the only thing that distinguishes these lines i s their e l e c t r i c a l position within the counter. - I 6 8 - 233 Thus, to discriminate between the different counter output lines: a) Each HI output line must be multiplied by its respective weight. b) A l l the resulting weights must be added. SUIITITG AMPLIFIER FOR SELECTED VOLTAGE SOURCES A summing amplifier adds the voltages available at its input. In the circuits used in this section, one, two or more voltage sources are selected to make up the input or inputs to the summing amplifier. In order to connect these sources, one has to determine which source or sources are needed in the SUM, and then activate the desired choice by closing the appropriate switch or switches. The connection of the selected sources is done by manually openning or closing wires on an SK10 board, or with ordinary switches. For fast operation, electronic switches must be used, like the ones available in a 4016 or a 4066 integrated circuits. The potential level of the sources is set usually to voltages that are proportional to weighted binary coded variables. It is these weighted binary quantities that need to be converted into corresponding analog voltage levels. The circuit needed to convert the digital results from a binary coded count (0 to 15), into analog output voltages, is shown below. Notice that four sources and four switches constitute the inputs to the summing amplifier. Also that the values of each source are weighted and each source is switched ON by a position weighted selector switch. - I 69 - 234 Gd=8V - U FF D R SW4 ec=4V - U F F C ! R -AA/V SW3 FF B ! R -AA/V SW2 FF A | R s w R AND Rp8-RiN=R THEN e o a . = - e a . "_7 e o c=-e c The table of selector switches versus summing outputs i s given below. SELECTOR SWITCHING SELECTED SUMMING SW WEIGHT SOURCE OUTPUT 1 2° = 1 1 V 1 V 2 21 = 2 2 V 2 V 3 2 2 = 4 4 V 4 V 4 2 3 = 8 8 V 8 V As an example, consider the contents of a binary counter to be: QA = 1 (LSS); Q B = 0; Qc = 1 and Q D = 0 (MSB). The analog equivalent of this count i s made by closing selector switches 1 and 3. This way, the voltages from the 1 V source and the 4 V source are inputs to the summing amplifier and thus added. Their 5 V sum i s the desired analog equivalent. -no- 2 3 5 The operation of the "Summing Amplifier f o r Selected Voltage Sources" may be v e r i f i e d by assembling the following c i r c u i t . I t consists of: 1. - A 555 timer used to produce clock pulses at a variable rate. 2. - A 7490 BCD Decade Counter to produce a 0 to 9 binary count. 3. - Four voltage supplies with convenient weighted values, l i k e those shown i n the schematic diagram, i . e. 6V, 3V, 1.5V and 0.75V. NOTE.- I t must be kept i n mind, when choosing these supplies, that the maximum input to a summing amp l i f i e r i s limited by the value of i t s supply voltage, and that t h i s supply voltage should not exceed the maximum rated value of -18V. 4. - An electronic switch 4066, used i n the d i g i t a l mode. See i t s e l e c t r i c a l s p e c i f i c a t i o n s , included at the end of t h i s section. 5. - A/*A741 operational amplifier, used i n the summing amplifier mode. Two 9 V radio batteries may be used to provide the - 9 V supply requirements. Notice that i n t h i s c i r c u i t , the inputs to the operational amplifier are v i r t u a l grounds, as can be v e r i f i e d by measuring the voltage at pin number two of the/*A741. Therefore, when different voltage sources get "switched", i . e. connected to the operational amplifier, no loop currents ever r e s u l t . When the frequency i s s u f f i c i e n t l y low, the output voltage from the operational a m p l i f i e r may be measured with a volt-ohmmeter. The recorded values may be used to complete the accompanying table. When an oscilloscope i s available, the frequency must be increased to observe the r e s u l t i n g staircase display. The drawback with t h i s c i r c u i t i s that i t requires a large number of voltage sources with a high degree of accuracy i n t h e i r rated values. - I 7 I - 236 BINARY COUNT D C B A e 0 0 1 2 3 A 5 6 7 8 3 - ( 7 2 - 2 3 7 ST; ~ 1I17G AMPLIFIER 'WITH WEIGHTED IilrUT VOLTAGES This amplifier uses the supply voltage as i t s single reference voltage. The proper weighted voltages are achieved by selecting the correct voltage dropping resistors. This selection i s done with four individual switches in the cir c u i t shown below. + V cc o Vcc I0KJL -nAA/V/— FPC e 3*Vc C 20 Wl A W W - _2_ 1 e,=Vcc 80Kft - O MAMr- _2_ I vWW- The resistor values used i n the above c i r c u i t , have been selected using the summing amplifier equation, that was developed in the section of operational amplifiers: e ° = _ e i RIIT The f l i p flops from a binary counter may be used to activate each- individual switch. Thus, each f l i p flop controlled switch w i l l produce a weighted output voltage £Q^> e Q 3 ' e 0 2 a n c * e 0 1 5 - 1 7 3 - 238 e - - V 1 0 k = - V 04 cc 10 k cc e = _ V 1 Q k = - l y e03 cc 20 k 2 cc e = - V 1 0 k = - l y 02 cc 40 k 4 cc 01 cc SO k 8 cc I t can be seen, from above c a l c u l a t i o n s , that the output vo l tage s a re weighted va lues of the supply v o l t a ge . YiTien a l l the input swi tches are c l o s e d , the t o t a l output vo l t age i s g i ven by the summing a m p l i f i e r exp re s s i on : e 0 = " ( e 4 + 2 e3 + 4 6 2 + 8 V Where: = e2 = = eA = + The f o l l o w i n g c i r c u i t may be assembled and t e s t e d . I t uses a manual p u l s e r , so tha t a count may be stepped up manual ly . Th i s procedure pe rmi t s the use of a volt-ohmmeter to measure the r e s u l t i n g output v a l ue s . The t a b l e tha t accompanies the c i r c u i t may be completed w i t h the recorded v a l ue s . No t i ce tha t the power requirements are met by two 9 V r ad i o b a t t e r i e s f o r the ^uA741, p l u s a separate supply f o r the + V c c b i a s . Y/hen an o s c i l l o s c o p e i s a v a i l a b l e , a 555 t i m e r may be used to t r i g g e r the counte r a t h i ghe r f r e q u e n c i e s . Th i s procedure a l l ows to observe the r e s u l t i n g output vo l tage s t a i r c a s e on the o s c i l l o s c o p e sc reen. 239 The drawback f o r "this c i r c u i t i s the large range of r e s i s t o r s needed.Their value doubles every time that the binary inputs are increased. -175- s m - s m s r o A M P L I F I E R WITH •RESISTIVE LADDER ATTENUATOR 240 This circuit weights the binary input voltages with a resistive ladder attenuator. The advantage of the ladder network i s that i t uses only two values of resistance. The ci r c u i t configuration i s shown below: / e» *»• * Si. ̂  e 0 - - ( e ^ - r ^ t -j-* -j-) W H E R E EQUIVALENT VOLTAGE CONTRIBUTION AT POINT "I" DUE TO 'EACH SOURCE It i s shown in the appendix, v/ith the use of circuit analysis techniques, that the input voltages e^, e^, e^ and e^, when fed into such network, w i l l become attenuated in a weighted fashion. See appendix under Thevenin's Theorem, examples 1 and 2. Point "I" i n the above cir c u i t i s the output of the resistive ladder network. At this point, the input voltages produce the weighted values shown below. ^ 1 e 3 " 4 e 3 e2 *" 8 e2 1 e 1 16 e 1 -I76- 241 Thus, when a l l those v o l t a ge s are p resent , t h e i r c o n t r i b u t i o n a t po i n t " I " w i l l be: e e e 2 e±= — + — + — + — Above exp re s s i on i s c l e a r l y the sum. However, the summing a m p l i f i e r i s s t i l l needed to i n s u r e that the r e s i s t i v e l a d d e r network i s i s o l a t e d and does not l oad o t he r c i r c u i t s . Be s ides , by s e l e c t i n g the proper feedback r e s i s t o r i n the o p e r a t i o n a l a m p l i f i e r , d i f f e r e n t va l ue s of a m p l i f i c a t i o n can be ob ta ined . BQUIYALEffg RESISTANCE OE EACH SOURCE AS SEEN YRQ11 POINT " I " Aga i n , by the use of c i r c u i t a n a l y s i s techn iques , discussed i n the appendix, i t can be shown that as f a r as p o i n t " I " i s concerned, each i nput source e^, e^, e 2 and e^, can be rep laced by equ i va len t sources w i t h e4 e 3 e 2 e1 weighted va l ue s : — , ~ , — and •yg- r e s p e c t i v e l y , on ly i f each of these new sources i s connected i n s e r i e s -.vitr. an equ i va len t r e s i s t o r R, i n s t e a d of the r e s i s t i v e l a d d e r network. EQUIVALENT CIRCUIT r Thus, when the input sources and l a dde r network get r ep l a ced by t h e i r c o u i v a l e n t c i r c u i t , the f o l l o w i n g c o n f i g u r a t i o n r e s u l t s . Compare i t with, the Summing A m p l i f i e r f o r Se l e c t e d Voltage Sources. -I77- I WWW 1 242 e 0 = -2e.- Above cir c u i t ,.vill produce the sszm, voltages at point as those produced by the original sources, when tied to the original resistive ladder network. The advantage of this equivalent ci r c u i t i s that i t i s easier to analyze. ?or example, using the equations developed for the summing amplifier, i t i s clear that 3. i s equal to H, a fact that i s not obvious from the i n ' original resistive ladder network. If in above c i r c u i t , R_, i s chosen oo that Ep B = 2R, then the resulting voltage eQ at the output of the operational amplifier becomes: FTB 25 . eo = - e i - T — = " e i — = " 2 e i ' i n Thus, every voltage at point ; II" in the above circuit i s inverted and doubled by the operational amplifier. Notice that other values for could be selected, depending on the desired ratio for output voltages. The f i n a l expression for the output voltage due to e,,, e^, e^ and - 1 7 8 - 243 •The fo l l o w i n g c i r c u i t may be assembled. I t con s i s t s of a 555 timer, a 7490 BOD decade counter and a r e s i s t i v e ladder network. I f the clock frequency i s s u f f i c i e n t l y slow or manually applied, the output voltages may be measured with a volt-ohmmeter. I f an os c i l l o s c o p e i s a v a i l a b l e , the clock frequency may be stepped up to observe the r e s u l t i n g s t a i r c a s e display. Recorded values may be used to complete the accompanying t a b l e . 7 4 9 0 5 8 14 9 PINS mm— C tea) 81 KA vWVW— 82 Kfl -vVWVW- & 6 2 K A • 39 m a, e, » f 8 : 39 KCl 1 COUNT D C 3 A e o 0 1 2 3 4 5 6 7 8 9 - I 7 9 - 244 ID LADDER \'!:T ..'ORK Most counters with a t o t a l count greater than 10, use BCD boxes, so that the count i s made i n multiples of 10, e. g. 009, 099, 999, etc. The following approach, to convert BCD box counts into analog voltages i s used: 1. - Each BCD box must be weighted with binary weights, using the previously discussed summing a m p l i f i e r with weighted input voltages. Notice that the voltage l e v e l s are s t i l l given i n 1 e3 e2 e1 — T increments, since e„ = e. + — + — + — , even though o U 4 c. 4 o these voltage l e v e l s are used to represent a count from 0 to 9. 2. - The r e s u l t i n g analog contents of each BCD box are then weighted again, t h i s time to account f o r the multiple of 10 that each one of them must contain. Thus, each BCD box should provide the 1 correct voltage c o n t r i b u t i o n i n -^Q increments. The f o l l o w i n g network i s used f o r t h i s conversion. I t shows each B C D box replaced by a summing a m p l i f i e r with weighted input voltages. - 1 8 0 - D ~ / \ZVVvV- blNARV CONVERSION C — - e 3 2 0 W I ) y/wwir- B— _L yA/W/VIr _ i e, 8fl Kil A,— -O— IAWV- _L c — wwv— e3 2 O K A i w w w - i <M/v\r- e, 80 KA 1 uVWV- e, i OKA WWV*- e 3 20K0. MVW- 40 Kil e, 80 KA. AWVV- DECIMAL CONVERSION / \ 245 HUNDREDS TENS UNITS Rc ANALOG OUTPUT 1 This network should produce three simultaneous s t a i r c a s e s , one corresponding to the binary weight conversion f o r "un i t s " , one corresponding to the "tens" and one to the "hundreds". Since the three s t a i r c a s e s are added at point " I " , the output r e s u l t s i n a single s t a i r c a s e v/ith 999 voltage l e v e l s . See the fo l l o w i n g f i g u r e s . -18/- 246 A BCD BOX OUTPUTS 247 DETERMINATION OP VALUES POR R AITD Ĥ. c t The equivalent ci r c u i t for the network must be defined f i r s t . This i s done using the ci r c u i t analysis techniques discussed in the Appendix. Por this particular case, see appendix under Thevenin's Theorem, examples 3 and 4. It i s shown in this section, that the BCD voltages for "hundreds" e^, and "tens" ê ,, produce the equivalent values e^' and ê ,' at the output of the BCD ladder network, i . e. at point " I " : R̂ "H ®H R̂  + R = e. t "s R. H R 'T' "T R, + R t s R, + R t s = e„ Where R represents the resistance of each BCD box when a l l i t s s voltage sources are shorted, i . e. 10 K A \ZVVW— IOKCL -www 4 0 K A -VVWW 8 0 Ka •www 1 R s = - 80 k = 5 . 3 3 k + 40 k 20 k 10 k and Also, as far as point " I " i s concerned, each input source e^, ê ,, e^ can be replaced by their equivalent sources e ', e 1 and e. ' , only i f each of these new sources i s connected i n series with an equivalent R.R "t s resistor — , instead of the BCD ladder network, t S With above values, the equivalent ci r c u i t for the BCD ladder network oecomes: - 1 8 3 - 2 4 8 R t e » = e « R t + R s _ | + 3 Rt+Rs 'F v V W \ A - H p vWW— RtRs _ 1 + Rt + Rs -Hi /WVW- - l - I -VAVW r 1 EQUIVALENT CIRCUIT OF BCD LADDER NETWORK IJotice t h a t e^ 1 has to be -JQ of e^' , i n order to s a t i s f y the d e s i r e d decimal weighting: t _ - i e ' 10 E H Theretore: "T Th/V R s E t + R ^ ~ 10 ^ 8 H R / + R ^ Al s o n o t i c e that when each BCD box has the same count, d i s r e g a r d i n g t h e i r decimal weights, t h e i r i n d i v i d u a l voltage outputs are the same, due t o the f a c t t h a t a l l BCD boxes use the same voltage reference +V , i . e, cc e 1 = e ' = "U Therefore, our previous equation gets f u r t h e r s i m p l i f i e d : R 1 f4 R. + R 10 t s Therefore: R s = 9 R t S u b s t i t u t i n g the value f o r R found'above, i . e. R = 5.33 k i l , s s i n t o our l a s t expression, y i e l d s the value f o r R.. - I8<1- 249 R, = 9 R = 9 x 5.33 k = 43 kil t s The value for R i s derived from the basic network relationship shown below: I VvWr R t R s Rs t i/WWV- Therefore: R t E s R c = R t " R~~Hr 43.2 kfl. Using above values, we can assemble and test the following c i r c u i t . An oscilloscope w i l l be useful to show the discrete voltage levels, but a volt-ohmmeter can s t i l l show the gradual increase in the analog output voltage as the count proceeds upwards from 0 to 99. 7490 (TENS) Cc s II B IH 9 PINS 1,11 7490(UN|TS) 11 8 14 PINS 10 ML 20Kil - M W W - 82KI1 •www— IOKCL -AVVW- 2 0 K f l - JWWV- 39KA. -www— •WWvV— ANALOG OUTPUT * 1 43.2KC1 ~ (39KHt47KXL) Rt (39Ka+IOK£L) - 1 8 5 - ANALOG- TO DIGITAL CONVERTERS Analog to Digital Converters (ADC) are also referred to as Encoders. They constitute the link between the external analog world and a d i g i t a l system. Most of nature's processes are in analog form. Some examples are: ' temperatures, pressures, wind velocities, distances, acceleration rates, amounts of illumination, volume variations of sound (pressure), f r i c t i o n forces, etc. Man has tried to relate the amount of those processes with ratios of measurable quantities, e. g. twice as much light as three times as fast as half as warm as etc. El e c t r i c a l transducers have allowed him to convert those -amounts into analog voltages. The process i s the following. a) A man has to read the analog display, e. g. the indicator needle of a volt-ohmmeter. b) He then makes up a decision, either to record the measured quantity into a f i l e , IN DIGITAL POEM! , or use the recorded information to determine the outcome of other a c t i v i t i e s . Above task can be done using an Analog to Digital Converter. These ADC's allow the conversion of analog voltage read outs into binary coded weighted quantities. The read out can then be displayed using seven-segment displays, or stored directly into the memory of a computer. Then the computer program can take over to activate other instruments or equipment. An ADC performs i t s function as follows. a) It compares the analog input with internally generated counts or quantities. -/86- 251 b) When the external analog read out equals the internal count, a message is sent to stop the counter. Thus, i t is the contents of a counter, in digital form, that become the digital read out. Hence the great importance of counters and comparators in the Analog to Digital conversion of external data. SWEP TIMING ANALOG- TO DIGITAL CONVERTER This analog to digital converter uses the following block configuration. S T A R T / R E S E T Ml MM B I N A R Y i * COUNTER R E S E T O — ANALOG INPUT> L I N E A R R A M P GENERATOR VOLTAGE COMPARATOR RAMP DESCRIPTION 1.- A start pulse: a) Resets a counter to zeroes. b) Sets a control f l i p flop. The control EE then enables clock oulses into a counter. - 1 8 7 - 252 c) T r i g g e r s a l i n e a r ramp generator to beg in a ramp. 2. - An ana log input i s compared w i t h the va lue of the l i n e a r ramp. 3. - Vvhen the "RAMP VOLTAGE" exceeds the "ANALOG INPUT", the comparator sends a HI pu l se i n t o the re se t input of the c o n t r o l f l i p f l o p , 4. - Once the c o n t r o l FF i s r e s e t , i t i n h i b i t s the c l o c k pu l s e s from t r i g g e r i n g the counter . 5. - The counte r d i s p l a y s the number of c l o c k pu l se s accepted before the generated ramp exceeds the analog i n p u t . ' The f o l l o w i n g f i g u r e s show the g r a p h i c a l comparison between the "ANALOG SIGNAL" and the "GENERATED RAMP". The r e s u l t s of the count are a l s o i n d i c a t e d , i n the i n t e r v a l where the "ANALOG SIG2CAL" i s g r e a t e r than the "GENERATED RAI.1P". COMPARISON < A START PULSE \ PRODUCES A R f lMP — — t A START PULSE ^ ALSO ENABLES J/L CLOCK PULSES ^ \ _ i 1 I i i y ^ CLOCK PULSES ARE i 'A O Y 5K> AK1 y Y, /, INHIBITED WHEN y. yy // (RAMP) > (ANALOG I/P) // V. V, CLOCK PULSES <3ET COUNTED AND DISPLAYED ON A SEVEN SEGMENT DISPLAY 253 The disadvantage of above configuration i s that a slight variation in the slope of the ramp w i l l produce a large variation in the number of pulses counted. See the following figure. ANALOG I N P U T 1 *- -IBS- ANALOG- T O DIGITAL CONVERTER - ZISD3ACK LE3THOD 254 Th i s c onve r t e r compares the analog input versus a s t a i r c a s e waveform ( i n s t e a d of a ramp).The s t a i r c a s e waveform i s the DAC of the s t a t e of a counte r . See the f o l l o w i n g genera l b lock diagram. CLOCK >i START/C RESET S Q CONTROL F F _ R Q RESET BINARY COUNTER ANALOG INPUT, DAC VOLTAGE COMPARATOR -ANALOG COUNT DESCRIPTION FOR POSITIVE INPUTSjWHEN (ANAL0G\ > /ANALOGS V COUNT ) 'llNPUT / A "HI" PULSE IS SENTTOf?ESET T H E CONTROL FLIP FLOP 1 . - A s t a r t pu l s e : a) Resets the counter t o zeroes. b) Sets the c o n t r o l f l i p f l o p . The c o n t r o l f l i p f l o p then enables c l o c k pu l se s to t r i g g e r the coun te r . c) Once the counte r begins to count, i t s count i s shown on a seven-segment d i s p l a y , and i s a l s o converted i n t o an analog v o l t a ge e q u i v a l e n t . Th i s analog, equ i va l en t i s a s t a i r c a s e waveform. 2. - An ana log i nput i s compared w i t h above s t a i r c a s e waveform. 3. - When the "ANALOG COUNT" i s g r e a t e r than the "ANALOG INPUT", -(90- assuming that both of these i npu t s a re p o s i t i v e , then 255 the comparator sends a HI pu l se i n t o the re se t input of the c o n t r o l f l i p f l o p . 4. - When the c o n t r o l f l i p f l o p i s r e s e t , i t i n h i b i t s the c l o c k pu l s e s f rom t r i g g e r i n g the counter . 5 . - The va lue s to red by the counter corresponds to the va l ue of the "ANALOG INPUT". CIRCUIT IMPLANTATION An Ana log to D i g i t a l Conve r te r C i r c u i t , u s i n g the feedback method, i s i n c l u d e d nex t . Th i s c i r c u i t may be assembled to co r robora te above d e s c r i p t i o n . The ope r a t i on of i t s main b l o c k s , enc lo sed i n dashed l i n e s , i s the f o l l o w i n g . CLOCK.- I t p r ov i de s the c l o c k pu l s e s f o r the counte r . I t c o n s i s t s of a 5 5 5 t i m e r i n the a s t a b l e m u l t i v i b r a t o r mode, and i t s f requency may be c o n t r o l l e d manual ly . "AID" GATE.- A 7400-1 i n t e g r a t e d c i r c u i t i s used to l o g i c a l l y "AND": a) The enab l i ng pu l se from the c o n t r o l f l i p f lop, " and b) The c l o c k pu l se s f ed i n t o the BCD counter . When the START/RESET SWITCH i s c l o s e d , i t uses a NAND gate from t h i s same 7400-1, to produce a III pu l se out of i t s p i n number 3. CONTROL P P . - I t i s an RS f l i p f l o p made up w i t h two NAND gates f rom a second 7400 i n t e g r a t e d c i r c u i t , (7400-11). When the START/RESET SWITCH i s c l o s e d , a HI from p i n number 3 of the 7400-1 set s the c o n t r o l f l i p f l o p . The Q-output of the c o n t r o l f l i p f l o p i s then used to ENABLE c l o ck pu l se s i n t o the 7490 counte r . BCD COUNTER.- I t c o n s i s t s of a 7490 Decade Counter. When a START/RESET SWITCH i s c l o s e d , i t produces a HI pu l se i n t o i t s p i n s 2 and 3, r e s e t i n g the counter to zeroes . 256 DRIVER AI7D DISPLAY.- It consists of a 7447, BCD-TO-SEVEN-SEGMNJT DECODER/ DRIVER, and an ?ND507, COISm ANODE SEVEN-SEGMENT DISPLAY. DAC- The Digital to Analog Converter uses a resistive ladder attenuator, and a/(A741 operational amplifier. The output voltage from the ladder network, i . e. the "ANALOG COUNT", i s a positive increasing staircase waveform, like the one shown below. V A Once above waveform i s fed into the inverting pin number 2 of the _/'A741, i t results in an inverted staircase waveform at i t s pin number 6, see the figure below. t -V Y COMPARATOR.- A /*A741 i s used in the comparator mode. The inverted "ANALOG COUNT" i s fed into i t s pin number 2 and a negative "ANALOG INPUT" i s fed into i t s pin number 3« When.a comparison takes place, and the "ANALOG COUNT" i s greater than the "ANALOG INPUT", then the output of the /A741 becomes - 9 V. If a diode i s connected at the output, as -192- shown below, then the output l e v e l gets c l o s e r to "GP.OUND", 257 producing a LO l e v e l output, ( i t a c t u a l l y measures about -0.7 V, i . e. the value of the forward bias voltage drop across the diode). AIIALOQ ANALOG COUNT ANALOG INPUT - (ANALOG COUNT) > (ANALOG l/P ) -o LO When the "ANALOG INPUT" becomes greater than the "ANALOG COUNT", the output of the _//A741, normally an expected + 9 V, (no more than the supply voltage f o r the /*A741), gets clamped down to + 5.2 V. This event takes place only i f above diode i s replaced by a + 5.2 V zener diode. Thus, a l o g i c a l HI l e v e l i s obtained. ANAlMi ANALOG COUNT "o \ ^ ANALOG INPUT (ANALOG I/P)>(ANALOG COUNT) + 'A LO Above HI l e v e l output i s then used to "reset" the FtS cont r o l f l i p f l o p , so that i t DISABLES f u r t h e r clock pulses from reaching the counter. -/93- ANALOG TO DIGITAL CONVERTER FEEDBACK METHOD 258 A N A L O G ° C O U N T "VftNAtOG (COWftRHToR)! WHEN (ANALOG I/P) > (COUNT) , A "HI" INTO "RESLT'OF CONTROL FF WILL CAUSE rr TO DISABLE CP'S ( N T O T H E C O U N T E R ANALOG T INPUT -VANAU>« -m- 259 ANALOG TO DIGITAL CONVERTER - TRACKING METHOD Tracking converters use an up/down counter to determine the equivalent d i g i t a l count of analog inputs. If the analog inputs vary, their variations w i l l be tracked down by the converter. The block diagram of this method i s shown below. CLOCK UP/DOWN COUNTER UP/ON ANALOG COUNT D A C VOLTAGE COMPARATOR A " L 0 " STEPS COUNTER UP A "HI STEPS COUNTER DOWN ANALOG INPUT \ FOR POSITIVE INPUTS = I- WHEN (ANALOG l/P)>(AMALOG COUNT) A "LO" PULSE STEPS THE COUNTER UP 2 r WHEN (ANALOG COUNT)> ("ANALOG I/p) A "HI" PULSE STEPS THE COUNTER DOWN SINCE NO TWO VOLTAGES ARE. EXACTLY E Q U A L , A CONTIMUOUS ~ ONE-BIT RESULTS CLOSE TO BALANCE. DESCRIPTION When the power i s turned on: 1. - An analog input i s compared with the analog contents of a binary up-down counter. 2. - The results of above comparisons are used to step up or to step down the contents of the counter. - 1 9 5 - 260 3. - A comparator, being a very s e n s i t i v e c i r c u i t , can detect even the most minute d i f f e r e n c e between two v o l t a g e s . Since no two v o l t a g e s are e x a c t l y a l i k e , the balance c o n d i t i o n can never be reached. Therefore, the d i g i t a l equivalent of an analog input i s found only when a continuous - one-bit i n the counter causes a l i k e change i n the Least S i g n i f i c a n t D i g i t of the d i s p l a y . 4. - Any f u t h e r changes of the analog input w i l l be detected by the comparator, causing the counter to t r a c k down the new value or values, w i t h i n the range of the counter, u n t i l a - one-bit c o n d i t i o n e x i s t s again. CIRCUIT IITIKVENTATION The f o l l o w i n g c i r c u i t i s an Analog to D i g i t a l Converter, i t uses the Tracking Method. T h i s c i r c u i t may be assembled to corroborate the d e s c r i p t i o n given above. The diagram i s shown subdivided i n t o f u n c t i o n a l b l o c k s . The components and f u n c t i o n of these blocks i s given below. CLOCK.- A 555 t i m e r i n the a s t a b l e m u l t i v i b r a - t o r mode, w i t h manual c o n t r o l over i t s frequency. UT/DO-ViJ COUNTER.- A 74190 i n t e g r a t e d c i r c u i t i s used. This c i r c u i t i s a synchronous UP/DOWN BCD Decade Counter, v/ith Down/Up mode c o n t r o l . I t s t e c h n i c a l s p e c i f i c a t i o n s are included at the end of t h i s s e c t i o n . An ENABLE inp u t i n t h i s c i r c u i t , l o c a t e d i n p i n number 4, must be connected to ground. T h i s l a s t connection permits the c l o c k pulses to step the counter. The c i r c u i t counts U? v/ith a LO input i n t o p i n number 5, and i t counts DOT/IT w i t h a II I input i n t o the same p i n . - 1 9 6 - 261 DRIVER AND DISPLAY. - It consists of a 7447 BCD-T0-3EVEN-SE0I.IENT DECODE?/ DRIVER, and an END507 COMMON ANODE SEVEN-SEGMENT display„ DAC- The Digital to Analog Converter consists of a resistive ladder attenuator and a juA741 operational amplifier. This DAC i s used to obtain the analog count. For a negative Analog Input, when the power i s turned on, an up-count i s initiated from zero. The resulting count i s an inverted staircase. COMPARATOR.- A /*A741 i s used in the comparator mode. This circuit compares the voltage levels fed into i t s two inputs. These voltage levels correspond to: a) . The Analog Count, which i s fed into pin number 2, i . e. the inverting input of the operational amplifier. This Analog Count i s a negatively biased staircase from the DAC. b) The Analog Input, which i s fed into pin number 3) i . e. the non-inverting input of the operational amplifier. This Analog Input must be negative, so that i t can be tracked down and crossed over by the negatively biased Analog Count. This last condition occurs when both voltages are close to the same value. -197- 262 COMPARATOR OPERATION V/hen the power i s f i r s t turned on, the voltage of a negative ANALOG INPUT i s compared with that of an ANALOG COUNT. At this instant, the ANALOG COUNT i s zero volts, which i s greater than the negative ANALOG INPUT. As long as the ANALOG COUNT remains greater than the ANALOG INPUT, the output of the /A741 w i l l be a negative voltage (-9 V). In order to convert this negative voltage into a logical LO level, a zener diode i s connected across the output terminals of the J*A7A1. The zener diode conducts v/hen i t s anode terminal, which i s connected to ground, becomes less negative than i t s cathode terminal. This forward bias conduction clamps the negative output voltage of the /"A741 to a nearly ground potential, thus resulting in the desired logical LO. Above LO, when fed into the up/down counter, w i l l step the count upwards. -198- 263 When the ANALOG INPUT becomes greater than the ANALOG COUNT, the output of the/*A741 w i l l t r y to be equal to +9 V. Due to the zener diode, that has a reverse break down voltage of +5.2 V, the output e Q i s clamped, t h i s time to +5.2 V, r e s u l t i n g thus i n a p o s i t i v e HI l e v e l . Above HI, v/hen f e d into the up/down counter, w i l l step the count down. \MPinJ ( COUNT NOTE." N E X T CLOCK PULSE ( D f l S U E D L I M E S ) /ANALOG^ / ANALOS\ \̂  COUNT J \ INPUT / HI —I LO s t Since a comparator cannot determine a balance condition, the next clock pulse w i l l f i n d that the ANALOG COUNT, having been stepped down, i s now greater than the ANALOG INPUT. This cond i t i o n r e s u l t s i n a LO that w i l l step the counter up again. Thus, the d i g i t a l equivalent of an analog input i s found when a continuous - one-bit r e s u l t s i n the counter. -199- ANALOG TO DIGITAL CONVERTER 264 TRACKING METHOD 9+V, ANALOG INPUT (NEGATIVE") -200- 265 SUCCESSIVE APPROXIMATION The methods previously described for Analog to Digital Conversion are often referred to as "integration methods". A count i s i n i t i a t e d to match the value of the Analog Signal. Each step of the count corresponds to a clock pulse. Devices employing this method are slow but accurate, and not very expensive. When higher speeds of conversion are required, one must use Successive Approximation Methods. These methods require fewer clock pulses per conversion than the integration types, though they are more expensive. Successive approximation may be of the "analog type" or of the "ladder type" ( d i g i t a l ) . ADC - ANALOG- TYPE This analog type of conversion may be described by the following example. To measure the unknown volume of liquid in an uncalibrated container, the following procedure may be used: Eour binary weighted measuring containers are used for this example. The volume of each of these containers i s a submultiple of the maximum measurable volume V The submultinle volumes are as follows: ref TT V „ , 4" V J> •> V J> > ^ d -T4- V _ . 2 ref ' 4 ref 7 8 ref ' 16 ref A l l the measuring containers are to be tried, starting f i r s t with the largest one, and then proceeding to the smaller ones. Each container used must be f i l l e d to maximum capacity. A f u l l container w i l l indicate a "one" and an empty container a "zero". Once the unknown volume has been distributed among the four -201- 266 measuring containers, a four d i g i t read-out w i l l i ndicate the value of the unknown volume. The small amount l e f t over i s the measurement error. This e r r o r may be reduced f u r t h e r by increasing the number of binary weighted measuring containers. EXAMPLE.- Assume that the unknown volume i s 0.69 V „, then by r e f J using the above procedure, the f o l l o w i n g measured volume w i l l r e s u l t : NOTE.-THIS CONTAINER IS NOT USED, BECAUSE AFTER FILLING THE j CONTAINER, THERE 15 NOT ENOUGH LIQUID LEFT TO FILL IT UP. (UNKNOWN YOLTAGE)=(SUM OF FULL MEASURING CONTAINERS) + (ERROR) 2*' 2"* 2"a 2"H MEASURED VOLUME =(o. I 0 I l ) = (|*2~,+Dx2*2+ I * I 3 +1 x Z~*) V, REF = (0.5+ O +0.125+0.O62 5-) V«F = 0.6875 VREF ERROR = 0.0O2.5 VREF The accuracy of the above r e s u l t s i s dependent on: 1. - The accuracy of the standard volume chosen as V r e f » 2, - The number of a v a i l a b l e measuring containers. One possible c i r c u i t implementation, f o r the above analogy, i s given below, where the volumes are replaced by voltages, and the measuring containers are replaced by the r e s u l t s of a comparator, which decides whether a subtraction of voltages should or should not take place. -202- 8 VRKF I Z J SU8TRACT0R 2" 21 2'3 I : I SUBTRACTOR i ~- 1 SUBTRACTOR F 0 R A ( A ^ E ) U T W } M " S U R E 0 V O L T A G E = (0. I 0 l ) V t o = 0.625vW > ERROR = 0.0625 V W F 2*' 2"*2"3 2"4 The accuracy of the results i n the above circuit i s dependent on: 1. - The accuracy of the standard voltage chosen as v ^. 2. - The number of available comparators and subtractors. VOLTAGE REFERENCES Prom the above considerations, i t can be seen that the accuracy of the reference voltage i s a c r i t i c a l factor in determining the absolute accuracy of i t s DAC or ADC systems. In electronic circuits, this reference voltage i s usually provided by specially designed zener diode circuits. These circuits are temperature compensated to prevent drift or fluctuation due to changes i n temperature. A guide for reference voltage circuits i s usually supplied by most manufacturers. One of these guides i s provided next and i s from the "National Semiconductor Linear Data Book". -203- 268 ADC - LADDER TYPE This method of measurement consists of balancing the desired Analog Input in a similar way to the process used to weigh an object on a chemical or apothecary balance. The sample object to be weighed i s placed on one side. It i s counterbalanced by the heaviest reference weight f i r s t . If i t i s heavier than the sample object, i t gets replaced by the next weight or weights, and the procedure i s repeated u n t i l the smallest weight has been tried and the closest match occurs. A similar process i s used in the ADC0800 Analog to Digital Converter from National Semiconductors. Its specification sheets are included here and were taken from the "National Data Acquisition Book". SAI.Ii-L3 A 1 T D HOLD CIRCUITS 69 When measuring constant values of analog inputs, the time taken for measurement i s not important, and any ADC method w i l l do, see the figure below, where an integrator ADC generates the Analog Count: ANAL06 INPUT ANALOG COUNT However, when measuring rapidly changing analog signals, the integrator ADC may give an erroneous answer, see the figure below: ANALOG SIGNAL ANALOG COUNT The value of the analog input i s known at the time t^, when the analog count equals the analog signal, but not at the time t Q , when the read-out i s desired. A solution to this problem i s to use a faster converter, such as the successive approximation type. Another general solution i s the use of "Sample and Hold" c i r c u i t s . These circuits are used to measure rapidly changing voltages at specified intervals of time. A sample voltage i s taken from those rapidly -205- 270 varying quantities by charging a capacitor, and then obtaining the dig i t a l equivalent of the voltage across the capacitor terminals. The advantage of these circuits i s that taking the sample usually takes less time than carrying out the A-D conversion. Thus, one can know the value of the voltage very close to the time the sample was obtained. An analogy for the above procedure occurs when one considers making the chemical analysis of river water. Chemical analyses usually include several tests and may not be done on the spot. Therefore, so long as a careful record i s kept of the time at which the samples are removed, then the analysis can take as long as necessary. For very high speed applications, even the successive approximation methods require "sample and hold" ci r c u i t s . Sample and Hold ci r c u i t s are available in integrated circuit form. For u l t r a high speed applications, the sample and hold circuits include a tracking function, where the sampling capacitor follows the voltage variations of the analog signal at a l l times. This way, the voltage across the sampling capacitor terminals i s readily available for measurement when required, without having to wait for i t to charge from a 0 V discharged condition up to the value of the analog input. This tracking function i s analogous to tailing the photograph of a fast moving object by following i t s motion with the camera finder. The object w i l l appear stationary during the lens aperture time, and i t s picture w i l l not be blurred. See the attached data specifications for an Ultra High Speed Sample/Track-and-Hold Amplifier, manufactured by Analog Devices, Inc. -206- POWER SOURCES FOR DIGITAL CIRCUITS Electronic circuits are powered by two kinds of voltage source. One of til em, such as u t i l i t y outlets, supply an alternating voltage (AC), whereas other sources, such as batteries, supply a constant voltage (DC). For a given c i r c u i t , i t s different functional blocks may have different DC voltage requirements. As an example, most TTL logic circuits discussed in this book require +5 V, whereas linear systems, like those used for summing and comparing, require from -3 V to ^18 V, see supply voltage requirements for the operational amplifieryWA741. '.Then different voltage levels are needed, those voltage levels can be obtained from different sources. This i s an expensive procedure, and a more practical approach i s to obtain them from a single source. The u t i l i t y outlet supplies AC voltages. These voltages are easy to step up or to step down, by the use of transformers. The resulting AC voltage levels are then rectified and f i l t e r e d to yield the required constant DC voltage levels. A given DC voltage level can then be stepped down using voltage dividers, to obtain as many different levels as needed. However, v/hen the original main source of energy i s a battery, while i t s voltage may be stepped down easily, the process of stepping this same voltage up i s not that simple. Transformers cannot be used to directly step up DC voltages, because transforemers only operate v/ith dynamic voltage changes at their input in order to induce AC voltages at their output. The special circuits used to step up DC voltages are known as voltage converters. These circuits may use transformers and/or capacitors to raise the supply DC voltage level. -207- 272 Basically, voltage converters produce an AG voltage from a given DC input. Then, this AC voltage i s stepped up by: a) Using a transformer, where the resulting AC voltage levels are then rectified and f i l t e r e d , or b) Using the nC voltage to act on a set of electronic switches to charge or discharge capacitors, so that a voltage doubling effect can take place. i A +5 V POWEB SUPPLY A useful +5 V power supply, adequate for most of the applications suggested in this book, i s described below. It operates from the u t i l i t y AC voltage. TRANSFORMER Above power supply includes a transformer made by Hammond, catalog number 166F6, with a transformation ratio of 115 V / 6 . 3 V. It must be noted that transformers are made by many manufacturers to suit a large variety of applications. Manufacturer's catalogs permit the selection of the transformer that i s most suitable for a particular application. A typical specification sheet i s included at the end of this section, which also l i s t s the above transformer. Y/hen the primary of this transformer i s connected to the AC power outlet, i t steps the 115 V (?I!S) down into a 6.3 V (RMS). The secondary voltage, seen on an oscilloscope, appears as follows: -Z08- 273 * t i "* T = 16.6 mi > f - - f = 6 0 H € RECTIFIER A bridge r e c t i f i e r circuit w i l l provide f u l l wave rectification of the above input. The r e c t i f i e r bridge can be made by connecting four diodes as shown below. AT Notice that conventional current flow i s considered in the above figure. Also notice that the graphic symbol for a diode i s derived from this conventional flow. Its symbol i s an arrowhead pointing in the direction of conventional flow. It also indicates that no conventional current flows against i t s arrowhead. -209- 274 In order to observe the rect i f i e d output, a du:~:ray load R ^ = 2.2 k l l with 2 V / rating may be connected across the r e c t i f i e r output. The corresponding oscilloscope display i s as follows: V E P = 6.9 V I 1 0 | - T = l6.6ws *-j Above bridge may be replaced by one already assembled in a Dual-In- Line package, such as the one available from Varo Semiconductor, Inc., catalog number VT,I18. This package offers the advantage of reduced space and i t i s also easy to mount on a strip bread board, of the kind recommended for the assembly of experimental circuits in this book. See the technical specifications sheet for this 1 Amp Dual-In-Line bridge, at the end of this section. FILTER The resulting output from a r e c t i f i e r i s a DC pulsating wave. This wave must be f i l t e r e d , in order to make the output a constant EC value. A good size capacitor, such as a 1000 unit, w i l l produce a f a i r l y smooth output, except for some small amount of voltage ripple. This resulting voltage ripple can be nearly eliminated with the use of a voltage regulator, described next. Notice that the property associated with capacitors i s called capacitance, and i t i s the property that opposes changes of voltage. This property i s analogous to what happens in a reservoir tank, where the drain pipe does not follow the fluctuations that occur in the main pipe used to f i l l i t . -2/0- 275 115 V, + RECTIFIER BRIDGE + s RL 2.2 KTL VOLTAGE JULATOH3 Voltage regulators are circuits that control the value of their output voltage, by comparing i t with an accurate internally generated reference value. Their input voltage must be greater than the controlled output voltage. Their principle of operation i s described next, making reference to the following block diagram. (UNREGULATED) R E F E R E N C E VOLTAGE COMPARATOR (REGULATED) Ic -HI- A sample of the output voltage i s obtained from resistors R and a R, , which are connected across the load. By voltage divider action, the voltage 7^, across R̂ , i s proportional to the load voltage V^. Above voltage V, i s then compared with the reference value from a zener diode. The result of this comparison i s used to control the current through R , and in this way, the load current I T . R may be a transistor c Jj c ci r c u i t , and a change of i t s biasing results in a change in the current through i t . When 7 T tries to drop due to either a drop in 7. or an increase in I , because of additional load requirements, then the comparator w i l l cause R i> c to decrease, restoring 7^ to i t s regulated value. Also, when 7 T rises, due to either a rise i n 7. or a decrease in l i in 1^, because of a reduction in load requirements, then the comparator w i l l cause R to increase, which once again restores 7 T to i t s regulated value. This regulating action effectively causes the regulator to act as a f i l t e r . 7oltage regulators are commercially available as integrated ci r c u i t s . For most of the examples in this book, where the 7 c c requirements are +5 7, the voltage regulator/,A73"05UC was found satisfactory, since i t can deliver up to 500 mA of output current, i . e.' 200 mA above the output current of the transformer 166F6. When larger amounts of current are required, i t i s recommended to consult the manufacturer's data sheets. For your convenience, the technical specifications for the/'A78M05UC have been included at the end of this section. -212- 277 The complete power supply i s shown below. The 0.1 f$ capacitor has been added across the output to by-pass any high frequency ripple that may be present. I I 5 V / 6.3 V II5V, RMS 6.3V, RMS I 6 6 F 6 TRANSFORMER ( A DUAL-IN-LINE BRIDGE VM 18 3 TERMINAL VOLTAGE REGULATOR /A78M0ETUC (UNREGULATED) •9 + :0.1/F 5 V (REGULATED) -6 - -215- 278 VOLT AG-ID CONVERTERS Above +? V power supply i s very u s e f u l f o r most d i g i t a l f u n c t i o n s . However, i n systems where ana log f u n c t i o n s are used, such as DAC's and ADC ' s , cormonly found i n Data A c q u i s i t i o n Systems, a -5 V supply should a l s o he made a v a i l a b l e . Rather than u s i ng two separate s u p p l i e s , the -5 V v o l t age may be de r i v ed from the e x i s t i n g + 5 V source, u s i ng a vo l t age conve r te r . The ICL 7660 vo l t age conve r t e r i s commerc ia l l y a v a i l a b l e from I n t e r s i l , I n c . . I t generates an AC vo l tage tha t a c t s on e l e c t r o n i c sw i tches . These switches charge o r d i scharge c a p a c i t o r s and produce a vo l t a ge doub l ing e f f e c t . The t e c h n i c a l s p e c i f i c a t i o n s f o r the ICL 7660, which comes i n a d u a l - i n - l i n e package, are i n c l uded at the end of t h i s s e c t i o n . Th i s v o l t a ge conve r t e r may be used to b i a s the yfA741 o p e r a t i o n a l a m p l i f i e r s used i n the Analog to D i g i t a l Conver te r s d i scussed i n t h i s book. The th ree b i a s s upp l i e s used f o r .the above ADC's are represented i n the f o l l o w i n g b lock diagram. These s upp l i e s a re : a 6 V source f o r d i g i t a l c i r c u i t s , and two 9 V sources f o r the analog components ( y M A 7 4 l ) . o +V C C K6V) DIGITAL REQUIREMENTS A D C 'A74I 9 V • g V -2J4- 279 The above three bias supplies may be replaced by a single one (+V ), and an ICL 7600 Voltage Converter. The peripheral components and connections for the voltage converter are shown below: 9 + V c c ( 6 V) DIGITAL REQUIREMENTS ADC / A 7 4 I -Vc< + Vce ICL 7660 NCHTf.-THE MAXIMUM RATING OF THE I C L 7 6 6 0 (PIN 8 ) IS +I0.5V / I U| [3 ] |4 IN4005 -Kh - o - V c c ^ + I0/«F Notice that i n the sections for DAC's and ADC's, the operational amplifiers were biased v/ith -9 V supply voltages. The DAC's were designed to yield maximum output values, so that the staircase waveforms could be observed clearly v/ith a Volt-Ohmmeter. The following two basic considerations were met, applicable to operational amplifiers in the Summing Mode: 1.- Its input values should not exceed the supply voltage. The right choice of resistors in the resistive ladder attenuator was used to meet this requirement. -21S- 280 2.- The output voltage should not exceed the supply value. This requirement was achieved by choosing the right value of feed- back resistors. Since the bias for the operational amplifiers w i l l be reduced to ^6 V, we must make sure that above requirements are s t i l l met. Voltages e_, e~, e^ and e. when taken from the true outputs of a 7490 BCD counter, are approximately equal to 4 V. These voltages are applied to the summing amplifier as shown below: 82 KA vVWV 1 -0 O - -VWWA :c o- 82 Ka •vwww ' B O - 82 K 0. -rVVVW - A O BlKd -wwwv The maximum input to the operational amplifier i s : = J-5__ +_i2_ + J A _ _ 4 , 4 . 4 . 4_ imax 2 4 8 16 ~ 2 4 8 1 6 3.75 V The above voltage i s less than the new supply voltage for the /*A741, ( i . e. -6 V), and condition (l) i s met. Regarding condition ( 2 ) , the output of the operational amplifier i s given by: *B ^ B / eD eC in 16 ; '..here P L , was chosen to be twice the value of R . ( R = 39 left), •sB i n v m so that a larger output could be measured more easily on a Volt-Ohmmeter. - 2 ( 6 - 281 Y/hen a l l the input voltages are present: m This output voltage now exceeds the new supply values of -6 V, and condition (2) i s HOT satisfied. If the ci r c u i t i s not modified, i t s operation w i l l result in the loss of the higher counts. 7/hen the output voltage attempts to exceed the supply bias, the inputs to the operational amplifier are no longer vi r t u a l grounds. A satisfactory solution i s to reduce the output voltage by reducing the value of the feedback resistor. For H. = 39 k/L, in ' a) If It™ i s made to be 39 k A then: e ~ -3.75 V TB o max b) If IL,_ i s made to be 22 kfLthen: e = -1.875 V TB o max Above steps reduce the output voltage considerably and thus are not easily measured with a Volt-Ohmmeter, but they are readily observed on an oscilloscope. -2 I7- THE INTERFACE OF ELECTRONIC SYSTEMS The term INTERFACE refers to the interconnection between two pieces of equipment having different functions. In digital systems, interfacing i s used to: a) Collect and transmit information from equipment external to a d i g i t a l system, into this l a t t e r system. This operation i s referred to as DATA ACQUISITION. Data from the external equipment may be in analog form, in which case, i t must be converted f i r s t into i t s - d i g i t a l equivalent. ADC's are used to perform this conversion. b) Send messages to external devices, in order to alter the operation of other systems. This i s a CONTROL FUNCTION that often requires d i g i t a l data to be converted into i t s analog, equivalent. When this conversion i s required, a DAC must be used. Digital systems that include a Data Acquisition System(BAS), as well as a Control System, are used to monitor, analyze and control real time events, such as: Continuous Processes in Manufacturing, Flight Control Systems, Navigation Systems, Security and Alarm Systems, Fire Control Systems, Machine Controls, etc. This section considers the development of an interface system, to control illumination devices. The state of these illumination devices w i l l be defined by the logical state of a d i g i t a l c i r c u i t . The procedures outlined here may be made extensive to other similar applications. - 2 1 8 - 283 II\?5EFACIKG A DIGITAL CIRCUIT TO Al; AC, 120 V DEVICE This interfacing consists of using the state of a JK master/slave fl i p flop to control the ON-OFF condition of a 120 V lamp. The lamp is powered by a 120 V, 60 Hz system, whereas the f l i p flop is powered by a 5 V DC supply. The interface circuit will interconnect these two electrical systems. The output from a f l i p flop has very low current drive, therefore a simple approach is to use the logical "0" or logical "1" from the f l i p flop to drive a 2H2222 transistor. This transistor will provide the necessary current to drive other electronic switching devices, such as Silicon Controlled Rectifier Diodes (SCR), or Triacs, as well as Electromechanical relays. As an example of driving requirements, consider the following typical devices: a) An SCR GE-X1 requires a triggering current of 15 to 25 mA at 1.2 to 2.5 V. b) A Triac Q2004L4 requires a triggering current of 25 mA at 2.5 V. c) A small electromechanical relay, such as the R10-E1-Y2/V52, requires an energizing current of 0.115 A at 6 V. This current is calculated, from the appropriate technical specifications, as follows: The technical specification sheets for the SCR GE-X1, for the Triac Q2004L4 and for the relay R10-E1-Y2/V52, are included at the end of this section. -2/9- 2 8 4 ELECTRONIC SWITCHING DEVICES A triggered SCR w i l l act as a regular diode, conducting i n only one d i r e c t i o n . '.Then the SCR i s connected i n se r i e s v/ith a 60 Hz system, i t w i l l conduct only on every other a l t e r n a t i o n . Therefore, a lamp i n se r i e s with the SCR w i l l glow on every other a l t e r n a t i o n and w i l l produce only h a l f the amount of l i g h t compared with a d i r e c t connection to the power main. A T r i a c i s a back to back connection of two 3CR's. When connected i n s e r i e s with a lamp, t h i s feature enables the lamp to be operated at f u l l brightness. Each one of these two devices has i t s advantage as well as i t s shortcoming. The SCR w i l l prolong the l i f e - t i m e of the lamp, by allowing the lamp to operate only at h a l f brightness, whereas the Tr i a c permits f u l l brightness but a shorter l i f e - t i m e . The power requirements to t r i g g e r an SCR are s i m i l a r to those of a T r i a c . Both require low current and low voltage to be triggered. The f o l l o w i n g c i r c u i t s c o n t r o l the OH-OEF c o n d i t i o n of external devices according to the state of a d i g i t a l f l i p f l o p . They use e i t h e r one of the above e l e c t r o n i c switching devices. The f o l l o w i n g precautions must be observed when assembling these c i r c u i t s . CAUTION.- Because the d i g i t a l system and the power main share a common connection, the following precautions must be taken: 1 . - A p o l a r i z e d plug must be used to ensure that the ground of the l i n e i s always connected to the common of the c i r c u i t . -220- 285 POLARISED PLUG UTILITY OUTLET 2. - The casing f o r the c i r c u i t must be made of non-conducting materials, such as p l a s t i c or wood, and the c i r c u i t r y must not be allowed to touch the casing. 3. - An i s o l a t i o n transformer should be used i f t e s t s are to be made on the c i r c u i t , such as osc i l l o s c o p e measurements. CO;.J,DiI COLLECTOR DRIVER This c i r c u i t uses a t r a n s i s t o r 2112222to drive the gate of an SCR. The t r a n s i s t o r i s connected i n the Common C o l l e c t o r mode, therefore, the signals into i t s base are not inverted when taken out from i t s emitter. Consequently, when the Q output from the f l i p f l o p i s a l o g i c a l HI, the lamp i s switched Oil, and the same lamp i s switched OEP when the Q output becomes a LO. Q + V c c -221- 286 The p h y s i c a l configuration of the GE-X1 i s the following: - — A N O D E GATE — 4J — - CATHODE Note.- The above SCR must be mounted on a Heat Sink i n order to d i s s i p a t e the generated heat of the device. COMMON ELTTTBR DRIVER '.Tnen i n v e r s i o n of the d i g i t a l s i g n a l i s desired, the 2N2222 t r a n s i s t o r may be connected i n the Common Emitter Configuration, as shown below. The signals into the base of the t r a n s i s t o r w i l l now be inverted when taken out from i t s c o l l e c t o r . Thus, the load w i l l be switched ON whenever the Q output from the f l i p f l o p i s a . l o g i c a l LO, and the same load w i l l be switched ORE when the Q output becomes a l o g i c a l HI. In t h i s c i r c u i t , a T r i a c performs the e l e c t r o n i c switching function. o+Vcc Q 1 F F iwn ANODE (MT2) CONVENIENCE INDICATOR LED \ \ (OPTIONAL) -222- 287 Phe physical configuration of the Triac i s the following: CATHODE MTI A N O D E M T 2 GATE Hote.- The above Triac must also be mounted on a Heat Sink to dissipate the generated heat. Caution.- The leads of the Triac must be insulated to prevent possible shorts. OPTOISOLATORS Optoisolators may be used to isolate the d i g i t a l system from the pov/er l i n e . The control pulses from the dig i t a l system are then transferred through a beam of light into the controlled system. See the technical specification sheet, at the end of this section, for a GENERAL IESTPJJIuEET Optoisolator, catalog number 611138, 6ITT39. Optoisolators protect the d i g i t a l system from possible power overloads in the 120 V li n e . However, two separate power supplies are required, and one of them s t i l l has to share a common connection with the pov/er main. -223- 288 3L3G TKOI.EC IIAHIC AL RELAYS Relay contacts close by electromagnetic induction, and their coils may be completely isolated from the power main. Gee the following ci r c u i t diagram: CONTROL PULSE Zl Ktt -VWW 2N2222 » WHEN THIS PULSE IS HI,THE TRANSISTOR CONDUCTS AND THE COIL DE ENERGIZES. essential: Some of the shortcomings for electromechanical relays are: a) They require more power to become energized than the power used.by electronic switching devices. b) Because of their moving components, they lack the fast switching capabilities needed in high frequency applications. c) They are more expensive than electronic switches. They have the following advantages when rapid switching i s not a) V.hen activated, their contacts conduct AC signals during a f u l l cycle, without the loss of alternations. b) Because their contacts are not connected elec t r i c a l l y to their c o i l , they do not require too many isolation precautions. An example of a practical application of relays i s in Digital Alarm Clocks. The c o i l i s connected to the Digital System, and the contacts may be connected i n series with the power line, to activate a radio or a -224- 289 television set. Thus, the control pulses generated in the clock may be used to: a) Automatically activate a radio or TV set at a predefined time, or b) Automatically disconnect the above appliances, after a predefined period of operation. VARIABLE SPEED FLASHER The following circuit may be used to turn on or to turn off a lamp or a string of lamps, such as those used to decorate Christmas trees. It consists of a 555 timer with a rheostat to manually control i t s frequency of oscillation. The interfacing circuit i s one of those discussed in this section. The same precautions previously mentioned for circuits that share a common connection with the power main are applicable, and must be observed. 2N2222 9 V ' - ^ VOLTAGE DROPPING RESISTOR RADIO BATTERY ANODE MTZ 25: 7 GATE q2004L4 43011 i CATHODE MTI -MLOAD 120 V 60 H z -225- A l 2 9 0 COLOUR CODE FOR RESISTORS CONSIDER A RESISTOR WITH COLOUR BANDS AS SHOWN BELOW SILVER ORANQEI B L U E G R E E N f ACM BAND INDICATES f FIRST SECOND NIUM&EJ? 4 SIGNIFICANT SIGNIFICANT OF TOLERANCE FIGURE FIGURE Z E R O E S THE EQUIVALENT DIGIT FOR EACH COLOUR IS: (SfE TABLE Ba0W) 0 0 0 1 1 0 % T H E R E F O R , TH-E R E S I S T O R S H O W N A B O V E H A S A N O H I W C R E S I S T A N C E O F ; 5b 0 0 0 n 1 1 0 % . COLOUR CODE TABLE C O L O U R D I G I T BLACK 0 B R O W M 1 RED 2 ORANGE 3 MELLOW A GjREEN 5 B L U E 6 P U R P L E 7 G R A Y 8 WHITE 9 TOLERANCE T A 6 L E COLOUR PERCENT NONE i 2 0 ° / o SILVER i JO % GOLD 1 5 V o RED ± 2 % -226- 291 MAKING A PC BOARD LAY OUT Do the lay out on Mylar. Use the matted side to apply S l i t Tape, Donut pads, IC DIP Peed Through Leads, Lettraset Letters, etc. See Technical Manual & Catalog 106 (1978). ° aiQisisieisio e.g. IC DIP Peed Through Leads BjBJBIBIBIM 6 ? 8 1 ( p g # 3 2 ) S l i t Tape: 0.015" x 20 yds 201-015-11 (pg.57) 0.040" x 20 yds ' 201-040-11 (pg.57) 0.050" x 20 yds 201-050-11 (pg.57) Donut Pad (0.093") D1 37 (pg.60) Donut Pad (0.100") 9 D101 (pg.60) MULTIPLE LAYOUTS Multiple Layouts can be ordered from places l i k e : B l a i r Behnsen/ 835 Oambie / ph. 684-6581 GDL Graphics / c/o Larry Wells / ph. 685-2358 Make CUT MARKS on your original tape positive, so that the multiple layouts just overlap on those cut marks. CUT MARKS ^ n TAPE POSITIVE " Multiple layouts are made on sheets v/ith the following standard dimensions 10" x 12" ; 8" x 10" ; 14" x 17" Reproduction shops v / i l l provide both, a Positive and a Negative of the reproduced tape positive. Note.- For etching purposes, i t i s advisable to use only the Positive Slide, since i t c a l l s for chemicals that are not flamable and which do not have a bad smell. -227- 292 S e n s i t i z i n g the Popper Covered Board a) Cleaning the Board.- The board must be clean. Cleaning i s done using "SCRUB CLEM POWDER". This powder i s applied with a sponge and water i n the same way one uses any other cleaning powder. The scrubbing on the board i s done i n one d i r e c t i o n only, u n t i l a l l o x i d i z i n g marks are removed. A clean board loses some of i t s copper glow but looks very uniform i n colour. Make sure the board i s properly dry before proceeding to the next step. b) Applying Photo Resist (Shipley f o r P o s i t i v e S l i d e s ) . - Buy a DeCoupage Brush and attach to the cover of a dark glass j a r . The brush should reach the bottom of the j a r . SCREW D A R K G L A S S L J i S P O N G E A D O S T A P L E S , S INCE T H / N N E R W I L L S O F T E N T H E ORIGINAL. G L U E - Combine f- parts of Resist to i part of Thinner. Using the brush, apply r e s i s t on clean board h o r i z o n t a l l y ( T) and then v e r t i c a l l y (III). Let the r e s i s t to completely dry by r e s t i n g the board on a paper towel f o r 15 min to -g- hour. The use of a heat gun i s recommended, f o r i t d r i e s as i t cures. An oven may be used, v/hen set at 1 5 0 ° f o r hour, however, the oven w i l l be l e f t smelling pretty bad. -229 - 293 A hot drier may also be used. There i s no need to have a dark room during this step. Note.- Due to the action of gravity, the resist w i l l drip down, leaving the upper portion with a thinner cover of resist than the lower portion. This w i l l cause the upper part to expose more rapidly and to develop quicker than the bottom portion. To prevent above discrepancy in thicknesses, a turntable may be used to dry the board. 4.- EXPOSURE a) Use four equally spaced lamps (F15T8BL) inside a glass covered box. MYLAR LAY OUT ^ — UPSIDE DOWN 6LASS COVER LIGHT BOX F I 5 T 8 B L LAMBS ^ CAUTION.- These lamps produce short-wave ultraviolet light. At these frequencies, damage to unprotected eyes i s permanent. Avoid looking at these lamps when they are l i t . - 2 2 9 - 294 b) Place the mylar layout upside down c) Place the copper board on top with the resist treated side facing the light box. d) Expose to light. Different times may be tried. About 1-g minutes i s an expected average. Optimum time can be found by t r i a l . 5. - DEVELOPMENT Use Shipley Developer. Mix one part of this developer to eight parts of water. Wash and Dry. Development comes as a negative. The exposed portions turn out purple and the unexposed parts (circuit lines) come out red. Note.- If the board was not exposed long enough, the lines w i l l wash out. 6. - ETCHING Use warm f e r r i c chloride, heated to 130°F. A double tray may be used to warm the fer r i c chloride. Note.- Cold PeCl takes longer to etch a board, up to hour, instead of Caution.- Use rubber gloves and a laboratory coat. Ferric Chloride stains do not wash out. -230- 295 Clean etching can be obtained by using the a i r bubbles from two a i r tubes and an a i r pump. The tubes and pump may be acquired at a retailer shop of acquarium supplies. BOARD TO B E E T C H E D Make sure the board i s at an inclined plane, so that the bubbles can wash the etched copper particles as they move upwards. Wipe excess copper on a sink to prevent the FeCl from getting too dirty. 7.- FINISHING THE PRINTED CIRCUIT BOARD a) Wash the Printed Circuit Board on a sink. b) Dry i t . c) D r i l l holes into i t . Use a: Dremel Mototool 381 Dremel Stand 210 D r i l l s #55 to #60 (for most holes) V/hen the hole i s positioned, the dremel stand pushes the board up against the rotating d r i l l . -231- 296 THEVEI7IN' S THEOREM This theorem states that a network with sources may be replaced by an equivalent source E^. in series with an equivalent resistor R^n» NETWORK WITH SOURCES -o °~ - O b MM -TH T - O O. -o b The equivalent circuit w i l l perform just as the original one. Therefore, a load placed between points "a" and "b" w i l l have the same voltages and currents regardless of the circuit that drives i t , i . e. whether driven by the original circuit or by i t s equivalent. The equivalent source E ^ and the equivalent resistor R^n are defined as follows: E m t J = Open Circuit Voltage between joints "a" and "b". It can be measured or calculated. R^ = Resistance between points "a" and "b", provided a l l the active sources of the original network are removed. This means that a l l the voltage sources must be short circuited, and a l l the current sources must be open circuited. R. can i n be measured or calculated. The advantages of the equivalent circuit are that i t f a c i l i t a t e s the calculation of voltages and currents on any given load, by replacing complex looking configurations with a single voltage source in series with a single resistor. -232- 297 KAIvIPLE 1.- Determine the equivalent circuit for the following network: (See section on Digital to Analog Conversion). e 4 2 R MAW- ZR -wvw- 2 R 2R •VWVW- :R ! R I • 2R I I SOLUTION.- The dashed section can be reduced by combining resistors i n parallel and.series: e 4 2R 0 _o A. 2R Now we apply Thevenin's Theorem. a) The open cir c u i t voltage, across points "a" and "b" V — T (9V\ — "TH " x  K C x > ~ 2R + 2E ^ 2 ?^ = "4R -  2 R = "IT b) The resistance R. between points "a" and "b", when the voltage source i s shorted: 2 R -vWWr :2R <F= RH,=———- = R N £R t 2 R -2 S3- 298 Therefore, the equivalent circuit i s : § 2 2 R -O CL EXAMPLE 2.- Determine the equivalent circuit of the following network. (See section on Digital to Analog Conversion) 2R JVW 2R 2 R P. 1 *2R I i i i SOLUTION.- The dashed section can be reduced by combining resistors i n parall e l and series: a The equivalent c i r c u i t between points "a" and "b" i s easier to calculate, i f we know the equivalent circuit between points "c" and "d". This means we can apply Thevenin's Theorem to obtain intermediate results, before the determination of the system's -234- 299 overall equivalent. The cir c u i t between points "c" and "d", shown above i n dashed lines i s : d 2R Applying Thevenin 1s Theorem to above c i r c u i t : a) The open circuit voltage across points "c" and "d" i s : 0 Q Q E 1 = I 1 (2^0 = (21.) — (2l) - TH x K<L"' 2R + 2R K A > ~ 4R K<L*' ~ 2 b) The resistance R. ' between points "c" and "d" when e„ i s xn j) shorted: 2R 2R -o c Riw' = R The ci r c u i t between points "c" and "d" becomes: C 0 R -235- Therefore, incorporating above partial equivalent c i r c u i t into our overall c i r c u i t : 2R -vvvw- i i z R -VWVWr O b Applying Thevenin's Theorem once more: c) The open circuit voltage across points "a" and "b" i s : ETH = 1 ^ = R + R + 2R ( 2 R) = 4 e, d) The resistance R. between points "a" and "b" when —r- i s xn 4 shorted: M 2R -MMW- -wvvw—1 c ^— Rw- aR(R+R~) _ 2R<R+R") Therefore, the total equivalent ci r c u i t becomes: -4 - 1 + R -vwvw- CK I : ob The voltage across points "a" and "b" can be calculated directly by OHM'S LAW MATRIX, see the corresponding appendix. 301 EXAI.IPLE 3-- Determine the equivalent circuit for the following network. (See the section on the BCD Ladder Attenuator). I -vVWWV- - V V W V I A - Rc Rt SOLUTION.- The dashed section can be reduced using the basic ladder network relationship: R.H R+ = „ V + R t ii.+B. c t s Then, above circuit becomes: eR R 5 —^r 1 WWvW How we apply Thevenin 1s Theorem. a) The open circuit voltage, across points "a" and "b": R. ETH = 1 ( V = 6H R+ + R t s b) The resistance R. between points "a" and "b", when the ' i n voltage source i s shorted: vwvvv Rt RIM - RtRs ' N ' R t * R s -237- Therefore, the equivalent circuit i s : + 302 -o o- EXAKPLE 4-.- Determine the equivalent circuit for the following network: (See the section on the BCD Ladder Attenuator). -VVVVW- -O CL R s -wwwv- -WVYVW- Rc SOLUTION.- Using the basic ladder network relationship (see previous example), the dashed portion reduces to R̂ , and above circuit simplifies into the following one: Rs •vVVVVVv- Rc •wWWMr Rt -ob before calculating the equivalent c i r c u i t , between points "a" and "b", we can reduce above dashed section by an intermediate application of Thevenin's Theorem. -239- 303 Therefore, considering only the dashed section, between points "c" and "d": a) The open cir c u i t voltage, across points "c" and "d" i s : V = I ' ( V = T T F - ^ ) t s b) The resistance R." ' between points "c" and "d", when e m ' xn ^ ' T i s shorted: R t Rs Therefore, the cir c u i t between points "c" and "d" becomes d Q C 0 f| MAAtf - 2 3 9 - 304 Incorporating above ci r c u i t into our overall configuration: b , d •VWWWr l?t | Rt Rs Rt+Rs 1 Rt + Rs _ r H L + _ J (MMA/V- Rt Using Thevenin's Theorem once more on above circ u i t : c) The oioen circuit voltage across points "a" and "b" i s R t T R,+R R. V - T (v ^ t s _ e "t s TH _ X ^ s ; _ R̂  + R s ~ T R.+R R̂  + R d) The resistance R. between points "a" and "b" when the source ' i n R, ' T R t + R s i s shorted i s : 6= R Therefore, the total equivalent circuit becomes: <h± i M W — a -240- SOLUTION 0? CIRCUITS USING- THE OHM'S LAW MATRIX This method permits one to order the data of any ele c t r i c a l c i r c u i t into mathematically meaningful arrays. The resulting data arrays make up a matrix equation. I refer to this equation as the Ohm's Lav; Matrix. It i s another way of writing the simultaneous equations that describe a given el e c t r i c a l c i r c u i t . The Ohm's Law Matrix may be solved directly or i t may be rewritten f i r s t as a set of simultaneous equations. Any method to solve simultaneous equations may be used to solve for the unknowns. In the examples that follow the method of determinants i s employed. Due to the mechanical nature involved in the solution by determinants, any microprocessor or programmable pocket calculator may be advantageously used. The Ohm's Law Matrix i s made up of three arrays of data, i t s format looks lik e the regular Ohm1s Law: (R) (I) = ( E ) Where: ( R ) i s the array of the resistive data of a given c i r c u i t , (i) i s the array of the loop currents in that c i r c u i t . ( E ) i s the array of the voltage sources i n the c i r c u i t . The Ohm's Lav/ Matrix combines loop analysis techniques, Kirchhoff' Voltage and Current Laws, plus Ohm1s Law. Later on, i n this section, i t w i l l be shown how to derive the Ohm1s Law Matrix. However, f i r s t we w i l l show how to transpose el e c t r i c a l data into arrays and then solve for the unknowns. -24/- TRANSPOSITION OP ELECTRICAL DATA INTO THE OHM'S LAV/" L/IATRIX 306 Any electrical c i r c u i t , with one, two or more loops, can be solved using the Ohm's Law Matrix. Consider the two loop system shown below: SOLUTION 1. - Define the two loop currents as 1̂  and Ig, always in the clockwise direction. NOTE.- If any current or a l l currents happen to be assigned the wrong direction, their resulting numerical value w i l l be negative. This negative answer indicates that their direction needs to be reversed. 2. - The Ohm's Lav/ Matrix for two loops i s stated as follows: R 11 -R -R 21 R 22 h E E 2 V.here: a) R^ i s the total resistance in loop 1. Nor above example: E 11 = R 1 + S 3 Rgg i s the total resistance in loop 2. Por above example: Rgg — Bg + R̂ (-R^) or (-Rg^) i s the resistance common to both loops. Por above example: (-R12) = (-R21) = (-R3) -Z4Z- 307 1TOTE.- In the matrix equation, the resistance common to both loops i s always written as negative. This i s done to account for the direction of the loop currents through this element. Por one loop, the voltage due to one loop current w i l l be always positive, whereas for the other loop, i t w i l l be always negative, because the second loop current w i l l oppose the f i r s t one, (loop currents were defined to be CV/). b) The sign for sources and Eg i s defined as follows: It i s considered as positive, i f the corresponding loop current sees i t as a voltage rise, i . e. i f the current moves from the negative terminal to the positive terminal. Otherwise, i t i s considered as negative, because the loop current w i l l see i t as an effective voltage drop. Above Ohm's Lav/ Matrix can easily be converted into simultanous equations by manipulating the array terms as follows: R11 *1 " E12 1 2 ~ 31 - F L I + R I = E n21 x1 "22 2 2 4 . - The solutions for the unknowns, in above case 1̂  and Ig, can be obtained by several methods. The method of determinants i s used below. This method can be programmed into a microprocessor or a programmable pocket calculator. E 1 - R 12 22 R 11 l21 - R 12 R , 22 ( E 1 ) ( R 2 2 ) - ( E g ) ( - R 1 2 ) ( R 1 1 ) ( R 2 2 ) - ( - R 2 1 ) ( - R 1 2 ) -2^3- 308 X2 = R. 11 - R 21 R 11 -R 12 -R. 21 R. 22 ( R 1 1 ) ( E 2 ) - ( - R ^ ) ^ ) ( R 1 1 ) ( R 2 2 ) - ( - R 2 1 ) ( - R 1 2 ) 5.- Once the loop currents are known, then the currents through the common elements may be calculated. They w i l l be the difference of the loop currents that flow through the same common element. For above example, i f I^ i s considered moving downwards, i t w i l l be: EXAMPLE 1.- Determine the currents through each of the resistors R̂ , R2 and Rj in the-following c i r c u i t . R2-20iI SOLUTION 1. - Define the loop currents 1̂  and l 2 in the clockwise direction, and mark them on the circuit as shown above. 2. - For above ci r c u i t , i t s Ohm1 s Law Matrix i s : 10 + 15 -15 -15 15 + 20 h X 2 +6 -9 3.- The corresponding simultaneous equations are: 25 I, - 15 I 0 = + 6 -15 I i + 35 I . = - 9 -244- 4.- The solution by determinants i s : 309 X2 = 650 650 6 -15 -9 35 (6)(35) - (-9)(-15) 75 25 -15 (25)(35) - ( -15X -15) 650 -15 35 25 6 -15 -9 (25)(-9) - (-15)(6) -135 =+ 0.115 A 650 = - 0.208 A 5.- Prom above results: I 3 = I 1 - I 2 = + 0.115 - (-0.208) = 0.323 A Notice that Ig i s negative. This means that the direction of Ig i s opposite to the one shown on above c i r c u i t . U.IPLE 2.- Determine the voltage across points " a " and "b" in the next c i r c u i t . Notice that this voltage was calculated by Thevenin's Theorem in the corresponding appendix. -Z4S- 310 SOLUTION Define the loop currents I 1 and I 2 in the clockwise direction, and mark them on the circuit as already done above. 2.- The Ohm's Law Matrix i s : 5R -2R -2R 4R h X2 - e„ 3. - Above matrix may be rewritten as a set of simultaneous equations: (5R) I 1 - (2R) I 2 = - e 3 (-2R) I 1 + (4R) I 2 = e 3 4. - While solving for the unknowns by determinants, we can calculate the denominator determinant f i r s t : A = 5R -2R -2R 4R 2 2 2 = 20 R - 4 R = 16 R The loop currents 1̂  and I 2 are calculated next: I, = -e- -2R 4R 16R -4Re~ + 2Re5 16R -2Re_ 16R 8R I„ = 5R -2R -e. 16R 5Re, - 2Re_ 3 3_ 16R2 3Re_ 16R 16R 5.- Therefore: ab R 2R w x1 + K ' - J ±2 2e^ 3B, e3 , 3 e 3 8 8 8 -Z46- 311 OHM' 3 LA'.V MATRIX POE A THREE LOOP SYSTEM Consider the three loop circuit shown below. Assume that we want to know the expression for the voltage between the points "a" and "b". -www SOLUTION R 4 -vWW\A- 1.- Define the looo currents I 1 5 I 0 and I„ i n the clockwise direction as 1 2 -j shown above. 2.- Above system i s described by the general Ohm's Law Matrix: 13 p -'11 -R 1 2 -R •p il21 R 2 2 -R - R31 "R32 R 25 33 E 1 Where: R^ represents the total resistance in loop 1 R 2 2 represents the total resistance i n loop 2 R^3 represents the total resistance in loop 3 (-R 2̂) or (-R^) represents the resistance common to loops 1 and 2 (-R^) or (-R^) represents the resistance common to loops 1 and 3 (-R23) or (-R 2̂) represents the resistance common to loops 2 and 3 - 2 4 7 - 312 E.| represents cne algeoraic sum of the voltage sources in loop 1 . E 2 represents the algebraic sum of the voltage sources in loop 2 . E., represents the algebraic sum of the voltage sources i n loop 3 . Transposing the ele c t r i c a l data from above circuit into the Ohm's Law Matrix yields: N / N R 1 + H 2 + R 4 " R 2 h + E " E 2 R 2 + R 3 + R l y I 0 R 4 + \  + E 5 h 0 3 . - If desired, we can write the corresponding simultaneous equations: -H2 I, 4 3 ( R . , + R 2 + H4) I 1 - R 2 I 1 + ( R 2 + R 3 + R J P I 2 - - R J J I 2 + ( R 4 + R J J + R 5 ) I i.i 3 " R 4 Z1 + E 0 0 Above l i t e r a l values may be substituted determinants, given below: R n - R 1 2 - R 1 3 A = - R 2 1 R 2 2 - R 2 3 = - R 3 1 " R 3 2 R 3 3 = aRu)(R22)(R.^3) + ( - R 1 2 ) ( - R 2 3 ) ( - R 3 1 ) + ( - R 1 3 ) ( - R 2 1 ) ( - R 3 2 ) ) - - ( ( - R 3 1 ) ( R 2 2 ) ( - R 1 3 ) + ( - R 3 2 ) ( - R 2 3 ) ( R n ) + ( x R 3 3 ) ( - R 2 1 ) ( - R l 2 ) ) E 1 - R 1 2 " R 1 3 E 2 R 2 2 - R 2 3 T S 3 " R 3 2 ^ 3 3 A R 2 2 ) ( R 3 3 ) + ( - R 1 2 ) ( - R 2 3 ) ( E 3 ) + ( - E 1 3 ) ( E 2 ) ( - R 3 2 ) ) - - ( ( E 3 ) ( R 2 2 ) ( - R 1 3 ) + ( - R 3 2 ) ( - R 2 3 ) ( S l ) + ( R 3 3 ) ( E 2 ) ( _ R 1 2 ) ) -248- R11 E1 -13 313 -R21 E2 "R31 E3 233 A ( ( R 1 1 ) ( E 2 ) ( R 3 3 ) + (E^(-H23){-R^) + (-E 1 3)(-H 2 1)(E 3)) - -((-R 3 1)(E 2)(-R 1 3) + ( E 3 ) ( - R 2 3 ) ( R n ) + (R 3 3 ) ( - R 2 1 ) ( E 1 ) ) - R11 ~R12 E1 -R21 R 2 2 E2 "R31 "R32 E3 ( ( R 1 1 ) ( R 2 2 ) ( E 3 ) + (-R 1 2)(E 2)(-R 3 1) + (Z^(-R2^(-Z32)) - - ( ( - R 3 1 ) ( R 2 2 ) ( E 1 ) + (-R 3 2)(E 2)(R n) + (E 3)(-R 2 1)(-R 1 2)) A 5.- Prom Kirclihoff s Current Law: ' I., = I_ - I, ul <L 3 Therefore: V"ab = 1,^ NOTE.- The Ohm's Law Matrix holds true for any number of loops. In actual practice, the largest number of loops found in most electrical circuits i s three. However, when a four loop system i s found, the solution by determinants ca l l s for the use of cofactors. Another way to solve four simultaneous equations i s the use of Gauss's Elimination Method, also known as the Addition and Subtraction Method, and i s suitable for computer programming. An alternate procedure to solve a four loop system, i s to reduce i t into a three loop system by a careful application of Thevenin's Theorem. Whichever i s the chosen procedure to solve simultaneous equations, the Ohm's Law Matrix i s always a valid representation of the e l e c t r i c a l system or systems. -149- 3 1 4 The following examples have been solved using the Ohm's Law Matrix and a computer. The computer program was based on the previous determinant equations. EXAMPLE 3.- Determine the current IT,j in the following c i r c u i t . I0JI f WWW T 1 SOLUTION 1. - Define the loop currents 1^, Ig, and 1 ^ in the clockwise direction as shown above. 2. - The corresponding 01am' s Law Matrix i s : 60 -20 -30 h 80 -20 85 -50 0 -30 -50 90 h 0 \ / \ \ ) 4«- The computer solutions to above matrix are: 11 = 3.0183 A 1 2 = 1.934 A 1 3 = 2.0805- A 5.- 3y Kirchhoff's Current Law: . I T T = I - I = 0.1465 A - 2 5 0 - 315 ZiilS'IuZ 4.- Determine the load Voltage in the following circuit: 150 V 2 2 K / 1 -vVWvW 56 K& •vWWW 50LUTI0! Define the loop currents I., T 0 and I, in the clockwise direction as shown above. The Ohm's Law Matrix i s : 9 0 k a - 6 8 k a 0 - 1 5 0 - 6 8 k X L 1 5 7 k * L - 3 3 k a = - 1 0 0 0 - 3 3 k f l , 34kft h 100 4.- The computer solutions for the currents are: I 1 = - 2 . 8 6 x 10 -3 I 2 = - 1 . 5 7 9 x 10 I_ = 1 . 4 0 7 x 10 3 -3 5.- Therefore, by Ohm's Law: V T = I , x 1 k f l . = 1 . 4 0 7 V L ;> -25/- 3 1 6 DERIVATION ON THE OHM1 S LAY.' LiATNIX This equation i s derived using loop analysis techniques. As a sample c i r c u i t , consider the two loop array shown below. v2  - V . - -vWvW- I. + Kl - vWWV1 v 31 R3 (jT), —-WWvV1 — — — V 4 > -t Eor the above ci r c u i t : 1.- Assume loop currents 1̂  and 1̂ , and draw them clockwise (CW). Assume the resulting center branch current 1̂  to be moving downwards. Its value i s determined by Kirchhoffs Current Law, which states that a l l the currents entering a connection must be equal to a l l the currents leaving that connection: By Kirchhoff s Current Lav/: 1̂  = I^ + 1^ Therefore: NOTE.- If any or a l l the current directions were to be assumed in the wrong direction, then, the resulting current(s) w i l l be negative, reminding one to correct i t s / t h e i r direction. -252- 317 Above currents w i l l produce voltage drops on the resistors i n their path. Therefore, assign polarity marks to each resistor, based on the direction assumed for each current, i . e. CURRENT Use Kirchhoffs Voltage Law for each of the loops of the ci r c u i t configuration. Kirchhoffs Voltage Law states that in a closed loop a l l the voltage drops must equal a l l the voltage rises. Voltage signs are assigned, depending on what polarities the loop current encounters in each element, as shown below: l + , L 0 ° P CURRENT _ . LOOP CURRENT 4 ? 6 POSITIVE V POSITIVE E NEGATIVE V NEGATIVE E (EFFECTIVELY A (EFFECTIVELY A VOLTAGE RISE) VOLTAGE DROP) The f i r s t loop yields: V 1 + V 3 = E l The second loop yields: v 2 - v 3 + V^ (1) (2) I 3 Apply Ohm's Law to each voltage drop in the above equations: 0 ' ) (2') H 2 I 2 - H 3 - I 2) + H I 4 2 " ^2 - 2 5 3 - 318 factor a l l the loop currents: 3 -1 + ^2 + R3 + V -2 - -2 R_ I (1") (2") Order the terms of above simultaneous equations into arrays, ;o yield the following matrix equation H 1 + R 7 - R„ - it- R2 + R̂  + H 4 1 r2 '2 'Te can v/rite above equation i n i t s general form: / \ / \ / s R 1 1 2 h E 1 -R21 R 2 2 J2 2 ^ / k > '.There: Rj^ corresponds to ( E 1 + R a l l the resistance i n loop 1. R 2 2 corresponds to (R 2 + R̂  + R^). That i s , i t i s the sum of a l l the resistance in loop 2. (-R12) or (-R2_|) corresponds to (-R^). That i s , i t i s the resistance common to either loop with a negative sign. This sign accounts for the fact that the two loop currents, having a l l of them been drawn clockwise, produce positive.or negative voltages on the same common element. Por example, when R i s multiplied by loop current 1̂  i n loop one, the resulting voltage has a positive value, but, when in loop two, the same R 2̂, • when multiplied by the same loop current 1̂ , results i n a negative voltage. -254- 319 8.- Above matrix equation can be rewritten symbolically as: (H) (I) = (E) In either form, I c a l l this expression the OHM'S LAY/ MATRIX. Yfnen this matrix i s written as shown above, i t i s very easy to remember and to use. Matrices as well as determinants, are arrays of numbers meant to be used as mnemonic aids, that i s , aids to the memory. Their purpose i s to simplify some equations and their mathematical procedures of solution. - 2 5 5 -

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