Open Collections

Faber, Simon

University of British Columbia

Industry-standard construction of solar panels involves connecting solar cells in series or parallel configurations with bypass diodes. This configuration of panels causes a reduction in efficiency when the intensity of light and temperature varies between cells due to series-connected strings being limited by the cell with the lowest current generation in the circuit. In this work, an alternative panel configuration is proposed where individual sub-arrays of series-connected cells are load-matched to minimize the losses due to mismatch from partial shading and variation of cell parameters due to manufacturer process variation. To evaluate and compare the performance of series-connected and sub-array panels, a mathematical expression for "Utilization Factor" (UF) is expressed as a ratio of the output power of a series-connected string over the maximum power available (MPA) from each cell in the string. The UF of a variety of panel and string configurations are determined using a solar simulator and an experimental testbed. The experimental results are verified using an equivalent circuit model simulated in LTSpice. The loss of power due to manufacturing process variation is ultimately deemed negligible for the cells used in experimentation. The losses due to partial shading are demonstrated as significant for any shading scenario and intensity. Ultimately, the potential use of load-matched sub-arrays to reduce the effect of cell mismatch and therefore reduce power lost due to partial shading conditions is evaluated through UF. These alternative configurations are demonstrated to provide up to a 60% increase in efficiency compared to series-connected bypass diode-protected panels under extreme partial shading conditions. However, these increases are highly dependent on cell variance due to partial shading conditions and manufacturing process variation. Therefore, practical use of alternative panel configurations is recommended when the user or manufacturer has prior knowledge of the panel's operating environment. This allows for the calculation of efficiency lost due to additional hardware compared to the efficiency gained from alternative panel configurations.

Text

2023-06-08

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/84820

Electrical Engineering

University of British Columbia

UBCO

http://creativecommons.org/licenses/by-nc-nd/4.0/