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Saeidi, Mehdi

University of British Columbia

Efficient utilization of time and frequency resources in communication networks is crucial to meet the demands of the fast growing global internet traffic. The concept of packing data more densely in time and frequency via so-called Fasterthan- Nyquist (FTN) transmission, originally proposed in the 1970’s, has therefore regained popularity. This faster, more bandwidth-efficient transmission of data results in interference between symbols adjacent in time and frequency, which must be mitigated in the receiver. Hence, computational complexity of FTN receivers is generally higher than for non-FTN receivers and constitutes a bottleneck for practical adoption. Although there have been significant advances in algorithm design for reducing the computational complexity of state-of-the-art FTN decoders, research on efficient hardware acceleration has only been sporadic. In particular, hardware implementations of different components that constitute the FTN decoder have been investigated in isolation. As a result, the only hardware FTN decoder proposed to date utilizes the hardware resources extremely inefficiently (its hardware utilization is on the order of 54.1%). In this thesis, we offer algorithmic and architectural insights for efficient implementation of complete FTN decoder systems. We identify convergence properties and parallelism opportunities unique to how the computational blocks operate and communicate with each other when combined in an FTN decoder, and describe how to leverage the insights for speed and area-efficiency. Our proof-of-concept field-programmable gate-array (FPGA) implementation reduces memory and logic footprints to within 26% and 4% of an idealized FTN hardware decoder, and achieves a throughput of 1.46 Gbps.

Text

2022-11-21

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/83168

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/