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Sharkia, Ahmad

University of British Columbia

Phase-locked loops (PLLs) are commonly used as clock generators for sub-systems within integrated circuits at the cost of significant power, area, and complexity. This thesis presents an attempt at simplifying the integration of multiple clock generators within a chip and presents three clock generators designed in a 65 nm CMOS process. The first design includes a dual-loop LC-voltage-controlled oscillator (VCO)-based frequency synthesizer, composed of an all-digital frequency-locked loop and a voltage-mode, type-I, subsampling PLL. A compact subsampling phase detector is described which also acts as a loop filter. The synthesizer occupies a small footprint of 100 × 100 µm², thanks to its compact loop filter and full integration underneath the VCO inductor. It achieves sub-200 femtoseconds of root-mean-square integrated jitter across its tuning range of 4.6–5.6 GHz while consuming no more than 1.1 mW. The second design includes a serrodyne modulator-based fractional frequency divider. The divider is built using a quadrature divide-by-2 circuit and a 4:1 multiplexer that is controlled by a secondary programmable fractional divider. The serrodyne modulator receives its input signal with large deterministic jitter (DJ) from the mux, and by employing linear sawtooth modulation of delay, attenuates the DJ, achieving low-noise fractional frequency synthesis. With a 0.01 mm² footprint, it is ideal for multi-output clock generation, fast frequency switching, and spread-spectrum clocking. With an on-chip PLL-generated 5 GHz signal as input, and 2.4899 GHz output, the circuit achieves ≥ 7.2× reduction in the peak-to-peak DJ (DJpp). With an external 8.7 GHz input, and 4.33 GHz output, DJpp reduction is ≥ 6.4×. Aimed for microprocessor applications, the design compares favorably to prior art. Despite its effectiveness at attenuating some DJ components, this fractional clock generator design suffers from secondary DJs that are caused by mismatches in the input signal path and the action of the delta-sigma modulator (DSM). The third design attempts to address the limitations of the second design by reducing the input signal paths from 4 to 1 to eliminate the mismatch caused DJs, and by integrating an additional DJ cancelation path to attenuate the DSM-caused spurs.

Text

2025-01-31

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/80557

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/