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UBC Theses and Dissertations

Computational lithography for silicon photonics design Lin, Stephen 2020

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Computational Lithographyfor Silicon Photonics DesignbyStephen LinB.ASc., The University of British Columbia, 2016A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinThe Faculty of Graduate and Postdoctoral Studies(Electrical and Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)March 2020c© Stephen Lin, 2020The following individuals certify that they have read, and recommend tothe Faculty of Graduate and Postdoctoral Studies for acceptance, the thesisentitled:Computational lithography for silicon photonics designsubmitted by Stephen Lin in partial fulfillment of the requirements forthe degrees of Master of Applied Sciencein Electrical and Computer EngineeringExamining Committee:Dr. Lukas ChrostowskiSupervisorDr. Jeff YoungSupervisory Committee MemberDr. Nicolas A. F. JaegerAdditional ExamineriiAbstractA lithography model is built using physical measurements obtained froma fabricated test pattern. The method is able to accurately predict theproximity and smoothing effects characteristic of a 193 nm deep-ultraviolet(DUV) lithography process.The accuracy of the model is verified by visually inspecting the fabri-cated test patterns and comparing them to the predictions of the lithographymodel. Furthermore, using a benchmark device (the contra-directional cou-pler), the prediction accuracy of the optical response is compared againstexperimental measurements. The comparisons showed the predictions hadgood agreement with the fabricated devices.Subsequently, an application of the lithography model is demonstrated.Design correction methods enabled by the lithography model are performedon the contra-directional coupler. The new designs were fabricated usingelectron-beam lithography and their experimental measurements confirmedan improved optical performance.iiiLay SummaryDeep-ultraviolet lithography (DUV) is a method of fabrication for siliconphotonic devices with the ability to perform large volume fabrications. How-ever, the DUV process produces fabrication errors known as lithographyeffects.In this thesis, a model able to predict the lithography effects of a DUVprocess is built. The model can generate a prediction of the lithographyeffects from any device layout. The predictions of the model demonstratedgood accuracy when verified using scanning electron microscope images andexperiment data.Enabled by the lithography model, first-time-right design methods aredemonstrated. These methods provide information useful for device proto-typing on the DUV process without performing a DUV fabrication. Fur-thermore, the emulation of the DUV process using a low-cost electron beamlithography (EBL) process was demonstrated.Lastly, using the first-time-right design methods, a revised photonic de-vice was fabricated using EBL which produced an improvement in opticalperformance.ivPrefaceThe contents in Chapter 3 of this thesis are based on the following publica-tion of which I am the primary author:S. Lin, M. Hammood, H. Yun, E. Luan, N. A. F. Jaeger andL. Chrostowski, ”Computational Lithography for Silicon Pho-tonics Design,” in IEEE Journal of Selected Topics in QuantumElectronics. doi: 10.1109/JSTQE.2019.2958931I was the lead investigator responsible for concept formation, data collectionand analysis, layout design, building the lithography model, and manuscriptcomposition. H. Yun, M. Hammood, and E. Luan were involved in earlystages of concept formation, layout design, and contributed to manuscriptedits. N. A. F. Jaeger was involved in manuscript edits. L. Chrostowskiwas the supervisory author on this project and was involved throughout theproject in concept formation and manuscript edits.The schematics and scanning electron microscopy images of sub-wavelengthdevices presented in Chapter 1 of this thesis are designs developed by HanYun and Enxiao Luan of the Microsystem and Nanotechonology Group atthe Department of Electrical and Computer Engineering of the Universityof British Columbia.The scanning electron microscopy images presented in Chapters 1, 2, 3, 4and 5 were taken by Dr. Gethin Owen from the Centre for High-ThroughputPhenogenomics at the Faculty of Dentistry at the University of BritishColumbia.The test pattern set used to develop the lithography model in Chapter 3is provided by the Mentor Graphics Calibre Workbench Software.vTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . viList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixList of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . xviiAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . xviiiDedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Periodic Devices . . . . . . . . . . . . . . . . . . . . . . . . . 21.1.1 Bragg Grating Filters . . . . . . . . . . . . . . . . . . 31.1.2 Contra-directional Couplers . . . . . . . . . . . . . . 61.2 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.2.1 Deep-Ultraviolet Lithography . . . . . . . . . . . . . 131.2.2 Smoothing and Proximity Effects . . . . . . . . . . . 172 Cross-Sectional Analysis of Contra-DCs . . . . . . . . . . . 203 Computational Lithography Model . . . . . . . . . . . . . . . 243.1 Test Pattern Data Extraction . . . . . . . . . . . . . . . . . 243.2 Model Optimization . . . . . . . . . . . . . . . . . . . . . . . 293.3 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31vi4 Designing for Manufacturability . . . . . . . . . . . . . . . . 404.1 DUV-Emulation using EBL . . . . . . . . . . . . . . . . . . . 414.2 Self-reflection Surpression via Mismatched Corrugations . . . 464.3 Compensating for Lithography Effects . . . . . . . . . . . . . 485 Summary, Conclusions, and Suggestions for Future Work 565.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565.2 Suggestions for Future Work . . . . . . . . . . . . . . . . . . 57Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62AppendixA Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69viiList of Tables2.1 Bandwidth and central wavelength for a contra-DC of W1,2=560, 440 nm at various angles. . . . . . . . . . . . . . . . . . . 222.2 Bandwidth and central wavelength for a contra-DC of W1,2=370, 270 nm at various angles. . . . . . . . . . . . . . . . . . . 222.3 Bandwidth and central wavelength for a contra-DC of W1,2=560, 440 nm at various waveguide heights. . . . . . . . . . . . 232.4 Bandwidth and central wavelength for a contra-DC of W1,2=370, 270 nm at various waveguide heights. . . . . . . . . . . . 233.1 Contra-DC Parameters . . . . . . . . . . . . . . . . . . . . . . 353.2 Contra-DC main band Bandwidths . . . . . . . . . . . . . . . 393.3 Contra-DC SR-band Bandwidths . . . . . . . . . . . . . . . . 40viiiList of Figures1.1 An example Bragg response is depicted. The bandwidth isdepicted centered around a wavelength of 1550 nm. The re-flection response shows null peaks useful for determining thebandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2 A diagram of the contra-DC device with the parameters labeled. 71.3 The phase match condition for a contra-DC with parametersof W1=560 nm, W2=440 nm, Gap=220 nm, Λ = 318 nm,∆W1=50 nm, and ∆W2=30 nm is shown. W1’s effective indexis plotted in red, W2’s effective index is plotted in blue. Theaverage effective index of the two waveguides is plotted inpurple. The phase match condition is plotted in orange. Thecenter wavelength (at λ=1550 nm of the main bandwidth ismarked with a green dot. The locations of the self-reflectionbandwidths (λ=1510 and 1585 nm) are marked with red dots. 81.4 The couple mode theory-transfer matrix method simulationresponse for a contra-DC of W1,2=560, 400 nm, Gap=220nm, Λ=318 nm, and ∆W1,2=50, 30 nm. The through-portis shown in blue and the drop-port is shown in orange. Themain band can be seen centered at λ=1550 nm and the lowerself-reflection can be seen centered around λ=1510 nm. Notethat only the self-reflection of the input waveguide will bevisible from the through-port. The plot was generated usingthe SiEPIC Photonics Package. . . . . . . . . . . . . . . . . . 91.5 The magnitude of the Fourier Transforms of the time domainsignal at various kz values are depicted. The two peaks foreach transform can be used to obtain the bandwidth and cen-ter wavelength. The peaks can also be plotted to obtain thebandstructure diagram shown in Figure 1.6. . . . . . . . . . . 111.6 The bandstructure plot obtained from a sweep of kz is de-picted. The main band is around kz=0.48 while the self-reflection band can be seen at kz=0.5. . . . . . . . . . . . . . 12ix1.7 A simplified diagram of the DUV Lithography Process. TheOptical light is selective filtered using the light-field pho-tomask to create the desired topography shapes. The filteredlight beam is then focused via a lens and then imprinted ontothe wafer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.8 An illustration of the shape profile of the silicon device. Thedark-field photomask as-drawn design is shown on the left inblue. A top-down view of the resulting fabrication is shownon the right in pink. . . . . . . . . . . . . . . . . . . . . . . . 161.9 The layout and DUV fabrication result of a Bragg gratingfilter are depicted. The grating is made of rectangular notcheswhich periodically modulate the refractive index. Smoothingeffects on the gratings reduce the optical performance. TheSEM is taken at 25,000x magnification with 15.00 kV voltage,50 pA current, using secondary electron mode. The SEM wastaken at the University of British Columbia. . . . . . . . . . . 171.10 The layout of a contra-directional coupler and SEM imageof the DUV fabrication are depicited. The device functionssimilar to a Bragg grating filter. An additional complexity isintroduced in the form of a second coupling grating waveg-uide. As seen from the SEM image, the device is prone tosmoothing of the gratings and proximity-effects at couplingregion between the two waveguides. The SEM is taken at65,000x magnification with a voltage of 15 kV, current of 50pA, using secondary electron mode. The SEM was taken atthe University of British Columbia. . . . . . . . . . . . . . . . 181.11 The layout and DUV fabrication of a SWG coupler are de-picted. The DUV fabrication rounds the gratings noticibly.Furthermore, proximity effects can be seen; the distance be-tween gratings on both the right side vary. The SEM is takenat 120,000x magnification with a voltage of 15 kV, current of50 pA, using secondary electron mode. The SEM was takenat the University of British Columbia. . . . . . . . . . . . . . 192.1 Orthogonal view of the schematic used for 3D-FDTD simula-tions depicting sidewall angles on the grating faces. . . . . . . 212.2 Cross-sectional profile of the contra-directional coupler devicedepicting the sidewall angles. The angle variation locationsare labelled in green. . . . . . . . . . . . . . . . . . . . . . . . 22x2.3 Cross-sectional SEM of a contra-DC demonstrating sidewallangles taken at 64,963x magnification using a voltage of 2.00kV, current of 0.10 nA, in back-scatter electron mode. Thepocket located between the two trapezoidal silicon structuresis a manufacturing error. The SEM was taken at the Univer-sity of British Columbia. . . . . . . . . . . . . . . . . . . . . . 223.1 The SEM of a section of the test pattern is depicted. ThisSEM is obtained by stitching together individual SEM imagesof the patterns each taken at a magnification of 5000x, avoltage of 20 kV, and a current of 0.10 nA. . . . . . . . . . . 253.2 The types of structure included on the standard test patternare illustrated. The structures consist of solid structures ([a]to [h]), and inverse structures ([i]) to [l]). . . . . . . . . . . . . 263.3 The as-fabricated CDs are plotted against the as-drawn CDsfor the structures shown in Fig. 3.2e - 3.2l. Each solid struc-ture and their inverse counterpart have shown different CDtrends, indicating different process biases are required for eachtype of structure. The simulated CDs are also included tocompare the closeness of the lithography model. . . . . . . . . 273.4 (a) An SEM of an Inverse Contact structure. (b) A zoom-in il-lustrating the thick white border can create CD measurementdiscrepancies. Our convention is to use the average distancebetween the outer and inner edge of the border. . . . . . . . . 283.5 A 1-dimension search (varying numerical aperture) is pre-sented. The error root-mean-square is plotted against thenumerical aperture. The error root-mean-square is obtainedby comparing the lithography predictions of the model to theCD measurements. The search aims to obtain the parame-ter value which produces the minimal error root-mean-squarevalue. In the plot, the optimal value for NA is 0.67 with anerror root-mean-square of 5.237 nm. The entire model build-ing process performs this search in 3-dimensions (varying NA,σ, and δσ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.6 Steps to optimize the lithography model: (a) the ideal as-drawn mask. (b) the computed illumination generated usingthe optical wavelength, NA, σ, and δσ. (c) the selection ofthe threshold value, shown in red. (d) the predicted post-lithography output. . . . . . . . . . . . . . . . . . . . . . . . . 31xi3.7 A Broken H structure is depicted. The CD location is betweenthe two center protrusions and captures how small grating-like structures will be effected by photolithography. The CDpredicted by our method (b) is nearly identical to the fabri-cated one (c). . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.8 The Corner structure, which captures how two corners inter-act when in close proximity, is depicted. The resulting CDfrom our simulation is highly similar to that of the fabricatedone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.9 The schematic of a contra-DC, with the design parametersand the four ports labeled. A single segment block of theBragg grating with a pitch (Λ) is repeated to obtain a desiredlength. There are two corrugation widths (∆Ws), which willoften be affected differently by the fabrication process. . . . . 353.10 (a) A simplified contra-DC design, with symmetrical waveg-uide widths and ∆Ws to demonstrate the smoothing and theproximity effects of photolithography. (b) The post-fabricationchanges in the gap, ∆Winner, and ∆Wouter dimensions are de-picted, showing a large asymmetry between the ∆Ws. Thesize reduction of ∆Winner is due to both the smoothing, andproximity effects, where as the size reduction of ∆Wouter isonly due to the smoothing effect. . . . . . . . . . . . . . . . 363.11 The main band nulls bandwidths of CDC3. (a) The as-drawnlayout, (b) the lithography model as-predicted, and (c) theDUV as-fabricated, are depicted. The as-drawn simulatednulls bandwidth is 11.5 nm, the as-predicted nulls simulatedbandwidth is 5.6 nm, and the as-fabricated measured nullsbandwidth is 6.4 nm. The noise floor of c) is due to instrumentmeasurement limitations. . . . . . . . . . . . . . . . . . . . . 373.12 The SR nulls bandwidths of (a) the as-drawn, (b) the as-predicted, and (c) the as-fabricated, are depicted. The as-drawn simulated bandwidth is 11.1 nm, the as-predicted sim-ulated bandwidth is 6.0 nm, and the as-fabricated measuredbandwidth is 5.4 nm. . . . . . . . . . . . . . . . . . . . . . . . 383.13 The contra-DC main band nulls bandwidths for the as-drawn(blue I-bars), the as-predicted (red squares), and experimen-tally measured (black triangles) contra-DC devices are plot-ted. The data values can be found in Table 3.2. . . . . . . . . 39xii3.14 The contra-DC self-reflection band nulls bandwidths for theas-drawn (blue I-bars), the as-predicted (red squares), andexperimentally measured (black triangles) contra-DC devicesare plotted. The data values can be found in Table 3.3. . . . 404.1 The bandwidths vs. corrugation width of a Bragg filter de-vice comparing the difference between fabrications and theemulation of the DUV fabrication process (EMU). . . . . . . 434.2 SEM images of the EBL fabrication (left), DUV-emulation(EMU) (center), and DUV fabrication (right) is shown. TheEMU shows high similarity with the actual DUV fabrication.The EBL and EMU images were taken using 13,900x magni-fication, voltage of 15 kV, and a working distance of 6.7 mm.The DUV image was taken using 25,000x magnification, volt-age of 15 kV, current of 50 pA, with secondary electron mode.The images were resized to the same scale using the pixel dis-tance provided. . . . . . . . . . . . . . . . . . . . . . . . . . . 434.3 The main bandwidth versus mismatch corrugation width isplotted. The main bandwidth is expected to remain negligiblyunchanged as the corrugation mismatch increases. The EBLfabrication design (blue) shows this stable trend. The DUVfabrication (purple) also shows this trend with a reduction inbandwidth due to the fabrication variations. The emulationfabrication (EMU) (orange) closely follows the DUV results,demonstrating good agreement between the emulation andthe actual DUV fabrication. . . . . . . . . . . . . . . . . . . . 44xiii4.4 The SEM images of the three fabrications of the contra-DCdevices are shown. The EBL contra-DC (left) shows balancedcorrugations, and orthogonal corrugation profiles. The emu-lation (EMU) of the DUV-process (center) shows smoothedand reduced corrugations with mismatched corrugations. TheDUV fabrication (right) is closely resembles by the EMU,demonstrating smoothed & reduced corrugations, and an ob-vious mismatch between the inner and outer corrugations.However the EMU still slightly differs from the DUV, specif-ically between the inner corrugations, and requires furtherinvestigation and improvement. The EBL and EMU SEMimages are taken at a magnification of 37,720x, voltage of 15kV, and a working distance of 6.7mm. The DUV SEM sim-age was taken at a magnification of 65,000x, voltage of 15 kV,current of 50 pA, using secondary electron mode. The imageswere adjusted to the same scale using the pixel measurementprovided by the images. . . . . . . . . . . . . . . . . . . . . . 454.5 The layout with the definitions for Wouter and Winner for thenarrow waveguide (W1) and the wide waveguide (W2). . . . . 474.6 The simulated bandwidths of ∆∆W2 from -30 to 30 nm isdepicted. The main band bandwidth (orange) shows a hori-zontal trend indicating minimal influence from ∆∆W2. Theself-reflection bandwidth (blue) shows a decrease as the outercorrugations becomes smaller than the inner corrugations. Aminimum is observable around ∆∆W2 = -10 nm. . . . . . . . 484.7 The simulated bandwidths of ∆∆W1 from -50 to 30 nm is de-picted. The main band bandwidth (orange) shows horizontaltrend. The self-reflection bandwidth (blue) shows a gradualdecrease in bandwidth. A minimum bandwidth below 1 nmoccurs around ∆∆W1 = -30 nm . . . . . . . . . . . . . . . . . 494.8 The simulated results (purple) are compared against the mea-sured bandwidths (blue) of the devices using as-drawn lay-outs. The trend follows closely with the simulations, demon-strating as suppressed self-reflection when ∆∆W2 = -10 nm. . 504.9 The responses of the as-drawn layout (blue) and the lithography-emulated (EMU) (orange) devices are compared. The com-plete suppression is visible in both measurement results. Thelithography-emulated devices also show a rightwards shift. . . 50xiv4.10 The main band bandwidths of the FDTD simulation (purple),as-drawn layout (blue), and lithography-emulated (EMU) lay-out (orange) are shown. The as-drawn bandwidths agree withthe FDTD simulations, confirming that the main band band-widths have not changed when using mismatched corruga-tions. The EMU results indicate that the main bandwidthwill be reduced by around 2 nm when DUV-lithography ef-fects are introduced. . . . . . . . . . . . . . . . . . . . . . . . 514.11 The measured spectrum of the EBL fabricated corrugationmismatched contra-DC devices. The control for the exper-iment (∆∆W2 = 0 nm) is depicted in (a) and the devicedemonstrating successful bandwidth suppression is depictedin (b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.12 The DUV-lithography emulation (EMU) response of ∆∆W2= 0 is shown. The measured response indicates that whensmoothing is considered, the suppression of the self-reflectionwill occur with the nominal design parameters. . . . . . . . . 534.13 (a) The as-drawn gap and ∆W parameters of CDC3 is shown.(b) A lithography prediction of the as-drawn parameters. Theresults show asymmetry for the ∆Ws and a larger gap. (c) Aredesign of CDC3 using the information obtained from (b).(d) The lithography prediction of the redesigned CDC3. Theresults indicate that the ∆Ws and gap sizes will match theoriginal as-drawn values. . . . . . . . . . . . . . . . . . . . . . 544.14 The simulated main bandwidth response of the CDC3 idealdesign (Fig. 4.13a) and redesign (Fig. 4.13d) using 3D-FDTD. The bandwidth of the ideal design is 11.5 nm and thebandwidth of the redesign is 9.8 nm. A significant improve-ment over the as-fabricated bandwidth of 6.4 nm (demon-strated in Fig. 3.11c) when the device undergoes a redesignto compensate for lithography effects. . . . . . . . . . . . . . 55xv5.1 (a) The schematic of a contra-DC using a cavity design is de-picted. The cavity has a size of 160 nm which is within thefabrication’s guaranteed ranges. (b) A lithography simulationof the schematic showing that the cavities should be fabri-cated with a size of approximately 88 nm. (c) An SEM of thecavity-based contra-DC. The image was taken with 65,000xmagnification, voltage of 15 kV, current of 50 pA, using sec-ondary electron mode. The image shows that the cavitiesof the contra-DC were unresolved despite the schematic us-ing conservative feature sizes and the lithography simulationindicating resolving of cavities. . . . . . . . . . . . . . . . . . 585.2 (a) The GDS schematic of the ”inverse contact” test pattern,aimed at capturing the fabrication of cavity structures. Thecavity has a size of 180 nm. (b) A SEM of the test patternfrom which the lithography model was built upon. The cavityis successfully resolved at 83 nm. (c) A SEM of the testpattern from a second run of the same process in which cavityhas failed to resolve. . . . . . . . . . . . . . . . . . . . . . . . 595.3 A mock up of an automatic CD extraction procedure. Theinput image a) is processed by a thresholding algorithm toclean up the contrast and pixel artifacts. The output is shownin b). Finally, an edge-finding is performed to map out theshape and obtain the CD measurement, as shown in c). . . . 60xviList of AbbreviationsArF Argon Fluoride. 2, 14CD Critical Dimension. xi, xii, xvi, 24, 27–32, 34, 57, 60CMOS Complementary Metal-Oxide-Semiconductor. 1, 13–15contra-DC Contra-directional Coupler. viii, ix, xi–xvi, 2, 3, 6–11, 17, 18,20–23, 31–33, 35–37, 39–42, 45–47, 52, 56–58DUV Deep-Ultraviolet. x, xii–xv, 1, 13–21, 24, 29, 37, 41–47, 53, 56, 57,59, 60EBL Electron Beam Lithography. xiii–xv, 1, 13, 14, 41–46, 52EMU Emulation of Deep-Ultraviolet Lithography. xiii–xv, 42–45, 50, 53FDTD Finite-Difference-Time-Domain. x, xv, 6, 10, 11, 20, 21, 33, 46, 47,55, 56, 61KrF Krypton Fluoride. 14OPC Optical Proximity Correction. 1SEM Scanning Electron Microscopy. x, xi, xiii, xiv, xvi, 2, 17–20, 22, 24,25, 28, 29, 31, 32, 42, 43, 45, 56–60SOI Silicon-on-Insulator. 1, 6, 13, 14SR Self-Reflection. viii, xii, 32, 33, 38, 40SWG Sub-wavelength Grating. x, 17–19xviiAcknowledgementsSincerest gratitude to Dr. Lukas Chrostowski for offering the opportunity tolearn about Silicon Photonics, supplying lab equipment, organizing multi-project wafer runs with foundries, and providing expert advice that madethis thesis possible.Sincerest gratitude to Dr. Nicolas A. F. Jaeger for providing exceptionalsupport and editorial suggestions in the publishing of my paper.Very grateful to Mustafa Hammood, Han Yun, Enxiao Luan, and Rui Cheng:the discussions on grating-based design and fabrication variations were anintegral part of the results produced in this thesis.Special thanks to Dr. Gethin Owen from the Centre for High-ThroughputPhenogenomics at the Faculty of Dentistry at the University of BritishColumbia for his assistance with SEM imaging and customized stitchingof images.Thank you.xviiiTo all the hardworking and brilliant people of science,I hope the results showcased in this thesis contributes in your endlesspursuit of improving technology and human knowledge.xixChapter 1IntroductionIn recent years, silicon-on-insulator (SOI) platforms have increased in pop-ularity. Many key devices, such as, filters [1], modulators [2], and photode-tectors [3] have been demonstrated on such platforms [4][5]. SOI platformshave two common choices for patterning the silicon: electron-beam lithog-raphy (EBL) and deep-ultraviolet (DUV) lithography. EBL is performed bywriting the design directly onto the resist via an electron beam. This mask-less fabrication approach can achieve smaller feature sizes with fast turn-around times, at the cost of low throughput. This makes EBL attractive forrapid-prototyping research and development purposes [6]. Conversely, DUVlithography performs the design patterning using a binary mask. The maskexposes the resist via a laser within a projection system (such as full-waferprojection, full-wafer scanning, step-and-repeat also known as a stepper, andstep-and-scan also known as a scanner) which prints a copy of the designonto the wafer[7]. As a result, the DUV process has high throughput and ismore suitable for mass production.SOI device performance suffers from discrepancies between as-designedand as-fabricated structures. Photolithographic effects, such as smooth-ing [8] and proximity effects [9], are large contributing factors to these dis-crepancies. Previous efforts have been made to correct for photolithographyeffects. These include optical proximity correction (OPC) [10][11][12][13][14]and using phase shifted masks [15][7]. However, the SOI platform does notyet have a “first-time-right” design approach akin to that of the CMOSplatform [16].As silicon photonics marches towards commercialization, it is crucial thatit brings with it the robustness in fabrication that exists in mature CMOSprocesses [4]. Previous work demonstrated that photolithography smoothingeffects of 2-port Bragg grating devices could be modelled by fitting themodelled responses to experimental responses [8][17]. However, designerswould ideally wish to understand and model the effects of photolithographyprior to fabrication.In this work, we use a computational lithography model to predict theoutcomes of a commercial dry 193 nm DUV lithography fabrication process,1that uses an ArF laser stepper and a binary mask. The predictive modelis built using measurement data obtained from fabricated test patterns andsimulates the photolithography effects on an input shape. Our model isprocess specific and allows designers to predict their device’s performancefor a particular fabrication process. To verify the accuracy of the model,we use the optical response of a 4-port, Bragg-grating-based filter, knownas a contra-directional coupler (contra-DC) [18], as a benchmark. The con-figuration of the contra-DC consists of two Bragg gratings placed in closeproximity to each other for coupling purposes. We use the contra-DC asa benchmark because it is particularly susceptible to photolithography ef-fects, such as smoothing and proximity effects. The device is susceptibleto smoothing because it uses sidewall-corrugated, Bragg-grating waveguidesand is susceptible to proximity effects because the two waveguides are inclose proximity to each other. As the contra-DC has two output ports, andan optical response sensitive to design parameters, it is an excellent candi-date for the validation of our model. We are able to demonstrate excellentvisual resemblance between the output of our computational lithographymodel and the Scanning Electron Microscopy (SEM) images of a fabricatedtest pattern set. Furthermore, we are able to accurately reproduce the ex-perimental measurements made on our benchmark device by simulating theresponse of the predicted device structure generated by our model.1.1 Periodic DevicesThis section explains the fundamental theory of grating-based devices us-ing a 2-port Bragg grating filter. The focus is then shifted to a specificgrating-based filter, the 4-port contra-directional coupler (contra-DC). Asthe remainder of the thesis emphasizes the comparison of the bandwidth,we will present the theories of the bandwidth relationship. It is especiallyimportant for readers to appreciate/understand how sensitive the deviceperformance is due to fabrication variations.The contra-DC is a 4-port grating-based filter device. The device con-sists of two grating-based waveguides placed in close proximity for couplingpurposes. During fabrication, lithography smoothing and proximity effectsoccur on the device. The gratings are subject to smoothing due to theirshape (square) and small dimensions (typically ≤100 nm). The gaps be-tween the two waveguides are minimized (typically around 100 nm) to obtainthe highest possible coupling strength. The gap size approaches fabricationlimits and inevitably induces proximity effects. Minute variations to these2parameters incur large changes to the device performance such as band-width reductions and central wavelength shifts. This makes the contra-DCan ideal benchmark device to evaluate the accuracy/validity of the lithogra-phy model as we can compare the experimentally measured response againstthe predicted response.1.1.1 Bragg Grating FiltersThe Bragg grating structure is a photonic device that utilizes periodic mod-ulation to create a filter response. The device is simple in structure and doesnot require special fabrication steps for realization. The Bragg grating hasperiodic effective refractive index variations along its direction of propaga-tion. The variations of the index induce reflections at each boundary wherethe index changes. The reflected signals interfere constructively near a selectrange of wavelengths which is determined by the pitch (Λ) parameter of thedesign and the effective refractive index (neff ). This select wavelength isknown as the Bragg wavelength and is determined by the Bragg conditionshown in equation 1.1.λB = 2Λneff (1.1)Outside of the Bragg wavelength, the reflected signals will instead inter-fere destructively, thus creating a filter response. Fig. 1.1 shows a typicalBragg filter response.Fundamentally, the gratings function to couple the forward and back-ward modes. Using coupled-mode theory [19] the electric field can bedescribed as a summation of the forward-propagating wave (R) and thebackward-propagating wave (S) as shown in equation 1.2 [19]. β0 is theBragg propagation constant shown in equation 1.3E(z) = R(z)exp(−jβ0z) + S(z)exp(jβ0z) (1.2)β0 =2piλBneff (1.3)Using the derivations shown in [19], the coupled mode equations 1.4 and1.5 can be obtained. k is the coupling coefficient describing the couplingamount per unit length.dRdz+ j∆βR = −jkS (1.4)3Figure 1.1: An example Bragg response is depicted. The bandwidth isdepicted centered around a wavelength of 1550 nm. The reflection responseshows null peaks useful for determining the bandwidth.dSdz− j∆βS = jkR (1.5)For step-wise effective index variation gratings (square gratings), thereflection at each index interface can be written as ∆n2neff using Fresnel’sequations where the numberator ∆n = neff1 − neff2 and the denominatorneff is the effective index average of the two variations.The coupling occurs at each grating period which is the pitch (Λ) param-eter of the device. Each period will create two reflections which we includewhen writing the relationship of the coupling coefficient in equation 1.6.The coupling coefficient can be further simplified using the Bragg condition(equation 1.1) to obtain equation 1.7 [19].κ = 2∆n2neff1Λ(1.6)κ = 2∆n2neff2neffλB=2∆nλB(1.7)4From the solutions of the coupled mode equation [19], we can obtain thereflection coefficient relationship shown in equation 1.8 for a uniform gratingwith a length L [19].r =−iκsinh(γL)γcosh(γL) + i∆βsinh(γL)(1.8)where γ2 = κ2−∆β2 and ∆β has the relationship shown in equation 1.9[19].∆β = β − β0 = 2pineff (λ)λ− 2pineff (λB)λB≈ −2pingλ2B∆λ (1.9)The group index ng and wavelength relation [4] being:ng = neff − λdneffdλ(1.10)When ∆β = 0 the reflection of the Bragg grating is at its maximum, thissimplifies the reflection equation down to equation 1.11 and 1.12 for fieldand power respectively [19].r = −itanh(κL) (1.11)Rmax = tanh2(κL) (1.12)Aside from the power, we are also interested in the bandwidth of thedevice. We define the bandwidth in this case to be between the first nullsaround the target wavelength’s reflection peak. Using equation 1.11 andour relation for γ, we can write an equation for the condition at which thereflectivity in the system is equal to zero (equation 1.13).−γ2 = ∆β2 − κ2 =(MpiL)2M = 1, 2, 3, .. (1.13)Now, by taking the first order (M = 1) of equation 1.13 which corre-sponds to the two null peaks next to the Bragg wavelength and rearranging,the expression shown in equation 1.14 for the bandwidth can be obtained[20][21].∆λ =λ2Bping√κ2 +(piL)2(1.14)5As a final note, the gratings described in this chapter are considered to belossless. To include the loss in the equations ∆β can be instead substitutedwith ∆β − jαf where αf is the loss coefficient for the field.1.1.2 Contra-directional CouplersThe contra-DCs in this thesis are designed in the following steps:1. Match Bragg condition - determine the period (Λ)2. Evaluate coupling strength - determine the corrugation widths (∆W )3. Calculate using equations - rough estimates for the bandwidths4. Simulate using FDTD bandstructure - fine estimates for bandwidthsBuilding on the Bragg reflectors discussed in the previous section, K.Ikeda, et. al [18] showed on the SOI platform that two reflectors can beplaced in coupling proximity to create a four-port device in which the reflec-tion spectrum can be read from the drop port. Ikeda referred to this deviceas a wavelength selective coupler with vertical gratings. In recent years, ithas become commonly known as the contra-directional coupler (contra-DC)first proposed by Yariv [22].As the name implies, the contra-DC operates in the contra (opposite)direction of the input flow. The device functionally solves many of the nui-sances of a standard SOI Bragg reflector which will first be briefly discussed:In application, the reflections from the Bragg reflector prove challengingto read and measure, requiring either an isolator/circulator [23] or costlymeasurement apparatus. A potential solution involving using an integratedcirculator is possible [24], but there is a substantial trade-off in device foot-print.In contrast, the contra-DC provides an on-chip integrated solution thatseparates the input, transmission, and reflection ports, removing the needof isolators or circulators [25][26]. Furthermore, the contra-DC has 4-ports,creating potential for multiplexing and demultiplexing applications [27].To design a contra-DC, we first have to meet three Bragg conditions,shown in equations 1.15, 1.16, and 1.17.2β1 =2piΛ(1.15)2β2 =2piΛ(1.16)6Figure 1.2: A diagram of the contra-DC device with the parameters labeled.β1 + β2 =2piΛ(1.17)where β is the propagation constant and Λ is the pitch of one unit cellof the grating. The subscripts on β refer to waveguide 1 or 2 of the contra-DC system. Equation 1.17 can be interpreted as the average of equation1.15 and equation 1.16. Hence, the average propagation should be chosen inrelationship to our target wavelength. As the propagation β relates directlyto the refractive index n, and thus the waveguide’s width (W1 , W2), we areable to narrow down potential width parameters for our contra-DC. Figure1.2 shows a diagram depicting the contra-DC paramters. Figure 1.3 showsan example of the phase-match condition for a contra-DC with W1 = 560nm, W2 = 440 nm, Gap=220 nm, Λ = 318 nm, ∆W1=50 nm, and ∆W2=30nm. The corresponding simulated response of this device is shown in Figure1.4 using the SiEPIC Photonics Package [28]. Note that only the lower self-reflection is shown. This is because the input is set to W2. If the input inW1 the self-reflection at the higher wavelength will show instead.With the phase match condition satisfied, the next parameter of interestis the gap and corrugations of the contra-DC. These two parameters directlycorrespond to the coupling strength of the device. There are three couplingcoefficients that are of interest [26]: the backward coupling of waveguide 1(equation 1.18), the backward coupling of waveguide 2 (equation 1.19), and7Figure 1.3: The phase match condition for a contra-DC with parameters ofW1=560 nm, W2=440 nm, Gap=220 nm, Λ = 318 nm, ∆W1=50 nm, and∆W2=30 nm is shown. W1’s effective index is plotted in red, W2’s effectiveindex is plotted in blue. The average effective index of the two waveguidesis plotted in purple. The phase match condition is plotted in orange. Thecenter wavelength (at λ=1550 nm of the main bandwidth is marked witha green dot. The locations of the self-reflection bandwidths (λ=1510 and1585 nm) are marked with red dots.8Figure 1.4: The couple mode theory-transfer matrix method simulation re-sponse for a contra-DC of W1,2=560, 400 nm, Gap=220 nm, Λ=318 nm, and∆W1,2=50, 30 nm. The through-port is shown in blue and the drop-portis shown in orange. The main band can be seen centered at λ=1550 nmand the lower self-reflection can be seen centered around λ=1510 nm. Notethat only the self-reflection of the input waveguide will be visible from thethrough-port. The plot was generated using the SiEPIC Photonics Package.9the contra-cross coupling between waveguide 1 and waveguide 2 (equation1.20).κ1 =ε0ω4〈E1|∆n2g|E1〉 (1.18)κ2 =ε0ω4〈E2|∆n2g|E2〉 (1.19)κc =ε0ω4〈E1|∆n2g|E2〉 (1.20)Here, ε0 is the vacuum permittivity, ω is the angular frequency of light,and E1, E2 are the field distributions of waveguide 1 and 2 respectively.∆n2g ={−(n2core − n2clad)f(z)+12 , In silicon region0, In oxide region(1.21)For Equation 1.21, ∆n2g is the index perturbation. In the grating re-gion, the perturbation is related to the index of the core and the index ofthe cladding. The period function f(z) here describes the geometry of thegrating (relating to the pitch Λ). Furthermore, equation 1.21 reveals thatlarger corrugations (larger ∆n2g) will increase the coupling strength of ourcontra-DC.Using the equation 1.22, the rough estimates of the bandwidth can beobtained [18]. Here, κ is the backward coupling coefficient. κ1,2 is eachwaveguide’s local backward coupling (this is also known as the self-reflectionbandwidth). κc is the coupling of the main bandwidth centered at the targetwavelength. κ can also be used with the couple mode theory-transfer matrixmethod [26] to simulate the spectrum response of the device.∆λi =λ2|κi|pineffLi =1|κi| i = 1, 2, c (1.22)Subsequently, using the device parameters to create a 3D polygon, a fineestimate of the bandwidth can be obtain via the Finite-Difference-Time-Domain (FDTD) bandstructure method. The bandstructure method oper-ates by assuming an infinitely long periodic grating. Only one unit cell ofthe grating is required to be simulated [29]. The FDTD Bloch boundaryconditions are applied along the propagation direction. The Fourier trans-forms of the time domain signals can then be used to estimate the bandwidth(∆λ) and center wavelength (λ0). Furthermore, The coupling value κ canbe extracted from the bandstructure and used in equation 1.22 or in the10Figure 1.5: The magnitude of the Fourier Transforms of the time domainsignal at various kz values are depicted. The two peaks for each transformcan be used to obtain the bandwidth and center wavelength. The peaks canalso be plotted to obtain the bandstructure diagram shown in Figure 1.6.couple mode theory-transfer matrix method [26][28] to produce a responseplot.Figure 1.5 shows an example of the magnitude of the Fourier transformsof the time domain signals from a FDTD simulation of a contra-DC. Figure1.6 shows a plot of the wave vector kz versus the wavelength. kz is a unit-less wavevector (normalized by length to the period of the contra-DC). Thepeaks of Figure 1.5 correspond to the data points highlighted in Figure1.6. The most narrow section of the bandstructure, highlighted in Figure1.6 at kz = 0.48, corresponds to the devices main bandwidth, i.e. contra-directional coupling bandwidth, and center wavelength. Furthermore, theself-reflection bandwidths and their center wavelengths can be seen at kz =0.5. The reflection of the narrow waveguide is at the lower wavelength andthe reflection of the wide waveguide is at the higher wavelength.11Figure 1.6: The bandstructure plot obtained from a sweep of kz is depicted.The main band is around kz=0.48 while the self-reflection band can be seenat kz=0.5.121.2 FabricationFor designers of the silicon-on-insulator (SOI) platform the fabrication pro-cess is often the limiting factor between academic proof-of-concept devicesand large scale commercialization.There are two choices available for SOI fabrication: electron beam lithog-raphy (EBL), and a state-of-the-art optical lithography known as deep-ultraviolet lithography (DUV). The DUV process is derived from CMOSfabrication processes with the intent of reusing existing CMOS foundries tosave money and smooth the transition of adopting photonic technologies.EBL and DUV each have their own benefits and drawbacks for photonicsfabrication. EBL fabrication uses an electron beam to write the patternonto the substrate. Hence, EBL is known as the “maskless” fabrication andhas the benefits of a smaller feature size, and lower production cost perfabrication. This makes EBL very suitable for academics and designers forrapid-prototyping purposes [6]. However, as designs must be written oneby one in the EBL process its main drawback is the rate of writing [7],consequentially making it unsuitable for commercial large scale production[6]. Unlike EBL, DUV lithography uses a mask to expose the whole chipschematic all at once onto the substrate [30], hence, DUV lithography isfitting for large volume chip production. Unfortunately, DUV lithographyhas drawbacks of larger feature sizes, high production costs per fabrication[6], and significant lithography effects [31][32].Ideally, both processes are utilized to drastically reduce the time fromprototyping to commercial production: designers would prototype usingEBL until the mature design is ready for DUV lithography mass fabrica-tion. Additionally, the transition from EBL designs to DUV is difficult dueto feature size limits and lithography effects. Opportunely, the lithographymodel proposed in this thesis would enable designers to simulate the DUVlithography effects on their designs. Furthermore, this method could be usedto prototype for DUV process using EBL fabrication.In the next section, the details of DUV lithography are provided startingwith an overview of the fabrication process. Afterwards, the lithographyeffects are described and the examples on various devices are showcased.1.2.1 Deep-Ultraviolet LithographyDeep-ultraviolet (DUV) lithography is an optical fabrication process adoptedfrom the fabrication of CMOS circuits [33]. This allowed for lower produc-tion costs, higher yields [34] and the potential for photonic integrated circuits13(PIC) to be built alongside CMOS [35][36]. Originally using KrF lasers [7]operating at the 248 nm wavelength [37][38][39][40], modern, state-of-the-artArF lasers [7] operating at the 193 nm wavelength are being promoted by in-dustry foundries [37][38][39][40]. In photonics fabrication, DUV lithographyoperates by using a mask and an illumination source to expose areas on theresist on the silicon-on-insulator (SOI) wafer [7][37][31]. The primary ma-chine, known as a wafer stepper, exposes and steps to sections on the wafer,imprinting the circuit design onto the wafer [41]. Hence, DUV lithographyhas a high rate of production and is suitable for commercialization purposes[34][6]. The individual steps of the lithography process can be summarized[41]:1. Adhesion promotion: The SOI wafer surface is treated to improvebonding with the resists. Resist coating: The resist, typically made oforganic polymers, are applied onto the wafer. A standard method isto apply the resist to the center of the wafer and spun wafer at highspeeds to evenly coat the wafer. As the solvent in the resist evaporates,the resist layer becomes solid.2. Softbake: The wafer with resist is baked to fully dry off any residualsolvent.3. Patterning and Exposure: The mask designs are patterned onto theresist via lithography using ultraviolet light. The exposed resist un-dergoes a chemical reaction: The selectively of the developer chemicalto the resist is determined by the type of mask and resist used. Ulti-mately the circuit pattern is created onto the resist film.4. Development: The photonic circuits are created by stripping/etchingthe resists and underlying silicon layer in selective areas (based on themask and resist combination).Prior to the DUV lithography described above, a mask of the desiredcircuit is created using a maskless process such as electron beam lithography(EBL) [42]. The mask are planes of glasses covered with an opaque material(typically Chromium) [7] [41]. An electron beam exposes the resists on themask used for DUV fabrication and is then developed using chemicals tocreate the desired patterns.On a related note, EBL fabrication is an alternative fabrication methodto DUV for silicon photonics fabrication. The EBL SOI fabrication usesdirect writing on the SOI wafer by first exposing the resist of the wafer14using an electron beam and then using a reactive ion etch to create thephotonic devices onto the wafer [43]. In this thesis, the mentions of EBLwill be referring to the EBL SOI fabrication.There are two types of photomasks: dark-field masks where the patternareas are etched to allow light to pass, and light-field masks where thepattern areas are etched to block light [7][41][44]. Each type of mask has itsown fabrication effect such as linewidth widening/shortening [7][32], thus,fabrications can involve multiple mask types based on the desired devices[7].Once the mask is ready, the type of resist is considered. Photoresists arecategorize into two types: positive and negative [7]. Positive resists havelow solubility in the developer chemical and become soluble upon exposureby the DUV light. Negative resists are instead soluable in the developerchemical and become insoluable upon exposure to the DUV light [41]. Basedon the designs utilized in the circuit, the mask and resist combination ischosen.An example of the DUV fabrication process is depicted in Fig. 1.7. Thefigure shows a light-field mask and positive photoresist combination: TheDUV light passes through the light-field photo mask to expose the resist,creating an outline of the desired pattern. As the resist is a positive resist,the exposed areas become soluble to the developer chemical. During thedevelopment step, the exposed resist areas (and the silicon underneath thosesections) are washed away. A secondary developer targeting only the resiststrips the unexposed areas. The result is the desired pattern formed ontothe silicon layer. For complex chip designs requiring different layers: thepatterning & exposure, and development steps are repeated as necessary.Figure 1.8 shows an illustration of the characteristic smoothing of aDUV lithography PIC fabrication. A dark-field mask of the desired patternis shown on the bottom left and an aerial render of the resulting fabricationis shown on the bottom right. It is important to note the smoothing ofcorners, slight reduction in widths of the patterns, and changes in the gapbetween the two structures. These lithography effects create difficulties formany photonic devices and lack a solution akin to CMOS optical proximitycorrection (OPC) methods [14]. OPC defines the smoothing is known astwo effects: linewidth shortening and corner smoothing. For simplicity thelinewidth shortening and corner smoothing will be referred to as “smoothingeffect” in this thesis. There are also “proximity effect”, which are dimen-sional changes induced by structures being placed closely to one another.The smoothing effect and proximity effect are discussed in detail in the nextsection.15Figure 1.7: A simplified diagram of the DUV Lithography Process. TheOptical light is selective filtered using the light-field photomask to createthe desired topography shapes. The filtered light beam is then focused viaa lens and then imprinted onto the wafer.Figure 1.8: An illustration of the shape profile of the silicon device. Thedark-field photomask as-drawn design is shown on the left in blue. A top-down view of the resulting fabrication is shown on the right in pink.16(a) As-drawn layout. (b) DUV fabrication.Figure 1.9: The layout and DUV fabrication result of a Bragg grating filterare depicted. The grating is made of rectangular notches which periodicallymodulate the refractive index. Smoothing effects on the gratings reduce theoptical performance. The SEM is taken at 25,000x magnification with 15.00kV voltage, 50 pA current, using secondary electron mode. The SEM wastaken at the University of British Columbia.1.2.2 Smoothing and Proximity EffectsIn this thesis the lithography effects of the deep-ultraviolet (DUV) lithog-raphy process are categorized into two categories: smoothing effects andproximity effects. Smoothing effects include the reductions to aerial dimen-sions (length and width) of the drawn pattern (known as line shortening[7]) and corner rounding [7]. Proximity effects [7] are additional smoothingeffects that can occur when a pattern requires two structures to be placedin close range to each other. In silicon photonics, the lithography effectsheavily affect the optical responses. Many published devices, such as Braggfilters [8], contra-direcional couplers (contra-DC) [1][9], and sub-wavelengthgrating devices (SWG) [45] to name a few examples, have attributed lithog-raphy effects as the cause for reduced optical performance. The following arethree example devices showcasing the lithography effects and the differencebetween the as-drawn layout and the DUV fabrication:1) Figure 1.9a illustrates a Bragg grating filter device. The device con-sists of a waveguide with gear-like notches along the side walls. Thesesidewalls act like mirrors to reflect the target wavelength(s) backwards, ef-fectively filtering the response of those wavelength(s). The depths of thegratings, known as the corrugation width ∆W , and the pitch Λ are pre-cise parameters chosen based on the target operation wavelength. Figure1.9b shows the DUV fabrication of the Bragg-grating filter. The ∆W havebecome sinusoidal-like and their widths reduced significantly.2) Figure 1.10 shows a contra-DC device consisting of two Bragg grating17(a) As-drawn layout. (b) DUV fabrication.Figure 1.10: The layout of a contra-directional coupler and SEM image ofthe DUV fabrication are depicited. The device functions similar to a Bragggrating filter. An additional complexity is introduced in the form of a secondcoupling grating waveguide. As seen from the SEM image, the device isprone to smoothing of the gratings and proximity-effects at coupling regionbetween the two waveguides. The SEM is taken at 65,000x magnificationwith a voltage of 15 kV, current of 50 pA, using secondary electron mode.The SEM was taken at the University of British Columbia.filters placed within coupling range from each other. The coupling distance,referred to as the gap, affects the coupling power between the waveguides:a smaller gap results in substantial increased coupling. Hence, the gap isapproaching fabrication feature size limits. As such, the gap of the contra-DC oftens exhibits proximity effects post-fabrication. Figure 1.10b showsthe DUV fabrication of the contra-DC. The gratings are smoothed in asimilar manner as the Bragg grating filters. The proximity effect can beseen between the two waveguides: The gratings of the coupling region aresmoothed more than the gratings on the outer waveguide edge resultingin a mismatch of the ∆W parameter and thus undesired optical responsechanges.3) Figure 1.11 illustrates the layout of a SWG device. The device con-sists of rectangular silicon structures placed at a fixed spacing (Λ). Thewidths of the rectangles (W ) and the Λ are chosen with respect to the tar-18(a) As-drawn layout. (b) DUV Fabrication.Figure 1.11: The layout and DUV fabrication of a SWG coupler are depicted.The DUV fabrication rounds the gratings noticibly. Furthermore, proximityeffects can be seen; the distance between gratings on both the right sidevary. The SEM is taken at 120,000x magnification with a voltage of 15 kV,current of 50 pA, using secondary electron mode. The SEM was taken atthe University of British Columbia.get operating wavelength. Figure 1.11b shows the DUV fabrication in whichthe rectangular gratings have become oblong due to the smoothing effects.Also, there are proximity effects between each grating of the same waveguideresulting in different gaps between the gratings.To summarize, the examples demonstrate the smoothing and the prox-imity effect. The SEM images depict a clear difference between the as-drawnlayouts and the fabrication. As small geometric changes can greatly reduceoptical performance, it is necessary to develop a lithography model.19Chapter 2Cross-Sectional Analysis ofContra-DCsIn this thesis, the contra-directional coupler (contra-DC) is used as a bench-mark device to verify the lithography model. Since the lithography modelonly considers the aerial shape profile of the device it is important inves-tigate optical performance changes due to the cross-section geometry. Inthis chapter we conduct an analysis on the contra-DC at various sidewallangles and boundary cases of waveguide height variations. We compare thebandwidth and central wavelength to determine which value is unaffected bythe cross-sectional changes and therefore would be suitable to evaluate thetop-down lithography effects of DUV. The values for the sidewall angle andwafer thickness are chosen based on the fabrication process specificationsprovided by the foundry.The results are from 3D-Finite-Difference-Time-Domain (FDTD) simu-lations performed using Lumerical Inc.’s FDTD software. We compare theoptical performance of the contra-directional coupler, specifically the centerwavelength and bandwidth of the device.Two sets of width parameters were used in the contra-DC of this the-sis. As such, an analysis is performed for each of the following: 1) widthsW1,2=560, 440 nm, period Λ=318 nm, gap=160 nm, and corrugation widthsof ∆W1,2=50, 30 nm. 2) widths W1,2=370, 270 nm, period Λ=325 nm,gap=185 nm, corrugation widths of ∆W1,2=60, 50 nm, and a 90 nm highslab layer.Figure 2.1 shows a schematic of how our variations are modelled in thesoftware. Regarding sidewall angles, we measure the angle from the base ofthe device forming a trapezoid cross section. The width of the waveguide isdefined to be located at the center of the structure height-wise, and measuredhorizontally to the opposite edge.Regarding sidewall angles, Table 2.1 provides the range of parametersand the corresponding center wavelengths and bandwidths.Figure 2.2 illustrates the cross-sectional geometry assumed in this analy-sis. Figure 2.3 shows a SEM image of a contra-directional coupler fabricated20Figure 2.1: Orthogonal view of the schematic used for 3D-FDTD simulationsdepicting sidewall angles on the grating faces.in a DUV process, verifying the geometric assumption.We define two figures of merit for simplified comparison: 1) The aver-aged change in bandwidth/central wavelength per change in angle. 2) Theaveraged change in bandwidth/central wavelength per change in waveguideheight.Regarding the sidewall angles, the bandwidths and central wavelengthfor at each angle increment is listed in Table 2.1 for W1,2=560, 440 nm andTable 2.2 for W1,2=370, 270 nm.For a contra-DC of W1,2=560, 440 nm the figures of merit are∆∆λθ =0.012nmθ for the bandwidth and∆λ0θ =0.033nmθ for the central wavelength. Thisindicates that the sidewall does not have significant impact on the bandwidthnor the central wavelength (less than 1 nm per angle in both cases).For a contra-DC of W1,2=370, 270 nm the figures of merit of∆∆λθ =0.026nmθ for the bandwidth and∆λ0θ =0.429nmθ for the central wavelength. Thisindicates that devices using this width parameter have bandwidths that aretolerant to the sidewall angle but the central wavelengths is sensitive tochanges (shifting nearly 0.5 nm per angle).21Figure 2.2: Cross-sectional profile of the contra-directional coupler devicedepicting the sidewall angles. The angle variation locations are labelled ingreen.Figure 2.3: Cross-sectional SEM of a contra-DC demonstrating sidewallangles taken at 64,963x magnification using a voltage of 2.00 kV, currentof 0.10 nA, in back-scatter electron mode. The pocket located between thetwo trapezoidal silicon structures is a manufacturing error. The SEM wastaken at the University of British Columbia.Angle (Θ) Bandwidth (nm) Center Wavelength (nm)90◦ 7.49 1534.6685◦ 7.45 1534.7680◦ 7.47 1534.8875◦ 7.59 1535.14Table 2.1: Bandwidth and central wavelength for a contra-DC of W1,2= 560,440 nm at various angles.Angle (Θ) Bandwidth (nm) Center Wavelength (nm)90◦ 16.63 1351.76585◦ 16.88 1349.5880◦ 16.94 1347.4575◦ 17.02 1345.33Table 2.2: Bandwidth and central wavelength for a contra-DC of W1,2= 370,270 nm at various angles.22Waveguide Height (nm) Bandwidth (nm) Center Wavelength (nm)215 7.53 1528.19220 7.49 1534.66225 7.65 1541.29Table 2.3: Bandwidth and central wavelength for a contra-DC of W1,2= 560,440 nm at various waveguide heights.Waveguide Height (nm) Bandwidth (nm) Center Wavelength (nm)215 16.38 1350.52220 16.63 1351.765225 17.09 1355.645Table 2.4: Bandwidth and central wavelength for a contra-DC of W1,2= 370,270 nm at various waveguide heights.Regarding wafer height variations, we performed a corner analysis us-ing the expected height variation provided by the foundry. The results forW1,2=560, 440 nm are listed in Table 2.3 and Table 2.4 for W1,2=370, 270nm.For a contra-DC of W1,2=560, 440 nm the figures of merit are∆∆λh =0.020nmnm for the bandwidth and∆λ0h =1.31nmnm for the central wavelength. Thisindicates the bandwidth is insensitive to height variations but the centralwavelength is highly sensitive (shifting more than 1 nm per nm of heightchange).For a contra-DC of W1,2=370, 270 nm the figures of merit are∆∆λh =0.071nmnm for the bandwidth and∆λ0h =0.513nmnm for the central wavelength. Thefigures of merit show that the bandwidth remains tolerant to the heightchanges while the central wavelength will have a noticeable change (shiftingby 0.5 nm per nm of height change).From the results we conclude that the bandwidth is insensitive to thesidewall angles and waveguide height variations as each respective figure ofmerit shows insignificant change. Concurrently, the central wavelength hasshown high sensitivity to the sidewall angles and waveguide height variationsin each respective analysis. Hence, the bandwidth of the contra-DC is asuitable choice for verification of the lithography model, as the changes to thebandwidth can be attributed to solely the aerial smoothing and proximityeffects.23Chapter 3Computational LithographyModelThe computational lithography model is built using the known parametersof the 193 nm DUV process, estimated parameters of the process, and fea-ture size measurements obtained from a fabricated test pattern set. Theparameters of the model are optimized such that the error between the pre-dicted feature sizes and the measured feature sizes are minimized. As themodel is built from a fabricated test pattern, it is foundry process specific.However, our methodology in building the model can be applied generallyto any foundry process.The model is built using Mentor Graphics Calibre software [46]. A stan-dardized test pattern set is included in the software. Figure 3.1 shows theSEM of a section of the test pattern. Each test structure in the test patternset has a feature size of interest, e.g., a gap or width, from which we takemeasurements. These feature size measurements are also known as criticaldimension (CD) measurements.3.1 Test Pattern Data ExtractionThe test pattern set consists of 216 structures. The various structures usedare depicted in Fig. 3.2. The structures can be categorized into “solid” and“inverse” structures. Solid structures have the surrounding silicon removedto obtain their shape, as shown in Figs. 3.2a - 3.2h. Their inverse counter-parts are negative imprints of the structure, as shown in Fig. 3.2k - 3.2l. Asthe solid and inverse pairs share the same as-drawn CD, it is anticipated thatthey would fabricate similarly. However, in each case, the as-fabricated CDtrends of the solid and inverse pairs are different. Figure 3.3 shows the trendsA version of Chapter 3 has been published: S. Lin, M. Hammood, H. Yun, E. Luan,N. A. F. Jaeger and L. Chrostowski, ”Computational Lithography for Silicon PhotonicsDesign,” in IEEE Journal of Selected Topics in Quantum Electronics, vol. 26, no. 2, pp.1-8, March-April 2020, Art no. 8201408.24Figure 3.1: The SEM of a section of the test pattern is depicted. This SEMis obtained by stitching together individual SEM images of the patterns eachtaken at a magnification of 5000x, a voltage of 20 kV, and a current of 0.10nA.25(a) Broken H (b) Corner (c) Isolated line pad(d) Dense line end (e) Contact (f) Line end(g) Isolated line (h) Pitch (i) Inverse contact(j) Inverseline end(k) InverseIsolated Line(l) InversepitchFigure 3.2: The types of structure included on the standard test pattern areillustrated. The structures consist of solid structures ([a] to [h]), and inversestructures ([i]) to [l]).26Figure 3.3: The as-fabricated CDs are plotted against the as-drawn CDs forthe structures shown in Fig. 3.2e - 3.2l. Each solid structure and their inversecounterpart have shown different CD trends, indicating different processbiases are required for each type of structure. The simulated CDs are alsoincluded to compare the closeness of the lithography model.27of the as-fabricated CDs for the solid and inverse structures. This indicatesthat different process biases are needed for different structures. Overall,the aim is to capture the photolithography effects on possible shapes thata designer might draw. SEM images are used to obtain the CD measure-ments of each structure on the fabricated test pattern. The measurementsare performed by counting the pixels between the two locations we wish tomeasure. The number of pixels is then converted to SI units using a scaleprovided by the SEM image. The SEM images, shown in Fig. 3.4, 3.7, and3.8, are taken using the Helios NanoLab 650 scanning electron microscopeat a magnification of 5000x, using a voltage of 20 kV, and a beam currentof 0.10 nA. The white borders of the structures in the SEM images (Fig.3.4a) make it difficult to discern where a pixel measurement should be taken.As the white borders are very thick (Fig. 3.4b), a particular measurementdepends on where we define the edge of the structure. To address this prob-lem, our convention uses the average distance of the outer and inner edge ofthe white border. Here we are assuming that the white borders occur dueto sidewall angles cause by fabrication processes [47] and that the sidewallshave a linear slope from the top to the bottom of the structure.(a) Square hole test structure500 nm(b) Magnification of the edgeFigure 3.4: (a) An SEM of an Inverse Contact structure. (b) A zoom-in il-lustrating the thick white border can create CD measurement discrepancies.Our convention is to use the average distance between the outer and inneredge of the border.283.2 Model OptimizationCalibre provides an optimization function which operates by adjusting thelithography model parameters within the aforementioned range. The op-timization aims to minimizes the error between the predicted CD and theas-fabricated CD. The model’s inputs are the optical lithography wavelengthand each test pattern’s measured CD. The optimized output produces 4 pa-rameters of the lithography model: 1) the optical wavelength of the DUVprocess; 2) the NA, which is a dimensionless number that describes theranges of angles of the projection lens seen from the position of the wafer;3) the σ, defined as the fraction of the NA of the projection lens filled bythe illuminating beam [46]; and 4) the δσ, defined as the delta ranges fromwhich the intensity of the optical beam rises from 0.5% to 99.5% [46]; and5) the threshold value, defined as the percentage of the computed illumina-tion which is applied.The optical wavelength is known for the 193 nm DUV dry-etch process.Unfortunately, the NA, σ, δσ, and the exposure threshold, are not publiclyavailable. Hence, we instead refer to values given in previous publicationsfor similar processes [48][49][7] to determine a range for optimization.The optimization is performed by sweeping the NA, σ, and δσ param-eters, and generating a lithography prediction of the test patterns. Thesweep aims to obtain the lowest error root-mean-square value for the pre-dicted CDs versus the as-fabricated CDs. Figure 3.5 plots the NA sweepversus the error root-mean-square value. The sweep is performed in a 3-dimensional search space (as we are optimizing three parameters, the NA,σ, and δσ values). The parameters starting point begin at NA = 0.6 σ = 0.6,and δσ = 0 of which the NA and σ values reported from a previous publi-cation [8]. The ranges for the sweeps are chosen from values reported in theliterature [48][49], as well as being based on our own estimations.The equation for the error root-mean-square is shown in Equation 3.1.Wi is the weight value for each CD measurement, CDsim is the CD measure-ment prediction by the model, and CDmeas is the measured CD obtainedfrom SEM images.ErrorRMS =√∑iWi(CDsim − CDmeas)2∑iWi(3.1)During each sweep of the optimization, the optical parameters are usedto generate a computed illumination of a structure’s mask, as shown in Fig.3.6b. Next, a lithography prediction is generated using a threshold value.29Figure 3.5: A 1-dimension search (varying numerical aperture) is presented.The error root-mean-square is plotted against the numerical aperture. Theerror root-mean-square is obtained by comparing the lithography predictionsof the model to the CD measurements. The search aims to obtain theparameter value which produces the minimal error root-mean-square value.In the plot, the optimal value for NA is 0.67 with an error root-mean-squareof 5.237 nm. The entire model building process performs this search in3-dimensions (varying NA, σ, and δσ).30The threshold value is the percentage of the predicted illumination that willbe applied to the structure. The optimization will select the threshold valueproducing the best fit (Fig. 3.6c). The error between the CD measurementsare then evaluated against errors from previous sweeps. The optimizationcontinues until a combination of parameters with the minimum error is found(Fig. 3.6d). The optimized lithography model has the following parameters:NA = 0.671, σ = 0.884, δσ = 0.882, and threshold = 0.165.(a) Mask (b) Optical (c) Threshold (d) OutputFigure 3.6: Steps to optimize the lithography model: (a) the ideal as-drawnmask. (b) the computed illumination generated using the optical wave-length, NA, σ, and δσ. (c) the selection of the threshold value, shown inred. (d) the predicted post-lithography output.3.3 VerificationIn this section we verify the lithography model using two comparison meth-ods. First, we visually evaluate the accuracy of the lithography model. Wecompare the overall shape and CD measurements of predicted structuresto those of the as-fabricated structures obtained from SEM images. Sec-ond, we compare the optical responses of contra-DC devices. The simulatedresponses of the as-drawn designs and the predicted designs are comparedagainst experimental responses.As regards the visual verification, Fig. 3.7 shows the Broken H structurewhich has an as-drawn gap of 120 nm. The computational lithography31results predict a gap of 182 nm. The predicted gap (182 nm) closely matcheswith the fabricated gap (181 nm) shown in SEM images. Other features,such as the end roundings, are common to both the predicted and fabricatedstructures. Figure 3.8 shows a Corner structure predicting the effects onclose-proximity corners. In this structure, the as-drawn gap between thetwo tips of the corners is 150 nm. Our computational lithography predictsa gap of 214 nm. This is very similar to the SEM image which shows a gapof 210 nm. Visually, the output of the computational lithography modelcorresponds very closely to the as-fabricated test patterns.Figure 3.3 shows a plot of the CD of the contact, line end, isolated line,and pitch patterns (note the change in scale for the vertical axis of the pitchpattern). The model is able to produce results comparable to the measuredCD. However, the models predictions are less accurate for the inverse lineend pattern; The cause for this requires further investigation.As regards the optical response, Fig. 3.9 illustrates the schematic of acontra-DC device. The device consists of two coupled Bragg-grating waveg-uides. The bandwidth of the contra-DC is sensitive to the corrugation widths(∆Ws), e.g., small changes in the ∆W will cause large changes in the band-width. The contra-DCs used in our comparison have the anti-reflectionconfiguration described in Ref. [50]. Each contra-DC consists of two waveg-uides with different widths, and, hence, different propagation constants. Themain band of each contra-DC will be centered at an operating wavelengthat which the phase-match condition [18][50] is satisfied.However, two side-bands, known as the self-reflection (SR) bands, willexist next to the “main band” for the contra-directional coupling on thecontra-DC [50]. The SR bands occur due to each mode of the two waveguideshaving their own propagation constants leading to the conventional single-waveguide Bragg reflection at a wavelength of λ1,2 = 2neff 1,2λ0, where neff 1,2correspond to the effective indices for the waveguide modes located mainlyin waveguide 1 and 2, respectively. For broad spectrum applications, thereis an appeal to reduce the SR as the SR bands limit the operating spectralranges.Figure 3.10 demonstrates the photolithography effects on the contra-DC.Coupling gaps can increase and ∆Ws of the device can become mismatchedbetween the inner and outer portions. As the asymmetry between the ∆Wsincreases, the SR bands on the drop-port of the contra-DC become increas-ingly prominent. As the SR bands are related to the individual modes,and by extension the waveguide widths, small variations in the ∆Ws, gap,and widths, will significantly change the main bandwidth and the SR band-widths [50]. In our experimental results, the SR bands are approximately3240 nm away from the main band. Due to measurement limitations, we willbe comparing SR nulls bandwidth at the shorter wavelength.The simulated response of the as-drawn device is not accurate enoughto match the as-fabricated result, as demonstrated in Fig. 3.11 for themain band and Fig. 3.12 for the SR band. Thus, it is apparent that thephotolithography effects of the fabrication process have heavily impactedthe contra-DC’s performance.Using the lithography model, we predict the resulting shape of the contra-DCs after photolithography effects have been taken into account. The pa-rameters of each of our contra-DCs are listed in Table 3.1. We perform aFinite-Difference-Time-Domain (FDTD) simulation using Lumerical Inc.’sFDTD software and bandstructure method [17]. The coupling coefficient,kappa, and bandwidths are extracted from the bandstructure. The contra-DC response is then simulated using kappa and a Couple-Mode-Theory-Transfer-Matrix-Method based model [26][22][51]. We calculate the nullsbandwidths of the experimental results listed in Table 3.2 and Table 3.3using the nulls method [52].Figure 3.11 shows the main band response of our CDC3 device. The as-drawn simulation (Fig. 3.11a) shows an ideal bandwidth of 11.5 nm. Our as-predicted simulation (Fig. 3.11b) shows a reduced bandwidth of 5.6 nm. Theactual (experimental) bandwidth of 6.4 nm (Fig. 3.11c) closely correlateswith the predictions of the lithography model.Furthermore, Fig. 3.12 shows the SR band response of our CDC3 device.The drop-port response is illustrated for readability purposes. In the idealas-drawn simulation, the SR bandwidth is shown to be 11.1 nm (Fig. 3.12a).Using the lithography model, we predict that the bandwidth will be reducedto 6.0 nm (Fig. 3.12b). The experimental result, shown in Fig. 3.12c, has aSR bandwidth of 5.4 nm.Figure 3.13 and Figure 3.14 show the main band nulls bandwidths andthe SR band nulls bandwidths respectively, for the as-drawn simulation, theas-predicted simulation and the experimentally measured results. The idealas-drawn simulations include process width variations from Ref. [53]. Eachas-predicted simulation showed a significant improvement in accuracy overthe as-drawn simulation for both the main nulls bandwidth and the SR nullsbandwidth.33(a) Test Pattern182(b) Simulation (c) FabricatedFigure 3.7: A Broken H structure is depicted. The CD location is betweenthe two center protrusions and captures how small grating-like structureswill be effected by photolithography. The CD predicted by our method (b)is nearly identical to the fabricated one (c).150 nm(a) Test Pattern214 nm(b) Simulation (c) FabricatedFigure 3.8: The Corner structure, which captures how two corners interactwhen in close proximity, is depicted. The resulting CD from our simulationis highly similar to that of the fabricated one.34Figure 3.9: The schematic of a contra-DC, with the design parameters andthe four ports labeled. A single segment block of the Bragg grating with apitch (Λ) is repeated to obtain a desired length. There are two corrugationwidths (∆Ws), which will often be affected differently by the fabricationprocess.Table 3.1: Contra-DC ParametersDeviceNameΛ(nm)Width 1(nm)Width 2(nm)Gap(nm)∆W 1(nm)∆W 2(nm)Length(µm)CDC1 270 370 270 175 60 50 270CDC2 270 370 270 178 60 50 270CDC3 325 370 270 185 60 50 325CDC4 325 370 270 182 60 44 32535(a) Ideal Mask (b) As-Predicted MaskFigure 3.10: (a) A simplified contra-DC design, with symmetrical waveguidewidths and ∆Ws to demonstrate the smoothing and the proximity effectsof photolithography. (b) The post-fabrication changes in the gap, ∆Winner,and ∆Wouter dimensions are depicted, showing a large asymmetry betweenthe ∆Ws. The size reduction of ∆Winner is due to both the smoothing, andproximity effects, where as the size reduction of ∆Wouter is only due to thesmoothing effect.36(a) Simulated main band response ofthe as-drawn contra-DC(b) Simulated main band response ofthe as-predicted contra-DC(c) Measured main band response of the fabricated contra-DCFigure 3.11: The main band nulls bandwidths of CDC3. (a) The as-drawn layout, (b) the lithography model as-predicted, and (c) the DUVas-fabricated, are depicted. The as-drawn simulated nulls bandwidth is11.5 nm, the as-predicted nulls simulated bandwidth is 5.6 nm, and theas-fabricated measured nulls bandwidth is 6.4 nm. The noise floor of c) isdue to instrument measurement limitations.37(a) As-drawn (b) As-predicted (c) FabricatedFigure 3.12: The SR nulls bandwidths of (a) the as-drawn, (b) the as-predicted, and (c) the as-fabricated, are depicted. The as-drawn simulatedbandwidth is 11.1 nm, the as-predicted simulated bandwidth is 6.0 nm, andthe as-fabricated measured bandwidth is 5.4 nm.38Figure 3.13: The contra-DC main band nulls bandwidths for the as-drawn(blue I-bars), the as-predicted (red squares), and experimentally measured(black triangles) contra-DC devices are plotted. The data values can befound in Table 3.2.Table 3.2: Contra-DC main band BandwidthsDeviceNameIdealAs-Drawn(nm)LithographyAs-Predicted(nm)Experimental(nm)CDC1 9.9 ± 0.22 3.6 4.3CDC2 7.6 ± 0.68 3.2 3.9CDC3 11.5 ± 0.85 5.6 6.4CDC4 11.4 ± 0.22 5.7 8.039Figure 3.14: The contra-DC self-reflection band nulls bandwidths for theas-drawn (blue I-bars), the as-predicted (red squares), and experimentallymeasured (black triangles) contra-DC devices are plotted. The data valuescan be found in Table 3.3.Table 3.3: Contra-DC SR-band BandwidthsDeviceNameIdealAs-Drawn(nm)LithographyAs-Predicted(nm)Experimental(nm)CDC1 5.6 ± 0.009 1.8 2.2CDC2 6.4 ± 0.051 1.7 2.6CDC3 11.1 ± 0.134 6.0 5.4CDC4 10.4 ± 0.190 4.8 6.140Chapter 4Designing forManufacturabilityHere, we demonstrate the application of the lithography model for preemp-tive compensation of fabrication changes and present two ideas for improv-ing manufacturability on the deep-ultra violet (DUV) process are explored.First, the potential for using the Electron Beam Lithography (EBL) processin conjunction with the lithography model to emulate a DUV lithographyprocess is discussed. The method takes advantage of the small feature sizecapabilities of EBL to precisely fabricate the predicted shapes from thelithography model. Second, the designer-side compensation for lithographyeffects is presented. Using a contra-directional coupler (contra-DC) designpresented previously for verification, the lithography effects predicted by themodel are analyzed and the contra-DC design is modified to counteract thelithography changes.4.1 DUV-Emulation using EBLEBL is a popular fabrication process well-suited for rapid-prototyping withfeatures such as fast fabrication cycles, small minimum feature sizes, andlow cost. However, given the nature of the EBL process, it has a longerpatterning time and is unsuitable when the production volume is large. Tomake the leap to commercialization, silicon photonic devices would need torely on optical lithography processes, such as DUV, which are capable ofhandling large volume fabrications. Unfortunately, DUV lithography hasdifferent limitations than EBL such as lithography effects which makes de-vices difficult to produce with the DUV process. Furthermore, DUV hashigh production costs and longer fabrication cycles than EBL, effectivelyinhibiting its use as a rapid-prototyping process.However, with the lithography model demonstrated in the previous chap-ters, the EBL process has the potentially to be used as an intermediate stepfor the DUV emulation method. The method uses the lithography model41to simulate a DUV fabrication outcome. The simulated result is then fabri-cated via EBL. Alterations can be considered after obtaining measurementsand the iteration cycle can then be repeated. Ultimately, when there is con-fidence in the device’s success, designers can then decide to invest in a DUVprocess, consequently, reducing the overall cost of prototyping for device tobe fabricated using the DUV process.To evaluate our emulation method, we compared the bandwidths of mul-tiple Bragg filter and contra-DC devices. We fabricated the devices usingthe EBL and DUV processes. We also fabricated our lithography predic-tions using the EBL process (which we will be referring to as EMU). TheBragg filters have parameters: W=500 nm, Λ=318 nm, and a sweep of thecorrugation ∆W from 20 to 105 nm. The contra-DCs used have parameters:W1,2=560, 440 nm, Λ= 318 nm, ∆W1,2= 50, 30 nm, G = 220 nm.Figure 4.1 shows the bandwidths of the Bragg filter devices. The EBLmeasurements are plotted in blue, the DUV measurements are plotted inpurple, and the EMU measurements are plotted in orange. Using the EBLbandwidths as a baseline for comparison, the DUV bandwidths are notice-ably smaller. This is expected as the corrugation widths of gratings arecharacteristically reduced in the DUV process. The EMU bandwidths showgood agreement with the DUV results, verifying that the emulation methodcan recreate the DUV lithography effects on the EBL process.Figure 4.2 shows the SEM images of a device from the Bragg filter setcomparing the three fabrications. We can see in the EBL image that thegratings are square-like as previously mentioned. Furthermore, we can seevery similar results in the smoothed profile of the gratings in the EMU andDUV sets.Figure 4.3 plots the main bandwidths versus the ∆∆W2 of the contra-DCdesigns. The three fabrications are compared here to evaluate the validityof the emulation when proximity effects affect the device. Once again, theEBL results are shown in blue, the DUV results are shown in purple, andthe DUV-emulation (EMU) are shown in orange. From the plot, we can seethat the EMU results closely match the DUV results, indicating that theemulation is also properly emulating the proximity effects.Figure 4.4 shows the SEM images of the contra-DC throughout the threefabrications. Here, we can see that the EBL fabrication (left) yielded idealgratings that are nearly square. The EMU device (center) shows that thegratings are reduced significantly, rounded, and a mismatch occurs betweenthe outer and inner gratings. The DUV fabrication (right) matches up veryclosely with the EMU and also shows the fabrication variations predicted forthe EMU device. Note that there are differences between the EMU and DUV42Figure 4.1: The bandwidths vs. corrugation width of a Bragg filter devicecomparing the difference between fabrications and the emulation of the DUVfabrication process (EMU).Figure 4.2: SEM images of the EBL fabrication (left), DUV-emulation(EMU) (center), and DUV fabrication (right) is shown. The EMU showshigh similarity with the actual DUV fabrication. The EBL and EMU imageswere taken using 13,900x magnification, voltage of 15 kV, and a working dis-tance of 6.7 mm. The DUV image was taken using 25,000x magnification,voltage of 15 kV, current of 50 pA, with secondary electron mode. Theimages were resized to the same scale using the pixel distance provided.43Figure 4.3: The main bandwidth versus mismatch corrugation width is plot-ted. The main bandwidth is expected to remain negligibly unchanged as thecorrugation mismatch increases. The EBL fabrication design (blue) showsthis stable trend. The DUV fabrication (purple) also shows this trend witha reduction in bandwidth due to the fabrication variations. The emulationfabrication (EMU) (orange) closely follows the DUV results, demonstratinggood agreement between the emulation and the actual DUV fabrication.devices near the inner corrugation, indicating potential for improvement.Our comparisons show that DUV-emulation using EBL fabrication isa viable method. The method provides a substantial improvement for therapid-prototyping process of DUV devices. Using this method, designers areable to obtain measurement data of their devices at a low cost.44Figure 4.4: The SEM images of the three fabrications of the contra-DCdevices are shown. The EBL contra-DC (left) shows balanced corruga-tions, and orthogonal corrugation profiles. The emulation (EMU) of theDUV-process (center) shows smoothed and reduced corrugations with mis-matched corrugations. The DUV fabrication (right) is closely resembles bythe EMU, demonstrating smoothed & reduced corrugations, and an obviousmismatch between the inner and outer corrugations. However the EMU stillslightly differs from the DUV, specifically between the inner corrugations,and requires further investigation and improvement. The EBL and EMUSEM images are taken at a magnification of 37,720x, voltage of 15 kV, anda working distance of 6.7mm. The DUV SEM simage was taken at a mag-nification of 65,000x, voltage of 15 kV, current of 50 pA, using secondaryelectron mode. The images were adjusted to the same scale using the pixelmeasurement provided by the images.454.2 Self-reflection Surpression via MismatchedCorrugationsThe contra-directional coupler (contra-DC) exhibits side-bands known as“self-reflections” which are wavelengths innately supported by each indi-vidual grating waveguide in the contra-DC system. The side-bands are alimiting factor to the contra-directional coupler’s capabilities as describedin Section 1.1.2. Anti-reflection gratings [50] have been demonstrated withsuccess in reducing the self-reflection and are used in many recently proposedgrating devices [54][55][45].It is speculated that the reduction of the self-reflection bandwidth canbe further reduced, or perhaps even eliminated completely. During mea-surements of contra-DC devices fabricated using DUV, it was noticed thatmismatches in corrugations (∆∆W = ∆Wouter −∆Winner) cause the band-widths to change. A diagram of the definition for ∆Wouter and ∆Winner isshown in Fig. 4.5, 3D-FDTD simulation sweeps were performed to inves-tigate the effects of ∆∆W . Figure 4.6 shows that the bandwidth changeswith mismatched corrugations as observed experimentally. However, an in-teresting phenomenon in which the self-reflection bandwidth is minimizedto beyond detection of the FDTD simulations (being on the orders of pi-cometers) was illustrated. This minimization is simulated to occur when∆∆W2=-10 nm for a contra-DC with parameters: Λ = 318 nm, G = 160nm, W1 = 560 nm, W2 = 440 nm, ∆W1 = 50 nm, and ∆W2 = 30 nm.In this case, the ∆∆W was applied only to the smaller waveguide to re-duce the self-reflection bandwidth at the lower wavelength. This is duethe measurement equipment limitations only being capable of capturing theself-reflection bandwidth at the lower wavelength. Simulations of the the∆∆W being applied to the larger waveguide are included in Fig. 4.7, butmeasurements were unable to be obtained for comparison due to equipmentlimitations.The designs were fabricated using EBL and the main bandwidth and self-reflection bandwidth were measured. Figure 4.8 shows the FDTD simulatedself-reflection bandwidth alongside the experimental measurement. When∆∆W2 = -10 nm, the simulation and measurement are in agreement, show-ing a complete suppression of the self-reflection bandwidth. Figure 4.9 showsthe measured bandwidth of the as-drawn layout and the DUV-emulated lay-out. When DUV lithography effects are added, a shift in the trend towardsthe right is observed, indicating that the maximum suppression exists at∆∆W2 = 0 nm. The optical response showing full self-reflection suppres-46Figure 4.5: The layout with the definitions for Wouter and Winner for thenarrow waveguide (W1) and the wide waveguide (W2).sion can be found in Fig. 4.11b for the ∆∆W2 = -10 nm, and Fig. 4.12 forits lithography emulated counterpart.Figure 4.10 plots the main bandwidth of the FDTD simulation, the as-drawn layout, and the emulated layout. It is observed that the main band-width remains stable throughout the ∆∆W2 sweep. The addition of DUVlithography effects reduces the overall bandwidth across the devices, but thetrend of a stable main bandwidth remains.In conclusion, the experimental measurements confirm the simulationresults of an optimized design in which the self-reflection can be fully sup-pressed. The simulations also demonstrate that the method can be used onboth waveguides simultaneously to reduce the self-reflection of each waveg-uide with minimal losses to the main bandwidth; This remains to be con-firmed experimentally. Lastly, it should be noted that the amount of ∆∆Wsuppression is dependent on the parameters chosen for the contra-DC.47Figure 4.6: The simulated bandwidths of ∆∆W2 from -30 to 30 nm is de-picted. The main band bandwidth (orange) shows a horizontal trend indi-cating minimal influence from ∆∆W2. The self-reflection bandwidth (blue)shows a decrease as the outer corrugations becomes smaller than the innercorrugations. A minimum is observable around ∆∆W2 = -10 nm.4.3 Compensating for Lithography EffectsUsing the predicted lithography effects obtained from the lithography model,we perform a redesign of CDC3. Our aim is to produce a predicted resultin which the gap and the ∆Ws match the intended parameters. First, wedecrease the distance between the two waveguides, as we know that thelithography effects will widen gap. Next, we increase ∆Winner while tak-ing note that our changes will also effect the gap. Finally, we increase∆Wouter until the predicted result for ∆Wouter is equal in size to the pre-dicted ∆Winner. This process is repeated until the prediction achieves ourobjective, i.e., the gap=185 nm and ∆W=50, 60 nm for the top and bottomwaveguides, respectively.Figure 4.13c shows the CDC3 redesign with parameters: gap=179 nm,top waveguide corrugations of ∆Winner=67 nm & ∆Wouter=78 nm, and48Figure 4.7: The simulated bandwidths of ∆∆W1 from -50 to 30 nm is de-picted. The main band bandwidth (orange) shows horizontal trend. Theself-reflection bandwidth (blue) shows a gradual decrease in bandwidth. Aminimum bandwidth below 1 nm occurs around ∆∆W1 = -30 nmbottom waveguide corrugations of ∆Winner=80 nm & ∆Wouter=88 nm. Thepredicted result for this redesign shows that the gap and ∆Ws will have theoriginally intended values, see Fig. 4.13d.The main bandwidth response of the original device and the redesigneddevice are shown in Fig. 4.14a and Fig. 4.14b respectively. Comparisonof the two bandwidths indicate that the bandwidth will be improved andcloser to the ideal simulation when the redesign method is applied.49Figure 4.8: The simulated results (purple) are compared against the mea-sured bandwidths (blue) of the devices using as-drawn layouts. The trendfollows closely with the simulations, demonstrating as suppressed self-reflection when ∆∆W2 = -10 nm.Figure 4.9: The responses of the as-drawn layout (blue) and the lithography-emulated (EMU) (orange) devices are compared. The complete suppressionis visible in both measurement results. The lithography-emulated devicesalso show a rightwards shift.50Figure 4.10: The main band bandwidths of the FDTD simulation (purple),as-drawn layout (blue), and lithography-emulated (EMU) layout (orange)are shown. The as-drawn bandwidths agree with the FDTD simulations,confirming that the main band bandwidths have not changed when usingmismatched corrugations. The EMU results indicate that the main band-width will be reduced by around 2 nm when DUV-lithography effects areintroduced.51(a) ∆∆W = 0 nm(b) ∆∆W = -10 nmFigure 4.11: The measured spectrum of the EBL fabricated corrugationmismatched contra-DC devices. The control for the experiment (∆∆W2 =0 nm) is depicted in (a) and the device demonstrating successful bandwidthsuppression is depicted in (b).52Figure 4.12: The DUV-lithography emulation (EMU) response of ∆∆W2= 0 is shown. The measured response indicates that when smoothing isconsidered, the suppression of the self-reflection will occur with the nominaldesign parameters.5360 nm60 nm(a) As-drawn design (b) As-drawn prediction88 nm78 nm67 nm80 nm179 nm(c) DFM redesign (d) Redesign predictionFigure 4.13: (a) The as-drawn gap and ∆W parameters of CDC3 is shown.(b) A lithography prediction of the as-drawn parameters. The results showasymmetry for the ∆Ws and a larger gap. (c) A redesign of CDC3 usingthe information obtained from (b). (d) The lithography prediction of theredesigned CDC3. The results indicate that the ∆Ws and gap sizes willmatch the original as-drawn values.54(a) Ideal (b) RedesignFigure 4.14: The simulated main bandwidth response of the CDC3 idealdesign (Fig. 4.13a) and redesign (Fig. 4.13d) using 3D-FDTD. The band-width of the ideal design is 11.5 nm and the bandwidth of the redesign is9.8 nm. A significant improvement over the as-fabricated bandwidth of 6.4nm (demonstrated in Fig. 3.11c) when the device undergoes a redesign tocompensate for lithography effects.55Chapter 5Summary, Conclusions, andSuggestions for Future WorkA lithography model was built from test patterns fabricated using a 193nmDUV process. The model demonstrated good agreement with experimen-tal results and is able to predict lithography effects for any input shape.Methods to improve prototyping of DUV devices enabled by the model suchas DUV-emulation and lithography compensation were demonstrated. TheDUV-emulation method would provide designers with measurement dataprior to investing in a DUV fabrication. The lithography compensationmethod is a feedback design loop allowing designers to iterate their devicesto become fabrication tolerant. Both methods are cost efficient and com-patible with standard simulation methods such as FDTD.5.1 ConclusionThe results presented in this thesis demonstrated that a lithography modelfor a 193 nm DUV fabrication process can be built using fabricated testpatterns. The lithography model’s predictions are accurate in both visualcomparisons to SEMs of the test patterns it was built from and opticalresponse comparisons with a benchmark contra-DC device.It should be noted that the lithography model presented in this thesisanalyzes the lithography effects through an aerial top-down perspective. Inreality, designers will find that the lithography effects are more complex as itis the 3-dimensional geometry that changing. Thus, it is crucial to considerthe cross sectional shape as well, namely sidewall angles and wafer heightvariations.For this thesis, a cross-sectional analysis for the benchmark contra-DCdevice was performed and it was determined the bandwidth response of thecontra-DC device is highly resilient towards the cross-sectional lithographychanges. A simplified explanation to this is that the waveguide widths usedare sufficiently wide allowing the light to remain fully confined even when56sidewalls are extreme and/or the waveguide widths are at their extremes.The detailed analysis of the sidewall angles and wafer height variation canbe found in Chapter 2. As such, when using the lithography model, it isimportant perform a separate optical analysis for the sidewall angles andthicknesses variations.Additionally, when designing devices containing cavities, larger cavitysizes are more likely to be fabricated successfully. In a second fabrication ofthe same 193 nm DUV process use to build the lithography model, devicescontaining cavities were not fabricated properly. The devices analyzed werecontra-DCs with a cavity design [26] and are shown in Fig. 5.1. Figure5.1a shows the layout of the contra-DC which has a cavity size of 160 nm.This width is within the safe limit of the DUV fabrication. The lithographyprediction, as shown in Fig. 5.1b, predicts a hole of 88 nm to be fabricated.However, as shown in Fig. 5.1c, the fabrication did not produce any cavitiesof the contra-DC.The cavity test pattern was subsequently analyzed. The layout is shownin Fig. 5.2a has a gap of 180 nm which is also within the safe limits of thefabrication. Figure 5.2b shows the fabricated test pattern on the first DUVfabrication (of which the lithography model was built from). The cavity wasproperly produced on this run with a size of 83 nm. Figure 5.2c shows thesame pattern from the second fabrication. Here, the test pattern did nothave a cavity. Further investigations with support from the foundry wouldbe required to properly draw any conclusions.Designers looking to use the lithography model should compensate forthe model’s limitations by conducting cross-sectional analysis of their de-vices similar to what is shown in chapter 2. For devices with cavities, in-cluding a test pattern and/or a small section of the device can provide moreinformation of the lithography effects via SEM imaging.5.2 Suggestions for Future WorkThe lithography model demonstrated in this thesis has potential for furtherimprovement. The following are three suggestions of future work: 1) increasethe number of data sets the model is built from, 2) automating the SEMCD extraction process, and 3) developing a 3D lithography model by com-bining the cross-sectional variations and the lithography model predictions.These suggestions would greatly improve the accuracy of the lithographypredictions and usability of the model.First, the amount of data provided to the model should be increased.57(a) GDS Schematic (b) Lithography Simulation(c) SEM ImageFigure 5.1: (a) The schematic of a contra-DC using a cavity design is de-picted. The cavity has a size of 160 nm which is within the fabrication’sguaranteed ranges. (b) A lithography simulation of the schematic showingthat the cavities should be fabricated with a size of approximately 88 nm. (c)An SEM of the cavity-based contra-DC. The image was taken with 65,000xmagnification, voltage of 15 kV, current of 50 pA, using secondary electronmode. The image shows that the cavities of the contra-DC were unresolveddespite the schematic using conservative feature sizes and the lithographysimulation indicating resolving of cavities.58(a) GDS Schematic(b) First DUV Fabrication (c) Second DUV FabricationFigure 5.2: (a) The GDS schematic of the ”inverse contact” test pattern,aimed at capturing the fabrication of cavity structures. The cavity has asize of 180 nm. (b) A SEM of the test pattern from which the lithographymodel was built upon. The cavity is successfully resolved at 83 nm. (c) ASEM of the test pattern from a second run of the same process in whichcavity has failed to resolve.59Currently, the model is built from a single data set from one fabrication ofthe 193 DUV process. Additional data from test patterns could improvethe accuracy of the predictions. A collaboration with the foundry wouldprovide an even greater improvement via the sharing of process parameters.If provided with the process parameters, the model could more accuratelysimulate the optical and resist process, resulting in improved lithographyeffect predictions. It should be noted that the turn-around time for a DUVfabrication can be a limiting factor. Furthermore, for accurate CD measure-ments, the test patterns require an open-oxide area which might require adedicated chip.Second, the extraction of CD measurements is currently a very time con-suming task. A method should be developed by combing image processingwith edge-finding algorithms to extract the measurements automatically.This would reduce the data collection time, standardize the data collectionmethod, and remove potential for human error. Figure 5.3 shows a mockup of the automatic extraction process. The challenge of this task occursin image processing. Either all the SEM images would need to have similarexposure, hence allowing the software to easily determined a threshold valueand find the edges of the patterns, or a dynamic thresholding algorithm canbe developed to process SEMs that differ in contrast and pixel noise.(a) SEM Image (b) Threshold Corrected (c) Edge FindingFigure 5.3: A mock up of an automatic CD extraction procedure. The inputimage a) is processed by a thresholding algorithm to clean up the contrastand pixel artifacts. The output is shown in b). Finally, an edge-finding isperformed to map out the shape and obtain the CD measurement, as shownin c).Lastly, a 3D lithography method/model should be developed combiningthe methodologies presented in this Chapter 2 and Chapter 3. The cross-section information can be obtained using a Focused Ion Beam machine.60With the cross-section width, height, and sidewall angle known, devices canbe simulated using the lithography model, and then created in 3D using thecross-section information. The realistic 3D geometry would allow accurateFinite-Difference-Time-Domain (FDTD) simulations using software such asLumerical FDTD.61Bibliography[1] Mustafa Hammood, Ajay Mistry, Minglei Ma, Han Yun, Lukas Chros-towski, and Nicolas A. F. Jaeger. Compact, silicon-on-insulator, series-cascaded, contradirectional-coupling-based filters with >50db adjacentchannel isolation. Opt. Lett., 44(2):439–442, Jan 2019.[2] Tom Baehr-Jones, Ran Ding, Yang Liu, Ali Ayazi, Thierry Pinguet,Nicholas C. Harris, Matt Streshinsky, Poshen Lee, Yi Zhang, Andy Eu-Jin Lim, Tsung-Yang Liow, Selin Hwee-Gee Teo, Guo-Qiang Lo, andMichael Hochberg. Ultralow drive voltage silicon traveling-wave modu-lator. Opt. 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                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            data-media="{[{embed.selectedMedia}]}"
                            async >
                            </script>
                            </div>
                        
                    
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