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Ultra-low-power event-driven radio system for miniaturized biomedical implants Cai, Mengye 2019

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  Ultra-Low-Power Event-Driven Radio System for Miniaturized Biomedical Implants  by  Mengye Cai  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY in THE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES (Electrical and Computer Engineering)    THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver)  October 2019  © Mengye Cai, 2019  ii  The following individuals certify that they have read, and recommend to the Faculty of Graduate and Postdoctoral Studies for acceptance, the dissertation entitled:  Ultra-Low-Power Event-Driven Radio System for Miniaturized Biomedical Implants  submitted by Mengye Cai in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering   Examining Committee: Shahriar Mirabbasi Supervisor  Kenichi Takahata Supervisory Committee Member   Supervisory Committee Member Mu Chiao University Examiner Peyman Servati University Examiner  Additional Supervisory Committee Members:  Supervisory Committee Member  Supervisory Committee Member iii  Abstract  The aggressive scaling of the CMOS technologies has made it possible to implement denser, cheaper, higher performance and lower power integrated circuits (ICs) for a widespread of applications. Among these applications in various implantable medical devices (IMDs) such as cochlear implants, capsule endoscopy, brain-machine interface, and smart stents, telemonitoring and wireless communication are key functions. The radio-frequency (RF) communication systems for IMDs differ from conventional data-driven radios in various aspects including form factor, power consumption, communication range, and operation manner. The focus of this thesis is on exploring novel circuit- and system-level design techniques for monolithic CMOS wireless event-driven radios intended for miniaturized biomedical implants.  To fulfill the stringent power requirement, conventionally various forms of envelope-detection-based receivers are used. However, such receivers suffer from inferior sensitivity and also need calibration or external components, which are not amenable solutions for IMDs. To address these issues, a crystal-less receiver that employs a programmable envelope detector to provide a better trade-off between sensitivity and power consumption is presented. Furthermore, a double-mixing receiver is robust to process, supply voltage and ambient temperature (PVT) variations. By suppressing flicker noise and DC offsets, the proposed architecture while achieving an improved sensitivity eliminates the need for external components and calibration.  There are typically three wireless links existing in an implantable radio system, the uplink, the downlink, and the power link. In this work, the up- and down-stream datalinks are realized by exploiting 915 MHz frequency band using time division duplexing (TDD) that is manipulated by a smart control module, while remote power link is realized in the 2.4 GHz band. Without any iv  external components and calibration overhead, the radio is also robust to PVT variations, leading to a low-cost and highly integrated wireless node. To confirm the validity of the proposed technique, proof-of-concept prototypes have been designed and fabricated. All prototype circuits have been implemented in CMOS technology and have been successfully evaluated. The applications of proposed techniques are not limited to IMDs and they can also be used in other applications where energy resources are constrained and/or low power operation with miniaturized size are required.  v  Lay Summary  The ongoing trend towards miniaturized biomedical implantable systems calls for alternative implementations with higher levels of integration to avoid external components and minimize the size, and reduce the power consumption, without sacrificing the overall performance.    In this thesis, several design techniques are investigated, and various system- and circuit-level approaches are proposed to meet the size and power requirements of biomedical implantable devices. Two receiver prototypes are presented that have improved sensitivity and lower hardware cost as compared to those of the state-of-the-art while consuming a low power, and having a small form factor and improved performance. The proposed solutions also have a great potential for other low-power applications such as Internet of Things.  vi  Preface  All the content presented in this thesis are original, independent work conducted in System-on-a-chip (SoC) lab by the author, Mengye Cai.  The circuit design techniques described in Chapter 2 were designed preliminary by me. CMC Microsystems provided access to the computer aided design (CAD) tools as well as to the fabrication technology. We taped out three different chips using a 0.13-μm CMOS process. The research was my own work and I wrote the manuscripts under the supervision and editorial assistance of Professor Shahriar Mirabbasi.   A version of Chapter 3 has been published in the following two conference papers: 1. M. Cai, R. Sobot, and S. Mirabbasi, "A 32-μW Programmable Crystal-less Event-driven Receiver for Miniaturized Biomedical Implants," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-4. 2. M. Cai, K. Fricke, and R. Sobot, "Embedded RF switch for implantable telemetry systems designed in 130nm CMOS," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 2735-2738. I was the leading investigator in developing the concept, designing the circuit and testing it. My colleague K. Fricke gave editorial assistance. Professor R. Sobot and Professor S. Mirabbasi were the supervisory authors on this project and were involved in composing the manuscript.  A version of Chapter 4 has been published in the following journal paper: 3. M. Cai, Z. Wang, Y. Luo, and S. Mirabbasi, "An RF-Powered Crystal-Less Double-Mixing Receiver for Miniaturized Biomedical Implants," in IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 11, pp. 5129-5140, Nov. 2018. vii  I was the leading researcher in developing the concept, designing the circuit and performing the experiments. My colleagues Z. Wang and Y. Luo gave valuable technical advices. Professor S. Mirabbasi was the supervisory author on this project and was involved in supervising the research and composing the manuscript.  A version of Chapter 5 has been submitted in the following journal paper: 4. M. Cai, A. Asoodeh, Y. Luo, R. Sobot, and S. Mirabbasi, “A CMOS Ultra-Low-Power Crystal-Free Battery-Less TDD Radio for Miniaturized Biomedical Implants” submitted to a journal. I was the leading researcher in developing the concept, designing the circuit and performing the measurements. My colleagues Y. Luo and A. Asoodeh provided technical advice and Professor R. Sobot gave helpful editorial assistance. Professor S. Mirabbasi was the research supervisor for this work and helped with composing the manuscript.    viii  Table of Contents  Abstract ......................................................................................................................................... iii Lay Summary .................................................................................................................................v Preface ........................................................................................................................................... vi Table of Contents ....................................................................................................................... viii List of Tables ............................................................................................................................... xii List of Figures ............................................................................................................................. xiii List of Abbreviations ................................................................................................................ xvii Acknowledgements ......................................................................................................................xx Dedication ................................................................................................................................... xxi Chapter 1: Introduction ............................................................................................................... 1 1.1 Motivation ................................................................................................................... 1 1.2 Trends in Implantable Medical Devices ..................................................................... 3 1.3 Biomedical Implantable Transceivers: Overview and Considerations ....................... 6 1.3.1 Remote Power Transfer and Radio Operation Pattern ............................................ 6 1.3.2 Data Rate and Modulation Scheme......................................................................... 9 1.3.3 Reliability and Link Budget .................................................................................. 11 1.3.4 Biomedical Implants Considerations .................................................................... 14 1.4 Review of State-of-the Art Radios for Biomedical Implants.................................... 15 1.4.1 Envelope-Detector-Based Receiver Architectures ............................................... 16 1.4.2 Ultra-Low-Power Wireless Radio Architectures .................................................. 18 1.4.3 Switchable Power Management in IMDs ............................................................. 21 ix  1.5 Thesis Outline and Summary of Research Objectives and Contributions ................ 21 Chapter 2: Low-Power Design Techniques in Deep-Submicron CMOS Technology .......... 25 2.1 Passive Devices ......................................................................................................... 25 2.2 Active Design Techniques ........................................................................................ 28 2.2.1 CMOS Transistors from Strong to Weak Inversion ............................................. 29 2.2.2 Forward Body Biasing .......................................................................................... 31 2.2.3 Active Inductor ..................................................................................................... 32 Chapter 3: Proof-of-Concept Circuits ...................................................................................... 39 3.1 A 32-μW Programmable Crystal-less Event-driven Receiver .................................. 39 3.1.1 Background ........................................................................................................... 39 3.1.2 Noise Analysis of the envelope-detector based receiver ...................................... 39 3.1.3 Envelope Detector with Programmable Scaling Factor ........................................ 42 3.1.4 Circuit Implementation and Measurement Results ............................................... 45 3.1.5 Summary ............................................................................................................... 50 3.2 Embedded RF switch for implantable telemetry systems ......................................... 51 3.2.1 System Overview .................................................................................................. 51 3.2.2 Circuit Implementation and Simulation Results ................................................... 52 3.2.3 Summary ............................................................................................................... 56 Chapter 4: An RF-Powered Crystal-Less Double-Mixing Receiver for Biomedical Implants....................................................................................................................................................... 58 4.1 Introduction ............................................................................................................... 58 4.2 System Overview ...................................................................................................... 58 4.2.1 The Crystal-less Double-Mixing Architecture ...................................................... 58 x  4.2.2 Requirements on Sampling Clock ........................................................................ 62 4.3 Circuit Implementation ............................................................................................. 64 4.3.1 RF-to-DC Converter ............................................................................................. 64 4.3.2 On-chip Sampling Clock and Delay Cell.............................................................. 65 4.3.3 Input Mixer ........................................................................................................... 67 4.3.4 Envelope Detector ................................................................................................. 68 4.3.5 IF Band-pass Amplifier......................................................................................... 69 4.3.6 Output Mixer ......................................................................................................... 71 4.4 Measurement Results and Discussion ....................................................................... 74 4.5 Summary ................................................................................................................... 83 Chapter 5: An Ultra-Low Power Crystal-Free, Battery-Less TDD Radio for Miniaturized Biomedical Implants ................................................................................................................... 84 5.1 Introduction ............................................................................................................... 84 5.2 System Overview ...................................................................................................... 85 5.2.1 Receiver Architecture ........................................................................................... 86 5.2.2 Smart Control Module .......................................................................................... 87 5.2.3 Transmitter Architecture ....................................................................................... 89 5.3 Circuit Implementation ............................................................................................. 90 5.3.1 RF-to-DC Converter ............................................................................................. 90 5.3.2 Crystal-free Double Mixing Receiver ................................................................... 91 5.3.3 Smart Control Module .......................................................................................... 95 5.3.4 ULP Data Transmitter ........................................................................................... 96 5.4 Measurement Results and Discussion ....................................................................... 98 xi  5.5 Summary ................................................................................................................. 105 Chapter 6: Conclusions and Future Work ............................................................................. 107 6.1 Conclusions ............................................................................................................. 107 6.2 Future Work ............................................................................................................ 109 6.2.1 Design Technique Improvements ....................................................................... 109 6.2.2 Antenna Considerations ...................................................................................... 110 6.2.3 In-Vitro and In-Vivo Studies ............................................................................... 111 Bibliography ...............................................................................................................................113  xii  List of Tables Table 2. 1: Transistor design parameters in a RF amplifier .......................................................... 37 Table 3. 1: Design parameters of the complete RF amplifier with active inductor load………...47 Table 4. 1: Transformer and Inductor Parameters……………………………………………….68 Table 4. 2: Power Breakdown of Proposed Receiver .................................................................... 79 Table 4. 3: Receiver Performance Summary and Comparisons ................................................... 80 Table 5. 1: Inductor Design Parameters………………………………………………………… 92 Table 5. 2: Inductor Design Parameters ........................................................................................ 98 Table 5. 3: Power Breakdown of Proposed Radio System .......................................................... 102 Table 5. 4: Performance Summary and Comparison with Prior State-of-the-arts ...................... 105  xiii  List of Figures Figure 1.1: Evolution of the peacemaker technology ..................................................................... 2 Figure 1.2: Block diagram of an implantable telemetry system ..................................................... 4 Figure 1.3: Wireless channel utilization: (a) protocol-based and (b) event-driven based communication ................................................................................................................................ 8 Figure 1.4: Frequency range of the biopotential signals ................................................................. 9 Figure 1.5: General application scenario of medical implants ..................................................... 12 Figure 1.6: State-of-the-art envelope-detector-based receiver: (a) tuned-RF, (b) super-regenerative, (c) injection-locked, (d) uncertain-IF and (e) rectifier-based receiver. ................... 17 Figure 1.7: State-of-the-art ULP radio architecture ...................................................................... 20 Figure 2.1: Lumped circuit model of the on-chip inductor………………..……………………. 27 Figure 2.2: Transconductance efficiency (gm/ID) characteristics .................................................. 30 Figure 2.3: Common-source stage with (a) resistive and (b) inductive loads .............................. 33 Figure 2.4: Common-source stage with active inductor load ....................................................... 34 Figure 2.5: Small signal model of active inductor ........................................................................ 35 Figure 2.6: Noise model of the active inductor............................................................................. 36 Figure 2.7: Simulated transfer function of (a) Req and (b) RX versus frequency ........................... 37 Figure 3.1: Noise analysis model of the generic envelope detection-based receiver…………... 39 Figure 3.2: a) Classic envelope detector topology; b) Envelope detector with scalable gain factor....................................................................................................................................................... 42 Figure 3.3: Brief circuit model of the envelope detector .............................................................. 43 Figure 3.4: Sensitivity improvement of common-source envelope detector with scaling factor . 44 Figure 3.5: Chip micrograph of the event-driven receiver ........................................................... 45 xiv  Figure 3.6: Power-efficient two-stage RF amplifier with on-chip matching network .................. 46 Figure 3.7: Measured RF front-end adjustable input return loss S11............................................. 48 Figure 3.8: Envelope detector circuit and 3-stage baseband amplifier ......................................... 49 Figure 3.9: Power breakdown of the receiver ............................................................................... 50 Figure 3.10: RF start-up system block diagram ............................................................................ 51 Figure 3.11: Three-stage differential RF-DC converter ............................................................... 52 Figure 3.12: Block diagram of CDR system ................................................................................. 53 Figure 3.13: The settling process of the control voltage in sumulation ........................................ 55 Figure 3.14: Simulated control logic of the digital block ............................................................. 56 Figure 4.1: Block diagram of the prototyped receiver………………………………………….. 59 Figure 4.2: (a) Clock frequency change due to PVT variations, (b) Monte-Carlo simulation results. ........................................................................................................................................... 62 Figure 4.3: Double-mixing operating method in frequency domain ............................................ 63 Figure 4.4: Schematic of matching network and voltage rectifier ................................................ 65 Figure 4.5: Schematic of clock signal generation ......................................................................... 66 Figure 4.6: Block diagram of the delay cell .................................................................................. 67 Figure 4.7: Schematic of the input mixer...................................................................................... 67 Figure 4.8: Schematic of envelope detector .................................................................................. 69 Figure 4.9: Schematic of the IF band-pass amplifier .................................................................... 70 Figure 4.10: Schematic of the common-mode feedback network ................................................ 70 Figure 4.11: Post-simulated IF band-pass amplifier frequency response ..................................... 71 Figure 4.12: Schematic of the output mixer .................................................................................. 72 Figure 4.13: Clock and IF amplifier output waveforms in different corners ................................ 73 xv  Figure 4.14: Chip microphotograph .............................................................................................. 75 Figure 4.15: (a) Measured transient waveform and (b) Measured frequency spectrum of clock signal ............................................................................................................................................. 75 Figure 4.16: (a) Clock frequency drift with temperature change, (b) Clock frequency stability feature over 30 days ...................................................................................................................... 76 Figure 4.17: Input reflection coefficient (S11) ............................................................................... 77 Figure 4.18: (a) Input and output signal waveform of RF-powered receiver, (b) Rectified DC signal settling procedure ............................................................................................................... 78 Figure 4.19: Output signal level and noise PSD of the receiver ................................................... 79 Figure 4.20: Measured output SNR with respect to input power on different data rate ............... 81 Figure 4.21: Experimental setup for the RF wireless link ............................................................ 82 Figure 5.1: Block diagram of the prototyped radio system…………………………………….. 85 Figure 5.2: Block diagram of the receiver .................................................................................... 86 Figure 5.3: Block diagram of the smart control module ............................................................... 87 Figure 5.4: Encoding scheme diagram .......................................................................................... 88 Figure 5.5: Operational flow-chart of the IDR block ................................................................... 88 Figure 5.6: Block diagram of the proof-of-concept data transmitter ............................................ 89 Figure 5.7: Schematic of the RF-to-DC converter ........................................................................ 91 Figure 5.8: Schematic of the receiver front-end circuit ................................................................ 92 Figure 5.9: Circuit configuration of the two-stage IF amplifier ................................................... 94 Figure 5.10: Block diagram of the master clock generator and the delay cell .............................. 94 Figure 5.11: Schematic of the wave shaping circuit and integrator .............................................. 95 Figure 5.12: Block diagram of the IDR module ........................................................................... 96 xvi  Figure 5.13: Schematic of the ULP data transmitter ..................................................................... 97 Figure 5.14: Chip microphotograph of the radio system .............................................................. 99 Figure 5.15: Input and output waveform of the RF-to-DC converter ........................................... 99 Figure 5.16: Measured receiver output SNR versus input power ............................................... 100 Figure 5.17: (a) Measured output spectrum and (b) PN of the free-running data transmitter .... 101 Figure 5.18: Measured time-domain waveforms in radio chain: (a) The received demodulated signal in monitoring mode; (b) Enable signal for mode switching; (c) The modulated output of the data transmitter in interrogation mode .................................................................................. 103 Figure 5.19: Experimental setup for the RF wireless data link ................................................... 104  xvii  List of Abbreviations  ASK   Amplitude-Shift Keying  ADC  Analog-to-Digital Converter BER  Bit-Error-Rate  BAN   Body Area Network  BB   Baseband CMOS  Complimentary Metal-Oxide Semiconductor  CDR   Clock and Data Recovery  CQFP  Ceramic Quad Flat Package  CMFB  Common-Mode Feedback CDRF   Clock and Data Reconfiguration CDRF   Clock and Data Reconfiguration CRC   Cyclic Redundancy Check EEG   Electroencephalogram  ECG   Electrocardiogram  EMG   Electromyogram EIRP   Effective Isotropic Radiated Power  EKV   Enz-Krummenacher-Vittoz  FCS  Frame Check Sequence FCC   Federal Communications Commission IDR   Identification Recognition IDC   Identification Code xviii  IoT  Internet-of-Things  IoE  Internet-of-Everything IEEE   Institute of Electrical and Electronics Engineers  ISM   Industrial, Scientific, and Medical  ILO   Injection-Locked Oscillator  IF   Intermediate Frequency  IMDs  Implantable Medical Devices IC  Integrated Circuit LC   Inductor-Capacitor  LO   Local Oscillator  MPE   Maximum Permissible Exposure  MIM   Metal-Insulator-Metal  MEMS Micro-Electro-Mechanical System  RF   Radio Frequency  PAN   Personal Area Network  OOK   On-Off Keying  PoR   Power-on-Reset PLL   Phase-Locked Loop  PSD  Power Spectral Density  PVT   Process, Supply Voltage and Temperature  RFID   Radio Frequency Identification  SRO   Super-Regenerative Oscillator SNR  Signal-to-Noise Ratio  xix  SCM   Smart Control Module TDD   Time-Division Duplexing ULP   Ultra-Low-Power  ULV   Ultra-Low-Voltage  VCO   Voltage-Controlled Oscillator  WPT   Wireless Power Transfer     xx  Acknowledgements  My first debt of gratitude owned to Prof. Shahriar Mirabbasi for his continuous self-giving support, generous encouragement and professional academic guidance through the way during my Ph.D career. For me, he is not only my supervisor, but also a mentor and a good friend. I will never go that far, and this thesis is not possible without his kindness and persistent help. Thank him for offering me this great opportunity to pursue my dreams in University of British Columbia (UBC) and have a chance of spending four valuable years in such a beautiful city of Vancouver. I count myself incredibly fortunate to work with him.  My deep gratitude also goes to my colleagues and friends working in System-on-a-Chip research group in UBC. It is really a great memory to share thoughts with them in such a friendly atmosphere and they have inspired me a lot to continue my research in this field. Also, I would like to thank R. Mehrabadi and Dr. R. Rosales from the department of electrical and computer engineering for their technical support with the CAD tools and measurements.  Special thanks are owed to my parents, who have consistently supported me mentally and financially throughout my years of education, especially for the six years of academic life in Canada. I feel regret of not being with you, my beloved mother, when you really need me to stay aside. I really appreciate your unconditional love and support in my process of growing up. Your kindness, wisdom, generosity and perseverance have a profound impact on my character, helping me to become a man. I wish that I could pay you back in future and make you proud of me.     xxi  Dedication  To my parents. To Amitabha. To Shakyamuni Buddha. To Avalokitesvara Bodhisattva.  To all the people who have helped, inspired, guided me along this journey.   1  Chapter 1: Introduction 1.1 Motivation  Chronic diseases are persistent and generally slow in progression and many of them can be treated but rarely cured. This includes medical conditions such as cancer, diabetes, arthritis and cardiovascular diseases. Such kind of diseases tend to become more common in aging population with a long-lasting detrimental influence on the normal function of the human body, while other related postoperative complications also effect patients’ living quality or shorten their life span. More importantly, the lack of access and delay in receiving health information from patients often results in undesirable outcomes. An efficient monitoring system is therefore desired (and in many cases is required) to constantly check for any unscheduled medical event. Such a system should also have the ability to communicate and process necessary information in a timely manner in order to better serve seniors or patients who are not necessarily in a hospital but do need access to 24-hour health monitoring and nursing care.  To better support and assist individuals impacted by a chronic health condition, the implantable medical devices (IMDs) with event-driven sensing, long-term telemonitoring and real-time communication abilities are necessary to enhance the sustained healthcare services on a daily basis. To be specific, the IMDs can record abnormal biological data that is transmitted to an external base-station, which is responsible for collecting information and sharing through various internet connections to health-care provider. Thus, doctors can monitor their patient’s health condition regardless of their physiological state such as sleeping, walking, and exercising, etc or geographical location. Over the past few decades, the implantable electronic devices intended for healthcare services and clinical usage have become the major driving force of the wellness revolution [1].  2  Before overviewing the evolution of the IMDs, it is meaningful to look back when the first general-purpose computer ENIAC (Electronic Numerical Integrator and Computer) was invented in the research lab of Pennsylvania University. The computer operated with 17,840 vacuum tubes, consumed 170,000 watts of power, weighed 28 tons and occupied about 1,800 square feet of area. Since then, there have been groundbreaking breakthroughs in the computing technologies, especially after the invention of Complimentary Metal-Oxide Semiconductor (CMOS) integrated circuit (IC) technology in 1963. The fast advances of the semiconductor IC industry represented by the “Moore’s Law” have continuously pushed the boundary of computation devices into multi-functionality and intelligence with smaller form factors by using multitude of transistors integrated on a single chip. Furthermore, the widespread application in mixed-signal and radio frequency (RF) segments have been benefiting from the accelerated scaling trend in CMOS technology, creating a digital era that has changed and continues to change the world significantly. For example, today’s portable devices such as tablets and smartphones can fit into pocket without compromising their computational capabilities. There is no doubt that the fast development of IC industry has deeply reformed the lifestyle of individuals and it is hard to imagine a day without using any such electronic devices.   Figure 1.1: Evolution of the peacemaker technology The IMDs ideally combine multiple functions including computational capabilities, wireless communication and medical diagnosis to provide a better service to patients. The evolution of 3  wellness-related industry and business, including the development of medical and healthcare technology, is experiencing the similar trend as consumer electronics [2]. To exemplify this trend, consider the evolution of pacemakers. The first clinical pacemaker, which was encapsulated in biocompatible cylindrical package with a size of approximately 55 mm in diameter and 16 mm thickness, was successfully tested in 1958. Since then, their weight and size have continuously reduced over the past 60 years as shown in Figure 1.1. The most recent self-contained pacemaker model (Micra) [3] is small enough to be implanted directly into the patient’s heart with a minimally invasive operation. In addition, Micra is designed to cause minimum tissue trauma during deployment (is 93% smaller than conventional pacemakers), and has optimal electrode tissue interface with necessary force to hold the device in place. To sum up, as further discussed in the next section, the trends in the development of the next generation IMDs and healthcare electronic devices are moving towards smaller form factors and more advanced functionalities with low power consumption [4]. 1.2 Trends in Implantable Medical Devices  The functionalities of IMDs are application specific, nonetheless, wireless communication is an indispensable function of an implantable device that further avoids transcutaneous wiring and facilitate patient’s movements during the medical treatment or monitoring, minimizing the chance of infection. Such wireless communication between different IMDs and base stations are generally relying on Personal Area Network (PAN) and Body Area Network (BAN) techniques, such as Zigbee, Bluetooth, ultra-wideband and many other emerging low-power versatile short distance wireless communication technologies.  There has been an impressive progress in CMOS ICs which foster low cost and versatile functionality of the mixed-signal systems such as implantable RF wireless telemetry that offers 4  multiple benefits and possibilities including monitoring, diagnosing, and treating of health conditions of the patients with chronic diseases [5], [6]. A typical block diagram of an implantable telemetry system is shown in Figure 1.2. Most of the function blocks are integrated on a single chip in order to minimize the size and cost. Compared to external or wearable biomedical devices, IMDs face the following main restrictions and requirements:   Figure 1.2: Block diagram of an implantable telemetry system • Miniaturized geometry and lightweight: bulky implants further complicate the required invasive surgery and efficient use of available space inside human body, preventing them from many clinical usages due to the discomfort of the patients. Moreover, excessive size and weight of the implants can cause damage or inflammation to the surrounding tissues and exacerbate body response to a foreign object. Therefore, the ongoing miniaturization trend calls for the next generation of IMDs that are highly integrated without discrete components [7]. On the other hand, it is highly desirable that the implantable telemetry system can operate autonomously without frequent reconfiguration and calibration overhead [8].  • Low power consumption: The implantable micro-sized telemetry system is typically relying on energy-constrained source such as batteries or remote power harvesting techniques. 5  Thus, the functional blocks in the telemetry system must be as low power as possible in order to ensure prolonged operation lifetime. As the feature size of the standard CMOS process shrinks, the maximum allowed supply voltage is reduced accordingly, which is a desirable trend for low-power operation. At the system level, certain blocks are required to remain active while others are operating in low-power standby or in switch-off (sleep) mode as indicated in Figure 1.2. For instance, the energy source and power management should remain active in order to guarantee proper functionalities of other blocks in the telemetry system. The controller and processing unit that detect ambient events based on the sensory data and verify the user commands sent from an external base station should be able to operate in the standby mode. For event detection routine, the radio should also function in a standby manner (as needed), while sensors and their interface circuits can go to sleep mode to conserve power.   • Enhanced information processing capability and intelligence: the IMDs for healthcare applications should ideally have functions such as signal acquisition, power management, data processing, and wireless data transmission [9]. As such, the acquired biological information can be stored, analyzed, computed and relayed to the appropriate person or medical institutions with minimum latency, improving the interaction among patients, nurses and doctors.  • Safety and Reliability: considering the high cost and time associated with the surgical replacement of the implants, any failure on IMDs could cause severe outcomes such as discomfort, pain, local damage or even death of the patients, thus, long-term reliability is of critical importance for IMDs. Beyond that, the safety consideration is also of paramount importance, especially in wireless power link, as the body tissue exposed to excessive RF electromagnetic (EM) field could potentially experience temperature increase due to absorption and/or possibly result in irreversible 6  tissue damage [10]. To prevent this from happening, the restrictions of Federal Communications Commission (FCC) on maximum permissible exposure to human body must be respected. Finally, yet importantly, the proper coating or encapsulation of IMDs are essential to accommodate and protect the module from causing implant-associated infections.  1.3 Biomedical Implantable Transceivers: Overview and Considerations  1.3.1 Remote Power Transfer and Radio Operation Pattern  A reliable in-body power supply is a major concern due to various constrains and requirements for medical implants. Typically, the leading source of powering the IMDs is using (rechargeable) batteries that are designed to have a high energy density and a small size to fit into a relevant cavity inside the body. Using such batteries is a robust solution and has been widely used in IMDs such as implantable cardiac pacemakers.  However, the physical size of implants, depending on where they are going to be implanted, could restrict the size of the battery. In some cases, the available space may not enough for a battery as batteries’ dimensions do not scale at the same rate as an IC system. Moreover, rechargeable batteries are typically made of lithium that would increase the health risk in patients in case of any leakage. As such, some types of batteries are hermetically sealed in a biocompatible package to prevent direct contact with tissues, which also makes their form factor rather bulky.     An elegant approach for providing power is to use a wireless power transfer (WPT) system to provide power and/or recharge an onboard battery. Usually, WPT systems use near-field or far-field power harvesting approaches. In a near-filed system, the distance between the IMD and external RF source is generally up to one wavelength (λ) of the operation frequency. Over this short transmission length, the EM fields are reactive and the power radiation into free space is limited, leading to a higher power transfer efficiency. The near-field WPT systems are normally 7  realized by either a capacitive coupling scheme via electric field or an inductive coupling method through a magnetic field. However, both approaches are inevitably constrained by the short range of the system and the alignment requirement between external and implantable coils for power transmission is very important [11], [12]. In a far-field energy harvesting system, the RF source and the IMD are separated by a relatively larger distance, typically much greater than one wavelength. In such cases, the external RF power source excites a propagating EM wave that radiates in the air and the body to wirelessly power the implant. The far-field WPT method has a longer operation distance and better orientation immunity as compared to the near-field WPT system [13], [14], thus, it is commonly used in the wireless health monitoring and alert systems. Traditionally, the solutions to reduce the average power consumption of the implantable RF telemetry include using protocol-based duty-cycle control by placing the system or parts of it in the sleep mode and turning them back on to exchange data for only short periods of time. The wireless communication with implants is usually initiated by the transmitting node at the external hub as shown in Figure 1.3(a). To be specific, the RF telemetry system is duty-cycle controlled by a time reference, it is activated periodically depending on the protocol to check whether there is a user request in the communication channel. If no signal is received in the listening period, the implant node returns to sleep mode until another start-up request is heard, then the implant node wakes up to exchange data with the external hub. Although there is no need to employ time synchronization between two nodes, a large amount of energy is wasted on trying to establish a successful wireless data link. Most importantly, this protocol introduces a critical trade-off between network latency and the amount of average power. To reduce the latency, one approach is to adjust the protocol timing and check the receiving node more frequently, which results in an increase in the average power. Also, elaborate timing circuits for such approaches would increase 8  the overall power consumption. On the other hand, long latency is undesirable in some biomedical applications such as those monitoring vital parameters that require immediate action when detected (emergency conditions).  Figure 1.3: Wireless channel utilization: (a) protocol-based and (b) event-driven based communication The conventional data-driven radio is required to exchange a large amount of data in an extended duration, which means the wireless channel is occupied for most of the time and the interval between different wireless activities is scheduled regularly. Therefore, the optimizations in the data-driven radios are focused on spectral efficiency, storage management, interferer rejection, etc. On the contrary, the event-driven radio that is commonly seen in IMDs is used to accommodate any unscheduled communication request, that is, it responds to ambient biological events and shares the physiological data with external hub in minimum latency [15]. Specifically, the receiver in the implant node is ideally continuously monitoring the channel so that any event request can be detected and responded to immediately as shown in Figure 1.3(b). The 9  communication channel is only occupied for critical medical events and the interval between wireless activities is irregular and unpredictable. Furthermore, the event-driven based communication protocol breaks the trade-off relationship between average power consumption and network latency. Note that the radio in the implants remains responsive during the listening period and therefore the active power consumed in establishing and maintaining wireless data link should be minimized.    1.3.2 Data Rate and Modulation Scheme  Biological signals, such as electroencephalogram (EEG), electrocardiogram (ECG) and electromyogram (EMG), vary rather slowly so that the bandwidth of such signals are relatively low [16]. The frequency range of biopotential signals are illustrated in Figure 1.4. Therefore, the event-driven radio in the implant node is not required to transmit or receive large amounts of data for an extended period as only brief description of the medical events, simple user requests or biopotential signals are relayed in the wireless data packet.   Figure 1.4: Frequency range of the biopotential signals  The wireless communication range in most biomedical applications is typically from several centimeters to a few meters between the IMDs and the external hub [17]. At the implant side, the antenna gain is considerably lower than that of the free space; for two main reasons. First, the size of the antenna is typically smaller than the wavelength of the RF signal due to limited available 10  space in the human body, and second, different permittivity of human tissues can cause high in-vivo loss. Thus, most biomedical implants operate over a short range, which in turn reduces path loss and the requirement for high radiation power from the external hub.  Given such a low data rate and short communication range, non-coherent and less complex modulation schemes such as amplitude-shift keying (ASK) and on-off keying (OOK) can be used in the implantable transceivers to facilitate low-power and low-cost operation. The RF signal is directly modulated by the output data in amplitude modulation (AM) schemes. It is worth mentioning that the AM schemes are more sensitive to noise as compared to other modulation schemes such as phase or frequency modulation. Nevertheless, the AM schemes can effectively reduce the hardware cost when implementing the envelope-detection-based demodulation circuit. Note that a noncoherent system would not capture the phase information from the received and transmitted signal, so that the transceiver only needs to maintain synchronization at the bit period level.  In AM-based systems, the information is only encoded in the amplitude of the wireless signal and thus, phase synchronization is not required. Noncoherent modulators and demodulators can tolerate relatively large frequency and phase offsets because synchronizing to the bit period, especially in low data-rate systems which is the case here, typically require timing accuracies which are order(s) of-magnitude less stringent than synchronizing to the carrier. For example, the Institute of Electrical and Electronics Engineers (IEEE) 802.15.4a standard specifies an RF frequency accuracy requirement of ±20 ppm for coherent signaling, whereas noncoherent signaling can tolerate RF frequency accuracies over ±1000 ppm [18]. Because of these relaxed RF frequency tolerances, noncoherent receivers typically do not require a phase tracking hardware, 11  and thus the overall system power consumption can be reduced. Indeed, most of the noncoherent receivers do not need an RF frequency synthesizer at all. Although the average data rate of a biological signal is very low, the instantaneous data rate in the wireless channel of the radio maybe high enough to have an impact on the network latency. There is an important observation that transmitting at higher data rates allows the implantable radio to employ duty cycling. For instance, if the sensory data is at 1 kb/s rate while the data rate of the transmitter is 100 kb/s, the amount of data that collected in the duration of 1 s can be delivered in a 10 ms burst. Therefore, the transmitter can stay asleep 99% of the time with its average power consumption 100 times lower than its peak power consumption during operation. In order to cater for different medical services scenarios, the receiver in an implantable radio system aims to accommodate data rates with the range between 1 kb/s and 100 kb/s, while higher transmission data rates are preferred in the transmitter so that bio-information can be delivered to external hub in short bursts. 1.3.3 Reliability and Link Budget  The wireless communication and EM propagation inside and around human body should take the properties of the transmission media into account. In contrast to free-space wireless communication, the IMDs should consider in-vivo loss; human skin and tissues with different permittivity would cause reflection and absorption of the EM waves that adversely affect the amount of power received by IMDs [10]. It has been shown that transcutaneous power and data transfer are more efficient when the wireless link operates in the range of sub-gigahertz (GHz) to low GHz frequencies [19].  In order to compensate for the high in-vivo loss, a traditional method is to increase the radiating power from external transmission hub. However, the effective isotropic radiated power 12  (EIRP) in unlicensed industrial, scientific, and medical (ISM) band, which is commonly used for IMDs, is limited to under 36 dBm (4 watts) due to rules and regulations issued by FCC [20]. Furthermore, it also has restrictions on the maximum incident power on human body to prevent biological tissue damage. The corresponding limit for exposure to an intentional radiator operating at 915 MHz band is maximum permissible exposure (MPE) of 6 W/m2 [21]. The relationship between power flux density at distance d from the radiation source to the human body interface is described in (1-1). Thus, the minimum distance between external transmitter hub and human body is calculated at 23 cm when the EIRP of the external hub is 4 watts. On the other hand, the loop or coil antenna structures are usually preferred for implementation inside the human body due to their compact geometry, which is normally in the range of millimeter-scale [19], [22].   {𝑆𝑑} =𝐸𝐼𝑅𝑃4×𝜋×𝑑2 ≤  6 𝑊 𝑚2⁄   (1-1)  Figure 1.5: General application scenario of medical implants To avoid costly over design of the radio in IMDs, the top-level link budget analysis is essential in order to offer a better trade-off among feasibility, power efficiency, and system performance. The study of the link budget starts with the path loss estimation on the wireless communication channel in and around the human body. Usually, IMDs are within 5 cm depth under human skin with the external hub of about 2-meter distance away from the skin, as depicted in Figure 1.5. The path loss is calculated utilizing Friis transmission formula (1-2), where λ is the carrier wavelength 13  in medium, d is the transmission distance, GR, GT is the gain of the receiver and transmitter antenna, PR, PT is the received and transmitted power.  𝑃𝑅𝑃𝑇⁄  =  𝐺𝑅𝐺𝑇 (𝜆4𝜋𝑑)2  (1-2) The attenuation in air and body are two major terms composing the path loss, thus they are analyzed separately due to different propagation medium through (1-3). c0 is the speed of light in free space, f is the transmission frequency and we are considering it to be 915 MHz, the relative permeability µr is assumed to be 1 in both cases for simplicity, whereas the relative permittivity ɛr which describes the dielectric conductivity of human body environment can be up to 74.3 [23]. Thus, the power loss in body is much higher as compared to that of air where the ɛr is approximately 1.   𝜆 = 𝑐 𝑓⁄ =𝑐0𝑓∙√𝜇𝑟𝜖𝑟  (1-3) For simplicity, the receiver/transmitter antenna gains (GR and GT) are set to 0 dB (unity gain) and the influence of the matching network is ignored. From (1-2), the path loss in the air is about 37.75 dB when d is 2 m. On the other hand, the attenuation in human body with 5 cm implant depth can be calculated from (1-2) and (1-3) to be about 24.42 dB. Furthermore, the wave impedance is influenced by air-skin interface that brings an extra power loss of about 3.88 dB [24]. The total attenuation in the transmission channel is estimated to be 66.05 dB, so the maximum received power PR can be calculated as (1-4).  𝑃𝑅 = 𝑃𝐸𝐼𝑅𝑃 − 𝑃𝑝𝑎𝑡ℎ + 𝐺𝑅  (1-4) If the maximum EIRP is restricted under 30 dBm, thus the maximum received power is calculated at –36.05 dBm. In order to recover the transmitted information successfully, the maximum received power should be higher than the sensitivity of the receiver. For the generic 14  implantable application scenario described in Figure 1.5, the requirement on sensitivity of the receiver should be lower than –36.05 dBm.     To sum up, the requirements for the receiver and transmitter is not consistent for medical implantable transceivers. To be specific, the receiver should have a good input sensitivity to compensate for the high in-vivo loss, while reduction of transmitter output power helps relax the stringent power and size requirements at the implant side.  1.3.4 Biomedical Implants Considerations  The focus of this work is on the design of energy-efficient transceivers intended for miniaturized biomedical implants. Such IMDs can be used for monitoring biomedical signals such as EEG, EMG, and body temperature. Our proposed CMOS radio system was designed with the smart stent [25], [26] application in mind. Such stents are intended for monitoring in-stent restenosis (i.e., re-narrowing of the stented site), for example in coronary arteries, and the IC device is supposed to be embedded onto the small platform on the stent where the stent acts as both structural support as well as an antenna for the device [27]. When such stents are implanted into coronary arteries, the use of any external components including crystal oscillators and batteries are not possible and thus should be avoided. Also, there is a constraint of the physical size of the integrated solution and it has to have a small footprint. The silicon chip also needs to be thinned to less than 200 μm of thickness so that it has a low profile and can be embedded on the small platform on the smart stent. Note that other than requirements of small form factor, low-power consumption and long-term reliability, the IMDs also face other issues and challenges. These include biocompatibility and proper encapsulation to prevent adverse reactions of human body to the IMD and forming scar tissues around it after implanting the device. There are many methods for encapsulation of the IMDs such as using titanium alloy, ceramic or silicone cases [28]. The biocompatibility, 15  hermeticity, and mechanical stability of the package should be confirmed by in-vitro and in-vivo studies. Frequency detuning issues, that is, the frequency shift of the EM waves when propagating inside and in the vicinity of human body, are also needed to be considered and are affected by the thickness and electrical properties of various organs, tissues, and cells, as well as the material of the package or coating [29], [30].         To sum up, developing biomedical implantable devices is a multi-faceted problem and requires design considerations in various fields including microelectronics, electromagnetic propagation, material science, and biocompatibility. In addition, a series of laboratory studies and animal experiments are required to confirm the proper functionality of the IMDs. Attending to all these issues is outside the scope of this thesis. Here, we will mainly focus on the electrical aspects of the IMDs with an emphasis on a small form factor, low-power, and low-cost wireless radio system in CMOS technology.   1.4 Review of State-of-the Art Radios for Biomedical Implants  The main goal of this research work is to exploit ultra-low-power (ULP) and ultra-low-voltage (ULV) design techniques to implement circuits and systems for a low-cost and highly integrated wireless transceiver tailored for miniaturized implants. In the following sections, a literature review on both receiver architecture and entire radio system, as well as the allocation of wireless data and power links are presented for the application in wireless implantable event-driven nodes. While achieving this goal, there are many other design considerations and constrains need to be investigated and discussed, including operation method, modulation scheme, frequency plan, input sensitivity, and output radiation power. Therefore, designing such an event-driven radio for IMDs has its own challenges.  16  1.4.1 Envelope-Detector-Based Receiver Architectures  Recent interests in low-power radio system has led to the popularity of receiver that perform signal down-conversion by the envelope detector with squaring function. The state-of-the-art even-driven receiver structures are summarized in Figure 1.6; they use the simple envelope detection principle to detect the RF signal while maintaining high power efficiency. Nevertheless, the main drawbacks of the generic topology include the nonlinear conversion gain and excessive noise of the envelope detector circuit. An effective way to overcome these issues is to improve the amplitude of the signal preceding the envelope detector. A tuned RF architecture [31] as shown in Figure 1.6(a), the front-end (active) amplifier provides voltage gain at high frequency at the cost of higher power consumption. Moreover, as the desired signal after envelope detection resides around DC, the receiver is vulnerable to circuit mismatch and DC offset, thus an offset cancellation algorithm is needed that would increase the cost of the end solution.  Several techniques for improving the gain at RF stages to amplify the received signal before it reaches envelope detector have been explored. The super-regenerative receiver architecture [32], [33] is illustrated in Figure 1.6(b) with its core oscillator resonating at the same frequency of the RF input signal. This super-regenerative oscillator (SRO) is turned on and off periodically by another low frequency quench signal, delivering a large front-end gain at low complexity. However, it has drawbacks of inherent frequency instability and the receiver’s performance is highly dependent on the characteristics of SRO. To address these issues, the injection-locked RF receiver structure [34], [35] of Figure 1.6(c) has been presented. An injection-locked oscillator (ILO) is used to improve the phase noise performance and provide better frequency stability while simultaneously offering a large front-end gain. However, these benefits only exist within the locking range of ILO, so a calibration loop is required to tune the frequency and keep it within the 17  locking range of ILO. Most importantly, both SRO and ILO would require resonant oscillator using an inductor-capacitor (LC) tank, which usually leads to hundreds of microwatts power consumption.   Figure 1.6: State-of-the-art envelope-detector-based receiver: (a) tuned-RF, (b) super-regenerative, (c) injection-locked, (d) uncertain-IF and (e) rectifier-based receiver. Alternatively, the signal amplification is performed at intermediate frequency (IF) to get rid of the power-hungry RF amplification [36], [37]. However, these systems require an accurate reference clock that is usually an external crystal oscillator. In addition, in these systems the crystal 18  is continuously working with the receiver, thus increasing the power consumption of the overall system. To avoid the off-chip bulky crystal, signal amplification at IF can be done by using a down-conversion mixer and a non-crystal-based on-chip local oscillator (LO) [38]. As shown in Figure 1.6(d), a power-efficient ring oscillator can be used for LO generation. However, the frequency drift of the always-on free running oscillator is typically too large to operate within the desired band, and thus a periodic off-line frequency calibration is needed that raises the overall system cost. Another alternative approach utilizes sub-1-µW rectifier-based receivers that avoid using power-hungry active RF amplification have been reported recently in [39], [40] as seen in Figure 1.6(e). However, they achieve their low power at the cost of larger area by using high quality factor off-chip matching network or transformer to realize a high passive voltage gain at RF. Another receiver exploited in [41] use ASK modulated data with Manchester-encoding which has no important distribution at DC in its spectrum. Hence, the large DC component generated by self-mixing envelope detector could not mask any desired receiving signal. However, a correlated complex demodulation mechanism would increase the cost and system latency.   1.4.2 Ultra-Low-Power Wireless Radio Architectures Although to date a number of ULP bidirectional transceivers have been published, most of the existing implementations are not ideal approaches for IMDs either due to their significant high-power consumption [42], [43] or bulky form factors by using off-chip components [44], [45].  Additional attempts to conserve power include devices that rely on radio frequency identification (RFID) platform are explored [46], [47], which guarantees ULP operation by putting uplink into passive transmission method while using backscattering-based transmitter. In spite of the efforts, the backscattering architectures face the issue of self-jamming [48], which greatly confines the uplink communication range. To address such limitation, active transmission schemes 19  for both up and downlink communication have been exploited. Operating in an aggressive duty cycle manner is an effective approach to reduce the average power consumption since the transmitter only need to operate for a short duration [49]. However, such systems are usually controlled by a global timer, which is not suitable for biomedical applications because of their latency and associated limitations for event-driven real-time communications. Besides, the communication protocol between implants and external hub often leads to correlated synchronizing circuity or quartz oscillator for timing control, which would inevitably lead to higher power consumption and a larger form factor.  On the implant side, many design techniques are employed in RF front-end circuity. Other than the super-regenerative and inject-locking approach as discussed in 1.4.1, an alternative method is based on off-chip quartz frequency reference used by ring-based oscillator or frequency doublers to produce the RF carrier for wireless data communication [33], [50], as shown in Figure 1.7(a). The integration level is improved, and the external reference is eliminated when a phase-locked loop (PLL)-based RF front-end is used (Figure 1.7(b)), which offers both data recovery and carrier synthesis [51], [52]. The drawback is that the PLL circuit is power hungry and its settling time inevitably adds network latency. Thus, it prevents the radio from operating in the event-driven format.    In general, implantable radio system is designed to facilitate simultaneous power harvesting and data reception and transmission. Therefore, it employs up to three separate wireless links: bidirectional data link and the remote power link. In order to enhance the system’s integration level, the power link is usually combined with the downstream datalink over the same channel [41], [52]. Consequently, the length of the downlink operating range is constrained by the sensitivity of the power harvester, which is typically much lower than a fully functional wireless 20  receiver. This is especially true in the case of AM system while the inconstant envelope of the incident RF carrier inevitably impacts the power flow to the IMD. Thus, AM factor must be reduced to sustain the energy flow, which results in an inferior receiver sensitivity.   Figure 1.7: State-of-the-art ULP radio architecture Some attempts have been made to combine the power and data link in different frequency bands over a single antenna (Figure 1.7(c)). Nevertheless, the area taken by off-chip passives or power-hungry active duplexers and circulators that are required to provide adequate isolation between up and downlink communication, significantly increasing the system’s power and size budget [41], [43], [53], [54]. In order to avoid using duplexers or circulators, different antennas are employed to separate the uplink and downlink communication in different frequency bands. Moreover, the power and down-stream data links can be optimized independently by implementing 21  the bulky energy storage elements such as super-capacitors [52], [55] in the radio system (Figure 1.7(d)), which inevitably increase hardware cost and the overall form factor. 1.4.3 Switchable Power Management in IMDs  Traditional implantable RF medical devices that rely on small sized batteries or remote energy harvesting techniques as power sources also need to reduce their power consumption to ensure prolonged operation lifetime. One such efficient method of power reduction in the IMD is in the form of switchable power, this ensures that implant is not activated until required by the user by using switches or enable circuits for power management on different sub-blocks.  The idea of switchable power to conserve battery life dates back to 1966, where an external loosely coupled pulsed transmitter acts as a switch to control the implanted transmitter’s power supply [56]. Limited by low coupling factor and relative high-power consumption with a bulky form factor, this method can only implement in a centimeter range, which is not suitable for modern medical applications. Alternatively, the implanted system can be controlled by a series of reed switches magnetically operated in close proximity to the implanted device, one such system is described in [57]. Several IC based RF transmit/receive switch circuits have been designed for wireless communication applications [58], [59]. However, minimal research has been presented on IMDs based RF switches due to the unique constraints in implants such as form factor, power consumption, and package issues.  1.5 Thesis Outline and Summary of Research Objectives and Contributions  The research objectives and main contributions of this work are to address the above-mentioned challenges and limitations. To do this we first review the unique features of medical implants as well as trends for their integration using CMOS technology.  22  In Chapter 1: we explore trends, constrains and challenges in the development of IMDs and review system-level considerations, as well as link budget analysis on both wireless bidirectional data and remote power links. We also review ULP envelope-detector-based receiver architectures and the trade-offs among system complexity, power consumption, input sensitivity, form factor and the cost of external device for the implementations in the IMD. Furthermore, the chapter include literature review of transceivers and critical requirements from both architecture level and circuit design techniques in order to have smaller form factor and lower cost solution in the implantable telemetry system.  In Chapter 2, design constrains and circuit implementation techniques in deep submicron CMOS technology are exploited. We first investigate properties and constrains of the integrated passive devices such as resistors, capacitors and inductors. Then, design margin and implementation techniques from IC design perspective in active ULP and ULV circuits, such as weak-inversion operation and forward body biasing are explored. Moreover, a detailed analysis of the active inductor as well as their benefits and drawbacks of using in a RF amplifier are provided.  The main objectives and contributions of the thesis are presented in Chapters 3 to 5 and are summarized as follows:  Objective 1: A programmable event-driven receiver for biomedical implants Contributions: -- Noise analysis on a generic envelope-detector based receiver for better trade-offs between input sensitivity and power consumption. (Chapter 3)   -- A novel structure of envelope detector is proposed for better conversion gain without increasing the power consumption. (Chapter 3)   23  -- External components are eliminated in the proposed receiver, while one-time manual calibration is required. (Chapter 3)  Objective 2: Embedded RF switch for implantable telemetry systems  Contributions: -- A clock and data recovery (CDR) based wireless switch is proposed for implantable telemetry systems. (Chapter 3)   -- The system is powered by harvested energy and it is suitable for controlling multiple on-chip regulators, which are used to manage the supply of other blocks that powered by batteries in order to extend the lifetime of the IMD. (Chapter 3)    Objective 3: An RF-Powered Crystal-Less Double-Mixing Receiver for miniaturized Biomedical Implants Contributions:  -- A double-mixing receiver architecture is proposed to improve the sensitivity by eliminating the impact of DC offset and low-frequency noise. (Chapter 4)   -- The proposed architecture is robust to process, supply voltage and ambient temperature (PVT) variations. (Chapter 4)   -- The proposed receiver does not require any external device and there is no need for calibration. (Chapter 4)   -- The event-driven receiver uses simple modulation scheme while keep system’s simplicity, resulting in a ULP and ULV solution. (Chapter 4)  Objective 4: An Ultra-Low Power Crystal-Free, Battery-Less TDD Radio for Miniaturized Biomedical Implants Contributions:  24  -- The RF powered radio system benefits from splitting of the data and power links so that they can be optimized separately. (Chapter 5)   -- The bidirectional time-division data link is orchestrated by a smart control module, where the cyclic redundancy check is conducted to switch the system between the monitoring and the interrogating modes. (Chapter 5) -- A clock and data reconfiguration block is proposed to replace the clock and data recovery module in the smart control unit for higher power efficiency and lower hardware cost.  (Chapter 5) -- A current-reuse free-running LO is codesigned with output buffer stage for enhanced drive ability. The ULP transmitter obviates the requirement for power amplifier and bulky output matching networks. (Chapter 5)  25  Chapter 2: Low-Power Design Techniques in Deep-Submicron CMOS Technology In the first chapter, critical design specifications and major functionalities of radio systems for accommodating the stringent power and form factor requirements in IMDs were overviewed. In this chapter, we focus on strategies to tackle the design challenges and will further explore the available design space of such devices. The performance of the active circuit strongly depends on the underlying CMOS process used for implementation. Therefore, the properties of the components, including both active transistors and passive devices, in deep-submicron CMOS technologies are analyzed. Then, the low-power design techniques and transceiver system level considerations are summarized.    2.1 Passive Devices In order to minimize the number of bulky off-chip components, various on-chip passive devices such as resistors, capacitors, and inductors are generally available and are commonly used in a standard CMOS process, even though many integrated passive devices have an inferior quality as compared with their off-chip counterparts [60].  Resistors are often found in biasing circuits, feedback networks and amplifier stages. It is worth mentioning that the on-chip resistor may require additional masks during fabrication and is also sensitive to PVT variations with up to ±20% deviation from its nominal value [61]. The silicon-based resistors are commonly formed by implanted crystal, polysilicon or tantalum nitride. For instance, the polysilicon resistors are usually placed on an n-well to better shield the noise coupled from substrate. Moreover, the polysilicon stripes with n+ or p+ implant doping offer different values of sheet resistivity, allowing for a compact layout. On the other hand, the 26  resistances with different temperature coefficients are also realized by doping [62]. For example, positive and negative temperature characteristics are found in p+ and n+ polysilicon resistors, respectively.  The on-chip capacitors are mainly classified into two forms, i.e., the linear capacitor and variable capacitor. Variable capacitors, also known as varactors, are often found in building blocks such as voltage-controlled oscillators (VCOs) [63]. Electrical characteristics of a varactor rely on its physical form factor since depending on their area and perimeter these voltage controlled capacitances generally have different voltage dependencies. Accumulation mode MOS varactors [64] are sensitive to biasing voltage while offering a large tuning range with a lower parasitic resistance. Larger linear capacitors are usually realized by metal-insulator-metal (MIM) parallel plate capacitance. They can achieve a better temperature-voltage linearity, good stability and accurate capacitance matching. However, the MIM capacitors may be impacted by the process variations.      𝑄 = 2𝜋 ∙𝑒𝑛𝑒𝑟𝑔𝑦 𝑠𝑡𝑜𝑟𝑒𝑑𝑒𝑛𝑒𝑟𝑔𝑦 𝑙𝑜𝑠𝑠 𝑝𝑒𝑟 𝑐𝑦𝑐𝑙𝑒  (2-1) The integrated on-chip inductors are typically realized by spiral traces using CMOS interconnection metal layers. The inductor’s quality factor (Q), defined by (2-1), plays a critical role in the performance of the RF blocks as it indicates how good an energy-storing element the inductor is. The equivalent circuit model of an on-chip inductor with one port and the substrate connected to ground is shown in Figure 2.1. It is worth mentioning that the inductor is normally a three-port device with symmetric topology, and only half-circuit model is analyzed for simplicity. In the model, Ls is the spiral inductance, Rs represents the metal series resistance, the feedforward capacitance Cs models the overlap of the spiral traces with the center-tap underpass. Other major  27  CsRsLsCoxRsi CsiCsRsLsRp Cp(a) (b) Figure 2.1: Lumped circuit model of the on-chip inductor parasitic components are modeled by capacitors Cox, Csi and the resistor Rsi, where Cox accounts for the oxide capacitance between spiral and substrate, and the capacitance and resistance of the silicon substrate are represented by Csi and Rsi, respectively. In Figure 2.1(b), the combination of the parasitic is substituted by frequency dependent Rp and Cp so that (2-1) can be rewritten as (2-2) and (2-3) [60]  𝑄 =𝜔𝐿𝑠𝑅𝑠∙𝑅𝑝𝑅𝑝+[(𝜔𝐿𝑠𝑅𝑠)2+1]𝑅𝑠=𝜔𝐿𝑠𝑅𝑠∙ 𝑠𝑢𝑏𝑠𝑡𝑟𝑎𝑡𝑒 𝑙𝑜𝑠𝑠 𝑓𝑎𝑐𝑡𝑜𝑟  (2-2)  𝑅𝑃 = 1𝜔2𝐶𝑜𝑥2 𝑅𝑠𝑖+𝑅𝑠𝑖(𝐶𝑜𝑥+𝐶𝑠𝑖)2𝐶𝑜𝑥2   (2-3) where ωLs/Rs defines the ratio of the desirable impedance (magnetic energy storage) and the ohmic loss in the series resistance (Rs) of the spiral inductor, while the substrate loss factor represents the energy dissipating in the lossy silicon substrate. There is an important observation from the first term in (2-2) that a larger spiral inductor (Ls) is preferred for a higher Q, while its series resistance (Rs) is highly undesirable and need to be reduced. It is unfortunate that the on-chip inductors cannot benefit from the technology scaling because CMOS process is optimized towards digital circuits for faster speed and lower cost. Therefore, the availability of the thick metal layers for inductors is limited. For example, the top-layer metal used in a standard 0.13 μm CMOS process is only a few micrometers thick, which is still not thick enough for an optimum Rs. On the other hand, on-28  chip inductors normally occupy a greater silicon area, resulting in big footprints and long interconnections between inductors and other blocks.  In particular, the substrate loss factor accounts for about 10% to 30% reduction from ωLs/Rs at the frequencies of interest below 2 GHz [65]. This value approaches unity if Rp is close to infinity, implying that substrate loss can be reduced by having a short or open silicon substrate, thereby improving the Q. Thus, an array of metal wires is normally used as the patterned ground shield so that the substrate is isolated from the inductor by blocking the inductor EM field from the silicon substrate. By doing so, the silicon is equivalent to a shorting substrate (Rsi ≈ 0) so that Rp is maximized as illustrate in (2-3). Furthermore, it also minimizes the loss associated with the induced current in the substrate which deteriorates the Q. Even though, the on-chip spiral inductors are still formed by thin metal layers and built on lossy silicon substrate, resulting in a lower Q compared with their external counterparts.   To sum up, the integrated passive components have many design limitations and implement constrains due to their inferior properties on the lossy silicon substrate. Therefore, a major challenge in RF IC design is how to achieve good performance with relatively poor quality on-chip passive devices.      2.2 Active Design Techniques  The maximum allowed supply voltage is typically shrunk with the scaling of the CMOS technologies. The use of low supply voltage of between 0.5 and 0.7 V [66] is considered to reduce the power consumption in modern IC designs. Operating from a low power supply also further facilitate the option of powering the system by scavenged energy from the ambient environment. However, the reduction in the supply voltage also forces the drain-source voltage (Vds) of the transistors to be in the close proximity to the threshold voltage (Vth), which has significant impacts 29  on the performance of CMOS transistors, causing problems with voltage swing, current efficiency, intrinsic gain (gm/gds), transit frequency, noise figure, etc.  2.2.1 CMOS Transistors from Strong to Weak Inversion Depending on different drain current and transconductance properties, the regions of operation of CMOS transistors can be broadly categorized into two: strong inversion (SI) and weak inversion (WI) region.  A CMOS transistor is operating in its strong inversion region when the gate-source voltage (Vgs) is sufficiently high. In this region, the channel is strongly inverted, and the drain drift current takes over the channel current. Therefore, the drain current in the strong inversion region is approximated using the Enz-Krummenacher-Vittoz (EKV) model [67] as:  𝐼𝐷,𝑆𝐼 =12(𝜇𝐶𝑜𝑥𝑛)𝑊𝐿(𝑉𝑔𝑠 − 𝑉𝑡ℎ)2  (2-4)  where, μ is the channel carrier mobility, Cox is gate-oxide capacitance per unit area, n is the process dependent sub-threshold slope factor, and W and L are the effective channel width and length of the CMOS transistor, respectively.  Weak inversion occurs when Vgs drops to the vicinity of or below Vth, where the channel is weakly inverted. Note that the diffusion current dominates in this situation and the current value is determined by (2-5) based on EKV model, where VT is the thermal voltage which is 26 mV at room temperature (27 ℃).  𝐼𝐷,𝑊𝐼 = 𝐼𝐷0 · (𝑒𝑉𝑔𝑠−𝑉𝑡ℎ 𝑛𝑉𝑇 ) = (𝑛 − 1)𝑉𝑇2𝜇𝐶𝑂𝑋(𝑊𝐿)(𝑒𝑉𝑔𝑠−𝑉𝑡ℎ 𝑛𝑉𝑇 )  (2-5)    Traditionally, long-channel transistors operating in weak inversion are considered to be slow. To better explain this point, in order to sustain a given drain current while operating in this region, a bigger transistor is required, resulting in a larger parasitic capacitor of Cgs. Nevertheless, the 30  short-channel device with deep-submicron length offers higher speed, and thus even in weak inversion region the speed of operation of modern CMOS transistors is relatively high. Therefore, transistors biased in weak inversion are commonly used due to their superior ability in operating in ULP and ULV modes. It is worth mentioning that any mismatch in Vth is amplified exponentially for weak inversion transistors as describe in (2-5), and the model of the transistor in this region is not accurate. Therefore, the use of weak-inversion transistors should be avoided in precision analog circuits such as current mirrors.   Figure 2.2: Transconductance efficiency (gm/ID) characteristics The global inversion coefficient (IC) is defined in (2-6), it is a numerical value that indicates MOS transistors inversion level for operation from strong inversion (IC >> 1) to weak inversion (IC < 1) [68]. The transconductance efficiency of the transistor is the ratio of transconductance (gm) and the drain current (ID), and it is also a function of IC as expressed in (2-7) [68]. The gm efficiency has the physical significance of describing how much transconductance can be achieved per certain amount of drain current. It is an important criterion for designing analog low-power circuits as a larger gm efficiency indicates a high energy efficiency. 31   𝐼𝐶 =𝐼𝐷2𝜇𝐶𝑂𝑋𝑉𝑇2(𝑊/𝐿)  (2-6)  𝑔𝑚𝐼𝐷=1𝑛𝑉𝑇∙21+√4𝐼𝐶+1  (2-7) Figure 2.2 illustrates the relationship between gm/ID and inversion coefficient; the best transconductance efficiency can be achieved when the transistor is biased in weak inversion region, with the maximum gm efficiency of about 26 S/A. When the drain current, ID, increases, the value of gm/ID decreases with 1 √𝐼𝐶⁄ . In the strong inversion region, the gm efficiency is normally below 16 S/A.  2.2.2 Forward Body Biasing  The desire to reduce power in the presence of low supply voltage leads to challenging circuit design trade-offs among specifications such as speed and gain. Forward body biasing is one of the techniques that has been widely implemented in different circuitries in order to improve the characteristics of the circuit [69]–[71]. In this section, two major advantages (i.e., threshold voltage reduction and intrinsic gain enhancement) that are closely related to ULP and ULV design are briefly discussed. Given that in the more advanced CMOS nodes, there is no noticeable reduction in threshold voltage (Vth) as transistors are scaled down, the choice of overdrive voltage and Vds become critical especially under low supply voltages. Forward body biasing could be an attractive solution as it would efficiently decrease Vth of the transistor by adjusting its source-bulk voltage (Vsb). The Vth of the CMOS transistor is given by [72]  𝑉𝑡ℎ = 𝑉𝑡ℎ0 + 𝛾(√2𝛷𝐹 + 𝑉𝑠𝑏 −√|2𝛷𝐹|)  (2-8) where Vth0 is the intrinsic threshold voltage without substrate bias, γ represents the process dependent body-effect coefficient, and ΦF is the substrate Fermi potential. Forward body biasing 32  leads to a decreased value of Vsb, so that the threshold voltage is reduced accordingly. The direct benefit of a lower Vth is the reduced Vgs required to achieve the desired overdrive voltage, which is denoted as the value of Vgs−Vth. Moreover, the Vth reduction can also improve the speed of the transistor and further facilitate RF operation from a low supply voltage.   The undesired short channel effects have profound impacts on the performance of deep sub-micron MOS transistors. In short channel CMOS transistors, the depletion region of source or drain terminal can easily intrude the channel area even without gate biasing voltage. In this case, the source and drain terminals can directly impact the channel charge, which is otherwise only controlled by the gate terminal. As the increasing voltage on the drain would cause the depletion region around it to expend towards the source terminal and hence the potential barrier is weakened, which results in a lower effective Vth. This circumstance is known as drain-induced barrier lowering (DIBL) effect and it is the main reason for the drain conductance degradation [72]. To be specific, the output conductance (gds) is the derivative of drain current (ID) with respect to Vds. At a given Vds and ID, DIBL leads to a higher gds, resulting in an inferior intrinsic gain. Applying forward body bias could effectively decrease the area of drain depletion region and thus reducing the impact of drain voltage on the channel, which in turn, reduces the output conductance and thus increases the intrinsic gain (i.e., gm/gds) of the CMOS transistor.  2.2.3 Active Inductor In a simple common-source stage RF amplifier, the load is normally formed by resistors as shown in Figure 2.3(a), however, such topology has two major issues. First, the frequency bandwidth at the output node is given by   𝜔−3𝑑𝐵 =1(𝑅𝐷‖𝑟𝑜1)·𝐶𝑃  (2-9) 33  where ro1 is the output impedance of the transistor M1, RD is the load resistance, and CP is the sum of all the parasitic capacitances at the drain node. Second, the load resistance (RD) consumes voltage headroom that is trading off with the voltage gain given as gm1(RD‖ro1), while gm1 is the transconductance of the transistor M1. The scaling of the CMOS technology advances the 3-dB frequency while scarifying the voltage headroom. Thus, such topology with a resistive load is not suitable for RF front-end circuitry where a higher frequency bandwidth and a larger voltage headroom are required.   Figure 2.3: Common-source stage with (a) resistive and (b) inductive loads An alternative trade-off is provided by employing an inductor as the load (Figure 2.3(b)). In this case, the inductor LD and capacitor CP forms a resonant network and the common-source stage can operate in a much higher frequency while offering a reasonable voltage gain. Furthermore, the voltage headroom is conserved as the load inductor LD only contributes little DC voltage drop, leading to a possibility of operating from low supply voltages.  Owning to the above-mentioned advantages, inductors have become very common and are widely employed in RF ICs such as RF amplifiers, mixers, and local oscillators. Nevertheless, among all the integrated devices on the silicon such as transistors, resistors, and capacitors, inductors typically have a larger dimension with a more sizable footprint. Other than the area 34  penalty, the lossy silicon substrate also leads to a lower Q as mentioned in 2.1. If the series resistive network of the inductor is transformed into a parallel model as shown in Figure 2.3(b), then the parallel equivalent resistance RP of the inductor is redefined in (2-10) [60], where f0 is the operation frequency and L is the inductance value. Note that there is no physical meaning when the loss resistance is modeled by RP. However, it is useful to illustrate the gain of the amplifier, which can be maximized by optimizing the product of L and Q in order to have a larger gain for a given drain current. This RP is greatly constrained by the maximum attainable and availability of L and Q in a standard CMOS process.   𝑅𝑃 = 2𝜋𝑓0 · 𝐿 · Q  (2-10)    M1VinCPM2DM3M4M5DLeqRpCeqDXRs Figure 2.4: Common-source stage with active inductor load Active inductors are commonly used in filter design due to their smaller size and programmability [73], [74]. They are becoming popular as the load of an RF amplifier to address the issues that traditional on-chip passive inductors have [31]. Unlike integrated spiral inductors, the active inductor can emulate the behavior of a large load impedance at the cost of smaller chip area since it is implemented by only transistors. The schematic of a simple RF amplifier with an active inductor load is shown in Figure 2.4. The active inductor contains two PMOS transistors M3 and M4, and an NMOS transistor M5 that is used as a current source. The equivalent inductance 35  at node D is resonating with the load and other parasitic capacitance. In order to better explain this point, the small-signal model of the active inductor is depicted in Figure 2.5 and the analysis is performed using Kirchhoff’s Current Law (KCL) [75] in (2-11). Cgs3VinVXro5 Dgm3VXgm4Vin ro4ro3 Cgs4iin+  Yin Figure 2.5: Small signal model of active inductor  { 𝑔𝑜5𝑉𝑋 + 𝑠𝐶𝑔𝑠3𝑉𝑋 = 𝑔𝑚4𝑉𝑖𝑛 + (𝑉𝑖𝑛 − 𝑉𝑋)𝑔𝑜4𝑔𝑚4𝑉𝑖𝑛 + (𝑉𝑖𝑛 − 𝑉𝑋)𝑔𝑜4 + 𝑔𝑚3𝑉𝑋 + 𝑔𝑜3𝑉𝑖𝑛 + 𝑠𝐶𝑔𝑠4𝑉𝑖𝑛 = 𝑖𝑖𝑛  (2-11) where gm3 and gm4 are the transconductance of transistors M3 and M4, respectively. go,i is the output conductance of the transistor i. At the gate node of the CMOS transistor, the gate-source capacitance (Cgs) usually dominates and thus for simplicity, the gate-drain capacitance (Cgd) is neglected in this analysis. The input reactance seen from node D of the network is given as  𝑌𝑖𝑛 =𝑖𝑖𝑛𝑉𝑖𝑛= 𝑔𝑜3 + 𝑔𝑜4 + 𝑔𝑚4 + 𝑆𝐶𝑔𝑠4 +(𝑔𝑚3−𝑔𝑜4)𝑔𝑚4𝑔𝑜4+𝑔𝑜5+𝑆𝐶𝑔𝑠3  (2-12) The equivalent circuit model of the active inductor is shown in Figure 2.4, and the values of the equivalent RLC network at node D is given in  {𝑅𝑒𝑞 = 𝑟𝑜3‖𝑟𝑜4‖1𝑔𝑚4;  𝑅𝑠 =𝑔𝑜4+𝑔𝑜5(𝑔𝑚3−𝑔𝑜4)𝑔𝑚4𝐿𝑒𝑞 ≈𝐶𝑔𝑠3𝑔𝑚3𝑔𝑚4⁄ ; 𝐶𝑒𝑞 = 𝐶𝑔𝑠4  (2-13) The equations in (2-13) give intuition on how to synthesize an inductor by using CMOS transistors. The goal of the design is to maximize the load impedance at the desired resonate frequency with a good frequency selectivity property. The Q of the active inductor is given by (2-14) where f0 36  represents the operating frequency of the active inductor. The Q drops as f0 increases, whereas, the property of transistor M3 is critical as a higher value of gm3/Cgs3 also improves the Q.   𝑄 =𝑅𝑒𝑞𝜔𝐿𝑒𝑞≈1 𝑔𝑚4⁄2𝜋𝑓𝑜∙𝐶𝑔𝑠3 (𝑔𝑚3𝑔𝑚4)⁄=𝑔𝑚32𝜋𝑓0∙𝐶𝑔𝑠3  (2-14) VDDGNDM1M2M3M4+  -+  -+  -𝑉𝑛, 12𝑉𝑛, 32𝑉𝑛,𝑡𝑜𝑡2𝑉𝑛, 42DX Figure 2.6: Noise model of the active inductor Major drawbacks of the active inductors include their power consumption and poor noise performance over the passive inductors. In order to quantify their noise penalty, the noise model of a complete RF amplifier is illustrated in Figure 2.6. The total output noise voltage (𝑣𝑛,𝑡𝑜𝑡2 ) of a RF amplifier is dominated by the noise source from transistors M1, M3 and M4: 𝑣𝑛,𝑡𝑜𝑡2 = 𝑣𝑜𝑢𝑡, 12̅̅ ̅̅ ̅̅ ̅̅ ̅ + 𝑣𝑜𝑢𝑡, 32̅̅ ̅̅ ̅̅ ̅̅ ̅ + 𝑣𝑜𝑢𝑡, 42̅̅ ̅̅ ̅̅ ̅̅ ̅  =4𝑘𝑇𝛾𝑔𝑚1∙ (𝑔𝑚1𝑅𝑒𝑞)2+4𝑘𝑇𝛾𝑔𝑚3∙ (𝑔𝑚3𝑅𝑒𝑞)2+4𝑘𝑇𝛾𝑔𝑚4∙ (𝑔𝑚4𝑅𝑋)2 · (𝑔𝑚3𝑅𝑒𝑞)2  (2-15)  where gm1, gm3 and gm4 are the transconductance of the transistor M1, M3 and M4, respectively. γ refers to the excess noise coefficient, which is about 2/3 in long-channel CMOS devices and may be as high as 2 in short-channel transistors [60]. Req is the equivalent parallel resistance of the 37  active inductor. RX is the impedance at node X, its value can be derived from the small-signal model as illustrated in Figure 2.5.  Table 2. 1: Transistor design parameters in a RF amplifier Transistor M1 M2 M3 M4 Size (W/L) 25μm/120nm 5μm/120nm 5μm/250nm 3μm/120nm gm (μS) 620 528 285 50  The design parameters of an RF amplifier are obtained by taking energy efficiency as top priority in order to meet the stringent power requirement. The entire RF front-end and active inductor is designed to operate in ISM 915 MHz frequency band. With transistor sizes and biasing conditions given in Table 2. 1, the transfer function of equivalent impedance at node D and X, denoted as Req and RX, are verified with simulation results as shown in Figure 2.7(a) and (b). The active inductor can synthesize high impedance over the frequency of interests, the peak resistance is about 5.87 kΩ and the value of Req varies between 5.87 and 5.73 kΩ in the desired frequency range from 902 to 928 MHz. At node X, the transfer function of the equivalent impedance shows  Frequency (Hz)1KEquivalent Req (Ω)2K04K5K3K6K108 109 1010Equivalent RX (Ω)2K4K08K10K6K12KFrequency (Hz)101 109 1010102 103 104 105 106 107 108100(a) (b) Figure 2.7: Simulated transfer function of (a) Req and (b) RX versus frequency 38  that RX is a relative constant resistance of about 5.8 kΩ when operating below 74 MHz. Note that node X is the drain of the current source transistor M5 (Figure 2.4), therefore it only operates at low frequency around DC.    𝐹 = 1 +𝑣𝑛,𝑡𝑜𝑡2𝐴𝑣2∙4𝑘𝑇𝑅𝑆= 1 +4𝛾∙(𝑔𝑚1+𝑔𝑚3+𝑔𝑚4𝑔𝑚32 𝑅𝑋2 )𝑔𝑚12 ∙𝑅𝑆  (2-16) The noise factor of the complete RF amplifier can be calculated by (2-16). Assuming the source resistance RS is 50 Ω and it is matched to the input of the RF amplifier, the noise factor of the complete RF amplifier is calculated at 22.7, resulting in a noise figure of 13.6 dB. In order to quantify the impact of the active inductor, the first term in (2-15) that represents the noise contribution from the main transconductor device M1 is ignored. The rest of two terms in (2-15) denote the noise contribution from the active inductor, yielding an excess noise figure of 11 dB. On the other hand, the extra power consumed by the active inductor is determined by the amount of current sink from node X from the current source, which is about 1.8 µA in simulation. Therefore, compared with the on-chip passive inductor, the implementation of the active inductor can enhance the front-end voltage gain with virtually no area penalty (in fact, saving area as compared to using passive inductors), at the cost of lower but tolerable noise performance (~11 dB excess noise figure) and slightly more (<1 µW) power consumption. 39  Chapter 3: Proof-of-Concept Circuits  3.1 A 32-μW Programmable Crystal-less Event-driven Receiver 3.1.1 Background Envelope detection-based receivers have been studied extensively in recent years due to its low cost and high energy efficiency property. However, it is challenging to meet the stringent size and power requirements of the implantable telemetry systems without compromising the performance of the receiver. In this section, a detailed noise analysis of an envelope-detector based receiver is presented. Then, an event-driven receiver with envelope detector that can provide programmable gain factors for desired input sensitivity is proposed.  3.1.2 Noise Analysis of the envelope-detector based receiver   Figure 3.1: Noise analysis model of the generic envelope detection-based receiver The noise model of the generic envelope detection receiver is shown in Figure 3.1. RF amplifiers are used to provide voltage gain to increase the signal level in order to overcome the noise generated in the following stages. However, the RF amplifier also contributes noise to the input signal, resulting in an inferior signal-to-noise ratio (SNR) at the output of the receiver. The envelope detector down-converts the input signal and the baseband signal components at the output of the envelope detector are amplified by the baseband amplifier. By low pass filtering at the output of the receiver, the desired signal is attained while the noise at higher frequencies is removed.   40  Due to the nonlinear behavior (squaring function) of the envelope detector, standard small-signal noise analysis in not valid. For better understanding and optimizing of noise performance, the main noise contributors can be classified into two categories, one is the RF front-end noise generated from the RF amplifiers, which is assumed to be a linear function for simplicity. Thus, the impact of the RF front-end noise can be represented by   𝑃𝑆𝐷𝐸𝐷,𝐼𝑁 = 𝐾𝐵𝑇 × 𝐴𝑅𝐹2 × 𝐹𝐿𝐼𝑁  (3-1)  where PSDED,IN is the noise power spectral density (PSD) at the input of the envelope detector, ARF is the voltage gain of the RF front-end, FLIN is the linear noise factor, KBT is the thermal noise floor which is −174 dBm at the room temperature. The noise at the input of the envelope detector is determined by the bandwidth (BWRF) of the RF front-end circuit, the total noise power (σ2ED,IN) can be estimated by using brickwall approximation (i.e. assuming white Gaussian noise in-band, and zero noise contribution from out-of-band).     𝜎𝐸𝐷,𝐼𝑁2 =  𝑃𝑆𝐷𝐸𝐷,𝐼𝑁 × 𝐵𝑊𝑅𝐹  (3-2) The signal power at the input of envelope detector is given as  𝑆𝐸𝐷,𝐼𝑁2 = 𝑃𝐼𝑁 × 𝐴𝑅𝐹2   (3-3) where PIN is the power of the input signal. After the non-linear squaring function, the variance of the noise at the output is given in (3-4) after Gaussian distribution estimation [76], where K is the conversion gain (scaling factor) of the envelope detector.  𝜎𝐸𝐷,𝑂𝑈𝑇2 =  4𝐾2𝑆𝐸𝐷,𝐼𝑁2 𝜎𝐸𝐷,𝐼𝑁2 + 2𝐾2𝜎𝐸𝐷,𝐼𝑁4   (3-4) Note that the noise from the baseband amplifier is neglected in the calculation while the signal at the output beyond BWBB is suppressed in order to improve the SNR, therefore, the receiver output SNR is given as 41   𝑆𝑁𝑅𝑅𝐹,𝑂𝑈𝑇 =𝑆𝐸𝐷,𝑂𝑈𝑇2𝜎𝑂𝑈𝑇2 =12𝐾2𝑆𝐸𝐷,𝐼𝑁44𝐾2𝑆𝐸𝐷,𝐼𝑁2 𝜎𝐸𝐷,𝐼𝑁2 +2𝐾2𝜎𝐸𝐷,𝐼𝑁4 ∙𝐵𝑊𝑅𝐹𝐵𝑊𝐵𝐵=𝑆𝐸𝐷,𝐼𝑁48𝑆𝐸𝐷,𝐼𝑁2 𝜎𝐸𝐷,𝐼𝑁2 +4𝜎𝐸𝐷,𝐼𝑁4 ∙𝐵𝑊𝑅𝐹𝐵𝑊𝐵𝐵   (3-5)   The SNRMIN represents the minimum achievement of the SNR at the output of the receiver, which can guarantee the proper demodulation of the input signal. In other words, the minimum power level of the input RF signal while the receiver’s output has achieved its minimum required SNR refers to the receiver’s input sensitivity (PSEN-RF).         𝑃𝑆𝐸𝑁−𝑅𝐹 = 4𝑆𝑁𝑅 𝐼𝑁𝐵𝑊𝐵𝐵𝐹𝐿𝐼𝑁𝐾𝐵𝑇 + 2𝐹𝐿𝐼𝑁𝐾𝐵𝑇√𝐵𝑊𝑅𝐹𝐵𝑊𝐵𝐵𝑆𝑁𝑅 𝐼𝑁 + 4𝐵𝑊𝐵𝐵2 𝑆𝑁𝑅 𝐼𝑁2      (3-6) The other part refers to the baseband noise from baseband circuits in the receiver. The SNR is given in  𝑆𝑁𝑅𝐵𝐵 =𝑉𝐼𝑁,𝐵𝐵2𝑣𝑛,𝑒𝑞2̅̅ ̅̅ ̅̅ ̅ =𝐾2𝐴𝑅𝐹4 𝑃𝐼𝑁2𝑣𝑛,𝑒𝑞2̅̅ ̅̅ ̅̅ ̅   (3-7) The power of input-referred baseband noise 𝑣𝑛,𝑒𝑞2̅̅ ̅̅ ̅̅  is mainly comprised of flicker and thermal noise and its spectrum profile is determined by the PSD of both noise sources. 𝑣𝑛,𝑒𝑞2̅̅ ̅̅ ̅̅  can be obtained by the integration of the noise PSD in the frequency range of interest, which is depend on the output bandwidth BWBB, data rate and the spectrum of the signal. Therefore, the minimum detectable signal power is   𝑃𝑆𝐸𝑁−𝐵𝐵 =√𝑆𝑁𝑅MIN𝐾𝐴𝑅𝐹2 ∙ 𝑣𝑛,𝑒𝑞  (3-8) Several important observations could be made from (3-6) and (3-8). The RF front-end noise that is mainly determined by RF amplifiers is linearly proportional to the noise factor FLIN. Moreover, a narrower BWRF and BWBB can improve the sensitivity, while the baseband noise is inversely proportional to K and the square of ARF. When ARF increases, the sensitivity improves dramatically, while optimizing K factor of the envelope detector without increasing the power budget is another option. It has been proved that for power budget below 100 μW, baseband noise 42  dominates the sensitivity of envelope detection based receiver [77]. Thus, the requirement on RF front-end noise is marginally relaxed and one can focus on a power efficient RF front-end circuit rather than a low-noise one.  3.1.3 Envelope Detector with Programmable Scaling Factor In an envelope detection-based receiver, the baseband noise power decreases quadratically as ARF increases. Thus, a higher front-end gain ARF is highly desirable to improve the sensitivity of the receiver.  However, the RF amplifier is normally the most power-hungry block in the receive signal path, therefore, the increase of its gain can result in a higher overall power consumption.  CLVinM1M2M1(a) (b)RDCLVinVbiasVoVoIDID Figure 3.2: a) Classic envelope detector topology; b) Envelope detector with scalable gain factor An alternative method to suppress noise and improve the sensitivity is to increase the scaling factor K of the envelope detector. The traditional structure of the envelope detector is based on a source-follower topology [78] as shown in Figure 3.2(a), the CMOS transistor (M1) behaves like a bipolar transistor by biasing it in weak inversion region so that the drain current (ID) is an exponential function of the input signal  𝐼𝐷 = 𝐼𝑏𝑖𝑎𝑠exp (𝑉𝑖𝑛𝑛𝑉𝑇⁄ )(1 − exp (−𝑉𝐷𝑆𝑉𝑇⁄ )) ≈ 𝐼𝑏𝑖𝑎𝑠exp (𝑉𝑖𝑛𝑛𝑉𝑇⁄ )  𝑇𝑎𝑦𝑙𝑜𝑟→    𝐼𝑏𝑖𝑎𝑠 + 𝐼𝑏𝑖𝑎𝑠𝑉𝑖𝑛𝑛𝑉𝑇+𝐼𝑏𝑖𝑎𝑠2(𝑛𝑉𝑇)2𝑉𝑖𝑛2 + ···  (3-9) 43  where VT is the thermal voltage (kT/q), and Ibias is the biasing current. The second-order term in the Taylor series expansion squares the input signal and generate the desired baseband signal. This yields the extracted circuit model of the envelope detector as shown in Figure 3.3. The load capacitor (CL) is connected to output and Ro is the equivalent impedance at the output of the detector. At the output node, the frequency bandwidth is determined by 1/(2π·RoCL), which is designed to be much lower than the incoming RF signal, but higher than the given baseband data rate. Therefore, the linear term at fundamental frequency and other higher harmonics are eliminated by the output low-pass filtering network. Although high-order terms in (3-9) also produce DC components, those contributions are too small to compare with the DC results generated from the second-order term. Assuming the incoming RF signal is simply defined by Vin·cos(ωRFt), the output voltage (Vo) is created when the drain current (ID) flows through Ro. As a result, the envelope of the RF input signal (Vin) appears across the gate-source node of transistor M1 is extracted at the output.  𝑉𝑜 = 𝐼𝐷 × 𝑅𝑜 =𝑔𝑚1𝑅𝑜4𝑛𝑉𝑇∙ 𝑉𝑖𝑛2  (3-10)  𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑐𝑜𝑛𝑣𝑒𝑟𝑠𝑖𝑜𝑛 𝑔𝑎𝑖𝑛 =𝑉𝑜𝑉𝑖𝑛=𝑔𝑚1𝑅𝑜4𝑛𝑉𝑇∙ 𝑉𝑖𝑛 = 𝐾 ∙ 𝑉𝑖𝑛  (3-11) CLVinV IVoID(·)2 +  Ro+   Figure 3.3: Brief circuit model of the envelope detector The voltage conversion gain is the function of the input RF signal and the scaling factor K is determined by the voltage gain of the envelope detector. There is an important observation from (3-12) that the source-follower topology does not provide any voltage gain. However, if a 44  common-source topology is employed in the envelope detector, the sub-threshold biased transistor M1 nonlinearly converts the input voltage into current, this current is then turned into a voltage by using the load resistance RD so that the new scaling factor becomes K' in (3-13). Therefore, we can have an extra gain factor if gm1RD is greater than 1. Based on this discussion, we utilize a programmable scaling factor common-source envelope detector as shown in Figure 3.2(b).   𝐾 =𝑉𝑜𝑉𝑖𝑛=𝑔𝑚14𝑛𝑉𝑇∙1𝑔𝑚1=14𝑛𝑉𝑇  (3-12)  𝐾′ =𝑉𝑜𝑉𝑖𝑛=14𝑛𝑉𝑇× 𝑔𝑚1𝑅𝐷  (3-13)  Figure 3.4: Sensitivity improvement of common-source envelope detector with scaling factor As a proof-of-concept, two gain settings are realized by variable RD. For the purpose of comparison, identical size and biasing condition are employed in the conventional source-follower and the proposed common-source envelope detector. The results presented in Figure 3.4 show that the receiver sensitivity is improved linearly with conversion gain as expected by equation (3-8). Black solid curve is the sensitivity of the conventional source-follower-based topology with the scaling factor of K, whereas the dash-dotted blue and dotted purple curves are for the sensitivity 45  of the proposed common-source topology with improved scaling factor K' that is realized by two gain settings of RD and 2RD, respectively. 3.1.4 Circuit Implementation and Measurement Results  The proposed proof-of-concept receiver is designed and fabricated in a 0.13-µm CMOS process and the chip is packaged in a 44-pin surface-mount ceramic quad flat package (CQFP). The chip micrograph is shown in Figure 3.5, and the active circuit area is about 0.208 mm2 (520 µm 400 µm) excluding the bondpads. The system operates from a 0.5 V supply in the ISM band of at 915 MHz which is within the frequency range that the body exhibits relatively low attenuation. The design details and measurement results of the main building blocks are discussed below.  Figure 3.5: Chip micrograph of the event-driven receiver Traditionally, RF amplifiers in the receiver signal path are designed to provide a reasonable voltage gain over the frequency band of the RF input signal while achieving a low noise figure, however, power efficiency and low area (for small size) are more important in IMDs. Therefore, in this design, instead of passive spiral inductors, on-chip active inductors are used as load in each stage to minimize the chip area. It has been proved in 2.2.3 that active inductors generate a higher noise as compared to their passive counterparts. However, as already mentioned in 3.1.2, a 46  reasonable amount of more noise can be tolerated in envelope detection-based receiver in RF front-end circuity. In this design, the input matching network is implemented fully on chip with a LC network as shown in Figure 3.6. Capacitors C1 and C2 form a capacitive transformer together with an inductor Lm and are tuned to match the impedance of the antenna to the input impedance of the RF amplifier in the desired frequency band. C1 is in parallel with Lm to adjust the resonant frequency of the network and C2 is used to have a better input return loss S11. By adjusting 8 control bits in the capacitor bank, appropriate input matching can be achieved from 850 MHz to 980 MHz while providing a passive voltage gain given in (3-14), where C1 and C2 are the value of capacitances, respectively.  𝑔𝑎𝑖𝑛 =(𝐶1 + 𝐶2)𝐶1⁄   (3-14)  Figure 3.6: Power-efficient two-stage RF amplifier with on-chip matching network In general, multi-stage amplifiers are often preferred considering the limited gain-bandwidth (GBW) product of a single-stage amplifier [37]. The schematic of a two-stage RF amplifier with active inductor as load is shown in Figure 3.6. In order to maintain proper operation of the active inductors, the bulk terminal of transistors M1-4 are forward biased to VDD/2 so that the resulting lower threshold voltage can conserve voltage headroom under low supply voltage. Transistor M1 47  is biased in the weak-inversion region for higher transconductance efficiency (gm/ID). The width of the cascode transistor M2 is sized one fifth of the width of M1 in order to reduce capacitive loading at the output node. The active inductor formed by transistors M3-5 is designed to synthesize a larger load impedance at the desired RF frequency than a typical passive on-chip inductor. A tunable voltage Vbias is provided to control the bias current for M3 and M4 so that the inductance value, equivalent impedance and resonance frequency could be adjusted through tuning gm3 and gm4. Furthermore, AC coupling capacitors are used between each stage so that biasing of stages are independent of each other and proper biases can be chosen to minimize the adverse effects of process variations. The detailed design parameters of the transistors and passive devices are concluded in Table 3.1.    Table 3.1: Design parameters of the complete RF amplifier with active inductor load Transistor M1 M2 M3 M4 Width/Length 25μm/120nm 5μm/120nm 5μm/250nm 3μm/120nm Transistor M5 M6 M7 M8 Width/Length 1μm/350nm 6μm/120nm 1.2μm/120nm 3μm/180nm Transistor M9 M10   Width/Length 2μm/120nm 1μm/350nm   Device C1 C2 Cc Lm Value 1.75pF 4.2pF 2pF 14.3nH  The S-parameter and voltage gain of the standalone RF front-end on the test chip are measured by a network analyzer which is directly connected to the receiver without preselect filter in order to present the intrinsic performance of the receiver. It should be noted that the input tunable matching network is set at 50 Ω match only for testing purpose and the matching network should be retuned if the receiver is connected to other non-50 Ω interfaces. As shown in Figure 3.7, the 48  input matching over the frequency range of 850 to 980 MHz is lower than −10 dB and within the desired ISM band is greater than −15 dB without any external matching components. It is worth mentioning that an output test buffer is designed on chip to drive the RF front-end output. Considering the gain loss of the buffer, the overall in-situ voltage gain of the entire RF front-end driving the envelope detector is about 20 dB. The noise figure of the standalone RF front-end is measured at 18.7 dB using a spectrum analyzer and a noise source. The overall power consumption of the RF front-end is 24 µW, and the measured 3-dB bandwidth of the RF amplifier is 98 MHz, wider than the ISM band due to low Q of passive on-chip inductor. It means that out-of-band signals could also converted down to the baseband by envelope detector and thus deteriorate the sensitivity performance. Thus, a SAW or micro-electro-mechanical system (MEMS) based preselect filter could be placed at the back of the chip in order to filter out out-of-band signals with minimal addition area.     Figure 3.7: Measured RF front-end adjustable input return loss S11 The envelope detector uses the same topology described in 3.1.3 and the detailed circuit schematic is shown in Figure 3.8. In the envelope detector, the second-order non-linearity is realized by transistor M1 that is biased in the weak inversion region. While another NMOS 49  transistor M2 creates an identical branch to generate a replica reference Vref that makes the rest of the baseband circuit differential. Offset between the signal path and reference path can be removed via tuning the bias voltage (Vtune) on the gate of transistor M2 so that the tail current in the reference path is independent from the current consumed in the signal path. Thus, this scheme provides an efficient way to remove input-referred offset of the continuous-time baseband amplifier.   Figure 3.8: Envelope detector circuit and 3-stage baseband amplifier The output signal of the envelope detector is amplified before it is passed to the quantizer through a three-stage resistive-load differential amplifier (Figure 3.8) which has cumulative gain of about 35 dB in simulation. As mentioned before, the programmable load resistor RD is used in the envelope detector and in the proof-of-concept design can provide two different scaling factor settings. Adjusting the gain with RD does not compromise the power consumption and improves the sensitivity by 3 dBm when RD increases by the factor of 2. The proposed receiver results from −50 dBm to −53 dBm sensitivity for 10−3 BER at 200 kb/s at 915 MHz for the two different gain settings. As shown in Figure 3.9, the total power consumption of the proposed receiver is 32 µW, the RF amplifiers draw about 75 % of the total power, with 24 µW while the envelope detector and baseband amplifier consume 6 µW and 2 µW, respectively. The power breakdown illustrates 50  the fact that active RF amplification still consumes most of the power by providing adequate gain at the RF front-end.   Figure 3.9: Power breakdown of the receiver  3.1.5 Summary In this section, a fully integrated ULP receiver for miniaturized biomedical implants is presented. Power-efficient front-end amplification is realized by two-stage amplifier with active inductor loads. Based on the presented noise analysis, a common-source envelope detector is used to improve sensitivity.  The proposed receiver consumes little power and area while offering a reasonable sensitivity without using any external components. Nevertheless, for this prototype, a one-time manual calibration is required to cancel the offset between signal path and replica path before testing by adjusting the current in the reference path. An efficient approach is to employ a calibration algorithm, which can be implemented in the digital domain using analog-to-digital converter (ADC) to adaptively adjust the bias current in the replica path. However, this method inevitably increases power budget, which motivates us to find a better solution for applications in IMDs.   51  3.2 Embedded RF switch for implantable telemetry systems 3.2.1 System Overview In this section, a custom CMOS IC based RF switch architecture is presented. It is used to operate enable control logic within on-chip regulators by a demodulated ISM band RF signal with multiple enable options.       Figure 3.10: RF start-up system block diagram Our start-up power circuit is placed between the RF link and the main implant telemetry system as shown in Figure 3.10. The circuit is controlled only by an external operator, thus preventing wasted power consumption when not in use. The complete system is comprised of a RF-to-DC converter, a demodulation block, a CDR and a Digital Control block. The multiple enables can provide switch on/off signals for various applications within a single RF telemetry system, for example, multiple voltage regulators or advanced control applications. The system is operated in the ISM 915 MHz band and utilizes a demodulation block (i.e. a receiver presented in 3.1) at the RF front end.  The received RF EM energy is first rectified and stored in an on-chip capacitor that provides a stable DC supply voltage for the CDR and digital control blocks. Furthermore, by implementing this technique, the start-up circuit blocks do not consume any energy from the implant’s miniature battery, thus prolonging the lifetime of the implant. Once the capacitor is charged and a stable 52  voltage (1.2 V) is created, the demodulated RF signal is used as the input of the CDR to recover clock and data information that is applied to the digital control to determine which enable to operate. 3.2.2 Circuit Implementation and Simulation Results (1) RF to DC Converter  The incoming EM signal must be converted to DC with high efficiency in order to provide a stable power supply rail. Here, a three stage CMOS differential rectifier [79] is used to convert RF power to a DC voltage as shown in Figure 3.11.    Figure 3.11: Three-stage differential RF-DC converter The gates of the MOS devices are connected through the capacitor to one end of the input terminal. When the voltage at the gate terminals of the MOS devices becomes positive, the NMOS device is turned ON with a large gate-source overdrive voltage. Conversely, when the gate voltage becomes negative, the PMOS device is turned ON. The rectifier is designed to output a 1.2 V DC supply voltage. (2) Clock and Data Recovery  CDR circuits have two main tasks: 1) the extraction of transmitted data information from the distorted input RF signal; 2) recovery of the clock signal that has a frequency equal to data rate with negligible drift. Monolithic high-speed CDR circuits have been widely used in optical 53  communication systems for years and have various architectures and specifications based on different application areas [80]. CDR circuits built in optical transceivers have very stringent jitter and loop bandwidth requirements resulting in complex topologies with high power consumption. On the contrary, in our application, the CDR is only required to identify ON/OFF modes and is not used for high speed data communication. In addition, the limited size and power demands require minimum analog front-end power consumption and less passive components. For our specific application, a single loop reference-less CDR is designed, that includes sub-blocks: phase detector (PD), voltage to current converter, loop filter, VCO, and re-time circuit, Figure 3.12.   Figure 3.12: Block diagram of CDR system The CDR used in this system is based on the Bang-Bang CDR architecture [81]. Although a common CDR architecture, loop parameters must be properly selected to ensure a low-power stable loop. A second-order low-pass filter is used in the loop, Figure 3.12, thus the CDR has a third order open loop transfer function (3-15) where KPD and KVCO refer to the gain of phase detector and VCO, respectively.  𝛷𝑠|𝑜𝑝𝑒𝑛 =𝐾𝑃𝐷𝐾𝑉𝐶𝑂(𝑠𝑅𝐶1+1)𝑠3𝑅𝐶1𝐶2+𝑠2(𝐶1+𝐶2)  (3-15) The closed loop CDR design parameters derived from control theory [82] are (3-16) where ζ represents the damping factor, ωn the natural frequency, and ω−3dB is the 3-dB bandwidth. 54   {    𝜁 =12𝜔𝑛𝑅𝐶1𝜔𝑛 = √𝐾𝑃𝐷𝐾𝑉𝐶𝑂𝐶1𝜔−3𝑑𝐵 = 2𝜔𝑛𝜁 = 𝐾𝑃𝐷𝐾𝑉𝐶𝑂𝑅  (3-16) The closed loop parameters (ζ, ωn and ω−3dB) can be adjusted to optimize for specific applications and specifications. For example, the larger ζ ·ωn, the lower the settling time; a smaller ω−3dB, the less ripple on VCO control voltage; the larger loop gain KPD·KVCO, the smaller static phase error. However, under all conditions, the CDR closed loop must be stable. In our application, the loop parameters are optimized for smaller on-chip resistor and capacitor values to reduce the area of our design. Specifically, the designed closed loop parameters are summarized as R is 328 Ω, C1 is 48.5 pF and C2 is 4.5 pF. The early-late phase detection method also known as the Alexander binary PD [83] is utilized is this CDR system and includes four low-power, high-speed performance Flip flops (DFFs) and two XOR gates [84]. This PD not only behaves as an edge detector, but also indicates when the data is leading or lagging the feedback clock signal. In practice, the Alexander PD has a finite slope for a small input phase difference which results in linear operation and a large phase error creates slewing behavior. A charge-pump (CP) topology is used to implement the voltage to current functionality. The CP responds to the PD output immediately, if data arrives earlier then the clock, current is sourced into control line and the VCO will speed up to minimize the phase difference. However, if the data is late, current will be sunk causing the control voltage to drop and the slowing the VCO to track the input. In this circuit, a fully differential four stage ring oscillator with multi-phase output is designed to reproduce the clock signal at the data rate frequency. The re-timing of the data is accomplished with DFF’s and the recovered clock. 55  (3) Digital Control Block The control unit operating in base band is usually more complex with multi-function such as detection, encoding, compression, modulation and demodulation and most of circuits are implemented in digital form. In this design, the digital control block’s main function is to take the re-timed data and clock signals from the CDR, extract the control information from the internal shift register and make decisions about which enable to turn on or off. The control information is encoded in a 20-bit packet format and is divided into three parts: the first 8 bits are the “data header”, the last 8 bits are the “data tail”, and the 4 bits payload command signal is in the center of the header and tail. The data header and tail are set by the user and are used to ensure no false positives are generated. The head/tail as well as payload must be confirmed, otherwise, the switch will be kept closed for any other combination. Moreover, the 4-bit payload control signal can allow up to 16 enables circuits to be controlled with full on/off capability.   Figure 3.13: The settling process of the control voltage in simulation The function of the entire wireless RF switch system is verified in simulation. After the required supply voltage is established in the RF to DC converter, system start to receive incoming RF signal that carries the user-defined data stream and then deliver the demodulated signal to CDR. 56  However, the CDR cannot operate properly and response to the input signal until its loop get locked as the control voltage of the VCO becomes stable. The settling time of the CDR is about 8.8 μs in simulation as shown in Figure 3.13, then it starts to recover the data and clock and they are provided to the following digital control block for further action. As a proof of concept, the recovered data sequence with the data rate of 1 Mb/s is repeated with alternating values of the payload to illustrate the enable signal. The enable signal outputs high when the payload is “1111” and remains low for all other signals. The enable is then connected to the LDO of the telemetry system to turn on the main battery power source, Figure 3.14. The synthesized layout for the digital control block as well as all other blocks in analog domain occupies approximately 176 μm  200 μm silicon area. Amplitude (V)0.20.400.810.6Time (μs)40 80 120 160 2000 0.2 Figure 3.14: Simulated control logic of the digital block  3.2.3 Summary We present our RF start-up power switch designed in 0.13-μm CMOS technology that is suitable for implantable devices. The RF switch uses a CDR system to extract control signals sent from the 57  user via RF link in the ISM 915 MHz band. The control signals are processed with a custom digital control block that will produce enable signals used in the main telemetry system to turn power ON/OFF. Data headers and tails are used to further increase data reliability and prevent false positives. The complete start-up RF switch circuit operates with 164 μW power from the CDR and can control up to 16 enable circuits within an implantable telemetry system. The low-power consumption and small area make this block suitable for implantable telemetry systems.  58  Chapter 4: An RF-Powered Crystal-Less Double-Mixing Receiver for Biomedical Implants 4.1 Introduction  In this chapter, a double-mixing receiver structure is proposed to eliminate the need for both external components and calibration overhead. Meanwhile, it is also robust to PVT variations, operating in the unlicensed ISM band ranging from 902 to 928 MHz which is within the frequencies for which the body exhibits relatively low attenuation. The receiver could be powered wirelessly using a far-field EM propagation method, which has a longer operation distance and better orientation immunity as compared to resonance and inductive links [12], [50], or via the power supply such as an implantable rechargeable battery that is better than a super charge reservoir capacitor [52], [55]. Meanwhile, custom ASK modulation is adopted in the proposed event-driven receiver. The rest of the chapter is organized as follows: in 4.2, system-level analysis of the proposed receiver architecture is presented. Circuit design and implementation details are described in 4.3. Measurement results and comparison with state-of-the-art designs are provided in 4.4. Finally, concluding remarks are given in 4.5.     4.2 System Overview In this section, the system-level theoretical analysis regarding the proposed receiver are discussed. We will then present design specifications for improved trade-off between power efficiency and system performance of the proposed receiver. 4.2.1 The Crystal-less Double-Mixing Architecture The complete block diagram of the proposed receiver is illustrated in Figure 4.1, comprising an RF-to-DC converter and a double-mixing receiver. The RF-to-DC converter serves as the power 59  source of the receiver that includes a matching network and a rectifier. The receiver core consists of an envelope detector, an IF band-pass amplifier, input and output mixers, an on-chip master clock and a delay cell.     Figure 4.1: Block diagram of the prototyped receiver The input RF signal is expressed in (4-1), where A0 is the amplitude of the carrier, ωRF is the angular frequency and φ is the phase of input signal.    𝑅𝐹𝑖𝑛 = 𝐴0𝑐𝑜𝑠(𝜔𝑅𝐹𝑡 + 𝜑)   (4-1) The on-chip clock generates a 50% duty cycle square wave alternating between 1 and 0 at clock frequency ωCLK, the first three major harmonics of the clock signal in Fourier expansion are taken into account as described in (4-2).     𝑉𝑐𝑙𝑘 = 12+2𝜋𝑐𝑜𝑠𝜔𝑐𝑙𝑘𝑡 −  23𝜋𝑐𝑜𝑠3𝜔𝑐𝑙𝑘𝑡 + ⋯  (4-2) Assuming the voltage conversion gain of the first mixer is G1 so that its output can be written as (4-3).                       𝑉𝑚1_𝑜 = 𝐺1 × 𝑅𝐹𝑖𝑛 × 𝑉𝑐𝑙𝑘  =𝜋𝐴0𝐺12𝑐𝑜𝑠(𝜔𝑅𝐹𝑡 + 𝜑) + 𝐴0𝐺1𝑐𝑜𝑠[(𝜔𝑅𝐹 ± 𝜔𝑐𝑙𝑘)𝑡 + 𝜑]  (4-3) The output current of the envelope detector is a nonlinear function which is also depends on the input signal and can be written as (4-4). 60   𝐼𝑒𝑛𝑣_𝑜𝑢𝑡 = 𝐼𝑜 +𝐼0𝑛𝑉𝑇𝑉𝑚1_𝑜 +𝐼02(𝑛𝑉𝑇)2𝑉𝑚1_𝑜2 +⋯  (4-4) During envelope detection, the input signal components at different frequencies are down-converted to baseband by the square function. The generated desired signal resides at clock frequency, meanwhile we also have DC component and twice of the clock frequency signal at the output. If we define k as a voltage scaling factor, the expression for the output of the envelope detector is given by (4-5).  𝑉𝑒𝑛𝑣_𝑜𝑢𝑡 = 𝐴02𝐺12𝜋2𝑘 {(1𝜋2+18) +1𝜋𝑐𝑜𝑠 𝜔𝐶𝐿𝐾𝑡 +1𝜋2𝑐𝑜𝑠 2𝜔𝐶𝐿𝐾𝑡}  (4-5) Note that the output of the envelope detector does not depend on the phase of the RF input signal, φ. Next, the signal spectral content around the clock frequency is selected by IF band-pass amplifier, and the output signal could be written as (4-6), where ABB is the voltage gain of the IF amplifier and the extra phase delay due to the IF amplifier stage is denoted by φ'. This phase shift can be estimated by the expression that is given in (4-7), where ωIF and ω-3dB are the center frequency and the bandwidth of the IF band-pass amplifier. For simplicity, the phase delays introduced by the input mixer and envelope detector are neglected, since the bandwidth of these blocks is typically much larger than that of the IF band-pass amplifier.     𝑉𝐵𝐵_𝑜𝑢𝑡 = 𝜋𝑘𝐴𝐵𝐵𝐴02𝐺12 𝑐𝑜𝑠(𝜔𝑐𝑙𝑘𝑡 + 𝜑′)  (4-6)  𝜑′ = 𝑡𝑎𝑛−1[𝜔𝑐𝑒𝑛𝜔−3𝑑𝐵(𝜔𝑐𝑒𝑛𝜔−𝜔𝜔𝑒𝑛)]  (4-7) The IF band-pass amplifier output is then mixed with the two clock signals, CLK'+ and CLK'– that are generated by the delay cell and are non-overlapping clocks with 25% duty cycle. The clock signals are derived from the LO signal, thus the clock signals track the master LO and any uncertainty in the master LO is also observed by the clock signals. On the other hand, the phase delay, denoted by φ'', is introduced by the delay cell circuit. It is optimized in the design to 61  compensate for the phase delay of the IF band-pass amplifier, namely, φ'. The clock signal is toggling between 1 and –1 that is generated for the second mixer expressed as  𝑉𝑐𝑙𝑘′ =  4𝜋𝑐𝑜𝑠(𝜔𝑐𝑙𝑘𝑡 + 𝜑′′)  −  43𝜋𝑐𝑜𝑠(3𝜔𝑐𝑙𝑘𝑡 + 𝜑′′) + ⋯  (4-8) Assuming the voltage conversion gain of the second mixer is G2 the output of the mixer can be written as (4-9). Note that only the desired signal at clock frequency is down-converted to baseband whereas the low frequency noise and DC offset are up-converted to clock frequency, which is suppressed by the subsequently low-pass filter. The output amplitude, to some extent, is affected by the relative phase discrepancy (φ'–φ'') due to PVT variations. Nevertheless, this effect is minimized as long as φ' is designed to be close to φ'' (i.e., cos (φ'– φ'') ≈ 1), so that the receiver is still robust to clock uncertainty and is suitable for single-chip implementation.  𝑉𝑚2_𝑜 = 𝐺2 × 𝑉𝐵𝐵_𝑜𝑢𝑡 × 𝑉𝑐𝑙𝑘′    = 𝑘𝜋2𝐴𝐵𝐵𝐴02𝐺12𝐺2[2𝜋𝑐𝑜𝑠(𝜑′ − 𝜑′′) +2𝜋𝑐𝑜𝑠(2𝜔𝑐𝑙𝑘𝑡 +   𝜑′ + 𝜑′′) −23𝜋𝑐𝑜𝑠(2𝜔𝑐𝑙𝑘𝑡 +𝜑′ − 𝜑′′) −23𝜋𝑐𝑜𝑠(4𝜔𝑐𝑙𝑘𝑡 + 𝜑′ + 𝜑′′)]𝐿𝑃𝐹→  2𝑘𝜋𝐴𝐵𝐵𝐴02𝐺12𝐺2 cos(𝜑′ −𝜑′′)                                   (4-9) To sum up, the receiver could be considered as a double-mixing topology, consisting of input, output mixing and one-time self-mixing in the envelope detector, eliminating the need for the crystal oscillator and any calibration overhead. The proposed receiver holds advantages over other state-of-the-art designs. Firstly, the requirements on the frequency accuracy, stability, and jitter of the on-chip LO are significantly relaxed. Secondly, the design is resilient to the unwanted DC components generated by the self-mixing behavior of the envelope detector. In addition, the low frequency noise and DC offsets could not distort the received information because the desired signal resides at the clock frequency. Thirdly, there is no special requirement on internal demodulation and external modulation to ensure a simple topology and reduce cost without any 62  latency. Finally, the signal amplification is performed at IF rather than RF frequency which also conserves power consumption. 4.2.2 Requirements on Sampling Clock  Among different topologies for generating clock, CMOS ring oscillators are low power and low cost (i.e., require low amount of area) as compared to their LC counterparts, however, due to their high sensitivity to PVT variations, low frequency stability and poor phase noise, an off-chip crystal is often used as the reference clock. The proposed receiver overcomes these issues at architecture level by employing double-mixing receiver structure to relax frequency accuracy and stability requirement. Nevertheless, explicit analysis and simulation are necessary for the free-running on-chip clock to accommodate the large frequency variations in CMOS process.   Figure 4.2: (a) Clock frequency change due to PVT variations, (b) Monte-Carlo simulation results. The choice of sampling clock frequency depends on the data rate and low frequency noise which may range above 1 MHz in modern sub-micron transistors. To be specific, the clock frequency in typical designs could not be arbitrarily low since reliable operation need to be guaranteed in worst-case scenario. Thus, a worst case 5 MHz clock frequency is chosen in this prototype to provide a better trade-off and offer enough design margin (5 times higher than 1 MHz) 63  in order to cover the full range of variation possibilities. To be specific, such implantable system would be able to handle ±10% power supply variation, slow to fast process corner variations and human body temperature change which is normally between 32 and 42 ℃, as shown in Figure 4.2(a), the variations of clock frequency change from 5 MHz to 10 MHz. Monte Carlo simulations are performed to verify the robustness of generated clock signal. Figure 4.2(b) shows the simulation results where the mean value of clock frequency is 7.2 MHz with the standard deviation of 1.24 MHz at 36.5 ℃ human body temperature.     Figure 4.3: Double-mixing operating method in frequency domain The proposed receiver overcomes the drawbacks of the traditional envelope-detection-based receivers by exploiting double-mixing architecture to address the clock variations and to improve the receiver sensitivity. Figure 4.3 shows the frequency domain operation of the system. The narrow band input matching network filters out the signal images and out-of-band interferences. Then, the passing RF signal is mixed with the on-chip master clock by the first mixer, thus creating two sidebands located at fRF ±fclk that are amplified by the RF amplifier and fed into the envelope detector. Note that without calibration these two side bands have an uncertain frequency range (as shown by the dashed spectra in Figure 4.3). During the envelope detection, the squaring function down-converts signals at different frequencies indiscriminately. However, the desired signal 64  resides at fclk instead of DC, and thus it is not affected by the low frequency noise. Then the following IF band-pass amplifier amplifies the desired signal at fclk while attenuating other frequency components at the output of the envelope detector. Finally, the second clock signal derived from the master clock through the delay cell accomplishes the final down-conversion in the output mixer. At the same time DC offsets, flicker and other low frequency noise are up-converted to fclk, which are suppressed by the following passive low pass filter at the output of the receiver, thus improving SNR of the receiver. Note that the SNR is mainly determined by the low-frequency noise (mostly flicker noise) at the baseband especially for low data rate applications.  4.3 Circuit Implementation  In this section, the circuit design of main building blocks of the proposed receiver is presented. Designing a clock generator and an IF band-pass amplifier is specially challenging for the low supply voltage designs. However, the design requirements are significantly relaxed by using the proposed architecture of the receiver. It only requires low frequency clock generator and narrow band IF amplifier. 4.3.1 RF-to-DC Converter  The purpose of RF-to-DC converter is to provide a stable DC voltage from the incident RF waves and utilize the retrieved voltage as power supply of the receiver. Figure 4.4 shows the schematic of the RF-to-DC converter. A transformer-based matching network is co-designed with the two-stage rectifier [79]. The primary winding of the transformer is connected in series with the CS and the secondary winding is connected to the differential input of the rectifier. The equivalent input capacitance of the rectifier and the equivalent inductance of the transformer winding forms a parallel LC tank, therefore the voltage across the input is boosted at resonance. The primary and secondary windings are designed and laid out in an interleaved formation for better coupling 65  coefficient. The turn ratio between two windings in the on-chip step-up transformer is 3:9 to provide passive voltage amplification hence increase the available voltage when input power is low.     Figure 4.4: Schematic of matching network and voltage rectifier The CMOS rectifier is based on the differential self-threshold voltage (Vth) cancellation structure [85] designed to provide higher power conversion efficiency at low input power levels. Transistor M1 to M8 operate as switches in rectifier and the gates of the MOS devices are connected through the capacitor to one end of the input terminal. When the voltage at the gate terminals of the MOS devices becomes positive, the NMOS devices are turned ON. Conversely, when the input voltage becomes negative, the PMOS devices are turned ON. Employing more stages of rectifier would be favorable for larger output voltage generation, but it will inevitably deteriorate the power efficiency of the system. The rectifier is designed to supply a 500 mV output DC voltage (VDC). Depending on the application, VDC can be further increased if the output supply current is limited to a lower level. 4.3.2 On-chip Sampling Clock and Delay Cell  Traditionally, the basic ring oscillator uses an odd number of inverters connected in a chain that satisfies Barkhausen criteria to sustain oscillation. The oscillating frequency depends on the delay time between each inverter stage, which could be controlled by the branch current to improve the 66  frequency stability and power efficiency. For this application, the on-chip free-running LO is generated by a current-starved ring oscillator as shown in Figure 4.5 where transistors M1–M6 form a 3-stage CMOS inverter chain and transistors M7–M9 and M10–M12 operate as current sources.  Figure 4.5: Schematic of clock signal generation The oscillation frequency is determined by equation (4-10), where ID is the bias current in each inverter stage, N is the number of stages and VDD is the supply voltage. Ctot is the total capacitance seen at the output of each inverter stage as written in (4-11), Cox is the gate oxide capacitance per unit area, Wn, Ln and Wp, Lp represent the width and length of NMOS and PMOS transistors, respectively. The pulse width shaping circuit consists of a D-flip-flop and LO buffers. To be specific, the clock division is performed by a D-flip-flop, which reduces the jitter and provides a 50% duty-cycle clock signal. The delay cell is used to generate the clock signal for the input and output mixer blocks.  𝑓𝑜𝑠𝑐 =𝐼𝐷𝑁𝐶𝑡𝑜𝑡𝑉𝐷𝐷  (4-10)  𝐶𝑡𝑜𝑡 = 𝐶𝑜𝑥(𝑊𝑛𝐿𝑛 +𝑊𝑝𝐿𝑝) +32𝐶𝑜𝑥(𝑊𝑛𝐿𝑛 +𝑊𝑝𝐿𝑝)  (4-11) As illustrated in Figure 4.6, the logic circuits including the inverters and NOR gates are used to generate clock signals CLK'+ and CLK'– for the output mixer. These signals are delayed and buffered by a chain of current-starved inverters. The delay time is designed and optimized to 67  compensate the phase delay in IF band-pass amplifier. On the other hand, the CLK_B signal is acquired through a three-stage inverter buffer to drive the input mixer.  Figure 4.6: Block diagram of the delay cell 4.3.3 Input Mixer The input mixer performs mixing between input RF signal and clock signal. Figure 4.7 illustrates a single-ended dual-gate mixer, which is driven by the CLK_B on the gate of transistor M2. This clock signal is directly coupled to the output through gate and drain capacitance (Cgd) of M2, thus distort the output signal. By employing the LC load resonant tank to enhance the frequency selectivity property, the low-frequency clock feedthrough signal at the output node is filtered out before arriving at the input of the envelope detector.  Figure 4.7: Schematic of the input mixer 68  As M2 is driven by the rail-to-rail clock signal, it could be modeled as an on-off switch that is modulating the drain current of transistor M1. The input RF signal is applied to the gate of M1 through the matching network, while the DC bias voltage is applied to the gate via an on-chip resistor. The voltage conversion gain, G1, of the first mixer can be calculated using Fourier series in (4-12), where gm1 is the transconductance of transistor M1, RP is the equivalent load resistance at resonance that is determined by the resonant frequency, ωRF, inductor value L and its quality factor QL. A series spiral inductor is optimized for maximum L·QL to reduce gm1, which would further conserve power of the input mixer. To be specific, the on-chip inductor that has a higher inductance per unit area is chosen to resonate with parasitic capacitance in order to improve the overall quality factor of the resonant load. The design parameters of the inductor L and the transformer used in matching network are summarized in Table 4.1.  𝐺1 =1𝜋𝑔𝑚1𝑅𝑝 =1𝜋𝑔𝑚1𝜔𝑅𝐹𝐿𝑄𝐿  (4-12) Table 4.1: Transformer and Inductor Parameters Transformer Inductor L Width Spacing Primary Coil Width Spacing 5 µm 5 µm 2 nH 5 µm 5 µm Turn Ratio k factor Secondary Coil Q @ 915 MHz Inductance 3:9 0.8 14 nH 12.3 16.4 nH  4.3.4 Envelope Detector The envelope detector circuit shown in Figure 4.8 is based on a common-source topology with an RC load where transistor M is biased in weak inversion region to maximize the second-order nonlinearity. The output signal of the input mixer is squared, and the resulting signal at high frequencies is suppressed by the load with low-pass filter. Therefore, the desired signal at the 69  output of the envelope detector resides at the clock frequency instead of DC. The low frequency noise and DC components can be removed by adding an AC coupling capacitor between the envelope detector and the IF band-pass amplifier.     Figure 4.8: Schematic of envelope detector The voltage conversion gain of the proposed envelope detector is the function of the input signal magnitude given in (4-13), where gm is the transconductance of the transistor M, n is about 1.5 in a 0.13-µm CMOS process.   𝑔𝑎𝑖𝑛 = 𝐾′ · 𝑉𝑖𝑛 =𝑉𝑖𝑛4𝑛𝑉𝑇∙ 𝑔𝑚𝑅𝐷  (4-13) 4.3.5 IF Band-pass Amplifier  As clarified in the architecture-level discussion, the active amplification stages must provide adequate gain for the output of envelope detector across the frequency range of the on-chip free-running clock. Therefore, the IF band-pass amplifier is adopted to amplify and further suppress the undesired signals prior to being processed by the output mixer. It consists of input and output amplifiers and the circuit configuration is shown in Figure 4.9. The input amplifier converts its single-ended input signal into a differential output. It is realized by differential input NMOS transistors M1 and M2 operating in the weak-inversion region in order to attain high transconductance efficiency. The load resistance, RL, contributes less noise as compared to using 70  a current source load. The output amplifier utilizes a fully differential two-stage topology with its input transistors M4 and M5 directly connected to the differential output of the input amplifier. Transistors M8 and M9 form the current source load for the first stage and the second stage is implemented by a push-pull structure to ensure a rail-to-rail output swing.  Figure 4.9: Schematic of the IF band-pass amplifier  Figure 4.10: Schematic of the common-mode feedback network The IF band-pass amplifier is operated in an open-loop fashion instead of a closed-loop configuration to conserve power and reduce the cost. In addition, frequency compensation is not necessary for differential operation mode. However, a common-mode feedback (CMFB) block as shown in Figure 4.10 is critical to make sure the output common-mode voltage at the half level of 71  the power supply in order to facilitate the largest possible output swing. To be specific, the CMFB circuit is designed to set the output common mode voltage to Vref, which is set to VDD/2 in order to maximize the output swing. Note that the smaller size of transistors is used to conserve power. Frequency compensation of the CMFB loop is achieved by capacitor Cc. Furthermore, the source degenerated resistor Rs is used to provide a better control over the gain of the output stage determined by the system-level analysis and simulations. On the other hand, the AC coupling capacitor Cc at the input of the amplifier rolls off the IF gain close to DC, resulting in a band-pass frequency response. This technique also helps in preventing voltage offsets accumulated through IF amplifier stages. The simulated transfer function of the complete IF band-pass amplifier is shown in Figure 4.11 with parasitic extraction from the final layout. The –3-dB bandwidth is from 1.1 to 10 MHz, with the peak voltage gain at around 34 dB.      Figure 4.11: Post-simulated IF band-pass amplifier frequency response 4.3.6 Output Mixer The output mixer is utilized to down-convert the desired signal at the output of the IF band-pass amplifier. The schematic is illustrated in Figure 4.12. It is a double-balanced passive mixer that effectively reduces the LO to DC feedthrough and charge-injection effects of MOS switches [60]. 72  Compared with its active counterpart, the passive mixer does not contribute any low frequency noise because there is no DC current flowing inside, therefore it would be a suitable choice for the second mixer as the noise contribution at this stage will directly appear at the output of the receiver and affects the noise performance of the system. Transistors M1-4 form four switches driven by clock signals CLK'+ and CLK'–. The output signal is held on the output capacitor CLP with the bandwidth being limited to 400 kHz. The voltage conversion gain, G2, is given as 2/π. The capacitor Ci is used at the input to absorb the charge injection when MOS transistors are switched on and off, thus stabilizing the common-mode voltage at input node.   Note that all the dc bias voltages used in the abovementioned blocks are provided by the biasing circuit through a high impedance resistor. With the circuit topologies and design parameters established above, the input output relationship could be rewritten as (4-14).    𝑉𝑜𝑢𝑡 𝑉𝑖𝑛⁄ =𝐴02𝐴𝐵𝐵𝑔𝑚𝑔𝑚12 𝑅𝐷𝑅𝑃2𝑉𝑖𝑛𝐷𝑛𝜋3𝑉𝑇⁄   (4-14)  Figure 4.12: Schematic of the output mixer It is almost impossible to perfectly match the phase delay between clock delay cell and the IF amplifier across PVT variations. The changing trends of the two blocks are the same, however, with different degree of variations. Thus, system level optimization, simulation and verification are performed in this design to prove that the proposed receiver has reasonable tolerance across 73  PVT variations. Thanks to the double-mixing architecture, the blocks such as clock generation, delay cell and bandpass amplifier are operating at IF frequency. Since, due to PVT variations, the center frequency varies by a certain percentage on a chip and from chip to chip [86], operating at a low IF frequency will have significantly lower variation as compared with operating at a high RF frequency. Nevertheless, elaborate simulations and verifications are critical to make sure that the output signal will not vanish due to PVT variations. The post-layout simulated waveforms of the clock signal after delay cell and the differential output signal of the IF band-pass amplifier under different corners are compared in Figure 4.13. The relative delay discrepancy between receiver chain and the delay cell is varying from 1.2 to 8.4 ns under different process corners. To be specific, the reference line is designed under tt (typical-typical) corner Figure 4.13(a) at   Figure 4.13: Clock and IF amplifier output waveforms in different corners 74  nominal human body temperature 36.5 ℃, the relative delay discrepancy is about 1.2 ns with the clock cycle of 139 ns. As illustrate in Figure 4.13(b) and (c), from ff (fast-fast) to ss (slow-slow) corner, the relative delay discrepancy is changing from 5.1 to 8.4 ns with 112 and 182 ns clock cycles, respectively. Therefore, the worst-case scenario happens in ss corner with equivalent 16.6 phase discrepancy. Secondly, simulations under temperature variations between 32 and 42 ℃ are verified, the delay variation is between −0.68 ns at 32 ℃ and +0.54 ns at 42 ℃ with reference to the nominal delay at 36.5 ℃, resulting in a maximal equivalent phase discrepancy of 2.2. Finally, the variation caused by ±10% power supply is evaluated by simulations as well. The delay variation is between –4.6 ns and +5.4 ns, leading to maximum equivalent phase discrepancy of 10.7. The signal loss is proportional to the phase mismatch as captured by D = cos (φ'–φ''). Therefore, the worst-case signal degradation due to the PVT variations (PVT) is summed up at about –1.2 dB in (4-15), which can be tolerated in most cases. This implies that the receiver is robust to PVT variations even without any calibration overhead.    𝑃𝑉𝑇 = −20 𝑙𝑜𝑔[𝑐𝑜𝑠(16.6 + 2.2 + 10.7)] = −1.2 𝑑𝐵  (4-15) 4.4 Measurement Results and Discussion  As a proof-of-concept, the proposed receiver is designed and fabricated in a 0.13-µm CMOS process and the die is packaged inside a 44-pin surface-mount CQFP for measurement purpose. The die micrograph is shown in Figure 4.14. The active circuit area excluding the pads is about 0.75 mm2 (1.0 mm × 750 µm). The receiver operates in the ISM band of 908–928 MHz without any external components since all the employed inductors and capacitors are implement on chip. The measurement results of the main building blocks are illustrated and discussed below. 75   Figure 4.14: Chip microphotograph  Figure 4.15: (a) Measured transient waveform and (b) Measured frequency spectrum of clock signal A standalone clock generation block is included on the chip for the purpose of characterization. The test clock signal CLK_B is connected to a Rohde & Schwarz RTO1044 real-time oscilloscope through a single-ended active probe. The active probe is used to minimize the loading effects of the measurement equipment. The measured clock signal is plotted in Figure 4.15(a) and has a peak-to-peak swing (VPP) of 500 mV at room temperature (25 ℃) and the 76  nominal clock period, T, is 180 ns. The frequency spectrum of the clock signal is illustrated in Figure 4.15(b), where the nominal oscillation frequency of the clock is 5.56 MHz with the power level of –1.8 dBm.  Figure 4.16: (a) Clock frequency drift with temperature change, (b) Clock frequency stability feature over 30 days In order to verify the process deviation, five different die samples are tested, and each sample is measured while its ambient temperature was changing between 32 to 42 ℃ that covers a reasonable temperature range for the human body. The ambient temperature is monitored and controlled by a Signatone Digital Hot Chuck Model S-1045. As shown in Figure 4.16(a), over the temperature range of interest, the clock frequency changes within the range of 6 MHz and 7.2 MHz for all the five chip samples. Since the receiver is intended to implant inside of the patient’s body, a long-term transient stability is another critical property of the proposed receiver. To quantify its long-term operation, the frequency of the on-chip clock was measured over a one-month period 77  while the environmental temperature was kept around 36.5 ℃ (nominal human body temperature). Figure 4.16(b) illustrates that the measured frequency varies between 6.1 MHz and 7.06 MHz over the 30-day continuous monitoring period for five different samples. The measured clock frequency variation range for both short and long-term operations is well within the bandwidth of IF band-pass amplifier. An Agilent (Keysight) E5061B network analyzer is used to characterize the input node of the receiver. As shown in Figure 4.17, center frequency of the matching network is around 915 MHz and the input reflection coefficient (S11) over the frequency range of 902-928 MHz is varying between –16 and –19.3 dB, covering the desired band without any external matching components. For all the sample chips used, the variations of the input matching would not affect the receiver measurement accuracy. On the other hand, the input carrier signal is generated from the Agilent (Keysight) 8648D signal source modulated by an Agilent (Keysight) 33250A arbitrary waveform generator. This setup facilitates generating test signals with different modulation data for the proposed receiver.  Figure 4.17: Input reflection coefficient (S11) 78   Figure 4.18: (a) Input and output signal waveform of RF-powered receiver, (b) Rectified DC signal settling procedure The measurement is performed in two different scenarios to characterize the RF power harvesting and the performance of receiver. The receiver can achieve the data rate that is scalable from 1 Hz to 100 kHz in both cases. Such data-rates can accommodate transferring various kinds of bio-signals. In the first scenario, a –10 dBm available input power is applied to the RF-to-DC converter and it generates an output voltage of 0.5 V for the rest of the circuit. In order to generate this voltage level, the RF-to-DC converter requires a voltage swing of at least 0.9 VPP at its input. Figure 4.18(a) shows an RF signal encoded with a 1 and 0 on 915 MHz carrier frequency with 10% modulation index received at the input of receiver. The receiver output (i.e., the output of the second mixer) is acquired by using a differential active probe at the voltage level of 61 mV. In addition, the output of the RF-to-DC converter is captured by the RTO1044 oscilloscope after the receiver starts to receive the RF signal. With a 120-pF on-chip metal-insulator-metal (MIM) decoupling capacitor, the settling time of the output dc voltage is measured at 22.1 µs and the ripple is about 3.13 mV, as shown in Figure 4.18(b).  79  Table 4.2: Power Breakdown of Proposed Receiver Building Block Power Dissipation Percentage Input Mixer 2 µW 21.98 % Envelope detector 1.2 µW 13.19 % IF Amplifier 5.1 µW 56.04 % Output Mixer 0 µW 0.00 % Uncertain Clock & Delay Cell 0.6 µW 6.59 % Bias 0.2 µW 2.20 % Total Power 9.1 µW 100 %  In the second test scenario, a 0.5 V power supply is applied and the RF-to-DC converter is disabled. The power breakdown of the proposed receiver is presented in Table 4.2. The total power consumption of the proposed receiver is 9.1 µW. The IF band-pass amplifier consumes 5.1 µW, about 56% of the total power. The first mixer consumes around 2 µW whereas the second mixer is a passive mixer and does not consume any power. The on-chip clock and its delay cell circuit including buffers consume 0.6 µW of power and the envelope detector and bias circuit account for the remaining 1.4 µW.  Figure 4.19: Output signal level and noise PSD of the receiver 80  Table 4.3: Receiver Performance Summary and Comparisons Items References [38] [37] [22] [41] Objective Ⅰ Objective Ⅱ Technology 90nm 130nm 180nm 40nm 130nm 130nm Carrier (MHz) 2000 915 915 1850 915 915 Supply  0.5 V 0.5 V Inductive -coupling EM 0.5 V EM 1.1 V 0.5 V Modulation OOK OOK OOK Mach. ASK OOK ASK Data Rate (kbps) 100 100 40.7 2500 200 1/10/100   Sensitivity (dBm) –72 –75 -- 3 -53 –10 –25 –48/–43/–39 Active Power (µW) 52 22.9 71.6 9.4 34 9.1 Chip Area (mm2) 0.1 0.2 2.5 0.8 0.208  0.75 Crystal NONE XTAL NONE NONE NONE NONE Calibration   off-line Manual off-line Auto NONE NONE off-line Manual NONE  Table 4.3 summarizes the overall performance of the proposed receivers and compare them to the state-of-the-art published ULP receivers. All the presented data are measured results and only sub-100 µW receivers are considered for comparison. When the proposed receiver is powered by the RF-to-DC converter, the functionality range is limited by the rectifier as it requires a minimum voltage swing to be able to generate the intended power supply. Nevertheless, when the receiver is powered by a 0.5 V voltage supply and a –30 dBm OOK modulated signal is given at the input, the output signal power and the output noise PSD with respect to the modulation rate are plotted in Figure 4.19. Both output signal and noise spectrum are flat when baseband frequency varying between 1 Hz and 100 kHz. The noise PSD is integrated within the twice of the signal bandwidth and is compared with the signal power level in order to calculate the SNR of the receiver. Figure 4.20 illustrates the measured output SNR as a function of the input power with different 81  data rata settings. An output SNR of higher than 12 dB is required for demodulation of an OOK modulated signal that could achieve a bit-error-rate (BER) lower than 10–3 [87]. At the data rate of 100 kb/s, the receiver achieves the sensitivity of –39 dBm. If the data rate is reduced to 10 and 1 kb/s, the sensitivity improves by 4 and 9 dB achieving –43 and –48 dBm, respectively. Such sensitivities compare favorably with other works and satisfy the requirements discussed in 1.3.3 for short range in-vivo wireless communication.  Figure 4.20: Measured output SNR with respect to input power on different data rate The entire system is monitored over a time span of 30-day continuous operating time on the five different samples at an ambient temperature that is equal to that of the nominal human body temperature. During the tests, we did not witness any disturbances, interruptions of operation, or faultiness in the output signal that also confirm the long-term stability property of the proposed receiver. Note that the proposed receiver could work correctly even if the supply voltage goes as low as 0.44 V. In addition, the system is also immune to clock jitter, the measured peak-to-peak jitter of the clock signal in Figure 4.15 is about 19 ns, 10.56% of the clock period. The measurement results confirm that this jitter has a negligible impact on the operation of the proposed 82  receiver, which further proves the architecture’s robustness and tolerance to the variations of the clock frequency. For the sake of comparison, the output signal is also calculated using (4-14) at an output power level of –11.3 dBm with all the parameters provided from post-layout simulation results, which is 1.3 dBm higher than the achieved measurement results at output. Nevertheless, the simulation results are very close to the measurements.  Figure 4.21: Experimental setup for the RF wireless link An experimental setup is shown in Figure 4.21, it is used to further verify the function of RF wireless link. The IC chip is packaged and accommodated on a FR4 PCB board with the dimension of 2 cm1.8 cm. A commercial 915 MHz whip antenna is used as the receiving antenna in the experiment. The effect of the commercial antenna is de-embedded based on its features provided in data sheet. Furthermore, the antenna with SMA connector has a compact housing with the length of 4.1cm and the diameter of 0.8 cm. In this setup, another discrete transmit antenna is connected to a Rohde&Schwarz SMB-100A signal generator as the external hub in order to deliver an OOK modulated signal to the receiver wirelessly. The receiving antenna is surrounded by a piece of 5 cm thick pork meat which includes skin and fat tissue. The distance between the SMB and the receiving antenna is 1.7 m and a successful wireless data link is established with the data rate of 83  100 kb/s on the 915 MHz carrier with a BER of lower than 10–3. To test the wireless power harvesting feature of the circuit, the transmitter is moved closer to about 0.6 m away from the receiving antenna to establish the wireless power link from an RF signal that is in compliance with the FCC rules.   4.5 Summary  A fully integrated ultra-low-power event-driven receiver optimized for biomedical implants is developed in this chapter. The requirements and features of biomedical implants are discussed. A crystal-less double-mixing architecture is proposed to simplify the system structure, reduce power consumption and overcome PVT variations. The proposed receiver can tolerate the frequency instability of the on-chip clock generator that is addressed at the system level. Moreover, the receiver does not require any complex modulation scheme while maintaining simplicity and low latency without any external components or calibration overhead. Furthermore, the system can operate by RF power harvesting using an integrated RF-to-DC converter or via an alternative power source (e.g., a rechargeable battery) to accommodate different biomedical application scenarios. Consequently, the receiver shows a significant potential for the implementation in miniaturized IMDs. 84  Chapter 5: An Ultra-Low Power Crystal-Free, Battery-Less TDD Radio for Miniaturized Biomedical Implants 5.1 Introduction  A self-sustained fully integrated and versatile ULP radio suitable for miniaturized implantable systems is presented in this chapter. In order to address the design challenges and implement limitations in 1.4.2, three techniques are proposed and used in the design:  1) The receiver that is based on the double-mixing topology presented in Chapter 4 is implement. It is re-designed to have an improved input sensitivity by employing an RF amplifier at the RF front-end for an extended range of downlink data communication.    2) A ULP active transmitter is designed to reduce both instantaneous and average power consumption with the limited amount of harvested energy. The transmitter is realized by an output buffer that is codesigned with a free-running LO in order to reuse the core current. The proposed transmitter obviates the need for the usage of an energy intensive PA and bulky off-chip matching networks.  3) A real-time smart control module (SCM) is integrated to facilitate an intelligent duty-cycling technique so that the radio can coordinate two different modes of operation in a time-division duplexing (TDD) manner. This technique improves the overall energy efficiency and reduces the system latency.    The rest of this chapter is organized as follows. In 4.2 system overview of the proposed transceiver architecture is presented. Circuit design and implementation methodology for building blocks are described in 4.3. Experimental results and discussions are presented in 4.4. Finally, 4.5 provides concluding remarks.    85  5.2 System Overview As shown in Figure 5.1, the radio system consists of a RF-to-DC converter, a double mixing receiver, a data transmitter, and the SCM. The proposed prototype does not employ any off-chip components neither it has any calibration overhead, resulting in a ULP and miniaturized solution.  The energy harvesting block converts the continuous incident EM waves into DC voltage for the rest of the blocks. After the required supply voltage is established, the radio system starts to work in monitoring mode, that is, the receiver keeps listening to the channel and the demodulated signal that contains commends delivered from the external hub is verified by the SCM. The transmitter starts to send output data only if a valid identification code is confirmed. At the same time, the system enters interrogation mode and the receiver is turned off to conserve power. The receiver and transmitter work independently in different time slots, which leads to reduced average power while the interaction between up and downlink data transmission is circumvented, thus, eliminating the usage of the circulator or duplexer.   Figure 5.1: Block diagram of the prototyped radio system After collecting the information, external hub is turned off, which results in the radio being disabled and reset to its initial state by the power-on-reset (PoR) circuit. The proposed highly 86  integrated bidirectional radio operates in ISM band of 915 MHz for the data link and 2.4 GHz for the power link. Note that these frequencies are within the range that body tissue shows a relatively low attenuation. Separation of power and data links reduces their cross-modulation, while interruption in the power flow due to amplitude modulation is also avoided. Thus, enhanced receiver sensitivity is achieved, which further extends the operating range. In addition, the power and data links can be optimized independently and the bulky energy storage elements such as super-capacitors [52], [55] are not required for this design. 5.2.1 Receiver Architecture Receiver’s architecture comprises of the input matching network, RF amplifier, envelope detector, IF amplifier, input and output mixers, on-chip master clock, and a delay cell (Figure 5.2).  Figure 5.2: Block diagram of the receiver The input RF signal is denoted as A0 cos(2πfRFt), where A0 is amplitude and fRF is the frequency of input signal. The on-chip master clock generates a square wave signal (CLKin) at frequency fclk, which is used to mix with the input RF signal in the input mixer. Assuming the conversion gain of the input mixer is G1 and the gain of the RF amplifier is ARF, then the signal at the output of the RF amplifier is  𝑆𝑅𝐹𝐴 = 𝐴0𝐺1𝐴𝑅𝐹 {𝜋2𝑐𝑜𝑠(2𝜋𝑓𝑅𝐹𝑡) + 𝑐𝑜𝑠[2𝜋(𝑓𝑅𝐹 ± 𝑓𝑐𝑙𝑘)𝑡]}  (5-1) The envelope detector extracts the envelope of the incoming signal by using the squaring function approximation and the signal content around fclk in its output is selected and amplified by 87  the band-pass IF amplifier. The second mixer (G2) mixes the output signal from IF amplifier with clock signal (CLKout), which is generated by the delay cell in accordance with CLKin. Note that the frequency of the clock signal does not change and CLKout is another square wave clock signal. Therefore, the desired term at the output of the receiver is given as   𝑆𝑜𝑢𝑡 = 2𝑘𝜋𝐴𝐼𝐹𝐴02𝐴𝑅𝐹2 𝐺12𝐺2 cos(𝜑′ − 𝜑′′)  (5-2) where AIF is the gain of the IF amplifier, G2 is the conversion gain of the output mixer, the phase mismatch in the signal path and the delay cell is evaluated by cos(φ'–φ''). 5.2.2 Smart Control Module The smart control module (SCM) consists of a clock and data reconfiguration (CDRF) module and an identification recognition (IDR) block (Figure 5.3). CDRF is responsible for reconstruction of the baseband signal and clock from the waveform being delivered by the receiver. Output of the CDRF is connected to IDR, whose function is to perform cyclic redundancy check (CRC) and to make decisions based on the user-defined communication protocol. Specifically, the received data packet is compared with the identification code (IDC) stored in the IDR for the command validity verification. When correct IDC is received, IDR block generates enable signal that switches the radio into interrogation mode upon user’s requirement.  Figure 5.3: Block diagram of the smart control module The data and clock signals received by IDR block are first reconstructed by the CDRF, while the data frame of the coding scheme is simply defined by the user. As mentioned, the need for 88  synchronization circuity increases the total power budget. Thus, asynchronous protocol that encodes the data into pulse-width is proposed to conserve energy and reduce system latency. As described in Figure 5.4, data bit “0” is defined by two consecutive negative to positive pulses ‘0101’, while data bit “1” is signified by three consecutive positive pulses followed by negative pulse ‘1110’. After that, the reconfigured data is sent to IDR for verification against the predefined IDC 20-bit data packet, which includes two frame check sequences (FCS) to prevent false switching due to interference or disturbance signal. To be specific, valid data frame is divided into three parts: the first 8 bits are the prefix FCS, the last 8 bits are the suffix FCS and the middle 4 bits are the payload control command.   Figure 5.4: Encoding scheme diagram  Figure 5.5: Operational flow-chart of the IDR block The operation flowchart of the IDR block is shown in Figure 5.5. The first 8 bits prefix sequence are confirmed once the data packet gets into the IDR register, and then the last 8 bits 89  suffix sequence is checked. Any failure during the CRC would automatically trigger reset process, putting the IDR in its original state and the switch to change the operation mode of the system will not toggle. After the data packet passes CRC, the 4-bit payload evaluation is performed. Once a successful ID is confirmed, the enable signal is activated to enable the data transmitter and the radio system is switched into interrogation mode. Note that the enable is kept high after triggered until the receipt of the PoR signal from RF-to-DC converter. 5.2.3 Transmitter Architecture Typically, RF transmitters use some type of a frequency synthesizer to generate a stable carrier using an external reference crystal oscillator. For our application, however, a frequency synthesizer is not necessary for two reasons: the frequency stability requirement is more relaxed especially in OOK modulation scheme; and, the human body is an excellent temperature stable environment. Thus, both the overall frequency drift and rate of change are lower than many other applications. Therefore, it is beneficial to further simplify the overall transmitter by shifting the communication complexity away from the implant and move it to the external hub.   Figure 5.6: Block diagram of the proof-of-concept data transmitter The simplified block diagram of the ULP transmitter is illustrated in Figure 5.6; it consists of a free-running inductor-capacitor (LC) based LO that is employed to relax the stringent power and size requirements at the implant side. Instead of using an energy intensive PA, an LO buffer is implemented to provide adequate reverse isolation and potentially enhance its drive capability to 90  the load (e.g., an antenna). Meanwhile, the OOK modulated signal is provided by switching on and off the LO buffer according to the output data at the data rate frequency. 5.3 Circuit Implementation   In the following subsections more detailed discussions as well as schematics of main building blocks of the system, including, RF-to-DC converter, crystal-free double mixing receiver, SCM module, and ULP data transmitter, are presented. 5.3.1 RF-to-DC Converter The purpose of the RF-to-DC converter (RDC) is to harvest energy from the incident RF waves by rectifying the EM waves into a stable DC voltage and delivering the stabilized voltage as the power supply of the system.  A differential self-Vth cancellation based 3-stage rectifier [79] is implemented in the RDC as shown in Figure 5.7. A balanced matching network is co-designed with the rectifier with only on-chip capacitors, Cs and Cp, that have compact size and high-quality factor. The gate of the transistors M1-2 are connected through the capacitors C1 to the output terminal of the matching network. As these transistors in the rectifier operate as switches, PMOS and NMOS transistors turns on and off sequentially when the RF voltage at the gate node changes from negative to positive.  The rectifier is designed to provide a 0.5 V DC voltage (Vrec), which is also tracked by the PoR circuit [88]. To be specific, the PoR signal enables the radio system when the desired and sustained value for Vrec is acquired at the output of the rectifier. Conversely, if Vrec drops under a certain threshold level, the PoR disables the radio and reset the system to its original status. Moreover, the PoR circuit helps preventing failures of the analog circuits and malfunction of the digital sub-block that could result from insufficient supply voltage.   91   Figure 5.7: Schematic of the RF-to-DC converter 5.3.2 Crystal-free Double Mixing Receiver 5.3.2.1 RF Front-end Circuit  The RF front-end refers to the circuity operating at RF frequency in the receive signal path. It includes a matching network, the input mixer, a two-stage RF amplifier and the envelope detector as shown in Figure 5.8. The input matching is realized using a fully on-chip LC network: C1 and C2 form a capacitive transformer to obtain passive voltage gain, and with the equivalent capacitance of this capacitive transformer, the inductor Lm creates an LC resonator at the input carrier frequency. Then, a single-ended dual-gate input mixer [60] multiplies the clock signal (CLKin) and the RF signal. The LC load of the input mixer forms another resonator network around RF frequency (fRF) that filters out the unwanted clock feedthrough signal as well as the up-converted flicker noise which are in the vicinity of fclk. The conversion gain (G1) of the input mixer is     𝐺1 =1𝜋𝑔𝑚1𝑅𝑝 = 2𝑔𝑚1𝑓𝑅𝐹𝐿1𝑄𝐿1  (5-3) where gm1 is the transconductance of transistor M1 and Rp is the equivalent resistance of the LC tank that is determined by the inductor value (L1) and the quality factor (QL1). Note that inductors Lm and L1 are spiral structures that are optimized for lower series resistance by connecting top two ultra-thick metal layers in parallel so that a higher Q factor is achieved to enhance the frequency 92  selectivity. In addition, an array of metal wires is used as the patterned ground shield so that the substrate noise is isolated from the inductor and it also minimizes the loss associated with the induced current in the substrate which deteriorates the Q. The design parameters of the inductor Lm and L1 are given in Table 5.1. Table 5.1: Inductor Design Parameters Inductor Lm Inductor L1 Outer Width Spacing Outer Width Spacing 280 µm 5 µm 5 µm 300 µm 5 µm 5 µm Turns Ind (nH) Q (fRF) Turns Ind (nH) Q (fRF) 8 15.1 15.7 8 17.7 16.3   Figure 5.8: Schematic of the receiver front-end circuit A two-stage RF amplifier is employed to provide active voltage gain so that a larger signal is delivered to the envelope detector for better receiver sensitivity. The first stage of the RF amplifier is shown in Figure 5.8. The second stage is the same and for clarity of the schematic is omitted from the figure. The driving transistor M3 is biased in weak-inversion region for higher current efficiency while the width of the cascode transistor M4 is sized one-fourth of the width of M3 to reduce capacitive loading at the output node. In this design, an on-chip active inductor (2.2.3) 93  comprising of transistors M5-7 is implemented as the load to synthesize a large impedance with minimum chip area. The resonance frequency of the active inductor load is determined by Leq and Ceq, and the load is designed to have bandpass response centered around carrier frequency.  It is especially beneficial to forward bias the bulk terminal of the transistors in the RF amplifier. By setting the voltage Vb at VDD/2, the drain depletion region is reduced so that the output conductance is decreased, leading to an increased intrinsic gain (i.e., gm/gds) of the MOS transistor. The envelope detector employs a common-source structure with the transistor M8 operating in weak-inversion region so that the squaring function is realized by the 2nd-order nonlinearity of the transistor. The desired output signal resides at fclk while the linear term at the carrier frequency is suppressed by the low-pass RC load. 5.3.2.2 Analog Baseband and Clock Generator The analog baseband circuit consists of a two-stage band-pass IF amplifier (Figure 5.9) that provides adequate gain for the output signal of the envelope detector across the frequency variation range of fclk. To be specific, the first amplifier converts the single-ended input into differential output. It is implemented by NMOS transistor pair M1 and M2 that operate in weak-inversion region to increase the transconductance efficiency.  The second amplifier is realized by a two-stage fully differential topology. The first stage comprises of the input PMOS differential pair M4 and M5 loaded by NMOS current sources M6 and M7, while the second stage is a push-pull structure so that the output signal swing is maximized to rail to rail. Note that the IF amplifier is operating in an open-loop configuration and therefore the frequency compensation circuitry is not necessary. In addition, a common-mode feedback (CMFB) loop (not shown) is used to stabilize the DC voltage (Vcmfb) and the output common-mode voltage (Vout). 94   Figure 5.9: Circuit configuration of the two-stage IF amplifier The on-chip master clock is realized by a ring oscillator and a pulse shaping circuit, as shown in Figure 5.10. The free-running oscillator employs three-stage inverters with their respective branch currents controlled by associated current sources for better power efficiency and frequency stability. In order to reduce the jitter and to provide 50% duty cycle clock signal (CLKin) for the input mixer, the pulse shaping circuit is composed of a D-flip-flop (and an output buffer) to perform the divid-by-2 clock division. On the other hand, the output clock signal (CLKout±) used by the output mixer is produced by a delay cell, which is realized by basic logic circuits (i.e., NOR and inverter gates). The delay cell creates phase difference between CLKin and CLKout, denoted as φ'', by using a chain of inverters that is designed and optimized to offset the phase delay (φ') introduced in the receiver signal path.    Figure 5.10: Block diagram of the master clock generator and the delay cell The bandpass response of the IF amplifier is designed to cover this frequency range for better power efficiency, while the accumulated DC offsets in the receiver path are eliminated by the AC coupling capacitor Cc (Figure 5.9). The passive output mixer (not shown) is realized by a double-95  balanced topology [60] and is used to down-convert the desired signal at the output of the IF amplifier to baseband. The output of the mixer is sampled and held on capacitor CH (Figure 5.2) with the bandwidth limited to 300 kHz. 5.3.3 Smart Control Module As described in Figure 5.3, the CDRF block consists of a wave shaping circuit, an integrator and a chain of inverters as the clock buffer. The wave-shaping circuit includes a differential amplifier and a Schmitt-trigger inverter. To be specific, the differential amplifier is a low-power stage that provides a high gain over a wide range of common-mode input voltages, and the Schmitt-trigger ensures correct logic transition.   Figure 5.11: Schematic of the wave shaping circuit and integrator The first wave-shaping circuit is used to reshape the demodulated signal at the output of the receiver into standard logic signal. The dynamic reference voltage (Vref) is generated by passive RC circuit with a large time constant that is effectively averaging the envelope signal (Vin). Thereafter, the output full-swing voltage (VRR) passes through the integrator, which is an inverter with a capacitive load as shown in Figure 5.11. The value of the load capacitance (Cint) determines the transition time and integration rate, thus it defines the pulse width of the coding scheme depicted in Figure 5.4. Specifically, transistors M14 and M15 are sized equally to provide fast falling but slow rising edges. Then, Vint passes through another wave-shaping circuit to achieve a rail-to-96  rail digital signal as the reconstructed data for the IDR block, while the signal VRR is used as the clock signal accordingly. The architecture of the IDR block is described in Figure 5.12. The digital circuitry is used to verify the ID code based on the recovered data and clock from CDRF. In order to initialize the data transmitter, the enable signal is produced at the output so that the system can switch into interrogation mode upon successful ID reception. Once the 20-bit data packet is sequentially shifted into the register, CRC detects the prefix FCS, and then the suffix FCS to verify whether the switch command is coming. Upon confirmation of the payload control command, it triggers the enable signal that is kept high until the reset signal is received. Note that the clock stability and synchronization issues are circumvented because the clock and the signal are derived from the same input signal.  Figure 5.12: Block diagram of the IDR module 5.3.4 ULP Data Transmitter A fully integrated ULP data transmitter consists of an NMOS-only free-running LO and a buffer which also incorporates the output matching network (Figure 5.13). Transistors M1 and M2 form a cross-coupled pair that provides negative resistance to the resonator tank formed at the output node of the LO from inductor L2 and parasitic capacitors. The equivalent parallel resistance (Rp) at the resonance frequency (fRF) is calculated as 97   𝑅𝑃 =1𝑔𝑚1,2= 2𝜋𝑓𝑅𝐹 ∙ 𝑄2 ∙ 𝐿2  (5-4) where, L2 is the inductance value and Q2 is the quality factor of the inductor L2. Note that the product of L2 and Q2 should be as high as possible since it translates to a small transconductance, which in turn is proportional to the current draw (power consumption) of the LO. Thus, inductor (L2) is made by combining the top two ultra-thick metal layers in series and forming a spiral structure that has a higher inductance per unit area. It has a Q factor of 5.7 at 915 MHz, leading to a Rp value of 4.3 kΩ.  Figure 5.13: Schematic of the ULP data transmitter By implementing the AC-coupling network formed by resistor R2 and capacitor C2, the LO is DC-isolated from the buffer stage while the current dissipated in LO is reused by the buffer stage. An on-chip decoupling capacitor (CD) is used to stabilize the voltage at node D and it reduces the noise coupled to the oscillator from the power supply. The LO buffer is implemented to drive the output node while providing adequate reverse isolation. Transistors M3 and M4 compose a common-source amplifier with the inductor L3 as load to maximize the output voltage swing. Capacitors C3 and C4 are integrated on-chip and co-designed with the LO buffer for optimal output matching. Moreover, inductor L3 has a symmetrical structure that uses the parallel combination of 98  the top two metal layers together with cross-over connections to create low resistance and a higher Q factor. In addition, the compact symmetrical layout is more area efficient than using two asymmetrical spiral inductors.  The “Enable” signal and the output data modulate the switches (Sw1,2) that turn on/off the LO buffer at the data rate frequency. Without employing a voltage-controlled oscillator, the transmission carrier is affected by process, supply voltage and body temperature variations. The post-layout simulation results show a maximum of 1.1% frequency drift due to process corners (slow/fast), ±10% supply voltage and body temperature variations, resulting in about 10 MHz frequency variations that is still staying within ISM 902-928 MHz band. However, larger frequency range is tolerated by the transmitter if there is a non-coherent receiver with sufficient bandwidth in the external hub. The design parameters of the on-chip inductor L2 and L3 are summarized in Table 5.2.   Table 5.2: Inductor Design Parameters Inductor L2 Inductor L3 Outer Width Spacing Outer Width Spacing 270 µm 5 µm 5 µm 300 µm 8.5 µm 5 µm Turns Ind (nH) Q (fRF) Turns Ind (nH) Q (fRF) 22 130.8  5.7 8 11.7  14.4  5.4 Measurement Results and Discussion  A proof-of-concept radio system is fabricated in a 0.13-µm CMOS process with 8 copper interconnect layers of top-three thick-copper option. The die micrograph is shown in Figure 5.14 with the active chip area including pads of 1.4 mm2 (1.4 mm × 1 mm). The transceiver is fully integrated on a single chip and the die is packaged and soldered on an FR4 printed circuit board (PCB) for measurement purposes. The radio system operates in the ISM 902-928 MHz band for 99  data transmission and 2.4-2.5 GHz for power reception, and the measurements are performed at nominal human body temperature around 36.5 ℃.  Figure 5.14: Chip microphotograph of the radio system  Figure 5.15: Input and output waveform of the RF-to-DC converter The receiver is able to handle data rates ranging from 1 to 100 kb/s that would be sufficient for covering most bio-signals. The transmitter achieves 5 Mb/s data rate, and the sensory data is transferred to the external hub in a burst. To characterize the performance of each building block, two different measurement scenarios are used. First, the radio system is powered by the DC voltage generated by the RDC. The input and output waveform of RDC is captured by a RF digital 100  oscilloscope and is shown in Figure 5.15. Power level of −8 dBm input power at RDC is required to generate the output voltage of 0.5 V. The transition period for the rectified DC voltage is 5.66 μs after reception of the continuous 2.45 GHz RF signal, with the steady-state ripple of about 3.32 mV. The sensitivity of the receiver is characterized for different input powers and data rates provided by an RF signal generator. Note that the demodulation of the OOK-modulated signal requires an output SNR of higher than 12 dB in order to achieve the BER lower than 10-3. For 100 kb/s OOK modulation, the receiver achieves the sensitivity of −59 dBm. If the data rate is reduced to 10 and 1 kb/s, the sensitivity of the receiver improves by 4 and 10 dB at −63 and −69 dBm, respectively, Figure 5.16.    Figure 5.16: Measured receiver output SNR versus input power The data transmitter includes a free-running LO operating in the desired frequency band of 902-928 MHz, its functionality is verified by a RF spectrum analyzer. Figure 5.17(a) shows the output spectrum of the data transmitter over the frequency span of 1.83 GHz without modulation. The transmitting carrier resides at 918.4 MHz and the output power is about −30.6 dBm with 50 Ω load. The PN performance is evaluated by a signal source analyzer as shown in Figure 5.17(b). At 101  the center frequency of 918.4 MHz, the measured PN at 100 kHz and 1 MHz offset is about −96.2 and −113.7 dBc/Hz, respectively.   Figure 5.17: (a) Measured output spectrum and (b) PN of the free-running data transmitter In the second test scenario, the system is supplied by a 0.5 V external precision source to evaluate the current dissipation, and the power breakdown of the proposed radio system is presented in Table 5.3. The total power consumption during monitoring and interrogation modes are 28.8 µW and 49.5 µW, respectively. The up and down-stream data links are operating in TDD manner, so that the peak power consumption of the radio system is 49.5 µW. It is worth mentioning that the average power during the interrogation mode is generally lower than this value and depends on the duty-cycle of the radio system. For instance, if the data transmitter is active at a duty ratio of 0.1% and transmitting in 1 ms out of 1 s period, then the average power consumption would be 49.5 nW. However, since the proposed radio system operates in an event-driven manner, 102  only peak instantaneous power consumption is discussed. In this respect, there is a negligible difference in performance of the transceiver between the two measurement setups. Table 5.3: Power Breakdown of Proposed Radio System Main Block Sub Block Power Dissipation RDC POR & Biasing 0.2 µW Receiver RF Front-end 23.2 µW Analog Baseband 3.6 µW Clock Generator 0.7 µW Total Power 27.5 µW SCM CDR 1.1 µW IDR 6.8 nW Total Power 1.1 µW Transmitter LO & Buffer 48.2 µW  The validation of the functionality of the radio system is performed, and the measured time-domain waveforms are illustrated in Figure 5.18. After the required supply voltage is established, the radio starts its operation in the monitoring mode. In this mode, the receiver and the SCM monitor the channel while the transmitter is off. During this period, the radio starts to receive an RF signal that is modulated by an OOK data at the power level of −50 dBm. In order to verify the function of the SCM, the user-defined data stream is formed by the combination of the non-CRC and CRC sequence with valid ID at the data rate of 100 kb/s. The RF signal is demodulated by the receiver, Figure 5.18(a), then the CRC check is performed in SCM and after the CRC data stream is received the enable signal is generated at the output. Subsequently, the enable signal forces the radio system into interrogation mode as shown in Figure 5.18(b). While in the interrogation mode, the data transmitter is turned on and the receiver is disabled to conserve power, which creates the setup for the interrogating process. The output waveform of the transmitter modulated by an output 103  data stream with 5 Mb/s pseudorandom binary sequence (PRBS) clearly shows these steps in Figure 5.18(c).   Figure 5.18: Measured time-domain waveforms in radio chain: (a) The received demodulated signal in monitoring mode; (b) Enable signal for mode switching; (c) The modulated output of the data transmitter in interrogation mode In order to verify the system’s robustness to the process, supply voltage and ambient temperature variations, the proposed radio is tested in three different die samples with ambient temperature changing between 32 to 42 ℃. The entire system can work correctly even if the supply voltage drops as low as 0.4 V while the uplink transmission carrier varies in the range from 914.8 to 922.1 MHz, which is still in the scope of ISM 902-928 MHz frequency band. Moreover, the proposed radio system is intended for biomedical applications where the long-term stability is an important feature. Therefore, in our experiments, both the receiver and the transmitter are monitored separately over a week time span while continuously operating at nominal human body temperature of 36.5 ℃ and three different die samples are used for this experiment. During this 104  evaluation period, no disturbances, interruptions or faultiness happened at the output, indicating that the proposed radio operates in a stable fashion and has the ability for a long-term operation.  Figure 5.19: Experimental setup for the RF wireless data link The wireless power and data link as well as the functionality of the radio system are further verified in the experimental setup as shown in Figure 5.19. For test purposes, the radio under test (RUT) is surrounded by a 3.5 cm thick layer of pork meat that has skin and fat tissue. The RUT prototype is connected to discrete whip antenna to achieve the up and down link wireless data transmission at 915 MHz and receive power at 2.45 GHz. In the external hub, the RF signal generator is used to deliver an OOK modulated RF signal to the RUT wirelessly at the power level of 30 dBm.  The distance between the RUT and the RF signal generator is 2.8 m, and a successful wireless data link is created with a BER of lower than 10−3 with the data rate of 100 kb/s. After the RUT enters interrogation mode, the external hub receives an RF signal at 918.2 MHz with the power level of −93 dBm, implying that a sensitive external receiver is required. On the other hand, the remote power link operates successfully even when the external power source is located at 1.2 m away from the RUT. 105  The overall performance of the proposed radio system along with the comparison with previously published works are summarized in Table 5.4. All the data presented in the table are measurement results and only sub-1-mW transceivers with active data transmission are included in the table. Table 5.4: Performance Summary and Comparison with Prior State-of-the-arts References [89] [33] [90] [49] [55] [41] This Work  CMOS Technology 90 nm 90 nm 65 nm 130 nm 180 nm 40 nm 130 nm Chip Area 2 mm2 0.55 mm2 2 mm2 13.5 mm2 2.025 mm2 0.8 mm2 1.4 mm2 Power Source Frequency Power Supply Power Supply 904.5 MHz Solar, TEG 915 MHz 1.86 GHz 2.45 GHz Sensitivity −20 dBm −10 dBm 3 dBm −8 dBm Operation Frequency RX 403 MHz 400 MHz 904.5 MHz 0.4-2.4 GHz 915 MHz 1.86 GHz 902-928 MHz TX 403 MHz 400 MHz 402 MHz 4 GHz 457.5 MHz 1.74 GHz 902-928 MHz Modulation Scheme RX OOK OOK N/A OOK OOK ASK OOK TX MSK OOK OOK OOK OOK OOK OOK Data Rate RX 120 kb/s 1 Mb/s N/A 7.8125 kb/s 1 Mb/s 2.5 Mb/s 1 to 100 kb/s TX 120 kb/s 1 Mb/s 250 kbps 187.5 kb/s 1 Mb/s 58 Mb/s 5 Mb/s Peak Power consumption RX 350 µW 180 µW 13 µW 6.45* µW 141 µW 7.2 µW 28.4 µW TX 400 µW 160 µW 215 µW 93 µW 48.2 µW Datalink Sensitivity −93# dBm −65 dBm −20 dBm N/A −10 dBm −25 dBm −69- −59 dBm POUT N/A −17 dBm −18 dBm −28.9 dBm −22 dBm −18.5 dBm −30.6 dBm External Components No XTAL No XTAL Supercapacitor Duplexer No Calibration Yes No Yes No No No No *Average power after heavy duty cycling   # Sensitivity is quoted for BER of 10−2 5.5 Summary A ULP event-driven radio system has been presented in this chapter, which includes improvements at both circuit and architecture levels. Specifically, the double mixing receiver improves the input sensitivity, and it can tolerate a range of frequency instability of the clock generator while maintaining circuit simplicity. Furthermore, it is fully integrated and does not require any external components and calibration overhead. The data transmitter utilizes a free-funning LO to achieve 106  active uplink transmission that overcomes the self-jamming issue and enables longer transmitting range. In addition, to conserve power while providing drive ability to versatile load impedance at the output node, the current reuse technique is used between LO and buffer stage. Moreover, due to the adopted SCM that does not need an external quartz oscillator or a passive circulator (usually needed to perform monitoring and interrogation operations in the same frequency band), a low-cost and highly integrated solution is achieved. The system also benefits from having separate power and data links so each link can be optimized separately to accommodate different application scenarios. With demonstrated low-power dissipation and small form factor, the proposed radio system is suitable for applications where energy resources and device footprint are constrained such as IMD and IoE. 107  Chapter 6: Conclusions and Future Work 6.1 Conclusions  Wireless radio systems have been studied extensively in recent years, however, meeting the stringent power requirements and form factor in some applications including biomedical implants is still an ongoing research activity.  In the down-stream data link, the receivers used in telemetry system have difficulties in realizing high-level integration while keeping reasonable sensitivity without increasing the power consumption. In addition, most of existing bidirectional communication mechanisms have difficulties on coexisting with the power link. Traditional solutions lead to higher power and cost and have troubles to meet the desired distance of operating due to high in-vivo loss. The focus of this thesis is motivated by the interests to explore the receiver as well as the entire radio system with low-power consumption and higher levels of integration to address the above-mentioned design challenges. The system-on-chip integration radios are intended for event-driven wireless nodes and are potentially suitable for mass application in various markets.  1)  It is critical to further investigate, at both system and circuit levels, configurations that are suitable for miniaturized biomedical implants. We propose architectures that are amenable to higher integration and lower power consumption. The thesis starts with the trends and regulations of transcutaneous data and power transmission, and then the implementation platforms and the literature review in receiver structure and radio architecture. In the first two chapters, the link budget analysis determines the design specifications of the wireless transceiver in order to provide a better trade-off between energy efficiency and input sensitivity. In addition, several low-power design techniques are explored for sub-building blocks such as envelope detector and RF amplifiers.  108  2)  We present our custom wireless RF switch designed in 130nm CMOS that utilizes a CDR system to extract control signals from the user in ISM bands and evaluated with our custom digital controller. The correct operation of the proposed switch architecture is verified by detailed simulations. The RF switch circuit operates on 164 μW power and can control up to 16 enable circuits within an implantable telemetry system. 3) A prototype of crystal-less event-driven receiver is presented. In order to facilitate operation using harvested energy, the receiver operates from a low supply voltage of 0.5 V. The system uses an envelope detector with programmable scaling factor to provide a better trade-off between sensitivity and power consumption. A proof-of-concept receiver with two gain settings is designed and fabricated in a 0.13-μm CMOS process. The system does not require any external components, occupies a chip area of 0.208 mm2, and consumes 32 μW while achieving sensitivity of −50 and −53 dBm for two different scaling factors.  4)  We present a low-power event-driven receiver intended for biomedical implants. The fully integrated system can operate by power harvesting from electromagnetic fields using an RF-to-DC converter or through a 0.5 V voltage supply such as a rechargeable battery. Without any external component and calibration overhead, the proposed double-mixing receiver structure is operating at the frequency of 915 MHz ISM band and is robust to PVT variations. The proof-of-concept receiver is designed and implemented in a 0.13-µm CMOS technology. The system occupies a silicon area of 0.75 mm2 and consumes only 9.1 µW power while achieving a sensitivity of –48 and –39 dBm at the data rate of 1 and 100 kb/s, respectively. 5)  An event driven ULP radio is developed for miniaturized biomedical implants. Its powerlink employs an RF-to-DC converter to scavenge radio frequency energy at 2.4 GHz ISM band. The bidirectional time-division datalink occupies 915 MHz ISM band and its operation is 109  orchestrated by a smart control module, where the cyclic redundancy check is conducted to switch the system between monitoring and interrogation modes. The proof-of-concept radio is fabricated in 0.13-µm CMOS process with the chip area of 1.4 mm2. Its nominal functionality is achieved without any external component nor the need for calibration, while at the same time it can tolerate PVT variations, leading to a low-cost and fully integrated wireless solution. During the monitoring mode, the downlink data reception and demodulation are realized by a double-mixing receiver that consumes 29.4 µW while achieving a sensitivity of −69 and −59 dBm at the data rate of 1 and 100 kb/s, respectively. Dissipating peak power of 48.2 µW in the interrogating mode, the data transmitter delivers an output power of −30.6 dBm with the data rate up to 5 Mb/s.    In summary, the receiver and radio system developed in this thesis have a small form factor with an ultra-low power consumption and offer suitable and robust solutions for biomedical implants. Although they were intended for applications such as smart stents that require miniaturized solutions, however, the proposed techniques are general, and can be used for any other power-efficient and size-constrained telemonitoring applications such as wireless sensor networks, IoT and IoE. 6.2 Future Work Based on the contributions presented in this thesis, several related areas of work can be exploited in future.  6.2.1 Design Technique Improvements The receiver and transmitter frontends, as well as the analog/digital baseband and matching networks presented in this thesis have already been integrated together on a single chip with a low hardware cost and a low power consumption. Nevertheless, some circuit-level design aspects in both receiver and transmitter can still be improved and they are summarized as follows: 110  • The power consumption of the transceiver can be further reduced to support more energy-constrained applications. This can be realized if the system is fabricated in a more advanced CMOS technology. However, careful design is required by the designers for not scarifying the system performance.  • Further improvement on the RF-to-DC converter is necessary in order to optimize the power conversion efficiency. The on-chip rectifier redesign is required especially for low input power densities and when the voltage is not high enough to bias the synchronous rectifier properly.  • The autonomous transceiver in the telemetry system can incorporate other functionalities such as sensing, signal processing, artificial intelligence or machine learning for the next generation of IMDs.  6.2.2 Antenna Considerations   Antenna design and optimization are not within the scope of this research, and it is worth mentioning that the RF front-end circuitry developed in our work is designed based on the assumption that the antenna has a 50 Ω impedance.  In many practical cases, such as smart stent, the impedance of the antenna may be different. In order to address this issue, one can either explore a customized stent-antenna fabrication, or an (adaptive) input matching network should be included in the design. Moreover, the through-body wireless power transfer and data communication are highly relied on the properties of the antenna, which is different from the antenna used in a data-driven radio operating in the free air. Designing a high-efficiency antenna in the human body is an interesting research area and the major considerations are concluded as follows: 111  • The antenna used in the human body faces the media of tissues exhibiting quite different electrical characteristics that are also varying with frequencies.  • Antenna gain and its radiation efficiency is critical and determines the minimum incident RF power levels.  • It is difficult to characterize the antenna inside of human body. More experiments are required to find the actual in-vivo loss of the RF signal in different frequency bands by using a specific antenna under working conditions close to the real situation.  • An integrated antenna gives more freedom in the design to accommodate for the small area inside of human body. In this thesis, the interface impedance is assumed to be 50 Ω, which is a universal value for off-the-shelf antennas and measurement equipment. If antennas can be integrated with the design, the interface is not limited to this value anymore so that there may be other optimum matching impedances to improve the overall system efficiency. 6.2.3 In-Vitro and In-Vivo Studies In this work, we have not studied the biocompatibility requirements of the IMDs which typically require coatings and proper packaging of the IMD. Furthermore, the effects of surrounding tissues and fluids such as blood on the performance of the system needs to be considered. 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