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Ring resonator based silicon photonic transmitter and receiver

University of British Columbia

Ring resonators in silicon photonics platform hold great potential in various applications due to their compact size and wavelength selectivity, enabling densely integrated optical systems. This thesis focuses particularly on the application of ring resonators in silicon photonic transmitters and receivers. In transmitters, all-pass ring resonators with PN junctions can be driven in depletion mode to provide high-speed binary modulated signals. Pulse-amplitude-modulation-4 (PAM4) schemes can be adopted to achieve higher bit rates by providing four levels of amplitude instead of two. Instead of relying on a power-hungry digital-to-analog converter (DAC) in the driver, the four optical levels can be realized by using two separate non-return-to-zero (NRZ) drivers on either a single ring resonator with segmented PN junctions or a dual cascaded ring resonator. In this thesis, the two DAC-less PAM4 modulation methods in ring resonators are compared using frequency and time domain analytic equations, with a target bit rate of 25Gb/s. Under the same constraints in terms of ring resonator dimensions and electrical signal voltages, the single ring resonator with segmented PN junctions is found to be the superior candidate, due to the smaller number of stabilization circuits required while achieving a larger modulation amplitude. In receivers, add-drop ring resonators can be used as wavelength division multiplexing (WDM) channel filters, but they suffer from high polarization dependence, which motivates the need for a polarization management solution on chip. In this thesis, a 4-channel polarization-insensitive WDM receiver is designed by forming a waveguide loop between the two output ports of a polarization-splitter-rotator. The input signals in the quasi-transverse-electric and the quasi-transverse-magnetic polarization states can be demultiplexed without active polarization tuning or independent processing of the two polarization states. Large signal measurements at 10 Gb/s indicate that the design can tolerate a signal delay of up to 30% of the unit interval (UI) between the two polarization states, which implies that compensating for manufacturing variability with optical delay lines on chip is not necessary for a robust operation. The inter-channel crosstalk is found negligible down to 50 GHz spacing, proving its compatibility with dense WDM systems.

Text

2020-01-31

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/68273

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/