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CMOS circuits for RF energy harvesting applications Dehghani, Soroush 2018

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CMOS Circuits forRF Energy Harvesting ApplicationsbySoroush DehghaniA THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHYinThe College of Graduate Studies(Electrical Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Okanagan)January 2018© Soroush Dehghani 2018The following individuals certify that they have read, and recommend to the College ofGraduate Studies for acceptance, a thesis/dissertation entitled:CMOS Circuits for RF Energy Harvesting Applicationssubmitted by Soroush Dehghaniin partial fulfillment of the requirements of the degree of, Doctor of Philosophy.Dr. Thomas JohnsonThesis SupervisorDr. Wilson EberleSupervisory Committee MemberDr. Lïoc MarkleySupervisory Committee MemberDr. Solomon TesfamariamUniversity ExaminerDr. José Angel GarcíaExternal Examiner from the University of CantabriaiiAbstractThe explosive growth in Wireless Sensor Networks, ranging from the Internet of Things toembedded sensors for smart infrastructures and biomedical implants, continues to motivatethe design and development of low-power energy harvesting systems that can either remotelycharge a battery in the sensor unit or completely self-power the sensor from harvested energy.This thesis focuses on designing new benchmarks for monolithic RF rectifiers imple-mented in CMOS technology. A design procedure based on the theory of time-reversalduality is applied to transform power amplifier circuits into self-synchronous rectifier cir-cuits. The methodology is distinctly different from other CMOS RF rectifier designs whichuse voltage-multiplier techniques. An advantage of transforming amplifier into rectifier cir-cuits is that output matching in the amplifier is transformed to input matching in the rectifier.All the rectifier circuits described in this work include single-ended RF input ports matchedto 50 Ω. Also, the circuits are self-biased and completely powered from the RF signal.Terminating rectifiers with an optimum load is important to maximize the RF to dc powerconversion efficiency. The optimum load resistance can vary as a function of input power.Therefore, an adjustable load that tracks changes in RF power is proposed to maximizeefficiency. As a way of implementing an adjustable load circuit, a discontinuous mode dc todc converter that is controlled by an input loop to regulate the load impedance of the rectifieris presented. The analysis, design and experimental results of the adjustable load circuit aredescribed and the performance is verified with 10 W GaN Class-F RF rectifier.In the final part of this thesis, a bidirectional and reconfigurable class-DE circuit isproposed to support the implementation of embedded sensor nodes that are self-powered andiiiAbstractusing a time-division duplexing architecture. The circuit reconfigures the same RF front-endcircuit into either a high-efficiency rectifier or a highly efficient power oscillator that canbe modulated to transmit sensor data. The two modes can be time multiplexed to switchbetween RF energy harvesting and transmission. The design was implemented in 65 nmCMOS technology and experimental results for both modes of operation are presented.ivPrefaceThis thesis is original, independent work by the author, Soroush Dehghani.The circuit designs and experimental setups described in Chapter 2 were designed andbuilt primarily bymyself. A licensed copy ofCadence software, provided through a universitypartnership between CMC Microsystems and UBC, was used for simulating and laying outall the CMOS circuits. Three different CMOS chips were fabricated by IBM using 0.13 µmtechnology and allocations for fabrication services were obtained through a competitive CMCpeer-review university program. The circuits described in Chapter 2 have been previouslypublished in IEEE Transactions on Microwave Theory and Techniques in May 2016 and intwo IEEE International Microwave Symposium conferences in 2015 and 2016. The researchwas my own work and I wrote the manuscripts under the supervision and editorial assistanceof Dr. Thomas Johnson.The work described in Chapter 3 was carried out in conjunction with Dr. SadeghAbbasian. A load tracking circuit was used as a back-end circuit for Dr. Abbasian’s 10 WGaN HEMT class-F synchronous rectifier. The circuits and experimental setups in Chapter 3were designed and built primarily by myself. Two versions of this chapter were published inIEEE Transactions on Microwave Theory and Techniques in Feb. 2016 and IEEE WirelessPower Transfer Conference at Boulder, CO, USA. I was responsible for all major areas ofconcept formation and analysis, as well as the majority of the manuscript composition underthe supervision and editorial assistance of Dr. Thomas Johnson.InChapter 4, a bidirectional and reconfigurable circuit is described. I designed the circuitsand conductedmost of the experimental work to characterize the circuits. Amanuscript usingvPrefacethe work in Chapter 4 is in preparation and expected to be submitted for publication. I wasresponsible for conducting all parts of the research and preparing the manuscript. A licensedcopy of Cadence and ADS Keysight softwares were used for design and layout simulationsand the chip was fabricated through CMC using a TSMC 65 nm CMOS technology process.The entire manuscript was prepared using the LATEX package and Computer Concretefont family. For schematics and conceptual figures, the extensible, free drawing editor “Ipe"software was used. Simulation and experimental results were plotted using “OriginPro"software.viTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviiiGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Preliminary Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Wireless Energy Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Challenges in Far-Field Wireless Power Systems . . . . . . . . . . . . . . 51.4 RF Energy Harvesting Systems . . . . . . . . . . . . . . . . . . . . . . . 71.4.1 Integration, Size and Cost . . . . . . . . . . . . . . . . . . . . . . 81.4.2 Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . 81.4.3 Antenna Requirements . . . . . . . . . . . . . . . . . . . . . . . . 91.4.4 Link Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5 Review of State-of-the-Art Energy Harvesting Circuits . . . . . . . . . . . 12viiTable of Contents1.5.1 RF Rectifier Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 131.5.2 DC Load Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 161.5.3 Reconfigurable Architectures for RF Energy Harvesting . . . . . . 161.6 Summary of Research Objectives and Contributions . . . . . . . . . . . . 202 Synchronous Rectifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.2 The Principle of Time-Reversal Duality . . . . . . . . . . . . . . . . . . . 232.2.1 Time-Reversal Duality Relations . . . . . . . . . . . . . . . . . . 242.2.2 Power Flow in time reversed Networks . . . . . . . . . . . . . . . 252.2.3 Amplifier and Rectifier Circuit Duals . . . . . . . . . . . . . . . . 252.2.4 Effect of Loss in TRD Networks . . . . . . . . . . . . . . . . . . . 272.2.5 Phase Differences in Amplifier and Rectifier Circuit Duals . . . . . 282.3 Class-E Synchronous Rectifier . . . . . . . . . . . . . . . . . . . . . . . . 292.3.1 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . 322.3.2 Ideal Class-E Amplifier Equations . . . . . . . . . . . . . . . . . . 332.3.3 Resistive Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.3.4 Class-E Amplifier Reference Design . . . . . . . . . . . . . . . . 402.3.5 Class-E Synchronous Rectifier Design . . . . . . . . . . . . . . . 442.3.6 Overlap Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452.3.7 Gate Bias and Sinusoidal Drive Signals . . . . . . . . . . . . . . . 462.3.8 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 492.4 Class-D Synchronous Rectifier . . . . . . . . . . . . . . . . . . . . . . . . 532.4.1 Ideal Class-D Amplifier Design . . . . . . . . . . . . . . . . . . . 532.4.2 Feedback Network Design Methodology . . . . . . . . . . . . . . 542.4.3 Simulation and Experimental Results . . . . . . . . . . . . . . . . 552.5 Transconductance Mode Rectifier . . . . . . . . . . . . . . . . . . . . . . 582.5.1 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . 59viiiTable of Contents2.5.2 Layout Constrains . . . . . . . . . . . . . . . . . . . . . . . . . . 602.5.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 622.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 Adjustable Load with Tracking Loop . . . . . . . . . . . . . . . . . . . . . . 663.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663.2 Design and Analysis of the Adjustable Load . . . . . . . . . . . . . . . . . 683.2.1 Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 703.2.2 Inductor Size for DCM Mode Operation . . . . . . . . . . . . . . 723.3 Analog Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743.3.1 Linear Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . 743.3.2 Control Loop with Charge Pump . . . . . . . . . . . . . . . . . . 763.3.3 Circuit Implementation of the Analog Control Loop . . . . . . . . 793.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 Bidirectional and Reconfigurable Circuit . . . . . . . . . . . . . . . . . . . . 864.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864.2 Circuit Concepts and Requirements . . . . . . . . . . . . . . . . . . . . . 864.3 Class-DE Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 894.3.1 General Class-DE Amplifier Relations . . . . . . . . . . . . . . . 894.3.2 Ideal Class-DE Amplifier Design Equations . . . . . . . . . . . . 914.4 Class-DE Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 984.4.1 Barkhausen Criteria . . . . . . . . . . . . . . . . . . . . . . . . . 984.4.2 Synthesis of the Feedback Network . . . . . . . . . . . . . . . . . 1004.5 Class-DE Synchronous Rectifier Design . . . . . . . . . . . . . . . . . . . 1054.6 Nonlinear Optimization of The Oscillator Performance . . . . . . . . . . . 1104.6.1 Nonlinear Optimization for Steady State Conditions . . . . . . . . 111ixTable of Contents4.6.2 Start-Up Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 1144.6.3 The Effect of Gate Bias . . . . . . . . . . . . . . . . . . . . . . . 1164.7 Bias Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204.8 Feedback Modifications for Synchronous Rectifier Mode . . . . . . . . . . 1244.9 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . 1284.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1335 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . 1355.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385.2.1 Rectifier Topologies and Devices . . . . . . . . . . . . . . . . . . 1385.2.2 Antenna Considerations . . . . . . . . . . . . . . . . . . . . . . . 1395.2.3 Integration With Power Management and Energy Storage . . . . . 139Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141xList of Tables1.1 Comparison of energy harvesting sources . . . . . . . . . . . . . . . . . . . . 21.2 Summary of RF survey measurements for London, UK. . . . . . . . . . . . . . 61.3 Time to fully charge different devices using RF power sources. . . . . . . . . . . 61.4 Path loss for different ISM band for different distances. . . . . . . . . . . . . . . 71.5 Performance comparison of recently reported RF rectifier circuits . . . . . . . . . 152.1 Practical circuits derived from time-reversal duality theory. . . . . . . . . . . . . 242.2 Simulation results for different class-E amplifier circuits . . . . . . . . . . . . . 422.3 Summary of CMOS synchronous rectifier designs. . . . . . . . . . . . . . . . . 654.1 Comparison of analytic and optimized (simulation) component values for the class-DE amplifier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984.2 Terminal voltages and currents required at the class-DE amplifier reference planes. 1034.3 Feedback network element values. . . . . . . . . . . . . . . . . . . . . . . 103xiList of Figures1.1 Wireless power transfer: (a) near-field and (b) far-field systems. . . . . . . . . . . 41.2 Sensor node using FDD architecture with RF energy harvesting. . . . . . . . . . 121.3 Performance comparison of reported RF rectifier circuits: (a) integrated rectifiercircuits and (b) discrete rectifier circuits. . . . . . . . . . . . . . . . . . . . . . 141.4 Sensor node using TDD architecture with a bidirectional front-end reconfigurablefor RF energy harvesting and transmission modes. . . . . . . . . . . . . . . . . 172.1 Block diagrams of (a) a power amplifier, (b) synchronous rectifier dual. . . . . . . 262.2 Schematics of: (a) class-E power amplifier circuit and (b) class-E synchronousrectifier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.3 Waveforms for the class-E amplifier circuit in Fig. 2.2(a) (top row) and the class-Erectifier dual (bottom row). The gate drive signal has rise and fall times equal toT/10 for both the class-E amplifier and class-E rectifier. . . . . . . . . . . . . . 312.4 Class-E amplifier with dissipative losses in the switch and the inductors. . . . . . 382.5 Impedance of the CMOS class-E amplifier load network: ZA( f ). . . . . . . . . . 442.6 Dynamic I-V curve for the class-E rectifier. The gate drive is a square wave signalwith 10% rise and fall times. . . . . . . . . . . . . . . . . . . . . . . . . . . 462.7 Dynamic I-V curves for the class-E rectifier for different gate drive signals anddifferent feedback phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482.8 Microphotograph of the class-E synchronous rectifier. . . . . . . . . . . . . . . 492.9 S11 of the class-E synchronous rectifier for three different source powers. . . . . . 50xiiList of Figures2.10 Measured power efficiency as a function of frequency of the class-E synchronousrectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512.11 Power efficiency and output voltage as a function of: (a) load resistance of the class-E synchronous rectifier for an input power of 10 dBm, (b) available input power inthe class-E synchronous rectifier cross a 250 Ω load . . . . . . . . . . . . . . . 522.12 Class-D amplifier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532.13 Class-D synchronous rectifier circuit. . . . . . . . . . . . . . . . . . . . . . . 552.14 Microphotograph of the class-D synchronous rectifier. . . . . . . . . . . . . . . 562.15 Measured power efficiency as a function of frequency of the class-D synchronousrectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572.16 Power efficiency and output voltage as a function of load resistance of the class-Dsynchronous rectifier.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572.17 Measured power efficiency as a function of available input power of the class-Dsynchronous rectifier.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582.18 Rectifier circuits: (a) a low power circuit consisting of a shunt configuration of azero-voltage threshold device M1 and a positive threshold voltage device M2; (b) ahigh power rectifier circuit operating in class-C. . . . . . . . . . . . . . . . . . 602.19 Relative amplitude of frequency components in the drain voltage signal for lowpower rectifier at a power of 1 dBm and high power rectifier at a power of 10 dBm 612.20 Microphotograph of the transconductance mode synchronous CMOS rectifier circuits. 622.21 Power efficiency versus input power for the CMOS rectifiers of the transconductancemode synchronous rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 632.22 Efficiency characteristics of the high power CMOS rectifier as a function of loadresistance of the transconductance mode synchronous rectifier. . . . . . . . . . . 643.1 RF rectifier with a power management circuit. . . . . . . . . . . . . . . . . . . 673.2 Schematic of the boost converter. . . . . . . . . . . . . . . . . . . . . . . . . 683.3 The boost converter when the switch is closed (on state). . . . . . . . . . . . . . 69xiiiList of Figures3.4 The boost converter when the switch is open (off state). . . . . . . . . . . . . . 693.5 DCM boost converter current waveform iL (t). . . . . . . . . . . . . . . . . . . 703.6 Analog control loop for the DCM converter. . . . . . . . . . . . . . . . . . . . 753.7 Adaptation method employed in the analog controller. . . . . . . . . . . . . . . 773.8 PWM input voltage at steady state condition. . . . . . . . . . . . . . . . . . . . 783.9 A class-F synchronous rectifier with a tracking DCM load. . . . . . . . . . . . . 803.10 Input resistance of the DCM boost converter versus duty cycle. . . . . . . . . . . 813.11 Measured power efficiency of the DCM converter. . . . . . . . . . . . . . . . . 823.12 Class-F synchronous rectifier and adjustable load with tracking loop test bench. . . 833.13 The power efficiency of the rectifier versus RF input power for a tracking load anda fixed load. The response for the optimum dc load is also shown. . . . . . . . . 833.14 Close-loop tracking error as a function of RF input power. The power efficiencyerror for a fixed load resistance of 50 Ω is also shown for comparison. . . . . . . 844.1 Sensor node using TDD with a bidirectional front-end reconfigurable for RF energyharvesting and transmission modes. . . . . . . . . . . . . . . . . . . . . . . . 874.2 Reconfigurable power oscillator and synchronous rectifier with reversible power flow. 884.3 Class-DE power amplifier circuit with intrinsic switches’ capacitors. . . . . . . . 904.4 Class-DE amplifier circuit with single shunt capacitor. . . . . . . . . . . . . . . 914.5 Waveforms for the class-DE amplifier circuit in Fig. 2 (top row): (a) drain voltage,output voltage and gate voltages for the switches M1 and M2, (b) drain currentsthrough the switches M1 and M2 and current through the shunt capacitor C, (c)dynamic I-V curve for the switches. Waveforms for the class-DE rectifier dual(bottom row): (d) drain voltage, output voltage and gate voltages for the switchesM1 and M2, (e) drain current through the switches M1 and M2 and current throughthe shunt capacitor C, (f) dynamic I-V curve for the switch. The non-overlap gatedrive signals have rise and fall times equal to T/20 and the duty cycle of 25% forboth the class-DE amplifier and class-DE rectifier. . . . . . . . . . . . . . . . . 97xivList of Figures4.6 Positive feedback system for implementing an oscillator. . . . . . . . . . . . . . 994.7 Schematic of class-DE amplifier with a sinusoidal drive. The input-frequency is setto the oscillation frequency and a transmission line (TL) is used to create a phasedelay for synchronizing the gate drive for M1 and M2. Dashed lines represent thereference planes for the feedback loop synthesis. . . . . . . . . . . . . . . . . . 1004.8 The class-DE oscillator circuit which adds a feedback loop F (s) to the class-DEamplifier circuit in Fig. 4.7. The input and output reference planes for the feedbackloop are shown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014.9 Parallel-to-series conversion to implement outputmatch including bondwire inductance1044.10 The complete schematic of the class-DE oscillator. The feedback network consistsof capacitorsCT1 andCT2, an inductor LT3, a bondwire inductor Lw and a 50Ω load.The feedback loop also includes a fictitious current source and an ideal bandpassfilter shown in the dashed box. The fictitious components are added in a harmonicbalance circuit simulation to evaluate nonlinear large-signal oscillator responses. . 1054.11 Class-DE synchronous rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . 1064.12 The complete schematic of the class-DE oscillator including the large-signal simu-lation source in the oscillator feedback loop . . . . . . . . . . . . . . . . . . . 1124.13 Contour plots of the: (a) simulated dc to RF power efficiency, (b) output power and(c) oscillation frequency. The solutions satisfy the condition that ZLS = 0. . . . . 1134.14 Contour plots showing the sensitivity of the loop gain and frequency for differentvalues ofCT1 andCT2. (a) The loop gain magnitude corresponding to the zero phaseloop gain condition and (b) the frequency corresponding to the zero phase loop gaincondition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164.15 Complete schematic of the CMOS class-DE power oscillator. . . . . . . . . . . . 117xvList of Figures4.16 Simulated class-DE oscillator characteristics as a function of bias voltages for theNMOS and PMOS transistors. Responses are shown for different supply voltage.(a) dc to RF power efficiency, (b) output power and (c) oscillation frequency. Thesolutions satisfy the condition that ZLS = 0. . . . . . . . . . . . . . . . . . . . 1184.17 Contour plots to show how the class-DE open loop gain changes a function of NMOSand PMOS bias voltages. The plots are shown for VDD = 2 V, CT1= 290 fF andCT2=1.2 pF. (a) The simulated loop-gain magnitude where the loop phase is zeroand (b) the corresponding oscillation frequency for the zero phase condition. . . . 1194.18 A cascode current mirror for generating bias voltages. . . . . . . . . . . . . . . 1204.19 Modified bias circuits for (a) the PMOS device and (b) for the NMOS device. . . . 1214.20 NMOS and PMOS bias voltages vs. supply voltage. . . . . . . . . . . . . . . . 1244.21 Complete schematic of class-DE synchronous rectifier withNMOS and PMOS devices.1254.22 Circuit to change the loop phase for the oscillator and rectifier. When S1 is off, thephase shift network consists of only the inductor L1 for the rectifier mode. WhenS1 is on, the phase shift network consists of a parallel resonator (L1 and C2). Thecapacitor C2 is a dc blocking capacitor. . . . . . . . . . . . . . . . . . . . . . 1264.23 Reconfigurable power oscillator and synchronous rectifier circuit. The circuit isreconfigured with a mode control signal: “O" for oscillator and “R" for rectifier. . . 1274.24 Test bench and die micrograph for the class-DE bidirectional power oscillator andsynchronous rectifier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 1284.25 DC to RF power conversion efficiency of class-DE power oscillator mode. Thesimulation and measurement results correspond to the dash-dot red line and the bluetrace, respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294.26 Class-DE power oscillator mode: (a) operating frequency of class-DE power oscil-lator versus supply voltage, (b) oscillator phase noise. . . . . . . . . . . . . . . 130xviList of Figures4.27 Class-DE synchronous rectifier RF to dc power conversion efficiency as a functionof RF input power. The simulation and measurement results correspond to thedash-dot red line and the blue trace, respectively. . . . . . . . . . . . . . . . . . 1314.28 Class-DE synchronous rectifier mode: (a) RF to dc power conversion efficiency asa function of dc load, and (b) Input match as a function of frequency and RF inputpower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132xviiAcknowledgementsAn education is never a one man endeavor. This thesis, as with everything I have achievedin my life, would not have been possible without so many people that have lent me their timeand help in support of my educational career.My first debt of gratitude is to my supervisor Prof. Thomas Johnson for his ongoingsupport, generous encouragement, expert guidance and sound instruction. He has been morethan an academic supervisor. I have been lucky to have him as my mentor throughout mystudy and research. This thesis would not have been possible without his kindness andpersistent help. I count myself incredibly fortunate.My deep gratitude also goes to Prof. Shahriar Mirabbasi for sharing their lab equipment,and for being generous with his time and knowledge and encouragement during my research.I also thank Prof. Wilson Eberle and Prof. Loïc Markley for their comments on sectionsof this thesis. I would like to appreciate Prof. José Angel García from the Universityof Cantabria, Prof. Solomon Tesfamariam and Prof. Sudip Shekhar as members of myexamining Committee.I owe a great debt tomy friends for their encouragement and help. I would like to thankmycolleagues and friends at the System-on-a-Chip (SoC) Research Laboratory and MicrowaveTechnology Laboratory (MTL) for the technical discussions, the friendly environment theycreated for me and all the fun memories we had together.My parents, and my brother, Soheil, have provided tremendous support despite beingthousands of kilometers away. Thanks for your love and believing in me. Mom and dad, Ihope I will make you proud one day. I wish to express my sincere gratitude to them for theirxviiiAcknowledgementsimpressive daily 10 minute talks and my mother and father who is the source of all goodness.Soheil, good luck in medical school and I know that you will pursue your interests with allthe heart that you can give.My elders, especially my grandmother and grandfather have always been there for saga-cious advice and stories. My aunts and uncles and all of my cousins have always kept myspirits high and I thank them for that.To my passed away grandmother and grandfather: I am sorry that you had to leave theworld before you could see all your grandchildren graduate from college. Those years that Ispent living with you were some of the most influential times of my life. I learned honestyand compassion from you and I hope that as you watch on our family from Heaven, you areproud and content. We all miss you dearly.Most of all, I would like to thank God, for without His blessing, I would not be where Iam today. I may have strayed many times in the past but I have faith that You will lead me inthe right direction. "Who responds to the anguished soul when it calls to Him, and relievesits suffering? And who made you trustees on the earth? Is there any other god along withGod? How little it is that you reflect!"xixAcknowledgementsTranslationAdapted from: https://www.hafizonlove.com/divan/04/196.htmThose who turn lead into goldWill they ever our sight behold?I hide my ills from false physiciansMay my cure come from the invisible fold.When beloved reveals a glimpseMany tales by many are told.Salvation is not in piety,The deed for its own sake should unfold.Hafiz, sustained union cannot be cajoled;Kings in the marketplace rarely strolled.Hafiz:Ghazal 196xxGlossaryCCM Continuous Conduction Mode.CMOS Complementary Metal Oxide Semiconductor.DCM Discontinuous Current Mode.EH Energy Harvesting.EIRP Effective Isotropic Radiated Power.EM Electromagnetic.ES Energy Scavenging.FCC Federal Communications Commission.FDD Frequency-Division Duplexing.FPGA Field Programmable Gate Array.GaAs Gallium Arsenide.GaN Gallium Nitride.HB Harmonic Balance.HEMT High Electron Mobility Transistor.xxiGlossaryIoT Internet of Things.ISM Industrial, Scientific, and Medical radio band.KCL Kirchhoff’s Current Law.KVL Kirchhoff’s Voltage Law.LS Large-Signal.MESFET Metal Semiconductor Field Effect Transistor.MMIC Monolithic Microwave Integrated Circuit.MOSFET Metal Oxide Semiconductor Field Effect Transistor.PDK Process Design Kit.PWM Pulse Width Modulation.RF Radio Frequency.SAR Specific absorption rate.TDD Time-Division Duplexing.TEG Thermoelectric Generators.TRD Time-Reversal Duality.VNA Vector Network Analyzer.WPT Wireless Power Transfer.xxiiChapter 1Introduction11.1 Preliminary RemarksThe Internet of Things (IoT) is an evolving and massive network of interconnected electronicdevices, sensors and software. Many IoT devices are battery powered and it is estimated thathundreds of millions of battery replacements will need to be replaced every day in a networkof trillions of interconnected devices [1]. Therefore, there is great interest in devising waysto either remotely charge batteries in sensors or to completely self-power sensors using otherenergy sources. The development of maintenance free sensors has significant environmentalbenefits as well as providing improved technology for embedded applications includinginfrastructure monitoring sensors, power for biomedical implants, and wearable sensors.Different methods of scavenging or harvesting power have been investigated by re-searchers. Examples include the conversion of Thermoelectric Generators (TEG), Electro-magnetic (EM) radiation, and mechanical energy into electrical energy. A summary of thesemethods and the typical power density available at the sensor are shown in Table. 1.1 [2].Micro-power energy harvesting using indoor solar cells has gained interest for theiruse in ultra-low power IoT devices [3]. Usually, they are small in size and harvest energyat µW levels. Another harvester that is well suited for IoT devices is the piezoelectricharvester, harvesting mechanical energy from vibration. Electrical energy is generated when1Parts of Chapter 1 have been published as a journal paper:• S. Dehghani and T. Johnson. “A 2.4-GHz CMOS class-E synchronous rectifier," IEEE Trans. Microw.Theory Techn., 64(5):1655-1666, May 2016.11.1. Preliminary Remarksmechanical stress is applied to a piezoelectric material. Recently, piezoelectric energyharvesting circuits suitable for IoT devices have been demonstrated. They can harvest energyfrom a few µW to 100s of µW at efficiencies above 80% [4].TEGs can also be used to harvest energy from the temperature difference betweentwo objects. They have found widespread usage in industrial applications, where largetemperature gradients can provide hundreds of watts of power. Smaller TEGs that are moresuited for wearable devices can harvest energy from the temperature difference between thebody temperature and the room temperature. A 1-10◦C temperature difference can existbetween the human body and ambiance temperature which can provide 10-100 µW of power[5]. Recent TEG energy harvesting circuits can harvest energy from a very low temperaturedifference, usually 1-2◦C, where the TEG output voltage was less than 50 mV [6].Table 1.1: Comparison of energy harvesting sourcesEnergySource CategoryPower density(µW/cm2) Pros ConsSolar Power EM 100,000 High powerdensityNeedsexposureRF Signal EM0.02(at 5 km from50 kW AM radio)Integrated withembeddedsystemsVery lowpower densityRF Signal EM40(at 10 m from1 W RF source)Integrated withembeddedsystemsLow powerdensityBody Heat Thermal60(at 5◦Cdifference)Easy tobuildNeeds hightemperaturedifferencesExternal Heat Thermal135(at 10◦Cdifference)Easy tobuildNeeds hightemperaturedifferencesBody Motion Mechanical 800 High powerdensityDependent onmotionBlood Flow Mechanical 930,000 Very highpower densityVery lowconversionefficiency21.2. Wireless Energy TransferAmongst these different methods of harvesting energy for low power sensors, therehas been growing interest in utilizing Radio Frequency (RF) signal power because of thewidespread availability of wireless communications services. The RF spectrum is becom-ing increasing dense with sources such as TV, radio, cellular, satellite, and Wi-Fi signals.New communications technology is also becoming increasingly more sophisticated with theadoption of beam-forming technology to spatially direct RF power to specific geographiclocations.Although harvested power levels from EM sources are typically several order of magni-tude less per unit area relative to solar power, there are other advantages which RF energyharvesting has especially in terms of propagation through complex mediums. Since RFenergy can travel through materials such as water, plastic, glass, and tissue, RF embeddedsystems can be placed in areas where there is no “exposure” to light. In such scenarios, RFpower harvesting might be the only alternative as a reliable and robust source of energy.Furthermore, most wireless sensor devices use ultra-low power Complementary MetalOxide Semiconductor (CMOS) radio circuits and there is great interest in developing technol-ogy to implement fully integrated designs that include a CMOS wireless power subsystem.In a self-powered sensor, the device needs to multiplex between a power harvesting modeand a communication mode, or it must simultaneously harvest power and communicate witha remote host. Finding CMOS circuits that can implement these features is the main focusof this thesis.1.2 Wireless Energy TransferRF Energy Harvesting (EH) systems are a subset of what is more broadly called WirelessPower Transfer (WPT). Wireless power systems are divided into two main types of systemscalled near-field and and far-field. In a near-field system, the distance between the RF sourceand the receiver (device) is typically less than one wavelength (λ) at the operating frequencyas shown in Fig. 1.1(a) [7]. Over this short distance, the electromagnetic fields are reactive31.2. Wireless Energy Transferand a traveling wave which radiates into free space is suppressed. Under these conditions,coupling between the source and receiver can be obtained either through the electric fieldusing capacitive coupling or through the magnetic field using inductive coupling. Althoughnear-field wireless power transmission can be efficient, the primary limitation is the shortdistance between the source and receiver.Distanced ≈ λDistanceCapacit_ive CouplingInduct_ive Coupling(a)d λDistanceobstacleobstacle(b)Figure 1.1: Wireless power transfer: (a) near-field and (b) far-field systems.In far-field wireless power systems, the source and receiver are separated by a largedistance typically much greater than one wavelength as shown in Fig. 1.1(b). Under theseconditions, the transmitter excites a traveling electromagnetic wave that radiates through freespace. An antenna functions as the interface between the transmitter and free space, and thetransmitted power is absorbed by the environment [7].Based on how RF energy is used, far-field wireless power systems can be categorized intotwo different domains: RF Energy Scavenging (ES) and RF EH. In the ES scenario, a devicescavenges RF power from the environment using random signals from existing televisionbroadcasts, Wi-Fi and cellular communications.In this case, the available energy is dependenton location and highly time-variable. Furthermore, the transmitter side performance (suchas the dc to RF conversion efficiency), the RF output power, radio channel, and the antenna41.3. Challenges in Far-Field Wireless Power Systemsradiation behavior are not available and can only be roughly estimated. Because the ultimategoal is to scavenge all RF sources at the same time and at any possible frequency, polarization,angle of arrival, and power intensity, it is apparent that the design of such scavenging systemsis a very demanding task. Furthermore, it has been proven [8] that the available ambientRF power density is usually very low (ranging from a few nanowatts to a few microwattsper square centimeter), so highly efficient (resonant) antennas as well as carefully optimizedrectifiers are needed.On the other hand, the EH scenario is provided with dedicated, known RF sources. Inthis configuration, the receiving system design takes advantage of the knowledge of the RFfrequencies and the direction of arrival power. Energy harvesting is an example of far-fieldwireless power transfer and it has many potential applications including the powering sensorsfor the IoT. The received power in the EH system building blocks can be higher and possiblymore predictable. Directive, single-band, resonant antennas having polarizations coherentwith those of the transmitting side can be used, and the overall system efficiency can thus bemaximized.1.3 Challenges in Far-Field Wireless Power SystemsThe implementation of practical circuits that are robust enough to power sensors is a chal-lenging problem. Design constraints that make the implementation of energy harvestingcircuits difficult to implement are described below.1. Receive power is typically very low. Ambient RF energy has very low power densitiesin the range of 0.2 nW/cm2 to 1 µW/cm2which is low compared to other energy sources.An example of RF power densities measured in London, U.K. for different frequencybands is shown in Table 1.2 [9].2. The space available for the receiving antenna is (very) small. Although integrationis highly desirable in self-powered sensors, this presents significant challenges in the51.3. Challenges in Far-Field Wireless Power SystemsTable 1.2: Summary of RF survey measurements for London, UK.Band Frequency(MHz)Average SBA(nW/cm2)Maximum SBA(nW/cm2)DTV 470-610 0.89 460GSM900 925-960 36 1,930GSM1800 1805-1880 84 6,3903G 2110-2170 12 240WiFi 2400-2500 0.18 6available area for antennas. The total power received by the sensor is proportionalto the effective aperture area of the antenna. Compact antennas have small apertureswhich reduces the amount of power received for energy harvesting.3. Long integration times are required to accumulate significant energy. Sincereceive power is low, there is a trade-off in terms of the power consumption of the elec-tronic device and the time required to recharge the batteries. Examples of harvestingtime for different RF power levels are shown in Table 1.3.Table 1.3: Time to fully charge different devices using RF power sources.Battery Type Receive Power PowerandCapacity10 µW(-20 dBm)10 mW(10 dBm)1 W(30 dBm)Usage(mW)Low Power Sensor(0.5 Wh) 50,000 hrs 50 hrs 0.5 hrs 0.5E-book reader(5 Wh) 500,000 hrs 500 hrs 5 hrs 178iPhone 7(7 Wh) 700,000 hrs 700 hrs 7 hrs 580iPad 2(27 Wh) 2,700,000 hrs 2,700 hrs 27 hrs 27004. Path loss increases with distance. Although the ambient RF power density is usuallyhigher in urban areas, the distance from the RF source significantly affects the availablepower density received by the energy harvester. Propagation loss (L) in a line-of-sight61.4. RF Energy Harvesting Systemsradio system in decibels can be expressed asL = 20 log(4piRλ0)(1.1)where, R is the distance from the RF source, and λ0 is the wavelength of the sourcefrequency. Propagation loss (L) is proportional to the square of the distance betweenthe transmitter and receiver as well as the square of the frequency of the radio signal. Inother words, free-space path loss increases significantly over distance and frequency.Three Industrial, Scientific, and Medical radio band (ISM) bands, namely 900 MHz,2.4 GHz and 5.8 GHz, are heavily used in far-field wireless power transfer applications.Examples of path loss for the three ISM bands are shown in Table. 1.4.Table 1.4: Path loss for different ISM band for different distances.Transmitter/Receive DistancesFrequencyBand 1 m 10 m 20 m900 MHz 31.5 dB 51.5 dB 57.5 dB2.4 GHz 40 dB 60 dB 66 dB5.8 GHz 47.7 dB 67.7 dB 73.7 dB1.4 RF Energy Harvesting SystemsDeveloping RF energy harvesting solutions is a system design problem that includes aconsideration of a wide range of factors. At the highest level, there is the system architecturethat influences choices in frequency, receive power, and antenna size. System architecturealso affects the high level design of circuitry including the requirements of circuit blocksin the wireless power subsystem. After the system architecture is established, the detaileddesign of different circuit blocks such as RF rectifiers can be commence. The research workin this thesis relates to specific circuits and a brief overview of the system considerations arepresented first to give context to the research objectives.71.4. RF Energy Harvesting Systems1.4.1 Integration, Size and CostSince most ultra-low power radios in wireless sensors are fabricated in CMOS technology,a fully integrated design which includes a CMOS wireless power subsystem is desirable. Inaddition to integration, CMOS technology is low cost and scalable to large volume manu-facturing processes. On the other hand, CMOS technology has frequency and performancelimitations compared to discrete designs using compound semiconductor technologies suchas Gallium Nitride (GaN) or Gallium Arsenide (GaAs) devices. Therefore optimized CMOScircuits that can meet the system requirements for energy harvesting applications are ofinterest.1.4.2 Operating FrequencyThe power density of ambient RF sources is highest in the spectrum below 10 GHz. Withinthe spectrum below 10 GHz there are unlicensed ISM bands that are used extensively formany applications. Although these bands are unlicensed, they are regulated, and transmit-ters must not exceed specified power levels. Spectrum regulations defined by the FederalCommunications Commission (FCC) or Industry Canada are similar in most countries andoften cited as a benchmark in research work.Health Canada [10] and Industry Canada [11] specify that for these three ISM frequencyband, the maximum power that can be delivered to the antenna is 30 dBm (1 Watt) andthat the maximum Effective Isotropic Radiated Power (EIRP) from the antenna is 36 dBm(4 Watt). EIRP is defined as the sum of the transmit power (dBm) plus the antenna gain(dBi). Health Canada regulations state that the Specific absorption rate (SAR) limit is settp 0.08 W/kg for the public area (uncontrolled environment). There are also some specificexceptions to maximum radiated power for fixed point-to-point wireless links. These are:1. In the 5.8 GHz band, the maximum EIRP allowed is 53 dBm (30 dBm plus 23 dBi ofantenna gain).81.4. RF Energy Harvesting Systems2. In the 2.4 GHz band, EIRP can be increased above 36 dBm to a maximum value of53 dBm providing transmit power to the antenna is reduced by 1 dB for every 3 dBiincrease in antenna gain.Based on the regulatory constraints for radiated RF power levels, energy harvesting ismost attractive in the 2.4 GHz and 5.8 GHz bands. Designs which use ambient RF power ordirected RF power using beam-forming methods are both possible in these bands providingthe maximum EIRP levels are not exceeded. Therefore, this work focuses on circuit designfor frequencies at 2.4 GHz and 5.8 GHz.1.4.3 Antenna RequirementsThe wavelength of frequencies in the 2.4 GHz and 5.8 GHz bands are much larger thanthe typical size of CMOS chips which may have sizes in the millimetre or sub-millimetrerange. This makes the integration of an antenna on the silicon chip very challenging andpractical designs are likely to require off-chip antennas to obtain reasonable receive powerlevels for powering the device. Therefore, an off-chip antenna is considered as a reasonableconstraint in the design of the energy harvesting circuits. Since antennas require a matchedimpedance to maximize power transfer from the antenna to the circuit, on-chip antennamatching is highly desirable. However, the matching circuit design is also closely linked tothe packaging design which includes bond wires and a lead frame. Therefore, the interfacebetween the antenna and chip must be modeled.1.4.4 Link BudgetThe requirements for the overall system efficiency and effective coverage area must be con-strained to realize practical EH systems. The system trade-offs are found from an analysisof the link budget between the RF source and the energy harvesting device. The link budgetanalysis also establishes requirements for circuit blocks in the EH system. Important speci-fications that are obtained from the link budget analysis include the selection of frequency,91.4. RF Energy Harvesting Systemsbandwidth, transmit power, antenna gains, and the dynamic range requirements of the energyharvesting rectifier.To limit the scope of this thesis, only line-of-sight links will be considered. The followingequation shows the basic elements that need to considered when calculating a link budget:Received Power (dBm)=Transmitted Power (dBm)+Gains (dB)-Losses (dB)Similar to a wireless data link, if the estimated received power is sufficiently large(typically relative to the receiver power sensitivity), the link budget is said to be sufficient forsending power under perfect conditions. The amount by which the received power exceedsreceiver sensitivity is called the link margin.In a line-of-sight radio system, losses are mainly due to free-space path loss in (1.1).Other losses in a radio system include antenna cabling and connectors. For example, typicallosses for an external antenna at a frequency of 5.8 GHz are 0.25 dB loss per connector and0.08 dB loss for every 30 cm of antenna cable [12].The line-of-sight path loss expression shown earlier in equation (1.1) can be furthersimplified toL = 20 log (R) + 20 log ( f ) + 32.45 (1.2)where R is distance measured in meters and f is the frequency in GHz. In addition to adirect path, most radio environments generate multiple interference paths and margin formultipath fading should be allocated. For example, a 10 dB margin for multipath fading maybe required to obtain robust operation in a cluttered environment. Therefore, link margin canbe summarized asLink Margin (dB)=Received Power (dBm)-Receiver Sensitivity (dBm)101.4. RF Energy Harvesting SystemsThe following example illustrates how a link budget is calculated:Example:• Distance: 10 m• Frequency: 5.8 GHz• Link Type: Point-to-Point (PxP)• Line-of-Sight: Yes• RX Antenna Model: Ubiquiti Networks AMO-5G13• RX Antenna Gain: 13 dBi• TX Antenna Model: Ubiquiti Networks PBE-M5-400-ISO• TX Antenna Gain: 25 dBiLink Budget Analysis: First, we need to calculate the receive power. In order to do that,we need to know the transmitter power and antenna gains in the sensor system. The transmitpower is +18 dBm and the transmit antenna has a gain of 25 dBi. The receive antenna has again of 13 dBi and at this point we will neglect cables and connectors losses.Since this is a point-to-point link, the primary loss is free-space-path loss given inequation (1.2). The path loss at 10 m is 67.7 dB for 5.8 GHz as shown in Table 1.4. Thereceived power can then be calculated as follows:Rx (dBm) = Tx (dBm) + Tx Ant.(dBi) + Rx Ant.(dBi) - L (dB)=18 + 25 + 13 - 67.7 = -11.7 dBmTherefore, if the energy harvesting receiver has a sensitivity of -12 dBm, then the point-to-point EH system can operate over a 10 m distance assuming a transmit power of +18 dBm.If an additional 10 dB of margin is required for multipath fading, then the requiredtransmit power for the link budget is +28 dBm which is still within regulatory limits. Underthis condition, the line-of-sight receive power increases to -2 dBm. If the distance betweenthe transmitter and receiver is reduced to 5 m at a frequency of 5.8 GHz, then the receive111.5. Review of State-of-the-Art Energy Harvesting Circuitspower increases further to +4 dBm. From these scenarios it is concluded that the RF inputpower range to the energy harvesting rectifier could range for -12 dBm to +4 dBm dependingon the antenna gains and distance. Other scenarios could shift this power range and therectifier designs investigated in this thesis are designed to align with these typical cases.1.5 Review of State-of-the-Art Energy Harvesting CircuitsMany energy harvesting systems employ Frequency-DivisionDuplexing (FDD) to implementa radio link that can simultaneously harvest power while transmitting or receiving sensordata. In these systems, two different frequencies are used for energy harvesting and for datatransmission. The primary circuit blocks in a FDD type wireless power subsystem consistof a RF rectifier followed by a dc power management block. The concept is illustrated inFig. 1.2 [13, 14].TX (f2)RX (f1)Transmit_terPARect_ifierRF Energy HarvesterPower management&Energy storageFrequencyDuplexerSensoroscLNAmixerDecoderReceiverFigure 1.2: Sensor node using FDD architecture with RF energy harvesting.The RF rectifier converts the incident RF power to dc power. The dc power managementblock controls the load impedance to the rectifier as well as provides a regulated outputvoltage for charging a battery or directly powering a sensor and a receiver block. The main121.5. Review of State-of-the-Art Energy Harvesting Circuitsfeature of this architecture is that it incorporates a dedicated energy harvesting circuit that isalways powering the system sensor. Therefore, energy harvesting and communication withthe sensor can occur simultaneously.In the following sections, a literature review is presented on the design RF rectifiers. Thereview establishes important benchmarks that are useful for comparing the power conver-sion efficiency of new work in CMOS rectifiers as well as highlight circuit topologies thathave been implemented. Following the rectifier review, two new concepts are proposed toimprove the implementation of efficient energy harvesting systems. The first concept is atracking load circuit that can dynamically change the load impedance as RF power changes.By adding a tracking dc load, rectifier efficiency can be maximized under variable RF inputpower conditions. The second concept is a new type of sensor architecture that implementsTime-Division Duplexing (TDD) where the energy harvesting block cycles between a har-vesting and transmission mode at the same frequency. A unique circuit is proposed that isbidirectional and can function as both a rectifier and oscillator. Therefore, literature refer-ences related to the design of bidirectional circuits and CMOS power oscillators are alsoreviewed.1.5.1 RF Rectifier CircuitsPublished work on the design of RF to dc rectifiers can be broadly classified into integrateddesigns (CMOS andMonolithic Microwave Integrated Circuit (MMIC)) and discrete designsimplemented with diodes or transistors. There are different metrics which can be used tocompare designs including frequency, efficiency, dynamic range, area, matching and circuittopology. Using these metrics, a summary of recent work is shown in Table 1.5. Thecomparison table is complemented by Fig. 1.3 which shows the dynamic range versus powerefficiency for each design listed in the table.CMOS rectifier designs in Table 1.5 span a frequency range of 950 MHz to 5.8 GHzand designs [15–21] use voltage multiplier circuits to rectify low power RF input signals.131.5. Review of State-of-the-Art Energy Harvesting CircuitsWhen comparing these designs, it is important distinguish the conditions under which powerefficiency is reported. In [17–19, 21], the designs include input matching circuits with asingle-ended RF input source and RF to dc power efficiency ranges from 8.8% to 15.9%.In other work, [15, 16] and [20], the power efficiency that is reported ranges from 29% to67.5% and the measurements have been de-embedded to exclude input mismatch loss. Inputmismatch loss can be quite significant if the input impedance deviates from the antennaimpedance and therefore de-embedding input mismatch loss can result in significantly higherpower efficiency.-20 -15 -10 -5 0 5 10 15 20 25 30 35010203040506070 [15] CMOS 0.35 m [16] CMOS 0.18 m [17] CMOS 0.18 m [18] CMOS 0.13 m [19] CMOS 0.13 m [20] CMOS 0.18 m [21] CMOS 0.13 m [22] MMIC 0.35 mPower Efficiency (%)Input Power (dBm)Integrated Rectifier(a)0 5 10 15 20 25 30 35 400102030405060708090Discrete Rectifier [23] HSMS 3923 diode [24] HSMS 8202 diode [26] HSMS 8202 diode [27] HSMS 2820 diode [29] E-pHEMT transistor [30] GaN HEMT transistor [31] GaAs pHEMT transistorPower Efficiency (%)Input Power (dBm)(b)Figure 1.3: Performance comparison of reported RF rectifier circuits: (a) integrated rectifier circuitsand (b) discrete rectifier circuits.Another distinction between different designs is whether the circuit requires a differential141.5. Review of State-of-the-Art Energy Harvesting Circuitsinput signal. In a differential design, if a single-ended antenna is connected to the rectifier,an input balun is required and losses associated with the balun reduce the overall efficiency.Table 1.5: Performance comparison of recently reported RF rectifier circuitsRef. f0(GHz)Pin(dBm)ηRF-dc(%)CircuitTopology TypeInputMatchingCMOS RF Rectifiers (Integrated)[15] 0.953 -9.9 29 Self-ThresholdCancellationCMOS0.35 µm Not Included[16] 0.953 -12.5 67.5 DifferentialDriveCMOS0.18 µm Not Included[17] 2.4 12 8.8Full WaveVoltage MultiplyingUsing TransformerCMOS0.18 µm Included[18] 2.4 6 10.2 8 stagesVoltage MultiplyingCMOS0.13 µm Included[19] 2.4 0 15.9 4 stagesDifferential DriveCMOS0.13 µm Included[20] 2.4 8.9 47 2 stagesDifferential DriveCMOS0.18 µm Not Included[21] 5.8 0 14 5 stagesVoltage MultiplyingCMOS0.13 µmIncluded(Bondwire)MMIC RF Rectifiers (Integrated)[22] 10.1 26 63.94 Class-C HEMT GaN0.15 µm IncludedSchottky Diode RF Rectifiers (Discrete)[23] 0.8 16 60 Class-E HSMS 3923 Included[24] 0.9 13 80 Class-F HSMS 8202 Included[25] 2.45 10 61 Modified Bridge HSMS 2863 Included[26] 2.45 14.7 77 Shunt Diode HSMS 8202 Included[27] 2.45 13 72 Half-WaveSeries Diode HSMS 2860 Included[28] 2.45 10.8 60 Dual Diode HSMS 2820 IncludedSwitched Transistor RF Rectifiers (Discrete)[29] 0.7 17 83 Class-E E-pHEMTATF54143 Included[30] 0.985 40.3 81.3 Class-F HEMT GaNCGH40010F Included[31] 5.1 16 51 — pHEMT GaAs0.15 µm IncludedFrequency is also another variable which affects the power efficiencies in Table 1.5.Higher power efficiency is reported for lower frequencies; for example, in [16, Fig. 7] powerefficiency was measured at frequencies of 100 MHz, 500 MHz, 953 MHz, and 2 GHz. Thecorresponding power efficiencies for a differential input source and without input mismatch151.5. Review of State-of-the-Art Energy Harvesting Circuitsloss are 82%, 73%, 67% and 57%.For comparison with CMOS rectifier designs, Table 1.5 also shows recent work in theimplementation of RF to dc rectifiers using MMIC’s [22] and discrete devices. Discrete RFrectifier designs include diode circuits [23–28] and transistor switching circuits [29–31]. Thetypical power efficiency of discrete rectifier designs is higher than CMOS and ranges from51% to 83%. However, despite the high performance of discrete designs, they are not easilyintegrated into ultra-low power CMOS wireless radio hardware.1.5.2 DC Load CircuitsSimilar to the input RF match for the rectifier, the dc load impedance has a significant effecton the overall power efficiency of the RF rectifier. The optimum dc load varies as a functionof RF input power, and in this research project, a two stage dc to dc converter is proposedas a way of implementing a robust load management circuit that provides the optimum loadimpedance to the RF rectifier over a range of RF input power conditions.The first stage is configured as a dc to dc converter, which operates in a DiscontinuousCurrent Mode (DCM). The control for the DCM converter is steered by the measurement ofcurrent and voltage at the input of the converter. The control loop adjusts the duty cycle ofthe DCM converter to a condition that maximizes the power delivered by the rectifier. Sincethe control loop is designed to maximize load power, it can also track changes in RF inputpower. A detailed analysis of the circuit is described in Chapter 3 and relevant literaturereferences are cited there.1.5.3 Reconfigurable Architectures for RF Energy HarvestingOne of the objectives in this thesis is to design and implement a bidirectional and reconfig-urable circuit block that has both rectification and transmit modes. The concept is shown inFig. 1.4. After conducting a literature survey, the concept appears to be novel.In this architecture, a single antenna is used for both communication with the device161.5. Review of State-of-the-Art Energy Harvesting CircuitsPower management&Energy storageTimeDuplexerBidirect_ional CircuitPower Oscillator /Rect_ifierSensorLNAmixerDecoderReceiverTX(f)RX(f)RF Energy HarvesterTransmit_terFigure 1.4: Sensor node using TDD architecture with a bidirectional front-end reconfigurable forRF energy harvesting and transmission modes.and powering the device. Instead of using an FDD duplexer, the structure uses TDD anda bidirectional and reconfigurable circuit block that multiplexes between a rectifier/receivemode and an oscillator/transmit mode. An advantage of the TDD architecture is that theduplexing can be integrated on the chip with a switch avoiding the need to use an off-chipfrequency duplexer. A reduction in the overall circuit area is also possible with reconfigurablecircuits used in the TDD architecture. A survey of recent work in the implementation ofCMOS rectifiers was described earlier in section 1.5.1 and a brief literature review of poweroscillators and bidirectional circuits are described next.Power OscillatorsIn recent work related to the design of CMOS oscillators there has been significant effortfocused on improving the phase noise of CMOS oscillators [32–36] and reducing dc power.However, these designs are focused on small signal oscillators that drive high impedance loadsand the designs are appropriate formixers in transmitters and receivers. Thework ismotivatedby reducing power consumption for ultra-low power transceivers. Other techniques which171.5. Review of State-of-the-Art Energy Harvesting Circuitshave been used to reduce power consumption include operating devices with low conductionangles such as class-B or class-C or switching techniques that use harmonic terminations toreduce device dissipation [37–39].Although progress has been made to create ultra-low power CMOS oscillators, thesedesigns cannot be used to generate significant RF output power. In fact, the power efficiencyof these designs are very low because they have been optimized to drive high impedanceloads. A power oscillator is fundamentally different and the design must balance phase noiserequirements with high-power. The efficiency of the oscillator is also very important in awireless relay node.High-power and high-efficiency oscillator designs have been primarily limited to discretedesigns. A number of papers [40–42] have been devoted to improve the dc to RF conversionefficiency of power oscillators with discrete devices by adopting the switchingmode amplifierconcepts. In [40], a 800 kHz class-E oscillator was designed with an output power of 1 W.Because the frequency of the designwas low, a feedback networkwith the required phase shiftcould be designed without considering the effects of intrinsic device capacitance. At highfrequencies, device capacitance modifies the loop phase and it is more difficult to implementthe feedback network. In [41], an experimentally tunable feedback networkwas used to designa 5 GHz class-E oscillator. The oscillator has an output power of 300 mW and the optimumphase for maximizing the efficiency of the oscillator was obtained by experimentally tuningthe prototype. More formal oscillator design methodologies appropriate for high frequencyoscillators have also been worked on. In [42], a systematic nonlinear design procedurebased on load pull optimization of the transistor harmonic terminations has been presented.However, the procedure requires an accurate nonlinear device model or experimental loadpull measurements for the device which may not always be available.181.5. Review of State-of-the-Art Energy Harvesting CircuitsBidirectional and Reconfigurable Oscillator/Rectifier CircuitsThe operation of the proposed bidirectional and reconfigurable circuit block relies on theconcept of Time-Reversal Duality (TRD) [43]. Time-reversal duality shows that a circuit canbe used both as an oscillator and a rectifier by reversing the power flow in the circuit. In theoscillator mode, dc power is converted to RF power, while in the rectifier mode, RF power isconverted to dc power. The duality of oscillator and rectifier circuit topologies has been usedto implement very high frequency switching dc to dc converters. A reconfigurable class-Eoscillator/rectifier in the UHF band is detailed in [44] for power in the mW range. Althoughhigh-efficiency was demonstrated for both circuit modes, the efficiency was sensitive to biaspoints and high-efficiency is limited to a small dynamic range. Other examples of high-power oscillator and rectifier circuits used in dc-dc converters are shown in [45, 46]. Thesedesigns use a class-E oscillator (inverter) and a class-E rectifier that are connected together toimplement a dc to dc converter. The authors refer to these converters as class-E2 convertersand the designs demonstrate operation at 780 MHz and 1 GHz with efficiencies around 70%at an output power of approximately 10 W. However, all these designs use discrete MetalSemiconductor Field Effect Transistor (MESFET) or GaN High Electron Mobility Transistor(HEMT) devices and they are not appropriate for low power sensor applications.After reviewing the literature, a fully integrated CMOS bidirectional circuit block basedon the theory of TRD is proposed. Design challenges which need to be addressed includethe implementation of a high-efficiency power oscillator and a high-efficiency synchronousrectifier. Other desirable features include a circuit that is:1. self-biased and does not require an external supply;2. a rectifier which operates over a wide dynamic RF input power range;3. a power oscillator which operates over wide range of supply voltage;4. and an RF input/output port that is matched to 50 Ω.191.6. Summary of Research Objectives and ContributionsA design methodology that is rigorous and considers layout and intrinsic device capacitancesis also required to fabricate a monolithic CMOS circuit. In this work, a new systematicnonlinear technique to optimize the output power and efficiency of switching-mode poweroscillators in CMOS technology is proposed. Although constrained to a specific feedbacknetwork topology, the technique enables a simple and reliable design of high-efficiency poweroscillators. The self bias operation in both modes (power oscillator/synchronous rectifier) isanother main contribution of the this work.1.6 Summary of Research Objectives and ContributionsThe research objectives and contributions described in this thesis are summarized below.• Objective 1: Selecting a suitable RF rectifier circuit topology for integration intoCMOS processes.Contributions:– Reviewed RF energy harvesting architectures and essential systems requirements(Chapter 1).– Identified CMOS implementation challenges (Chapter 1).– Selected synchronous rectifier solutions as an appropriate circuit topology basedon the time-reversal duality concept (Chapter 2).– Analyzed the performance (power efficiency, dynamic range, bandwidth, inputmatch) of the proposed RF rectifier circuit topology and compared designs withother published work (Chapter 2).• Objective 2: Design and implement high-efficiency CMOS synchronous rectifierscircuits using the concept of time-reversal duality.Contributions:– Used time-reversal duality theory to transform switch-mode amplifier circuitsinto synchronous rectifier circuits (Chapter 2).– Designed and implemented three different self-bias synchronous rectifier, namely:class-E synchronous rectifier, class-D synchronous and transconductance mode201.6. Summary of Research Objectives and Contributionssynchronous rectifier in IBM 0.13 µm CMOS technology (Chapter 2).– Characterized and compared the different synchronous rectifier circuit imple-mentations in terms of performance and chip area (Chapter 2).– Tested and verified the CMOS synchronous rectifier circuits using a probe station,vector network analyzer, spectrum analyzer and power meter (Chapter 2).• Objective 3: Investigate the sensitivity of synchronous rectifiers to dc loadimpedance and methods to adapt load impedance to maximum rectifier powerefficiency.Contributions:– Studied the input impedance characteristics of a dc to dc converter as a variableload for RF rectifiers. (Chapter 3)– Analyzed and designed an analog control loop to autonomously adjust dc loadimpedance as RF power changes. (Chapter 3)– Implemented a high-efficiency dc to dc converter with analog control loop usingdiscrete components. (Chapter 3)– Verified dc matching performance with a high-power class-F synchronous recti-fiers under variable input power. (Chapter 3)• Objective 4: Design and implement a bidirectional circuit block suitable for TDDsensor architectures.Contributions:– Selected a reconfigurable class-DE circuit topology. (Chapter 4)– Designed a high-power high-efficiency CMOS circuit for both power oscillatorand rectifier modes. (Chapter 4)– Proposed self-bias and self-synchronous circuits for both modes. (Chapter 4)– Implemented a design in 65 nm TSMC CMOS technology. (Chapter 4)– Conducted experimental tests to verify oscillator and rectifiermodes of operation.Compared theoretical, simulation and experimental results. (Chapter 4)21Chapter 2Synchronous Rectifiers22.1 IntroductionIn this chapter, the design of CMOS synchronous rectifiers are investigated. The rectifiercircuits are derived from high-efficiency amplifier circuits using the theory of time-reversalduality (TRD). The theory is first applied to transform high-efficiency switch-mode amplifiersoperating in class-E and class-D modes into high-efficiency synchronous rectifiers. Themethodology provides a good starting point for the CMOS rectifier designs but a practicaldesign requires significant optimization to maximize efficiency.Switching losses are high at GHz frequencies and another class of synchronous rectifierscan be obtained by transforming transconductance amplifiers. The transconductance modeamplifier is biased in a way that enables class-C operation at high RF input powers, and class-B and class-A modes as the RF power is backed off. A dual range design is investigated as away of extending the dynamic range of rectifiers. The design methodology and experimentalresults for the different synchronous rectifiers are described in the following sections.Applying the principle of TRD to power amplifiers, three different RF synchronousrectifiers were designed using the IBM CMRF8SF process design kit for 0.13 µm CMOS2Some parts of Chapter 2 have been published as a journal paper and two conference papers:• S. Dehghani and T. Johnson. “A 2.4-GHz CMOS class-E synchronous rectifier," IEEE Trans. Microw.Theory Techn., 64(5):1655-1666, May 2016.• S. Dehghani and T. Johnson. “2.4-GHz CMOS class-D synchronous rectifier," In IEEE MTT-S Int.Microw. Symp., pages 1-3, May 2015.• S. Dehghani and T. Johnson. “Transconductance mode CMOS synchronous rectifier circuits," In IEEEMTT-S Int. Microw. Symp., pages 1-3, May 2016.222.2. The Principle of Time-Reversal Dualitytechnology. In all cases, the rectifiers are compared to the amplifier duals and the workprovides new benchmarks for RF CMOS rectifiers. Most literature references describingimplementations of RF CMOS rectifiers typically use the voltage multiplier or Dicksonmultiplier [47] to create CMOS rectifiers without providing a systematic design of inputmatching circuits [15, 16]. Therefore, many published results do not include input mismatchpower loss and the rectifier efficiency is calculated mathematically from measured mixed-mode S-parameters. The disadvantage of this method is that the rectifier efficiency thatwould be obtained in a practical circuit with input matching may be significantly less than ade-embedded measurement which removes input mismatch loss.Other highlights of the research work include a comparison of class-E, class-D andtransconductance mode rectifiers under similar ranges of input RF power conditions. Theoptimal load resistance which maximizes RF to dc conversion efficiency is also characterizedfor the different rectifier designs.2.2 The Principle of Time-Reversal DualityThe concept of duality in circuit theory is useful for transforming circuits to create newtopologies that are equivalent in the sense that voltage and current waveforms are inter-changed. Examples of circuit duals include series and parallel resonators [48]. Amplifiercircuits also have voltage and current duals. For example, class-D, class-E, and class-Famplifiers switch voltage, while the current duals, called inverse class-D, inverse class-E andinverse class-F, switch current [49].Another form of duality is the theory of time-reversal duality. The concept of time-reversal has been used in digital circuits to read in reverse order the data written into digitalmemory [50, 51]. Time-reversal duality has also been applied and developed for analogcircuits by Hamill [52] in 1990. The work of Hamill is relevant to the design of synchronousrectifiers and important relations are reviewed next.232.2. The Principle of Time-Reversal Duality2.2.1 Time-Reversal Duality RelationsThe operation of the time reversed network is similar to the original network providing lossesare negligible. An n-dimensional continuous-time dynamical system D with state vectorx ∈ IRn is characterized by the vector differential equationddtx(t) = f [x(t), t]. (2.1)Hamill shows that a second unique dynamical system D† can be constructed from D that hasa state vector x† ∈ IRn such that x†(t) = x(t). The vector differential equation for x† can bewritten asddtx†(t) = − f [x†(t),−t] = f †[x†(t), t]. (2.2)The transformation to f † is obtained by changing the sign of f and reversing time.In circuit theory, a network must satisfy Kirchhoff’s laws for voltages and currents thatare constrained by relations which model circuit components. From these relations, it canbe shown that there are four possible combinations of voltages and currents that satisfy thetime reversed dynamical system. The corresponding time reversed relations are summarizedin Table 2.1. In the table, L, C and R are defined as time invariant inductance, capacitanceand resistance, respectively, and E(t) and J (t) are time variant voltage and current sources,respectively. Of the four combinations, two lead to practical circuits implementations (Type1 and Type 2). However, Type 3 and Type 4 due to their negative reactances are not practical.Table 2.1: Practical circuits derived from time-reversal duality theory.Type i†(t) v†(t) L† C† R† E†(t) J†(t)Type 1 −i(−t) v(−t) L C −R E(−t) −J (−t)Type 2 i(−t) −v(−t) L C −R −E(−t) J (−t)Type 3 i(−t) v(−t) −L −C R E(−t) J (−t)Type 4 −i(−t) −v(−t) −L −C R −E(−t) −J (−t)242.2. The Principle of Time-Reversal DualityThe currents in Type 1 circuit duals (i† and J†(t)) are obtained by reversing the directionof current flow and reversing time, while the voltages in the circuit are only time reversedwith the same polarity as in the original circuit. On the other hand, in Type 2 circuit duals,both the polarity and time of the voltages are reversed, while the currents are only timereversed.2.2.2 Power Flow in time reversed NetworksIn Type 1 and Type 2 circuits, either the current or voltage becomes negative, but not both.Since power is the product of current times voltage, the instantaneous power p† in the dualcircuit is given byp†(t) = v†(t) i† (t) = −v(−t)i(−t) = −p(−t). (2.3)An important consequence of time reversed circuit duals is that power flow is reversedin the transformed circuit because of the sign change in current or voltage. This propertyis very useful in applications such as power electronics, because it allows the synthesis ofpower converters with reversed or bidirectional energy flow.Resistive circuit losses are dissipative and an exact time reversed dual requires negativeresistance to operate in the circuit dual. This is shown in Table 2.1 where the dual for R† is−R. Since negative resistance is not physically realizable, TRD is not exact when losses aresignificant. However, the theory of TRD is still very useful to develop circuit topologies thatcan reverse power flow.2.2.3 Amplifier and Rectifier Circuit DualsThe concept of time-reversal duality is central to this work and can be used to convertamplifier circuits into synchronous rectifier circuits. An example is shown in Fig. 2.1. Inan amplifier, the primary input power is the dc drain supply, PDC , and the output is the252.2. The Principle of Time-Reversal Dualityamplified RF signal, Pout . The TRD network is a rectifier circuit where RF input power Pinis converted into a dc power P′DC . In other words, an amplifier can be thought of as a dc toac converter (inverter), while the corresponding time reversed circuit dual is a rectifier, or anac to dc converter.VDDRLVSLDDMatchingCircuitVGGLGGRS M1MatchingCircuitIDC PDCPoutIout(a)VSLDDMatchingCircuitVGGLGGRS M1MatchingCircuitI′DCP′DCPinRDCVinRLIin(b)Figure 2.1: Block diagrams of (a) a power amplifier, (b) synchronous rectifier dual.Time-reversal duality also has implications in terms of the operating region of the activedevices (switches) in the circuit [53]. In a switch-mode amplifier like class-E, current flowsinto the drain of the switch and the device operates in quadrant I of the I −V plane. However,in the rectifier configuration, current flow is reversed and current flows out of the drain, whichmeans the device operates in quadrant III.Although the time reversed circuit dual of an amplifier is a rectifier, the rectifier as shownin Fig. 2.1 requires a separate gate drive signal in addition to the RF input signal. Theseparate gate drive signal is undesirable and, rather than having a second source for the gate,262.2. The Principle of Time-Reversal Dualitythe signal can be derived from the RF input. If a feedback circuit is added to sample the RFinput signal and if the phase of the signal is adjusted to switch the device synchronous relativeto the drain signals, then the rectifier can be driven entirely from the RF input signal. Acorrectly phased gate drive signal is critical to obtaining high-efficiency in the synchronousrectifier and the phase shift network must include the effects of intrinsic device capacitancesand extrinsic layout capacitances. Also, device capacitances such as gate-drain capacitance(CGD) can be exploited to implement the phase shift network.Another important consideration for the rectifier circuit shown in Fig 2.1 is the require-ment for a separate gate bias through the gate inductor LGG . In a self-powered synchronousrectifier, an external gate bias supply is undesirable and a better design would incorporate aself-biasing circuit that uses the rectified output voltage as a source. Other possible methodsof self-bias could use low or zero-threshold voltage Metal Oxide Semiconductor Field EffectTransistor (MOSFET)s. Both types of gate biasing methods are used in subsequent designs.2.2.4 Effect of Loss in TRD NetworksWhen loss is present in the dynamical systems D and D† and assuming the loss is notcompensated by negative resistance, the duality is no longer exact. The implications of losshave practical consequences especially in terms of laboratory measurements to demonstratethe principals of duality [30].In the original system D, an input power of Pin is required to deliver to an output powerPout . On the other hand, in the dual system D†, an input power of P†in is required to deliveran output power P†out . Now consider two different test methods.In the first method, the efficiency of the dual, D†, is measured under the condition wherePout = P†in are matched. In this case, the output power Pout of original system is the sameas the input power P†in of the dual system. This matched power falls out naturally from atest configuration where the original network D and the dual network D† are arranged as aseries cascade. The disadvantage of this test condition is that the input power of D and the272.2. The Principle of Time-Reversal Dualityoutput power from the D† differ by the product of the efficiencies of the systems D and D†.A second method is to measure the two circuits under conditions where the input powersare identical. In this case, the input power for the original network (Pin) is equal to the inputpower (P†in) for the dual network. Under conditions of equal input powers, the originalnetwork D and its dual network D† should have similar power efficiencies and the powerdelivered to the loads should be similar.The consequence of matching input powers in the second method is that the input powerto the dual network is scaled relative to the output power delivered by the original network.The advantage of the second method is that the operating points of the devices in the originalnetwork and its dual are closer than in the first method where the losses in the D and D† areaccumulated. Therefore, the second method is used for comparing the power efficiency ofcircuit duals.2.2.5 Phase Differences in Amplifier and Rectifier Circuit DualsAnother important implication of using time-reversal duality to construct circuit duals is thechange in phase shift that occurs in the circuit dual. This becomes very important in Chapter4 where time-reversal duality is applied to a bidirectional circuit that functions as both anoscillator and rectifier.To see how the phase changes in circuit duals, consider the amplifier and rectifier dualsin Fig. 2.1. In general, the output current of the power amplifier will have a phase shift ϕwith respect to the gate drive signal at the input. Assuming the output current is sinusoidal,it can be expressed asIoutamp (t) = Iom sin(ωt + ϕ) (2.4)where Iom is the peak amplitude of the current.Nowconsider the signals in the synchronous rectifierwhich are derived from time-reversal282.3. Class-E Synchronous Rectifierduality theory. Let the rectifier have an input current of the formIinrec = Iim sin(ωt + ϕ′) (2.5)where ϕ′ is the relative phase shift between the RF input signal and corresponding gate signalin the synchronous rectifier. The input current is also equal to the time reversed and signreversed amplifier current. Therefore, Iinrec (t) can also be expressed asIinrec (t) = −Ioutamp (−t) = −Iom sin(−ωt + ϕ) = Iom sin(ωt − ϕ) (2.6)Equating equations (2.5) and (2.6) then shows that Iim = Iom which is satisfied assuming thecircuits are lossless andϕ′ = −ϕ + 2pik for k ∈ Z. (2.7)The implication of (2.7) is that the relative phase shift between the gate drive and the outputcurrent in the amplifier changes in the time reversed circuit. This is particularly important ifthe amplifier were instead configured as an oscillator where the output signal is connected tothe input through a phase shift network. The synchronous rectifier dual would then have adifferent phase shift ϕ′ given by (2.7). For the case k = 0, ϕ′ = −ϕ; a result that is used later.2.3 Class-E Synchronous RectifierThe circuit topology for theRF class-E rectifier is obtained from the theory ofTRD.Therefore,a synchronous class-E rectifier is designed by transforming an amplifier into a rectifier andthen adding feedback to provide the required gate drive. The class-E amplifier circuit isshown in Fig. 2.2(a) and the transformed rectifier circuit is shown in Fig. 2.2(b).A feedback path from the RF input to the gate is also added in the rectifier dual to providea gate drive signal from the RF input port. In the amplifier, power flows from the dc supply to292.3. Class-E Synchronous RectifierVDDLS CS LMRL VLCVSLDDSeriesResonator Phase Shif_tInductorVGGLGGRS CinZA(ω)M1IDCiCisw iLiAA(a)LS CS LMRL VSLDDSeriesResonator Phase Shif_tInductorRSC CsampleCdcM1I′DCPhase Shif_terLT1CTCTPLT2LbGate DCPathi′sw i′CVLAi′A(b)Figure 2.2: Schematics of: (a) class-E power amplifier circuit and (b) class-E synchronous rectifiercircuit.the RF load, while in the rectifier power flows from the RF input to the dc load. Consequently,the transformation swaps the input and output nodes of the circuit.The effect of reversing the input and output nodes in the amplifier is that the drain voltageand drain current waveforms in the rectifier are time reversed compared to the amplifierwaveforms. Examples of class-E amplifier waveforms and the corresponding rectifier dualare shown in Fig. 2.3. The time-reversal of the rectifier waveforms relative to the amplifierwaveforms is clearly evident. In addition to time reversing the waveforms, the current throughthe switch in the rectifier is flipped in terms of amplitude because there is a net dc current,I ′DC , flowing out of the drain inductor LDD into the dc load (see Fig. 2.2(b)).302.3.Class-ESynchronousRectifier-1012345efdcba Gate voltage         Drain voltageVoltage (V)-1012345(d)(a)f'e'd'b'a'c' Gate voltage         Drain voltageVoltage (V)-30-20-100102030(b)fedcba Drain current         Capacitor currentCurrent (mA)-30-20-100102030(e)f'e'b'a'd'c' Drain current         Capacitor currentCurrent (mA)-1 0 1 2 3 4-5051015202530Quadrant IQuadrant IVQuadrant IQuadrant IIIQuadrant II(c)fedcba Dynamic I-V amplifier          = 77.3 %Drain Current (mA)Drain Voltage (V)-1 0 1 2 3 4-30-25-20-15-10-505Quadrant IIIQuadrant IIQuadrant IV(f)e'b'f 'a'd'c' Dynamic I-V rectifier           = 78.6 %Drain Current (mA)Drain Voltage (V)Figure 2.3: Waveforms for the class-E amplifier circuit in Fig. 2.2(a) (top row) and the class-E rectifier dual (bottom row). The gate drivesignal has rise and fall times equal to T/10 for both the class-E amplifier and class-E rectifier.312.3. Class-E Synchronous Rectifier2.3.1 Design MethodologyThe theory of class-E amplifiers is well known [54, 55], and in the ideal analysis, lossesare assumed to be negligible. On the other hand, when losses are not negligible, thevalues of circuit elements needs to be modified to optimize power efficiency. Loss analysis isparticularly relevant to monolithic CMOSRF designs because on chip inductor Q is relativelylow compared to off-chip components and conduction losses in the switch are significant.The implication of different losses is analyzed after first reviewing the ideal class-E designequations.Current and Voltage Equations for Class-E AmplifiersA class-E amplifier circuit is shown in Fig. 2.2(a). In the circuit, a switch M1 is shunted bya capacitance C. The switch closes with a frequency of fsw , also called the fundamentalswitching frequency. The switch and capacitor are combined into a subnetwork indicatedby the dashed box. At the output node labeled A there are three currents that must satisfyKirchhoff’s Current Law (KCL):iA = IDC − iL . (2.8)We now consider the different frequency components which make up the currents atnode A. A dc current, IDC , is the power supply current for the amplifier and the dc currentpasses through inductor LDD . The inductor is sufficiently large and has high impedance atthe fundamental frequency switching frequency, fsw , and at all harmonics of the switchingfrequency. The series resonator (LS and CS) has sufficiently high Q at fsw to ensure theload current, iL , is sinusoidal. Therefore, a harmonic balance analysis of currents at nodeA shows that the current iA which flows into the switch subnetwork has only two frequencycomponents: a dc component and a sinusoidal frequency component at fsw .Inside the switch subnetwork, the current iA is split between the switch current (isw) and322.3. Class-E Synchronous Rectifierthe capacitor current (iC). Therefore,iA = isw + iC . (2.9)The switch state is controlled by the input gate signal VS . When the switch is on, current iAflows through the switch, and when the switch is off, current iA flows through the capacitor.In Fig. 2.2, the voltage waveform at node A, vA, is directly linked to the shape of thecapacitor current waveform, iC . The relation is given byvA(t) =1C∫ t0iC (t) dt. (2.10)Since the capacitor current has harmonic frequency components, the voltage waveform atnode A also has harmonic frequency components. At this point, it is important to note thatno assumptions have been made about switching time. Equations (2.8), (2.9), and (2.10) arevalid for both instantaneous switching as well as for finite switching times.2.3.2 Ideal Class-E Amplifier EquationsIn a CMOS design, losses are significant. Our goal is to investigate how different lossmechanisms impact power efficiency, as well as determine how component values for anideal class-E design need to be modified to maximize power efficiency in the presence ofloss. As a first step, equations for the ideal class-E amplifier with no loss are summarized.These equations are then used to study losses.All signals in the class-E circuit are assumed to be periodic and in the steady state. Sincethe signals are periodic, it is convenient to work with the instantaneous phase of signalsrather than time. The instantaneous phase is defined as θ = ωswt = 2pi fswt. It is assumedthe gate drive signal has a 50% duty cycle, and over a 2pi interval of θ, the switch is on from0 to pi and off from pi to 2pi.332.3. Class-E Synchronous RectifierThe output load current iL is sinusoidal and defined asiL (θ) = −Iom sin(θ − ϕ) for θ ∈ [0, 2pi] (2.11)where Iom is the peak amplitude of the load current. The load current has an initial phaseϕ determined by imposing a zero voltage switching condition on the capacitor voltagewaveform. The dc supply current is IDC , and the current into the switch subnetwork isiA(θ) = IDC + Iom sin(θ − ϕ) for θ ∈ [0, 2pi]. (2.12)Equation (2.12) can also provide an expression for the dc current by noting that the currentiA is zero at θ = 0. Evaluating this condition showsIDC = Iom sin ϕ. (2.13)This equation also shows that the peak load current Iom can be expressed as IDC csc ϕ.When the switch is on for the interval [0, pi], the voltage is ideally zero, and all the currentiA flows through the switch. Using equations (2.12) and (2.13), the switch current isisw (θ) = IDC (1 + cot ϕ sin θ − cos θ) (2.14)for θ ∈ [0, pi].The voltage across the switch is found using equation (2.10). When the switch is openduring the interval [pi, 2pi], the capacitor current iC is equal to iA, and the correspondingvoltage isvA(θ) =12pi fswC∫ θpiiA(θ ′) dθ ′=Iom2pi fswC[(θ − pi) sin ϕ − cos(θ − ϕ) − cos ϕ] (2.15)342.3. Class-E Synchronous Rectifierfor θ ∈ [pi, 2pi]. An ideal class-E amplifier has zero voltage switching which requiresvA(pi) = vA(2pi) = 0. The zero voltage switching is satisfied providingϕ = arctan( 2pi)= 32.482◦. (2.16)The dc supply voltage for the amplifier is found by calculating the average value of theswitch voltage waveform vA over a 2pi interval. Noting that the voltage is zero when theswitch is closed over the interval (0, pi), and using equation (2.15) for vC over the open switchinterval,VDD =12pi∫ 2pipivA(θ)dθ =IDCpiωsw C. (2.17)The last expressions required to design an ideal class-E amplifier are values for the phaseshift inductor LM and the shunt capacitance C.These values can be found from the required impedance seen looking towards the loadat node A (see Fig. 2.2(a)). The optimum load impedance at node A is [56–58]ZA,opt (ωsw) = (0.1836 + j0.2116)/(ωsw C) (2.18)for the fundamental frequency. For harmonic frequencies, ZA,opt (ω) is ideally open; however,in practical circuits the loaded Q of the output network is finite and the impact of finiteharmonic impedance needs to be considered. From equation (2.18), the real and imaginaryparts can be used to find expressions for C and LM :C = Re[ZA,opt (ωsw)] = 0.1836/(ωsw RL) (2.19)andLM = Im[ZA,opt (ωsw)]/(ωsw) = 0.2116/(ω2sw C). (2.20)352.3. Class-E Synchronous RectifierCurrent/Voltage Overlap LossesWhen the gate drive signal has finite switching times, this modifies the waveforms in theclass-E amplifier. Since the switch current waveform follows the gate voltage, the currentiA has finite rise and fall times which overlaps with the voltage waveform vA. Other factorswhich affect the shape of the waveforms are the threshold voltage of the device, nonlineartransconductance during the switching interval, and current saturation during the switchinginterval. These factors complicate the analysis of modified waveforms resulting from finiteswitching time and instead we investigate the effect of switching times qualitatively bylooking at simulated waveforms and dynamic I-V curves. A detailed analysis of overlap lossis not particularly useful in the CMOS circuit because, as will be shown, other resistive lossmechanisms are much more significant and limit power efficiency.As a way to investigate the effect of finite switching in class-E circuits, the switch inFig. 2.2(a) is modeled as a nonlinear transconductance that is extracted from the BSIM4device model in the CMOS Process Design Kit (PDK). All other components are assumed tobe ideal. The corresponding waveforms for a class-E amplifier and a rectifier dual are shownin Fig. 2.3. For these circuit simulations, the gate drive is a square wave with rise and falltimes of T/10 where T = 1/ fsw . The top row corresponds to the amplifier, while the bottomrow corresponds to the rectifier.Six points have been labeled in Fig. 2.3 to follow the evolution of one RF cycle over aninterval of [0, 2pi]. The RF cycle in the amplifier begins at point a which is defined as thestart of the rising edge of the gate drive signal shown in Fig. 2.3(a). As the gate voltage risesit eventually reaches the threshold voltage of the device at point b. The threshold voltage forthis CMOS device is approximately 0.4 V and the time it takes to reach threshold creates ashort period of time where the current through the switch is zero. This is seen in the draincurrent waveform in plot Fig. 2.3(b). The drain current has a small delay and then steps upto the saturation current. Above threshold, drain current flows through the switch. At pointc, the drain current peaks and current continues to flow until the switch turns off at point d.362.3. Class-E Synchronous RectifierThe falling edge of the gate waveform corresponds to the interval d-e and during this time thecurrent through the switch is chopped while the capacitor current starts to rise. By the endof the switching interval at point e, the capacitor carries all the current entering the switchsubnetwork. The zero crossing of the capacitor current is at point f and this corresponds topeak drain voltage. After point f , the drain voltage falls and the voltage transitions to zero atthe end of the RF cycle returning to point a.A dynamic I-V curve illustrating how the drain current and drain voltage change over anRF cycle is shown in Fig. 2.3(c). Power loss associated with the overlap of the drain currentand drain voltage as the switch turns off is evident by the contour d-e which sweeps acrossthe I-V plane. The power loss can be estimated by assuming the drain current and capacitorcurrent transition linearly over the interval d-e. The switching transition time is τs, the phaseat point d is θD , and the phase at point e is θE . Using these variables, the switch current isisw (θ) = i(θD)(1 − θ − θDτs)for θ ∈ [θD, θE ] (2.21)and the capacitor current isiC (θ) = i(θD)( θ − θDτs)for θ ∈ [θD, θE ]. (2.22)The corresponding drain voltage is found by integrating the capacitor current andvA(θ) =i(θD)2ωswCτs(θ − θD)2 for θ ∈ [θD, θE ]. (2.23)The corresponding power dissipated from the overlap of drain current and drain voltageduring the on to off transition interval isPov =12pi∫ θEθDisw (θ)vA(θ) dθ. (2.24)The switch current at θD is approximately equal to the ideal switch current for θ = pi.372.3. Class-E Synchronous RectifierTherefore, from equation (2.14) it follows that isw (pi) = isw (θD) = 2IDC . Using thisrelation, and equations (2.21), (2.23) and (2.24)Pov =I2DC τ2s12pi ωsw C. (2.25)2.3.3 Resistive LossesIn a CMOS implementation, the most significant loss mechanisms which reduce powerefficiency are dissipation in switch saturation resistance (rsat ), resistive losses (rDD) in thedrain inductor LDD , and resistive losses (rM ) in the output inductor, LM + LS . A class-Ecircuit model with these losses is shown in Fig. 2.4. Equations for these power losses arederived next.VDDCS LM + LSRL VLCVSLDDVGGLGGRS Cin M1IDCiCisw iLiA ArDD rmrsatFigure 2.4: Class-E amplifier with dissipative losses in the switch and the inductors.The switch has an average saturation resistance rsat during the on state. Over one RFcycle, the switch is on for half a period from [0, pi]. The corresponding power dissipation inrsat isPrsat =12pi∫ pi0i2A(θ) rsat dθ =rsat I2DC16(pi2 + 28). (2.26)382.3. Class-E Synchronous RectifierThe power loss in the drain inductor LDD isPrDD = rDD I2DC (2.27)and the power loss in the output inductor isPrm =12pi∫ 2pi0i2L (θ) rm dθ =I2om rm2. (2.28)Another way to express the loss from the resistance of the output inductor is to combineresistance rm with the load RL and then express the loss in terms of the dc supply power.Using this method,Prm = PDCrmrm + RL. (2.29)Equations (2.26) through (2.28) give expressions for the absolute power losses created byresistive losses. It is also useful to normalize these power losses to the total dc power (PDC) todetermine the relative significance of each specific lossmechanism. Using equation (2.17) forthe dc drain supply voltage, and rearranging (4.15) to obtain the relationωsw C = 0.1836/RL ,the dc supply power isPDC = VDD IDC =I2DC RL0.1836 pi. (2.30)Normalized power losses are then expressed as:PrsatPDC= 1.365rsatRL, (2.31)PrDDPDC= 0.5767rDDRL, (2.32)392.3. Class-E Synchronous RectifierandPrmPDC=rmRL + rm. (2.33)These equations are used in the next section to compare analytic results with simulationsresults.2.3.4 Class-E Amplifier Reference DesignA 2.4 GHz class-E amplifier was designed using components in the IBM CMRF8SF processdesign kit for 0.13 µmCMOS technology. The switch is an NMOS device and the device hasa maximum operating voltage of 3.3 V. A drain supply voltage (VDD) of 1 V is selected andprovides headroom for the peak voltage across the device [59, 60]. The NMOS switch has agate width of 360 µm and the device is sized to directly match to a 50 Ω load. The gate biasvoltage (VGG) for the switch is 500 mV and the bias is compatible with a 1 V peak-to-peakgate drive signal.Initial component values for the design were found using the ideal class-E design equa-tions in section (2.3.2). From the design equations, the switch capacitance C is 243.5 fF andthe phase shift inductance LM is 3.8 nH. The series resonator capacitance, CS , is 700 fF andhas a loaded Q of approximately 5. The Q needs to be sufficiently large to ensure the loadsignal is sinusoidal. The corresponding resonator inductor, LS , is 6.3 nH for operation at afundamental frequency of 2.4 GHz. The estimated dc current is 11.5 mA calculated fromequation (2.17) and the total dc power supplied to the drain is 11.5 mW.Although the ideal class-E amplifier design equations provide a good starting point, apractical CMOS amplifier requires further refinement in component values to compensate forloss. Factors which modify the ideal design equation values include finite switch resistance,finite inductor Q, trade-offs between area and inductance, and finite capacitor Q. These factorsreduce the power efficiency of the class-E design and a sequential design methodology isadopted to independently evaluate the effect of each non-ideal component.A summary of the design steps which were used to arrive at the final values for the CMOS402.3. Class-E Synchronous Rectifierclass-E amplifier design are summarized in Table 2.2. The table includes component values,simulation results and analytic results. For the simulation, the input signal to the amplifier isa 2.4 GHz square wave with a peak-to-peak amplitude of 1 V and a dc offset of 0.5 V.The first row in the table corresponds to the ideal class-E amplifier. The ideal amplifieruses a switch for the active device, and the switch has negligible on resistance (1 mΩ) andchanges state nearly instantaneously (trise = tf all = 0.024/T ). Since the output resonatorhas a Q of 5, the harmonic impedances at reference plane A (see Fig. 2.2(a)) are not infinite.Therefore, the ideal values do not lead to zero voltage switching and the values forC and LMare increased by approximately 18% to obtain ideal zero voltage switching. The readjustmentin component values leads to nearly ideal performance with a power efficiency of 99.5%.In row 2, the power loss associated with the output inductors, LS and LM , are evaluated.The final inductor used in the CMOS design is 14 nH (see row 6) and the Q of the inductoris 13.9 at a frequency of 2.4 GHz. Based on these values, the equivalent series resistance,rm, is 15 Ω. A series resistance is added to the ideal class-E amplifier as shown in Fig. 2.4to model the inductor loss. The class-E is then re-optimized to find the best values for C andLM with the addition of the inductor loss. The simulated power efficiency including rm is76.5% and this compares very closely to the analytic obtained using equation (2.33).In row 3, the on state switch resistance is changed from 1 mΩ (ideal) to rsat . For thisdesign, rsat is approximately 7.75Ω, and the switch loss reduces power efficiency by 21.6%.The analytic estimate for the power loss associated with rsat is 21.2%, very close to thesimulated value. The addition of rsat also changes the switching waveforms in the amplifier,and C and LM are re-optimized to maximize the power efficiency with the additional loss.In row 4, the overlap loss from finite switching times are evaluated. The switch model inrow 3 is used for the simulation. The results show that the additional power loss generatedby changing the gate waveform from instantaneous switching to a waveform with rise andfall times of T/10 has a very small effect on power efficiency — only 1% in this case.412.3.Class-ESynchronousRectifierTable 2.2: Simulation results for different class-E amplifier circuits# ConfigurationLDD(nH)LS(nH)LM(nH) C(fF)Pout(dBm)Pdc(dBm)PowerEff. %(Sim.)PowerEff. %(Model)QDD QS QM1 Ideal Components Choke 6.3 4.5 288 9.93 9.95 99.5 100∞ ∞ ∞2 Ideal Components Choke 12.8 230 6.97 8.12 76.5 76.9+ Finite Q Inductor: LM , LS ∞ 12.93 Ideal Components Choke 6.3 5 250 7.99 9.04 78.4 78.8+ NMOS switch model ∞ ∞ ∞4Ideal Components Choke 6.3 5 250 7.86 8.98 77.3 77.9+ NMOS switch model+ 10% of gate drive ∞ ∞ ∞5 Ideal Components 18.7 6.3 4 443 8.33 9.56 75.2 73+ Finite Q Inductor LDD 12 ∞ ∞6 PDK components 18.7 14 — 7 10.3 46.7 —+ NMOS switch (W=360 µm) 12 13.9422.3. Class-E Synchronous RectifierIn row 5, the power loss from the drain inductor is evaluated. In the final design (row6), a 18.7 nH inductor is used and the inductor has a Q of 12 at a frequency of 2.4 GHz.The inductor loss is modeled by rDD in Fig. 2.4. The simulated power efficiency with theaddition of rDD is 75.2% and the analytical estimate is 73% using equation (2.31).Conclusions from the loss study show that the contribution to power loss from rsat ,rm, and rDD are similar and result in power efficiencies that range from 75.2% to 78.4%.The study also shows that each impairment requires a re-optimization step to adjust theshunt capacitance C and the phase shift inductance LM to maximize power efficiency in thepresence of loss. Other conclusions are that it is difficult to predict the superposition of allthe losses, and the analytic results are most useful to evaluate the relative significant of aspecific loss.In row 6, results are shown for a complete simulation of the CMOS class-E amplifier. Thesimulation results were generated using Spectra RF and the PDK for the CMOS process. Thedesign includes all loss mechanisms which were evaluated independently, as well as otherimpairments including nonlinear device capacitances and models for the physical layout ofthe inductors. In the final design, the intrinsic device capacitance of the device is used forC and no additional discrete capacitance is added. The simulated power efficiency for thecomplete CMOS class-E amplifier design is 46.7%.The impedance of the output network at reference plane A is important and the simulationresults for the final output network design implemented with the CMOS PDK are shown inFig. 2.5. At the fundamental frequency, the real part of the impedance is close to 50Ω and thereactive part is 72 Ω. The reactive part is associated with the choice of LM . The harmonicimpedances should ideally be an open, and in this design the magnitude of the second andthird harmonic impedances are approximately 800 Ω. The harmonic impedances are morethan an order of magnitude larger than the fundamental harmonic impedance and provide agood compromise between theory and implementation constraints in CMOS.432.3. Class-E Synchronous Rectifier0.−j0.2+j0.5−j0.5+j1.0−j1.0+j2.0−j2.0+j5.0−j5.00.0 ∞2f03f0f0Figure 2.5: Impedance of the CMOS class-E amplifier load network: ZA( f ).2.3.5 Class-E Synchronous Rectifier DesignThe class-E rectifier circuit is developed from the class E amplifier by reversing the dc sourceand RF output nodes in the amplifier. A feedback path from the RF input to the gate is alsoadded to provide a gate drive signal. The class-E rectifier circuit is shown in Fig. 2.2(b).The effect of reversing the input and output nodes in the amplifier is that the drain voltageand drain current waveforms in the rectifier are time reversed compared to the amplifierwaveforms. In addition to time reversing the waveforms, the current through the switch inthe rectifier is flipped in terms of amplitude because there is a net dc current, I ′DC , flowingout of the drain inductor LDD into the dc load (see Fig. 2.2(b)). Examples of class-E rectifierwaveforms are shown in Fig. 2.3(d) and 2.3(e). The waveforms can be compared with theamplifier waveforms in Fig. 2.3(a) and 2.3(b), and the time-reversal is clearly evident.442.3. Class-E Synchronous Rectifier2.3.6 Overlap LossThe simulated class-E waveforms shown in Fig. 2.3 correspond to a class-E rectifier modelbased on the class-E amplifier model shown in row 4 of Table II. The switch is modeledas a nonlinear transconductance based on extracted characteristics from the CMOS BSIM4device model, and the gate drive signal is a 1 V square wave signal with rise and fall timesof T/10. For this simulation, the gate drive is provided from an external source similar tothe amplifier configuration and the circuit model can be directly compared with the amplifierdual. Although the shape of the amplifier waveforms in Fig. 2.3(a) and (b) are similar to thetime reversed rectifier waveforms in Fig. 2.3(c) and (d), there are differences caused by thedirection of current flow through the switch. In the amplifier, current flows into the drainwhen the switch is on; conversely, in the rectifier, current flows out of the drain when theswitch is on. Since the rectifier on state current flow is out of the drain, the device operatesin quadrant III, while the amplifier on state operates in quadrant I. The difference in theoperating states is clearly seen in the corresponding dynamic I-V plots shown in Fig. 2.3 (c)and (f).Another difference between the rectifier and amplifier duals is the phase reversal of thevoltage and current waveforms with respect to the switching instants in the gate signal. Inthe amplifier, the switch transition from off to on corresponds to interval a-b. During thisinterval, the drain voltage and drain current are low, ideally zero. On the other hand, in therectifier, the switch transition from off to on corresponds to interval d′-c′. During intervald′-c′, current transfers from the capacitor to the switch, and the current through the switchmust change from zero to nearly maximum current (point b′).The negative drain current also means the on state voltage drop is negative, and thecombination of high current and switch voltage leads to overlap loss. The overlap loss inthe rectifier is slightly higher than the amplifier. This is evident in both the drain currentand drain voltage waveforms where there is a small peak at point c′. The overlap loss isalso easily seen by examining the loop area in the dynamic I-V curve for the rectifier. This452.3. Class-E Synchronous Rectifieris shown in Fig. 2.6 and clearly the power loss associated with the rising edge of the gatewaveform (off to on state) is much larger than the falling edge (on to off state). Although theoverlap loss is slightly higher in the rectifier, the on state switch resistance is slightly lowerin quadrant III compared to quadrant I and the overall power efficiency of the amplifier andrectifier are very similar. For the simulation results in Fig. 2.3, the amplifier has an efficiencyof 77.3% and the rectifier has an efficiency of 78.8%. Therefore, the results show that thenet losses in the circuit duals are quite similar.- 1 0 1 2 3 4- 3 0- 2 5- 2 0- 1 5- 1 0- 5051 0e'c'b'a'f' R  i s e  t i m e  l o s s F a l l  t i m e  l o s sDrain current (mA)D r a i n  V o l t a g e  ( V )d'Figure 2.6: Dynamic I-V curve for the class-E rectifier. The gate drive is a square wave signal with10% rise and fall times.2.3.7 Gate Bias and Sinusoidal Drive SignalsThe class-E amplifier is designed assuming a switching signal is applied to the gate. Theswitched gate signal in the amplifier is generated by a driver stage, and in a practical design,the requirements for the gate drive can be established independently. In a self-poweredrectifier design, the gate drive must be derived from the sinusoidal RF input signal, and the462.3. Class-E Synchronous Rectifierinput signal affects both the design of the gate bias circuit and the phase shift network.The implementation of a bias circuit needs to consider both complexity and performance.Since CMOS devices have low threshold voltages, a zero bias scheme is used in this design,and the gate is tied to ground through a 5.6 nH bias inductor, Lb. Ideally, the device shouldbe biased near threshold, and therefore the trade-off using a zero bias scheme is a reductionin power efficiency especially for low amplitude input signals.The design of the phase shift network is considered next. The purpose of the phaseshift network is to create a gate drive signal that synchronously switches the device, and theimplication of converting the square wave drive signal in the amplifier into a sinusoidal gatedrive signal in the rectifier needs to be considered. If an equal amplitude sinewave is appliedto the gate instead of a square wave, the peak is delayed by T/4 relative to the rising edgeof the square wave, and the timing of on and off states in the device are shifted. Therefore,the optimum phase shift for a sinewave gate drive signal is not the same as for a square wavedrive signal.The change in gate phase required to synchronously switch the device was exploredthrough simulation. For the first set of simulations, the circuit model in row 4 of Table II wasused. In this model, the switch is modeled as a nonlinear transconductance and the modelincludes overlap and on state losses. Different gate drive signals with different phase shiftsrelative to the RF input signal were simulated and the conclusions are summarized by thedynamic I-V plots in Fig. 2.7. A benchmark for power efficiency was first established usinga square wave drive signal with a peak-to-peak amplitude of 1 V and a 0.5 V dc offset. Therise and fall times are approximately instantaneous and the power efficiency of the rectifier is82.1% for a phase shift of 120◦. The square wave drive was then replaced with an equivalentsinewave drive with a 1 V peak-to-peak amplitude and a 0.5 V dc offset. For a phase shift of120◦, the power efficiency is 51.4%, and if the phase of the sinewave drive is readjusted to28◦, power efficiency is improved significantly to 78.7% within a few percent of the powerefficiency for a square wave signal. The difference in phase between the square wave signal472.3. Class-E Synchronous Rectifierand sinewave signal is 92◦ confirming the change in phase delay is approximately T/4.Similar simulation experiments were run with the full CMOS design using post layoutmodels. A bridged tee phase network was designed to create a gate drive signal from the RFinput signal as shown in Fig. 2.2(b). After optimizing the post layout simulation for powerefficiency, the phase shift was readjusted to 89◦. The final design values for the phase shiftnetwork circuit elements are: Csample = 29.7 fF, LT1 = LT2 = 5.3 nH, CT = 1 pF, andCTP = 302 fF.The simulated power efficiency of the CMOS rectifier is 43% at 2.4 GHz with a +11 dBmsinusoidal RF input signal. This result can be compared with the simulation result for theclass-E amplifier dual shown earlier in Table II, row 6. The amplifier power efficiency is46.7% for a square wave gate drive signal. The difference in power efficiency between theamplifier with a square wave gate signal and the rectifier with a sinewave gate signal is 3.7%.-1 0 1 2 3 4-30-25-20-15-10-5051015202530 Square wave drive  Phase = 120o   RF-DC= 82.1% Sinewave drive       Phase = 120o   RF-DC= 51.4% Sinewave drive       Phase =   28o   hRF-DC= 78.7%Drain Current (mA)Drain Voltage (V)Figure 2.7: Dynamic I-V curves for the class-E rectifier for different gate drive signals and differentfeedback phase.Referring back to Fig. 2.7, a difference of 3.4% in power efficiency was obtained when482.3. Class-E Synchronous Rectifierthe gate drive signal in the rectifier was changed from a square wave to a sinewave. Therefore,the reduction in power efficiency from a square wave gate signal to a sinewave gate signal isrelatively small in this design providing the phase shift is optimized for the sinewave drive.2.3.8 Experimental ResultsA photograph of the CMOS class-E synchronous rectifier is shown in Fig. 2.8. The circuithas an area of 850 µm × 870 µm and the rectifier circuit was verified using using an EP6Cascade probe station with two coplanar waveguide probes.Figure 2.8: Microphotograph of the class-E synchronous rectifier.Since power efficiency is a key metric, it is very important to calibrate the available powerat the probe tips. A power meter was connected to a directional coupler which samples theinput signal to the probe station. The frequency response of the coupler and cable werethen measured to correct for frequency response errors between the probe tip and the powermeasurement point at the coupler. An Agilent Vector Network Analyzer (VNA) (N5241A)was used as a signal source and a full two port calibration at the probe tip plane was made.With this setup, the available input power at the probe tips was known and S11 measurementscould also be made.For this design, the input power range of the rectifier was within the power range of thenetwork analyzer and the input match (S11) of the circuit could be measured directly underlarge signal conditions. The measurements are shown in Fig. 2.9. As shown, the input492.3. Class-E Synchronous Rectifiermatch is centered at approximately 2.4 GHz and the return loss is greater than 10 dB over a200 MHz bandwidth. The input match is power sensitive which is expected since the gateamplitude changes with input power. As the results show, the match is best at high inputpower (12 dBm) and slowly starts to degrade as power is reduced. These results show thatat the design frequency input mismatch loss is small and the power efficiency is determinedprimarily by power losses in the circuit.2.0 2.2 2.4 2.6 2.8 3.0-20-18-16-14-12-10-8-6-4-2 Input power = 8 dBm Input power = 10 dBm Input power = 12 dBmS11 (dB)Frequency (GHz)Figure 2.9: S11 of the class-E synchronous rectifier for three different source powers.The phase shift network is critical in terms of optimizing power efficiency and insightinto the performance of the feedback network is obtained by measuring power efficiencyover frequency. The test results are shown in Fig. 2.10. As the measurements show, 32%peak efficiency is obtained around 2.3 GHz, 100 MHz below the design frequency. Themeasurements show that the feedback phase delay is slightly mistuned and better alignmentwith the input match would likely yield even better power efficiency than measured for thisdesign. However, for a first iteration of the design, the results are very encouraging and502.3. Class-E Synchronous Rectifierdemonstrate the potential of a class-E synchronous rectifier in CMOS.2.0 2.2 2.4 2.6 2.8 3.005101520253035 Input power = 8 dBm Input power = 10 dBm Input power = 12 dBmPower Efficiency (%)Frequency (GHz)Figure 2.10: Measured power efficiency as a function of frequency of the class-E synchronousrectifier.Other interesting measurement results include power efficiency at 2.4 GHz as a functionof dc load resistance RL (Fig. 2.11(a)) and power efficiency as a function of input power(Fig. 2.11(b)). In. Fig. 2.11(a), efficiency as a function of load resistance is shown andthe optimum load resistance is 225 Ω for an input power of 10 dBm. In Fig. 2.11(b), thepower efficiency of the rectifier as a function of available input RF power is shown. Themeasurements are made at 2.4 GHz with a load resistance of 250 Ω.As the data show, power efficiency peaks at 30% for an input power of 12 dBm, whilepower efficiency remains above 24% for a 10 dB dynamic range from 6 to 16 dBm. Full post-layout simulation results are also shown for the measurements in Fig. 2.11(a) and 2.11(b).The physical layout contributes significantly to the overall power efficiency of the CMOSdesign. Of particular note is the importance of modeling the gate resistance in the physical512.3. Class-E Synchronous Rectifierlayout as this can significantly affect the power efficiency of the rectifier.100 150 200 250 300 350 400222426283032 RF-dc Measurement RF-dc SimulationPower Efficiency (%)Load Resistance ( )0.500.650.800.951.101.25 Vout  Measurement Vout SimulationOutput Voltage (V)(a)0 3 6 9 12 15 180714212835Vout RF-dc Measurement RF-dc SimulationPower Efficiency (%)Input Power (dBm) Vout Measurement Vout SimulationOutput Voltage (V)(b)Figure 2.11: Power efficiency and output voltage as a function of: (a) load resistance of the class-E synchronous rectifier for an input power of 10 dBm, (b) available input power in the class-Esynchronous rectifier cross a 250 Ω load .522.4. Class-D Synchronous Rectifier2.4 Class-D Synchronous RectifierThe on-chip environment is challenging especially in terms of losses such as limited inductorQ. Therefore, to minimize inductor loss, an active switch and capacitor can be used insteadof the drain inductor which is used in class-E rectifiers as shown earlier in Fig. 2.2(a). If thedrain inductor in a class-E amplifier is replaced with a switch, the class-D circuit topologyis obtained. However, similar to the class-E rectifier circuit, the class-D rectifier circuit isdeveloped from the class-D amplifier by reversing the source and load nodes in the amplifier.2.4.1 Ideal Class-D Amplifier DesignA CMOS class-D switch-mode amplifier is shown in Fig. 2.12. The circuit has an nMOSswitch, M1, and a pMOS switch, M2, that are driven by a common gate signal. Since thedevices are complementary, under ideal switching conditions only one device is on and theswitching action generates a switched voltage signal vD (t) at node D. The switched voltagesignal is filtered by a series resonator (LS and CS) with sufficient selectivity to attenuateharmonics in vD (t) resulting in a sinusoidal load signal vL (t).RL VLVSVGGLGGRSCinZD(ω)M1iRLVDDM2iM1iM2CDS1CDS2LM CS LSSeriesResonatorCMMatchingNetworkDGIDDCdcFigure 2.12: Class-D amplifier circuit.Although the class-D amplifier is ideally operated as a switch-mode amplifier, the rectifierapplication has a sinusoidal input signal and the operation of the amplifier needs to beconsidered under sinusoidal drive conditions. Hence, when the amplitude of the input signal532.4. Class-D Synchronous Rectifieris below the threshold voltage of the nMOS device (VTh,n), the nMOS device is off and thepMOS device is on. Conversely, when the amplitude is large, the pMOS device is off andthe nMOS device is on. There is also a transition region where both the nMOS and pMOSdevices are on. When both devices are on, power is dissipated in both devices and this leadsto a power loss. The duration of time when both devices are on istD =1pi f[sin−1(VDD − |VTh,p |−VGGAm)− sin−1(VTh,n − VGGAm)]. (2.34)In this equation, f is the fundamental frequency, Am is amplitude of AC component ofthe gate voltage, and VGG is the DC gate bias voltage. Since the duration tD reduces powerefficiency, it should beminimized. The equation shows that oneway to achieve this is to selectthe supply voltage to be equal to the sum of the threshold voltages VTh,n + |VTh,p |. However,the disadvantage of operating in this condition is that device utilization is compromised if thesum of the threshold voltages is less than the maximum operating voltage of the transistor.The power delivered to the load isPout =2pi2V 2DD|ZD | (2.35)and load power depends on the supply voltage, VDD , and the drain load impedance, ZD (ω),at node D in Fig. 2.12. Therefore, equations (2.34) and (2.35) are design trade-offs.2.4.2 Feedback Network Design MethodologyThe class-D rectifier circuit is developed from the class-D amplifier by reversing the sourceand load nodes in the amplifier as shown in Fig. 2.13. An important difference between theamplifier and rectifier is the gate drive circuitry. In the rectifier, a self synchronized gatedrive circuit is implemented by adding feedback from the drain node D to the gate node G as542.4. Class-D Synchronous Rectifiershown in Fig. 2.13. The circuit includes device capacitances that are important in designingthe feedback network. The feedback network is a pi network. Working from the drain nodeto the gate node, the first element in the feedback network is a shunt capacitance equal toCDS1 +CDS2 +CM . The next element is a series inductor LPS . The third element is the totalgate capacitance equal to CGS1 +CGS2 shunted by 2(CGD1 +CGD2) where the factor of twoaccounts for the Miller effect on CGD . In the design, the phase shift inductor LPS is tunedto give the required feedback phase shift.CDS1CDS2LM CS LSVSRSSeriesResonatorCMIM2IM1CGS1CGS2RL CdcIDCVLM2M1MatchingNetworkCGDLPSG DFigure 2.13: Class-D synchronous rectifier circuit.The phase shift inductor LPS also provides a dc path from the drain to gate node. Inthis way, the gate is self-biased to the average dc value at the drain node. Although notnecessarily optimum, the gate biasing scheme provides a way to implement a completely selfpowered rectifier that works directly from the applied RF input signal.2.4.3 Simulation and Experimental ResultsA class-D self-synchronous rectifier for a frequency of 2.4 GHz was designed in 0.13 µmCMOS using IBM’s CMRF8SF design kit. CMOS devices with a 3.3 Vworking voltage wereused. For the rectifier design, the supply voltage is 1.65 V and the gate bias is 925 mV. Thegate widths for the nMOS and pMOS devices are 300 µm and 400 µm, respectively, and thegate width ratio is selected to equalize the saturation resistance of two devices. The optimum552.4. Class-D Synchronous Rectifierload impedance ZD (ω) at a frequency of 2.4 GHz for the device sizes and supply voltageis approximately 130 Ω. For this design, the matching inductor is 4.2 nH and the matchingcapacitor is 645 fF. In the circuit, the matching inductor LM and the resonator inductor LSare combined into a single inductor of 11.4 nH. The Q of the inductor is approximately 15.9at a frequency of 2.4 GHz. In the design, the phase shift inductor LPS is tuned to give therequired feedback phase shift; in this design, approximately 165 degrees at 2.4 GHz. Thefinal value of the phase shift inductor was 7.2 nH with a Q of 17.6.The rectifier circuit was verified using using an EP6 Cascade probe station with twocoplanar waveguide GSG Z-Probes. An Agilent Vector Network Analyzer (VNA) (N5241A)was used as a signal source and a full two port calibration at the probe tip plane was made.A photograph of the CMOS class-D rectifier design is shown in Fig. 2.14. The dimensionsof the die are 780 µm × 670 µm.Figure 2.14: Microphotograph of the class-D synchronous rectifier.In Fig. 2.15, the power efficiency of the rectifier is measured as function of frequency forthree different input powers with a load resistance of 340 Ω.For an input power of 10 dBm, a peak efficiency of 30% is measured at a frequency of2.4 GHz. In Fig. 2.16, power efficiency and output voltage are shown as a function of load.The measurements are made at a frequency of 2.4 GHz with a 10 dBm RF input signaland show that 330 Ω is the optimum load resistance. Measurement results for a range ofdifferent RF input power levels are summarized in Fig. 2.17.562.4. Class-D Synchronous Rectifier2 2.2 2.4 2.6 2.8 3Frequency (GHz)161820222426283032Power Efficiency (%)Input Power=8dBmInput Power=10dBmInput Power=12dBmFigure 2.15: Measured power efficiency as a function of frequency of the class-D synchronousrectifier.50 100 150 200 250 300 350 400 450 500Load Resistor ( )101520253035Power Efficiency (%) Voltage (V)Figure 2.16: Power efficiency and output voltage as a function of load resistance of the class-Dsynchronous rectifier..572.5. Transconductance Mode Rectifier2 4 6 8 10 12 14 16 18Input Power (dBm)21222324252627282930RF to dc Power Efficiency (%)RL=160 RL=220 RL=280 RL=341 RL=400 Figure 2.17: Measured power efficiency as a function of available input power of the class-Dsynchronous rectifier..The figure includes input power sweeps for different load resistances and shows how theoptimum load resistance changes as a function of input power. For a fixed load resistanceof 341 Ω, the rectifier efficiency is greater than 25% over a 10 dB dynamic range for inputpower ranging from 4 to 14 dBm. If the load resistance is adjusted to track input power, thenthe dynamic range can be extended.2.5 Transconductance Mode RectifierMost synchronous RF rectifier circuits are derived from time reversed circuit duals of switch-mode power amplifiers such as class-E. Although the class-E circuit has very high efficiency,the gate drive signal needs to have sufficient amplitude to switch the device. The switchingaction is usually obtained at peak power, and when the RF input power is reduced, powerefficiency is also reduced because the gate drive signal is insufficient to switch the device.Since the RF input signal is typically sinusoidal, it is difficult to create a switched gate582.5. Transconductance Mode Rectifiersignal in a synchronous rectifier, especially when operating the rectifier over a large RFdynamic power range. Therefore, as a way to extend the dynamic range of the synchronousrectifier, a third design based on a transconductance amplifier mode is investigated next.2.5.1 Design MethodologyTwo different synchronous rectifiers circuits are shown in Figs. 2.18(a) and 2.18(b). InFig. 2.18(a), a zero-threshold voltage NMOS device M1 is shunted by a positive thresholdNMOS deviceM2. The two devices are sized to provide a change in operatingmode as the RFinput power changes. When the RF input power is low, the gate signal is small. Under theseconditions, the zero-threshold device M1 operates in class-B and M2 is off. When the RFinput power is sufficiently large, the gate drive signal amplitude is large enough to start turningon M2 for a short duration near the peak of the RF signal. The current conduction anglethrough M2 therefore changes from cut-off to class-C as the RF input amplitude increases.In the second design shown in Fig. 2.18(b), a single transistor M1 is operated in class-C.The device has a positive threshold voltage and the current conduction angle depends on theRF input power applied to the rectifier. Since the device has a positive threshold voltage,there is a minimum RF input power where the device starts to conduct.The size of the two transistors in Fig. 2.18(a) are selected to match a specific dynamicrange of RF input signals. In this design, a 35 dB dynamic range from -30 dBm to +5 dBmis selected. The design is implemented in 0.13 µm CMOS technology and the gate widthof M1 is 112 µm and the gate width of M2 is 56 µm. Device M1 is a zero-voltage thresholddevice, while device M2 has a threshold voltage of 0.4 V.In the second design shown in Fig. 2.18(b), a single transistor M1 is operated in class-C. The device has a positive threshold voltage of 0.4 V and the current conduction angledepends on the RF input power applied to the rectifier. Since the device has a positivethreshold voltage, there is a minimum RF input power where the device starts to conduct.For this design, the device is sized to operate over a 20 dB dynamic range from -10 dBm to592.5. Transconductance Mode RectifierCSVLMNRSVSRL CdcIDCLDLGCGDCGSCDS M1C′GSM2 C′DSC′GD(a)CSVLMNRSVSRL CdcIDC LDLGCGDCGSCDS M1(b)Figure 2.18: Rectifier circuits: (a) a low power circuit consisting of a shunt configuration of a zero-voltage threshold device M1 and a positive threshold voltage device M2; (b) a high power rectifiercircuit operating in class-C.+10 dBm. The gate width of the device is 140 µm.As a way of verifying the operating modes in the rectifier, a spectral analysis of simulateddrain waveforms is used. In class-B and class-C, the drain voltage waveforms are sinusoidalwith a dc component and the amplitude of harmonic frequency components should be low.The relative magnitude of the different frequency components in the drain voltage wave-form is shown in Fig. 2.19. The dc and fundamental frequency components are dominantand the harmonic components are attenuated confirming the impedance characteristics of theload network.2.5.2 Layout ConstrainsOne of the important consideration in the circuit is determining the size of the dc output filtercapacitorCL . IdeallyCL should be made as large as possible and the size affects the ripple in602.5. Transconductance Mode Rectifier Drain voltage (High power)Amplitude (dB)Frequency (GHz)Figure 2.19: Relative amplitude of frequency components in the drain voltage signal for low powerrectifier at a power of 1 dBm and high power rectifier at a power of 10 dBmthe dc output load voltage. There are also constraints on the size of the capacitor which canbe implemented on-chip. In this design, a 400 pF dual layer MIM capacitor is implementedand the capacitor has an area of 151 µm by 670 µm.The two rectifier circuits in Fig. 2.18 were implemented on a single die and a picture ofthe fabricated design is shown in Fig. 2.20. The rectifiers operate at a frequency of 2.4 GHzand together they can rectify RF signals over a 45 dB dynamic range from -30 dBm to15 dBm.Post layout simulations which include circuit models for interconnects were used tooptimize the design. This is a critical step in the design process especially to ensure thephase shift network works properly to create synchronous rectification. For the low powerdesign in Fig. 2.18(a), the physical layout adds 20 fF to CGD , 110 fF to CDS and 50 fF toCGS , and for the high power rectifier, the layout adds 10 fF to CGD , 110 fF to CDS and 30 fFto CGS . Final values for the inductors are also determined from post layout simulations. Forthe low power circuit in Fig. 2.18(a), LD is 9.2 nH and LG is 7.2 nH. The Q of both inductorsis 17.6 at a frequency of 2.4 GHz. For the high power circuit in Fig. 2.18(b), LD is 11 nH,612.5. Transconductance Mode RectifierLG is 10.4 nH, and the Q of the inductors is 17.6. The drain inductor LD must also resonatewith the output capacitance at the drain node to ensure a low impedance path is provided forharmonic currents in the class-B and class-C modes.2.5.3 Experimental ResultsA photograph of the CMOS transconductance rectifier is shown in Fig. 2.20. The total areafor both the low power and the high power rectifiers are 900 µm by 500 µm including dcoutput lowpass filters.Figure 2.20: Microphotograph of the transconductance mode synchronous CMOS rectifier circuits.The CMOS rectifiers were tested on a microwave probe station using a GSGSG coplanarwaveguide probe. A full two port calibration was made by Agilent Vector Network Analyzer(VNA) (N5241A) for S-parameter measurements and a power calibration was made tocompensate for cable and probe losses. All power efficiency measurements reported aredefined asη =PdcPRF,in=Pdc(1 − |S11 |2)Pavs (2.36)where Pdc is the dc power delivered by the rectifier, Pin,RF is the RF power delivered tothe input of the rectifier, Pavs is the available RF source power, and 1 − |S11 |2 is the inputmismatch loss. Compensation for input mismatch loss is included because the design will622.5. Transconductance Mode Rectifieruse off chip matching including the series bond wire to complete the input match.-30 -25 -20 -15 -10 -5 0 5 10 1505101520253035404550556065 High power rectifier (measurement) High power rectifier (simulation) Low power rectifier (measurement) Low power rectifier (simulation)Power Efficiency (%)Input Power (dBm)Figure 2.21: Power efficiency versus input power for the CMOS rectifiers of the transconductancemode synchronous rectifier.The power efficiency characteristics of theCMOSclass-C rectifiers are shown in Fig. 2.21.As shown, the high power CMOS rectifier design has a device sized to operate over a 25 dBdynamic range from -10 dBm to 15 dBm, while the low power design operates over a 35 dBdynamic range from -30 dBm to +5 dBm. Post layout simulation results are also shownin the figure. The simulation and measurement results for the high power class-C rectifiertrack very closely over most of the dynamic range up to +10 dBm. For RF input powerlevels above +10 dBm, the transistor is overdriven, and the characteristics are similar to anamplifier operating in deep saturation. Simulation and measurements results for the lowpower rectifier are nearly identical for RF input power levels below -18 dBm, and above-18 dBm, the maximum error between simulated and experimental results is 5%.The load resistance RL has a significant impact on the power efficiency of the rectifier andtests were made to measure power efficiency as a function of load resistance. The results for632.6. Summarythe high power rectifier are shown in Fig. 2.22. The corresponding optimum load resistancesfor RF input power levels of -9.5 dBm, 1 dBm, and 8.5 dBm are 1.95 kΩ, 1.15 kΩ, and650 Ω, respectively.0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.005101520253035404550556065  Input power= 8.5 dBm  Input power= 1 dBm  Input power= -9.5 dBm  Power Efficiency (%)Output Load (k )Optimum LoadFigure 2.22: Efficiency characteristics of the high power CMOS rectifier as a function of loadresistance of the transconductance mode synchronous rectifier.The optimum load resistance therefore decreases as RF input power increases. Theresults also show that maximum power efficiency would be obtained with a tracking load toadjust the load resistance as RF input power varies over a large dynamic range.2.6 SummarySince most ultra-low power radios are implemented in CMOS, CMOS RF to dc rectifiercircuits are attractive to facilitate integration into a complete CMOS sensor. As a way tosystematically implement high-efficiency rectifier circuits, the theory of time-reversal dualityhas been used to exploit well known amplifier circuits that have high efficiency.642.6. SummaryTRD theory was used to implement four different synchronous rectifier designs and thesedesigns are summarized in Table 2.3. Initial designs focused on switch-mode operatingconditions in class-E and class-D. Good efficiency was obtained considering the limitationsof on-chip components available in the 0.13 µm IBMCMOS process. Although switch-modeoperation has high peak efficiency, the self synchronous design of the circuits is limited bya sinusoidal gate drive signal that is sampled from the RF input signal. The sinusoidal gatedrive signal can switch the transistors in the rectifier providing the amplitude of the gate drivesignal is high. When the RF input amplitude decreases, the switching condition becomescompromised and efficiency starts to decrease.As a way to improve the dynamic range of the synchronous rectifiers, two transconduc-tance mode circuits were implemented. These circuits can be described as duals of amplifierswhich operate in class-B and class-C. Experimental results show that the transconductancemode can significantly improve the dynamic range of the rectifier. Using this technique aclass-B rectifier was implemented that had a sensitivity as low as -30 dBm. It was also shownthat a very large dynamic range from -30 dBm to +15 dBm could be obtained by overlappingthe dynamic range of the class-B and class-C designs. Overall the four synchronous rectifierdesigns provide new benchmarks for circuits implemented in CMOS technology.Table 2.3: Summary of CMOS synchronous rectifier designs.Structure Frequency(GHz)Sensitivity(dBm)DynamicRange(dB)PeakEfficiency(%)AreaEfficiency(mm2)Class-E 2.4 0 18 30 0.74Class-D 2.4 -5 23 30 0.52Class-B 2.4 -30 35 40 0.2Class-C 2.4 -10 25 58 0.265Chapter 3Adjustable Load with Tracking33.1 IntroductionSimilar to the input RF match, the dc load impedance has a significant effect on the overallpower efficiency of the RF rectifier and there is an optimum load for a specific RF input powerthat maximizes the power efficiency of the rectifier. Therefore, the sensitivity of rectificationefficiency to dc load impedance is general and the requirement to select an appropriate dcload impedance has broad application.In this work, we pursue the idea of using a dc to dc converter as a way of implementing arobust load management circuit that provides the optimum load impedance to the RF rectifierover a range of RF input power conditions. The concept is shown in Fig. 3.1.The first stage is configured as a dc to dc converter, which operates in a DiscontinuousConduction Mode (DCM). The control for the DCM converter is steered by the measurementof current and voltage at the input of the converter. The control loop adjusts the duty cycle ofthe DCM converter to a condition that maximizes the power delivered by the rectifier. Sincethe control loop is designed to maximize load power, it can also track changes in RF inputpower.3Parts of Chapter 3 have been published as a journal paper and a conference paper:• S. Dehghani, S. Abbasian, and T. Johnson. “Adjustable load with tracking loop to improve RF rectifierefficiency under variable RF input power conditions," IEEE Trans. Microw. Theory Techn., 64(2):343-352, Feb 2016.• S. Dehghani, S. Abbasian, and T. Johnson, “Tracking load to opti- mize power efficiency in RF to DCrectifier circuits," in IEEE Wireless Power Transfer Conf., May 2015, pp. 1-3.663.1. IntroductionDCMAdjustableLoadDC / DCConverter LoadInputResistanceControllerOutputVoltageControllerFirst Stage Second StageVLVin , IinPower Management Circuit BlockVoutRF Rect_ifierRinRF InputPower(PRF)Load InputPower(Pin)DutyCycleControlDutyCycleControlFigure 3.1: RF rectifier with a power management circuit.Because the first stage converter is input regulated, the output voltage, Vout , in Fig. 3.1fluctuates depending on the RF input power to the rectifier. In order to create a regulatedsupply voltage (VL), a second stage is added. The second stage can be any classical boost/buckconverter circuit, and therefore we do not focus on the design of this stage. Instead, the focusin this work has been on the design of the first stage and integration with the RF rectifier.The challenge of designing adjustable loads that can maximize the power efficiency of asource is not unique to RF rectifiers, and other applications such as photovoltaic systems andwind power systems require similar types of load circuits. A review of these literatures showthat much of the research has focused on the implementation of software control algorithms,which are used to control the operation of dc to dc converters in order to obtain a maximumpower point tracking load characteristic [61–64]. Although a digital controller and softwarecan be used to steer the first stage DCM converter, other close-loop control methods are alsopossible including analog controllers.In this work, we significantly expand on the concept of using a DCM converter as away of implementing a tracking load circuit for a RF rectifier. A detailed analysis of theDCM converter is made and equations are derived to show how the load resistance changesas a function of duty cycle. Design equations are also derived for circuit elements. Anexperimental implementation of the load circuit was built and compared to analytic and673.2. Design and Analysis of the Adjustable Loadsimulated results.After verifying the adjustable load in an open-loop configuration, the design of an analogclose-loop control for automatically adjusting the load impedance is presented. The trackingload is then integrated with a 985 MHz GaN HEMT Class-F synchronous RF rectifier [30].Experimental results are shown to verify the operation of the tracking load as RF inputpower changes over a 13 dB dynamic range from 0.5 W to 11 W. The tracking circuit iscompared with the optimal load resistance as well as operation with a fixed load resistance.The measurements confirm a tracking load can significantly improve the power efficiency ofthe rectifier especially when the optimal load deviates significantly from a fixed load.3.2 Design and Analysis of the Adjustable LoadIn this section, the operation of the first stage dc to dc converter is analyzed to determine therelationship between the input resistance of the converter and the duty cycle of the converter.Once the relations between resistance and duty cycle are known, a controller can adjust thefirst stage converter to acquire and track the optimum load resistance for the rectifier.A simple boost converter model is used for analysis and is shown in Fig. 3.2. Theconverter consists of an input capacitor Cin and a series input inductor L, which is shuntedby a switch. When the switch is on, the circuit charges the inductor and the input voltageRLCoutL DRQ1 VoutiLPWMGeneratorIoutCinVSRSDC to DC Converter asthe Adjustable LoadVinIinRect_ifier ModelFigure 3.2: Schematic of the boost converter.Vin is applied across the inductor. The series diode DR prevents current from flowing backfrom the load into the closed switch. Therefore, during the on state, the load is effectively683.2. Design and Analysis of the Adjustable LoadCoutL DRVin VoutiL IoutCinIinRLFigure 3.3: The boost converter when the switch is closed (on state).CoutL DRVin VoutiL IoutCinIinRLFigure 3.4: The boost converter when the switch is open (off state).disconnected from the input as shown in Fig. 3.3. When the switch is off, the inductor currentiL (t) flows directly into the load circuit, which consists of a shunt RC circuit composed ofthe load resistance RL and a filter capacitor Cout . The off state equivalent circuit is shownin Fig. 3.4. Depending on the size of the inductor, the boost converter can operate either ina Continuous Conduction Mode (CCM) or a DCM. In the CCM configuration, the inductoris large enough to ensure that current through the inductor is always greater than zero. Inthe DCM configuration, the inductor size is smaller than in the CCM configuration, andthe inductor current is zero for a short interval each switching cycle. For integrated circuitdesigns where the inductor is on chip, the DCMmode is advantageous because inductor sizeis constrained. Since the focus here is on converters that can be integrated with RF to dcrectifiers, we proceed with an analysis of the DCM configuration.An example of a DCM inductor current waveform is shown in Fig. 3.5. The input currentis subdivided into three time intervals each specified by a duty cycle relative to the switchingperiod TS . The on state duration is ton = DTS where D is the duty cycle. The off stateduration is subdivided into two intervals: the first interval corresponds to the period thatinductor current is falling but non-zero; the second interval corresponds to the time where693.2. Design and Analysis of the Adjustable Loadinductor current is zero (discontinuous). The corresponding off state duty cycles are D2 andD3, respectively. Therefore tof f = (D2 + D3) TS .TSD2 × TsD× Ts∆ILiLIoutD3 × TsCurrentTimeFigure 3.5: DCM boost converter current waveform iL (t).3.2.1 Input ResistanceThe DCM boost converter is now analyzed to determine the relation between duty cycleD and the dc input resistance of the converter. Assuming the input capacitor is large, theharmonic components of iL (t) are shunted to ground and the input current to the converteris a dc current Iin. The input current is equal to the expected value of iL (t):Iin = 〈iL〉 = 1Ts∫ (D+D2)TS0iL dt =∆IL2(D + D2). (3.1)As shown in Fig. 3.5, the peak to peak amplitude swing of the inductor current is ∆IL .When the switch is on, the inductor is connected to ground and Vin is applied directly acrossthe inductor. The voltage across the inductor (Vin) is equal to L d iL/dt = L ∆ IL/(DTS).Therefore, these relations show∆IL =VinLDTS . (3.2)If the expression for ∆IL in (3.2) is substituted in (3.1), the input resistance to the DCM boost703.2. Design and Analysis of the Adjustable Loadconverter isRin =VinIin=2LD(D + D2)TS. (3.3)Equations are now derived to replace D2 with other fundamental design variables includingthe boost voltage ratio Av and the output load resistance RL .When the switch is open, during interval D2TS the inductor current is discharging intothe load. In this state, the inductor voltage is Vin − Vout which must equal L diL/dt =−L ∆ IL/(D2TS). Therefore a second expression for ∆IL for the interval D2TS is:∆IL =Vout − VinLD2 TS . (3.4)Since we have two equations for ∆IL , they can be equated to find an expression for the voltagegain of the DCM boost converter:Av =VoutVin=D + D2D2. (3.5)Equation (3.5) can also be arranged to find an expression for D2:D2 =DAv − 1 . (3.6)At the output terminals of the converter, the load resistance R is equal to Vout/Iout . Thedc output current is equal to the mean inductor current iL (t) over the discharge period D2 TS:Iout = 〈iL〉 = 1TS∫ (D+D2)TSDTSiL (t) dt =12∆IL D2. (3.7)If the expression for ∆IL in (3.2) is substituted in (3.7), thenIout =VoutRL=12Vin DTSLD2. (3.8)713.2. Design and Analysis of the Adjustable LoadRearranging this equation gives a second expression for the voltage gain of the DCM con-verter:Av =VoutVin=RL DTS2LD2. (3.9)We have two expressions for the DCM boost converter gain Av given by (3.5) and (3.9). Theequations can be combined to eliminate the variable D2, which then gives a third equationfor Av:Av =1 +√1 + 2 RL D2 TS/L2. (3.10)If the expression for D2 in equation (3.6) is substituted in equation (3.3), thenRin =2LD2TSAv − 1Av. (3.11)Together, equations (3.10) and (3.11) show how duty cycle D controls the input resistance ofthe first stage DCM converter.An analysis of a CCM boost converter is much simpler because D2 = D − 1. Forcompleteness, the CCM equations are:Av, CCM =1(1 − D) (3.12)Rin, CCM = (1 − D)2 RL (3.13)3.2.2 Inductor Size for DCMMode OperationThe previous analysis shows how the input resistance varies as a function of duty cycle. Theequations depend on the load resistance RL , the switching period TS , and the inductor valueL. For a design, the load and switching period are known, and L must be selected to operatethe boost converter in the DCM condition.723.2. Design and Analysis of the Adjustable LoadIn order to be in the DCM condition, the average input current of the boost convertershould be less than half of ∆IL , the peak of inductor current. Therefore,Iin <∆IL2. (3.14)By substituting (3.2) into (3.14) for ∆IL , the input current must satisfyIin ≤ Vin DTS2L . (3.15)From this relation, a bound on the maximum value of L is obtained:L ≤ Vin DTS2 Iin=12Rin DTS . (3.16)The corresponding input resistance at the boundary between the DCM and CCM condi-tions can be found from (3.13). The input resistance is (1−D)2 RL , which can be substitutedin (3.16) to getL ≤ 12(1 − D)2 DTS RL . (3.17)For the range of 0 < D < 1, the maximum of D(D − 1)2 occurs at D = 13 ; therefore,D (1 − D)2 ≤ 427(3.18)andL ≤ 227TS RL . (3.19)An inductor of approximately 13 max(L) was used for implementation.733.3. Analog Control Loop3.3 Analog Control LoopA control loop is required to adjust the duty cycle of the DCM load such that the impedancepresented to the RF rectifier is close to the optimal load resistance. There are different waysto implement the control loop ranging from digital control methods using a microcontrolleror Field Programmable Gate Array (FPGA) to analog control loops. In this work, we explorethe implementation of an analog control loop as an alternative to digital control loops. Twocontrol loops are discussed in the following sections. The first is a linear control loop, andthe second is a control loop with a charge pump and loop filter. The latter design is similarto circuits employed in phase lock loops.The purpose of the control loop is to adjust the duty cycle of the Pulse Width Modulation(PWM) converter such that the input resistance of the DCM converter is near the optimal dcload impedance for the RF rectifier. Under this condition, the power delivered to the DCMis maximized.3.3.1 Linear Control LoopA block diagram of the analog controller is shown in Fig. 3.6. The current and voltage atthe input of the DCM converter are measured. The power measurement block multiplies thevoltage and current to measure power, and an output voltage proportional to the input poweris generated. The voltage is amplified by a gain block, Km. The gain, Km, controls the loopgain and is a design variable. In the linear feedback loop, the output of gain block Km isconnected directly to the PWM block, and the voltage controls the duty cycle, and the dutycycle controls the input resistance of the DCM.In a linear control loop, a specific operating point is selected, and the duty cycle is variedlinearly around the operating point to track changes in input power. The operating point isdefined in terms of a load power Po, which corresponds to a PWM duty cycle of Do. If there743.3. Analog Control LoopRLCoutL DRQ1 VoutiL IoutCinVinIinFirst Stage DC to DC ConverterDriverKmGain StageVSRSRect_ifier ModelDelayLoopFilterIRecVRecPkPk−1PowerMeasure-mentComparatorCharge Pump BlockLinear pathVoltagetoPWMQ¯QclkDFigure 3.6: Analog control loop for the DCM converter.is to be no error at the operating point, then the loop gain must either satisfyPo Km = (1 − Do) (3.20)for a positive slope rectifier slope, orPo Km = Do (3.21)for a negative rectifier slope. The sign of the rectifier slope is defined as whether the loadresistance needs to increase as RF input power increases (a positive slope) or whether theload resistance needs to decrease as RF input power increases.Once the loop gain Km is determined to meet a specific operating point, the response ofthe control loop can be determined for other RF input power conditions. If the measured loadpower is Pm, then the corresponding duty cycle generated by the loop assuming a positiverectifier slope isD = 1 − Pm Km. (3.22)753.3. Analog Control LoopAn expression for the input resistance of the DCM converter as a function of the measuredpower for a linear control loop is found by substituting equation (3.22) into (3.11). The inputresistance isRin =2L(1 − Pm Km)2TS ×(1 − 21 +√1 + 2 RL (1 − Pm Km)2 TS/L). (3.23)These equations show that the gain Km not only determines the operating point for theloop, but it also determines how well the loop will track. If the gain response Km is differentfrom the combined gain response of all the other components in the loop, then a trackingerror will accumulate as soon as the measured power deviates from the operating point.The primary limitation of the linear loop is that the operating point determines the trackingperformance and there are not enough independent variables to set both the operating pointand the gain response. For these reasons, the linear control loop has a limited operating rangeand a better control loop is required to reduce tracking error.3.3.2 Control Loop with Charge PumpIf a charge pump is added to the analog control loop, significantly better dynamic range canbe obtained. An example of an analog control loop with a charge pump is shown in Fig. 3.6.Instead of directly connecting the output of the gain block Km to the PWM input, the signalis split into two paths. One path is delayed, while the other is not. By comparing the currentpower with the delayed power, the comparator generates an output pulse that is integrated bya loop filter to steer the control voltage of the PWM converter. A change in operating pointcorresponds to an average change in the PWM control voltage.The principle theory of the loop design is illustrated in Fig. 3.7. For a specific RF inputpower condition, there is an optimum dc load resistance that maximizes the power deliveredto the input of the DCM converter. If the load resistance were swept by sweeping the dutycycle of the converter, then a parabolic power contour would be generated with a unique763.3. Analog Control Loopmaximum that is marked as point ‘a’. Now consider a delayed version of this same contour.By comparing a sample of the delayed contour with the non-delayed version, a difference inpower is measured which can be used to determine which way the control voltage needs tochange to increase load power. During acquisition, the loop climbs up one side of the powercontour until the maximum power point ‘a’ is reached. The loop then continues to pass themaximum and steps to point ‘b’. At point ‘b’, the delayed power measurement Pk−1 is atpoint ‘c’ and exceeds point ‘b’. When Pk−1 > Pk , the comparator output changes sign andthe output of the D-flip flop switches polarity reversing the direction of the charge pump.Under steady conditions, the loop dithers back and forth between two points (‘a’ and ’c’),which creates an average load resistance (point ‘b’) that is near the optimum point.Load Resistance (R)τPdelay ≤P Pdelay ≥PPower (P)abc PdelayPFigure 3.7: Adaptation method employed in the analog controller.Once the steady state is reached, the average control voltage is Vb, which corresponds topoint ‘b’ in Fig. 3.7. With reference to Fig. 3.8, the control voltage fluctuates about Vb witha ripple of ∆V .The ripple is associated with the time constant of the loop filter, τLF , and the averageperiod of the comparator signal. If the comparator oscillates with an average period Tc, thenthe loop filter is charged and discharged by ∆V . The switching period of the comparatordetermines the duration of the charge and discharge times, and ∆V can be approximated by773.3. Analog Control Loopexpanding the exponential response of the loop filter with a Taylor series. Retaining only thelinear terms, and noting that the control voltage to the PWM is normalized to 1 V, then∆V ∝ Tc/2τLF. (3.24)The steady state fluctuation about the operating point provides approximately linear gaincontrol in the loop assuming the fluctuation ∆V is small. Therefore, the charge pump controlloop has a small signal response that is similar to the linear analog control loop with theadditional feature that the operating point can track changes in RF power. The simple linearloop can only be adjusted for a single operating point, hence it has a much smaller trackingrange. Equation (3.23), which shows how Rin varies in the linear control loop, can also beapplied to charge pump loop around a specific operating point providing Km is substitutedwith the equivalent loop gain in the charge pump.TimePWM VoltageVbt1t0 t2∆VFigure 3.8: PWM input voltage at steady state condition.As shown in equation (3.24), the charge pump ripple voltage (∆V ) depends on the averageperiod (Tc) of the comparator pulse train. The average period is in turn dependent on thedelay τ chosen to create a delayed power sample Pk−1. The value of the delay should havesufficient resolution for the comparator to accurately distinguish between the delayed poweredpower sample, Pk−1, and current power sample, Pk . The offset voltage of the comparator783.4. Experimental Resultsand the signal-to-noise ratio of the power measurement signals also need to be considered inselecting the delay to ensure the comparator is triggered reliably. On the other hand, a largeamount of delay leads to more error at the convergence point. Therefore, the final choice fordelay is a trade-off that determines the relative error between points ‘a‘ and ‘b’ in Fig. Circuit Implementation of the Analog Control LoopA detailed schematic of the analog controller that has been built is shown in Fig. 3.9. In thisdesign, a delay is implemented in the loop using a RC network consisting of a 1 kΩ resistorand a 100 nF capacitor. The output of the delay feeds the inverting input of the comparator(LT1018) and the non-delayed path feeds the non-inverting input. The time constant of thedelay network is 10 µs and the delay determines the displacement between the two powercontours shown in Fig. 3.7.The comparator has a 5V supply voltage and the output is a switching signal that oscillatesbetween 0 V and 5 V. The output is buffered through an inverter and then amplitude scaled bya resistive voltage divider to generate a 0-1 V control signal for the PWMconverter (LT6992).The pulse train is then filtered by a loop filter consisting of an equivalent 1.8 kΩ resistorand a 4.7 µF capacitor. The component values have been optimized experimentally basedon maximizing the tracking and acquisition range of the loop when tested with the class-Frectifier.3.4 Experimental ResultsAs a verification of the analysis of the DCM converter presented in the previous section, aDCM converter was designed and tested.The primary requirements for the DCM converter load are the input resistance range andthe load power. For the class-F synchronous rectifier described in [30], an input resistancerange of 14 Ω to 61 Ω is required, and the converter needs to handle at least 10 W of load793.4. Experimental ResultsVSRSM1LbGate DCPathPRF LDDRbCinPhaseShif_terTL10rTL9rTL8r(λo / 12)(λo / 8)TL7rTL6r(λo / 4)VGGTL5rTL4rTL3r(λo / 12)(λo / 8)TL2rTL1r(λo / 4)Harmonic GateMatching NetworkMult_iplierFreq. Set63 kΩVoltage to PWM IRecVRecVoutiLIout IinDC to DC Converter1ΩGain StagePower SensingMUR415470 µF3.3 µH4.7 µF150 Ω RFD14N05EL7104LTC6992AD6331 kΩ1 kΩ4 kΩ4.7 µFLoop Filter100 nF1 kΩ20 kΩ1 kΩLT1636DelayLT1018Decision StageLT1636LT1636Direct_ionalCoupler50 ΩDirect_ionalCoupler PinPower MeterClass F Rect_ifierHarmonic Drain Matching NetworkClass F AmplifierPSQ1Q¯Q clkD50 ΩFigure 3.9: A class-F synchronous rectifier with a tracking DCM load.power. A switching frequency of 600 kHz is used and the inductor value is calculated usingequation (3.19) for a load resistance of 149 Ω.The DCM converter load was first characterized in an open-loop configuration usinga power supply as a source and a resistive output load. From these measurements, theinput resistance was measured as a function of duty cycle for different input voltages. Withreference to Fig. 3.10, measurements of the input resistance are shown for a range of inputvoltages from 2 V to 18 V.803.4. Experimental ResultsDuty Cycle (%)Input Resistance (Ω)  10 15 20 25 30 35 40 45 50020406080100120Measurement for Vin= 2 V to 18 VAnalytical ModelSimulation Figure 3.10: Input resistance of the DCM boost converter versus duty cycle.For these measurements, the DCM output was connected to a 149 Ω resistor. Themeasurement results are compared with a simulation of the circuit as well as the analyticvalue found from evaluating equation (3.11). Experimental, simulation and analytic resultsare all very similar and verify the operation of the adjustable load. The results also show thatthe input resistance of the DCM converter can span nearly a decade range from 15 Ω to 95 Ωas the duty cycle changes from 50% to 5%.The power efficiency of the DCM converter was measured and the results are shown inFig. 3.11. The results show that power efficiency is relatively insensitive to input voltagechanges. For an input voltage range of 6-18 V, the power efficiency varies by no more than10% and the overall power efficiency remains above 78% (refer to the inset in Fig. 3.11).From these results, we conclude that the input resistance of the load is relatively constant anddoes not dependent significantly on the input voltage. This is consistent with the theoreticalanalysis presented in earlier where equation (3.11) shows that input resistance in the DCMcondition is not dependent on the absolute input voltage, only the relative voltage gain Av.Hence, input voltage changes affect the output voltage Vout , but not the input resistance.813.4. Experimental ResultsDuty Cycle (%)Power Efficiency of DC to DC Converter (%)  10 15 20 25 30 35 40 45 5002040608010010 20 30 40 5075808590  Vin= 2 V to 18 VVin = 6 VVin = 10 VVin = 14 VVin = 18 VFigure 3.11: Measured power efficiency of the DCM converter.After conducting experiments to verify the operation of the DCM load, the circuit wasintegrated with a 10 W GaN HEMT Class-F synchronous rectifier to evaluate the loadtracking performance in combination with a rectifier [30]. The test bench for measuring thepower efficiency of the rectifier is shown in Fig. 3.12.Three different tests were made to evaluate the performance of the load tracking circuitas a function of RF input power. For the first set of tests, the DCM load was run in anopen-loop mode where the duty cycle is controlled by an external source. Under open-loopconditions, the control voltage can be adjusted to maximize load power for each power leveland this determines the optimum load resistance for the rectifier. This corresponds to thebest power efficiency that can be delivered by the rectifier. The measured results for the opentest correspond to the solid blue line shown in Fig. 3.13.For the second set of tests, the analog control loop was used to automatically adjustthe duty cycle of the DCM load to maximize the power which could be delivered by theRF rectifier. The close-loop operation of the converter corresponds to dashed red line inFig. 3.13. As shown, the analog control loop closely follows the ideal open-loop responseover the entire RF input power range from 0.5 W (27 dBm) to 11 W (40.4 dBm).823.4. Experimental ResultsFigure 3.12: Class-F synchronous rectifier and adjustable load with tracking loop test bench.Input Power (dBm)Power Effieicny (%)  26 28 30 32 34 36 38 40 4201020304050607080Optimum loadClosed loopFixed load (50 Ω)Figure 3.13: The power efficiency of the rectifier versus RF input power for a tracking load and afixed load. The response for the optimum dc load is also shown.For the third test, the power efficiency of the RF rectifier was measured with a fixed 50Ωload. The load is close to the optimal resistance for high RF power levels but becomes lessoptimal for low RF power levels. The corresponding power efficiency of the rectifier overthe RF input power range is shown by the dash-dot trace in Fig. 3.13. As expected, a fixedload is a compromise and power efficiency is reduced compared to the tracking load circuit.833.4. Experimental ResultsThe tracking error in the analog loop is shown in Fig 3.14. The error shows howmuch thetracking loop deviates from the optimal load. As shown, the loop tracks very well over mostof the power range with a worst case error of 12% around 34 dBm. The plot also shows thecorresponding power efficiency error that results when a fixed load is used. The fixed loadprovides relatively good performance over a 6 dB range for RF power levels above 34 dBm;however, for power levels below 34 dBm, the error becomes increasingly large. Therefore,the tracking load has significant benefit especially as the dynamic range of the RF rectifier isexpanded.Input Power (dBm)Power Efficiency Error (%)  26 28 30 32 34 36 38 40 42−60−50−40−30−20−100Closed LoopFixed load (50 Ω)Figure 3.14: Close-loop tracking error as a function of RF input power. The power efficiency errorfor a fixed load resistance of 50 Ω is also shown for comparison.In this design, a load tracking circuit with a dynamic range of 13 dB has been achieved.As the dynamic range is expanded, the signal-to-noise ratio in the loop starts to limit theacquisition and tracking range of the loop. The amplitude of the power measurement signalsat the input of the comparator and the relative difference in the amplitude between the delayedand non-delayed signals are important. Hence, a loop that can track over a broader range willprobably require adjustable loop gain similar to an automatic gain control circuit. Anotherdesign constraint in terms of dynamic range is the operating range of the DCM converter.As shown in Fig. 3.10, the input resistance is a nonlinear function of duty cycle and the843.5. Summarybest operating range which offers good sensitivity ranges from about 5% to 50%. Over thisrange, the resistance changes by a ratio of about 10:1. If a larger range of load conditions isrequired, then the DCM would need to expand the resistance range.3.5 SummaryFor energy harvesting andwireless power applications it is important to optimize the completeRF rectifier system including the implementation of the rectifier and the load. The powerefficiency of an RF rectifier is load dependent and there is an optimal load resistance thatmaximizes efficiency. The concept of using a discontinuous mode dc to dc converter as anadjustable load circuit for RF rectifiers has been described. The effective load resistance isset by the duty cycle in the converter and the resistance is independent of the input voltage.A power measurement circuit and an analog control loop were added to the DCM converterto maintain an efficient load resistance as the RF input power to the rectifier changes.As a demonstration of the adjustable load and tracking loop, an experimental designof the load was implemented and tested with a 10 W GaN HEMT Class-F synchronousrectifier. The performance of the tracking load was compared to the optimal performance ofthe rectifier as well as with a fixed load. The tracking load provided good performance overa 13 dB dynamic range of RF input power, and the load performed substantially better thana fixed load especially at low RF power levels.85Chapter 4Bidirectional and ReconfigurableCircuit4.1 IntroductionIn this chapter, a bidirectional and reconfigurable circuit block that multiplexes between arectifier/receive mode and an oscillator/transmit mode is proposed. The application of thebidirectional circuit is linked to a new architecture for wireless sensors that can use Time-Division Duplexing (TDD) to cycle between RF energy harvesting periods and transmissionperiods for sensor data. One of the advantages of a TDD architecture shown in Fig. 4.1 is thatit eliminates the need for a front-end filter block that is required in FDD architectures thatuse different frequencies for receive and transmit modes. The reconfigurable circuit can alsoreduce chip area for the transmit oscillator and the RF energy harvesting circuit by exploitingcircuit duality between oscillator and synchronous rectifier circuits.4.2 Circuit Concepts and RequirementsAs a starting template for the proposed bidirectional circuit, different high-efficiency amplifiercircuits including class-D and class-Ewere initially considered. Class-E has the disadvantageof high-peak drain voltages that are typically more than three times the drain supply voltage.For low-voltage CMOS, voltage peaking significantly limits the oscillator output power.Class-D amplifier circuits can switch the full voltage of the drain supply without peaking;864.2. Circuit Concepts and RequirementsPower management&Energy storageTimeDuplexerBidirect_ional CircuitPower Oscillator /Rect_ifierSensorLNAmixerDecoderReceiverTX(f)RX(f)RF Energy HarvesterTransmit_terFigure 4.1: Sensor node using TDD with a bidirectional front-end reconfigurable for RF energyharvesting and transmission modes.however, the circuit has two switches and overlap loss, from the drain current and the drainvoltage waveforms during switching intervals, can be very significant at high frequencies. Asa compromise between class-D and class-E, class-DE amplifiers create dead-time intervalswhere both switches are off. During the dead-time interval, the continuity of load currentis maintained by a shunt drain capacitor similar to class-E circuits. For these reasons, theclass-DE topology was selected for this design.The proposed reconfigurable bidirectional class-DE structure is shown in Fig. 4.2. Inthe transmit mode, the circuit is configured as a power oscillator which can be modulated totransmit data. Configured as an oscillator, the circuit converts dc supply power to amodulatedcarrier and power flows from the supply to the antenna. Using TRD theory, power flow canalso be reversed to implement a synchronous rectifier. By integrating ‘Mode’ switches intothe circuit, the power flow can be controlled and the circuit can be configured either as apower oscillator or as a synchronous rectifier.As described earlier in Chapter 1, the 5.8 GHz ISM band is an attractive frequencyband for implementing RF energy harvesting technology, because in this frequency band874.2. Circuit Concepts and RequirementsClass-DEDevices LoadNetwork MatchingNetworkFeedbackNetworkVin , IinClass DE Power OscillatorClass DE AmplifierVout , IoutRF LoadRF SourceDC SourceDCLoadModeModeOscillator Power Flow; p(t) = v(t)× i(t)Rect_ifier Power Flow; −p(−t) = v(−t)×−i(−t)BiasCircuitsFeedbackControllerFigure 4.2: Reconfigurable power oscillator and synchronous rectifier with reversible power flow.the maximum EIRP for a radiating device such as a wireless basestation is 53 dBm. Thesensitivity requirements for RF input power are therefore similar to the other CMOS designsdescribed in Chapter 2. However, the challenge in the reconfigurable circuit is to maintainhigh-power efficiency both in a rectification mode as well as a power oscillator mode.Many novel CMOS oscillator designs can be found in the literature, but the focus of muchof this work is on the implementation of bidirectional designs. In this work, the primarydesign objective was to focus on power conversion efficiency and implement a high-efficiencyCMOS power oscillator that can be directly modulated and used for sensing applications.As in previous chapters, TRD provides a framework for designing the synchronousrectifier and oscillator circuit. However, as will be shown, a practical implementation ofthe circuit does exhibit challenges that include differences in loop phase and differencesin bias conditions. The oscillator has additional requirements including transient start-up conditions. Therefore, the oscillator design has both transient and steady state designconsiderations, while the synchronous rectifier is primarily designed based on large signalsteady state conditions. A 65 nm CMOS process was selected for the design and the goalwas to implement a design with a peak power conversion efficiencies of at least 50% at 5.8884.3. Class-DE Power AmplifierGHz in both mode of operations.In the following sections, we begin with the analysis of a class-DE amplifier. Afterdesigning the amplifier, the circuit is reconfigured into a power oscillator by adding feedbackto the circuit. The conversion from an amplifier to an oscillator also converts the three portamplifier network (RF input, RF output, and dc) into a two port oscillator network (RF outputand dc). After designing a power oscillator, TRD is used to reverse power flow and convertthe oscillator into a synchronous rectifier. Differences in the circuit bias and loop phaseare for the two circuit modes (oscillator and rectifier) are analyzed to implement a robustbidirectional circuit block.4.3 Class-DE Power AmplifierAclass-DE amplifier circuit is shown in Fig. 4.3. General equations for the class-DE amplifierare developed first, then a simplified analysis of the ideal class-DE amplifier is presented.The ideal equations provide insight into the key variables which determine the optimum loadimpedance and the source power requirements in terms of current and voltage.4.3.1 General Class-DE Amplifier RelationsIn the circuit, switches M1 and M2 are shunted by a capacitance C1 and C2, respectively.The switch closes with a frequency of fsw , also called the fundamental switching frequency.These switches and capacitor are combined into a subnetwork indicated by the dashed box.At the output node labeled A there are three currents that must satisfy KCL:iA1 − iA2 = iL . (4.1)We now consider the different frequency components which make up the currents at nodeA. The series resonator (LS and CS) has sufficiently high Q at fsw to ensure the load current,iL , is sinusoidal. Therefore, a harmonic balance analysis of currents at node A shows that894.3. Class-DE Power Amplifierthe harmonic frequency components in the currents iA1 and iA2 must sum to zero and onlythe fundamental frequency component flows to the load.RLVS2iLLMCS LSSeriesResonator Phase Shif_tInductorM2 C2M1 C1iA1iA2isw1isw2iC1iC2VS1VLAVDD CdcFigure 4.3: Class-DE power amplifier circuit with intrinsic switches’ capacitors.Inside the switch subnetworks, the current iA1 and iA2 are split between the switch currents(isw1 and isw2) and the capacitor currents (iC1 and iC2). Therefore,iA1 = isw1 + iC1 (4.2a)iA2 = isw2 + iC2 (4.2b)The switches states are controlled by the input gate signals VS1 and VS2 . There is animportant assumption that the two switches are not on at the same time. When the switchM1 is on and M2 is off, the load current iL flows through M1. Conversely, when M1 is offand M2 is on, the load current iL flows through the M2. In class-DE there are also dead-timeintervals when both switches are open and during these intervals, the current flows throughcapacitances C1 and C2.Since both switch capacitances C1 and C2 shunt node A in the class-DE circuit, they canbe combined into a single capacitance to simplify the circuit model. The simplified model904.3. Class-DE Power Amplifieris shown in Fig. 4.4 where the total capacitance at node A is modelled by a capacitance C.The voltage waveform at node A, vA , is directly linked to the shape of the capacitor currentwaveform, iC . The relation is given byvA(t) =1C∫ t0iC (t) dt. (4.3)Since the capacitor current has harmonic frequency components, the voltage waveformat node A also has harmonic frequency components. At this point, it is important to notethat the only assumption made in these equations is that the gate drive signals are non-overlapping. Therefore, the equations are valid for both instantaneous switching as well asfor finite switching times.VS2LMCS LSSeriesResonator Phase Shif_tInductorM2isw1isw2VS1RLiLCiCM1VLAVDD Cdc ZAoptFigure 4.4: Class-DE amplifier circuit with single shunt capacitor.4.3.2 Ideal Class-DE Amplifier Design EquationsThe ideal class-DE amplifier design equations are summarized next. Although idealized,these equations provide a good starting point for initial component values used in the designand they provide insight into the basic concepts that determine the operating conditions ofthe circuit.The following assumptions are made for the ideal analysis of the class-DE amplifiercircuit shown in Fig. 4.4:914.3. Class-DE Power Amplifier1. All signals in the amplifier are periodic and in the steady state.2. The output resonator has sufficiently high Q that the current through the output res-onator (LS and CS) and the load resistance (RL) are sinusoidal at the operating fre-quency, fsw .3. The active devices, M1 and M2, are modelled as ideal switches.4. Losses in inductors and capacitors are neglected.Since the signals are periodic, it is convenient to work with the instantaneous phase ofsignals rather than time. The instantaneous phase is defined as θ = ωswt = 2pi fswt. The gatedrive signals have a duty cycle D and, over a 2pi interval, the gate waveforms do not overlap.The 2pi switching period is partitioned into four intervals corresponding to differentswitch states.Interval [0, θ0]: The first dead-time interval when both switches are off.Interval [θ0, pi]: Switch M1 is on and switch M2 is off. The duration of this intervalcorresponds to the duty cycle of gate drive signal for M1.Interval [pi, pi + θ0]: The second dead-time interval when both switches are off.Interval [pi + θ0, 2pi]: Switch M1 is off and switch M2 is on. The duration of thisinterval corresponds to the duty cycle of gate drive signal for M2.In the ideal class-DE amplifier, the output load current iL is sinusoidal and defined asiL (θ) = Iom sin(θ − ϕ) for θ ∈ [0, 2pi] (4.4)where Iom is the peak amplitude of the load current. The load current has phase shift ϕ withrespect to the gate signal. The relative phase shift ϕ is determined by the duty cycle of thegate drive signals.924.3. Class-DE Power AmplifierVoltage at node A for the first dead-time interval [0, θ0] when both switches are open:An expression for the switched voltage signal at node A can be found using equation (4.3).When both switches are open, the capacitor current iC is equal to −iL and the shunt capacitorC is charged by a negative going iL . During this interval, the voltage at node A increasesfrom 0 V to VDD; therefore, the voltage at node A for the interval θ ∈ [0, θ0] isvA(θ) =12pi fswC∫ θ0−iL (θ ′) dθ ′=Iom2pi fswC[cos(θ − ϕ) − cos ϕ] (4.5)For an ideal class-DE amplifier, zero derivative switching is considered as a key factor.This condition forces the load current to be zero at the switching time, iL (θ0) = 0. Hence,M1 is switched when θ0 = ϕ and vA(θ0) = VDD . By applying the zero voltage switchingcondition across the switch in (4.5) and solving for Iom we getIom =2pi fswCVDD1 − cos ϕ (4.6)Substituting (4.6) into (4.5) then yieldsvA(θ) = VDD[cos(θ − ϕ) − cos ϕ1 − cos ϕ](4.7)Voltage at node A for the interval [θ0, pi] when M1 is closed and M2 is opened: For thetime interval [θ0, pi], switch current isw1 is equal to iL and the voltage at node A remainsconstant and is equal to VDD .Voltage at node A for the second dead-time interval [pi, pi + θ0] when both switches areopen: During the second dead-time interval [pi, pi + θ0], the capacitor current iC is equalto iL and the shunt capacitor C is discharged by a positive flowing load current iL . During934.3. Class-DE Power Amplifierthis interval the voltage at node A falls from VDD to 0 V . Therefore, over the intervalθ ∈ [pi, pi + θ0]vA(θ) = VDD[cos(θ − ϕ) + 11 − cos ϕ](4.8)Voltage at node A for the interval [pi + θ0, 2pi] when M1 is open and M2 is closed: Forthe interval [pi + θ0, 2pi], the current isw2 is equal to negative iL and the voltage at node Aremains constant and is equal to 0.Based on the preceding analysis, we see that the voltage at node A is switched betweenground and VDD with two dead-time intervals where the voltage transitions between the twoamplitude levels. An example of the switched voltage waveform is shown Fig. 4.5(a) wherethe trace labelled as ‘drain’ corresponds to the voltage at node A.A more accurate analysis of the voltage at node A would include losses in the switchesand the simulation results shown in Fig. 4.5(a) include switch losses. The switch in Fig. 4.4is modeled as a nonlinear transconductance that is extracted from the BSIM4 device modelin the CMOS PDK. All other components are assumed to be ideal. As shown, the switchloss is resistive and the on and off state waveforms are modified by the switch voltage dropcreated by the sinusoidal load current.Expressions for the required capacitance C at node A, the phase shift inductor LM andthe optimum load resistance RL are derived next for the ideal class-DE amplifier. Let thefundamental frequency component of the current iL be represented by phasor IL1 and thefundamental component of vA be represented by the phasor VA1 . The phasors are written as:VA1 =1pi∫ 2pi0vA(θ ′)e(−j (θ′−ϕ)) dθ ′=VDD2pi(1 − cos ϕ)[2ϕ − sin 2ϕ − j (1 − cos 2ϕ)](4.9)944.3. Class-DE Power AmplifierandIL1 =1pi∫ 2pi0iL (θ ′)e(−j (θ′−ϕ)) dθ ′=− jωCVDD1 − cos ϕ . (4.10)At nodeA inFig. 4.4, the effective impedance seen looking towards the load is ZAopt (ω) =VA/IL = RA + jXA. At the fundamental frequency, fsw , the resistance isRA1 =1 − cos 2ϕ2piωC(4.11)and the reactance isXA1 =2ϕ − sin 2ϕ2piωC. (4.12)At harmonic frequencies (ω , ωsw) the impedance ZAopt is ideally open; however, in apractical circuit the loaded Q of the output network is finite and the impact of finite harmonicimpedance needs to be considered. From equations (4.11) and (4.12), the real and imaginaryparts can be used to find expressions for C and LM :C =1 − cos 2ϕ2piωsw RL(4.13)andLM =RL (2ϕ − sin 2ϕ)ωsw (1 − cos 2ϕ) . (4.14)An expression for the optimum load resistance, RL , can be found using equations (4.6)954.3. Class-DE Power Amplifierand (4.11):RL =12Pout(1 − cos 2ϕ1 − cos ϕ)2 (VDD2pi)2. (4.15)For the ideal class-DE amplifier, there is no overlap loss from the voltage and currentwaveforms in the switch and consequently the ideal drain efficiency is 100%. This impliesthat the dc power and the fundamental frequency output power delivered to the load are equal.Therefore,IDCVDD = RL I2om/2. (4.16)Later, in the synchronous rectifier, it is useful to estimate the optimum load resistancewhich can be found from the Thevenin equivalent resistance of the dc supply (VDD). Usingequations (4.6) and (4.13) and substituting into (4.16), the equivalent resistance of the dcsource isRin,dc = 8pi2RL( 1 − cos ϕ1 − cos 2ϕ)2. (4.17)The ideal class-DE equations are used to implement a first pass design of the amplifier.In TSMC 65 nm CMOS technology, the nominal drain-source voltage is 1 V for standard RFtransistors. Therefore, in a class-DE amplifier that consists of two transistors, the nominalsupply voltage, VDD , is selected to be 2 V. The gate drive signals are assumed to be non-overlapping with finite rise and fall times equal to T/20 and a duty cycle of 25% where T isdefined as the switching period. With this gate drive signal, the corresponding phase delay(ϕ) between the gate drive and load current is pi/2. Using these conditions, the analyticalvalues for the class-DE amplifier are summarized in Table 4.1.964.3.Class-DEPowerAmplifier- /20/2 3 /2 2 5 /2 3 7 /2-1.0- (V)- /20/2 3 /2 2 5 /2 3 7 /2-18-13-8-3281318 NMOS Drain    PMOS Drain    Capacitor NMOS Drain    PMOS Drain    CapacitorCurrent (mA)-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5-18-13-8-3281318Quadrant IVQuadrant IIQuadrant IIIQuadrant IQuadrant IIIQuadrant IIQuadrant IV Dynamic I-V of NMOS    Dynamic I-V of PMOSDrain Current (mA)Drain Voltage (V)Quadrant I- /20/2 3 /2 2 5 /2 3 7 /2-1.0- NMOS Gate   PMOS Gate   Drain   RF Input NMOS Gate   PMOS Gate   Drain   RF OutputVoltage (V)- /20/2 3 /2 2 5 /2 3 7 /2-18-13-8-3281318Current (mA)-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5-18-13-8-3281318 Dynamic I-V of NMOS    Dynamic I-V of PMOSDrain Current (mA)Drain Voltage (V) (a)Figure 4.5: Waveforms for the class-DE amplifier circuit in Fig. 2 (top row): (a) drain voltage, output voltage and gate voltages for theswitches M1 and M2, (b) drain currents through the switches M1 and M2 and current through the shunt capacitor C, (c) dynamic I-V curvefor the switches. Waveforms for the class-DE rectifier dual (bottom row): (d) drain voltage, output voltage and gate voltages for the switchesM1 and M2, (e) drain current through the switches M1 and M2 and current through the shunt capacitor C, (f) dynamic I-V curve for theswitch. The non-overlap gate drive signals have rise and fall times equal to T/20 and the duty cycle of 25% for both the class-DE amplifierand class-DE rectifier.974.4. Class-DE Power OscillatorThe table also includes a comparison of the analytic values with an optimized circuitusing the full BSIM4 transistors model in the TSMC 65 nm CMOS PDK. The transistorsizes are selected such that the intrinsic device capacitances in M1 and M2 sum to implementthe required value of the shunt capacitance C. Based on extracted capacitances, the NMOStransistor has a width of 35.2 µm and the PMOS transistor has a width of 70.4 µm. Aminimum gate length of 60 nm is used for both transistors. The waveforms shown in Fig. 4.5are based on a simplified device model for the transistors that models the dc IV characteristicsof the transistors and a lumped equivalent capacitance C to model the device capacitances.Table 4.1: Comparison of analytic and optimized (simulation) component values for the class-DEamplifier circuit.Analyize Lm (nH) C (fF) Pout (dBm) Rin (Ω) Efficiency (%)Analytic(Ideal Switches) 2.15 174 6.07 986.9 100Simulation(BSIM4 Models) 2 150 6.23 859.5 90.24.4 Class-DE Power OscillatorIn this section, a feedback loop is added to the class-DE amplifier to implement a poweroscillator. The feedback path samples the output RF signal and provides positive feedbackto drive the gates of the two switches in the class-DE circuit. Basic requirements for thefeedback loop are given by the Barkhausen criteria. The synthesis of the required feedbackloop tomeet both start-up and steady state conditions is the primary implementation challengeand a detailed description of the methodology used to synthesize the loop is described.4.4.1 Barkhausen CriteriaThe oscillator can be implemented by a positive feedback loop that consists of a forwardtransfer function H (s) and a feedback transfer function F (s) as shown in Fig. 4.6.984.4. Class-DE Power OscillatorH(s) Vout(s)Vin(s)F(s)Figure 4.6: Positive feedback system for implementing an oscillator.The positive feedback loop creates an inherently unstable starting condition that enablesa small signal (noise) to grow in amplitude and eventually limit cycle at a periodic frequency( fos) determined by the loop-gain transfer function, L( f ) = H ( f )×F ( f ). The requirementsfor the loop-gain and phase are given by the well known Barkhausen Criteria:|L( fos) |≥ 1 (4.18a)∠L( fos) = 2npi (for n ∈ N) (4.18b)∂∂ω∠L( f ) f= fos ≤ 0. (4.18c)The Barkhausen criteria shows that in order for the oscillator to start, the loop-gain mustbe greater than one and the net phase shift around the loop must be 2npi (n ∈ N) degreescorresponding to positive feedback. After a transient start-up period, the oscillator reachesa steady state amplitude which is determined by nonlinear device characteristics, and theeffective loop-gain tends to unity with a net phase shift equal to the phase shift of one ormore periods of the oscillating frequency.The requirement that the derivative of the phase is negative at the oscillation frequency asshown in (4.18c) is essential and ensures that small fluctuations in frequency create a stableoutput frequency for the oscillator. When the instantaneous frequency drops below the steadystate frequency, the phase of the loop increases and consequently the phase grows for every994.4. Class-DE Power Oscillatortrip around the loop. The phase accumulation increases the instantaneous frequency andrestores the loop to the steady state oscillation frequency. Similarly, when the instantaneousfrequency is higher than the steady state oscillation frequency, the loop phase decreases, andthe round trip action of the loop acts to restore the loop to its steady state frequency. If thederivative of the loop phase at the oscillating frequency were positive, then a small frequencyfluctuation would drive the loop away from the steady state oscillating frequency. Therefore,(4.18c) is a necessary condition for oscillation.4.4.2 Synthesis of the Feedback NetworkAfter the optimization of the class-DE amplifier has been accomplished, the synthesis of thefeedback network F (s) is an important step in the oscillator design. In order to synthesize thefeedback network, reference planes in amplifier circuit (dashed lines in Fig. 4.7) are selectedto determine the required voltages and currents to satisfy oscillation conditions.vinLMCS LSSeriesResonator Phase Shif_tInductorM2 RLCM1A ioutvoutiinTLOutput Ref.PlaneInput Ref. PlaneVDD CdcFigure 4.7: Schematic of class-DE amplifier with a sinusoidal drive. The input-frequency is set to theoscillation frequency and a transmission line (TL) is used to create a phase delay for synchronizingthe gate drive for M1 and M2. Dashed lines represent the reference planes for the feedback loopsynthesis.For the analysis, the gate drive signal is assumed to be sinusoidal with a frequency equal tothe oscillation frequency. In addition, a transmission line (TL) is used tomake the appropriatephase difference for switching M1 and M2. In order to facilitate the synthesis of the feedback1004.4. Class-DE Power Oscillatornetwork and assure that voltage and current at the output reference plane are sinusoidal atthe oscillating frequency, the series resonator, composed of LS andCS , is included inside theforward path transfer function H (s). Therefore, the synthesis of the feedback loop transferfunction need only consider the loop response at the oscillation frequency.Conceptually, the feedback circuit can be implemented either as a T-network, a Π-network, or combination of these two types. In this work, a Π-network is chosen as a startingpoint for equations to create an appropriate feedback from output reference plane of theclass-DE power amplifier to the input reference plane.vinCS LSSeriesResonatorM2 CM1A ioutvoutiinTLOutput Ref.PlaneInput Ref.PlanejBΠ2jBΠ3 jBΠ1Feedback Network; F(s)Forward Network; H(s)VDD CdcGΠFigure 4.8: The class-DE oscillator circuit which adds a feedback loop F (s) to the class-DE amplifiercircuit in Fig. 4.7. The input and output reference planes for the feedback loop are shownThe feedback network in Fig. 4.8 consists of three reactive elements ( jB1, jB2 and jB3)and one resistive element (G1) representing the amplifier load resistance. For this network,1014.4. Class-DE Power Oscillatorthe two-port Y -parameters relating the terminal currents Iin, Iout and voltages Vin, Vout are:IinIout =j (BΠ2 + BΠ3) − jBΠ2− jBΠ2 GΠ + j (BΠ1 + BΠ2)VinVout . (4.19)The Y -parameter matrix equation has four unknown parameters (BΠ1, BΠ2, BΠ3 andGΠ)which must be found. Since the equations are complex, and the network must satisfy bothamplitude and phase constraints, there are two complex equations which can be solved forfour real variables. The element values are found by imposing a condition on the relativephase difference between Vin and Vout and ensuring the output voltage is not trivial (zero)[65]. The four element values expressed in terms of the terminal voltages and currents are[66]:BΠ2BΠ3 =Im(Vout ) − Im(Vin) − Im(Vin)Re(Vin) − Re(Vout ) Re(Vin)−1×Re(Iin)Im(Iin) (4.20a)GΠBΠ1 =Re(Vout ) − Im(Vout )Im(Vout ) Re(Vout )−1×Re(Iin + Iout ) + BΠ3 Im(Vin)Im(Iin + Iout ) − BΠ3 Re(Vin) . (4.20b)The required current and voltages at the terminal planes of the feedback network arefound from the simulation of the optimized class-DE amplifier. These values are shownin Table 4.2. The component values for the feedback network can then be calculated from(4.20). The element values for the Π feedback network are summarized in Table 4.3. As canbe seen, the network susceptances and conductance can be implemented with three inductorscorresponding to BΠ1, BΠ2 and BΠ3, and a resistive load RΠ corresponding to GΠ.1024.4. Class-DE Power OscillatorTable 4.2: Terminal voltages and currents required at the class-DE amplifier reference planes.Vin (V) Iin (mA) Vout (V) Iout (mA)2 ∠ 0 9.74 ∠ -90.3 0.95 ∠ 169.9 10.94 ∠ 115.1Table 4.3: Feedback network element values.Element GΠ XΠ1 XΠ2 XΠ3Evaluated 6.5 mS -8.4 mS -0.3 mS -4.4 mSCircuit RΠ LΠ1 LΠ2 LΠ3Value 153.7 Ω 3.25 nH 86.2 nH 6.22 nHAs shown in Table 4.3, the load impedance RΠ is 153.7 Ω, and to implement a practicaldesign that can be tested, the impedance needs to be transformed to 50 Ω. Therefore amatching circuit is required to implement the impedance transformation. The matchingcircuit can be implemented either on-chip or off-chip and trade-offs include insertion lossand size. Although on-chip matching is more compact, the losses in on-chip inductors arequite substantial. On the other hand, off-chip matching can reduce losses using transmissionlines and lumped components, with the trade-off being an increase in area. For this design,on-chip matching has been selected as a compromise between power efficiency and size.To convert RΠ (153.7 Ω) to 50 Ω and at the same time include the effect of bond wireinductance, Lw , a circuit transformation is applied to the parallel combination of RΠ and LΠ1in the feedback network. The transformation is summarized in Fig. 4.9 and consists of twosteps. First, the parallel network consisting of RΠ and LΠ1 is impedance transformed into asecond parallel network that consists of three components: CΠ, LΠnew and RΠ. The elementsin the second network are chosen to map to a third network which is an L-match impedancetransformer that consists of a shunt capacitance CΠ, a series bond wire inductance Lw andthe 50 Ω load resistor. Note that the shunt capacitance in the second and third networks hasthe same capacitance CΠ. Therefore, the second to third network transform is constructed to1034.4. Class-DE Power Oscillatorchange the parallel combination of LΠnew and RΠ into an equivalent series combination ofLw and RL where the two networks have the same Q.The value of Q is found from the impedance transformation ratio and is given byQ =√RΠ50− 1. (4.21)The value of Q can then be used to relate the bond wire inductance Lw to LΠnew:LΠnew = Lw (1 + 1/Q2). (4.22)Finally, the susceptance of LΠnew in parallel with CΠ must match the susceptance of LΠ1 inthe original feedback network. Therefore, the matched susceptance condition can be used todetermine the value of CΠ whereCΠ1 =1ω2osLw (1 + 1Q2 )− 1ω2osLΠ1. (4.23)Therefore, using the impedance transformation shown in Fig. 4.9, the original BΠ1 and RΠcomponents in the feedback network can be replaced by an equivalent network that includesbond wire inductance and an impedance transformation to 50 Ω.RΠLΠnew CΠ1Lbond50 ΩCΠ1RΠLΠ1Figure 4.9: Parallel-to-series conversion to implement output match including bondwire inductanceAs shown in Table 4.3, the feedback inductor LΠ2 which is required for the oscillatordesign has a value of 86.2 nH. This is a very large inductor value for an on chip componentand further manipulation of the feedback network is made to realize amore practical feedback1044.5. Class-DE Synchronous Rectifier Designnetwork. If instead of the Π network topology, a T network is used, then more reasonablecomponent values are obtained. Therefore a Π to T conversion is made to realize the finalfeedback network that is used in the oscillator design. The final circuit topology of thefeedback network is shown in Fig. 4.10.CS LSM2M1ATLCT2 50ΩFeedback Network; F(s)Forward Network; H(s)LT3 LwCCT1VDD CdcFigure 4.10: The complete schematic of the class-DE oscillator. The feedback network consists ofcapacitors CT1 and CT2, an inductor LT3, a bondwire inductor Lw and a 50 Ω load. The feedbackloop also includes a fictitious current source and an ideal bandpass filter shown in the dashed box.The fictitious components are added in a harmonic balance circuit simulation to evaluate nonlinearlarge-signal oscillator responses.4.5 Class-DE Synchronous Rectifier DesignNow that a class-DE oscillator has been synthesized, the next step is to design a class-DE synchronous rectifier. The rectifier circuit is obtained by using time-reversal dualityto transform the class-DE amplifier into a rectifier. Once the rectifier circuit is designed,conditions to simultaneously satisfy oscillation and rectification are investigated.The class-DE synchronous rectifier circuit is shown in Fig. 4.11. For analysis it isassumed that the RF input current is sinusoidal and that the two switches, M1 and M2, are1054.5. Class-DE Synchronous Rectifier Designideal. Similar to the amplifier, the switches are also shunted by an ideal capacitorC to providecurrent continuity during dead-time intervals. The output of the rectifier is connected to adc resistive load, Rdc, in parallel with an output capacitor Cdc.VS2LMCS LSSeriesResonator Phase Shif_tInductorM2isw1isw2VS1 iinCiCM1ARdc Cdc50ΩvRFVoZinoptFigure 4.11: Class-DE synchronous rectifier.Similar to the class-DE amplifier analysis, the 2pi switching interval is partitioned intofour intervals corresponding to different switch states. When a switch is close, the potentialat node A is constant and during dead-time intervals, the voltage at node A is determinedfrom the current through the shunt capacitor C. Expressions for the node voltage at point Aare found for each interval where the input RF current is assumed to have the formiin(θ) = Iim sin θ for θ ∈ [0, 2pi]. (4.24)The peak amplitude of the input current is Iim and θ is the instantaneous phase defined asθ = ωswt = 2pi fswt.Voltage at node A for the first dead-time interval [0, θ0] when both switches are open:Let the initial voltage across the output capacitor at θ = 0 be Vo. In order to satisfy theclass-DE condition at θ = 0, dvA/dt = 0.The voltage across the switch can be found using equation (4.3). When both switchesare open during this interval, the capacitor current iC is equal to iin and the shunt capacitorC is charged by a positive flowing iin. The voltage at node A increases from 0 V to reach1064.5. Class-DE Synchronous Rectifier DesignVDD; therefore, the corresponding voltage isvA(θ) =12pi fswC∫ θ0iin(θ ′) dθ ′=Iim2pi fswC[1 − cos θ](4.25)for θ ∈ [0, θ0].At the end of the dead-time interval, M1 is turned on. Since class-DE imposes a zerovoltage switching condition, this imposes the requirement that at θ = θ0, vA(θ0) = Vo becausethe voltage across the switch should be zero. Using this condition in (4.25) and solving forIim,Iim =2pi fswCVo1 − cos θ0 . (4.26)Both switches are open over the interval [0, θ0] and substituting (4.26) into (4.25),vA(θ) = Vo[ 1 − cos θ1 − cos θ0]. (4.27)Voltage at node A for the interval [θ0, pi] when M1 is closed and M2 is open: For theinterval [θ0, pi], M1 is closed and M2 is open; therefore, current isw1 is equal to −iin and thevoltage at node A remains constant and equal to Vo.Voltage at node A for the second dead-time interval [pi, pi + θ0] when both switches areopen: For this interval, both switches are open and the capacitor current iC is equal to −iin.The shunt capacitor C is discharged by a negative iin current and the voltage at node A fallsfrom Vo to reach 0. Therefore, the corresponding voltage at node A isvA(θ) = Vo[cos θ − cos θ01 − cos θ0](4.28)1074.5. Class-DE Synchronous Rectifier Designfor θ ∈ [pi, pi + θ0].Voltage at node A for the interval [pi + θ0, 2pi] when M1 is open and M2 is closed: Duringthe interval [pi + θ0, 2pi], M1 is closed and M2 is open. The switch current isw2 is equal to apositive current iin and the voltage at node A remains constant and equal to 0.Similar to the class-DE amplifier, expressions for the capacitance at node A,C, the phaseshift inductor LM and the optimum input impedance are derived next for the ideal class-DErectifier. The fundamental frequency component of the current iin is represented by phasorIin1 and the fundamental frequency component of the voltage vA is represented by the phasorVA1 . The phasors can be written as:VA1 =1pi∫ 2pi0vA(θ ′)e−jθ′dθ ′=Vo2pi(1 − cos θ0)[sin 2θ0 − θ0 − j (1 − cos 2θ0)](4.29)andIin1 =1pi∫ 2pi0iin(θ ′)e−jθ′dθ ′=− jωCVo1 − cos θ0 . (4.30)At the fundamental frequency, fsw , the effective input impedance (see Fig. 4.11) isZinopt (ω) = VA1/Iin1 + jωLM = RA1 + jXA1 . Therefore,RA1 =1 − cos 2θ02piωC(4.31)andXA1 =sin 2θ0 − 2θ02piωC+ ωLM . (4.32)1084.5. Class-DE Synchronous Rectifier DesignFor harmonic frequencies, Zinopt is ideally open; however, in practical circuits the loadedQ of the output network is finite and the impact of finite harmonic impedance needs to beconsidered.For the interval [θ0, pi], both the output capacitor Cdc and shunt capacitor C are chargedby positive iin and the voltage across them remains constant and equal to VDD . For theinterval [pi + θ0, 2pi], both the output capacitor Cdc and the shunt capacitor C are dischargedby negative iin and the voltage across them remains constant and equal to 0. Therefore, theamount of charge transferred to Cdc during a cycle isQo1 =1ωsw[ ∫ piθ0iin(θ ′) dθ ′ −∫ 2pipi+θ0iin(θ ′) dθ ′]=2Iimωsw− CVo . (4.33)The charge flowing through Rdc during a cycle isQo2 =2piωswVoRdc. (4.34)In the steady state condition, Qo1 = Qo2 . Hence,Iim = Vo( piRdc+ωswC2). (4.35)By substituting (4.35) into (4.26) and using the identity sin2 θ0 + cos2 θ0 = 1,cos θ0 =2pi − ωswCRdc2pi + ωswCRdc(4.36)sin θ0 =√8piωswCRdc2pi + ωswCRdc(4.37)Using the relation R′dc= ωswCRdc in equations (4.31) and (4.32), the resistance and1094.6. Nonlinear Optimization of The Oscillator Performancereactance at the input of the rectifier can be written asRA1 =8Rdc(2pi + R′dc)2(4.38)andXA1 =√8piRdc (2pi − R′dc)(2pi − R′dc)2− RdcpiR′dccos−12pi − R′dc(2pi − R′dc)2+LR′dcCRdc. (4.39)Equation (4.38) is an important relation and shows how the resistance at the RF inputterminal of the rectifier depends on the dc load resistance at the output of the rectifier. Inaddition, the imaginary part of the RF input impedance (4.39) is controlled by output dcload. Therefore, the optimum dc load corresponds to the condition where the reactive partof the input impedance is identically zero.Finally, an expression for the dc load voltage can be determined from (4.35) whereVo =2IimRdc2pi + R′dc. (4.40)4.6 Nonlinear Optimization of The Oscillator PerformanceAlthough the synthesis of class-DE power oscillator was described in section 4.4, there aretwo critical limitations for this design. Firstly, in order to synthesize the feedback network, thefundamental frequency is only considered and this was justified by selecting feedback inputreference plane after the series resonator. However, this approach may not be appropriate toaccurately predict the performance of switching-mode oscillators in which many harmonicsare strongly generated. Second of all, the start-up condition for oscillation was not consideredthrough out the steady state design procedure. The oscillator start-up behaviour should beinvestigated separately to check whether or not the oscillator starts and goes to a stable steadystate output amplitude.1104.6. Nonlinear Optimization of The Oscillator Performance4.6.1 Nonlinear Optimization for Steady State ConditionsA more comprehensive steady state verification of the oscillator is made using a harmonicbalance (Harmonic Balance (HB)) simulation. Unlike amplifiers which have an explicit inputport and output port, an oscillator only has an output port. The fact that there is no inputport means that it is difficult to directly simulate large signal (Large-Signal (LS)) behaviourusing harmonic balance techniques because the large signal state is highly dependent on theinitial transient which establishes the large signal conditions.As a way to effectively simulate large signal characteristics and decouple the simulationfrom the necessity of first simulating transient behaviour, an auxiliary generator can beincluded in the feedback loop to activate large signal steady state conditions [67]. Theauxiliary source is shown in the dashed box in Fig. 4.12 and is composed of a current sourceand a high Q bandpass filter. The current source frequency and the center frequency of thebandpass filter are made equal to the oscillation frequency, fLS = fos. When the circuit isoscillating at the resonant frequency of the series bandpass filter, it is an ideal short circuitat fLS and an open circuit at all the other frequencies. Further, when the loop is oscillatingunder large signal signal steady state conditions, the current source ILS should be perfectlysynchronized to the fundamental frequency of the oscillator. Under these conditions, theharmonic balance simulator converges to the condition where the voltage across the currentsource is identically zero. Therefore, when fLS = fos,ZLS = VLS/ILS = 0 (4.41)where VLS is the voltage across the LS current source at fLS . Equation (4.41) is solvedthrough error-minimization or optimization procedures with the HB simulator.For the optimization of the power oscillator, the LS current source is connected in seriesat the input-reference plane defined in Fig. 4.7. At this point in the circuit, the LS amplitudeILS is set equal to the input amplitude Iin = 9.74 mA consistent with the value given in1114.6. Nonlinear Optimization of The Oscillator PerformanceCS LSM2M1ATLCT2 50ΩFeedback Network; F(s)Forward Network; H(s)LT3ILSfLSBPFat fLSLwCCT1VDD CdcFigure 4.12: The complete schematic of the class-DE oscillator including the large-signal simulationsource in the oscillator feedback loopTable 4.2. In this way, both NMOS and PMOS transistors are in the saturation region duringthe nonlinear simulation, which leads to a class-DE of operation for the oscillator. The LSfrequency fLS is set to the desired oscillation value of 5.8 GHz. After fixing the valuesfor both the LS amplitude of the current at the input reference plane and the oscillationfrequency, the HB simulator can sweep different component values in the feedback networkuntil the loop condition in equation (4.41) is satisfied.Two nested sweeps were made to optimize the values of CT1 and CT2. The simulated3-D contours of constant power efficiency and constant output power as a function of CT1and CT2 are shown in Fig. 4.13(a) and Fig. 4.13(b), respectively. It is important to note thatthe oscillation amplitude is kept equal to the desired value during the entire double sweepprocess because the LS current amplitude is always equal to 9.74 mA. On the other hand, theoscillation frequency changes during the sweep since fLS is one of the optimization variablesthat is adjusted to obtain convergence. Therefore, the corresponding oscillation frequenciesare shown in Fig.4.13(c).1124.6.NonlinearOptimizationofTheOscillatorPerformance(a) (b) (c)Figure 4.13: Contour plots of the: (a) simulated dc to RF power efficiency, (b) output power and (c) oscillation frequency. The solutionssatisfy the condition that ZLS = 0.1134.6. Nonlinear Optimization of The Oscillator PerformanceThe maximum power efficiency in Fig. 4.13(a) corresponds to component values of230 fF for CT1 and 5.4 pF for CT2. By comparing the point of maximum efficiency withthe point for maximum output power in Fig. 4.13(b), it can be seen that the two conditionsare not simultaneously satisfied. However, the deviation from maximum output power issmall for the corresponding pair of capacitance values (CT1, CT2) which are selected tomaximize the power efficiency of the oscillator. The compromise between efficiency andpower is common in nonlinear circuits and, in this design, maximizing power efficiency isan important objective.The above analysis and optimization are applied to the circuit in the steady state oscillatoryregime. However, even if the obtained solutions are accurate and valid, the oscillator mightfail to start-up from its dc solution with the optimized values. Therefore, a transient analysiswith the optimized feedback component values is essential to verify whether the large signaloscillating conditions can be established from the dc operating.4.6.2 Start-Up ConditionsTo verify the oscillation start-up, the stability of the circuit must be analyzed. The initialconditions in the circuit must be unstable and implement positive feedback in order to havenoise start the oscillator. Both close-loop pole-zero techniques [68] and open-loop techniquessatisfying the Barkhausen Criteria can be used to evaluate start-up conditions. The open-looptechnique is selected for this design.In the class-DE oscillator, the loop is opened at the gate terminal. Due to the open-loopconsideration, the feedback network needs to be terminated with the proper impedance whichcorresponds to the close-loop termination impedance. However, it is generally difficult tofind the proper impedance to terminate the open-loop configuration at the cut plane. To workaround this problem, the feedback is considered as an infinite number of identical open-loopnetwork connected end to end [69, 70]. Under this condition, the loop-gain can be expressed1144.6. Nonlinear Optimization of The Oscillator Performancein terms of the two-port Z-parameters for the open-loop network andL(s) =2`1 +√1 − 4(Z12/Z21)l2(4.42)where` =Z21Z11 + Z22. (4.43)A special condition of interest arises when the open-loop gain L(s) takes on a value of oneat some point in the complex plane. This operating point satisfies the boundary conditionsimposed by a close-loop. Specifically, at this point, the input is equal to the output. Fromclassical control theory, this point corresponds to a pole in the close-loop transfer function.The condition that |L(s) |= 1 is satisfied wheneverZ11 + Z22 = Z21 + Z12. (4.44)In other words, the open-loop gain L(s) describes the poles of a single close-loop network[71]. It is therefore possible and convenient to determine stability by applying the Nyquistcriteria directly to the parameter. As a reminder, the Nyquist criteria for oscillation states thatthe polar open-loop response and its imagemust make at least one net clockwise encirclementof the point 1 + j0 as frequency is increased [71].Similar to the large signal HB steady state simulations, two nested sweeps are carried outto evaluate the loop gain for different values of CT1 and CT2. For each pair of capacitancevalues (CT1, CT2), the magnitude of the loop gain function and the corresponding oscillationfrequency where the phase of the loop is zero are found. The results of these sweeps areshown in Fig. 4.14(a) and Fig. 4.14(b), respectively. As shown in Fig. 4.14(a), for a value ofCT2 less than 1.25 pF, the condition that |L(s) |≥ 1 is satisfied.1154.6. Nonlinear Optimization of The Oscillator Performance(a) (b)Figure 4.14: Contour plots showing the sensitivity of the loop gain and frequency for different valuesof CT1 and CT2. (a) The loop gain magnitude corresponding to the zero phase loop gain conditionand (b) the frequency corresponding to the zero phase loop gain condition.The frequency of oscillation determined from start-up conditions does not generallysatisfy steady state oscillation condition ( due to the non-linear component varied by thesignal levels). Thus, the oscillation frequency fos at steady state can be slightly differentfrom the frequency determined by the oscillation start-up condition.4.6.3 The Effect of Gate BiasTypically, class-DE amplifiers and oscillators exhibit higher efficiency for gate bias below thethreshold voltage [72]. However, in the case of oscillators, start-up does not occur for gatebias below the threshold voltage because no gain (gm,n +gm,p) is exhibited by the transistors.Under these conditions, the dc solution is stable and the oscillator will not start. Therefore itis important to evaluate bias conditions in the oscillator for both start-up and steady state..The voltage vin at the input reference plane isvin = VA sin(ωost). (4.45)1164.6. Nonlinear Optimization of The Oscillator Performancewhere VA is the amplitude of input voltage. Although the the fundamental frequency com-ponent of the gate signals are the same for both devices, as shown in Fig. 4.15 different biasvoltages Vb,n and Vb,p can be applied to the NMOS and PMOS transistors, respectively.CS LSM2M1ACT250ΩLT3LwCCT1Cb2Cb1Vb,nVb,pvinPoutRFVDD CdcPindcFigure 4.15: Complete schematic of the CMOS class-DE power oscillator.When the amplitude of the gate signal is below the NMOS threshold voltage, VTh,n, theNMOS is off while the PMOS is on. Conversely, when gate signal is above VDD −VTh,p, thePMOS is off and the NMOS is on. Therefore, the on-time for NMOS and PMOS areton,NMOS =12 fos[1 − 2pisin−1(VTh,n − Vb,nVA)](4.46a)ton,PMOS =12 fos[1 − 2pisin−1(Vb,p − |VTh,p |VA)]. (4.46b)Consequently the conduction angle for the transistors areϕon,NMOS = pi − 2 sin−1(VTh,n − Vb,nVA ) (4.47a)ϕon,PMOS = pi − 2 sin−1(Vb,p − |VTh,p |VA ). (4.47b)1174.6.NonlinearOptimizationofTheOscillatorPerformance(a) (b) (c)Figure 4.16: Simulated class-DE oscillator characteristics as a function of bias voltages for the NMOS and PMOS transistors. Responsesare shown for different supply voltage. (a) dc to RF power efficiency, (b) output power and (c) oscillation frequency. The solutions satisfythe condition that ZLS = 0.1184.6. Nonlinear Optimization of The Oscillator PerformanceThe evolution of the steady state oscillation when reducing the bias is analyzed here usingan LS analysis. For the simulation, the feedback components are selected to be CT1=290 fFand CT2=1.2 pF. These values correspond to optimal points shown in Figs. 4.13 and 4.14.Two nested simulation sweeps are made to determine the optimal bias voltages for theoscillator. The NMOS gate bias is varied between 0.2-1.8 V and the PMOS gate bias is variedfrom 0.5 V to 3.5 V. Simulations are also made for six different supply voltages (VDD) from1 V to 3.5 V in 0.5 V steps. The corresponding simulation results are shown in Fig. 4.16.Three plots are shown the figure which show how efficiency, power and oscillation frequencyvary as a function of bias voltages. All solutions also satisfy the large signal steady statecondition where ZLS = 0. From these simulation it is observed that the power efficiency isnear a maximum when the NMOS bias voltage is kept roughly constant and equal to VThn0while the PMOS bias voltage should track changes in the supply voltage, VDD − VThp0 .(a) (b)Figure 4.17: Contour plots to show how the class-DE open loop gain changes a function of NMOSand PMOS bias voltages. The plots are shown for VDD = 2 V, CT1= 290 fF and CT2=1.2 pF. (a) Thesimulated loop-gain magnitude where the loop phase is zero and (b) the corresponding oscillationfrequency for the zero phase condition.As a final step in determining the required bias conditions for the oscillator, the open1194.7. Bias Configurationloop gain function is evaluated as a function of bias. Multidimensional sweeps were madein the simulator for different bias conditions and the results are shown in Fig. 4.17(a) andFig. 4.17(b). The responses are shown for a nominal supply voltage of 2 V and feedbackcapacitances of CT1 equal to 290 fF and CT2 equal to 1.2 pF. The plots confirm that biasconditions selected to maximize efficiency also satisfy start-up conditions.4.7 Bias ConfigurationA bias circuit that generates the required voltages needs to be designed. The bias circuit isdeveloped from modifications of the cascode current mirror circuit shown in Fig. 4.18[73].VDDI1VbM1M2M3VDDR1VbM2R2Figure 4.18: A cascode current mirror for generating bias voltages.The bias circuit in Fig. 4.18 needs to be modified to reduce sensitivity to the loadresistance. Improvements to the circuit are made by replacing the reference current source I1and transistor M1 with R1 and R2, respectively. The diode connected transistor M3 can alsobe removed to make the proposed circuit more simple. After modification, two separate biascircuits are obtained for biasing the PMOS and NMOS transistors in the class DE oscillator.These bias circuits are shown in Figs. 4.19(a) and 4.19(b), respectively. The operation ofthese bias circuits is analyzed next.1204.7. Bias ConfigurationR3p Vb,pVDDR1pR2pQ1I1p(a)Q1R3nQ2R2nVDDR1nVb,nVDDI2nI1n(b)Figure 4.19: Modified bias circuits for (a) the PMOS device and (b) for the NMOS device.In Fig. 4.19(a), Q1 must operate in the saturation region and this requires that twoconditions are met:VSG ≥ |VThp0 |VGD ≤ |VThp0 |.(4.48)The voltage VGD can be found using Kirchhoff’s Voltage Law (KVL) such that VSD =VSG − R1p I1p. In conjunction with (4.48), the voltage drop across R1p should be less thanor equal to the PMOS threshold-voltage (R1p I1p ≤ |VThp0 |). Therefore,I1p ≤ VThp0R1p . (4.49)Using a second KVL loop from supply to ground (VDD − VSG = R3p I1p) and with (4.49),VDD − VSG ≤ R3pR1p |VThp0 |. (4.50)In order to minimize the power consumption of the PMOS bias circuit,Q1 in Fig. 4.19(a)1214.7. Bias Configurationis set at the edge of saturation, VSG = |VThp0 |; henceR3pR1p≥ VDD|VThp0 |− 1. (4.51)Furthermore, I1p in Fig. 4.19(a) can be written as a simple quadratic equationI1p = kp (VSG − |VThp0 |)2. (4.52)Replacing VDD − R3p I1p with VSG , the current I1p is calculated asI21p −2R3p (VDD − VThp0 ) + k−1pR23pI1p +(VDD − VThp0 )2R23p= 0. (4.53)The general solution for I1p isI1p =VDD − VThp0R3p+1√1 + 4R3pkp (VDD − VThp0 )2R23pkp. (4.54)The positive root is not acceptable because of the saturation requirement for the PMOSdevice; therefore, the negative root is selected and Vb,p can be written asVb,p ' (VDD − VThp0 ) +1 − √1 + 4R3pkp (VDD − VThp0 )2R3pkp. (4.55)The rate of change in Vb,p with respect to the supply voltage (∂Vb,p/∂VDD) is positivefor small values of VDD; however, as VDD is increased, this rate becomes constant. From(4.55), it can be shown that∂Vb,p∂VDD= 1 − 1√1 + 4R3pkp (VDD − VTh0 ). (4.56)The bias circuit for the NMOS device in class-DE oscillator is shown in Fig. 4.19(b).According to Fig. 4.19(b), the absolute values of the gate-source voltage of the NMOS and1224.7. Bias ConfigurationPMOS devices are equal (VGS1 = VSG2). Since the drain current in both the NMOS andPMOS transistors are quadratic relations with respect to the overdrive voltage (|VGS |−|VTh |),a linear relationship between I1n and the supply voltage (∂I1n/∂VDD = constant) can only besatisfied if the overdrive voltage of the NMOS device varies as the square root of the supplyvoltage (VGS1 − VThn0 ∝√VDD). Using the body effect of the PMOS transistor as a secondorder effect, the corresponding drain current in the PMOS transistor isI2n = kp (VSG2 − |VThp |)2= kp[VGS1 − |VThp,0 |−γ(√|2ΦF + VBS2 | −√|2ΦF |)]2(4.57)where kp is a technology parameter, ΦF is the built-in potential, and VBS2 is the body-sourcevoltage in PMOS transistor. The constant γ is also technology dependent and determineshow current varies as a function of the body-source voltage.Given that VBS2 = R1n(I1n + I2n), and using the assumption that there is a• a linear relationship between I1n and supply voltage (I1n ∝ VDD)together with the intention of having a fixed I2n, (4.57) can be written asIn2 = kp[√αVDD −√βVDD + VThn0 − VThp0 + δ]2. (4.58)The variables α, β and δ are constants and depend on R1n, R2n and R3n. With the properchoice for these constants, I2n is constant, and consequently a constant bias voltage Vb,n isobtained for changes in VDD . In addition, based on (4.58), it is possible to set R1n, R2n andR3n such that I2n and Vb,n have a square root (−√VDD) dependency on VDD . In other words,as VDD is increased, Vb,n decreases with a rate proportional to −√VDD .As a verification of the bias circuit design, post-layout simulation results are shown inFig. 4.20 for the final bias circuit design. As shown, the NMOS bias voltage is constant as1234.8. Feedback Modifications for Synchronous Rectifier Modethe supply voltage varies while the PMOS bias increases linearly with supply voltage.1.0 1.5 2.0 2.5 3.0 3.5 Voltage (V)Supply Voltage (V) PMOS Bias Voltage  NMOS Bias VoltageFigure 4.20: NMOS and PMOS bias voltages vs. supply voltage.4.8 Feedback Modifications for Synchronous Rectifier ModeUp to this point, the class-DE circuit has been optimized for the oscillator mode. Therequirements to reconfigure the circuit into a class-DE rectifier are considered next.As described earlier in section 2.2.5, when time reversal duality is used to reverse powerflow in an amplifier circuit to transform the circuit into a rectifier, the relative phase betweenthe gate drive and the RF port signal change. Recall that the relative phase change was 2ϕfor k = 0 with reference to equation (2.7). Since the oscillator has similar phase relationsto the amplifier, we can expect that the dual mode circuit will require feedback loops withdifferent phase requirements.In the previous sections, the feedback network in the class-DE oscillator has been opti-1244.8. Feedback Modifications for Synchronous Rectifier Modemized for steady state, transient and bias conditions. This led to the final form of the feedbacknetwork shown in Fig. 4.10. The next step in the design methodology is to determine howthe feedback network can be modified to satisfy synchronous switching in the rectifier mode.Further, the changes required in the feedback network should be minimized to reduce thecomplexity of reconfiguring the circuit for the two modes.After investigating the requirements for the rectifier feedback loop and after evaluatingdifferent concepts to modify the oscillator feedback loop, a suitable circuit was realized bychanging only one element in the T network of the oscillator feedback circuit. The capacitorCT1 in Fig. 4.10 is replaced with an inductor LT1. The corresponding synchronous rectifiercircuit is shown in Fig. 4.21. The feedback circuit implements a phase shift of approximately120 degrees at a frequency of 5.8 GHz.CS LSM2M1ACT250ΩLT3LwCLT1Cb2Cb1Vb,nVb,pRdc CdcVoPoutdcPinRFvRFFigure 4.21: Complete schematic of class-DE synchronous rectifier with NMOS and PMOS devices.Since the objective is to design a bidirectional circuit with two modes, the feedback loopneeds to be configured for the oscillator and rectifier modes. The reconfigurable feedbackloop requires a switch to select either CT1 for the oscillator or LT1 for the rectifier.The circuit which was used to implement this function is shown in Fig. 4.22. The circuitconsists of two parallel branches: one branch has an inductor L1, while the other branch has1254.8. Feedback Modifications for Synchronous Rectifier Modea switch S1 in series with a capacitor C1. Capacitor C2 is a dc blocking capacitor and doesnot affect the phase of the feedback circuit.ModeINOUTL1C2C1S1Figure 4.22: Circuit to change the loop phase for the oscillator and rectifier. When S1 is off, thephase shift network consists of only the inductor L1 for the rectifier mode. When S1 is on, the phaseshift network consists of a parallel resonator (L1 andC2). The capacitorC2 is a dc blocking capacitor.When the gate of the mode switch S1 is low, the switch is off and the branch with thecapacitor is open. In this state, the feedback loop satisfies the synchronous rectifier mode.When S1 is on, a parallel resonant circuit is created by C1 and L1. The resonant frequencyis selected to be below the required frequency in the oscillator such that the combinationof the two elements has negative reactance which matches the reactance of CT1. Therefore,by incorporating this switchable element block in the feedback loop, a mode switch canbe controlled to configure the loop a feedback loop that satisfies the conditions for boththe oscillator and rectifier modes. The final bidirectional and reconfigurable circuit blockincluding the switchable feedback loop and the bias circuits is shown in Fig. 4.23.1264.8. Feedback Modifications for Synchronous Rectifier ModeCS LS + L′MM2M1ACT2LT3LwCCb2CdcModeL1C2 C1S150ΩvRF50ΩVDDRdcFeedback NetworkForward NetworkRect_ifier: dc LoadOscillator: dc SourceRect_ifier: RF SourceOscillator: RF LoadFeedback ControllerLoad NetworkClass DEROOR ModeModeBNMOS biasR3pR1pR2pQ3R2nQ1Q2R′3nR′′3nR1nPMOS biasFigure 4.23: Reconfigurable power oscillator and synchronous rectifier circuit. The circuit isreconfigured with a mode control signal: “O" for oscillator and “R" for rectifier.1274.9. Simulation and Experimental Results4.9 Simulation and Experimental ResultsAn implementation of the bidirectional circuit block was designed using a 65 nm CMOSprocess design kit from TMSC. The circuit is designed to operate in the 5.8 GHz ISM bandand be fully reconfigurable for both oscillator and rectifier modes. A photograph of the dieis shown in Fig. 4.24 and the dimensions of the die are 500 µm × 700 µm. The figure alsoshows the test bench that was used to experimentally verify the design.OscillatorRect_ifierRFin/outV DDRF scopeRF generatordc scopeSPDTSwitchROModeBidirect_ional Circuit700 µmG G GGGRFVCdc voltagecapacitorLS + L′ML1LT3 Act_ive500µmFigure 4.24: Test bench and die micrograph for the class-DE bidirectional power oscillator andsynchronous rectifier circuit.An Agilent Vector Network Analyzer (VNA) (N5241A) was used as a power sourcefor testing the synchronous rectifier mode as well as measuring the input impedance of thedevice at different power levels. A wafer probe station was used for the measurements andthe station was calibrated for two port S-parameters. Accurate RF power measurements weremade with a calibrated power meter (Agilent E4417A EPM-P) and cable loss and probe losswere compensated such that power measurements were referenced to the coplanar waveguideinput on the die.For the oscillator mode, spectral measurements were made with an Agilent EXA signalanalyzer (N9010A). The oscillator phase noise characteristics were made with test equipmentfrom Berkeley Nucleonics (BNC 7300). Accurate power measurements were made with an1284.9. Simulation and Experimental ResultsAgilent E4417A power meter.1.0 1.5 2.0 2.5 3.0 3.53941434547495153dc to RF Power Conversion Efficiency (%)Input dc Voltage (V) Simulation  MeasurementFigure 4.25: DC to RF power conversion efficiency of class-DE power oscillator mode. Thesimulation andmeasurement results correspond to the dash-dot red line and the blue trace, respectively.Experimental results for the oscillator mode are shown in Fig. 4.25 to 4.26(b). The outputpower for the oscillator is controlled by the dc supply and the dc to RF power conversionefficiency ranges from 40% for 1 V to 51% at 3.5 V with a peak of 52% at 2.5 V as shownin Fig. 4.25.1294.9. Simulation and Experimental Results1.0 1.5 2.0 2.5 3.0 3.55.725.735.745.755.765.775.785.795.80Oscillation Frequency (GHz)Input dc Voltage (V) Simulation Measurement(a)1k 10k 100k 1M-136-128-120-112-104-96-88-80-72-64-56SSB Phase Noise (dBc/Hz)Frequency (Hz) Phase Noise-115.7 @ 1 MHz(b)Figure 4.26: Class-DE power oscillator mode: (a) operating frequency of class-DE power oscillatorversus supply voltage, (b) oscillator phase noise.1304.9. Simulation and Experimental ResultsThe sensitivity of the oscillator frequency to dc supply voltage is shown Fig. 4.26(a).Over a range from 1.5 V to 3.5 V, the oscillator frequency is approximately 5.74 GHz andrelatively insensitive to supply variations. The phase noise characteristics of the oscillatorare shown in Fig. 4.26(b) and the phase noise at an offset of 1 MHz is −115.7 dBc/Hz.For the rectification mode, the RF to dc conversion efficiency is shown in Fig. 4.27 as afunction of the RF input power. The efficiency ranges from 31% to 51% which comparesfavorably with other state-of-the-art CMOS rectifier designs. The measurements span an18 dB range from -2 dBm to 16 dBm; post layout results are also shown for comparison.The simulation and measurement results for the high power class-DE rectifier track veryclosely over most of the dynamic range up to +3 dBm. For RF input power levels above +3dBm, the maximum error between simulated and experimental results is 5%.-2 0 2 4 6 8 10 12 14 16 1825303540455055RF to dc Power Conversion Efficiency (%)RF Input Power (dBm) Simulation MeasurementFigure 4.27: Class-DE synchronous rectifier RF to dc power conversion efficiency as a function ofRF input power. The simulation and measurement results correspond to the dash-dot red line and theblue trace, respectively.1314.9. Simulation and Experimental Results70 140 210 280 350 420 490 560 630 700 770 840 91025303540455055RF to dc Power Conversion Efficiency (%)dc load ( ) Simulation Measurement(a)0.2 0.5 1.0 2.0 5.0-0.2j0.2j-0.5j0.5j-1.0j1.0j-2.0j2.0j-5.0j5.0j S11 vs. RF Input Power S11 vs. FrequencyPin: -2 to 17 dBmfin: 5.5 to 6 GHz(b)Figure 4.28: Class-DE synchronous rectifier mode: (a) RF to dc power conversion efficiency as afunction of dc load, and (b) Input match as a function of frequency and RF input power.1324.10. SummaryThe efficiency of class-DE synchronous rectifier circuit changes with dc load resistanceand measurement results as a function of dc load resistance are shown in Fig. 4.28(a). Apeak power efficiency of 51% is measured for a dc load of 400 Ω and an efficiency of 45%is maintained over a broad load range from 100 to 900 Ω.The input impedance characteristics of the RF rectifier are shown in Fig. 4.28(b). Thecircuit is designed to be matched to 50 Ω and the measurements confirm that a good matchis obtained.4.10 SummaryThe concept of a reversible dual mode circuit which can function both as a power oscillatorand as a synchronous rectifier has been proposed. Except for a single mode switch, the circuitis completely reversible and the RF input port is used either as an output for the oscillatoror an input for the rectifier. Since the circuit can support two functions, it can be used intime multiplexed sensor networks which switch between an energy harvesting mode and atransmission mode.A detailed analysis of the oscillator and synchronous rectifier was presented for a class-DE switching condition. The synthesis of the feedback loops for both modes was a significantchallenge in the design. Also, a tracking bias circuit to adapt to changes in supply voltagewas required to implement an efficient oscillator that would operate over a wide range ofsupply voltages and provide sufficient gain to start the oscillator.From the analysis of the bidirectional circuit, two important analytic results were alsoderived and are summarized below.1. There is an inherent phase difference in the loop transfer function that differs forthe oscillator and rectifier circuit duals. The phase shift can be traced back to thetheory of time-reversal duality. Consequently, a switchable phase shifter is required toimplement a reconfigurable oscillator and synchronous rectifier circuit.1334.10. Summary2. There is a relationship between the dc load impedance and the RF impedance at theinput of the synchronous rectifier. Equations were derived for class-DE to show thisrelationship. The link between dc load resistance and RF input impedance shows thathow the input match, which affects rectifier efficiency, can be controlled by the dc loadresistance. This explains why there is an optimum load resistance which maximizesefficiency in the rectifier.These analytic results are general and give insight into fundamental relations that are expectedto be useful for future work.An experimental circuit was implemented in 65 nm CMOS technology to verify theconcept of the bidirectional oscillator and rectifier. A frequency of 5.8 GHz was selected forthe design. Experimental measurements show that the circuit functions as expected and apeak power efficiency greater than 50% was measured for both modes. The high-efficiencyobtained for the CMOS power oscillator represents a new benchmark for CMOS circuits, asmost other reports in the literature have primarily focused on low-power oscillator design.134Chapter 5Conclusions and Future WorkThe research work in this thesis has been motivated by interest to improve the power conver-sion efficiency of CMOS RF power oscillator and CMOS RF rectifier for energy harvestingapplications. It is absolutely essential to understand factors which affect power conversionefficiency and evaluate newmethods to improve the design of RF blocks in energy harvestingsystems. Conclusions from this research and recommendations for future work follow.5.1 ConclusionCMOS technology is an attractive technology platform to develop RF energy harvestingcircuits that can be seamlessly integrated into ultra-low power sensors. As the developmentof far-fieldwireless power transfermatures, the goal is to eventually realize circuits that can beeither be completely self-powered from incident RF power or used as a means of rechargingan energy storage device like a battery. It is these applications that have motivated theresearch in this thesis.One of the most important requirements in RF energy harvesting circuits is the powerconversion efficiency of the rectifier. RF power is rectified to generate dc power and thismust be done as efficiently as possible.As a way of realizing high-efficiency rectifiers, this work has relied on the theory of time-reversal duality to transform power efficient amplifier circuits into power efficient rectifiercircuits. Although the theory of time-reversal duality was first described by Hamill in 1990,the application of this technique to implement high frequency synchronous rectifiers is much1355.1. Conclusionmore recent.As described in Chapter 2, the main advantage of using time-reversal duality is to realizecircuit topologies that can be optimized for synchronous rectification. At high frequencies,losses limit the exact synthesis of circuit duals and the losses have implications on how timereversed duals should be compared. It was proposed that circuits are duals under conditionsof equal source power. Another important contribution of this work has been to highlight thedifference in the phase relationships between the oscilator and synchronous rectifier circuits.The implications of the phase difference led to the requirement of having a switchablefeedback network in the bidirectional circuit to support both oscillator and rectifier modes.Another significant aspect of this work has been to systematically explore the powerefficiency of a number of different circuit topologies which are known to have high-efficiencyin terms of amplifier classes. The study began with two switch-mode classes: class-E andclass-D. These classes were analyzed in terms of synchronous rectifier applications andexperimental implementations of the circuits were realized to verify performance. Class-Ecircuits have a series inductor for biasing the drain, while class-D circuits replace the biasinductor with a second switch. Class-E circuits also have high voltage peaking, while class-Dconstrains the voltage swing across the devices. Small scale CMOS transistors have very lowoperating voltages; therefore circuits which limit voltage swing such as class-D are attractiveand limit potential damage to the devices. Experimental results for the class-D circuit showedthat a power efficiency of 30% was obtained for input power levels in the 0-20 dBm range.One of the limitations of switch-mode classes such as class-E and class-D is that theyare designed for hard switched rectangular gate drive signals. Although this condition canbe realized with large amplitude RF signals, the dynamic range of the switching classes islimited as RF power decreases. As RF power is reduced, the gate drive signal becomes moresinusoidal and the operation of the switch reverts to a transconductance mode. It was thisobservation that led to the third class of circuits that were investigated in Chapter 2 whichare transconductance mode circuits.1365.1. ConclusionThe primary design goal for the transconductancemode circuitswas to optimize efficiencyfor sinusoidal signals. In the transconductance mode, the conductance angle of the devicecurrent changes with RF power. In this way, at high amplitudes the device operates in class-Cand then back-offs with RF power, eventually changing to class-B then class-A. A circuit wasalso proposed that used two overlapping ranges of synchronous rectifiers to obtain a highdynamic range circuit. The high power CMOS transconductance mode rectifier design hasa device sized to operate over a 25 dB dynamic range from -10 dBm to 15 dBm with a peakof 58% efficiency. The low power design was optimized to operate over a 35 dB dynamicrange from -30 dBm to +5 dBm and had peak efficiency of 40%.Another important factor that affects the power efficiency of synchronous rectifiers is thedc load resistance. The dc load resistance and the RF input impedance of the rectifier arelinked and an improper load resistance can mismatch the RF input port leading to reducedpower efficiency. Therefore, a tracking load that is adjusted to maximize the power efficiencyof the rectifier is very useful. In Chapter 3, a discontinuous mode dc to dc converter stagewith a control loop that regulates the input impedance of the converter was proposed as a wayto implement a tracking dc load. As a demonstration of the adjustable load and tracking loop,an experimental design of the load was implemented and tested with a 10-W GaN HEMTClass-F synchronous rectifier. The performance of the tracking load was compared to theoptimal performance of the rectifier, as well as with a fixed load. The tracking load providedgood performance over a 13 dB dynamic range of RF input power, and the load performedsubstantially better than a fixed load, especially at low RF power levels.After spending several years working on different CMOS rectifier circuits, and aftergaining experience with the utility of time-reversal duality, the concept of a reversible RFfront-end that could be configured as both a power oscillator and synchronous rectifier wasreached. This circuit was the subject of Chapter 4. The bidirectional circuit block opens upthe possibility of implementing remote sensors that can time multiplex between an energyharvesting mode and a transmission mode.1375.2. Future WorkA class-DE switching amplifier was used as a starting template for the bidirectionalcircuit where class-DE takes advantage of both limiting voltage swing across the switches, aswell as improving switching efficiency by limiting gate overlap loss. A self-bias mechanismensures the circuit does not require an auxiliary power supply for both oscillator and rectifiermodes. A detailed methodology for synthesizing the feedback circuit was described as wellas how the circuit was optimized to handle a wide range of conditions including oscillatorstart-up and steady state conditions.An experimental implementation of the class-DE bidirectional circuit was built to operateat a frequency of 5.8 GHz. The dc to RF power conversion efficiency of the oscillator isgreater than 40% for the supply range of 1.2-3.5 V, while the RF to dc power conversionefficiency of the synchronous rectification mode is greater than 40% for a 16 dB dynamicrange of the RF input power. The efficiency of the class-DE synchronous rectifier exceedsthe performance of the earlier designs which used class-E and class-D switching conditions.Therefore, the work described in Chapter 4 builds on the earlier success of circuits describedin Chapter 2.5.2 Future WorkThe contributions presented in this thesis have opened up many exciting possibilities forfuture work.5.2.1 Rectifier Topologies and DevicesFor low power densities where the RF voltage is not high enough to bias the synchronousrectifier properly, pre-biasing the rectifier using power stored in the sensor could improve therectification efficiency at low RF power. The circuit complexity would increase and futuredesign challenges could focus on how to balance complexity with power efficiency.Although RF to dc power conversion efficiencies of the integrated rectifier with matching1385.2. Future Workstructures presented in this thesis are high in comparison to previous work for CMOStechnologies, further improvement may be possible. The selection of the specific CMOStechnology is critical, and although for the ISM bands presented here the silicon workedwell, other technologies such as GaAs and GaN might prove to be better choices for higherfrequencies or high power applications. Nevertheless, no matter what device technology ischosen, the designs can build on the insight gained from the analysis and circuit designsdescribed in this thesis. In addition, it is possible to extend the theory presented in thisthesis to differential synchronous rectifiers. The gate drive for differential circuits is morecomplex but it may improve the maximum power efficiency which can be achieved over alarger dynamic range of RF power.5.2.2 Antenna ConsiderationsAwirelessly-powered sensorwill require an integrated antennawhich receives power radiatedfrom a transmitter in the far-field. The sensor should be relatively insensitive to spatialorientation and this will require careful antenna design to ensure robust operation for energyharvesting. Also, the antenna gain will be important and affect the requirements for theincident RF power levels.Integrated antennas also provide new freedom in the design of the input impedanceof the rectifier. In the designs described in this thesis, the input impedance is 50 Ω, aconvenient impedance for test equipment and off-the-shelf antennas. On the other hand, ifthe antenna design is integrated with the rectifier design, the interface impedance is no longerconstrained to 50 Ω and there may be more optimal interface impedances that improve theoverall efficiency of the energy harvesting system.5.2.3 Integration With Power Management and Energy StorageAnother significant opportunity for future work is in the area of power management circuitswhich utilize the rectified output power. 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