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Automatic tuning circuits for Mach-Zehnder interferometer optical switches AlTaha, Mohammed Wadah 2017

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Automatic Tuning Circuits for Mach-Zehnder Interferometer Optical Switches by  Mohammed Wadah AlTaha  B.A.Sc., The University of British Columbia, 2011  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF  MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES (Electrical and Computer Engineering)  THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver)  November 2017  © Mohammed AlTaha, 2017 ii  Abstract Optical communication networks are the foreseeable solution to meet the increasing demand for high data rates. An important part of a communication network is the network switch that facilitates the routing of data from sources to destinations, from a set of input streams to a set of output streams. Silicon photonics is poised to play a significant role in optical communication networks due to its suitability to build scalable and highly integrated photonic structures and systems, in addition to the use of established fabrication methods inherited from the electronics industry. One of the applications where silicon photonics can play a critical role is in implementing network switches. A Mach-Zehnder interferometer (MZI) is an optical device that is ideally suited to build network switches, as it can be dynamically controlled to achieve high-quality switching of optical signals. However, the performance of silicon photonics devices is sensitive to fluctuations in ambient temperature, fabrication tolerances, and device aging, and MZI devices are no exception.  This work describes the factors that degrade the performance of an MZI switch, and then presents an electronic feedback system that monitors and automatically tunes a 12 MZI switch to its optimum operating point and compensate for the aforementioned performance-degrading factors. A design for a 22 MZI switch monitoring technique is also presented that uses feedforward interferometry to enable more efficient use of the MZI as a switch for two simultaneous optical inputs at different wavelengths, and an electronic feedback and tuning system for such switches is also demonstrated.  iii  Lay Summary Crossroads and intersections facilitate journeys from any starting point to any destination, and traffic control centers strive to optimize the flow of traffic. Data switches and switch controllers play analogous roles in optical communication networks. However, the performance of the network switches used in these networks is susceptible to fluctuations in the ambient temperature, device aging, and variations in the device dimensions after manufacturing. We demonstrate electronic techniques to mitigate such adverse effects. We also introduce a novel switch-monitoring structure that enables more traffic to be routed, thereby increasing the efficiency of optical switches for communication networks. iv  Preface This research aims to invent a method of monitoring the performance of an optical switch and offsetting effects that may adversely degrade the switch performance. This research problem was identified through a collaboration project with industry partners. Following is a description of the contributions to the content presented in this thesis:  For the material presented in chapter 3 on a control method for a 12 MZI switch, I developed the proposed system and hill-climbing algorithm. I did the complete system design, layout, and measurements of the chip. As the system constituted of several circuits, several colleagues assisted me. Hasitha Jayatilleka assisted in understanding the behavior of the switch, doing preliminary behavioral simulations for optical switch and as well as finding out a way to extract performance metrics of the Analog to Digital Converter (ADC). Abdelrahman Ahmed designed the front-end CMOS receiver that includes the transimpedance amplifier (TIA), low pass filter (LPF), and DC offset cancellation loop. Spoorthi Nayak came up with the symmetric layout of the capacitor array used in the ADC and the Digital to Analog Converter (DAC), and both of us worked iteratively to improve the design. Ahmad Sharkia proposed the design for the voltage-output DAC and assisted in the layout and characterization of the OPAMP used therein. Ray Chung verified the hill-climbing algorithm on an FPGA and tested it with the 12 MZI switch.  For the material presented in chapter 4, Dr. Lukas Chrostowski, Ray Chung, and Hasitha Jayatilleka proposed the monitoring interferometer structure, and I, along with Zeqin (Chris) Lu, assisted them in theoretical verification of the concept. Ray Chung carried out v  the simulations, and he and Hasitha Jayatilleka did the testing of the e-beam chip. Zeqin (Chris) Lu did the layout for both the e-beam and MPW chips, and I did the optical characterization of the MPW chip along with him. I implemented the electronic system that reads the photodetector (PD) current, interfaced the switch to an FPGA, implemented the appropriate digital blocks around the hill-climbing algorithm. A United States patent has been filed for the proposed design. We submitted a paper on the work presented in this chapter to the Optical Fiber Communication (OFC) 2018 conference, and are waiting for the acceptance decision. We are also planning to submit a journal version of the work presented in this chapter. vi  Table of Contents  Abstract .......................................................................................................................................... ii Lay Summary ............................................................................................................................... iii Preface ........................................................................................................................................... iv Table of Contents ......................................................................................................................... vi List of Tables ................................................................................................................................ ix List of Figures .................................................................................................................................x List of Abbreviations ................................................................................................................. xiv Acknowledgements .................................................................................................................... xvi Dedication ................................................................................................................................. xviii Chapter 1: Introduction ................................................................................................................1 1.1 Motivation ....................................................................................................................... 1 1.2 About This Thesis ........................................................................................................... 4 Chapter 2: Background .................................................................................................................5 2.1 Phase-Shifting Methods .................................................................................................. 5 2.1.1 The Electro-optic Effect (Plasma Dispersion Effect) ................................................. 5 2.1.2 Thermo-Optic Effect ................................................................................................... 6 2.2 Mach-Zehnder Interferometer (MZI) Optical Switch ..................................................... 7 Chapter 3: Automated Tuning of 12 MZI Switch ..................................................................11 3.1 System and Circuits ...................................................................................................... 11 3.1.1 Transimpedance Amplifier (TIA) ............................................................................. 12 3.1.2 Analog to Digital Converter (ADC) ......................................................................... 19 vii  3.1.3 Hill-Climbing Algorithm .......................................................................................... 23 3.1.4 Synthesized Controller .............................................................................................. 26 3.1.5 Digital-to-Analog Converter (DAC) ......................................................................... 26 3.1.5.1 Design ............................................................................................................... 26 3.1.5.2 Simulation and Measurement Results ............................................................... 29 3.1.6 Simulated Closed Loop Operation of the CMOS Feedback Controller ................... 32 3.1.7 Measurement of the Integrated Controller ................................................................ 35 3.2 Measurements with FPGA ............................................................................................ 38 Chapter 4: Automated Tuning Structure for a 22 MZI Switch ............................................43 4.1 Need for 22 Switch Tuning ......................................................................................... 43 4.2 Proposed Design ........................................................................................................... 44 4.3 Simulation Results ........................................................................................................ 48 4.4 Measurements and Tuning Results ............................................................................... 54 4.4.1 Measurements of the e-beam Chip ........................................................................... 55 4.4.2 Measurements of the MPW Chip .............................................................................. 58 Chapter 5: Conclusion .................................................................................................................70 5.1 Concluding Remarks ..................................................................................................... 70 5.2 Comparison with Existing Works ................................................................................. 70 5.3 Future Work .................................................................................................................. 72 5.3.1 Integrated Controller ................................................................................................. 72 5.3.2 Controller Design for Scaled-Up Switch Fabrics ..................................................... 72 Bibliography .................................................................................................................................75 Appendices ....................................................................................................................................78 viii  Appendix A : Hill-Climbing Algorithm Verilog Codes ........................................................... 78 A.1 Hill-Climbing Algorithm Verilog Code.................................................................... 78 A.2 Comparison Block .................................................................................................... 82  ix  List of Tables Table ‎3.1: Heater voltage and achieved extinction ratio with and without digital filter at the output [ack: Ray Chung] ............................................................................................................... 42  x  List of Figures Figure ‎2-1: General construction of an MZI optical switch with description of bar and cross states ................................................................................................................................................ 7 Figure ‎2-2: Plot of MZI outputs vs. phase difference, ∆φ, between the MZI arms ........................ 9 Figure ‎3-1: MZI as a 12 switch with monitoring optical tap and PD ......................................... 11 Figure ‎3-2: MZI switch with the proposed automatic tuning controller ....................................... 12 Figure ‎3-3: MPD with passive resistor TIA and parasitic capacitance ......................................... 14 Figure ‎3-4: A simplistic representation of a resistive-feedback TIA ............................................ 15 Figure ‎3-5: TIA-LPF front-end receiver with DC offset cancellation .......................................... 16 Figure ‎3-6: Transistor-level depiction of the TIA-LPF front-end receiver with DC offset cancellation [Designed by A. Ahmed]. ......................................................................................... 17 Figure ‎3-7: SAR ADC block diagram .......................................................................................... 20 Figure ‎3-8: Clocked comparator [11] ........................................................................................... 22 Figure ‎3-9: Simulated behavior of the hill-climbing algorithm with positive-slope operation (circles) and negative-slope operation (triangles) ......................................................................... 24 Figure ‎3-10: M-bit Digital to analog converter with OPAMP-based voltage output stage .......... 28 Figure ‎3-11: Simulated performance of the DAC......................................................................... 29 Figure ‎3-12: Measured performance of the DAC with increasing input ...................................... 31 Figure ‎3-13: Measured performance of the DAC with decreasing input...................................... 31 Figure ‎3-14: Simulated MZI output power during closed-loop operation of the CMOS controller....................................................................................................................................................... 33 Figure ‎3-15: Simulated output of the DAC to the MZI heater ..................................................... 34 Figure ‎3-16: Simulated output voltage of the DAC nodes ........................................................... 35 xi  Figure ‎3-17: CMOS chip micrograph ........................................................................................... 36 Figure ‎3-18: Open-loop transient measurements of the controller ............................................... 38 Figure ‎3-19: Test setup for automatic tuning and control of 12 MZI switch with the hill-climbing algorithm using an FPGA board [setup and measurements done by Ray Chung]. ....... 39 Figure ‎3-20: Automated tuning of a 12 MZI with hill-climbing algorithm on FPGA: (a) progression of the algorithm on the MZI switching spectrum, and (b) oscilloscope capture of the voltage to the MZI heater [Results obtained and plotted by Ray Chung] .................................... 40 Figure ‎3-21: Tuning results of 12 MZI with hill-climbing algorithm on FPGA: (a) Transient of heater voltage and (b) achieved average extinction ratio with DAC digital filtering. (c) Transient of heater voltage and (d) achieved average extinction ratio without DAC digital filtering [results and plots by Ray Chung]............................................................................................................... 41 Figure ‎4-1: 2x2 MZI optical switch with thermo-optic phase tuners ........................................... 43 Figure ‎4-2: 22 MZI switch with a monitoring-tap and MPD ..................................................... 43 Figure ‎4-3: Proposed MZI switch with nested feed-forward monitoring interferometer ............. 45 Figure ‎4-4: Operation of the proposed 2x2 switch in the bar state ............................................... 47 Figure ‎4-5: Operation of the proposed 2x2 switch in the cross state ............................................ 48 Figure ‎4-6: Lumerical INTERCONNECT simulation model ....................................................... 48 Figure ‎4-7: Simulation sweeps for the proposed switch. (a) Output of the MI arm, (b) output of the bar arm, and (c) output of the cross arm [Acknowledgment: Ray Chung] ............................. 50 Figure ‎4-8: Simulation sweep results for the bar state. (a) optical power and spectrum of MI's output (b) optical power at output 1 of the switch (c) optical power at output 2 of the switch [Acknowledgment: Ray Chung] ................................................................................................... 52 xii  Figure ‎4-9: Simulation result for the cross state: (a) optical power and spectrum of MI output (b) optical power at output 1 of the switch, and (c) optical power at output 2 of the switch [Acknowledgement: Ray Chung] ................................................................................................. 54 Figure ‎4-10: Layout of feedforward switch submitted for fabrication using e-beam technology [Layout done by Zeqin Lu] ........................................................................................................... 55 Figure ‎4-11: Micrograph of the feedforward switch on the e-beam PIC ...................................... 56 Figure ‎4-12: Measurement results of the e-beam feedforward switch: (a) Output of monitoring interferometer while sweeping switch heater voltage (DC-coupled), (b) AC-coupled signal from (a), and (c) switching spectrum of the main switch showing bar state at 2.05 V and cross state at 2.8 V [Acknowledgement: Ray Chung and Hasitha Jayatilleka] ................................................. 57 Figure ‎4-13: Layout of MPW feedforward switch cell [Layout done by Zeqin Lu] .................... 59 Figure ‎4-14: Micrograph of fabricated feedforward switch with wirebonded pads ..................... 60 Figure ‎4-15: Feedforward switch measurement setup .................................................................. 60 Figure ‎4-16: Picture of the PIC-on-board setup and coupling fiber array .................................... 61 Figure ‎4-17: Switching spectrum of the main MZI switch ........................................................... 62 Figure ‎4-18: MPD output current vs. heater power at 0V dithering input .................................... 63 Figure ‎4-19: Optical output power of the switch and measured MPD current swing due to dithering signal.............................................................................................................................. 64 Figure ‎4-20: Resistor TIA with a unity-gain buffer ...................................................................... 65 Figure ‎4-21: Resistive-feedback TIA with biasing ....................................................................... 65 Figure ‎4-22: Transient capture of the dithering‎signal‎applied‎to‎the‎MI’s‎phase‎shifter‎and‎TIA‎output voltage at bar state of main switch .................................................................................... 66 xiii  Figure ‎4-23: Transient capture of dithering signal applied to the‎MI’s‎phase‎shifter‎and‎TIA‎output voltage near cross state of main switch ............................................................................. 67 Figure ‎4-24: FPGA tuning of feedforward switch (a) and (b) without DAC output averaging, and (c) and (d) with DAC output averaging ........................................................................................ 69 Figure ‎5-1: Illustration of an MZI cell (green) and IO pads (brown) ........................................... 73 Figure ‎5-2: Possible implementation of a CMOS chip containing 8 controllers .......................... 74  xiv  List of Abbreviations  AC   Alternating Current ADC   Analog-to-Digital Converter CDAC   Capacitor Digital-to-Analog Converter CMOS  Complementary Metal Oxide Semiconductor DAC   Digital-to-Analog Converter DC   Direct Current   DC   Directional Coupler DNL   Differential Nonlinearity ER   Extinction Ratio ESD   Electro-Static Discharge FFT   Fast Fourier Transform FPGA   Field-Programmable Gate Array FSM   Finite State Machine HDL   Hardware Description Language IC   Integrated Circuit LSB   Least-Significant Bit LPF   Low-Pass Filter MI   Monitoring Interferometer MPD   Monitoring Photodiode  MPW   Multi-Project Wafer MZI   Mach-Zehnder Interferometer xv  MZM   Mach-Zehnder Modulator NRZ   Non-Return to Zero OSA   Optical Spectrum Analyzer PD   Photodiode or Photodetector PIC   Photonic Integrated Circuit SAR   Successive Approximated Register SOI   Silicon on Insulator TIA   Transimpedance Amplifier VCCS   Voltage-Controlled Current Source VDAC   Voltage Digital-to-Analog Converter  WDM   Wavelength Division Multiplexing xvi  Acknowledgements I would like to start by expressing my deep gratitude and recognition for the big part my parents and brother played in making my progress in this program possible. Their support on all levels is unparalleled and I can never thank them enough, let alone repay their gracious favors. I express my sincere appreciation and gratitude to my supervisors – Dr. Shahriar Mirabbasi and Dr. Sudip Shekhar. I acknowledge and thank them for their continuous support and concern for my progress, development, and excellence. I also acknowledge them for introducing educating and challenging courses at the department, and also for their challenging questions, both inside and outside the classroom, which taught me to seek to fully understand a subject, in addition to learning to answer questions clearly and concisely. I would like to thank Dr. Lukas Chrostowski for providing insightful feedback and suggestions during the design and measurement phase, and for accepting to serve on my examination committee. I also extend my thanks to Dr. Nick Jaeger for his course on optical waveguides Sincere thanks also go to my esteemed colleagues Hasitha Jayatilleka, Abdelrahman Ahmed, Ahmad Sharkia, Spoorthi Nayak, Ray Chung, and Zeqin (Chris) Lu, for their insights into concepts and help with simulations, designs, and measurements. Special thanks go to Dr. Roberto Rosales and Mr. Roozbeh Mehrabadi for their support with design for testing, testing equipment, and CAD support. I would also like to thank our industry partner Huawei Technologies Canada, and specifically Dritan Celo, Dominic J. Goodwill, and Eric Bernier, for their time and helpful and insightful discussions as well as for providing us with a test chip of the optical switches. xvii  Lastly, we acknowledge the Natural Sciences and Engineering Research Council (NSERC) and the SiEPIC program for financial support, and Canadian Microsystems Corporation (CMC) for support with research tools and fabrication services. xviii  Dedication To my parents and brother for all their love and support throughout this journey.  1  Chapter 1: Introduction 1.1 Motivation Fiber optics has become a keyword used by companies to describe how they provide products and services that address the ever-increasing demand for data-intensive content, such as video streaming, and services, such as social networks. While fiber optics as a short hand keyword‎ technically‎refers‎ to‎ the‎“wires”‎ that‎carry‎ the‎desired‎data,‎ the‎wider‎communication‎structure employing fiber optics is referred as optical communication networks. An important part of any communication network is a networking switch. A networking switch is to a communications network what intersections are to road networks and what stations are to a public transit network. For example, instead of building a road or a public transit line from every origin to every destination, intersections and transit stations allow the construction of a limited number of roads and lines that share common points, i.e. road intersections and transit stations,‎where‎a‎commuter‎can‎‘switch’ the roads or transit lines. Similarly, a networking switch is a common point between multiple communication channels that allows data sent on one channel to hop onto a different channel. Communication channels, and their network switches, operated solely in the electrical domain. But with the increasing demand for faster communication networks, electrical networks keep facing greater obstacles in keeping up with this demand. This is because the physical channels (often Copper) carrying these communication signals demand greater increase in the transmission energy than the corresponding increase achievable in communication bandwidth. Furthermore, one networking approach to satisfy the increasing demand for data is the parallel transmission of data streams on multiple channels. But in order to implement this approach in electrical networks, it would take a corresponding increase in the number of input-output (IO) 2  pads, and also an increase the in the number of channels and power dissipated by the on-chip circuitry.  As a result, optical communication networks emerged as the solution to these challenges because of inherent advantages of the physical channels, e.g. the optical fiber, used in optical communication networks over their electrical counterparts such as a much larger bandwidth and an ability to support the transmission of data over multiple wavelengths down a single optical channel (wavelength-division multiplexing (WDM)). As for switching functionality, it is no exception to the limitations presented above, and as a result, two options emerge for implementing switches. First is keeping the switching functionality in the electrical domain, with the incoming and outgoing data streams being in the optical domain. While this option allows the amplification and retiming of data, if such functionalities are needed, it requires converting the incoming optical signals to electrical signals, performing the switching, and converting the electrical signals back to optical signals. This optical-to-electrical (OE) and electrical-to-optical (EO) conversion happens at the full data rate of the incoming and outgoing data streams. Furthermore, if the incoming and outgoing optical data streams are part of a WDM system, the incoming data streams need to be demultiplexed (DMUXed) to separate the different wavelength channels into parallel data streams at single wavelengths before doing the OE conversion. At the output of the electrical switch, the output parallel streams go through an EO conversion before being multiplexed (MUXed). These MUX/DEMUX operations add loss, area, and possibly power consumption. The other option is to perform all-optical switching. All-optical switching is done using photonic structures that perform the switching action directly on the optical signals, and contrary to the previous approach, does not require any O-E-O conversions. Furthermore, these switches 3  do not need to be actuated at the full data rate, but rather only at the switching speed, which is both application-dependent and significantly less than the data rate. Silicon photonics is an emerging technology that has made long strides towards providing a suitable platform for scaling up optical communication networks. Silicon has become synonymous with the electronics industry because it is the backbone of the complementary metal-oxide-semiconductor (CMOS) technology that facilitated the widespread adoption of digital electronics. In addition, CMOS technology is a very mature technology with established design and simulation tools, fabrication, yield, and packaging capabilities. CMOS technology also enabled the very dense integration of millions of transistors on a single chip, which in turn enabled large-scale integration of many functionalities on a single chip, thus reducing the packaging and assembly costs of building systems. Similarly, silicon photonics, on a silicon-on-insulator (SOI) platform, promises to employ these established properties of the CMOS technology to building photonic integrated-circuits (PICs) with many functionalities on a single chip. The SOI platform uses silicon as the waveguiding material in which optical signals propagate, surrounded by insulating material, namely silicon dioxide (SiO2).   However, the performance of photonic structures built with the SOI platform is sensitive to factors such as fluctuations in the ambient temperature of the devices and uncontrolled variations in the fabrication process. There exist approaches to eliminate or mitigate the adverse effects of these factors such as novel design structures that have inherently increased resilience towards these factors or using device fabrication technologies that add special materials to the standard fabrication process of SOI platforms [9], rendering the fabricated devices less sensitive to temperature variations, for example. 4  Another method is an active-control approach which uses extraneous electrical signals to induce controlled changes in the structure of the photonic devices or in their ambient environment such that the result of these controlled changes cancel out the adverse effects of the uncontrolled changes in said devices or surroundings thereof [1]. 1.2 About This Thesis This thesis explores active control approaches to automatically and continually optimize the performance of optical switches fabricated through an SOI silicon photonics platform. The thesis is organized as follows:  Chapter 2 gives background on the particular optical switches that are addressed in this thesis, particularly Mach-Zehnder Interferometer (MZI) switches, as well as the physical effects that can be used to actively actuate them.  Chapter 3 presents a proposed design of a CMOS electronic active controller and an optimization algorithm for use with an 1-input, 2-output (12) MZI switch, and demonstrates the operation of the optimization algorithm on a field-programmable gate array (FPGA) interfaced to such switch.  Chapter 4 presents the challenge of implementing an active controller of a 2-input, 2-output (22) MZI switch and proposes a feedforward MZI switch structure and an active control technique to remedy those challenges. The chapter then presents measurements of the new structure with the optimization algorithm on an FPGA.  Chapter 5 concludes the thesis and discusses future works. 5  Chapter 2: Background This chapter outlines the basics of an MZI optical switch and the electro-optical effects that can be utilized to control it. 2.1 Phase-Shifting Methods There are two main methods used to introduce the phase shift needed to perform the switching action of an MZI switch; the electro-optic effect and the thermo-optic effect. Both these effects introduce the needed phase shift in the MZI by locally affecting the refractive index, n, of the waveguide. The phase change, φ, experienced by an optical signal propagating in a waveguide section of length L is [5]:  𝜑 =2𝜋𝐿𝑛𝜆𝑜, (‎2-1) where λo is the wavelength of light in vacuum, and n is the refractive index of the waveguide. 2.1.1 The Electro-optic Effect (Plasma Dispersion Effect) The refractive index of a material can be changed by changing the concentration of charge carriers, i.e. electrons and holes, in the material, which is known as the plasma dispersion effect. An empirical study in [6] showed that the plasma dispersion effect in silicon can be described by the following equation:  Δ𝑛(@1550nm) = −5.4 × 10−22Δ𝑁1.011 − 1.53 × 10−18Δ𝑃0.838, (‎2-2) where‎∆N and‎∆P are the change of concentration of electrons and holes, respectively. However, the plasma dispersion effect has an associated loss to it due to the free-carrier absorption effect. In the same study, [6] also showed that the loss associated with changing the concentrations of charge carriers in silicon is:  Δ𝛼(@1550nm) = 8.88x10−21Δ𝑁1.167 + 5.84x10−20Δ𝑃1.109 [𝑐𝑚−1], (‎2-3) 6   In silicon photonics and on the SOI platform, the plasma dispersion effect is realized through either one of two methods: 1) Carrier depletion using a PN (P-doped, N-doped) junction which uses the modulation of the depletion region of a reverse-biased PN junction as the means of changing the concentration of charge carriers, and hence induce the plasma dispersion effect. 2) Carrier injection using a PIN (P-doped, Intrinsic, N-doped) junction where the forward biasing causes current to flow through the junction, changing the concentration of charge carriers, and inducing the plasma dispersion effect in the process. Since the plasma-dispersion effect relates to the motion of charge carriers, the junction can be modulated at high speeds, e.g. up to tens of GHz for the carrier depletion effect [7]. 2.1.2 Thermo-Optic Effect As mentioned in the introduction, temperature variations in the environment surrounding the photonic structures implemented on an SOI platform adversely affect the performance of these photonic devices. This is due to the large thermo-optic effect of silicon. Just as with the plasma dispersion effect, the thermo-optic effect is quantified via the effect of temperature change on the refractive index of silicon. At room temperature, 300 K, the thermo-optic effect of silicon is [8]:  𝑑𝑛𝑑𝑇= 1.86 × 10−4 [𝐾−1], (‎2-4) and hence the refractive index of a waveguide as a function of temperature, T, can be expressed as: 7   𝑛(𝑇) = 𝑛𝑜 +𝑑𝑛𝑑𝑇Δ𝑇, (‎2-5) where no is‎the‎nominal‎refractive‎index,‎i.e.‎without‎temperature‎change,‎and‎∆T is the change in temperature. Since the thermo-optic effect is larger than the plasma-dispersion effect in silicon, and does not have associated optical loss, it can be used to implement compact optical switch cells. This results in reduced signal loss and area consumption, and hence cost, when implementing large switch fabrics [12]. Furthermore, the thermo-optic effect can be used to implement active thermal stabilization of photonic devices [1].  2.2 Mach-Zehnder Interferometer (MZI) Optical Switch Figure ‎2-1 shows the construction and operation of an MZI optical switch. The device has three main sections. First and last sections of the device are 50% splitters that split and combine the light on its input side to the output side. Details of operation of these splitters can be found in [3]. The main section of the MZI has two arms, upper and lower, and one or both of these arms may contain optical phase shifting elements that have the ability to change the phase of the light propagating in the arm.  Figure ‎2-1: General construction of an MZI optical switch with description of bar and cross states A balanced MZI is one where the lengths of the two arms of the main section are equal. The two beams of light propagating in the main section of the MZI would experience the same 8  phase shift because they are propagating the same distance, provided that the phase shifter(s) in the main section are not excited such that they introduce a phase change to the light propagating the arms. If we define Δ𝜑 = 𝜑1 − 𝜑2, then the following equations relate the optical power at the outputs O1 and O2, 𝑃𝑂1 and 𝑃𝑂2, respectively, to the optical power to the input, 𝑃𝐼𝑖 [4]:  𝑃𝑂2𝑃𝐼𝑖= cos2(Δ𝜑) =12[1 + cos(Δ𝜑)] (‎2-6)  𝑃𝑂1𝑃𝐼𝑖= sin2(Δ𝜑) = 1 − cos2(Δ𝜑) =12[1 − cos(Δ𝜑)], (‎2-7) One important performance metric‎of‎an‎MZI‎switch‎is‎the‎switch’s‎extinction‎ratio‎(ER),‎which is defined as:  𝐸𝑅 = 10 log (𝑃𝑂2𝑃𝑂1), (‎2-8) 9  and, for an MZI switch, is seen as a measure of how well the MZI routes the input light to either one of its output without any leakage to the other output.  Figure ‎2-2: Plot of MZI outputs vs. phase difference, ∆φ, between the MZI arms Figure ‎2-2 plots‎the‎transfer‎functions‎of‎the‎MZI’s‎outputs‎as‎outlined‎by‎equations‎(‎2-6) and (‎2-7), when the MZI is constructed with only one input, I1, as shown in Figure ‎2-1. The plot shows that when Δ𝜑 = 0 all the input power, 𝑃𝐼𝑖, appears at output port O2, resulting in maximum value for 𝑃𝑂2 and constituting the cross state of the switch. Conversely when Δ𝜑 = 𝜋 all the input power, 𝑃𝐼𝑖, appears at output port O1, resulting in maximum value for 𝑃𝑂1 and constituting the bar state of the switch (as shown in the insert of Figure ‎2-1). Figure ‎2-2 also shows that the switching behavior of the MZI is periodic with a 2𝜋 period, which is clear from the fact that 𝑃𝑂2 reaches another maxima when Δ𝜑 = 2𝜋. 10  As discussed in the previous section, inducing phase change in silicon can be done either using the plasma dispersion or the thermo-optic effect, and in this thesis we discuss the implementation of active controllers for MZI switches employing the thermo-optic effect because of its expected importance in large scale switch matrices, as mentioned at the end of section ‎2.1. From the earlier discussion, using (2-1) and (2-5), we conclude that the phase change induced by a thermal phase shifter of length L is:  𝜑 =2𝜋𝐿 𝑛(𝑇)𝜆𝑜=  2𝜋𝐿𝜆𝑜(𝑛𝑜 +𝑑𝑛𝑑𝑇Δ𝑇), (‎2-9) and‎hence‎ the‎phase‎difference,‎∆φ, between the two arms of the balanced‎MZI‎switch’s‎main‎section is:  Δ𝜑 = 𝜑1 − 𝜑2 =2𝜋𝐿1𝜆𝑜(𝑛𝑜1 +𝑑𝑛𝑑𝑇Δ𝑇1) −2𝜋𝐿2𝜆𝑜(𝑛𝑜2 +𝑑𝑛𝑑𝑇Δ𝑇2) =2𝜋𝐿𝜆𝑜𝑑𝑛𝑑𝑇(Δ𝑇1 − Δ𝑇2),  (‎2-10) where the two arms have identical length (L1 = L2 = L) and refractive indices (𝑛𝑜1= 𝑛𝑜2). Equation (2-9) shows that‎the‎phase‎difference,‎∆φ, between the two arms of the MZI, which in turn determines the switching state of the MZI, is indeed dependent upon the temperature difference between the two arms. This temperature change can be introduced to the local ambience of the waveguide by means of dissipated electrical power through a resistor, where the temperature change is linearly proportional to this dissipated electrical power, and hence it is proportional to square of the current through resistor or the square of the voltage across it,  Δ𝑇 ∝ 𝑃 = 𝐼2𝑅 =𝑉2𝑅. (‎2-11)  11  Chapter 3: Automated Tuning of 12 MZI Switch In this chapter, we first present a feedback system for active control and automatic tuning of an MZI switch that is being used to switch a single input, I1 at‎λ1, to one of its two outputs, O1 or O2, as shown in Figure ‎3-1. A portion of the optical power is tapped from one of the outputs, and is incident on a monitoring PD (MPD) to generate a current, iPD. An integrated circuit (IC) implementation is first proposed, followed by simulation results. We also present measurement results of such a system, where an FPGA is used to implement the digital control.    Figure ‎3-1: MZI as a 12 switch with monitoring optical tap and PD 3.1 System and Circuits Figure ‎3-2 shows the proposed implementation of an electronic feedback system that automatically tunes the 12 MZI switch. The following subsections describe the components of this system. 12   Figure ‎3-2: MZI switch with the proposed automatic tuning controller 3.1.1 Transimpedance Amplifier (TIA) The output signal from the monitoring photo-diode (MPD) is a current signal; however, the decision circuits of the active controller operate in the voltage domain. Thus, the first requirement is a transimpedance converter that converts this output signal from the current domain to the voltage domain according to the relation:  𝑉𝑜𝑢𝑡 = 𝑘. 𝑖𝑖𝑛, (‎3-1) which shows that the unit for the conversion constant, k, is Ohms. Furthermore, the MPD receives a small portion of the output optical signal; to minimize the degradation in the output signal intensity at O1, and as a result, the output current at the MPD is small. In order for this current to be reliably processed by the following circuits, it needs to be amplified to appropriate levels, which tells us that the factor k needs to be more than 1, i.e. provide gain. 13  From the above two requirements, we conclude that the first stage of the controlling circuitry must be a trans-impedance amplifier (TIA). The simplest TIA is a just resistor that obeys‎Ohm’s‎law:‎  𝑉 = 𝐼. 𝑅, (‎3-2) where the transimpedance gain is simply the resistance value. The advantage of using a resistor as a TIA is simplicity and reduced power consumption. However, being a passive component, a resistor TIA has three main disadvantages: 1) It has a direct gain-bandwidth tradeoff: Figure ‎3-3 shows the typical connection of a resistive TIA, where CPD is the total capacitance seen across the MPD, which includes the diode capacitance, pad capacitance, Electro-Static Discharge (ESD) capacitance, etc. The TIA gain of this circuit is:  𝑉𝑜𝑢𝑡 = 𝑖𝑃𝐷 (𝑅//1𝑠𝐶𝑃𝐷) = 𝑖𝑃𝐷𝑅1 + 𝑠𝑅𝐶𝑃𝐷, (‎3-3) 14  which is essentially a low-pass system where the cutoff frequency is inversely proportional to the low frequency gain (R). For tuning and stabilization of a switch, the active control circuitry is designed to monitor and compensate only for the slow variations in the performance of the optical devices due to the low frequency variations of the ambient environment; e.g. ambient temperature and device aging. Thus, the gain-bandwidth tradeoff of resistor TIAs is not a limitation for tuning applications.  Figure ‎3-3: MPD with passive resistor TIA and parasitic capacitance 2) Loading effects: a resistor TIA can be loaded by the input impedance of the next stage. This may degrade the TIA gain. 3) Varying PD bias: As the state of the switch is varied, the amount of light routed to the MPD, and consequently the MPD’s‎current‎and‎ the‎resulting‎voltage‎across‎ the‎resistor would also vary. However, the voltage across the resistor is also the reverse-bias voltage for the MPD, and as a result, the MPD experiences a varying reverse-bias voltage.  While the gain-bandwidth tradeoff of a passive TIA may not be a limiting factor for monitoring systems, the loading effects and varying PD bias point are the main reasons for the implementation of an active TIA in this work. Active TIAs can be constructed as resistive-feedback amplifiers as shown in Figure ‎3-4, where the TIA gain is given by Rf. 15   Figure ‎3-4: A simplistic representation of a resistive-feedback TIA An opamp is not necessarily needed for the resistive-feedback TIA; an inverter can be used instead. An inverter can be operated as a small-signal amplifier if it is biased properly; i.e. in the region where it has a large (negative) slope. The feedback resistor, Rf, self-biases the inverter at this point for small signal operation [9]. However, as the current of the PD undergoes large signal excursions due to ON/OFF signaling (non-return to zero, NRZ), an average (DC) current must be subtracted from the PD output so as to generate a bipolar swing. Therefore, a DC offset cancellation loop is needed for proper operation. Figure 3-2 shows the offset cancellation loop implemented in this work, consisting of an active balun, a differential low pass filter (LPF), and an error amplifier. A detailed block level diagram is shown in Figure ‎3-5, and a detailed, transistor-level diagram is shown in Figure ‎3-6. 16   Figure ‎3-5: TIA-LPF front-end receiver with DC offset cancellation   An active balun, as shown in Figure ‎3-6, converts‎the‎TIA’s‎output‎signal‎to‎two‎signals‎that are out of phase with respect to each other, or in other words, one signal has a positive gain with respect to the original signal and the other signal has a negative gain with respect to the original signal. The schematic for the active balun is shown in Figure ‎3-6, where the output of the TIA is effectively connected to two amplifier circuits; one circuit is a common-gate amplifier circuit (where the signal from the TIA is connected to the source of an NMOS whose gate is connected to a DC bias voltage), and the other circuit is a common source amplifier (where the signal from the TIA is connected to the gate of an NMOS transistor with its source grounded). The gain of the common-gate stage is:  𝑣𝑥𝑣𝑡𝑖𝑎,𝑜𝑢𝑡= 𝑔𝑚3. 𝑅𝑑1, (‎3-4) whereas the gain of the common-source circuit is:  𝑣𝑦𝑣𝑡𝑖𝑎,𝑜𝑢𝑡= −𝑔𝑚4. 𝑅𝑑2, (‎3-5) where gm3 and gm4 represent the small signal transconductance of transistor M3 and M4, and Rd1 and Rd2 represent the load resistors, respectively. Thus, if the transistors and their respective load resistors are sized properly, the two outputs can be made differential. 17   Figure ‎3-6: Transistor-level depiction of the TIA-LPF front-end receiver with DC offset cancellation [Designed by A. Ahmed]. The next block in the loop is a differential LPF as shown in Figure ‎3-6. The capacitor is implemented using a MOS transistor, and therefore the capacitance and the cutoff frequency is controllable with a bias voltage, Vbias. The LPF only retains the low-frequency components, which represent both the slow variations in the optical power output of the MZI resulting from slow‎variations‎in‎the‎MZI’s‎state,‎and‎the‎DC‎drift.  The output of the LPF is then fed to an error amplifier, as shown in Figure ‎3-6, which amplifies the difference between the outputs of the LPF. The output of the error amplifier is related to the inputs by the following relationship:  𝑣𝑜𝑑𝑣𝑖= 𝑔𝑚𝑅𝑑 , (‎3-6) where vo is the small-signal voltage output of the error amplifier, Rd is the equivalent resistance of the resistance at the drains of the transistors M7 and M8, gm is the small-signal transconductance of the transistors M5 and M6, and vi is the differential input to the error amplifier, given by: 18   𝑣𝑖 = 𝑣𝑖𝑛+ − 𝑣𝑖𝑛− , (‎3-7) The‎ error‎ amplifier’s‎ output‎ is‎ connected‎ to‎ the‎ following‎ stage‎ in‎ the‎ tuning‎ loop‎ for‎processing,‎ since‎ it‎ contains‎ the‎ information‎ about‎ the‎MZI’s‎ state.‎ It‎ is‎ also‎ connected‎ to‎ the‎gate of an NMOS transistor whose drain is connected back at the input of the TIA, as shown in Figure ‎3-6. The output signal of the error amplifier changes the current being drawn by the NMOS, making it operate like a controlled current source. Thus, the input current of the TIA can be changed by changing the current drawn by the NMOS current source from a constant PD current. For example, if the error signal increases, it causes an increase in the current being drawn by the transistor, which reduces the current flowing into the TIA, for a constant PD current. Conversely if the error signal decreases, it cause less current to be drawn by the transistor, and thereby increasing the current into the TIA. The offset cancellation loop extracts the low-frequency variations of the signal as indications of the variation in the DC bias point of the input, and cancels this offset. But this slow variation in the signal level is also indicative of the state of the MZI switch, and the higher the signal level, the closer is the system to the desired bar state of the switch. As a result, this extracted low-frequency signal is also passed to the later stages of the MZI switch tuning loop to be used in the control algorithm, as shown in Fig. 3-2. This signal is used by the tuning loop before its effect manifests in the DC cancellation loop. As a result, the TIA is biased at its optimum point, and simultaneously, pass the low-frequency variation signal that is indicative of the‎switch’s‎state‎to‎the‎latter‎stages‎of‎the‎tuning‎loop. 19  3.1.2 Analog to Digital Converter (ADC) In order to have the flexibility of implementing different control architectures, a digital implementation of the control algorithm is chosen in this work. Therefore, the analog output of the TIA-DC cancellation loop is fed to an analog-to-digital converter (ADC). An ADC topology that provides the best tradeoff between size and power-consumption, with power consumption being a higher priority for this work, is the successive-approximation register (SAR) ADC architecture [11]. As the name implies, the SAR ADC architecture does the analog to digital conversion by iteratively guessing the value, comparing the guess to the input, and modifying the guess. In particular, the SAR ADC follows a binary search approach to arrive at the digital code output that is closest to its analog input. For example, a 2 bit SAR ADC does a two-stage binary search where in the first stage it guesses that its analog input is one-half of its reference voltage, Vref, and compares this guess with the actual analog input. If the input voltage was found to be greater than ½ Vref, then the next comparison would be between the analog input and ¾ Vref, and this last comparison would determine whether the input is in the range ½ Vref to ¾ Vref, or in the range ¾ Vref to Vref. Similarly, an N-bit SAR ADC goes through N stages of binary search, starting with ½ Vref followed by successive addition or subtraction of decreasing portions of the reference voltage in powers of two, i.e. ±1/4, ±1/8, ±1/16,‎…‎±1/2N. This process means that the N-bit SAR ADC goes through N clock cycles before finishing its conversion process. Thus, the sampling rate, fs, of a SAR ADC is:  𝑓𝑠 =𝑓𝑐𝑙𝑘𝑁, (‎3-8) where fclk is the clock frequency. 20   Figure ‎3-7: SAR ADC block diagram Figure ‎3-7 shows the schematic of the SAR ADC implemented in this work. The box labelled CDAC is a capacitor bank that constitutes a binary weighted digital to analog converter (DAC). The array makes the shared node between the plates have a controllable voltage divider between‎the‎DAC’s‎reference‎voltage,‎Vref, and ground. For example if bits b0 and b1 connected the bottom plates of their respective capacitors to Vref while the bits b2…bN connected their respective capacitors to ground, then the voltage at the shared node is:  𝑉𝑡𝑜𝑝 =𝐶0 + 𝐶1𝐶𝑡𝑜𝑡𝑎𝑙 𝑉𝑟𝑒𝑓 , (‎3-9) where C0 is the capacitor controlled by bit b0, C1 is the capacitor controlled by bit b1, with C1 = 2C0, and Ctotal is the sum of all the capacitances in the capacitor array.  A switch is added to the capacitor array to reset the shared array node to ground. This has two main benefits: 1) It removes any charges that might have accumulated on the capacitors during the fabrication process. 21  2) It resets the capacitor array to a known voltage level after each conversion cycle such that successive conversion cycles start from the same starting point, which in this implementation, is ground level. The area highlighted as S/H is the sample and hold circuit which samples the analog input, Vin, onto a sampling capacitor, Cs, that holds the sampled Vin value for the duration of the conversion cycle. The comparator compares the sampled analog input with the value of the DAC and determines which is greater. The comparator implemented in this work is a clocked comparator as shown in Figure ‎3-8 [11]. The comparator resets at the positive half of the clock cycle, i.e. when the clock is high, such that both its outputs are reset to Vdd, and starts evaluation of the inputs when the clock goes low. For example, if the input Vi+ is smaller than the Vi- input, the transistor M1 has a larger overdrive voltage than M2 and causes more of the current from source, M12, to flow through it than M2. This larger current causes the node VL1 to charge up quicker than VL2, causing M4 to turn ON quicker than M3 (which are connected in a cross-coupled pair fashion), and in turn M4 pulls the node VL2 down even faster. The inverter pair, M9-M7 and M10-M8, then converts the VL1 and VL2 voltages to digital levels, Vdd and ground.  22   Figure ‎3-8: Clocked comparator [11] Finally, the area highlighted as SAR logic is the digital block that implements a finite state machine (FSM) that goes through the successive-approximation algorithm, and also controls the sampling of the analog input and the resetting of the capacitor array. The most important metric of the ADC for the operation of the controller is monotonicity. A monotonic ADC is one that guarantees that an increasing/decreasing analog input gives correspondingly increasing/decreasing digital output. This requirement is important to the hill-climbing algorithm implemented in this work. Consider the situation when the controller gives an‎ input‎ to‎ the‎MZI‎ switch’s‎ thermal‎phase‎ shifter‎ that‎brings‎ the‎ switch‎closer‎ to‎ the‎desired‎state, but the ADC is not monotonic. It would seem to the controller that the output it gave to the switch‎causes‎it‎to‎move‎away‎from‎the‎switch’s‎desired state, and the controller would adjust its output according to this false information. The monotonicity of a data conversion block such as an ADC is measured as the differential nonlinearity, DNL, of the ADC. Differential nonlinearity successively measures the 23  difference from one conversion level to the next and compares it to the ideal difference between those successive conversion codes, and reports the worst-case deviation. Ideally, the DNL would be zero, meaning that the actual difference between successive conversion levels is identical to the theoretical difference of 1 least-significant bit, LSB. The monotonicity of an ADC is guaranteed if its DNL is less than 1LSB, and is usually stated as follows:  |𝐷𝑁𝐿| < 1𝐿𝑆𝐵, (‎3-10)  3.1.3 Hill-Climbing Algorithm As shown in equations (‎2-6) and (‎2-7), and in Figure ‎2-2, the transfer function of the MZI switch is a raised cosine function of the form:  𝑃𝑜2𝑃𝑖=12[1 + cos(Δ𝜙)] =12[1 + cos (2𝜋𝐿𝜆Δ𝑛)]. (‎3-11) As described earlier in Section ‎2.2, the optical power at each of the MZI outputs is a sinusoidal function of the phase difference, ∆φ, introduced in the main section of the MZI. When the phase difference is achieved by sweeping the heater voltage using a VDAC, there exists only one maximum power point over one period of phase difference spanned by the VDAC codes. The shape of the transfer function also suggests that the slope of the curve on each side of the maximum point is monotonic. These facts can be leveraged in designing a simple hill-climbing algorithm to track the maximum power.  Assume the algorithm starts at‎point‎‘a’‎on‎the‎left‎side‎of‎the‎maximum‎point, where the slope of the curve is positive.  24   Figure ‎3-9: Simulated behavior of the hill-climbing algorithm with positive-slope operation (circles) and negative-slope operation (triangles) Assume that the algorithm has no prior information of the‎ position‎ of‎ point‎ ‘a’‎ on‎ the‎output curve.‎ The‎ algorithm‎ stores‎ the‎ value‎ of‎ the‎ curve‎ at‎ point‎ ‘a’‎ and‎ makes‎ a‎ random‎decision to step forward or backward as an initial guess. Assume that the initial guess is to take a step‎forward‎(to‎the‎right),‎and‎move‎to‎point‎‘b’.‎The‎algorithm‎then‎observes the new value of the‎curve‎at‎point‎‘b’‎and‎compares‎it‎to‎the‎stored‎value‎at‎point‎‘a’.‎This‎comparison‎allows‎the‎algorithm to know whether it is on a positive slope or on a negative slope. In this example, moving to the right is the correct decision in moving towards the peak of the curve. The algorithm then updates its‎ position‎ to‎ indicate‎ that‎ it‎ is‎ at‎ point‎ ‘b’,‎ and‎ takes‎ another‎ step‎forward, and so on until it reaches the peak of the curve. As the algorithm does not know the absolute location of the peak, it keeps moving forward, but the result would indicate that it is now moving on the negative slope of the curve. The algorithm again updates its current position, Output Optical Power (linear) VDAC Code a b 25  but it switches its moving direction to start going backwards. The algorithm keeps going backwards until it overshoots the peak and notices that taking a step backward leads to a lower point on the curve. This implies a movement on a negative slope, so the algorithm reverses its direction again. When the algorithm settles, the output oscillates around the peak of the curve. This dithering must be minimized in order to not degrade the extinction ratio of the switch, which is maximum at the peak. We mentioned earlier in section 3.1.1 that a resistive TIA experiences varying PD bias. This phenomenon can prove advantageous if the MPD gain increases with increased reverse-bias voltage across it, i.e. it gives more output current for the same amount of optical power incident upon it. For this case, let us imagine that the control algorithm is‎approaching‎the‎switch’s‎bar‎state,‎i.e.‎the‎peak‎of‎the‎MZI’s‎sinusoidal‎optical‎power‎at‎the‎bar‎output‎along‎a‎positive‎slope‎(either from the left of the peak while moving to the right or from the right of the peak point while moving left). The control algorithm now sees that the output signal of the PD is increasing upon moving closer and closer to the bar state, as well as moving in the correct direction results in‎larger‎increments‎in‎the‎PD’s‎output‎signal‎because‎the‎PD‎is‎now‎capable‎of‎providing‎more‎output current for the same increment in optical power. Now let us imagine that the control algorithm is‎moving‎along‎a‎negative‎slope‎of‎the‎MZI’s‎output curve (being on the right of the peak while moving rightward or being to the left of the peak while moving leftward). If the control algorithm keeps moving along this negative slope, then a decrease in the optical power incident upon the PD, due to a motion away from the bar state of the switch, causes the output current of the PD to decrease. This decreased PD current results in smaller reverse bias voltage seen by the PD, which decreases the gain of the PD, and in turn, decreases the output current of 26  the PD further. This behavior results in a positive feedback action from the PD, and while positive feedback is often undesirable in many systems due to potential for instability, positive feedback from the PD in a resistor TIA may be desirable. One can also think about the benefit of the‎PD’s‎positive‎feedback‎from‎the‎point‎of‎view‎that‎since‎the‎output‎optical‎power‎of‎the‎MZI‎switch is sinusoidal, the slope of the curve decreases close to the peak of the output power curve. When moving with constant increment along the curve, the resulting increments in optical power incident upon the PD get smaller and smaller near the peak of the curve. Thus, having positive feedback in the PD would effectively provide a zooming functionality that compensates for the decreasing‎slope‎of‎the‎switch’s‎transfer‎function. Nevertheless, the propensity of a resistor TIA to be loaded by the successive stage in the front end resulted in our decision to use an inverter-based TIA in this work.  3.1.4 Synthesized Controller The hill-climbing algorithm is implemented as a digital block. The algorithm is written in Verilog hardware-description language (HDL), and synthesized and laid out using an automatic place and route (P&R) tool. A standard cell library design provided by ARM Artisan is used for the 0.13µm CMOS process. 3.1.5 Digital-to-Analog Converter (DAC) The last block in the active controller, as seen in Figure ‎3-2, is the digital-to-analog converter (DAC). 3.1.5.1 Design After the controller processes the input of the TIA-LPF-ADC chain and determines how the switch is to be actuated in order to get it in the desired‎state,‎the‎controller’s‎output‎needs‎to‎be translated to a driving signal to be given to the MZI switch. Since the output of the controller 27  is a digital word, and the input to the MZI phase shifter is an analog signal, a DAC is needed. As the driving signal to the MZI switch can be either a current or a voltage, either a current DAC or a voltage DAC (VDAC) can be used. As shown in [10], a voltage-driving signal is preferred over a current-driving signal as it provides an additional degree of resistance to the effects of temperature variations. The justification for using a voltage signal instead of a current signal is that the electrical power, P, dissipated in a resistor is expressed as:  𝑃 =  𝐼2𝑅 =  𝑉2𝑅, (‎3-12) where I and V represent the current through, and voltage across the resistor, R, respectively. As mentioned in equation (‎2-5) earlier, the refractive index of silicon, nSi, increases with temperature, T, linearly. The resistance also increases with temperature [10]. Hence if the thermal heater of the switch is driven with a current signal, the power dissipated therein is:  𝑃 =  𝐼2𝑅 ∝ 𝑇, (‎3-13) Thus, the power dissipated in the resistor increases with temperature. This, combined with the linear increase of nSi with temperature, would exacerbate the effects of temperature variations on the performance of the switch. But‎if‎the‎MZI‎switch’s‎thermal‎heater‎is‎driven by a voltage signal, the power dissipated therein is:  𝑃 =  𝑉2𝑅∝1𝑇, (‎3-14) The power is now inversely proportional to temperature, while nSi is proportional to temperature, and hence the combination would result in a smaller effect of temperature variations on‎ the‎ switch’s‎ performance. Consequently, we decided to implement a VDAC as the output driver of the controller as shown in Figure ‎3-10.  28   Figure ‎3-10: M-bit Digital to analog converter with OPAMP-based voltage output stage It can be seen from Figure ‎3-10 that the same binary-weighted capacitor array, as used as the DAC in the SAR ADC described in section ‎3.1.2, is employed for the heater driver. This capacitor DAC (CDAC) is the main component which translates the digital word to an equivalent analog voltage at the top plate of the capacitors, VDAC.  The thermal phase shifter in the MZI switch acts as a resistive load, Rload. If this load was connected directly to the CDAC, it would start draining the charge accumulated at the top of the CDAC, and hence gradually decrease VDAC. Instead, an Opamp driving a PMOS-based controlled resistor drives the heater, as shown by the part highlighted in red in Figure ‎3-10. A resistive divider delivers a portion of the output voltage, Vout, as Vfdbk to the OPAMP. The relation between Vfdbk and Vout is:   𝑉𝑓𝑑𝑏𝑘 =𝑅1𝑅1 + 𝑅2𝑉𝑜𝑢𝑡. (‎3-15) The feedback resistors R1 and R2, are chosen based on two criteria: 1) The load seen at the output node is solely the resistance of the thermal phase shifter, Rload. Thus, R1 and R2 should be large such that their equivalent resistance does not make a current divider with Rload. 29  2) The MZI photonic switch is designed with a switching period that necessitates a heater voltage of 2 V. This is significantly higher than the nominal 1.2 V supply for the 0.13-µm CMOS process. Therefore, as seen in Figure ‎3-10, the OPAMP and PMOS, operating in a 2.5 V supply domain, are constructed using the thick oxide I/O transistors that are available in the CMOS process. But the CDAC is designed using regular transistors which operate with a 1.2 V supply. This necessitates an amplification circuit that scales the voltage of the CDAC, VDAC, from a range of 0 to 1.2 V to the range of 0 to 2.5 V. This scaling is done using the resistor divider. Equation (‎3-15) can be rewritten as:  𝑉𝑜𝑢𝑡𝑉𝐷𝐴𝐶= (1 + 𝑅2𝑅1), (‎3-16)  leading to:  1 +  𝑅2𝑅1=  2.51.2= 2.083 →   𝑅2𝑅1= 1.083. (‎3-17) 3.1.5.2 Simulation and Measurement Results  Figure ‎3-11: Simulated performance of the DAC 30  Figure ‎3-11 shows the simulated performance of the DAC when stimulated with a monotonically increasing digital sequence, which is effectively a sawtooth signal. The DAC is measured separately by driving it through the on-chip controller, by setting the controller to give monotonically rising or falling digital sequences to the DAC. Figure ‎3-12 and 3-16 show the measured output of the DAC when the controller feeds monotonically increasing and decreasing digital signal to the DAC, respectively. The DAC output does not span the same voltage range in the latter, when compared to the former. This is because the controller is programmed in such a way that if the DAC output keeps decreasing till (digital) zero, the controller resets its output to a digital value less than the maximum digital code, for example 1111 for a 4-bit controller. This design choice was made to‎avoid‎a‎situation‎where‎the‎particular‎MZI’s‎transfer‎function‎causes‎the algorithm to keep switching between very low and high output levels, but a possible drawback of this design choice is that the- hard coded- reset level does not land on a part of the MZI’s‎transfer‎function‎that‎contains‎the‎maxima‎of‎the‎transfer‎function‎without‎overflowing‎or‎underflowing the output of the hill-climbing algorithm. 31   Figure ‎3-12: Measured performance of the DAC with increasing input  Figure ‎3-13: Measured performance of the DAC with decreasing input 32  3.1.6 Simulated Closed Loop Operation of the CMOS Feedback Controller Figure ‎3-14 shows the simulation result of the CMOS feedback controller, consisting of the TIA, ADC, synthesized hill-climbing algorithm block, and DAC, when interfaced to a behavioral model of an MZI switch. A VerilogA model for the MZI is used for simulation. Since the VerilogA language does not support optical signals, the model calculates outputs of the MZI based on equations (‎2-6) and (‎2-7), but represent them using voltage signals. The MPD current to the TIA is modeled using a voltage-controlled current source (VCCS).  The simulated optical power at the through output port of the MZI when it is controlled by the CMOS controller is shown in Figure ‎3-14 where it can be seen that the closed-loop operation of the controller with the MZI results in gradual increase of the output power of the MZI before reaching the maximum value, followed by cycles where the output goes below the maximum value and then climbs back up, and so on. Figure ‎3-15 shows the waveform of the DAC’s output‎voltage‎to‎the‎MZI’s‎heater during closed-loop operation of the controller where it can be seen that the waveform starts with a sudden climb to an initial value, and then the output of the DAC becomes similar to a periodic triangular wave where the increasing portions of the output correspond to climbing up the hill, and the decreasing portions of the output correspond to a reversing‎of‎the‎controller’s‎climbing‎direction‎as‎was‎described‎in‎the‎discussion‎on‎the‎hill-climbing algorithm in section ‎3.1.3. The steady state behavior of the hill-climbing algorithm, as described in section ‎3.1.3, is toggling between two states around the desired peak of the MZI transfer curve, but the behavior seen in Figure ‎3-14 and Figure ‎3-15 shows that the output power of the MZI and the output voltage of the DAC stay in one state for few cycles before switching to another state. This seemingly suboptimal behavior is in fact expected due to two limitations: 33  1) DAC output resolution: the output of the DAC is stepped up in the voltage domain, and has a certain resolution determined by the reference voltage and the number of bits. But this voltage step may not be sufficient to cause detectable change in the output optical power, especially around the peak of the MZI’s‎ transfer‎ curve‎ since‎ its‎ slope‎ is‎ small‎around the peak. 2) Input‎ gain:‎ the‎ gain‎ of‎ the‎ controller’s‎ input‎ chain including the TIA gain and ADC resolution determine‎the‎minimum‎change‎of‎the‎MPD’s‎current‎that‎can‎be‎detected‎and‎then processed by the hill-climbing algorithm. Of these two factors, the latter is the bigger determinant of the steady-state toggling behavior of the hill-climbing algorithm, and if the gain in‎the‎controller’s‎input‎blocks is not sufficiently high, the hill-climbing algorithm will keep incrementing/decrementing its output until there is detectable change.  Figure ‎3-14: Simulated MZI output power during closed-loop operation of the CMOS controller  34   Figure ‎3-15: Simulated output of the DAC to the MZI heater It is noticeable from Figure ‎3-14 that during the climbing portion of the algorithm, the simulated output power of the MZI has some droop following a positive step, as highlighted in the figure. This droop can be explained by Figure ‎3-16, which shows a close-up of the simulated outputs of the VDAC shown in Figure ‎3-10. It can be seen from the simulation results that the output of the DAC also has a droop that is caused by leakage in the capacitor array voltage, which is only compensated at the next change in the digital code. For this reason, commercial VDACs such as the one in [15] use resistor network to perform the digital-to-analog conversion. 35    Figure ‎3-16: Simulated output voltage of the DAC nodes 3.1.7 Measurement of the Integrated Controller Figure ‎3-17 shows the die micrograph of the integrated controller. The biasing pads at the top connect the supply, ground, clock, ADC reference, and other inputs to the controllers. The die contains multiple controllers arranged in rows as highlighted by the box. The CDACs used in the ADC and VDAC are also highlighted on the picture. 36   Figure ‎3-17: CMOS chip micrograph Under ideal operating conditions, the output of the hill-climbing algorithm is either monotonically increasing or decreasing for a constant input. However, when we measured the behavior at a constant input current to the TIA, the output of the DAC did not consistently show monotonous behavior, but rather more closely resembled the expected closed loop operation of the system as it was going through periods of increasing output and periods of decreasing output, which is the expected behavior if the controller is receiving changing input and is correspondingly varying the output to compensate for this varying input. Nevertheless, we were able to excite the system to simulate the condition of a slow, square wave, input, which causes the controller to switch from an increasing output to a decreasing one, and vice versa. A transient capture of this measurement is shown in Figure ‎3-18. The portion of the figure highlighted in box‎‘A’‎shows‎a‎period‎where‎ the‎CMOS controller is receiving an unchanging input, and the direction of the hill-climbing algorithm is set to decreasing output, resulting in the output Biasing Pads 1 Controller Gnd pads DAC pad PD pad ADC CDAC DAC CDAC 37  waveform to be a decreasing sawtooth. At the end of this portion of the figure, the CMOS controller is stimulated with a changing input, and the portion of the figure within box ‘B’‎shows‎the resulting transition from the decreasing sawtooth waveform to an increasing sawtooth waveform. Finally, the controller is excited‎again‎at‎the‎end‎of‎time‎period‎‘B’‎and‎as‎a‎result‎the‎hill-climbing algorithm reversed the direction of the output, switching from an increasing to decreasing output at‎the‎transition‎between‎boxes‎‘B’‎and‎‘C’‎(where the controller is operating similar‎to‎the‎scenario‎described‎for‎box‎‘A’).  Based on these results we concluded that the CMOS controller would not work as expected from the simulations, and that the most likely reason is that the hill-climbing algorithm was program in such a way that it responded to changes in the actual value of the ADC conversion result without any implementation of digital filters to make the algorithm less susceptible to ADC noise. And as a result we decided to verify the validity of the hill-climbing algorithm with programmable logic, namely on an FPGA.  38   Figure ‎3-18: Open-loop transient measurements of the controller 3.2 Measurements with FPGA The CMOS chip did not lead to successful closed-loop measurements, as discussed at the end of section ‎3.1.7. In order to investigate the effectiveness of the hill-climbing algorithm, and in order to find out what modifications are needed in either the algorithm or in the circuitry of the controller, the hill-climbing algorithm is further tested in conjunction with an 12 MZI switch (as shown in Figure ‎3-1) using an Altera MAX10 FPGA board with on-chip ADCs and on-board VDACs (development kit options).   A B C 39   Figure ‎3-19: Test setup for automatic tuning and control of 12 MZI switch with the hill-climbing algorithm using an FPGA board [setup and measurements done by Ray Chung]. Figure ‎3-19 shows the setup used to test the hill-climbing algorithm on an Altera Max10 FPGA development board. The light exiting one of the outputs of the MZI switch is coupled to a benchtop optical receiver that has an on-board PD and TIA. The output from the receiver is then sampled by the FPGA’s on-chip ADC, filtered by HDL-described digital filters, and passed to the hill-climbing algorithm. The output of the algorithm block is sent to an on-board VDAC whose output is buffered before connecting it to the thermal phase shifter of the MZI switch. Figure ‎3-20 (b) shows the measured heater voltage while the tuning loop is active, and Figure ‎3-20 (a) illustrates the switching behavior of the 12 switch and the starting and settling point of the algorithm. MZI Switch with Thermal Phase Shifters 40   (a)  (b) Figure ‎3-20: Automated tuning of a 12 MZI with hill-climbing algorithm on FPGA: (a) progression of the algorithm on the MZI switching spectrum, and (b) oscilloscope capture of the voltage to the MZI heater [Results obtained and plotted by Ray Chung] 41  The algorithm is also implemented with and without digital filtering at the output of the controller, and it is observed that the setup that did not use filtering on the output achieved better results in terms of the extinction ratio of the MZI switch, as can be seen from Figure ‎3-21 and Table ‎3.1. Table ‎3.1 reports two sets of extinction ratios and heater voltages. As shown in Figure ‎3-21 (b) and (d), the extinction ratio has multiple peaks, which are highlighted by the dashed lines.  Figure ‎3-21: Tuning results of 12 MZI with hill-climbing algorithm on FPGA: (a) Transient of heater voltage and (b) achieved average extinction ratio with DAC digital filtering. (c) Transient of heater voltage and (d) achieved average extinction ratio without DAC digital filtering [results and plots by Ray Chung] Avg. steady-state heater voltage 42  Table ‎3.1: Heater voltage and achieved extinction ratio with and without digital filter at the output [ack: Ray Chung] Digital filter at the DAC output? Yes  No Average of Heater voltage, Vheater 0.443 V 0.828 V 0.458 V 0.83 V Average extinction ratio achieved 19 dB 29 dB 34 dB 30 dB  43  Chapter 4: Automated Tuning Structure for a 22 MZI Switch In chapter 3, we described automatic tuning and control for a 1-input, 2-output optical switch. In this chapter, we propose a structure that assists in implementing automated tuning for a 2-input, 2-output optical switch. First, we introduce the proposed design, and then present its simulation and measurement results. 4.1 Need for 22 Switch Tuning Figure 4.1 shows how a single MZI switch can be used to perform switching action on two simultaneous inputs, I1 and I2, at different wavelengths. As mentioned in section ‎2.2, either one or both arms of the MZI can have a phase-shifting element; e.g. a thermo-optic phase shifter. The bar state of this 22 switch means that I1 is routed to output arm O1 and input I2 is routed to output arm O2, while the routing is reversed in the cross state.   Figure ‎4-1: 2x2 MZI optical switch with thermo-optic phase tuners Figure 4.2 shows the 22 switch with the monitoring approach as described in chapter 3.   Figure ‎4-2: 22 MZI switch with a monitoring-tap and MPD 44  Assume that the insertion loss through the switch, i.e. from input arm, to input coupler, to middle section waveguides and phase shifters, to output coupler, is wavelength insensitive. Thus, both light beams I1 & I2 undergo the same insertion loss from input to output arms. When the switch is tuned to route a certain amount of light beam I1 from one output arm to the other, a similar amount/intensity of light beam I2 is simultaneously routed in the opposite direction. As a result, the intensity of the total amount of light exiting each output arm of the switch remains constant, even though the wavelength composition of each output light beam changes. In other words, the two outputs of the switch have the same optical intensity regardless of the state of the switch. The performance of the MPD is independent of the wavelength (over a certain range of wavelengths), or in other words, once the optical signal reaches the PD, wavelength information is lost. So if an MPD is used as the sole monitoring apparatus, as in Figure ‎4-2, then any wavelength information is lost, the optical power delivered to this MPD does not change with the state of the 22 MZI switch, and the active control method as described in Chapter 3 does not have the requisite information to make a decision. A wavelength sensitive monitoring method is therefore needed to properly tune the switch. 4.2 Proposed Design The need for a wavelength sensitive monitoring method for a 22 switch suggests a solution involving interferometry as the underlying principle. Interference is a wavelength-sensitive phenomenon where optical signals that have the same wavelength can interfere with each other, undergoing constructive or destructive interference, provided they are coherent, i.e.,  each signal has a well-defined and predictable phase relation [13]. Optical signals at different wavelengths do not interfere, even if they are coherent, but rather they produce a beating pattern 45  with a frequency equal to the difference of frequencies of the optical signals [14]. For example, if two optical communications channels are separated by 1nm, this corresponds to a difference of their frequencies of 100GHz, which will be filtered out by the detection system. This property permits multiple wavelengths to propagate down a single optical waveguide, without data on one wavelength corrupting data on a different wavelength.    Figure ‎4-3: Proposed MZI switch with nested feed-forward monitoring interferometer Figure ‎4-3 shows the proposed device, with boxes highlighting the 22 MZI switch and the proposed design. The new design constitutes of a nested interferometer that is in parallel with the MZI switch. We refer to this nested interferometer as the monitoring interferometer (MI). One input to the MI is tapped off from one of the inputs to the main MZI switch (e.g. using the optical tap on arm 1), in which optical beam I1 at‎wavelength‎λ1 flows into. The second input to the MI is tapped off from one of the outputs of the main MZI switch (e.g. using the optical tap at arm 3). For ease of optical routing, this output arm (arm 3) is preferably chosen as the output arm that is in-line with the input arm (arm 1). If the main MZI switch is configured in the bar state, i.e. to route all the input light in arm 1 to output arm 3, then both inputs to the MI are at the same wavelength,‎λ1. Conversely, if the switch is in the cross state, where the input from arm 1 at‎wavelength‎λ1 is routed to output arm 46  4, then the inputs to MI are either of different wavelengths (e.g. if there was input light I2 at wavelength‎λ2 propagating into arm 3), or of the same wavelength, but the input to the second MI arm (arm 6) has very low, ideally zero, intensity since it is tapped off from arm 3 of the switch which ideally does not have any of I1 propagating in it. In the case where both inputs to the MI are of the same wavelength, these two inputs can undergo constructive and destructive interference depending on the relative phase difference between them, and this interference pattern is periodic with a period of 2π radians. In constructive interference the two inputs to the MI reinforce each other and the resulting intensity is maximized at the output of the MI, and in destructive interference the two inputs negate each other resulting in minimized optical intensity at the output of the MI. As is the case in the main MZI, a phase shifting element is inserted in the path of the first (or second) input to the MI to be able to control the relative phase difference between the two inputs. If the relative phase difference between these two arms through the phase shifter spans through 2π or more, then a constructive as well as a destructive interference point manifest in the output of the MI. So if the phase shifter in the MI is excited with a periodic signal whose amplitude is sufficient to cover 2π or higher relative phase shift between the two arms, then the output of MI is also a periodic signal with amplitude that is dependent upon the extent of interference happening between the two inputs of MI. On the other hand, when the main MZI switch is in the cross state, the input to arm 5 of the MI does not change while the input to arm 6 is small, ideally zero, which means that the output of the MI is predominated by the light in arm 5 instead of the combination of arm 5 and arm 6. As a result, the difference between constructive and destructive interference is very small. 47  Thus, in the case of a single input I1 at λ1 to the main switch, when the main MZI switch is in the bar state, the output of the MI has maximum amplitude when the phase shifter in the MI is driven with a periodic signal. Conversely, the output of the MI would have minimum amplitude when the main switch is in the cross state, for the same periodic electrical signal applied to the phase shifter in the MI. Now consider the situation when the main switch has two input light beams, as shown in Figure ‎4-3. Bar state of the switch means that light beam I1 exits at arm 3 and light beam I2 exits at output arm 4, while the cross state of the switch means that light beam I1 exits at arm 4 and light beam I2 exits at arm 3. In the bar state, the two inputs to the MI would be at the same wavelength, and the operation of the MI would be similar to the case described earlier with a single input beam to the main switch at bar state. The operation is depicted in Figure ‎4-4.  However, in the cross state, the inputs to the MI have high intensity but at different wavelengths.‎So‎applying‎a‎periodic‎driving‎signal‎to‎the‎MI’s‎phase‎shifter,‎even‎with a swing to cause 2π or higher phase shift in the first input of the MI, does not result into constructive and destructive interference patterns between the two inputs of the MI. As a result, even if the Bar State Operation Time I PD Max Self-Interference I1 I2 Figure ‎4-4: Operation of the proposed 2x2 switch in the bar state 48  average‎of‎the‎MI’s‎output‎is‎at‎high‎intensity because both its inputs are at high optical power intensity, the amplitude of this output is minimum due to the lack of constructive and destructive interference. The operation of the switch in the cross state is depicted in Figure ‎4-5.  Figure ‎4-5: Operation of the proposed 2x2 switch in the cross state 4.3 Simulation Results A model of the proposed switch is constructed in Lumerical INTERCONNECT optical circuit simulation tool. Input I1 of the switch is fed from a 1550nm and input I2 from a 1540nm source. The outputs of the switch – the two output arms of the main switch and the output of the MI, are connected to an optical spectrum analyzer (OSA) input to analyze the wavelength and optical power of each output. A closer depiction of the model is shown in Figure ‎4-6.  Figure ‎4-6: Lumerical INTERCONNECT simulation model Cross State Operation Time I PD Min Self-Interference I1 I2 49  The simulation sweeps the voltage input to the thermal phase shifters in the main section of the MZI switch while applying a periodic (sinusoidal) waveform to the phase shifter in the top arm of the MI.  (a)  50  (b)  (c) Figure ‎4-7: Simulation sweeps for the proposed switch. (a) Output of the MI arm, (b) output of the bar arm, and (c) output of the cross arm [Acknowledgment: Ray Chung] Figure ‎4-7 shows the simulation results where the voltage to the heaters is varied linearly from 0 to 4V. It can be seen that in addition to the expected periodicity of the outputs of the MZI switch, the output of the MI is also periodic. 51   (a)  (b) 52   (c) Figure ‎4-8: Simulation sweep results for the bar state. (a) optical power and spectrum of MI's output (b) optical power at output 1 of the switch (c) optical power at output 2 of the switch [Acknowledgment: Ray Chung] Figure ‎4-8 shows a similar simulation sweep, but the voltage applied to the thermal phase shifters is swept from 0 V to the bar state voltage of 2.05 V. Figure ‎4-8 (a) shows the optical power at the output of the MI. At the steady state, i.e. when the voltage to the heaters settles at 2.05 V, the 1550 nm wavelength (green) has a maximum swing, even though its average power level is not at its maximum, while the 1540 nm wavelength (blue) is at its minimum. Figure ‎4-8 (b) shows the power and wavelength at output arm 1 of the switch. At steady state, the 1550 nm wavelength is at its maximum value, while the 1540 nm wavelength has little power. It should be noted that the maximum level of the 1550 nm wavelength is less than that of the 1540 nm wavelength because the tap at the input of the switch takes some power from the 1550 nm wavelength input. 53   (a)  (b) 54   (c) Figure ‎4-9: Simulation result for the cross state: (a) optical power and spectrum of MI output (b) optical power at output 1 of the switch, and (c) optical power at output 2 of the switch [Acknowledgement: Ray Chung] Figure ‎4-9 shows the same simulation sweep, but this time the voltage being applied to the thermal phase shifters is swept from 0 V to the cross state voltage of 3.1 V. Figure ‎4-9 (a) shows the optical power at the output of the MI where it can be seen that at steady state, the 1550 nm wavelength (green) has minimum swing, even though its average power level is not at its minimum, while the 1540 nm wavelength (blue) is at its maximum. Figure ‎4-9 (b) shows the power and wavelength at output arm 1 of the switch. At steady state, the 1550 nm wavelength is at its minimum value, while the 1540 nm wavelength is at its maximum. 4.4 Measurements and Tuning Results The proposed device of Figure ‎4-3 is fabricated in an electron-beam (e-beam) fabrication facility for preliminary proof of concept. Because the e-beam process does not support active 55  components such as PIN phase shifters and PDs, a different version of the design is then submitted for fabrication on a multi-project wafer (MPW) run to IME. 4.4.1 Measurements of the e-beam Chip The device is constructed as shown in Figure ‎4-10, and a micrograph of the fabricated chip is presented in Figure ‎4-11. Since the e-beam process has metal resistive heaters, but does not have active components such as PDs and PIN phase shifter, the e-beam design uses a heater as the dithering phase shifter in the MI. The inputs and outputs of the MZI switch, as well as the output of the MI, are routed to input/output grating couplers.  Figure ‎4-10: Layout of feedforward switch submitted for fabrication using e-beam technology [Layout done by Zeqin Lu] 56   Figure ‎4-11: Micrograph of the feedforward switch on the e-beam PIC   (a) Heaters Thermal dithering phase shifter 57   (b)   (c) Figure ‎4-12: Measurement results of the e-beam feedforward switch: (a) Output of monitoring interferometer while sweeping switch heater voltage (DC-coupled), (b) AC-coupled signal from (a), and (c) switching spectrum of the main switch showing bar state at 2.05 V and cross state at 2.8 V [Acknowledgement: Ray Chung and Hasitha Jayatilleka] Bar State @ ~ 2.8V Bar State @ ~ 2.8V Cross State @ ~ 2.05V Cross State @ ~ 2.05V 58  Figure ‎4-12 shows different measurement results from the e-beam chip. Figure ‎4-12(a) shows the full output of the MI resulting‎from‎applying‎a‎periodic‎waveform‎to‎the‎MI’s‎phase‎shifter‎while‎linearly‎sweeping‎the‎MZI‎switch’s‎heater‎voltage,‎which‎includes‎the‎DC‎variation‎in‎ the‎MI’s‎output.‎Figure ‎4-12 (b) shows the same output but AC-coupled to remove the DC variations. Figure ‎4-12(c) shows the switching spectrum of the switch. It can be seen from Figure ‎4-12(b) and (c) that the cross state of the switch aligns with the minimum swing of the MI’s‎output,‎while‎the‎bar‎state‎of‎the‎switch‎aligns‎with‎the‎maximum‎swing‎of‎the‎MI’s‎output. It is noticed from Figure ‎4-12 (b) that the measured swing of the optical power at the output of the MI does not go to zero as predicted in the simulation results of Figure ‎4-9 (a). A viable explanation is that this swing is due to noise from the measurement equipment such as power-supply noise from the bench-top optical receiver or noise from the oscilloscope itself, where these noise sources become more pronounced when the signal amplitude becomes low. We do not attribute this swing to our system implementation, because the phase shifter in the monitoring arm is thermo-optic, i.e. without any dithering-signal dependent optical loss, as may be the case with a charge-injection phase shifter. 4.4.2 Measurements of the MPW Chip This section describes the measurement results of the MPW chip tuned automatically using an automatic feedback controller built using off-the-shelf components and an FPGA board.  59   Figure ‎4-13: Layout of MPW feedforward switch cell [Layout done by Zeqin Lu] Figure ‎4-13 shows the layout of the feedforward switch with pad and component labels, and Figure ‎4-14 shows a picture of the fabricated chip along with the wirebonds to the pads. Two PIN phase shifters are included in the MI – one to introduce the dithering signal, and another acting as a dummy to ensure balance between the two arms of the MI. MPD Gnd Dithering PIN Heater 1 Heater 2 Dithering PIN pads MPD pads Heaters Dummy PIN 60   Figure ‎4-14: Micrograph of fabricated feedforward switch with wirebonded pads  Figure ‎4-15: Feedforward switch measurement setup Gnd Heaters Dithering PIN MPD Dummy PIN 61  Figure ‎4-15 shows the measurement setup. Light is coupled into and out of the PIC using a fiber array for purposes of fiber alignment and measuring the response of the main switch.  The PIC is glued onto a PCB, as shown in Figure ‎4-16, and the pads that connect to the thermal phase shifters of the main switch, the PIN phase shifter of the MI, and the monitor PD, are all wirebonded to pads on the PCB that are routed to header pins.   Figure ‎4-16: Picture of the PIC-on-board setup and coupling fiber array This chip-on-board configuration results in easier testing and reliable results. It is easier to test because the whole board is easier to move and connect to, as compared to landing probes onto the chip pads. Furthermore, the‎ PCB’s‎ header‎ pins‎ are‎much more resilient to repeated connection‎ and‎ disconnection‎ than‎ the‎ PIC’s‎ pads‎ to‎ repeated‎ probing.‎ In‎ our‎ setup and alignment procedure, the stage upon which the PCB is placed is connected to computer-controlled servo motors, and can be moved in two lateral directions, while the fiber array can only move up and down. The probes, on the other hand, can only be fixed to the testing station isolation table, and cannot move simultaneously with the station holding the PCB. Our two-stage alignment process starts with a manual, visual, coarse alignment that gets the fiber array carefully‎close‎to‎the‎PIC’s‎surface‎and‎relatively‎close‎to‎the‎alignment‎grating‎couplers.‎This‎is‎62  then followed by a computer controlled fine-alignment step where a program controls the servo motors of the stage to find the position that results in the best coupling, as measured by the detected optical power from the output grating coupler. If we were to probe the chip, then we either land the probes before or after the fine-alignment process. If we land the probes before the fine-alignment step, then the fine-alignment step would move the stage while the probes are connected‎to‎the‎PIC’s‎pads,‎which‎is‎very‎likely‎to‎damage‎the pads, the probes, or both. On the other hand, if we land the probes after the fine-alignment step then the lateral force that results from establishing a good probe connection may move the PIC laterally, rendering the fine alignment futile. Figure 4-17 presents the static performance of the switch through its switching spectrum, i.e.‎the‎plot‎of‎the‎switch’s‎states‎versus‎the‎heater‎power.  Figure ‎4-17: Switching spectrum of the main MZI switch Through port Cross port 63   Figure ‎4-18: MPD output current vs. heater power at 0V dithering input The output current of the MPD is shown in Figure ‎4-18 as a function of the heater power. The MPD output current can reach a maximum or minimum at points that correspond to neither the bar state nor the cross state of the switch. This further illustrates the point described earlier, and depicted in the simulation results in Figure ‎4-8 and Figure ‎4-9, that monitoring the static value of the MPD current is not necessarily indicative of the desired switch state. This in turn calls for the detection of the MPD current swing. (µA) 64   Figure ‎4-19: Optical output power of the switch and measured MPD current swing due to dithering signal Figure ‎4-19 shows the measured optical power of the main switch at its cross and bar outputs ( shown by green and blue curves, respectively), as well as the calculated swing of the PD current, defined as the difference between the maximum and minimum measured MPD current. The maximum and minimum PD current indeed aligns with the bar and cross state of the switch, respectively. The output current of the MPD, with a typical value of less than 1 µA, is amplified and converted to voltage using a simple resistor, R, as a TIA followed by a unity-gain buffer, as shown in Figure ‎4-20. The buffer isolates the MPD from the controller circuits and also provides the drive capability for those circuits due to its low output impedance and the wide output range of the opamp. A quad-opamp LM324 IC chip is used.  Through port Cross port 65   Figure ‎4-20: Resistor TIA with a unity-gain buffer However, this simple resistor based TIA suffers from a signal-dependent bias voltage as described earlier in Chapter 3. A resistive-feedback TIA, similar to the one shown earlier in Figure ‎3-4, is therefore used next. As shown in Figure ‎4-21, the feedback in the circuit forces the voltage at the negative terminal of the OPAMP, V-, to be equal to Vbias, and this V- appears as the reverse bias voltage of the MPD. As a result, this circuit allows for a signal-independent biasing of the MPD.  Figure ‎4-21: Resistive-feedback TIA with biasing 66   Figure ‎4-22: Transient capture of the dithering signal applied‎to‎the‎MI’s‎phase‎shifter‎and TIA output voltage at bar state of main switch Dithering Signal TIA Output 67   Figure ‎4-23: Transient capture of dithering signal applied‎to‎the‎MI’s‎phase‎shifter‎and TIA output voltage near cross state of main switch Figure ‎4-22 and Figure ‎4-23 show oscilloscope capture plots of the dithering signal applied to the PIN phase shifter of the MI and the output of the TIA. At the bar state of the switch, the swing of the MPD current, and hence the swing of the TIA output is maximized. For the cross state, the results are opposite. The output of the TIA is then connected to the FPGA board, where it is sampled by the on-board  ADC at a 1 MHz sampling rate. Since the monitoring metric is the swing of the TIA output signal, the processing block in Figure ‎4-15 goes through a sufficient number of ADC conversion outputs to cover few periods of the TIA output signal. It detects the maximum and minimum values of the waveform, and calculates the swing thereof. This swing value is then Dithering Signal TIA Output 68  forwarded to the hill-climbing algorithm, which in turn feeds its decision to the on-board 16-bit VDAC. Finally, the output of the VDAC is connected to the MZI heater via the specific PCB header pin. Figure ‎4-24 shows the tuning results of the feedforward switch. Two sets of measurements are done, one with averaging the output of the hill-climbing algorithm to the DAC, shown in Figure ‎4-24 (c) and (d), and one without such averaging, shown in Figure ‎4-24 (a) and (b). For each set we let the controller run for 10 minutes and capture the optical power read by a power meter every second, and also plot a histogram of the calculated extinction ratio. The histogram distributions show that the results obtained without output averaging are better, with an average ER of > 20 dB.  (a)  (c) Through Port Cross Port Transient of output optical power during tuning  Transient of output optical power during tuning 69   (b)  (d) Figure ‎4-24: FPGA tuning of feedforward switch (a) and (b) without DAC output averaging, and (c) and (d) with DAC output averaging  Extinction Ratio (dB) Extinction Ratio (dB) Histogram of Extinction Ratio Histogram of Extinction Ratio 70  Chapter 5: Conclusion In this chapter, we present some concluding remarks and discuss opportunities for future work. 5.1 Concluding Remarks In this thesis, we have presented techniques to automatically tune MZI-based photonic switches using electronic feedback. First, a CMOS-based integrated system is proposed for the automatic tuning of a 12 MZI switch employing a hill-climbing algorithm. Simulation results for the overall system are presented, and measurement results of individual components are also shown. Due to errors in the synthesized digital circuits, the entire IC prototype did not work as expected. The system was then replicated using an FPGA board with on-board ADC and DACs and the operation of the hill-climbing algorithm was successfully verified. FPGA measurements with the photonic chip demonstrated that a very good stabilization performance of the switch using the proposed algorithm can be achieved, with an average extinction ratio of more than 30 dB. A feedforward structure is then presented for a 22 MZI photonic switch, and techniques to monitor and tune this switch using hill-climbing algorithms are proposed. Simulation and measurements results from two fabricated PICs along with automatic tuning using an FPGA board successfully demonstrate the proposed concepts. Preliminary results show that an average extinction ratio of 20 dB or higher is achieved with automatic tuning. 5.2 Comparison with Existing Works Because of their importance for modulation and switching applications, MZI device stabilization approaches have been proposed before, and here we briefly compare some proposed solutions to our own hill-climbing approach. 71  The approach proposed in [16] is geared towards QPSK Mach-Zehnder Modulators (MZMs) and it depends on dithering the bias voltages and detecting the average optical power as well as the low-frequency (integrated RF) power to determine the appropriate bias voltages for the desired bias point of the whole modulator. The authors were able to stabilize the QPSK modulator operating at 12.5 GSym/s with about 1dB eye-power penalty. This approach aimed to bias the modulator at the quadrature point, i.e. the 90o point, on the MZI transfer function, which has the highest slope, so there is an inherent benefit in that a small dithering amplitude at the bias voltage produce large changes in the output optical power. Additionally, the authors needed an MPD with 750 MHz bandwidth along with an RF detector, in addition to the low-frequency detector, to implement their approach. In our proposed approach, we only use the low-frequency detector components such that the high-bandwidth components are not required, and consequently can have reduced area and power consumption. The approach proposed in [17] is also a dithering signal approach, but the monitoring signal in this approach is a ratio between the average output optical power and the first harmonic of the dithering signal. The advantage of this approach is that it does not need high-speed components and that since the monitoring signal is a ratio, it is less sensitive to fluctuations of the input power. However, the method of detecting the amplitude of the first harmonic of the dithering signal may present a challenge, as the authors only demonstrated their approach by obtaining this component from the spectrum of the MPD current using a 128-point Fast Fourier Transform (FFT), which adds complexity to system implementation. The work presented in [18] is demonstrated for MZI switches and aims to tune a switch network to avoid paths of excess loss. It first maps‎the‎states‎of‎the‎fabric’s‎building‎units‎to‎the‎driving voltages needed. When the optical power exiting a certain path falls below a threshold, 72  the algorithm then tries to switch that signal to a lower loss path. The disadvantage of this approach is that the saved values are not adjusted with variation in temperature. Another disadvantage is in the need to define a threshold. Finally, the approach proposed in [19] is very similar to our proposed approach in that it extracts the low-frequency information of the output optical signals and adopts a mixed-signal approach to implement the tuning method. But the approach proposed uses look-up tables to choose the best tuning parameters, which is disadvantageous since it does not adapt to fluctuations in temperature. 5.3 Future Work Next, we discuss some future research opportunities to extend the scope of this research. 5.3.1 Integrated Controller Based on the measurements with the FPGA board and discrete components, a redesign of the controller on an integrated circuit with additional filtering in the digital domain is suggested for the entire system to work in an IC prototype. 5.3.2 Controller Design for Scaled-Up Switch Fabrics An interesting area for future work is to investigate modifications or redesign of the proposed control system to target large-scale NN switch fabrics, where N can be 32, 64 or even larger. One research trend in the design of MZI switch is to decrease its footprint so that larger switch matrices occupy as small of an area as possible. Correspondingly, the switch stabilization controller must also shrink in size, and preferably occupy the same footprint as the MZI switch cell in a flip-chip assembly. One major contributor to the overall footprint of an MZI switch cell 73  is the size and pitch of the pads that interface the PD output current and the phase shifters input voltage.   Figure ‎5-1: Illustration of an MZI cell (green) and IO pads (brown) Assuming flip-chip co-packaging of the CMOS chip containing the integrated controllers and the PIC, Figure ‎5-1 illustrates a possible layout and pad placement of a CMOS controller (green area) that matches the estimated size of an MZI cell. There are four pads in the figure for the following connections:  PD current input to the CMOS controller,  DAC output to the heater on the PIC,  State input indicating the state of the MZI (bar/cross) that the controller should tune/optimize to, and  A common pad that is shared between multiple adjacent controllers. For example, one use of such shared pad is routing supply, ground, or clock signals needed by the controllers. A further optimization of the pad count can be done by replacing state pads for each controller with a serial-to-parallel interface for the whole CMOS chip that takes 74  in the desired state for each controller serially and distribute them to the individual controllers locally on the CMOS chip. Figure ‎5-2 shows a possible chip-level implementation of a CMOS chip containing eight individual controllers. Although that the figure includes both individual state pads as well as five scan pads, practically only one of these two options need to be used.   Figure ‎5-2: Possible implementation of a CMOS chip containing 8 controllers As the optical signals propagate through the switch matrix, they accrue additional loss with each stage/cell in the switch matrix. This means that the available optical power that can be monitored, and hence the maximum output PD current keeps decreasing. Thus, another venue for further research is the investigation of wide dynamic range optical front-end receivers for the controllers, or new automatic gain control schemes.   75  Bibliography [1] M. W. AlTaha, S. Nayak, H. Jayatilleka, S. Shekhar and S. Mirabbasi, "Silicon-photonic devices: electronic control and stabilization," 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Vancouver, BC, 2016, pp. 1-4. [2] L. Chen, E. Hall, L. Theogarajan and J. Bowers, "Photonic switching for data center applications," in IEEE Photonics Journal, vol. 3, no. 5, pp. 834-844, Oct. 2011. [3] L. Chrostowski and M. Hochberg, Silicon Photonics Design. Cambridge University Press, ch. 7, May 2015. [4] G. T. Reed, Silicon Photonics: The State of the Art. John Wiley & Sons, Ltd, ch. 7, 2008. [5] G. T. Reed and A. P. Knights, Silicon Photonics: An Introduction. John Wiley & Sons, Ltd, ch. 6, 2004. [6] M.‎ Nedeljkovic,‎ R.‎ Soref,‎ and‎ G.‎ Z.‎ Mashanovich,‎ “Free-carrier electrorefraction and electroabsorption modulation predictions for silicon over the 1–14um infrared wavelength‎range,”‎IEEE Photonics Journal, vol. 3, no. 6, pp. 1171–1180, 2011. [7] D. Patel, S. Ghosh, M. Chagnon, A. Samani, V. Veerasubramanian, M. Osman, and D. V. Plant,‎ “Design,‎ analysis,‎ and‎ transmission system performance of a 41 GHz silicon photonic modulator,”‎Opt. Express, vol. 23, no. 11, pp. 14263–14287, 2015. [8] M. Jamal Deen and P. K. Basu, Silicon Photonics: Fundamentals and Devices. John Wiley & Sons, Ltd, ch. 7, 2012. [9] A. H. Ahmed, A. Sharkia, B. Casper, S. Mirabbasi and S. Shekhar, "Silicon-photonics microring links for datacenters – challenges and opportunities," in IEEE Journal of Selected Topics in Quantum Electronics, vol. 22, no. 6, pp. 194-203, Nov.-Dec. 2016. 76  [9] K. Padmaraju and K. Bergman,‎“Resolving‎the‎thermal‎challenges‎for‎silicon‎microring‎resonator‎devices,”‎Nanophotonics, vol. 2, no. 4, pp. 1–13, Sep. 2013. [10] S. Nakamura, et‎ al.,‎ “High‎ extinction‎ ratio‎ optical‎ switching‎ independently‎ of‎temperature with silicon‎photonic‎1‎x‎8‎switch”,‎OFC‎2012. [11] W.‎Guo,‎“A‎low-power 10-bit 50 MS/s CMOS successive approximation register‎ADC,”‎M.A.Sc. Thesis, University of British Columbia, Vancouver, Canada, 2012. [12] D. Celo, et al., "Thermo-optic silicon photonics with low power and extreme resilience to over-drive," 2016 IEEE Optical Interconnects Conference (OI), San Diego, CA, 2016, pp. 26-27. [13] G. T. Reed and A. P. Knights, Silicon Photonics: An Introduction. John Wiley & Sons, Ltd, ch. 1, 2004. [14] C. K. Madsen and J. H. Zhao, OpticalFilter Design and Analysis: A Signal Processing Approach. John Wiley & Sons, Ltd, ch. 2, 1999. [15] Texas‎ Instruments,‎ “16-Bit, Ultralow-Glitch, Voltage-Output‎ Digital‑to‑Analog‎Converter,”‎DAC8551‎datasheet,‎Apr.‎2005‎[Revised‎Feb. 2017]. [16] P.‎ S.‎ Cho,‎ et‎ al.,‎ “Closed-loop‎ bias‎ control‎ of‎ optical‎ quadrature‎ modulator,”‎ IEEE Photon. Tech. Lett., vol. 18, no. 21, pp. 2209–2211, Nov. 2006  [17] Y. Li, et‎ al.,‎ “Any‎ bias‎ point‎ control‎ technique‎ for‎Mach–Zehnder‎Modulator,”‎ IEEE Photon. Tech. Lett., vol. 25, no. 24, pp. 2412–2415, Dec. 2013. [18] C. P. Chen, et al., “Programmable Dynamically-Controlled Silicon Photonic Switch Fabric,” in Journal of Lightwave Technology, vol. 34, no. 12, pp. 2952-2958, June15, 15 2016. 77  [19] L. Chen, et al., “Photonic Switching for Data Center Applications,” in IEEE Photonics Journal, vol. 3, no. 5, pp. 834-844, Oct. 2011. 78  Appendices  Appendix A   : Hill-Climbing Algorithm Verilog Codes This appendix contains the Verilog codes that implemented the hill-climbing algorithm and assisting blocks such as a comparison block. A.1 Hill-Climbing Algorithm Verilog Code module hillClimbing(reset, clk, curr_level, dac_out, cap_rst, adc_enable);  //Define parameters  parameter bits = 7;  //State parameters  parameter heat=1'b1, cool=1'b0, sample_state = 2'h1, compare_state= 2'h2, output_state = 2'h0, wait_state = 2'h3;  //Define inputs and outputs  output [bits-1:0] dac_out;  output adc_enable;  output cap_rst;  input clk, reset;  input [bits-1:0] curr_level;  wire compare_local; //output carry_local used to determine local comparison  wire compare_global;//output carry_local used to with global comparison  wire nxt_dac_state;  wire lclk;  wire rst;  reg [bits-1:0] tmp_lcl; //temp local   reg [bits-1:0] tmp_glbl; // temp global  reg [bits-1:0] tmp_dac_out; //temp dac output  reg dac_state; // state of DAC, either heat or cool  reg [1:0] state; //state of the algorithm  reg first_time;  reg cap_rst; // reset the top plate of the capacitor bank  reg [bits-1:0] tmp_current;  reg adc_enable;  reg [bits-1:0] count;  //Component Instantiation  //compare_block: compares current level with local and global values and produces 2 flags  compare_block compare (.curr_lvl (tmp_current), .local (tmp_lcl), .global (tmp_glbl),                         .compare_lcl (compare_local),                         .compare_glbl (compare_global)); 79   // clock divider block: divide by 8                         clkdivider_8 clock_divider (.clk(clk), .clk8(lclk), .reset(reset), .ctrlr_rst (rst));  // Combinational assignment statements  assign dac_out = ~tmp_dac_out; //output needs to be inverted for the DAC's switches  assign nxt_dac_state = (dac_state ^ compare_local);  // rising clock edge process  always @(posedge lclk)  begin //begin 2    if (rst == 1'b1)     begin      tmp_lcl <= 7'b0;      tmp_glbl <= 7'b0;      tmp_dac_out <= 7'b0;      dac_state <= heat;      state <= output_state;      first_time <= 1'b1;      cap_rst <= 1'b1;      tmp_current <= 7'b0;      adc_enable <= 1'b0;      count <= 7'b0;     end    else     begin     case (state)                                                  //case 1     sample_state: //during this cycle the ADC is doing the conversion       begin  //begin 3        state <= compare_state;        tmp_lcl <= tmp_current;        dac_state <= dac_state;        tmp_dac_out <= tmp_dac_out;        tmp_glbl <= tmp_glbl;        cap_rst <= 1'b0;        first_time <= first_time;        tmp_current <= tmp_current;        adc_enable <= 1'b1;        count <= 7'b0;      end //end 3     compare_state: // new current level received. This cycle gives time to determine next dac state       begin  //begin 4         state <= output_state; //next state is init_state         tmp_lcl <= tmp_lcl; //update local value         tmp_glbl <= tmp_glbl;         dac_state <= dac_state;         tmp_dac_out <= tmp_dac_out; 80          tmp_current <= curr_level;         count <= 7'b0;         adc_enable <= 1'b0;         cap_rst <= 1'b0;       end // end 4     output_state:       begin //begin 5         state <= wait_state; //next state is output_state         dac_state <= nxt_dac_state;         tmp_lcl <= tmp_lcl;         tmp_glbl <= tmp_glbl;         tmp_current <= tmp_current;         count <= 7'b0;         adc_enable <= 1'b0;         cap_rst <= 1'b0;         if (first_time == 1'b1)           begin             tmp_dac_out <= 7'b0100000;             first_time <= 1'b0;             cap_rst <= 1'b0;           end         else           begin             case (nxt_dac_state)                                         // case 2             heat:               begin  //begin 6                 if (tmp_dac_out < 7'b1111111)                   begin //begin 7                     tmp_dac_out <= tmp_dac_out + 1'b1;                   end  //end 7                 else                   begin  //begin 15                     tmp_dac_out <= 7'b0010000;                   end    //end 15               end  //end 6             cool:               begin //begin 8                 if (tmp_dac_out != 7'b0)                   begin  //begin 9                   tmp_dac_out <= tmp_dac_out - 1'b1;                  end    //end9                else                  begin  //begin 16                    tmp_dac_out <= 7'b0010000;                  end    //begin  81               end  //end 8            default:              begin  //begin 10               tmp_dac_out <= tmp_dac_out + 1'b1;              end    //end 10            endcase                                                      //endcase 2                end         end  //end 5     wait_state:       begin         tmp_dac_out <= tmp_dac_out;         tmp_lcl <= tmp_lcl;         tmp_glbl <= tmp_glbl;         tmp_current <= tmp_current;         dac_state <= dac_state;         if (count < 7'b1100100) //if count is <= 100, keep counting           begin             state <= wait_state;             adc_enable <= 1'b0;             count <= count + 1'b1;           end         else           begin             count <= 7'b0;             state <= sample_state;             adc_enable <= 1'b1;           end       end     default:       begin //begin 11         state <= output_state;         dac_state <= dac_state;         tmp_dac_out <= tmp_dac_out;         tmp_lcl <= tmp_lcl;         tmp_glbl <= tmp_glbl;         first_time <= 1'b0;       end   //end 11      endcase                                                       //endcase 1            if (compare_global == 1'b0)       begin  //begin 12         tmp_glbl <= curr_level;        end     //end 12    end  end         //end 2  82  endmodule  A.2 Comparison Block module compare_block(curr_lvl, local, global, compare_lcl, compare_glbl);   //Define parameters   parameter bits = 7;      //Define inputs and outputs  output compare_lcl;  output compare_glbl;  input [bits-1:0]curr_lvl;  input [bits-1:0]local;  input [bits-1:0]global;    //Define wires and registers  reg compare_lcl;  reg compare_glbl;     always @(curr_lvl or local or global)  begin    if (curr_lvl < local)      begin        compare_lcl <= 1'b1;      end    else      begin        compare_lcl <= 1'b0;      end    if (curr_lvl < global)      begin        compare_glbl <= 1'b1;      end    else      begin        compare_glbl <= 1'b0;      end  end      endmodule  

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