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Analysis and design of analog interface circuits for capacitive detector readout systems Beikahmadi, Mohammad 2017

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Analysis and Design of Analog Interface Circuits forCapacitive Detector Readout SystemsbyMohammad BeikahmadiM.Sc., Electrical and Electronics Engineering, Swiss Federal Institute ofTechnology in Lausanne (EPFL), 2009B.Sc., Electrical Engineering, University of Tehran, 2007A THESIS SUBMITTED IN PARTIAL FULFILLMENTOF THE REQUIREMENTS FOR THE DEGREE OFDoctor of PhilosophyinTHE FACULTY OF GRADUATE AND POSTDOCTORALSTUDIES(Electrical and Computer Engineering)The University of British Columbia(Vancouver)August 2017c©Mohammad Beikahmadi, 2017AbstractAdvances in sub-micron complimentary metal-oxide semiconductor (CMOS) tech-nologies have enabled implementation of ultra-low-power circuits and systems forvariety of applications including readout systems for capacitive radiation detectors.As state-of-the-art readout systems may integrate thousands of electronic channelson chip, designing low-power and low-noise interface circuits is of great interest.The focus of this work is on developing a design methodology for such readoutcircuits with an emphasis on interfacing with capacitive sensors, in general, andsolid-state radiation detectors, in particular. The critical aspects of the design fromanalyzing the specifications to noise optimization and circuit design are taken intoaccount and the proposed circuits offer improved performance for the readout sys-tem.To facilitate the noise analysis of modern readout systems, the equivalent noisecharge equations of the system are derived analytically. The analysis takes intoaccount the stringent requirements of modern readout systems as well as the noisesources associated with deep submicron CMOS technologies. The analysis is basedon the EKV (Enz, Krummenacher, and Vittoz) model of MOS transistors which isa model valid for all regions of operation.As a proof of concept, the analysis and design of three low-power and low-noise interface circuits are presented. The proposed circuits are fabricated in a0.13 µm CMOS process. The first interface circuit consists of a novel charge-sensitive amplifier (CSA), a pole-zero cancellation (PZC) circuit, and a 2nd-orderprogrammable pulse shaper. The proposed CSA accepts signals of both polarities,exhibits 111 e¯-rms noise, and consumes only 37.5 µW. The second interface circuitconsists of a CSA, a reset network, a 1st-order shaper, and a PZC circuit. The circuitiiconsumes about 1 mW and exhibits 66 to 101 e¯-rms noise at different peakingtimes. The third interface circuit is a mixed-signal design and consists of a CSAwith leakage compensation, a 5th-order programmable Gaussian shaper, a peak-detect and hold, a discriminator, and a novel Wilkinson-based digitizer. The circuitconsumes 1.97 mW and exhibits 58 e¯-rms noise. The design performs favourablyin terms of power consumption and noise behavior in comparison with similarworks in the literature.iiiLay SummarySolid-state radiation detectors measure the dose of radiation and are used in a broadrange of applications such as medical imaging, spectroscopy, and astrophysics. Thefocus of this work is on developing circuit design methodology for readout circuitsthat measure the amount of deposited charge in such detectors. Based on the pre-sented methodology, an interface circuit for the readout of a specific type of thesedetectors, namely, Cadmium Zinc Telluride (CZT) detectors, is designed, fabri-cated and successfully tested. The circuit connects to the individual detector pixelsand measures the amount of charge generated by each pixel. Since noise perfor-mance of a readout circuit limits the resolution of detection, we have proposed amethod to estimate the noise of the circuit analytically. Measurement results ofthe fabricated integrated readout circuit confirm that the proposed methodologycan be used to design a high performance readout system for solid-state radiationdetectors.ivPrefaceI, Mohammad Beikahmadi, am the principle contributor to all the chapters of thethesis. My supervisor, Professor Shahriar Mirabbasi, has provided technical as-sistance and has also reviewed the thesis. Dr. Krzysztof Iniewski has providedtechnical assistance and guidance with the design of the chips for CZT radiationdetectors. Dr. Roberto Rosales has provided technical assistance with laboratorymeasurements. He has also provided guidance with printed circuit board (PCB)design, test setup preparation, and performing the measurements.Some of the chapters in this manuscript have been written based on the follow-ing publications. Below is a list of published or submitted conference and journalpapers based on this work.Conference Papers1. M. Beikahmadi, K. Iniewski, and S. Mirabbasi, “A Low-Power Continuous-Reset CMOS Charge-Sensitive Amplifier for the Readout of Solid-State Ra-diation Detectors,” in the proceedings of the IEEE 14th International NewCircuits and Systems Conference (NEWCAS), 26-29 June 2016 (Chapters 3and 4). The authors received ReSMiQ best student paper award, 1st place.2. M. Beikahmadi, and S. Mirabbasi, “A low-power Wilkinson-type ADC forCdZnTe detectors in 0.13-µm CMOS,” 21st IEEE International Conferenceon Electronics, Circuits and Systems (ICECS), pp. 730-733, 7-10 Dec. 2014(Chapter 6).3. M. Beikahmadi, and S. Mirabbasi, “A low-power low-noise CMOS charge-sensitive amplifier for capacitive detectors,” IEEE 9th International New Cir-vcuits and Systems Conference (NEWCAS), pp. 450-453, 26-29 June 2011(Chapters 3). The authors received the best student paper award, 2nd place.Journal Papers1. M. Beikahmadi, S. Mirabbasi, and K. Iniewski, “Design and Analysis of aLow-Power Readout Circuit for CdZnTe Detectors in 0.13-µm CMOS”, inIEEE Sensors Journal, vol. 16, no. 4, pp. 903-911, Feb. 15, 2016 (Chapter5).2. A. Farsaei, Y. Wang, R. Molavi, H. Jayatilleka, M. Beikahmadi, A.H. Mas-nadi Shirazi, M. Caverley, L. Chrostowski, and S. Mirabbasi, “A Review ofWireless-Photonic Systems: Design Methodologies and Topologies, Con-straints, Challenges, and Innovations in Electronics and Photonics”, OpticsCommunications journal, 2016 (Other work).viTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviiiAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix1 Literature Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Introduction to Capacitive Detector Readout Systems . . . . . . . 11.1.1 The Detector . . . . . . . . . . . . . . . . . . . . . . . . 21.1.2 The Readout System . . . . . . . . . . . . . . . . . . . . 31.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3 Summary of Contributions . . . . . . . . . . . . . . . . . . . . . 141.3.1 Analytical Noise Analysis of Front-end Circuits for Solid-State Radiation Detectors . . . . . . . . . . . . . . . . . . 151.3.2 A Low-Power Charge-Sensitive Amplifier . . . . . . . . . 15vii1.3.3 Design and Analysis of a 4-Channel Readout System forSolid-State Radiation Detectors . . . . . . . . . . . . . . 151.3.4 Design and Analysis of a Complete Readout System forSolid-State Radiation Detectors . . . . . . . . . . . . . . 161.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Readout System Design for Capacitive Radiation Detectors . . . . . 182.1 System Specifications . . . . . . . . . . . . . . . . . . . . . . . . 182.2 Circuit Design Specifications . . . . . . . . . . . . . . . . . . . . 182.3 Technology Selection . . . . . . . . . . . . . . . . . . . . . . . . 202.4 Readout Circuit Design . . . . . . . . . . . . . . . . . . . . . . . 212.4.1 Charge-Sensitive Amplifier . . . . . . . . . . . . . . . . . 232.4.2 Reset Network . . . . . . . . . . . . . . . . . . . . . . . 262.4.3 Pole-Zero Cancellation (PZC) Circuit . . . . . . . . . . . 312.4.4 Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . 322.4.5 Peak-Detect and Hold (PDH) . . . . . . . . . . . . . . . . 342.4.6 Discriminator . . . . . . . . . . . . . . . . . . . . . . . . 342.4.7 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . 352.5 Noise Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 392.6 Layout Considerations and Chip Design . . . . . . . . . . . . . . 413 Analytical Noise Analysis of Front-end Circuits for Solid-State Ra-diation Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.1.1 Noise Sources in MOS Devices . . . . . . . . . . . . . . 453.1.2 Pulse Shaper Analysis . . . . . . . . . . . . . . . . . . . 463.2 Derivation of Equivalent Noise Charge (ENC) Equations . . . . . 473.2.1 Power Spectral Density of the Equivalent Voltage NoiseSource . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.2.2 Power Spectral Density of the Equivalent Current NoiseSource . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.2.3 Pulse Shaper’s Parameters . . . . . . . . . . . . . . . . . 523.2.4 Process Scaling . . . . . . . . . . . . . . . . . . . . . . . 53viii3.3 Measurement of Noise of the Readout System . . . . . . . . . . . 544 Analysis and Design of a Novel Low-Power Charge-Sensitive Amplifier 574.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.2 The Proposed Charge-Sensitive Amplifier . . . . . . . . . . . . . 584.3 Noise Analysis of the Readout Circuit . . . . . . . . . . . . . . . 604.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 624.5 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . 645 Design and Analysis of a 4-Channel Readout System for Solid-StateRadiation Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 685.1 Readout Circuit Design . . . . . . . . . . . . . . . . . . . . . . . 685.1.1 Design of the Charge-Sensitive Amplifier . . . . . . . . . 705.1.2 Design of the Pulse Shaper with a PZC Circuit . . . . . . 725.1.3 Design of the Reset Network . . . . . . . . . . . . . . . . 745.1.4 Noise Analysis and Optimization . . . . . . . . . . . . . 765.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 795.2.1 Transient Response of the Readout System . . . . . . . . 795.2.2 Noise Evaluation of the Readout System . . . . . . . . . . 815.3 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . 866 Design and Analysis of a Complete Readout System for Solid-StateRadiation Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 896.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896.2 Readout Circuit Design . . . . . . . . . . . . . . . . . . . . . . . 906.2.1 Charge-Sensitive Amplifier and Reset Network . . . . . . 926.2.2 Gaussian Pulser Shaper . . . . . . . . . . . . . . . . . . . 926.2.3 Peak-Detect and Hold . . . . . . . . . . . . . . . . . . . 936.2.4 Discriminator . . . . . . . . . . . . . . . . . . . . . . . . 956.2.5 Conversion Controller . . . . . . . . . . . . . . . . . . . 986.2.6 Wilkinson-Based ADC . . . . . . . . . . . . . . . . . . . 996.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 1066.3.1 Amplification and Pulse Shaping . . . . . . . . . . . . . . 1086.3.2 Pulse Height Digitization and Processing . . . . . . . . . 112ix6.3.3 Noise Behavior . . . . . . . . . . . . . . . . . . . . . . . 1176.4 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . 1197 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . 1217.1 Research Summary and Contributions . . . . . . . . . . . . . . . 1217.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Appendix A Detailed Design of a 5th-Order Gaussian Pulse Shaper . . 144Appendix B Verilog Model for the Conversion Controller Block of theComplete Readout System . . . . . . . . . . . . . . . . . . . . . . . 147Appendix C Verilog Model for the Controller Block of the Wilkinson-Based ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Appendix D Developed Software Program for Automating the ADCData Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160xList of TablesTable 1.1 Performance comparison of recent readout systems . . . . . . 9Table 2.1 System-level specifications for capacitive detector readout sys-tems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 2.2 Main circuit design specifications for capacitive detector read-out systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 2.3 Performance comparison of various digitization techniques fordetector readout circuits . . . . . . . . . . . . . . . . . . . . . 39Table 4.1 Readout circuit performance comparison . . . . . . . . . . . . 67Table 5.1 Device sizes of the CSA . . . . . . . . . . . . . . . . . . . . . 72Table 5.2 Device sizes of the main amplifier of the pulse shaper . . . . . 73Table 5.3 Specifications of the ASIC . . . . . . . . . . . . . . . . . . . . 80Table 5.4 Readout circuit performance comparison . . . . . . . . . . . . 88Table 6.1 ADC performance summary and comparison . . . . . . . . . . 108Table 6.2 Readout circuit performance comparison . . . . . . . . . . . . 120Table A.1 Pole locations of the 5th-order pulse shaper . . . . . . . . . . . 146xiList of FiguresFigure 1.1 (a) Capacitances in a capacitive detector, and (b) electricalmodel of the detector. . . . . . . . . . . . . . . . . . . . . . . 3Figure 1.2 Simplified block diagram of a typical readout channel for solid-state radiation detectors. . . . . . . . . . . . . . . . . . . . . 4Figure 2.1 The block diagram of a complete readout channel. . . . . . . 22Figure 2.2 Principle operation of a typical CSA. Cdet and CT are the de-tector and test capacitances respectively. The input dynamiccapacitance is represented as Ci = (A+1)C f . . . . . . . . . . 24Figure 2.3 Common reset circuits using a (a) resistor [1], (b) MOS device[2, 3], (c) MOS switch [4, 5], (d) current mirror [6], (e) self-adaptive biasing scheme [7, 8], (f) current conveyor feedback[9], (g) a MOS device and N times replica of it [10, 11], (h)low-frequency feedback loop [12–14], and (i) cold resistor [15]. 28Figure 2.4 (a) Circuit schematic of a first-order CR-RC pulse shaper, and(b) use of a PZC network in the CR-RC pulse shaper circuit tocancel the long decay time of the input signal. . . . . . . . . . 31Figure 2.5 PDH employing (a) a diode, (b) an amplified diode, and (c)current mirrors and an OTA. . . . . . . . . . . . . . . . . . . 35Figure 3.1 The block diagram of a Semi-Gaussian pulse shaper. . . . . . 46Figure 3.2 (a) Model of a noisy two-port network, and (b) model of thenetwork with the noise sources referred to the input. . . . . . 48xiiFigure 3.3 Effect of shaping time and order of the shaper on the ENCs ofa detector readout system in a 0.13 µm CMOS process. . . . . 53Figure 3.4 Effect of shaping time and order of the shaper on ENCs of adetector readout system in a 90 nm CMOS process. . . . . . . 54Figure 4.1 The proposed low-power continuous-reset CMOS charge-sensitiveamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Figure 4.2 Block diagram of the readout circuit employing the proposedCSA, a PZC, and a 2nd-order Semi-Gaussian programmablepulse shaper. . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 4.3 Chip micrograph. The chip is packaged in a standard 44-pinCQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 4.4 Measured waveforms at the output of the CSA (upper) and thepulse shaper (lower) for an injected charge of about ±2.5 fC. . 63Figure 4.5 Measured voltage peak amplitudes at the outputs of the CSAand the shaper versus injected charge. . . . . . . . . . . . . . 64Figure 4.6 Measured total output voltage noise density of the integratedreadout circuit. The measurement includes the noise of theactive probe and the instrument. . . . . . . . . . . . . . . . . 65Figure 4.7 Measured voltage noise density of the active probe and the in-strument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Figure 5.1 Simplified block diagram of one front-end channel. Capacitorbanks are used to implement Cp and Cz. A 2-to-4 decoder isused to select the peaking time of the pulse shaper. Buffer-s/output drivers are not shown for simplicity. . . . . . . . . . 69Figure 5.2 Circuit schematic of the CMOS charge-sensitive amplifier. Properbias voltages and currents are supplied from an integrated biascircuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 5.3 Circuit realization of the gain block of the pulse shaper. . . . . 74xiiiFigure 5.4 The designed reset network which is a modified version of theKrummenacher low-frequency feedback loop. Drain currentof transistor M2 is adjusted to compensate the leakage currentof the detector. Transistor M1 is introduced to adjust the decaytime constant of the CSA. . . . . . . . . . . . . . . . . . . . 75Figure 5.5 Theoretical optimum ENC of the front-end circuit and the cor-responding optimum channel width as a function of peakingtime for a PMOS input device for the 0.13-µm CMOS pro-cess used in this work. Since the input device size does notaffect the detector leakage current, the noise associated withthis leakage current is not taken into account in this optimization. 77Figure 5.6 Chip micrograph. The chip includes four identical readoutchannels and is packaged in a standard 44-pin CQFP. . . . . . 78Figure 5.7 Custom-designed FR4 printed circuit board (PCB). . . . . . . 79Figure 5.8 Captured waveforms at the output of the pulse shaper for aninjected charge of about 10 fC. The overshoot voltage is can-celled by adjusting the gate bias voltage (i.e., V resPZ) of theMOS device in the PZC network. . . . . . . . . . . . . . . . 81Figure 5.9 Measured voltage at the output of the pulse shaper for high andlow ranges. The integration is linear up to 5 and 45 fC for thelow and high ranges, respectively. . . . . . . . . . . . . . . . 82Figure 5.10 Measured waveforms at the output of the pulse shaper for var-ious peaking times. VresPZ voltage is not altered during themeasurement. . . . . . . . . . . . . . . . . . . . . . . . . . . 83Figure 5.11 Measured waveforms at the output of the CSA for various val-ues of the V resPre control voltage. The discharge time of theCSA can be adjusted from about 1 to 7 µs. . . . . . . . . . . 84Figure 5.12 Noise measurement setup diagram. Several switches and volt-age dividers are used to supply the digital inputs and the biasvoltages to the chip, respectively. Note that only one switchand one voltage divider is shown for simplicity. . . . . . . . . 85Figure 5.13 Measured voltage noise density at the output of the pulse shaperfor a peaking time of 1140 ns. . . . . . . . . . . . . . . . . . 86xivFigure 5.14 Measured equivalent noise charge of the system versus differ-ent peaking times for a 250 fF detector capacitance. . . . . . . 87Figure 6.1 Simplified block diagram of the fabricated readout system. Theblock diagram shows (a) the charge-sensitive amplifier, the re-set network, and two 2-4 decoders, (b) a 5th-order Gaussianpulse shaper, and (c) the peak-detect and hold, the discrimi-nator, the Wilkinson-based analog-to-digital converter, and thedigital conversion controller. . . . . . . . . . . . . . . . . . . 91Figure 6.2 Structure of a second-order active filter with complex poles. . 93Figure 6.3 Circuit schematic of the 5th-order active Gaussian pulse shaper. 94Figure 6.4 Circuit schematic of the implemented peak-detect and hold. . 95Figure 6.5 Circuit schematic of the implemented operational transconduc-tance amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . 96Figure 6.6 Circuit schematic of the implemented (a) discriminator, and(b) operational amplifier block of the discriminator. . . . . . . 97Figure 6.7 Simulated transient response of the discriminator. The dis-criminator has a propagation delay of less than 10 ns for theinput signals shown. The signal rise and fall times are lessthan 1 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Figure 6.8 (a) Generic block diagram of a Wilkinson digitizer, (b) sim-plified circuit of the proposed Wilkinson-type ADC, and (c)timing signals of the proposed ADC. . . . . . . . . . . . . . . 100Figure 6.9 Simulated voltage across the capacitor. In the absence of theEA, M5 and S3, a voltage drop of about 5 mV is observed dur-ing the sampling period. . . . . . . . . . . . . . . . . . . . . 102Figure 6.10 Layout of the proposed ADC in a 0.13-µm CMOS process. . 103Figure 6.11 Simulated transient behaviour of the digitizer for maximuminput voltage. The sampled voltage across the capacitor dis-charges linearly with the falling edge of the Start signal. TheOut put ready flag is raised at the end of conversion. The ADChas no missing codes. . . . . . . . . . . . . . . . . . . . . . . 104xvFigure 6.12 Simulated differential and integral nonlinearities of the ADC.The converter shows excellent differential linearity. MaximumDNL and INL are ± 0.065 LSB and 0.954 LSB, respectively. 105Figure 6.13 Simulated spectrum of the output signal for a sinewave inputwith an amplitude of 2.7 V and a frequency of 90 Hz. . . . . . 106Figure 6.14 Photographs of the (a) printed circuit board, and (b) the shieldedchamber used for evaluating the performance of the fabricatedchip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Figure 6.15 Sample oscilloscope waveforms. The waveform in green showsthe applied step signal to the input capacitor and the waveformin violet shows the signal captured at the output of the pulseshaper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Figure 6.16 Captured waveforms at the output of the pulse shaper for threevalues of the V res PZC control signal (refer to Figure 6.3. Theundershoot at the output signal is effectively removed by ad-justing the value of the V res PZC signal. . . . . . . . . . . . 110Figure 6.17 Captured waveforms at the output of the pulse shaper for vari-ous peaking times. . . . . . . . . . . . . . . . . . . . . . . . 110Figure 6.18 Captured waveforms at the output of the pulse shaper for theavailable gain settings. . . . . . . . . . . . . . . . . . . . . . 111Figure 6.19 Measured change in the output of the pulse shaper for injectedcharges of up to 40 fC. . . . . . . . . . . . . . . . . . . . . . 111Figure 6.20 Captured waveforms at the outputs of the pulse shaper and thePDH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Figure 6.21 Captured waveforms at the outputs of the Wilkinson-based ADCfor an input voltage of 3.3 V. . . . . . . . . . . . . . . . . . . 113Figure 6.22 Measured transfer curve of the proposed ADC. . . . . . . . . 114Figure 6.23 Calculated INL and DNL of the ADC from histogram testing. 114Figure 6.24 Measured total output voltage noise density of the integratedreadout circuit. The measurement includes the noise of theactive probe and the instrument. . . . . . . . . . . . . . . . . 117Figure 6.25 Measured voltage noise density of the active probe and the in-strument. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118xviFigure A.1 Block diagram of a 5th-order Gaussian pulse shaper . . . . . . 145xviiGlossaryASIC application-specific integrated circuitADC analog to digital converterCMOS complimentary metal-oxide semiconductorCSA charge-sensitive amplifierDAC digital to analog converterDNL differential non-linearityENC equivalent noise chargeINL integral non-linearityPZC pole-zero cancellationPCB printed circuit boardPDH peak-detect and holdSAR successive approximation registerSNR signal-to-noise ratioSG Semi-GaussianSPECT single-photon emission computed tomographyxviiiAcknowledgmentsI would like to express my sincere thanks to my supervisor, Professor ShahriarMirabbasi, for his guidance and for providing me with all the necessary facilitiesfor the research. He has been supportive by all means throughout my doctoralstudies and I am truly grateful for that. I must also thank Dr. Krzysztof Iniewskifor providing technical assistance and guidance in chip designs.I would also like to acknowledge the National Sciences and Engineering Re-search Council of Canada (NSERC) and the Institute for Computing, Informationand Cognitive Systems (ICICS) at the University of British Columbia. I also ap-preciate Canadian Microelectronics Corporation for fabrication services and CADtools support.I also take this opportunity to express gratitude to all of my colleagues at theSystem-on-a-Chip research laboratory at the Electrical and Computer EngineeringDepartment for their extensive help and support. Special thanks goes out to Dr.Roberto Rosales for his support, guidance and technical assistance on laboratorymeasurements. I must also thank Roozbeh Mehrabadi for CAD tools support.Finally, I would like to take this opportunity to thank my family for their love,support, and attention throughout my life. In particular, I am thankful to my wifeand best friend, Kimia, who supported me and encouraged me through this venture.xixChapter 1Literature Overview1.1 Introduction to Capacitive Detector Readout SystemsRoom-temperature solid-state radiation detectors have broad applications in med-ical, space, and security systems [16, 17]. These detectors benefit from a betterenergy resolution and a smaller form factor in comparison with conventional scin-tillators. Cadmium Zinc Telluride (CdZnTe or CZT) is an example of these de-tectors which has gained a lot of attention in recent years. High density (≈ 5.9g/cm3), high atomic number (Cd: 48, Zn 30, and Te: 52), and tunable widebandgap (≈ 1.5− 2.2 eV) make CZT detectors favourable choices for many ap-plications that require room temperature operation [18]. Furthermore, fabricationof CZT detectors with large number of imaging pixels has become economicallyand technologically viable thanks to recent advancements in their fabrication pro-cess. This requires integration of a large number of readout circuits on chip toprocess the output signal of each pixel. In order to make such an integration fea-sible, the power consumption, size, and noise of each readout circuit must be keptat acceptable levels. As CZT appears to be widely available for future detectorreadout systems, the proof of concept integrated circuit that we will design in thisresearch will be optimized for this detector.Conventional readout circuits had only a small number of electronic channelsand were implemented using discrete components while today’s imaging systemsmay have thousands of electronic channels per cm2 [19, 20]. Implementing a large1number of highly densed electronic channels using discrete components is not afeasible solution due to the high cost and large area. Thus front-end electron-ics needs to be integrated in a custom-made application-specific integrated cir-cuit (ASIC). Current integrated readout circuits are implemented mainly in com-plimentary metal-oxide semiconductor (CMOS) technologies. Submicron CMOStechnologies offer high integration density, low power consumption as well as theability to integrate various analog and digital functions on the same chip [21] andtherefore minimizing the overall system cost, size, and weight.1.1.1 The DetectorRadiation detectors generate electron-hole pairs by absorbing the received electro-magnetic wave. When enough energy is absorbed by the detector, electron-holepairs are generated. The pairs drift to corresponding electrodes in the presence ofan electric field generated by an applied external voltage. The generated electronsand holes migrate in opposite directions. The motion of electric charges under theinfluence of the electric field generates a signal that can be modelled by a time-variant current source.A detector pixel is often modelled by the capacitances to the adjacent neigh-bours (Cad j) and to the backside (C0). The capacitances are shown in Figure 1.1a.The pixels are held at a constant potential with the help of the amplifiers. The com-bination of these capacitances form an effective capacitance of Cdet . This capac-itance is shown on the electrical model of the detectors illustrated in Figure 1.1b.To model the detector leakage current, a constant current source is added to themodel. The Isig in Figure 1.1b is the signal that is generated by the motion of thepairs under the influence of the electric field. Various factors are involved in de-termining the shape of the signal such as the applied bias voltage, the position anddepth of interaction, and the properties of the detector material [22].The CZT detectors that we will design the proof-of-concept readout systemfor, are manufactured by Redlen Technologies, Inc. The detectors typically have500 fF pixel capacitance and produce a leakage current in the range of 1 fA to50 nA. When used in single-photon emission computed tomography (SPECT), eachpixel generates about 5 fC charge at each event. The events occur typically 1 ms2Cadj CadjC0Bump padCdetIleak IsigIsigtTo CSAHigh voltage(a)(b)Figure 1.1: (a) Capacitances in a capacitive detector, and (b) electrical modelof the detector.apart.1.1.2 The Readout SystemFigure 1.2 shows a simplified block diagram of a typical readout system. Thereadout system for capacitive detectors consists of amplification, pulse shaping,and signal processing stages. The stages are briefly reviewed in the followingsubsections.AmplificationThe sensor generates a small amount of charge which appears as a weak signalat the electrodes. This weak signal is often needed to be amplified by a charge-3Cdet-AReset networkCfH(s)To Pulse Processing UnitDetector modelhνAmplification Pulse shapingFigure 1.2: Simplified block diagram of a typical readout channel for solid-state radiation detectors.sensitive amplifier (CSA) before further processing. The core of the CSA consistsof an inverting high-gain voltage amplifier and a feedback capacitor. The generatedcharge by the sensor is integrated on the feedback capacitor. This generates a step-like signal at the output terminal of the CSA. The amplitude of the output signal isapproximately equal to Q/C f where Q is the amount of injected charge and C f isthe feedback capacitance. The charge gain, defined as AQ =Vo/Q = 1/C f , is thusdetermined by C f . Note that C f is a well-controlled component and therefore, thecharge gain of the amplifier becomes (to the first order of approximation) robustto the detector capacitance variations. A reset mechanism, either continuous ordiscrete, needs to be implemented in order to avoid pulse pile up at the output ofthe CSA.Pulse ShapingThe resulting output signal from the CSA is then filtered by a pulse shaper. Apulse shaper is an active or passive filter whose main function is to enhance thesignal-to-noise ratio by reducing the bandwidth of the noise. This is achieved bychoosing a proper peaking time for the filter which also sets the duration of thepulse. The resulting voltage pulse at the output terminal of the shaper has an am-plitude proportional to the amount of the injected charge. This signal can be storedor digitized for further processing.4Digitization and Signal ProcessingThe signal from the pulse shaper is often digitized before storage or further process-ing. In order to identify the channels with incidents discriminators are employed.They provide a trigger signal whenever the signal from the pulse shaper rises abovea threshold level. The signal from the pulse shaper is passed to a peak-detect andhold (PDH) circuit before digitization. A PDH tracks the signal from the pulseshaper, stores and keeps the peak voltage. This peak voltage is then passed to ananalog to digital converter (ADC) for digitization. After the signal is digitized, itcan be stored on the chip or transferred to a computer for storage or processing.1.2 MotivationThe design of readout systems for capacitive solid-state radiation detectors hasbeen discussed extensively in the literature [12, 17, 18, 20–52], however, con-tinuous improvement in readout circuit design is necessary in order to meet thestringent requirements of modern detector systems. The readout system can berealized using either discrete components or integrated circuits. In [53], an exper-imental comparison between CMOS and discrete charge-sensitive amplifiers forCZT detectors is given. The measured results show that it is possible to reach ahigh performance using both approaches, however, the integrated circuit approachoffers a smaller size and a lower power consumption. As state-of-the-art readoutsystems may have hundreds or thousands of electronics channels, it would makesense to realize such systems using the integrated circuit approach to save powerand lower the cost of the system. Thus for the rest of this work we will mainlyfocus on readout systems that are realized using the integrated circuit approach. Inthe following, we review the most recent and popular designs in detail.RENA-2/3 [41, 42] ASICs are designed in 0.5 µm CMOS technology for read-out of CZT detectors. The newest generation of the design contains a charge-sensitive amplifier, leakage compensation, pulse shaper, comparator, Digital toAnalog Converter, and Peak-Detect-Hold. It has selectable dual energy range andthe peaking time is adjustable from 0.36 to 38 µs. The detector capacitance canvary from 2 to 9 pF. All these features make the chip suitable for a variety of ap-plications. The power consumption of the chip is about 5.8 mW and the equivalent5noise charge (ENC) of the system is 140-150 e¯-rms with no detector attached. Thedesign is not suitable for the systems that require lower power consumption andhigher resolution.0.35 µm CMOS process has been a popular choice for the development of in-tegrated circuits for capacitive radiation detectors. A low-noise 64-channel ASICis proposed in [37] in a 0.35 µm CMOS process for readout of CZT detectors.Each readout channel includes a charge-sensitive amplifier with leakage currentcompensation, a CR-RC shaper, two filters, an inverse proportional amplifier, apeak-detect-and-hold circuit, a discriminator, a control circuit and a buffer. The in-put range is from 5 to 190 keV. The measured ENC is 66 e¯-rms at a peaking time of1.5 µs with no detector attached. However, the power consumption of each chan-nel is 8 mW. In [35], a multi-channel readout circuit is proposed for CZT-basedspectrum analyzer in a 0.35 µm CMOS process. The front-end circuit includes acharge-sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer.The power consumption of the front-end circuit is 2.8 mW and the measured ENCis 133 e¯-rms with no detector attached. However, there is no leakage compensationblock on the chip and the detector is assumed to be AC-coupled to the front-end cir-cuit. In [21], another design is proposed for radiation sensor interfaces in 0.35 µmCMOS technology. The design contains a charge-sensitive amplifier and a novelCR−RC2 pulse shaper and a buffer. The power consumption of the front-end cir-cuit is 1 mW per channel but the equivalent noise charge is 382 e¯-rms with nodetector attached. The peaking time of the pulse shaper is adjustable, however, thepeak amplitude of the output signal changes when the peaking time is adjusted. Thechip proposed in [43] is called DEDIX and is intended for digital X-ray imagingsystems. Each readout channel is built of a charge-sensitive amplifier, a pole-zerocancellation circuit, a shaper, two discriminators and two counters. The detec-tor capacitance can vary from 1 to 3 pF. The measured equivalent noise charge is110 e¯-rms for a detector capacitance of 1 pF at the shaper peaking time of 160 ns.The power consumption per channel is 5 mW. A low-noise ASIC, called KW03,is proposed in [44] which is intended for Silicon and CdTe Sensors in 0.35 µmCMOS technology. Each readout channel includes a charge-sensitive amplifier,bandpass filters and a sample-and-hold circuit. The equivalent noise level of atypical channel is about 89 e¯-rms with no detector attached. However, the ENC6increases to 260 e¯-rms when the ASIC is housed in a standard QFP package. Thepower consumption of each readout channel is about 3 mW.A design in 0.25 µm CMOS process is proposed in [54] for CZT Co-planargrid sensors. The ASIC implements three front-end channels. Two channels aredesigned for amplification and processing of the collecting and non-collecting elec-trodes. The third channel provides amplification and processing of the cathodesignal. The circuit dissipates 25 mW and achieves an ENC of 500 e¯-rms.A self-triggered pulse amplification and digitization ASIC, called SPADIC, isproposed in [55] in 0.18 µm CMOS technology. Each readout channel includesa charge-sensitive amplifier, a pole-zero cancellation circuit, a second-order pulseshaper, a comparator, a DAC, and a pipeline analog-to-digital converter. The powerconsumption per channel is 4.5 mW and the equivalent noise charge is above 200 e¯-rms with no detector attached.A family of prototype pixel readout chips operating in single photon countingmode, called Medipix1,2,3, is introduced in [20, 23, 56]. They were implementedin 1, 0.25 and 0.13 µm CMOS technologies, respectively. The latest chip containsa CSA, a first-order shaper with 300 ns shaping time, discriminators, and digitalcircuits. The chip has two gain settings and each analog channel consumes only16.2 µW. The ENC of the readout circuit at high gain setting is about 72 e¯-rms,however, when the input range is extended by applying a lower gain setting, theENC increases to 105 e¯-rms.Ultra-deep submicron CMOS processes seems to be appealing to applicationsthat require fast signal processing. A fast prototype chip in 90 nm technology,called PX90, is introduced in [45] for readout of hybrid pixel detectors. Each pixelcontains a charge-sensitive amplifier with leakage compensation, a main amplifier,two discriminators, two DACs and two ripple counters. The power consumptionof each pixel (excluding the power consumption of other circuits on the chip) isabout 47 µW. This chip achieves an ENC of 204 e¯-rms with no detector attached.The measured noise spread from pixel to pixel is σ = 22 e¯-rms . The ENC risesto 240 e¯-rms for a detector capacitance of 50 fF. The offset spread from pixel topixel is σ = 35 mV. In order to minimize the effect of threshold spread acrossthe chip, the DACs are controlled by an external software. After correction, theeffective threshold spread at the discriminator inputs reduces to σ = 1.8 mV which7equals to an input offset of 64 e¯-rms. The input dynamic range is limited andthe gain and noise performance of the readout circuit vary significantly with thebias condition of the leakage compensation block. More recently, a chip calledCHIPIX65 [40, 46] has been under development in a 65 nm process for use inthe Large Hadron Collider (LHC) experiments in CERN with collaboration of 35experts in the field. The experiments demand very high data rates, high integrationdensity, low power, and low noise performance. The analog front-end contains acharge-sensitive amplifier with leakage compensation, a comparator and a time-over-threshold counter. This design achieves a low power consumption of 5 µWand an equivalent noise charge of 110-120 e¯-rms per pixel. However, the dynamicrange is limited, and a slight change in the detector capacitance affects the risetime and the peak amplitude of the signal noticeably. Table 1.1 summarizes theadvantages and drawbacks of the aforementioned readout systems.As mentioned earlier, state-of-the-art readout systems may integrate thousandsof electronic channels on chip. For an example, a pixel detector called ATLAS uses28000 readout chips and each chip integrates 2880 readout channels [57, 58]. Thishigh level of integration requires low power consumption. The detector pixel sizehas also shrunk in recent years. The Medipix2 [20] chip, for an example, contains65536 readout channels for the readout of pixels with dimensions of 50 µm by50 µm. The pixel size dictates the area available for the integration of each readoutchannel. Considering such high level of integration and the small area availablefor heat dissipation, any small improvement in power consumption of each readoutcircuit can significantly improve the performance of the readout system. As thereadout channels are placed as close as possible to the detector pixels, the generatedheat by the readout circuits can increase the operating temperature of the integratedcircuits and the detector. The increase in temperature deteriorates the performanceof the system by• increasing the noise of the devices in the readout circuits. Thermal noisein both resistors and MOS devices increases with temperature. The thermalnoise of the input device of the CSA is the main contributor to the overallnoise of the system.• increasing the leakage current of the detector [59, 60]. The increase in the8leakage current can change the DC bias levels and ultimately saturate thefront-end electronics. The shot noise due to the leakage current of the de-tector can also contribute significantly in the noise of the readout circuitsspecially at long shaping times [61, 62].• changing the electrical properties of the detector. For example, electron andhole drift mobilities and electric field uniformity across the detector varywith temperature [63–65]. In general, radiation detectors perform better atlower temperatures. It has been shown in [66] that 1 ◦C increase in thedetector temperature decreases the detected energy by 0.1 keV for eventsdepositing 30 keV. This loss of resolution is problematic for applicationsthat require high spatial resolution.Designing a low-noise and low-power integrated readout system requires mak-ing trade-offs between several key design parameters, including noise performance,gain, linearity, dynamic range, and power consumption. The trade-offs are de-scribed in detail below.• In a readout system it is often desired to improve the resolution of detectionwhich means the noise of the system needs to be reduced. The noise of thereadout circuit is mainly dominated by the noise of the CSA and the noise ofthe CSA can be enhanced at the expense of increasing its power consump-tion. This is in contrast with the low-power requirement of modern readoutcircuits. Besides, increasing the power consumption of the circuit generatesextra heat which in turn can deteriorate the performance of the detector andthe readout circuit and ultimately limit the resolution of detection.• Linearity is a design parameter that is desired to be increased. Increasing thelinearity of design is usually achieved by increasing the power consumptionof the readout system which is undesired.• As the signal produced by the detector is weak, the readout circuit mustprovide sufficient gain to amplify the signal for further processing. The gainof the readout circuit is often enhanced by increasing the power consumptionof the circuit which is undesired. Increasing the gain can limit the dynamic10range of the readout circuit. This is due to the scaling of CMOS technologywhere there is less and less headroom voltage is available for analog circuitsin ultra deep submicron technologies.As explained earlier, submicron CMOS technology is of great interest for de-signing front-end electronics for detector applications. Advanced CMOS technolo-gies offer lower supply for both analog and digital circuits which reduces the powerdissipation of the readout circuit. Low power dissipation enables high level of in-tegration which is essential in design of multi-channel detector readout systems.Digital circuits also benefit from higher speed with the advancement of CMOStechnology. The noise performance of the readout system is also enhanced withthe scale of CMOS technology from micron to submicron [67]. In older CMOStechnologies the bias conditions and dimensions of the input device of the charge-sensitive amplifier was dictated by the bandwidth requirements of the amplifier.With the advancement of CMOS technology, cut-off frequency of MOS deviceshas increased significantly. This means that speed is not an issue any more and theinput device can be biased in weak inversion region where the transconductanceof the input device depends only on the bias current and not on the device dimen-sions. As a result, the bias conditions and dimensions of the input device can beoptimized for noise performance. On the other hand, designing readout systems indeep submicron technologies is becoming more challenging [68]. Reduced supplyvoltage restricts the output swing (i.e., lower dynamic range) and constrains thecircuit topology. Designing precise analog circuits with reduced supply voltage isbecoming difficult and requires a good understanding of physical effects and char-acteristics of devices in deep submicron CMOS processes. Matching of transistorsand passive components in analog circuits realized in advanced processes is alsodifficult. For example, for minimum size MOSFETs in 0.13 µm technologies thestandard deviation of threshold voltage mismatch is about 35 mV which increasesto about 50 mV for the MOSFETs in 90 nm technologies [67]. Operation of dig-ital circuits using minimum length devices is also affected by mismatch and largetiming fluctuations can occur. In addition to increased mismatch between devicesand components in each readout channel, the channel to channel mismatch alsoincreases. For example, the measured offset spread from pixel to pixel in a readout11chip in 90 nm technology is σ = 35 mV [45].When it comes to noise analysis, understanding noise mechanisms that causeperformance degradation is essential to design low-noise front-end circuits. Withthe advancement of CMOS technology into nanometer regime, additional noisesources need to be taken into account in order to accurately model the noise behav-ior of a readout system. Therefore, it is essential for a designer to clearly under-stand the trade-offs involved in designing readout systems using deep submicrontechnologies. Detailed noise analysis of readout systems for solid-state radiationdetectors can be found in literature [10, 12, 69–78]. The analysis provided in theliterature needs to be reconsidered in order to accurately model the noise behaviorof the current state-of-the-art front-end circuits. The reasons include• The input MOS device of the CSA is often assumed to operate in strong in-version region which is in contrast with low-power operation of the modernreadout systems. In state-of-the-art low-power circuit designs the input tran-sistor is biased in weak (or moderate) inversion regions [74]. This change inthe region of operation needs to be taken into account when the noise of thesystem is being modelled and evaluated.• MOS devices in ultra-deep submicron technologies exhibit additional noisesources that cannot be safely ignored. An example of such noises is theparallel noise contributions from the gate current of the input device of theCSA. The gate leakage current increases significantly with reduction of thegate-oxide thickness in advanced CMOS technologies [79]. This currentmust be modelled and taken into account when noise behavior of the systemis being evaluated and optimized.• It is often assumed in the literature that the power spectral density of theseries flicker noise has a pure 1/ f distribution. Experimental results in deepsubmicron technologies show that slope of the 1/ f noise component of thespectrum α f is smaller than 1 for N-type and larger than 1 for P-type MOSdevices [80, 81]. The 1/ f noise coefficient (K f ) can also be bias dependent.Based on the aforementioned reasons, it is necessary to reconsider evaluationof the noise of the modern detector readout system taking into account the new12noise sources, biasing conditions of the devices, and noise models of devices inultra-deep submicron technologies. In this work we will use the EKV (Enz, Krum-menacher, and Vittoz) model [82] of the MOS device to efficiently analyze thenoise performance of modern readout systems. EKV is a fully analytical MOSdevice model which is intended for design, analysis and simulation of low-powerand low-voltage analog circuits in advanced CMOS technologies. It offers a bettermodeling of the weak and moderate inversion regions. It is also a compact modeland has a small number of DC parameters compared to other MOS models. BSIM3(Berkeley Short-channel IGFET) model, for example, is overly empirical and hasover 400 DC parameters, but EKV has only 22. The use of this model in simula-tors can lead to shorter simulation time. EKV version 2.6 is currently supported bymany simulators, including Spectre, SpectreRF, Star-Hspice, PSPICE, and others.EKV model is also available in commercial design libraries from foundries suchas Toshiba, Atmel, and EM Marin. Examples of commercial integrated circuitsdesigned using the EKV model can be found in [83]. One of the limitations of thismodel is the assumption of constant doping in the channel which causes inaccuratemodeling of capacitances in high voltage MOS devices [84]. Another limitationin EKV version 2.6 is the difficulty of the model to accurately fit ID-VG curves forlow and high values of VD simultaneously [85]. This is due to drain-induced barrierlowering (DIBL) effect in short-channel MOS devices and is claimed to be fixed inEKV version 3.0.The EKV model is based on fundamental physical properties of the MOS struc-ture and takes advantage of the inherent symmetry of the device by referring all thevoltages to the local substrate. In this model all the small- and large-signal vari-ables are continuous in all regions of operation. The drain current in this model isdefined as a difference between a forward (IF ) and a reverse (IR) component. Theforward and reverse components are a function of VP−VS and VP−VD through aspecific current IS, respectively. The function is quadratic in strong inversion andexponential in weak inversion. VP is the pinch-off voltage and is a function of gatevoltage for long-channel devices. The pinch-off voltage in short-channel devicesbecomes a function of gate, source and drain voltage due to the charge-sharingeffect. An interpolation function is used to model the current in the moderate in-version region which results in a continuous expression for all regions of operation.13The details of the EKV MOS model equations can be found in [82, 86].The focus of this research is on developing design methodology for low-powerand low-noise integrated readout circuits for capacitive and in particular, for solid-state radiation detectors. We will show how to design an integrated readout circuitfor CdZnTe detectors based on the described methodology as a proof of concept.Unique features and recent advances in these detectors will be taken into accountand the analog channel will be optimized to achieve high efficiency and perfor-mance. As estimation of the noise performance of state-of-the-art readout circuitis an important factor in designing an optimized readout system, we will showhow to analytically derive the noise equations of the system taking into account thebehaviour of devices in ultra-deep submicron CMOS processes.1.3 Summary of ContributionsIn this thesis, we provide a detailed analysis of capacitive detector readout circuits.We start off by introducing the procedure for designing a readout system for ca-pacitive detectors. We discuss all the important steps of the procedure, includinganalyzing the specifications, choosing an appropriate technology for the realiza-tion of the design, designing the analog and digital blocks, noise evaluation, layoutconsiderations and chip design. We present state-of-the-art designs of each blockof the system, compare the designs, and discuss advantages and disadvantages ofeach design. Furthermore, we present a comprehensive noise analysis of moderncapacitive detector readout circuits. We take into account the new noise sourcesassociated with deep submicron technologies. The analysis is based on the EKVmodel [82] of MOS transistors which is a model valid for all regions of operation.As a proof of concept, we present the analysis and design of a novel low-powercharge-sensitive amplifier and the design and analysis of a readout system for solid-state radiation detectors. The analytical equations for the estimation of the noise ofthe readout system are derived. The proposed circuits are fabricated in a 0.13 µmCMOS process. We briefly review the contributions in the following subsections.141.3.1 Analytical Noise Analysis of Front-end Circuits for Solid-StateRadiation DetectorsIn this work we analyse the noise behavior of state-of-the-art readout systems forsolid-state radiation detectors in detail. We will derive the equivalent noise charge(ENC) equations of the system analytically taking into account the additional noisecontributions and the requirement of modern readout systems. Unlike other noiseanalysis methods, the analysis given in this work is based on the EKV model ofMOS transistors which is valid for all regions of operation (i.e., from weak tomoderate and strong inversion regions). A Semi-Gaussian pulse shaper is used asan example to show the procedure for noise analysis and optimization. The effectsof the design parameters of the shaper on the ENC equations of the readout systemare discussed.1.3.2 A Low-Power Charge-Sensitive AmplifierIn this work the design of a novel low-power continuous-reset CMOS CSA is pre-sented. The proposed CSA is intended for capacitive sensor readout circuits, inparticular, interface circuits for solid-state detectors used in medical imaging andX-ray spectroscopy. A proof-of-concept interface circuit is designed and fabricatedin a 0.13-µm CMOS process and consists of the proposed CSA, a pole-zero can-cellation circuit, and a second-order semi-Gaussian programmable pulse shaper.Unlike most of the CSAs in the literature, the proposed CSA can accept signals ofboth polarities. Measurement results confirm low-power operation of the circuit.The CSA consumes only 37.5 µW from dual supply voltages of 0.9 and 1.2 V. Themeasured equivalent noise charge of the CSA is about 111 e¯-rms.1.3.3 Design and Analysis of a 4-Channel Readout System forSolid-State Radiation DetectorsIn this work we present the design and analysis of a low-power and low-noise 4-channel readout circuit intended for the readout of solid-state radiation detectors (inparticular, CZT detectors). The circuit consists of a CSA, a reset network to providea discharge path for the feedback capacitor, and a first-order pulse shaper with apole-zero cancellation (PZC) circuit. We have presented a simple method to adjust15the discharge time constant of the CSA in order to accommodate various eventrates. Moreover, we have proposed a simple method for the overshoot removalat the output of the pulse shaper when the discharge time constant of the CSA isadjusted. Furthermore, a comprehensive noise analysis of the readout system ispresented and the design is optimized in terms of noise performance and powerconsumption. A proof-of-concept interface circuit is laid out and fabricated in a0.13-µm CMOS technology. Measurement results of the circuit confirm the low-noise and low-power operation of the readout system. The readout system offersexcellent power consumption and superior noise performance in comparison withsimilar works in the literature.1.3.4 Design and Analysis of a Complete Readout System forSolid-State Radiation DetectorsIn this work we focus on the design and analysis of the pulse shaper and the signalprocessing blocks of a readout system. As a proof of concept, we will design andintegrate a complete mixed-signal readout system. The integrated readout systemconsists of a CSA with leakage compensation, a Gaussian pulse shaper, a PDH,a discriminator, and a Wilkinson-based ADC. In addition to conventional blocksof a Wilkinson-type digitizer, the ADC contains additional circuitry that preventsa voltage drop at the moment when conversion commences. The test chip is laidout and fabricated in a 0.13 µm CMOS technology. Measurement results of thereadout circuit confirm the feasibility of the design. The readout system performsfavourably in terms of power consumption and noise behavior in comparison withsimilar works in the literature.1.4 Thesis OutlineSo far, we have introduced the readout system for solid-state radiation detector anddiscussed the challenges involved in designing low-power and low-noise readoutcircuits. The rest of the thesis is organized as follows.In chapter 2, we present the methodology for designing a low-power and low-noise readout system for capacitive radiation detectors. The methodology includesanalyzing the specifications of the detector and the system, choosing an appropri-16ate technology for the realization of the system, designing the analog and digitalblocks, noise evaluation, layout considerations, and chip design. In Chapter 3, weprovide a detailed noise analysis of modern readout systems for capacitive and inparticular, solid-state radiation detectors in detail. We will derive the equivalentnoise charge equations of the readout system analytically taking into account theadditional noise contributions and the requirement of the readout system. In Chap-ter 4, the design of a novel low-power continuous-reset CMOS charge-sensitiveamplifier is presented. The proposed CSA is intended for capacitive sensor read-out circuits, in particular, interface circuits for solid-state detectors used in medicalimaging and X-ray spectroscopy. A proof-of-concept interface circuit is designedand fabricated employing the proposed amplifier. Measurement results of the read-out system are presented. In Chapter 5, we focus on the design and noise analysisof a low-power and low-noise four-channel readout circuit consisting of a CSA anda first-order pulse shaper. We present a comprehensive noise analysis of the read-out system. Measurement results of the readout system are also presented and thedesign is compared with similar works in the literature. In Chapter 6 we discuss thedesign and analysis of a complete mixed-signal readout system. The focus of thedesign is on the pulse shaper and signal processing circuits. We present detaileddesign and analysis of the blocks. The measurement results of the fabricated chipare presented and discussed. Finally, Chapter 7 summarizes the research resultsand future work.17Chapter 2Readout System Design forCapacitive Radiation DetectorsIn this chapter the procedure for designing a readout system for capacitive solid-state radiation detectors is described. A readout system consists of the radiation de-tector, readout circuit, supporting structures, and cooling (if any). To properly de-sign an efficient readout system, both system- and circuit-level requirements mustbe taken into account. A successful design requires making trade-offs on severaldesign aspects which cannot be optimized simultaneously.2.1 System SpecificationsFrom a system point of view, a designer must consider several specifications. Themain system-level specifications are summarized in Table 2.1 [87]. It is worthmentioning that these specifications cannot be optimized simultaneously and thedesigner must make trade-offs carefully.2.2 Circuit Design SpecificationsIn analog circuit design the designer is given a set of specifications and is askedto transform the specifications into circuits. The designer has to find an optimalsolution to the given problem such that the design requirements are met. Thisinvolves finding the right technology, creating schematics and layouts, and then18Table 2.1: System-level specifications for capacitive detector readout systemsSpecification DescriptionDetector geometry How to arrange the detector modules? Howmany modules are needed? What is the coverageof the modules? Are there any dead regions?Efficiency How much charge must be collected for efficientdetection? what are the properties of the detectorthat affect the noise of the system?Event rate What is the event rate of the system? Would thereadout circuit be able to deal with the event rate?Is segmentation required?Readout What is the architecture of the readout circuit?What are the burdens on the readout circuit?Cooling, supportstructures and cablesWhat are the required mechanical supports? Iscooling required? How the data are readout?Cost What is the overall cost of the system? How doesthe cost of the system affect the design consid-erations? Does the cost of the system affect itsrobustness?simulating the design using available tools. The designer has to change and opti-mize the design numerous times until simulations confirm that the design meets allthe specifications.When the circuit to be designed is intended for the readout of radiation detec-tors, the design must satisfy the characteristics of the sensor as well as the require-ments of the readout system. The main circuit design specifications of capacitivedetector readout systems are summarized and described in Table 2.2.19Table 2.2: Main circuit design specifications for capacitive detector readoutsystemsSpecification DescriptionDetector capacitance The capacitance of each pixel that loads thecharge amplifier.Detector leakage current The leakage current of each pixel that must becompensated.Energy range The range of absorbed energy by the detector.Energy resolution The smallest amount of deposited energy (orequivalently charge) that the system must beable to process.Input dynamic range The maximum amount of charge that the sys-tem must handle linearly.Signal-to-noise ratio (SNR) SNR determines the gain and noise level ofthe system.Counting rate Counting rate determines how fast the readoutsystem must process the signals.Radiation hardening tolerant Determines if the readout system must useprocesses that are tolerant to radiationPower consumption The maximum possible power consumptionof the readout systemSize The size of the module or the integrated cir-cuit2.3 Technology SelectionAfter analyzing the design requirements, the designer must decide on the technol-ogy to use for the integration of the design. A number of technologies exist for therealization of circuits including Bipolar, SOI, CMOS, and BiCMOS to name a few.Bipolar devices are often used for amplification. They can switch signals atvery high speeds and can provide large currents to the loads. So they are used inhigh frequency, high slewing, or high bandwidth applications. They are not suitablecandidates for applications that require high input impedance.20SOI technology is based on the use of a layered silicon-insulator-silicon sub-strate. In comparison with Bulk CMOS technology, it offers a lower parasitic ca-pacitance, lower leakage current, less antenna issues, resistance to latchup, and ahigher performance. However, it is not well adapted for the development of typicalanalog circuits. This technology is mostly used in silicon photonics, microproces-sors, and high performance radio-frequency applications.Bulk CMOS has been a popular choice for the integration of circuits. Theprocess is well-adapted for analog, digital, and mixed-signal applications. Whenit comes to small scale fabrication, it is very economical to use CMOS processesthanks to foundries that offer multi-project runs. The disadvantages of using bulkCMOS technology are high flicker noise, rapid scaling of technology which resultsin reduction of dynamic range and worsening of noise. When compared to Bipolartechnology, CMOS devices have worse matching. They also need to burn morepower for a given transconductance. In short, Bipolar technology offers betterperformance for the design of amplifiers, while CMOS technology has better noiseperformance, and offers many advantages for the integration of digital circuits.A BiCMOS process, as the name suggests, is designed to offer the advantagesof both Bipolar and CMOS technologies. The disadvantage of this technology isthat many advantages of CMOS and Bipolar technologies are not directly offeredby this technology without extra fabrication steps which adds to the cost. So thecomplexity of process and cost have been major factors in preventing this technol-ogy from widespread use.2.4 Readout Circuit DesignAs described in the previous chapter, a readout system usually contains variousstages for signal amplification, pulse shaping, digitization and further signal pro-cessing. Depending on the available silicon area and power consumption budget,the pulse shaping, digitization and signal processing may be performed outside ofthe integrated device using available commercial ICs. Figure 2.1 shows a detailedblock diagram of a complete readout system. A readout channel may contain oneor more of the following building blocks.• Charge-Sensitive Amplifier (CSA)21• Reset Network• Pole-Zero Cancellation (PZC)• Pulse Shaper• Peak-Detect and Hold (PDH)• Discriminator• Analog-to-Digital Converter (ADC)FromsensorCSA with leakage compensationPZ cancellationDiscriminatorPeak Detect Hold ADCPulse ShaperTriggerAnalogoutDigitaloutFigure 2.1: The block diagram of a complete readout channel.The signal at the output of the shaper (or sometimes CSA) must be digitizedfor storage or further processing. Analog-to-Digital Converters (ADCs) are usedfor this purpose. The waveform at the output of the pulse shaper must be trackedand then its peak value stored before passing the signal to the ADC. A Peak-Detectand Hold (PDH) circuit performs this task. For systems with a large number ofchannels, it is impractical to allocate an ADC per channel due to high cost in termsof area and power. Thus it is essential for such systems to multiplex the outputs ofchannels into a fewer number of ADCs. This way, only the events that need to bedigitized are processed by the ADCs. Obviously, a trigger signal must be generatedto identify the events. A discriminator is used for generating a trigger signal. Atrigger signal is generated whenever the signal level at the output of the shaper ishigher than a threshold level. In the following sections, we describe the operationand design of each block in detail.222.4.1 Charge-Sensitive AmplifierCharge-sensitive amplifiers are widely used in the design of readout circuits forvarious capacitive sensors, in particular, for solid-state radiation detectors. Otherapplications of CSAs include amplification of signals from piezoelectric sensors[88], photodiodes [89], and charge-coupled device (CCD) imagers [90]. Insensi-tivity of the gain to detector capacitance variations is the main motivation of usingCSAs in the front-end circuit of readout systems [22]. To maximize the achievableresolution, the noise of the readout circuit must be minimized. Since the noise ofthe system is mainly dominated by the noise of the CSA input device, designing alow-noise low-power CSA is of paramount importance in such readout circuits.Several design architectures exist for CSAs in the literature. Single-ended con-figuration is commonly used in design of CSAs to save power. In CSA design itis desired to increase the transconductance of the input device in order to improveboth speed and noise performance which ultimately results in increased devicewidth and capacitance. Use of cascode circuitry allows the designers to couple awide input device with narrow cascode devices. This unique feature of a cascodetopology helps provide a high gain as well as a high GBW. However, there is aconflicting trade-off associated with the cascode topology. From a noise point ofview, the input device must operate at a high current level in order to achieve agood noise performance. In contrast, in order to have a high output resistance (andconsequently a high gain), low cascode current level is desired. To overcome thisproblem, folded-cascode-based designs have been introduced by the designers. Infolded-cascode topology the DC and signal paths are separated. Therefore, theinput device and the cascode branch can operate at their optimum current levelsto achieve both a low-noise performance and a high gain. Early designs used thecascode topology [89, 91–93], however, most of the current designs are based onthe use of folded cascode topology [8, 44, 71, 94–102]. In addition to cascode andfolded-cascode designs a few different architectures exist in the literature. For ex-ample, in [103] an all NMOSFET CSA is proposed that has a power consumptionof only 1.2 µW but uses zero threshold voltage devices. In [96] split-leg straightcascode is chosen for implementation of the CSA which maximizes the currentin the input device. However, the output voltage swing is reduced compared to a23Cdet-AfCiQs QiCTΔVff CRte−fiCQfFigure 2.2: Principle operation of a typical CSA. Cdet and CT are the detectorand test capacitances respectively. The input dynamic capacitance isrepresented as Ci = (A+1)C f .split-leg folded cascode topology. In addition to standard CMOS designs, othertopologies exist for CSAs in the literature that use either bipolar or JFET devices[104–110].Figure 2.2 shows the principle of operation of a typical CSA. A CSA consistsof an inverting voltage amplifier with a high input resistance, a feedback capac-itance and a reset network (R f here). We assume that an input signal producesa signal charge of Qs = Qi +Qdet where Qdet is the deposited charge on the de-tector capacitance and Qi is the delivered charge to the input node of the CSA.Since the amplifier ideally has an infinite input resistance, no current can flow intothe amplifier and thus all the delivered charge must be integrated on the feedbackcapacitance.Qi =C f v f =C f [vi− (−A)vi] = (1+A)C f vi. (2.1)Therefore, C f appears as a dynamic input capacitance with an enhanced value ofCi =Qivi=(1+A)C f vivi= (1+A)C f . (2.2)The ratio of the integrated charge to signal charge then equals toQiQs=CiCi+Cdet=11+ CdetCi, (2.3)24which suggests that maximum charge transfer occurs when the dynamic input ca-pacitance is considerably larger than the detector capacitance (i.e., CiCdet).One advantage of CSAs compared to voltage amplifiers is that the charge gain iswell-defined.AQ =voQi=AviCivi=A(1+A)C f≈ 1C f. (2.4)Another advantage is ease of charge calibration. A test capacitor can be integratedon chip which can be used to inject a well-defined charge into the input node of theCSA (see Figure 2.2). If a voltage step of 4V is applied to a test capacitance ofCT , the injected charge will be equal toQin j =CT1+ CTCi+Cdet4V ≈CT (1− CTCi+Cdet )4V. (2.5)We will now calculate the input time constant of a CSA. This is particularly im-portant in order to understand how quickly charge is transferred from the detectorand also to estimate the required Gain-Bandwidth Product (GBW) for the CSA. Atfrequencies much larger than the corner frequency ( fc) of the amplifier and muchsmaller than the unity gain frequency ( f0), the input impedance of the amplifier canbe approximated asZi =Z f1−Av ≈Z f−Av =1jωC f−1j( ωω0 )=1ω0C f, fc f  f0. (2.6)which appears as a resistance (Ri). Therefore, the detector capacitance is dis-charged by a time constant ofτi = RiCdet =1ω0C fCdet =1ω0(C fCdet). (2.7)The required GBW of the amplifier can be calculated using (2.7). By combining(2.3) and (2.7), the charge transferred to the amplifier can be approximated asQ(t)≈ Qs1+ CdetCi(1− e−tτi ). (2.8)25In this equation Ci determines what fraction of the signal charge from detector istransferred to the amplifier and the time constant, τi, determines how quickly thecharge is transferred.2.4.2 Reset NetworkAs explained earlier, the generated charge from the detector is integrated on thefeedback capacitor. After integration, the voltage across the capacitor must bedischarged in order to prepare the system for another event. The role of a resetnetwork is to provide a path for discharging the capacitor either continuously ordiscretely. The reset network must be carefully designed as it directly contributesto the noise of the system. The discharge time of the CSA must be significantlylarger than the shaping time and also short enough to prevent pulse pile-ups at highevent rates. Implementing a large discharge time has the challenge of integratinga high value feedback resistor in the reset network. In our work, we need a circuitthat can accommodate leakage current of CZT detectors in the range of 1 fA to50 nA.A number of reset mechanisms can be found in the literature based on the tar-get application. The reset circuit are typically based on the use of a resistor [1],MOS device [2, 3], MOS switch [4, 5], current mirrors [6], self-adaptive biasingscheme [7, 8], current conveyor feedback [9], MOS device and N times replica ofit [10, 11], low-frequency feedback loop [12–14], or cold resistor [15] (see Fig-ure 2.3). Reset circuits that use resistors (see Figure 2.3a) are simple to design,however, it is often desired to increase the time constant of the reset network byincreasing the value of the resistor. Integrating a large-value resistor is difficult andarea consuming. Besides, the leakage current of the detector can saturate the chargeamplifier if the value of the resistor or the leakage current is high enough. The re-sistor is usually used in applications where charge integration and pulse shaping isfast.In the single MOS device configuration shown in Figure 2.3b the reset deviceis biased with a constant voltage source which provides the desired resistance. Thedevice is usually biased in weak inversion (or subthreshold) region to provide ahigh-value feedback resistance. This is essential in order to increase the discharge26-ACfRfOutIn-ACfOutInVb-ACfOutInS1(a) (b) (c)-ACfOutIn(d)-ACfOutIn(f)Vdd-ACfOutIn(h)RIbIbVddVrefVddM1M2M1 M2M3-ACf(e)In OutCompensation CircuitryR1R2-ACfOutInVbN×CfN×MfMf-AZ(g)-ACfRfOutIn Roffset A0C1R1R2(i)1:N27-ACfRfOutIn-ACfOutInVb-ACfOutInS1(a) (b) (c)-ACfOutIn(d)-ACfOutIn(f)Vdd-ACfOutIn(h)RIbIbVddVrefVddM1M2M1 M2M3-ACf(e)In OutCompensation CircuitryR1R2-ACfOutInVbN×CfN×MfMf-AZ(g)-ACfRfOutIn Roffset A0C1R1R2(i)1:NFigure 2.3: Common reset circuits using a (a) resistor [1], (b) MOS device[2, 3], (c) MOS switch [4, 5], (d) current mirror [6], (e) self-adaptivebiasing scheme [7, 8], (f) current conveyor feedback [9], (g) a MOSdevice and N times replica of it [10, 11], (h) low-frequency feedbackloop [12–14], and (i) cold resistor [15].28time-constant of the CSA and to lower the noise contribution of the resistor. Thisconfiguration is advantageous over a single resistor from an area point of view,however, the MOS device may exhibit non-linearities that need to be compensatedin the next stages.The MOS switch configuration (see Figure 2.3c) operates with a periodic re-set signal and discretely discharges the capacitor. This configuration suffers fromcharge injection and does not provide a discharge path for the leakage current ofthe detector.In the current mirror configuration shown in Figure 2.3d device M2 is biased inthe linear region. If a signal appears at the output of the CSA, the device enters thesaturation region and the bias current is copied to M1. Device M1 then dischargesthe capacitor with a constant current equal to Ib + Ileak where Ileak is the leakagecurrent of the detector. The bias current of the MOS devices must be small inorder to reduce the noise contributions of the reset network. This configurationmay introduce additional non-linearities that need to be compensated. The leakagecurrent of the detector can cause a DC shift at the output of the charge amplifier.In the self-adaptive biasing scheme shown in Figure 2.3e the output voltage isattenuated and applied to the source terminal of a PMOS device which is biasedin weak inversion region. Since the effective drain-source resistance of the MOSdevice is extremely dependent on the biasing condition, an adaptive compensa-tion circuitry is designed which compensates for the variations in the temperature,threshold voltage of the device, and the node voltages. This reset configuration canaccommodate a large leakage current because when the leakage current increases,the effective resistance of the device reduces and prevents the CSA from satura-tion. However, accommodation of the leakage current is achieved at the expenseof introducing additional non-linearities like the change in the associated pole.The current conveyor feedback (see Figure 2.3f) consists of a source follower,a small resistor, and a current mirror. The drain current of M3 is proportional to theoutput voltage (i.e., Vout = R.ID3). This current is scaled down by the current mirrorand then injected back to the input. Thus the configuration provides an equivalentfeedback resistance equal to N.R where N is the current gain of the current mirror.A Bipolar Junction Transistor (BJT) is used as the input device of the CSA in orderto sink the leakage current of the detector. This scheme offers a good linearity by29using a resistor. The noise from the resistor and the scaling down network must beminimized.The configuration shown in Figure 2.3g uses a MOS device and a feedbackcapacitor connected to the next stage through N times replica of the MOS and thefeedback capacitor. The MOS devices are biased above threshold and in the sat-uration region. They share the same gate-to-source voltage. An N times leakagecurrent of the detector appears at the input terminal of the following stage whichmust be absorbed without saturating the stage. This configuration completely com-pensates the leakage current of the detector and also provides a good linearity, how-ever, implementing and matching of N times replica of the MOS and the feedbackcapacitor is challenging (e.g., N can be as high as 144).The low-frequency feedback loop shown in Figure 2.3h uses a differential pairand a current mirror. Each transistor of the differential pair is biased at Ib/2 in thesteady state mode. After each integration the output of the CSA recovers back to itsDC level (i.e., Vre f ) thanks to the low-frequency feedback loop. This configurationoffers a good linearity and complete leakage compensation.The cold resistor configuration shown in Figure 2.3i uses an amplifier and pas-sive components to automatically zero the DC voltage at the output of the CSA.This configuration can provide full leakage compensation. The reset mechanismused in the configuration reduces the effective value of the feedback resistor (i.e.,makes it a cold resistor). As a result, the resetting process becomes faster withno additional noise and no loss of sensitivity. However, the offset voltage of theamplifier needs to be compensated or will affect the final offset of the circuit.Amongst the mentioned reset configurations, the Krummenacher’s low fre-quency feedback loop is the most popular one [23, 44, 111]. In this circuit theoutput of the CSA is compared with a reference voltage and then drain current of aMOS transistor is adjusted to compensate the leakage current. This configurationprovides full leakage compensation but may introduce a pole and a zero and somenon-idealities that need to be compensated.30C3R31Vin VoutR4C21R2C11VinR1C21R2Vout(a)(b). ftk e. ftk e 1.tk eIntegratorDifferentiatorPZC circuitIntegratorFigure 2.4: (a) Circuit schematic of a first-order CR-RC pulse shaper, and (b)use of a PZC network in the CR-RC pulse shaper circuit to cancel thelong decay time of the input signal.2.4.3 Pole-Zero Cancellation (PZC) CircuitThe signal from the charge-sensitive amplifier is not an ideal step function andhas a finite decay time. If this signal is passed through a shaping network, thefinite decay time of the amplifier causes a long undershoot at the output which isundesired. The amplitude of the undershoot is higher when the amplifier passes alarge pulse to the pulse shaper. This will temporarily shift the baseline which is alsoundesired. In order to suppress the undershoot at the output of the pulser shaper,the associated pole with the preamplifier must be cancelled. This is achieved usinga pole-zero cancellation (PZC) network. To see how the PZC circuit functions,let’s consider a first-order pulse shaper and analyze the equations.Figure 2.4a shows a first-order CR-RC pulse shaper. The transfer function of31the pulse shaper is given byVout(s)Vin(s)=sτ1(1+ sτ1)(1+ sτ2), (2.9)where τ1 and τ2 are the time constants of the differentiator and integrator in thepulse shaper’s network respectively. The signal from the preamplifer has a formof k.exp(−tτ f ) and is passed to the pulse shaper. The resulting output signal infrequency domain isVout(s) =kτ f1+ sτ fsτ1(1+ sτ1)(1+ sτ2). (2.10)As can be seen in (2.10), the associated pole with the preamplifier appears at theoutput of the pulse shaper. It is possible to cancel this pole by introducing a zero inthe transfer function of the pulse shaper. The modified circuit of the pulse shaper isshown in Figure 2.4b. In this figure, the differentiator is replaced with a circuit thatproduces a zero and a pole in the transfer function of the pulse shaper. The outputsignal in Figure 2.4b is given byVout(s) =ks+ 1τ fs+ 1R3C3s+ 1C3 (1R3+ 1R4 )1s+ τ2. (2.11)In (2.11), if we set 1τ f =1R3C3and 1C3 (1R3+ 1R4 ) =1τ1 , then the equation for the outputsignal in frequency is reduced toVout(s) =ks+ τ11s+ τ2. (2.12)The above equation shows that the associated pole with the preamplifier is can-celled by the zero of the PZC network.2.4.4 Pulse ShaperIn detector readout circuits, the signal from the CSA is often passed through afilter before performing amplitude or time measurements. As the filtering processaffects the amplitude or timing of the pulse signal, this type of signal processing32is called pulse shaping. The most common pulse shaping method is to produce apulse whose peak amplitude is proportional to the detected charge in the detector.Several pulse shaping methods can be found in the literature including CR-RC [23, 44], trapezoidal/ triangular [112, 113], delay-line [114, 115], and Semi-Gaussian (SG) pulse shaping [10, 21, 95]. Passive CR-RC pulse shapers are real-ized by cascading a differentiator by an integrator. They can also be realized usingactive elements. The simplicity of design and ease of controlling the shaping timemakes these pulse shapers very attractive. However, the signal-to-noise ratio (SNR)in this pulse shaping method is not very good and large pulse pile-up errors willoccur at high event rates because of the long tail of the output pulse. The prob-lem of slow return to zero can be solved by adding another differentiation stage.The resulting pulse shaping filter is called double differentiation shaper. This pulseshaper produces bipolar shaped pulses which are useful for high event rate applica-tions. In practice, double differentiation shaping introduce a small baseline shift asthe two lobes of the shaped signal are not of exactly equal area. At low event rates,the noise performance of these pulse shapers is worse than that of CR-RC shapers.Theoretically, triangular pulse shaping results in a higher SNR compared toCR-RC or Gaussian shaping. In practice, true triangular shaping can not be realizedusing passive components. However, it is possible to achieve a semi-triangularpulse shaping by using active elements but the design is usually difficult and cost-ineffective. Trapezoidal pulse shapers are mostly used for detectors in which thecharge collection time is dependent on the position of radiation interaction. The flattop of these pulse shapers results in pulses with the same peak amplitudes whereasuse of others pulse shapers without a flat top will produce pulses with slightlydifferent amplitudes. Delay-line shapers (single or double) are not popular choicesfor high resolution solid-state detectors due to their poor noise performance. Theyusually introduce undesirable artifacts into the signal and to alter the width of thepulse it is necessary to change the length of the delay line [22].SG filters are the most popular pulse shapers for solid-state radiation detectors.They can be realized using either active or passive elements. The peaking timein these shapers is longer than CR-RC pulse shapers and the shape of the signal ismore symmetrical. This results in a faster return to the baseline and thus pulse pile-up errors at high event rates are reduced. A 4th-order SG shaper produces shaped33pulses which are quite close to true Gaussian ones.2.4.5 Peak-Detect and Hold (PDH)The analog voltage at the input of the ADC must stay constant during conversion.To fulfil this requirement, the output of the pulse shaper must be passed to a PDHcircuit (also called a pulse stretcher). The PDH generates a signal with an am-plitude equal to the height of the input signal but for a longer duration. The mostsimple PDH consists of a diode and a capacitor which is shown in Figure 2.5a. Fig-ure 2.5b shows a modified version of this architecture which effectively decreasesthe impedance of the diode by a factor of (A+1). The main drawback of this cir-cuit is the reverse dark current of the diode which causes progressive lowering ofthe hold voltage. Figure 2.5c shows a popular CMOS PDH [39, 116–119]. Therectifying elements in this architecture are realized using current mirrors insteadof diodes. The circuit in Figure 2.5c suffers from offset. An offset-free two-phasePDH is proposed in [120]. Another design for high speed and high event rate ap-plications is introduced in [121] which is based on the offset-free two-phase circuitdescribed in [120]. The proposed design uses a leakage compensation scheme tolower the output DC error. Another design is introduced in [122] which uses tworamps with different slopes to sample the input voltage. The simulated error ofthe peak value is less than 1% for this design and the droop voltage is less than20 µV/µs. The drawback of this approach is its high power consumption.2.4.6 DiscriminatorPulse height discriminators are used to generate trigger signals for the channelswith incidents. Ideally, a discriminator must deliver a signal when the input pulseheight is higher than a threshold level regardless of the input pulse shape. Thediscriminator must also recover fast enough and completely in order to processtwo close signals. In addition, the dead-time must be constant with respect to thepulse height of the signal at the input of the discriminator.A common method to realize a discriminator is by using a fast comparator.The general design techniques for high-speed comparators is described in [123]. Afully differential realization of a discriminator is presented in [124]. In [125], the34(b)AVinVoutCh---(a)Vin VoutCh(c)ChLoadVinVb ResetVoutVddFigure 2.5: PDH employing (a) a diode, (b) an amplified diode, and (c) cur-rent mirrors and an OTA.design of high-speed and high-resolution multi-stage comparators is described indetail. The design is optimized in terms of number of stages as well as the offset ofthe circuit. A low-power autozeroed high-speed comparator is introduced in [126].The achieved resolution is better than 1 mV at operating speeds more than 10 MHz.2.4.7 Analog-to-Digital Converter (ADC)The ADCs used in detector readout circuits must satisfy several design specifica-tions:35• ResolutionThe resolution of an ADC is a measure of granularity of the digitized output.In order to accurately digitize the analog input, the resolution of the ADCmust be considerably better than the noise level of the input. This means thatthe digitization error must be small compared to the noise level of the inputsignal.• Integral nonlinearityThis parameter shows how much the relationship of the digitized output tothe analog input deviates from absolute linearity. The linearity of the ADCvaries by the pulse shape and duration of the input signal. Increasing theduration of the input signal can improve the integral nonlinearity of the ADC.• StabilityStability shows whether conversion gain and baseline change over time. Inprecise measurements it is necessary to monitor changes in conversion pa-rameters of the ADC.• Differential nonlinearityDifferential nonlinearity is used to express how uniform the digitization in-crements are. Special attention must be given to the differential nonlinear-ity as a differential nonlinearity of higher than ± 0.5 LSB can result in anonmonotonic conversion. This means for some analog inputs an increasein signal will generate decreased digital outputs. In poor ADC designs thewidth of bins may differ systematically.• The count-rate performanceThe count-rate performance of the ADC must be examined carefully as de-tectors often generate signals randomly which is in contrast with most sys-tems where inputs are sampled at regular intervals.• Conversion timeThis parameter shows how long it takes for the ADC to complete the digi-tization. Obviously, the system cannot accept a new input during this dead36time. Signal acquisition time, conversion time, and readout time contributein the dead time of the system. In continuous-event systems, the dead timecan be ignored if the event rate is smaller than the conversion time.Different conversion techniques exist in the literature which are suitable for usein detector readout circuits. Flash [127, 128], successive approximation [129, 130],Wilkinson [131–134], and pipelined [135, 136] ADCs are relevant architectureswhich are usually used for digitization of the output signal of the pulse shapers.A combination of these architectures may also be used in order to obtain highresolution and fast conversion time. The principle of operation and pros and consof relevant digitization techniques are reviewed.• Flash ADCFlash conversion is the simplest technique which enables fast conversion butwith the expense of area and high power consumption. In this technique theanalog input is fed to a bank of comparators. An n-bit converter requires 2ncomparators. The threshold voltage of comparators are set by a resistive di-vider which provides a constant relative resolution over the entire conversionrange.• Successive Approximation Register ADCsuccessive approximation register (SAR) ADC is commonly used in vari-ous readout circuits which require medium to high resolution of digitization.This technique makes efficient use of circuitry but with a drawback of poordifferential nonlinearity. In this technique the analog input is fed to a pulsestretcher and a binary search algorithm is used to determine the digitizedoutput. In the first step the Most Significant Bit (MSB) of the output code isset to 1 and the code is passed to a digital to analog converter (DAC). Thisforces the output of the DAC to be Vref/2 where Vref is the reference voltagesupplied to the DAC. The output voltage of the DAC is then compared withthe output voltage of the pulse stretcher. If the output voltage of the DACis greater than the output voltage of the pulse stretcher, the MSB is set to 0,otherwise remains at 1. In the next step the second MSB is set to 1 and acomparison is made. Again, depending on the result of comparison, this bit37is cleared or remains at 1. The sequence continues until the last bit is deter-mined. Thus, an n-bit successive approximation converter requires n steps.The major concern in this technique is the accuracy of the resistors that setthe DAC levels. It is very difficult to implement extremely accurate resistorson chip and this leads to poor differential nonlinearity.• Pipelined ADCPipelined ADC is one of popular techniques which is used in applicationsthat require fast conversion time. Unlike other techniques, the throughput isdetermined by the maximum time per stage and not the total conversion time.In one implementation of a 12-bit pipelined ADC the input signal is fed to asample and hold (S&H) and a 3-bit Flash ADC. The output of the Flash ADCis fed to a DAC with 12-bit resolution. The resulting signal is then subtractedfrom the original signal which has been maintained by the S&H. The outputsignal from this stage is then passed to three similar stages sequentially forfurther quantization. Each stage provides 2 bits of resolution and one bit forerror correction. The last 4 bits are resolved using a 4-bit Flash ADC. Thedrawback of this architecture is high number of components.• Wilkinson ADCWilkinson ADC was first introduced in 1950 and since then has been widelyemployed in precision pulse digitization systems. This technique is basedon comparison of the voltage across a discharging capacitor with a baselinevoltage. The input analog input is first fed to a pulse stretcher/peak detectorand its peak amplitude voltage is stored on a capacitor. Then the capacitoris disconnected from the input and a current source is turned on which dis-charges the capacitor with a constant current. As the discharge commences,a counter is enabled to count the number of clock pulses until the voltageacross the capacitor reaches the baseline level. The discharge time of the ca-pacitor and consequently the conversion time is a linear function of the inputpeak amplitude. This technique basically offers excellent differential linear-ity as the clock pulses are precise and uniform. Other advantages includeefficient use of circuitry and low power consumption. The only drawback is38the relative long conversion time.In summary, flash ADCs enable fast conversion rates but at the expense oflarger area and higher power consumption. SAR ADCs are commonly used inreadout circuits which require medium to high resolution digitization. This tech-nique makes efficient use of hardware; however, its relatively poor differential lin-earity is usually problematic. Pipelined ADCs are also popular candidates whichare used in applications that require fast conversion time. Unlike other techniques,the throughput is determined by the conversion time of one stage. The powerconsumption of these types of ADCs is moderate but they typically have a highercomplexity in comparison with SAR structures. The pros and cons of the commontechniques for digitization of the output signal of the pulse shaper are summarizedin Table 2.3.Table 2.3: Performance comparison of various digitization techniques for de-tector readout circuitsDigitization technique Advantages DrawbacksFlash ADC fast conversion high number of compo-nentsmonotonic conversion high power consump-tionSuccessive approximation moderate power con-sumptionpoor differential nonlin-earityADC efficient use of circuitryWilkinson ADCexcellent differentialnonlinearityrelatively long conver-sion timeefficient use of circuitrylow power consumptionPipelined ADC* moderate power con-sumptionhigh number of compo-nentsfast conversion*Assuming Flash ADCs are used in implementation of the pipeline stages2.5 Noise EvaluationThe minimum detectable signal from the detector is limited by the electronic noiseof the readout system. This is often referred to as the detection resolution of the39system. The noise of the readout system must be minimized to improve the res-olution of detection. Measurement of energy, timing or position are affected byrandom noise. For an example, if a timing signal is measured by a comparator, thefluctuations in the leading edge of the signal due to noise is translated into timeshifts.Electronics noise can be divided into random and non-random categories. Ran-dom noise in electronic elements has a Gaussian distribution. Three commonsources of noise exist in electronic elements which include thermal (or Johnson),flicker (or 1/f), and shot noise.Thermal noiseThis noise is due to thermal fluctuations of the electron distribution in a conductor.The spectral voltage and current densities in a resistance R are [137]de2nd f= 4kT R, (2.13)anddi2nd f=4kTR(2.14)where k is Boltzman constant and T is the temperature. As the thermal spectralvoltage and current densities are independent of frequency, the thermal noise isoften referred to as white noise. The total noise is obtained by integrating overthe bandwidth of the system. Increasing the bandwidth of the system increases thetotal noise. Increasing the speed of a pulse measurement system will increase thenoise since bandwidth is inversely proportional to rise time.Flicker noiseThis type of noise exists in many electronic devices such as FETs. The source offlicker noise is not unique meaning that different devices can exhibit flicker noisedue to different mechanisms. The noise power spectrum has a 1/f dependence andis shown by [138]de2nd f=A ff α f, (2.15)40where A f and α f depend on the device and fabrication process.Shot noiseShot noise is due to the statistical fluctuation in the number of charge carriers. Shotnoise requires the presence of a current flow with the condition that the carriers areinjected independent of each other. This is the case in semiconductor diodes. Thefrequency spectrum of the noise current is given by [138]di2nd f= 2qI, (2.16)where q is the charge of one electron, and I is the current.To evaluate the noise of a detector readout system simulations and analyticalmethods are often used. We will discuss analytical noise analysis of modern detec-tor readout circuits in Chapter 3. Noise simulations can be done using commercialcircuit simulators (e.g., Cadence Analog Design Environment or HSPICE). Thedesigner specifies the input and output ports of the circuit as well as the frequencyrange for which the output noise will be calculated. The tool calculates the DCoperating points, and computes the transfer function between the specified inputand output ports. The simulator linearizes the circuit about the DC operating pointand calculates the total noise spectral density at the output port.2.6 Layout Considerations and Chip DesignAfter the circuit is simulated a layout must be generated to enable the fabricationof the chip. The layouts are used by the foundries to extract the masks used for fab-rication. The geometries of transistors, resistors, capacitors and other componentsare entered in a computer aided design (CAD) tool (e.g., Cadence Virtuoso R©). Anumber of design rules must be obeyed during the layout. The rules are intendedfor the manufacturability, robustness, and maximizing the yield of the technology.They prevent failure mechanisms such as electrostatic discharge (ESD), electro-migration, antenna effects, and metal fracturing [139]. ESD can be prevented byusing ESD structures such as diodes at the input and output pads. To prevent elec-tromigration, metal widths can be made wider. Antenna effects can be avoided41by changing the order of the routing layers, adding vias near the gates, or addingdiodes to the nets. Metal fracturing is caused by sharp steps since the requiredcurrent cannot be passed. To avoid this phenomenon sharp steps must be replacedby several smaller steps.After the layout is done and the design passed the rule checks, layout versusschematic (LVS) must be called. This is to ensure that the generated layout repre-sents the designed schematic. After this process the parasitics must be extracted.The parasitics mainly include bulk resistances, capacitances between conductors,and capacitances from conductors to ground. The integrated circuit must be sim-ulated again with the parasitics included. This ensures that the parasitics do notcause failure or undesired behaviour.Once the layout of the chip is done and post-layout simulations are carried out,the chip can be sent to foundries for fabrication. After the device is fabricated, itis usually housed in a packaged. A package protects the die, powers up the circuit,and provides the electrical connection between the circuit and other components ofthe system.The integrated circuits used in detector readout systems are exposed to irradi-ation. Irradiation can cause latch up, shift the threshold voltage of devices, andincrease the leakage current. It can ultimately fail the readout circuit. Dedicatedradiation hard technologies exist for the systems that require high radiation toler-ance. For other systems it is possible to use standard CMOS technologies underconditions.Irradiation measurements on transistors in different CMOS technologies showthat the threshold shift due to irradiation reduces significantly for oxides thinnerthan about 10 nm [140, 141]. Current sub-micron CMOS technologies offer de-vices with an oxide thickness in that range. So it is expected that the thresholdvoltage shift due to irradiation in deep sub-micron technologies would be negligi-ble. However, irradiation can be ionizing which causes leakage in NMOS devices[140]. The leakage current in these devices can be reduced significantly by properlayout techniques. It has been shown in [142] that use of enclosed geometry forNMOS devices and guard rings prevents radiation-induced leakage current in astandard CMOS process. The approach described in [142] is appealing for deep-micron technologies where overhead area is to some extent compensated by the42increased integration density.43Chapter 3Analytical Noise Analysis ofFront-end Circuits for Solid-StateRadiation Detectors3.1 IntroductionIn this chapter, we analyse the noise behavior of state-of-the-art readout systemsfor solid-state radiation detectors in detail. We will derive the ENC equations ofthe system analytically taking into account the additional noise contributions andthe requirement of modern readout systems. The equations are valid for all regionsof operation of the input MOS device of the CSA. We will use a Semi-Gaussian(SG) pulse shaper as an example to show the procedure for noise analysis andoptimization. We will also discuss the effects of the design parameters of the shaperon the ENC equations of the readout system.A readout circuit may have one or more amplification stages. Assuming thatthe circuit is well-designed, the noise of the amplifier chain is dominated by thenoise of the first amplifier stage (i.e., the CSA). A CSA must be designed suchthat its noise is dominated by the noise of its input amplifying device [87]. SinceCSAs often employ MOS devices as their input amplifying element, it is essentialto understand the noise sources in these devices. In the following subsection we44review the main noise sources in MOS devices.3.1.1 Noise Sources in MOS DevicesThermal and flicker noise are the two primary noise sources in MOS devices. Othernoise sources that are often neglected include thermal noise associated with theresistive poly-gate, thermal noise associated with the resistive substrate, and shotnoise due to the gate leakage current. We hereby review the primary noise sourcesin these devices. The contribution of other noise sources becomes significant whenthe devices are realized in ultra-deep submicron technologies. We will deal withsuch noise sources in the rest of this chapter.Thermal noiseThe thermal noise is due to the thermal velocity fluctuations of the charge carriersin the channel [87]. The behavior of the thermal noise can be modelled by a voltagenoise source in the gate of the device. This noise is frequency independent and itsspectral power density is given by [82, 138]Sw,ser = Γ4kBTgm, (3.1)where Γ is the coefficient of the channel thermal noise, T is the absolute temper-ature, kB is the Boltzmann’s constant, and gm is the transconductance of the inputdevice of the CSA.Flicker noiseThe origin of flicker noise in MOS devices is the number fluctuation due to chargetrapping [138]. This noise can be modelled by a frequency-dependent voltage noisein the gate of the device. The spectral power density of flicker noise is given by[82, 138, 143]S f ,ser =K f sf α f s CoxWL, (3.2)where K f s is the intrinsic process parameter, W is the device width, L is the devicelength, and Cox is the gate oxide capacitance per unit area. The value of α f s is tech-nology and device dependent. In conventional noise analysis it is often assumed45∫ ∫n integratorsdifferentiatorVin VoutFigure 3.1: The block diagram of a Semi-Gaussian pulse shaper.that the flicker noise is independent of the device bias current and the noise spectralpower density is inversely proportional to the frequency (i.e., α f s = 1). Contrary,recent studies show that the value of K f s can be bias dependent [143] and the valueof α f s is not exactly equal to 1.3.1.2 Pulse Shaper AnalysisPulse shapers play an important role in the overall noise performance of the readoutsystem. Understanding the behaviour of pulse shapers is essential when designinga low-noise readout system is concerned. Let’s first consider a simple CR−RC fil-ter. This pulse shaper is basically a CR high-pass filter (a differentiator) followedby an RC low-pass one (an integrator). The integrator limits the bandwidth of thesignal and the differentiator sets the desired decay time. The readout systems thatuse CR−RC pulse shapers cannot operate at high counting rates. This is due tothe fact that the output of the filter returns to the baseline slowly preventing highcounting rates. The problem can be avoided by passing the signal through addi-tional integrators which makes the output pulses more symmetrical. The resultingfilter is called a Semi-Gaussian CR− (RC)n pulse shaper. Its block diagram isshown in Figure 3.1. Better signal-to-noise characteristic is another advantage ofSG over CR−RC pulse shapers [22].The transfer function of an SG pulse shaper consisting of one differentiatorfollowed by n integrators isH(s) =sτd1+ sτd×(ASH1+ sτi)n, (3.3)46where τd and τi are the time constants of the differentiator and integrators respec-tively. ASH is the DC gain of the integrators and n is the order of the shaper. Thepeaking time defined by τs = nτi is the time that the output of the shaper reachesthe peak amplitude. τs is an important design parameter as it affects the noise band-width. It is very common to choose τd = τi = τ in SG pulse shapers which reducesthe transfer function toH(s) =(ASH)n sτ(1+ sτ)n+1. (3.4)In time domain, the output signal due to one electron charge delivered by the de-tector can be simply calculated as [71]Vo(t) = L−1{qsC fH(s)}=qAn nnC f n!(tts)ne(−ntτs ), (3.5)where q corresponds to one electron charge (i.e., q = 1.6× 10−19 C). The peakamplitude of the signal equals toVo,max =Vo(t = τs) =qAn nnC f n!en. (3.6)3.2 Derivation of Equivalent Noise Charge (ENC)EquationsThe noise of a detector readout system is usually expressed as the equivalent noisecharge or ENC. The ENC is defined by the ratio of rms noise at the output ofthe pulse shaper to the signal amplitude due to one electron charge [71]. In otherwords, ENC is the number of input charges for which the signal-to-noise ratio at theoutput of the pulse shaper equals one. Although ENC is a convenient measure ofsystem noise, it is not a primary quantity. In fact ENC is derived from contributionsof the voltage and current noise sources of the system. ENC is often expressed interms of units of electric charge (i.e., q = 1.6×10−19 C) or in fC. Mathematically,ENC can be expressed asENC =√V 2no,totV 2o,max, (3.7)47Noisy circuitNoiseless circuit- +en2in2(a) (b)Figure 3.2: (a) Model of a noisy two-port network, and (b) model of the net-work with the noise sources referred to the input.where V 2no,tot is the total integrated noise power at the output of the pulse shaper,and Vo,max is the peak amplitude of the output signal due to one-electron charge.The ENC depends on the characteristics of both the CSA and the pulse shaper.For the purpose of noise analysis, we first need to model the noise of the read-out system. The noise of any two-port network can be modelled by equivalentvoltage (series) and current (parallel) noise sources, typically referred to the inputports of the network [144]. These noise sources are illustrated in Figure 3.2. In awell-designed front-end circuit, the noise of the system is dominated by the noiseof the input MOS device of the CSA. The series and parallel noise power spectraldensities are uncorrelated [71] and therefore, the total equivalent noise charge ofthe readout circuit can be calculated by the sum of the individual ENC contribu-tions.The power spectral densities of the readout circuit can be expressed by thefollowing equationsde2nd f= Sw,ser +S f ,ser, (3.8)di2nd f= Sw,par +S f ,par. (3.9)where the first term in each equation contains frequency independent (white-like)and the second term frequency dependent portion of the noise power spectral densi-ties. The series and parallel power spectral densities are uncorrelated and therefore48the total noise power spectrum at the output of the CSA can be expressed asV 2no,CSA =∣∣∣∣Cdet +C f +CinC f∣∣∣∣2 e2n+ ∣∣∣∣ 1sC f∣∣∣∣2 i2n=∣∣∣∣CtotC f∣∣∣∣2 e2n+ ∣∣∣∣ 1sC f∣∣∣∣2 i2n, (3.10)where Cdet is the detector capacitance, and Cin is the input capacitance of the inputdevice of the CSA. Cin can be extracted from SPICE simulations.The total integrated rms noise at the output of the pulse shaper can be calculatedusing the following equationV 2no,tot =∫ ∞0|Vno,CSA|2×|H( j2pi f )|2 d f . (3.11)The ENCs of the readout system can now be calculated by substituting (3.6) and(3.11) into (3.7). Since the power spectral densities in equations (3.8) and (3.9) aretotally uncorrelated, it is more convenient to deal with them separately.3.2.1 Power Spectral Density of the Equivalent Voltage Noise SourceThe series white noise voltage spectrum can be expressed by the following equationSw,ser = Γ4kBTgm, (3.12)where Γ is the coefficient of the channel thermal noise, T is the absolute temper-ature, kB is the Boltzmann’s constant, and gm is the transconductance of the inputdevice of the CSA. The value of Γ depends on the region of operation of the de-vice and can be described by the following equation which is valid for all inversionregions of MOS devices [82]Γ= αw nsub γ. (3.13)In this equation αw is the thermal noise excess factor, nsub is the sub-thresholdslope factor, and γ the thermal noise coefficient. The value of the coefficient γvaries from 1/2 in weak inversion to 2/3 in strong inversion [82]. By substituting(3.12) into (3.10) and (3.11) and taking the integral, the total integrated rms thermal49noise at the output of the shaper can be obtained asV 2n,w,ser = αw nsub γ4kBTgm(CtotC f)2×((ASH)2nB(3/2,n−1/2)n4pi τs), (3.14)where n is the order of the pulse shaper. B(x,y) represents the Beta function and isdefined byB(x,y) =∫ 10tx−1(1− t)1−y dt =∫ ∞0tx−1(1+ t)x+ydt. (3.15)The value of B(x,y) can be obtained using the beta function in MATLAB R©.The ENC of the system due to thermal noise can be calculated by substituting(3.14) and (3.6) into (3.7) and is given byENC2w,ser = αw nsub4KBTgm×((n!)2e2nn2n)×(C2tot(ASH)2nB(3/2,n−1/2)nq2 τs). (3.16)This general expression for the series white noise is valid for all regions of opera-tion of the CSA input device.The series flicker noise voltage spectrum can be expressed by the followingequation [143]S f ,ser =K f sf α f s CoxWL, (3.17)where K f s is the intrinsic process parameter. Experimental data for MOS devices insubmicron technologies shows that the parameter K f s can be bias dependent [143].The corresponding ENC f ,ser due to series flicker noise is given by the followingequationENC2f ,ser =K f sC2tot2q2CoxWL×((n!)2e2nn2n)× (2piτ0)α f s−1×B(3−α f s2,n+α f s−12). (3.18)503.2.2 Power Spectral Density of the Equivalent Current Noise SourceThe reduction of the oxide thickness with the scaling of CMOS technology hasincreased contributions of a few noise sources that otherwise could have been ne-glected without significantly affecting the overall noise performance of the system.When implemented in advanced CMOS processes, a major noise source that needsto be taken into account is the gate leakage current of the input device of the CSA.This leakage current is mainly due to the tunnelling phenomena. Gate-to-invertedchannel current (IGC) and the parasitic current through gate-to-source or gate-to-drain extension overlap region (IGS or IGD) are the main components contributingto the gate leakage current [143]. A combination of white-type and quasi 1/ f noisebehaviour is generally used to model the noise associated with the gate leakage cur-rent.The frequency independent (white-like) noise contributions in the device gateleakage current can be modelled by the following equation [79]Sw,par = 2q(|IGC|+ |IGS|+ |IGD|) = 2qI0, (3.19)where I0 is the total gate leakage current. The ENCw,par is obtained by evaluating(3.7) using (3.19) and (3.6) and is given byENC2w,par = 2qI0τsq24pin((n!)2e2nn2n)× B(12,n+12). (3.20)Please note that (3.20) can also be used to calculate the ENC of the system due tothe leakage current of the detector.The frequency dependent noise contribution in the gate leakage current is mod-elled by the following equation [79]S f ,par =K f pf α f p×[I2GCW (L−2∆L) +I2GS+ I2GDW∆L]=K′f α f p, (3.21)where K f p is the intrinsic parallel flicker noise coefficient, W is the device width,L is the channel length, and ∆L is the gate-to-source/drain overlap length. TheENC f ,par of the system due to parallel flicker noise is given by the following equa-51tionENC2f ,par =(K′ (τ0)22q2 (2piτ0)1−α f p)((n!)2e2nn2n)×B(1−α f p2,n+1+α f p2). (3.22)The total equivalent noise charge of the readout circuit is given by the sum of theindividual ENC contributionsENC2tot = ENC2w,ser +ENC2f ,ser +ENC2w,par +ENC2f ,par. (3.23)Optimal design of the readout system is achieved by minimizing (3.23) withrespect to the design parameters of the CSA and pulse shaper simultaneously. Inthe following section we discuss the effects of the parameters of the shaper on theoverall noise of the system.3.2.3 Pulse Shaper’s ParametersThe transfer function of a SG pulse shaper is characterized by three parametersbut only two of them appear in the ENC equations: the shaping time (τs) andthe number of integrators (n). In order to obtain insight into the effects of shaper’sparameters on the overall noise of the readout system, we evaluate noise of a typicaldetector readout circuit in a 0.13 µm CMOS process. Let us assume that a detectorwith 0.5 pF capacitance is read out by a CSA and a SG pulse shaper. The inputtransistor of the CSA is an NMOS device with W/L = 41µm/0.2µm and drawsIDS =10 µA. The feedback capacitance is assumed to be 20 fF. Figure 3.3 showsthe ENCtot of the readout circuit in a 0.13 µm CMOS process as a function ofpeaking time and order of the pulse shaper. Gate current noise data are taken from[79]. As expected, for a fixed order n and for short peaking times, the ENCtotgradually decreases when shaping time increases. However, at large peaking timesthe gate leakage current slightly increases the noise of the readout circuit. So thenoise due to gate leakage current can be safely neglected in this technology withoutsignificantly affecting the overall noise performance of the system. Similarly, fora fixed peaking time, the ENCtot decreases when the number of integrators (n)52Figure 3.3: Effect of shaping time and order of the shaper on the ENCs of adetector readout system in a 0.13 µm CMOS process.increases. Please note that the shot noise due to the dark current of the detector isnot taken into account in this analysis. This noise source, modelled with a parallelnoise current, gradually gives rise to the ENCtot after a range of peaking times.3.2.4 Process ScalingIn order to see the effects of process scaling, ENCtot of the same readout circuit iscalculated in a 90 nm CMOS process. The result is shown in Figure 3.4. Compar-ing the ENCs plotted in Figure 3.3 and Figure 3.4 shows that in deep submicrontechnologies the noise due to the gate leakage current cannot be neglected espe-cially at large peaking times. The gate leakage current in a 90 nm process is about2-3 orders of magnitude larger than in a 0.13 µm process [79]. Moreover, in deepsubmicron processes the gate leakage current is strongly dependent on the drain-to-source voltage of the input MOS device when the device is biased in weak ormoderate inversion regions [79, 145]. This noise analysis confirms that the paral-lel noise sources must be accurately modelled when improving the resolution ofreadout system implemented in an advanced CMOS process is concerned.53Figure 3.4: Effect of shaping time and order of the shaper on ENCs of a de-tector readout system in a 90 nm CMOS process.3.3 Measurement of Noise of the Readout SystemAs explained earlier in Section 3.2, the ENC is defined by the ratio of rms noiseat the output of the pulse shaper to the output signal amplitude due to one electroncharge [71]. In practice, it is not possible to inject one electron charge into thecircuit and measure the corresponding output peak amplitude. This means that it isessential to inject a practical amount of charge to be able to determine the ENC ofthe system. To account for this practical limitation, equation (3.7) can be rewrittenasENC = Qsig/(S/N) = (Vno/Vsig)Qsig, (3.24)where Qsig is the input signal charge, and Vsig and Vno are the output signal pulseheight and output noise respectively. These three parameters must be carefullymeasured in order to calculate the noise of the system. To do this, a known step-like signal (VTest) is applied to an integrated test capacitance (CTest) and the relevantoutput parameters of the pulse shaper are measured. In this situation, the inputcharge is known (i.e., Qsig = VTestCTest) and the other two parameters need to bemeasured by a proper instrument.The easiest method to calculate the ENC of the readout system is to use a mul-54tichannel pulse height analyzer. A multichannel analyzer (MCA) is an instrumentthat measures the pulse height spectrum. The output of the MCA is usually sentto a computer for analysis, display, or storage. An MCA usually consists of a dis-criminator, an analog-to-digital converter (ADC), a memory, and a display. Whenthe amplitude of the incoming pulses is higher than a threshold, the pulse is cap-tured for further processing. The ADC only digitizes the maximum height of thepulse and the digitized value is stored in a memory. The MCA only accepts anotherpulse once the processing of the current pulse is finished. By counting the numberof pulses of each height over a period of time we can plot the energy spectrum ofthe electromagnetic wave. The peak centroid shows the magnitude of the signaland the width of the peak represents the noise. The equivalent noise charge of thereadout system can be calculated usingFWHM = 2.35×Qn, (3.25)where FWHM is the full width of the peak at half its maximum height and Qn isthe equivalent rms noise charge.Since multichannel analyzers are highly specialized instruments, they may notbe available for use at every research laboratory. Another method exists to calculatethe ENC of the readout system and it uses a spectrum anlayzer [146] or a voltmeterand an oscilloscope. The signal pulse height can be easily measured using anoscilloscope. The noise level can be determined from a spectrum analyzer or avoltmeter. The measured values can then be substituted into (3.24) to calculate theequivalent noise charge of the system.If a voltmeter is used to measure the noise, it must have enough bandwidthand adequate sensitivity. Most of the voltmeters in the market measure the peakamplitude of the signal and display it in rms. This conversion is valid for onlysinusoidal signals. A voltmeter that measures true rms of the signal must be usedfor the purpose of measuring the noise of the system. Such a voltmeter uses athermal sensor or alternatively squares the signal and calculates the square root.The bandwidth of the voltmeter must also be sufficiently higher than that of thereadout system.If a spectrum analyzer is used to measure the noise of the system, it must also be55able to measure the true rms value of the signal. The spectrum analyzer measuresthe magnitude of the signal versus frequency. It is important to choose a propervalue for the resolution bandwidth of the instrument as the measured noise levelstrongly depends on it. It is possible to find instruments in the market that measurespectrum of the signal in terms of V/√Hz. The total noise of the system is thencalculated using [87]Vno =√N∑k=0[v2no(k).4 f ], (3.26)where N is the number of frequency bins, and 4 f is the size of the frequencybin. The measurement can be repeated with the chip turned off, to get the back-ground noise generated by the measurement system. The background noise is thensubtracted in quadrature to get the noise of the readout system [147].56Chapter 4Analysis and Design of a NovelLow-Power Charge-SensitiveAmplifier4.1 IntroductionSolid-state radiation detectors produce a small amount of charge that needs to beamplified by charge-sensitive amplifiers (CSAs). An important feature of CSAs isthe robustness of their charge gain to detector capacitance variations [22]. Noiseperformance, gain (and linearity), and power consumption are the key parametersthat pose several trade-offs in the design of CSAs. In order to improve the reso-lution of detection, the noise of the system needs to be reduced. The noise of thereadout circuit is mostly due to the noise of the CSA and thus designing a low-noise CSA is of paramount importance [148]. The noise performance of the CSAcan be enhanced at the expense of increasing its power consumption which is incontrast with the low-power requirement of modern readout circuits. Besides, in-creasing the power consumption of the circuit generates extra heat which in turnmay deteriorate the performance of the detector and ultimately limit the resolu-tion of detection. Furthermore, charge amplifiers are usually implemented usingsingle-ended configurations to save power. Thus their gain is usually low, and is57improved at the expense of increasing the power consumption which is undesirable.Also, they do not usually process signals of both polarities. We address these is-sues by introducing an improved CSA. The proposed CSA is then used in a readoutcircuit. Measurement results of the front-end circuit confirm the operation of thecircuit. In the following section, we present the design of the proposed low-powercontinuous-reset CMOS CSA.4.2 The Proposed Charge-Sensitive AmplifierThe discussion on the gain of the CSA in Chapter 1 is based on the assumptionthat the gain of the inverting amplifier is sufficiently large. The large gain of theamplifier significantly increases the value of the reflected capacitance at the inputterminal of the amplifier (due to the Miller effect on the feedback capacitor). Thisin part facilitate the desired property that the charge gain of the CSA would be-come robust to the detector capacitance variations. The increase in the gain of theamplifier is often achieved by both employing a folded-cascode architecture in thedesign of the CSA and by increasing the transconductance of the input transistorof the CSA. The latter results in an increase in the overall power consumption ofthe CSA.The proposed low-power continuous-reset CMOS CSA is shown in Figure 4.1.A regulated folded-cascode stage and a source follower buffer are used in the de-sign of the CSA. A gain-boosting technique [144] is employed in both upper andlower branches of the cascode stage in order to enhance the overall gain of theamplifier with negligible overhead power consumption. In the schematic shown inFigure 4.1, device MN4 (MP4) helps to increase the output impedance of the lower(upper) cascode branch by regulating the voltage across the device MN3 (MP3).The cascode current source consisting of MP5 and MP6 (MN5 and MN6) providesa 0.5 µA bias current to transistor MN4 (MP4). A 97 fF compensation capacitor(Cc) is placed between the source terminal of MP7 and the drain terminals of MN2and MP2 for stability purposes.The input device of the CSA is chosen to be a PMOS device since it generatesa lower flicker noise as compared to an n-type MOS device [149]. It is biased inthe middle of the moderate inversion region with an inversion coefficient approxi-58VinVoutVddmCfCcVb1Vb2Vb3Vb4VbnVbpVpMP1MN3MN2MN4MN1MP2MP3MP6MP5MN5MN6MP4MP7MP810 µA0.5 µA0.5 µA2.5 µA15 µAVddVb5Figure 4.1: The proposed low-power continuous-reset CMOS charge-sensitive amplifier.mately equal to 1 [82]. This is to achieve a satisfactory trade-off between linearity,dynamic range, and speed while keeping the power consumption at a reasonablylow level. The gate length of the input transistor is chosen to be 0.25 µm whichis ∼ 2× larger than the minimum feature size in the process used. As the inputdevice is biased at relatively high current levels, to further decrease the power con-sumption of the amplifier, the source terminal of the input device is connected toVddm, a supply voltage lower than Vdd.The value of the feedback capacitor of the CSA is chosen to be 100 fF whichresults in a theoretical gain of 10 mV/fC. An integrated high-value DC feedbackresistor discharges the capacitor continuously. The resistor is implemented by ann-type MOS device (MN1) biased in weak inversion region and provides a DC59Qdet-ACfPulse shaperReset networkCpRpCSA+reset network PZCRsKCzRzKCzRzRsVoutRfFigure 4.2: Block diagram of the readout circuit employing the proposedCSA, a PZC, and a 2nd-order Semi-Gaussian programmable pulseshaper.path for the leakage current of the detector. Other reset mechanisms may be useddepending on the desired linearity and the amount of leakage current that needs tobe compensated. Please refer to Section 2.4.2 for the pros and cons of the mostfrequently used reset networks.In order to validate the operation of the proposed CSA, it is employed in afront-end circuit that is optimized for the readout of CZT detectors. The circuitconsists of the proposed CSA, a pole-zero cancellation circuit, and a second-ordersemi-Gaussian programmable pulse shaper. Its block diagram is shown in Fig-ure 4.2. The required bias voltages/currents are generated on chip using an exter-nal reference current. Analytical noise analysis of the readout circuit is given inthe following section.4.3 Noise Analysis of the Readout CircuitIt can be shown that if Rz×Cz = Rs×Cp and Rs  Rp are met, then the transferfunction of the cascade of the pulse shaper and the PZC circuit can be written asH(s) =Vout(s)Vout,CSA(s)=RzRpRzRs1+RpCps(1+ stp)3 , (4.1)60where, tp = RzCz. If R fC f = RpCp, then pole-cancellation occurs and the outputvoltage due to one electron charge (q) can be written asVout (t) =q2C f(CpCz)2( ttp)2e−ttp . (4.2)The peak amplitude of the signal occurs at t = 2tp and equals toVo,max = |Vout (t = 2tp)|= 2qC f(CpCz)2e−2. (4.3)Note that the peak amplitude due to one electron charge depends only on the valueand/or ratio of capacitors which are well-controlled values. Following the pro-cedure described in Chapter 3, the noise equations of the readout circuit can bederived analytically. The ENC contribution due to the series white noise equals toENC2w,ser = Γ4kBTgmC2tot16piq2e−4tp∣∣∣∣B(32 , 32)∣∣∣∣ , (4.4)where Γ is the coefficient of the channel thermal noise, Ctot is the total capacitancethat shunts the amplifier input, T is the absolute temperature, kB is the Boltzmann’sconstant, gm is the transconductance of the input devices of the CSA, and B is theBeta function [71]. The ENC contribution due to series frequency-dependent noisecan be written asENC2f ,ser =K f sWLCoxC2tot8q2e−4(2pitp)1−α f s×∣∣∣∣B(3−α f s2 , 3+α f s2)∣∣∣∣ , (4.5)where, K f s is an intrinsic process parameter, Cox is the gate oxide capacitance perunit area, and α f s is the fitting exponent of f for the flicker noise equation, and Wand L are the width and length of the input device of the CSA, respectively. TheENC contribution due to the parallel white noise equals toENC2w,par = 2qI0tp16piq2e−4∣∣∣∣B(12 , 52)∣∣∣∣ , (4.6)61Figure 4.3: Chip micrograph. The chip is packaged in a standard 44-pinCQFP.where, I0 is the sum of the input devices gate currents, the detector leakage currentand its associated bias network. The total ENC of the readout circuit is the sum ofthe individual ENC contributions.4.4 Experimental ResultsThe readout circuit is fabricated in a 0.13-µm CMOS process. Fig. 4.3 showsa micrograph of the chip that is packaged in a standard 44-pin ceramic quad flatpackage (CQFP). The main building blocks of the readout channel are marked onthe figure. To evaluate the functionality of the readout circuit, a 0.5 pF test capaci-tance is also integrated on chip. A controlled amount of charge can be injected intothe circuit by applying an external step signal to the test capacitor. The capacitanceof the detector is modelled by integrating a 0.5 pF capacitance in parallel with theinput terminal of the CSA. Figure 4.4 shows the signals at the output terminals ofthe CSA and pulse shaper for an injected charge of about ±2.5 fC. According tothis figure, the CSA and the pulse shaper can accept signals of both polarities. Thelong discharge time constant of the CSA allows for shaping times in the order ofµs. The measured shaping time is about 1µs.Figure 4.5 shows the voltage peak amplitude at the output of the CSA (uppercurve) and the pulse shaper (lower curve) versus injected charge. Based on this fig-620 50 100 150 2000.480.50.520.540.560.580.60.62CSA's and shaper's output voltages [V]Time [µ  s]Figure 4.4: Measured waveforms at the output of the CSA (upper) and thepulse shaper (lower) for an injected charge of about ±2.5 fC.ure, the conversion gains of the CSA and the shaper are about 8.8 and 13.9 mV/fC,respectively. The measured gain for the CSA is in good agreement with the theo-retical value when the effects of the parasitic capacitances as well as the detectorcapacitance are taken into account. The charge integration at the output of the CSAis linear from about −9 to 6 fC. The gain linearity can be improved by biasing theinput device of the CSA more into the strong inversion region.The noise performance of the readout circuit is also evaluated. The noise mea-surement is done in a shielded chamber. Agilent PXA N9030A with a frequencyrange of 3 Hz to 26.5 GHz is used to measure the output voltage noise density. Theinput impedance of the instrument is derived by HP 1144 Active Probe. Figure 4.6shows the measured total output voltage noise density of the integrated readout cir-cuit. The measurement includes the noise of the active probe, power supplies andthe instrument. To calculate the noise of the readout circuit, the noise of the mea-surement system must be excluded. Figure 4.7 shows the measured voltage noisedensity of the probe, power supplies, and the instrument. The equivalent noise63-10 -5 0 5 10-150-100-50050100150Injected charge [fC]Output peak amplitudes [mV]  CSAShaperFigure 4.5: Measured voltage peak amplitudes at the outputs of the CSA andthe shaper versus injected charge.charge of the readout circuit can be calculated by subtracting the noise of the mea-surement system in quadrature [147]. The measured ENC of the readout circuit isabout 111 e¯-rms. The CSA consumes 37.5 µW of power from power supplies ofV dd = 1.2V and V ddm= 0.9V and occupies 0.0021 mm2 of silicon area. Table 4.1compares the performance of the designed readout circuit with similar work in theliterature.4.5 Summary and ConclusionsIn this chapter, the design of a novel low-power continuous-reset CMOS charge-sensitive amplifier is presented. The proposed CSA is intended for capacitive sen-sor readout circuits, in particular, interface circuits for solid-state detectors usedin medical imaging and X-ray spectroscopy. A proof-of-concept interface circuitis designed and fabricated in a 0.13-µm CMOS process and consists of the pro-posed CSA, a pole-zero cancellation circuit, and a second-order semi-Gaussian64Figure 4.6: Measured total output voltage noise density of the integratedreadout circuit. The measurement includes the noise of the active probeand the instrument.programmable pulse shaper. Measurement results show that the conversion gainsof the CSA and the pulse shaper are about 8.8 and 13.9 mV/fC, respectively. TheCSA can accept signals of both polarities and the charge integration is linear fromabout−9 to 6 fC. The measured equivalent noise charge of the CSA is about 111 e¯-rms. The CSA occupies 0.0021 mm2 of silicon area and consumes 37.5 µW fromdual supply voltages of 0.9 and 1.2 V.65Figure 4.7: Measured voltage noise density of the active probe and the instru-ment.66Chapter 5Design and Analysis of a4-Channel Readout System forSolid-State Radiation DetectorsIn this chapter the design and analysis of a low-power and low-noise 4-channelreadout circuit intended for solid-state radiation detectors (in particular, CZT de-tectors) is presented. The design is optimized in terms of noise performance andpower consumption. A comprehensive noise analysis of the readout system is pre-sented. The analysis is based on the EKV model [82] of MOS transistors which isvalid for all regions of operation. The readout circuit is laid out and fabricated in astandard 0.13-µm CMOS technology. Measurement results of the circuit are alsopresented.5.1 Readout Circuit DesignThe simplified block diagram of the implemented front-end circuit is shown in Fig-ure 5.1. The circuit consists of a charge-sensitive amplifier (CSA), a reset networkto provide a discharge path for the feedback capacitor, and a first-order pulse shaperwith a pole-zero cancellation (PZC) circuit. All the bias voltages and currents inthis figure are generated on chip using a single external reference bias current. Thereset network also accommodates the leakage current of the detector and is a modi-68-ACf1CpRpRsKCzRzReset networkCTestVTestIn VoutCf2Vout_CSAIpIbPreVddVresPreVoffsetVresPZVCMIbSHVdd2-to-4 Decodertp_SEL1tp_SEL0Gain-sel100 ns shaping time200 ns shaping time500 ns shaping time1000 ns shaping time0123M1M2VddmFigure 5.1: Simplified block diagram of one front-end channel. Capacitorbanks are used to implement Cp and Cz. A 2-to-4 decoder is used toselect the peaking time of the pulse shaper. Buffers/output drivers arenot shown for simplicity.fied version of Krummenacher’s low-frequency feedback loop [12]. Output drivers(buffers) are not shown for simplicity. The design of buffers and amplifiers is dis-cussed extensively in the literature [152–155] and thus we will not focus on suchdesigns in this work. Capacitor banks are used in the design to allow adjusting theshaping time of the filter. The pulse shaper is designed to provide 100, 200, 500 and1000 ns shaping times. The shaping time for each channel can be independentlyselected by using a 2-to-4 on-chip decoder. The circuit is capable of handling 0to 5 fC and 5 to 45 fC injected charge. The corresponding conversion gain of theCSAs can be selected using the Gain-sel signal. A test capacitor is integrated onchip to enable precise charge injection for test purposes.In Figure 5.1, transistor M1 is used to change the effective DC feedback resis-69tance and accordingly the discharge time constant of the CSA. Improper pole can-cellation may occur at the output of the pulse shaper as a result of adjustment of thevalue of the feedback resistance of the CSA or any mismatches or non-idealitiesin the fabricated resistors and capacitors. Therefore, either an under- or an over-compensated signal may occur at the output of the pulse shaper. The former willhave an undershoot which is not completely eliminated and the latter will cause theoutput to decay to the baseline with the preamplifier time constant. To overcomethese problems, we have introduced transistor M2 in the PZC circuit which enablescancellation of the pole due to preamplifier’s pulse decay time. The adjustmentcan be made by varying the bias voltage of M2 such that the pulses at the output ofthe pulse shaper return to baseline in the minimum time with no undershoot. Thedetailed design of the main building blocks and a comprehensive noise analysis ofthe readout system will be presented in the following subsections.5.1.1 Design of the Charge-Sensitive AmplifierCharge-sensitive amplifiers are widely used in the design of readout circuits forvarious capacitive sensors, in particular, for solid-state radiation detectors. Insen-sitivity of their gain to the detector capacitance variations is the main motivation ofusing CSAs in the front-end circuit of such systems [22]. To maximize the achiev-able resolution, the noise of the readout circuit must be minimized. The noise ofthe overall system is typically dominated by the noise of the CSA. Furthermore, tominimize the length of the interconnect between the detector pixels and their cor-responding CSA, which in turn minimizes the coupling and crosstalk noise, eachCSA is typically placed as close as possible to its corresponding detector pixel.Due to this proximity low-power consumption of the CSA also becomes impor-tant as the excessive heat generated by the CSA would increase the noise of thesystem and also may deteriorate the performance of the detector. This is particu-larly important in high resolution systems with a large number of readout channels.Therefore, designing a low-noise low-power CSA is of paramount importance insuch systems.The circuit schematic of the proposed CSA is shown in Figure 5.2. A single-ended configuration is used in the design of the CSA to save power. In the CSA70InVout 40 µAVddmVBCfM1 M2M8M6M4M5M3M7M10M9M11M12VddVddFigure 5.2: Circuit schematic of the CMOS charge-sensitive amplifier.Proper bias voltages and currents are supplied from an integrated biascircuitry.design it is desired to increase the transconductance of the input device in order toimprove both the speed and noise performance. This is achieved by using a folded-cascode topology. P-type MOS devices, i.e., M1 and M2, are chosen as the inputdevices of the CSA since they exhibit a lower flicker noise contribution as com-pared to n-type MOS devices [149]. Furthermore, the source terminals of the inputdevices are connect to V ddm, a supply voltage that can be made much lower thanV dd. This lower supply voltage will in turn results in a reduced power consump-tion of the CSA as the input devices are biased at high current level to increase71the speed and reduce the white noise. To reduce the flicker noise contribution andto improve the matching among different readout channels, the gate length of theinput devices is chosen to be slightly larger than the minimum feature size. Thefeedback capacitor of the CSA is discharged through the reset network. The resetnetwork also provides a DC path for the leakage current of the detector. The devicedimensions of the CSA are given in Table 5.1.Table 5.1: Device sizes of the CSAM1: 100/0.2 M2: 100/0.2 M3: 200/1 M4: 200/1M5: 100/1 M6: 100/1 M7: 200/0.5 M8: 200/1M9: 30/2.5 M10: 10/2.5 M11: 5/2.5 M12: 10/2.5All the dimensions are in µm.5.1.2 Design of the Pulse Shaper with a PZC CircuitIn detector readout circuits, the output of the CSA is often passed through a filterbefore further signal processing, for example, for amplitude or peak-time measure-ments. Such filtering is referred to as pulse shaping as it affects the amplitude ortiming of the resulting pulse signal. The most common pulse shaping method is toproduce a pulse whose peak amplitude is proportional to the detected charge in thedetector.Since these filters are typically active structures, in this design, we use a first-order pulse shaper in order to minimize the power overhead of the active filter.The pulse shaper is designed to provide four different peaking times. The desiredpeaking time can be selected with a 2-to-4 decoder integrated on chip.The decay of the charge amplifier pulses usually causes an undershoot in thepulse shaper output signal [22]. If another event occurs while the output signalis recovering, it will be superimposed on the undershoot and a pulse pile-up errorwill occur. For the large signals that overload the amplifier, the undershoot tail canlast for a long time. To overcome these problems, a PZC circuit is placed betweenthe CSA and the pulse shaper (See Figure 5.1). The PZC circuit must be carefullydesigned to properly cancel the pole associated with the decay of the CSA signal.Referring to Figure 5.1, it can be shown that if Rs Rp and Rz×Cz = Rs×Cp,72Table 5.2: Device sizes of the main amplifier of the pulse shaperM1: 14/0.52 M2: 14/0.52 M3: 28/0.35 M4: 28/0.35M5: 20/5 M6: 40/5 M7: 80/5 M8: 110/0.35All the dimensions are in µm.then the transfer function of the cascade of the pulse shaper and the PZC circuitcan be written asH(s) =Vout(s)Vout,CSA(s)=−RzRp1+RpCps(1+ stp)2 , (5.1)where, tp is the peaking time, defined astp = RzCz = RsCp. (5.2)In time domain, the pulse shaper output signal due to one electron charge deliveredby the detector can be derived as [71]Vout(t) = L−1{(+q)R f1+ sR fC f−RzRp1+RpCps(1+ stp)2}, (5.3)where, q denotes the charge of one electron (i.e., q = 1.6× 10−19 C), R f is theeffective feedback resistance of the CSA, and C f is the total feedback capacitance.Pole cancellation occurs when R fC f = RpCp and thus the output voltage can bewritten asVout (t) =−qC fCpCzttpe−ttp . (5.4)The peak amplitude of the signal occurs at t = tp and equals toVo,max = |Vout (t = tp)|= qC fCpCze−1. (5.5)A two-stage amplifier is used to realize the gain block of the pulse shaper. Theschematic of the amplifier is shown in Figure 5.3 and the device sizes are listed inTable 5.2. The amplifier draws ∼ 60 µA from a 1.2 V supply, and provides a gainof 56.6 dB with a phase margin of 46◦ and a unity gain frequency of 46.6 MHz.73VipVinVo10 µARc CcM1 M2M3M4M5M6M8M7VddVddFigure 5.3: Circuit realization of the gain block of the pulse shaper.5.1.3 Design of the Reset NetworkAs explained in Chapter 2, the generated charge from the detector is integrated onthe feedback capacitor. After integration, the capacitor must be discharged in orderto reset the system and prepare it for the next event. The role of a reset network isto provide a path for discharging the capacitor. The reset network must be carefullydesigned as it directly contributes to the noise of the system. The discharge time ofthe CSA must be significantly larger than the shaping time and also short enoughto prevent pulse pile-ups at high event rates. Implementing a large discharge timehas the challenge of integrating a high value feedback resistor in the reset network.In this design, we need a circuit that can accommodate leakage current of CZTdetectors which is in the range of 1 fA to 50 nA. The Krummenacher low-frequencyfeedback loop [12] appears to be a good choice for compensation of the leakagecurrent of the CZT detectors based on the analysis of common reset mechanismsdescribed previously in Chapter 2. The reset network that we have implementedis a modified version of the Krummenacher low-frequency feedback loop and isillustrated in Figure 5.4. In the original configuration the DC feedback resistance isfixed and is realized by the transconductance of the differential pair in the feedbacknetwork (i.e., R f = 1/gm3a). Once the bias current of the differential pair is set, the74Vref2Ip-AIpCCfVoutIpVresPreM3aM3bM2IleakM1VddFigure 5.4: The designed reset network which is a modified version of theKrummenacher low-frequency feedback loop. Drain current of tran-sistor M2 is adjusted to compensate the leakage current of the detec-tor. Transistor M1 is introduced to adjust the decay time constant of theCSA.75discharge time constant of the CSA will be fixed. In some applications, it might benecessary to adjust the decay time constant of the CSA in order to deal with variousevent rates. We have modified the circuit by introducing a MOS device that can beused to change the effective DC feedback resistance and accordingly the dischargetime constant of the CSA. The bias current of the reset network is set to 250 pA tolower the noise contributions of the MOS devices in the network.5.1.4 Noise Analysis and OptimizationAs explained previously in Section 3.2, the noise of a detector readout system isusually expressed in terms of the ENC. The noise of the readout circuit is mod-elled by series and parallel noise sources referred to the input of the circuit [156].The series and parallel noise power spectral densities are uncorrelated. Followingthe procedure described in Section 3.2, the input-referred series and parallel noisesources are derived analytically and are given by the following equations.ENC2w,ser = αwnsubγ4kBTgmC2tot4piq2e−2tp×∣∣∣∣B(32 , 12)∣∣∣∣ , (5.6)ENC2f ,ser =K f sWLCox2pi2t2pC2totq2e−2(2pitp)3−α f s×∣∣∣∣B(3−α f s2 , 1+α f s2)∣∣∣∣ , (5.7)ENC2w,par = 2qI0tp4piq2e−2×∣∣∣∣B(12 , 32)∣∣∣∣ , (5.8)ENC2f ,par = A f ptp22q2e−2(2pitp)1−α f p×∣∣∣∣B(1−α f p2 , 3+α f p2)∣∣∣∣ . (5.9)In these equations, B represents the Beta function. The total ENC of the readoutcircuit is the sum of the individual ENC contributions and is given byENC2tot = ENC2w,ser +ENC2f ,ser +ENC2w,par +ENC2f ,par. (5.10)In the 0.13-µm CMOS process used in this analysis, the frequency-dependentparallel current noise sources of the readout circuit can be neglected without sig-7610-810-710-610-5Peaking time [s]  101102103Optimum width (µm)PMOS 0.13 µm process  L=0.13 µmL=0.2 µm L=0.35 µm101102103Optimum ENC [ē -rms]Cdet = 500 fFId = 120 µACf = 100 fFFigure 5.5: Theoretical optimum ENC of the front-end circuit and the corre-sponding optimum channel width as a function of peaking time for aPMOS input device for the 0.13-µm CMOS process used in this work.Since the input device size does not affect the detector leakage current,the noise associated with this leakage current is not taken into accountin this optimization.nificantly affecting the overall noise performance of the system [79]. Note that ina properly designed circuit, for the purpose of optimization of the input device sizeof the CSA, the detector leakage current and the noise sources in the reset networkcan be ignored since these noises are typically independent of the input device size.Obviously, the noise contributions from the detector and the reset network must beincluded in the noise calculations of the system. To optimize the noise perfor-mance of the readout system, one has to minimize (5.10) with respect to the designparameters of the CSA and those of the pulse shaper simultaneously. Figure 5.5shows the theoretical optimum ENC of the front-end circuit and the correspondingoptimum channel width as a function of the peaking time for a p-type MOS inputdevice in the 0.13-µm CMOS process used in this work. It is assumed that thedetector has a capacitance of 0.5 pF and the overall drain current of the CSA input771.5 mm1.5 mmCSA & Reset networkPad driver Pad driverBias circuitryPulse shaperFigure 5.6: Chip micrograph. The chip includes four identical readout chan-nels and is packaged in a standard 44-pin CQFP.devices is 120 µA. The optimization has been performed for three different chan-nel lengths. Based on Figure 5.5, the optimum width increases with increasing thepeaking time, whereas the optimum ENC decreases as the peaking time increases.For larger peaking times, the increase in the optimal width is more pronounced.This can be explained by taking a closer look at the individual ENC contributions.At large peaking times, the series flicker noise is the main contributor to the totalENC whereas at small peaking times the series white noise dominates the overallnoise. Since the flicker noise is inversely proportional to W ×L of the input device,for large peaking times, the optimal ENC is achieved by increasing the device size.At small peaking times, however, the optimum width does not vary significantlywith respect to the peaking time, since the series white noise of the input device isa weak function of the device dimensions.78Figure 5.7: Custom-designed FR4 printed circuit board (PCB).5.2 Experimental ResultsThe designed ASIC is implemented in a standard 0.13-µm CMOS technology.Figure 5.6 shows a micrograph of the chip that is packaged in a standard 44-pin ce-ramic quad flat package (CQFP). The main building blocks of the chip are markedon the figure. To evaluate the performance of the chip, we have designed a customFR4 printed circuit board (PCB) where the chip is mounted on. Figure 5.7 showsthe picture of the fabricated PCB. The ASIC contains four identical readout chan-nels with a total die area of 1.5×1.5 mm2. The power consumption of each readoutchannel is about 1 mW when connected to a 1.2 V supply. The specifications ofthe 4-channel device are summarized in Table 5.3.5.2.1 Transient Response of the Readout SystemFigure 5.8 shows the measured waveforms at the output of the pulse shaper forthree values of VresPZ. The injected charge is about 10 fC which is injected tothe input terminal of the CSA by applying an external pulse to an integrated test79Table 5.3: Specifications of the ASICSpecification ValueFabrication process Standard 0.13-µm CMOSDie size 1.5×1.5 mm2Package CQFP-44Number of channels 4Power supply 1.2 VPower consumption 1 mW/channelRate Max. 100 kcycles/sSensor< 5 pF capacitance< 50 nA dark currentcapacitance of 250 fF. As shown in this figure, the output overshoot voltage iscancelled by adjusting the gate voltage of the MOS device in the PZC network.After adjustment, the output signal quickly returns to the baseline which verifiesthat the PZC circuit functions as expected.Figure 5.9 shows the measured voltage at the output of the pulse shaper forhigh and low charge ranges. The voltage gain is estimated to be 8.5 and 50 mV/fCfor high and low ranges, respectively. The integration is linear up to 5 and 45 fCfor the low and high ranges, respectively.The desired peaking time for each channel can be selected using two digitalinputs (t p SEL1 and t p SEL0 as shown in Figure 5.1). Figure 5.10 shows the mea-sured waveforms at the output of the pulse shaper for various peaking times. Fromthis figure, the measured peaking times are 108 ns, 220 ns, 560 ns, and 1.14 µs.The VresPZ voltage is kept constant during the measurement. It is possible to bringthe peaking times closer to their theoretical value by adjusting this voltage.The discharge time constant of the CSA can be adjusted by varying the biasvoltage of transistor M1 (i.e., V resPre) in Figure 5.1. The captured waveforms atthe output of the CSA for different values of V resPre are shown in Figure 5.11.According to this figure, the discharge time can be adjusted from about 1 to 7 µs.A short discharge time is desired in applications where a high event rate is required,whereas, a long decay time is useful in applications where a long shaping time anda low noise performance are required.800 5 10 15 20 250.90.9511.05time [s]Shaper's output voltage [V]  VresPZ=840 mVVresPZ=889 mVVresPZ=911 mVFigure 5.8: Captured waveforms at the output of the pulse shaper for an in-jected charge of about 10 fC. The overshoot voltage is cancelled byadjusting the gate bias voltage (i.e., V resPZ) of the MOS device in thePZC network.5.2.2 Noise Evaluation of the Readout SystemIn Section 3.3 we described how to measure the noise of the readout system. Fig-ure 5.12 shows the block diagram of the designed noise measurement setup. Thesetup consists of a PCB test board, an active probe, and three types of instruments.The instruments include two power supplies, a function generator, and a spectrumanalyzer. Separate power supplies are used for the chip and the components onthe PCB. Low dropout (LDO) linear voltage regulators are placed on the board toprovide clean voltage to the chip and other components. They also compensatefor voltage drops on the supply cables. The digital inputs are provided to the chipusing toggle switches. Voltage dividers are placed all over the board to provide815 10 15 20 25 30 35 40 45 5000.10.20.30.40.5Vout, High range [V]1 2 3 4 5 600.10.20.30.4Vout, Low range [V]Q [fC]Figure 5.9: Measured voltage at the output of the pulse shaper for high andlow ranges. The integration is linear up to 5 and 45 fC for the low andhigh ranges, respectively.analog bias voltages to the chip. Please note that only one switch and one voltagedivider is shown on the figure for simplicity. A function generator will producepulses which will inject a precise amount of charge into the circuit at desired inter-vals. The spectrum analyzer will be used to measure the signal to noise ratio at theoutput of the pulse shaper.The designed text fixture operates with a 5 V supply voltage. One XantrexLXQ-30-2 power supply is used to power up the device under test (DUT). Theoutput voltage of this instrument ranges from 0 to 30 V and the maximum availablebias current is 2 A which is much higher than the minimum required current tooperate the DUT. The accuracy and precision of the power supply is of no concern820 5 10 150.70.750.80.850.90.9511.051.1time [µs]Pulse shaper's output [V]  peaking time: 1.14 µspeaking time: 560 nspeaking time: 220 nspeaking time: 108 nsFigure 5.10: Measured waveforms at the output of the pulse shaper for vari-ous peaking times. VresPZ voltage is not altered during the measure-ment.because the power supply will be set to provide an input voltage of 5 V which ismuch higher than the minimum required voltage for operating the regulators. TheDUT is designed conservatively and therefore can tolerate even a 2 V change inthe supplied voltage.We have used Agilent 33250A for generating pulses with desired amplitudeand frequency. This instrument is an arbitrary function generator and is capable ofproducing up to 50 MHz pulse waveforms with variable rise/fall times. The outputamplitude of this instrument can be set with a resolution of 0.1 mV and an accuracyof (±1% of setting ±1 mVpp) which is acceptable for our measurements.The instrument that we choose to measure the signal-to-noise ratio at the outputof the circuit must satisfy two important requirements. The first requirement is that830 5 10 15 20 250.550.60.650.70.750.80.85time [s]CSA's output voltage [V]  VresPre=  0 mVVresPre=734 mVVresPre=793 mVVresPre=837 mVFigure 5.11: Measured waveforms at the output of the CSA for various valuesof the V resPre control voltage. The discharge time of the CSA can beadjusted from about 1 to 7 µs.the minimum dynamic range of the instrument must be higher than that of thesystem. Lets assume that we need to measure an ENC of as low as 10 e¯-rms. Thisresults in a calculated signal-to-noise ratio of about 56 dB when 1 fC charge isinjected into the circuit. Most of current spectrum analyzers have a dynamic rangeof 100 dB or more and can satisfy the minimum dynamic range requirement. Thesecond requirement is that the instrument must be able to measure the noise of thesystem at very low frequencies. This is essential in order to determine noise of thesystem accurately as most of noise power falls within low frequencies.Amongst available signal analyzers, Agilent N9030A is the only instrumentthat can cover very low frequencies. The frequency range of this instrument is3 Hz to 26.5 GHz. The only problem with this instrument is that the input DC level84ChipPCBAgilent 33250AVTest VoutLDOLDOVddXantrex LXQ-30-2 Digital inputs Analog bias voltagesPot.R1Pot.R1IrefLDO Vdd for the componentsof the PCBVddCSAAgilent N9030AC1C1C1 C2C2C2HP 1144 Active Probe Xantrex LXQ-30-2 +15-15Probe tipFigure 5.12: Noise measurement setup diagram. Several switches and volt-age dividers are used to supply the digital inputs and the bias voltagesto the chip, respectively. Note that only one switch and one voltagedivider is shown for simplicity.must be within ±0.2 V when DC coupled. The output signal from the DUT has aDC level of around 0.8 V. Besides, the integrated chip buffers are not designed toderive the 50 Ω input impedance of the instrument. To overcome these problems,we use the HP 1144 Active Probe. The probe has a bandwidth of 800 MHz whichis much higher than the bandwidth of our system. The integrated chip buffers caneasily derive the input impedance of the active probe which is 2 pF in parallel with1 MΩ. The probe has a rise time of 440 ps or less which is sufficient for ourmeasurements.Figure 5.13 shows the measured voltage noise density at the output of the pulseshaper for a peaking time of 1140 ns. The measurement is done in a shielded cham-ber. Figure 5.14 shows the measured ENC of the readout circuit for the availablepeaking times. The calculated ENC of the readout system varies between 66 to101 e¯-rms for a peaking time in the range of 108 to 1140 ns. This is in agreement8510210410610800.511.522.5Frequency [Hz]Output voltage noise density [ V/ Hz]Figure 5.13: Measured voltage noise density at the output of the pulse shaperfor a peaking time of 1140 ns.with the theoretical results where the ENC of the system decreases with an increasein peaking time. Table 5.4 summarized the performance of the proposed readoutcircuit and compares it with relevant designs.5.3 Summary and ConclusionsIn this chapter, the detailed design and analysis of a low-power low-noise four-channel readout circuit for solid-state radiation detectors, in particular CZT, is pre-sented. Each readout channel includes a charge-sensitive amplifier, a reset networkto accommodate the leakage current of the detectors, and a first-order pulse shaperwith a pole-zero cancellation circuit. The CSAs have two gain settings for 0 to860 0.2 0.4 0.6 0.8 1 1.26065707580859095100105Measured ENC [e−rms]Peaking time [µ s]Figure 5.14: Measured equivalent noise charge of the system versus differentpeaking times for a 250 fF detector capacitance.5 fC and 5 to 45 fC injected charge. The pulse shaper is programmable and isdesigned to provide four different shaping times. The discharge time constant ofeach CSA can also be adjusted to accommodate various event rates. Furthermore,a comprehensive noise analysis of the readout system is presented. To facilitatenoise analysis, the equivalent noise charge equations are derived analytically. Op-timization of the noise performance of the front-end circuit is also discussed. Theapplication-specific integrated circuit (ASIC) is fabricated in a 0.13-µm CMOSprocess. For a detector capacitance of 250 fF, the measured ENC varies between66 to 101 e¯-rms at available peaking times. The power consumption of each chan-nel is measured to be only 1 mW.87Table 5.4: Readout circuit performance comparisonSpecification This work [44] [157] [158] [159] [160]Fabrication process 0.13-µmCMOS0.35-µmCMOS0.25-µmCMOS- 0.8-µmCMOS0.8-µmBiCMOSSignal processingchainCSA, leak-age com-pensation,shaper, PZCCSA, PZC,fast/slowshaper,comparator,Sample-and-HoldCSA,shaper,PZC, Base-line Holder,Peak-Detect& HoldCSA,shaper, dis-criminator,Sample-and-HoldCSA,shaper,two dis-criminators,countersReset CSA,shaper, PZCDetector capaci-tance [pF]0.25 0* 0* 1 3 0*Peaking time [µs] 0.1-1.14 8 2 10 0.8 1.2Power consump-tion per channel[mW]1 3 2 2.8 4 0.5ENC [e¯-rms] 66-101 89 ≈ 100 85** 200 220−500* without detector attached ** in the presence of a leakage current of 20 pA88Chapter 6Design and Analysis of aComplete Readout System forSolid-State Radiation Detectors6.1 IntroductionIn the previous chapter we presented the detailed design and analysis of a fourchannel device which consisted of a CSA with leakage compensation, pole-zerocancellation circuit, and a first-order pulse shaper. The focus of the design was ondesign of the CSA, and noise optimization. The focus of this chapter is on the de-sign and analysis of the pulse shaper and the signal processing blocks of a readoutsystem. The design of the signal processing blocks of the readout signal is chal-lenging as it requires design and simulation of mixed-signal circuits. As a proof ofconcept, we will design a complete readout system. The integrated readout systemconsists of a CSA with leakage compensation, a Gaussian pulse shaper, a peak-detect-hold (PDH), a discriminator, and an analog-to-digital converter (ADC). Thetest chip is laid out and fabricated in a 0.13-µm CMOS technology. Measurementresults of the readout circuit will be presented.The first-order pulse shaper in Chapter 5 consists of one gain stage and a num-ber of passive and active devices. Although the design of this pulse shaper is simple89and its power consumption is small, it is not a good choice for high resolution orhigh counting rate applications. In high resolution readout systems it is essentialto employ a pulse shaper which exhibits a superior noise performance. Gaussianpulse shapers are popular choices for such systems. In high counting rate appli-cations the return to baseline of the pulses must be fast. Gaussian pulse shapersare also good choices for high counting rate applications. The return to baselineof the Gaussian pulse shapers is shortened by increasing the number of integrators,however, the power consumption of the circuit will increase accordingly as thesefilters are often realized using active circuits.6.2 Readout Circuit DesignThe readout system is intended for the readout of capacitive detectors, particularly,CdZnTe detectors. The block diagram of the readout system is shown in Figure 6.1.The readout system consists of a charge-sensitive amplifier, a reset network, a PZCcircuit, a 5th-order Gaussian pulse shaper, a peak-detect-hold (PDH) circuit, a dis-criminator, a Wilkinson-based analog-to-digital converter, and a digital conversioncontroller circuit. The peaking time and the gain of the pulse shaper can be adjustedusing two 2-to-4 decoders. Most of the bias voltages and currents are generated onchip using an external bias current. The readout system operates as follows.The weak signal from the sensor is converted to voltage at the output terminalof the CSA. The reset network creates a discharge path for the feedback capacitorand also compensates for the leakage current of the detector. The discharge time-constant of the signal at the output of the CSA can be controlled by adjusting thegate voltage of M1. After integration over the feedback capacitance, the signalis passed to the pulse shaper. The pulse shaper is a 5th-order Gaussian filter andconsists of a differentiator followed by two active filters. The gain and peakingtime of the pulse shaper can be controlled using two 2-to-4 decoders. After pulseshaping the signal is passed to the PDH (also called a pulse stretcher) and thenthe ADC for digitization. A conversion control state machine is designed thatcontrols the digitization process. For systems with a large number of channels, it isimpractical to allocate a dedicated ADC per channel due to the high cost in termsof area and power. Thus, it is essential for such systems to multiplex the outputs of90-ACfReset networkCTestVTestInVout_CSAVresPre2-to-4 Decodertp_SEL1tp_SEL0tp0tp1tp2tp30123M12-to-4 DecoderGain_SEL1Gain_SEL00123G0G1G2G3Vres_PZCM21DifferentiatorActive filter 1Active filter 2Vout_SHPulse shaper(a)Vout_SH1Peak Detect & HoldWilkinson based ADCVth_DiscrConversion ControllerPDH_WPDH_RPDH_ResetDiscr_ResetStartCLKCLRVref_ADC9ReadyOut [8:0](b)(c)Vout_CSAFigure 6.1: Simplified block diagram of the fabricated readout system. Theblock diagram shows (a) the charge-sensitive amplifier, the reset net-work, and two 2-4 decoders, (b) a 5th-order Gaussian pulse shaper, and(c) the peak-detect and hold, the discriminator, the Wilkinson-basedanalog-to-digital converter, and the digital conversion controller.91several channels and use a fewer number of ADCs. To identify the events that needto be digitized a discriminator is used which generates a trigger signal wheneverthe signal level at the output of the pulse shaper is higher than a threshold level.In the following subsections we will describe the design and analysis of the mainbuilding blocks of the readout system in detail.6.2.1 Charge-Sensitive Amplifier and Reset NetworkThe implemented CSA is a folded-cascode configuration with single-ended inputand output ports. The circuit topology of the CSA is the same as the one de-scribed in Section 5.1.1. The implemented reset network is a modified version ofthe Krummenacher’s low frequency feedback loop. The design of the reset networkwas described in detail in Section 5.1.3.6.2.2 Gaussian Pulser ShaperGaussian pulse shapers are popular choices for many readout circuits. The outputsignal returns to baseline quickly and a good signal-to-noise ratio is achieved. Theimplemented pulse shaper is a 5th-order Gaussian filter with adjustable gain andpeaking time. The pulse shaper consists of a differentiator followed by a buffer,and two active filters. The structure of the active filter is shown in Figure 6.2. Eachactive filter has a complex pole pair. The transfer function of the active filter isgiven by [161]H(s) =−R1R3R1R2C1C2s2+R1C1s+1(6.1)As can be seen from this equation, resistor R3 has no effect on the location of thepoles of the filter. This suggests that the gain of the filter can be varied by adjustingthe value of this resistor. We have used this feature in the design of the pulse shaper.One of the decoders allows adjusting the gain of the pulse shaper by selecting oneof the available R3 resistors.The circuit schematic of the implemented pulse shaper is shown in Figure 6.3.The design procedure for the pulse shaper is given in detail in Appendix A. Thetransistor shown in this figure is used for pole-zero cancellation. The transistor92R3-AC1R2Vout1C2R1VinFigure 6.2: Structure of a second-order active filter with complex poles.introduces a zero in the transfer function of the differentiator and modifies thelocation of the associated pole with the differentiator. The amplifiers in the designare two-stage CMOS opamps with frequency compensation. The circuit schematicof the amplifiers was shown previously in Figure 5.3.6.2.3 Peak-Detect and HoldThe output of the pulse shaper is connected to the input of a PDH before the digiti-zation stage. A PDH generates a signal that follows the input signal up to the peakof the signal and stays constant after the peak is detected.The principle operation of the designed PDH is based on a popular two-phasearchitecture described in [120]. The circuit schematic of the PDH is shown inFigure 6.4. The designed PDH is offset-free and uses a low-power operationaltransconductance amplifier (OTA), a current mirror, switches, and a hold capacitor.The switches in this figure are implemented using complementary MOS devices.The circuit schematic and the device sizes of the OTA block of the PDH are shownin Figure 6.5. A PMOS differential pair is chosen as the input stage of the OTAwhich allows processing of input signals with low common-mode voltages.The operation of the PDH is as follows. The switches S1, S2, and S5 are closedin the Write (W) phase. The input signal is applied to the negative terminal of theOTA and the OTA drives the current mirror. As the input voltage increases, theOTA sinks the current and the capacitor charges accordingly. When the voltage93tp0 200 fFtp1 624 fFtp2 1.32 pFtp3 2.79 pFVres_PZCM2VinVCMVdiff100 kΩG0G1G2G350.35 kΩ39.75 kΩ31.8 kΩ23.85 kΩVo1tp0 351 fFtp1 1.1 pFtp2 2.33 pFtp3 4.93 pFVCM100 kΩ 1tp01.45 pFtp1689 fFtp2325 fFtp3102 fFVCM100 kΩG0G1G2G347.7 kΩ37.1 kΩ31.8 kΩ23.85 kΩVdifftp0 225 fFtp1 707 fFtp2 1.49 pFtp3 3.16 pFVCM100 kΩ 1tp01.71 pFtp1811 fFtp2383 fFtp3122 fFVCM100 kΩVo1VoutFigure 6.3: Circuit schematic of the 5th-order active Gaussian pulse shaper.9410 pFVoutVddOTAVin --- S2WVhResetS6S1WS3RVCMS5WRS40.50.50.50.5M1 M2Figure 6.4: Circuit schematic of the implemented peak-detect and hold.across the capacitor reaches the peak voltage of the input signal, the current mirrorstops charging the capacitor and the peak voltage of the input signal is stored onthe capacitor. So in the Write phase the circuit tracks the input signal, and detectsand holds its peak voltage. The offset voltage of the OTA is also stored on the holdcapacitor (Ch). In the Read (R) phase, S1, S2, and S5 switches are opened and S3,and S4 switches are closed. The OTA is placed in a buffer configuration and itsoutput terminal is connected to the output port. In this phase the offset voltage ofthe OTA is subtracted from the hold voltage of the capacitor (that includes the offsetof the OTA from the Write phase) and the peak voltage of the signal is providedto the output. After the voltage is read out, S6 switch is closed which resets thecapacitor and the PDH becomes ready to accept another signal. The W, R, andReset signals are provided by the Conversion Controller block.6.2.4 DiscriminatorA discriminator is often used in readout systems to identify the channels with in-cidents [23, 162–164]. The discriminator compares the output signal of the pulseshaper with a threshold voltage and toggles whenever its input signal crosses thethreshold level. Thus the discriminator generates a pulse whenever the signal at the95VipVinVdd3000.41000.4Vout3000.42000.41000.41000.43000.4400.4400.43000.4Figure 6.5: Circuit schematic of the implemented operational transconduc-tance amplifier.output of the pulse shaper crosses the threshold and returns to baseline. The con-version controller reacts to the change in the the output voltage of the discriminatorby generating the timing signals for the PDH and ADC. The delay of the discrim-inator is often desired to be minimized since in some readout systems the PDH isenabled only after the output of the discriminator changes state. Figure 6.6a showsthe circuit schematic of the implemented discriminator. When the Reset signal ishigh, the operational amplifiers are placed in a unity gain configuration and theoffset voltage of the amplifiers is stored on the capacitors. When the Reset signalis low, the discriminator acts as a high-speed comparator.The circuit schematic of the operational amplifier for the discriminator is shownin Figure 6.6b. The device dimensions are marked on the figure. Each opamp con-96Reset 60 fF60 fFVinpResetResetVinnResetResetReset 60 fF60 fFResetResetResetResetResetResetResetVoutpVoutnopamp opampVinnVinpVoutpIbVdd VoutnVdd(a)(b)400.5 400.51200.5600.550.450.420.520.550.590.50.50.40.50.490.53.50.515.50.515.50.53.50.5Vout0.5550.510.520.520.510.5VddVddFigure 6.6: Circuit schematic of the implemented (a) discriminator, and (b)operational amplifier block of the discriminator.sists of two differential pairs with active loads. Figure 6.7 shows the transientsimulation results of the discriminator. In this simulation, the applied voltage atthe negative input terminal of the discriminator is kept constant at 1.65 V while thevoltage at the positive terminal is swept from 1.645 to 1.655 V. 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