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The study of field programmable gate array based servos in atomic, molecular and optical physics experiments Yu, Shi Jing 2017

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The Study of Field ProgrammableGate Array Based Servos in Atomic,Molecular and Optical PhysicsExperimentsbyShi Jing YuB.ASc., The University of British Columbia, 2014A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinThe Faculty of Graduate and Postdoctoral Studies(Engineering Physics)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)April 2017c© Shi Jing Yu 2017AbstractThe use of Field Programmable Gate Array (FPGA) is becoming increasingly popular in newdesigns for instrumentation tools. Among them, the FPGA-based servo is emerging as a replace-ment for the traditional analog servo as a more versatile, automated and remotely controllablealternative. Despite the demonstration of FPGA servos for the control of lasers in the literature,the practical constraints of an FPGA servo have not yet been fully investigated. This workpresents an open-source FPGA servo design that is capable of reaching a total signal latencyof 200 ns including both conversion delay and computation delay. This work also investigatesvarious limitations inherent in a digital implementation of a servo arising from the computationprecision of an Infinite Impulse Response (IIR) filter and the effect that signal quantizationhas on the transfer function that a digital servo can implement. These technical details arenot widely discussed, but are important both for the design and the operation of the FPGAservo. Applying the FPGA servo in an intensity stabilization application allows direct testsof these limitations. In particular, this work compares the performance of the FPGA servoand a high-performance commercial analog servo with a focus on key specifications includingthe closed-loop bandwidth, noise floor and the resolution of the transfer functions. For closed-loop control scenario with a bandwidth below 1 MHz, we achieve better performance with theFPGA servo than the analog servo through the use of more complex transfer functions includinga Proportional and Integral Cubed (PI3) and a Proportional Integral and Integral (PII) withlag-lead.iiPrefaceAll the work presented in this thesis was conducted at the Quantum Degenerate Gas (QDG)laboratory at the University of British Columbia. The author was heavily involved through-out the development of the FPGA servo and its application in a cold atom experiment, asdescribed by this thesis. The early design of the analog front-end circuit (Section 2.3) and theinvestigation of the performance of the FPGA servo based on the Development and Educationboard 3 (DE3) (Section 4.2.6 and Section 4.2.6) was completed upon collaboration with EmmaFajeau; the investigation of noise floor of the two FPGA servos based on the Development andEducation board 2 (DE2) and the DE3 (Section 4.1) was completed upon collaboration withLin Qiao (James) Liu. The remaining work in Chapter 2, 3 and 4, include the hardware andthe firmware design of the FPGA servo, the design of the intensity stabilization setup and theservo verification is independent and unpublished work by the author S. Yu.The study on the relationship between the active intensity stabilization and evaporationefficiency of trapped atoms was carried out independently by the author but was based ona cold atom apparatus that have been built and maintained by members of the QDG lab.(Details on this apparatus can be found at Will Gunton’s thesis [53]) The final result thatdemonstrates the use of passive stability of the trap laser as the final solution to improveevaporation efficiency (Section 5.4.4) is the result of the investigation by multiple membersthat worked on the apparatus, including Will Gunton, Gene Polovy and Mariusz Semczuk (avisitor at the time).iiiTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xixAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FPGA Servo Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 FPGA Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2.1 Selection Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2.2 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3 Analog Frontend Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.3.1 Design Rationale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.3.2 IC Selection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 112.3.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3.4 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.4 Conversion Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ivTable of Contents2.4.1 ADC and DAC Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.4.2 Single-Ended to Differential Conversion . . . . . . . . . . . . . . . . . . . 222.4.3 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.4.4 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.5 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.5 Servo Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 FPGA Servo Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2 IIR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.2.1 Controller Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.2.2 First-Order IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.2.3 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.2.4 Verification and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 433.2.5 Characterization: Pole and Zero Resolution . . . . . . . . . . . . . . . . . 493.2.6 Characterization: Resource Allocation . . . . . . . . . . . . . . . . . . . . 543.2.7 Comments on Computation Delay . . . . . . . . . . . . . . . . . . . . . . 573.2.8 Comments on PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583.2.9 More on Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.3 Arbitrary Waveform Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.3.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.3.2 Coefficients, Residual Error and Verification . . . . . . . . . . . . . . . . 663.3.3 Alternative Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.3.4 Future Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.4 Proposal on Feature Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.4.1 Lock-in Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693.4.2 Auto-Lock Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703.4.3 Plant Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 Servo Performance and Intensity Stabilization . . . . . . . . . . . . . . . . . . 714.1 Self Lock Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72vTable of Contents4.1.1 Locking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.1.2 Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744.1.3 Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764.1.4 Corner Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764.1.5 Gain Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774.1.6 The Optimal Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804.2 Intensity Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814.2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824.2.2 A Note About Noise Units . . . . . . . . . . . . . . . . . . . . . . . . . . 824.2.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834.2.4 PII Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884.2.5 PI3 Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904.2.6 PII + Lag-Lead Improvement . . . . . . . . . . . . . . . . . . . . . . . . 904.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 Case Study: Evaporation in a Dipole Trap . . . . . . . . . . . . . . . . . . . . . 945.1 Motivation and Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945.2 Dipole Trap and Trap Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 955.3 Loss Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.3.1 Background Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985.3.2 Loss Due to Resonant Scattering . . . . . . . . . . . . . . . . . . . . . . . 985.3.3 Parametric Heating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995.4 Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995.4.1 Heating Rate of Existing Trap . . . . . . . . . . . . . . . . . . . . . . . . 1005.4.2 The Effect of Intensity Stabilization . . . . . . . . . . . . . . . . . . . . . 1005.4.3 Passive Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025.4.4 Improved Evaporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045.5 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106viTable of ContentsBibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109AppendicesA The Servo Daughter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115A.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115A.2 Pending Design Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116A.3 Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116B The Variable Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136B.1 Design Details and Pending Changes . . . . . . . . . . . . . . . . . . . . . . . . 136B.2 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137B.3 Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137B.4 Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137C Register Address of FPGA Peripheral . . . . . . . . . . . . . . . . . . . . . . . 141D PC-Side Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144D.1 Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144D.2 IIR Coefficients and Screening of Transfer Functions . . . . . . . . . . . . . . . . 144D.3 Slow DAC Calibration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146viiList of Tables2.1 A summary of various servo used in the study. . . . . . . . . . . . . . . . . . . . 72.2 Viable ADC and DAC options, their pipeline delay, resolution, etc . . . . . . . . 223.1 A summary of filters implemented in various FPGA platform in this work. Theformat Qx.y means that the Fixed Point (FP) representation of the coefficienthas x integer bits and y fractional bits. In the case of the Q3.28 format, a totalof 32 bits are needed to represent 1 sign bit, 3 integer bits and 28 fractional bits.In the case of the Q5.10 format, a total of 16 bits are needed. . . . . . . . . . . . 413.2 Test values for the IIR filter used in the DE2 servo, where FP representation ofthe the IIR coefficients, B0, B1, B2, B3, A1, A2 and A3, all have 10 bits (therelationship between the FP numbers and the IIR coefficients can by found inEquation 3.25 and 3.26). The implementation details of a first order IIR filtercan be found in Figure 3.4. The input width and the output width of the IIRfilter are both 14-bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3 A summary of the computation footprint of various IIR filters with differentdepth and coefficient widths, quantified by the number of 18 × 18 multipliers. . 563.4 Comparison of computation resources in various FPGA platforms . . . . . . . . . 573.5 The best fit parameters to implement a sine or a Gaussian waveform. The Ar-bitrary Waveform Generator (AWG) is implemented as 4th order fixed pointpolynomial. The parameters related to the ramp (“min”, “max” and “incre-ment”) are 32-bit FP numbers with 16-bit fractional resolution. The parametersfor the polynomial, A0, A1, A2, A3 and A4, are 16-bit FP numbers with 10-bitfractional resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66viiiList of Tables4.1 The expected output noise from sources in the loop in two limits assumingG1G2 = 0.5 and all other components in the loop have unity gain. . . . . . . . . 75A.1 The bill of material of the servo daughter card . . . . . . . . . . . . . . . . . . . 128B.1 The bill of material of the variable attenuator unit. . . . . . . . . . . . . . . . . . 140C.1 The address at which the IIR coefficients can be accessed in the general purposeIIR filter tested on the DE2 FPGA. The coefficients are signed. . . . . . . . . . 142C.2 The address at which the IIR coefficients can be accessed in the IIR filter designedfor the DE3 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142C.3 The register address of the Finite Impulse Response (FIR) filter. . . . . . . . . . 142C.4 The register address for the Serial Peripheral Interface (SPI) module that is usedto control the slow Digital to Analog Converter (DAC)s in the FPGA servo basedon the DE2 and the custom-made servo daughtercard. In the daughtercard, twoIntegrated-Circuit (IC)s are connected in a daisy chain fashion. To communicateto the second IC in the chain, data has to be sent out in multiples of 3 bytes.The SPI module is generated from Altera’s toolbox. . . . . . . . . . . . . . . . . 143C.5 The register address of the AWG module . . . . . . . . . . . . . . . . . . . . . . 143ixList of Figures2.1 A typical control loop consists a servo (also referred to as a controller), an actu-ator (also referred to as a plant or a process) and a detector (also referred to asthe feedback). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 The design architecture of the FPGA servo. The servo is composed of the follow-ing modules, in the order of appearance in this chapter a) FPGA developmentboard b) offset circuit c) gain circuit d) slow DAC e) ADC driver f) ADC g) DAC 62.3 Schematics of the variable offset circuit. Both the current compensation scheme(C306) and the voltage compensation scheme (C307) are shown. . . . . . . . . . 112.4 Schematics of the variable gain circuit. . . . . . . . . . . . . . . . . . . . . . . . . 132.5 Noise model of the offset circuit. The input noise at the op-amp Ninput is small at1.7 nV/√Hz. The noise from the offset voltage varies. For the input offset circuit,Noffset is 3 nV/√Hz and the noise level of the external offset. For the outputoffset circuit, Noffset is 60 nV/√Hz. Nmeasurement varies between 10-100 nV/√Hzdepending on signal amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.6 Noise level of the adder circuit highly depends on noise in the offset voltage, asit is shown in the change in noise floor in frequencies <1 kHz. In frequencies >1kHz the noise floor is limited by the measurement noise floor. . . . . . . . . . . . 152.7 Noise model of the variable gain circuit. The input noise of the Variable GainAmplifier (VGA) is small at 1.3 nV/√Hz. The noise at the control input(Ngain)is 3 nV/√Hz in voltage, which correspond to an error of 120 ndB/√Hz in gain. . 16xList of Figures2.8 Noise at the output of the AD603 at various gain setting, with the input of theAD603 terminated to ground. The Vector Network Analyzer (VNA) input rangeis set to -44 dBV. In frequencies < 200 Hz, the effect of the input noise of theAD603 can be observed to vary with gain. In frequencies >200 Hz, the outputnoise of the AD603 can be observed as it is independent of the gain at a level ofabout -142 dBV/√Hz (this is equivalent to 79.4 nV/√Hz). . . . . . . . . . . . . . 172.9 AD829 bandwidth as affected by external compensation capacitance in the cur-rent compensation mode. The optimal capacitance is 2-4 pF for the negativefeedback configuration of AD829 with a gain of 4, feedback resistance of 4 kΩand feedback capacitance of 1 pF, which agrees with manufacturer’s recommen-dation. It is important to note that the capacitance in the feedback networkaffects the optimal compensation capacitance. . . . . . . . . . . . . . . . . . . . 182.10 AD603 has a constant bandwidth over the whole range of gain, tested between-10 dB and 30 dB at 10 dB intervals. . . . . . . . . . . . . . . . . . . . . . . . . . 202.11 The technology landscape of Analog to Digital Converter (ADC)s, provided byAnalog Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.12 Schematics of the ADC driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.13 Investigation in the noise of signal conversion (ADC/DAC) section of the DE2servo prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.14 Servo transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.1 The general structure of the System on Chip (SOC) design in an FPGA servo.The exact composition of an SOC design and the interface between the FPGAand the ADC and the DAC (represented in dotted lines) vary on a per platformbasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.2 The Direct Form I (DFI) (left) and Direct Form II (DFII) (right) representationof a second order IIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35xiList of Figures3.3 An incorrect implementation of a first order IIR filter with FP coefficients (B0,B1 and A1) with 10-bit fractional resolution. The FPGA implementation is madeup of simple operations like multiplication (×), addition (∑), division (÷) bythe power of 2 implemented as a shift operation, saturation logic ( ) and clockdelays ( ). the width of internal path is noted in grey next to the path. Theplacement of the ÷210 operation has a large effect on the effectiveness of theimplementation. The difference between the incorrect implementation and thecorrect implementation shown in Figure 3.4 is highlighted here in red. . . . . . . 403.4 A correct implementation of a first-order IIR filter with FP coefficients (B0, B1and A1) with 10-bit fractional resolution. The placement of ×210 and ÷210 hasa large effect on the width of the internally stored values and subsequently thecorrectness of the IIR implementation. The FPGA implementation is made upof simple operations like multiplication (×), addition (∑), division (÷) by thepower of 2 implemented as a shift operation, saturation logic ( ) and clockdelays ( ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403.5 Implementation of a 1st order IIR with a built-in gain of 1/2. The coefficientsare FP with 10-bit fractional resolution. The difference between the gain of1/2 implementation and the unity gain implementation is highlight in red. Thedivision of 2 is placed at the output of the filter but the width of the internallystored values are increased to compensate for the potential loss of the outputrange. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.6 Two methods for expanding the order of IIR, depth-wise (left) and length-wisein cascaded form (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.7 Simulation scheme of IIR in a) open-loop and b) closed-loop. Both simulation areimplemented in Hardware Description Language (HDL) and in C++ to 1) verifythe implementation of the IIR in FPGA and 2) to provide better understand ofIIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47xiiList of Figures3.8 The closed-loop simulation with white noise as disturbance. This data shows thespectrum at the input of the closed-loop for two versions of IIR filter: the versionof the IIR with the error in Least Significant Bit (LSB) handling (in red) andthe correct version (in blue). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.9 The effect of noise amplitude on noise suppression. This shows simulation ofdifferent level of noise injected until the servo break out of lock. . . . . . . . . . 493.10 Transfer function measurement (with SR780) of a Proportional and Integral (PI)filter with chirp input of different amplitude. The measured transfer functionapproach the ideal shape as the chirp signal becomes smaller in amplitude. Thissuggests that the non-ideal behaviour of the implemented PI transfer function isdue to clipping at the output of the IIR filter or the FPGA servo. . . . . . . . . 543.11 Transfer function measurement that demonstrates the frequency resolution ofa zero in a PI filter, where coefficients has 10 bit fractional resolution. Thecoefficients are set to B0 = 1024, A1 = 1024 and B1 = −1021, B1 = −1022 andB1 = −1023 for each filter. The corner frequency of the PI filters can be foundas the 3 dB frequency (intersection with the dashed line) and are respectively 22kHz, 14 kHz and 7.1 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.12 Comparison between DE2 (left) and DE3 (right) computation resources . . . . . 553.13 The open-loop simulation of the PI filter and the PII filter in cascaded form,showing the offset at the output of the PI filter and the ramp at the output ofthe PII filter in cascade. As it can be observed in this figure, the input to thefilter is a sine wave with no offset. . . . . . . . . . . . . . . . . . . . . . . . . . . 593.14 The open-loop simulation of a second-order IIR filter configured as a PII filter.The PII in this configuration fails to saturate at its boundary, as opposed to itsexpected behaviour in Figure 3.13 with a PII filter in cascaded form. Instabilitiesoccur at the clock frame 6.6 · 104 (shown in the inset), 8.0 · 104, 8.8 · 104 and9.5 · 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61xiiiList of Figures3.15 Comparison of three different digital filters all implementing a notch filter withcenter frequency at 0.1fclk. Only the bandstop filter designed with the bilinearmethod (lag-lead) is suitable for used in closed-loop, because the elliptic bandstopfilter changes sign at 0.7 fclk and 0.14 fclk and the FIR bandstop filter hasexcessive delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.16 A block diagram of the arbitrary waveform generator, implemented as a counterfollowed by a 4th order polynomial. The counter produces a 32-bit triangularwaveform and can be controlled through internal registers: “max”, “min”, “inc”and “prescaler”. The triangular wave at the output of the first module has arange between “max” and “min” control and a slope of fclk · (inc/prescaler). Thepolynomial coefficients are implemented as 16-bit FP numbers with 10 fractionalbits. Signal responsible for external trigger are “rst” and “trig”. . . . . . . . . . . 653.17 The sine and Gaussian waveform output of the AWG, with their respective resid-ual error. The AWG has two trigger mode, a single trigger modes (in black) anda continuous-trigger mode (in grey). . . . . . . . . . . . . . . . . . . . . . . . . . 673.18 An implementation proposal of lock-in amplifier in the FPGA servo. The servologic is divided in to demodulation, servo and modulation (what is not shownhere is the rest of the servo and the laser configured in closed-loop. Both in-phasecomponent (x) and 90 degree out-of-phase component (y) are recovered from theinput signal and they must be combined as complex numbers (rather than assimple addition of the amplitudes) to generate the error signal. . . . . . . . . . . 694.1 The self-lock configuration is a closed-loop feedback system formed by the FPGAservo and no other detectors or actuators. This is a convenient method forevaluating the performance of a servo. . . . . . . . . . . . . . . . . . . . . . . . . 72xivList of Figures4.2 The self lock data of the DE2 servo and the DE3 prototype servo. The minimumnoise floors of the two servos are -152 dBV/√Hz and -159 dBV/√Hz. They areequivalent to 25 nV/√Hz and 11 nV/√Hz respectively. The self-lock spectrumis optimized according to techniques discussed in sections 4.1.3 - 4.1.6. Addi-tionally, the origin of the spikes in frequencies between 60 Hz and 40 kHz morevisible on the DE2 spectrum is covered in Section 2.4.5. . . . . . . . . . . . . . . 734.3 The model used for analysing the noise suppression in a closed-loop servo systembased on an FPGA servo. For a simpler analysis on noise suppression regardinggain distribution, the non tunable gain in the circuit. . . . . . . . . . . . . . . . . 744.4 The effect of loop gain on noise suppression. As loop gain increases the widthof the suppression band also increases. However, once the amplitude of the loopdelay resonance (at frequencies above 1 MHz) exceed the input range of the ADC,the closed-loop system amplifies rather suppresses noise. . . . . . . . . . . . . . . 774.5 The effect of corner frequency on noise suppression. As the corner frequenciesof the PII filter increase the width of the suppression band also increases. Thelimitation of this optimization technique is covered in the text. . . . . . . . . . . 784.6 The effect of G1 and G2 on noise suppression. When loop gain is kept constant,a higher G1 leads to an improvement in noise suppression in frequencies wherenoise suppression is limited by N1 (the ADC) in the noise model. . . . . . . . . 794.7 The effect of G2 and logic gain on noise suppression. When loop gain and G1are kept constant, decreasing gain through the servo logic in the FPGA andincreasing G2 (the gain between the DAC and the servo output) increases themaximum amplitude of noise that the closed-loop system can correct. . . . . . . 80xvList of Figures4.8 The opto-electrical system used to study intensity stabilization. The intensitystabilization consists of a Radio Frequency (RF) source (RF1), a variable attenu-ator (VAtt1), an Acoustic Optical Modulator (AOM) (AOM1), a photo-detector(PD1) and an analog or an FPGA servo. To study the performance of the in-tensity stabilization system on various level and type of intensity noise, a noisemodulation system is constructed from a RF source (RF2), a variable attenuator(VAtt2), an AOM (AOM2) and a noise generator. Finally, the out-of-loop detec-tion of intensity noise of the system is accomplished via a second photo-detector(PD2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844.9 Diagram of the variable attenuator circuit with the AD829 configured in currentcompensation mode. A snapshot of the layout and additional details can befound in Appendix B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864.10 Control voltage versus transmission through the variable attenuator. It is im-portant to note the variation in the response to input voltage and in maximumRF suppression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864.11 Transfer function of the variable attenuator + AOM + PD system. The loopdelay is about 400 ns. As the delay is dominated by the distance between thelaser beam and the ultrasonic source in the AOM, this delay is modified at variouspoint of the intensity stabilization study due to small positional changes but iskept to a range of 200-400 ns. The modulation bandwidth is in excess of 3 MHz.This opens up the use of this system in high speed intensity modulation. . . . . 874.12 Alternative baseline comparison of DE2, DE3 and Vescent servo for the intensitystabilization study. All servos realize a PII transfer function to match Vescent.The gain and corner frequencies of all servos are tuned to optimize the noisesuppression. The origin of the spikes in frequencies between 60 Hz and 40 kHzvisible on the DE2 spectrum is covered in Section 2.4.5. . . . . . . . . . . . . . . 894.13 Demonstration of the DE3’s ability to implement an additional integrator andits effect on noise suppression. The corner frequency of 70 kHz is used for all3 poles. The suppression slope changes from 40 dB/decade to 60 dB/decade asexpected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91xviList of Figures4.14 The transfer function of the lead-lag and the lag-lead filer with center frequencyat 1 MHz and a bandwidth of 1.5 MHz. The lead-lag filter is composed of zerosat 250 kHz and 4 MHz and poles at 500 kHz and 2 MHz. The lag-lead filter iscomposed of zeros at 500 kHz and 2 MHz and poles are 250 kHz and 4 MHz. . . 924.15 Demonstration of the DE3’s ability to implement lag-lead filter at center fre-quency of 700 kHz. The lag-lead filter has two effects 1) suppression of loopresonance of the servo system 2) allowing increase in gain and thus widening ofthe noise suppression band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925.1 Side view of a focused Gaussian beam (left), the Gaussian-shaped potential, inthe cross section (middle) often approximated as a harmonic potential in thedeep trap limit and the top view of crossed focused beam (right). . . . . . . . . . 975.2 heating rate of the atom cloud when SPI held at 10W. The heating rate corre-spond to a e-folding time of 1.9 s. this is also a screenshot not a proper plot . . . 1015.3 Side by side comparison of Relative Intensity Noise (RIN) level responsible formeasured heating rate and RIN of laser. The constant heating rate line show20 dB/decade slope. It appears that active intensity stabilization should reduceheating rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025.4 Evaporation efficiency of the sample without (yellow) and with (red) intensitystabilization. It is possible to see a small improvement in efficiency for end trappower of 50, 25 and 12 W, but the evaporation still cannot reach the desired trapdepth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035.5 passive stability of fiber laser at various power settings in RIN. . . . . . . . . . . 104xviiList of Figures5.6 The atom number versus final power in the evaporation ramp using the SPIat near its maximum power setup (where the passive stability of the laser isrelatively good) and an AOM to control the power delivered to the atoms showeda highly efficient evaporation (η = 10). The atom number shows an apparentdrop when the ensemble is imaged at zero magnetic field since Feshbach moleculesare forming at powers below 1 W and are not imaged at low magnetic fields. Theimages taken at high magnetic field show that the ensemble is still present andstill evaporating very efficiently down to powers below 100 mW. . . . . . . . . . . 105D.1 Example output of the Personal Computer (PC) software. In this case, the userinput are zeros at -70 kHz and -1 MHz and poles at 0 and -10 MHz and theunderlying servo logic is implemented as a single IIR filter. The input forms anProportional Integral and Derivative (PID) controller, but IIR filter with differentcoefficient resolution emulate the transfer function with different accuracy. Theresulting transfer function from the IIR filter with 16-bit coefficient (Q5.10) failsto implement the integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146xviiiGlossaryECDL External Cavity Diode LaserAO Analog OutputDDR2 Double Data Rate 2LE Logic ElementASIC Application-Specific Integrated CircuitMCU Microcontroller UnitDC Direct CurrentLNA Low Noise AmplifierADC Analog to Digital ConverterDAC Digital to Analog ConverterROM Read-Only-MemoryRAM Random-Access-MemoryGPIO General-Purpose Input OutputIO Input OutputPWM Pulse-Width ModulationRC Resistor-CapacitorPLL Phase-Locked LoopxixGlossaryHSMC High Speed Mezzanine CardADDA Analog-Digital Digital-AnalogADA Analog-Digital-AnalogSRAM Static Random-Access MemorySDRAM Synchronous Dynamic Random-Access MemoryHPS Hard Processor SystemGBP Gain-Bandwidth ProductAMO Atomic, Molecular and OpticalQDG Quantum Degenerate GasFPGA Field Programmable Gate ArrayPC Personal ComputerAWG Arbitrary Waveform GeneratorDE0 Development and Education board 0DE2 Development and Education board 2DE3 Development and Education board 3DE1-SOC Development and Education board 1 System on ChipSOC System on ChipPID Proportional Integral and DerivativePIID Proportional double-Integral and DerivativePD Proportional and DerivativePI Proportional and IntegralxxGlossaryHP High PassLP Low PassP ProportionalI IntegralD DerivativePII Proportional Integral and IntegralPI3 Proportional and Integral CubedIIR Infinite Impulse ResponseFP Fixed PointFIR Finite Impulse ResponseDFI Direct Form IDFII Direct Form IIHDL Hardware Description LanguageFFT Fast Fourier TransformLSB Least Significant BitLUT Look-up TablePDH Pound-Drever-HallNIST National Institute of Standards and TechnologyAOM Acoustic Optical ModulatorLC Inductor-CapacitorIC Integrated-CircuitxxiGlossaryPCB Printed-Circuit-BoardTeO2 Tellurium DioxideESA Electrical Spectrum AnalyzerNEP Noise-Equivalent PowerRIN Relative Intensity NoiseTOF Time-of-FlightMOT Magneto-Optical TrapVNA Vector Network AnalyzerSNR Signal to Noise RatioRF Radio FrequencyVGA Variable Gain AmplifierCPU Central Processing UnitIO Input OutputROM Read Only MemoryRAM Random Access MemoryDSP Digital Signal ProcessingGUI Graphical User InterfaceHDL Hardware Description LanguageDDS Direct Digital SynthesizerSPI Serial Peripheral InterfaceNOP No OperationxxiiAcknowledgementsI would like to thank my supervisor prof Kirk Madison for his unconditional support towardsmy thesis project, prof David Jones for helpful conversations, Emma Fajeau, James Liu forcollaborating on the FPGA servo project and William Bowden, Mandana Amiri and PavelTrochtchanovitch for their insights on laser controllers, FPGA and analog circuits, respectively.I would also like to acknowledge the Altera (now Intel FPGA) University Program for providingfree samples of the DE3 and the ADC/DAC that was used to build the DE3 servo.Thanks to everyone at the lab who are involved in training me on tuning lasers and runningthe cold atom experiments. They are, my supervisor (of course), prof James Booth, WillGunton, Gene Polovy, Janelle Dongen and Mariusz Semczuk. Also thanks to my peers, KahanDare and Kais Jooya for adding a touch of social aspect to graduate level courses.I would also like to thank my boyfriend, now fiance and soon husband, Jonathan Fraserand his parents, Cindy and Peter, for their support, and most importantly, my parents, WenSong (Vincent) Yu and Xiu Ju (Judy) Wang, for all the foresight and sacrifice that went intoenabling me with a great education.xxiiiChapter 1IntroductionThe Field Programmable Gate Array (FPGA) is a rapidly developing technology that has en-abled a broad array of applications in both basic science and industry. An FPGA chip hasthe advantage of both speed and flexibility. It can achieve similar speeds to a MicrocontrollerUnit (MCU) or an Application-Specific Integrated Circuit (ASIC), but unlike the MCU andASIC, the FPGA digital circuitry is not hardwired but can be programmed and re-programmed.In the infancy of this technology, implementing digital logic produced circuits that ran slower,consumed more space and were less energy efficient than competing technologies, but the ad-vantage of flexibility and a shorter development cycle kept the FPGA in demand [1]. Over theyears, significant improvements regarding speed, space consumption and energy consumptionhave been made. Additionally, more sophisticated routing mechanisms and Digital Signal Pro-cessing (DSP) computation resources have also been implemented on FPGAs (a survey on theFPGA technology up to 2008 can be found at [2]). These benefits and advancements have, inturn, been enjoyed by both industrial and the scientific communities.Like most research communities, the Atomic, Molecular and Optical (AMO) experimentalcommunity has a strong demand for versatile instrumentation and computational tools. AMOexperiments rely on precise control of lasers including their wavelength, phase, polarization andintensity. To accomplish this, an array of instrumentation tools are needed. The laser servo isan instrument used to form a closed feedback loop control system to make corrections to thelaser with an actuator and a detector. (The term servo is in analogy to the use of the term“servo in motion control.)Traditionally, laser servos, also sometimes referred to as loop-filters, are built from analogcomponents like opamps and impedence networks. The design of an analog servo can be foundas early as John Hall’s original paper on the Pound-Drever-Hall (PDH) modulation method in1Chapter 1. Introduction1989 [3]. In this paper, the phase detector is constructed as a mixer and the control mechanism(servo), in the form of a Proportional Integral and Derivative (PID) filter, is built from twocascaded op-amp stages, each implementing an integrator and a differentiator. Traces of JohnHall’s servo design can be observed in published works with references to the “Jila loop-filter”[4] and commercial stand-alone units based on the Hall design have now become available.Migration of instrumentation systems from op-amp based analog systems to digital designsnaturally follows from the advancement of digital technologies.The development of an FPGA-based servo was reported in published work as early as 2002[5]; however, the high cost of the FPGA hardware at the time meant that adoption of thisapproach was not immediate and widespread use of FPGAs for servos would happen muchlater. Today, phase locked loops, lock-in detectors, and arbitrary waveform generators have allbeen realized in the digital domain including, recently, FPGA based implementations [6], [7].The question of how quantization error affects digital servos has not yet been fully addressedand is one of a main topics of investigation in this work. This question of quantization erroris embedded in similar questions regarding the use of digital designs for feedback control: howdoes a digital servo implemented in an FPGA compare with a high-performance analog servo?Similarly, is there any trade off made with gaining versatility and automated control? The useof an FPGA servo spans may applications including the locking of an External Cavity DiodeLaser (ECDL) in atom/ion trapping experiments [8], [9] for spectroscopy [10] and for atominterferometry [11], [12]. The advantage of digital system is its flexibility since, as it is oftenargued, it requires no soldering to be reconfigured with a different transfer function.Naturally, the need to understand and quantify the role of quantization error follows theintroduction of digital systems. In the implementation of lock-in logic in a digital form, it wasclear that the sampling quantization error has an effect on the Signal to Noise Ratio (SNR) ofthe lock-in detector [13], and thus should be handled with care.The question of how quantization error affects digital servos has not yet been fully addressedand is one of the main topics of investigation in this work. This question of quantization erroris embedded in similar questions regarding the use of digital designs for feedback control: howdoes a digital servo implemented in an FPGA compare with a high-performance analog servo?Similarly, is there any trade off made with gaining versatility and automated control?2Chapter 1. IntroductionIn the attempt to answer some of these questions, this work started with the development ofan FPGA servo. The hardware developed by this work focuses on the high performance aspectsoffered by the FPGA technology. Similar work that focuses on high-performance FPGA servosare relatively few [14] and should be differentiated from digital servo designs with bandwidths<100 kHz, suitable for low bandwidth applications that also need servos in large quantities[6], [15], [16]. This work is also interested in understanding how to push the performance ofan FPGA servo beyond what is capable with an analog servo, and this necessitates testingin a closed-loop application. In this work, we chose intensity stabilization as our applicationfor closed-loop studies, and, with it, we achieved a closed-loop bandwidth of 1 MHz. Thisapplication allowed us to benchmark the FPGA servo in a high bandwidth setting and toexplore some of its advantages over a high-performance analog servo including its ability tofine tune the transfer function to achieve optimal performance. It also allowed us to identifypreviously unrecognized limitations and areas of particular concern with FPGA servosThis thesis follows the development of our FPGA servo. Each chapter covers topics in thevarious stages of our development efforts in the following order: hardware design, firmwaredesign, closed-loop performance tests and, finally, the application of the FPGA-based servoin a cold atom experiment. The theoretical background pertinent to the various topics iscovered in each chapter. The thesis is meant to acquaint a new designer with all aspects in thedevelopment an FPGA servo, and, therefore, it is explicit with describing mistakes made duringthe development of the FPGA servo. This work may also be of interest to researchers that areinterested in using recently developed FPGA servo products, such as Digilock by Toptica (200ns total signal delay) [17], as this work investigates some of the considerations and limitationsone should be aware of when using an FPGA based servo. Moreover, we believe this workprovides some insight into the present state and the development bottle necks of FPGA basedservo technology.3Chapter 2FPGA Servo HardwareThe hardware of the FPGA is the development platform for all servo logic and signal process-ing related elements used in a closed-loop control application. Thus, the hardware plays anindispensable role in determining the performance of an FPGA based servo. The underlyinghardware, therefore, affects whether an FPGA servo is suitable to replace existing analog servosin many applications. This chapter focuses on the design and specification of a complete set ofFPGA servo hardware elements. Later chapters discuss the development and implementationof the servo logic and signal processing units.Two design specifications are important for a servo design and thus are recurring throughoutthis thesis. They are the closed-loop bandwidth and the noise floor. The closed-loop bandwidthof the servo is important because it determines the highest frequency that the servo can correctfor. As it is shown in Figure 2.1, a typically control loop consists of a servo/controller thatis responsible for generating correction to a quantity under control, an actuator/plant respon-sible for carrying out the correction and a detector that monitors the quantity under controland provides feedback to the servo. It makes little sense to use a actuator/plant that has aextremely high closed-loop bandwidth of, for example, 10 MHz, if the servo can only respond todisturbances up to 100 kHz. In this scenario, the closed-loop bandwidth of the overall systemwould be dominated by the servo because the closed-loop bandwidth is determined by the sumof delay in all the component. Hence, the closed-bandwidth of the FPGA servo limits its usewith actuators/plants and its applications.Servo ActuatorDetectorSetpoint OutputFigure 2.1: A typical control loop consists a servo (also referred to as a controller), an actuator(also referred to as a plant or a process) and a detector (also referred to as the feedback).42.1. Architectural OverviewThe other design specification, the noise floor of the servo, is important because it determinesthe signal level that the servo can correct at. We are rather familiar with the typical noisesources in an analog circuit such as the input-derived op-amp noise and Johnson noise. Oneinitial concern in the addition of digital system to the servo is the quantization errors at theAnalog to Digital Converter (ADC) and the Digital to Analog Converter (DAC). As laterexperimentation shows, quantization error at the ADC or the DAC is not neccessarily an issuefor the noise floor of an FPGA servo, expecially when the signals can be over-sampled andaveraged, as the effect is explained at some external sources [18]. It is nevertheless importantto keep in mind that the quantization affects a digital servo in areas besides the noise floor,and the details are covered in more detail in Chapter 3.Based on these general considerations, this work was carried out under the intuitive assump-tion that a faster and quieter servo is in general more useful. To explore the best FPGA servothat the current technology has to offer, we set out to design the FPGA servo “from scratch”,while knowing that the final hardware needs to be competitive against existing analog servoswith 10 MHz closed-loop bandwidth and 10 nV/√Hz noise floor [19].The design specification on speed and noise floor is addressed by each component of theservo. The chapter starts with the architectural overview and then describes the particulardesign challenges in individual sections in detail.2.1 Architectural OverviewThe FPGA servo is a mixed-signal system, as illustrated in Figure 2.2, that can be dividedinto a digital section, an analog front-end section and a signal conversion section. Reductionof noise and optimization in bandwidth are important in each section although subtly differentdesign objectives are present in each module.The digital section, mainly consisting of the FPGA, is responsible for high-speed signalprocessing and the implementation of the servo logic. This work relies on commercially availableFPGA platforms to access high-performance FPGAs that would otherwise take too long todesign and test on a Printed-Circuit-Board (PCB). It is nevertheless important to ensurethat the FPGA can accommodate an on-board MCU and intensive signal processing. The52.1. Architectural Overview+ +Remote PCPIDMicro-controllerDACDACslowDACslowDACslowDACslowADCa)b) c)d)e) f) g)Fast data pathSlow data pathFigure 2.2: The design architecture of the FPGA servo. The servo is composed of the followingmodules, in the order of appearance in this chapter a) FPGA development board b) offsetcircuit c) gain circuit d) slow DAC e) ADC driver f) ADC g) DACrequirement for an on-board MCU, whether it is in the form of a softcore MCU or a hardcoreMCU, is advantageous for feature expansion. Additionally, the requirement for computationcapability is necessary to implement the servo logic and other DSP tool in the FPGA, which isrequired to accomplished the primary objective of this work. The hardware description of theFPGA in Section 2.2 provides more details.The analog front-end is responsible for conditioning the signals at the input/output of theservo to match the voltage range of the ADC and DAC. The design of the analog front-endproduced by this work provides extensive flexibility with the use of a variable gain circuit anda variable offset circuit on each of the input/output of the servo. Digital control of theseconditioning circuits is provided by an array of slow-updating DAC directly accessible by theFPGA. This design allows the FPGA servo to be remotely controlled in a wide range of controlapplications.Finally, the signal conversion section, mainly consisting of the ADC and the DAC, is re-sponsible for converting an analog signal to the digital domain and vice versa. In the signalconversion section, the optimization for closed-loop bandwidth is equivalent to reducing theconversion latency through the ADC and the DAC. In contrast to our initial impression, thelatencies through many high-speed ADCs and DACs is much higher than what the clock speedsof these devices suggest.62.2. FPGA SectionDevelopment TimelineTwo FPGA servos, based on the Development and Education board 3 (DE3) FPGA platform[20] and the Development and Education board 2 (DE2) FPGA platform [21], are first con-structed as prototypes from modular pieces, as shown in Table 2.1. In the prototypes, the analogfront-end is designed and tested as a PCB that consistings a variable offset circuit followed bya variable gain circuit. The slow DAC needed to control the variable gain and variable offsetcircuit is based on an existing 8-channel Analog Output (AO) design by Todd Meyrath [22].The signal conversion sections of the prototypes are based on commercially available cards thathave to be modified to accommodate Direct Current (DC) signals. The prototype servos allowus to verify the closed-loop performance of FPGA servos on two different FPGA platform, theDE2 and the DE3.Table 2.1: A summary of various servo used in the study.FPGA Conversion Offset and Gain Slow DACDE3-Prototype DE3 [20]AD/DAby Altera [23]Custom PCBPCBDE2-Prototype DE2 [21]THDB-ADA by Todd Meyrath[22]by Altera [24]DE2-Final DE2 Custom PCB as shown in Appendix AOnce the performance of the servos is confirmed, we compiled the electronics design onto acustom daughtercard compatible with the DE2, DE3, a few of the other Altera FPGA develop-ment boards. The servo design based on the custom daughtercard is easily replicated and moreconvenient to use than the prototypes. The final servo design is characterized and provide mostof the supporting data in this chapter unless it is otherwise specified.2.2 FPGA SectionThe FPGA section is responsible for high-speed signal processing and the implementation ofthe servo logic. This section describes the selection criteria of the FPGA in detail and thecompatibility of our FPGA daughter card design with other existing FPGA platforms.72.2. FPGA Section2.2.1 Selection CriteriaIO InterfaceThe Input Output (IO) interfaces of the FPGA development board need to support high-speedparallel signals for use with the ADC and DAC. Two types of IO are popular among theAltera development boards, with one being the High Speed Mezzanine Card (HSMC) high-speed connection and the other one being the 2×20 General-Purpose Input Output (GPIO)connectors. The HSMC connector is suitable for high speed signals and is available on the DE3board among other high-speed research development boards. The GPIO connector is availableon a wider range of development board, including the DE3, DE2, Development and Educationboard 0 (DE0) and Development and Education board 1 System on Chip (DE1-SOC). Bothinterfaces seem to be supported by many of Alteras boards including some data acquisitiondaughter cards. For the FPGA servo prototypes realized in this work, the DE3 platform ispaired with the Analog-Digital Digital-Analog (ADDA) card with HSMC interface and theDE2 platform is paired with the Analog-Digital-Analog (ADA) card with the GPIO interface.The two types of interfaces are not directly compatible but conversion can be made using acommercially available converter.MCU UnitThe second consideration is the support for a MCU in the digital system. It is becoming morecommon for FPGA designs to accommodate a MCU rather than co-processor as a separate chip.Less urgent tasks can be more quickly implemented in the MCU rather than in the FPGA, sothe use of an softcore or a hardcore MCU reduces to development time needed for featureexpansion. The more recent FPGA are equipped with Hard Processor System (HPS), but theDE2 and DE3 platform that this work uses do not contain HPS but rather contain sufficientnumber of Logic Element (LE)s to instantiate a NIOs II softcore MCU provided by Altera.Besides sufficient number of LEs to instantiate an MCU inside the FPGA, other platformrequirements include sufficient run-time memory in the form of Random Access Memory (RAM)and non-volatile storage of both the FPGA configuration binary and the MCU executable. TheDE3 is equipped with 1 GB external RAM in the form of Double Data Rate 2 (DDR2) RAM,82.2. FPGA Sectionbut the memory bits that are built-in to the FPGA of a total of 5,499 kbit and is sufficient torun the Nios II MCU. The DE2 FPGA doesn’t have enough on-chip memory to run the NiosII MCU, so the design uses 512 KB of Static Random-Access Memory (SRAM) or 8 MB ofSynchronous Dynamic Random-Access Memory (SDRAM) for run-time memory. In terms ofkeeping nonvolatile configuration of the FPGA and the MCU on the development board, theEEPROM serial configuration Integrated-Circuit (IC) on each of the platforms, EPCS16 (DE2)and EPCS128 (DE3), are sufficient, as the FPGA image and the MCU image can be combinedinto the same image and stored onto the same chip (the commands for doing this can be foundhere [25]).DSP UnitsThe final consideration is the computation capability of the FPGA. In the case of the DE3, 38418-bit by 18-bit multiplier is available on the Stratix III EP3SL150 FPGA on the developmentplatform. However, in the case of the DE2 the number of multiplier is more scarce at 35 18-bitby 18-bit multipliers. This is why, after computation resources needed for a FPGA servo isinvestigated in Section 3.2.6, the study come to the conclusion that the DE2 isn’t the mostsuitable for an FPGA servo design and rather recommends an FPGA development platformwith more computation resources (refer to Section 3.2.6 for more details) for future development.While it is true that regular LEs in an FPGA can be configured as multipliers but are certainlyslower due to the additional length of wires need to configure LEs into multipliers compared toa hard-wired multiplier.2.2.2 CompatibilityBecause a servo daughtercard is designed to be easily reproducible for future use, it is importantto note its future-proof-ness and compatibility with other FPGA development board. BecauseAltera’s line of FPGA development board has moderate compatibility with one another due toits common expansion header, a daughtercard designed to be compatible with one developmentboard needs very little modification to be used with another development board. This iscertainly true with the daughtercard originally designed for the DE2 and that means the DE3and the more recent DE1-SOC is also compatible with the servo daughter card design by this92.3. Analog Frontend Sectionwork. This compatibility matrix makes it is rather effortless to upgrade to a newer FPGAplatform from a hardware standpoint as long as Altera continues to support the format of theGPIO header. The servo firmware is also written with future migration in mind to the best ofour ability. Information on compatibility of the servo logic with other FPGA can be found inChapter 3.2.3 Analog Frontend SectionThe analog front-end is responsible for conditioning the signals at the input/output of theservo to match the voltage range of the ADC and the DAC. This section describes the designrationale, IC selection criteria and the characteristics of the analog front-end circuit in detail.2.3.1 Design RationaleAn FPGA servo needs to work with a wide range of measurement devices and laser controllers,but voltage ranges of the ADC and the DAC are rather limited (0-3.3 V in this design). Thismotivates the design of the analog frontend. When designing the analog front-end, the varietyof measurement devices and actuators, like the photodetector, frequency discriminator, lasercurrent driver and piezo driver can all be simply regarded as an input/output voltage range,with common voltage ranges like 0-10V, ±10V, 0-3.3V and 0-5V.Tunable gain and offset is useful when working with different voltage range and signal sizes.A tunable gain circuit can be used match the amplitude of the measurement signal to the ADCor the DAC voltage range to the laser controller. The tunable offset can be used to removeany DC component in the signal that contains little information about the signal but takes upvaluable operation range of the ADC or the DAC. The offset circuit at the input of the servoalso controls the setpoint that the servo locks to. Modulation of this input offset signal addsmodulation capability to a closed-loop system.Remote tunability of the analog front-end is accomplished by the use of slow DAC to controlthe offset and the gain at the input and the output of the servo. This tunablity is complimentaryto the ability for the FPGA servo to implement various transfer functions (Chapter 3).102.3. Analog Frontend Section2.3.2 IC Selection ConsiderationsThe choice of three ICs is specially important for the performance of the analog frontend. TheICs are the op-amp for the offset circuit, the amplifier used for the gain circuit and the slowDAC used for digitally controlling the offset and the gain. This section covers the selectioncriteria for each chip and some alternative designs that are rejected in the design process.Variable Offset StageThe variable offset circuit is simply an op-amp configured in the adder configuration, as shown inFigure 2.3. The adder configuration does not restrict the selection of op-amps, but requirementfor speed and noise does. The design uses the AD829 for a bandwidth of 12 0MHz, a slew rateof 230 V/µs and low input noise of 1.7 nV/√Hz, as indicated by its datasheet. The morecommonly used LM741 and OP37 were briefly considered although their were finally rejecteddue to to their lower slew rate, 0.5 V/µs and 17 V/µs respectively, and rather high input noiseof 20 nV/√Hz in the case of the LM741.The AD829 opamp requires external compensation in the picofarad range to operate at fullspeed. It is therefore not wise to prototype this circuit on a breadboard/stripboard becausethe parasitic capacitance in a breadboard/stripboard can affect the slew rate of the op-amp.The schematics shown in Figure 2.3 shows the configuration for both voltage compensation(C307) and current compensation (C306), as the compensation schemes are defined by theAD829 datasheet. The external compensation scheme is finally decided to be the currentcompensation, (C306) after the AD829 is tested on a PCB.R306R300C300R309AGND C306C307AGNDOFFSET_INPUTSIGNAL_INSIGNAL_OUT2365COMPAD829JRFigure 2.3: Schematics of the variable offset circuit. Both the current compensation scheme(C306) and the voltage compensation scheme (C307) are shown.112.3. Analog Frontend SectionVariable Gain StageThe variable gain stages are needed to scale the input/output signal of the servo to fit in theoperating range of the the ADC or the DAC. A few implementation schemes for a variable gainstage are available, so some work went into searching for a suitable Variable Gain Amplifier(VGA) design.Potential designs for the variable gain stage include the use of digital potentiometers orrheostats, which are resistors that can be digitally programmed. The limitation of this technol-ogy is resolution and bandwidth. The chipsets that represent the state-of-the-art technologyare the Analog AD514x and AD512x series, with bandwidth of 3 MHz and resolution of 8 bit.It is possible to mitigate the lack of resolution with a network of digital potentiometers, butbandwidth limitation can not be overcome and that leads to the rejection of this design scheme.Other rejected designs are VGAs with a discrete selection of gain and ADCs packaged withVGAs in single ICs. The former can be troublesome to tune as it does not provide a continuousrange of gain. The later is rejected for its obscurity and a lack of high speed options.Within the selection of VGA with continous range of tunable, we found it important to testthe VGA to make sure that the IC is rated for DC. One unsuccessful example is the use of theAD8367, a VGA that represents a class of multi-hundred MHz VGAs that are not rated for DCsignals. In the case of the AD8367, the gain is constant over two distinct frequency regions buthas a change of 3 dB in gain between the two frequency regions. This renders the IC uselessfor closed-loop servo applications. Accordingly, we proceeded by carefully selecting and testinghigh speed VGAs from the selection table provided by manufacturer to avoid similar problems[26].After surveying the whole design space, this work came up with the single variable gain op-amp AD603 that has 40 dB of tunability, a constant passband of DC - 91 MHz and a tunablegain of 40 dB. The design of the variable gain stage is very simple as shown in Figure 2.4.Besides the signal input to and output from the amplifier, the VGA takes a control input of±0.5 V. A voltage divider is installed to accept a voltage input range of ±10 V. The voltagedivider also doubles as a low-pass filter and is used to suppress noise in the slow-DAC at highfrequencies.122.3. Analog Frontend Section+5V-5VAGNDGAIN_INPUTGAIN_CTRL18kR3211KR3241uFC325AGNDGAIN_CTRL499R311AGNDSIGNAL_INSIGNAL_OUT12345678COMMING-G+FBAD603ARFigure 2.4: Schematics of the variable gain circuit.Slow DAC SelectionThe use of the slow DAC in controlling the gain and offset of the analog front-end allows theservo to be tuned digitally. The speed requirement on the slow DAC is rather relaxed comparedto the ADC and the DAC that are directly responsible for the servo action. This allows thecommunication interface of the slow DAC to be serial to reduce the total IO usage on theFPGA.The design consideration behind the slow DAC is an economic one because a total of 8 DACchannels is needed for the dual-channelled FPGA servo (one tunable offset and one tunable gainon each of the input/output of a servo channel).The implementation of the 8-channel DAC is different in the prototypes and the final designof the servo daughter card. In the case of the servo prototypes, the slow DAC channels arecontrolled by a separate FPGA platform that interfaces with the 8-channel DAC card designedby Todd Meyrath [22]. The DAC card is based on 2 DAC7744 ICs and exposes a parallelinterface and it is controlled by an USB-to-parallel converter that this work commissioned onanother FPGA platform. A total of two FPGAs are used in constructing each servo prototypethat we used to test out understanding about the FPGA servo. The construction is unnecessarilybulky and that motivated the design of the servo daughtercard.In the case of the servo daughter card, the number of unused IOs on the GPIO header issmall. This necessitates serial communication and sharing of signals between the slow DAC132.3. Analog Frontend SectionICs. The slow DAC IC used in the daughtercard design is a serialized version of the IC usedin Todd’s design, with ±10 V output range and a noise level of 60 nV/√Hz. This meansthat measurements made on the prototype servos apply to the daughtercard. This work alsoconsidered the use of AD5669, an 8-channel DAC, but the lower SNR of the IC (120 nV/√Hzwith an output range of 0-5 V) degrades the performance of the servo, so it is subsequentlyrejected.Another feature of the slow DAC section is the synchronous latching of the control param-eters, enabled the connection between the latching signals on the slow DACs and the FPGA.We speculate that updating all servo parameters at the same time causes less disturbance inthe servo loop and can be very useful in feature developments in the future.2.3.3 NoiseOffset CircuitThe work in reducing noise in the analog front-end circuit does not stop at the use of low noiseamplifiers. A noise model for the offset circuit is helpful in identifying and eliminating noisesources.The noise model for the offset circuit is based on the adder configuration, as shown in Figure2.5. Noise sources include the noise in each branch of the adder and the input derived noiseof the op-amp. The thermal noise of the feedback resistors (in the range of 1-10 kΩ which isresponsible for 4-12 nV/√Hz of thermal noise) is neglected which lead to a less accurate butstill sufficient model. It is to note that the noise floor of the measurement can limit the qualityof the noise measurement. The SR780 Vector Network Analyzer (VNA) used the study hasa minimum noise floor of 10 nV/√Hz but can have a higher noise floor when the samplingwindow is increased to measure a larger input signal.The dominating sources of noise in the offset circuit is the offset voltage from the slow DAC,rather than the op-amp input noise. Reduction of noise from the slow DAC improves the noisefloor of the offset circuit substantially. In the case of the offset circuit at the input of the servo,the slow DAC voltage of ±10 V is reduced to a range of ±0.6 V with a 19:1 voltage divider.This should in theory reduce noise of the slow DAC from 60 nV/√Hz to 3 nV/√Hz. The result142.3. Analog Frontend Section+ +Ninput Noffset Fixed Gain+Nmeasurement+Figure 2.5: Noise model of the offset circuit. The input noise at the op-amp Ninput is smallat 1.7 nV/√Hz. The noise from the offset voltage varies. For the input offset circuit, Noffsetis 3 nV/√Hz and the noise level of the external offset. For the output offset circuit, Noffset is60 nV/√Hz. Nmeasurement varies between 10-100 nV/√Hz depending on signal amplitude.of this improvement is illustrated in Figure 2.6 where noise level after improvement is belowthe noise floor of the measurement.10 1 10 2 10 3 10 4 10 5Frequency [Hz]-140-135-130-125-120-115Noise[dB(Vpk=pHz)]Noise Spectral Denisty, Offset CircuitOffset circuit with slow DAC,without the 19:1 voltage dividerOffset circuit,slow DAC by-passedFigure 2.6: Noise level of the adder circuit highly depends on noise in the offset voltage, as itis shown in the change in noise floor in frequencies <1 kHz. In frequencies >1 kHz the noisefloor is limited by the measurement noise floor.In the absent of this input offset, the servo locks to 0 V. The final design of the servo allowsthe slow DAC to be turned off and it allows the use of an external offset. The user must thenbe careful with selecting the offset source, as any noise in the offset voltage can degrade thenoise performance of the offset circuit.152.3. Analog Frontend SectionIn the case of the offset circuit at the output of the servo, the range of ±10 V in offset isneeded to accommodate a wide range of laser applications. The divider is then absent in theoutput offset circuit. The decision is justified by the ability of a servo to suppress noise at itsoutput, as it is demonstrated in Chapter 4.Gain CircuitA noise model is also built for the VGA to investigate noise sources in the variable gain circuit.As shown in Figure 2.7, noise is present at the signal input and the signal output of the amplifierand at the control input for the gain. The input noise of the amplifier is small at 1.3 nV/√Hz.The noise in the control signal is originally 60 nV/√Hz from the slow DAC but is reduced aftera voltage divider of 19:1. The control input is responsible for an error in gain of 120 ndB/√Hz.In the worse case scenario when the input signal or the output signal saturate at either railof the AD603 (maximum output range of ±3 V), the error in gain converts to a theoreticalmaximum noise level of 41 nV/√Hz.Ninput Ngain NmeasurementNoutput + + ++Figure 2.7: Noise model of the variable gain circuit. The input noise of the VGA is small at1.3 nV/√Hz. The noise at the control input(Ngain) is 3 nV/√Hz in voltage, which correspondto an error of 120 ndB/√Hz in gain.The noise source at the output of the AD603 is a significant source of noise as it is demon-strated by the set data shown in Figure 2.8. In the measurement, the input to the AD603 isterminated to ground and the gain is set to three settings that are 10 dB apart. The noise floorin frequencies >200 Hz is not dependent on the gain, and this suggests that the noise sourceis at the output of the amplifier. The possibility of the limiting factor being the measurementnoise is carefully eliminated, which lead to the conclusion of the presence of about 80 nV/√Hznoise at the output of the AD603 amplifier. We decided that this noise does not necessarilydegrade the performance of the servo, because the noise is similar in amplitude as the noise162.3. Analog Frontend Sectionlevel in the ADC region. We simply move on to different part the the servo design with theknowledge of this issue.10 1 10 2 10 3 10 4 10 5Frequency [Hz]-145-140-135-130-125-120-115-110Noise[dB(Vpk=pHz)]Noise Spectral Denisty, Gain CircuitAD603, Gain = 31AD603, Gain = 10AD603, Gain = 3.3Figure 2.8: Noise at the output of the AD603 at various gain setting, with the input of theAD603 terminated to ground. The VNA input range is set to -44 dBV. In frequencies < 200Hz, the effect of the input noise of the AD603 can be observed to vary with gain. In frequencies>200 Hz, the output noise of the AD603 can be observed as it is independent of the gain at alevel of about -142 dBV/√Hz (this is equivalent to 79.4 nV/√Hz).2.3.4 BandwidthOffset CircuitThe AD829 opamp needs to be configured with external capacitance in the pidofarad range tooperate at full speed. The optimal compensation scheme for a fixed gain of 1 or 4 is investigatedin the first PCB design of the analog frontend design, which allows both external compensationschemes (current and voltage) to be tested. After the compensation scheme is decided, thespeed of the offset circuit in the final design of the servo is characterized over a range ofexternal capacitances. The purpose of the test is to optimize the speed of the offset circuit inthe final servo design and to ensure that similar speed can be reproduced over the tolerance172.3. Analog Frontend Sectionvariance of the capacitors. The result of this test is shown in Figure 2.9.-50 0 50 100 150 200Time (ns)-0.500.511.522.533.54Voltage (V)AD829 Current Compensation Mode, Large Signal ResponseInput SignalCcomp  = 2 pFCcomp  = 3 pFCcomp  = 4 pFCcomp  = 9 pFCcomp  = 12 pFCcomp  = 18 pFCcomp  = 25 pFFigure 2.9: AD829 bandwidth as affected by external compensation capacitance in the currentcompensation mode. The optimal capacitance is 2-4 pF for the negative feedback configurationof AD829 with a gain of 4, feedback resistance of 4 kΩ and feedback capacitance of 1 pF, whichagrees with manufacturer’s recommendation. It is important to note that the capacitance inthe feedback network affects the optimal compensation capacitance.The input to the circuit is generated from a digital output of an FPGA, which approximatesa step function with the exception of some ripples due to impedance mismatching at the termi-nals. The response at the output of the opamp is measured with an oscilloscope and the delaythrough coaxial cables to and from the circuit is calibrated away. A set of step response withvariation in compensation capacitance (current compensation) is shown in Figure 2.9. The useof large signal response helps to reveal the slew rate of the op-amp. It is worth noting thatall step response shown is the current compensation mode as we are not able to reproducesimilar speed in the voltage compensation configure as described by the AD829 datasheet inany iteration of the analog front-end design.When a gain of 4 and a feedback capacitance of 1 pF is used, the optimal compensationcapacitance is 2-4 pF. The result agrees with manufacturer’s recommendation. In the data, the182.4. Conversion Sectionvariation of 2-4 pF in capacitance results in a very small variation in slew rate. This suggeststhat the bandwidth performance in a larger production of the servo daughtercard will not varymuch from the results obtained by this work.Gain CircuitFor designers who are familiar with the constant Gain-Bandwidth Product (GBP) of an op-amp, the ability for the AD603 to maintain a constant bandwidth of 90 MHz over a 40 dBrange of gain can be surprising. This unique property of the AD603 is accomplished usinghigh bandwidth digital potentiometer followed by an Low Noise Amplifier (LNA). The digitalpotentiometer is responsible for varying the gain by a range of 40dB when the gain through theLNA remains fixed. The gain in the LNA is determined by an externally configured feedbackloop where in this design is set to the lowest gain setting to produce the highest bandwidth(DC-90 MHz).The measurement of bandwidth shown in Figure 2.10 is accomplished with step input andan oscilloscope as described in the step response measurement of the offset circuit. The responseof the AD603 over different gains confirms that a high bandwidth is maintain over the entirerange of gain settings. The small amount of variation in response time with a spread of roughly1 ns is likely due to the presence of ripples in the trigger signal and the shot-to-shot variationin the shape of the ripples.2.4 Conversion SectionThe conversion section is the bridge between the analog front-end and the FPGA in the designof an FPGA servo. It is also a main source of delay in the FPGA servo. This section describesthe selection criteria for the various ICs that fulfill the function of the conversion and theiroverall characteristics, both in terms of noise and latency.2.4.1 ADC and DAC SelectionsThe key selection criteria for the ADC and the DAC are signal latency and resolution. Thesetwo criteria are almost the opposite of each other since a high resolution ADC or DAC typically192.4. Conversion Section-10 0 10 20 30 40 50 60 70 80 90Time (ns)-0.0500.050.10.15Voltage (V)Small Signal Response of AD603 at Various GainInput SignalGain = 0.33Gain = 1Gain = 3.3Gain = 10Gain = 31Figure 2.10: AD603 has a constant bandwidth over the whole range of gain, tested between -10dB and 30 dB at 10 dB intervals.has a high latency and and a low latency ADC or DAC typically has a smaller bit depth. Thistrend can be observed from the technology landscape of ADCs made by Analog Devices, asshown in Figure 2.11. The available ADCs requires choosing a resolution of 16-bit or lower tokeep the sampling rate above 10 MHz, a must for a digital servo to compete with traditionalanalog servo technology with close-loop bandwidth of >10 MHz (laser servo D125 by Vescent).It is worth noting that the absolute delay through the ADC is not necessarily proportionalto the inverse of the sampling rate since multiple clock cycles are often needed to completelyconvert an analog signal into the digital domain. For example, the AD9254 ADC used in DE3prototype has a maximum clock speed of 150 MHz, but its 12 clock cycles of clock delay makesit less favourable than the ADC LTC2195 used in the National Institute of Standards andTechnology (NIST) servo design [14] with a lower clock speed of 125 MHz but also a lowerpipeline delay of 7 cycles. Unfortunately, the number of clock cycles required by each ADC orDAC to complete the conversion is often not part of the search criteria in search engines forADCs and DACs. This makes it rather cumbersome to find suitable ADC and DAC to be used202.4. Conversion Sectionin an FPGA servo.Figure 2.11: The technology landscape of ADCs, provided by Analog DevicesSince the latency through the conversion section is an important characteristic of a digitalservo, a survey is conducted on suitable ADCs and DACs for use in a servo design. Part ofthe survey is shown in Table 2.2, where ADCs and DACs used in three FPGA servo platformsare listed, including a recently published work on high-bandwidth FPGA servo by NIST [14].The minimum conversion latencies in each of the FPGA servos, in the order of the DE3 servoprototype, the DE2 servo prototype and the recently published servo design is respectively 95ns, 108 ns and 70 ns.The use of commercially available ADC and DAC daughtercards compatible with the DE2and the DE3 in designing the FPGA servos greatly reduces the development time. This alsomeans that the selection of ADC and DAC is limited to two daughtercards and their respectiveADC and DAC options. It is worth noting that out of all the ADCs and DACs listed in Table2.2, the ADC/DAC combination that would produce the minimum conversion delay is theADC LTC2193 (NIST paper) and the DAC AD9766 (DE2 platform) with a total delay of 56ns. Reduction of delay in the conversion section can be worthwhile as it lead to an increase ofservo closed-loop bandwidth.The Oversampling EffectA higher clock speed has other advantages, although it may not indicate the the total conversiondelay through an IC. With the appropriate DSP tools, precise control of the timing of a signal212.4. Conversion SectionTable 2.2: Viable ADC and DAC options, their pipeline delay, resolution, etcIC Resolution Type MaxClock(MHz)Latency(clk)TotalPipelineDelay(ns)NoteADC AD9254 14 SAR 150 12 80 DE3 Servo Proto-typeAD9248 14 Pipeline 65 7 108 DE2 PrototypeFinal DesignLTC2195 16 125 7 56 NIST paper [14]DAC DAC5672 14 - 275 4 15 DE3 Servo Proto-typeAD9767 14 - 125 0 0 DE2 PrototypeFinal DesignAD9783 16 - 500 7 14 NIST paper [14]can be traded off for signal resolution and vice versa with the use of oversampling. In analog-to-digital conversion, oversampling and averaging can lead to higher accuracy in the data as longas sufficient amount of white noise is present in the input signal. Similarly, in digital-to-analogconversion, Pulse-Width Modulation (PWM) is the use of a 1-bit DAC (a digital output) withhigh-accuracy timing control to produce a high resolution analog output. Additional readingmay be very helpful on this subject and this reference provides the reasoning on why for every4 times in over-sampling the resolution of the sampled signal can be improved by a factor of 2[18].2.4.2 Single-Ended to Differential ConversionADCs and DACs with high resolution often have differential analog inputs and outputs forbetter noise immunity. Conversion between single-ended signals and differential signals needsto be carefully handled to prevent signal contamination.The differential DAC outputs are relatively straightforward to convert to a single-endedsignal. The key is to make sure that the DAC differential outputs have matched load (25 Ωresistors) to ground. The “+” signal of the differential pair can be used as an single-ended signaland the “−” signal can be disregarded. This is the recommended practice by the manufacturerfor DC-coupling the differential DAC outputs [27].On the other hand, an amplifier with differential output is required to interface with the222.4. Conversion Sectiondifferential inputs of an ADC. The ADC driver AD8137 is used and configured according to theschematics shown in Figure 2.12. The ADC driver is also used as the anti-aliasing filter beforethe ADC to suppress noise components that is higher in frequency than the Nyquist frequency(1/2 of the sampling frequency) of the ADC. The corner frequency of the anti-aliasing filter isdetermined by passive components, C301 and R301, in the feedback path of the ADC driver.They form a low pass filter around 25 MHz. It is to note that the exact Resistor-Capacitor (RC)time constant is often changed to match the Nyquist frequency of the system in the prototypingstage of the servo. Another low-pass filter formed by R305 and C302 at the output of the ADCdriver is also used to suppress noise at high frequency, but the cut-off frequency of this low-passfilter is chosen to be a few times larger than that of the anti-aliasing filter to prevent additionaldecrease in loop bandwidth.270R305270R31356pC30256pC304AGND1K1R3031K1R3141K1R3161K1R3019p1C3019p1C308SIGNAL_OUT+SIGNAL_OUT-VOCMSIGNAL_IN-INVOCM+OUT-OUT+INAD8137AGNDFigure 2.12: Schematics of the ADC driver.2.4.3 LatencyThe latency through the conversion section needs to be carefully optimized for a high loopbandwidth even when ICs with low latency are used. This section describes the techniquesused in identifying the causes of delay and how to eliminate them.Delay can be categorized into propagation delay and pipeline delay. It is helpful to distin-guish between the two, because eliminating each type of delay takes a different strategy.Pipeline delay can be used as an umbrella term for delays that scale with the clock frequency.The ADC, the DAC and the FPGA all have a moderate amount of pipeline delay. It is oftenhelpful to measure the number of clock cycles in the pipeline delay in a system by making232.4. Conversion Sectionlatency measurement at a few different clock frequencies. To ensure that the ADC and theDAC can operate at their rated maximum frequencies, any infrastructure carrying high-speedsignals to and from the ICs also need to be properly rated. This ultimately motivated the useof commercially available FPGA platforms and ADC/DAC daughtercards in the prototypingstage of the servo. In the design of the custom servo daughtercard commissioned by the end ofthis thesis, signals in each 14-bit wide digital bus are carefully length-matched to the respectiveclock and latch signals, with the Altium trace length matching tool.The master clock frequency of the servo also affects the total pipeline delay. One designconstraint is the maximum clock speed of the ADC and the DAC, which are often not the same,as shown in Table 2.2. Clocking the ADC, the FPGA and the DAC at multiples of a masterclock frequency can produce a better result than clocking them all at the maximum frequencyof the slowest IC. For example, the DE3 servo prototype produces a lower delay of 97 ns whenthe ADC and the DAC are each clocked at 150 MHz and 225 MHz than if both ICs are clockedat 150 MHz. A second constraint is the capacity of the Phase-Locked Loop (PLL) in the FPGAbecause a PLL has a defined set of clock multipliers and dividers. In the case of the DE2, 65MHz cannot be derived from a 50 MHz source. This prevents the DE2 servo from achievingthe theoretical minimum conversion delay of 108 ns.The other type of delay, the propagation delay, can be used as an umbrella term for delaysthat do not scale with the clock speed. Both analog signals and, somewhat surprisingly, digitalsignals can produce propagation delay. The typical method to reduce propagation delay is toreduce any unnecessary internal or external signal paths. This applies to coaxial cables, PCBtraces and etc although the propagation speed in each median is different from one another.The delays of a few ns can quickly add up to 10-20 ns even after extensive optimization.2.4.4 BandwidthThe bandwidth of ADC driver dominates the bandwidth of this section as its corner frequencyis deliberately set to be low to act as the anti-aliasing filter. The optimal corner frequencyof this filter changes as the clock frequency of ADC changes, so modification to this cornerfrequency is typically made after the clock frequency of the ADC is fixed.242.4. Conversion Section2.4.5 NoiseCompared to the noise level of < 10 nV/√Hz in the analog front-end section, the conversionsection is noisier at the 100 nV/√Hz level and it is susceptible to noise spikes introduced bypoor grounding practices. In this work, the noise level in the conversion section is measured atthe DAC output with a low frequency spectrum analyser SR780, and the conversion section isconfigured in three different ways to reveal information about the circuit.The first configuration, as shown in the inset of Figure 2.13, establishes the noise level atthe output of the DAC at 32 nV/√Hz by holding the DAC output at a constant value. Thesecond configuration measures the noise floor of the ADC with terminated inputs, by configuringthe FPGA in the “follower” mode (where the DAC relays the ADC data). This measurementreveals that the ADC noise floor is higher than the DAC and that some frequency spikes appearbetween 60 Hz and 10 kHz, as shown in Figure 2.13. The frequency spikes worsens in the finalconfiguration, where the ADC is driven by the ADC driver with a terminated input. Thefrequency spikes can be seen in many of the noise spectrum data throughout this work. Weinvestigated in this issue extensively.Since the amplitude of these frequency spikes observed in the signal conversion section canpotentially make the use of these FPGA undesirable, we thoroughly investigated in the matterand developed a few techniques to eliminate the spikes. First, it is often helpful to improvethe ground connection of the circuit. That means to eliminate ground loops and to reducethe impedance to ground by, for example, connecting the optical table to the power supplychassis. Secondly, we find that the ground setting on the spectrum analyser used to make themeasurement greatly affects the appearance of these spikes. Setting the ground configurationon the spectrum analyser to “floating” typically helps. Finally, the output of loop measurementof a closed-loop controlled quality almost never show these spikes. This observation strengthensour speculation that the spikes are associated with the grounding configuration, as the out-of-loop measurement provides electrical isolation between the servo circuit and the measurementcircuit. Although we often use these techniques to eliminate the frequency spikes, this thesisdid not go into great length to retake all existing data. So some inconsistency in the appearanceof these spike is present in this chapter and Chapter 4.252.4. Conversion Section101 102 103 104 105Frequency [Hz]-150-140-130-120-110-100-90-80Noise Spectral Denisty, Conversion Section, DE2 PrototypeLimited by measure-ment noise floorDAC, midrangeADC, DACADC Driver, ADC, DACDACFPGADACA FPGADACADC FPGAFigure 2.13: Investigation in the noise of signal conversion (ADC/DAC) section of the DE2servo prototype.262.5. Servo Transfer FunctionThis work takes the indirect approach to identify the noise sources in the ADC and theADC driver. The direct approach would be to make Fast Fourier Transform (FFT) analysis ofthe ADC data directly. This can be accomplished either by the FPGA or off-line in a computer.The development of an FFT module in the FPGA can add a useful tool in the FPGA servo.2.5 Servo Transfer FunctionThe overall servo transfer function is characterized with a network analyser. As illustrated thetransfer function in Figure 2.14, the FPGA servo has constant gain at low frequency and ahigh-frequency drop off at 10-20 MHz. The phase response is also constant at low frequenciesand phase response of a constant latency of about 200 ns becomes visible at >100 kHz.Figure 2.14: Servo transfer function.The closed-loop bandwidth of the servo is at the 180 degree phase shift of the servo. Inthe comparison between the FPGA servos and the analog servo in Figure 2.14, the bandwidthof the FPGA servos are significantly lower at 2-3 MHz compared to the 10 MHz of the analogservos. The difference in closed-loop performance is visible when the total latency of the plantand the detector is very small. Despite a slightly reduced bandwidth, the FPGA servo is stilluseful in closed-loop applications that involve Acoustic Optical Modulator (AOM), fast piezosand current modulation of lasers, where the closed-loop bandwidth of the plant is typically<500 kHz.27Chapter 3FPGA Servo FirmwareThe FPGA servo design is motivated by the opportunity to replace an analog servo controllerbased on op-amps with a digital servo that can be controlled and monitored remotely. In orderto replace analog servos already in use in AMO experiments, the digital FPGA servo needs toachieve a similar transfer function and performance as the analog servo. The bandwidth andnoise floor is addressed by the previous chapter on servo hardware. This chapter focuses on theFPGA firmware with the goal of maintaining a good stability and noise level.The servo logic is implemented in the form of a Infinite Impulse Response (IIR) filter similarto what was described in various published work [12], [14]. The work of this thesis is aimed ata demonstration of viability and the exploration of the practical constraints of implementingservo logic in the form of an IIR filter. The issues addressed in this work include the precisionwith which the poles and zeros can be placed, the computation resources needed in an FPGAto implement IIR filters of various precision, and the effects of computation delay. This workalso discusses the details of the verification of an IIR filter.This work also looks into various ways of implementing an Arbitrary Waveform Generator(AWG) as an added feature to the FPGA servo. The FPGA servo hardware can be used asa high-speed waveform generator without needing any circuit modification, with similar datarate (50 MHz - 135 MHz) as the DS345 function generator (30 MHz).The implementation of other useful servo tools such as a lock-in detector input stage, anauto-locking algorithm and a transfer function identification system are discussed at the end ofthis chapter as potential future expansion features to the servo. Besides the proposed featureexpansion, the FPGA servo hardware is a high performance platform and many more featurescan be added without hardware changes.283.1. Overview3.1 OverviewIn realizing the FPGA servo as a toolbox for control applications in AMO experiments, thework produces a number of System on Chip (SOC) solutions applicable to common experimentalapplications. This section covers the design of the SOCs and the organization of the FPGAfirmware. Here with the word “firmware” we refer to all designs that reside in the FPGAincluding both the configurable circuitry and the assembled C program inside the CentralProcessing Unit (CPU) built into the FPGA. This is different from the vocabulary used inwhite pages by FPGA manufacturers such as Altera, where FPGA circuitry is referred to ashardware and the assembled C program is referred to as software. In this work, however, theterm hardware is reserved for the hardware design described in Chapter 2; the term software isreserved for programs on the Personal Computer (PC) which is discussed in Appendix D.This thesis investigates the use of two FPGA platforms, the DE3 and the DE2, in designinglaser servos. The DE3 is a high-performance FPGA and the DE2 is an economic option,both offered by Altera. For both FPGA platforms, this work included SOC designs with thestructure illustrated in Figure 3.1. Each SOC was composed of a CPU in the form of a Nios IIprocessor and several specialized signal processing units like the IIR filter, the Finite ImpulseResponse (FIR) filter and the AWG. The work conducted in this thesis adheres to the principleof modularity so it aims to produce individually testable modules. The advantage of this designis that it produces not only well tested code but also designs that can be rather effortlesslytransferred into other applications. The following sections discuss the design of servo logic inthe form of the IIR filter (Section 3.2), implementation of the FIR filter (Section 3.2.9) and theAWG (Section 3.3) in detail. These modules share a common control interface that includes aclock, an asynchronous reset, a parallel bidirectional data port, an address port for accessinginternal registers and simple read/write signals. This control interface is compatible with notonly the master bus of the Nios II processor controls (the Avalon bus) but also the AXI busof the hardcore ARM processor embedded into the DE1-SOC FPGA among other CPU busstandards.The softcore CPU, implemented as a NIOS II MCU provided by Altera, is tasked withhandling communication to the host computer, interpretation of commands and passing down293.1. OverviewSPI(Slow DAC) AWG(Waveform)IIR(Servo)SerialNios II(master)FIRAvalon BusDACslowDACslow... DACADCPCIIR(Servo)Figure 3.1: The general structure of the SOC design in an FPGA servo. The exact compositionof an SOC design and the interface between the FPGA and the ADC and the DAC (representedin dotted lines) vary on a per platform basis.commands to the specialized signal processing units that interact more closely with the elec-tronic hardware. These messaging tasks are insensitive to delay and can be generated from theAltera toolbox or implemented in C directly. These design tools allow effortless implementationof human readable commands like “set 1 1024” through the serial port and allow the productionof designs that can be easy replicated on another platform like the DE1-SOC. When the CPUand the specialized signal processing units are assembled together to form an SOC, the internaladdresses of all the signal processing units are also combined to form a coherent memory space.The memory layout as seen by the CPU is detailed in Appendix C on a per module basis.We note here that the Quartus 13.1 design suite was used to design the firmware in theDE3 whereas Quartus 13.0 was used for the DE2 firmware design. In the case of the DE2, theassociated FPGA Cyclone II was depreciated in later versions. This also prompted our interestin porting DE2-related development into a more recent platform, the DE1-SOC. This thesistries to make explicit the FPGA used for each study, and it also comments on the compatibilityof the design with other FPGA platforms, especially the DE1-SOC whenever applicable.303.2. IIR Module3.2 IIR ModuleThe servo logic of the FPGA servo is implemented an IIR filter or set of filters. This is because anIIR filter can describe transfer functions of various levels of complexity and has a mathematicalrepresentation that is straightforward to implement in an FPGA. This section covers the useof IIR filters in FPGA servos in detail. It starts with the representation of controller logic inthe IIR format and subsequently covers the computation precision, delay and footprint of anIIR filter.3.2.1 Controller RepresentationPID control is a common form of controller. The PID controller and the variations of a PIDcontroller, such as the Proportional and Derivative (PD) controller and the Proportional andIntegral (PI) controller, cover a large range of applications. Extension of PID into a morecomplex controller such as a Proportional Integral and Integral (PII) controller, a Proportionaland Integral Cubed (PI3) controller or a PI controller with lag-lead compensation is possibleand often offers improvement in control performance. The derivation of PID into its IIR formis covered in detail here, although the FPGA implementation of the servo, an IIR filter, isn’tlimited to the PID alone.The Proportional (P), Integral (I) and Derivative (D) parameters used in various PID tuningprocedures usually refer to one of the three most common PID forms. They are the standardform, the series form or the parallel form [28, p.159-162], with the following expressions.Cstandard(s) = Kp(1 +1Tis+TdsτDs+ 1)(3.1)Cseries(s) = Ks(1 +Iss)(1 +DssγsDss+ 1)(3.2)Cparallel(s) = Kp +Ips+DpsγpDps+ 1(3.3)Here, the letters I and D refers to the integral gain and the derivative gain in the respectivePID form with the subscript “p” for parallel and “s” for series. The letter K represents either313.2. IIR Modulethe overall gain (in the case of the standard PID form and the series PID form) or only thegain for the proportional component (parallel PID). As an alternative expression, integral andderivative components are expressed by their corresponding time scales as the integral (reset)time (Ti) and the derivative time (Td) in the standard form. The PID forms are all secondorder systems each representing two poles, with one of them at s = 0 and two zeros. Thenon-zero pole is omitted in some references for brevity [29], equivalent to setting τD, γs, and γpin equation 3.1, 3.2 and 3.3 to zero (these parameters are technically needed to limit the gainof the transfer functions as frequencies approach infinity). From a practical standpoint, thevariety of PID forms are motivated by their similarity with various underlying implementationstructures. The series form is often associated with an analog PID circuit based on op-amps,where each component implements part of the transfer function and are cascaded in stages toform the PID. The parallel form is often seen in MCU implementation of PID where integral,derivative of error and the error itself are weighted separately and summed at the end of each“for” loop.The PID form most suitable for the IIR implementation in the FPGA servo can be describedby the following relationship.CFPGA(s) = K(s− ωz0)(s− ωz1)(s− ωp0)(s− ωp1)(3.4)Here, the poles and zeros are explicitly stated as ωp0,1 and ωz0,1 . The poles and zeros are labelledsuch that |ωp0 | ≤ |ωp1 | and |ωz0 | ≤ |ωz1 |. This implies that the low frequency pole, ωp0 is ats = 0 and it refers to the integral term. The expressions for ωz0 and ωz1 can be obtained in thelimit when τD, γs, and γp are close to 0, and is given by the following relationships.ωz0,1(standard) =−Ti ±√T 2i − 4TiTd2TiTd(3.5)ωz0,1(series) = −Is,−1Ds(3.6)ωz0,1(parallel) =−Kp ±√K2p −DpIp2Dp(3.7)323.2. IIR ModuleThe assumption of τD, γs, and γp being close to 0 does not affect the shape of the transferfunction in the region s  |ωp1 |. This is because the assumption is equivalent to omitting thehigh frequency pole ωp1 , and in a PID controller, the corner frequency of the poles and zeros aretypically arrange to be 0 = |ωp0 |  |ωz0,1 |  |ωp1 |. In this approximation, the high-frequencypole ωp1 in equation 3.1, 3.2 and 3.3, responsible for limiting controller gain at high frequency,are removed. The value of this high-frequency pole can be directly obtained from equation 3.1,3.2 and 3.3 as the following,ωp1 = −1τDstandard= − 1γsDsseries= − 1γpDpparallel(3.8)resulting in a transfer function gain of the following.K =KpTdτDstandard=Ks(γs + 1)γsseries=Kpγpparallel(3.9)When τD, γs, and γp are zero, the gain take on the value of the following.K = Kpstandard= Ks ·Dsseries= Dpparallel(3.10)In the above expressions, the zeros and poles are explicitly written to have a negative real part,indicating that all the poles and zeros of the PID controller are on the left-hand-side of thes-plane. The collection of poles and zeros in the s-domain can be mapped into the z-domain,with the following relationship.z = esT (3.11)Here, T is the sampling time, inversely related to fs, the sampling frequency. The samplingfrequency is also sometimes referred to as the clock frequency fclk. This relationship is derivedfrom the definition of Laplace transformation and Z-transformation. Reference can be found invarious texts [30], [31]Because the PID controller has 2 poles and 2 zero in the s-domain, its corresponding z-domain representation should also have 2 poles and 2 zeros, in the format of the following333.2. IIR Modulerelationship,CFPGA(z) = K(z − z0)(z − z1)(z − p0)(z − p1) (3.12)This relationship can be expanded like the following,CFPGA(z) = K1− (z0 + z1)z−1 + (z0z1)z−21− (p0 + p1)z−1 + (p0p1)z−2 (3.13)Here, the z-domain poles and zeros are related to the s-domain poles are zeros with the followingrelationships.z0,1 = eωz0,1/fs , p0,1 = eωp0,1/fs (3.14)Here, the s-domain poles and zeros, ωz0,1 and ωp0,1 , have been defined previously in Equations3.5 - 3.8.To convert the z-domain representation of the PID controller in the form of an IIR filter, afinal transformation is needed to cover the z-domain relationship into a discrete-time domainrelationship. The transformation converts z−1 in z-domain to a single clock delay in the discretetime domain. This transform the previous z-domain relationship into the following.Kx[n]−K(z0 + z1)x[n− 1] +K(z0z1)x[n− 2] = y[n]− (p0 + p1)y[n− 1] + (p0p1)y[n− 2] (3.15)Here, x[n] and y[n] are the time domain input and output for CFPGA(z). By introducing theIIR coefficients, we arrive at the typical form of an IIR filter.b0x[n] + b1x[n− 1] + b2x[n− 2] = y[n] + a1y[n− 1] + a2y[n− 2] (3.16)Here, the IIR coefficients, b0, b1, b2, a1 and a2, are defined according to the convention of theDirect Form I (DFI) and the Direct Form II (DFII) as shown in shown in Figure 3.2.343.2. IIR Modulez-1Σz-1z-1z-1b0b1b2-a1-a2Σz-1z-1-a1-a2Σb0b1b2DFI DFIIFigure 3.2: The DFI (left) and DFII (right) representation of a second order IIR.The IIR coefficients has the following relationship to z-domain transfer function.b0 = Kb1 = −K(z0 + z1)b2 = Kz0z1a1 = −(p0 + p1)a2 = p0p1(3.17)The graphical representation of an IIR in DFI shown in Figure 3.2 corresponds to the FPGAimplementation almost exactly. Details of the IIR implementation are discussed in section 3.2.3.Bilinear TransformationIn general, an arbitrary transfer function in the s-domain can be converted into the z-domainby first extracting the gain, poles and zeros as illustrated in Equation 3.4 and then applyingthe transformation relationship between the s-domain and the z-domain described by Equation3.11. Other variations of this transformation exist and the most widely used variation is thebilinear transformation. The bilinear transformation is the first order approximation of the s-to-z transformation described by Equation 3.11. The bilinear transformation has the followingexpression.s =1Tln(z) ≈ 2Tz − 1z + 1(3.18)353.2. IIR ModuleThis expression can be used to perform a “substitution of variable” to convert an s-domaintransfer function into its z-domain equivalent. The approximation has good accuracy when allpoles and zeros in the s-domain are much smaller than the sampling frequency. [32, p.221226].The bilinear transformation has the advantage of being much less computationally intensivethan the exact transformation and is available in both MATLAB’s control system tool box andScipy’s Signal Processing library. Both tools can be helpful for generating and verifying IIRcoefficients.In addition to the exact pole-zero mapping and the bilinear transformation method, otherways of generating IIR coefficients are investigated for the use in a servo system. Section 3.2.9elaborates on the varying degrees of success of this endeavour.3.2.2 First-Order IIR FiltersMany commonly used filters can be realized with a first-order IIR filter. This section describesthe formulation of 4 filters: the pure integrator,the PI filter, the Low Pass (LP) filter and theHigh Pass (HP) filter. The IIR representation of these filters can can be obtained from theirs-domain transfer functions followed by an s-to-z transformation; however, this section providesan alternative interpretation for each filter in an attempt to promote an intuitive understandingof the IIR filters.The pure integrator is a filter that integrates continuously. The following is an IIR filterthat implements a pure integrator.y[n] = b0x[n]− a1y[n− 1] (b0 = 1, a1 = −1) (3.19)Here, the definition of the IIR coefficients is according to Equation 3.16, with the coefficientsb1, b2 and a2 set to 0. Equation 3.19 can be treated as a recursive relationship between theinput and the output of the IIR filter for a more intuitive perspective. By converting therecursive relationship into a direct relationship between the input and the output of the IIR363.2. IIR Modulefilter, Equation 3.19 can be expanded like the following.y[n] = x[n] + y[n− 1]= x[n] + x[n− 1] + y[n− 2]= x[n] + x[n− 1] + x[n− 2] + y[n− 3]· · ·=n∑i=0x[i] (3.20)This leads to the expression of an accumulator, where the output of the filter is the sum of allpast inputs.A PI filter is a variant of the PID controller without the D component. The PI filter is asingle order system because it contains a pole at DC and a zero at a finite frequency. The PIfilter can be implemented in a first-order IIR filter in the following way.y[n] = x[n] + b1x[n− 1] + y[n− 1], − 1 < b1 < 0 (3.21)The PI filter resembles the pure integrator, with the exception of a non-zero b1. A negative b1coefficient places a zero at a finite frequency and it effectively reduces the effect of the integratorat high frequencies.Another example, the LP filter, is a filter that attenuates high frequency components in asignal. The following is a LP filter in its IIR form.y[n] = b0x[n]− a1y[n− 1] (b0 = 1, − 1 < a1 < 0) (3.22)Here, we can see a similarity between this expression and an averaging technique in signalprocessing called the “weighted sum”. By converting the recursive relationship into a directrelationship between the input and the output of the filter, Equation 3.22 can be expanded like373.2. IIR Modulethe following,y[n] = x[n] + αy[n− 1] (α = −a1 ∈ (0, 1) )= x[n] + α(x[n− 1] + αy[n− 2])= x[n] + αx[n− 1] + α2(x[n− 2] + αy[n− 3])· · ·=n∑i=0αix[n− i] (3.23)Here, the components in the sum are exponentially weighted based the amount of time elapsedsince that sample was taken.The final example, the HP pass filter, can also be considered a DC block with finite gainat high frequencies. A HP filter has a zero at DC and a pole at a finite frequency. It has thefollowing IIR relationship.y[n] = b0x[n]− b1x[n− 1]− a1y[n− 1] (b0 = 1, b1 = −1, − 1 < a1 < 0)= x[n]− x[n− 1]− a1y[n− 1] (− 1 < a1 < 0) (3.24)The DC blocking behaviour of the IIR form of an HP filter can be observed from the coefficientsb0 = 1, b1 = −1, where the sum of a static input weighted with the coefficients b0 and b1 is 0.The additional requirement of −1 < a1 < 0 is equivalent to adding a LP filter, which limits thegain at high frequency.3.2.3 Implementation DetailsFractional Resolution RepresentationIn this work, the IIR filter is implemented in the form of Fixed Point (FP) arithmetic due tothe forbidding high cost of floating point arithmetic in FPGAs used in this project. All the IIRcoefficients are implemented as FP numbers with the fractional resolution of R bits. The FP383.2. IIR Modulenumber satisfy the following =Bn2R, R=fractional width (3.25)an = −An2R(3.26)Here the IIR coefficients in capital letter are the FP numbers, and the IIR coefficients in lowerletters are defined Section 3.2.1. The programming interface between the the FPGA servo andthe PC also adopt the FP format. It is important to note the negative sign in Equation 3.26when programming the IIR coefficients. This negative sign is the result of reducing negationoprations in the IIR implementation in the FPGA. Programming the An coefficients with thewrong sign will result in poles being placed on the right-hand-side of the s-domain (oscillatory)rather than the left-hand-side of the s-domain (stable).Since the implementation of arithmetic operation in FPGAs requires explicit declarationof all underlying operations (as opposed to designing within a selection of arithmetic opera-tions that have been previously defined in an MCU), some design pitfalls exist in the FPGAimplementation of an IIR filter. One such mistake is illustrated in Figure 3.3. Here, the IIRcoefficients are 16-bit in width and the width of all operands are explicitly annotated like itwould be in an Hardware Description Language (HDL) description of an IIR filter. At a firstglance, the IIR filter appears to implement 10 fractional bits in all the coefficients correctly.This can be confirmed by tracing the gain through each data path in the IIR filter. What goeshardly noticed in this IIR filter is the loss of computation precision. We can identify this issueby setting B0 = 1, B1 = 0 and A1 = 210 = 1024, which should configure the IIR as a pureintegrator with a very small gain. When the input is set to a small value, 1 for example, theoutput of a pure integrator should produce a shallow ramp, but the implementation shown inFigure 3.3 produces a sustained 0 at the output.The correct implementation, as shown in Figure 3.4 is similar to the previous implemen-tation, but many of the internally stored values in the correct implementation are wider inwidth. The filter does not have the computation issue described above due to the additionalcomputation precision.393.2. IIR ModuleΣB0B1210÷A114 143032 2230Figure 3.3: An incorrect implementation of a first order IIR filter with FP coefficients (B0, B1and A1) with 10-bit fractional resolution. The FPGA implementation is made up of simpleoperations like multiplication (×), addition (∑), division (÷) by the power of 2 implementedas a shift operation, saturation logic ( ) and clock delays ( ). the width of internal path isnoted in grey next to the path. The placement of the ÷210 operation has a large effect on theeffectiveness of the implementation. The difference between the incorrect implementation andthe correct implementation shown in Figure 3.4 is highlighted here in red.ΣB0Σ210B1210÷210÷A114 30 24 144031 41 42 32Figure 3.4: A correct implementation of a first-order IIR filter with FP coefficients (B0, B1 andA1) with 10-bit fractional resolution. The placement of ×210 and ÷210 has a large effect on thewidth of the internally stored values and subsequently the correctness of the IIR implementation.The FPGA implementation is made up of simple operations like multiplication (×), addition(∑), division (÷) by the power of 2 implemented as a shift operation, saturation logic ( ) andclock delays ( ).403.2. IIR ModuleIIR Implementation for Different FPGA ServosIt is worthwhile to summarize the variety of IIR filters commissioned in this work. In broadcategories, as listed in Table 3.1, two IIR filters are commissioned, one for the DE3 FPGAexclusively and the other one for the DE2 FPGA but the latter is not platform dependent. Table3.1 also summarizes other differences between the two implementations. One such difference isthat the DE3 version implements 32-bit coefficients while the DE2 version implements 16-bitcoefficients. We note that the DE2 version is designed to have adjustable coefficient width uponsynthesis of the HDL.Table 3.1: A summary of filters implemented in various FPGA platform in this work. Theformat Qx.y means that the FP representation of the coefficient has x integer bits and yfractional bits. In the case of the Q3.28 format, a total of 32 bits are needed to represent 1 signbit, 3 integer bits and 28 fractional bits. In the case of the Q5.10 format, a total of 16 bits areneeded.Platform Portability Coefficient Format Complexity (Single)IIR DE3 No Q3.28 3IIR DE2 Yes Q5.10 3The flexibility of the DE2 implementation means that little effort is needed to adopt thisimplementation onto a different FPGA like the DE1-SOC, or to change the coefficient widthwith from 16-bit to 32-bit. This portability, combined with compatibility of the daughter-cardwith DE1-SOC (described in Chapter 2) means that the DE2 servo design can be ported toDE1-SOC and most other development education platform by Altera.Integral Anti-WindupIn control systems, integral anti-windup is often implemented to limit the maximum contribu-tion the integral term has to the total control gain. The purpose is to prevent the controllerfrom over compensating as the closed-loop system recovers from an out-of-lock state. In theFPGA servo, integral anti-windup is implemented as a saturator block at the output of thefilter, as shown in Figure 3.4 with the symbol of , that clamps the IIR output to the DACrange. We note that this particular implementation of integral anti-windup has a problem withthe high order of integration as discussed in Section 3.2.8, but is nevertheless chosen due to itsnegligible computation delay and modest resource footprint.413.2. IIR ModuleLess Than Unity Servo GainAdapting an existing IIR filter, as it is shown in Figure 3.4 to implement a gain of 2a, witha < 0 calls for modification of the filter. Changing the input coefficient values to implementa lower gain is not advisable because the coefficients are coupled to the frequency resolution(refer to Section 3.2.5 for the relationship between the coefficients and the frequency resolutionof poles and zeros). Alternatively, implementing the lower gain can be done by dividing theoutput of the IIR filter; however, this must be done with care because an incorrect placement ofthe division can reduce the output range of the IIR filter. A reasonable way to implement logicgain of 1/2 is illustrated in Figure 3.5. In the case of a gain that is less than unity, the internallystored past IIR output needs to be expanded to have more fractional bits to compensate forthe attenuation at the output of the IIR filter.ΣB0Σ210B1210÷211÷A114 30 25 144131 41 42 32Figure 3.5: Implementation of a 1st order IIR with a built-in gain of 1/2. The coefficients areFP with 10-bit fractional resolution. The difference between the gain of 1/2 implementationand the unity gain implementation is highlight in red. The division of 2 is placed at the outputof the filter but the width of the internally stored values are increased to compensate for thepotential loss of the output range.This particular filter implementation is used in the study of the optimal distribution of gainin a closed-loop system in Section 4.1.5. The gain distribution is investigated because of itseffect on noise, and the results of this study are presented in Chapter 4. Our findings show thatincreasing the input gain and reducing the gain through the FPGA logic can improve the noisesuppression capability of the closed-loop system. However, the IIR filter with 16-bit coefficientsis found to have a limited frequency resolution for the placement of poles and zeros.How Higher Order Filters are ImplementedTransfer functions with a higher number of poles and zeros are implemented by adding depthto each IIR or by cascading them as illustrated in Figure 3.6. An IIR filter of high-order can423.2. IIR Moduleimplement a maximum number of zeros or poles that is equal to the depth of the IIR filter. Afew high-order IIR filter when cascaded implement a transfer function in the z-domain like thefollowing.CFPGA(z) =(b0 + b1z−1 + ...+ bn−1z−(n−1) + bnz−n1 + a1z−1 + ...+ an−1z−(n−1) + anz−n)(b′0 + b′1z−1 + ...1 + a′1z−1 + ...)... (3.27)z-1Σz-1z-1z-1z-1z-1b0... ...b1bnbn-1-a1-an-1-anz-1Σz-1b0'b1' -a1'...Figure 3.6: Two methods for expanding the order of IIR, depth-wise (left) and length-wise incascaded form (right)Both methods of implementing multiple poles and zeros have some disadvantages. Whenusing a single high-order IIR filter to implement multiple poles and zeros, the frequency resolu-tion for pole or zero placement diminishes as more poles of a half of or zeros are implemented inthe same IIR filter. In the case of the cascaded configuration the disadvantage is a larger delay.When implementing complex filters such as the PII with lag-lead filter used in Chapter 4, bothtechniques are used. For the PII filter with lag-lead, the 6 poles and 6 zeros in the transferfunction are divided up into two third-order IIR filters with 32-bit coefficients in a cascadedconfiguration. The poles and zeros are distributed in such a way that both IIR configurationsrequire similar amount of computation precision.3.2.4 Verification and SimulationVerification at the basic level is essential for correctly designing a moderately complex system.The importance of verification at the HDL level was often overlooked in this FPGA servoproject and this often leads to detours. Three levels of verification were implemented by theend of the project. The simulation includes testing of individual data paths of an IIR filter, the433.2. IIR Moduleopen-loop simulation of IIR filters and the closed-loop simulation of IIR filters.As the simplest verification method illustrated here, the data path verification of an IIR filteris sufficient to confirm the correctness of an IIR implementation. The open-loop and closed-loop simulation serves more as way to strengthen our understanding of the IIR filter. Morespecifically, the result of an open-loop simulation resembles the transfer function measurementof the FPGA servo made by a network analyzer (as shown in Section 3.2.5). Similarly, theresult of a closed-loop simulation result allows us to predict the closed-loop performance of theFPGA servo (which is evaluated in Chapter 4).Issues encountered in implementing the FPGA servo are investigated with the verificationand simulation tools described in this section. An example of an issue encountered is the lossof computation precision due to the incorrect handling of the Least Significant Bit (LSB)s asillustrated in Figure 3.4 in Section 3.2.3. Another issue is the saturation of signals at the inputor output of an IIR filter, similar to the saturation of the error signal at the ADC describedin Section 4.4. Finally, a set of closed-loop simulations are useful to investigate the maximumlevel of white noise that a closed-loop IIR filter can suppress, a study that is much more time-consuming if done with the FPGA servo hardware.All the HDL simulations are made using the Altera Edition of Modelsim provided in theVersion 13.1 of the Quartus II design suite. The compatibility between the simulation tool andthe Cyclone II FPGA is not affected by the removal of Cyclone II from the list of supporteddevices in Quartus 13.1. The HDL simulation is checked against a separate implementation ofan IIR filter in C++. The rest of the tasks, including signal processing, analysis and plottingof simulation results are made in MATLAB.IIR Data Path VerificationThe verification of all data paths in an IIR filter insures the correctness of the IIR filter. Thetest values, as listed in Table 3.2, cover the most commonly made mistakes in implementing anIIR filter in an HDL. The tests are designed such that if any of the test conditions were to fail,the tester should be able to quickly isolate the problem to a few lines of code.The correct gain and delay in an IIR filter insures that the filter implements the correct trans-fer function. An HDL implementation of an IIR filter is particularly susceptible to unintended443.2. IIR ModuleTable 3.2: Test values for the IIR filter used in the DE2 servo, where FP representation ofthe the IIR coefficients, B0, B1, B2, B3, A1, A2 and A3, all have 10 bits (the relationshipbetween the FP numbers and the IIR coefficients can by found in Equation 3.25 and 3.26). Theimplementation details of a first order IIR filter can be found in Figure 3.4. The input widthand the output width of the IIR filter are both 14-bit.Test Data In B0 B1 B2 B3 A1 A2 A3 Data OutGain, 100 1024 0 0 0 0 0 0 100Signed 0 2048 0 0 0 0 0 200and 0 0 3072 0 0 0 0 300Delay 0 0 0 4096 0 0 0 4001024 0 0 0 1024 0 0 100, 200, 300, ...1024 0 0 0 0 1024 0 100 x 2 cycle,200 x 2 cycles,300 x 2 cycles, ...1024 0 0 0 0 0 1024 100 x 3 cycle,200 x 3 cycles,300 x 3 cycles, ...Bound 4096 16384 0 0 0 0 0 0 8192-16384 0 0 0 0 0 0 -8191LSB 1 1024 -1023 0 0 1024 0 0 0 x 1024 cycles,1 x 1024 cycles, ...Low-pass0↓10016 0 0 0 1008 0 0 Reaching 76 in 64cycles, approach-ing the steadystate of 100latches which can modify the relationship between the IIR coefficients and the frequencies ofpoles and zeros that an IIR filter implements. The gain and delay in an IIR filter can be testedby monitoring the IIR output while activating one IIR coefficient at a time. The forward pathcoefficients, B0, B1, B2 and B3, are assigned different values and the output is expected to beupdated with the gain and the corresponding delay of 1, 2 or3 clock cycles. The feedback pathcoefficients, A1, A2 and A3 are tested by configuring the IIR filter as an integrator, by settingB0 to 2R (R is the fractional resolution of the coefficient in bit) and one of A1, A2 or A3 to apositive value. The outputs of these integrators are expected to be ramps that update at aninterval of 1, 2 or 3 clock cycles that correspond to the data path tested.Testing the IIR filter around bound condition verifies the saturation and truncation logiclocated at the output of the IIR filter, and this prevents overflow or under-utilization of theIIR output. Whenever the bound condition fails the IIR filter can still implement the correct453.2. IIR Moduletransfer function for a sufficiently small input, but a larger input triggers overflow and causesinstability. In the tests for bound conditions, the IIR input is sufficiently large to cause theoutput to clip. The output is expected to clip at the maximum or minimum of the IIR output.Any other clipping behaviours need to be investigated.Careful LSB handling is important for reaching a low noise floor when the IIR filter is usedin a closed-loop system. Unwanted LSB truncation can manifest either as insensitivity to smallfluctuation at the IIR input or inability to accurately address the frequency of a pole or a zero.Both scenarios can be tested by configuring the IIR as an integrator with the lowest frequencyzero that the system can implement and setting the IIR input to 1. If the IIR filter produces avery slow ramp at the output then the LSBs are likely handled correctly. Otherwise, a sustained0 at the IIR output indicates that the LSBs are handled incorrectly.Open-Loop SimulationThe open-loop simulation of the IIR is a set of tests where the HDL implementation of IIR filtersare given an input waveform generated from MATLAB, as opposed to the static test valuesdescribed in the previous section. The most useful test waveform is the sinusoidal waveformwhich can be used to measure the transfer function of the HDL implementation of a IIR filterwhen the period of the sinusoidal wave is varied. The open-loop simulation of the HDL iscompared against an C++ implementation of an IIR filter. As the C++ implementation usesdouble float operands, any mistakes frequently made in HDL with fixed point mathematics insign extension, numerical saturation, numerical rounding can also be detectedClosed-Loop SimulationThe closed-loop simulation of IIR filters is very helpful for a better understanding of the IIRfilter. The simulation is implemented by configuring an IIR filter in a closed loop in the HDLtestbench and allowing a disturbance to be injected into the loop with a waveform generatedfrom MATLAB. Figure 3.7 shows the similarity between the open-loop and closed-loop simu-lation of an IIR filter as they can be configured from the same simulation resources.The test waveform used in the closed-loop simulation is typically a white noise source ratherthan the sinusoidal disturbance used for the open-loop simulation. The use of white noise has463.2. IIR ModuleIIR IIR IIR IIR +export to MATLABimport from MATLABa) b)import from MATLABexport to MATLABexport to MATLABFigure 3.7: Simulation scheme of IIR in a) open-loop and b) closed-loop. Both simulation areimplemented in HDL and in C++ to 1) verify the implementation of the IIR in FPGA and 2)to provide better understand of IIR filtersthe advantage of probing a range of frequencies rather than a single one. The simulation canoptionally export signals at various points of the loop. When the signal is analyzed with FFT,result is equivalent to taking the transfer function of the IIR filter when it is configured inclosed-loop.The method of extracting the transfer function from an IIR filter with the FFT and a whitenoise input is computationally intensive. This is because the resolution of transfer function islimited by the bandwidth of the white noise. This means that to obtain the transfer function ofthe simulated system at low frequency (with high resolution) the IIR filter needs to be simulatedagainst a long duration of white noise. In quantitative terms, probing the frequency response ofthe IIR at 100Hz requires the IIR to be simulated over 10 ms worth of white noise waveform ofthe same duration. That is 200,000 frames of data if the IIR logic is clocked at 50 MHz. Boththe HDL simulation in Modelsim and the C++ implementation can process a similar amountof data in under 15 minutes, although such a simulation in MATLAB would be less practical.To demonstrate the usefulness of the closed-loop simulation, Figure 3.8 shows the effectof loss of computation precision. In this simulation, two cascaded IIR filters are configuredin closed-loop and the noise spectrum at the input of the first IIR filter is computed. It isimportant to note that the amplitude of white noise is evaluated in spectral density with thequantization step at the input of the IIR filter used as the unit. In this simulation, a whitenoise disturbance with spectral density of 140 /√Hz is injected into the loop at the outputof the cascaded filters. As shown in Figure 3.7, the IIR implementation with LSB error haslimited ability to suppress noise at low frequency. In comparison, the IIR performance without473.2. IIR Modulethe LSB error reaches far below the quantization level of the IIR input, giving a maximumnoise suppression of 104 times. It is important to note that a noise suppression of 104 timesis equivalent to 80 dB, a level of suppression that is never achieved with the FPGA hardware(refer to Chapter 4). We speculate that other factors, such as input noise floor, limits theperformance of the real FPGA servo.102 103 104 105 106 107Frequency, Hz10-1100101102103104Noise Suppression Capability of IIR FiltersIIR Implementation (Correct)IIR Implementation (LSB Error)Figure 3.8: The closed-loop simulation with white noise as disturbance. This data shows thespectrum at the input of the closed-loop for two versions of IIR filter: the version of the IIRwith the error in LSB handling (in red) and the correct version (in blue).Another set of simulations demonstrates the versatility of the closed-loop simulation. Asshown in Figure 3.9, this set of simulations reveals the effect of a limited IIR input and outputrange as the amplitude of disturbance increases. This set of simulations is implemented in C++to emulate a single IIR filter with 14-bit wide input and output, configured in closed-loop. Thelevel of noise injected into the loop is varied. It is important to note that amplitude of whitenoise is evaluated in spectral density with the quantization step at the input of the IIR filterused as the unit. For white noise with spectral density of 140 /√Hz the peak-to-peak amplitudeof the error signal becomes larger than the input range of the IIR module (−8191 ∼ 8192 fora input width of 14-bit). This clipping causes the closed-loop system rapidly breaks down andamplifies noise rather than suppressing it. This behaviour is similar to the amplification of noiseobserved in Section 4.1.3 when the gain in the FPGA servo is over-tuned. However, when the483.2. IIR Moduleinput and output range of the IIR filter is extended, the amplification effect lessens. This allowsus to conclude that the amplification of noise observed in Section 4.1.3 and this simulation isdue to clipping at either the IIR input or the IIR output.102 103 104 105 106 107Frequency, Hz101102103104Noise Suppression over a Range of Noise AmplitudeAmp=100Amp=109Amp=118Amp=130Amp=141Amp=154Amp=167Amp=183Amp=200Amp=500Amp=1000Figure 3.9: The effect of noise amplitude on noise suppression. This shows simulation of differentlevel of noise injected until the servo break out of lock.3.2.5 Characterization: Pole and Zero ResolutionIn analog servos, the frequencies of poles and zeros are determined by the set of RC constantsimplemented in the feedback circuit of op-amps. The RC corner frequencies are often carefullyselected to implement poles or zeros with even spacing in logorithmic scale at frequencies suchas 10 Hz, 30 Hz, 100 Hz and etc [33]. The mechanism of enabling the poles or zeros in analogservos is through mechanical switches. In comparison, the FPGA servo can be configured withdifferent frequencies of poles and zeros by simply updating the parameters of the IIR filterinside the FPGA servo. The added flexibility of the FPGA servo is nevertheless constraintby the frequency resolution of poles and zeros that the IIR filter can implement. This sectionexplores the origin of these limitations in a simple first-order IIR filter.493.2. IIR ModuleDerivation of Frequency ResolutionThrough experimenting with an IIR filter, we found that frequencies at which the poles andzeros can be placed in an IIR filter is quantized with a resolution set by the clock speed of the IIRfilter (fclk) and the fractional width of the coefficients (R), like in the following proportionalityrelationship.∆f ∝ fclk2R(3.28)This means that the frequency resolution of the IIR filter scales linearly with the clock frequencyand increases exponentially as the fractional width of the coefficients increases. This intuitivescaling relationship can be derived from the mapping relationship between the s-domain andthe z-domain as shown in Equation 3.11. The scaling factor in Equation 3.28 can be found byfollowing the derivation provided in the following text.In this derivation, ωp0 and ωz0 are used to represent radial frequency of a pole and a zeroin the s-domain, and z0 and p0 are used to represent the z-domain equivalent of the pole andthe zero. According to the mapping relationship between the z-domain and the s-domain asthe following.sT = ln z, T = 1/fclk (3.29)Here, ωp0 and p0 has the following relationship.ωp0T = ln (p0), T = 1/fclk (3.30)Here T is the sampling time and is the inverse of clock frequency fclk of the IIR filter.It is important to note that the value of the pole in radial frequency is different from its valuein ordinary frequency by a factor of 2pi. The radial frequency is the quantity that s-domainpoles or zeros are evaluated in, and the ordinary frequency is the quantity that is typicallyreferred to when describing the periodicity of a waveform in the time domain. Here, fp0 is usedto represent the pole in ordinary frequency (in Hz), and it is related to ωp0 by the following503.2. IIR Modulerelationship.ωp0 = 2pifp0 (3.31)This means that the ordinary frequency of a pole is related to its z-domain equivalent by thefollowing relationship.fp0 =fclk2piln (p0) (3.32)Here, the term ln (p0) can be evaluated by taking the linear approximate of ln as p0 approach1 from below. This approximation is equivalent to implementing a pole or a zero with frequencymuch lower than the clock frequency of the IIR filter (z → 1− is equivalent to s→ 0−). In thetypical usage of a PID controller, the corner frequency of a pole or a zero is lower than 1 MHzwhile the IIR filter is clock between 50 MHz and 75 MHz in this work. This suggests that it isvalid to approximate p0 and z0 as approaching 1 from below.To reflect the hardware implementation in the FPGA, the z-domain pole p0 is written interms of the FP number like the following.p0 =A12R(3.33)Here A1 is an FP number with R fractional bits (refer to Section 3.2.3 for definition of the IIRcoefficients). Using this relationship, the frequency resolution of fp0 can be expanded like thefollowing.∆fp0 =fclk2piln (A12R)− fclk2piln (A1 −∆A12R) (3.34)Here, the smallest change that is allowed in A1 is ∆A1 = 1. By expanding the ln around 1, thefrequency resolution can be found to be the following,∆fp0 =fclk2pi(A12R− A1 −∆A12R), ∆A1 = 1=fclk2pi · 2R (3.35)This concludes that the scaling factor in Equation 3.28 is 2pi. This is confirmed by checking513.2. IIR Modulethe transfer function of various IIR filters in MATLAB. When fclk is to 50 MHz, the frequencyresolution of a single pole or zero that implemented by a first order IIR filter is about 7.1kHz when the coefficients has 10-bit fractional resolution (16-bit coefficients). Details on themeasurement of frequency resolution can be found in the next section. When coefficients with28-bit fractional resolution (32-bit coefficients) are used, the frequency resolution of a pole ora zero can be as low as ∆f = 48 mHz.The same scaling factor does not necessarily hold true for the frequency resolution of a zeroin a first order IIR filter. This is because the z-domain implemented in the FPGA has thefollowing relationship,z0 =B1B0(3.36)as indicated by the definition of the IIR coefficients in Section 3.2.3. When the B0 coefficientis fixed at B0 = 2R (the FP equivalent of b0 = 1), the frequency resolution of the zero has thesame relationship as the frequency resolution of a pole as shown by the following relationship,∆fp0 =fclk2pi · 2R , B0 = 2R (3.37)However, when B0 is not fixed at 2R, the frequency resolution of the zero is < fclk/2pi · 2R forB0 > 2R and > fclk/2pi · 2R for B0 < 2R.In a more general case, an IIR filter of higher order can implement multiple poles and zeros.It is possible to show that the resolution of the pole placement in a multi-order IIR filter,depends on the value of all the other poles implemented in the same IIR filter, by factoringand reducing Equation 3.27 in Section 3.2.3. In summary, it is important to keep in mind thatthe resolution of a pole in an IIR filter that implement multiple poles is always worse than if asingle pole is implemented (for further reading, please see [34, p.383]).When working with IIR filter of higher order, it is important to note that small adjust topoles and zeros in z-domain can lead to dramatic change in the transfer function. In somecases, the phase response of the transfer function can be modified by as much as 180 degree,which can cause instability in a closed-loop system. While IIR filter with high computationprecision can implement a more complex transfer function without introducing instability, for523.2. IIR Moduleany IIR filter with finite fractional resolution, this problem can occur if the transfer functionbecomes too complex. As a solution to this issue, this work develops a MATLAB routine (referto Appendix D) that compares the s-domain transfer function and the closest transfer functionthat the hardware can implement in both amplitude and phase. Ultimately, it is up to the userto make sure that the phase response of the s-domain transfer function is not compromisedwhen converted to a hardware implementation.Measurement of Frequency ResolutionThe frequency resolution of poles and zeros in an IIR filter can be characterized as a series oftransfer function with small variation in the IIR coefficients. A network analyzer like the SR780can be used to take the transfer function. The network analyzer generates a chirp signal andwhen it is used as the input to the FPGA servo, the cross correlation (computed by the SR780)between the output of the FPGA servo and the chirp signal gives the transfer function.A typical result of this measurement is shown in Figure 3.10. Here, the IIR filter is configuredas a PI filter with a fixed corner frequency and is tested against chirp signals of differentamplitudes. In all of the measurements, the transfer function agrees with the ideal transferfunction of a PI (in the dotted line) at intermediate frequencies, between 10 kHz to 1 MHz(only the regions between 10 kHz and 100 kHz is shown). At low frequencies, the amplituderesponse of the measured transfer function saturates, while the phase response does somethingcompletely unrecognizable. The non-ideal behaviour of the PI filter at low frequencies is notvisible in its z-domain transfer function where the input and the output signals are unlimited inamplitude. As it can be observed in Figure 3.10, the transfer function measurement approachesthe ideal PI transfer function, as the input amplitude is lowered and the IIR output saturatesaround 200 mV regardless of the input amplitude. This suggests that the non-ideal behaviouris rather caused by saturation at the output of either the IIR filter or the FPGA servo. Thissaturation voltage may differ in other testing scenarios if any DC component is present in thechirp signal or if the gain and the offset circuit is part of the measurement.Figure 3.11 shows the lowest 3 non-zero zeros implementable by a first order IIR withcoefficients with 10 fractional bits. The coefficients are programmed as B0 = 1024 and A1 =1024 for all three filter, and B1 = −1021, B1 = −1022 and B1 = −1023 respectively for each533.2. IIR Module01020304050Magnitude, dBMeasurement of PI Filter Transfer Functions Implemented in the FPGA servofPI=25 kHz, Vpk=20 mVfPI=25 kHz, Vpk=60 mVfPI=25 kHz, Vpk=100 mVfPI=25 kHz, ideal102 103 104 105Frequency, Hz90135180Phase, degreeFigure 3.10: Transfer function measurement (with SR780) of a PI filter with chirp input ofdifferent amplitude. The measured transfer function approach the ideal shape as the chirp signalbecomes smaller in amplitude. This suggests that the non-ideal behaviour of the implementedPI transfer function is due to clipping at the output of the IIR filter or the FPGA servo.filter. The corner frequencies of these PI filters are, 22 kHz, 14 kHz and 7.1 kHz, indicatinga frequency resolution of roughly 7.1 kHz. When compared against an IIR filter with highfracitonal resolution, a higher resolution of zero can be found.An alternative method for measuring the frequency resolution of a single pole or zero is toset the IIR filter to the lowest pole or zero that is allowed by the IIR filter and use a functiongenerator to scan over a small frequency range until the 3 dB (corner) frequency is found. Thismethod do not verify the shape of the transfer function everywhere else in the frequency range,but is an extremely fast sanity check for a first order IIR filter, and it should be used with careon a higher order IIR filter.3.2.6 Characterization: Resource AllocationThe computation footprint of IIR filters is an important consideration in selecting the rightFPGA in an FPGA servo design. Before investigating this issue, we would like to identify thecomputation resources in an FPGA. The simplest type of configurable logic unit in an FPGAis the LE (by Altera convention) or Look-up Table (LUT) (by Xilinx convention). Although543.2. IIR Module-50510152025Magnitude, dBFrequency Resolution of a Zero in a PI filter, Clock Frequency = 50 MHzB0=1024, B1=-1023B0=1024, B1=-1022B0=1024, B1=-10213 dB102 103 104 105Frequency, Hz90135180Phase, degreeFigure 3.11: Transfer function measurement that demonstrates the frequency resolution of azero in a PI filter, where coefficients has 10 bit fractional resolution. The coefficients are setto B0 = 1024, A1 = 1024 and B1 = −1021, B1 = −1022 and B1 = −1023 for each filter. Thecorner frequency of the PI filters can be found as the 3 dB frequency (intersection with thedashed line) and are respectively 22 kHz, 14 kHz and 7.1 kHz.LEs can be configured to form any kind of logical devices, arithmetic operations are bestimplemented with the FPGAs DSP resources. The DSP based computation resources in thetwo FPGAs used in this thesis, the high-performance Stratix III in DE3 and the economicCyclone II in DE2, are different in complexity, as illustrated by the comparison in Figure 3.12.CLRND QENAData AData Baclrclockenasigna (1)signb (1)CLRND QENACLRND QENAData OutEmbedded Multiplier BlockOutputRegisterInputRegister++144 44InputDataInput Register BankPipeline Register BankAdder/AccumulatorOutput Register BankHalf-DSP BlockResultFigure 3.12: Comparison between DE2 (left) and DE3 (right) computation resourcesThe DSP resources in an Cyclone II FPGA are simple multipliers with optional input and outputlatches as illustrated in Figure 3.12 (left). In comparison, the DSP resources in an Stratix III553.2. IIR ModuleFPGA are DSP engines which contain multipliers followed by two stages of accumulators,with the first accumulator responsible for summing the output of multipliers and the secondaccumulator responsible for summing of output several DSP engines, as illustrated in Figure3.12 (right). It is important to note that the HDL synthesizer shipped in Quartus 13.1 does notprovide full support to all necessary features of the DSP engines in the Stratix III FPGA, whichnecessitates declaration of the DSP explicitly. Although using specific accumulator features inthe DSPs helps to lower the computation delay in the IIR filter, reference to the DSP featuresreduces the portability of this HDL implementation. Thus, specific references to DSP structuresare avoided unless necessary.In order to accurately assess the computation footprint of IIR filters in FPGAs, we use18-bit by 18-bit multipliers as the unit of the assessment. Among the IIR filters implementedin this work (Table 3.1), the most suitable IIR implementaion for this study is the filter usedin the DE2 servo because it can be easily configured to implement a variety of coefficient widthand various IIR depth. This study also assumes that the accumulators absent in the Cyclone IIFPGA are to be constructed out of LEs. Table 3.3 shows that the number of 18×18 multipliersneeded to implement IIR filters of various coefficient widths and depths.Table 3.3: A summary of the computation footprint of various IIR filters with different depthand coefficient widths, quantified by the number of 18 × 18 multipliers.16 bit coeff., with 10 bit 32 bit coeff., with 20-28fractional resolution bit fractional resolution(18×18 multipliers) (18×18 multipliers)1st order IIR 4 82nd order IIR 7 133rd order IIR 10 18With the computation footprint of IIR filters in Table 3.3 and the computation resourcesin FPGAs in Table 3.4, it is possible to devise a strategy on distributing DSP resources in anFPGA servo. For example, the IIR filter needed to implement the PII + lag-lead control isin the form of 2 third-order IIR filters in cascaded configuration both with 32-bit coefficients.The computation footprint of this IIR filter is 36 multipliers per channel, an impossibility forthe DE2 FPGA (with 35 multipliers in total), but is manageable for both the DE3 FPGA (384multipliers) and the DE1-SOC FPGA (174 multipliers).563.2. IIR ModuleTable 3.4: Comparison of computation resources in various FPGA platformsDE3 DE2 DE1-SOC18×18 Multiplier 384 35 174Since the DE2 FPGA is limited in computation resources, a reasonable way of distributingthe DSP resources is to implement in each channel 2 first-order IIR filters in a cascaded config-uration. One of the IIR filters can be configured with 16-bit coefficients and other with 32-bitcoefficients to allow implementation of PII with one high frequency zero and one low frequencyzero. Many variations exist, but they all have to work within the resources available in theDE2 FPGA. The ultimate solution is to port existing DE2 implementation to the DE1-SOCto allow a more complex filter.3.2.7 Comments on Computation DelayThe computation delay through the IIR logic can be combined with the delay through the analogfrontend and the ADC/DAC described in Chapter 2 to compute the total latency through theFPGA servo (typically around 200 ns in total). This computation delay is not absolute asa lower computation delay can often be achieved by additional computation resources andadditional development time. In an effort to minimize the computational delay, the IIR filtercommissioned in this project is optimized to have a delay of 1 cycle at either the maximumfrequency allowed for the ADC and the DAC or at twice of this frequency. For example, asingle DE2 IIR filter with 16-bit coefficients has 1 cycle of delay at fclk = 130 MHz while theADC and the DAC are clocked at 65 MHz. The fclk for the DE3 32-bit coefficients IIR is lowerand various versions of the design are clocked with a single cycle of delay at either 50 MHz or75 MHz although more optimization would allow an additional increase in the clock frequency.As the result of this optimization, the computation delay is similar or less than the ADC/DACdelay, even when up to 3 IIR filters are cascaded to realize a more complex filter.The main tool used in reducing the IIR computation delay is Altera’s TimeQuest timinganalyser. The timing analyzer helps by identifying the limiting factor in computation delay andproviding clues to reduce the total delay. Another look at the IIR implementation illustratedin Figure 3.4 in Section 3.2.3 should reveal that the forward paths (the signal paths between573.2. IIR Modulethe IIR input and the IIR output) and the feedback paths (the signal paths between the pastIIR output and the current IIR output) has different computation complexity. The feedbackpaths have a larger computation load because the scaling factors for the feedback paths, A1, forexample, need to multiple against internally stored values that are wider. This is why it is oftenthe feedback path that has trouble satisfying the timing constraint. As a concrete example, thetotal timing budget for one IIR filter in the DE2 implementation is 7.7 ns. This is assumingthe IIR filter is clocked at 130 MHz. Each feedback path (An) is composed of two 18-bit by18-bit multiplications that takes 3.5 ns (specification is obtained from [35, 5-21]), while workingin parallel. An additional summation step must follow the two 18-bit by 18-bit multiplicationoperation, and this summation step is not present in the case of the forward paths (Bn).A few optimization techniques were found to be helpful. In one case, the FPGA synthesisplanner is allowed to place redundant buffers for a few internally stored values which allowthe synthesis planner more freedom in placing the slowest signal paths, and eventually leads toreduction in delay. In another instance, the design of three cascaded IIRs are allowed 4 totalclock delays, with the additional clock cycle designated to allow the signals to travel from theIIR output to the FPGA pins. Having an additional delay allows the maximum frequency ofthis block (derived from the same master clock as that derived for the ADC and DAC driver)to be higher than if the IIR filters were designed to have 3 clock delay (each IIR filter takesup one clock delay). This allowed the servo logic to be clocked at twice of the clock frequencyfor the ADC and the DAC rather than at the same frequency, so as a result the total delayis reduced by 1/3. Admittedly, these examples of reducing the computation delay may not befeasible in all optimization scenarios. Many optimization strategies are discussed in text onreducing delays in FPGA design [36].3.2.8 Comments on PIIThis section comments on some observations made during the use of a PII filter. Some of theseobservations, regarding the offset at the output of the PII filter specifically, is inherent to thePII filter and should be present regardless of the underlying implementation (whether is digitalor analog). The observations regarding the strange saturation behaviour of the PII is specific tothe implementation of the IIR filter by this work and is not present in an analog implementation583.2. IIR Moduleor likely IIR filters with a different saturation logic.PII OffsetThe IIR filter produces an offset on its output when configured as an integrator. This offsetcan be observed at the output of a single PI filter as illustrated in Figure 3.13 . Similarly, whentwo PI filters are cascaded together to form an PII filter, a ramp appears on its output as it isalso evident in Figure 3.13. The offset and the ramp at the output of the IIR filters may seemcounter intuitive as the input sinusoid contains no offset. However, this behaviour is expectedfrom the integral of a sinusoid over a finite interval. The first order integration of a sine wavehas a DC offset dependent on phase of the input. The second order integration subsequentlyintegrates this offset and produces a ramp with a slope that is dependent on the phase of theinput sine wave. The simulation shown in Figure 3.13 produces this behaviour after it was firstdiscovered with the FPGA servo hardware. The details of the simulation method are discussedin Section 2000 3000 4000 5000 6000 7000 8000 9000 10000Clock010002000300040005000600070008000Digital CodeOpen-Loop Simulation of a PI Filter and a PII Filter in Cascade FormIIR InputPI OutputPII OutputFigure 3.13: The open-loop simulation of the PI filter and the PII filter in cascaded form,showing the offset at the output of the PI filter and the ramp at the output of the PII filterin cascade. As it can be observed in this figure, the input to the filter is a sine wave with nooffset.The ramp at the output of the PII causes the IIR output to quickly “rail to either the min-593.2. IIR Moduleimum or the maximum of the IIR output. This behaviour complicates the open-loop measure-ment of the transfer function of the PII. In contrast to the inconvenient open-loop behaviour,when the PII is used in closed-loop this ramp is suppressed by the servo logic and does notaffect the closed-loop performance of the servo.An Unusual Saturation Behaviour of the PII FilterThe IIR filter commissioned by this work (as illustrated in Figure 3.4 in Section 3.2.3) has anedge case where instability exists. The instability occurs when a single IIR filter implementsa PII filter in the form of a second-order IIR filter. The instability occurs when the outputof the IIR filter saturates but the filter fails to hold the output in saturation as illustrated inFigure 3.14 starting roughly at 6.6 · 104 clock in the simulation. The spectral measurement ofthe output the filter may appear normal if the instability does not frequently occur. However,this is a serious problem in a closed-loop system because when the plant drifts further awaythan the range of the actuator the servo would fail to hold the actuator at its limit and result inlosing the lock. As this instability does not occur when a single IIR filter implements more thanone non-zero pole/zero (as opposed to the PII containing 2 poles at s = 0), this work resortsto avoiding the instability by limiting each IIR to implement a single order of integration andadd IIR in cascade if needed.To examine the cause of this instability, the exact instability scenario is emulated in sim-ulation, which then provides the values of internal registers at the moment when instabilityoccurs, as shown in the inset of Figure 3.14. The simulation reveals that the problem occursat the moment when the saturation logic is activated. Activating the simple saturation logic isequivalent to introducing an impulse at the IIR output, with a sufficient amplitude to preventthe IIR output from overflowing. The record of this impulse, remains in the IIR filter andmanifests itself as a ramp at the IIR output over time.A better saturation logic is to modify the internal states of the IIR filter in a coherentmanner to avoid introducing this impulse. One way is to scale all the internal states by thesame amount that the IIR output is changed by. This is equivalent to modifying internal statesof the IIR filter as if all past inputs were smaller in amplitude. We were able to simulate thisimplementation in C++ and to confirm that this saturation logic fixes the unusual saturation603.2. IIR Module0 1 2 3 4 5 6 7 8 9 10Clock 104-8000-6000-4000-200002000400060008000Digital CodeDFI Instability When Implementing PIIIIR Input, x[n]IIR Output, y[n]IIR Output, y[n-1]IIR Output, y[n-2]Saturation Logic AcitivatedFigure 3.14: The open-loop simulation of a second-order IIR filter configured as a PII filter. ThePII in this configuration fails to saturate at its boundary, as opposed to its expected behaviourin Figure 3.13 with a PII filter in cascaded form. Instabilities occur at the clock frame 6.6 · 104(shown in the inset), 8.0 · 104, 8.8 · 104 and 9.5 · 104.behaviour for a PII filter or a PI3 filter when implemented in a single IIR filter.3.2.9 More on Filter DesignIIR and FIR are two broad classes of digital filters that can be designed with many differentstrategies. Two such strategies of designing an IIR filter are described in Section 3.2.1 includingthe use of an exact s-domain to z-domain transformation and the use of a bilinear approximation.This section describes two other methods of designing filter, and it also comments on whetherthese alternatives are suitable for use in a closed-loop system.Higher Order of Approximation for an IntegratorIn Section 3.2.1, the controller is designed in the s-domain, transformed into the z-domain andthen converted into the time domain to produce the IIR coefficients. Another method, lesscommonly used, is to design the controller directly in the time domain. This method is basedon transforming the differential equation that describes the relationship between the filter inputand the filter output into a difference equation that can be directly implemented with an IIR613.2. IIR Moduleor an FIR filter. For example, a pure integrator controller can be described by the followingexpression where x(t) is the input and y(t) is the output.y(t) =∫ t00x(t)dt (3.38)This continuous-time relationship can be converted into a discrete-time relationship using var-ious numerical integration methods including the rectangular integration rule, the trapezoidalintegration rule, or other rules (see, for example, ch.6 of ref [37]). The continuous-time expres-sion evaluated to the lowest order using the rectangular integration rule yields the followingdifference relationship,y[n] = Tx[n] + y[n− 1] (3.39)where T is the sampling period of the discrete-time system. Similarly, the next higher orderapproximation using the trapezoidal integration rule results in the following equation.y[n] = T(x[n] + x[n− 1]2)+ y[n− 1] (3.40)It is worth noting that this method yields the same result as the s-domain equivalent of thedifferential equation followed by a transformation into the z-domain using the bilinear approx-imation (refer to Section 3.2.1).Like the rectangular integration rule, the trapezoidal integration rule has a residual errorwhen used to integrate smooth functions. The residual error can be reduced with a second orderapproximation of integration, called the Simpson’s Integration rule. By following this rule, thedifferential relationship in Equation 3.38 can be transformed into the following relationship.y[n] = T(x[n] + 4x[n− 1] + x[n− 2]3)+ 0 · y[n− 1] + y[n− 2] (3.41)In preliminary tests of the FPGA servo, this Simpsons Integration rule relationship was com-bined with a zero around 70 kHz to form a PI filter and was used to form closed-loop lock withthe FPGA servo hardware. The servo system was able to lock with this PI filter but exhibitedno obvious advantage over the trapezoidal integration rule. Rather, compared to the PI filter623.2. IIR Modulethat follows the trapezoidal integration rule, a PI filter that follows the Simpson’s integrationrule increases the loop delay by one clock cycle and takes up more computation resources.To conclude, this study is meant to illustrate that transforming a continuous-time rela-tionship into a discrete-time relationship by converting the integral or differential equation(Equation 3.38) into difference equations (Equation 3.39, 3.40 and 3.41) is a valid method ofproducing IIR coefficients for use in the servo logic. This study also shows that a closed-loopcontrol system is rather forgiving with integration error and that reducing the integration errordoes not seem to result in a significantly better closed-loop performance. The later observationis reminiscent of the observation made in Section 3.2.8 where the PII offset error does not havea detrimental effect on the closed-loop control performance.IIR vs FIR in Implementing a Phase CompensatorTo reduce the impact of the loop resonance in a closed-loop system, the use of a lag-lead filteris investigated in detail in Section 4.2.6. Before arriving at the decision to use the lag-leadfilter, the work also considered other types of digital filters to form a bandstop filter to be usedalong with a PII filter to cancel the loop resonances. Two other types of bandpass filters areconsidered. They are an elliptic bandstop filter that has an equivalent form as an IIR filter andan FIR bandpass filter designed via the windowing methods. To keep the comparison fair, allthe bandstop filters are designed with a centre frequency of 0.1 fclk where the fclk is the clockfrequency of the filter. Their frequency domain response (transfer function) is shown in Figure3.15 along side with the lag-lead filter, which is designed via the bilinear transformation.One filter candidate is a second order elliptic bandstop filter with a target stop-band between0.05fclk − 0.2fclk. The filter is computationally equivalent to a fourth order IIR filter. Oneunacceptable feature of the elliptic filter is the sign change at each node of the filter, as shownin Figure 3.15 at approximately 0.07fclk and 0.14fclk. This means that the filter has differentsigns in frequencies between 0.07fclk − 0.14fclk than all other frequencies, making it impossibleto avoid positive feedback for all frequency. This positive feedback is undesired for closed-loopsystems as it often leads to instability.The other candidate is a 30th order FIR bandstop filter with a target stop band between0.05fclk − 0.2fclk. Although the computation complexity of FIR filter is not directly compa-633.2. IIR Module0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20-10010Magnitude (dB)IIR vs FIRIIR-BilinearIIR-EllipticFIR0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Normalized Frequency (x  rad/sample)-1000100Phase (degree)Figure 3.15: Comparison of three different digital filters all implementing a notch filter withcenter frequency at 0.1fclk. Only the bandstop filter designed with the bilinear method (lag-lead) is suitable for used in closed-loop, because the elliptic bandstop filter changes sign at 0.7fclk and 0.14 fclk and the FIR bandstop filter has excessive delay.rable with an IIR filter, the comparison can be made by assessing the amount of computationresources used by the two filters. In this way, a 30th order FIR filter in this study is found touse a similar number of 18-bit by 18-bit multipliers as a 9th order IIR filter. Besides the largecomputation footprint, the FIR bandstop filter also has a large delay that scales with the orderthe of the filter (the order is 30 in this case). Despite these disadvantages, the FIR filter can,nevertheless, be used in a closed-loop controller and should be considered if a better alternativeis not available.As the remaining candidate, the IIR filter designed via the bilinear method is composed oftwo poles, at 1 MHz and 8 MHz and two zeros, at 2 MHz and 4 MHz and converted to z-domainwith a clock frequency of fclk = 50 MHz. Although the IIR filter obtained via the bilinearmethod has a wide attenuation band and attenuates much less within the band, as shownin Figure 3.15, it has a stable phase response and uses a reasonable amount of computationresources as only a second order IIR filter. As a result of this comparison, the lag-lead filterdesigned with the bilinear method was chosen, and it is used as the compensator to reduce loopresonances. A detailed discussion of its closed loop performance is provided in Section Arbitrary Waveform Generator3.3 Arbitrary Waveform GeneratorWaveform generation is a ubiquitous and versatile tool in an AMO laboratory. The need forwaveform generation ranges from dithering laser frequencies to modulating laser intensities.It is convenient feature for a laser servo to combine the function of stabilizing the laser withwaveform generation and this can be easily implemented in an FPGA servo. Additionally, thewaveform generation capability of an AWG can be used to implement new features, such as lock-in detection and system identification. This section describes the design of an AWG producedby this work, how the AWG can be program, its residual error, and other characteristics of themodule.3.3.1 ImplementationWith flexibility and speed as the main design requirement, the waveform generator is imple-mented as a fourth order polynomial with programmable coefficients as illustrated in Figure3.16. The timescale of the polynomial is controlled by a ramp generator (left module). Theshape of the waveform can be controlled by the coefficients to the fourth order polynomial(right). All the ramp parameters and the polynomial coefficients can be controlled from a PCvia USB. A soft-core MCU in the FPGA receives the parameters through the serial link andthen transfers the parameters to the AWG. The address where the parameters can be accessedis provided in Appendix C.maxminincprescaler( )clkclkrsttrigrampy=a0+a1x+a2x2+a3x3+a4x4out(31:16)Figure 3.16: A block diagram of the arbitrary waveform generator, implemented as a counterfollowed by a 4th order polynomial. The counter produces a 32-bit triangular waveform and canbe controlled through internal registers: “max”, “min”, “inc” and “prescaler”. The triangularwave at the output of the first module has a range between “max” and “min” control and aslope of fclk ·(inc/prescaler). The polynomial coefficients are implemented as 16-bit FP numberswith 10 fractional bits. Signal responsible for external trigger are “rst” and “trig”.Synchronous control of the AWG is accomplished with an external trigger signal. Thisallows the waveform generator to operate in synchronization with the rest of the experiment.653.3. Arbitrary Waveform Generator3.3.2 Coefficients, Residual Error and VerificationA simple configuration of the AWG is an triangular wave generator, where the coefficients areprogrammed as a1 = 1 and an = 0. The slope and the amplitude of the ramp is controlled by thecounter parameters, like “ramp min”, “ramp max”, “increment” and “prescaler”. Configurationof an arbitrary waveforms is accomplished by adjusting the AWG coefficients A0, A1, A2, A3and A4. They are the FP representation of the coefficients of a fourth polynomial and aredefined like the following.An = an · 2R, R=fraction resolution=10 (3.42)The coefficients can be found by a least square fit to fourth order polynomial. The samplecoefficients for implementing sinusoidal or Gaussian waveform are listed in Table 3.5. Becausethe underlying implementation in the AWG is in FP arithmetic, the coefficients here are alsoin the format of FP number with 10-bit fraction resolution.Table 3.5: The best fit parameters to implement a sine or a Gaussian waveform. The AWGis implemented as 4th order fixed point polynomial. The parameters related to the ramp(“min”, “max” and “increment”) are 32-bit FP numbers with 16-bit fractional resolution. Theparameters for the polynomial, A0, A1, A2, A3 and A4, are 16-bit FP numbers with 10-bitfractional resolutionRamp Ramp Pre-Min Max Increment scaler A0 A1 A2 A3 A4Gaussian 0 0x800000 0x10000 1 13 899 −1522 1825 −372Sine 0 0x4000000 0x10000 1 4096 1000 −27415 18277 0A small but significant residual error remains when fitting the target waveform to a polyno-mial, as it is shown in Figure 3.17 for both the sine wave and the Gaussian wave. When a fourthorder polynomial is used, the residual error in fitting to a sine or a Gaussian waveform is about2% of the total amplitude of the waveform. Although increasing the order of the polynomialdecreases the residual error, the cost of computation resources increases rapidly as the benefitof a smaller residual error diminishes.Another potential issue is that the residual error is not smooth at the boundary of thepolynomial. This can be observed at the 0th, 500th, 1000th clock frame in Figure 3.17. This isbecause the least square method is used for fitting the waveform to a polynomial. If a fitting663.3. Arbitrary Waveform Generator00.51TrigArbritrary Waveform Generator, Signal I/O0500Ramp00.51Gaussian-0.0200.02Error-500 0 500 1000 1500 2000 2500Clock012Sine-0.0200.02Error(Fractional)(Fractional)Figure 3.17: The sine and Gaussian waveform output of the AWG, with their respective residualerror. The AWG has two trigger mode, a single trigger modes (in black) and a continuous-triggermode (in grey).method is based on the Laguerre polynomials with smooth boundary conditions, the AWGoutput would not exhibit this behaviour.The AWG implemented in this work has a verification scheme, where the HDL descriptionof the AWG is compared against another description of the same algorithm programmed inMATLAB. The MATLAB description of the AWG anticipates the computation precision of theHDL implementation and no discrepancy is expected from the two sets of implementation. Theverification scheme is in the spirit of modular testing already described in previous sections andit is meant to produce self-documenting and reusable code.3.3.3 Alternative DesignsAn AWG with an underlying polynomial implementation has the advantage of needing very littlebandwidth to program since the waveform is generated within the FPGA. Another approach isto use the FPGA as a memory device. This implies generating the waveform on a PC and thenuploading it into the FPGA. This work explored this approach and comments are providedbelow on what was found.The very first iteration of the waveform generator simply stored the waveform in the on-chip673.4. Proposal on Feature Expansionmemory bits in an FPGA in the form of Read Only Memory (ROM) and used a counter tostep through the data (The syntax of doing this in Verilog can be found at this reference [38,p.295]). This design is incredibly easy to make, but the waveform is read only. Changing thewaveform requires access to the FPGA design program and this creates a barrier to update thewaveform for other experimenter in the lab.Another possible implementation of an AWG is to store the waveform in random accessmemory of the FPGA and to program it from a PC through a softcore MCU. This immediatelyturns out to be a bad idea on the DE2 FPGA platform, due the lack of a fast communicationoption between the FPGA and the PC. It is important to keep in mind that the AWG consumes14-bit data at 50 MHz. The constraint of slow communication interface between PC and theFPGA platform is lifted on newer FPGA platforms and should allow the implementation of amemory-based AWG.3.3.4 Future ImprovementsIn general, implementing an AWG in the form of polynomial function has the advantage ofbeing quick to re-configure. However, as the complexity of the waveform increases additionalcomputation complexity is needed. Implementing a polynomial function with higher complexityis exponentially more work as the complexity increases. In the case when truly arbitrary wave-form with lots of discontinuities is needed, the memory-based AWG implementation describedin Section 3.3.3, may become more favourable.3.4 Proposal on Feature ExpansionThe FPGA servo designed by this work has the potential to become a versatile, control toolboxwith wide adoption in AMO experiments. So far, this work has explored the implementation oftwo of these tools, the IIR filter and the AWG. More features can be added to the FPGA servoover time, and this section is meant to discuss potential implementations for some of these newfeatures, including lock-in detection, auto-lock detection and plant detection. A few of thesefeatures have already been demonstrated in published work by NIST [14], and while this canserve as reference design it may not be easily transferable to an Altera platform.683.4. Proposal on Feature Expansion3.4.1 Lock-in DetectionThe lock-in technique is a detection technique for weak signals that is widely used in AMOexperiments. Some example applications are the PDH technique [39] and the use of lock-indetection in saturated absorption spectroscopy [33]. The theory underlying the operation oflock-in amplifiers is discussed in various texts [40]. In essence, a lock-in amplifier is a modulationand demodulation technique that is based on the orthogonality principles of sine waves. Theoutcome of this technique is a very sharp notch filter at the modulation/demodulation frequencyand this helps to recover signal from a high level of background noise. The implementation ofa lock-in amplifier is illustrated in Figure 3.18. In this design, both the in-phase and the 90degree out-of-phase component is recovered from the lock-in input. Some comments on thistype of digital lock-in implementation can be found at a white paper by Zurich tech [41]. Somelock-in implementation does not include the 90 degree out-of-phase component, but we suspectthat those types of implementation are suitable for modulation frequency that are low enoughthat the signal latency through the plant is not sufficient to cause a significant phase shift.IIRADC DACsincosDemodulation (Lock-in)ServoModulationxyFigure 3.18: An implementation proposal of lock-in amplifier in the FPGA servo. The servologic is divided in to demodulation, servo and modulation (what is not shown here is the rest ofthe servo and the laser configured in closed-loop. Both in-phase component (x) and 90 degreeout-of-phase component (y) are recovered from the input signal and they must be combinedas complex numbers (rather than as simple addition of the amplitudes) to generate the errorsignal.The lock-in detection logic can be implemented in the FPGA servo and be used in conjunc-tion with the servo logic without the need for additional electronics. Some of the basic buildingblocks of a lock-in an amplifier are already implemented in this work. The sine and cosinewaveform can be handled by the AWG described in Section 3.3, or by the alternative design of693.4. Proposal on Feature Expansionthe AWG where the waveform is preprogrammed in ROM. The period of the sine and cosinecan be controlled with clock prescalers to the AWG module. In addition, the LP filter thatfollows the multiplier can be implemented in the form of IIR. The remaining pieces are simplearithmetic and pose no obstacle to implementing lock-in detection.3.4.2 Auto-Lock LogicThe auto-lock logic, sometimes referred to as the lock-recovery logic, is the mechanism toautomatically lock a plant to a pre-programmed setpoint. The use of an auto-lock mechanismin an experiment reduces the manual work need to lock lasers and is very beneficial in ancomplex AMO experiment. The typical locking method is to manually adjust an offset tothe laser controller until the frequency of a free-running laser is within detectable range of afrequency discriminator. This manual adjustment can be replaced by ramping the slow-DAC inthe FPGA servo slowly until an error signal is detected. Once the error signal is detected, theFPGA servo can engage the lock by setting the IIR coefficients. The trick to this implementationis to keep the auto-lock logic in the MCU that is built-in to the FPGA. The auto-lock routineis a sequential process and is more intuitive to be implemented in C/C++.3.4.3 Plant DetectionPlant detection, or sometimes referred to as system identification, is a set of control techniques,widely used in identifying the optimal control parameters in applications such as motor servos.Some system identification techniques measure the transfer function of a plant in an open-loop configuration. In some implementations, a chirped sine wave is used as the control inputof the plant and a cross-correlation or an FFT is used to identify the transfer function.Another set of techniques configures the plant in closed-loop when identifying the optimalcontrol parameters. The second type of detection techniques is sometimes the preferred methodwhen locking the frequency of a laser or a cavity, because it is often the case that the laser orcavity to be locked is not passively stable enough to allow a thorough open-loop investigation.Despite the widespread use in other applications, the technique of plant detection in a closed-loop configuration is not common practice in AMO experiments. The addition of closed-loopplant detection would therefore be a valuable tool in an AMO researcher’s toolbox.70Chapter 4Servo Performance and IntensityStabilizationThe hardware design and the firmware design of the FPGA servo is discussed in previouschapters. In both designs, the noise level and the delay of the servo are optimized for a betterclosed-loop performance. This chapter focuses on the resulting closed-loop performance of theFPGA servo with an emphasis on noise suppression.For users only previously exposed to analog servos, the closed-loop performance of a digitalservo is not obvious. The signal quantization introduced by the ADC and DAC can be especiallyworrisome. For example, the quantization level of the ADC used in the DE2 system is in theoryaround 60 uV, with 14-bit resolution and an input range of 1 V peak-to-peak. This level ofcorrection isn’t acceptable for most applications, but in practice the computation precisionallows the servo to correct to level much lower than the quantization step of the ADC or theDAC. Precision below the quantization step is the result of oversampling and signal averagingand this has been reported in [14], [18].In the following section, we describe various techniques that are useful in maximizing thelevel of noise suppression in a closed-loop system. The closed-loop performance is investigatedwith two setups, one with the FPGA servo forming a closed-loop system onto itself, referredto as the “self-lock configuration” and the other with the FPGA servo installed in an intensitystabilizing setup. The self-lock investigation focuses on exploring the limit of the FPGA servoperformance while the intensity stabilization setup focuses on demonstrating the additionalimprovement that an FPGA servo can offer when compared to an analog servo.714.1. Self Lock Benchmark4.1 Self Lock BenchmarkThe self-lock test is a convenient method for determining the performance limits of a servo.When used in control applications, the self lock performance of the servo can be combined withthe noise floor and the bandwidth of the detector and the actuator to predict the closed-loopperformances in a specific application.4.1.1 Locking PerformanceBefore using the FPGA servo in any application, it is necessary for the user to confirm that theservo performs as expected. The self-lock test, illustrated in Figure 4.1, provides a convenientbenchmark. In the self-lock test shown in Figure 4.1, the FPGA servo is configured as a PIIcontroller with negative feedback and is configured with two corner frequencies at 200 kHz.It is important to set the corner frequencies high to reveal the input noise of the servo for alarge range of frequencies but not too high to worsen the loop resonance. Here, the PI cornerfrequencies (200 kHz) are set to be roughly a decade below the loop bandwidth (2-2.5 MHz)of the servo. The typical input noise level of the servo and the bandwidth of the servo can beobserved from the data.+ +ServoPIFigure 4.1: The self-lock configuration is a closed-loop feedback system formed by the FPGAservo and no other detectors or actuators. This is a convenient method for evaluating theperformance of a servo.The spectrum can be examined in two frequency ranges, for frequencies less than 200 kHzwhere noise suppression is active, and for frequencies larger than 200 kHz where the noisesuppression is not effective. In the frequency range less than 200 kHz, the spectrum is limitedby the input noise of the servo, shown in the self-lock data in Figure 4.2 to be around 11 nV/√Hzfor the DE3 prototype and around 25 nV/√Hz for the DE2 prototype. In the high frequencyrange, the frequency of the lowest resonance reveals the total delay of the servo, with the724.1. Self Lock Benchmarkfollowing relationship.fbandwidth =12Tlatency(4.1)It can be observed from the data, that these two servo prototypes has a loop delay of 277 nsand 227 ns respectively. Additionally, a small resonance can be observed at 200 kHz and it isthe closed-loop behaviour of two zeros place at the same frequency. This effect can be avoidedif the two zeros of the PII filter is spaced a decade apart.101 102 103 104 105 106Frequency (Hz)-155-150-145-140-135-130-125dBVpp/rt(Hz)Noise spectral denisty, Self LockDE2 Prototype (PII), 200kHz, 200kHzDE3 Prototype (PII), 200kHz, 200kHzFigure 4.2: The self lock data of the DE2 servo and the DE3 prototype servo. The minimumnoise floors of the two servos are -152 dBV/√Hz and -159 dBV/√Hz. They are equivalentto 25 nV/√Hz and 11 nV/√Hz respectively. The self-lock spectrum is optimized according totechniques discussed in sections 4.1.3 - 4.1.6. Additionally, the origin of the spikes in frequenciesbetween 60 Hz and 40 kHz more visible on the DE2 spectrum is covered in Section 2.4.5.We note that even without a spectrum analyser (eg SR780 and RSA3303A), it is possibleto check the performance of a servo in closed-loop. The delay of the servo can be investigatedby increasing the loop gain to purposely introduce an oscillation at the loop resonance. Thefrequency of the oscillation follows the same relationship shown in Equation 4.1. With carefulplanning, the noise floor of the servo can be investigated with an oscilloscope and analysed734.1. Self Lock Benchmarkeither with a built-in FFT function on the scope or downloaded to a computer and analysedoff line. It is important to note the noise floor of the oscilloscope in this case, and it is possiblethat only high resolution oscilloscopes with deep memory buffers are suitable for this task.If the performance of the servo deviates from normal, then each circuit components can beinvestigated further with information in the hardware and firmware chapter.4.1.2 Noise SuppressionBefore discussing the practical side of noise suppression, we will first discuss a theoretical modelfor noise in a closed-loop control system. Figure 4.3 shows a schematic of the FPGA servoconfigured in closed-loop, with the variable gain amplifiers modelled by frequency independentgain factors G1 and G2 and with the offset circuit omitted. It is important to note that althoughnot shown in the diagram, other factors of amplification are present in the loop. Examplesinclude the logic gain, any fixed amplification or attenuation in the servo and amplification inthe actuator or the detector. These factors are not included in this model as they only clutterthe argument on noise suppression that is presented here. In a more general sense, G1 can beregarded as the total gain between the input of the closed-loop system and the servo logic, andG2 can be regarded as the total gain between the servo logic and the output of the closed-loopsystem.+- + + +ss+wPIG1 G2N0 N1 N2 N3PI=IN OUTFigure 4.3: The model used for analysing the noise suppression in a closed-loop servo systembased on an FPGA servo. For a simpler analysis on noise suppression regarding gain distribu-tion, the non tunable gain in the circuit.Noise sources N0, N1, N2 and N3 model noise introduced at different locations in the loop.The output of the loop (including the contribution from each noise) has the following transfer744.1. Self Lock Benchmarkfunction.OUT = ING1G2PI1 +G1G2PI+N0G1G2PI1 +G1G2PI+N1G2PI1 +G1G2PI+N2G21 +G1G2PI+N311 +G1G2PI(4.2)The denominator for any of the terms in the transfer function remains the same regardlessof the location of the noise source, but the numerator of each term in the transfer function isthe forward path between the location of the noise and the output of the closed-loop system.The transfer efficiency of the noise to the closed-loop output in two limits is summarized inTable 4.1. Understanding the behaviour in the two limits helps with the interpretation of thedata and with identifying the location of the noise sources.Table 4.1: The expected output noise from sources in the loop in two limits assuming G1G2 =0.5 and all other components in the loop have unity gain.OUT=ω  ωPI ω  ωPIN0N03N1G1N1G21 +G1G20 ·N2 N2G21 +G1G20 ·N3 N33The suppression of noise at frequencies ω >> ωPI is not complete regardless of where thenoise is injected into the loop. This is consistent with our empirical experience of a servohaving a limited bandwidth. In contrast, the noise level at frequencies ω << ωPI depends onthe location of the noise. Any noise introduced after the servo logic, whether it is N2 or N3,is completely suppressed regardless of the loop gain. On the other hand, noise injected at theinput of the servo (N0), is written directly onto the output of the closed-loop system. This754.1. Self Lock Benchmarkmeans that the noise at the first stage of the servo is the most influential on the overall servoperformance. The noise N1 (injected after the variable input gain) has a transfer efficiency ontothe output of the closed-loop system that depends on the distribution of the gain inside theloop. In particular, increasing the input gain G1 while keeping the product of G1G2 constantdecreases the transfer efficiency of N1 onto the output, at no cost to the other noise sources.This means that increasing G1 while keeping G1G2 constant beneficial to the noise performanceof the closed-loop system, when N1 is substantial.Equipped with these conclusions, we are able to continue the investigation in an informedfashion. In the studies that follow, the effect of loop gain, corner frequency and gain distributionon noise suppression is investigated.4.1.3 Loop GainBased on empirical tuning experience, we know that there is an optimal loop gain for suppressingnoise. Figure 4.4 illustrates the behaviour of the noise spectrum when the loop gain is varied.We observe an optimal loop gain of 0.5 (equivalent to G1G2 = 1.2 due to other factors for gainin the loop) because when the gain is lowered the width of the suppression band shrinks, butwhen gain is increased the height of the resonance due to loop delay increases. The loop delayresonance is not visible in this plot as it is above 1 MHz. Nevertheless when the height of theloop delay resonance increases, the peak-to-peak amplitude of the error signal also increasesuntil it exceeds the peak-to-peak range of the ADC. When the error signal exceeds the ADCinput range, the servo loop adds noise to the quantity being controlled rather than suppressingit. As seen in Figure 4.4, the range of gain where the closed-loop controller switches from noisesuppression (at G1G2 = 1.2) to noise amplification (at G1G2 = 1.76) is small.4.1.4 Corner FrequencySimilar to the effect of increasing the gain, increasing the corner frequency of the PI filterwidens the suppression band, as shown in Figure 4.5. The upper bound of the corner frequencyof the PI filter is limited by the bandwidth of the closed-loop. Because a PI filter introducesa 90 degree phase delay in the output for frequencies ω << ωPI , when corner frequency istoo close to the bandwidth of the closed-loop, the delay introduced by the PI filter interacts764.1. Self Lock Benchmark101 102 103 104 105Frequency [Hz]-140-130-120-110-100-90-80Noise Spectral Denisty, Scan Loop Gain, DE2 PrototypeG1=8, G2=0.060G1=8, G2=0.085G1=8, G2=0.100G1=8, G2=0.150G1=8, G2=0.220Figure 4.4: The effect of loop gain on noise suppression. As loop gain increases the width of thesuppression band also increases. However, once the amplitude of the loop delay resonance (atfrequencies above 1 MHz) exceed the input range of the ADC, the closed-loop system amplifiesrather suppresses noise.with the bandwidth of the loop and exacerbates the loop delay resonance. A worse loop delayresonance can cause the closed-loop system to amplify noise when the amplitude of the errorsignal exceeds the ADC input as it is already seen in the case of an excessive loop gain inSection 4.1.3. To avoid this issue, it is often safe to first set the corner frequency at a tenth ofthe loop bandwidth and to then make fine adjustment to the corner frequency.4.1.5 Gain DistributionInput Gain vs Output GainSection 4.1.2 makes the argument that the gain distribution has an effect on the noise suppres-sion through the evaluation of the transfer function of a closed-loop control system, and thissection presents data on this effect. Figure 4.6 shows a higher gain at the input of the servo (G1)while keeping the total loop-gain constant improves the noise floor of the closed-loop system.774.1. Self Lock Benchmark101 102 103 104 105Frequency [Hz]-140-130-120-110-100-90Noise Spectral Denisty, Scan Corner Frequency, DE2 PrototypePII, 70kHz, 7kHzPII, 140kHz, 14kHzFigure 4.5: The effect of corner frequency on noise suppression. As the corner frequencies ofthe PII filter increase the width of the suppression band also increases. The limitation of thisoptimization technique is covered in the text.784.1. Self Lock BenchmarkThis behaviour indicates that the performance of the servo is limited by a noise source after thevariable gain amplifier (refer to Section 2.3.3 and Section 2.4.5 for details on the noise floor ofthe FPGA servo hardware). Unfortunately, G1 cannot be increased indefinitely. As the inputgain G1 increases, the amplified error signal eventually becomes larger than the input range ofthe ADC and causes the servo to lose lock. This gain distribution effect on the servo noise flooris also present for an analog servo as well, but the FPGA servo needs special consideration dueto the limited the input range of an ADC compared to that of a standard opamp.101 102 103 104 105Frequency [Hz]-140-130-120-110-100-90-80Noise Spectral Denisty, Scan Gain Distribution, DE2 PrototypeG1=1, G2=1.2G1=2, G2=0.6G1=4, G2=0.3G1=8, G2=0.15Figure 4.6: The effect of G1 and G2 on noise suppression. When loop gain is kept constant, ahigher G1 leads to an improvement in noise suppression in frequencies where noise suppressionis limited by N1 (the ADC) in the noise model.FPGA Gain vs Output GainSimilar to the limitation of ADC range, the DAC is also limited and it needs sufficient amplifi-cation to correct the noise in the system. As seen before, trading off output gain for input gainimproves noise performance; however, the actuation range of the closed-loop system is reducedin the process and this in turn reduces the maximum amplitude that the system can correct794.1. Self Lock Benchmarkfor. This scenario can be avoided by decreasing the gain through the FPGA logic rather thanat the variable gain stage following the DAC. Reducing the gain through the FPGA logic issimpler with 32-bit IIR coefficients as the pole-zero resolution is high and a reduction of thepole-zero resolution is unlikely to affect the ability of the system to lock. On the other hand,reducing the gain through the FPGA is not as straightforward with 16-bit IIR coefficients asthe pole-zero resolution placement is already 7 kHz (details of this implementation is discussedin Section 3.2.3). Figure 4.7 shows a scenario where the lock was able to suppress a higher levelof error when the FPGA gain is traded off for output gain.101 102 103 104 105Frequency [Hz]-135-130-125-120-115-110-105-100-95-90-85Noise Spectral Denisty, Decrease Logic Gain, DE2 Prototypemax noise = 0.2Vpp, G1=4, GL=1, G2=0.3max noise = 0.4Vpp, G1=4, GL=0.5, G2=0.6Figure 4.7: The effect of G2 and logic gain on noise suppression. When loop gain and G1 arekept constant, decreasing gain through the servo logic in the FPGA and increasing G2 (thegain between the DAC and the servo output) increases the maximum amplitude of noise thatthe closed-loop system can correct.4.1.6 The Optimal StrategyBased on the study, we can conclude that the optimal tuning strategy is to choose the total loopgain and the poles and the zeros suitable for the laser system and then redistribute the gainwithin the servo for the optimal noise performance. (We follow this practice in the later stages804.2. Intensity Lockof this project.) The tuning example discussed is for a PI filter but all the same principles applyfor a different transfer function. Thus, compared to an analog servo, the FPGA servo has anadditional step of choosing the gain distribution. Here, the optimal distribution can be obtainedby first deciding on the output amplification needed to give the actuator a sufficient range andthen maximizing input amplification without letting the amplified error signal saturates theADC. The gain through the FPGA can then be used as a free parameter to keep loop-gainconstant.The best experimental result for suppressing white noise with a 30 MHz bandwidth, asshown already in Figure 4.7 is in excess of 40 dB. The suppression of single tone noise withinthe suppression band can be much better and is estimated to be as high as 160 dB. This isunder the assumption that sufficient gain follows the DAC to amplify the correction to 10Vand the input gain is at least 8 to obtain a input noise floor of 100 nV/√Hz. The differencein the ability of a servo to suppress white noise and single-tone perturbation can illustrate theconstraints of a digital servo. In the case of white noise, a large band of the noise can not besuppressed so the residual error is large which in turn limits the input gain. The single toneperturbation is another extreme where the perturbation can be completely suppressed and littleresidual noise is left to limit the input gain so the maximum perturbation that the servo cansuppress is set by the DAC range and the amplification that follows. A realistic applicationwill likely involve a noise spectrum somewhere between the two extremes, and either the ADCrange or the amplification after the DAC can be the limiting factor for the noise performance.4.2 Intensity LockIn this section, the FPGA servo system is applied to an intensity stabilization application. Thisis a different application from the use of an FPGA to provide PDH based frequency control ofa laser previously demonstrated in various published works [9, 14]. The intensity stabilizationbuilds upon the FPGA servo discussed in previous sections, with the addition of intensitymodulation and measurement hardware. This section first covers the design of the hardwareand then describes some optimization techniques used to improved the closed-loop performanceof the intensity stabilization system.814.2. Intensity LockThis study also focuses on demonstrating the performance of the FPGA servo in comparisonto and beyond that of a high-performance analog servo. The ease for such improvement on thesame piece of hardware is all thanks to the ease of reprogramming the FPGA and its ability toemulate complex transfer functions. Three servos, the Vescent D2-125, the DE2 servo prototypeand the DE3 servo prototype are used to make the baseline comparison. The DE2 prototypeis equipped with a 16-bit IIR and the DE3 prototype is equipped with a 32-bit IIR (refer toChapter 3 for details on IIR implementation). Two aspects of the servo performance can beobserved from the study. First, the two servos have similar noise floors at the highest gainsetting, both are in the 10 nV/√Hz range. Secondly, the bandwidth of the closed-loop systemis dominated by the intensity control hardware (i.e. the plant) with a delay of 400 ns, makingthe bandwidth difference of the analog servo (at 10 MHz) and that of the FPGA servo (2.5MHz) less consequential.4.2.1 MotivationThe shot-to-shot variation between experimental cycles in a scientific investigation often directlyaffects the quality of the result. The laser intensity is a factor that can affect a cold-atomexperiment in many stages, including changing the the population of the initial atomic sample,changing the AC Stark shift relevant for spectroscopy and changing the exposure intensity ofatom cloud during absorption imaging [42]. The dependence of cold-atom experiments on thisquality makes active stabilization of intensity a viable route in making the experiments robust.The hardware developed under the umbrella of intensity stabilization has another use andthat is intensity modulation. Wide bandwidth modulation of intensity also has use in coldatom experiments. Example applications include dynamic formation of dipole trap [43] andtransformation of the internal quantum state population [44].4.2.2 A Note About Noise UnitsIn previous sections, the electronic noise level of the servo and the associated electronics isevaluated in nV/√Hz. In this section, the intensity stability of the laser is evaluated in824.2. Intensity LockRelative Intensity Noise (RIN), with the following relationship.RIN =〈∆P (t)2〉P 20(4.3)Here, P is the laser power and the square of which (intensity) is proportional to the detectedelectrical power, PE , at a photodetector [45]. This gives rise to the expression for RIN as thefollowing.RIN =∆PEPE0=(VAC)2(VDC)2(4.4)Here, the direct observables VAC and VDC can be obtained from an Electrical Spectrum Analyzer(ESA) and an multimeter respectively.Here, the RIN is an evaluation of the closed-loop intensity stabilization system rather thanthe just the servo alone. This means that the conversion from servo noise floor to RIN of thelaser highly depends on the noise floor of the detector and the amount of light being detected.The implementation detail of this intensity stabilization system is covered in the followingsection.4.2.3 ImplementationIntensity stabilization is achieved with an AOM driven by a Radio Frequency (RF) source witha variable power and a Si biased amplified photodetector. The AOM allows manipulation oflaser intensity by splitting the beam with a variable diffraction efficiency controlled by the RFpower sent to the AOM. The latency of the AOM depends on the proximity of the laser beamwith respect to the piezo element that creates the moving diffraction pattern in the crystaland is typically in the 200-400 ns range. The Si detectors used are the Thorlabs DET10Aphotodetector and the Hamamatsu S5971 Si photodiode biased with well regulated 5 V. TheDET10A and the S5971 detectors respectively have the Noise-Equivalent Power (NEP) of 1.2×10−13 W/√Hz and 7.4× 10−15 W/√Hz and bandwidth of 350 MHz (calculated from the rise-time of 1ns) and 100 MHz.For a more thorough study, additional intensity noise is injected into the system via a secondAOM whose RF power is modulated by a VGA driven by a DS345 function generator that is834.2. Intensity Lockconfigured to generate white noise with bandwidth of 30 MHz. The system that artificiallyinjects intensity noise resembles a laser with an inherent noise of the same level. It may becounter-intuitive at first, but the latency through the noise injection AOM and the locationwhere the noise is injected (before or after the correction AOM) does not affect the noisesuppressing capability of the system.AOM 1ServoAOM 2NoiseRF 1 VAtt 1 RF 2 VAtt 2 PD 1 PD 2Figure 4.8: The opto-electrical system used to study intensity stabilization. The intensitystabilization consists of a RF source (RF1), a variable attenuator (VAtt1), an AOM (AOM1),a photo-detector (PD1) and an analog or an FPGA servo. To study the performance of theintensity stabilization system on various level and type of intensity noise, a noise modulationsystem is constructed from a RF source (RF2), a variable attenuator (VAtt2), an AOM (AOM2)and a noise generator. Finally, the out-of-loop detection of intensity noise of the system isaccomplished via a second photo-detector (PD2).ActuatorThe AOM is a diffraction device with a diffraction grating dynamically formed inside an acousto-optical material by a compression wave. The compression wave is generated by a piezo mountedat one end of the crystal and travels at the speed of sound. The piezo is often driven from anRF source through an Inductor-Capacitor (LC) resonator. At different RF power levels, thecompression wave forms diffraction grating of different contrast in the crystal.The RF power is controlled using a fast analog switch based on the MAAVSS0006, whichis only available as a single IC. For this work we designed a PCB with coaxial connectors asthe interface to the IC. The core schematic of the design is shown in Figure 4.9 with additional844.2. Intensity Lockdetails in Appendix B.Figure 4.10 shows the relationship between the control voltage and the transmission effi-ciency. This analog RF switch can only accept a rather low input power (10 dBm), so it is oftenthe first component in the RF amplification chain. A few observations can be made from thedata in Figure 4.10. For example, the leakage when the switch is off, typically in the -60 dB to-80 dB range, suggests the need for a mechanical shutter when the light level must be fully off.In addition, we observe variation between devices, suggesting that calibration maybe needed foreach device. Finally, we note that the transition between on and off is not linear but appears tobe roughly linear in dB in the transition region. This means that the closed-loop system usingthis intensity modulator may not maintain a constant gain for all set points and open-loop useof this modulator may need special consideration on the nonlinearity of the modulator.In this design of an analog RF switch, speed is a major consideration. The variable atten-uator is chosen for the fast rise and fall time specified to be 10 ns in the datasheet [46]. Sincethe variable attenuator is to be used as part of an intensity modulator, its transfer function isevaluated. The transfer function shown in Figure 4.10 shows the performance of the analog RFswitch together with an AOM. In this particular case, the transfer function has modulationbandwidth of 3 MHz, and a latency of about 400 ns observed from the phase response plot. Inthe case of the latency, the time it takes the compression wave to travel to the laser beam isthe dominant source of delay with every 1 mm of distance between the laser beam to the piezodriver costing about 230 ns (calculated from the speed of sound in Tellurium Dioxide (TeO2)[47]). The latency time causes the closed-loop bandwidth of an intensity stabilization schemewith AOM to be limited to about 1 MHz, although the modulation (open-loop) bandwidth ismuch higher. The modulation bandwidth of 3 MHz shown in this transfer function data islikely the result of the finite beam size coupled with the speed of sound in the crystal. We notethat these data were taken with an OP37 opamp in the which was subsequently replaced withAD829 with a faster response. The AD829 was observed to have a bandwidth of 90 MHz. Itwould be interesting to see if the modulation bandwidth increases from this change.With use in closed-loop, some optimization is done to reduce the total loop latency. Besidesplacing the focus of the laser beam close to the piezo driver, the BNC cable lengths are minimizedand this led to a small reduction in delay.854.2. Intensity Lock11223344D DC CB BA ATitleNumber RevisionSizeADate: 2016-10-25 Sheet    ofFile: C:\Users\..\VAtt_diagram.SchDoc Drawn By:R31kR21kR510kGND15V-15V GND GNDRFIN1GND 2RFOUT 3GND4VC5MAAVSS0006100pFC13GND7pFC15R14k0.1uFC17GND2365COMPAD829JRRF IN RF OUTVCTRLPIC1301PIC1302COC13PIC1501PIC1502COC15PIC1701PIC1702COC17PIR101PIR102COR1PIR201PIR202COR2PIR301 PIR302COR3PIR50CCWPIR50CWPIR50WCOR5PIU201PIU202PIU203PIU204PIU205COU2PIU?02PIU?03PIU?05PIU?06COU?PORF IN PORF OUTPOVCTRLFigure 4.9: Diagram of the variable attenuator circuit with the AD829 configured in currentcompensation mode. A snapshot of the layout and additional details can be found in AppendixB.0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Control Voltage, V-90-80-70-60-50-40-30-20-100RF Transmission, dBTransmission vs Control VoltageVR1VR2VR3VR4VR5VR6VR7Figure 4.10: Control voltage versus transmission through the variable attenuator. It is impor-tant to note the variation in the response to input voltage and in maximum RF suppression.864.2. Intensity Lock-15-10-50Magnitude, dBAOM-Based Intensity Actuator, Transfer Function102 103 104 105 106Frequency, Hz-360-270-180-900Phase, degreeFigure 4.11: Transfer function of the variable attenuator + AOM + PD system. The loopdelay is about 400 ns. As the delay is dominated by the distance between the laser beamand the ultrasonic source in the AOM, this delay is modified at various point of the intensitystabilization study due to small positional changes but is kept to a range of 200-400 ns. Themodulation bandwidth is in excess of 3 MHz. This opens up the use of this system in highspeed intensity modulation.DetectorAs the interpretation of the closed-loop transfer function in Section 4.1.2 shows, the noise floorof the closed-loop system, especially at low frequencies is highly dependent on the noise levelof the first stage. This means that the noise level of the detector sets the lower bound onthe closed-loop performance. The intensity stability achieved by this work is the result ofoptimizations made to reduce the noise level of the detector as much as possible.The major contributor of noises at the detector is the electronic/photon shot noise, thethermal noise of the charge carriers, the op-amp flicker noise often referred to as the 1/f or pinknoise, and the easily over-looked power supply noise that often couples into electronic circuits.The shot noise expressed for electricity〈i2〉= 2eI∆f (4.5)where e is elementary charge and ∆f is bandwidth, is hard to work around without increasing874.2. Intensity Lockthe intensity of indecent light onto a photo-detector, as the shot-noise is the by-product of theparticle-like property of both the electronics and photons and is proportional to square rootof the number of particles. Once the intensity is fixed, the impedance that is driven by thephotodetector (modelled as a variable current source) and the gain after the photodetector areboth free design parameters that affect the SNR of the detector. An excellent source on designprinciples can be found here [48]. In the work conducted here, the noise floor of the detectoris much lower than the noise floor of the servo, with detector noise floor at the 1 nV/√Hzlevel (assuming 1 mA average photocurrent and 50 Ω impedance). This suggest that additionalgain at or after the detector can improve the overall performance, by a factor of 100 until thephoton/electronic shot noise becomes the limiting factor.Another technique for identifying noise sources is to apply the characteristic shape of thenoise spectrum of various noise type. This is a useful technique when the only direct observableis the spectrum of the noise from an ESA. For example, both shot noise and thermal noise areconstant in frequencies[49]. The op-amp flicker noise or the 1/f has a slope of -20 dB/decadeat low frequency [50, p.84]. Noise with any other characteristic shapes whether is it is in theform of spikes or a broad spectrum are likely a result of poor practice in the form of improperground, noisy power supply or inadequate shielding of signals.In the implementation scheme shown in Figure 4.8, intensity is monitored by two photode-tectors with only one detector in the feedback loop of the system. This technique is oftenreferred to as out-of-loop detection, and it is helpful for detecting whether the noise floor of thedetector is higher than the servo. When adding the out-of-loop detection, we focus the laserbeam onto both detectors and keep the path difference minimal. The in-loop spectrum looksidentical to the out-of-loop spectrum, but to eliminate differences at low frequencies, we foundit necessary to reduce the air circulation near the detectors.4.2.4 PII ComparisonIn comparing the performance of the FPGA servo against analog servos, we use a well-reputedcommercial analog servo by Vescent as a benchmark (D2-125). For this comparison, the FPGAservo needed to work within the constraints set by the analog servo. The D2-125 model byVescent, implements a Proportional double-Integral and Derivative (PIID) with configurable884.2. Intensity Lockcorner frequencies.In the interest of fairness in comparing the three servos, the total loop gain of each closed-loop system is kept the same after we determined the optimal loop gain. The corner frequenciesof the servos are chosen according to the loop delay of each system. In the case of the Vescentservo, with the higher servo bandwidth of 10 MHz, a higher corner frequency at 100 kHz ispossible without worsening the oscillation at the loop delay resonance. In the FPGA servo,with a lower servo bandwidth of 2.5 MHz, a corner frequency of 70 kHz is chosen due to thehigher loop latency. As it can be observed in Figure 4.12, the width of the suppression band isnot substantially different between the systems formed by different servos, since the latency ofthe AOM is the limiting factor to the closed-loop performance.10 1 10 2 10 3 10 4 10 5 10 6Frequency (Hz)-130-120-110-100-90-80Relative Intensity Noise (dBc/Hz)Noise spectral denisty, Baseline Comparison PIIDE2 (PII), 70kHz, 7kHzDE3 (PII), 70kHz, 7kHzVescent (PII), 100kHz, 10kHzFigure 4.12: Alternative baseline comparison of DE2, DE3 and Vescent servo for the intensitystabilization study. All servos realize a PII transfer function to match Vescent. The gain andcorner frequencies of all servos are tuned to optimize the noise suppression. The origin of thespikes in frequencies between 60 Hz and 40 kHz visible on the DE2 spectrum is covered inSection 2.4.5.To complete the controller’s transfer function, the corner frequency for the second integratoris chosen to be a decade below the corner frequency of the first PI. This was done because894.2. Intensity Lockwhen two zeros are too close in frequency, the closed-loop system pushes the zeros away fromthe real axis in the s-domain (this can be observed in a root locus diagram) and this can resultin oscillation. The contribution of the derivative component is not studied here and and thuswas not enabled.The spectrum shows that the FPGA and the Vescent servo have similar noise floors ofroughly 10 nV/√Hz at 1 kHz. With the exception of the small difference in the frequencies ofthe loop resonances, the noise spectrum capability of the two types of servo is nearly identical.This is not surprising as similar transfer function are implemented in the servos.4.2.5 PI3 ImprovementAs a natural extension of the PII servo, a PI3 (3 integrator in cascade) was attempted on theintensity stabilization system. This is accomplished by cascading three IIR filters in the FPGAservo, all configured as integrators. The difference between the PII filter and the PI3, shown inFigure 4.13 is that it widens the suppression band without adding oscillation at the loop delayresonance. This is an example of a filter that cannot be easily implemented in an analog servowithout additional hardware.4.2.6 PII + Lag-Lead ImprovementThe lag-lead filter is another example of a filter that can not be easily implemented in an analogservo. Unlike the PI3 filter, which can still be constructed by chaining multiple existing analogservos, the lag-lead filter is impractical to implement as an analog circuit due to its large numberof tunable poles and zeros.The lag-lead filter is effectively a notch filter composed of two poles and two zeros. Similarto the lead-lag filter (a bandpass filter), the lag-lead filter can be introduced into a transferfunction to modify the transfer function locally, as illustrated by their transfer functions shownin Figure 4.14. The lag-lead filter can be used to suppress loop resonance when implementedwith a center frequency that is the same as the frequency of the loop resonance. Because thelag-lead filter reduces the gain locally at the loop resonance, the amplitude of the loop oscillationis reduced. Another benefit of a notch filter (the lag-lead filter) at loop resonance is to allowthe loop gain to be increased and thus results in a wider suppression band for noise. Both904.2. Intensity Lock10 1 10 2 10 3 10 4 10 5 10 6Frequency (Hz)-110-105-100-95-90-85-80-75Relative Intensity Noise (dBc/Hz)Noise spectral denisty, PI3DE3 (PII), 70kHz, 70kHzDE3 (PI3), 70kHz, 70kHz, 70kHzFigure 4.13: Demonstration of the DE3’s ability to implement an additional integrator andits effect on noise suppression. The corner frequency of 70 kHz is used for all 3 poles. Thesuppression slope changes from 40 dB/decade to 60 dB/decade as expected.effects are illustrated in Figure 4.14, where the DE3 prototype servo with 32-bit IIR coefficientimplements a PII + lag-lead filter with total latency of about 200 ns.The lag-lead filter and the PI3 are merely examples of advanced servo transfer function thatan FPGA servo can implement without costing hardware development time or servo perfor-mance. This also means that the use of FPGA servo can lower the barrier for exploring the useof advanced servo transfer function for the use in laser control. Despite of the added flexibilityin implementing servo transfer functions, it is still important to keep in mind at additionalservo gain is only beneficial at frequencies where the noise floor of the servo is not a limitingfactor. That is to say that noise suppression is still fundamentally limited by the input noiseof the servo.914.2. Intensity Lock1234Amp (dB)Lead-lag Transfer Function105 106 107 108Frequency (kHz)-15-10-5051015Phase (degree)-4-3-2-1Amp (dB)Lag-lead Transfer Function105 106 107 108Frequency (kHz)-15-10-5051015Phase (degree)Figure 4.14: The transfer function of the lead-lag and the lag-lead filer with center frequencyat 1 MHz and a bandwidth of 1.5 MHz. The lead-lag filter is composed of zeros at 250 kHz and4 MHz and poles at 500 kHz and 2 MHz. The lag-lead filter is composed of zeros at 500 kHzand 2 MHz and poles are 250 kHz and 4 MHz.10 1 10 2 10 3 10 4 10 5 10 6Frequency (Hz)-115-110-105-100-95-90-85-80-75Relative Intensity Noise (dBc/Hz)Noise spectral denisty, PII+Lag-leadDE3 (PII), 70kHz, 7kHzDE3 (PII+LL), 70kHz, 7kHzDE3 (PII+LL+Gain), 70kHz, 7kHzFigure 4.15: Demonstration of the DE3’s ability to implement lag-lead filter at center frequencyof 700 kHz. The lag-lead filter has two effects 1) suppression of loop resonance of the servosystem 2) allowing increase in gain and thus widening of the noise suppression band924.3. Conclusion4.3 ConclusionThe most intriguing conclusion drawn from the study covered in this chapter is the similar inperformance of the analog servo and the FPGA servos when configured in closed-loop (Section4.2.4). Specifically, when the analog servo and the FPGA servo are configured with similartransfer functions, both as PII filters, the closed-loop performance does not show substantialdifferences in either noise suppression or the frequencies of the loop resonance. The similarityin loop resonance is a result of the plant being a substantial source of delay in the closed-loopsystem and the similarity in noise floor is a result of carefully design circuits with detailedconsideration in noise reduction already covered in Chapter 2.The work by this chapter demonstrates the versatility of an FPGA servo and its ability toform advanced transfer functions. The implementation of advanced transfer function an FPGAservo is suggested by a few published work as a potential benefit this new technology [14], butthis work is the first to demonstrate the use of advanced transfer functions in the form of PI3and PII+lag-lead in an FPGA servo (Section 4.2.5 - 4.2.6). We are able to show the benefitof these advanced transfer functions in widening the noise suppression band beyond what wasdemonstrated with PII, which is considered a benchmark in this study.Another contribution covered in this chapter is the summary of the tuning techniques neededto work with an FPGA and how the techniques differ from working with an analog servo (Section4.1). The study shows that tuning parameters like loop gain and frequencies of the poles andzeros affect the closed-loop transfer function of the FPGA servo similarly to its effect on theanlog servo. In comparison to the analog servo, the FPGA servo has a stronger dependence ongain distribution as the system is limited by the noise floor at the ADC and the output rangeof the DAC. The work summarize a strategy for the optimal gain distribution when using anFPGA servo (Section 4.1.6), where the user must be careful to avoid the signals from exceedingthe range of the ADC or the DAC at any time.93Chapter 5Case Study: Evaporation in a DipoleTrapPrevious chapters describe the design of a high-performance FPGA servo and the evaluationof its performance in closed-loop. As a natural extension to the work described so far, we lookinto using the FPGA-based system to improve existing experiments. In this case study, weinvestigate in the relationship between the active stabilization of the laser intensity and theevaporation efficiency in a dipole trap. This case study demonstrates the use of an FPGAservo in the intensity stabilization of lasers and shows that its use is not limited to frequency orphase stabilization (as demonstrated in various published work [8], [14]). This chapter starts bymotivating the importance of laser intensity in a dipole trap and eventually reach the conclusionof whether active intensity stabilization is a suitable solution to improving evaporation efficiency.5.1 Motivation and BackgroundOptical-only traps with wavelength far detuned from the cooling transitions of Alkali atomshave long been used to trap and cool neutral atoms to study the dynamics of atomic cloudsat temperatures under the micro Kelvin level [51]. At the Quantum Degenerate Gas (QDG)laboratory, an dipole trap is used to perform a second cooling stage to create ultra-cold Li orLi+Rb atomic mixtures, and it is preceded by loading and cooling of neutral Li and/or Rbatoms in a Magneto-Optical Trap (MOT) [52], [53]. The dipole trap is generated by focusingthe output of a 1090 nm, 100 W fiber laser onto the atoms, and it is responsible for evaporativelycooling the atom cloud further and confining the cloud for scientific investigation. The finalstage of each experiment is the absorption imaging of the atomic cloud with a small amount ofon resonance light, which captures the atom number and the physical distribution of the atoms945.2. Dipole Trap and Trap Frequencyand provides clues as to what happened during the experiment.The purpose of this investigation of evaporative cooling of Li in a dipole trap is to improvethe evaporation efficiency since this will increase the number of atoms available for the ex-periments. A higher atom population has many benefits. Examples include a higher qualityabsorption image due to a higher signal to noise and a better evaporation efficiency of an atomicmixture (Li and Rb for example) where Li acts as the sympathetic coolant [54]. Prior to thisstudy, the atoms undergo a transfer from a D2 MOT to a high power dipole trap formed bya 100 W multimode fiber laser (SPI SP-100C-0013), and then another transfer to a low powerdipole trap formed by a 20 W single mode fiber laser (IPG YLR-20-1064-LP-SF). The transferis necessary because the 100 W SPI laser lacks the intensity stability to cool the Li cloud belowtemperatures of 1 uK, and the 20 W IPG laser is not powerful enough to allow a direct transferto it from the D2 MOT. This study investigates the stability issues in the 100 W SPI laser andaims to minimize the atom losses due to transfer between the two dipole traps.5.2 Dipole Trap and Trap FrequencyImproving the evaporation efficiency starts with a basic understanding of dipole traps. Althoughdetailed reviews of dipole traps can be found in various published work [55], this thesis providesa condensed overview that covers the basic concepts needed for investigating issues relatedto evaporation efficiency. One concept is the approximation of the profile of a dipole trapas a harmonic potential, which has constant spacing between adjacent energy levels. Thisapproximation is good for atoms with very low energy as they only explore the bottom ofthe Gaussian shaped potential which is very nearly harmonic. Here the energy spacing ischaracterized by the harmonic trap frequency, and the atoms are most sensitive to perturbationsat this frequency.The trapping potential produced by a focused laser beam is proportional to the intensity.The profile of a focused Gaussian beam is illustrated in Figure 5.1 (left) and it has the followingexpression.I = I0e− 2x2w(z)2 (5.1)955.2. Dipole Trap and Trap FrequencyHere I0 is the peak intensity, z is the position on the propagating axis of the laser and x is theposition on an axis perpendicular to the propagation axis of the laser. The parameter w(z) isthe width of the Gaussian profile as a function of z position with the following expression.w(z) = w0√1 +(zzR)2(5.2)The interaction between the light field and neutral atoms depends on the wave length of thelight field and the atomic transitions available in the atoms. Fine structures aside, the singlevalence electron in an 6Li atom can make transition between the ground state 1s22s1 and theexcited state 1s22p1 with light at 671 nm. Both the SPI laser and IPG laser with respectivecentral wavelengths of 1091 nm and 1065 nm are far-red-detuned from the transition and formattractive potentials for the atoms.The attractive energy potential has the profile of the followingU ∝ I ∼ U0e−2x2w(z)2 , w(z) = w0√1 +(zzR)2(5.3)When only considering radial motion at the beam waist, this expression can be converted intothe following by applying Taylor expansion.U ∼ U0(1− 2x2w20+4x4w40) (5.4)After dropping the higher order terms in the Taylor expansion, the energy potential can beapproximated as a harmonic potential with the following expression,U = U02x2w20(5.5)which is harmonic and therefore has evenly spaced energy levels. This approximation is illus-trated in Figure 5.1 (middle). This means that trapped atoms can be excited by a perturbation(acting on their positional degree of freedom) at this frequency and move up the ladder ofenergies leading to heating of the ensemble and eventually loss of particles from the trap. The965.3. Loss Mechanismsspacing between energy level has the following expression,∆U = h¯√4U0mw0(5.6)which can be characterized by the followingωr =√4U0mw0(5.7)referred to as the trap frequency. Here, the subscript “r” refers to the radial axis of the laser.The same second order approximation can be applied to the propagating axis, z, with thefollowing expression,ωa =√4U0mzR(5.8)where the characteristic length scale, rather than the width of the beam waist, is the Rayleighlength. The ensemble temperature is sensitive to perturbations at or near these frequencies. Inour experiments, we also use a crossed beam geometry, as illustrated in Figure 5.1 where thetrap frequencies are determined by the combined potential of the two beams.xz x ωrωa x'z'Figure 5.1: Side view of a focused Gaussian beam (left), the Gaussian-shaped potential, in thecross section (middle) often approximated as a harmonic potential in the deep trap limit andthe top view of crossed focused beam (right).5.3 Loss MechanismsA commonly used cooling technique in an optical dipole trap is so-called forced evaporativecooling where the potential of the trap is lowered slowly by decreasing the beam intensityforcing the hottest atoms to escape and leaving behind a cooler sample after the ensemble has975.3. Loss Mechanismsre-thermalized. In this process, not all atoms that started in the dipole trap remain. As shownby OHara et al [56], [57], when the re-thermalization timescale is very rapid, the evaporation isefficient and the ensemble temperature closely tracks the trap depth. In this case, the ratio ofthe trap depth to the temperature U/kT = η is typically of the order η = 10 and the numberof atoms in the trap follows the following scaling law.NNi=( UUi)3/[2(η−3)]=( UUi)0.22(5.9)Here, Ui and U are the depth of the initial and the final trap potential and the Ni and N arerespectively the initial and final population. A detailed discussion of the efficiency of the forceevaporative cooling is provided by the work of OHara at el [56] [57].With the knowledge of the achievable efficiency of a force evaporation routine, it was sur-prising to see the evaporation efficiency of 6Li in the 100 W SPI laser drastically deviate fromthe scaling law in trap less than 10 W in power. Some detective work went into debugging thisproblem. The investigation is based on an understanding of various loss mechanisms that canlead to a loss of atoms in a dipole trap.5.3.1 Background ScatteringTrap loss can be caused by collisions with residual particles in the vacuum. It is somewhatsurprising that collisions with these room temperature particles can sometimes be soft enoughto leave the trapped particles in the trap but with a higher kinetic energy. Both loss andheating of the ensemble reduce the efficiency of evaporation. However, in our case, we observedefficient evaporation in the 20 W IPG laser. To completely rule out background collisions as theproblem, we measured the loss rates in both dipole traps at different laser powers to confirmthat the poor SPI evaporation was not the result of a poor vacuum in our experiment.5.3.2 Loss Due to Resonant ScatteringWith background scattering eliminated as a possible cause, the next possible cause evaluatedwas the loss of atom due to spectral components close to Li6 D2 line in the SPI. Off resonantscattering was ruled out since the evaporation in the IPG laser at similar powers was better985.4. Studyand its operation wavelength is actually closer to the D2 line at 671nm. The SPI laser wasfound to have no significant spectral power near 671 nm on an optical spectrum analyzer AndoQ6315. These observations lower the likelihood of resonant scattering as a possible cause. Theseobservations lower the likelihood of optical pumping as a possible cause.5.3.3 Parametric HeatingWith the first two candidates deemed unlikely causes, the final candidate is the stability ofthe laser itself. The work by Savard at el categorized stability of a dipole trap into two types,the pointing stability which affects the physical location of the trap and the intensity stabilitywhich affects the depth of the trap and the trap frequencies [58]. Both types of instability,when oscillating on similar time scales as the trap frequency, are able to excite trapped atomsto higher energies leading to ensemble heating and, eventually, to trap loss. In our experiment,the pointing stability of the SPI is carefully handled with the use of a CNC-machined fiber-mounts from solid stainless steel, weighted mechanical posts and stable commercial mirrormounts. This leaves the intensity noise of the SPI laser the only remaining and a highly likelycause of the evaporation issue.5.4 StudyAs a starting point for this study, we note that it was shown by Savard et al [58] that theheating rate of a trapped atomic ensemble is related to the intensity noise of the trap laser bythe following expression.Γ = pi2υ2trapS(2υtrap) (5.10)Here Γ is the e-folding time of temperature in the trap due to intensity noise in the laser. Itis related to the value of the trap frequency and the one-sided power spectrum of the relativeintensity noise at twice of the trap frequency. This relationship allows us to make the connectionbetween intensity noise of the laser (in RIN) and heating rate.995.4. Study5.4.1 Heating Rate of Existing TrapThe heating rate of the trapped ensemble can be characterized by measuring the temperatureafter various hold times. The ensemble temperature is measured using a Time-of-Flight (TOF)method, where the atom cloud is allowed to expand in free space for some time, and the cloudsize after expansion (i.e. the speed of the expansion) provides a measure of the average kineticenergy at the beginning of the expansion and in turn the average temperature [42]. The heatingrate measurement is therefore a series of TOF measurements after the atom cloud is held in thedipole trap for different times. The heating rate measurement is therefore more time-consumingthan a loss rate measurement, but the heating rate measurement gives more insight into theevolution of the ensemble over time.As shown in Figure 5.2, the temperature of a 6Li cloud is shown for different hold timesin the SPI laser trap at 10 W, corresponding to the power where the evaporation efficiencywas observed to be poor. The data is consistent with an exponential increase in the cloudtemperature with an e-folding time of 1.9 s. With the knowledge of the e-folding time, and therelationship between the laser intensity noise and heating rate in Equation 5.10, it is possibleto infer the level of intensity noise that would be responsible for the heating rate. Figure 5.2shows a measurement of the intensity noise of the SPI laser at a similar output power, andthe noise level is consistent with an e-folding time of 1.9 s. The intensity noise of the laser atsimilar power can be seen in Figure 5.2, to be in similar level as what would be responsible fora e-folding time of 1.9 s. The trap frequency is estimated to be 5 kHz in the axial direction and1 kHz in the radial direction.While this agreement is evidence that the problem is related to the intensity noise, we needto confirm that reducing the intensity noise of the SPI actually leads to a lower heating andloss rates.5.4.2 The Effect of Intensity StabilizationIn order to check if a reduction in the intensity noise reduces the atom loss during evaporationdue to heating, we used the active intensity stabilization system presented in Chapter 4 toreduce the intensity noise. This involved using an AOM together with the FPGA servo. The1005.4. Study0 0.5 1 1.5time (s)100120140160180200220240260280temperature (uK)Heating Rate in SPI at cross trap (10W set power)temperature at 10W (TOF)exponential fitFigure 5.2: heating rate of the atom cloud when SPI held at 10W. The heating rate correspondto a e-folding time of 1.9 s. this is also a screenshot not a proper plotanalog signal previously used to control the SPI power output was used as the setpoint for theFPGA servo.The effect of the active stabilization on the intensity noise can be seen in Figure 5.3. Theactive intensity stabilization has a finite bandwidth, but it is able to suppress the intensitynoise at the trap frequency to a much lower level. To investigate how the evaporation efficiencychanges as a result, a forced evaporation routine was developed to compare the evaporationwith and without active stabilization. The evaporation efficiency both with and without activestabilization was independently optimized by choosing the durations of a set of piecewise linearramps that optimized each linear stage in which the laser power dropped by a factor of 2.This crude optimization method was employed to perform a quick check to determine if activestabilization had any effect on the evaporation efficiency.The evaporation efficiency of the free-running SPI laser and the SPI laser with noise sup-pression is shown in Figure 5.4. The predicted number versus final power (given in Eqn. 5.9) foran efficient evaporation (η = 10) is included in this plot for reference. The active stabilizationis observed to provide a slight improvement in atom numbers down to 12 W, but the efficiencydrops sharply compared to the unstabilized case for powers below 10 W. This drop was notfurther investigated but may have been due to an instability in the servo at lower setpoints or1015.4. Study10 1 10 2 10 3 10 4 10 5Frequency (Hz)-5.5-5-4.5-4-3.5-3-2.5-2-1.5-1-0.5Relative Intensity Noise, log10SPI RIN at 5W and TOF at 10Wpassive noiseactiveHeating, temperature e folding time = 10 sHeating, temperature e folding time = 1 sHeating, temperature e folding time = 0.1 sTOF measurement at 10 W (radial)TOF measurement at 10 W (axial)Figure 5.3: Side by side comparison of RIN level responsible for measured heating rate andRIN of laser. The constant heating rate line show 20 dB/decade slope. It appears that activeintensity stabilization should reduce heating rate.due to noise features near to the trap frequency below 10 W not being evident in Figure 5.3since this was an in-loop rather than an out-of-loop measurementWe are not able to show whether active intensity stabilization with AOM is is sufficientat improvement evaporation efficiency. because the study opt for a simpler method to reduceintensity noise once the method is revealed. We speculate that the effect of active intensity sta-bilization is not necessarily thoroughly monitored during the experiment as the noise spectrumof the laser is taken at a single power with an in-loop measurement rather than an out-of-loopmeasurement at multipler power setting.5.4.3 Passive StabilityIn investigating the intensity stability of the 100 W SPI laser, we found that the passive stabilityof the SPI laser is better at high power setpoints. With the use of the SR780 VNA and theDET10A photodetector, the intensity noise measurement of the SPI laser is taken at variouspower settings between 1 W and 100 W. The results are shown in Figure 5.5 and reveal thatthis laser exhibits a relatively low RIN at high power setpoints and a much higher RIN at lowpowers. The data revealed a much more simple remedy to fix the evaporation efficiency. The1025.4. Study10 0 10 1 10 2SPI Set Power, (W)10 -110 0Normalized Atom NumberForced Evaporation in Dipole Trap with Intensity Stabilization2 = 10With IntensityStabilizationWithout IntensityStabilizationFigure 5.4: Evaporation efficiency of the sample without (yellow) and with (red) intensitystabilization. It is possible to see a small improvement in efficiency for end trap power of 50,25 and 12 W, but the evaporation still cannot reach the desired trap depth.solution was to operate the laser at a high intensity setpoint and to turn the power down usingan external AOM. This behavior also provides a rather clear explanation as to the drasticperformance difference between our two dipole trap lasers. By driving forced evaporationthrough lowering the power setpoint of the SPI laser, the RIN and ensemble heating wouldincrease counteracting the cooling of the sample and leading to a rather inefficient evaporation.1035.5. Future Work101 102 103 104 105Frequency (Hz)-6-5-4-3-2-1RINNoise spectral denistySPI Power = 1WSPI Power = 3WSPI Power = 12WSPI Power = 25WSPI Power = 50WSPI Power = 100WT e-folding time = 0.1 sT e-folding time = 1 sT e-folding time = 10 sFigure 5.5: passive stability of fiber laser at various power settings in RIN.5.4.4 Improved EvaporationWith a better knowledge of the RIN of the SPI laser, we were able to depreciate the use ofthe power setting on the SPI and instead use an AOM and a Direct Digital Synthesizer (DDS)with variable RF output to modify the depth of the trap. Indeed, the equipment was alreadyin place due to the previous work on active intensity stabilization. As shown in Figure 5.6,this method produced a highly efficient evaporation in the SPI down to very low trap depths.This one change yielded a factor of 4 improvement in atom number and eliminated the need totransfer the atoms to the IPG for the final evaporation stages.5.5 Future WorkSince the primary objective of this particular study was to improve the total atom numberat the lowest temperatures by improving the evaporation in the SPI and avoiding the needto transfer between the two dipole traps, the study ended once this objective was fulfilled.While some evidence was obtained that active intensity stabilization improved the evaporation,further investigation was unnecessary.Although the observed improvement in evaporation was only marginal, this study does not1045.5. Future WorkFigure 5.6: The atom number versus final power in the evaporation ramp using the SPI at nearits maximum power setup (where the passive stability of the laser is relatively good) and anAOM to control the power delivered to the atoms showed a highly efficient evaporation (η =10). The atom number shows an apparent drop when the ensemble is imaged at zero magneticfield since Feshbach molecules are forming at powers below 1 W and are not imaged at lowmagnetic fields. The images taken at high magnetic field show that the ensemble is still presentand still evaporating very efficiently down to powers below 100 mW.undermine the usefulness of active stabilization. One likely use of the IPG laser that was freedup from the new evaporation routine is in lattice-forming. As it was shown in the work by Blattet al, active intensity stabilization can improve the lifetime in a lattice trap where the passivestability of the laser, at 106 level in RIN, was improved to the 107 level with the use of anAOM-based noise-eater [59]. It should be noted that the active intensity stabilization discussedin the work have to undergo a redesign, particularly in the detection and front end section, toachieve a similar noise floor as the one presented in the work by Blatt el at.105Chapter 6ConclusionIn the quest to understand the theoretical and practical limitations of digital servos realized byFPGAs, this work involved the design and construction of FPGA servos based on two differentFPGA development platforms (Chapter 2): the DE2 and the DE3 by Altera. Both servosare shown to be capable of reaching loop delay of less than 200 ns (including conversion andcomputation delay) and are competitive against the published open-source design by NIST witha total delay of 320 ns [14] and the Digilock product by Toptica with a total delay of 200 ns[17]. The design based on the DE2 platform is consolidated onto a single daughtercard thatis compatible with most of the development platforms provided by Altera, such as the DE3through an adapter and the new FPGA platforms that have built-in HPS processors like theDE1-SOC.On the firmware side, this work included servo logic designs in the form of the IIR filterand other useful instrumentation tools like the AWG (Chapter 3). This work also exploredthe practical aspects of developing high speed signal processing modules in an FPGA with anemphasis on the verification of the each part of the implementation. Contributions are madeto the development of digital servos by optimizing each IIR filter to a single clock delay witha master clock speed of 50-75 MHz. This feature reduces the computation delay through theFPGA servo and reduces the overall latency through the FPGA servo. In addition, this workexplores an interesting and important limitation of discrete-time filters that is highly relevantto the present discussion. We explore the discrete frequency resolution of poles and zerosimplemented by an IIR filter, and an expression is derived for the frequency resolution in a firstorder IIR filter.This work also reports on a side-by-side comparison between an FPGA servo and a high-speed analog servo in closed-loop in both a self-lock configuration and an intensity stabilization106Chapter 6. Conclusionconfiguration (Chapter 4). In the comparisons, it is clear that the noise floor and the bandwidthof the servos play an important role in the closed-loop performance of the system. In our designof the FPGA servos, the overall noise floor of the servo has a best case scenario of 10 nV/√Hzat 1 kHz, when the input gain (gain between the servo input and ADC) is set to the maximum.This performance is similar to that of the analog servo. However, it is important to note thatthe noise floor of a FPGA servo is limited by the ADC at 177 nV/√Hz which means that alarge gain is needed between the servo input and the ADC. Also, the distribution of gain inthe FPGA servo loop has to be carefully tuned to produce the 10 nV/√Hz noise performance.The analog servo and the FPGA servo are also different in signal latency. Broadly speaking,a high-speed analog servo is faster than the FPGA servo designed in this work by >4 times.In this work, we benchmarked a fast commercial analog servo with closed-loop bandwidth ofof 10 MHz. In comparison, the FPGA servos produced by this thesis operate with closed-loopbandwidth of 2-2.5 MHz. In the present design, the signal conversion from the analog to thedigital domain and back again to the analog domain from the digital domain is substantial.The conversion delay is 80-120 ns and accounts for 40-60% of the total delay in the FPGAservo. The computation delay takes up a smaller fraction as a result of the speed optimizationin designing the IIR logic, with the cascade of two third order IIR filters costing between 23ns (DE2 servo) and 40 ns (DE3 servo). This account for 13 - 20% of the total delay. Thedelay in the analog signal conditioning stage in this design is only 30 ns (15% of the total)and other propagation delay, such as the time it takes for the digital signals to travel from theADC to the FPGA and then back to the DAC), makes up for the rest. We note that the totaldelay through an analog servo should be similar in magnitude to the delay through the analogfront-end of this FPGA servo with the use of similar op-amp technology. The delay in signalconversion and, to a lesser extent, the computational delay are the culprits in the additionaldelay in an FPGA servo. The longer total delay of the FPGA servo limits its use to closed-loopsystem with a target closed loop bandwidth of <1 MHz. However, even with this constraint,the FPGA servo is still able to satisfy a large number of closed-loop applications.This work also explores the use of a digital servo design and the quantization error thatresults. Some published works has already argued for and demonstrated that the quantizationerror of the ADC and the DAC does not degrade the performance of an FPGA servo [14],107Chapter 6. Conclusion[18]. The work done in thesis agree with these findings and found the noise level of the ADCin nV/√Hz almost more important. In this work, we observed two other quantization effects.The first is the quantization of the z-domain due the finite computation precision that the IIRcan be implemented in (Section 3.2.5). The second is the effect of computation precision onthe noise floor of the overall servo system. To the best of our knowledge, these effects have notbeen explicitly investigated previously.One application of an FPGA servo explored in this work is the intensity stabilization ofa laser for atom trapping. In particular, we examined the evaporation efficiency of atomsfrom an optical dipole trap with and without intensity stabilization (Chapter 5). The workfound preliminary evidence suggesting that intensity stabilization improved the evaporationefficiency; however, because a different solution was found further work to quantify this effectwas not performed. In particular, this study found that the passive intensity stability of thelaser is sufficient when the laser operates at a high power setting and thus forced evaporationwas performed using an external AOM to modify the beam intensity. The study does notundermine the usefulness of active intensity stabilization in scenaios where the passive stabilityof the laser is not sufficient [60]; nor does it undermine the usefulness of FPGA servos in AMOexperiments as demonstrated in many published works the use in active stabilization of laserfrequency and phase [5], [8], [14].The development of fast FPGA servo hardware and logic are only the the first steps towardswide spread use of digital servos in closed-loop laser control applications. This work argues thata well-designed FPGA servo is comparable with a high-performance analog servo as long as thetarget closed-loop bandwidth of the laser system is less than 1 MHz. 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This section covers the rest of technical details includingschematics, circuit layout, bill of material and a few mistakes on the board that needs to beworked around and be eliminated in future revisions.A.1 Power SupplyOperation of the servo daughter requires additional power supply besides the power supply onthe FPGA development board. A quiet ±13 ∼ 15V voltage is needed to power the analogfrontend and the current consumption depends on whether the signal conversion section, theADC and the DAC, is powered through the GPIO header on the FPGA development board orthrough the power supply input on the servo daughter card. The ADC and DAC on the servodaughter card consumes up to 600 mA of current, whereas the rest of the daughter card circuitconsumed up to 200 mA. When the ADC and the DAC is powered through the power supplyinput on the daughter card via a chain of linear regulators, the high current consumption ofthe ADC and the DAC cause the linear regulators to operate too close to their thermal limit sothis mode of operation is not recommended without additional thermal relief around the linearregulators. Powering the ADC and DAC via the 3.3 V supply on the GPIO header is moreconvenient, but can not guarantee noise performance.115A.2. Pending Design ChangesA.2 Pending Design ChangesThe next few pages provides the schematics, the layout and the bill of material for the servodaughter card and what is shown here is the very first iteration of the PCB design. All majorparts of the design works as intended, but a few quirks exist at the schematics level and needsto be worked around in the assembly process. The first is the polarity of the LDAC signal onthe slow DAC IC, DAC8734. The pull up resistor R504(A/B) on the LDAC signal should bemodified into a pull down with a near by ground pad on the PCB to enable latching the DACoutput by default. The second is a missing input signal to the DACMODE pin on the fast DACIC, AD8967. This can be fixed with a solder bridge between the DACMODE pin (48) to theadjacent A3V3 pin (47) which selects the independent access mode of the two DAC channelwithin the IC. The third mistake is the missing resistive divider between the slow DAC outputand some of the offset input of the analog frontend. The missing divider need to be inserted inplace of the resistor R309(A/B), likely in the form of a ”dead-bug”The above problems, including the thermal limitation around the linear regulators are tobe fixed in future revisions, but there is one other quirk of this design that is to stay. A carefulcomparison between the ADA card provided by Altera and the daughter servo card designedin this work should reveal that the pin mapping on the GPIO header of the two daughter cardare not the same. Because the pin mapping of the fast DAC is different between the two board,change of pin mapping is needed to port FPGA design for one daughter card to the other. Tomatch the servo daughter card to the ADA card means significant redesign of the PCB layoutand offer little benefit, this quirk of the design is to stay.A.3 Design FilesThe following page shows the schematics, layout and bill of material of the servo daughter card.The design is meant to be self-documenting, with a hierarchical schematics structure and deviceannotation that are meant to inform the schematics sub-page that the device is from.11611223344D DC CB BA A1Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 2086812016-06-07 5:40:02 PMC:\Users\Public\Documents\qdg_projects_repo\trunk\PRJ_servo_daughter_card\top.SchDocTitleSize: Number:Date:File:Revision:Sheet ofTime:LetterU_PowerPower.SchDocVIN_A+VIN_A-VIN_B+VIN_B-VREFADC_CLKAADC_CLKBADC_OTRAADC_OTRBADC_DA[0..13]ADC_DB[0..13]ADCADC.SchDocDAC_DA[0..13]DAC_DB[0..13]DAC_WRTADAC_CLKADAC_WRTBDAC_CLKB VOUT1VOUT2DACDAC.SchDocGAIN_INPUT VIN_A+VIN_A-OFFSET_INPUTMANUAL_OFFSETEXTERNAL_OFFSETVIN1SERVO_INVOCMIAF1Input_AF.SchDocGAIN_INPUTVOUT1OFFSET_INPUTSERVO_OUTOAF1Output_AF.SchDocVSLOW[1..4]SL_CSSL_SCLKSL_SDISL_SDOSL_LDACREF1Slow_DAC_w_REF.SchDocADC_OTRAADC_OTRB DAC_WRTBDAC_WRTAADC_CLKAADC_CLKBDAC_CLKADAC_CLKBMS_SCLKMS_SDOMS_LDACMS_SDISLAVE1_CSSLAVE2_CSDAC_DA[0..13]DAC_DB[0..13]ADC_DA[0..13]ADC_DB[0..13]InterfaceInterface.SchDocGAIN_INPUT VIN_A+VIN_A-OFFSET_INPUTMANUAL_OFFSETEXTERNAL_OFFSETVIN1SERVO_INVOCMIAF2Input_AF.SchDocGAIN_INPUTVOUT1OFFSET_INPUTSERVO_OUTOAF2Output_AF.SchDocVSLOW[1..4]SL_CSSL_SCLKSL_SDISL_SDOSL_LDACREF2Slow_DAC_w_REF.SchDocVA1VA2VA3VA4VB1VB2VB3VB4VA[1..4]VB[1..4]MANUAL_OFFSETIMO1Input_Manual_Offset.SchDocMANUAL_OFFSETIMO2Input_Manual_Offset.SchDoc512 3 4J2COAX-F512 3 4J6COAX-FJ4ABNC_DUALJ4BBNC_DUALAGNDAGNDAGNDAGNDVOUT1VOUT2VOUT1SERVO_OUT1SERVO_OUT2SERVO_OUT1512 3 4J1COAX-F512 3 4J5COAX-FJ3ABNC_DUALJ3BBNC_DUALAGNDAGNDAGNDVOUT2SERVO_OUT2AGNDVEXT1VEXT2VIN1VIN2J9ABNC_DUALJ9BBNC_DUAL512 3 4J7COAX-F512 3 4J11COAX-F512 3 4J13COAX-FAGNDAGNDAGNDAGNDAGNDSERVO_IN1VINVEXT1SERVO_IN1SERVO_IN2J10ABNC_DUALJ10BBNC_DUAL512 3 4J8COAX-F512 3 4J12COAX-F512 3 4J14COAX-FAGNDAGNDAGNDAGNDAGNDSERVO_IN2VIN2VEXT2VOCMADC_VREFU_VOCM_generateVOCM_generate.SchDocPIJ101PIJ102 PIJ103 PIJ104 PIJ105COJ1PIJ201PIJ202 PIJ203 PIJ204 PIJ205COJ2PIJ301PIJ302COJ3APIJ302PIJ3034BPIJ401PIJ402COJ4APIJ402PIJ4034BPIJ501PIJ502 PIJ503 PIJ504 PIJ505COJ5PIJ601PIJ602 PIJ603 PIJ604 PIJ605COJ6PIJ701PIJ702 PIJ703 PIJ704 PIJ705COJ7PIJ801PIJ802 PIJ803 PIJ804 PIJ805COJ8PIJ901PIJ902COJ9APIJ902PIJ9034BPIJ1001PIJ1002COJ10APIJ1002PIJ10034BPIJ1101PIJ1102 PIJ1103 PIJ1104 PIJ1105COJ11PIJ1201PIJ1202 PIJ1203 PIJ1204 PIJ1205COJ12PIJ1301PIJ1302 PIJ1303 PIJ1304 PIJ1305COJ13PIJ1401PIJ1402 PIJ1403 PIJ1404 PIJ1405COJ14NLSERVO0 NNLSERVO0 NNLSERVO0OUNLSERVO0OUNLVEXT1NLVEXT2NLVIN1NLVINNLVOUT1NLVOUNLVA010040NLVA1NLVA2NLVA3NLVA4NLVB0 0040NLVBNLVB2NLVBNLVB11711223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\DAC.SchDoc Drawn By:DAC_DA0DAC_DA1DAC_DA2DAC_DA[0..13] DAC_DA[0..13]DAC_DA3DAC_DA4DAC_DA5DAC_DA6DAC_DA7DAC_DA8DAC_DA10DAC_DA11DAC_DA12DAC_DA13DAC_DA9DAC_DB[0..13] DAC_DB[0..13]DAC_DB0DAC_DB1DAC_DB2DAC_DB3DAC_DB4DAC_DB5DAC_DB6DAC_DB7DAC_DB8DAC_DB10DAC_DB11DAC_DB12DAC_DB13DAC_DB9DAC_WRTADAC_WRTADAC_CLKADAC_CLKADAC_MODEDAC_SLEEPGAINCTRLFSADJ2FSADJ1100R102100150R104150100R103100150R105150DNPR100DNP2KR1062KDNPR101DNP0R10702KR1082K2KR1092K0.1uFC1080.1uFIOUTA1IOUTB1IOUTA2IOUTB2DB0-P1 (LSB)1DB1-P12DB2-P13DB3-P14DB4-P15DB5-P16DB6-P17DB7-P18DB8-P19DB9-P110DB10-P111DB11-P112DB12-P113DB13-P1 (MSB)14DCOM115DVDD116WRT1/IOWRT17CLK1/IQCLK18CLK2/IQRESET19WRT2/IQSET20DCOM221DVDD222DB0-P2 (LSB)23DB1-P224DB2-P225DB3-P226DB4-P227DB5-P228DB6-P229DB7-P230DB8-P231DB9-P232DB10-P233DB11-P234DB12-P235DB13-P2 (MSB)36SLEEP37ACOM38IOUTA2 39IOUTB2 40FSADJ241GAINCTRL42 REFIO 43FSADJ144IOUTB1 45IOUTA1 46AVDD47MODE48U100AD9767DAC_WRTBDAC_CLKBDAC_WRTBDAC_CLKBFSADJ2FSADJ1GAINCTRLDAC_SLEEPDAC_CLKADAC_CLKB+A3.3V +A3.3VAGND AGND AGND AGNDDGND DGND+D3.3V +D3.3V+A3.3V+D3.3VAGND DGNDAGND25R11050R11125R11250R113AGND AGNDAGND AGNDAGND+A3.3VDGND+D3.3V10uFC1000.1uFC10410uFC1011uFC1021uFC1030.1uFC1050.01uFC1060.01uFC1071uFC1091uFC1101uFC1110.01ufC1120.01uFC1130.01uFC114VOUT1VOUT2PIC10001PIC10002COC100PIC10101PIC10102COC101PIC10201PIC10202COC102PIC10301PIC10302COC103PIC10401PIC10402COC104PIC10501PIC10502COC105PIC10601PIC10602COC106PIC10701PIC10702COC107PIC10801PIC10802OC10PIC10901PIC10902OC10PIC11001PIC11002OC 1PIC11101PIC11102OC11PIC11201PIC11202OC 1PIC11301PIC11302OC 13PIC11401PIC11402OC 14PIR10001PIR10002COR100PIR10101PIR10102COR101PIR10201PIR10202COR10PIR10301PIR10302COR10PIR10401PIR10402COR104PIR10501PIR10502COR105PIR10601PIR10602COR106PIR10701PIR10702COR107PIR10801PIR10802COR108PIR10901PIR10902COR109PIR11001PIR11002COR110PIR11101PIR11102COR111PIR11201PIR11202COR 12PIR11301PIR11302COR11PIU10001PIU10002PIU10003PIU10004PIU10005PIU10006PIU10007PIU10008PIU10009PIU100010PIU100011PIU100012PIU100013PIU100014PIU100015PIU100016PIU100017PIU100018PIU100019PIU100020PIU100021PIU100022PIU100023PIU100024PIU100025PIU100026PIU100027PIU100028PIU100029PIU100030PIU100031PIU100032PIU100033PIU100034PIU100035PIU100036PIU100037PIU100038PIU100039PIU100040PIU100041PIU100042 PIU100043PIU100044PIU100045PIU100046PIU100047PIU100048COU100NLDAC0CLKPODAC0CLKANLDAC0CLKBPODAC0CLKBNLDAC0MONLDAC0SLNLDAC0W APODAC0WRTA NLDAC0WPODAC0WRTBNLFSADJ1NLFSADJ2NLGAINCTRLNLIOUTA1POVOUT1NLIOUTA2POVOUT2NLIOUTB1NLIOUTNLDAC0 A00 0130NLDAC0D 0PO 0 0000130NLDAC0DA1NLDAC0DA2NLDAC0D 3NLDAC0D 4NLDAC0D 5NLDAC0DA6NLDAC0DA7NLDAC0D 8NLDAC0D 9NLDAC0D 10NLDAC0DA11NLDAC0D 12NLDAC0D 13NLDAC0 B00 0130NLDAC0DPO 0 0000130NLDAC0DB1NLDAC0DNLDAC0DNLDAC0DNLDAC0DB5NLDAC0DB6NLDAC0DNLDAC0DNLDAC0DNLDAC0DB10NLDAC0DB11NLDAC0D 12NLDAC0D 13ODAC DA012456789AC0DAODAC DB012456789AC0DB11811223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\ADC.SchDoc Drawn By:AGND1VIN+_A2VIN-_A3AGND4AVDD5REFT_A6REFB_A7VREF8SENSE9REFB_B10REFT_B11AVDD12AGND13VIN-B14VIN+_B15AGND16AVDD17CLK_B 18DCS 19DFS 20PDWN_B 21OEB_B 22D0_B (LSB) 23D1_B 24D2_B 25D3_B 26D4_B 27DRGND28DRVDD29D5_B 30D6_B 31D7_B 32D8_B 33D9_B 34D10_B 35D11_B 36D12_B 37D13_B (MSB) 38OTR_B 39DRGND40DRVDD41D0_A (LSB) 42D1_A 43D2_A 44D3_A 45D4_A 46D5_A 47D6_A 48D7_A 49D8_A 50D9_A 51DRVDD52DRGND53D10_A 54D11_A 55D12_A 56D13_A (MSB) 57OTR_A 58OEB_A 59PDWN_A 60MUX_SELECT 61SHARED_REF 62CLK_A 63AVDD64U200AD9248AGND DGNDADC_DA0ADC_DA1ADC_DA2ADC_DA3ADC_DA4ADC_DA5ADC_DA6ADC_DA7ADC_DA8ADC_DA9ADC_DA10ADC_DA11ADC_DA12ADC_DA13ADC_OTRAADC_OEAADC_CLKAADC_POWERONMUX_SELECTSHARED_REFDCSDFSADC_OTRBADC_OEBADC_CLKBADC_POWERONADC_DB0ADC_DB1ADC_DB2ADC_DB3ADC_DB4ADC_DB5ADC_DB6ADC_DB7ADC_DB8ADC_DB9ADC_DB10ADC_DB11ADC_DB12ADC_DB130.1uFC21910uFC218AGNDAGND0.1uFC2140.1uFC217 10uFC2150.1uFC2160.1uFC2200.1uFC223 10uFC2210.1uFC222REFB_BREFT_BVIN_B-VIN_B+REFB_AREFT_AVIN_A+VIN_A-AGNDAGND+A3.3V +D3.3V100R200150R204100R201150R205ADC_CLKAADC_CLKBDGND DGND+D3.3V +D3.3V1KR208DNPR2161KR209DNPR217ADC_OEAADC_OEBAGND AGND+A3.3V +A3.3VDNPR2101KR218DNPR2111KR219DFSADC_POWERONAGND AGND+A3.3V +A3.3VDNPR2021KR206DNPR2031KR207DCSSHARED_REFDGND DGND+D3.3V +D3.3VVIN_A+VIN_A-VIN_B+VIN_B-AGND+A3.3VDGND+D3.3V10uFC2000.1uFC20410uFC2011uFC2021uFC2030.1uFC2050.01uFC2060.01uFC2071uFC2081uFC2091uFC2100.01uFC2110.01uFC2120.01uFC213ADC_CLKAADC_CLKBADC_OTRAADC_OTRBADC_DA[0..13]ADC_DB[0..13]ADC_DA[0..13]ADC_DB[0..13]VREFPIC20001PIC20002OC20PIC20101PIC20102COC20PIC20201PIC20202OC20PIC20301PIC20302OC20PIC20401PIC20402OC20PIC20501PIC20502OC20PIC20601PIC20602OC20PIC20701PIC20702OC20PIC20801PIC20802COC208PIC20901PIC20902COC209PIC21001PIC21002COC210PIC21101PIC21102COC211PIC21201PIC21202COC212PIC21301PIC21302COC213PIC21401PIC21402OC21PIC21501PIC21502COC215PIC21601PIC21602COC216PIC21701PIC21702OC21PIC21801PIC21802COC218PIC21901PIC21902COC219PIC22001PIC22002COC220PIC22101PIC22102COC221PIC22201PIC22202COC222PIC22301PIC22302COC223PIR20001PIR20002COR200PIR20101PIR20102COR201PIR20201PIR20202COR202PIR20301PIR20302COR203PIR20401PIR20402COR2PIR20501PIR20502COR20PIR20601PIR20602COR20PIR20701PIR20702COR20PIR20801PIR20802COR2PIR20901PIR20902COR20PIR21001PIR21002COR21PIR21101PIR21102COR21PIR21601PIR21602COR216PIR21701PIR21702COR217PIR21801PIR21802COR218PIR21901PIR21902COR219PIU20001PIU20002PIU20003PIU20004PIU20005PIU20006PIU20007PIU20008PIU20009PIU200010PIU200011PIU200012PIU200013PIU200014PIU200015PIU200016PIU200017PIU200018PIU200019PIU200020PIU200021PIU200022PIU200023PIU200024PIU200025PIU200026PIU200027PIU200028PIU200029PIU200030PIU200031PIU200032PIU200033PIU200034PIU200035PIU200036PIU200037PIU200038PIU200039PIU200040PIU200041PIU200042PIU200043PIU200044PIU200045PIU200046PIU200047PIU200048PIU200049PIU200050PIU200051PIU200052PIU200053PIU200054PIU200055PIU200056PIU200057PIU200058PIU200059PIU200060PIU200061PIU200062PIU200063PIU200064 COU20NLADC0CLKAPOAD 0CLKANLADC0CLKBPOAD 0CLKBNLADC0ONLADC0OEBNLADC0OTR POADC0OTRANLADC0OT POADC0OTRBNLADC0POWERNLDCSNLDFSNLMUX0SELPOVREFNLREFB0ANLREFB0NLREFT0ANLREFT0BNLSHARED0NLVIN0A0POVIN0A0NLVIN0A0POVIN0A0NLVIN0B0POVIN0B0NLVIN0B0POVIN0B0NLADC0DA0000130NLADC0DPO 0 0000130NLADC0DNLADC0DA2NLADC0DA3NLADC0DNLADC0DNLADC0DNLADC0DA7NLADC0DA8NLADC0DNLADC0DNLADC0DNLADC0DA12NLADC0DA13NLADC0 B00 0130NLADC0DPO 0 0000130NLADC0DB1NLADC0DB2NLADC0DNLADC0DNLADC0DNLADC0DNLADC0DB7NLADC0DNLADC0DNLADC0D 10NLADC0D 11NLADC0D 12NLADC0D 13OADC DA012456789DC DA 3OADC DB012456789DC DB 311911223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\Input_AF.SchDoc Drawn By:23174658U300AD829JR12345678GNDINU302AD603AR-IN1VOCM2VS+3+OUT 4-OUT 5VS-6/PD 7+IN8U301AD8137 270R305270R31356pC30256pC3041uFC3151uFC31310nFC31410nFC3161uFC3231uFC32110nFC32210nFC324+12V-12V+5V-5V+5V-5V+5V-5VAGNDAGNDAGNDGAIN_INPUTGAIN_CTRL18kR3211KR3241uFC325AGNDGAIN_CTRL0R307DNPR312AGND0R3020R308499R3111K1R3031K1R31425pFC30325pFC305AGNDAGND470R304470R3151K1R3161K1R3019p1C3019p1C3081KR3061KR3003pFC300HACK2R30950R310AGNDVIN_A+VIN_A-AGND 3pFC30625pFC307AGNDNULL1NULL2DNPR317DNPR319NULL2NULL1-12VR318DNPINPUT_AF_OUT1uFC31110nFC3121uFC31910nFC320+12V-12VAGNDOFFSET_INPUTDNPR320DNPR322MANUAL_OFFSETSERVO_INVIN1EXTERNAL_OFFSETVOCMPIC30001 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PIR32202COR32PIR32401PIR32402COR3PIU30001PIU30002PIU30003PIU30004 PIU30005PIU30006PIU30007PIU30008COU300PIU30101PIU30102PIU30103PIU30104PIU30105PIU30106PIU30107PIU30108COU301PIU30201PIU30202PIU30203PIU30204PIU30205PIU30206PIU30207PIU30208 COU302NLGAIN0CNLINPUT0AF0OUTPOVIN1POVIN0A0POVIN0A0POSERVO0INPOO FSET0INPUTPO XTERNAL0OFFSETPOGAIN0INPUTPO 0O FSETPOVOCMLNULNLNULL212011223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\Output_AF.SchDoc Drawn By:12345678GNDINU401AD603AR23174658U400AD829JRGAIN_INPUT18kR4081KR4121uFC407AGNDGAIN_CTRL+12V1uFC40310nFC404AGND-12V1uFC40910nFC410+5V1uFC40510nFC406AGND-5V1uFC41110nFC412AGNDGAIN_CTRL 0R402499R4051KR4031KR4061KR400+12V-12V3pFC400AGND0R401+5V-5V0R404VOUT1OFFSET_INPUT1K5R409401R4131uFC408AGNDOFFSET_CTRLOFFSET_CTRLAGND3pFC40125pFC402AGNDNULL1NULL2DNPR410DNPR414NULL2NULL1-12VR411DNPDNPR407AGND23174658U402DNP+24V+24V1uFC41510nFC416AGND-5V1uFC41710nFC418-5V1KR4171KR418100pFC414AGND100pFC413AGNDNULL3NULL4DNPR419DNPR421NULL4NULL3-5VR420DNP0R4160R415SERVO_OUTPIC40001 PIC40002COC400PIC40101PIC40102COC401PIC40201PIC40202COC402PIC40301PIC40302OC40PIC40401PIC40402COC40PIC40501PIC40502OC40PIC40601PIC40602OC40PIC40701PIC40702COC407PIC40801PIC40802COC408PIC40901PIC40902OC40PIC41001PIC41002COC41PIC41101PIC41102OC411PIC41201PIC41202OC41PIC41301PIC41302OC41PIC41401PIC41402OC41PIC41501PIC41502OC41PIC41601PIC41602OC41PIC41701PIC41702OC41PIC41801PIC41802OC41PIR40001 PIR40002COR400PIR40101 PIR40102COR401PIR40201 PIR40202COR402PIR40301PIR40302COR403PIR40401 PIR40402COR404PIR40501PIR40502COR405PIR40601 PIR40602COR406PIR40701PIR40702COR407PIR40801 PIR40802COR408PIR40901 PIR40902COR409PIR41001PIR41002COR410PIR4110CCWPIR4110CWPIR4110WCOR411PIR41201PIR41202COR412PIR41301PIR41302COR413PIR41401PIR41402COR41PIR41501 PIR41502COR415PIR41601 PIR41602COR416PIR41701PIR41702COR41PIR41801PIR41802COR418PIR41901PIR41902COR419PIR4200CCWPIR4200CWPIR4200WCOR420PIR42101PIR42102COR42PIU40001PIU40002PIU40003PIU40004 PIU40005PIU40006PIU40007PIU40008COU400PIU40101PIU40102PIU40103PIU40104PIU40105PIU40106PIU40107PIU40108 COU401PIU40201PIU40202PIU40203PIU40204 PIU40205PIU40206PIU40207PIU40208COU402NLGAIN0CTPOVOUT1POGAIN0INPUT PO ET0INPUTPO ERVO0OUTNLNULL1NLNULL2NLNULNLNULL4NLO FSET0CT12111223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\Slow_DAC_w_REF.SchDoc Drawn By:CS2SCLK3SDI4SDO5LDAC6RST7GPIO-08GPIO-19UNI/BIP-A10DGND11IOVDD13DVDD14VOUT-0 15RFB2-0 16RFB1-0 17SGND-0 18SGND-1 20RFB1-1 21RFB2-1 22VOUT-1 23AVDD26AVDD35AGND27AVSS28AVSS33REFGND-A29REF-A30REF-B31REFGNG-B32VMON 34VOUT-3 38RFB2-3 39RFB1-3 40SGND-3 41SGND-2 43RFB1-2 44RFB2-2 45VOUT-2 46AIN47UNI/BIP-B48NC1NC12NC19NC24NC25NC36NC37NC42U501DAC87340.1uFC50510uFC5031uFC5040.01uFC5060.1uFC51510uFC5131uFC5140.01uFC516+12V-12VAGND+12V -12VAGNDAGNDVSLOW1VSLOW2VSLOW3VSLOW4VSLOW[1..4]VSLOW[1..4]1KR503AGNDCSSCLKSDISDOLDACAINPOLARITY_APOLARITY_BRSTCSSCLKSDISDORSTPOLARITY_APOLARITY_BDNPR5071KR513DNPR5081KR514+D3.3V +D3.3VDGND DGND0R5100R5110R5120R506LDAC0R5161KR509DNPR515+D3.3VDGND1KR502HACK1R504+D3.3V+D3.3VSL_CSSL_SCLKSL_SDISL_SDOSL_LDACDGND+D3.3V +D5VAGND1KR505AGNDAGNDNCVIN2TEMP3GND4TRIM/NR 5VOUT 6NCNCU500REF5050+12VAGNDAGND10uFC501 0R50110uFC502AGND0R50047uFC500AGNDREFREFREFDGND+D3.3V1uFC5070.01uFC508DGND+D5V1uFC5090.01uFC510AGND+12V1uFC5110.01uFC512PIC50001PIC50002OC50PIC50101PIC50102COC501PIC50201PIC50202COC502PIC50301PIC50302OC50PIC50401PIC50402OC50PIC50501PIC50502OC50PIC50601PIC50602OC50PIC50701PIC50702OC50PIC50801PIC50802COC5PIC50901PIC50902OC50PIC51001PIC51002OC51PIC51101PIC51102COC51PIC51201PIC51202OC51PIC51301PIC51302OC51PIC51401PIC51402OC51PIC51501PIC51502OC51PIC51601PIC51602OC51PIR50001 PIR50002COR500PIR50101PIR50102COR50PIR50201PIR50202COR502PIR50301 PIR50302COR503PIR50401PIR50402COR504PIR50501PIR50502COR505PIR50601 PIR50602COR50PIR50701PIR50702COR50PIR50801PIR50802COR50PIR50901PIR50902COR50PIR51001 PIR51002COR510PIR51101 PIR51102COR511PIR51201 PIR51202COR512PIR51301PIR51302COR513PIR51401PIR51402COR514PIR51501PIR51502COR515PIR51601 PIR51602COR516PIU50001PIU50002PIU50003PIU50004PIU50005PIU50006PIU50007PIU50008COU500PIU50101PIU50102PIU50103PIU50104PIU50105PIU50106PIU50107PIU50108PIU50109PIU501010PIU501011PIU501012PIU501013 PIU501014PIU501015PIU501016PIU501017PIU501018PIU501019PIU501020PIU501021PIU501022PIU501023PIU501024PIU501025PIU501026PIU501027PIU501028 PIU501029PIU501030PIU501031 PIU501032PIU501033PIU501034PIU501035PIU501036PIU501037PIU501038PIU501039PIU501040PIU501041PIU501042PIU501043PIU501044PIU501045PIU501046PIU501047PIU501048COU501NLAINNLC\S\NLL\D\A\C\POSL0CSPOSL0SCLKPOSL0SDIPOSL0SDOPOSL0LDACNLPOLARITY0NLPOLARITY0B NLR\S\T\NLREFNLSCLNLSDINLSDONLVSLOW010040NLVSLOW1PO LOW010040NLVSLOW2NLVSLOW3NLVSLOW4OVSLOW12312211223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\Interface.SchDoc Drawn By:DAC_DA11DAC_DA10DAC_DA7DAC_DA6DAC_DA3DAC_DA2DAC_DB11DAC_DB10DAC_DB5DAC_DB4DAC_DB1DAC_DB0DAC_WRTBDAC_DA13DAC_DA12DAC_DA9DAC_DA8DAC_DA5DAC_DA4DAC_DA1DAC_DA0DAC_WRTADAC_DB13DAC_DB12DAC_DB9DAC_DB8DAC_DB7DAC_DB6DAC_DB3DAC_DB2ADC_OTRAADC_OTRBADC_DB2ADC_DB3ADC_DB6ADC_DB7ADC_DB10ADC_DB11ADC_DA2ADC_DA3ADC_DA6ADC_DA7ADC_DA10ADC_DA11ADC_DB0ADC_DB1ADC_DB4ADC_DB5ADC_DB8ADC_DB9ADC_DB12ADC_DB13ADC_DA0ADC_DA1ADC_DA4ADC_DA5ADC_DA8ADC_DA9ADC_DA12ADC_DA13ADC_OTRAADC_OTRBDAC_WRTBDAC_WRTAADC_CLKAADC_CLKBDAC_CLKADAC_CLKBADC_CLKAADC_CLKBDAC_CLKADAC_CLKBMS_SCLKMS_SDOMS_LDACMS_SDISLAVE1_CSSLAVE2_CSDGNDDGNDDAC_DA[0..13]DAC_DA[0..13]DAC_DB[0..13]DAC_DB[0..13]ADC_DA[0..13]ADC_DB[0..13]ADC_DA[0..13]ADC_DB[0..13]MS_SCLKMS_SDOSLAVE2_CSSLAVE1_CSMS_LDACMS_SDIInterface to DE21 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40J600GPIO1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40J602GPIOiADC_CHA ADC_OTRAADC_CLKAADC_DA[0..13]iADC_CHA iADC_CHAiADC_CHBiADC_CHBiADC_CHBiDAC_CHAiDAC_CHBiDAC_CHAiDAC_CHAiDAC_CHBiDAC_CHBADC_CLKBADC_OTRBDAC_DA[0..13]DAC_CLKADAC_WRTADAC_CLKBDAC_WRTBADC_DB[0..13]DAC_DB[0..13]PIJ60001 PIJ60002PIJ60003 PIJ60004PIJ60005 PIJ60006PIJ60007 PIJ60008PIJ60009 PIJ600010PIJ600011 PIJ600012PIJ600013 PIJ600014PIJ600015 PIJ600016PIJ600017 PIJ600018PIJ600019 PIJ600020PIJ600021 PIJ600022PIJ600023 PIJ600024PIJ600025 PIJ600026PIJ600027 PIJ600028PIJ600029 PIJ600030PIJ600031 PIJ600032PIJ600033 PIJ600034PIJ600035 PIJ600036PIJ600037 PIJ600038PIJ600039 PIJ600040COJ600PIJ60201 PIJ60202PIJ60203 PIJ60204PIJ60205 PIJ60206PIJ60207 PIJ60208PIJ60209 PIJ602010PIJ602011 PIJ602012PIJ602013 PIJ602014PIJ602015 PIJ602016PIJ602017 PIJ602018PIJ602019 PIJ602020PIJ602021 PIJ602022PIJ602023 PIJ602024PIJ602025 PIJ602026PIJ602027 PIJ602028PIJ602029 PIJ602030PIJ602031 PIJ602032PIJ602033 PIJ602034PIJ602035 PIJ602036PIJ602037 PIJ602038PIJ602039 PIJ602040COJ602NLADC0CLKPOADC0CLKANLADC0CLKBPOADC0CLKBNLADC0OTRAPOADC0OTRANLADC0OT POADC0OTRBNLDAC0CLKAPODAC0CLKANLDAC0CLKPODAC0CLKBNLDAC0WRTAPODAC0WRTANLDAC0WPODAC0WRTBNLMS0LDA POMS0LDACNLMS0SCLPOMS0SCLK NLMS0SDIPOM 0SDINLMS0SDOPOM 0SDONLSLAVE10CSPO LAVE10CSN SLAVE20CPO LAVE20CSNLADC0 A00 0130NLADC0D 0POADC0DA00 0130NLADC0DA1NLADC0D 2NLADC0D 3NLADC0D 4NLADC0D 5NLADC0D 6NLADC0DA7NLADC0D 8NLADC0DA9NLADC0DNLADC0DNLADC0D 12NLADC0D 13NLADC0 B00 0130NLADC0DB0POADC0DB00 0130NLADC0DB1NLADC0DNLADC0DNLADC0DNLADC0DNLADC0DNLADC0DB7NLADC0DNLADC0DB9NLADC0D 10NLADC0DNLADC0D 12NLADC0D 13NLDAC0 A00 0130NLDAC0D 0PODAC0DA00 0130NLDAC0D 1NLDAC0D 2NLDAC0D 3NLDAC0D 4NLDAC0D 5NLDAC0D 6NLDAC0D 7NLDAC0D 8NLDAC0D 9NLDAC0DNLDAC0DNLDAC0DNLDAC0DA13NLDAC0 B00 0130NLDAC0DPODAC0DB00 0130NLDAC0DNLDAC0DNLDAC0DNLDAC0DNLDAC0DNLDAC0DNLDAC0DNLDAC0DNLDAC0DNLDAC0D 10NLDAC0DNLDAC0D 12NLDAC0D 13O DC DA012456789C0DAO C DB0124567890DBO C DA0124567890DAO C DB0124567890DB12311223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\Power.SchDoc Drawn By:AGND/SHDN1GND2IN3ADJ 4OUT 5TAB/IN6U701LT3015/SHDN1IN2GND3OUT 4ADJ 5TAB/GND6U700LT1963VIN+VIN-12V10uFC7061uFC7090.01uFC71010uFC7111uFC7120.1uFC7130.1uFC7140.01uFC71510KR7001K2R70110uFC7271uFC7300.01uFC731 10uFC7221uFC7230.1uFC7240.1uFC7250.01uFC72612.1KR702100KR703HACK3L701HACK3L70410uFC70810uFC70710uFC72810uFC729AGNDAGNDAGNDAGNDAGND+12V-12VAGND/SHDN1GND2IN3ADJ 4OUT 5TAB/IN6U705LT3015/SHDN1IN2GND3OUT 4ADJ 5TAB/GND6U703LT196312V10uFC73910uFC7400.1uFC74110uFC7421uFC7430.1uFC7440.1uFC7450.01uFC7463K3R7051KR70710uFC75910uFC7600.1uFC761 10uFC7541uFC7550.1uFC7560.1uFC7570.01uFC75810KR70833KR710AGNDAGNDAGNDAGNDAGND+5V-5V+12V-12V/SHDN1IN2GND3OUT 4ADJ 5TAB/GND6U702LT196310uFC7320.1uFC73310uFC7341uFC7350.1uFC7360.1uFC7370.01uFC7382KR7041KR706AGNDAGND+12VAGND+A3.3VAGND+A3.3VHACK3L70010uFC70310uFC700HACK3L7020.1uFC7010.01uFC7020.1uFC7040.01uFC705DGND+D3.3V/SHDN1IN2GND3OUT 4ADJ 5TAB/GND6U704LT196310uFC7470.1uFC74810uFC7491uFC7500.1uFC7510.1uFC7520.01uFC7533K3R7091KR711AGNDAGND+12VAGND+A5VAGND+A5VHACK3L70310uFC71910uFC7160.1uFC7170.01uFC7180.1uFC7200.01uFC721DGND+D5VVIN_FILTERED+VIN_FILTERED-12J701Header 2123J700Header 3VIN+VIN-AGND AGND+24VPIC70001PIC70002OC70PIC70101PIC70102OC70PIC70201PIC70202OC70PIC70301PIC70302OC70PIC70401PIC70402OC70PIC70501PIC70502OC70PIC70601PIC70602COC706PIC70701PIC70702COC707PIC70801PIC70802COC708PIC70901PIC70902COC709PIC71001PIC71002COC710PIC71101PIC71102COC711PIC71201PIC71202COC712PIC71301PIC71302COC713PIC71401PIC71402COC714PIC71501PIC71502COC715PIC71601PIC71602OC71PIC71701PIC71702OC71PIC71801PIC71802OC71PIC71901PIC71902OC71PIC72001PIC72002OC72PIC72101PIC72102OC72PIC72201PIC72202COC722PIC72301PIC72302COC723PIC72401PIC72402COC724PIC72501PIC72502COC725PIC72601PIC72602COC726PIC72701PIC72702COC727PIC72801PIC72802COC728PIC72901PIC72902COC72PIC73001PIC73002COC730PIC73101PIC73102COC731PIC73201PIC73202OC73PIC73301PIC73302COC733PIC73401PIC73402OC734PIC73501PIC73502COC73PIC73601PIC73602OC73PIC73701PIC73702OC73PIC73801PIC73802OC73PIC73901PIC73902COC739PIC74001PIC74002OC74PIC74101PIC74102OC74PIC74201PIC74202COC74PIC74301PIC74302OC74PIC74401PIC74402OC74PIC74501PIC74502OC74PIC74601PIC74602OC74PIC74701PIC74702OC74PIC74801PIC74802OC74PIC74901PIC74902OC749PIC75001PIC75002COC75PIC75101PIC75102OC75PIC75201PIC75202OC75PIC75301PIC75302OC75PIC75401PIC75402COC75PIC75501PIC75502OC75PIC75601PIC75602OC75PIC75701PIC75702OC75PIC75801PIC75802OC75PIC75901PIC75902OC75PIC76001PIC76002OC76PIC76101PIC76102OC76PIJ70001PIJ70002PIJ70003COJ700PIJ70101PIJ70102COJ701PIL70001 PIL70002COL700PIL70101 PIL70102COL701PIL70201 PIL70202COL702PIL70301 PIL70302COL703PIL70401 PIL70402COL704PIR70001PIR70002COR700PIR70101PIR70102COR701PIR70201PIR70202COR702PIR70301PIR70302COR703PIR70401PIR70402COR70PIR70501PIR70502COR70PIR70601PIR70602COR70PIR70701PIR70702COR707PIR70801PIR70802COR708PIR70901PIR70902COR70PIR71001PIR71002COR71PIR71101PIR71102COR711PIU70001PIU70002PIU70003PIU70004PIU70005PIU70006COU700PIU70101PIU70102PIU70103PIU70104PIU70105PIU70106COU701PIU70201PIU70202PIU70203PIU70204PIU70205PIU70206COU702PIU70301PIU70302PIU70303PIU70304PIU70305PIU70306COU703PIU70401PIU70402PIU70403PIU70404PIU70405PIU70406COU70PIU70501PIU70502PIU70503PIU70504PIU70505PIU70506COU70NLVIN0FILTERED0NLVIN0FILTER 012411223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\Input_Manual_Offset.SchDoc Drawn By:NCVIN2TEMP3GND4TRIM/NR 5VOUT 6NCNCU801REF5050+12VAGNDAGND100pFC806 1KR804100pFC809AGND32674U800OPA735 or AD829+12V-12VAGND1KR800R803ValueAGND100pFC808AGND1KR801MANUAL_OFFSET1KR8021KR805100pFC807AGND100pFC802100pFC800100pFC801100pFC803100pFC804100pFC805+12V-12VAGNDPIC80001PIC80002COC800PIC80101PIC80102COC801PIC80201PIC80202COC802PIC80301PIC80302COC803PIC80401PIC80402COC804PIC80501PIC80502COC805PIC80601PIC80602COC80PIC80701PIC80702OC80PIC80801PIC80802COC808PIC80901PIC80902COC809PIR80001 PIR80002COR800PIR80101 PIR80102COR801PIR80201 PIR80202COR802PIR8030CCWPIR8030CWPIR8030WCOR803PIR80401PIR80402COR804PIR80501PIR80502COR80PIU80002PIU80003PIU80004PIU80006PIU80007 COU80PIU80101PIU80102PIU80103PIU80104PIU80105PIU80106PIU80107PIU80108COU801POM 0O FSET12511223344D DC CB BA ATitleNumber RevisionSizeA4Date: 2016-06-07 Sheet    ofFile: C:\Users\..\VOCM_generate.SchDoc Drawn By:NCVIN2TEMP3GND4TRIM/NR 5VOUT 6NCNCU901REF5050+12VAGNDAGND10uFC901 0R90210uFC902AGND6K8R90010uFC900AGND23174658 U900AD829JR3K3R903AGND+12V-12VVOCM0R901DNPR904ADC_VREF1uFC9030.1uFC9041uFC9050.1uFC906+12V-12VAGND1uFC9070.1uFC908+12VAGNDPIC90001PIC90002OC90PIC90101PIC90102OC90PIC90201PIC90202OC90PIC90301PIC90302OC90PIC90401PIC90402OC90PIC90501PIC90502OC90PIC90601PIC90602OC90PIC90701PIC90702OC90PIC90801PIC90802OC90PIR90001 PIR90002COR90PIR90101 PIR90102COR90PIR90201PIR90202COR9PIR90301PIR90302COR90PIR90401 PIR90402COR904PIU90001PIU90002PIU90003PIU90004 PIU90005PIU90006PIU90007PIU90008 COU900PIU90101PIU90102PIU90103PIU90104PIU90105PIU90106PIU90107PIU90108COU90P VOCMPOADC0VREF126PAC10002 PAC10001COC100PAC10102 PAC10101COC101PAC10202 PAC10201COC102PAC10302 PAC10301COC103PAC10402PAC10401COC104PAC10502PAC10501COC105PAC10602PAC10601COC106PAC10702PAC10701COC1078 8COC108PAC10902 PAC10901COC109PAC11002 PAC11001COC110PAC11102 PAC11101COC111PAC11202PAC11201COC112PAC11302PAC11301COC113PAC11402PAC11401COC114PAC20002PAC20001COC200PAC20102PAC20101COC201PAC20202PAC20201COC202PAC20302 PAC20301COC203PAC20402 PAC20401COC204PAC20502 PAC20501COC205PAC20602 PAC20601COC206PAC20702 PAC20701COC207PAC20802PAC20801COC208PAC20902PAC20901COC209PAC21002PAC21001COC210PAC21102 PAC21101COC211PAC21202 PAC21201COC212PAC21302 PAC21301COC213PAC21402PAC21401COC214PAC21502PAC21501COC215PAC21602PAC21601COC216PAC21702PAC21701COC217PAC21802PAC21801COC218PAC21902 PAC21901COC219PAC22002PAC22001COC220PAC22102PAC22101COC221PAC2220222COC222PAC22302PAC22301COC223PAC300A02 PAC300A01COC300APAC300B02 PAC300B01COC300BPAC301A02 PAC301A01COC301APAC301B02 PAC301B01COC301BPAC302A02 PAC302A01COC302APAC302B02 PAC302B01COC302BPAC303A02 PAC303A01COC303APAC303B02 PAC303B01COC303BPAC304A02PAC304A01COC304APAC304B02PAC304B01COC304BPAC305A02PAC305A01COC305APAC305B02PAC305B01COC305BPAC306A02PAC306A01COC306APAC306B02PAC306B01COC306BPAC307A02PAC307A01COC307APAC307B02PAC307B01COC307BPAC308A02 PAC308A01COC308APAC308B02 PAC308B01COC308BPAC311A02 PAC311A01COC311APAC311B02 PAC311B01COC311BPAC312A02 PAC312A01COC312APAC312B02 PAC312B01COC312BPAC313A02PAC313A01COC313APAC313B02PAC313B01COC313BPAC314A02PAC314A01COC314APAC314B02PAC314B01COC314BPAC315A02 PAC315A01COC315APAC315B02 PAC315B 1COC315BPAC316A02 PAC316A01COC316APAC316B02 PAC316B01COC316BPAC319A02 PAC319A01COC319APAC319B02 PAC319B01COC319BPAC320A02 PAC320A01COC320APAC320B02 PAC320B01COC320BPAC321A02 PAC321A01COC321APAC321B02 PAC321B01COC321BPAC322A02 PAC322A01COC322APAC322B02 PAC322B01COC322BPAC323A02PAC323A01COC323APAC323B02PAC323B01COC323BPAC324A02PAC324A01COC324APAC324B02PAC324B01COC324BPAC325A0PAC325A01COC325APAC325B0PAC325B01COC325BPAC400A02 PAC400A01COC400APAC400B02 PAC400B01COC400BPAC401A02PAC401A01COC401APAC401B02PAC401B01COC401BPAC402A02PAC402A01COC402APAC402B02PAC402B01COC402BPAC403A02 PAC403A01COC403APAC403B02 PAC403B01COC403BPAC404A02 PAC404A01COC404APAC404B02 PAC404B01COC404BPAC405A02PAC405A01COC405APAC405B02PAC405B01COC405BPAC406A02PAC406A01COC406APAC406B02PAC406B01COC406BPAC407A02PAC407A01COC407APAC407B02PAC407B01COC407BPAC408A02 PAC408A01COC408APAC408B02 PAC408B01COC408BPAC409A02 PAC409A01COC409APAC409B01PAC409B02OC409BPAC410A02 PAC410A01COC410APAC410B02 PAC410B01COC410BPAC411A02 PAC411A01COC411APAC411B02 PAC411B01COC411BPAC412A02 PAC412A01COC412APAC412B02 PAC412B01COC412BPAC413A02PAC413A01COC413APAC413B01 PAC413B02COC413BPAC414A02 PAC414A01COC414APAC414B01PAC414B02COC414BPAC415A02 PAC415A01COC415APAC415B01PAC415B02COC415BPAC416A02 PAC416A01COC416APAC416B01PAC416B02COC416BPAC417A02 PAC417A01COC417APAC417B01PAC417B02OC417BPAC418A02 PAC418A01COC418APAC418B01PAC418B02COC418BPAC500A02 PAC500A01COC500APAC500B02 PAC500B01COC500BPAC501A02PAC501A01COC501APAC501B02PAC501B01COC501BPAC502A02 PAC502A01COC502APAC502B02 PAC502B01COC502BPAC503A02PAC503A01COC503APAC503B02PAC503B01COC503BPAC504A02 PAC504A01COC504APAC504B02 PAC504B01COC504BPAC505A02PAC505A01COC505APAC505B02PAC505B01COC505BPAC506A02 PAC506A01COC506APAC506B02 PAC506B01COC506BPAC507A01 PAC507A02COC507APAC507B01 PAC507B02COC507BPAC508A01 PAC508A02COC508APAC508B01 PAC508B02COC508BPAC509A02PAC509A01COC509APAC509B01 PAC509B02COC509BPAC510A02PAC510A01COC510APAC510B02PAC510B01COC510BPAC511A02PAC511A01COC511APAC511B02PAC511B01COC511BPAC512A02PAC512A01COC512APAC512B02PAC512B01COC512BPAC513A02PAC513A01COC513APAC513B02PAC513B01COC513BPAC514A02PAC514A01COC514APAC514B02PAC514B01COC514BPAC515A02 PAC515A01COC515APAC515B02 PAC515B01COC515BPAC516A02 PAC516A01COC516APAC516B02 PAC516B01COC516BPAC70002PAC70001COC700PAC70102PAC70101COC701PAC70202PAC70201COC702PAC70302PAC70301COC703PAC70402PAC70401COC704PAC70502PAC70501COC705PAC70601PAC70602COC706PAC70702PAC70701COC707PAC70802PAC70801COC708PAC70902PAC70901COC709PAC71002PAC71001COC710PAC71102PAC71101COC711PAC71202PAC71201COC712PAC71302PAC71301COC713PAC71402PAC71401COC714PAC71502PAC71501COC715PAC71602PAC71601COC716PAC71702PAC71701COC717PAC71802PAC71801COC718PAC71902PAC71901COC719PAC72002PAC72001COC720PAC72102PAC72101COC721PAC72202PAC72201COC722PAC72302PAC72301COC723PAC72402PAC72401COC724PAC72502PAC72501COC725PAC72602PAC72601COC726PAC72701PAC72702COC727PAC72802PAC72801COC728PAC72902PAC72901COC729PAC73002PAC73001COC730PAC73102PAC73101COC731PAC73202PAC73201COC732PAC73302PAC73301COC733PAC73402PAC73401COC734PAC73502PAC73501COC735PAC73602PAC73601COC736PAC73702PAC73701COC737PAC73802PAC73801COC738PAC73901PAC73902COC739PAC74002PAC74001COC740PAC74102PAC74101COC741PAC74202PAC74201COC742PAC74302PAC74301COC743PAC74402PAC74401COC744PAC74502PAC74501COC745PAC74602PAC74601COC746PAC74702PAC74701COC747PAC74802PAC74801COC748PAC74902PAC74901COC749PAC75002PAC75001COC750PAC75102PAC75101COC751PAC75202PAC75201COC752PAC75302PAC75301COC753PAC75402PAC75401COC754PAC75502PAC75501COC755PAC75602PAC75601COC756PAC75702PAC75701COC757PAC75802PAC75801COC758PAC75901PAC75902COC759PAC76002PAC76001COC760PAC76102PAC76101COC761PAC800A02 PAC800A01COC800APAC800B02 PAC800B01COC800BPAC801A01PAC801A02COC801APAC801B01PAC801B02COC801BPAC802A01 PAC802A02COC802APAC802B01 PAC802B02COC802BPAC803A02PAC803A01COC803APAC803B02PAC803B01COC803BPAC804A02 PAC804A01COC804APAC804B02 PAC804B01COC804BPAC805A02 PAC805A01COC805APAC805B02 PAC805B01COC805BPAC806A02 PAC806A01COC806APAC806B02 PAC806B01COC806BPAC807A02 PAC807A01COC807APAC807B02 PAC807B01COC807BPAC808A02PAC808A01COC808APAC808B02PAC808B01COC808BPAC809A02 PAC809A01COC809APAC809B02 PAC809B01COC809BPAC90001PAC90002COC900PAC90101PAC90102COC901PAC90201PAC90202COC902PAC90301PAC90302COC903PAC90401PAC90402COC904PAC90501PAC90502COC905PAC90601PAC90602COC906PAC90701 PAC90702COC907PAC90801 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PAR419A01COR419APAR419B01PAR419B02COR419BPAR420A0CWPAR420A0WPAR420A0CCWCOR420APAR420B0CCWPAR420B0WPAR420B0CWCOR420BPAR421A02 PAR421A01COR421APAR421B02 PAR421B01COR421BPAR500A02 PAR500A01COR500APAR500B02 PAR500B01COR500BPAR501A02 PAR501A01COR501APAR501B02 PAR501B01COR501BPAR502A02 PAR502A01COR502APAR502B02 PAR502B01COR502BPAR503A02 PAR503A01COR503APAR503B02 PAR503B01COR503BPAR504A02 PAR504A01COR504APAR504B02 PAR504B01COR504BPAR505A02PAR505A01COR505APAR505B02PAR505B01COR505BPAR506A02 PAR506A01COR506APAR506B02 PAR506B01COR506BPAR507A02 PAR507A01COR507APAR507B02 PAR507B01COR507BPAR508A02 PAR508A01COR508APAR508B02 PAR508B01COR508BPAR509A02 PAR509A01COR509APAR509B02 PAR509B01COR509BPAR510A02 PAR510A01COR510APAR510B02 PAR510B01COR510BPAR511A02 PAR511A01COR511APAR511B02 PAR511B01COR511BPAR512A02 PAR512A01COR512APAR512B02 PAR512B01COR512BPAR513A02PAR513A01COR513APAR513B02PAR513B01COR513BPAR514A02PAR514A01COR514APAR514B02PAR514B01COR514BPAR515A02PAR515A01COR515APAR515B02PAR515B01COR515BPAR516A02 PAR516A01COR516APAR516B02 PAR516B01COR516BPAR70002PAR70001COR700PAR70102PAR70101COR701PAR70202PAR70201COR702PAR70302PAR70301COR703PAR70402PAR70401COR704PAR70502PAR70501COR705PAR70602PAR70601COR706PAR70702PAR70701COR707PAR70802PAR70801COR708PAR70902PAR70901COR709PAR71002PAR71001COR710PAR71102PAR71101COR711PAR800A02 PAR800A01COR800APAR800B02 PAR800B01COR800BPAR801A02 PAR801A01COR801APAR801B02 PAR801B01COR801BPAR802A02PAR802A01COR802APAR802B02PAR802B01COR802BPAR803A0CWPAR803A0WPAR803A0CCWCOR803APAR803B0CWPAR803B0WPAR803B0CCWCOR803BPAR804A02 PAR804A01COR804APAR804B02 PAR804B01COR804BPAR805A02 PAR805A01COR805APAR805B02 PAR805B01COR805BPAR90001PAR90002COR900PAR90101 PAR90102COR901PAR90201 PAR90202COR902PAR90301PAR90302COR903PAR90401PAR90402COR904PAU10001PAU10002PAU10003PAU10004PAU10005PAU10006PAU10007PAU10008PAU10009PAU100010PAU100011PAU100012PAU100013PAU100014PAU100015PAU100016PAU100017PAU100018PAU100019PAU100020PAU100021PAU100022PAU100023PAU100024PAU100025PAU100026PAU100027PAU100028PAU100029PAU100030PAU100031PAU100032PAU100033PAU100034PAU100035PAU100036PAU100037PAU100038PAU100039PAU100040PAU100041PAU100042PAU100043PAU100044PAU100045PAU100046PAU100047PAU100048COU100PAU200016PAU200015PAU200014PAU200013PAU200012PAU200011PAU200010PAU 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PAU90006 PAU90007 PAU90008PAU90004 PAU90003 PAU90002 PAU90001COU900PAU90105 PAU90106 PAU90107 PAU90108PAU90104 PAU90103 PAU90102 PAU90101COU901C3 3B450742345603 A3 B13125 1130788 093 0B5 0ABB0223344A900901120910025347809100 100B23BC321B2347875456789B2103 A3 B1B5005 522356189031813 0BB55 5A90002000000000000000000000000000009001062734562 22233445 5556 6667 7778 88899110 J110J1101102 2223 3334 4442A1003 0B 3 B115 0AB BBBBBB0 02 23 34 45A1BB100 100100100100100100100100100100100100100100 100 100 100100100100100100100100100100100100100100 100100 100002100 100B100 1003 B11009J1122410013100100 100B0000100003 A3 A3 0B3 3 A5 0A9009011 15 0B02354AA A9010033180B1 3180 B1BBB BBBBB7984635B B B BBB BB3410610027127A.3. Design FilesTable A.1: The bill of material of the servo daughter cardDesignator Values Digikey Number QuantityC100, C101, C200, C201,C215, C218, C221, C500A,C500B, C501A, C501B,C502A, C502B, C503A,C503B, C513A, C513B,C700, C703, C707, C708,C711, C716, C719, C722,C728, C729, C732, C734,C740, C742, C747, C749,C754, C760, C900, C901,C90210uF 311-1459-1-ND 38Continued on next page128A.3. Design FilesTable A.1 – continued from previous pageDesignator Values Digikey Number QuantityC102, C103, C109, C110,C111, C202, C203, C208,C209, C210, C311A, C311B,C313A, C313B, C315A,C315B, C319A, C319B,C321A, C321B, C323A,C323B, C325A, C325B,C403A, C403B, C405A,C405B, C407A, C407B,C408A, C408B, C409A,C409B, C411A, C411B,C415A, C415B, C417A,C417B, C504A, C504B,C507A, C507B, C509A,C509B, C511A, C511B,C514A, C514B, C709, C712,C723, C730, C735, C743,C750, C7551 uF 399-1284-1-ND 58Continued on next page129A.3. Design FilesTable A.1 – continued from previous pageDesignator Values Digikey Number QuantityC104, C105, C108, C204,C205, C214, C216, C217,C219, C220, C222, C223,C505A, C505B, C515A,C515B, C701, C704, C713,C714, C717, C720, C724,C725, C733, C736, C737,C741, C744, C745, C748,C751, C752, C756, C757,C761, C904, C906, C9080.1 uF 1276-1003-1-ND 39C106, C107, C112, C113,C114, C206, C207, C211,C212, C213, C506A, C506B,C508A, C508B, C510A,C510B, C512A, C512B,C516A, C516B, C702, C705,C710, C715, C718, C721,C726, C731, C738, C746,C753, C7580.01uF 311-1136-1-ND 32C300A, C300B, C306A,C306B, C400A, C400B,C401A, C401B3 pF 399-1107-1-ND 8C301A, C301B, C308A,C308B9.1 pF 311-1098-1-ND 4C302A, C302B, C304A,C304B56 pF 1276-1833-1-ND 4Continued on next page130A.3. Design FilesTable A.1 – continued from previous pageDesignator Values Digikey Number QuantityC303A, C303B, C305A,C305B, C307A, C307B,C402A, C402B25 pF 1276-2621-1-ND 8C312A, C312B, C314A,C314B, C316A, C316B,C320A, C320B, C322A,C322B, C324A, C324B,C404A, C404B, C406A,C406B, C410A, C410B,C412A, C412B, C416A,C416B, C418A, C418B10 nF 311-1136-1-ND 24C413A, C413B, C414A,C414B, C800A, C800B,C801A, C801B, C802A,C802B, C803A, C803B,C804A, C804B, C805A,C805B, C806A, C806B,C807A, C807B, C808A,C808B, C809A, C809B100 pF 399-1122-1-ND 30C706, C727, C739, C759 10 uF PCE3914CT-ND 4J3, J4, J9, J10 BNC DUAL ACX1655-ND 4J600, J602 GPIO OR1153-ND 2R102, R103, R200, R201 100 Ω 311-100CRCT-ND 4R104, R105, R204, R205 150 Ω 311-150CRCT-ND 4R106, R108, R109, R704 2 kΩ 311-2.00KCRCT-ND 4Continued on next page131A.3. Design FilesTable A.1 – continued from previous pageDesignator Values Digikey Number QuantityR107, R302A, R302B,R307A, R307B, R308A,R308B, R401A, R401B,R402A, R402B, R404A,R404B, R415A, R415B,R416A, R416B, R500A,R500B, R501A, R501B,R506A, R506B, R510A,R510B, R511A, R511B,R512A, R512B, R516A,R516B, R901, R9020 311-0.0ARCT-ND 33 ΩR110, R112 25 Ω 311-24.9CRCT-ND 2R111, R113, R310A, R310B 50 Ω P49.9CCT-ND 4Continued on next page132A.3. Design FilesTable A.1 – continued from previous pageDesignator Values Digikey Number QuantityR206, R207, R208, R209,R218, R219, R300A, R300B,R306A, R306B, R324A,R324B, R400A, R400B,R403A, R403B, R406A,R406B, R412A, R412B,R417A, R417B, R418A,R418B, R502A, R502B,R503A, R503B, R504A,R504B, R505A, R505B,R509A, R509B, R513A,R513B, R514A, R514B,R706, R707, R711, R800A,R800B, R801A, R801B,R802A, R802B, R804A,R804B, R805A, R805B1k Ω 311-1.00KCRCT-ND 50R301A, R301B, R303A,R303B, R314A, R314B,R316A, R316B1.1 kΩ 311-1.10KCRCT-ND 8 ΩR304A, R304B, R315A,R315B470 Ω 311-470CRCT-ND 4R305A, R305B, R313A,R313B270 Ω 311-270CRCT-ND 4R311A, R311B, R405A,R405B499 Ω 311-499CRCT-ND 4Continued on next page133A.3. Design FilesTable A.1 – continued from previous pageDesignator Values Digikey Number QuantityR321A, R321B, R408A,R408B18 kΩ 311-18.0KCRCT-ND 4R409A, R409B 1.5 kΩ 311-1.50KCRCT-ND 2R413A, R413B 401 Ω 311-402CRCT-ND 2R700, R708 10 kΩ 311-10.0KCRCT-ND 2R701 1.2 kΩ 311-1.20KCRCT-ND 1R702 12.1 kΩ 311-12.1KCRCT-ND 1R703 100 kΩ 311-100KCRCT-ND 1R705, R709, R903 3.3 kΩ 311-3.30KCRCT-ND 3R900 6.8 kΩ 311-6.8KARCT-ND 1R710 33 kΩ 311-33.0KCRCT-ND 1U300A, U300B, U400A,U400B, U800A, U800B, U900AD829JR AD829JRZ-ND 7U301A, U301B AD8137 AD8137YRZ-REEL7CT-ND 2U302A, U302B, U401A,U401BAD603AR AD603ARZ-REEL7CT-ND 4U500A, U500B, U801A,U801B, U901REF5050 296-22211-5-ND 5U700, U702, U703, U704 LT1963 LT1963AEQ#TRPBFCT-ND 4U701, U705 LT3015 LT3015EQ#PBF-ND 2U100 AD9767 1U200 AD9248 1U501A, U501B DAC8734 2J1, J2, J5, J6, J7, J8, J11,J12, J13, J14COAX-F 10J700 Header 3 1Continued on next page134A.3. Design FilesTable A.1 – continued from previous pageDesignator Values Digikey Number QuantityJ701 Header 2 1135Appendix BThe Variable AttenuatorThe variable RF attenuator used for intensity control in Chapter 4 and Chapter 5 is constructedfor general use in the lab. The characteristics of this variable attenuator such as the speed ofthe variable attenuator and the relationship between input voltage and RF transmission iscovered in Section 4.2.3. This section covers the finer technical details, such as special assemblyinstructions and pending design changes.B.1 Design Details and Pending ChangesThe variable attenuator is designed around the MAAVSS0006 IC. Because the IC is not avail-able commercially in a package that is convenient to use, a PCB and enclosure is designed tohost the IC. This allows the variable attenuator to have a BNC interface. In this design, twovariable attenuating channels are designed into each package and they are mean to be used incascade mode to achieve modulation range of 60-70 dB. The device need a quiet ±13 − 15 Vpower supply, supplied through a 5-pin mini-XLR connector. The pin-out of this connector iscompatible with the standard power supply standard in the QDG lab.The design document presented here is the second PCB version of the variable attenuatordesign. It fixed various problem in the original PCB design although some problem still remains.One mistakes at the schematics level needs to be corrected in future revision and it isthe compensation scheme of the AD829. The compensation capacitor, C15 and C16 in theirrespective channels are incorrectly attached to the Pin 8 of the AD829, rather, it should beattached to Pin 5. The mistake is patched by soldering C15 and C16 between Pin 5 of therespective op-amp and a nearby via on the ground plane, but it should be fixed as the patchadd additional processing step to the design. While fixing this mistake, it is also a good chanceto try out the current compensation scheme, as the work found the current compensation scheme136B.2. Calibrationto be typically faster than the voltage compensation scheme. Section 4.2.3 shows evidence thatthe circuit around AD829 is the bottleneck in speed so such a change has the potential toimprove modulation speed. The change is very simple and should not disturb the layout elsewhere on the PCB.B.2 CalibrationEach variable attenuator has a different relationship between its input control voltage and theRF transmission. This can be observed in Figure 4.10 and we did not look into the cause ofthis variable. Thus, each variable attenuator needs to be calibrated. It may help to use thepotentiometer R5 and R10 to add an offset to the input voltage so that the variable attenuatortransition from “on” to “off” between 0 to 0.5 V.B.3 AssemblyIn the second version of the design (design files are included in later part of this section), allthe connectors are soldered to the PCB and can be fastened to the removable panel on theenclosure for extra security. The panels can be machined from a flat sheet of metal in a waterjet machine. Once the PCB is soldered and calibrated, the assembly is complete by sliding thePCB into the existing card guide in the commercial enclosure and attaching the panels. Theeasiest way to do this is to compress the enclosure on a vise to prevent the PCB from stickingto card guide.B.4 Design FilesThe design documents presented here, the schematics, PCB layout, the bill of material and thepanel design is sufficient to reproduce the variable attenuator design.13711223344D DC CB BA ATitleNumber RevisionSizeADate: 2016-06-07 Sheet    ofFile: C:\Users\..\VariableAttenuatorBoard.SchDocDrawn By:23647185U1Op AmpR31kR21kR510kGND15V-15V15V-15VGND GNDP2BNCP1BNCP3BNCGNDGNDGNDRFIN1GND 2RFOUT 3GND4VC5MAAVSS0006U20.1uFC80.1uFC1215VGND-15V0.1uFC40.1uFC1015VGND-15V23647185U3Op Amp1KR8Res31KR7Res3R1010kGND15V-15V15V-15VGND GNDP5BNCP4BNCP6BNCGNDGNDGNDRFIN1GND 2RFOUT 3GND4VC5MAAVSS0006U415V-15VGND100pFC13Cap SemiGND100pFC14Cap SemiGND+15V1+5V2GND5-5V3-15V4P7QDG Power Conn7pFC15Cap SemiGND7pFC16Cap SemiGNDR14kR64k0.1uFC17Cap Semi0.1uFC18Cap SemiGNDGND10uHL1Inductor10uHL2Inductor0.1uFC10.1uFC2GNDGND10uFC910uFC310uFC710uFC11PIC101PIC102OC1PIC201PIC202COC2PIC301PIC302COC3PIC401PIC402COC4PIC701PIC702COC7PIC801PIC802COC8PIC901PIC902COC9PIC1001PIC1002OC1PIC1101PIC1102OC1PIC1201PIC1202OC12PIC1301PIC1302COC13PIC1401PIC1402OC1PIC1501PIC1502COC15PIC1601PIC1602COC16PIC1701PIC1702COC17PIC1801PIC1802COC18PIL101 PIL102COL1PIL201 PIL202COL2PIP101PIP102COP1PIP201PIP202COP2PIP301PIP302COP3PIP401PIP402COP4PIP501PIP502COP5PIP601PIP602COP6PIP701PIP702PIP703PIP704PIP705COP7PIR101PIR102COR1PIR201PIR202COR2PIR301 PIR302COR3PIR50CCWPIR50CWPIR50WCOR5PIR601PIR602COR6PIR701PIR702COR7PIR801 PIR802COR8PIR100CCWPIR100CWPIR100WCOR10PIU101PIU102PIU103PIU104PIU105PIU106PIU107PIU108COU1PIU201PIU202PIU203PIU204PIU205COU2PIU301PIU302PIU303PIU304PIU305PIU306PIU307PIU308COU3PIU401PIU402PIU403PIU404PIU405COU4138PAC101PAC102COC1PAC201PAC202COC2PAC302PAC301COC3PAC402PAC401COC4PAC702PAC701COC7PAC802PAC801COC8PAC902PAC901COC9PAC1002PAC1001COC10PAC1102PAC1101COC11PAC1202PAC1201COC12PAC1302PAC1301COC13PAC1402PAC1401COC14PAC1501PAC1502COC15PAC1601PAC1602COC16PAC1701PAC1702COC17PAC1801PAC1802COC18PAL101 PAL102COL1PAL201PAL202COL2PAP101 PAP102COP1PAP201PAP202COP2PAP301 PAP302COP3PAP401 PAP402COP4PAP501PAP502COP5PAP601 PAP602COP6PAP705PAP704PAP703 PAP702PAP701PAP70NCCOP7PAR101PAR102COR1PAR202PAR201COR2PAR302PAR301COR3PAR50CWPAR50WPAR50CCWCOR5PAR601PAR602COR6PAR702PAR701COR7PAR802PAR801COR8PAR100CWPAR100WPAR100CCWCOR10PAU101PAU102PAU103PAU104PAU108PAU107PAU106PAU105COU1PAU205 PAU204PAU203PAU202PAU201COU2PAU301PAU302PAU303PAU304PAU308PAU307PAU306PAU305COU3PAU405 PAU404PAU403PAU402PAU401COU4L2C150678L2 R6C15678R6139B.4. Design FilesTable B.1: The bill of material of the variable attenuator unit.ElectricalDesignator Values Manufacturer Part Number QuantityU2, U4 Variable attenuator MAAVSS0006TR-3000 2U1, U3 AD829 AD829JRZ 2R2, R3, R7, R8 1k RC0805FR-071KL 4R1, R6 4.02k RC0402FR-074K02L 2R5, R10 10k SM-42TW103 2P1, P2, P3, P4,P5, P6BNC 1-1337543-0 6P7 Mini-XLR TRAPC5MX 1C13, C14 100pF C0805C101J5GACTU 2C15, C16 7pF CL21C070CBANNNC 2C3, C9, C7, C11 10uF GRM21BR61C106KE15K 4C1, C2, C4, C10,C8, C12, C17,C1810uF CL21B104KBCNNNC 8L1, L2 100uH LBR2012T100K 2MechanicalEnclosure - EX-4500 1140Appendix CRegister Address of FPGAPeripheralThe SOC design FPGA servo is composed of an MCU embedded in the FPGA and a fewspecialized modules for data processing. The MCU specializes in communication tasks suchas processing the commands between the PC and the servo and the coordination between themodules. The specialized modules handle high-speed signal processing tasks that require theflexibility of the FPGA to implement different logical structures.When generating an SOC, each module instantiated in the SOC are given a unique address.These addresses are used by the MCU to access the modules and each parameter in a specializedmodule can be accessed at a fixed offset from the base address. The offset addresses of theseparemeters are listed in Table C.1 - C.5. In an SOC that contains multiple IIR filters, eachfilter is given a unique base address.The advantage of this design scheme is flexibility and portability. Each specialized modulecan be designed and tested as a unit. To expand an FPGA servo design from a single IIR filterper channel to 3 IIR filter configured in cascade, the work only involves editing the configurationof the SOC to instantiate more IIR filters and editing the command interface in the MCU tomake sure that the PC can control the newly added IIR modules.It is important to note that although the Serial Peripheral Interface (SPI) module used tocontrol the slow DAC is a very general structure generated from Altera toolbox, the design inMCU needs to take into account the command structure of the slow DAC (each command tothe slow DAC is 3 Byte long). Because two ICs are connected in the daisy-chain fashion, inorder to talk the second IC in the chain, the MCU must issue 3 bytes carrying the commandintended for the second IC and the immediately issue another 3 Bytes (could be just a No141Appendix C. Register Address of FPGA PeripheralOperation (NOP) command) in order to prompt the first IC in the chain to relay the first 3bytes to the second IC.Table C.1: The address at which the IIR coefficients can be accessed in the general purposeIIR filter tested on the DE2 FPGA. The coefficients are signed.Register Address Register Function Format0 B 0 Q5.101 B 1 Q5.102 B 2 (If used) Q5.103 B 3 (If used) Q5.104 A 1 Q5.105 A 2 (If used) Q5.106 A 3 (If used) Q5.10Table C.2: The address at which the IIR coefficients can be accessed in the IIR filter designedfor the DE3 FPGA.Register Address Register Function Format0 B 0 Q3.281 B 1 Q3.282 B 2 (If used) Q3.283 B 3 (If used) Q3.284 A 1 Q3.285 A 2 (If used) Q3.286 A 3 (If used) Q3.28Table C.3: The register address of the FIR filter.Register Address Register Function Format0 B 0 Q5.101 B 1 Q5.102 B 2 (If used) Q5.103 B 3 (If used) Q5.104 B 4 (If used) Q5.105 B 5 (If used) Q5.106 B 6 (If used) Q5.10142Appendix C. Register Address of FPGA PeripheralTable C.4: The register address for the SPI module that is used to control the slow DACs in theFPGA servo based on the DE2 and the custom-made servo daughtercard. In the daughtercard,two ICs are connected in a daisy chain fashion. To communicate to the second IC in the chain,data has to be sent out in multiples of 3 bytes. The SPI module is generated from Altera’stoolbox.Register Address Register Function Format0 CPU Read U81 CPU Write U82 SPI Status 1-bit3 SPI Control 1-bit4 - -5 Slave Select 1-bit6 End of Packet 1-bitTable C.5: The register address of the AWG moduleRegister Address Register Name Format0 Ramp Inc U321 Ramp Max U322 Ramp Min U323 Ramp Prescaler U164 A 0 Q5.105 A 1 Q5.106 A 2 Q5.107 A 3 Q5.108 A 4 Q5.10143Appendix DPC-Side SoftwareThe PC-side software is responsible for generating the IIR coefficients, AWG coefficients andproviding a Graphical User Interface (GUI) for the FPGA servo user. The majority of the PC-side software including the GUI is developed in MATLAB. However, the design can be portedinto a different environment as the commands to the FPGA is well defined and non-proprietary.D.1 Command FormatThe command interface of the FPGA exposed control to modules in the SOC as setting thatcan be accessed at unique addresses. The address to the setting is defined in the code thatrun in the MCU where the commands are interpreted. The setting from different module aretypically assigned a unique offset. To access the setting the keywords “set”, “get” and “print”are used, with the format like “keyword address (value)”. For example, a dual channel FPGAservo with a single IIR filter maybe need a command “set 0 1024” and “set 16 1024” to set theB0 of the IIR filter for the first servo channel and the second servo channel respectively.D.2 IIR Coefficients and Screening of Transfer FunctionsBecause the IIR filter has limited resolution, the PC-side software find the nearest transferfunction that the FPGA servo can implement and compares it to the transfer function that theuser requested. The software leaves it up to the user to make sure that the transfer functionimplemented by the hardware does not cause instability in the loop.For the PC-side software to make this comparison correctly a few parameters need to berecorded correctly in PC-side software. The important parameters are the clock speed of the IIRlogic (not to be confused with clock speed of the ADC or the DAC which can be different), the144D.2. IIR Coefficients and Screening of Transfer Functionsresolution of the IIR coefficients that is implemented in the FPGA servo (the common formatsare Q5.10 and Q3.28) and how the IIR filters are cascade. The PC side program also needs toknow the format of the commands and the address that each coefficient can be accessed at (thisis not be confused with the location where these coefficients are stored in the MCU’s memoryspace).Currently, there is no way of knowing the exact configuration of IIR filters that is pro-grammed in the FPGA without accessing the source code that describes the FPGA circuitry.This can be a source of confusion when FPGA servos with different IIR configurations arepresent. We currently combat this problem with the use of unique system ID which is a periph-eral generated by the Altera toolbox which receives a unique timestamp every time the SOCis regenerated. The system ID peripheral is also given a device ID to differentiate IIR filterdesigned for different FPGAs.This method still requires access to the source code to make sure that the program on thePC and inside the MCU in the FPGA are compatible with the FPGA design. If the developermake sure to only release one servo design for general use then only one PC side programneeds to be released and no compatibility issue would surface. In the case where multiple servodesigns are needed, a comprehensive way of fixing this is to add special command in the MCUto allow the FPGA servo to inform any potential PC host its underlying IIR filter structure.The PC side program are then required to query this information from the FPGA servo andadapt its tuning interface accordingly.To illustrate the importance of this screening process, an example output of the tuninginterface is shown in Figure D.1. Here the tuning interface is “hard-coded” to interface withan FPGA servo where the underlying FPGA logic is a single third order IIR filter. The outputbased two IIR filters are overlay to illustrate the effect of computation precision in IIR filter.It can be observed in Figure D.1 that the IIR filter with 32-bit coefficients can implement theshape of a PID control although it has trouble addressing the high frequency pole precisely.In comparison, the IIR filter with 16-bit coefficients fails to implement the integrator (at lowfrequency) and the resulting transfer function is unusable in closed-loop.145D.3. Slow DAC Calibration TableFigure D.1: Example output of the PC software. In this case, the user input are zeros at -70kHz and -1 MHz and poles at 0 and -10 MHz and the underlying servo logic is implemented asa single IIR filter. The input forms an PID controller, but IIR filter with different coefficientresolution emulate the transfer function with different accuracy. The resulting transfer functionfrom the IIR filter with 16-bit coefficient (Q5.10) fails to implement the integrator.D.3 Slow DAC Calibration TableThe slow DAC calibration table is needed for the variable gain circuits in the FPGA servobecause often in a servo loop the gain has to be adjusted for optimal performance. The VGAused in this FPGA servo is linear-in-dB. Instead of approximating the gain as a exponentialfunction, this work approximate the gain with a calibration table with value in the slow DACand gain. Any intermediate gain is interpolated linearly from the closest two entries in thecalibration table.Each offset circuit is calibrated with a free parameter that represents the linear relationshipbetween the slow DAC value and the offset voltage.146


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