UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

A broadband self-interference cancellation circuit for simultaneous full-duplex radio applications El Sayed, Ahmed 2016

Your browser doesn't seem to have a PDF viewer, please download the PDF to view this item.

Item Metadata

Download

Media
24-ubc_2017_february_elsayed_ahmed.pdf [ 5.15MB ]
Metadata
JSON: 24-1.0340470.json
JSON-LD: 24-1.0340470-ld.json
RDF/XML (Pretty): 24-1.0340470-rdf.xml
RDF/JSON: 24-1.0340470-rdf.json
Turtle: 24-1.0340470-turtle.txt
N-Triples: 24-1.0340470-rdf-ntriples.txt
Original Record: 24-1.0340470-source.json
Full Text
24-1.0340470-fulltext.txt
Citation
24-1.0340470.ris

Full Text

A BROADBAND SELF-INTERFERENCE CANCELLATION CIRCUIT FOR SIMULTANEOUS FULL-DUPLEX RADIO APPLICATIONS by Ahmed El Sayed B.A.Sc. The University of British Columbia, 2014 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF  MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES (Electrical and Computer Engineering)  THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver)  December 2016  © Ahmed El Sayed, 2016   ii   Abstract All wireless communication systems so far have employed either time division duplexing (TDD), where the transmitter and receiver share the same frequency band but operate in orthogonal time slots, or frequency division duplexing (FDD), where the time slots are shared but orthogonal frequency bands are used. In order to meet the requirements for the upcoming 5G mobile standards, the concept of simultaneous full-duplex is being actively pursued, where both time slots and frequency bands can be shared between the transmitter and the receiver. The greatest hurdle in achieving full-duplex communication is the self-interference from the transmitter that is several orders of magnitude stronger than the desired signal at the receiver. Realizing such broadband cancellation has been hitherto very challenging, because not only does it demand broadband cancellation in amplitude, phase and group delay of the echo signals, but also require such a cancellation circuit to be linear, low-noise and ultra-compact for a mobile form factor.  This work will demonstrate the first self-interference radio-frequency cancellation circuit that achieves an 80 MHz linear time evolution (LTE) cancellation bandwidth in a linear, tunable, compact, and fully monolithic integrated circuit (IC) implementation for such full-duplex radios. A proof-of-concept prototype is realized in 0.13 µm complementary metal oxide semiconductor iii  (CMOS) process that utilizes techniques such as frequency translations and baseband Hilbert transforms to attain a measured 23 dB of self-interference cancellation over an 80MHz signal bandwidth. The entire circuit consumes 34 mW from a 1.2V supply in an active area of just 0.84 mm2.  iv   Preface This thesis is an original intellectual product of the author A. El Sayed. Part of the work has been filed as an invention disclosure (# 127532) to the US Patent Office in 2015. All of the work presented henceforth was conducted in the System-on-Chip (SoC) Laboratory at the University of British Columbia, Point Grey campus.    v   Table of Contents Abstract .......................................................................................................................................... ii Preface ........................................................................................................................................... iv Table of Contents .......................................................................................................................... v List of Tables .............................................................................................................................. viii List of Figures ............................................................................................................................... ix List of Abbreviations ................................................................................................................. xiii Acknowledgments ....................................................................................................................... xv Chapter 1: Introduction ............................................................................................................... 1 1.1. Motivation ............................................................................................................... 1 1.2. Prior Art ................................................................................................................... 4 1.3. Research Objectives ................................................................................................ 9 1.4. Thesis Overview .................................................................................................... 10 Chapter 2: Theoretical Analysis and Modelling ...................................................................... 11 2.1. Self-Interference Signal Model ............................................................................. 11 vi  2.2. Channel Model ...................................................................................................... 12 2.3. Proposed Solution ................................................................................................. 19 Chapter 3: Circuit Design .......................................................................................................... 29 3.1. System-Level Considerations ................................................................................ 29 3.1.1. Total Self-Interference Cancellation Required ................................................... 29 3.1.2. RF + Analog Self-Interference Cancellation Required ....................................... 30 3.1.3. ADC Dynamic Range.......................................................................................... 32 3.1.4. Amount of Cancellation Needed at RF ............................................................... 33 3.1.5. Canceller OIP3 .................................................................................................... 34 3.1.6. Canceller NF ....................................................................................................... 35 3.2. Circuit Description ................................................................................................ 36 3.2.1. Matching Circuits ................................................................................................ 37 3.2.2. Mixer Circuits ..................................................................................................... 37 3.2.3. LO Generation Circuit ......................................................................................... 39 3.2.4. Baseband Delay and Filtering ............................................................................. 41 3.2.5. Variable Attenuators ........................................................................................... 44 3.2.6. Coupling Capacitors ............................................................................................ 45 Chapter 4: Layout and Printed Circuit Board Design ............................................................ 47 4.1. Layout Considerations ........................................................................................... 47 vii  4.1.1. Self-Interference Canceller Tap 1 & 2 Layout .................................................... 48 4.1.2. Self-Interference Canceller Tap 3 Layout ........................................................... 52 4.1.3. LO Circuit Layout ............................................................................................... 52 4.2. Printed Circuit Board Design ................................................................................ 53 Chapter 5: Simulation and Measurement Results ................................................................... 57 5.1. Simulation Results ................................................................................................. 57 5.2. Measurement Setup and Results ........................................................................... 65 Chapter 6: Conclusions and Future Work ............................................................................... 81 6.1. Conclusions ........................................................................................................... 81 6.2. Future Work .......................................................................................................... 82 Bibliography ................................................................................................................................ 84    viii   List of Tables Table 3-1 Minimum system requirements for different isolation ................................................. 35 Table 5-1: I/Q imbalance in the LO .............................................................................................. 63 Table 5-2: Power Consumption .................................................................................................... 79 Table 5-3 Comparison of simulated and measured results ........................................................... 80 Table 6-1: Comparison to previous IC works ............................................................................... 82    ix   List of Figures Figure 1.1 Time Division Duplex (TDD) vs. Frequency Division Duplex (FDD) ........................ 2 Figure 1.2 Simultaneous full-duplex transceiver using one antenna and a circulator .................... 3 Figure 1.3 Prior Arts ....................................................................................................................... 6 Figure 1.4 Frequency domain equalization using one filter tap [10] .............................................. 7 Figure 1.5 Frequency domain equalization using two filter taps [10] ............................................ 7 Figure 1.6 Frequency-flat cancellation ........................................................................................... 9 Figure 2.1 Channel frequency domain model ............................................................................... 14 Figure 2.2 (a) Passband channel magnitude response (b) Decomposition of the channel response into I and Q components (c) Baseband representation of channel magnitude response using complex downconversion .................................................................................. 16 Figure 2.3 Magnitude and phase response of wireless channel and its estimations using real and complex coefficients ................................................................................................... 18 Figure 2.4 16-tap “real” interpolation of self-interference signal ................................................. 20 Figure 2.5 Two-tap complex estimation of self-interference signal ............................................. 21 x  Figure 2.6 Moving group delay implementation to baseband ...................................................... 22 Figure 2.7 (a) Magnitude Response, (b) phase response, and group delay of a single pole lowpass filter ............................................................................................................................. 23 Figure 2.8 Baseband Hilbert-transform-based scaling.................................................................. 25 Figure 2.9 Phase shift as weighted upconversion ......................................................................... 26 Figure 2.10 Final proposed implementation ................................................................................. 27 Figure 3.1  Required total analog cancellation for different isolation vs. signal bandwidth ........ 31 Figure 3.2 Required RX IIP3 for different isolation if the ADC dynamic range is kept constant 32 Figure 3.3 Required ADC dynamic range and digital cancellation for different isolation if RX IIP3 is kept constant ............................................................................................................ 33 Figure 3.4 Required self-interference cancellation at RF (before LNA) ...................................... 34 Figure 3.5 Overall system block diagram ..................................................................................... 36 Figure 3.6 Matching resistors bank ............................................................................................... 37 Figure 3.7 Double-balanced passive mixer ................................................................................... 38 Figure 3.8 LO generation circuit ................................................................................................... 40 Figure 3.9 Flip-Flop implementation ............................................................................................ 40 Figure 3.10 Single pole low pass filter ......................................................................................... 41 Figure 3.11 Second order low pass filter ...................................................................................... 42 Figure 3.12 Group delay of first order filter vs. second order filter ............................................. 43 Figure 3.13 Low pass filter variable capacitor .............................................................................. 44 xi  Figure 3.14 Current-steering differential attenuator ..................................................................... 45 Figure 3.15 Coupling capacitor bank ............................................................................................ 46 Figure 4.1 Die photo ..................................................................................................................... 48 Figure 4.2 Capacitor bank layout .................................................................................................. 50 Figure 4.3 Attenuator layout ......................................................................................................... 51 Figure 4.4 Self-interference canceller Tap 1 and Tap 2 layout ..................................................... 51 Figure 4.5 LO generation circuit layout ........................................................................................ 53 Figure 4.6 PCB design # 1. ........................................................................................................... 55 Figure 4.7 PCB design #2 ............................................................................................................. 56 Figure 5.1 Simulated SIC tap 1 insertion loss............................................................................... 58 Figure 5.2 Simulated SIC noise figure .......................................................................................... 58 Figure 5.3 Input referred 1-dB compression point of the canceller .............................................. 59 Figure 5.4 Tap 1 delay range and resolution................................................................................. 60 Figure 5.5 Tap 3 delay range and resolution................................................................................. 60 Figure 5.6 Attenuation range and resolution................................................................................. 61 Figure 5.7 Phase shift range and resolution .................................................................................. 61 Figure 5.8 Group delay change with attenuator settings............................................................... 62 Figure 5.9 Four phases of 25% duty cycle LO waveforms........................................................... 62 Figure 5.10 LO to RF leakage in SIC circuit ................................................................................ 64 xii  Figure 5.11 LO to IF Leakage in SIC circuit ................................................................................ 64 Figure 5.12 One tap SI cancellation using RLC channel .............................................................. 65 Figure 5.13 Measurement setup .................................................................................................... 66 Figure 5.14 Tap 1, 2 and 3 measured insertion loss...................................................................... 67 Figure 5.15 S11 and S22 of the Tap-1 SIC filter .......................................................................... 68 Figure 5.16 Measured noise figure of the Tap-1 SIC filter ........................................................... 69 Figure 5.17 Measured input referred 1-dB compression point of Tap-1 SIC filter ...................... 69 Figure 5.18 Measured in-band and out-of-band IIP3 for Tap-1 SIC filter ................................... 70 Figure 5.19 Channel group delay .................................................................................................. 71 Figure 5.20 Measured Tap 1, 2 and 3 group delay ....................................................................... 72 Figure 5.21 Two-tap cancellation over 80 MHz bandwidth for the wireless channel .................. 74 Figure 5.22 Wireline channel test setup ........................................................................................ 75 Figure 5.23 Sinusoidal input test setup ......................................................................................... 75 Figure 5.24 SIC circuit diagram with I/Q imbalance .................................................................... 76 Figure 5.25 Reduced search space for tap 1 ................................................................................. 76 Figure 5.26 One tap cancellation of a sinusoidal tone signal in a wireline setup ......................... 77 Figure 5.27 Wireline channel 80 MHz cancellation ..................................................................... 78 Figure 5.28 Wireless channel 80 MHz modulated signal one tap cancellation with I/Q error correction .................................................................................................................... 79   xiii   List of Abbreviations ADC  Analog to digital converter BB  Baseband BPF  Band pass filter BW  Bandwidth CMOS Complementary metal oxide semiconductor dB  Decibel dBm  Decibel-milliwatt DR  Dynamic range FDD  Frequency division duplexing I/OIP3 Input/output referred third order intercept point I/Q  In-phase and quadrature IC  Integrated circuit LNA  Low noise amplifier xiv  LPF  Low pass filter LTE  Linear time evolution MIMO Multiple-input multiple-output NF  Noise figure P1dB  One dB compression point PA  Power amplifier RF  Radio frequency RX  Receiver SAW  Surface acoustic wave SFDR  Spurious-free dynamic range SIC  Self-interference cancellation TDD  Time division duplexing TX  Transmitter   xv   Acknowledgments I would like to express my sincere gratitude to my parents whose continuous sacrifices and dedicated upbringing made me who I am today. I would also like to thank my wife for her support and encouragement. I also express my gratitude to my supervisor Dr. Sudip Shekhar for his guidance, commitment and his useful feedback that assisted me during this work. I would also like to thank my colleagues with whom I worked and had many insightful discussions. I especially thank Abdelrahman Ahmed and Amir Masnadi who collaborated with me on parts of this work. Finally, I acknowledge the Natural Sciences and Engineering Research Council of Canada for financial support. I also acknowledge the Canadian Microelectronics Corporation for access to CAD tools, fabrication and test equipment. I also acknowledge Intel Corporation and especially Intel Research Labs for their collaboration on this project  1   Chapter 1:  Introduction 1.1. Motivation The concept of duplexing has been used in telecommunication for a long time. It involves two devices that communicate with each other bi-directionally, meaning both devices can transmit and receive information. There are three types of duplex systems: half-duplex, full-duplex and simultaneous full-duplex. Half-duplex systems allow only one user to transmit at a time, and the user has to terminate the message before another user can start transmitting. An example of half-duplex system is a walkie-talkie set. Full-duplex systems are also bi-directional, and can either use two separate channels for each direction of communication, or share the same channel. For example, land-line telephone network employ full duplex over two channels (four wires) within the telephone network, and over the same channel (two wires) for connecting to subscribers.  The subscriber can speak and hear at the same time over the same frequency band because a hybrid coil is used to isolate the outgoing signal from the incoming signal. This type of duplexing over a wired medium is susceptible to interference, requiring echo cancellation. One way to achieve full-duplex communication is Frequency Division Duplex (FDD), where the communicating parties 2  are assigned orthogonal frequency bands (channels) for transmission and reception at the same time (Figure 1.1) [1], [2]. On the other hand, Time Division Duplex (TDD) is a technique used to emulate full-duplex communication on a half-duplex link: in TDD users share the same frequency channel but they can only access it in orthogonal time slots to each other (Figure 1.1). The use of FDD and TDD ensures that there is no interference between the transmitter (TX) and the receiver (RX) in each node. In the third type of duplexing, simultaneous full-duplex, the two communicating nodes share the same channel, the same time slot and the same frequency band. However, the interference from the transmitter to the receiver in each node (called self-interference, (SI)) is significant and has to be suppressed for the desired signal to be received correctly.   Figure 1.1 Time Division Duplex (TDD) vs. Frequency Division Duplex (FDD) In recent years, the explosion in the number of wireless users, and the desire to connect more devices in an Internet of Things has resulted in significant spectrum scarcity. To realize how significant this is, it is enough to know that the government of Canada has auctioned 68 MHz of wireless spectrum for $5.27 billion in 2014 [3]. If a simultaneous full duplex radio can be 3  developed where both users of the link exploit the same frequency and the same time frame, the bandwidth utilization can theoretically be halved or the transmission rate can be doubled.  The challenge in implementing simultaneous full duplex at a node is to isolate the strong self-interference signal from the transmitter (TX) to its local receiver (RX) in order for the RX to be able to listen to the weak desired signal coming from a remote node as shown in Figure 1.2. The only isolation provided natively in a transceiver comes from the use of a circulator, which can typically provide 15-30 dB of isolation. While circulators for base station applications are bigger and provide 20-30 dB of isolation, circulators for mobile devices are small and only able to provide 10-20 dB of isolation. Utilizing two separate antennas for the TX and RX, and separating them physically can provide higher isolation but at the expense of more hardware.   Figure 1.2 Simultaneous full-duplex transceiver using one antenna and a circulator Several methods using passive and active interference suppression of the local TX signal at the physical layer have been reported recently in literature [4]–[10]. Some of these prior attempts in realizing the hardware have been made using discrete components. Although feasible for base 4  station applications, they are not viable for mobile devices, where a compact fully-integrated monolithic implementation is necessary. Furthermore, many other issues still need to be resolved – increasing the extent of self-interference cancellation (SIC), reducing the area of the cancellation circuits, co-existence with MIMO (multi-input multi-output), etc. Monolithic implementations in smart form-factor have their own integration challenges, with on-chip non-idealities affecting the overall performance.  1.2. Prior Art In order to suppress self-interference, we need to replicate the self-interference signal including the changes it experiences in the channel. So, we need to tap a portion of the transmitted signal from the power amplifier (PA) output, introduce the same effects of the channel on it, and then subtract it from the received signal. These effects include attenuation, phase shift and group delay, where group delay is the effective common time delay experienced by the group of frequencies centered around a frequency ωo [1]. The circuit used to emulate the self-interference channel has to be very linear to withstand the high power tapped from the PA and not introduce its own non-linearities.  Figure 1.3 shows four prior approaches to achieve a simultaneous full-duplex link. Figure 1.3(a) shows one discrete implementation that uses 16 tapped transmission lines at the radio-frequency (RF) with 16 attenuators to estimate the self-interference signal by a linear combination of its delayed versions [4]. This technique is inspired by time domain interpolation using a sinc function to reconstruct continuous time signals from their discrete time samples [1]. However, using transmission lines to generate delay is a very area costly solution as several centimeters of transmission line length are needed to generate nanosecond scale delay. In addition, many copies of the signal are needed due to inaccurate modelling of the self-interference channel as will be 5  explained in chapter 2. 57 dB and 47 dB of RF cancellation has been shown for a 20 MHz and 80 MHz bandwidth respectively by amplitude tuning only as the delays are fixed and cannot be tuned.  Another discrete solution (Figure 1.3 (b)) uses fixed RF transmission-line delays on only two copies of the self-interference signal and scales the in-phase (I) and quadrature (Q) components of the signal differently using RF-based Hilbert transform [6], [11]. This adds a degree of freedom for rotating the phase of the cancellation signals which makes the cancellation more broadband and less dependent on the tap delay difference of the canceller and the actual delay of the self-interference signal. The reason for this will be described in detail in chapter 2 of this thesis. The tunable RF suppression achieved by this method is 48 dB for a 20 MHz signal bandwidth and 41 dB for 80 MHz bandwidth. Although superior to the implementation of Figure 1.3(a), this implementation is still discrete and utilizes transmission lines that are bulky and hard to integrate on-chip. Furthermore, the delay provided by the transmission line cannot be varied as the wireless channel changes. Figure 1.3(c) shows one integrated solution that demonstrates self-interference cancellation by frequency equalization using two active second-order band-pass N-path filters [10]. An N-path filter consists of N identical signal paths that are switched ON using N non-overlapping clocks. The multi-phase clock sampling action allows the frequency translation of baseband (BB) transfer functions to higher frequencies around the clock frequency [12]. In this implementation, a low pass filter response is translated to the clock frequency to create a band pass filter response. The band pass filter is shaped in frequency domain to mimic the frequency response of the self-interference channel while the delay of the low pass filter in baseband that can reach several nanoseconds is upconverted to the passband without the use of bulky transmission lines. 6   Figure 1.3 Prior Arts Figure 1.4 describes the cancellation in frequency domain. 20 dB of tunable RF cancellation is demonstrated for 25 MHz BW using two taps of BPF. Multiple taps of BPF can be used to emulate the channel response better, and get more frequency-domain cancellation, as shown in Figure 1.5. However, this requires use of transconductance (gm) amplifiers to tune the center frequency of each tap. The canceller circuit is therefore non-linear due to the use of gm cells. gm cells also introduce flicker noise. A maximum self-interference of -8 dBm peak interference power can be cancelled. Considering the PA output power (for example, 20 dBm in a Wi-Fi signal), the canceller Tap 1616 W16Tap 11 W1SI Channely(t)+-+0° W2iTap 2290° W1qTap 110° 90°W1iW1qSI Channely(t)+-+[1][2]x(t)x(t)Φ Φ SI Channely(t)x(t) +-[3][4]SI ChannelVector mod.φ1 φ2 cos ωtsin ωtcos ωtsin ωtyI(t)yQ(t)+-+-x(t)       (a) (c) (b) (d) 7  has a limited linearity and will put a higher dynamic range (DR) specification on the receiver analog to digital converter (ADC).  Figure 1.4 Frequency domain equalization using one filter tap [10]  Figure 1.5 Frequency domain equalization using two filter taps [10] 8  Another integrated-circuit (IC) based implementation (Figure 1.3(d)) exploits passive vector modulator (VM) with a mixer-first RX [9]. A mixer-first receiver does not use a low noise amplifier (LNA) as its first stage but a downconverting mixer instead, followed by baseband amplifiers/filters. The advantage of using a passive mixer in a mixer-first receiver is that it performs the dual function of downconversion and filtering at the same time by upconverting the low pass response of the channel selection filter into a band pass response at the input of the receiver. This relaxes the need for expensive surface acoustic wave (SAW) filters before the receiver and also makes it tunable by the clock frequency ensuring wideband operation. Furthermore, using passive components makes the circuit very linear. However, the envelope delay of the self-interference signal is not addressed in this implementation, and assumed to be implemented in digital domain. This leads to a narrowband cancellation because the group delay introduces frequency-selective scaling of the self-interference channel response while this technique can be explained as a frequency-flat equalization, as shown in Figure 1.6. Using a vector modulator, the amplitude and the phase of the self-interference signal can be matched exactly to the cancellation signal, and significant amount of cancellation can be achieved. However, this cancellation is only valid at one frequency point, and the cancellation degrades significantly across the desired signal bandwidth. This design reports 27 dB of cancellation for 24 MHz signal. Furthermore, the mixer-first architecture results in a poor receiver noise figure because the first stage has a high noise figure (NF) while not providing gain, and the addition of the self-interference cancellation circuit degrades the NF by an additional 6dB. 9   Figure 1.6 Frequency-flat cancellation The first two designs in Figure 1.3(a) and (b) [4], [6] implement the delay and the phase shift in the RF domain using precise discrete components that can introduce the required amount of delay at these high frequencies. The third implementation in Figure 1.3(c) [10] uses downconversion and baseband delay to produce the required delay. A discussion on the implementation of delay at baseband and the corresponding benefits will follow in the body of the thesis. 1.3. Research Objectives The first objective of this research is to adequately model the self-interference channel in a wireless transceiver employing complex modulation schemes and develop the theory necessary for analysing and estimating the self-interference signal. The second objective is to find the system-level trade-offs in a simultaneous full-duplex system as opposed to conventional half-duplex or TDD/FDD systems and identify additional constraints imposed on different system blocks. 10  The third objective is to design, fabricate and measure the performance of a self-interference cancellation circuit for simultaneous full-duplex radios that is amenable to monolithic CMOS implementation. 1.4. Thesis Overview In this thesis, prior arts implementing simultaneous full-duplex radios have been described in chapter 1. In chapter 2, I will develop the theory necessary to model self-interference as well as propose a solution to implement a self-interference cancellation circuit that can enable simultaneous full-duplex radio for mobile devices. Next, in chapter 3, I will identify system-level design trade-offs of simultaneous full-duplex transceivers and present design equations and specification for different system blocks. I will also describe a self-interference cancellation circuit prototype for simultaneous full duplex radios fabricated in a monolithic CMOS integrated circuit. In chapter 4, I will highlight the layout techniques used in the IC as well as in the printed circuit board (PCB). Then, in chapter 5, I will present the measurement setup and measurement results from the prototype. Finally, in chapter 6, I will provide the conclusions for this work and suggest enhancements for future work.   11   Chapter 2:  Theoretical Analysis and Modelling 2.1. Self-Interference Signal Model The transmitter leakage signal undergoes two effects through the self-interference channel: delay and attenuation [6], [13]. The delay can be decomposed into two phenomena: a carrier phase shift and an envelope group delay. By emulating these effects, a replica of the self-interference signal can be produced and subtracted from the received signal to cancel self-interference. Depending on the delay spread of the wireless channel, the delay can be in the order of a few nanoseconds. Consider a narrowband signal x(t) at the output of the power amplifier which has been modulated in both amplitude and phase (as is the case in many modern wireless standards):  𝑥(𝑡)  =  𝑎(𝑡) 𝑐𝑜𝑠 (𝜔𝑐𝑡 +  𝜑(𝑡) ) (2.1) where a(t) is the baseband envelope modulating signal, ωc is the carrier frequency and φ(t) is the phase modulating signal. Assuming the channel as non-selective in frequency domain, with an impulse response of h(t) = g(t – ), where the attenuation and delay of the channel is  modeled by g and τ respectively, the signal x(t) is shaped by the channel as: 12  𝑦(𝑡) = 𝑥(𝑡)ℎ(𝑡) = 𝑥(𝑡)𝑔(𝑡 − 𝜏) = 𝑔𝑥(𝑡 − 𝜏) = 𝑔 𝑎(𝑡 − 𝜏)𝑐𝑜𝑠 (𝜔𝑐(𝑡 − 𝜏)  +  𝜑(𝑡 − 𝜏) )  = 𝑔 𝑎(𝑡 − 𝜏)𝑐𝑜𝑠 (𝜔𝑐𝑡 +  𝜑(𝑡 − 𝜏) −  𝜃) (2.2) where θ = ωcτ is the phase shift acquired by the carrier in the self-interference channel. In order to cancel the self-interference from the transmitter at the input of the receiver, a copy of the transmitted signal must be tapped from the power amplifier output, and passed through a channel emulator implemented using circuit components that also creates the same effect as equation (2.2).  2.2. Channel Model In equation 2.2, the channel was considered to be non-selective in frequency. However, in reality, the wireless channel can be modeled in frequency domain as a filter with complex tap coefficients that distorts the signal [14], [15]. There are many reasons why the channel has a complex frequency response. When the transmitter sends an electromagnetic wave to the receiver, it generates an electric field E in the wireless medium. The electric displacement field D at any point in the channel is proportional to E, and describes the effect of E on electric charges, including charge migration and electric dipole representation. The relationship that governs them is given by D = E, where  is the permittivity of the medium. The polarization response of the charged particles in the channel is not instantaneous to E, but has a lag. Thus, permittivity is denoted as a complex number, with the real part representing energy storage and the imaginary part representing energy dissipation. The overall wave impedance for the channel is given by 𝑍 = √𝑗𝜔𝜇𝜔.𝐼𝑚𝑎𝑔(𝜀)+𝑗𝜔.𝑅𝑒𝑎𝑙(𝜀), which is complex [16]. Another way to explain the complex frequency response of the channel is that as a wave travels from the transmitter antenna to the receiver antenna, it has a dominant line-of-sight (LOS) path 13  but also has multiple other paths due to reflection, diffraction and scattering. Each of these paths has a certain attenuation and delay associated with it. The waves travelling from the transmitter to the receiver in these paths add up either constructively or destructively. The net effect of the channel is then two random variables: attenuation and phase shift (delay) produced by the sum of all the waves from the multiple paths. The attenuation has a normal distribution, the phase shift has a uniform distribution and the sum of the multipath waves has either a Rayleigh or Rician distribution. Hence, the net effect of the channel is a complex variable [14], [15]. Finally, part of the channel in a wireless link is made up of the printed circuit board (PCB) traces and microwave cables to and from the antenna on both sides. These traces and cables behave as transmission lines at RF. The losses in the transmission lines such as ohmic loss and dielectric loss give rise to a frequency dependent attenuation and phase shift in the line. The transmission line can then be modeled as a resistance R in series with a lossless inductor L and a conductance G in shunt with a lossless capacitor C. Then, the propagation coefficient becomes γ =  √(𝑅 + 𝑗𝜔𝐿)(𝐺 + 𝑗𝜔𝐶) and the characteristic impedance of the line 𝑍0 =  √𝑅+𝑗𝜔𝐿𝐺+𝑗𝜔𝐶 [17]. Thus, the channel in a wireless link can be modeled in frequency domain as a filter with multiple complex taps ck = αk + jβk where k is the frequency index. The input symbols (transmitted signal) are also complex variables xk = ak + jbk. Figure 2.1 shows the channel model with input and output signals in frequency domain. 14   Figure 2.1 Channel frequency domain model The output signal yk is then calculated to be: 𝑦𝑘 = (𝑎𝑘 + 𝑗𝑏𝑘)(𝛼𝑘 + 𝑗𝛽𝑘)  = (𝑎𝑘𝛼𝑘 − 𝑏𝑘𝛽𝑘) + 𝑗(𝑏𝑘𝛼𝑘 + 𝑎𝑘𝛽𝑘) (2.3) Equation (2.3) reveals that the channel has unequal I and Q gains. This leads to the important result that in order to replicate the self-interference signal at the receiver input, complex scaling and phase rotation is required on the copy of the self-interference signal tapped from the power amplifier [6].  Consider a typical wireless channel link centered around frequency fc whose magnitude response is shown in Figure 2.2(a). Although the absolute magnitude response is real (i.e. |H(f)| is symmetric around the y-axis), when considering the complex information, we find that the in-phase (I) and the quadrate phase (Q) components of the channel frequency response are neither equal in sign nor 15  in magnitude, as explained before. However, the impulse response of the channel has to be real because complex response has no physical meaning in time domain. This implicates necessarily that the response of the channel in the negative frequencies is the complex conjugate of the response in the positive frequencies (Figure 2.2(b)). It is also informative to look at the baseband representation of the channel frequency response in Figure 2.2(c) – the response is asymmetric around the y-axis, implying that it is complex. Consequently, both a copy of the signal and its Hilbert transform are needed to reconstruct the self-interference signal coming out of the channel. A Hilbert transform shifts the phase of a given signal by 90⁰, which is equivalent to multiplying the signal in frequency (ω) domain by –j sgn(ω), where sgn is the signum function. When the Hilbert transformed signal is then added to the original signal, the resulting signal’s I/Q components in the positive frequencies are the complex conjugate of the I/Q components in the negative frequencies. The generation of the Hilbert transform of the signal has been neglected in the implementation of [4] leading to the use of 16 “real” taps of the signal as compared to only 2 “complex” taps in [6] to achieve comparable self-interference suppression. 16   Figure 2.2 (a) Passband channel magnitude response (b) Decomposition of the channel response into I and Q components (c) Baseband representation of channel magnitude response using complex downconversion In order to illustrate the difference between “complex” (Hilbert transform based) channel estimation versus “real” channel estimation, a wireless channel composed of two antennas has been measured in the lab using a vector network analyzer (VNA) and imported to MATLAB. Next, a Wi-Fi 802.11g signal was generated and used as the transmitted signal through the channel. The received signal was then used to estimate the channel along with two copies of the transmitted 17  signal having two different delays equally spaced from the actual channel delay. Two cases were used: in the first case, the two echoes were used to estimate the channel directly, and in the second case, the two echoes and their Hilbert transforms were used to estimate the channel. This is a fair comparison because in both cases the number of transmission lines providing the necessary delay is the same. The only additional hardware required in the second case is two 90⁰ phase shifters which are much smaller than the transmission lines. The results of the channel estimation in both cases are shown in Figure 2.3. 18    Figure 2.3 Magnitude and phase response of wireless channel and its estimations using real and complex coefficients 19  It is clear that the Hilbert estimation matches the channel response over a much wider bandwidth than the “real-only” estimation. 2.3. Proposed Solution Rewriting equation (2.2) with the complex nature of the signal in mind: 𝑥(𝑡) =  𝑥𝑖(𝑡) 𝑐𝑜𝑠(𝜔𝑐𝑡) +  𝑥𝑞(𝑡) 𝑠𝑖𝑛(𝜔𝑐𝑡) where xi(t) and xq(t) are the baseband I and Q envelopes, respectively. Now, applying the effects of channel which is non-selective in frequency domain: 𝑦(𝑡) =  𝑔{𝑥𝑖(𝑡 − 𝜏) 𝑐𝑜𝑠(𝜔𝑐𝑡 − 𝜃) + 𝑥𝑞(𝑡 − 𝜏) 𝑠𝑖𝑛(𝜔𝑐𝑡 − 𝜃)} =  𝑔[𝑥𝑖(𝑡 − 𝜏) {𝑐𝑜𝑠(𝜔𝑐𝑡)𝑐𝑜𝑠 (𝜃) +  𝑠𝑖𝑛(𝜔𝑐𝑡)𝑠𝑖𝑛 (𝜃)}+ 𝑥𝑞(𝑡 − 𝜏) {𝑠𝑖𝑛(𝜔𝑐𝑡)𝑐𝑜𝑠 (𝜃) − 𝑐𝑜𝑠(𝜔𝑐𝑡)𝑠𝑖𝑛 (𝜃)}]   = 𝑔[𝑐𝑜𝑠(𝜔𝑐𝑡){𝑥𝑖(𝑡 − 𝜏) 𝑐𝑜𝑠(𝜃) − 𝑥𝑞(𝑡 − 𝜏) 𝑠𝑖𝑛(𝜃)}+ 𝑠𝑖𝑛(𝜔𝑐𝑡){𝑥𝑖(𝑡 − 𝜏) 𝑠𝑖𝑛(𝜃) + 𝑥𝑞(𝑡 − 𝜏) 𝑐𝑜𝑠(𝜃)}]  (2.4) However, as discussed in the previous section, the wireless channel is frequency selective. Thus, the right hand side of equation (2.4) must be expanded as a superposition of several delay taps, i. Thus, in [4], equation (2.4) is approximated by an interpolation of 16 taps at passband as shown in Figure 2.4 to produce the estimated self-interference signal. 20   Figure 2.4 16-tap “real” interpolation of self-interference signal The resulting signal is: ?̃?(𝑡) =  𝑤1𝑥(𝑡 − 𝜏1) + 𝑤2𝑥(𝑡 − 𝜏2) + ⋯ + 𝑤16𝑥(𝑡 − 𝜏16) Clearly, the tap delays have to be very close to the actual channel delay for cancellation to happen, and the resolution of the tap delay has to be very precise to match the delay spread of the channel, to obtain large suppression of the self-interference over the desired bandwidth. But because the delay of the channel is not known at the design stage and the delays are fixed and not made tunable, a large number of taps has to be used to approximate the channel delay. The implementation in [6] addresses this problem and implements complex tap weights using the signal and its Hilbert transform, making cancellation less dependent on the delay resolution of the taps. However, the delays are still fixed and implemented at passband using discrete delay elements as shown in Figure 2.5. 21   Figure 2.5 Two-tap complex estimation of self-interference signal The resulting signal is:  ?̃?(𝑡) =  𝑤1𝑖𝑥(𝑡 − 𝜏1) + 𝑤2𝑖𝑥(𝑡 − 𝜏2) + 𝑤1𝑞?̂?(𝑡 − 𝜏1) + 𝑤2𝑞?̂?(𝑡 − 𝜏2) (2.5) where wk,i and wk,q are the k-th tap I and Q weights, respectively, and x̂ is the Hilbert transform of the signal.  So how can a delay in nanoseconds be applied on-chip without using bulky transmission lines or inductors that vary with CMOS process? Since equation (2.4) suggests that we only need to apply this delay to the baseband envelopes, it may be easier to extract those baseband signals and perform the required delay on them in baseband. The baseband signal can be extracted by first downconverting the RF signal to baseband using mixers, and rejecting the upper sidebands using a low pass filter (LPF). Delay can then be implemented in baseband, and the signal be upconverted back to RF using mixers again. Thus, stepping forward from Figure 2.5, we can move the delay to baseband as shown in Figure 2.6. 22   Figure 2.6 Moving group delay implementation to baseband It should be noted that most of modern day wireless standards use complex modulation schemes such as Quadrature Amplitude Modulation (QAM). Hence, the signal should be downconverted and upconverted using I and Q mixers, as shown in Figure 2.6. This is a result of the asymmetry of the signal in baseband around the y-axis due to its complex nature. A low pass filter can be also used as a delay element provided that the bandwidth of the signal of interest is much smaller than the filter cut-off frequency (BW <<1𝑅𝐶). In this case, the frequency content of the signal experiences very linear phase shift which translates into constant group delay and avoids signal dispersion as shown in Figure 2.7 for a single-pole low pass filter. It should be noted that group delay is the frequency-derivative of the phase response.  23     Figure 2.7 (a) Magnitude Response, (b) phase response, and group delay of a single pole lowpass filter The benefit of implementing the group delay in baseband, as opposed to passband, is that a delay of a few nanoseconds can be produced without using large passive components such as inductors, transformers or transmission-lines. In addition, the delay can be easily made tunable by using a capacitor bank that changes the bandwidth of the low pass filter and hence the group delay. The (b) Constant delay region (a) 24  lower the bandwidth, the more delay the filter introduces, and vice versa. Therefore, the lower bound of the variable capacitance is determined by the minimum capacitor that can be used in the CMOS process and the higher bound is determined by the maximum bandwidth of the signal in order to not introduce time dispersion, as explained above. Before upconversion, we must implement complex rotation of the signal for optimal cancellation, as discussed earlier. Next, we derive the required complex weights from equation (2.5). The derivation here is made for only one tap; the other taps have similar expressions. ?̃?(𝑡) =  𝑤1𝑖𝑥(𝑡 − 𝜏1) +  𝑤1𝑞?̂?(𝑡 − 𝜏1) =  𝑤1𝑖𝑥𝑖(𝑡 − 𝜏1) 𝑐𝑜𝑠(𝜔𝑐𝑡 − 𝜃1) + 𝑤1𝑖𝑥𝑞(𝑡 − 𝜏1)𝑠𝑖𝑛(𝜔𝑐𝑡 − 𝜃1)+  𝑤1𝑞𝑥𝑖(𝑡 − 𝜏1)𝑠𝑖𝑛(𝜔𝑐𝑡 − 𝜃1) − 𝑤1𝑞𝑥𝑞(𝑡 − 𝜏1)𝑐𝑜𝑠(𝜔𝑐𝑡 − 𝜃1)  = 𝑥𝑖(𝑡 − 𝜏1)[𝑤1𝑖𝑐𝑜𝑠(𝜔𝑐𝑡 − 𝜃1) + 𝑤1𝑞𝑠𝑖𝑛(𝜔𝑐𝑡 − 𝜃1)]+ 𝑥𝑞(𝑡 − 𝜏1)[−𝑤1𝑞𝑐𝑜𝑠(𝜔𝑐𝑡 − 𝜃1) + 𝑤1𝑖𝑠𝑖𝑛(𝜔𝑐𝑡 − 𝜃1)] This leads to the block diagram in Figure 2.8. 25   Figure 2.8 Baseband Hilbert-transform-based scaling As discussed before, the low pass filter itself provides the delay τ. Also the weights w have been doubled to compensate the splitting of the signal at the input. However, this implementation still requires phase shift in the LO signal of the upconversion mixers [10], [13]. Adding phase shifters in the LO clock path instead of the RF signal path (Fig 2.7) is relatively easier since they can be implemented with digital phase interpolators using current-starved inverters. However, this requires additional power consumption in the clock generation and distribution circuits, area, and introduces uncorrelated phase noise between the downconversion and upconversion local oscillator (LO) signals, degrading the noise performance of the cancellation circuit.  Next, the phase shift is moved into the signal path using a vector modulator as described in section 2.1, leading to the block diagram in Figure 2.9. 26  ?̃?(𝑡) = 𝑥𝑖(𝑡 − 𝜏1) [𝑤1𝑖𝑐𝑜𝑠(𝜔𝑐𝑡)𝑐𝑜𝑠 (𝜃1) + 𝑤1𝑖𝑠𝑖𝑛(𝜔𝑐𝑡)𝑠𝑖𝑛 (𝜃1)+𝑤1𝑞𝑠𝑖𝑛(𝜔𝑐𝑡) 𝑐𝑜𝑠 (𝜃1) − 𝑤1𝑞𝑐𝑜𝑠(𝜔𝑐𝑡) 𝑠𝑖𝑛(𝜃1)]+ 𝑥𝑞(𝑡 − 𝜏1) [−𝑤1𝑞𝑐𝑜𝑠(𝜔𝑐𝑡)𝑐𝑜𝑠 (𝜃1)−𝑤1𝑞𝑠𝑖𝑛(𝜔𝑐𝑡)𝑠𝑖𝑛 (𝜃1)+𝑤1𝑖𝑠𝑖𝑛(𝜔𝑐𝑡) 𝑐𝑜𝑠 (𝜃1) − 𝑤1𝑖𝑐𝑜𝑠(𝜔𝑐𝑡) 𝑠𝑖𝑛(𝜃1)]  Figure 2.9 Phase shift as weighted upconversion With further mathematical simplifications to reduce the number of gain elements and mixers, we arrive at the final implementation as shown in Figure 2.10 27    Figure 2.10 Final proposed implementation It is obvious that the circuit in Figure 2.10 can replicate the effects of the channel from equation (2.4). All we need to do is map τ1,  and  in the circuit to τ, cos(θ) and sin(θ) respectively in equation (2.4).  As shown in Figure 2.10, a copy of the self-interference signal is first downconverted using I/Q mixers. Then the baseband I and Q envelopes are delayed by the means of a low pass filter. Next, the delayed baseband I and Q signals are weighted using the  and  variable attenuators (since cos(θ) and sin(θ) < 1) to provide the necessary phase shift before upconversion with I/Q mixers. It is important to note that the attenuators must be implemented in such a way so to not change the total resistance seen from their input node in order to not change the group delay set by the low pass filter capacitance. In other words, the control for the group delay and the phase shift should be completely decoupled from each other. It should also be noted that the input of the filter in Figure 2.10 should be matched to 50Ω if the input signal is going to be provided from an external signal generator. Additionally, the output of the filter should be matched to interface two 50Ω ỹ(t) 28  resistances: one from the antenna side and one from the receiver side. Both of these matching conditions should hold over a broadband bandwidth larger than the signal bandwidth. This self-interference cancellation filter also provides broadband operation since it is tuned by the clock frequency driving the mixers: the low pass response of the delay element is always upconverted to a band pass response at the input of the filter centered around the clock frequency no matter what this frequency is. In a complete transceiver, the clock will be generated by the same oscillator that provides the transmitter and receiver clocks and hence, the filter is automatically tuned to the same operating frequency of the transceiver.   29   Chapter 3: Circuit Design 3.1. System-Level Considerations Many challenges are associated with the integration of the self-interference cancellation filter with a radio transceiver [4], [10], [18]. The system-level specifications can be summarized in the following list:  The total amount of self-interference cancellation required  The amount of RF plus analog cancellation needed  ADC DR  The amount of cancellation needed at RF  Self-interference cancellation filter output-referred third order intercept point (OIP3)  Self-interference cancellation filter NF 3.1.1. Total Self-Interference Cancellation Required The requirement for total self-interference cancellation (SICtotal) required is very simple. It comes from the subtraction of the receiver noise floor from the transmitter output power (PTX) [10]. 30  𝑆𝐼𝐶𝑡𝑜𝑡𝑎𝑙 = 𝑃𝑇𝑋 − (−174 𝑑𝐵𝑚 𝐻𝑧⁄ + 𝑁𝐹𝑅𝑋 + 10 log10 𝐵) where NFRX is the receiver noise figure and B is the RF signal bandwidth. The objective is to ideally bring the interference power down to the noise floor of the receiver. Assuming PTX = 15 dBm, NFRX = 5 dB and B = 80 MHz, we find SICtotal = 105 dB. The SIC path must cancel the main signal as well as non-linearity and noise of the TX.  This 105 dB of SICtotal can be distributed among RF, analog baseband and digital baseband cancellation circuits (Figure 1.2). It is also important to note that any non-linearity that is itself added by the RF or baseband analog canceller circuits can be suppressed using a digital canceller at baseband. However, no canceller can suppress receiver induced non-linearity or noise affecting the “desired” signal such as gain compression or cross-modulation with a blocker. This dictates the distribution of the total amount of cancellation required in different stages, as discussed next. 3.1.2. RF + Analog Self-Interference Cancellation Required It is less trivial to specify the amount of cancellation needed at each part of the receiver chain. As depicted in Figure 1.2, the self-interference cancellation can happen before the RF frontend, after downconversion in the analog domain and after digitization at baseband. A minimum amount of cancellation is needed at each point to prevent the receiver’s performance degradation. The total cancellation at RF and analog baseband (SICRF and SICA–BB, respectively) should cancel the transmitter’s main signal and its harmonics down to the level where the residual self-interference is equal the input-referred distortion of the receiver as to not saturate the ADC [4], [10].   (𝑆𝐼𝐶𝑅𝐹  +  𝑆𝐼𝐶𝐴−𝐵𝐵) =  2 [𝐼𝐼𝑃3𝑅𝑋,𝑒𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 − (𝑃𝑇𝑋,𝑚𝑎𝑖𝑛  −  𝐼𝑆𝑂 −  3)] (3.1) where IIP3RX, effective is the input-referred third order intercept point (IIP3) of the receiver after connecting the SIC circuit, and ISO is the passive isolation between the transmitter and the 31  receiver, provided by the circulator. The above equation suggests that as the passive isolation between the transmitter and receiver worsens, the total RF and analog cancellation requirement becomes twice more stringent. The total RF and analog cancellation required for different levels of isolation is shown in Figure 3.1. The figure is generated under the assumption that the self-interference canceller will have an output-referred distortion equal to the input-referred distortion of the receiver. This is to ensure that the lower bound of the ADC DR does not rise due to the canceller distortion.   Figure 3.1  Required total analog cancellation for different isolation vs. signal bandwidth An important assumption made here unlike [10] is that the receiver IIP3 is constant and the ADC DR is increased to delegate the suppression of any non-linear components to digital baseband circuitry. Otherwise, the receiver IIP3 has to be increased by 1.5 in dBm scale with every dB drop in isolation, as shown in Figure 3.2, making the receiver unrealistic to design with CMOS technology. 15.020.025.030.035.040.00 20 40 60 80 100Analog + RF Cancellation (dB)RF BW (MHz)30dB25dB20dB32   Figure 3.2 Required RX IIP3 for different isolation if the ADC dynamic range is kept constant 3.1.3. ADC Dynamic Range The ADC dynamic range is bound by the residual self-interference after analog cancellation and the receiver noise floor. Equation (3.2) shows how to calculate the required dynamic range with a 6 dB margin on each bound [10].  𝐷𝑅𝐴𝐷𝐶 =  (𝑃𝑇𝑋,𝑚𝑎𝑖𝑛  −  𝐼𝑆𝑂 −  𝑆𝐼𝐶𝑅𝐹  − 𝑆𝐼𝐶𝐴−𝐵𝐵  +  6) − (𝑃𝑛𝑜𝑖𝑠𝑒 𝑓𝑙𝑜𝑜𝑟  −  6) (3.2) As mentioned before, we will compensate the drop in isolation by increasing the ADC dynamic range instead of trying to improve the receiver IIP3 because the suppression of non-linear components in digital baseband is a much easier task and less power consuming than increasing the linearity of the receiver RF frontend. This requirement goes hand in hand with the digital cancellation required, as shown in Figure 3.3. The required DR saturates at certain isolation because the non-linear components have been suppressed to the receiver noise floor. Obviously, -4.0-2.00.02.04.06.08.010.012.014.016.018.00 20 40 60 80 100RX IIP3 (dBm)RF BW (MHz)30dB25dB20dB33  an increase in the dynamic range of ADC results in additional ADC power consumption and design complexity. According to Figure 3.3, the maximum number of ADC bits required is 12 bits which is very challenging to design in CMOS.  Figure 3.3 Required ADC dynamic range and digital cancellation for different isolation if RX IIP3 is kept constant 3.1.4. Amount of Cancellation Needed at RF The requirement for the amount of cancellation needed at RF (SICRF) is derived from the linearity of the LNA. There is a maximum power that the LNA can handle before starting to generate non-linear products. Although the LNA is not a frequency translating device like the mixer, in the presence of a continuous wave (CW) blocker adjacent to the desired channel, the residual self-interference can cross-modulate with the blocker and raise the receiver noise floor. The power of the cross-modulation product can be found using equation (3.3) [10]  𝑃𝑥𝑚𝑜𝑑 = 2 (𝑃𝑇𝑋,𝑚𝑎𝑖𝑛 − 𝐼𝑆𝑂 − 𝑆𝐼𝐶𝑅𝐹) + 𝑃𝑏𝑙𝑜𝑐𝑘𝑒𝑟 − 2 𝐼𝐼𝑃3𝐿𝑁𝐴 (3.3) To ensure that the receiver noise floor is not degraded, Pxmod needs to be well below Pnoise floor. Then, SICRF can be written as: 45.050.055.060.065.070.075.00 20 40 60 80 10020dB40.045.050.055.060.065.070.00 20 40 60 80 100RF BW (MHz) RF BW (MHz)ADC DR (dB)Digital Cancellation(dB)25dB30dB25dB30dB20dB34  𝑆𝐼𝐶𝑅𝐹 =  𝑃𝑇𝑋,𝑚𝑎𝑖𝑛 − 𝐼𝑆𝑂 −  𝐼𝐼𝑃3𝐿𝑁𝐴 +12(𝑃𝑏𝑙𝑜𝑐𝑘𝑒𝑟 − 𝑃𝑛𝑜𝑖𝑠𝑒 𝑓𝑙𝑜𝑜𝑟 + 6) Then, assuming a blocker power of -15 dBm, Figure 3.4 plots the required the required RF cancellation for different isolation with a fixed LNA IIP3 of 6 dBm.  Figure 3.4 Required self-interference cancellation at RF (before LNA) 3.1.5. Canceller OIP3 In order to not degrade the spurious-free dynamic range (SFDR) of the ADC, the output distortion of the canceller should not exceed the input referred distortion of the receiver. Hence, using equation (3.1) we derive the required OIP3 of the canceller to be [10]: 𝑂𝐼𝑃3 + 𝐶𝑅𝑋 =  (𝑃𝑇𝑋,𝑚𝑎𝑖𝑛 − 𝐼𝑆𝑂 − 3) +12 (𝑆𝐼𝐶𝑅𝐹  +  𝑆𝐼𝐶𝐴−𝐵𝐵) where CRX is the coupling strength from the canceller output to the receiver input. CRX is a variable attenuation inserted after the canceller and before the input of the receiver on purpose to prevent injecting too much noise current into receiver. This will be further discussed in the next subsection. 10.015.020.025.030.035.00 20 40 60 80 10020dB25dB30dBSIC RF (dB)RF BW (MHz)35  3.1.6. Canceller NF The output noise power of the canceller (NFcanceller) will be injected directly into the receiver. If that noise power is much higher than the receiver noise floor, it will degrade the receiver noise figure (NFRX). Consequently, some of the cancellation signal power has to be sacrificed in order to attenuate the canceller output noise power going into the receiver, using the variable attenuator of coupling strength CRX. Then the new receiver noise figure (NFRX,total) can be derived as follows: 𝑁𝐹𝑅𝑋,𝑡𝑜𝑡𝑎𝑙 = 10 log10(10𝑁𝐹𝑅𝑋10 + 10𝑁𝐹𝑐𝑎𝑛𝑐𝑒𝑙𝑙𝑒𝑟−𝐼𝐿+𝐶𝑅𝑋10 ) where IL is the insertion loss of the SIC filter. That does not include the intentional loss added to mimic the channel attenuation but only the loss intrinsic to the circuit. Table 3-1 summaries the requirements for different blocks in a simultaneous full-duplex receiver for a channel bandwidth of 80 MHz, assuming a receiver IIP3 of 0.5 dBm and NFRX of 5 dB.  Table 3-1 Minimum system requirements for different isolation Isolation (dB) 20  25  30  SICtotal (dB) 105  105  105  SICRF + SICA-BB (dB) 37  27  17  ADC DR (dB) 80  65  50  SICRF (dB) 29.5  24.5  19.5  SIC OIP3 (dBm) 5.5  10.5  10.5  NFSIC (dB) 17.7  17.7  17.7  NFRX, total (dB) 11.4 8.2 8.2 36  3.2. Circuit Description The circuit block diagram is shown in Figure 3.5. The circuit was implemented in IBM 0.13µm RF process. Three taps of self-interference cancellation were implemented; the first two are identical whereas the third tap has an extended envelope delay capability that will be explained later in subsection 3.2.4. Each tap has two variable resistors at the input and output ports to provide 50Ω matching. A variable coupling capacitor Cc has been added at the output to tune the coupling strength (CRX) to ensure minimum receiver noise figure degradation as explained in subsection 3.1.6.   Figure 3.5 Overall system block diagram 37  3.2.1. Matching Circuits The matching circuits are required to be broadband so that the operating frequency of the filter is only dependent on the clock frequency. Thus, resistive matching is chosen to maintain broadband operation despite the additional insertion loss that it introduces. As CMOS resistors are not very precise and vary greatly with process and temperature, a switched resistor bank is implemented to tune the resistance after fabrication, as shown in Figure 3.6.  Figure 3.6 Matching resistors bank 3.2.2. Mixer Circuits The mixers are implemented as double-balanced voltage-mode passive mixers as shown in Figure 3.7. Passive mixers are chosen for their high linearity, low flicker noise and low power consumption. The mixers are operated as ON/OFF switches controlled by the clock signals and hence have very low ON resistance and very high OFF resistance, which makes them very linear. Also, they do not consume any DC current or power, and at the same time, produce minimum flicker noise. However, voltage-mode passive mixers, instead of contributing any gain, add a 4.4 dB loss per mixer [2]. This results in an 8.8 dB total loss in the signal path of cancellation circuit 38  from downconverting and upconverting mixers. A double-balanced architecture is chosen to mitigate even order non-linearity and DC offset, a common problem in direct-conversion receivers. And the use of a differential output reduces the required low pass filter capacitance by four times saving considerable area. Instead of implementing two separate capacitors of C each, a 4 smaller capacitance of C/2 can be connected between the two outputs.  The mixers are implemented as I/Q pairs to extract the I/Q envelopes of the signal separately and implement the Hilbert transform scaling, as discussed before. They are driven by non-overlapping, 4-phase, 25% duty cycle clocks to minimize losses and cross-talk between the different paths.  Figure 3.7 Double-balanced passive mixer Passive mixers have the property of bidirectional impedance transformation. For example, a dowconverting passive mixer downcoverts the signal at its RF port and at the same time, upconverts the signal at its baseband port. This results in the upconversion of their baseband impedance to an RF impedance at the input port. In case of the self-interference cancellation filter, 39  the baseband impedance is a low pass filter which appears at the RF port as a band pass filter. The band pass filter is centered around the local oscillator (LO) frequency driving the mixers and has a bandwidth equivalent to the baseband bandwidth [19].  Additionally, this impedance upconversion improves the out-of-band linearity of the filter by suppressing the out-of-band signals at the baseband port and as a result, they become attenuated at the RF port by the band pass response roll-off [19]. However, the thermal noise of the downconverting passive mixer transistors from all of the LO harmonic frequencies get folded back and added up at baseband, while the thermal noise of the upconverting passive mixer transistors from all of the LO harmonic frequencies get folded and added up at fc (the center frequency) contributing to the output noise of the filter [19]. 3.2.3. LO Generation Circuit The required LO signal is an N-phase non-overlapping clock that has the same frequency as the RF input frequency (fRF). This provides filtering centered around fRF as explained above. The choice of N is a design parameter. On one hand, increasing N provides lower insertion loss, less harmonic folding [20], better impedance tuning and noise performance [21]. On the other hand, increasing N requires much more dynamic power in the LO generation and driving circuitry [21]. As a compromise between power consumption and performance metrics, the LO circuit is designed to operate at the frequency of 1 GHz with four phases. The 4-phase generation circuit from [22], shown in Figure 3.8, is used. It consists of two back-to-back flip-flops acting as a divide-by-two circuit producing I and Q phases, followed by AND gates to produce the 25% duty cycle signals.  40   Figure 3.8 LO generation circuit The 4-phase generation requires feeding an external differential clock (CLK) at twice the required LO frequency. The flip-flops are implemented in current-mode-logic (CML) [23] to allow high speed operation with low swing, followed by SR latches to convert the signal to full rail (Figure 3.9).  Figure 3.9 Flip-Flop implementation 41  3.2.4. Baseband Delay and Filtering As explained in section 2.3, a low pass filter can be used to implement the group delay required for the signal provided its cut-off frequency is much larger than the signal of interest bandwidth. Figure 3.10 shows a single pole low pass filter implementation in the canceller. RS models the sum of the 50 source resistance (from the signal generator) and the mixer switch ON resistance, and RT models the total resistance seen at the output node, looking into the attenuators α and β, the upconverting mixers and the termination resistors (Figure 3.5).  Figure 3.10 Single pole low pass filter The delay (τ) provided by the low pass filter can be derived as follows: 𝑉𝑂𝑢𝑡𝑉𝐼𝑛(𝑗𝜔) = 𝐻(𝑗𝜔) =  𝑅𝑇(𝑅𝑇 + 𝑅𝑠)(1 + 𝑗𝜔𝑅𝑇𝑅𝑠𝑅𝑇 + 𝑅𝑠𝐶) ∠𝐻(𝑗𝜔) =  − 𝑡𝑎𝑛−1(𝜔𝑅𝑒𝑞𝐶) where 𝑅𝑒𝑞 =  𝑅𝑇𝑅𝑠𝑅𝑇+𝑅𝑠 𝜏 =  −𝑑∠𝐻(𝑗𝜔)𝑑𝜔=  𝑅𝑒𝑞𝐶1 +  (𝜔𝑅𝑒𝑞𝐶)2 Since ω << ReqC by design to prevent signal dispersion, then: OUTIN RsRTC42  𝜏 ≅  𝑅𝑒𝑞𝐶 The delay can be further extended by increasing the order of the low pass filter to second order as shown in Figure 3.11. For fair comparison with the first order filter, the amount of capacitance used is the same but it is split into two portions separated by resistance Rp. Rp together with RT and C/2 form a first order filter similar to the one in Figure 3.10. And their equivalent impedance Zin cascaded with Rs and the other C/2 form a second filter. However, because the two filters load each other, the total delay is not exactly twice the delay of a single pole low pass filter. Also, the range of the second filter delay is reduced because the left capacitor is now fixed.  Figure 3.11 Second order low pass filter  The transfer function of the second order filter is: 𝐻(𝑗𝜔) =  4𝑅𝑇[4(𝑅𝑠+𝑅𝑝 + 𝑅𝑇) − 𝜔2𝑅𝑠𝑅𝑝𝑅𝑇𝐶2] + 𝑗2𝜔(2𝑅𝑠𝑅𝑇 + 𝑅𝑠𝑅𝑝 + 𝑅𝑝𝑅𝑇)𝐶 The delay of a cascade of two RC sections is derived in [24] and shown to not be significantly greater than the delay of a single pole filter. However, in the proposed implementation, the loading the two RC sections by RT gives a considerable delay increase. Figure 3.12 shows the result of a circuit simulation of the group delay of a first order filter and a second order filter loaded by the OUTIN RsRTC/2 C/2RPZin43  input resistance of attenuators α and β. The second order filter exhibits a larger delay for equal bandwidth as the first order filter, or conversely more bandwidth for the same amount of delay. The third tap of the canceller in Figure 3.5 uses a second order low pass filter as a delay element.  Figure 3.12 Group delay of first order filter vs. second order filter Finally, the variable capacitor is implemented using a 6-bit bank of binary weighted dual metal-insulator-metal (MIM) capacitors, as shown in Figure 3.13. An always-ON capacitance with a value equal to the least significant bit is added to reduce differential non-linearity of the capacitor bank. 44  Cb0b02Cb1b132Cb5b5CIN_NIN_POUT_NOUT_P Figure 3.13 Low pass filter variable capacitor 3.2.5. Variable Attenuators  The attenuators are required to present a constant input impedance in order to not affect the delay of the low pass filter. In addition, they are preferred to be linear unlike the gm cells used in [10] in order to not degrade the overall filter linearity. Consequently, the attenuators are implemented as 6-bit bank of binary weighted current-steering differential pairs in the signal path, as shown in Figure 3.14. They do not consume any power and operate only as switches that direct the current in either the positive or negative directions of the output. The difference between the current steered into the positive terminal and the current steered into the negative terminal determines the amount of attenuation. In addition, as the same number of switches is always turned ON (26) and only the direction of the switches that are ON changes, the input impedance of the attenuator is fixed across codes. Another important feature in the attenuators is their capability to flip the sign of the signal (180⁰ phase shift) individually in each attenuator by setting the sign bit which is the 45  most significant bit. It should be noted that this feature is not implemented in [9], and hence it is not possible to implement equation (2.4) in that design.   Figure 3.14 Current-steering differential attenuator 3.2.6. Coupling Capacitors The coupling capacitor is made variable to vary the coupling strength as well as the noise of the self-interference cancellation signal injected into the receiver. It is implemented as a 4-bit binary weighted capacitor bank using MIM capacitors, with an option to completely bypass it by setting bit b3 = 1, as shown in Figure 3.15. 46  IN_N OUT_Nb3b2b1b0IN_P OUT_P4C2CCb3b2b1b04C2CC Figure 3.15 Coupling capacitor bank   47   Chapter 4:  Layout and Printed Circuit Board Design 4.1. Layout Considerations A die photo is shown in Figure 4.1 with each part of the circuit labelled. The active area occupied by the circuits is 1.7 mm x 0.8 mm. The clock generation circuit is placed as close as possible to the input clock running at twice the frequency to minimize the routing distance. The clocking circuit is placed in the middle between the first and second tap of the canceller to make the routing of the 4-phase clocks going to both taps symmetric. Due to area constraint, it was not possible to place the third tap in the vicinity of the clock generation circuit. All high frequency signals including the self-interference cancellation filter inputs, outputs and the clock inputs are routed on the two top metal layers E1 and MA to minimize their path resistance and capacitance. These top two metal layers have the lowest resistance in this CMOS process. A scan chain has been synthesized and placed on-chip to provide testing capability by loading the digital bits with a serial to parallel interface (SPI). An on-chip decoupling capacitor is added to filter the noise on the LO supply rail. All the pads are leveraged from the IBM library and are sized at 53µm x 53µm. Each pad has a human body model (HBM) electro-static discharge (ESD) 48  protection circuit that is also from the IBM library. No charge device model (CDM) ESD or clamps were used – this was a design hindsight, rendering the chip susceptible to ESD events.   Figure 4.1 Die photo 4.1.1. Self-Interference Canceller Tap 1 & 2 Layout The first two taps of the self-interference canceller are identical and consist of an input matching resistor bank, an I/Q downconverting mixer, two capacitor banks, four attenuator banks, an I/Q upconverting mixer, an output matching resistor bank and a coupling capacitor bank. Decap 49  The impedance matching resistors are chosen as polysilicon resistors due to their high current carrying capability and high resistivity, and hence, higher area efficiency. The current rating is important in this design because the input, the self-interference signal tapped from the output of a power amplifier, is a large signal. It is not recommended to use n-well resistors, in spite of their large current carrying capability, with signals interfacing with the I/Os of the chip to avoid latch-up and ESD problems. The mixers are made using RF transistors surrounded by guard rings to reduce substrate-coupled noise. RF transistors are also more accurately modeled in the process. The transistors in the mixers are designed to have a very low ON resistance of approximately 3 Ω, with minimum length and a large width of 400 µm. However, this large width increases the loading on the clock buffers that drive these transistors, thereby requiring more power consumption from the LO circuit. The low pass filter capacitor bank is made using dual MIM capacitors. They have low leakage and high density and therefore do not occupy a very large area. The capacitor bank shown in Figure 4.22 is composed of 64 unit capacitors and laid out in a common-centroid fashion to improve matching. The switches controlling the amount of capacitance connected are laid out underneath the capacitors. The unit capacitance is chosen to be 1 pF realising a delay step of 25 ps and a total capacitance of 64 pF, equivalent to 1.6 ns delay range. 50    Figure 4.2 Capacitor bank layout The current-steering differential pairs in the attenuators are also broken down into 64 units to improve linearity (Figure 4.3). In other words, the bigger transistors are implemented as multiple unit sized devices in shunt. They are laid out in a common centroid scheme and a dummy unit is added to improve matching. 320 µm 320 µm 51    Figure 4.3 Attenuator layout The first two taps occupy an area of 765 µm x 370 µm each excluding the matching resistors and coupling capacitor, as shown in Figure 4.4.  Figure 4.4 Self-interference canceller Tap 1 and Tap 2 layout 765 µm 45 µm 65 µm 370 µm 52  4.1.2. Self-Interference Canceller Tap 3 Layout The third tap has an additional resistor bank that splits the delay capacitor into two parts: the first part is a fixed 32 pF and the other is a variable 5-bit 32 pF capacitance. 4.1.3. LO Circuit Layout The layout for the clock generation and distribution circuit is shown in 5. The clock input from the external source comes in and gets divided by two to generate the quadrature phases. Those phases are distributed to four different AND gates via buffers. The outputs of the AND gates which are 25% duty-cycle non-overlapping clocks are distributed to the three self-interference filter taps using three sets of clock driving buffers. Each set of these buffers has a separate enable signal that turns ON a specific tap in the filter. Each differential pair of the four phases are routed next to each other to reject common-mode noise: the 0⁰ phase next to the 180⁰ phase and the 90⁰ phase next to the 270⁰ phase. The output 4-phase clocks are then routed on the top two metal layers MA and E1 to minimize their path resistance and capacitance. 53    Figure 4.5 LO generation circuit layout 4.2. Printed Circuit Board Design The chip is packaged in a CQFP-120 pin package. The bondwire inductance is estimated to be 5 nH. A four-layer printed circuit board (PCB) is designed to test the circuit. Four-layer circuit boards are recommended for RF applications to realise isolation on signal lines, control the impedance matching and prevent noise coupling on-board [25].  The first layer is used to route the RF signals on the left side of the board and DC signals on the right side. The middle two planes are used as ground planes: a general ground plane and an LO ground plane. The LO ground plane is placed separately to prevent current transients in the LO to couple into the rest of the circuit. The bottom layer is used to connect some DC signals. 260 µm 420 µm LO3_0 LO3_180 LO3_90 LO3_270 LO2_0 LO2_180 LO2_90 LO2_270 LO1_0 LO1_180 LO1_90 LO1_270 Divide by 2 AND gates Buffers 54  The signal lines are designed to have 50Ω impedance and are hence sized at 7.32 mils width. The power lines are sized to provide enough current carrying capability at 15.75 mils width. It was found that for all other DC signals a width of 7.9 mils provides enough current carrying capability. The PCB designed is shown in Figure 4.6. The external LO signal at twice the frequency is supplied single-endedly to an on-board balun that generates differential clocks. The differential clocks are then capacitively coupled to the chip inputs to remove any DC bias. The rest of the RF signals are supplied differentially using in-line 180⁰ hybrid couplers. The DC power is provided to the circuit from 1.2 V external power supplies via header pins and low dropout regulators (LDO) that can be bypassed on-board using jumpers. The power lines are decoupled using four bypass capacitors having the values of 0.1 µF, 1 µF, 10 µF and 100 µF.     55   Figure 4.6 PCB design # 1.  After the PCB was manufactured, it was found that in order to control the on-chip scan chain using a microcontroller, the outputs of the microcontroller have to be stepped down from 3.3 V to 1.2 V, the core voltage of the chip. An external resistive voltage divider on a breadboard was used to step down the microcontroller voltage. However, it was also found that the footprint of the on-board balun was designed wrong on the PCB, preventing the proper operation of the LO circuit. This rendered the board inoperative. A second version of the PCB shown in Figure 4.7 was designed to fix these errors. 56   Figure 4.7 PCB design #2 In this board, the on-board balun is removed and two SMA connectors are placed to provide a differential clock signal from an Anritsu MP1763B differential pulse pattern generator (PPG). A resistive voltage divider was also added on-board using 1 kΩ and 1.7 kΩ resistors to provide the voltage step down for the microcontroller’s outputs.   57   Chapter 5:  Simulation and Measurement Results 5.1. Simulation Results The circuit was first simulated at a center frequency of 2 GHz. Then it was found through measurement that the maximum operating frequency is 900 MHz, limited by the clocking circuit due to extremely long package bondwires (5 mm long). So, some of the schematic simulation results are reported at 2 GHz whereas some post-layout simulations which were rerun after measurement are reported at 900 MHz. The first simulation result is the self-interference cancellation tap 1 insertion loss shown in Figure 5.1. The insertion loss is 29.7 dB (shown in grey) in schematic simulation and 29.9 dB in post-layout (shown in blue). 58   Figure 5.1 Simulated SIC tap 1 insertion loss The simulated noise figure is shown next in Figure 5.2. The schematic simulation yields 29.1 dB whereas in post-layout simulation, the noise figure increases to 29.3 dB. The noise figure seems high because the insertion loss adds directly to it but the additional noise added by the filter to the receiver is much smaller, as discussed in subsection 3.1.6.  Figure 5.2 Simulated SIC noise figure 59  The input referred 1-dB compression point of the self-interference canceller is shown in Figure 5.3. The value from the schematic simulation at 900 MHz is about 11.8 dBm. Due the non-linear time varying nature of the circuit where two frequency translations happen, it is not possible to simulate the IIP3 using Spectre® RF. But it can be roughly estimated to be 9 dB above the 1-dB compression point [2].  Figure 5.3 Input referred 1-dB compression point of the canceller Next, the range and resolution of the self-interference canceller parameters are verified. These were simulated in schematic only as they require sweeping thousands of combinations of programmable bits and it is not feasible to simulate them in post-layout. Figure 5.4 shows the range and resolution of the first tap delay. The second tap is identical so it should have the same results. The envelope delay spans a range of 1.4 ns, from 277 ps to 1.7 ns in ~25 ps steps. 60   Figure 5.4 Tap 1 delay range and resolution The third tap delay using the second order low pass filter is shown in Figure 5.5. The delay spans a range of 2 ns from 1.6 ns to 3.6 ns in ~60 ps steps.  Figure 5.5 Tap 3 delay range and resolution The attenuation range and resolution are shown in Figure 5.6. It spans a range of 33 dB from -27.9 dB to -61 dB in steps of 0.25 dB. The phase shift range and resolution are shown in Figure 5.7. It is clear that the circuit provides full coverage of 360⁰ from -237⁰ to 123⁰ in 1⁰ steps. 61   Figure 5.6 Attenuation range and resolution  Figure 5.7 Phase shift range and resolution Another important parameter to verify is the change in group delay with the attenuators settings. As discussed in section 2.3 and subsection 3.2.5, the group delay should remain constant over different attenuator settings to decouple the group delay control from phase shift control. Figure 5.8 shows the group delay across attenuation settings with a total delay change of 130 ps. 62   Figure 5.8 Group delay change with attenuator settings Next the LO performance is verified. First, the 4-phase 25% duty cycle LO waveforms are plotted after routing in a post-layout simulation Figure 5.9.  Figure 5.9 Four phases of 25% duty cycle LO waveforms It is noted that there is an I/Q imbalance between the LO phases as well as differential imbalance. This post-layout simulation was not done before the chip tapeout, and led to performance 63  degradation in measurements, as described in the next section. Table 5-1 summarizes the amount of imbalance in seconds and degrees. Table 5-1: I/Q imbalance in the LO Ideal phase (⁰) Simulated absolute delay (ps) Ideal absolute delay (ps) Absolute delay error (ps) Absolute phase error (⁰) Simulated absolute phase (⁰) 0 0 0 0 0 0 90 240.7 277.8 37.05 -12.01 77.99 180 528.8 555.6 26.77 -8.67 171.33 270 821.3 833.3 12.02 -3.89 266.11 360 1111.1 1111.1 -0.06 0.02 360.02  Next, the LO to RF leakage and LO to IF leakage in the canceller circuit are simulated in post-layout. The LO leakage is harmful because it can produce DC offset and second order non-linearity that can saturate subsequent stages after the mixer. Figure 5.10 shows the LO to RF leakage at different harmonics up to 10 GHz and it is consistently below -65 dB. Figure 5.11 shows the LO to IF leakage to be consistently below -40 dB. However, this simulation does not capture random and systematic mismatches that are present in a manufactured chip, and therefore is very optimistic.   64   Figure 5.10 LO to RF leakage in SIC circuit  Figure 5.11 LO to IF Leakage in SIC circuit  Finally, a schematic simulation for cancellation using one tap of self-interference cancellation is shown in Figure 5.12. The channel used in the simulation is a distributed RLC transmission line, instead of a wireless channel. A perfect alignment of group delay, attenuation and phase shift is obtained which may not be the case in real measurements. In addition, the RLC channel has a very well-behaved response which may not be the case for a true wireless channel. So, the result is 65  considered a best case cancellation excluding the effects of parasitics from layout. 30 dB of cancellation over 80 MHz bandwidth is obtained. The upper portion of the figure shows the magnitude of the input signal (blue), the signal after the channel (green), the SIC output (red), and the subtraction of the SIC output from the channel output (black) using a 50Ω wideband balun. The bottom portion of the curve shows the phase of the channel output (red) and the phase of the SIC output (black).   Figure 5.12 One tap SI cancellation using RLC channel 5.2. Measurement Setup and Results The measurement setup consists of an Agilent MXG N5128B vector signal generator (VSG) that can generate a complex modulated RF signal. The output of the VSG is then split using a 0⁰ hybrid 66  coupler between the channel and the SIC filter. The SIC filter portion of the signal is then split again using another 0⁰ hybrid coupler between the first tap input and the second tap input. The channel is a formed by two monopole antennas separated by ~20 cm and inline attenuators that provide additional loss to match the SIC filter loss. The total loss in the channel is 50 dB. The output of the channel and the SIC filter are combined using a 0⁰ hybrid coupler and fed to an Anritsu VNA Master MS2034A spectrum analyzer to monitor the cancelled signal. All RF input and output signals are differential and are fed to the circuit using 180⁰ hybrid couplers. The 2 external clock signal is generated using the Anritsu MP1763B differential PPG and the differential clocks are fed to the circuit using phase-matched cables.  Figure 5.13 Measurement setup A Raspberry Pi® microcontroller is used to program the on-chip scan chain with the required digital bits to set different parameters of the circuit and to read the residual self-interference power after 67  cancellation from the spectrum analyzer. A sweep of the circuit parameters has to be run to find the optimum cancellation. First the RF performance of the circuit is demonstrated. It is found the circuit can operate at a maximum frequency of 900 MHz with all three taps turned ON. The insertion loss of the three taps of the filter is measured and shown in Figure 5.14. The insertion loss of the first two taps is measured to be 29.5 dB each, and 39 dB for the third tap. The first two taps insertion loss are in match with their post-layout simulated value in Figure 5.1.  Figure 5.14 Tap 1, 2 and 3 measured insertion loss 68  The return loss at both ports of the filter are measured. The results are shown in Figure 5.15. The return loss on the input port is -17 dB and on the output port is -14.5 dB, clearly demonstrating good matching to 50. The periodic dips in the return loss indicate several reflections that could be attributed to low quality SMA connectors on board.  Figure 5.15 S11 and S22 of the Tap-1 SIC filter 69  Next, the noise figure is measured to be 30 dB using an Agilent 364C noise source and an Agilent PXA N9030A spectrum analyzer with noise analysis capability as shown in Figure 5.16. The measured NF is less than 1 dB worse than the post-layout simulated NF.  Figure 5.16 Measured noise figure of the Tap-1 SIC filter The measured input referred compression point is 9 dBm as shown in Figure 5.17. This is 2.8 dB lower than the value found in schematic simulation.  Figure 5.17 Measured input referred 1-dB compression point of Tap-1 SIC filter 70  Two measurements are performed for IIP3: the in-band IIP3 using two tones around 900 MHz separated by 2 MHz, and the out-of-band IIP3 using two tones centered around 1.0136 GHz separated by 76 MHz such that they produce intermodulation products in the desired 900 MHz channel. The in-band IIP3 is measured to be 20.5 dBm and the out-of-band IIP3 is 24.5 dBm, as shown in Figure 5.18.  Figure 5.18 Measured in-band and out-of-band IIP3 for Tap-1 SIC filter 71  The first step in testing the amount of cancellation provided by the filter is to make sure that the channel group delay is within the range of the group delay that the canceller can provide. Figure 5.19 shows the channel delay measurement using the Anritsu VNA Master MS2034A. The channel group delay is 19.6 ns at 900 MHz.  Figure 5.19 Channel group delay Figure 5.19 shows the measured group delay of the three canceller taps vs. capacitor bank code. The first two taps have a 6-bit capacitor bank whereas the third tap has a 5-bit capacitor bank. Unfortunately, the delay range of the third tap is non-overlapping with the first two taps.  72   Figure 5.20 Measured Tap 1, 2 and 3 group delay Tap 1 and 2 delays span 1.4 ns with a 40 ps step in the linear regions of the curve. Tap 3 delay spans 3 ns with a 70 ps step. Next, Tap 1 and 2 are used for cancellation. In order to find the best settings for self-interference cancellation, the parameters τ1, α1 and β1 of tap 1 and τ2, α2 and -β2 of tap 2 in Figure 3.5 have to be swept across their 6-bit codes each while the residual interference power is read from the spectrum analyzer until the minimum power is found. However, after several optimizations of the microcontroller code, each iteration of writing to the scan chain and measuring the power from the analyzer takes on average 150 ms. That means the 73  total time required to measure all possible combinations is (26)6 x 150 ms which is thousands of days. Obviously, this exhaustive sweep becomes unfeasible and a shorter sweep must be conducted. The problem, however, is that we cannot use advanced search algorithms such as binary search to find the global minimum in the search space because the algorithm can get stuck in a local minimum. So, the following algorithm is used to provide exhaustive sweep of all parameters but not co-optimize all of them simultaneously: » Turn both Tap 1 and Tap 2 ON » Sweep the delay code of Tap 1 and Tap 2 and find maximum cancellation » Set delay 1 and delay 2 codes accordingly » Sweep α & β of Tap 1 while Tap 2 is ON and fixed to find maximum cancellation » Set α & β of Tap 1 accordingly » Sweep α & β of Tap 2 while Tap 1 is set to the values found in the previous step The maximum cancellation found is 15 dB over an 80 MHz RF bandwidth shown in Figure 5.21. However, the amount of cancellation is much lower than that found in the schematic simulation (Figure 5.12). So, a debug process is carried on to find the limiting factor of cancellation. First, we replace the channel with a cable to approximate the RLC channel used in simulation creating the test setup shown in Figure 5.22. But the results do not change significantly and the cancellation is still limited to 15 dB. Next, according to the post-layout simulation results in Table 5-1, the I/Q imbalance is suspected to be the limiting factor of the amount of cancellation achievable. 74   Figure 5.21 Two-tap cancellation over 80 MHz bandwidth for the wireless channel 2XLO1.8GHzRF Signal GeneratorSpectrum AnalyzerSIC FilterDUTmicrocontroller900 MHzQAM-16 Power Supplies50 dB loss 75  Figure 5.22 Wireline channel test setup To test this hypothesis, the effect of envelope delay has to be eliminated from the debugging process in order to only test the achievable magnitude and phase resolution by the circuit. This is done by turning OFF the modulation in the RF signal generator and using only a sinusoidal input signal as shown in Figure 5.23. 2XLO1.8GHzSpectrum AnalyzerSIC FilterDUTmicrocontrollerPower Supplies50 dB loss Figure 5.23 Sinusoidal input test setup The I/Q imbalance can be modelled in the circuit as an amplitude error ε and a phase error φ as shown in Figure 5.24. To counter the effect of I/Q imbalance, the parameters 1 and 2 can be set differently to introduce an intentional predistortion that is the inverse of the I/Q error. Similarly, 1 and -2 have to be set independently. But this results in four parameters that must be swept exhaustively instead of two, leading back to the problem of unreasonable sweep times. 76   Figure 5.24 SIC circuit diagram with I/Q imbalance This problem is overcome by reducing the search space. This means that the channel attenuation has to be placed within the range of attenuations of only the 5 least significant bits (LSB) of parameters  and  as shown in Figure 5.25, and the optimization is carried on for one tap only at a time.  Figure 5.25 Reduced search space for tap 1 77  First, it is verified that the 50 dB isolation in the channel falls within the range of attenuation of the 5 LSBs. Next, the sinusoidal input test is repeated with one tap cancellation and the result is 56 dB of self-interference cancellation as shown in Figure 5.26.   Figure 5.26 One tap cancellation of a sinusoidal tone signal in a wireline setup Then, for the same wireline channel and using the optimum 1, 2, 1 and -2 values found, the test is repeated with the 80 MHz modulated QAM-16 signal. The result is shown in Figure 5.27. The blue curve denotes the cancelled signal after setting the optimum  and  parameters achieving 22 dB cancellation. The yellow curve shows the cancelled signal after sweeping the group delay of the filter to match the channel group delay achieving 30 dB cancellation. It is obvious that matching the group delay provides more suppression and wider cancellation bandwidth than matching the magnitude and phase only. 78   Figure 5.27 Wireline channel 80 MHz cancellation Decoupling the optimization of the  and  parameters from the optimization of the τ parameter reduces the measurement time required significantly while ensuring the I/Q error is compensated in the circuit. Next, the same measurement procedure is followed using the wireless channel to demonstrate wireless cancellation. The setup is changed back to the one in Figure 5.13 and the results in Figure 5.28 show 19 dB cancellation by  and  optimization and 23 dB by further adding the τ optimization for one tap. This result proves that the cancellation is sensitive to I/Q errors in the LO as fixing the I/Q error increased the cancellation by 8 dB more than the result in Figure 5.21. 79   Figure 5.28 Wireless channel 80 MHz modulated signal one tap cancellation with I/Q error correction The entire power of the circuit is only dissipated in the LO generation and distribution circuit, as shown in Table 5-2, when measured from a 1.2 V supply. Table 5-3 compares the measured results of the implemented self-interference cancellation circuit against those obtained through simulations. Table 5-2: Power Consumption  current (mA) Power (mW) LO divider 8.8 10.6 Divider + 1 tap 19.6 23.5 Divider + 2 taps 28.3 34  80  Table 5-3 Comparison of simulated and measured results  Simulated Measured Tap 1 Insertion Loss [dB] 29.9 29.5 Noise Figure [dB] 29.3 30 IP1dB [dBm] 11.8 9 IB-IIP3 [dBm] N/A 20.5 OB-IIP3 [dBm] N/A 24.5 1-tap cancellation 30 23a/30b Power Consumption [mW] 37 34 VDD [V] 1.2 1.2  aUsing a wireless channel/bUsing a microwave cable channel    81   Chapter 6:  Conclusions and Future Work 6.1. Conclusions In this work, a compact, tunable and monolithic self-interference cancellation circuit prototype achieving 23 dB of self-interference suppression is demonstrated. The circuit achieves a very good linearity due to the lack of any active gain stages while consuming only 34 mW total power and 0.84 mm2 of area. This work compared to previous integrated works demonstrates comparable self-interference suppression using an older CMOS technology. It demonstrates, to the best of our knowledge, the widest self-interference cancellation bandwidth reported so far while occupying a fraction of the area occupied by other designs (after discounting their part of the area occupied by the receiver for the sake of fair comparison). Moreover, it demonstrates comparable or lower power consumption in the canceller circuit when compared to other works; and unlike [10], the power consumption in the canceller is constant and does not change with the settings of the circuit. A summary of the comparison with previous integrated works is shown in Table 6-1.  82   Table 6-1: Comparison to previous IC works  [10] [9] This work Architecture Active N-Path Frequency Equalization Frequency-Flat Passive VM Passive Hilbert-Transform Complex VM Center Frequency [MHz] 1400 2500 900 Cancellation BW [MHz] 25 24 80 Out-of-Band IIP3 [dBm] 25/27+ 22+ 24.5 P1dB [dBm] -8+ 1.5+ 9 Cancellation [dB] 20 27 23 Number of taps 2 1 2 In-Band IIP3 [dBm] 2+ 21.5+ 20.5 NF Degradation* [dB] 1.1 to 1.3 4.8 to 7 2.1 Power Consumption [mW] 88 to 184 23 to 56 (incl. RX) 34 Area [mm2] 4.8 2 0.84 CMOS Process [nm] 65 65 130 +Measured at the output of the receiver with respect to SIC input. *Assumes a 5 dB RX NF  It is concluded that the cancellation is very sensitive to the I/Q error in the LO phases. It is also concluded that complex Hilbert-transform-based scaling does indeed provide a wide cancellation bandwidth with fewer number of taps. 6.2. Future Work The first suggested future enhancement to the circuit is to correct I/Q phase imbalance in the LO generation and distribution circuit. This is a relatively easier fix that should yield even better 83  performance for self-interference cancellation, and reduce the number of exhaustive sweeps needed. The second suggested work is to add a closed loop calibration block to automatically detect the level of the residual self-interference and adjust the canceller parameters. This would eliminate the need to perform sweeps externally using digital scan and detect the power using a spectrum analyzer, which is currently limiting the possible measurement time.  The third suggested work is the addition of a power amplifier (PA) and/or an on-chip coupler from the PA output to the self-interference canceller input. This must be done in a way that does not degrade the PA efficiency and integrates with the current self-interference canceller to eliminate the need for input matching. Finally, an isolation of 20 dB is required from a circulator in a small form factor. Design of circulators that can provide such performance should be pursued.   84   Bibliography [1] A. V Oppenheim, A. S. Willsky, and S. H. Nawab, Signals and Systems, 2nd ed. Upper Saddle River, N.J.: Prentice Hall PTR, 1997. [2] B. Razavi, RF Microelectronics, 2nd ed. Upper Saddle River, NJ, USA: Prentice Hall Press, 2011. [3] “Vidéotron wins wireless licences outside Quebec in 700MHz auction,” CBC News, 2014. [4] D. Bharadia, E. McMilin, and S. Katti, “Full duplex radios,” Proc. ACM SIGCOMM 2013, vol. 43, no. 4, p. 375, 2013. [5] J. Choi, M. Jain, and K. Srinivasan, “Achieving single channel, full duplex wireless communication,” MobiCom, p. 1, 2010. [6] Y. S. Choi and H. Shirani-Mehr, “Simultaneous transmission and reception: Algorithm, design and system level performance,” IEEE Trans. Wirel. Commun., vol. 12, no. 12, pp. 5992–6010, Dec. 2013. [7] M. Duarte, C. Dick, and A. Sabharwal, “Experiment-driven characterization of full-duplex wireless systems,” IEEE Trans. Wirel. Commun., vol. 11, no. 12, pp. 4296–4307, Dec. 2012. [8] M. Duarte and A. Sabharwal, “Full-duplex wireless communications using off-the-shelf radios: Feasibility and first results,” Conf. Rec. - Asilomar Conf. Signals, Syst. Comput., pp. 1558–1562, 2010.   85  [9] D. J. Van Den Broek, E. A. M. Klumperink, and B. Nauta, “An in-band full-duplex radio receiver with a passive vector modulator downmixer for self-interference cancellation,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3003–3014, Dec. 2015. [10] J. Zhou, T. H. Chuang, T. Dinc, and H. Krishnaswamy, “Integrated wideband self-interference cancellation in the RF domain for FDD and full-duplex wireless,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3015–3031, Dec 2015. [11] J. Tamminen, M. Turunen, D. Korpi, T. Huusari, Y. Choi, and S. Talwar, “Digitally-controlled rf self-interference canceller for full-duplex radios,” Proc. European Wireless Conference, pp. 1–5, 2016. [12] L. E. Franks and I. W. Sandberg, “An alternative approach to the realization of network transfer functions: the N-Path filter,” Bell Syst. Tech. J., vol. 39, no. 5, pp. 1321–1350, Apr. 1960. [13] G. Agrawal, S. Aniruddhan, and R. K. Ganti, “Multi-band RF time delay element based on frequency translation,” Proc. - IEEE Int. Symp. Circuits Syst., pp. 1368–1371, 2014. [14] T. S. Rappaport, Wireless communications : principles and practice, 2nd ed. Upper Saddle River, N.J.: Prentice Hall PTR, 2002. [15] D. Tse and P. Viswanath, Fundamentals of Wireless Communication. New York: Cambridge university press, 2005. [16] “Complex permittivity.” [Online]. Available: https://en.wikipedia.org/wiki/Permittivity#Complex_permittivity. [Accessed:01-Dec 2016]. [17] D. Pozar, Microwave Engineering. 4th ed. John Wiley & Sons, 2009. [18] J. Zhou, A. Chakrabarti, P. R. Kinget, and H. Krishnaswamy, “Low-noise active cancellation of transmitter leakage and transmitter noise in broadband wireless receivers for FDD / co-existence,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 3046–3062, Dec. 2014. 86  [19] A. Molnar and C. Andrews, “Impedance, filtering and noise in N-phase passive CMOS mixers,” Proc. Cust. Integr. Circuits Conf., 2012. [20] A. Ghaffari, E. A. M. Klumperink, M. C. M. Soer, and B. Nauta, “Tunable high-q n-path band-pass filters: modeling and verification,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 998–1010, May 2011. [21] D. Yang, C. Andrews, and A. Molnar, “Optimized design of N-phase passive mixer-first receivers in wideband operation,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 62, no. 11, pp. 2759–2770, Nov. 2015. [22] C. Andrews and A. C. Molnar, “A passive mixer-first receiver with digitally controlled and widely tunable RF interface,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2696–2708, Dec. 2010. [23] I. Fabiano, M. Sosio, A. Liscidini, and R. Castello, “SAW-less analog front-end receivers for TDD and FDD,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3067–3079, Dec. 2013. [24] N. E. H. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. 2013. [25] S. Aniruddhan, A Fast-locking Frequency Synthesizer for GSM Base-stations in 180nm CMOS. Ph.D. Thesis, University of Washington, 2006.  

Cite

Citation Scheme:

        

Citations by CSL (citeproc-js)

Usage Statistics

Share

Embed

Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                        
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:
https://iiif.library.ubc.ca/presentation/dsp.24.1-0340470/manifest

Comment

Related Items