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A single-stage interleaved resonant power factor correction converter Saasaa, Raed 2016

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A Single-Stage InterleavedResonant Power FactorCorrection ConverterbyRaed SaasaaB.Sc. Hons., Cairo University, 2011A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinTHE COLLEGE OF GRADUATE STUDIES(Electrical Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Okanagan)September 2016c© Raed Saasaa, 2016        The undersigned certify that they have read, and recommend to the College of Graduate Studies for acceptance, a thesis entitled:   A Single-Stage Interleaved Resonant Power Factor Correction Converter  Submitted by           Raed Saasaa                                            in partial fulfillment of the requirements of   The degree of     Master of Science in Electrical Engineering                        .                                                                       Wilson Eberle , Applied Science/School of Engineering Supervisor, Professor (please print name and faculty/school above the line)  Mohammed Agamy, Applied Science/School of Engineering Co-Supervisor, Professor (please print name and faculty/school in the line above)  Liwei Wang, Applied Science/School of Engineering Supervisory Committee Member, Professor (please print name and faculty/school in the line above)  Sunny Li, Applied Science/School of Engineering University Examiner, Professor (please print name and faculty/school in the line above)   External Examiner, Professor (please print name and university in the line above)    (Date submitted to Grad Studies)  Additional Committee Members include:   Please print name and faculty/school in the line above   Please print name and faculty/school in the line above     AbstractApplications requiring DC voltages vary widely, from low power, such as LED light-ing, to high power, as in industrial motor drives and battery chargers. Accordingly,a unified power architecture for all applications is not practical for efficiency, size andcost optimization. The use of LED lighting system became popular due to its manyadvantages. The new outdoor applications such as street and flood lighting require highpower (i.e. >200 W) in contrast to the low power existing LED drivers. Generally, theconventional architecture of AC/DC converters consists of two main stages; The first iscurrent-shaping stage to improve PF and the second is to provide isolation and tightregulation over the output voltage.Recently, the research on AC/DC converters has focused on optimizing the con-verter design to be more reliable and efficient for low and medium power applications.Specifically, techniques have been proposed to eliminate the DC output bus electrolyticcapacitor by introducing auxiliary DC/DC converter. On the other hand, the integratedconverters were deployed by many researchers to decrease the number of switches, facil-itate the controller design, and improve the efficiency.This thesis presents a novel single-stage AC/DC converter that can achieve highpower factor with reduced switching losses for semiconductor devices. The topologyis derived by integrating the interleaved boost-type PFC and full bridge LLC resonantconverters. Due to interleaving at the input, the converter exhibits less input currentripple compared to the existing topologies. Therefore, it is suitable for applications upto approximately 500 W. A detailed analysis of the operation modes is presented. Also,a 350–W prototype is designed to verify the effectiveness of the topology.iiTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiDedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiiChapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Power Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1.1 Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1.2 Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . 31.2 Current Harmonics Standards . . . . . . . . . . . . . . . . . . . . . . . . 41.3 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 2: Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Conventional PFC Approach . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 Analysis of Basic Topologies for PFC Applications . . . . . . . . . . . . . 82.2.1 DCM Operation Analysis . . . . . . . . . . . . . . . . . . . . . . 9iiiTABLE OF CONTENTS2.2.2 Boost Converter Analysis under DCM . . . . . . . . . . . . . . . 112.3 Isolated DC/DC Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 132.4 Review of Integrated AC/DC Converters . . . . . . . . . . . . . . . . . . 152.4.1 Flyback PFC Converter . . . . . . . . . . . . . . . . . . . . . . . 152.4.2 Bridgeless Half Bridge Integrated PFC . . . . . . . . . . . . . . . 172.4.3 Full Bridge Integrated PFC . . . . . . . . . . . . . . . . . . . . . 192.4.4 Three Level Integrated PFC . . . . . . . . . . . . . . . . . . . . . 202.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Chapter 3: Analysis and Operation of Proposed Integrated PFC Con-verter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.2 Proposed Integrated PFC Topology . . . . . . . . . . . . . . . . . . . . . 223.3 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.3.1 Mode 1: (to → t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.3.2 Mode 2: (t1 → t2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.3.3 Mode 3: (t2 → t3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.3.4 Mode 4: (t3 → t4) and Mode 5: (t4 → t5) . . . . . . . . . . . . . . 293.3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.4 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.4.1 Boost Cell Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 313.4.2 Resonant Tank Analysis . . . . . . . . . . . . . . . . . . . . . . . 353.5 Control Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.5.1 Effect of Duty Cycle (D) . . . . . . . . . . . . . . . . . . . . . . . 383.5.2 Effect of Switching frequency (fs) . . . . . . . . . . . . . . . . . . 413.5.3 Proposed Control Technique . . . . . . . . . . . . . . . . . . . . . 423.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42ivTABLE OF CONTENTSChapter 4: Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 434.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434.3 Boost Cell Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444.3.1 Input Inductors (L1 and L2) Design . . . . . . . . . . . . . . . . . 444.3.2 DC Bus Capacitor (Cdc) Design . . . . . . . . . . . . . . . . . . . 464.4 Resonant Tank Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.4.1 Magnetizing Inductance (Lm) Design . . . . . . . . . . . . . . . . 474.4.2 Resonant Components (Lr and Cr) Design . . . . . . . . . . . . . 494.5 Practical Design Consideration . . . . . . . . . . . . . . . . . . . . . . . 494.6 Experimental Prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.7 Experimental Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.7.1 Full Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . 534.7.2 Half Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . 604.7.3 Off-Nominal Input AC Operation . . . . . . . . . . . . . . . . . . 674.8 PF and THD Measurements . . . . . . . . . . . . . . . . . . . . . . . . . 714.9 Efficiency Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 734.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Chapter 5: Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.2.1 Modeling and Control . . . . . . . . . . . . . . . . . . . . . . . . 775.2.2 Topology Modification . . . . . . . . . . . . . . . . . . . . . . . . 78Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79vList of TablesTable 1.1 IEC 61000-3-2 Standards . . . . . . . . . . . . . . . . . . . . . . . 4Table 4.1 Design requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 43Table 4.2 Passive components . . . . . . . . . . . . . . . . . . . . . . . . . . 50Table 4.3 Semiconductor devices . . . . . . . . . . . . . . . . . . . . . . . . 51viList of FiguresFigure 2.1 Two stage PFC architecture . . . . . . . . . . . . . . . . . . . . . 7Figure 2.2 DCM operation of the basic switching converters. . . . . . . . . . 9Figure 2.3 Input current of switching converters comparison. . . . . . . . . . 10Figure 2.4 Boost converter PFC modes of operation [6]. . . . . . . . . . . . 11Figure 2.5 Boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 2.6 DCM operation waveforms of boost converter. . . . . . . . . . . . 12Figure 2.7 Phase shifted full-bridge converter. . . . . . . . . . . . . . . . . . 14Figure 2.8 LLC resonant converter. . . . . . . . . . . . . . . . . . . . . . . . 14Figure 2.9 Integrated AC/DC converter. . . . . . . . . . . . . . . . . . . . . 15Figure 2.10 Flyback PFC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 2.11 Totem-pole integrated PFC [12]. . . . . . . . . . . . . . . . . . . 17Figure 2.12 Bridgeless integrated PFC [14]. . . . . . . . . . . . . . . . . . . . 18Figure 2.13 Full bridge integrated PFC [15]. . . . . . . . . . . . . . . . . . . . 19Figure 2.14 Three level PFC [18]. . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 3.1 Conventional two-stage converter. . . . . . . . . . . . . . . . . . . 23Figure 3.2 Proposed integrated converter. . . . . . . . . . . . . . . . . . . . 23Figure 3.3 Operation modes waveforms. . . . . . . . . . . . . . . . . . . . . 25Figure 3.4 Mode 1: (to → t1). . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 3.5 Mode 2: (t1 → t2). . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 3.6 Mode 3: (t2 → t3). . . . . . . . . . . . . . . . . . . . . . . . . . . 28Figure 3.7 Mode 4: (t3 → t4). . . . . . . . . . . . . . . . . . . . . . . . . . . 29viiLIST OF FIGURESFigure 3.8 Mode 5: (t4 → t5). . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 3.9 Normalized input current. . . . . . . . . . . . . . . . . . . . . . . 31Figure 3.10 PF in DCM boost . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 3.11 Effect of D on current ripples. . . . . . . . . . . . . . . . . . . . 34Figure 3.12 LLC equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . 35Figure 3.13 Effect of Q on LLC gain. . . . . . . . . . . . . . . . . . . . . . . 36Figure 3.14 Effect of k on LLC gain. . . . . . . . . . . . . . . . . . . . . . . . 37Figure 3.15 Tank voltage VAB at D < 0.5. . . . . . . . . . . . . . . . . . . . . 39Figure 3.16 Operation waveforms at D < 0.5. . . . . . . . . . . . . . . . . . . 39Figure 3.17 Effect of D on LLC gain. . . . . . . . . . . . . . . . . . . . . . . 41Figure 4.1 Inductor current over Ts at vin(pi/2). . . . . . . . . . . . . . . . . 44Figure 4.2 LLC equivalent circuit during deadtime td. . . . . . . . . . . . . . 48Figure 4.3 Equivalent circuit of boost cell during discontinuous time. . . . . 49Figure 4.4 Proposed solution for input diode voltage spikes. . . . . . . . . . 50Figure 4.5 Gate drivers auxiliary board. . . . . . . . . . . . . . . . . . . . . 51Figure 4.6 Photo of the experimental prototype. . . . . . . . . . . . . . . . . 52Figure 4.7 Measured waveforms of the rectified voltage vin, current it, andinductor current iL1. (Vin = 120V , Vo = 48V , Po = 350W , fs =135kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 4.8 Measured waveforms of the AC voltage vin, current iin, and it.(Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz) . . . . . . . . 54Figure 4.9 Measured waveforms of the output voltage Vo. (Vin = 120V , Vo =48V , Po = 350W , fs = 135kHz) . . . . . . . . . . . . . . . . . . 55Figure 4.10 Measured waveforms of the tank voltage VAB, current iLr, andresonant cap voltage vCr. (Vin = 120V , Vo = 48V , Po = 350W ,fs = 135kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56viiiLIST OF FIGURESFigure 4.11 Measured waveforms of the tank voltage VAB and diodes currentiD. (Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz) . . . . . . 56Figure 4.12 Measured waveforms of the output voltage Vo and diodes currentiD. (Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz) . . . . . . 57Figure 4.13 Measured waveforms of Q1 : current iQ1, gate to source VGS, anddrain to source VDS voltages at iin = 0. (Vin = 120V , Vo = 48V ,Po = 350W , fs = 135kHz) . . . . . . . . . . . . . . . . . . . . . . 58Figure 4.14 Measured waveforms of Q1 : current iQ1, gate to source VGS, anddrain to source VDS voltages at iin =√2Iin. (Vin = 120V , Vo =48V , Po = 350W , fs = 135kHz) . . . . . . . . . . . . . . . . . . 58Figure 4.15 Measured waveforms of Q4 : current iQ4, gate to source VGS, anddrain to source VDS voltages at iin = 0. (Vin = 120V , Vo = 48V ,Po = 350W , fs = 135kHz) . . . . . . . . . . . . . . . . . . . . . . 59Figure 4.16 Measured waveforms of Q4 : current iQ4, gate to source VGS, anddrain to source VDS voltages at iin =√2Iin. (Vin = 120V , Vo =48V , Po = 350W , fs = 135kHz) . . . . . . . . . . . . . . . . . . 59Figure 4.17 Measured waveforms of the rectified voltage vin, current it, andinductor current iL1. (Vin = 120V , Vo = 48V , Po = 172W , fs =140kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 4.18 Measured waveforms of the AC voltage vin, current iin, and it.(Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz) . . . . . . . . 61Figure 4.19 Measured waveforms of the output voltage Vo. (Vin = 120V , Vo =48V , Po = 172W , fs = 140kHz) . . . . . . . . . . . . . . . . . . 61Figure 4.20 Measured waveforms of the tank . . . . . . . . . . . . . . . . . . 62Figure 4.21 Measured waveforms of the tank voltage VAB, current iLr, andresonant cap voltage vCr. (Vin = 120V , Vo = 48V , Po = 172W ,fs = 140kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62ixLIST OF FIGURESFigure 4.22 Measured waveforms of the tank voltage VAB, current iLr, andprimary voltage Vpr. (Vin = 120V , Vo = 48V , Po = 172W , fs =140kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 4.23 Measured waveforms of the tank voltage VAB and diodes currentiD. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz) . . . . . . 63Figure 4.24 Measured waveforms of the output voltage Vo and diodes currentiD. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz) . . . . . . 64Figure 4.25 Measured waveforms of Q1 : current iQ1, gate to source VGS, anddrain to source VDS voltages at iin = 0. (Vin = 120V , Vo = 48V ,Po = 172W , fs = 140kHz) . . . . . . . . . . . . . . . . . . . . . . 65Figure 4.26 Measured waveforms of Q1 : current iQ1, gate to source VGS, anddrain to source VDS voltages at iin =√2Iin. (Vin = 120V , Vo =48V , Po = 172W , fs = 140kHz) . . . . . . . . . . . . . . . . . . 65Figure 4.27 Measured waveforms of Q4 : current iQ4, gate to source VGS, anddrain to source VDS voltages at iin = 0. (Vin = 120V , Vo = 48V ,Po = 172W , fs = 140kHz) . . . . . . . . . . . . . . . . . . . . . . 66Figure 4.28 Measured waveforms of Q4 : current iQ4, gate to source VGS, anddrain to source VDS voltages at iin =√2Iin. (Vin = 120V , Vo =48V , Po = 172W , fs = 140kHz) . . . . . . . . . . . . . . . . . . 66Figure 4.29 Measured waveforms of the rectified voltage vin and current it.(Vin = 140V , Vo = 48V , Po = 350W , fs = 140kHz) . . . . . . . . 67Figure 4.30 Measured waveforms of the output voltage Vo. (Vin = 140V , Vo =48V , Po = 350W , fs = 140kHz) . . . . . . . . . . . . . . . . . . 68Figure 4.31 Measured waveforms of the tank voltage VAB, current iLr, anddiodes current iD. (Vin = 140V , Vo = 48V , Po = 350W , fs =140kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68xLIST OF FIGURESFigure 4.32 Measured waveforms of the output voltage Vo and diodes currentiD. (Vin = 140V , Vo = 48V , Po = 350W , fs = 140kHz) . . . . . . 69Figure 4.33 Measured waveforms of the rectified voltage vin and current it.(Vin = 100V , Vo = 48V , Po = 350W , fs = 100kHz) . . . . . . . . 69Figure 4.34 Measured waveforms of the output voltage Vo. (Vin = 100V , Vo =48V , Po = 350W , fs = 100kHz) . . . . . . . . . . . . . . . . . . 70Figure 4.35 Measured waveforms of the tank voltage VAB, current iLr, anddiodes current iD. (Vin = 100V , Vo = 48V , Po = 350W , fs =100kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 4.36 Measured waveforms of the output voltage Vo and diodes currentiD. (Vin = 100V , Vo = 48V , Po = 350W , fs = 100kHz) . . . . . . 71Figure 4.37 Input current harmonics at full load. (Vin = 120V , Iin = 3.17A,Po = 350W , PF = 0.9967) . . . . . . . . . . . . . . . . . . . . . . 72Figure 4.38 Input current harmonics at 25% full load. (Vin = 120V , Iin =0.9944A, Po = 93W , PF = 0.9945) . . . . . . . . . . . . . . . . . 72Figure 4.39 Input current harmonics at low vin. (Vin = 100V , Iin = 3.837A,Po = 351W , PF = 0.9944) . . . . . . . . . . . . . . . . . . . . . . 73Figure 4.40 Efficiency measurements for different loading points. . . . . . . . 74Figure 4.41 Efficiency measurements for different input voltages. . . . . . . . 74xiAcknowledgementsAll praises and gratitude to Almighty Allah who gave me courage, strength andpatience to successfully complete this thesis work.This work would not have been possible without the support of many great indi-viduals. First, I would like to thank my supervisors, Prof. Wilson Eberle and Prof.Mohammed Agamy for their support throughout the process of developing this work tillthe end. They both supported me when I first started at UBCO and gave me anotherchance to work on power electronics after I was about to leave the field forever. Theirencouragement and support are unforgettable and will continue to affect my entire career.I would like also to thank my labmates Yanqi Yu, Sepehr Zarifmansour, and all theothers for the great environment they created and the discussions we had in the lab. Thetechnical help I got from Tim Giesbrecht and Marc Nadeau, is highly appreciated. I amvery grateful to my roommate Mohammed Yafia for his great friendship ad encourage-ment.Last but not the least, my sincere thanks go to Prof. Osama Mahgoub who firstintroduced me to power electronics and encouraged me to pursue postgraduate studies.xiiDedicationTo my parents who supported me emotionally and financially during my study period.xiiiChapter 1IntroductionAC transmission of electricity is widely used in electrical power. Usually, at thegeneration end, power is transmitted at high AC voltage levels to reduce losses on trans-mission lines. At the distribution point, step down transformers are used to deliver lowvoltage levels for residential and industrial areas. However, large portion of electricalloads requires DC source such as computers, battery chargers, LED lighting, and smallgadgets adapters (smart phones and tablets). Even the loads that consume AC powerdirectly, for instance induction motors and induction furnaces, depend mainly on con-verters, which are nonlinear and create a lot of harmonics in the current, to control andregulate the output.Such mismatch between the supply (AC) and the load demand (DC) causes problemsfor the electric grid if not considered on the load side. The perfect condition for theAC source is to see different loads emulated as pure resistance. In other words, the loadshould draw nearly sinusoidal current i(t), which is proportional to the source voltagev(t), with minimal harmonics. The required characteristics in the load current can besummarized in two points:• The wave shape should be proportional to the input AC voltage with low harmonicscontents.• The two waves (v(t) and i(t)) are aligned; there is no phase shift.11.1. Power Quality1.1 Power QualityPower quality is the key concept which quantifies the compliance of the load currentwith the electric grid requirements. Among many indices that should be observed toassure high power quality, power factor (PF) and total harmonic distortion (THD) areof great importance.1.1.1 Power FactorPower factor (PF) simply describes how perfectly the load utilizes the input linevoltage. In AC system, two quantities for power can be defined. Active power (P),which is calculated by (1.1), is the actual power consumed by the load and is measuredby Watt. Apparent or complex power (S) measured by (VA), is the multiplication of theRMS of both voltage and current supplied by the source. To have unity power factor,active and apparent power must be equal as in the case of resistor load. This yields tothe definition of power factor in equation (1.2).P =1T∫ T0v(t)i(t) dt (1.1)Power Factor =Active Power(P )Apparent Power(S)=V1I1 cos(φ1)V I(1.2)Assuming that the input AC voltage is sinusoidal and contains only the fundamentalcomponent (V = V1), only the fundamental component of the input current (I1) producesactive power as expressed in (1.2). The total RMS of the input current is denoted by(I) which includes fundamental as well as harmonic components. Using (1.2), PF canbe decomposed into two components. The first is the displacement factor , defined byequation (1.3), which represents the phase alignment between the voltage and the current.Whereas, the distortion factor indicates how close the current shape to sinusoidal is asexpressed in equation (1.4).21.1. Power QualityDisplacement Factor = cos(φ1) (1.3)Distortion Factor =I1I(1.4)1.1.2 Total Harmonic DistortionThe second index used to determine the amount of distortion in current is the to-tal harmonic distortion (THD). Assuming an arbitrary input current i(t), the Fourieranalysis can break down the current to fundamental and harmonic components as shownin (1.5), the analysis assumes odd symmetry in the current shape in which the wavecontains only odd harmonics. THD is defined as the ratio of the harmonic componentsRMS to the fundamental RMS as stated in (1.6). Low THD is desired for high powerquality.i(t) =√2I1 sin(ω1t+ φ1)︸ ︷︷ ︸Fundamental component+√2I3 sin(ω3t+ φ3) +√2I5 sin(ω5t+ φ5) + ...+√2In sin(ωnt+ φn)︸ ︷︷ ︸Harmonics components(1.5)THD =√∑i=3 I2iI1(1.6)The analysis of PF calculation shown previously, assumes that the input line is undis-torted with any harmonics. For a general input voltage, each component of the inputcurrent should be proportional to the corresponding component in the input voltage toachieve unity power factor as illustrated in (1.7) [1].PF = 1 ⇐⇒ In = VnRem(1.7)where Rem is the proportionality constant or the emulated resistance.31.2. Current Harmonics Standards1.2 Current Harmonics StandardsCurrent harmonics drawn by nonlinear loads have many negative effects on the electricgrid. For instance, line voltage distortion, radiated electromagnetic interference, andpoor utilization of the source are some of the undesirable effects. Certain regulations arenormally imposed on the permissible line current harmonics drawn by the loads. Withthe growing use of DC loads such as computers, LED lighting, and battery chargers, theregulations are becoming even tighter.Among the available line current harmonics standards, the International Electrotech-nical Commission (IEC) publishes widely used standards which are categorized mainlybased on the application and the power level. IEC 61000-3-2 Standards define the limitsof harmonic current emissions for equipments with current less than 16 A per phase.Within the standards, there are different classes. Class A is set for three phase balancedequipments and anything not included in the other classes. Class B includes portableand welding equipments and Class C includes lighting equipments. Finally, Class D is forpersonal computers and monitors. As shown in Table 1.1 [2], the limit of the permissiblecurrent for a given harmonic order is defined either by the absolute RMS value as in classA, B, and D or by the percentage to the fundamental component as in class C.Table 1.1: IEC 61000-3-2 Standardsnth Harmonic Class A Class B Class C Class D(A) (A) (% first harmonic) (mA/W)3 2.3 3.45 30 × PF 3.45 1.14 1.71 10 1.97 0.77 1.155 7 1.09 0.40 0.60 5 0.511 0.33 0.495 3 0.35≥ 13 0.21 0.315 3 3.85/n2 1.08 1.60 2 -4 0.43 0.645 - -6 0.30 0.45 - -8 ≤ n ≤ 40 1.84/n 2.76/n - -41.3. Research Motivation1.3 Research MotivationThe aforementioned standard limits of current harmonics and its effects on the elec-tric grid emphasize the necessity to maintain the power quality for electrical devices.Traditionally, the circuitry, which is responsible for this task, is called current shapingor power factor correction (PFC) circuit. In fact, PFC techniques have been applied fordecades, but the topic gets more attention due the increase demand of DC power bothin the number of applications and the power levels.Generally, power factor correction techniques can be classified into two main tech-niques, passive and active. Passive circuits use only capacitors, inductors, and diodesto shape the input current. They can provide acceptable performance over the nominalinput and load conditions, however they require large passive components (L and C)and are limited to low power applications. For example, the resonant input filter [1] andValley-fill [3] are two passive topologies.Active methods employ semiconductor devices to shape the input current by control-ling the switching instants. Switched mode converters are the perfect solution for powerfactor correction. In addition, the improvement in semiconductor switches and digitalcontrollers have enabled the design of high frequency converters which can achieve theconversion task with high efficiency. The main objectives of switched mode AC/DCconverters are :• Provide regulated DC output over input voltage and output load variations.• Insert isolation.• Draw acceptable input current (high PF and low THD).The research of this thesis investigates the design of a new AC/DC converter forLED light applications. Unlike the commonly used approach for AC/DC conversion, theconverter features single stage to achieve the aforementioned objectives. Moreover, it51.4. Thesis Outlineoperates at high efficiency with an input current in accordance with the internationalstandards.1.4 Thesis OutlineThe thesis consists of five chapters. Chapter 1 provides a general background aboutpower quality and the importance of AC/DC converters according to the internationalstandards.Chapter 2 reviews the existing AC/DC converters and compares between the two-stage and integrated approaches. A detailed description of boost PFC converter is pre-sented in different operation modes. The characteristic as well as the limitations of theexisting integrated topologies are presented.Chapter 3 states the advantages of the proposed converter over other topologies. Atheoretical analysis is provided which includes the operation modes, and the controltechnique.Chapter 4 provides detailed design steps of the experimental prototype which vali-dates the converter operation. Experimental waveforms at different operation conditionsare presented. In addition, the input current harmonics and PF are measured to ensurecompliance with the standards.Finally, chapter 5 contains the conclusion and suggests the possible research pointsfor future work.6Chapter 2Literature ReviewThis chapter discusses the use of switched mode topologies for PFC. Specifically, thethree common topologies (buck, boost and buck-boost) are analyzed as candidates forPFC circuitry at different operation modes of inductor current. A comparison betweentwo-stage and integrated approaches is made. Finally, a review of the existing integratedtopologies is presented, highlighting their advantages and limitations.2.1 Conventional PFC ApproachPFC IsolatedDC/DCiin vdc vovinPFCControlDC/DCControlFigure 2.1: Two stage PFC architectureAlthough there are two methods for PFC; active and passive, the review focuses onlyon active PFC due to the limitations of the passive method. Furthermore, the activemethod can provide regulated output over the line variations. Generally, the conventionalapproach of AC/DC converters consists of two main stages as shown in Figure 2.1. First,72.2. Analysis of Basic Topologies for PFC Applicationsthe input line voltage is rectified using bridge rectifier and one of the basic DC/DCconverters is utilized to shape the input current into a sinusoidal wave following theinput voltage for high power factor. Commonly, a boost converter is preferred for thefirst stage since the input inductor helps reduce current ripples.AC/DC converters suffer from a mismatch between the input instantaneous power,which contains a fluctuating component at double line frequency, and the output DCpower. As a result, double line frequency ripples appear across the filter capacitor at theoutput [4]. Therefore, an isolated DC/DC converter is mostly employed in the secondstage to perform two essential functions: provide tight regulation on the output DCvoltage, and galvanic isolation between the input and output sides.The design of PFC controller varies according to the operation mode of the inductorcurrent. Considering boost PFC , average current mode controller is usually employed,in which there are two control loops. The outer voltage loop is a low bandwidth loop toregulate the output voltage and avoid distortion in line current. A high bandwidth loop(1-10 kHz) is required to shape the inductor input current so that it follows a referencesignal proportional to the input voltage.2.2 Analysis of Basic Topologies for PFCApplicationsAccording to the inductor current in any basic switched-mode topology, the convertercan operate in either continuous conduction mode (CCM) or discontinuous conductionmode (DCM). Boost, buck-boost and buck converters, used as PFC, can operate in anyof the two modes to achieve input current shaping. CCM is typically for higher powerapplication (i.e. >200 W) due to the reduced current ripple. However, DCM is the choicefor low to medium power applications because of many advantages.82.2. Analysis of Basic Topologies for PFC Applications2.2.1 DCM Operation AnalysisDespite the high current ripples in DCM, it features many advantages such as simplic-ity of control design and low switching losses compared to CCM. In DCM, the inductorcurrent builds up from zero after each switching cycle, therefore the inductor current isnot a state variable and the converter model is simpler. The converters can be controlledwith single loop unlike CCM in which two loops are essential. In addition, the currentthrough the diode goes to zero before switchning off which eliminates the reverse recoverylosses.vinLvin−VoLvinLvin−VoLvin Vo0 DTs Ts 0 DTs 0 DTsBoost Buck-boost Buckvin Vo vin Voiin iin iin1 1 1 1slopeFigure 2.2: DCM operation of the basic switching converters.The idea of PFC under DCM is that the inductor current peak samples the input ACvoltage each switching cycle. This results in automatic current shaping. To accuratelyanalyze the validity of each topology for automatic current shaping, Figure 2.2 showsthe three main topologies with the input current waveforms at DCM. The input voltagevin can be considered as the rectified sine wave after the bridge, while the output voltageVo is constant. The average of input current triangular wave over switching period (Ts),equation (2.1), indicates the shape of the line current over the input line period.iinavg(t) =1Ts∫ Ts0iin(τ) dτ (2.1)92.2. Analysis of Basic Topologies for PFC ApplicationsApplying (2.1) to the waves depicted in Figure 2.2, equations (2.2)-(2.4) of averageinput current are derived for boost, buck-boost and buck converters receptively [5].iinavg(t) =D2Ts2Lvin(t)VoVo − vin(t) (2.2)iinavg(t) =D2Ts2Lvin(t) (2.3)iinavg(t) =D2Ts2Lvin(t)− D2Ts2LVo (2.4)The equations describe how the input current average is related to vin(t) and Vo.For a given steady state condition, the term (D2Ts2L) is constant. Clearly, buck-boostconverter input current is directly proportional to the input line voltage, equation (2.3),which achieves the best automatic current shaping out of the three converters. In boostconverter, the shape of input current depends not only on vin(t) but also the ratio betweenvin(t) and Vo. Figure 2.3 shows the shape of the current for the three topologies over aline period.1Buck-boostTBoostBucktimeiinavgFigure 2.3: Input current of switching converters comparison.102.2. Analysis of Basic Topologies for PFC ApplicationsAmong PFC topologies, boost and buck-boost are very popular due to their currentshaping capability as presented before. In general, boost converter is more efficient thanbuck-boost converter and predominant in industrial applications ranging from low tohigh power. Various controller IC are available to facilitate the design of boost PFC suchas UC3854 IC for CCM operation and UCC38050 for Critical conduction mode (CRM).Figure 2.4 depicts the differences between the three modes of operation.iLavg(a) CCM operation.iLpeakiLavg(b) CRM operation.iLpeakiLavg(c) DCM operation.Figure 2.4: Boost converter PFC modes of operation [6].2.2.2 Boost Converter Analysis under DCMBoost converter operating at DCM features low inductance and best stability overthe other two modes. Moreover, the power range can be easily extended by interleavingmultiple phases, which leads to ripple cancellation and input current shape very close toCCM operation with easier design.LCQDVoiLVinRFigure 2.5: Boost converter.112.2. Analysis of Basic Topologies for PFC ApplicationsFigure 2.5 shows boost converter with the paths of inductor current according to theswitching state. In CCM, the gain function between the input and output voltages is(Vo =VinD1−D ). DCM occurs when the inductor current ripple is high so that the currentreaches zero before the next switching cycle. K and Kcrit are defined in equations (2.5)and (2.6) to determine the mode boundary. If K is less than Kcrit, the converter entersDCM operation. In DCM, the gain is load dependent as in equation (2.7) [7].K =2LRTs(2.5)Kcrit = D(1−D)2 (2.6)VoVin=1 +√1 + 4D2/K2(2.7)The key waveforms of DCM operation are shown in Figure 2.6. Equation (2.7) isderived by applying volt-second balance to inductor voltage waveform.iLQvLTsDTsVinVin − VotON OFFFigure 2.6: DCM operation waveforms of boost converter.122.3. Isolated DC/DC Topologies2.3 Isolated DC/DC TopologiesThe second stage of the conventional AC/DC conversion approach is isolated DC/DCconverter as depicted before in Figure 2.1. In addition to galvanic isolation and tightlyregulated output, the second stage with the separate controller provides a fast dynamicresponse to the load changes.There are numerous DC/DC topologies that usually follow the current shaper inAC/DC conversion. Typically, they are classified according to different metrics such aspower level and control technique. For low power applications (i.e. <100 W), flybackconverter is very popular as it features low component count and cost, however thetransformer is not fully utilized (single quadrant B-H curve excitation) and auxiliarycircuit should be used to avoid high stresses on switches due to leakage inductance [8].For medium to low power applications, the topologies are classified to two main cat-egories: Pulse Width Modulation (PWM) and resonant converters. PWM convertersdepend on varying the duty cycle of the switching pattern to control the output. Forinstance, push-pull, forward, and full bridge converters are commonly used and well estab-lished in the literature. The predominant converter in this category is phase-shifted fullbridge converter shown in Figure 2.7. Utilizing the leakage inductance of the transformer,the converter achieves soft switching which reduces the losses. Also, the transformer isfully utilized leading to smaller core.On the other hand, resonant converters are controlled by varying the frequency of theswitching signal. The gain characteristics vary according to the resonant tank applied.Series and LLC resonant converters are two examples of widely-used converters. LLCconverter, shown in Figure 2.8, is very similar to series converter in which the transformermagnetizing inductance is purposely designed to gain additional features. Resonantconverters offer great advantages such as soft switching, excellent EMI performance andhigh frequency operation which leads to high power density.132.3. Isolated DC/DC TopologiesVdcABVABFigure 2.7: Phase shifted full-bridge converter.VdcABiLrVABFigure 2.8: LLC resonant converter.142.4. Review of Integrated AC/DC Converters2.4 Review of Integrated AC/DC ConvertersUnlike two-stage AC/DC converters depicted in Figure 2.1, integrated converters tryto utilize the same switching devices to achieve identical tasks. As stated earlier, inputcurrent shaping, isolation, and DC output tight regulation are the targeted requirementsas shown in Figure 2.9. Obviously, the potential advantages of such approach includeless number of components, single controller and higher reliability.PFC Isolationiin vovinControllerFigure 2.9: Integrated AC/DC converter.This section is dedicated to present the concept of integrated PFC or AC/DC con-verters. Also, a review of the existing topologies will be provided pointing to theirfeatures and limitations. A short description along with the schematic of each topologyis presented.2.4.1 Flyback PFC ConverterFlyback converter is the isolated version of buck-boost converter in which the prob-lem of reversed output polarity is solved. As depicted in Figure 2.10, the converterconsists of only two devices: MOSFET and output diode. The input rectified source isa representation of the AC line followed by a rectifier bridge.152.4. Review of Integrated AC/DC ConvertersMode 1Mode 2iinLmQDCn : 1VinFigure 2.10: Flyback PFC.When used as PFC converter in DCM, flyback exhibits the same automatic currentsharing capability as buck-boost converter. Equation 2.3 showed that the average of theinput current iin over switching period is directly proportional to the input voltage. Thisoffers high power factor after the input line filter.A simple representation of operation modes is shown in Figure 2.10. When the switchis ON, the magnetizing inductance (Lm) stores energy as the current starts from zero andincreases linearly. The output diode is reversed biased and the load is being suppliedby the output capacitor. After switching off the MOSFET, the stored energy in Lmis discharged through the secondary feeding the load and output capacitor until theinductor current becomes zero.The low component count and cost make flyback attractive for portable applicationssuch as smart phones’ adapters which require small size [9]. In addition, design improve-ments have been made to enable soft switching. Off-shelf controller ICs are variable forthis purpose such as L6565. However, there are some limitations. For instance, flybackconverter is intended to low power application (i.e. <100 W) due the discontinuous na-ture of the input current. Also, the transformer is not fully utilized. This limits the useof flyback to certain applications like low power LED lighting and adapters.162.4. Review of Integrated AC/DC Converters2.4.2 Bridgeless Half Bridge Integrated PFCMost of the single-stage PFC converters use boost current-shaping input and share theswitches with different types of isolated DC/DC converters. For instance, the integrationbetween boost-type PFC and half bridge DC/DC converters has been investigated in theliterature. Half bridge LLC resonant converter shares the same switches with boost-PFC cell is proposed in [10]. Similarly, the topology was modified to eliminate therectifier bridge in which totem pole PFC is used with series resonant converter insteadof the boost-PFC [11], with the LLC converter [12], and with asymmetrical pulse-widthmodulation half-bridge converter [13].LrLmLinCdcvin iinCriLrAMode 1Mode 2CoQ2Q1Figure 2.11: Totem-pole integrated PFC [12].Figure 2.11 shows the integrated converter in [12]. The principle of operation isconcisely illustrated as follow. The input inductor Lin operates at DCM allowing forconstant duty cycle at steady state. Considering the positive half cycle of vin, when Q1is ON, the inductor current iin starts from zero and increases linearly. Mode 2 startswhen Q2 is ON and Q1 is OFF, Lin discharge the stored energy to the bus capacitor Cdcuntil the current becomes zero.Simultaneously, the input of the resonant tank (point A to ground) is a square wave.The resonant current iLr , which is sinusoidal at the switching frequency, gets rectified172.4. Review of Integrated AC/DC Convertersby the diodes of the transformer and filtered by the output capacitor. The topologyfeatures low switching losses as the MOSFETs achieve zero voltage switching (ZVS) andthe output diodes have zero current switching OFF (ZCS).The control strategy proposed in [12] is to vary the switching frequency fs to changethe gain of the LLC tank, whereas the duty cycle D is the control variable to change thefundamental component of the square wave applied to the series resonant tank in [11].Recently, another bridgeless single stage topology is proposed which consists of fourswitches as shown in Figure 2.12. The inductor is operating at DCM and the switchingfrequency is changed as the control variable to the the LLC tank. Furthermore, therelation between the peak inductor current and the average over swtiching period isnonlinear which results in high current ripples [14].LriinC1viniLrLinLmC2Figure 2.12: Bridgeless integrated PFC [14].Despite the simplicity of the aforementioned topologies, they are inevitably limitedto low power applications (i.e. <200 W) due to high inductor current iin ripple in DCMoperation.182.4. Review of Integrated AC/DC Converters2.4.3 Full Bridge Integrated PFCOne of the earliest designs of single-stage AC/DC converters was presented in [15]and is shown in Figure 2.13. The converter can operate in different conduction modes.A full bridge is used, which is common for power ratings higher than 200 W.Liniin CdcQ1Q2Q3Q4vinrecFigure 2.13: Full bridge integrated PFC [15].The converter passes through different modes of operations. However, there are twomain modes, energy transfer and freewheeling modes. Energy transfer occurs whenevertwo diagonal switches are ON (Q1 and Q4 or Q2 and Q3). In this case, energy is transferedfrom the DC bus capacitor to the load and the input rectified voltage is applied tothe input inductor Lin. The converter enters the freewheeling modes when the bottomswitches are both OFF. A detailed analysis of the different modes is provided in [16].Although common full bridge is used, the gate signals are different from the standardfull bridge PWM which adds complexity to the design. Furthermore, the converter shouldoperate under CCM to achieve higher power factor which introduces the inductor currentas a state variable in modeling and control design.192.4. Review of Integrated AC/DC Converters2.4.4 Three Level Integrated PFCAnother class of integrated PFC is multilevel converters. Single-stage three level PFCconverters were proposed in [17] and [18].The approach allows the use of low-voltagerating MOSFETs which leads to lower conduction losses. The topology presented in[17] can operate in DCM or CCM and is controlled by a combination of phase shiftand variable frequency. However, it is best situated for higher power applications. Theconverter introduced in [18], shown in Figure 2.14, operates in DCM and suffers fromhigh input current ripples.LiniinvinrecQ1Q2Q3Q4C1C2D1D2Figure 2.14: Three level PFC [18].The converter proposed in [18] has a modified switching scheme compared to con-ventional three level DC/DC converter. When switches (Q2 and Q3) are ON, the inputvoltage is applied across the boost inductor Lin and the transformer current is freewheel-ing through one switch and one of the two diodes. When Lin is discharging, half of theDC bus voltage (Vdc/2) is applied across the transformer depending on the switchingstates. The middle two switches have zero current turn on, and the upper and bottomswitches have zero voltage turn on transition. However, the diodes (D1 and D2) are fastdiodes to reduce the reverse recovery losses.202.5. Conclusion2.5 ConclusionIn this chapter, the conventional method of AC/DC conversion was presented withdetails about each stage and the commonly used topologies. Then, the concept of inte-grated PFC converters was introduced which can be used as a means to higher efficiency,reliability, and simpler AC/DC conversion.A number of existing integrated topologies was investigated with a brief descriptionof operation principle, advantages, and limitations. Most of the proposed convertersoperate at DCM with a boost cell to enable the integration and sharing the switches withDC/DC stage. Both PWM and resonant isolated converters are employed in differenttopologies. DCM operation features low inductance value, and less order model, howeverthe inductor current contains high current ripples which increase the conduction losses.Reviewing the existing topologies shows the importance of designing a new converterwhich combines the simplicity of DCM operation with a low-ripple input current closeto CCM operation.21Chapter 3Analysis and Operation of ProposedIntegrated PFC Converter3.1 OverviewThis chapter presents the proposed converter and provides analysis of the operationprinciple. The chapter is organized as follows. Section 3.2 provides a schematic of theproposed topology and states the difference between it and the two-stage counterpart. Insection 3.3, a detailed explanation of operation modes is provided with the waveform foreach mode. Mathematical analysis for the operation is introduced in section 3.4. Finally,a control strategy for output regulation is presented in section 3.5.3.2 Proposed Integrated PFC TopologyThe derivation of the proposed converter starts with the conventional two-stage topol-ogy. As shown in Figure 3.1, the first stage is interleaved boost PFC converter. Eachstage carries half of the total power in lieu of single boost cell. The main advantageof interleaving is to significantly reduce the current ripple especially in DCM and CRMoperation. The second stage is full bridge LLC resonant DC/DC converter. Full bridgeis commonly used for power ratings starting from several hundred of Watts. There isa separate controller for each stage. Typically, LLC converter uses variable frequencycontroller and PWM controller is used for boost PFC.223.2. Proposed Integrated PFC TopologyLrVdcInterleaved Boost Full bridge LLCL1L2LmCrn1 : n2Figure 3.1: Conventional two-stage converter.From the topology aspect and by observing the conventional approach in Figure 3.1,it is obvious that the full bridge can be shared between the LLC resonant tank and theinterleaved boost cell. This leads to the proposed converter shown in Figure 3.2.VinABVdcQ2Q1Q3 Q4L1L2itD1 LriinD2LmCrn1 : n2Figure 3.2: Proposed integrated converter.233.3. Operation ModesIn the two-stage approach, boost converter can operate in one of three modes: DCM,CRM, or CCM since it is separate form the DC/DC stage. However, after the integration,the effect of each operating mode on the resonant tank behavior must be considered inorder to determine the valid mode out of the three. If boost converter is to operate atCCM, duty cycle has to change periodically at double line frequency, equation 3.1, tomaintain continuous inductor current [19].D(t) = 1− Vmax|sin(ωt)|Vdc(3.1)where Vmax is the maximum of the input AC voltage and Vdc is the DC bus voltage.Such variation drastically affects the input of the resonant tank, thus tight voltageregulation at the output can not be achieved. In CRM operation, both duty cycle andswitching frequency vary with the input voltage. In contrast to CCM and CRM modes,DCM seems to be a valid mode for the integrated topology as the duty cycle and frequencyis constant for a given steady state condition.Although some researchers have proposed variable-duty-cycle control for DCM toimprove PF [20], boost converter can achieve high PF at constant duty cycle as presentedearlier in section 2.2.1. In DCM, the inductor current is prevented from being negativeby the diode, hence diodes D1 and D2 are in the proposed topology to block any negativecurrent through L1 and L2.3.3 Operation ModesA detailed analysis of the operation modes is investigated in this section. The op-eration consists of five modes for which an equivalent circuit and description will beprovided. Figure 3.3 shows the key waveforms and the transition instants between eachmode. The input voltage is assumed to be constant since the switching frequency (fs) ismuch higher than the line AC frequency.243.3. Operation ModesZVS Q 1Q 2TStimeiLmiQ1ZCStiLriLiLitVABiQ3iDtottttVDCFigure 3.3: Operation modes waveforms.253.3. Operation Modes3.3.1 Mode 1: (to → t1)The operation can be explained starting from the switching instant of Q1. As Shownin Figure 3.4.ABQ2Q1Q3 Q4L1L2itD1 LrD2LmCrn1 : n2vinreciQ1iQ3iLriDiL1iL2D3D4VdcVoCdcFigure 3.4: Mode 1: (to → t1).In Mode 1: (to → t1), when Q1 is ON, given that the PFC inductors operate inDCM, current through inductor L1 (iL1) builds up from zero and increases linearly witha slope dictated by the instantaneous value of AC input vin(t). The current reaches themaximum value when Q1 is switched off.Due to the interleaving of boost cells to achieve ripple cancellation, Q1 and Q2 are180 o phase shifted. Assuming the duty cycle is 0.5, Q2 is OFF when Q1 is ON. Currentthrough inductor L2 (iL2) is decreasing linearly through Q4 to the DC bus capacitor Cdcwith a slope dictated by the instantaneous value of AC input vin(t) and the DC busvoltage. The input current it is the sum of indutors’ currents with reduced ripples.The conduction of Q1 and Q4 applies a negative voltage equal to Vdc across theLLC resonant tank VAB. D4 is conducting which imposes a negative voltage across themagnetizing inductance Lm equal to Vo ∗ (n1/n2). Lr and Cr resonate at the resonantfrequency (fo = 1/2pi√LrCr) as Lm is dynamically shorted by the reflected voltage. Theresonant current iLr minus the magnetizing current iLm gets reflected to the secondaryside through D4. This mode ends when iL2 reaches zero.263.3. Operation Modes3.3.2 Mode 2: (t1 → t2)ABQ2Q1Q3 Q4L1L2itD1 LrD2LmCrn1 : n2vinreciQ1iQ3iLriDiL1iL2D3D4VdcVoCdcFigure 3.5: Mode 2: (t1 → t2).Mode 2: (t1 → t2), shown in Figure 3.5, starts when iL2 is zero where the inputdiode D2 is blocking any negative current through L2. Inductor current iL1 continuesto increase linearly as Q1 is ON. Switch Q4 is still ON to allow the flowing of resonantcurrent iLr .The resonant tank with the secondary side behaves similarly to Mode 1. The magne-tizing current iLm approaches iLr and is equal to it at the end of this mode. The outputdiodes current iD completes the cycle and becomes zero, when iLr and iLm are equal,allowing zero current switching (ZCS) for D4. The average value of iD is delivered to theoutput load after being filtered by the output capacitor.At the end of Mode 2, Q1 and Q4 are switched off. Inductor current iL1 has reachedthe maximum and iLr is negative as shown in Figure 3.3.273.3. Operation Modes3.3.3 Mode 3: (t2 → t3)ABQ2Q1Q3 Q4L1L2itD1 LrD2LmCrn1 : n2vinreciQ1iQ3iLriDiL1iL2D3D4VdcVoCdcFigure 3.6: Mode 3: (t2 → t3).Mode 3 represents the inserted dead time in the switching transition from low-side tohigh-side switches or vice versa. Dead time enables soft switching transition by chargingand discharging the parasitic capacitances across the MOSFETs (Cds) before applyingthe gate signals.The negative current iLr discharges the capacitors across Q2 and Q3 and charges theones across Q1 and Q4 as shown in Figure 3.6. At the end of the dead time, capacitorsacross Q1 and Q4 are charged to the DC bus voltage Vdc while the voltage across Q2 andQ3 is zero, then the anti-parallel diodes conduct to achieve zero voltage switching ZVS.If the transition is from low to high side switch, the associated input inductor currenthelps with the discharging process.The resonant current is almost constant during this mode, and the load on the sec-ondary side is being supplied by the output capacitor. Mode 3 ends when the gate signalis applied to Q2 and Q3.283.3. Operation Modes3.3.4 Mode 4: (t3 → t4) and Mode 5: (t4 → t5)ABQ2Q1Q3 Q4L1L2itD1 LrD2LmCrn1 : n2vinreciQ1iQ3iLriDiL1iL2D3D4VdcVoCdcFigure 3.7: Mode 4: (t3 → t4).After the soft switching transitions, Mode 4 starts by applying gate signals to Q2 andQ3. Regarding the input inductors, a similar operation to Mode 1 is applied to the otherinductor L2. The current iL1 builds up linearly through Q2 while iL1 is decreasing todischarge L1 through Q3. Ripple cancellation is achieved to the input current it.Positive voltage is applied across the resonant tank VAB due to the conduction of Q2and Q3 as shown in Figure 3.7. D3 is conducting which imposes negative voltage acrossLm. Lr and Cr resonate at the resonant frequency fo. This mode ends when iL1 reacheszero.ABQ2Q1Q3 Q4L1L2itD1 LrD2LmCrn1 : n2vinreciQ1iQ3iLriDiL1iL2D3D4VdcVoCdcFigure 3.8: Mode 5: (t4 → t5).293.3. Operation ModesMode 5: (t4 → t5), shown in Figure 3.8, starts when iL1 is zero where the inputdiode D1 is blocking any negative current through L1. Inductor current iL2 continues toincrease linearly. Switch Q3 is still ON to allow the flowing of resonant current iLr .At the end of Mode 5, Q2 and Q3 are switched off. Inductor current iL2 has reachedthe maximum and iLr is positive. Before returning back to Mode 1, dead time is insertedto enable zero voltage transitions from (Q2 and Q3) to (Q1 and Q4). The analysis istypical to the dead time in Mode 3.3.3.5 SummaryThe aforementioned analysis assumed that the switching frequency (fs) is close to theresonant frequency (fo = 1/2pi√LrCr) and the duty cycle is 0.5 for full load operation.The modes will be slightly different if the converter is to operate at different frequencyand duty cycle, but the presented analysis is intended to give a general idea about theoperation principle.The operation can be summarized as follow: Switches (Q1, Q3) and (Q2, Q4) areswitched in a complementary manner, whereas the Q1 and Q2 gate signals are out ofphase so that ripple cancellation is achieved for the input current iL. The interleavedboost cells determine the DC bus voltage across Cdc. In addition, the switching actionapplies a square wave between point A and B as an input to the resonant LLC tank,which operates as a conventional LLC DC/DC converter.In the next section, a performance analysis is provided to quantify the input currentshaping and output voltage regulation of the converter.303.4. Performance Analysis3.4 Performance Analysis3.4.1 Boost Cell AnalysisThe boost cell of the converter, which is the input inductors (L1 and L2), is responsiblefor maintaining high PF for the AC side. To determine the effect of boost cell on theinput current and the amount of harmonics, the input current equation is studied indetails.Equation (2.2) of boost converter can be rearranged and written as follow:iin(t) = Kα sin(ωt)1− α sin(ωt) (3.2)whereα =VmaxVdc, (3.3)andK =D2TsVdc2L(3.4)0 45 90 135 18000.20.40.60.81α = 0.3α = 0.8Sine waveαNormalized Input CurrentAngleoFigure 3.9: Normalized input current.313.4. Performance AnalysisConsidering a single boost cell, equation (3.2) indicates that the input current isdependent on the ratio between input AC voltage maximum and DC bus voltage. α canvary between zero and one (0 < α < 1), as the output voltage must be higher than theinput voltage in boost converter.The input current is normalized to K, and drawn at different values of input outputvoltage ratios (α). As can be seen in Figure 3.9, the input current gets closer to sinewave for small values of α. In other words, the higher the DC bus voltage, the betterthe current shaping is.This can be interpreted by observing the inductor current over a switching period.The inductor current can be decomposed into two triangles which give the average inputcurrent after integration. The first triangle depends only on the input voltage, henceits area is proportional to sine wave. Whereas, the second triangle depends not onlyon input voltage, but also on the DC bus voltage. As the DC bus voltage gets higher(small α values), the time allocated to the second triangle gets smaller (discharging ofthe inductor current) leading to average current closer to sine wave.As stated earlier, Power Factor is critical in determining the quality of the inputcurrent. PF expression for boost PFC operated under DCM is derived next. First,equations (3.5)-(3.7) express the active power (P ) supplied by the AC source.P =1pi∫ pi0vin(t)iin(t) dωt (3.5)=1pi∫ pi0(Vmax sin(ωt))∗(Kα sin(ωt)1− α sin(ωt))dωt (3.6)=KVmaxpi∫ pi0α sin2(ωt)1− α sin(ωt) dωt (3.7)323.4. Performance AnalysisApparent power (S) is derived in equations (3.8)-(3.10).S = Vrms ∗ Irms (3.8)=Vmax√2∗√1pi∫ pi0K2(α sin(ωt)1− α sin(ωt))2dωt︸ ︷︷ ︸Irms(3.9)=KVmax√2∗√1pi∫ pi0(α sin(ωt)1− α sin(ωt))2dωt (3.10)Finally, PF can be obtained by dividing (3.7) by (3.10). The final expression is given inequation (3.11). A detailed solution to the integrations in (3.11) is provided in [21]. PFis plotted as a function of α in Figure 3.10.PF =√2pi∗∫ pi0sin2(ωt)1− α sin(ωt) dωt√∫ pi0(sin2(ωt)1− α sin(ωt))2dωt(3.11)0.60.650.70.750.80.850.90.9510 0.2 0.4 0.6 0.8 1αPower FactorFigure 3.10: PF in DCM boost333.4. Performance AnalysisAs can be seen in Figure 3.10, DCM can achieve high PF for a wide range of inputoutput voltage ratios (α). For example, to maintain a PF higher than 0.95 (PF > 0.95),α must be smaller than 0.8, which means that (Vdc > 1.25Vmax). Although smaller α ispreferred, the limit of Vdc is set by the switching devices stress and other componentsratings especially for 220 V supply.The last point to be discussed is the benefit of interleaving. By shifting the switchingsignals of each phase, interleaving results in lower current ripples. According to thenumber of phases (N), the phase shift is (360o/N) which is (180o) in the proposedconverter. The ratio between the net and single inductor current ripples varies with D.R(D), equation (3.12), is the function to express the change for CCM mode, but it alsoindicates that the minimum ripples for DCM is at 0.5 cuty cycle [22], see Figure 3.11.R(D) =1− 2D1−D , D ≤ 0.52D − 1D, D > 0.5(3.12)00.20.40.60.810 0.2 0.4 0.6 0.8 1R(D)Duty Cycle (D)Figure 3.11: Effect of D on current ripples.343.4. Performance Analysis3.4.2 Resonant Tank AnalysisResonant tanks have been widely used in power conversion for decades. They canbe employed in either half or full bridge configurations. They are typically categorizedaccording to the type of the connection with the load (series-parallel) or the number ofpassive elements. LLC converter was first introduced in [23]. Since then, it has beenthe preferable choice for DC/DC conversion due to many advantages. In this section,properties of LLC tank will be discussed.In order to find the gain function between the input and output voltage of the resonanttank, fundamental harmonic approximation (FHA) is used [24]. The equivalent circuitof LLC tank is shown in Figure 3.12. The input voltage VAB1 represents the fundamentalcomponent of the applied square wave voltage, and Rac is equivalent to the loading inthe secondary side of the transformer after being referred to the primary.The objective is to find the ratio of the output Vo to the input voltage VAB1 byperforming simple AC circuit analysis. The input voltage VAB1 is obtained by applyingfourier series to the square wave input, and the equivalent resistance Rac is defined byequation (3.13), where n is the transformer turns ratio and RL is the load resistance.Rac =8n2RLpi2(3.13)LrLmCrVoRacVAB1Figure 3.12: LLC equivalent circuit.353.4. Performance AnalysisThe gain (M) is given from the equivalent circuit by equations (3.14) and (3.15) [25]:M(ωn, Q, k) =VoVAB1(3.14)=1√(1 +1k− 1kω2n)2+Q2(ωn − 1ωn)2 (3.15)where ωn is the normalized switching frequency to the resonant frequencyωn =ωsωo, (3.16)Q is the quality factorQ =ωoLrpi28n2RL, (3.17)and k is the ratio between resonant and magnetizing inductances (k = Lm/Lr). The gainrelation is plotted for different loading conditions (Q) and constant k in Figure 3.13.0 0.5 1 1.5 20123Q=0.2Q=0.3Q=0.4Q=0.8Q=1.2Q=3Q=10Gain (M) ZVS Region ωnFigure 3.13: Effect of Q on LLC gain.363.4. Performance AnalysisFigure 3.13 shows clearly that the gain characteristics are load dependent, however theunity gain point at resonant frequency (ωo = 1/√LrCr), where the curves are tangent,is independent of the loading condition. For each gain curve, the resonant tank inputimpedance is inductive at any frequency higher than the peak frequency as shown bythe dashed area. The inductive behavior is necessary to achieve ZVS as the tank currentis lagging the voltage VAB. The output regulation is achieved by varying the frequencyabove the resonant frequency (ωo) for stepping down, or below ωo for stepping up. Inaddition, the gain characteristics is affected by the ratio (k). Specifically, the boostingcapability of the tank changes by varying the ratio between Lm and Lr. In Figure 3.14,the gain is plotted for different values of k assuming constant Q (loading point).As depicted in Figure 3.14, the gain curve becomes steeper below resonant frequency(ωo) as the magnetizing inductance (Lm) becomes smaller (small k). Hence, the ratiok is an important factor in designing the resonant tank inductances Lm and Lr. Afterspecifying the input voltage range of the LLC converter, ratio k is determined to extendthe boost capability and achieve the required regulation at the output. Although smallerLm can provide wide input regulation over limited switching frequency variations, it leadsto more circulating current in the resonant tank which increases the conduction losses.0 0.5 1 1.501234k=2k=3k=4k=6ωnGain (M)Figure 3.14: Effect of k on LLC gain.373.5. Control Technique3.5 Control TechniqueIn this section, the viable control methods of regulating the output voltage are re-viewed. Then, the effect of the controlling variables on the converter operation is ana-lyzed. Finally, a proposed control technique is presented.The basic idea of regulating the output voltage is to either control the input voltageof the resonant tank or change its gain. However, given the integrated nature of theconverter, varying the controlling variables (fs and D) has a combined effect on theboost cell and the resonant tank as they share the same switches. In [12], variablefrequency (fs) control scheme is utilized to regulated the output by changing the tankgain, while variable duty cycle (D) is used to control the fundamental input voltage tothe tank in [11].3.5.1 Effect of Duty Cycle (D)First, the effect of D variations on the proposed converter is analyzed. For the boostinterleaved cell, duty cycle changes the DC bus voltage as depicted by the gain equation(2.7) of DCM boost. Furthermore, the input of the resonant tank will be a quasi squarewave with a reduced fundamental component as shown in Figure 3.15. Thus, the outputvoltage will be regulated due to the change in both DC bus voltage and fundamentalinput. Applying fourier series to the quasi square wave, equations (3.18) and (3.19) showthe relation between fundamental component (VAB1) and DC bus voltage (Vdc).VAB1 =√2pi∫ pi0VAB(t) sin(ωst) dωst (3.18)=2√2Vdcpisin(piD) (3.19)383.5. Control TechniqueVABVdcDTsTs2t√2VAB1Figure 3.15: Tank voltage VAB at D < 0.5.The operation of the LLC tank is slightly different from the regular operation at 0.5duty cycle. Figure 3.16 shows the waveforms at D < 0.5 in which the high side switchesON time overlaps applying zero voltage across the tank. Large step voltage appears onLr and leads to rapid decrease in iLr which will be equal to iLm. During this operation,ZVS is still achieve for MOSFETs, but the secondary side diodes are hard-switched asshow in Figure 3.16.iLmiLrVABtttiDQ 1Q 3Q 4Q 3Q 2Q 4Q 4Q 3TS/DTS0ILr(0)Figure 3.16: Operation waveforms at D < 0.5.393.5. Control TechniqueIn order to find the effect of D on the gain of the resonant tank, a similar analysisto the one proposed in [26] is used. FHA is not accurate to calculate the gain undervariable D since the resonant current is distorted and not close to the sinusoidal shape.Based on LC circuit analysis, iLr can be expressed during the interval DTs by (3.20):iLr(t) =VLr(0)Zrsin(ωot) + ILr(0) cos(ωot) (3.20)where Zr =√Lr/Cr, and ILr(0) can be calculated by applying voltage current relationto Lm as in (3.21). VLr(0) is equal to DC bus voltage minus Lm and Cr voltages.ILr(0) = − nVoD2fsLm(3.21)The average output current (Io) is the integration of the reflected current from theprimary over half switching period. The integration can be simplified to (3.22) since theaverage of iLm is zero.Io =2nTs∫ DTs0iLr(t) dt =VoRL(3.22)Solving (3.22), the gain function between Vdc and the primary voltage is given by (3.23):G(D) =F1(D)F2(D)(3.23)where F1(D) and F2(D) expressions are as follow:F1(D) =nωspiZrωo[1− cos (2piDωoωs)](3.24)F2(D) =1nRL+nDLmωosin(2piDωoωs)+ωs(F (D)− n)piZrωo[cos(2piDωoωs)− 1] (3.25)F (D) =2pi4Crωs[2npiLmωsD(0.5−D) + 1nRL](3.26)403.5. Control TechniqueThe gain relation is plotted for different loading conditions (Q) at the resonant fre-quency under variable duty cycle operation in Figure 3.17.0.2 0.3 0.4 0.50.60.70.80.91Q=0.2Q=0.1Q=0.15Gain (G)DFigure 3.17: Effect of D on LLC gain.As shown in Figure 3.17, D variations can be utilized to significantly reduce the gainof the resonant tank instead of increasing the switching frequency.3.5.2 Effect of Switching frequency (fs)The gain characteristics of the LLC resonant tank as a function of fs have beendiscussed in section 3.4.2. Although the interleaved boost cells are integrated, the effectof fs variations on DC bus voltage are negligible compared to D variations’ effect sincethe boost converter is typically pulse width modulated.413.6. Summary3.5.3 Proposed Control TechniqueThe proposed control technique combines both duty cycle and frequency methods toutilize their advantages. The controller should be able to regulate the output voltageunder over loading and input AC voltage conditions. Besides, the optimum efficiency isachieved at the resonant frequency where the tank gain is one [27].Therefore, the converter is designed to operate at resonant frequency for full loadcondition such that the circulating current in the resonant tank is minimum and highefficiency can be achieved. The frequency is decrease below fo only if the input AC voltageis less than the nominal value to provide step up gain. Other than that, variable dutycycle method is employed to regulate the output voltage in cases of high input voltageor partial load conditions. The advantage of using D control instead of increasing fs isthat Vdc can be kept from reaching high values especially when Vin is higher than thenominal (120V).3.6 SummaryIn this chapter, a comprehensive description and theoretical analysis of the proposedtopology were presented. The operation modes were mentioned in details providingequivalent circuit for each mode. The performance of the converter was analyzed tounderstand different factors that affect input current shape and output voltage regulation.Finally, a control technique was proposed.Based on the theoretical analysis in this chapter, the next chapter starts with thedesign procedure of different components and devices. Then, an experimental prototypewill be designed and tested to verify the operation of the converter.42Chapter 4Experimental Results4.1 OverviewIn this chapter, the design of the experimental prototype is presented in details. First,the design of boost cell components is analyzed, which deals with the selection of inputinductors (L1 and L2) in order to maintain high power factor at the AC input side.Second, the resonant tank components are designed given the switching frequency andthe output regulation requirements. Also, practical design considerations are mentioned.Finally, the experimental results at different loading and input conditions are presented,which match the theoretical analysis in chapter 3.4.2 Design RequirementsTable 4.1: Design requirementsParameter ValueInput AC Range 100 : 140VOutput Voltage Vo 48VOutput Power Po 350WPower Factor > 0.95The component selection depends mainly on the power rating and input AC voltagerange of the converter. The experimental prototype is intended to be used with the NorthAmerican input AC voltage, 120V RMS, for high power LED lighting applications. Thefull load output power (Po) is 350W, and the output voltage (Vo) should be regulated434.3. Boost Cell Designat 48V over variations of input AC voltage and load conditions. Furthermore, the inputAC current should be in compliance with IEC 61000-3-2 Standards, Class C for light-ing equipments. The general design requirements, which initiate the design steps, aresummarized in Table 4.1.4.3 Boost Cell DesignDue to the popularity of boost PFC converter, its design has been discussed exten-sively in literature [28]. This section discusses the design of the passive componentsassociated with the interleaved-boost cells. Specifically, the design equations of L1, L2,and Cdc are derived based on the prototype requirements.4.3.1 Input Inductors (L1 and L2) Designvin(pi/2)Lvin(pi/2)−VdcLDTs D′TsFigure 4.1: Inductor current over Ts at vin(pi/2).The boost inductor design is one of the challenging steps in PFC design. It variesdepending on the operation mode: CCM, CRM, or DCM. In DCM, the inductance issmall to allow high ripple current. The proposed converter uses constant duty cycle toshape the input current. Therefore, the duty cycle at full load should be determinedprior to inductor design.444.3. Boost Cell DesignFor DCM, D′, expressed in (4.1), is defined as the duty cycle required for the inductorcurrent to discharge to zero. To ensure discontinuous current, inequality (4.2) must besatisfied over the line period of the input voltage. Figure 4.1 shows a switching cycle ofthe inductor current at the peak of vin. At this case, the inductor current is maximumand the discharging slope is minimum as shown in Figure 4.1. Thus, the limitation onD to operate in DCM is given by (4.3) using (4.1) and (4.2) at the peak of vin (Vmax).D′(t) =vin(t)Vdc − vin(t)D (4.1)D +D′(t) ≤ 1 (4.2)D ≤ 1− VmaxVdc(4.3)≤ 1− αDuty cycle depends on the ratio α which determines the shape of input current iinand PF accordingly. As discussed in section 3.4, to get PF higher than 0.95, α shouldbe smaller than 0.8 and the PF curve gets saturated and close to one when α < 0.4.However, the voltage stress of the components is the limiting factor for further decreaseof α. Considering these points, α is chosen to be approximately 0.44, as a result, theduty cycle at full load should be smaller than 0.55 by applying (4.3) and is set at 0.5 toachieve maximum ripple cancellation for the interleaving cells.After determining D at full load, the inductor is typically designed such that thecharging and discharging time is exactly equal to Ts at the peak of vin. Therefore, theaverage of the inductor current (L1 or L2) is equal to half of the input current iin peak asevery cell is processing half the input power. Equation (4.4) equates half the maximumof iin to the average over switching period Ts calculated from Figure 4.1.√2Iin2=√2VinD2fsL(4.4)454.3. Boost Cell Designwhere Vin and Iin are the RMS values of the input voltage and current.Rearranging (4.4) and expressing Iin in terms of input power, the equation of inductordesign can be written as (4.5). The analysis assumes the boost cells are lossless whichimplies that Po is equal to Pin. However, for the practical design, input inductors shouldbe less than the value obtained from (4.5) to account for any power losses in the rectifierbridge and the boost cell.L1,2 =V 2inDfsPo(4.5)4.3.2 DC Bus Capacitor (Cdc) DesignThe DC bus capacitor Cdc acts as energy buffer for the low line frequency ripplesdue to the mismatch between the input AC and output DC power. The design of Cdcdepends on three main factors; the amount of peak to peak ripple on DC bus voltage(∆vdc) specified, the RMS ripple current rating of the capacitor, and the hold timerequirements in some applications. Generally, equation (4.6) is used to determine theminimum requirements for Cdc.Cdc =2pifline∆vdcVdcPo(4.6)In the proposed converter, the full load operation is at the resonant frequency (fo) andthe tank gain is one. Therefore, the permissible output voltage ripples (∆vo) determine∆vdc, since the ripples are attenuated only by the transformer turns ratio.464.4. Resonant Tank Design4.4 Resonant Tank DesignThis section discusses the design of the LLC tank components: Lm, Lr, and Cr. Also,the transformer turns ratio is designed to get the required voltage level at Vo.4.4.1 Magnetizing Inductance (Lm) DesignThe design of Lm is related to the reflected voltage from the secondary side of thetransformer since it determines how the magnetizing current swings from Max to Minvalues. Therefore, the turns ratio should be calculated first according to the DC busvoltage Vdc and the output voltage Vo. The resonant tank has unity gain at fo, so theoutput voltage is stepped down by the turns ratio of the transformer (n). Hence, n canbe obtained from (4.7) considering the voltage drop across the fast diode (Vd) at theoutput.n =VdcVo + Vd(4.7)By determining n, the voltage across Lm, when any of the output diodes is on, isnVo. This voltage represents the slope at which iLm increases or decreases. Accordingly,the current of the resonant tank at the switching instant can be determined. Figure 4.2shows a simplified equivalent circuit of the resonant tank at the switching transition fromQ3 to Q1.It is required to design Lm so that the switching current during the transition fromlow to high switches or vice versa, is enough to discharge and charge the stray capacitance(CDS) and achieve ZVS. The design should be performed assuming the input inductorscurrents are zero in order to guarantee ZVS over the entire input line period.As sown in Figure 4.2, CDS3 should charge from zero to Vdc in the available deadtime (td). Applying the voltage current relation of the capacitor, the required constantmagnetizing current can be obtained by (4.8).474.4. Resonant Tank DesignABCDS1CDS3 CDS4LrLmCrn : 1 D3D4VdcVoCDS2ILm/2ILm/2tdVdcFigure 4.2: LLC equivalent circuit during deadtime td.ILm =2VdcCDStd(4.8)where ILm is the current of Lm at the switching instant, and CDS is the effective capaci-tance related to the charging time given in the switch datasheet.The magnetizing current iLm swings from −ILm to ILm during half of the switchingperiod at 0.5 duty cycle operation. The required Lm to achieve ZVS can be calculatedfrom (4.9).Lm =nVotd8fsVdcCDS(4.9)Due to the proposed control technique, duty cycle can vary less than 0.5. As result,the available time for iLm to swing is less than half the switching cycle. To achieve ZVSdespite the change of D, Lm should be less than the value from (4.9) according to theminimum D as in (4.10).Lm =nVotdDmin4fsVdcCDS(4.10)484.5. Practical Design Consideration4.4.2 Resonant Components (Lr and Cr) DesignThe design of Lr depends on the boosting gain to be provided by the tank duringlow input AC voltage conditions. The maximum gain is a function of the ratio k asdiscussed earlier. Once Lm is determined, Lr can be obtained by (4.11). Then, based onthe specified resonant frequency, (4.12) is used to get Cr.k =LmLr(4.11)Cr =1(2pifo)2Lr(4.12)4.5 Practical Design ConsiderationOne important design aspect should be considered to avoid undesirable voltage spikesand oscillations across the input diodes (D1 and D2) of the boost cells. Considering onecell at the input, the same applies to the other cell, after the current of L1 (iL1) is zero(Mode 5), the equivalent circuit during the discontinuous time is shown in Figure 4.3.The junction capacitance of the input diode D1 along with L1 form a resonant circuitwhich might impose voltage oscillations exceeding the diode stress depending on thevalue of vin as shown in Figure 4.3. One possible solution is to add two clamping orauxiliary diodes as shown in Figure 4.4.VdcVinQ3Q1CJ L1CDSVdc-VinCJ L12(Vdc-Vin)Figure 4.3: Equivalent circuit of boost cell during discontinuous time.494.6. Experimental PrototypeABVdcQ2Q1Q3 Q4L1L2D1vinrecAuxDiodesD2Figure 4.4: Proposed solution for input diode voltage spikes.It should be noted that the added diodes are low-rated devices and they are notcontributing to the power processing. Simply, they are switching-aid diodes activateonly during the discontinuous period to clamp the oscillation across D1 and D2.4.6 Experimental PrototypeAll the components were designed according to the aforementioned analysis to achievethe specified requirements of the input PF and output voltage regulation. The resonantfrequency is selected to be 140 kHz. Table 4.2 summarizes the converter componentsand their values based on the design equations. Also, the part number of each capacitorand the cores used for the magnetic design are mentioned.Table 4.2: Passive componentsComponent Value Part numberInput inductors (L1, L2) 110µH RM10 CoreResonant inductor (Lr) 70µH RM8 CoreResonant cap (Cr) 16.4nF EPCOS B32672L8822JDc bus cap (Cdc) 400µF EPCOS B43601B5477MOutput cap (Co) 9.9µF EPCOS B32562J1335KMag inductor (Lm) 350µH –Turns ratio (n1 : n2) 8 : 1 RM12 Core504.6. Experimental PrototypeTable 4.3: Semiconductor devicesComponent Part numberMOSFET (Q1–Q4) Fairchild FCP104N60FGate drivers ADuM3223Input Diodes (D1, D2) NXP BYV25D-600Output Diodes (D3, D4) ST STPS41H100CRectifier Bridge GBJ1504-FSimulation analysis has been conducted using PSIM software to ensure the operationand select the semiconductor devices to be used in the experimental prototype. Table 4.3lists the semiconductor devices and the part numbers used in the prototype. It shouldbe noted that the input diodes (D1 and D2) are DCM diodes as they switch off at zerocurrent, so schottky diodes are not needed. This helps reduce the conduction losses sinceDCM diodes have less forward voltage drop compared to super fast or schottky diodes.The prototype consists of two parts. The power circuit is shown in Figure 4.6 withall the components labeled similar to the topology schematic. The gate drivers moduleis shown in Figure 4.5, which contains the gate driver ICs with auxiliary power supplies.105 mm50 mm50 mmFigure 4.5: Gate drivers auxiliary board.514.6. Experimental PrototypeCoCdcL1L2CrLrBridgeInputConnectorsInputDiodesMOSFETsOutput DiodesPWMInputOutputConnectorsFigure 4.6: Photo of the experimental prototype.524.7. Experimental Waveforms4.7 Experimental WaveformsThe experimental prototype was tested to verify the operation and effectiveness of theproposed topology. This section is dedicated to present measurements at different loadingand input conditions. It is organized as follows. First, the measurement waveforms atfull load and partial load (50%) conditions are provided. Second, results at low and highinput AC voltage cases are presented.For each operating condition, the input low-frequency waveforms are shown to verifythe current shaping and the high PF. Then, the high frequency waveforms related to theresonant tank, switches, and the secondary side of the transformer are shown to ensurethe output regulation and the soft switching transitions.4.7.1 Full Load OperationAt full load, the converter operates at the resonant frequency and half duty cycle toachieve high efficiency. The experiment was conducted at 120 V input and 350 W outputpower.Input AC WaveformsThe key waveforms of the AC input are shown in the next figures. Figure 4.7 shows theeffect of interleaving, where it is noted that the high frequency ripple in it is significantlyreduced in comparison to iL1. This enables higher power ratings for the proposed topologycompared to the existing ones. Also, the AC current iin , after the line filter, is shownalong with AC voltage in Figure 4.8. As can be seen, the topology features high inputPF with low THD. A detailed analysis of the input current spectrum is provided in asubsequent section. Figure 4.9 shows the output voltage (Vo) along with the input ACvoltage which indicates very small low frequency ripples at the output.534.7. Experimental Waveforms90V / div 3A / div 5 mSec/ div3A / divvinitiLFigure 4.7: Measured waveforms of the rectified voltage vin, current it, and inductorcurrent iL1. (Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz)100V / div 3.5A / div 5 mSec/ div3.5A / divitviniinFigure 4.8: Measured waveforms of the AC voltage vin, current iin, and it. (Vin = 120V ,Vo = 48V , Po = 350W , fs = 135kHz)544.7. Experimental Waveforms90V / div 5 mSec/ div15V / divvinVoFigure 4.9: Measured waveforms of the output voltage Vo. (Vin = 120V , Vo = 48V ,Po = 350W , fs = 135kHz)Resonant Tank WaveformsThe main LLC tank waveforms are presented. Figure 4.10 shows the square waveinput VAB with no spikes due to the soft switching ZVS. The operation is at resonantfrequency fo, therefore iLr is pure sine wave and the LLC tank gain is one. Operationat resonant frequency is optimum from the efficiency perspective and is targeted for fullload operation of the proposed topology. Also, resonant capacitor voltage vCr is shownand leading iLr by 90o.The output diodes current iD is shown in Figure 4.11. Due to the resonant frequencyoperation, the current wave occupies the whole period (Ts/2), and ZCS is achieved. Thecurrent ripples frequency is twice the switching frequency and it gets filtered by theoutput capacitor. Figure 4.12 shows the output voltage with minimal high frequencyripples after filtering iD.554.7. Experimental Waveforms300V / div 2A / div 2 µSec/ div200V / divvCrVABiLrNo spikesFigure 4.10: Measured waveforms of the tank voltage VAB, current iLr, and resonant capvoltage vCr. (Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz)300V / div 2 µSec/ div8A / diviDVABZCSNo spikesFigure 4.11: Measured waveforms of the tank voltage VAB and diodes current iD. (Vin =120V , Vo = 48V , Po = 350W , fs = 135kHz)564.7. Experimental Waveforms15V / div 2 µSec/ div8A / diviDVoFigure 4.12: Measured waveforms of the output voltage Vo and diodes current iD. (Vin =120V , Vo = 48V , Po = 350W , fs = 135kHz)Switching WaveformsSwitching waveforms are presented for the low side switch (Q1) and the high sideswitch (Q4). For each switch, the waveforms were captured at both the peak and zerocrossing of the input AC current. Even though ZVS is guaranteed at the peak if it isachieved at zero crossing, the peak waveforms is important to show the shape of theswitch current while carrying the sum of input inductor and resonant tank currents.Low side switch Q1 waveforms are shown in Figure 4.13 and Figure 4.14, while highside switch Q4 waveforms are shown in Figure 4.15 and Figure 4.16. It can be seen thatfor all cases, the drain to source voltage drops to zero before the next gate signal isapplied. In other words, ZVS is achieved.574.7. Experimental Waveforms10V / div3A / div 200V / div 2 µSec/ diviQVDSVGSZVSFigure 4.13: Measured waveforms of Q1 : current iQ1, gate to source VGS, and drain tosource VDS voltages at iin = 0. (Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz)10V / div3A / div 200V / div 2 µSec/ diviQVDSVGSZVSFigure 4.14: Measured waveforms of Q1 : current iQ1, gate to source VGS, and drain tosource VDS voltages at iin =√2Iin. (Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz)584.7. Experimental Waveforms10V / diviQVDSVGS3A / div 200V / div 2 µSec/ divZVSFigure 4.15: Measured waveforms of Q4 : current iQ4, gate to source VGS, and drain tosource VDS voltages at iin = 0. (Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz)10V / diviQVDSVGS3A / div 200V / div 2 µSec/ divZVSFigure 4.16: Measured waveforms of Q4 : current iQ4, gate to source VGS, and drain tosource VDS voltages at iin =√2Iin. (Vin = 120V , Vo = 48V , Po = 350W , fs = 135kHz)594.7. Experimental Waveforms4.7.2 Half Load OperationThe prototype was tested at partial load. For instance, half load operation resultsare presented in this section. The experiment was conducted at 120 V input and 172 Woutput power.Input AC WaveformsThe output voltage is regulated under partial load conditions using variable dutycycle. The ripple cancellation for the input current is not maximum as for 0.5 duty cycle.Figure 4.17 shows the effect of varying D on it compared to single inductor current. Theinput AC current is shown with vin in Figure 4.18. Also, the output voltage (Vo) alongwith the input AC voltage are shown in Figure 4.19, which indicates very small lowfrequency ripples at the output.90V / div 3A / div 5 mSec/ div3A / divvinitiLFigure 4.17: Measured waveforms of the rectified voltage vin, current it, and inductorcurrent iL1. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz)604.7. Experimental Waveforms100V / div 2A / div 5 mSec/ div2A / divitviniinFigure 4.18: Measured waveforms of the AC voltage vin, current iin, and it. (Vin = 120V ,Vo = 48V , Po = 172W , fs = 140kHz)90V / div 5 mSec/ div15V / divvinVoFigure 4.19: Measured waveforms of the output voltage Vo. (Vin = 120V , Vo = 48V ,Po = 172W , fs = 140kHz)614.7. Experimental WaveformsResonant Tank WaveformsThe effect of duty cycle variations on LLC tank variables is depicted in the nextfigures. Figure 4.21 and Figure 4.22 show the semi square wave, which has lower fun-damental component, applied to the resonant tank and the resultant iLr. The highfrequency oscillations in iLr and the primary side across Lm (Vpr), are because of the res-onance between Lr and Lm in the primary, and the junction capacitances of the diodesin the secondary, see the equivalent circuit in Figure 4.20. The diodes current is shownwith the tank voltage in Figure 4.23, and with the output voltage in Figure 4.24 to checkthe high frequency ripples.LrLmCr Vpr2CJn2Figure 4.20: Measured waveforms of the tank300V / div 2A / div 2 µSec/ div200V / divvCrVABiLrNo spikesFigure 4.21: Measured waveforms of the tank voltage VAB, current iLr, and resonant capvoltage vCr. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz)624.7. Experimental Waveforms300V / div 2A / div 2 µSec/ div300V / divVprVABiLrNo spikesFigure 4.22: Measured waveforms of the tank voltage VAB, current iLr, and primaryvoltage Vpr. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz)300V / div 2 µSec/ div8A / diviDVABNo spikesFigure 4.23: Measured waveforms of the tank voltage VAB and diodes current iD. (Vin =120V , Vo = 48V , Po = 172W , fs = 140kHz)634.7. Experimental Waveforms15V / div 2 µSec/ div8A / diviDVoFigure 4.24: Measured waveforms of the output voltage Vo and diodes current iD. (Vin =120V , Vo = 48V , Po = 172W , fs = 140kHz)Switching WaveformsSimilar to full load operation, switching waveforms are presented for Q1 and Q4 at thepeak and zero crossing of iin. Low side switch Q1 waveforms are shown in Figure 4.25and Figure 4.26, while high side switch Q4 waveforms are shown in Figure 4.27 andFigure 4.28. It can be seen that ZVS is still achieved in all cases because variable dutycycle operation was considered in the design of Lm.644.7. Experimental Waveforms10V / div3A / div 200V / div 2 µSec/ diviQVDSVGSZVSFigure 4.25: Measured waveforms of Q1 : current iQ1, gate to source VGS, and drain tosource VDS voltages at iin = 0. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz)10V / div3A / div 200V / div 2 µSec/ diviQVDSVGSZVSFigure 4.26: Measured waveforms of Q1 : current iQ1, gate to source VGS, and drain tosource VDS voltages at iin =√2Iin. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz)654.7. Experimental Waveforms10V / diviQVDSVGS3A / div 200V / div 2 µSec/ divZVSFigure 4.27: Measured waveforms of Q4 : current iQ4, gate to source VGS, and drain tosource VDS voltages at iin = 0. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz)10V / diviQVDSVGS3A / div 200V / div 2 µSec/ divZVSFigure 4.28: Measured waveforms of Q4 : current iQ4, gate to source VGS, and drain tosource VDS voltages at iin =√2Iin. (Vin = 120V , Vo = 48V , Po = 172W , fs = 140kHz)664.7. Experimental Waveforms4.7.3 Off-Nominal Input AC OperationThe operation of the converter was tested at low and high input AC Voltage. Therange of vin is from 100 V to 140 V RMS. At high input voltages, the control technique issimilar to partial load operation. Duty cycle is less than 0.5 to limit the DC bus voltagefor increasing and applying semi square wave to the LLC tank. The input waveformsfor 140 V operation are shown in Figure 4.29 and Figure 4.30 with the output voltage.Also, the resonant tank waves are shown in in Figure 4.31 and Figure 4.32.On the other hand, the switching frequency is decreased below resonant frequency foin low input voltage condition. Operation below resonant fo provides boosting gain forthe reduced DC bus voltage as a result of low vin. The operation was tested at 100 Vinput and the results are given in Figure 4.33 and Figure 4.34. The change in iLr shape,due to below fo operation, can be seen in Figure 4.35. Finally, the output voltage isshown with iD in Figure 4.36.90V / div 5 mSec/ div3A / divvinitFigure 4.29: Measured waveforms of the rectified voltage vin and current it. (Vin = 140V ,Vo = 48V , Po = 350W , fs = 140kHz)674.7. Experimental Waveforms90V / div 5 mSec/ div15V / divvinVoFigure 4.30: Measured waveforms of the output voltage Vo. (Vin = 140V , Vo = 48V ,Po = 350W , fs = 140kHz)300V / div 2A / div 2 µSec/ div8A / diviDVABiLrNo spikesFigure 4.31: Measured waveforms of the tank voltage VAB, current iLr, and diodes currentiD. (Vin = 140V , Vo = 48V , Po = 350W , fs = 140kHz)684.7. Experimental Waveforms15V / div 2 µSec/ div8A / diviDVoFigure 4.32: Measured waveforms of the output voltage Vo and diodes current iD. (Vin =140V , Vo = 48V , Po = 350W , fs = 140kHz)90V / div 5 mSec/ div3A / divvinitFigure 4.33: Measured waveforms of the rectified voltage vin and current it. (Vin = 100V ,Vo = 48V , Po = 350W , fs = 100kHz)694.7. Experimental Waveforms90V / div 5 mSec/ div15V / divvinVoFigure 4.34: Measured waveforms of the output voltage Vo. (Vin = 100V , Vo = 48V ,Po = 350W , fs = 100kHz)300V / div 2A / div 2 µSec/ div8A / diviDVABiLrNo spikesbelow f  operationoFigure 4.35: Measured waveforms of the tank voltage VAB, current iLr, and diodes currentiD. (Vin = 100V , Vo = 48V , Po = 350W , fs = 100kHz)704.8. PF and THD Measurements15V / div 2 µSec/ div8A / diviDVoFigure 4.36: Measured waveforms of the output voltage Vo and diodes current iD. (Vin =100V , Vo = 48V , Po = 350W , fs = 100kHz)4.8 PF and THD MeasurementsIn order to specify the quality of the input AC current, PF and THD have to be incompliance with the international standards. As stated earlier, IEC 61000-3-2 standardsdefine the limits of harmonic current emissions for different applications and ratings.Class C limits are compared to the current harmonics of the experimental prototypesince it is used for driving LED lighting. As shown in Table 1.1, the limit of eachharmonic component is defined as a percentage of the fundamental current RMS.The input current harmonics and PF were measured using YOKOGAWA WT500power analyzer at different input and loading conditions. Figure 4.37 and Figure 4.38shows the comparison of iin harmonics to IEC standards at full and half loads respectively.Also, harmonics at full load and low input AC voltage are depicted in Figure 4.39. It isimportant to check the low input condition since the DC bus voltage is low at this casewhich affects the shape of iin due to high ratio α.714.8. PF and THD MeasurementsIEC 61000-3-2 Class CFull load Vin=120V05101520253035Harmonic order3 5 7 9 11 13 15IhI1%IhI1Figure 4.37: Input current harmonics at full load. (Vin = 120V , Iin = 3.17A, Po = 350W ,PF = 0.9967)05101520253035Harmonic order3 5 7 9 11 13 15IhI1%IEC 61000-3-2 Class CFull load Vin=120V25 %IhI1Figure 4.38: Input current harmonics at 25% full load. (Vin = 120V , Iin = 0.9944A,Po = 93W , PF = 0.9945)724.9. Efficiency Measurements05101520253035Harmonic order3 5 7 9 11 13 15IhI1%IhI1IEC 61000-3-2 Class CFull  load Vin=100VFigure 4.39: Input current harmonics at low vin. (Vin = 100V , Iin = 3.837A, Po = 351W ,PF = 0.9944)In all three cases, the harmonics are in compliance with IEC 61000-3-2 Class C.Furthermore, PF is higher than 0.994 for all cases (PF for each case is mentioned in thefigure caption).4.9 Efficiency MeasurementsYOKOGAWA WT500 power analyzer consists of three channels. By utilizing two ofthem for input and output power measurements, the efficiency was measured at differentloading points and is plotted against the output power in Figure 4.40. The converterachieves maximum efficiency of 92.3% at 120 V input AC and full load. Also, Figure 4.41shows the efficiency versus different input AC voltage values.734.9. Efficiency Measurements87 175 263 35085868788899091929394Efficiency η %Loading (W)Figure 4.40: Efficiency measurements for different loading points.Efficiency η %Input voltage (V)100 110 120 130 1409191.291.491.691.89292.292.492.692.893Figure 4.41: Efficiency measurements for different input voltages.744.10. Summary4.10 SummaryIn this chapter, the design details of each component were presented. Starting withthe boost cell, principles behind choosing the input inductors to achieve input currentshaping, were analyzed. Then, the DC bus capacitor design was based on limiting thedouble line frequency oscillation at the DC bus for better regulation at the output.For the resonant tank, resonant components (Lr, Cr, and Lm) were designed accordingto the switching frequency rang, ZVS requirement, input voltage range, and efficiencyoptimization. Semiconductor devices were selected to withstand the operational voltagesand currents based on the theoretical analysis and simulation results.Finally, an experimental prototype was designed and tested to verify the operationof the proposed topology. Experimental waveforms were presented at different loadingand input operating conditions. The results match the analysis presented in chapter 3.Furthermore, the input current quality was compared to the international standards toensure it compliance. The converter achieves high input current quality and efficiency.75Chapter 5ConclusionThis chapter presents an overview for the research proposed in this thesis. Also, itincludes suggested research points to improve the performance and control strategy ofthe proposed single-stage topology.5.1 OverviewWith the increasing demand for DC electricity in various applications, AC/DC con-verters have to be redesigned to enable more efficient and reliable solutions. The conven-tional two-stage AC/DC converters have been predominant for many decades regardlessof the type and power level of the application. However, specially for low to mediumpower applications, AC/DC converters can be optimized to offer lower cost, simpler con-trol, and more efficient conversion. Integrated single-stage AC/DC converters offer suchadvantages since they use the same active switches to achieve input current shaping andtightly regulated isolated output voltage.This thesis reviewed the existing single-stage topologies in the literature with a briefsummary of the operation, advantages, and disadvantages of each one. It was concludedthat the main shortcoming of the existing topologies is either the limited power due to theDCM operation of the input iductor, or the complicated switching scheme. Therefore,the proposed topology aims to provide simple control with a performance close to CCMoperation which pushes the limit of power ratings. The converter is well situated for highpower LED lighting applications.765.2. Future WorkThe proposed topology integrates boost-type interleaved PFC with LLC resonanttank employing shared full bridge. After introducing the basic principles of AC/DCconversion and the literature review in the first two chapters, the proposed converterwas analyzed in great depth in chapter 3 where the operation modes, performance, andcontrol technique were illustrated.After that, a comprehensive design procedure of an experimental prototype was pre-sented in chapter 3. Various tests were conducted using the prototype to verify theoperation of the converter. The results demonstrated compliance with the theoreticalanalysis and input current harmonic standards.5.2 Future WorkThere are several research points which can be based on the work proposed in thisthesis. The research focused mainly on the analysis and design of the proposed converterfrom the topology aspect. In addition, brief analysis for the proposed control techniquewas mentioned. The suggested research points are classified into two main areas.5.2.1 Modeling and ControlTypically, boost PFC is modeled using the popular state space averaging technique orthe current-injected equivalent circuit approach [29][30], whereas LLC resonant converteris modeled using Extended Describing Function method (EDF) [31][32]. The proposedtopology integrates both boost PFC and LLC tank, hence more research should be fo-cused on how to model the converter so that the dynamics can be captured accurately.Furthermore, the hybrid duty cycle and frequency control technique, see section 3.5,should be investigated to evaluate if the switching frequency can be determined based onpredefined table values proportional to the input AC voltage to achieve simpler controltechnique.775.2. Future Work5.2.2 Topology ModificationEfficiency improvements can be achieved if the bridge rectifier is eliminated. Onepossible solution to obtain bridgeless converter is CRM operation of the interleaved boostcell. However, under CRM, the frequency and duty cycle are variable which affect theLLC gain and the output voltage accordingly. Therefore, the proposed method in [33][34]might be applied to compensate for the changing duty cycle and switching frequency.78Bibliography[1] S. D. Freeland, I. A unified analysis of converters with resonant switches. II. Input-current shaping for single-phase AC-DC power converters. PhD thesis, CaliforniaInstitute of Technology, 1988.[2] I. Standard, “61000-3-2: 2004, limits for harmonic current emissions,” InternationalElectromechanical Commission. Geneva, 2004.[3] C. Branˇas, F. J. Azcondo, and S. Bracho, “Evaluation of an electronic ballast circuitfor HID lamps with passive power factor correction,” in Proc. IECON 02, vol. 1,pp. 371–376, 2002.[4] Y. Tang, F. Blaabjerg, P. C. Loh, C. Jin, and P. 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Ye, “Variable-duty-cycle control to achieve highinput power factor for DCM boost PFC converter,” Industrial Electronics, IEEETransactions on, vol. 58, no. 5, pp. 1856–1865, 2011.[21] K.-H. Liu and Y.-L. Lin, “Current waveform distortion in power factor correctioncircuits employing discontinuous-mode boost converters,” in Power Electronics Spe-cialists Conference, 1989. PESC’89 Record., 20th Annual IEEE, pp. 825–829, IEEE,1989.[22] M. OLoughlin, “350W, two phase interleaved PFC pre-regulator design review,” TIliterature No. SLUA369B, 2006.[23] B. Yang, F. C. Lee, A. J. Zhang, and G. Huang, “LLC resonant converter forfront end DC/DC conversion,” in IEEE Applied Power Electronics Conference andExposition (APEC), vol. 2, pp. 1108–1112, 2002.[24] R. L. Steigerwald, “A comparison of half-bridge resonant converter topologies,”Power Electronics, IEEE Transactions on, vol. 3, no. 2, pp. 174–182, 1988.[25] S. De Simone, C. Adragna, C. Spini, and G. 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