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Optimization of a grid-tied inverter : an application-oriented for designing multilevel converters Di Tullio, Luccas 2016

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cptimizution oz u GrixAhiyxInvyrtyrUn UppliwutionAcriyntyx Upprouwh zorDysigning aultilyvyl WonvyrtyrsbyLuccas Di TullioB.A.Sc., The University of British Columbia, 2012A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinThe Faculty of Graduate and Postdoctoral Studies(Electrical & Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)July 2016c© Luccas Di Tullio 2016UvstruwtRecent developments in energy systems, including the rapid adoption of renewable energysources and expansion of microgrids have been introducing new challenges and opportunitiesfor the power electronics industry. Of particular interest to this thesis is the increase of grid-connected DC systems. As a means to reduce cost of copper infrastructure these systemsfavour the utilization of higher DC link voltages. To accommodate higher voltages, a varietyof multilevel converters have been proposed, which generally can be built without specializedcomponents, present lower sd Lst losses and synthesize AC signals with better power quality.Irrespective of the application, the power electronics industry has traditionally relied ongeneric rules and practices to quickly design converters. Rarely does the development cycleallow for thorough investigation of the converter design, which could enhance performanceand give an edge over competitors. This thesis proposes using optimization techniques to aidpower electronics engineers in the design of multilevel converters.The Neutral Point Clamped (NPC) with its variant the Active NPC (ANPC) were selectedfor the exercise presented. Chapter 2 of this thesis explains the operation and modulationof the topologies. From the analysis, the conduction and switching losses of each devicecan be predicted. A description of three semiconductor technologies is presented with theircharacteristics and source of losses. Lastly an equation to size the filter inductor is introduced.All this information is packaged into a model used in the optimization.Chapter 3 introduces the optimization strategy. Given the complex nature of powerelectronics, four objective functions were adopted: efficiency, loss distribution, inductanceii3TefdScfand cost. These functions were combined through a weight system which allows priorities tobe asserted. Next, design variables are introduced along with their respective impacts on theobjective functions.Experiments performed with a hardware platform showed the model closely predicts theimpact of the design variables on the objective functions. Confident in the model, the opti-mization was carried out for various scenarios. Single objective optimization led to convertersthat excel in one aspect but were often not practical. When optimizing with multiple objec-tives a good compromise was reached with a practical converter.iiidryzuwyThis work is based on research performed at the Electrical and Computer Engineering de-partment of the University of British Columbia by Luccas Di Tullio, under the supervisionof Dr. Martin Ordonez. Some experimental validation work was completed in collaborationwith Dr. David Campos-Gaona. The optimization search was performed in collaborationwith Dr. Seyed Ali Arefifar.A subset of this thesis has been accepted in the IEEE International Symposium on PowerElectronics for Distributed Generation Systems (PEDG) 2016.As first author of the above-mentioned publication and work, the author of this thesisdeveloped the theoretical concepts and wrote the manuscripts, receiving advice and technicalguidance from Dr. Martin Ordonez. Chapter 4 presented experimental work on a hardwareplatform developed by Luccas Di Tullio with support of Dr. Martin Ordonez’s research team,in particular of Dr. David Campos-Gaona. In the same chapter, results of the optimizationproposed in this work was completed with collaboration of Dr. Seyed Ali Arefifar.ivhuvly oz WontyntsUvstruwt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iidryzuwy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivhuvly oz Wontynts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vList oz huvlys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiiList oz Figurys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixUwknowlyxgmynts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiE Introxuwtion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.1 Multilevel Inverter Topologies . . . . . . . . . . . . . . . . . . . . . . 31.2.2 Optimization of Power Electronics . . . . . . . . . . . . . . . . . . . 51.3 Contribution of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7F cptimizution aoxyl zor aultilyvyl hopologiys . . . . . . . . . . . . . . . . 92.1 Modeling of the Neutral Point Clamped Converter . . . . . . . . . . . . . . 92.1.1 Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 9vFSTlW af 5anfWnfe2.1.2 Modulation Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1.3 Conduction and Switching Losses . . . . . . . . . . . . . . . . . . . . 132.2 Modeling of the Active Neutral Point Clamped Converter . . . . . . . . . . 172.2.1 Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 172.2.2 Modulation Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . 182.2.3 Conduction and Switching Losses . . . . . . . . . . . . . . . . . . . . 212.3 Semiconductor Losses Model . . . . . . . . . . . . . . . . . . . . . . . . . . 242.3.1 MOSFET Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.3.2 IGBT Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.3.3 Diode Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.4 Inductor Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29G cptimizution drovlym gtruwtury . . . . . . . . . . . . . . . . . . . . . . . . 303.1 Objective Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.1.1 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.1.2 Loss Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.1.3 Filter Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.1.4 Semiconductor Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.1.5 Weighted Objective Function . . . . . . . . . . . . . . . . . . . . . . 333.2 Optimization Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.2.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 353.2.2 Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.2.3 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403.2.4 Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.3 Optimization Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43viFSTlW af 5anfWnfe3.3.1 Variable Output Power . . . . . . . . . . . . . . . . . . . . . . . . . 443.3.2 Variable Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3.3 Variable Output Power and Power Factor . . . . . . . . . . . . . . . 453.3.4 Optimization Based on Utilization Profile . . . . . . . . . . . . . . . 453.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Efipyrimyntul julixution unx fysults . . . . . . . . . . . . . . . . . . . . . . 474.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.2 Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.2.1 Efficiency Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.2.2 Loss Distribution Validation . . . . . . . . . . . . . . . . . . . . . . 514.3 Optimization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.3.1 Single Objective Function . . . . . . . . . . . . . . . . . . . . . . . . 534.3.2 Multi-Objective Function . . . . . . . . . . . . . . . . . . . . . . . . 564.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57I Wonwlusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Vivliogruphy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62viiList oz huvlys2.1 NPC Switching States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2 Device Currents in NPC Using SPWM . . . . . . . . . . . . . . . . . . . . . 152.3 Possible Combination of ANPC Switching States . . . . . . . . . . . . . . . 182.4 Device Currents in ANPC Using SPWM . . . . . . . . . . . . . . . . . . . . 233.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.2 Considered Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . 444.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.2 Optimization for Efficiency Only . . . . . . . . . . . . . . . . . . . . . . . . . 544.3 Optimization for Loss Distribution Only . . . . . . . . . . . . . . . . . . . . 554.4 Optimization for Inductance Only . . . . . . . . . . . . . . . . . . . . . . . . 554.5 Optimization for Cost Only . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.6 Optimization with Equal Weights . . . . . . . . . . . . . . . . . . . . . . . . 574.7 Optimization for Efficiency with Cost Restriction . . . . . . . . . . . . . . . 57viiiList oz Figurys1.1 Typical Microgrid Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Multilevel Inverter and Output Voltage Waveform . . . . . . . . . . . . . . . 31.3 Multilevel Topologies: (a) NPC, (b) Flying Capacitor, (c) MMC . . . . . . . 41.4 Multilevel Topologies: ANPC . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 NPC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.2 Modulation Strategies for NPC: Sinusoidal PWM . . . . . . . . . . . . . . . 122.3 NPC Driving Signals using Sinusoidal PWM . . . . . . . . . . . . . . . . . . 122.4 Conducting Devices on the NPC Converter . . . . . . . . . . . . . . . . . . . 142.5 NPC Switching Losses: (a) eoc and ioc in-phase, (b) eoc and ioc out-of-phase 162.6 ANPC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.7 Modulation Strategies for ANPC: Sinusoidal PWM . . . . . . . . . . . . . . 192.8 ANPC Driving Signals using Sinusoidal PWM . . . . . . . . . . . . . . . . . 192.9 Conducting Devices on the ANPC Converter . . . . . . . . . . . . . . . . . . 222.10 ANPC Switching Losses: (a) P to 0+1 when eoc and ioc in-phase, (b) P to 0+1when eoc and ioc out-of-phase, (c) P to 0+2 when eoc and ioc in-phase, (d) Pto 0+2 when eoc and ioc out-of-phase . . . . . . . . . . . . . . . . . . . . . . 252.11 IGBT and MOSFET Utilization Spectrum . . . . . . . . . . . . . . . . . . . 263.1 Representation of the Design Variables . . . . . . . . . . . . . . . . . . . . . 353.2 Efficiency at Different Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . 37ixLief af FiggdWe3.3 Loss Distribution at Different Loads . . . . . . . . . . . . . . . . . . . . . . . 373.4 Minimum Inductance at Different Loads . . . . . . . . . . . . . . . . . . . . 383.5 Efficiency at Different Power Factors . . . . . . . . . . . . . . . . . . . . . . 393.6 Loss Distribution at Different Power Factors . . . . . . . . . . . . . . . . . . 393.7 Efficiency at Different Switching Frequencies . . . . . . . . . . . . . . . . . . 403.8 Minimum Inductance at Different Switching Frequencies . . . . . . . . . . . 414.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.2 Topologies of the Experimental Platform (a) NPC and (b) ANPC . . . . . . 494.3 Hardware Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.4 Theoretical and Measured Efficiency: (a) 18 kHz with PF = 1 and (b) 9 kHzwith PF = -1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.5 Loss Distribution For NPC with MOSFET at PF = 1: (a) Calculated Lossesper Device and (b) Thermal Capture . . . . . . . . . . . . . . . . . . . . . . 524.6 Loss Distribution For NPC with MOSFET at PF = -1: (a) Calculated Lossesper Device and (b) Thermal Capture . . . . . . . . . . . . . . . . . . . . . . 524.7 Loss Distribution For ANPC with MOSFET at PF = 1: (a) Calculated Lossesper Device and (b) Thermal Capture . . . . . . . . . . . . . . . . . . . . . . 53xUwknowlyxgmyntsI would like to show my gratitude to my supervisor Dr. Martin Ordonez for accepting me aspart of his research team, for his support and above all his patience.I must acknowledge the team at Alpha Technologies Ltd, in particular Victor Goncalvesand Lucas Sinopoli, who inspired me to pursue this masters degree. Without their visionand experience, the value of this degree would not be evident and possibly never considered.To the members of the Dr. Ordonez Research Team, I would like to thank you all.Whether directly helping me setting up a hardware platform, troubleshooting software, or justchatting during breaks, without you my time in the lab would have never been as enjoyableas it was. A special thank you to Dr. Rafael Pena-Alzola for sharing some his extensivetechnical knowledge, Dr. Seyed Ali Arefifar for all his contributions to the optimization workof this thesis, and Dr. David Campos-Gaona for his countless hours of support, teachingsand encouragement.My deepest gratitude to my friends and most significantly my girlfriend Jenna, for keepingme going during the entire duration of this degree.And a very special thank you to my parents for their support, emotional and financial,during the journey that brought me to where I am at today. Without them, all my achieve-ments would not have possible, and this degree would have never been conceivable. For thatand much more I am extremely grateful.xiWhuptyr EIntroxuwtionEBE aotivutionTechnological advancements have been rapidly increasing the efficiency and reliability ofrenewable energy sources making them more financially attractive while reducing the envi-ronmental impacts of fossil fuels. As a consequence an increase in adoption of renewableshas taken place in recent years, and this trend is likely to continue as many governmentsaim to reduce their emissions. Although many obvious benefits drive the intention of mak-ing renewable utilization more widespread, several challenges arise from the deployment ofalternative energy plants. In the technical context, significant research is being conducted inthe areas of energy storage, dealing with intermittent nature of energy sources, microgridsand reliable grid integration.As renewable energy becomes more affordable the expansion of microgrids is inevitable.In such systems it is common to make use of a common DC bus to integrate different energysources, storage and loads such as in Fig. 1.1. A variety of power converters are used tointerface the different components of the microgrid to the DC bus, to ensure controlled powerflow and prevent equipment damage. Power converters are also necessary to reliably integratethe microgrid to the utility power grid without affecting power quality.Multilevel inverters have been proposed as a solution to convert elevated DC voltages,which in turn reduces copper cost on an energy system using a DC bus. These invertersare capable of synthesizing multiple output voltage levels, as shown in Fig. 1.2, whereas a11.1. MafihSfianGridLoadGeneratorGeneratorStorageStorageDC LinkFigure 1.1: Typical Microgrid Configurationtraditional inverter outputs the positive and negative values of the DC bus. The additionalvoltage levels lower the total harmonic distortion (THD) hence improving power quality.The semiconductors in multilevel topologies must block a fraction of the DC bus voltagewhich leads to lower sd Lst losses. Another advantage is the cost of the semiconductors sincestandard components may be used in multilevel inverters instead of expensive high rateddevices used in the two-level counterparts.Recent improvements in semiconductor technologies introduced a new horizon of optionsdesigners may consider to use in modern power electronics. Given the characteristics of dif-ferent component types, component selection must be carefully considered as it has a directimpact on performance, density and cost of the converter. Bearing these considerations inmind, designers must have a full understanding of the converter’s most probable operating21.2. LifWdSfgdW RWhiWiVdc+-Vdc+-VoutNVoutVdc-V dcFigure 1.2: Multilevel Inverter and Output Voltage Waveformconditions, and desired customer’s requirements such as efficiency and size, and design ac-cordingly. Optimization techniques used across different engineering fields, including powersystems, may become a powerful ally in the design process resulting in a cost effective andbetter performing converter for a given set of desired converter characteristics.EBF Lityrutury fyviywEBFBE aultilyvyl Invyrtyr hopologiysSince the first introduction of multilevel converters [1, 2], a vast variety of topologies andvariations thereof have been proposed. Among the most used topologies are the Neutral PointClamped (NPC) introduced in [1], the Flying Capacitor [3], Cascaded Inverters [4, 5] andModular Multilevel Converter (MMC) [6]. A three-level single-phase leg of the mentionedtopologies is shown in Fig. 1.3. Comparative analyses have been presented in [7, 8] whichallows a thorough understanding of each topology’s advantages and disadvantages.As an expected outcome of a comparative analysis, each topology presents more suitability31.2. LifWdSfgdW RWhiWiS1Vdc+-Vdc+-D5D6S2S3S4iphS1Vdc+-Vdc+-S2S3S4iphS11S12S21S22S31S32S41S42iphVdc+-Vdc+-(a) (b)(c)Figure 1.3: Multilevel Topologies: (a) NPC, (b) Flying Capacitor, (c) MMCfor specific applications. Some topologies favour applications with high AC frequency suchas high speed drives, while others present higher reliability in case of component failures.Among the mostly used topologies, the Neutral Point Clamped (NPC) converter has beenadopted as the most adequate for grid connected applications.Originally introduced in [1], the NPC inverter is arguably the most widely used multileveltopology across a diverse range of applications and industries. The high utilization of thetopology has lead to a good understanding of its limitations and extensive research has beenconducted to improve its performance. A typical characteristic of the NPC converter isits uneven loss distribution [9], which leads to difficult heat management and restricts powerdensity. In [10] a variation of the topology named the Active Neutral Point Clamped (ANPC)converter, shown in Fig. 1.4, was developed with the intention of dealing with the unevenlosses. From its initial conception several strategies have been proposed with the goal of41.2. LifWdSfgdW RWhiWiS1Vdc+-Vdc+-S5S6S2S3S4NiphFigure 1.4: Multilevel Topologies: ANPCimproving loss distribution. The most common strategies make use of additional zero statesprovided by the topology and propose new modulation techniques [11, 12], and some makeuse of a closed loop system to select the most adequate zero state [13, 14].EBFBF cptimizution oz dowyr ElywtroniwsFiercer competition in the power electronics industry, coupled with fast technology improve-ments have led to the development of significantly superior power converters. In order tosustain a competitive edge in such an environment, designers must make the best utilizationof available resources to meet the most critical consumer needs. Over recent years, optimiza-tion techniques have proven to be a great ally to power electronics designers allowing themto achieve better results faster.Experienced power electronics designers must have thorough understanding of severalareas within the engineering domain ranging from semiconductor characteristics to fast dy-namic control, passing through EMI, thermal management and packaging. Given the shortdevelopment time available, designers can seldom give appropriate attention to all the aspectsof the converter even though they all may affect the performance of the final product.Several types of optimization techniques have been applied to power electronics to aiddesigners. In [15, 16] a PFC converter was designed with goal of minimizing the cost of51.3. 5anfdiTgfian af fhW Iadkmagnetic components. Efficiency is often the main goal of optimization algorithms, anddifferent approaches have been proposed. In [17, 18] the efficiency of a two-level inverter wasoptimized by improving the switch driver design, a similar approach was also used to optimizethe efficiency of an ANPC converter [19]. In [20] the efficiency was indirectly optimized byminimizing the converter weight, which in turn lead to the design requiring the smallestheatsinks due to the lowest losses.Most optimization problems aim to design the converter for operation at one specificcondition. To account for the fact that converter must operate efficiently under differentloading conditions, a two stage optimization was proposed in [21]. This optimization leadto better efficiency distribution, but obviously does not beat a converter operating at itsdesigned operating point.EBG Wontrivution oz thy korkConsidering the benefits brought by multilevel topologies and the stricter power qualityregulations imposed by utilities, it is possible to foresee a demand increase for multilevelinverters aligned with a shift from traditional two-level inverters to their more advancedcounterparts. Such advancements require power electronics manufacturers to expand theirknowledge base on this topic, but accounting for all available topologies and technologiesindividually is an excessive burden on designers. A guidance tool which optimizes the designin a quick manner may become a valuable asset, providing engineers with fast solutions andbetter insight into the design.Optimization tools that consider different topologies for a given problem have been pro-posed [22], but are slow and only consider basic topologies. The work presented in this thesisconsiders different multilevel topologies along with different semiconductor technologies topropose a design. The optimization revolves around the designer, who decides what is the61.4. FhWeie AgflinWmost critical characteristic that should be optimized: efficiency, thermal distribution, induc-tor size, cost, or a combination thereof. Unlike previous solutions, the optimization routineaccounts for the utilization pattern in terms of loading conditions and power flow direction.The intent is to take advantage of the bidirectional nature of the topologies, since they arecapable of working strictly as a rectifier or inverter, but often will switch between the twomodes throughout normal operation.Provided the designer has basic understanding of multilevel converters and their operatingconditions, and provides the tool with reasonable design options the results include:• Selection between NPC and ANPC topology• Device combination optimized for the application• Optimized switching frequency• Estimated efficiency, loss distribution, required filter inductance and converter costEB4 hhysis cutlinyThe work performed for this thesis is presented in the following manner:• Chapter 2 presents the operation principle of the topologies considered for the opti-mization problem, the NPC and ANPC. The operating states of the topologies areintroduced along with their most common modulations. Diagrams show the voltageand current flow directions and assist in the visualization of the component stress,which is relevant to identify conduction and switching losses. Semiconductor devicestypes considered for the optimization are introduced, describing their typical powerlosses. Lastly inductor design considerations are introduced along with their impact onTHD.71.4. FhWeie AgflinW• Chapter 3 describes the structure of the optimization problem. It introduces a weightedobjective function, which allows designers to assert priorities over certain performanceaspects. The designed variables are presented along with an analysis of their impacton the objective function. Last the optimization stages are listed with potential appli-cations that could be benefited from each.• Chapter 4 presents experimental and optimization results of the work proposed inthe thesis. An experimental platform was built and its components and operation isdescribed. Using this platform, the models developed in Chapter 2 are validated interms of their accuracy and trends when calculating the desired parameters: efficiency,loss distribution, inductance and cost. Confident the model accurately estimates theperformance for various converter configurations under different operating conditions,the optimization is carried out. The optimization system introduced in Chapter 3 is putto test here. First single-objective optimization are performed their results analyzed.This study is useful to highlight the drawbacks of these simpler optimizations. Nextmulti-objective optimizations are carried out and their results are carefully analyzed toensure their feasibility, correctness, and if in fact the results are more realistic than thesingle-objective counterparts.• Chapter 5 concludes the thesis with comments and observations of the results presented.It wraps up with outstanding work that may be investigated to further enhance theresults.8Whuptyr Fcptimizution aoxyl zor aultilyvylhopologiysAs a first step in designing an optimized multilevel inverter, the key aspects of the targettopologies must be well understood. A model that estimates performance parameters of theconverter, such as losses, is developed in the chapter. The topologies are described along withtheir operation, which leads to a deep understanding of the system. Next the characteristicsof the semiconductors are introduced along with performance equations. Lastly the relevanceof the filter inductor is explained, with an equation to size it.FBE aoxyling oz thy byutrul doint WlumpyxWonvyrtyrFBEBE drinwiply oz cpyrutionShown in Fig. 2.1, the three-level NPC topology consist of 4 active switches and two diodesclamped to the neutral point. This topology allows the output voltage to match the positiveand negative DC bus voltages as well as setting the output voltage to zero by connectingto the neutral point. Given these possibilities a sinusoidal output can be synthesized bymodulating three commonly used states listed in Table 2.1[11]. Traditionally switch pairs b1and b3, and b2 and b4 are driven complementary, which allows this converter to be treated92.1. MaVWling af fhW NWgfdSl Bainf 5lSmbWV 5anhWdfWdS1Vdc+-Vdc+-D5D6S2S3S4iphNFigure 2.1: NPC Converteras two half-bridge inverters [23], consequently simplifying its control.Since switches b1 through b4 are bidirectional, this converter is capable of deliveringpositive and negative currents, hence working as an inverter or a rectifier. This characteristicallows the converter to control not only the output active power, but it is also suited forreactive power compensation.A common problem with this topology is the imbalance in the capacitor voltages causedby component tolerances, which results in a drift of the neutral point voltage. If not properlydealt with, this imbalance may lead to large DC drifts in the output voltage, possibly makingthe system unstable. Several solutions have been proposed to deal with this issue, amongthem using advanced modulation techniques or controlling the neutral point current [23].Another drawback to note in this topology is the uneven loss distribution among thecomponents. This arises from the fact that during the positive half cycle of the output sinewave, the converter must switch between states P and 0. Analyzing the states, it is possibleto notice that switch b2 remains on for the entire half-cycle while b3 alternately turn on andoff. A more detailed explanation is available in the losses calculation subsection.102.1. MaVWling af fhW NWgfdSl Bainf 5lSmbWV 5anhWdfWdTable 2.1: NPC Switching Statesgtuty bumy Uwtivy gwitwhys cutput Voltugyd S1,S2 +ercD S2,S3 Db S3,S4 −ercFBEBF aoxulution gtrutygiysTo generate the desired sinusoidal output voltage on the NPC converter, a modulation strat-egy must be carefully selected. An extensive list of options are available and normally splitinto three categories: Sinusoidal Pulse Width Modulation (SPWM), Space Vector Modu-lation (SVM) and Selective Harmonic Elimination (SHE). Due to the wider utilization andsimplified implementation with modern microcontrollers, SPWM strategies will be consideredin the optimization problem.Figure 2.2 shows a typical SPWM modulation scheme. A reference signal for the desiredoutput voltage is generated and compared to a pair of triangular carriers with frequencymatching the target switching frequency. In this modulation scheme, two carriers are usedto separately modulate the positive and negative half-cycles of the reference signal. Theamplitude of the reference signal is determined by the desired modulation index M, and isselected based on the relation between DC and AC voltages as shown in equation 2.1:M =2 · eOCIrms ·√2eRC(2.1)where |M | ≤ 1 to avoid overmodulation. In the case shown the modulation index is one.In this modulation scheme, the intersection between the carriers and the reference drivesthe switches as shown in Fig. 2.3. Analyzing the switching action it is possible to find theduty cycle of each device [24], presented in (2.2) This information is useful when calculating112.1. MaVWling af fhW NWgfdSl Bainf 5lSmbWV 5anhWdfWd0 1 2 3 4 5 6−1−0.8−0.6−0.4−0.200.20.40.60.81Figure 2.2: Modulation Strategies for NPC: Sinusoidal PWMONONS1S2S3S4S1S2S3S4ONVout Vout0-Vdc/20VRefVRefPNP00 0ONVdc/2ONONONFigure 2.3: NPC Driving Signals using Sinusoidal PWMdevice losses.122.1. MaVWling af fhW NWgfdSl Bainf 5lSmbWV 5anhWdfWdsa1 =8>><>>:M · sin(!) 0 ≤ ! ≤ 0  ≤ ! ≤ 2sa2 =8>><>>:1 0 ≤ ! ≤ 1 +M · sin(!)  ≤ ! ≤ 2sa3 =8>><>>:1−M · sin(!) 0 ≤ ! ≤ 1  ≤ ! ≤ 2sa4 =8>><>>:0 0 ≤ ! ≤ M · sin(!)  ≤ ! ≤ 2(2.2)FBEBG Wonxuwtion unx gwitwhing LossysTo calculate the conduction and switching losses, the converter must to be analyzed in detailover one entire cycle. A single cycle can be split into a positive and a negative half-cycle,and each of these may be split into in-phase and out-of-phase conduction. Fig. 2.4 showsthe conducting devices at each portion of the cycle. In the figure a sinusoidal voltage withpeak at 1.0 delivers power with a current of peaking at 0.8 and with a phase shift of .From this point onwards they will be named eoc and ioc, where eoc(t) = eo · sin(! · t) andioc(t) = Io · sin(! · t− )In order to calculate the losses in each device of the converter, the average and RMScurrents on each device will be calculated using (2.3) and (2.4) respectively:IanIovu =12·∫ 20san · ioc · s! (2.3)I2anIRMa =12·∫ 20san · i2oc · s! (2.4)Given that switches b1 through b4 consist of a transistor with an anti-parallel diode, theequations above must be evaluated for both components individually. Equations (2.5) to(2.8) show the calculations of the currents for c1 and S1, the components of b1, when using132.1. MaVWling af fhW NWgfdSl Bainf 5lSmbWV 5anhWdfWdS1Vdc+-Vdc+-D5D6S2S3S4NiphS1Vdc+-Vdc+-D5D6S2S3S4NiphS1Vdc+-Vdc+-D5D6S2S3S4NiphS1Vdc+-Vdc+-D5D6S2S3S4NiphS1Vdc+-Vdc+-D5D6S2S3S4NiphS1Vdc+-Vdc+-D5D6S2S3S4NiphS1Vdc+-Vdc+-D5D6S2S3S4NiphS1Vdc+-Vdc+-D5D6S2S3S4NiphP 0P 0N 0N 0Figure 2.4: Conducting Devices on the NPC Converter142.1. MaVWling af fhW NWgfdSl Bainf 5lSmbWV 5anhWdfWdSPWM:Ib1Iovu =12·∫ M · sin(!) · ioc · s!=M · Io4· [( − ) · cos() + sin()](2.5)I2b1IRMa =12·∫ M · sin(!) · i2oc · s!=M · I2o12· [3 + 4 · cos() + cos(2)](2.6)IR1Iovu =12·∫ 0M · sin(!) · ioc · s!=M · Io4· [cos()− sin()](2.7)I2R1IRMa =12·∫ 0M · sin(!) · i2oc · s!=M · I2o12· [3− 4 · cos() + cos(2)](2.8)The average and RMS currents for all devices are found by extending the calculationsabove to the remaining components. The results are displayed in Table 2.2.Table 2.2: Device Currents in NPC Using SPWMDyviwy Uvyrugy Wurrynt (fag Wurrynt)2c1; c4M ·Io4 · o( − ) · cos() + sin()] M ·I2o12 · oG + Hcos() + cos(F)]c2; c3M ·Io4 · oH +  ·Mcos()−Msin()] M ·I2o12 · oG · ( −M) + H ·Mcos()−Mcos(F)]S1; S4M ·Io4 · ocos()− sin()] M ·I2o12 · oG− Hcos() + cos(F)]S2; S3M ·Io4 · ocos()− sin()] M ·I2o12 · oG− Hcos() + cos(F)]S5; S+Io − M ·Io4 · o( − F) · cos()− Fsin()] M ·I2o12 · oG − 6M − FMcos(F)]To understand the switching losses experienced by each component, the commutationsmust be carefully analyzed. Due to the symmetry of this converter, performing the analysison half a cycle is sufficient to identify the stresses due to switching losses on the outer, inner152.1. MaVWling af fhW NWgfdSl Bainf 5lSmbWV 5anhWdfWdT1D5T3P P0T1D5T3P P0icondVblockSwitchingLossesReverse Recovery LossesicondVblockSwitchingLosses(a) (b)Figure 2.5: NPC Switching Losses: (a) eoc and ioc in-phase, (b) eoc and ioc out-of-phaseand clamping devices.Starting with the transition between the positive voltage state, P to state 0. During thetransition c1 turns off and c3 turns on. When eoc and ioc have the same polarity, the currentflow changes from the positive branch through c1 and c2 to the upper neutral point branchthrough S5 and c2. In this case c1 experiences switching losses while no losses are incurredon c3 due to the lack of current flow. Clamping diode S5 experiences reverse recovery losses.When eoc and ioc have opposite polarities, the current flows changes from the positivebranch through S1 and S2 to the lower neutral point branch through c3 and S+. Switchinglosses are incurred in c3 in this scenario. Reverse recovery losses are incurred in diodes S1.Since the voltage across S+ remains constant, no reverse recovery is experienced. Fig. 2.5shows the commutations of the devices and their respective losses.Extending this analysis to the commutation between states 0 and N , the same switchinglosses are found in the other switch of the pair. From this analysis the total switching losseson the switch pairs can be found as a function of the power factor.162.2. MaVWling af fhW 3cfihW NWgfdSl Bainf 5lSmbWV 5anhWdfWdS1Vdc+-Vdc+-S5S6S2S3S4NiphFigure 2.6: ANPC ConverterFBF aoxyling oz thy Uwtivy byutrul doint WlumpyxWonvyrtyrFBFBE drinwiply oz cpyrutionAs a variation of the NPC converter, the ANPC shown in Fig. 2.6 presents many similaritiesand a few critical differences. The first noticeable difference between the two topologiesis the presence of active bidirectional switches clamping the ourput to the neutral point.This modification results in more flexibility in terms of operating states, which are directlydependent on the modulation strategy adopted. As an example, the modulation techniqueintroduced in [11] contains 4 zero states, which are presented in Table 2.3. Another advantagein terms of the switching states is that by using a clamping switch forces the blocking voltageson the disable switches to be identical. As the main advantage of these switching states isthe ability to be more selective when modulating the output, which ultimately may result ina more balanced loss distribution.Just like the NPC, this topology uses bidirectional switches that allow for positive andnegative current flow hence being capable of controlling active and reactive power. In termsof common drawbacks, the ANPC also faces imbalances in the capacitor voltages due to172.2. MaVWling af fhW 3cfihW NWgfdSl Bainf 5lSmbWV 5anhWdfWdTable 2.3: Possible Combination of ANPC Switching Statesgtuty bumy Uwtivy gwitwhys cutput Voltugyd S1,S2,S+ +ercD+1 S2,S5 DD+2 S1,S3,S+ DD−1 S3,S+ DD−2 S2,S4,S5 Db S3,S4,S5 −erccomponent tolerances and requires a means of balancing them.FBFBF aoxulution gtrutygiysGiven the increased number of states in the ANPC topology, several modulation techniqueshave been proposed. In [11] three modulation strategies are presented: two relatively similarto the NPC modulations containing two separate carriers for positive and negative half-cyclesand one with two phase shifted carriers covering the entire cycle shown in Fig. 2.7. For thisthesis the third modulation is considered since it leads to the best loss distribution and alsoresults in a natural doubling of the output switching frequency.With the selected modulation strategy, the switches must be driven as shown in Fig. 2.8.Next in the analysis it is necessary to identify the duty cycle of each component. Relating thecomponent utilization to the operating states greatly assists in determining each individualduty cycle. Take the case of a switching cycle in the positive portion of the reference signal,with the selected modulation the total duty cycle is split between three operating state and(2.9) must hold true.2sP + 2sO+1 + 2sO+2= 1 (2.9)182.2. MaVWling af fhW 3cfihW NWgfdSl Bainf 5lSmbWV 5anhWdfWd0 1 2 3 4 5 6−1−0.8−0.6−0.4−0.200.20.40.60.81Figure 2.7: Modulation Strategies for ANPC: Sinusoidal PWMONONONS1S2S3S4S5S6S1S2S3S4S5S6ON ONONONVout VoutVdc/2 0-Vdc/2 0VRefVRefP N NP02+01+01+02-01-01-Figure 2.8: ANPC Driving Signals using Sinusoidal PWM192.2. MaVWling af fhW 3cfihW NWgfdSl Bainf 5lSmbWV 5anhWdfWdConsidering that the duty cycle of the positive operating state is directly proportionalto the level of the reference signal and that the amount of time spent in each zero state isidentical for a given reference level, the state duty cycles for the positive half-cycle are foundto be:sP =Msin(!) (2.10)sO+1 = sO+2=M2(1− sin(!)) (2.11)With the same reasoning the duty cycles of states of the negative half-cycles are found.sN = −Msin(!) (2.12)sO−1 = sO−2=M2(1 + sin(!)) (2.13)For each device the duty cycle is determined based on the states in which the componentis conducting. For instance switch b1 is active during P and O+2 states, but only conductsduring P . Fig. 2.9 shows the states in which the devices conduct. With these considerationsthe duty cycle of all components are found.202.2. MaVWling af fhW 3cfihW NWgfdSl Bainf 5lSmbWV 5anhWdfWdsa1 =8>><>>:sP =Msin(!) 0 ≤ ! ≤ 0  ≤ ! ≤ 2sa2 =8>><>>:sP + sO+1 =M2(1 + sin(!)) 0 ≤ ! ≤ sO−2 =M2(1 + sin(!))  ≤ ! ≤ 2sa3 =8>><>>:sO+2 =M2(1− sin(!)) 0 ≤ ! ≤ sN + sO−1 =M2(1− sin(!))  ≤ ! ≤ 2sa4 =8>><>>:0 0 ≤ ! ≤ sN = −Msin(!)  ≤ ! ≤ 2sa5 =8>><>>:sO+1 =M2(1− sin(!)) 0 ≤ ! ≤ sO−2 =M2(1 + sin(!))  ≤ ! ≤ 2sa+ =8>><>>:sO+2 =M2(1− sin(!)) 0 ≤ ! ≤ sO−1 =M2(1 + sin(!))  ≤ ! ≤ 2(2.14)FBFBG Wonxuwtion unx gwitwhing LossysTo find the average and RMS currents in each device of the ANPC converter, (2.3) and (2.4)are used with the duty cycles defined in (2.14).Once again splitting switches b1 to b+ into transistors c1 to c+ with anti-parallel diodesS1 to S+, the currents are individually calculated:Ib1Iovu =12·∫ M · sin(!) · ioc · s!=M · Io4· [( − ) · cos() + sin()](2.15)212.2. MaVWling af fhW 3cfihW NWgfdSl Bainf 5lSmbWV 5anhWdfWdS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphS1Vdc+-Vdc+-S5S6S2S3S4NiphPPNN0 00 00 00 01+2+1+2+1 2- -1 2- -Figure 2.9: Conducting Devices on the ANPC Converter222.2. MaVWling af fhW 3cfihW NWgfdSl Bainf 5lSmbWV 5anhWdfWdI2b1IRMa =12·∫ M · sin(!) · i2oc · s!=M · I2o12· [3 + 4 · cos() + cos(2)](2.16)IR1Iovu =12·(∫ 0M2· (1 + sin(!)) · ioc · s! +∫ 2M2· (1 + sin(!)) · ioc · s!)=M · Io4· [cos()− sin()](2.17)I2R1IRMa =12·(∫ 0M2· (1 + sin(!)) · i2oc · s! +∫ 2M2· (1 + sin(!)) · i2oc · s!)=M · I2o12· [3− 4cos() + cos(2)](2.18)These calculations are extended to all devices. The results are listed in table 2.2.Table 2.4: Device Currents in ANPC Using SPWMDyviwy Uvyrugy Wurrynt (fag Wurrynt)2c1; c4M ·Io4 · o( − )cos() + sin()] M ·I2o12 · oG + Hcos() + cos(F)]c2; c3M ·Io8 · oH + cos()] M ·I2o24 · oG + Lcos()]c5; c+M ·Io8 · o(F − )cos() + H− Fsin()] M ·I2o24 · oG − 6− Fcos(F)]S1; S4M ·Io4 · ocos()− sin()] M ·I2o12 · oG− Hcos() + cos(F)]S2; S3M ·Io8 o( +  − F) · cos( − F− sin()] M ·I2o48 oG(E−  +  + cos() · (−H + sin())) + cos(F)]S5; S+M ·Io8 · oH− ( + F)cos()− Fsin()] M ·I2o24 · oG − 6− Fcos()]To determine the switching losses on each device of the ANPC converter, a commutationanalysis similar to the NPC was performed. Like the NPC, the commutations during thepositive and negative cycles are symmetrical with respect to the switch pairs (outer, innerand clamping). Since the modulation used relies on more states, it is important to evaluateeach transition.232.3. SWmicanVgcfad LaeeWe MaVWlDuring the positive half cycle, the converter transitions between states P , 0+1 , and 0+2 withno transition between zero states. In the commutations between P and 0+1 , devices c1 and c5switch in a complimentary manner. Based on the polarities of eoc and ioc, and consequentlythe current flow, it is possible to determine that c1 and S5 respectively experience switchinglosses and reverse recovery losses when both ac parameters present the same polarity. Whenthe polarity is reversed the losses are incurred in S1 and c5. For the case of commutationsbetween P and 0+2 , the switching devices are c2 and c3. Analyzing the switching behaviour,it is noticeable that c2 and S3 suffer losses when eoc and ioc are in-phase, whereas S2 and c3are stressed when the current flow changes direction. Figure 2.10 shows the commutationson the positive half-cycle of the ANPC.From the analysis presented, the switching losses can be calculated based on the operatingpower factor. It is important to notice that due to the additional zero states, the stresseddevices only experience conduction losses at every other commutation consequently halvingthe losses on a given device and improving the loss distribution.FBG gymiwonxuwtor Lossys aoxylModern semiconductor technologies have allowed switch-mode power supplies to perform at amuch greater order of efficiency relative to non-switching counterparts, while also improvingpower quality. These enhancements require careful analysis of the converter and its operation,as well as deep knowledge of semiconductor technologies.When it comes to semiconductor selection, the enormous number of options may over-whelm inexperienced designers. Often designers will rely on rules-of-thumb to determinethe most appropriate semiconductor technology. In Fig. 2.11 the most adequate operatingconditions for MOSFETs and IGBTs is shown [26]. These rules serve as a starting point inthe selection process, but may not be ideal in every situation. Also as shown in the figure,242.3. SWmicanVgcfad LaeeWe MaVWlT1T5D1P PicondVblockSwitchingLosses01+D5Reverse Recovery vLossesT1T5D1P PVblock01+D5Reverse Recovery LossesicondSwitchingLossesT2T3D2P PicondVblockSwitchingLosses01-D3Reverse Recovery vLossesT1T5D1P PVblock01-D5Reverse Recovery LossesicondSwitchingLosses(a) (b)(c) (d)Figure 2.10: ANPC Switching Losses: (a) P to 0+1 when eoc and ioc in-phase, (b) P to 0+1when eoc and ioc out-of-phase, (c) P to 0+2 when eoc and ioc in-phase, (d) P to 0+2 when eocand ioc out-of-phasethere is a gray area in which the selection is not obvious.For the grid tie inverter of this thesis, the semiconductor selection will be highly influencedby the resulting losses. Losses in power converters are split into three types: conduction,switching and leakage losses. Leakage losses are generally small and can therefore be ne-glected.252.3. SWmicanVgcfad LaeeWe MaVWl200400600800100012001 10 1000100MOSFETMOSFETIGBTIGBT?fsw(kHz)VS(V)Figure 2.11: IGBT and MOSFET Utilization SpectrumFBGBE acgFEh LossysConduction losses in power MOSFETs arise from their on-resistance RRaon. This resistanceis generally provided in the datasheet, along with plots that allows designers to extrapolateand find its value at various operating conditions. With the resistance and the current valuescalculated previously, conduction losses can be calculated with the equation below:Pconr = RRaon · i2RMa (2.19)Switching losses are caused by the turn-on and turn-off behaviour of the MOSFET [27–29]. Equation 2.20 calculates the switching losses based on the turn-on and turn-off energies,TON and TOTT , and the switching frequency fswPsw = (TON + TOTT ) · fsw (2.20)A widely used approximation to calculate switching energies use the rising and fallingtimes provided in MOSFET datasheets. Reverse recovery in the diodes delay the turn-onprocedure, therefore also impact TON .262.3. SWmicanVgcfad LaeeWe MaVWlTON =12· eRaIplock · iovu · (trw + ttv) +Qrr · eRaIplockwnu (2.21)TOTT =12· eRaIplock · iovu · (ttw + trv) (2.22)In (2.21) and (2.22), trw and ttw are the current rise and fall times, trv and ttv the riseand fall times for the voltage, and QRR the reverse recovery charge of the anti-parallel diode.These values are provided by manufacturers.FBGBF IGVh LossysIGBTs can be treated as a MOSFET driving a BJT in a darlington configuration [27, 30].This combination results in a higher power limit compared to a MOSFET and is easier todrive than a BJT. Conduction losses in IGBTs are similar to BJTs, given by a diode-likevoltage drop and an on-resistance. The resulting conduction losses are given by the followingequation:Pconr = eon · iovu +Rc · i2RMa (2.23)Unlike MOSFETs, the on-resistance is not typically provided directly on the IGBTdatasheet as it is severely affected by the operating conditions. Manufacturers normallyprovide a plot of typical output conditions that relate the collector current iC to the collectoremitter voltage eCS. The slope of this plot will provide the on-resistance at a given operatingpoint by as shown in (2.24).Rc =∆eCS∆iC(2.24)To calculate switching losses, the turn-on and turn-off energies must be obtained from272.4. InVgcfad MaVWlthe IGBT datasheet and then be substituted into (2.25).Psw = (TON + TOTT ) · fsw (2.25)FBGBG Dioxy LossysConduction losses in power diodes are given by their forward voltage drop et and resistanceRr [31] as shown in (2.26). The resistance can normally be obtained from the diode forwardvoltage plot using (2.27) around the desired operating point.Pconr = et · iovu +Rr · i2RMa (2.26)Rc =∆et∆it(2.27)Switching losses in power diodes are mostly due to turn-on energy, given by its reverserecovery properties.Psw = Ton · fsw = 14·Qrr · eRIplockwnu (2.28)FB4 Inxuwtor aoxylPower converters generally require careful design of magnetic components as they have sig-nificant impact on efficiency, ripple, harmonic content and power density. For the grid tieinverter designed in this thesis, an inductor is used to interface the converter with the grid.The minimum inductance required is given by (2.29) as demonstrated in [25]:Lmwn =erc4 · ILIrwppls ·√48 · fsw√32M2 − 4√3M3 +98M4 (2.29)282.5. SgmmSdkwhere fsw is the switching frequency, erc is the total bus voltage across both capacitors,M is the modulation index and ILIrwppls is current ripple on the inductor which is obtainedfrom the THD requirements:ILIrwppls = Ioc · cWS√3(2.30)Losses in the inductor can be split into two types: core and copper losses. Core lossesare caused by hysteresis and eddy current losses. These losses hinge on the core selectedand its material properties. Copper losses are caused by the resistance of the wire used toconstruct the inductor winding. Given the dependency of the inductor losses to its physicalconstruction, which in turn present uncountable alternatives, the inductor design may betreated as an optimization of its own. For the purpose of this thesis, only the inductancemagnitude will be accounted for.FBI gummuryIn this chapter a mathematical model was developed based on relevant characteristics of amultilevel converter. Two topologies were considered, the NPC and ANPC, and their operat-ing states based on a selected modulation strategy were introduced. From those the currentflow through the all devices of the converter were analyzed which allowed the conductionand switching losses for each device to be calculated. A description of the semiconductortechnologies was presented with their source of losses and means to quantify them. Lastlya model for determining the minimum required inductance, based on the AC current andtarget THD was introduced.29Whuptyr Gcptimizution drovlym gtruwturyIn order to obtain meaningful results in any optimization problem, it is fundamental to havea well defined structure. This chapter presents an optimization scheme used to optimizea multilevel converter. As the first step in optimization, the objective must be defined.Considering complex systems generally have multiple requirements, a multi-objective functionis adopted. Next the variables that impact the objective function are identified along withtheir impact on the system. As the final section of this chapter, different optimizationscenarios considered for the multilevel converter are introduced.GBE cvjywtivy FunwtionsIn an optimization process, the objective function is the parameter or combination thereofthat is getting minimized or maximized. Simple optimization problems have a single opti-mization function, but complex problems normally present multiple functions that are re-quired to optimize. Given the nature of power electronics systems, many parameters canand should be optimized. Converter requirements and specifications normally dictate whichparameters are of higher importance. Nevertheless the optimization function must be care-fully selected to obtain meaningful results. For instance if only efficiency is accounted for itis likely the optimized converter would have oversized and expensive components while usingthe lowest possible switching frequency. For the multilevel converter optimized in this thesis,the objective function considers the four parameters covered in this section.303.1. ATjWcfihW FgncfianeGBEBE EffiwiynwyAs desired in any power electronic converter, the overall system efficiency needs to be maxi-mized. Efficiency directly impacts the thermal characteristics of the converter. Low efficiencyconverters require large heatsinks and active cooling, such as fans. These additions increasethe cost and the overall size of the converter i.e. decreasing the power density. From areliability perspective, a low efficiency converter is more likely to reach component thermalbreakdown. Fans and active cooling devices are also highly failure prone. In addition to theseissues, high efficiency power electronics are cheaper to operate from energy consumption view,consequently being of great value to consumers.Efficiency is traditionally calculated with (3.1). =PoutPwn(3.1)In the optimization problem presented, the equation is rearranged as shown in (3.2).Losses are calculated using equations (2.19) to (2.28). =PoutPout + Lossts(3.2)GBEBF Loss DistrivutionConverters with a large number of semiconductors are bound to experience an uneven distri-bution of losses. Even in a high efficiency converter, if the losses are not well distributed thepower density will be restricted. Components experiencing most of the losses require morecooling and are more likely to break down due to thermal stress. It is not surprising thatpoor loss distribution has similar side effects as low efficiency: lower power density, highercost, lower reliability.To quantify the loss distribution among the semiconductors, first the losses in each com-313.1. ATjWcfihW Fgncfianeponent is calculated with (2.19) to (2.28). For the purpose of this thesis, three semiconductortypes are considered: IGBT, MOSFET and diode. IGBT and MOSFET modules used inthis optimization contain a body diode, hence its losses must be considered and accountedfor. As a result the losses on switch bi are calculated with (3.3). In the equation Psw andPconrT are the switching and conduction losses of the transistors, while PconrD and Prr arethe conduction and reverse recovery losses of the diodes.Plossi =8>><>>:Psw + PconrT + PconrD + Prr IGBT or MOSFETPconrD + Prr Diode(3.3)As the next step in quantifying the distribution, the average semiconductor losses arecalculated with (3.4).Ploss =∑+w21(Plossi)6(3.4)Finally the standard deviation, , is calculated using (3.5). To result in a more equaldistribution, the optimization process seeks to minimize this value. =vuut +∑w21(Plossi − Ploss)2 (3.5)GBEBG Filtyr InxuwtunwySizing the inductor for the multilevel converter is a task that impacts several converterperformance aspects. As mentioned in Chapter 2, efficiency is affected by inductor core andcopper losses which can be treated as an optimization of its own and is not considered inthis thesis. Power quality is directly affected by the inductance as the inductor regulatesthe total harmonic distortion (THD). The physical size of the inductor is determined by theactual inductance and the selected construction, and is a major factor on the power density323.1. ATjWcfihW Fgncfianeand cost of the converter.In the optimization presented, the objective function seeks to minimize the inductance.Equation (3.6), introduced in Chapter 2, is used to calculate the minimum required induc-tance for a given load condition, THD requirement and switching frequency. The THD hereis constant and set to 5%, a commonly adopted value in many industrial applications.Lmwn =erc4 · ILIrwppls ·√48 · fsw√32M2 − 4√3M3 +98M4 (3.6)GBEB4 gymiwonxuwtor WostWhen designing a practical converter designers must account for the overall cost of the billof materials. Cost of the converter must be minimized in order to remain competitive.For the optimization presented here, the focus lays on the semiconductors costs. All othercosts associated with the bill of materials are indirectly affected by the objective functionsintroduced previously. For example the cost of heatsinks and cooling is linked to efficiencyand loss distribution, while the inductor cost is proportional to the inductance itself.Component prices vary considerably with volume and supplier, which is in essence asupply chain problem and therefore not in the scope of this thesis. For consistency pur-poses all semiconductor were obtained from the same supplier and purchased in low volume.Quantifying the cost is a simple matter of adding the price of each component as per (3.7).Rost =+∑w21(costw) (3.7)GBEBI kyightyx cvjywtivy FunwtionTo combine the objective functions presented in this section, a weight system is used. Due tomagnitude differences, all four objective functions are normalized prior to their addition. The333.2. AbfimilSfian VSdiSTlWenormalization is done based on the optimum value of each individual objective function. Forexample, the optimum efficiency opt is the best efficiency achieved when optimizing strictlyfor efficiency. Objective functions being maximized are added together as shown in (3.8). Inthe equation,fS,fR,fI andfC are the weights for efficiency, loss distribution, inductanceand cost respectively. These weights can be used by the designer to assert priorities basedon the converter requirements.Objtctivt =fS| − opt|opt+fR| − opt|opt+fI|Lmwn − LmwnIopt|LmwnIopt+fC|Rost− Rostopt|Rostopt(3.8)GBF cptimizution juriuvlysAn extensive set of parameters impact the performance and cost of a power electronics con-verter, which in turn determine its success in a highly competitive market. Consequentlydesigners must carefully analyze all these variables usually with very restrictive time frames.It is seldom that a decision regarding a given parameter has impact on only a single perfor-mance aspect, in fact the common occurrence that a single variable has a positive impacton a characteristic of the converter while degrading others. A compromise must then beachieved to obtain the most optimum combination of parameters that aligns well with con-verter requirements. This section introduces the parameters that drive the optimization ofthe multilevel converter under study, a representation of these variables are shown in Fig. 3.1.Their relevance is explained along with their impact on the previously introduced objectivefunctions. The operating conditions shown in Table 3.1 were used for the analysis.343.2. AbfimilSfian VSdiSTlWeTable 3.1: Operating Conditionsdurumytyr Vuluyeoc EFD ermserc GID eM DBM6MKLops D to EDDD e PLphpstPF AE to ES1S5S6S2S3S4i phfswMOSFET IGBTS1 S4-MOSFET IGBT DiodeANPC NPCS5 S6-Load (VA)PFFigure 3.1: Representation of the Design VariablesGBFBE cpyruting WonxitionsOperating conditions are fundamental parameters that drive the design of any power elec-tronics converter. It is common industry practice to design converters for a single operatingpoint where the converter is most likely to operate, and converter performance tends to de-grade and even require de-rating when operating at different conditions. For the optimizationperformed in this thesis, two operating conditions will be treated as variables: load (regardedas apparent power), and power factor (PF). Bearing in mind that a converter may not alwaysoperate at a fixed operating condition, it is important to understand and design the converterfor the most probable operating range instead of a single point. Other operating conditionparameters such as input voltage are treated as constants in the optimization in this thesis,as those values generally only vary under abnormal conditions and often the converter is353.2. AbfimilSfian VSdiSTlWedisabled as a protection mechanism.LouxAlthough not a parameter in which designers have freedom to adjust, load has considerableimpact on the design of a power converter. Regardless of whether the converter operates atfull load during its entire lifetime, all components must be rated to withstand the maximumpower with enough safety margins. In applications in which power fluctuations is experienced,it is very desirable to optimize the design around a load range. It is very important to statethat although the multilevel converter may be designed around a range, reliability at fullload must not be compromised.To understand how loading conditions affect a converter, the objective functions must beanalyzed for various loads. In Fig. 3.2, it is noticeable that efficiency increases as deliveredpower approaches full load. This behaviour is expected and justified by the fact that alldevices were selected based on the full loading conditions and have best performance at thatpoint. Loss distribution worsens at higher loads for NPC topologies, as the uneven lossesbecome more pronounced as seen in Fig. 3.3. For ANPC shift in the distribution is not assevere, due to its balancing properties. Since inductance is calculated based on allowablecurrent ripple, which in turn are a percentage of the operating current, it is natural thatlower loads requires tighter regulation hence larger inductance, see Fig. 3.4.dowyr FuwtorTo take advantage of the bidirectional nature of the topologies selected, the converter shouldbe capable of operating as an inverter (PF = 1), a rectifier (PF = -1), or somewhere inbetween delivering active and reactive power. As with the load, power factor is dictated bymarket specifications and designers have no ability to adjust them. It is though important tounderstand the impact of power factor on the objective functions, and to be able to design363.2. AbfimilSfian VSdiSTlWe200 300 400 500 600 700 800 900 10000.960.9650.970.9750.980.985Load (W)E!ciency  NPC − IGBTNPC − MOSFETANPC − IGBTANPC − MOSFETFigure 3.2: Efficiency at Different Loads0246Loss Distribution  NPC − IGBTNPC − MOSFET200 300 400 500 600 700 800 900 1000246810Load (W)Loss Distribution x 103  ANPC − IGBTANPC − MOSFETFigure 3.3: Loss Distribution at Different Loadsfor a fixed or a range of power factors.Due to the symmetrical nature of the topology, very little difference is noted in efficiencywhen operating as an inverter or a rectifier with unity power factor. As the power factordecreases and reactive power begins to flow, a rapid drop in efficiency is noted and is shown in373.2. AbfimilSfian VSdiSTlWe200 300 400 500 600 700 800 900 100000.0020.0040.0060.0080.010.0120.014Load (W)Inductance (H)  NPCANPCFigure 3.4: Minimum Inductance at Different LoadsFig. 3.5. Among the causes of such behaviour are the fact that current begins to flow thoroughotherwise non-conducting body diodes and more devices begin to experience switching losses.For a more detailed loss analysis, refer back to Chapter 2.One well known characteristic of the NPC is the uneven loss distribution of losses, inparticular at boundary conditions (PF = 1 and PF = -1). It is well understood that aspower factor shifts, the concentration of the losses vary. When operating at as an inverter(PF = 1), the outer transistors are the most stressed devices of the converter. For rectifieroperation (PF = -1) the inner transistors suffer the most losses. Anywhere in between resultsin a better distribution, which is seen in Fig. 3.6. A similar trend occurs, but in much smallerscale, in the ANPC.Since the inductance is calculated based on the peak current only, power factor has noimpact on it.383.2. AbfimilSfian VSdiSTlWe0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.860.880.90.920.940.960.98Power FactorE!ciency  NPC − IGBTNPC − MOSFETANPC − IGBTANPC − MOSFETFigure 3.5: Efficiency at Different Power Factors0246Loss Distribution  NPC − IGBTNPC − MOSFET0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 102468Power FactorLoss Distribution x 103  ANPC − IGBTANPC − MOSFETFigure 3.6: Loss Distribution at Different Power FactorsGBFBF gwitwhing FryquynwyAdjusting the switching frequency of the power converter is a relatively simple task that ma-jorly affects performance. Since switching frequency impacts multiple aspects of the objectivefunction, it must be treated as a key variable of the optimization problem. As was previously393.2. AbfimilSfian VSdiSTlWe2 4 6 8 10 12 14 16 18 200.9650.970.9750.980.9850.99Switching Frequency (kHz)E!ciency  NPC − IGBTNPC − MOSFETANPC − IGBTANPC − MOSFETFigure 3.7: Efficiency at Different Switching Frequenciesmentioned, switching losses are directly proportional to the switching frequency. As a resultincreasing this variable causes an overall increase in the losses which in turn leads to worseefficiencies, as shown in Fig. 3.7. In any situation in which the losses are increased thedistribution becomes more pronounced, as result increasing the switching frequency worsensthe loss distribution. On the other hand, a positive impact of high switching frequenciesis the allowable reduction in the inductor size. At higher frenquencies the multilevel con-verter synthesizes an output current that better resembles a sine wave, decreasing the filterrequirements to achieve the target THD. This trend is shown in Fig. 3.8.GBFBG hopologyAmong the objectives of optimization presented in this thesis, the method seeks to aid powerelectronics engineers in the selection of a multilevel topology. Two topologies are considered:the Neutral Point Clamped (NPC) and the Active NPC (ANPC), which is formed whenthe clamping diodes are replaced with active switches. A known characteristic of the twotopologies is the fact that at a given operating point, both present similar efficiencies as403.2. AbfimilSfian VSdiSTlWe2 4 6 8 10 12 14 16 18 2000.0050.010.0150.020.025Switching Frequency (kHz)Inductance (H)  NPCANPCFigure 3.8: Minimum Inductance at Different Switching Frequenciesshown in Figs. 3.2, 3.5 and 3.7. More important the efficiency follows the same trends forboth topologies.Considering the ANPC was initially developed as a means to balance the losses in theNPC converter, it is not surprising the ANPC presents a much lower distribution as shownin 3.3 and 3.6. This enhancement is largely due to the modulation strategy adopted for theANPC, which takes advantage of the alternative zero states introduced by it. In Chapter 2 itwas also mentioned that the selected modulation leads to a natural doubling of the effectiveswitching frequency. As consequence, the ANPC topology requires lower inductance thanthe NPC, see Figs. 3.4 and 3.8.A drawback of the ANPC is its elevated cost. Constructing the ANPC requires replacingthe two clamping diodes with either IGBTs and MOSFETs, which are normally considerablypricier and require additional drivers.413.2. AbfimilSfian VSdiSTlWeGBFB4 gymiwonxuwtorsSelecting semiconductors for power electronics can be an overwhelming task, given the largenumber of options suitable for a desired application. Designers must be capable of selectingnot only an appropriate semiconductor technology but also the best option among them.Given the topologies in this study the switch selection is split into three pairs: outer switches(b1 and b4), inner switches (b2 and b3) and clamping switches (b5 and b+). The pairings arejustified by the identical stresses on each device of the pair.For the switch types, three switch technologies were considered: IGBTs, MOSFETs anddiodes. In the optimization exercise, 6 IGBTs, 6 MOSFETs and 4 diodes were considered.The components are listed in Table 3.2. It is important to understand the main differencesamong the considered options to understand their benefits when optimizing the converter.When compared to MOSFETs, IGBTs tend to experience lower switching losses associ-ated with sd Lst and therefore are better in high voltage applications. Due to the fact thatIGBTs present a fixed voltage drop and an on-resistance when current flows through thetransistor, conduction losses are normally higher than MOSFETs. In a hard-switching envi-ronment such as the one in the multilevel converter of this thesis, MOSFETs experience highswitching losses, largely caused by the poor reverse recovery properties of their body diodes.Newer MOSFET devices have decreased their on-resistances, leading to much lower conduc-tion losses. Figures 3.2 to 3.8 show some comparisons between converters built with IGBTsand converters built with MOSFETs. For the clamping switches, diodes are also a consideredalternative. An obvious benefit of the diodes, is their much lower cost compared to activeswitches. Compared to the body diodes of IGBTs and MOSFETs, standalone diodes tend tohave better conduction and reverse recovery properties. As drawbacks, diodes are unidirec-tional devices, which limits the operating states of the converter, and their conduction lossesare considerably higher when compared to IGBTs and MOSFETs.423.3. AbfimilSfian SfSgWeAll semiconductors considered here are traditional Si components that are commerciallyavailable and can be obtained from several suppliers. Up-and-coming technologies such asGalium Nitride (GaN) and Silicon Carbide (SiC) show potential to push the limits of powerelectronics to higher level, but these technologies are in very early stages, are extremelycostly, and their potential issues not well known. For practical reasons and the industrialorientation of this thesis, these new devices are not considered.Irrespective of the technology used, semiconductor selection impacts the efficiency of theconverter since the device characteristics determine the switching and conduction losses. Forthe same reason, loss distribution is also affected by the semiconductors, as the imbalancebecomes more pronounced in converters with higher losses. From the variables accounted forin this optimization, only semiconductor selection drives the cost. The switch selection hasno significant impact on the inductance.GBG cptimizution gtugysWhen designing a power converter, it is common practice to choose a single operating con-dition and optimize the design around it. Most commonly, the selected operating conditionis at full load. Consequently the converter excels at full load, but often the performance isseriously degraded when operating under different conditions. This traditional approach isperfectly acceptable when designing a converter that always operates at full load, which isnot always the case.Given the possible operational nature of the multilevel converter, the optimization carriedout in this thesis accounts for operating ranges instead of a single operating point. In practicethe resulting design may not outperform a single point design at that given point, but itpresents a more balanced performance around the desired operating point. This strategyfollows the line of the optimization proposed in [21].433.3. AbfimilSfian SfSgWeTable 3.2: Considered SemiconductorsDyviwy hypy aunuzuwturyr durt bumvyr Wost (WUD)][VhE Ulphu & cmygu UcKIDV6DDE 86BG6][VhF Fuirwhild F[HGDb6DLgDhi 8EIBGH][VhG ghaiwroylywtroniws gh[WHIHF6DWD] 86BFK][VhH ]ntyrnutionul fywtiyr ]f[dGDV6DKD 8MBM6][VhI ghaiwroylywtroniws gh[WGIHF6DWD 8IBKD][Vh6 Fuirwhild F[HHDb6DgFDhiAFDLI 8KB6IacgFEhE Ulphu & cmygu UcKHFg6DL 8LBGFacgFEhF Fuirwhild FWHDKDb6DE 8EEBMLacgFEhG Fuirwhild FWHDKFb6DF 8MBHEacgFEhH Fuirwhild FWHHKb6DbF 8FGBIKacgFEhI ]nnyon ]dW6DfDMMW6 8LBMEacgFEh6 ghaiwroylywtroniws ghWILb6DDaFU[ 8EDBLEDiodyE Fuirwhild FFdFGDiU6Dg 8EBKIDiodyF Fuirwhild FFdGDg6Dghi 8FBGGDiodyG Vishuy VgAEhiGDD6FdAaG 8FBIHDiodyH Fuirwhild ]gLMfGD6DdF 8HBHDGBGBE juriuvly cutput dowyrA variety of power electronics applications deal with variable loading conditions. For examplephotovoltaic chargers that operate around the maximum power point of solar panels, thatchanges considerably throughout the day affecting the output conditions.The multilevel converter proposed in this thesis is designed as a grid-tie inverter integrat-ing the utility grid with a DC link joining renewable energy sources. Therefore it is expectedthat the output power will vary considerably during the converter operation, making it ap-pealing to design for of a range of probable output power instead of at single condition.443.4. SgmmSdkGBGBF juriuvly dowyr FuwtorTo take advantage of the bidirectionality of the NPC and ANPC converters, they must becapable of operating strictly as an inverter (PF=1) or as a rectifier (PF=-1). To makethe operation of the converter even more flexible, it is desirable to operate at other powerfactor levels while delivering or absorbing reactive power. This practice is common in grid-tieinverters operating as active power filters, which improves the power quality on the grid side.GBGBG juriuvly cutput dowyr unx dowyr FuwtorFor a situation in which the multilevel converter operates as an inverter (PF=1) providingactive power to the grid, as a rectifier (PF=-1) powering loads within a microgrid, all whileimproving power quality by controlling reactive power (-1<PF<1), would require a convertercapable of operating well under a variable output power range and different power factors.The resulting design targets a balanced performance across the entire range.GBGB4 cptimizution Vusyx on itilizution drolyRegardless of the application, converters tend to operate under some conditions more thanothers during its lifetime. Whether with variable output power, power factor or both, it isvery improbable that the converter would operate evenly across the entire operating range.To account for this, the last stage of the optimization performed in this thesis accounts forthe most probabley operating conditions based on the expected utilization profile.GB4 gummuryThis chapter presented the scheme adopted for the multilevel converter optimization. Fourobjective functions deemed relevant to achieve competitive performance were identified, along453.4. SgmmSdkwith their relation to the models developed in Chapter 2. A set of variables, includingoperating conditions, were considered due to their potential impact on the system. The effectsof these variables on the objective functions were carefully analyzed and explained. Lastlythe optimization stages considered in this thesis were presented, seeking to accommodate adiverse range of potential applications for the converter being designed.46Whuptyr 4Efipyrimyntul julixution unx fysultsIn the previous chapters, models for two multilevel converter topologies were developed topredict their performance under a fixed set of conditions, and a optimization scheme that re-lies on the models was introduced to obtain the best performing converter based on predefineddesign priorities. In this chapter a set of experimental work is introduced to demonstratethe accuracy of the model developed, and optimization results are shown for different sets ofweighting scheme. The designed converter had as target operating parameters as displayedin Table 4.1, unless otherwise specified.4BE Efipyrimyntul gytupTo carry out experimental work to validate the models presented in Chapter 2 and confirmthe results of the optimizations as introduced earlier in Chapter 3, the setup shown in Fig.4.1 was used. The grid simulator used allows for currents to flow in any power factor range,meaning it can act as either a current source (PF <0) or a sink (PF M0). To simulate theDC link, a 600 V DC Source with 50 A rating was used. In parallel with the DC Source,a 5kW DC electronic load was placed. This configuration allows bidirectional power flow:when operating as an inverter the DC source provides power to the system and the gridsimulator absorbs it, when operating as a rectifier the grid simulator injects power into thesystem which flows into the DC load. To interface the grid simulator with the rest of thesystem, an 8 mH inductor was selected.474.2. MaVWl VSliVSfianTable 4.1: Operating Conditionsdurumytyr Vuluyeoc EFD ermserc GID eM DBM6MKLops D to EDDD e PLphpstPF AE to EModulation signals were generated with a Texas Instruments (TI) microcontroller, theF28335 of the Delfino series. The modulation index is determined based on voltages andcurrent readings and an output power setpoint, set via JTAG communication and a CodeComposer Studio interface.Three hardware platforms developed in-house completed the test setup. As the powerstage, a three-level platform with six switches based on the ANPC was built. TO-247 wasselected as packaging for the switches (IGBTs and MOSFETs), which can also be populatedwith TO-220 diodes. This platform may be set as either an ANPC with 6 active switchesor an NPC by placing diode as the clamping devices, the topologies are shown in Fig. 4.2.To measure the voltage and current signals another hardware platform was used, adjusted toobtain optimum resolution of the voltage and current amplitudes targeted. Lastly a platformfor the microcontroller with signal conditioning layers housed the F28335. The assembledplatform is shown in Fig. 4.3.4BF aoxyl julixutionAs a first step to evaluate the work of this thesis, it is critical to cross check the expectedresults of the models presented in Chapter 2 with the results obtained using the experimentalplatform.484.2. MaVWl VSliVSfianGridSimulatorF28335Three-Level ConverterSensingPlatformDC SourceDC LoadJTAGDriver SignalsADCiacvacvdc,topvdc,bottom+-+-vaciacvdc,topvdc,bottom+-Figure 4.1: Experimental SetupS1Vdc+-Vdc+-D5D6S2S3S4Niph(u)S1Vdc+-Vdc+-S5S6S2S3S4Niph(v)Figure 4.2: Topologies of the Experimental Platform (a) NPC and (b) ANPC4BFBE Effiwiynwy julixutionTo ensure the efficiency calculated with the model developed in Chapter 2 is accurate, aset of experiments was carried out. The accuracy was verified for various possible operatingconditions with different configurations of the multilevel converter. Figure 4.4 plots thetheoretical efficiency with measured efficiencies at two switching frequencies in both inverterand rectifier operation. A small difference in the values is noticeable, likely due to parameter494.2. MaVWl VSliVSfianFigure 4.3: Hardware Platform300 400 500 600 700 800 900 100095.59696.59797.59898.5Load (W)E!ciency (%)  IGBT MeasuredIGBT TheoreticalMOSFET MeasuredMOSFET Theoretical(u)300 400 500 600 700 800 900 10009696.59797.59898.5Load (W)E!ciency (%)  IGBT MeasuredIGBT TheoreticalMOSFET MeasuredMOSFET Theoretical(v)Figure 4.4: Theoretical and Measured Efficiency: (a) 18 kHz with PF = 1 and (b) 9 kHzwith PF = -1extrapolation from semiconductors’ datasheets and simplifications assumed in the model.More relevant to the optimization than the exact number are the trends and behaviourof the converter under different conditions, an aspect in which the model closely matchesmeasurements.504.2. MaVWl VSliVSfian4BFBF Loss Distrivution julixutionA target of the optimization presented here is to even out the distribution of losses, as anindirect way of improving power density. The models proposed calculate the losses at eachswitch pair (outer, inner and clamping switches). Given the difficulty of measuring the lossesof each individual component, heat dissipation is used as a means to determine the modelaccuracy.To ensure a safe work environment, a protection shield is used around the setup whenperforming high power tests. This shield does not allow thermal captures of componentsinside of it to be taken, and removing it at target operating conditions would lead to un-safe working conditions. For this reason the operating conditions were changed to 60 ermsand 300 f which allows the accuracy of the models to be validated while maintaining safeworking conditions. At this power level, the fans which cool components and prevent ther-mal breakdown can be safely removed, which results in more realistic results, and excludestemperature gradients caused by the location of the fansThe loss distribution is significantly affected by the power factor. Starting with NPC, itis possible to notice that when operating with PF = 1, the losses tend to concentrate on theouter devices. When the power flow is reversed and the NPC operates with PF = -1, the innerswitches become the most stressed devices. The location of the losses calculated with themodel and the thermal captures are closely related as show in Figs. 4.5 and 4.6. Switching tothe ANPC topology, it is expected that the distribution gets more even. This case is visiblein Fig. 4.7. In all figures, point sp1 measures the temperature of one of the outer switches,sp2 one of the inner switches and sp3 one of the clamping devices. It is important to stateonce again that for the optimization, it is more critical to have more accurate trends thanexact numbers.514.3. AbfimilSfian RWeglfeTout Dout Tin Din Dclamp01234567Losses (W)  Conduction LossesSwitching Losses(u) (v)Figure 4.5: Loss Distribution For NPC with MOSFET at PF = 1: (a) Calculated Losses perDevice and (b) Thermal CaptureTout Dout Tin Din Dclamp01234567Losses (W)  Conduction LossesSwitching Losses(u) (v)Figure 4.6: Loss Distribution For NPC with MOSFET at PF = -1: (a) Calculated Lossesper Device and (b) Thermal Capture4BG cptimizution fysultsWith a validated model, a search algorithm was used to optimize the multilevel converterconsidering various design requirements. The optimization scheme proposed in this thesis,provides designers with the ability to prioritize performance characteristics based on systemrequirements. This is achieved by setting the components fS, fR, fI and fC of the524.3. AbfimilSfian RWeglfeTout Dout Tin Din Tclamp Dclamp01234567Losses (W)  Conduction LossesSwitching Losses(u) (v)Figure 4.7: Loss Distribution For ANPC with MOSFET at PF = 1: (a) Calculated Lossesper Device and (b) Thermal Captureobjective function represented by (4.1). All cases here were based on the operating conditionoutlined in Table 4.1. Power factor is restricted to 1 and -1, hence operating as an inverteror a rectifier with active power only. Instead of optimizing for a single loading condition,the converters were optimized for two load ranges, a wide range from 25% to full load and anarrow range from 75% to full load.Objtctivt =fS| − opt|opt+fR| − opt|opt+fI|Lmwn − LmwnIopt|LmwnIopt+fC|Rost− Rostopt|Rostopt(4.1)4BGBE gingly cvjywtivy FunwtionThe first step in the optimization is to identify the optimum points for each individual ob-jective function, which is achieved by setting a weight of one to the target objective function,and zero to all others.534.3. AbfimilSfian RWeglfeTable 4.2: Optimization for Efficiency OnlyP (W) PF Sfout Sfwn Sfclomp fsw(Hz) L(mH) mox  Cost(8)FIDAEDDD E acgFEhG acgFEhH DiodyG EDDD MGBFK DBMM DBGIM KEBDHKIDAEDDD E acgFEhH acgFEhH DiodyG EDDD GEBDM DBMM DBF6M MMBG6FIDAEDDD AE ][VhH ][VhH acgFEhH EDDD H6B6H DBML DBDDH L6BMLKIDAEDDD AE acgFEhH acgFEhH acgFEhH EDDD EIBIH DBML DBDDI EHEBHFEffiwiynwy cptimizutionBeginning with the optimization for efficiency only, weight fS is set to one while fR, fIand fC are set to zero. The results obtained with the optimization algorithm are shownin Table 4.2. From the results obtained, three aspects are very important to highlight.First the switching frequency is always the lowest allowable at 1000 Hz, regardless of theloading conditions. This is expected as the tool seeks to achieve the lowest possible switchinglosses. Another interesting factor is the dominance of MOSFET 4 in the results. This is thebest performing device and by far the most expensive. This device was purposely selectedto highlight the issue of optimizing for a single characteristic of the converter. Anotherinteresting characteristic to point out is the dominance of ANPC converters when operatingwith PF = -1. Under this condition, the body-diode of the active devices conduct currentwhich in turn alleviates the stress of switching devices, consequently lowering switching lossesmaking the utilization of active clamping switches more attractive.Loss Distrivution cptimizutionSetting fR to one and the remaining weights to zero, the converter that results in thebest distribution under various load ranges is found. Results are shown in Table 4.3. Themost interesting fact to point out from the results is the dominance of ANPC converter,which is expected since balanced distribution is the main benefit this topology brings. It is544.3. AbfimilSfian RWeglfeTable 4.3: Optimization for Loss Distribution OnlyP (W) PF Sfout Sfwn Sfclomp fsw(Hz) L(mH) mox  Cost(8)FIDAEDDD E acgFEhE acgFEhE acgFEhI FDDDD FBGF DBLL DBDMH IEBEDKIDAEDDD E acgFEh6 ][VhE acgFEh6 FDDDD DBKL DBMK DBDD6 IIBM6FIDAEDDD AE ][VhE ][VhG ][VhG FDDDD FBGF DBMK DBDHH GKBLDKIDAEDDD AE ][VhE ][VhG ][VhG FDDDD DBKL DBMK DBDGG GKBMLTable 4.4: Optimization for Inductance OnlyP (W) PF Sfout Sfwn Sfclomp fsw(Hz) L(mH) mox  Cost(8)FIDAEDDD E ][VhG ][VhF acgFEhG FDDDD FBGG DBM6 DBDDF 6FBDHKIDAEDDD E acgFEhF ][VhH acgFEhF FDDDD DBKL DBLI DBDHG 6KBLHFIDAEDDD AE ][Vh6 ][VhH acgFEhF FDDDD FBGG DBM6 DBEEE IMBELKIDAEDDD AE ][Vh6 ][VhG acgFEhH FDDDD DBKL DBMK DBDG KHBMLinteresting to point out though, that when optimizing for distribution only, often the resultingconverter will achieve the balance by increasing losses in some components, consequently theresulting converters use the maximum allowable switching frequency of 20 kHz and are notvery efficient.Inxuwtunwy cptimizutionProceeding to inductance optimization by setting only fI to one. Since the minimum re-quired inductance is only affected by the AC current, THD and switching frequency, it isnot surprising that the switching frequency is kept a maximum for all scenarios. With themodulation selected for the ANPC, a natural doubling of the switching frequency occurs,consequently all of the resulting converters used this topology. Regarding the load, the factthat the THD requirements limits the current ripple as a percentage its magnitude, lighterloads require tighter regulation, therefore needing a larger inductor.554.3. AbfimilSfian RWeglfeTable 4.5: Optimization for Cost OnlyP (W) PF Sfout Sfwn Sfclomp fsw(Hz) L(mH) mox  Cost(8)FIDAEDDD E ][VhI ][VhI DiodyE EDDD MGBFL DBM6 MBFD F6BGDKIDAEDDD E ][VhI ][VhI DiodyE EDDD GEBDM DBM6 MBFD F6BGDFIDAEDDD AE ][VhI ][VhI DiodyE EDDD MGBGD DBMK KBGK F6BGDKIDAEDDD AE ][VhI ][VhI DiodyE EDDD GEBDM DBMK KBGK F6BGDWost cptimizutionRunning the search algorithm with only fC set to one, results in a predictable outcome.Regardless of the load range or power factor, all of the optimum converters had the cheapestcombination of components possible. Referring back to Table 3.2, it is possible to identify thecheapest combination of components arise when using IGBT 5 as outer and inner switchesand Diode 1 and the clamping devices.4BGBF aultiAcvjywtivy FunwtionAs already pointed out, optimizing the design of a converter based on a single objective oftenleads to impractical results. Due to the complexity of power converters and strict marketrequirements, many performance characteristics must be optimized for. A good design thenaccounts for the trade-offs of the system variables and provide little compromise to theimportant performance aspects.The first case considered is a situation in which each parameter of the objective functionis of equal importance. In this scenario, all weights are then set to one. The results areshown in Table 4.6. Here it is important to point out that a good compromise was reached,and none of the values are too far from a reasonable range. When compared to the singleobjective optimizations previously performed, there were no outcomes with notoriously poorresults for any of the performance targets.564.4. SgmmSdkTable 4.6: Optimization with Equal WeightsP (W) dF Sfout Sfwn Sfclomp fsw(Hz) L(mH) mox  Cost(8)FIDAEDDD E acgFEhG acgFEhG acgFEhF KDDD 6B6G DBML DBDDF 6EB6DKIDAEDDD E ][VhE acgFEhG ][VhH EEDDD EBHE DBMK DBDDI IEBH6FIDAEDDD AE ][VhE ][VhE DiodyF FDDDD HB66 DBMK DBHKD GDBEDKIDAEDDD AE ][VhE ][VhG ][VhF ELDDD DB6I DBMK DBDDH IIBMHTable 4.7: Optimization for Efficiency with Cost RestrictionP (W) dF Sfout Sfwn Sfclomp fsw(Hz) mwn mox Cost(8)FIDAEDDD E acgFEhG acgFEhG acgFEhG EDDD DBMK DBMM I6BH6IDDAEDDD E acgFEhG acgFEhG DiodyG EDDD DBML DBMM HFBKFKIDAEDDD E acgFEhG acgFEhG DiodyG EDDD DBMM DBMM HFBKFFIDAEDDD AE ][VhH ][VhH acgFEh6 EDDD DBML DBML IMBK6IDDAEDDD AE ][VhH ][VhH DiodyG EDDD DBML DBML HHBMFKIDAEDDD AE ][VhH ][VhH DiodyF EDDD DBML DBML HHBMLThe next considered scenario is commonly seen in industry. Here the efficiency has beendeemed the most important feature for the converter, but a cost limit has been imposed.For this case, efficiency weight fS was set to one and cost was treated as constraint witha $60.00 limit. The results obtained in this scenario, shown in Table 4.7, not surprisinglyshares commonalities with the case where only efficiency was considered, such as low switchingfrequency. Restricting the cost though has lead some key divergences. Quite obviously thecost of the converters are considerably lower than previously, a slight inclination has beengiven to NPC topologies which are inherently cheaper, all without degrading the efficiency.4B4 gummuryThis chapter presented some of the results obtained in the development of this thesis. Anexperimental platform based on the ANPC was developed and used to validate the models574.4. SgmmSdkand assumptions made in Chapter 2. The main elements and functionality of this platformwere described. Next using this platform, a set of experiments were carried out to ensure theaccuracy of the model. Some of the key validators were shown to highlight the efficiency andloss distribution trends closely represent the real world. Lastly, the optimization strategywas put to test with different priorities set through the weights of the objective function.Optimization with single objectives were used to show how the optimum points describedin Chapter 3 are obtained, their merits were described and impractical results highlighted.Finally multi-objective scenarios were presented to show the capabilities of the optimizationtool proposed in this thesis.58Whuptyr IWonwlusionsIBE gummuryWith the expansion of DC systems and microgrids using a DC links, it is inevitable that anincrease in voltage level will be seen in the near future. As motivation for higher voltage levelis the potential cost reduction of the copper lines. To integrate these systems with the existingutility grids, grid-tie inverters capable of withstanding the voltage levels are required. Thiscaused an increased interest in multilevel converters, which not only are capable of handlinghigher voltages with standard devices but also improve power quality and suffer less lossesassociated with sd Lst.As more applications require multilevel converters, it is natural several topologies havebeen proposed, each with particular benefits. Due to all the possibilities, it may be cum-bersome to select the most appropriate topology for a target application. Even after theselection, power electronics designers must select the components that best fit their needs.This task is also not straightforward as an overwhelming amount of devices are available thatare potentially suitable for the target application. In a highly competitive industry such aspower electronics, designers seldom have the time and resources to investigate multiple al-ternatives and often rely on generic rules of thumb adopted by the industry. Although thesemay lead to acceptable performance, a more thorough analysis can lead to better perfor-mance and lower cost, hence gaining an edge over competitors. In this thesis an optimizationsystem was proposed with the intent of aiding power electronics engineers in designing better595.1. SgmmSdkconverters for a target application considering the critical requirements and specifications.Among the multilevel converter topologies, the Neutral Point Clamped (NPC) was se-lected due to its wide range of applications and for being a well understood and trustedtopology. As a natural alternative the Active Neutral Point Clamped (ANPC) was alsoconsidered. The operation of both topologies was explained, and an analysis was carriedout to understand the source of conduction and switching losses on devices of the converter.Regarding the devices that build these converter, MOSFETs, IGBTs and diodes were con-sidered, and their source of losses explained. For sizing the filtering inductor, an equationbased on the total harmonic (THD) distortion requirements, switching frequency and ACcurrent was presented. These segments were incorporated into a model to predict converterperformance based on a given set of operating conditions and design characteristics.With the model developed, the proposed optimization scheme was then introduced. Thissystem targeted four performance aspects which are highly desirable in any power electronicconverter: efficiency, distribution of losses, inductor size and cost. Using a weighting strategy,the objectives were normalized and added together to form a multi-objective optimizationsystem. Weights allow designers to assert priorities based on the specific requirements andspecification of the converter. The impact of the operating conditions (load and power factor)and design variables (topology, devices, switching frequency) on each objective function wasdemonstrated.As a means to validate the accuracy of the theoretical model an experimental platformwas built and a set of tests were performed. The trends obtained with the model showed closesimilarities to real world behaviour, which encouraged further optimizations. At first single-objective functions were considered, which showed relevant characteristics, but often led tonon-practical results. A case in which all performance characteristics were given equal priorityled to meaningful results in which acceptable compromise was reached among all parameters.Lastly a case which is commonly experienced in industry, where the converter was maximized605.2. FgfgdW Iadkfor efficiency but had cost constraints, successfully resulted in a high efficiency converter butwith a much more reasonable cost when compared to a strict efficiency optimization.Overall the work carried out in this thesis showed great potential in accelerating thedesign stage of multilevel converters, focusing on important market requirements. By tak-ing this approach converters may outperform their competition without any considerablecompromises.IBF Futury korkThe focus of this thesis was on practical industrial applications, and commonly adoptedpractices acted a driver. Consequently only technologies which are already established andhave been de-risked were considered. This leaves room to further elaborate on this topic byconsidering up-and-coming technologies such as GaN devices.To accommodate an even wider range of applications, the theoretical model that feeds intothe optimization algorithm can account for even more aspects. For instance more topologies,such as the flying capacitor, may be added to the possible topology alternatives, and higherlevel converters may be considered. Although new models would have to be derived, theprocess adopted can be reused. On a similar note, different modulation strategies can alsobe considered, which would result in slight variations of the equations of the model.Two more complex additions could potentially be included to provide an even more wellrounded design tool. In this thesis, the inductors were only optimized for their magnitude.Research can be performed on optimizing for all aspects of the inductor, including size, lossesand profile which could open the doors to the utilization of planar inductors for example.More complex filters, such as LCL, could also be considered. Another high value additionis an optimization that takes into account the power density of the converter. This wouldinvolve thermal models of the components experiencing losses, heatsinks and cooling devices.61Vivliogruphy[1] A. Nabae, I. Takahashi, H. Akagi, “A New Neutral-Point-Clamped PWM Inverter,” IEEETransactions on Industry Applications, vol.IA-17, no.5, pp.518-523, Sept. 1981[2] J. S. Lai, F. Z. Peng, “Multilevel Converters-A New Breed of Power Converters,” IEEETransactions on Industry Applications, vol.32, pp.509-517, May/June 1996[3] C. Hochgraf, R. Lasseter, D. Divan, and T. A. Lipo, “Comparison of Multilevel Invertersfor Static VAR Compensation,” in Conference Record of the 1994 IEEE , vol.2, pp.921-928, 2-6 Oct 1994[4] R. H. Baker and L. H. Bannister, Electric power converter, U.S. Patent 3 867 643, Feb.1975.[5] P. Hammond, “A New Approach to Enhance Power Quality for Medium Voltage ACDrives,” IEEE Transactions on Industry Applications, vol. 33, pp. 202-208, Jan./Feb.1997.[6] A. Lesnicar, R. Marquardt, “An Innovative Modular Multilevel Converter Topology Suit-able for a Wide Power Range,” in Power Tech Conference Proceedings, 2003 IEEEBologna , vol.3, pp.6, 23-26 June 2003[7] J. Rodriguez, J.S. Lai, F.Z. Peng, “Multilevel Inverters: A Survey of Topologies, Controlsand Applications,” IEEE Transactions on Industrial Electronics, vol.49, no.4, pp. 724-738,Aug. 2002624iTliagdSbhk[8] B.R. Andersen, L. Xu, P.J. Horton, P. Cartwright, “Topologies for VSC Transmission,”in Power Engineering Journal , vol.16, no.3, pp.142-150, June 2002[9] J. Rodriguez, S. Bernet, P.K. Steimer, I.E. Lizama, “A Survey on Neutral-Point-ClampedInverters,” IEEE Transactions on Industrial Electronics, vol.57, no.7, pp.2219-2230, July2010[10] T. Bru¨ckner, S. Bernet, “Loss Balancing in Three-Level Voltage Source Inverters Ap-plying Active NPC Switches,” in Power Electronics Specialists Conference, 2001. PESC.2001 IEEE 32nd Annual , vol.2, pp.1135-1140, 2001[11] D. Floricau, E. Floricau, M. Dumitrescu, “Natural Doubling of the Apparent SwitchingFrequency Using Three-Level ANPC Converter,” International School on NonsinusoidalCurrents and Compensation, 2008. ISNCC 2008., pp.1,6, 10-13 June 2008[12] L. Ma; T. Kerekes, P. Rodriguez, X. Jin, R. Teodorescu, M. Liserre, “A New PWMStrategy for Grid-Connected Half-Bridge Active NPC Converters With Losses Distri-bution Balancing Mechanism,” IEEE Transactions on Power Electronics, vol.30, no.9,pp.5331-5340, Sept. 2015[13] T. Bru¨ckner, S. Bernet, H. Guldner, “The Active NPC Converter and its Loss-BalancingControl,” IEEE Transactions in Industrial Electronics, vol.52, no.3, pp.855-868, June 2005[14] T. Bru¨ckner, S. Bernet, P.K. Steimer, “Feedforward Loss Control of Three-Level ActiveNPC Converters,” IEEE Transactions on Industry Applications, vol.43, no.6, pp.1588-1596, Nov.-Dec. 2007[15] S. Busquets-Monge, J.C. Crebier, S. Ragon, E. Hertz, D. Boroyevich, Z. Gurdal, M.Arpilliere, D.K. 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