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Design and simulation of a coded sequence ground penetrating radar Fraser, Jonathan 2015

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Design and Simulation of a CodedSequence Ground Penetrating RadarbyJonathan FraserB.ASc., The University of British Columbia, 2009A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinThe Faculty of Graduate and Postdoctoral Studies(Electrical and Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)December 2015c© Jonathan Fraser 2015AbstractIn the context of climate change, ground water monitoring has become an important task forwhich Ground Penetrating Radar (GPR) has been ideally suited. However, the limited depthof investigation has prevented GPR’s use in situations with deep water tables. In order tomeet these new depth objectives, a novel Radar has been designed. This new radar, marriesmodern digital coding techniques and the ever improving field of digital electronics with thatof a prototypical GPR. The sequences chosen for investigation include Golay-codes and M-sequences. This new GPR uses off the shelf digital equipment to meet these demands and doesso in a more cost effective manner than conventional GPR. The design and implementation ofthis radar is covered. Simulations of theoretical performance are included for both code typesand include factors for both white noise and digitizer quantization.Preliminary results demonstrate that the use of digital codes allow for greater dynamicrange above and beyond that afforded by an impulse radar. Specifically, we show that whenused with pre-existing dynamic range Golay-codes can add an additional 50 dB of dynamicrange. Contrarily, we show that M-sequences can provide a similar dynamic range but thisis total and not in addition to receiver sensitivity. In both cases, however, we achieve totaldynamic ranges greater than that of an impulse radar.According to the simulation, the increase in dynamic range from the sequences, combinedwith a lower frequency of radar (25MHz), allow us to achieve previously unseen depths of in-vestigation (180m). This depth is under a presumed attenuation of 1 dBm−1. As an additionalbenefit of using these codes, we can exploit the use of commercial FPGAs for code generationand processing. This substantially reduces the cost and opens up the radar for the intendedapplication of remote monitoring. This lower frequency has the adverse effect of lowering theradar’s resolution. Moreover, the use of long codes increases the device’s acquisition time.However, these limitations do not unduly impact its intended use.iiPrefaceThis dissertation is the original, unpublished, independant work by the author, J. Fraser.iiiTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiiGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.2 Electromagnetic Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2.1 Magnetic Vector Potential . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2.2 Radiation Due to Accelerating Charge . . . . . . . . . . . . . . . . . . . 132.3 Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.3.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17ivTable of Contents2.3.2 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.3.3 Repetition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.4 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.4.1 Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.4.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.4.3 Antennas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.4 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . 262.4.5 Capture Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.4.6 Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.4.7 Synthesized Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.5 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.5.1 Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.5.2 Synthesized Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.6 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.6.1 Archaeology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.6.2 Agriculture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.6.3 Geology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.6.4 Glaciology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.6.5 Hydrology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 Radar Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.1 Antennas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.2 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.3 Receiver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3.1 Digital Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3.2 Primary Analog Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.3.3 Main ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.4 Processing Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.4.1 SP605 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.4.2 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49vTable of Contents3.4.3 Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.4.4 DRAM Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.4.5 Embedded Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.4.6 Build System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76AppendicesA Receiver Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82B Transmitter Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90viList of Tables2.1 A sample link budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.1 User Logic Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503.2 CPU IO Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583.3 IO bit mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.4 Memory operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603.5 Memory Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603.6 UART Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.7 UART control bit mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.8 ADC control bit mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.9 VGA status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63viiList of Figures2.1 Field lines emanating from an positive charge . . . . . . . . . . . . . . . . . . . . 142.2 Field line disturbance due to accelerating charge . . . . . . . . . . . . . . . . . . 152.3 A typical Ground Penetrating Radar (GPR) flow diagram . . . . . . . . . . . . . 222.4 GPR digitization chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.5 Modified Chirp GPR with receive mixer. . . . . . . . . . . . . . . . . . . . . . . . 302.6 Simulated Pulse Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.7 Cross correlation of sample coded sequences . . . . . . . . . . . . . . . . . . . . . 363.1 Block diagram of the radar system . . . . . . . . . . . . . . . . . . . . . . . . . . 433.2 Flow diagram of receiver chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.3 Block diagram of a M-Sequence Linear Feedback Shift Register (LFSR) in Galoisform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523.4 Block diagram of the soft core CPU . . . . . . . . . . . . . . . . . . . . . . . . . 574.1 Simulated impulse response used for validation . . . . . . . . . . . . . . . . . . . 684.2 A flow diagram of the simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.3 Recovered response from a order 10 sequence . . . . . . . . . . . . . . . . . . . . 704.4 Recovered response from a order 27 sequence . . . . . . . . . . . . . . . . . . . . 714.5 Noise floor reduction as a function of sequence length and code type . . . . . . . 72viiiGlossaryPLL Phase-locked loopEM ElectromagneticGPR Ground Penetrating RadarPRI Pulse Repetition IntervalLNA Low Noise AmplifierADC Analog to Digital ConverterDUT Device Under TestVNA Vector Network AnalyzerPRF Pulse Repetition FrequencyLFSR Linear Feedback Shift RegisterSNR Signal to Noise RatioRF Radio FrequencyJEDEC Joint Electron Device Engineering CouncilMCB Memory Controller BlockMIG Memory Interface GeneratorFIFO First in, First OutFPGA Field Programmable Gate ArrayixGlossaryRPC Remote Procedure CallVGA Variable Gain AmplifierLVDS Low Voltage Differential SignallingIF Intermediate FrequencyCPU Central Processing UnitIO Input OutputOS Operating SystemROM Read Only MemoryRAM Random Access MemoryELF Executable and Linkable FormatGCS Golay Complementary SequenceENOB Effective Number of BitsDSP Digital Signal ProcessingLFSR Linear Feedback Shift RegisterECL Emitter Coupled LogicHDMI High-Definition Multimedia InterfaceDFS Data Format SelectXOR exclusive orADSL Asymmetric Digital Subscriber LineVHDL VHSIC Hardware Description LanguageHDL Hardware Description LanguageRAM random access memoryxAcknowledgementsI would like to acknowledge those who have helped me complete this work. My girlfriend,Shijing, who has been both supportive and provided a kick in the pants when I need it. To mylabmates, Daryl and Peter, whom always provided stimulating conversation into the realms ofall things electromagnetic, thank you. I would also like to thank my friend Christopher, whomI could always turn to when I needed to sort out building a firmware toolchain. My parentsof course, have been a big help in completeing this, both financially and emotionally. I wouldalso like to thank General Fusion, for allowing me to both complete this Thesis and providethe financial support I needed to do so. I would also like to thank my supervisor, Dr. Yedlin,for putting up with such a tardy student and providing the guidance needed to finish. Finally,I would like to thank beer, which helped suppress the urges to run for the hills and provide astate of mind which made the rest of this work make some sense.xiChapter 1IntroductionGround Penetrating Radar (GPR) is a tool of investigation into what lies beneath the surfaceof the earth through the use of propagating Electromagnetic (EM) waves. This concept is notnew, dating back to the middle of the 20th century, and shares much of its history with itsaviation cousin. Despite its age, the field of GPR is a promising and diverse area, with a largenumber of potential applications. Having been in use for so long, the software for transformingthe raw data captured by these radar into usable maps of the what lies beneath the surface iswell-studied. This is of course aided by the fact that the oil industry uses similar techniques foracoustic surveys. However, unlike the processing software, the technology used in this industryto capture the raw data has changed very little over the past 40 or so years. It is in modernizingand upgrading this capture technology which we hope to bring GPR technology into new roleswhich previously it was unable to fill.The technology of GPR is used to investigate structures on the order of centimetres froma wideband radar to tens of meters from a more penetrative one. For example, a typical GPRapplication would be in survey use to locate buried pipes, or perhaps during an archaeologicaldig to detect the remains of what used to be structural walls. In these areas, the depth ofdetection is on the order of a few meters due to attenuation in the earth. Moreover, these radartend to be of the pulse type. In more modern rolls, we see the emergence of ultra-wide bandtechnology in use. These higher bandwidths come at a cost, while resolution is improved, thedepth that these radar are capable of reaching is much shallower. It is however, in these newerradars, which we start to see some more advanced coding and interrogation techniques movingaway from a simple pulse [1–3]. What we do not see however, is the application of these newercoding techniques to the lower frequency, more deeply penetrating GPR units.11.1. Application1.1 ApplicationOver the past few decades, climate change has become an increasingly important subject [4].The drastic changes in rainfall and weather patterns have serious impact on the amount ofground water available in an area [5]. Combining this with the fact that, throughout thecontinental US, many of the water reserves are fossil reservoirs [6] and the monitoring of availableground water becomes of critical importance. Although the typical method of monitoring watertable depth is via borehole pressure transducer [7], this method is limited to where the drillingequipment can be located. There are, however, other more portable methods of monitoring thewater table such as GPR. These methods are typically limited to areas near the surface, inthe realm of 20m [8, 9]. However, not all water tables are within such a shallow depth and assuch a deeper radar is required. If we choose a monitoring application, where the radar will bepermanently installed, we can exploit the fact that the water table varies slowly to achieve thisadditional depth.1.2 ProblemAs previously stated, typical radar systems are limited to a very narrow band near the surface.As we will see in section 2.3.1, this limitation is primarily due to the attenuation experiencedby the radar impulse as it travels through the earth. If we are to construct a radar which iscapable of tracking these deeper water table levels it must be capable of overcoming these losses.For our purpose we will target a depth of 100m, which is inline with some of the deeper watertables [10]. The actual attenuation that would be encountered in the field is highly variable.We shall use a value of 1 dBm−1 for the purposes of estimating depth [11]. Moreover, the designneeds to be mobile and cost effective enough to be used for long term remote monitoring. Toovercome this, we will need a new type of radar, the design and simulation of which is the focusof this treatise.1.3 ContributionThe contributions demonstrated in this treatise are:21.4. Outline1. A GPR for water table investigations that is capable of greater than 40m of penetration.2. A complete hardware design for said radar utilizing a reconfigurable Field ProgrammableGate Array (FPGA).3. Testing on both the receiver hardware, and the FPGA and CPU codebase.By designing a unique low frequency coded-sequence radar, we can achieve the dynamic rangegoals to perform water table monitoring. We can overcome this unique dynamic range challengeby combining two different methods. Firstly, we lower the frequency of the radar below thestandard 500MHz [12], to a far more modest 25MHz. This decrease in frequency allows for fardeeper penetration even without an increase in Signal to Noise Ratio (SNR). Second, we exploitcoded sequences to decrease our effective receiver noise floor as compared to a typical impulseradar [13]. This lower noise floor directly translates into a deeper penetrating radar. The resultis a unique combination of both low frequency and coded sequences which together allow fordepth of penetration previously unobtainable. The combination of these design choices allowfor use to provide the first contribution. Moreover, the use of these coded sequence allow usto exploit commercial hardware which allows us to achieve the low-cost criterion. This designchoice, of using an FPGA, allows for a degree of configurability not typically provided by a GPRand thus achieve the second contribution. Additionally, as part of the development process forthis radar we can provide a tested design yielding the third contribution. The dynamic range ofthe radar described in this treatise (180 dB) is greater than the values of 60 dB[1] and 100 dB[14]reported previously for coded sequence radars.1.4 OutlineAside from this introduction, this treatise will proceed over the remaining four chapters, eachdedicated to a specific aspect of the radar design process. In chapter 2, we will cover a briefhistory of radar as well as some of the underlying EM theory. However, the primary focus ofthe chapter will be on the various aspects of a prototypical GPR. We will visit some of thecomponents which make up a radar, as well as the design factors which influence the form theytake. We will also touch on some of the different types of GPR already out there and how this31.4. Outlineaffects the make and form of the radar. In chapter 3, we will cover the specific implementationand design of our custom radar. The focus of this chapter will be a technical description of theradar as it is built, as well as justification for some of the critical design choices. In chapter4, we will cover a simulation of the radar as it is expected to perform. As at the time of thiswriting the system is not completely tested, we will investigate it’s theoretical performanceas well as provide an example of the form of signal processing necessary to utilize this radar.Finally in chapter 5, we will conclude with an overall summary of this work detailing what hasbeen accomplished as well as the work which still remains to be completed.4Chapter 2Previous WorkGPR has a relatively long history in the geophysics community [12]. However, the typical designof a GPR, has changed very little compared to its aviation cousin. This has been largely limitedby the fact that most GPR are required to be mobile. This requires small units which can behand carried or slightly larger units which can be vehicle mounted. There are relatively fewtechnologies that allow us to peer into the surface of our planet (and indeed other planets [15]).There is seismic sounding, which probes the earth with acoustic waves, and there are bore holesurveys in which one drills into the earth to access the deeper layers. Both these techniquespenetrate deeper than GPR in general. However they have their own short comings. Seismicsurveys search for density and stiffness variation within the rock which may not be correlatedwith the parameters of interest. Additionally, these methods are not exactly unobtrusive as thestimulus signals (read high explosive) tend to disturb their surroundings. Likewise, boreholeshave a relatively large overhead, as it is costly to drill and provide a view of only a singlelocation. Moreover, locating the required drilling equipment in remote areas can be difficult orprohibitively expensive.With the modern emphasis on climate change, accurate information with respect to thestate of the global climate is more and more of a priority. As such weather monitoring stationsare set up in remote locations and feed data back to scientists who track and predict the everchanging environment. However, these observations are surface limited, and cannot accountfor that which is below. As ground water subsides, there can be significant disturbances to thelocal biosphere as well as agriculture, and as such, monitoring the available water is a priority.In areas where there are numerous wells, this is a simple task as the well serves the purpose ofa monitoring borehole. In remote areas, where one wishes to track the ebb and flow of groundlevels, the installation of sensors in the monitoring stations mentioned above is required. As52.1. HistoryGPR is an ideal candidate for remote monitoring, the question remains, can it fulfill this task?Typical radar is limited to only a few tens of meters while the water table may be located muchfurther down. As we will later see, current advancements in digital technologies open up thedoor to a larger variety of options when constructing a GPR. In this chapter we will discussthe current state of the art in GPR design detailing some of the technical details and trade-offsthat must be made when designing a radar as well as the technologies available to do so.2.1 HistoryAs it so often does, war has a way of accelerating the development of technology. The prede-cessor to radar, sonar received this treatment during World War 1, when it was used to searchfor enemy submarines. It was only logical that during the next major war, the confluence ofmodern radio technology and sonar would coalesce into what we now call radar. Used as anearly warning system for the British during the blitz, the system was born more out of des-peration than inspiration. Early radar transmitters were simple and imprecise. These earlysystems proved invaluable as an early warning system against continuous onslaught of the Ger-man Luftwaffe, as the crucial minutes afforded by the system allowed for fighters to scrambleand climb to meet incoming fighters and bombers during the various aerial incursions and theBattle of Britain. When the war finally came to a close, radar found its way into civilian rolesas an assistant to air traffic controllers in civil aviation. It is for a different role, however, thatwe consider its use. As radio waves are capable of not only reflecting off of objects but alsopermeating them, it is possible to construct a system that can look into and through objectswhich would ordinarily be opaque. It is this imaging application, which, when applied to theearth that we call GPR. The premise of GPR and radar in general is to bounce or permeate asufficient amount of energy at a sufficiently wide bandwidth off or through a target and thenpick it up at the receiver. By sending and receiving these signals from multiple locations, onecan build up an image of the material with which the wave has interacted.62.2. Electromagnetic Background2.2 Electromagnetic BackgroundThe principles upon which radar is based date back to James Clerk Maxwell [16] and thediscovery of the so called Maxwell’s equations. Before these scientists came to the scene, itwas believed that light and electricity were completely separate phenomenon to be consideredindependently of one another. It was Maxwell’s inclusion of displacement current which unifiedthese two fields and laid the framework for our current understanding of electromagnetism. Inthis section we will go over the principles of electromagnetism and how they relate to radiation,so as to gain an understanding of the principles on which radar is based.Maxwell’s equations can come in several forms depending on the mathematical frameworkthat one is working in. Moreover, depending on the choice of units, the various equations canbe normalized in different ways. This is left as a warning to the reader when comparing theresults from this treatise with other resources. For the remainder of this document, wheneverwe are discussing fields, we will be referring to those easily expressed with vector calculus andan SI unit system. As such, previous knowledge and familiarity with these will be required.Let us begin by detailing the equations and detailing their relevance. For the remainder of thistreatise, derivations will maintain the conventions that vector quantities shall be in bold, whichscalar quantities will not.∇ ·E =ρǫ(2.1)∇ ·B = 0 (2.2)∇×E = −∂B∂t(2.3)∇×B = µJ+ µǫ∂E∂t(2.4)These four equations form the basis of radio and EM. Gauss’s law 2.1 states that electricfield lines form only closed loops or connect charges which are a monopole in the electric field.72.2. Electromagnetic BackgroundGauss’s law of magnetism 2.2 states that there are no monopoles in the magnetic field andtherefore only forms closed loops. Faraday’s law 2.3 states that a changing magnetic field willcreate an electric field around it. While Ampe`re’s law 2.4, states that a current will induce amagnetic field around it. Maxwell’s major addition to this set is the inclusion of the second termin Ampe`re’s law. That a changing electric field is, for all intents and purposes, a current andtherefore a magnetic field is generated by this displacement current. The inclusion of this termallows for a certain symmetry and coupling such that energy can flow between these two fields.For the purposes of deriving the radiation equations, we will assume the material in which weare operating to be homogeneous, while this assumption is certainly not true for radar (if thematerial doesn’t change there is nothing to detect) it is locally true for an arbitrarily smallregion and we can take account of actual material property changes via boundary conditionson these small regions. Additionally, we will make use of the linearity assumption (that is tosay material properties do not change with field strength), as well as assume that if materialproperties do change with time, they do so on a time scale which is much much longer than thepropagation time.Due to the fact that we are primarily concerned with transmitting and receiving radiatedwaves, we shall walk through a derivation of the radiation from a simple emitter. There aremultiple ways to go about doing this, and we shall touch on two of them, the first is a rela-tively mathematical and traditional methodology making use of the invented field known as themagnetic vector potential. The second, is a far more terse and somewhat geometric derivationwhich was originally formulated by J.J. Thomson, the discoverer of the electron. Both havebeen included both to expose the reader to a rigorous and intuitive understanding of radiationsimultaneously so they might better reason about these systems.2.2.1 Magnetic Vector PotentialThe magnetic vector potential is a tool used by those working from an analytical perspectiveto simplify certain equations relating the electromagnetism. It depends on Gauss’s law ofmagnetism in determining that the divergence of the magnetic field is zero. By exploiting thevector calculus relation, that the divergence of a curl is zero, one might invent a field suchthat its curl is the magnetic field. Indeed, this is exactly the definition of the magnetic vector82.2. Electromagnetic Backgroundpotential (A) and it is stated in equation 2.5.∇×A = B (2.5)We will start by substituting the definition of the magnetic vector potential in 2.5 intoFaraday’s law 2.3.∇×E = −∂∂t∇×A (2.6)At this point, equation 2.6 might imply that the electric field is simply the time derivativeof the magnetic vector potential, but this is not the case. Arbitrary curl free components couldexist in E at this stage which would not be reflected in this relation. As a gradient of a scalarfunction is curl free, we may add such a field without violating this relation. Doing so we arriveat equation 2.7E = −∇ϕ−∂A∂t(2.7)It should be recognized by now that ϕ totally determines the electric field in the static caseand is the familiar quantity of electric potential or voltage. The negative sign is included tomaintain established convention. At this point we will substitute equations 2.5 and 2.7 intoAmpe`re’s law 2.4 to close the relations and obtain a complete form of electromagnetic equationsthat depend only on the two potential fields.∇× (∇×A) = µJ+ µǫ∂∂t(−∇ϕ−∂A∂t)(2.8)We can now apply a vector calculus relation to simplify the left hand side. Moreover, wewill also make an additional assumption at this point, that the current due to a static electricfield is zero. This is the same thing as saying that the conductivity of the medium is zero.This simplifies the expressions and can be thought of as approximately true for most purposes.92.2. Electromagnetic BackgroundApplying this calculus relation and not expanding the current field we arrive at 2.9.∇ (∇ ·A)−∇2A = µJ+ µǫ∂∂t(−∇ϕ−∂A∂t)(2.9)We can then group like gradient terms and re-arrange:∇2A− µǫ∂2A∂t2= −µJ+∇(∇ ·A+ µǫ∂ϕ∂t)(2.10)A vector field is fully specified by its curl and divergence and we have only specified itscurl. As the magnetic vector potential is an invented field, we are free to arbitrarily specifyits divergence. This is the so called gauge condition and one should take heed of the fact thatthere are many fields which are called the magnetic vector potential and are symbolized by A,however, they vary in this gauge condition. From equation 2.10 it should be apparent that aparticular choice of divergence will simplify the equations. This gauge condition is referred tothe Lorentz gauge, and is detailed in equation 2.11.∇ ·A+ µǫ∂ϕ∂t= 0 (2.11)By taking the gauge specified in 2.11 and substituting it into 2.10, we can see that theleft hand term completely drops out and we are left with a Helmholtz equation specifying themagnetic vector potential and a function of the current distribution.∇2A− µǫ∂2A∂t2= −µJ (2.12)However, this expression is not a complete description of the electromagnetic phenomena.We had earlier required the use of a curl free field to fully specify the electric field. In order tocompletely specify the electromagnetic fields, let us finish the derivation by applying the lastrelation in the form of Gauss’s law 2.1. We will substitute into Gauss’s law the original formwe found for the electric field in equation 2.6.∇(−∇ϕ−∂A∂t)= −∇2ϕ−∂∂t∇ ·A =ρǫ(2.13)102.2. Electromagnetic BackgroundWe then arrive at and equation 2.13 which depends only on the electric potential and thedivergence of the magnetic vector potential which we have already specified in our choice ofgauge condition. Let us now substitute this gauge condition back in so that we can attempt toobtain an expression depending only on the electric potential and the space charge.∇2ϕ− µǫ∂2ϕ∂t2= −ρǫ(2.14)It is clear from equation 2.14 that we have arrived at another Helmholtz equation involvingthe electric potential and the free charge distribution as the driver. Moreover, this descriptionhas completely decoupled the electric potential from the magnetic vector potential. This pairof equations (2.12 and 2.14) form a complete description of radiation in free space and havesolutions specified by retarded potentials which are detailed below in equations 2.15 and 2.16with c = 1√µǫ.ϕ (t, r) =14πǫ∫Ωρ(t− |r′−r|c, r′)|r′ − r|dr′ (2.15)A (t, r) =µ4π∫ΩJ(t− |r′−r|c, r′)|r′ − r|dr′ (2.16)In the case of antenna radiation patterns and other such things, the assumption that thereare no free charges is applicable. In this case, the electric potential solution can be safely ignoredand we can concentrate on those fields caused by a current distribution. Moreover, we mayconcentrate on the fields generated by an infinitesimal radiator as the fields follow superpositionand they may be used to construct the fields from any arbitrary current distribution. With noloss in generality we assume an infinitesimal current radiator located on the origin, orientedalong the Z-axis. The magnetic vector potential for this radiator is specified below.Az (t, r) =µ4πI(t− |r|c)|r|δl (2.17)In addition to the our interest in those fields generated by current distributions, we are alsointerested in signals which are sinusoidally varying. Therefore we will change the representation112.2. Electromagnetic Backgroundof our magnetic vector potential field into so-called time harmonic form, this is expressed inequation 2.18. We take I0 to be the complex amplitude of the current in phasor form.Az =µI0δl4π |r|e−jω|r|c (2.18)As we are interested in fields radiating from this small current source, let’s change to aco-ordinate system which is more fitting. By changing the above expression into spherical co-ordinates we can exploit the fact that this distance parameter r, which is repeatedly appearing,becomes one of the ordinary directions. The result is shown below. As the spherical coordinater is a simple scalar quantity, we will cease to bold it but it is still related to our previousdefinition of r as it magnitude.Ar =µI0δl4πrcos θe−jωrc (2.19)Aθ = −µI0δl4πrsin θe−jωrc (2.20)The magnetic field B can then be found by re-applying our definition of the magnetic vectorpotential from equation 2.5. Substituting and taking the curl in spherical coordinates we getthe following.Bφ =µI0δl4πsin θe−jωrc(jωcr+1r2)(2.21)Taking the above result an applying Ampe`re’s law 2.4 we can also get the electric field.Er =µI0δl2πcos θe−jωrc(1ǫcr2+1jωǫr3)(2.22)Eθ =µI0δl4πsin θe−jωrc(jωǫc2r+1ǫcr2+1jωǫr3)(2.23)Here we will introduce the Poynting vector which describes electromagnetic power flowingthrough a surface. It is the electromagnetic equivalent of P = V I and is shown below in122.2. Electromagnetic Backgroundequation 2.24.S =Bµ×E (2.24)We are also interested in the power flowing away from our radiator, which in sphericalcoordinates is the radial direction. A cross product always produces and orthogonal field andso if we are interested in results in the radial direction we may safely ignore the radial componentof the electric field. The remaining quantities BφandEθ can then be used to determine the powerflow.Sr =BφEθµ= µ(I0δl4πsin θe−jωrc)2(jωcr+1r2)(jωǫc2r+1ǫcr2+1jωǫr3)(2.25)As shown above there is a net flow of power radiating away from the antenna with intensityvarying with elevation. This long and drawn out and somewhat mathematically verbose expla-nation of radiation gives a complete picture but is not completely tractable to those unfamiliarwith the subject matter. This strict dependence on mathematics can in a sense interfere withan intuitive understanding of radiation. As such we will now perform a second “derivation” ofradiation using a more geometric methodology.2.2.2 Radiation Due to Accelerating ChargeIn section 2.2.1 we discussed radiation from a simple Hertzian dipole. We derived this expressionvia the method of vector potentials and showed that a radiating field is present. While thisdescription is complete and accurate, it is difficult to reason with or about and so we shallalso present a second method which simplifies the way in which the radiation is produced.This second derivation is attributed to J.J. Thomson [17], and consists of an analysis of anaccelerating point charge. We will begin this discussion with a point charge, moving at aconstant velocity, which could be zero, along a straight line (let’s say θ = 0-axis). Equation 2.1states that this should produce a radially symmetric electric field shown in figure 2.1.We then take this particle and then make it experience a momentary change in velocity (anacceleration), such that it is now at a new velocity V ′. The steady state field of the particleis also translating at this new velocity. However, it is displaced relative to where the particle132.2. Electromagnetic BackgroundFigure 2.1: Field lines emanating from an positive chargewould have been, had it not undergone acceleration. The distance it has been displaced isthe change in velocity it has experienced ∆v multiplied by the time since it experienced theacceleration. As it takes time for this change to propagate outward from the particle, there isa disturbance in the electric field at the boundary between these two steady solutions for Vand V ′. Following again from Gauss’s law 2.1, not only is the steady state solution radiallysymmetric but also the field must be continuous when there are no charges present. This is dueto the requirement that the field lines must begin and be terminated on charges. Consequently,at this boundary between the two solutions, there are electric fields connecting them so as toensure that these field lines is continuous. This is shown in figure 2.2.It is with a careful analysis of this disturbance that we may obtain a formula for theradiation. First, it should be said that this disturbance radiates away from the charge atthe speed of light. Second, the spacial thickness of this shell of disturbance is equal to theamount of time the charge was accelerating for ∆t, multiplied by the speed of light (c). Thismakes sense as the disturbance is radiating away, and it began when the charge started toaccelerate and ended when it completed. This gives us the radial information with regard tothe disturbance but we also require lateral displacement. This second component of this fieldwe will call Eθ and it is in the plane of the acceleration and orthogonal to the radial component.As the acceleration was in a line, this gives use still a free parameter as we are free to rotateabout the line of acceleration. However, with no loss of generality we may chose any arbitraryangle as the symmetry of the problem ensures that they are all the same. Returning to the142.2. Electromagnetic BackgroundFigure 2.2: Field line disturbance due to accelerating chargedescription of the lateral vector, along the axis of acceleration, the electric field has obviouslynot diverged from the radial direction and therefore Eθ along that axis zero. Contrarily, at aposition perpendicular to the direction of travel, this field is exactly proportional to the extradistance travelled from where the particle would have been had it not accelerated. Carefulinspection of the remainder of the positions shows that this field component varies sinusoidallywith angular displacement, with θ = 0 in the direction of acceleration. The two proportionalityfactors in 2.26 form a ratio sufficient to describe the direction of the electric field to ensurecontinuity.EθEr=∆vt sin θc∆t(2.26)This ratio, however, does not describe the magnitude of the field. For that we must defer toGauss’s law once again,as this describes the field emanating from a point charge. By applyingthis magnitude to equation 2.26 and additionally applying the time distance relation ct = r we152.2. Electromagnetic Backgroundcan obtain an expression for a accelerating charge.Eθ =∆vt sin θc∆t∗kqr2=kq sin θc2r∆v∆t=kq sin θc2ra (2.27)It should be stated that the above field is not strictly divergence free. However, it approacheszero as 1r2and therefore decreases faster than the radiative term. Therefore, we can takeexpression 2.27 to be divergence free in the limit of a large radius (i.e. far field). The formulationin equation 2.27 is perfectly valid as a far field expression but is less useful than if we can expressit in the form of a current equation. To do this we will start with two different definitions, 2.28and 2.29. The first is the charge of the free carriers in an arbitrary cross-section of conductorwith area A. and the second is the flow of carriers through that cross section with I being thecurrent and v the velocity of the carriers.q = ρAδl (2.28)I = ρAv (2.29)By differentiating 2.29 we can relate changes in current to the acceleration of the carriers,this can then be re-arranged to give us an expression relating carrier acceleration to changes incurrent. This can be found in equation 2.30qa = Aρδl1AρdIdt= δldIdt(2.30)This relation can then be substituted into 2.27 to give as a more useful form of the equationfound in 2.31.Eθ =k sin θc2rdIdtδl (2.31)With our EM primer complete, we shall now move onto the radar systems which are thefocus of this treatise.162.3. Radar2.3 RadarIn order to construct a physical radar, there are certain requirements which must be specified.Properties such as the power level and bandwidth go hand in hand with the application re-quirements. Moreover, the critical choice of radar type must be chosen which will becomes amajor factor in how the radar is realized. In the following section we will cover these variousfacets of radar design and how they align with the requirements for the radar.2.3.1 PowerAs was touched on in section 2.1, power plays an important role in the design of a GPR. Whatdoes it means for a signal to be of sufficient power? Like any radio system, a link budget must bemade when designing a radar system. A link budget takes account of the power into the systemand all the loss factors that you experience as the signal propagates to the receiver. This willtell you by how much you need to decrease the noise floor of your Low Noise Amplifier (LNA) orincrease your transmit power so as to make the signal detectable. There are several factors thatcontribute to a GPR’s link budget [18, p.14-24]. The first item is the transmit power. This isthe amount of power the radar is capable of delivering. Next we have the receiver Noise power,this defines the minimal detectable signal at the receiver. Between the two of these we haveour maximal SNR, and we can start taking into account additional factors of the transmissionmedium. If GPR were to operate in free space, then the Friis’ equation [19] would likely be thedominate loss factor (G) and it is given in equation 2.32. This is the amount the surface powerdensity decreases as the signal spreads out from the antenna.G =(λ4πR)2(2.32)The Friis’ equation makes the simplifying assumption that the radiators are isotropic and assuch we have to take into account the fact that real antennas can never be isotropic [20]. Thisdeviation from a perfect sphere means that there are some directions below average powerand some which are above. Antenna gain characterizes what the maximal deviation above theaverage value is, so that when this direction is pointed at the receiver, the total link has an172.3. Radareffect apparent gain equal to this value.The major loss factor which affects GPR is absorption. The earth is often rich in mineralsand water which significantly affects the depth that can be penetrated with a radio signal.The rate of this attenuation is given by the standard skin depth (δ) formula 2.33. With theattenuation factor (A) given by equation 2.34, where x is the penetration depth.δ =√2ρµrµ0ω(2.33)A = e−xδ (2.34)The equation above is for a good conductor, this may not be true for GPR and as such thefull equation (2.35) should be used, which limits to 2.33 when ω << 1ρǫ.δ =√2ρµrµ0ω√√1 + (ρǫω)2 + ρǫω (2.35)Aside from some smaller factors such as polarization and transmission line mismatch thereare two final major line items to include in a GPR link budget. These are coding and averaginggain. Averaging gain is achieved by effectively decreasing the amplifier’s noise power by thenumber of averages performed. The ultimate limit that can be achieved by averaging is fromcorrelated noise sources within the radar as well as non-linear properties of the system, however,it is often practically limited by how long the user is willing to wait. Finally we have codinggain, when a radar uses a non-impulse transmission the reflection is spread out to be as longas the transmitted wave. This response may be below the noise floor of the amplifier, however,software post processing that will be described later can re-compress the actually transmittedwaveform into a synthetic impulse. The amount of power gain you can receive from this typeof processing is approximately τB where τ is the transmission duration and B is the signalbandwidth. When we combine all these factors together we get the final link budget which tellsus how effective the radar will be. A typical link budget can be found in Table 2.1.There is a significant caveat to the link budget which must be considered in any real radardesign and that is the dynamic range. Any real radar system will have a maximum input power182.3. RadarTransmit Power 20 dBTransmit Antenna 3 dBSpreading -5 dBAttenuation -150 dBReceive Antenna 3 dBAveraging Gain 3 dBCoding Gain 60 dBNoise Power -117 dBNet SNR 51 dBTable 2.1: A sample link budgetas well as a minimum input power defined by the link budget. This maximum input poweris determined by the amplifiers as well as the digitization equipment and fixes the maximumallowable input signal level. As a significant amount of signal will travel directly from thetransmitter to the amplifier, this will place limits on the max transmission amplitude. Thismeans that, in order to have a dynamic range which is greater than your front end amplifier itmust be picked up by coding and averaging gain during post-processing.2.3.2 BandwidthNow that we have an understanding of what is meant by sufficient power, lets take a look atwhat is meant by sufficient bandwidth. If we call the transmitted signal s(t) and the transferfunction of the earth g(t), then the received signal will be r(t) = s(t)⊗g(t) where⊗is theconvolution operation. Because the transmitted signal is convolved on top of the response, ithas the effect of broadening the received characteristics by its own width, which would implythat a temporally narrow transmitted signal is desirable. As will be shown in section later on inthis section this effect can be mitigated somewhat so long as the signal is sufficiently broadband,and indeed doing so is how one achieves the coding or compression gain described in section2.3.1. Additional bandwidth comes at a cost, however, as all the analog portions of the chainneed to be capable of supporting the extra bandwidth. Ultimately, the necessary bandwidthwill be determined by the requirements of the application, for a typical GPR this is usually inthe realm of 500MHz [12].Carrying on, let us more closely investigate the function of bandwidth on our signal reso-192.3. Radarlution. If we assume the Fourier transform of the transmitted pulse is h(f) and it has uniformamplitude in frequency, and with no loss in generality we will allow this constant to be one,then:|h(f)| = |h(f)|2 = 1 (2.36)If the impulse response of the earth is G(f) then the received signal is:r(f) = h(f) ∗G(f) (2.37)If we were to then cross correlate the received signal with the transmitted pulse and make useof the fact that a correlation is a time reversed convolution we then have:p(f) = h(f)∗ ∗ r(f) (2.38)We can then substitute in equation 2.37.p(f) = h(f)∗ ∗ h(f) ∗G(f) = |h(f)|2 ∗G(f) (2.39)Then applying equation 2.36 we arrive at the result that we were looking for, a recoveredimpulse response.p(f) = G(f) (2.40)While this derivation was performed on a signal that was assumed to be infinitely broadbandit applies in a approximation to any signal which is sufficiently broad. The difference beingthat |H(f)|2 = 1 : f0 < f < f1 whose inverse Fourier transform is given by equation 2.41.psf(t) = expj2πfct∆ωsinc(π∆ft) (2.41)In the derivation above, fc =f0+f12which is the carrier frequency and during processing itwould be mixed out of the equation. The sinc term however, provides a fundamental spreadingwidth which will limit the resolution of our final image. This means that rather than an exactreconstruction of our impulse response it is spread by the transmitter’s compressed impulse.202.3. Radar2.3.3 RepetitionA single transmission can only retrieve a limited amount of data. It is limited by both theamount of signal collected and the path traversed by the wave. In order to improve our viewof the ground, it is desirable to both repeat a transmission as well as sample from differentlocations. Repeating a transmission allows for the so called averaging gain referred to in section2.3.1. However, if the repetition rate is too quick, it may be possible for a response to returnfrom a deeper target after then next pulse has been transmitted. This means that there is arequired minimum interval between pulses which depends on the depth from which one expectsto receive reflections.T > 2d/c (2.42)where T is the time between transmissions, d is the maximum resolvable depth and c is thespeed of light in the medium. It should be noted that this is the total maximal resolvable depthincluding any averaging which is performed. This value, T, is known as the Pulse RepetitionInterval (PRI) and it placed an upper limit on the rate at which one can obtain further averages.In order to use averaging however, we should first show that it will improve the quality ofour reconstruction. Let us take the case then, where we have a digital signal which has beencontaminated by which noise, and compute averaging’s effect on the SNR. If r(t) is our receivedsignal and n(t) is a additive white noise contaminant injected by the receiver then:rav(t) =1NN∑rn(t) + nn(t) = r(t) +1NN∑nn(t) (2.43)The expected signal to noise ratio is therefore:SNR =E[r(t)2]E[ 1N2∑N−1i=0∑N−1j=0 ni(t)nj(t)]=E[r(t)2]1N2∑N−1i=0∑N−1j=0 E[ni(t)nj(t)](2.44)Because the noise is white ni and nj are uncorrelated except in the case of i = j theexpectation of ninj is therefore given in equation 2.45.E[ninj ] = δ[i− j]σ2 (2.45)212.4. Hardwarewhere σ is the variance of the noise and δ is the Kronecker delta function. Plugging equation2.45 back into equation 2.44 we get.SNR =r(t)21N2∑N−1i=0∑N−1j=0 δ[i− j]σ2(2.46)Finally we apply the sampling theorem to reduce the double summation into a single summation.SNR =r(t)21N2∑N−1i=0 σ2=r(t)2Nσ2N2(2.47)Re-arranging a bit, we arrive at our final equation in 2.48 which clearly shows that the SNR ofour signal increases proportionally to the number of averages we perform.SNR = Nr(t)2σ2(2.48)Now that we have discussed the various considerations and theory that must be addressedbefore designing a GPR, let us now discuss the various physical elements that are required fora functional radar.2.4 HardwareDespite the variations, there is a common topology associated with GPR. All radar in someform have a signal generator, a power amplifier, transmit antenna, receive antenna, LNA, anda capture device. However, in some cases the receive and transmit antenna are the same.Although the details of which will vary from design to design, a typical flow diagram can befound in Figure 2.3.Figure 2.3: A typical GPR flow diagram222.4. HardwareOne might recognize this as a similar topology to a Vector Network Analyzer (VNA) or astimulus response test set. Indeed it is. The only fact which differentiates the hardware of aGPR from these other devices, is that the power levels and frequencies are optimized for a casewhere the earth is the Device Under Test (DUT). However, the goal is the same, to characterizethe impulse response of the system.2.4.1 Signal GeneratorThe signal generator is responsible for building up the appropriate waveform for the GPR.The waveform in question depends on the type of radar and can vary from an impulse to moreadvanced digital patterns. Whatever the actual signal, it needs to have the broadband characterdescribed in section 2.3.2. A modern Digital Signal Processing (DSP) chip or software definedradio is capable of producing most signals in a flexible and dynamic way. However at thepower levels required by radar it may be difficult to construct a linear amplifier to bring therelatively small signal up in power to transmission strength. As a consequence, it is useful tochoose signals which are more easily matched to the amplifier in use, or to integrate both thegenerator and amplifier into one concrete device.2.4.2 AmplifierThe power amplifier portion of the radar is responsible for driving the signal produced by thesignal generator to sufficient levels for transmission. The type of amplifier needed depends onthe signal that is output and the application. Obviously a hand held radar does not need a10 kilowatt amplifiers; however, an aircraft radar might. When it comes to the pulse varietyof radar, the signal generator and amplifier are often same unit. Additionally, these amplifiersare often constructed to utilize one form of breakdown or another. In fact, the original form ofradar produced its output from a dielectric breakdown in air, an arc [21]. This arc was eitherproduced directly within a waveguide to either excite the radio pulse directly or the currentflowing through the gap was coupled electrically to the transmitting antenna. Moreover, thecoupling network from this switch usually had a pulse shaping network to mould the final radarpulse into the desired profile. Surprisingly, modern pulsed radar has not evolved much furtherthan this.232.4. HardwareOne of the biggest alteration to the pulsed amplifier has been the replacement of the sparkgaps with vacuum tubes and then eventually with semiconductors rigged up for it’s own rapidavalanche breakdown. This modification has increased the radar’s reliability and lifetime. How-ever its principle of operation is still very much the same. In other types of radar, where thetransmitted signal is more complex and there is a need for a distinct signal generator, the am-plifier will then likely become a linear one. One of the original radar amplifiers, and still in usetoday for high power applications, is a vacuum device known as a klystron [22]. This device willamplify and incoming microwave signal produced by the signal generator up to many kilowattsin power and is still used for aviation radar today. The Klystron is not limited to high powerapplications, although its centre frequency is determined by a resonant cavity. Smaller devicesare necessarily higher in frequency which may not be suitable for GPR applications. Movingaway from vacuum tubes and into the modern era, we find that most Radio Frequency (RF)amplifiers can be constructed using semiconductors and indeed this is usually the implementa-tion method of choice for most smaller RF transmitters. Unlike pulsed transmitters, the choiceto use a linear amplifier usually coincides with the choice of a transmit-waveform with niceproperties, for some context dependant definition of nice. As such, distortion becomes an issueas the real world non-linearities of these amplifiers will start to introduce mixing componentswhich pull the amplified signal away from that original waveform and the properties it holds.To some extent a pre-distortion filter can partially correct for this, extending the dynamic rangeof an amplifier, but this technique has its limits.Now that we have discussed how to get sufficient power, we must considered how it getsradiated into the object we are trying to measure. For this we must considered the matchingnetwork which is our antenna, a topic we will cover in the following section.2.4.3 AntennasThe purpose of the system antenna is to provide the impedance coupling mechanism betweenthe wave propagating within the feed transmission line and the free propagating wave in theearth. It also is responsible for spreading this coupling out over a larger area, and by doing soincrease the the directionality of the coupling. Continuing on from section 2.2, this couplingis accomplished via the non-propagating components of the wave, those not contributing to242.4. Hardwarethe Poynting vector, otherwise known as the near field. At any given frequency, some of theenergy which enters the antenna is radiated while the rest is stored momentarily in this nearfield and then directed back at the transmitter. Attentive readers will recognize this as acomplex impedance or in other terms a reactance and will no doubt see this is an opportunityfor resonance. Indeed by resonating, this power can be resent back into the antenna’s near fieldrepeatedly, preventing the loss associated with having it dissipated in the transmitter’s poweramplifier. However there is a catch. As was mentioned previously, in order to obtain sufficientresolution, a GPR must have sufficient bandwidth, and a resonant circuit with high Q has bydefinition a narrow bandwidth. It is therefore we find ourselves in a catch 22 of sorts wherein werequire sufficient bandwidth to resolve the reflections from the radar but also sufficient power todetect them in the first place. This whole matter is complicated by the fact that the geometryof the antenna’s near field is frequency dependent and therefore the impedance required tomaintain resonance also changes with frequency.While the most basic antenna building block was described in section 2.2, we do not as ofyet have a complete picture into the role and complexity of the antenna’s used for GPR. Despitebeing in use for more than 100 years, antennas in general are still an area of active research [23].The problem of correctly designing a antenna for a given application can be stated thus: Specifya spatial distribution of conductor and resistor such that current will flow along it in a mannerthat the far-field radiation pattern has the correct shape and gain over the correct bandwidth.To fully grasp this, one must bear in mind that the this is a highly coupled problem where ifa conductor is even in the proximity of a radiator but not physically connected, it will adopta current due to the near field interactions and this will subsequently effect the main radiator.These style of interactions are exploited in various antennas design such as the Yagi-Uda [24]array, where nearby conductors are utilized to increase the directivity and therefore the antennagain. While this problem has solutions in isolation [25], the combined package necessary forGPR is still an area to be explored and detailed design is beyond the scope of this dissertation.Needless to say the business of antenna design is complicated and methods and techniques togenerate these geometries include advanced optimizers such as evolutionary algorithms [26] andmore. It should be clear then, that even an antenna in free space, poses a challenge to designoptimally. Moreover, GPR requires interaction with the Earth at usually a very short distance252.4. Hardwareand as such this dielectric half space modifies the radiation equations [27], and consequentlythe radiation patterns.Fortunately, an engineer is not without options, as there are many “off the shelf” topologiesfor antennas which have been formulated and analyzed for both their free space characteristicsas well as their broadband properties. The simplest antenna after the Hertzian dipole is thea half-wave dipole, which is a single pair of wires with a total length of wavelength over 2.These antenna are pretty typical in free space, however, the requirement of the choice of awavelength means that this design is optimal at only a single frequency. The reason for thislength requirement is that the antenna acts as though it were a transmission line and the absenceof a matching network means that the feed current resonates in the antenna. This resonanceonly occurs at a discrete set of frequencies and hence the narrow bandwidth. One might havethe idea that terminating this line would improve the bandwidth and indeed that would becorrect. This brings us to the next class of possible antenna, the loaded dipole. This typeof antenna has resistive elements spread along the length to minimize or remove this resonantbehaviour. The downside to this, is these elements consume some of the power. Unlike the half-wave dipole where the resonant energy could slosh back and forth until it is ultimately radiatedout of the antenna, the loaded dipole ensures that power entering the antenna’s feeds are eitherradiated or consumed. This brings about an important point when it comes to loaded dipoles,that, although simple to build and implement, they establish a trade off between bandwidthand efficiency. To evade this trade off dipoles are not the only category of antenna used in theseapplications [28]. Which brings us to the main design point, choosing the right trade off betweenantenna performance and complexity is simply an engineering decision and the ”optimal” choiceis very application dependent. Therefore, I leave it as an exercise to the reader to choose theantenna that is correct for their application. With respect to the design choices withing thisproject, they are covered in section LNAThe fundamental limitation on the what can be directly received by a radio comes from theminute fluctuations caused by nothing more than heat. Short of cooling the receiver, this noisepower is fixed at Boltzmann’s constant times the temperature K ∗T ∗B. For a typical situation262.4. Hardwarethis is approximately 4 ∗ 10−21WattsHz. In order to get the most out of a radio, it’s input floorneeds to be as close as possible to this maximal constraint. An LNA is a specially designedamplifier for which its internal noise floor is one of the chief design constraints. An interestingconsequence of the way noise power works, is that only the first amplifier needs to have thisconstraint. This is because a chain of amplifiers will obey the Friis’ formula [29] for the noisefactor, with the total noise contribution dominated by the first amplifier in the chain. This caneasily be seen in equation 2.49.Ftotal = F1 +N∑i=2Fi − 1∏i−1k=1Gk(2.49)where Fn and Gk are the noise factor and power gain for each stage of the amplifier chain.If the gain of the first amplifier is sufficiently large and the noise factors are of similar size thenequation 2.49 approaches F1.The amplifier chain must also be linear, as any non-linearity within the amplifier will causesome of the received signal to be mixed back in and be potentially received as correlated noise.There are two major figures which are used to detail non-linearities in amplifiers. The first isthe 1dB compression point. This is the input amplitude where the output of the amplifier is1dB below what would be expected were the amplifier to apply its specified gain. In otherswords the 1 dB point is when in + G − out = 1dB where all figures are given in dB and G isthe specified gain of the amplifier. The second major factor when dealing with non-linearitiesis the IP3 point, otherwise known as the Third-order intercept. The IP3 point, is the inputpower level where the output power contained in the third order mixing terms is equal to thatof the fundamental component. This point is far higher than the 1dB compression point, andinputting power at this level will more than likely destroy the amplifier. Nevertheless, this termis an objective indicator as to the linearity of the amplifier.2.4.5 Capture DeviceThe capture device is responsible for converting the incoming waveform into something thatis recorded for later use. This could consist of an oscilloscope in experimental devices [30].However, most modern internally capture the waveforms for later retrieval. The capture device272.4. Hardwareis also responsible for any demodulation that is required. There are two major types of Capturedevices and their performance varies significantly. The first is a full bandwidth capture device,capable of digitizing the entire waveform in a single transmission. The second is a sample andhold unit, which is only capable of capturing a single point of the waveform for each transmissionsent.Figure 2.4: GPR digitization chainThe former is obviously preferred for performance because it can capture the information ina single pass and can therefore use subsequent passes for averaging gain. However, it requires adigitizer fast enough to handle the entire signals bandwidth. The latter is more cost effective,because the digitizer needs only be as fast as the repetition rate. The way the technique (sampleand hold) is performed is to ensure the waveform you wish to capture repeats itself reliably.This is approximately true for radar as the movement rate over the ground is slow compared tothe repetition rate. The next step is to utilize a fast switch to freeze the at an instance in time.It is necessary for this switch to have the required analog bandwidth. One then only needs torepeat the waveform moving the point at which the waveform is frozen by the desire samplingtime each repetition. This means that the recording hardware only needs to be as fast as therepetition frequency and not the original bandwidth.In subsequent sections, we are going to break down some of the common types of RADARsystems and highlight their differences.282.4. Hardware2.4.6 PulseAs the name implies, this form of radar uses a single large amplitude pulse as its probingsignal. The width of this pulse needs to be narrow enough to meet the bandwidth requirementsof section 2.3.2. However, it also must be large enough to meet the power requirements ofsection 2.3.1. This type of GPR is also the kind one might envisage when asked to imagineone. It emits a ”ping” and then listens for a reply. Within a Pulse radar, the signal generatorand amplifier are often combined into a single circuit and, in modern equipment, the pulse isgenerated by the rapid breakdown in a semiconductor.When designing these systems care must be taken to ensure repeatability of the pulse orelse the transmitted pulse must be separately recorded. This is because, although the signalis a good approximation to an impulse it is not an exact replica and when pushing the limitsof extracting data from a GPR, variation in the exact pulse shape acts as a noise source. Infact, this noise source has a power proportional to the signal level and can become the maincontaminant.2.4.7 Synthesized PulseWhile the output of a Pulse type GPR directly provides a sufficient approximation of the impulseresponse, the actual transmission of a pulse can have certain undesirable properties, the largerequired dynamic range for example. For this reason, there are some types of GPR which don’ttransmit a pulse directly, but instead transmit a signal that can be used to reconstruct theimpulse response. The requirement for this is simply that the signal needs to be as wide inbandwidth as a pulse would have been. These synthesized pulse GPR come in a few flavourswhich we shall discuss below.Chirp or Stepped FrequencyA so called Chirp GPR uses a linear sweep in frequency as its output signal, whereas a SteppedFrequency unit will emit fixed length bursts of a continuous wave at incrementally higherfrequencies. By sweeping over the frequency range of interest at the same rate as the PRI onecan build up a signal of sufficient bandwidth. These sinusoidal type of radars can have very low292.4. Hardwarebandwidth digitizers. By modifying the receiver section to include a mixer, the digitizer onlyneeds as much bandwidth as the sweep or step rate as shown in figure 2.5. Additionally thedigitizer must also be modified to capture both phases of the down-mixed signal. This can beperformed with a so called QI Analog to Digital Converter (ADC) or choosing an IntermediateFrequency (IF) frequency that is higher than the sweep rate, but low enough to be captured.It is in fact possible to effectively increase the apparent rate of sampling using sample and holdtechniques (as was described in section 2.4.5) and this is what was done here.Figure 2.5: Modified Chirp GPR with receive mixer.Coded SequenceNow we start to arrive at the heart of our discussion. What separates a coded sequence GPRfrom the other types of radar is, as the name implies, that it transmits some form of digitalsequence or ”code”. This code is constructed so that signal has the broadband nature requiredof it, but they can also have other convenient properties which will be discuss later on. Froma hardware perspective, there is relatively little difference between a coded sequence radar andthe others we have already discussed. The major difference again being in the signal generator,which is replaced with something capable of generating a binary sequence with the appropriateproperties. This binary sequence could be directly transmitted at baseband, or it could bemodulated onto a carrier. In the latter case, the receiver needs also be modified to down mixthe received signal for digitization. Because this signal is binary in nature it can be generatedby relatively simple digital electronics. Additionally, the dynamic range of the transmittedsignal is zero, like the chirp radar, as a binary sequence has constant amplitude over the entiretransmission.302.4. HardwareThere are several type of codes which can be used an each have their own unique properties.The most basic of these codes is the M-Sequence, or maximal length sequence, so called becauseit walks through all possible states of its generator before repeating and therefore is the longestcode which can be constructed for a given number of bits of state. While we go into detailon the correlation of truly random sequences in section 2.5.2, it is worth noting here that thedynamic range of the auto correlation is limited by the sequence length. That is to say, when aM-sequence is cross-correlated with itself, there is an expected correlation between the shiftedsequence and the unshifted sequence of 1/N for sequences of length N.The generator for an M-sequence is simply a Linear Feedback Shift Register (LFSR) con-figured with taps determined by a primitive polynomial over GF(2) [31]. The selected taps arethen XOR’d together to provide the value to shift into the generator. This exceptionally simpleconstruction is well suited for implementation in digital logic. Additionally, the length of thesequence grows exponentially with the shift-register size (2N − 1) and as such it only requires astate size of 80 bits or so before it will take longer than the age of the universe for the systemto repeat at a chipping rate of 25 MHz.Other sequences, such as Golay codes [32], can circumvent this 1/N limitation. In particularwe will look at Golay Complementary Sequence (GCS). These codes sequences come as a pair,with each code appearing similar to random binary noise, with all the spectral propertiesinherent to that. However, as these codes are deterministic, the noise value due to correlationis therefore predictable. These pair of codes is then chosen to have the property that thesum of the two independent aperiodic autocorrelations is in fact the ideal delta function. Theconstruction of these types of codes follows a simple recursive relationship which is detailedbelow in 2.50A′B′ = A,BA,−B (2.50)The comma in the above equation represents concatenation. Starting with a sequence whichalready satisfies the Golay condition such as the most basic A = 1, B = 1, the operation can beapplied recursively feeding the new primed sequence back into the operation. The result is asequence which doubles in length each operation and as such can be grown the any desired size.312.5. SoftwareAlthough Golay codes offer superior performance which will be seen in chapter 4, the recursivegeneration of these codes is not well mapped to real-time processing. It is therefore necessaryto pre-compute the codes prior to transmission.As for the bandwidth which these codes are capable of reaching, this depends on somethingcalled the chipping rate. This chipping rate is essentially the digital data rate for the sequenceor how frequently a new value is transmitter. For digital codes, the spectral maximum istypical what would be expected of a digital system or half the chipping rate. This value isconsistent with the Nyquist rate and rather expected, given that the fastest oscillation whichcan be produced requires two samples. However, when it comes to signal recovery the negativefrequencies become relevant and this has the effect of doubling the bandwidth. The net resultis that the minimum resolvable time for a coded system is equal to it’s chipping rate. Thisresult can be easily seen by the fact that the auto correlation of these coded sequences is asingle sample wide.2.5 SoftwareThe software used in GPR processing is the brains behind the brawn as it were. While thephysical radar collects the raw data, how it is processed and viewed has a strong affect on howuseful it is. The processing that can be performed on GPR data can be as little as nothing inthe case of pulse radar, all the way up to full wave 3D tomography [33]. The specifics of thesetypes of inversion problems are highly application dependant, and therefore the discussion ofprocessing within the context of this dissertation will be kept to idealized impulse recovery.This is the raw form of data which can then be fed to more advanced inversion algorithms.2.5.1 PulseAs was stated previously the processing to be performed on a pulse radar could be as simple asnothing. This is because a pulse radar is a direct approximation for the impulse response, and assuch the data which comes out of a pulse GPR can be used directly. However, in more advancedsystems, where compensating the for the specific shape of the pulse becomes necessary, one canperform some pre filtering techniques such as Wiener deconvolution, in order to partially correct322.5. SoftwareGround (m)Depth (m)Embedded Pipe−5 −4 −3 −2 −1 0 1 2 3 4 500. (m)Time (ns)Simulated Pipe Reflection−5 −4 −3 −2 −1 0 1 2 3 4 50246Figure 2.6: Simulated Pulse Responsefor the fact that the impulse produced by the transmitter is not a perfect Dirac. Even in it’sunprocessed state, this information is still useful. Take for example the system where a pulseradar is scanned over the surface of the ground and the response from each position is laid sideby side in an image or waterfall graph. Figure 2.6 contains a simulated version of this scenario.In the top image the actual state of the earth, it is uniform with the exception of a singlepipe located near the centre. The bottom of the image contains the simplified reconstruction.Although the bottom plot seems heavily distorted by the characteristic Hyperbola pattern, thepresence of a strong scatterer is readily apparent and detectable.2.5.2 Synthesized PulseAs one very might infer from the name, synthesized pulse GPR requires additional processingto reconstruct the impulse response of the system. However, the requirements listed above insection 2.3.2 for what properties a GPR pulse must have, necessitate a rather simple decodingscheme.332.5. SoftwareChirp Or Stepped FrequencyThe processing required for chirped or stepped frequency depends on the exact nature of thehardware that was used to collect it. If the signal was hardware down-mixed before it wasdigitized the processing that needs to be done is a simple inverse Fourier transform of the signal.If the signal was captured at full bandwidth, however, then the signal can be digitally downmixed and then inverse Fourier transformed, or one can also use the technique described in theprevious section to recover the signal via cross correlation. This cross-correlation technique isshown by Aldridge in [34], and results in an impulse recovery with a Klauder wavelet convolvedon top. This additional wavelet is due to the fact that the chirp, although spectrally broad, isnot exactly spectrally flat.Coded SequenceOne might imagine that the specifics of coded sequence processing would highly depend on theparticular sequence chosen. However the derivation in section 2.5.2 shows that the requirementsare, in fact, rather loose only requiring the signal to have a flat frequency response and then thesystem may be recovered by nothing more than a cross correlation. One interesting fact is thata random bit stream has this property and can be used as a stimulus channel for a GPR. Toshow this is true a derivation proceeds below for the auto correlation of a random bit stream.X[n] = xn ∼ B(1, 0.5) (2.51)B is the Binomial distribution. We now define Y to be the autocorrelation of the sequenceX.Y [n] =∑X[p+ n] ∗X[p] (2.52)The expectation of the autocorrelation isE[Y [n]] =∑E[X[p+ n] ∗X[p]] (2.53)As we are dealing with random variables, we will work with the expectation of this correla-342.5. Softwaretion, which has two cases:case 1 a 6= b:E[X[a] ∗X[b]] = E[X[a]] ∗ E[X[b]] = 0 (2.54)case 2 a = b:E[X[a] ∗X[b]] = E[X[a]2] = E[1] = 1 (2.55)From equations 2.54 and 2.55 it should be obvious thatE[X[a] ∗X[b]] = δ[a− b] (2.56)Substituting equation 2.56 into equation 2.53 we get:E[Y [n]] =∑δ[n+ p− p] = Nδ[n] (2.57)We have just shown that the expected autocorrelation of a random binary channel is aKronecker delta function, which is the same criterion that we had before in terms of frequencyresponse that was suitable for a GPR. True randomness, however, is difficult to generate andas such sufficient approximations which maintain the spectral properties described above areoften used. It is two of these approximations which we will touch on here, the generation ofwhich was discussed in section 2.4.7 and 3.4.3. Because M-sequences can be constructed with anLFSR they can be generated on the fly with relatively very little digital logic. As can be seenin figure 2.7 these sequences retain their cross correlation property. While their appearancein GPR applications appears to be relatively minor, these sequences take a prominent rollin a diverse range of fields because of their broad spectral properties, for example non-linearsystem identification [35] and cryptography. Additionally, the same orthogonality propertywhich makes them useful in this application allows them (or a derivative thereof) to be used asthe fundamental basis for code division multiple access communications channels.352.6. Applications−15 −10 −5 0 5 10 15−10010203040Coded Sequence Cross Correlation Sample  M SequenceGolay AGolay BGolay SumFigure 2.7: Cross correlation of sample coded sequences2.6 ApplicationsGPR finds a use in a broad range of sensing applications. There are many areas of scientificexploration where non-destructive investigation is useful. This section is devoted to exploringsome of those areas of research and how GPR pertains to them. In all cases there exists aneed to investigate subsurface without excavation, as to due so would be either prohibitive ordangerous.2.6.1 ArchaeologyOne major consumer of GPR is Archaeology. This field investigates the history of human civi-lization and a major focus is the recovery of remains and artifacts from the past. Archaeologicalartifacts, as they are typically not more than a few thousand years old, are found within a fewmeters of the surface. As such, some of the range limitations of GPR become a moot pointwhen considering methods of archaeological investigation. Moreover, many of the artifacts areof small size and the size resolution that can be obtained by GPR usually surpasses that ofother investigation techniques. As it is possible to scan large tracts of land simply by tracinga radar unit over it, a great deal of surface area can be catalogued and prioritized for inves-362.6. Applicationstigation. This allows scientists to dig only in the spots that have the greatest chance to yieldan artifact and therefore make an archaeological team implementing these methods that muchmore efficient.To crystallize this, we will refer to a case study of the Prediger Church in Zrich [36]. TheGothic style church that stands there today, is believed to be built in the 14th century. However,this church was built upon the remains of an even older church built in the 13th century.The current church as been modified several times in the intervening centuries, with one suchrenovation occurring in 1918. During a revamp of its interior as well as the addition of a newcellar, ancient walls were discovered. However, these findings weren’t properly recorded and assuch the floor plan and details of the ancient walls were lost. As these walls are believed to beremnants of the original 13th century church, details of their structure would give insight intothe style and age of the original construction. In the modern cellar, there are some outcrops ofthe original walls. These hint at what the floor plan may have been but are insufficient to tellexactly how the church was constructed. Knowing how the church was structured would allowarchaeologists to determine the style of the church. But this posed a problem, as the church isstill in use, excavation was out of the question and a non-destructive technique needed to beused.The chosen method as it turns out was GPR, allowing the scientists to image what liesbeneath the cellar with out digging through or otherwise uprooting the concrete floor. For theresolution and accuracy needed for this testing, a GPR with a centre frequency of 500MHz anda bandwidth of 1.3GHz was chosen. This resulted in a resolution on the order of 7 cm or so.Additionally a scan length of 60 ns was performed resulting in a depth range of approximately6m. The scan was performed in two passes with one course and the other fine. The first scancovered an area of 150m2 while the fine scan covered just 14m2. The results of this work wasthe discovery that the walls were part of the choir of the original church and indeed, it wasa rectangular choir separated from the nave by two partial walls. Additionally, a previouslyunknown an unrecorded altar was discovered. Armed with this new information, the Archae-ologist were able to ascertain that the church was built by Dominican monks in the style ofCistercian prototypes.372.6. Applications2.6.2 AgricultureFarming is another activity the involves working in and near the surface of the earth. Theproblem with traditional farming techniques is that it is impossible to examine what is occurringbeneath the surface with out destructively uprooting the plants. In order to overcome thislimitation, GPR has been employed to investigate and evaluate the performance of the crop.Of particular importance to tuber crops, where the commodity is growing beneath the surface,this technique allows farmers to evaluate the health of their crops and respond appropriatelyin order to maximize yield.One such application is in the farming of sugar beets [37], whose tubers grow undergroundand are later processed as alternative source for sucrose. Capable of growing in colder climatesthan the more familiar sugar cane, sugar beets can be found as one of the main sources ofsucrose for Europe. As previously mentioned, there is a desire the know a crop’s yield before it isharvested. While spot checking can be performed, this results in crop loss as they are harvestedbefore maturity. Additionally, more plants need to be checked to improve the accuracy of theresults. As such, a non-destructive method of estimating the yield would be preferred. Assugar beets are small (10mm-30mm), resolution is a critical factor which determining yield.Moreover, the beets are located close to the surface and therefore attenuation is not a dominatefactor. Combining these two facts indicates an ultra wideband radar would be preferred andindeed this is what was chosen. The specific frequency range was DC to 4.5GHz. Additionally,the encoding scheme chosen for the system was an M-Sequence. However the specific reasonsfor this choice were not described. As an M-Sequence is a continuous transmission, time-gatingbetween the transmitter and receiver antenna is not possible. Therefore this setup used separatetransmitting and receiving antennas. The processing model for the system, was to assume thebeets were approximately a near-surface point scatterer. This near-surface attribute causesproblems however, as the primary ground reflection occurs at approximately the same delay asthe desired reflection of the beets. To minimize this, the receiving antenna and transmittingantenna were angled forward so that they formed an oblique angle of incidence with the ground.This caused the majority of the ground reflection to be transmitted forward away from thereceive antenna, while the point scatter reflection from the beet acted in the opposite direction,382.6. Applicationsscattering backwards toward the receiver. The net result was a system that is able to detect thepresents of beets and produce a detection which is a function of the size of the beet. However,significantly more work is needed to construct a system which is capable of accurately measuringthe volume of the beets in-situ.2.6.3 GeologyGPR can provide significant advantages to Geologists working in the field. A GPR is capableof sweeping far more area then conventional borehole approaches might allow. Additionally,a GPR is capable of faster repetition and more mobility than a seismic survey. To examinethese advantages in a specific setting, we will summarize [38] and the search for bedrock soilsurfaces. The purpose of this investigation was to search for some potentially buried drums. Asthe drums could not be buried within the bedrock, mapping out the boundary between soil andbedrock was sufficient to provide a lower bound. The survey was taken over a paved parkingarea in southern Ontario with a 25MHz radar. Due to the stark contrast between bedrock andsoil in terms of electromagnetic properties, a clear boundary was detected. Moreover, the lackof shallow reflections dictated that the drums in question were not in fact there.2.6.4 GlaciologySoil and rock are not the only things that can be imaged with radar. With the focus on climatechange, glaciers have become “canaries in the coal mine” as it were, with regards to warming.As they are such good climate indicators, monitoring the extent and overall health of the world’sglaciers efficiently and effectively is of utmost importance. Curiously enough GPR also findsa role here [30]. Exploiting the fact that ice is not as lossy as soil or rock, and using a longerwavelength to further mitigate loss, GPR can be used to image the stratigraphy and depth ofglaciers along with fissures and crevasses. Additionally, the use of a longer wavelength allows forthe survey to completed from a further distance such as from a low flying aircraft. As Canada ishome to many such glaciers, let us take a look at some of the work done closer to home [39]. Thestudy in question was performed by aerial fly over of Canadian arctic glaciers. As the loss in iceis relatively low, a central carrier of 840MHz was selected in the UHF band. An impulse radarwas the type chosen for this task and to meet the link budget requirements, the transmitter was392.6. Applicationsselected to have at 4.1 kW peak power which was achieved via a triode amplifier. The antennaused was of a corner reflector type excited by two half wave dipoles. The desired bandwidthfor the radar was 40MHz, although a direct sampling at this rate exceeded the capabilities ofmodern electronics at the time this study was done. The sample and hold technique describedin section 2.4.7 was utilized with a Pulse Repetition Frequency (PRF) of 10 kHz the data wassampled at intervals of 12.5 ns creating an effective rate of 80MHz. The response was digitizedinto a length of 1024 samples representing a time base of 10.24 µs and this measurement wasperformed over a period of 100ms. As the PRF was low enough, these waveforms were recordedonto analog tape. Along with the response waveforms, timing and voice data was also recordedto give context to where the recordings were taken. The system was trialled on Kluane Lake,Yukon Territory with results giving information about the ice thickness and lake depth. Giventhe low loss environment which ice provides, the depth which this radar was capable of recordingtoo was 540m.2.6.5 HydrologyWith the certain knowledge of climate change, it is of the utmost importance to monitor itsprogress and effects. One major facet is the significant lack of rainfall and the correspondingdesertification. Among the more disturbing consequences of these patterns is the loss of groundwater reserves. As major cities and agriculture depend on the these unseen reservoirs for theirfresh water, it is important to monitor and track their health and level. Again we find ourselvesin a position where GPR can be of assistance. By utilizing GPR, one can scan large areasfor ground water levels and can even discern flow rates and direction by correlating waterheight with local rock diffusivity [40]. This monitoring allows early warning of trouble withinthe hydrological system long before the wells start running dry. This critical time providesbreathing room so that usage policy and consumption can be changed to ensure that there willalways be water present.An example of this use is a study done at Hyderabad in India [41] located 3km WNW ofGajularmaram. This investigation focused on a lineament located within the granite terrain.The lineament was scanned with two separate frequencies of 100MHz and 450MHz up to adepth of 450m. The purpose of the analysis was to analyze the rock porosity to evaluate the402.6. Applicationswater storage capacity in the area.41Chapter 3Radar ImplementationWe refer back to section 1.2 to remember the problem description. The target is a radar capableof 100m of penetration, or alternatively 100 dB of dynamic range. The radar need to be low-cost, but is allowed time to perform its depth measurement. Moreover, this radar’s designfocuses on penetration over resolution. Therefore the central frequency of the radar is on thelow side for a typical GPR (25MHz). Now that we have the requirements described we can goabout with an implementation.The radar consists of all the major components described previously, but has been separatedinto two distinct physical pieces. The first piece is a standalone amplifier and antenna whichreceives the signal to transmit via fibre optic link. The remaining elements are at the receivingend with an FPGA processing unit to handle the data throughput. The signal generator isalso here so that the receiver can be synchronous with the transmitted signal. The reason forthis separation is to minimize the amount of direct coupling that can occur via direct electricalpathways into the receiver chain from the transmitter. The radar is of a coded sequence variety,and there are a few reasons for this choice. Firstly, sequences are easy to generate in digitalhardware and can be readily transmitted via digital links. Secondly, the power amplifier forthe radar only needs to consist of high power digital electronics which are readily obtainable.Finally, the receiver can have its effective dynamic range larger than that of the digitizingelement. As we shall see in chapter 4, this is due to the coding gain afforded to us by the digitalsequence. Taken together, this means we have a cost effective radar with a large dynamic range.The system contains four main components, the power amplifier, the antennas and matching,the receiver board, and the FPGA unit. The power amplifier is designed to take the codedsignal from from the processing board, amplify it to appropriate levels and send the amplifiedsignal down a 50Ω transmission line to the antenna. The coded sequence is received by this423.1. Antennaspower amplification board via a fibre optic link. The antennas are of the Wu-King variety andtransformer matched to the 50Ω transmission line. This is true for both the transmitter andreceiver. The receiver board takes a signal from a 50Ω line from the receiver antenna andamplifies the received signal and then digitizes it for transmission to the processing board. Forpractical reasons, the receiver board also contains the fibre optic transmitters which provide thecoded sequence to the power amplifiers. Finally, we have the processing board. This consists ofan off-the-shelf development board which is responsible for most of the logic. This processingboard generates the coded sequence, captures the received data. It is also powerful enough toprocess the received data. Additionally, the processing board is responsible for command andcontrol of the entire radar. A system diagram for the radar is shown in figure 3.1Figure 3.1: Block diagram of the radar system3.1 AntennasAs was discussed previously in 2.4.3, the design and optimization of antennas is a complicatedand diverse field. For the practical purpose of designing a custom radar it would be prohibitiveto design a custom antenna unless one of the more common off-the-shelf antennas are unsuitablefor the task. Indeed this is the approach taken for this radar. There are a few types of antennawhich satisfy these requirements. However a so called Wu-King profile antenna [25] is commonlyused as it shares the same physical profile as a typical dipole antenna and meets the bandwidthrequirements. One down side to using this antenna is that it presents are relatively large433.2. Power Amplifierimpedance which must be matched to the 50Ω feed line. This large impedance is not withoutreason. When one attempts to resonate out the remaining inductance, the large impedanceallows for quite a low Q which as previously mentioned is desirable from a spatial resolutionperspective. This means that we find ourselves in a desirable situation that this ratio of twodifferent impedances is maintained over the bandwidth of interest. The solution to this problemis also well-known and consists of a broadband signal transformer. This transformer providesthe final match from the 50 ohm transmission line to the high impedance antenna. Althoughall of the previous discussion, such as in section 2.2, has been framed in the context of thetransmitting antenna, due to electromagnetic reciprocity [42], all of this applies equally to thereceive side.3.2 Power AmplifierThe power amplifier is responsible for driving the signal into the earth. There are several reasonswhy this unit is detached from the main radar. First, it allows for modularity. By having aseparate board, several can be built for varying power outputs and conditions. This allowsa common receiver to be used both in testing and in deployment with the only thing beingsubstituted is the power amplifier. Second, this also allows for unit testing. The transmittercan be independently designed and verified. Third, the transmitter can be non-local to thereceiver and therefore the transmit location can be moved about. This is important as it forcesthe interrogation signal to take different paths through the earth and can give us informationabout spatially distinct structures Indeed, the current receiver board is equipped to proved twoseparate output channels. Lastly, and this is the most important reason, it minimizes directcoupling between the receiver and transmitter. Although this is related to the third reason,(spatially separating the transmitter and receiver reduces coupling) it is important enough tomention separately. In the presence of direct coupling between the transmitter and the receiverit is often the dominant received component and limits the maximum allowable gain in thereceive chain before clipping of the digitizer occurs. By separating the power amplifier, wereduce this direct coupling and allow for more gain in the receive chain, thus increasing ourusable dynamic range.443.3. Receiver BoardThe fibre link is implemented by a silica fibre, ended with the Avago HFBR-x4xx seriesdevices. Properly modulated and through 62.5/125 micron fibre, the link is specified to becapable of a link length of 1.4 km. As the signal is amplitude modulated, off-the-shelf bitslicing components can be used to demodulate the received IR signal into a digital waveformfor amplification. As per the data sheets of these fibre link components most of the signalsare implemented in Emitter Coupled Logic (ECL) on the receiver side. Finally, the amplifica-tion for transmission is performed by a Asymmetric Digital Subscriber Line (ADSL) chip set.Schematics for the transmitter board may be found in Appendix B.3.3 Receiver BoardThe purpose of the receiver board is to provide the primary custom interface into the FPGA. Itsprimary purpose is to implement the analog receiver chain. However it additionally providesthe fibre optic transmitters used to output the synchronized coded sequence. The board issplit into two halves electrically, and are identified by the ground plane used in each. Thisseparation is to further isolate the sensitive analog input from the digital circuitry. Schematicsfor the receiver board may be found in Appendix A3.3.1 Digital DivideThe digital half of the board consists of three parts. The first part is the fibre optic transmitters.The transmitters consist of a separate power supply, which provides a regulated 5 volts for thetransmitter, a set of buffers and the fibre optic couplings themselves. There is no logic hereaside from a digital amplifier that takes a digital signal from the FPGA and directly sendsit to the transmitter. As recommended in the fibre link data sheet, there is an additionalpassive network designed to prevent the transmitter from fully switching on or off. This partialmodulation behaviour is required for full bandwidth in the fibre link. The second part ofthe digital components is the Variable Gain Amplifier (VGA). The VGA is configured via astandard serial interface and therefore has both an analog interface and a digital one. However,unlike the receiver ADC, the VGA amplifier is not separated into distinct digital and analoggrounds. To compensate for this, the VGA is connected to the analog portion of the chain and453.3. Receiver Boardthe two main ground planes are connected at a single point. As the traffic to the VGA is notcontinuous, this should have minimal impact on the noise floor of the receive chain.Finally, the last digital component is the data side of the receiver ADC. Unlike the VGA thereceiver ADC does separate its digital from its analog ground. The digital portion of the ADCis a parallel bus connection. All the high-speed digital signals are implemented via Low VoltageDifferential Signalling (LVDS). One might be familiar with LVDS as the physical signally layerto High-Definition Multimedia Interface (HDMI). The receiver consists of the 16-bit parallelbus to transmit back the received ADC samples and an over range bit that indicates the inputto the ADC is outside the allowable range. The clocks to the ADC are no exception, andare implemented via LVDS. There is an additional complication with respect to the clockshowever. In order to keep the outputs as synchronous as possible, the ADC provides a CLOCKoutput as well as a clock input. Although the ADC is not capable of generating the clockinternally, it does compensate for duty cycle variation. Additionally, this loop back patternensures that the bits from the ADC are correctly registered to its output clock and thereforeremain synchronous. Finally, there are some miscellaneous configuration bits that control theADC’s behaviour. The most relevant of these is the output format select bit that provides theoption of two’s complement output or a single range.3.3.2 Primary Analog ChainThe receiver chain is designed to provide the maximal dynamic range. At maximal gain,the receive chain is capable of amplifying the thermal noise floor of the input amplifier up to asignificant fraction of the receiver ADC. The total receiver chain is AC coupled with a minimumfrequency of 1MHz and limited on the top end by the anti-aliasing filter to 40MHz. The overallreceiver noise figure is limited when in high gain to that of its first LNA which is a total of 3 dB.Additionally, the entire receive chain maintains a 50Ω single ended impedance until the ADC.As the ADC samples a differential signal, the receive path here changes to 100Ω differential.By AC coupling, we are limited to a minimum frequency of 1MHz instead of DC. This hasseveral advantages however. The first is the fact that we can eliminate input bias currents andlevels that are different on various components. In the presence of significant amounts of gain,this leads to saturation of the ADC before any significant signal gain. The second advantage is463.3. Receiver Boardthe suppression of flicker noise which is present in the low frequency regime.The input receive chain can be broken into four main pieces: the input LNAs, the VGA,the anti-aliasing filter and the receiver ADC. The first two components make up the amplifierand the second two form the digitizer.The first piece provides the bulk of the input gain as well as defining our maximal SNR. Itconsists of two MAN-1LN amplifier modules which can be inserted or removed from the chainvia AS179-92 RF switches. The two amplifier together provide a total of 60 dB of gain at aninput noise figure of 3 dB. These amplifiers have a bandwidth that is far greater than is necessaryfor this application, however, as they exceed the requirements and provide a convenient dropin component to implement the front-end in lieu of designing one from scratch. The secondpiece is the VGA, a component from Analog Devices, the AD8370. This chip provides a serialcontrolled gain that allows us to fine tune control over the amplifier, providing 255 gain levelsbetween −11 dB and 34 dB. An overview of this amplifier chain can be found in figure 3.2.Between these two components the front end amplifier can provide a dynamic gain range of−11 dB up to 94 dB with a quantization of approximately 2 dB.Figure 3.2: Flow diagram of receiver chainThe VGA performs a secondary purpose, and that is the conversion of the single ended inputchain that is used by the LNAs into a differential signal consumed by both the anti-aliasingfilter and the receiver ADC. Additionally, the VGA provides a reference signal determines thezero level for the differential portion.The anti-aliasing filter is a 4th order elliptic filter. It is designed such that the end of it’spass band is positioned at 50MHz and the beginning of it’s stop band at the Nyquist frequencyof 59MHz.473.4. Processing Board3.3.3 Main ADCThe ADC is the heart of the GPR, and in this case is provided by the AD9461 device by AnalogDevices. As performance of this high speed digital system is limited by its ADC, the rest ofthe GPR needed to be designed around available digitization. The ADC chosen is designedspecifically for baseband sampling within the frequency range of interest. The ADC is capableof up to 130 Msps at an Effective Number of Bits (ENOB) of approximately 12 bits and apipeline delay of 13 clock cycles [43]. The front end is a differential analog signal with anoptional common mode reference.3.4 Processing BoardTo perform the actual computation as well as coordination, we include in this radar a processingboard capable of handling the data flow and managing the sensing operations. This is the finalpiece of the set and contains all the brains of the radar. The processing board is electricallyconnected to the receiver and is responsible for generating the code for the transmitter. Thisprocessing board, although being a single physical piece, is separated logically into several ele-ments. The first element is the physical circuitry itself, provided as is via an SP605 developmentboard. The second element is the digital logic which is programmed onto the include Spartan6 FPGA which handles the high speed data manipulation. Finally the third element is theembedded processor which facilitates the command and control logic to coordinate the wholeprocess.3.4.1 SP605The majority of the data flow and processing is performed on board an FPGA developmentboard. At the time this project was begun, there was a choice of which board would serve thepurpose needed for capture and processing of the coded sequence radar. As there are really onlytwo manufacturers of FPGA devices (Xilinx or Altera) the first order of business was to choosewhich company to go with. As both manufacturers make similar devices it more or less comesdown to the tool chain the various IP available from the manufacturer as well as developerexperience. At the onset of this project, the Altera tool chain did not support operation within483.4. Processing Boarda Linux environment. Moreover, there was existing experience with the Xilinx series devices.For these reasons, Xilinx was chosen as the manufacturer for the development kit. The nextdesign decision was which specific FPGA to use for the project. FPGAs can be considerablyexpensive. For example, the highest end chipsets can run for upwards of 50 thousand dollars fora single chip. This means the size of the FPGA needs to be the smallest it can be, but still ableto handle the 2Gbps data rate that will be produced by the ADC receiver. Xilinx manufacturestwo primary series of chips, the Spartan series and the Virtex series. The Spartan series is thelower end of the two running at about a tenth to a hundredth the cost of the Virtex series. Itis however more than capable of delivering data rates in the gigabits per second. At the onsetof this project, the latest series of chips from Xilinx was the 6 series and that choice was made.A 6 series Spartan based development board, found in the SP605 manufactured by AVnet waschosen to perform the data acquisition. In addition to some miscellaneous connections availableon the SP605, the primary data methods of data transport are an SFP connector, a PCI edgeconnector (allowing the board to be installed as a computer peripheral), and the mezzanineconnector. As the mezzanine connector provides the required number of parallel data channelsbetween the FPGA and the receiver ADC, it was chosen to connect the receiver board to theFPGA. This 160 position connector is a standard connector found on most Xilinx developmentboards, and as such it should be possible to connect the existing receiver board to a differentXilinx kit such as the Zed board or other new system.3.4.2 ClockingWhen it comes to FPGA design, clocking is very important. Specifically ensuring that the logicthat is being synthesized within the device meets timing closure [44]. Timing closure is thecondition that all the synthesized gates have their setup and hold times met. In simple designsconsisting of only one clock, this means that only the external signals leading off chip need to besynchronized with the internal clocks. Due to the precision necessary for clocks (the maximumon chip clock rate can exceed 1GHz) the clock signals are carried around the chip via dedicatedlines designed to minimize jitter and delay. Additionally, clocks coming from external sourcesneed to be assigned to pins that are designated as GCLK resources. It is these pins which haveaccess to the clock buffers and the dedicated clock network. It is not always possible, however,493.4. Processing Boardto keep everything on the same clock. Take the current design for example. The ADC must berunning at or near its maximum rate in order to meet the anti-aliasing condition on the inputas well as meet the bandwidth requirements. The CPU competes with this, as its complexitynecessitates the clock rate be substantially lower (about half) in order to meet the timing closurecondition mentioned above. Moreover, the coded sequence is transmitted at closer to 25MHz.Finally, there is the DRAM system which requires a 333MHz clock to meet the DDR standardrate required by the external chip. With these varied clock domains, it serves us to describehow these various rates are generated and how these clock domain crossings performed.First, the Xilinx FPGA is equipped with two types of internal blocks that are capable ofgenerating different rates. The first is the DCM which is available on all Xilinx devices, it isboth smaller and more numerous than the second block. The DCM is capable of changing clockrates in an integer ratio as well as varying the phase by increments of 90◦. The DCM cannot,however, improve the clock jitter or perform fine continuous phase adjustment. This designdoes not use any of the DCM clocking resources, but they are mentioned here for completeness.The second clocking resource is a Phase-locked loop (PLL). Although the PLL is also onlycapable of producing an integer ratio of an input clock it can do so with precise control overphase alignment.There are currently three PLL blocks utilized by the system. The first is generated by theMemory Interface Generator (MIG) system, it takes in the off chip clock and generates all theclocks necessary for the DRAM system as well as provides a 333MHz clock out to the rest ofthe user logic. The second PLL provides all the clocks used within the user logic processing. Ittakes the clock from the DRAM and produces three additional clocks described in table 3.1Table 3.1: User Logic ClocksName Rate DescriptionADC 118MHz Clock rate of the receiver ADCCPU 59MHz Clock rate of the internal 8bit cpuChip 26MHz Clock rate for the coded sequence outputThe values of these particular rates were chosen to target the chip rate to a near as possibleto 25MHz. The 25MHz point was chosen based off of the design bandwidth criteria 2.3.2 and thelimits of the receiver ADC. As was mentioned before, there are in fact a third PLL in use within503.4. Processing Boardthis design but its purpose is not to generate a separate clock rate. The receiver ADC providesa clock feedback that its data output bus is synchronized with. The purpose of the third PLLis to phase shift it’s output is such a manner to ensure the data returning from the ADC isphase aligned with the ADC clock provided by the second PLL. The advantage of this is twofold, firstly as it ensures that all the system clocks and data within the system are synchronous.This mitigates the needs for asynchronous domain crossings which can add considerable delayand complexity into the data pipelines. Secondly, and somewhat more practical, by generatingthe clock within the FPGA; the FPGA’s synthesis tools are able to analyze all the details ofthe clock without it being manually specified and this allows the synthesis tool chain to reportany timing issues associated with it.3.4.3 Signal GenerationAs mentioned previously, this radar is a coded sequence radar and as such the signal generatorconsists of a digital sequence generator. In particular, it is an M-sequence radar. The reasonfor the choice of M-sequences instead of some of the other available codes is that the sheercode length required for the targeted dynamic range would be impractical to store. This canbe taken to the extreme by creating a signal generator with a sufficient number of bits suchthat the generator with effectively never repeat. As was mentioned previously in section 2.4.7,the polynomials that generate M-Sequences are primitive over GF(2). As the coefficients tothese polynomials are just one or zero the coefficients can be represented by a simple integer.These notations may seem familiar to those versed in CRC implementations, and they areindeed related. There are two separate ways to implement an M-Sequence LFSR. The first isthe Fibonacci LFSR, which is more suited to architectures where a shift register is availableand logic operating on the complete state is cheap such as a CPU. The second is the GaloisLFSR, which requires logic in between each cell of the shift register, which is in line with anFPGA’s LUT configuration. The implementations utilize the same polynomials. However, theyare expressed in reverse order. Figure 3.3 gives and example of a 4 bit LFSR implementing the0xC polynomial in a Galois configuration.The plus like symbol in the above diagram are an exclusive or (XOR) operation, the exe-cution is performed by shifting the state and XORing the appropriate states (as indicated by513.4. Processing BoardFigure 3.3: Block diagram of a M-Sequence LFSR in Galois formthe polynomial) with the current output in the process. For the system to operate it must beinitialized. As was hinted by the fact that there are 2N − 1 distinct states, there is a statewhich is not included in the state rotation. This is the zero state. Inspection of the feedbackconfiguration should make it obvious that once put into the zeroed state, it will not leave it. Infact any initialization state, aside from the zero state, is sufficient to reach every other possiblestate in sequence and is therefore an acceptable initialization. The only difference between thevarious initializations is the phase in the sequence in which it starts.The secondary type of implementation, which is not used here but is included for complete-ness, is the Fibbonaci LFSR. In the Fibbonaci LFSR, the ordering of the taps are reversedwithin the shift register. However, it is still represented by the same polynomial. The imple-mentation of this style of LFSR is to XOR all the bits of state selected by the polynomial andshift the result in as the new state bit.If one chooses to utilize a Golay code, instead of a M-Sequence then the procedure forgenerating the codes is a little more complicated. There is no simple LFSR based approach,or indeed any order N or real time method for generating these pairs. Instead, the code mustbe pre-computed in DRAM via the processor using the recursive formulation found in section2.4.7. The transmitter then reads the sequence from DRAM and sends it to the transmitter.In addition to the main Sequence, the bandwidth of the final signal can be further expandedif it is modulated about a carrier [3]. Indeed, the ideal carrier is the chipping clock itself. In thedigital domain, this can be approximated by XORing the output M-Sequence with the chippingclock and as a result the bandwidth can be doubled. This provides the additional benefit ofconsistent modulation (DC value of zero) which is useful for the chopping circuitry in the fibrelink. However, the consequence of this technique is that the idealized response obtained fromcross correlation is no longer an impulse and is instead the autocorrelation of a single clockcycle. The ideal impulse can be recovered using this additional bandwidth via regression or523.4. Processing Boardother such filtering techniques. However this is not necessary. To increase the bandwidth of aM-sequence, one only needs to double its chipping rate. Unless there is a further limitation onrates, such as that imposed by FPGA fabric, then this is the preferred method to double theinput bandwidth.3.4.4 DRAM SubsystemProcessing the data from the receiver could be done in two ways. The first is real time, utilizingthe FPGA fabric to produce the transfer function in real time. The second option is to storethe stream of received data and process it later offline. As the data coming from the receiveris streaming in at a relatively high rate of speed (1.8Gbps), there are very few buses whichare capable of handling the transfer rate and even fewer which are accessible to the SP605development board. Even a gigabit Ethernet link would be beyond saturated. The DDR3ram included on the SP605 is, however, capable of transferring data at 10Gbps and meets ourrequirements for storage. This bandwidth also leaves room to account for some of the delayswhich are present in DRAM such as the refresh cycles. The particular RAM chip present onthe SP605 is the MT41J64M16XX-187E from Micron technologies [45]. It provides us with128MiB of storage or the equivalent of about a half second of storage.DDR memory conforms to the signalling standards laid out by Joint Electron Device Engi-neering Council (JEDEC), and actually implementing this specification in hardware would bea full project unto itself. Additionally, it is likely that the FPGA fabric would be incapable ofsynthesizing the clocking patterns needed for the memory bus at any reasonable frequency. Thespecifics of the memory interface are somewhat beyond the scope of this project as the hardwarelayout has already been done on the development board and additionally because the Spartan6series chips contain a hard silicon block known as an Memory Controller Block (MCB) [46].This MCB implements all the necessary clocking and signalling to talk with a DRAM chip. Inreality, the FPGA contains multiple MCBs. However, due to the amount of system memoryavailable on the SP605, only one MCB is required.One note with regards to the location of the MCB. The DRAM interface has fairly tighttiming requirements and the pins which can be connected to a DRAM from an MCB are in factfixed. If one were to go ahead an implement their own FPGA to DDR link, this constraint would533.4. Processing Boardneed to be considered during the initial layout of the system along. Moreover, the terminationrequirements that can be expected from such a high speed bus would also need to be factoredin.Unfortunately, the communication bus has not been completely abstracted away and thereare still some minor idiosyncrasies of dealing with DRAM which get exposed at the MCB.Firstly, the DRAM needs to be refreshed on occasion. While this actual refresh is performed bythe MCB it does result in non-deterministic delays when interfacing with the RAM. Secondly,and somewhat more intrusively, is delay tuning. At these high rates of speed the length ofthe traces as well as the specifics of the termination resistors all come into play with regard tocorrectly reading from memory. Specifically, one needs to account for the propagation delay ofthe bits down to the nanosecond level. This specific timing adjustment is not completely takencare of by the hardware MCB and as such needs to be dealt with in user fabric. Moreover, thisalignment must be continuously tracked and adjusted to account for changes which occur overtime during operation such as thermal drift. Again we find ourselves turning to work which hasalready been completed [47]. The Xilinx IP catalogue contains devices which perform all of thisin the form of the MIG. In order to use the MIG one must have an active logic developmentlicense. However, after the core has been generated it can be synthesized without it. TheMIG produces code, which connects to the MCB as well as generates system clocking and thecalibration code for the memory. Part of this generation process, is also to configure the amountand priority of the access ports into the DDR as the MCB allows arbitration of multiple softdevices attempting simultaneous access to the memory.The overall interface into this memory system is up to six data channels, two of which canbe bi-directional and the remaining four are unidirectional. Each one of these channels containsa First in, First Out (FIFO) queue 64 elements long (two for the bidirectional channels) and afour element command FIFO. The width of the data FIFO can be configured from 32, 64 or128 bits, but as we do not need the extra word width, for this project they are configured to 32bits. The way in which one interfaces with this memory unit is via a coordination between thecommand and data FIFO. The command FIFO takes information about the transaction suchas the byte address where to base it, the amount of data to transfer (up to 64 words), and thetype of transaction for example read or write. When that transaction then executes, it operates543.4. Processing Boardon the data FIFO associated with that command. For example, if a write transaction of length16 is written into the command FIFO then it is expected that there is 16 words available inthe output data FIFO for the MCB to operate on. Likewise, there needs to be room within theinput data FIFO for any read transaction. If these conditions are not met, it results in either anunderflow or overflow respectively and the MCB errors out. The only way to recover from thiscondition is to reset the MCB. Additionally, although the address exposed by the commandFIFO is a byte level address, it must be aligned to the word size, and so for this project thelower 2 bits of said address will always be zero to ensure 32 bit word alignment. Moreover, theinterface also provides a mechanism to allow partial words to be written. This comes in theform of a byte mask. For our word size this is a mask four bits in length and is written at thesame time the data is written into the output data FIFO. If any bit in the mask is set, thenthe corresponding byte within the word is not written into memory. This interface is even moreflexible than it first appears, in that each and every FIFO (command or data) is independentlyclocked with the MCB handling any and all appropriate domain crossing.3.4.5 Embedded ProcessorAlthough VHDL and other hardware description languages are useful for describing pipe-linedprocesses,a style of continuous processing ideal for implementation upon FPGA fabric. Itbecomes cumbersome to work with when dealing with sequential logic with a large numberof states. Likewise, in most projects there exists a need to control the pipeline, perhaps re-configuring it or synchronizing it with external software. These forms of sequential or statefultasks tend to be tedious and difficult to implement in hardware and are far more amenable tothe statement based languages of a conventional computer. This project is no different, and inorder to facilitate the remote access and control aspects of the project it was decided to includea small microprocessor within the FPGA fabric. The work this processor needs to do is quiteminimal, generally reserved to interfacing and responding to the serial port and to provide aRemote Procedure Call (RPC) layer to set up parameters and collect the status of the varioushardware blocks. Given the small load of work required of the processor and the desire tokeep it’s footprint small within the overall design, it was decided to go with an 8-bit softcoremicroprocessor.553.4. Processing BoardThe embedded processor within the current design is a Navre´ processor. The Navre´ isan 8-bit microprocessor softcore designed to be an AVR clone and as such meets our smallfootprint requirements. Additionally, the AVR core is supported by the GNU gcc compiler andas such gives us a well supported and documented platform from which to work. In additionto being supported by and open source tool chain, it is released and published under the GPLand written entirely in verilog, for which we have access to the source. The Navre´ is publishedand available from [48] and is designed to implement all the classic AVR coreinstructions. Since the work the Central Processing Unit (CPU) is doing is Input Output (IO)bound to the serial port anyway, we do not need the extra performance that comes with theenhanced core.The Navre´ is internally implemented as state machine which reads the opcodes from programmemory and executes them sequentially. There is no pipelining within the core as the originalAVR core did not implement this feature. This is brought up because there are other similaropen source AVR cores such as the pAVR which do implement pipelining and are thereforefaster. As a consequence of this the Navre´ is near cycle compatible with the original AVR core.At the frequency which the 59MHz which the CPU is run at, the performance is then 59Mips,typical for most instructions. There is one notable omission from the instruction set of theclassic core compared to that of the enhanced core and that is a set of multiply instructions. Solong as the processor is restricted to command and control and not needed for any numericalprocessing, then the multiply instruction should not be needed. Moreover, this restriction is nota problem for the compiler as the AVR cores are all strict subsets of one another. This meansone only needs to select the largest core whose instructions are fully implemented. There isan additional restriction that the Navre´ does not implement any interrupts and therefore mustoperate via polling. This lack of interrupts may become a deficiency if in the future the processoris required to multi-task and handle multiple event sources. While there were other open sourceprocessors available which implement the AVR instruction set, experience has determined thatthey contained several bugs within the CPU that are difficult to work around in code.Although, the Navre´ core implements a complete CPU, it leaves the system memory andIO up to the user. The layout of the Navre´ core is detailed in figure 3.4 As we are instantiatingthis within the FPGA, we can and do utilize the block random access memory (RAM) which563.4. Processing Boardare dedicated SRAM memory modules within the FPGA.Figure 3.4: Block diagram of the soft core CPUCombined with the DRAM, there are a grand total of three separate memory spaces withinthis project. The first two blocks of memory are declared and attached to the Navre´ CPUwithin navrewrapper.vhd. The current configuration provides 32KiB of “rom” space for theprogram code and 4KiB for the CPU RAM. These memory elements are initialized by theFPGA bit stream when it configures the FPGA. The third memory space is only accessible tothe CPU via the CPU’s IO ports and is implemented by the main DRAM store.The way in which the Navre´ interacts with the external world is via a specialized IO ports.Each IO port are a single byte in width and can both read and write. The IO ports “physically”consist of an output and input bus as well as a write and read strobe for their respectivechannel. There are 64 ports available in total and are mapped to the various peripherals. TheIO mapping itself is controlled by the top level block, by connecting a new device to the IOport array exposed by the CPU one can provide interaction with CPU. A list of current portnumber allocations can be found in table 3.2.While most of the IO ports are available for application purposes, it is worth noting herethat three of them are reserved and that is the last three (61 to 63). These IO ports areimplemented internally in the processor. The first two, 61 and 62 are reserved to give access tothe 16-bit stack pointer and the last (63) gives access to the CPU status register. Unless oneis writing or debugging assembly code these ports can be for the most part ignored. However,they are reserved and may not be used for external interfacing. The remainder of the exposedIO ports will be detailed in the following sections.573.4. Processing BoardTable 3.2: CPU IO MapPort Num VHDL Tag Description0 Q COUNT ADDR Millsecond counter1 IO ADDR Access to miscellaneous user io (buttons and LEDs)2 MEM CTRL ADDR control copies to the DRAM3 MEM STAT ADDR access to the DRAM status4 MEM ADDR0 ADDR First byte for DRAM access5 MEM ADDR1 ADDR Second byte for DRAM access6 MEM ADDR2 ADDR Third byte for DRAM access7 MEM ADDR3 ADDR Fourth byte for DRAM access8 MEM DATA ADDR DRAM memory data port9 INTERFACE ADDR UART control/status register10 BUFFER ADDR Access to the UART Data FIFOs11 ADC CTRL ADDR Disable/Enable the ADC as well as control setting lines12 VGA GAIN ADDR Gain setting for the front end Variable gain amplifier13 VGA CTRL ADDR Control Items for the Variable gain amplifier61 SP LSB lower byte of the stack pointer62 SP MSB upper byte of the stack pointer63 SREG CPU Status registerMillisecond CounterMillisecond counter is a continuously ticking register, it starts when the system boots up androlls over every 256 milliseconds. This allows the CPU the deal with typical interface difficultiessuch as timeouts.IO RegistersFor debugging or other interactions, it is useful to be able to expose a set of general purposeindicators and controls. The SP605 development board has included on it: user controlledLEDs, general purpose buttons, dip switches, and a single inline pin header with user IO’s onit. While the SP605 exposes a fair bit more IO’s, the number was restricted to easily fit into asingle byte interface, as the number of ports on the CPU are limited and should be preserved forapplication purposes. As such the user interface was implemented as a single byte IO registerthat has a separate context depending on whether the CPU perform a read or a write. Upon aRead, the Upper nibble is filled with the reading from the dip switches while the lower nibblecontains the state of the Buttons. When a write is performed instead, the upper nibble setsthe state of the Header pins while the lower nibble sets the state of the LEDs.583.4. Processing BoardTable 3.3: IO bit mappingBit 7 6 5 4 3 2 1 0Read Switch3 Switch2 Switch1 Switch0 Button3 Button2 Button1 Button0Write Header3 Header2 Header1 Header0 LED3 LED2 LED1 LED0CPU DRAM interfaceThe CPU DRAM interface gives the CPU the ability to communicate with the attached DDRmemory via the CPU’s IO ports. As the CPU is 8 bit and the memory exposes 128 MiB via a32 bit bus, the connection cannot be a simple memory mapped connection. Additionally, thisinterface provides a way to control transfers from the ADC to the system memory. There are4 major components to the interface, the address window, the data register, the control port,and the memory status. The general way that the system operates is as follows:1. ensure that a current transaction is not pending, which may interfere with your operation.2. provide the address on that you wish the system to operate in the ADDRn registers.3. (Optionally) write the data to operate on into the DATA register.4. write in the command word into the CTRL register to initiate the operation.5. (Optionally) wait for the command to complete and read result from DATA register.The DDR RAM requires a 32 bit address to be fully accessible from the CPU and the memoryaddress registers provide this link with ADDR0 and ADDR3 being the LSB and MSB respec-tively. These registers are used to convey the address to and from the memory unit for allthe memory access functions and provide byte level addressing into the DDR RAM. Unlike theDRAM control block, this address is byte level and does not need to be word aligned as thatlogic is handled in hardware. With the addressing registers providing a window into the mem-ory, the data register provides a general purpose byte store to convey information to and fromthe memory control unit. For example, when performing a read operation, this is the registerwhere the final byte is read from into the CPU. There are currently 3 operations implementedwithin the memory control unit detailed in table 3.4As a matter of convenience, the address register is automatically incremented after a reador write operation is performed so that a contiguous section of memory can be read out without593.4. Processing BoardTable 3.4: Memory operationsName Code DescriptionSingle Write 0x00 Writes a single byte into the specified addressSingle Read 0x01 Reads a single byte from the specified addressADC Transaction 0x02 Begins a transfer of ADC samples, directly into memoryconstantly rewriting the address. For both the read and write operations the data register isused to convey the data read from or to be written to memory respectively. However, whenperforming an ADC transaction, the data register takes on a subtly different context. Ratherthan convey the data to be written into memory, it contains the number of samples to capture.A single byte is not large enough to account for a total memory capture, and therefore thememory is instead broken up into smaller blocks 512 KiB in size. The data register then shouldbe filed not with the number of samples but the number of blocks. Additionally, it would beuseless to issue this command with a length of zero, and therefore the number of blocks readis the number in the data register plus one. This allows a transaction to be from 1 to 256blocks in length. These blocks can then be subsequently read out by the use of the single readinstructions.In order to determine when one can issue additional commands or know when the data isvalid, the status register provides a few bits that permit the CPU to re-synchronize with thememory. The details of this status register is provided in 3.5.Table 3.5: Memory StatusBit 7 6 5 4 3 - 0Read Transaction ADC Transfer reserved Calibration reservedThere are currently only 3 bits implemented within the status register. The Calibration bitindicates whether the MCB is currently within one of it’s calibration stages. These calibrationstages occur only at start-up and once cleared should not be re-entered unless the MCB isreset. If it is, then interfacing with the memory can have unknown consequences and the hostprogram should wait until it is complete to read or write from memory. The transaction bitindicates that the memory control block is currently executing a transaction such as a reador a write, or it is starting an ADC DMA operation. The host program should wait for anytransactions to complete before it considers the command to have taken effect, or it interfaces603.4. Processing Boardwith the registers in any way. The final status bit is the ADC Transfer bit, and this indicatesthat a previously issued DMA transaction is running writing ADC samples into memory. It isacceptable to issue a read or write but not another DMA transaction while the ADC Transferbit is set. Bear in mind there may exist a race condition if one attempts to read or write toan address which is queued up to be over written by the DMA transfer. Finally, the ADCTransfer bit will not be set until the transfer command has finished executing. Therefore, hostprograms wishing to issue a DMA transfer and then wait for completion it first must wait forthe Transaction to complete and then the ADC Transfer.UART interfaceThe serial port attached to the embedded processor provides a communication link to externalcomputers and resources. The settings for the serial link are hard coded and provided in Table3.6.Table 3.6: UART SettingsName ValueBaud 921600Width 8 bitsStop 1 bitsParity NoneFlow Control NoneThe serial transceiver code itself is provided by Xilinx for integration into Spartan6 FPGAs.Although the baud rate can be adjusted via a single constant within the VHSIC HardwareDescription Language (VHDL) code, adjusting the other serial parameters would require reim-plementing the serial transceivers. Moreover, there is not any handshaking implemented eventhough the signals have been plumbed through from the FTDI transceiver chip into the VHDLcode. As such, should handshaking become necessary, the hardware is available to implementit, but requires a modification to the VHDL code in order to be supported. As the transceiversfrom Xilinx include a small FIFO for the data transmission, there are a plethora of signalsexposed to ensure that no buffer overflows or overruns within the transceiver. Additionally,should one occur, it is detected and exposed to the CPU. There are two registers that controlthe serial transceiver and they are located at INTERFACE ADDR and the BUFFER ADDR.613.4. Processing BoardThe buffer IO port gives access to the data FIFO, wherein a read pulls the next byte off theFIFO and a write pushes a new byte onto the FIFO. The second IO port labeled as the interface,exposes the status signals for the UART as shown in table 3.7.Table 3.7: UART control bit mappingBit 7 6 5 4Read TX ERROR TX FULL TX HALF FULL TX DATAWrite TX ERROR reserved reserved reservedBit 3 2 1 0Read RX ERROR RX FULL RX HALF FULL RX DATAWrite RX ERROR reserved reserved reservedThe ERROR bits expose whether a transmitter buffer overrun or a receiver buffer under runhas occurred. They can be cleared by writing zeros into their respective positions. The FULLbits indicate that there is no more room in the FIFO for new data. Likewise the HALF FULLbits indicate that the FIFOs are half full and the DATA bits indicate that there is data presentwithin the FIFO.ADC ControlThe ADC that we are using to digitize the received data [43], has some configuration optionsthat may need to be changed for different modes of operation. These controls are exposed inthe ADC CTRL port. Additionally, some of the constructed infrastructure particularly aroundthe clocking of the ADC is also exposed in the same location. The mapping of these bits totheir IO port is detailed in table 3.8.Table 3.8: ADC control bit mappingBit 7 6 5 4 3 2 1 0- LOCK resrvd resrvd resrvd DFS DCS SFDR SWITCHThe locked bit is read-only and indicates whether or not the PLL responsible for driving theADC clock has locked and stabilized. The Data Format Select (DFS) bit sets whether the datareturned from the ADC is a signed or unsigned 16 bit integer. When set the data returned issigned and likewise when cleared it is unsigned. This is more of a convenience flag as the twoforms can be converted from one to the other fairly easily. The DCS bit enables or disables623.4. Processing Boardthe Clock Duty Cycle Stabilizer, the operation of which is detailed in the ADC datasheet [43].The recommended setting is 0, which corresponds to enabled. The next bit, SFDR controlsanother exposed line detailed in the datasheet. The purpose of this bit is to change the powerconsumption within the core of the ADC optimizing the SNR for different bandwidth ranges.For signals below 40MHz or above 215MHz, and this is ostensibly the range we are operating in,it should be disabled. The inclusion of control of this bit is for flexibility and experimentationwhen under different operating conditions. Finally, we reach the last exposed bit that is theSWITCH bit, this enables or disables the clock to the ADC, which effectively shuts it down.Upon restarting an ADC that was subsequently disabled, the LOCK bit should be polled towait for the ADC to fully start up.VGA interfaceIn order to account for the large swings in dynamic range that the radar may be exposed to, andspecifically the small signal level that one will receive as a reflection. The Front end amplifierdescribed in section 3.3.2 can be fully configured by the host program. In order to provide thiscontrol, two IO ports are exposed to the host program. The VGA STATUS register exposesmiscellaneous control bits over the front end amplifier, the function of which are described intable 3.9.Table 3.9: VGA status registerBit 7-4 3 2 1 0Read resrvd Rear LNA mode Front LNA mode vga power vga busyWrite resrvd Rear LNA mode Front LNA mode vga power resrvdThe Rear LNA and Front LNA mode bits, toggle the RF switches present in the front endamplifier. When the bits are set, the RF switches are configured in such a way as to ensurethat the received RF signal is directed through the corresponding amplifier, and when clearedthe RF switches are configured in such a way as to have the amplifier bypassed. The FrontLNA is the amplifier closest to the input connector. The VGA power bit, enables or disablesthe VGA. The VGA BUSY bit indicates whether or not the serial transmitter, which is used towrite the gain code into the VGA, is currently transmitting and if so the host program shouldnot attempt to write a new gain code. This brings us to the second port, the VGA GAIN port.633.4. Processing BoardWriting to this port issues a serial write into the VGA changing its gain. As specified in theVGA datasheet [49], the upper bit of the gain command sets the mode for the VGA either Highwhen set or Low when clear. The lower 7 bits specify the gain code which when multiplied bythe corresponding gain factors set the overall gain of the VGA. The gain factor for high gainmode is 0.409, while the gain factor for low gain mode is Build SystemThe build system for all of this is not complicated, however it is worth going over as it may be adifficult introduction for those not well vested in the Makefile build system. First and foremost,the build system requires a Linux Operating System (OS) although it may work on other *nixsystem. It has been tested in both Gentoo and Debian, and has worked in both. The secondcomponent of the tool chain is the Xilinx ISE tools. The ISE toolkit is currently at version 14.7at the time of this writing and it appears as though this will be the last version as Xilinx isputting it’s clout behind the Vivado tool chain. Unfortunately, Vivado only synthesizes for theseries 7 and later chips. As was mentioned previously, the connector used to interface with thereceiver circuits should be compatible with other dev kits such as the Zed board which uses aseries 7 Zynq processor. Never the less, in order to build for the Spartan-6, the tool chain mustremain the ISE toolkit.In addition to the tools for synthesizing the hardware, a compiler for the AVR processoris also required. The compiler currently configured for this project is avr-gcc. In Gentoo thiscan be obtained via crossdev and within Debian and its derivatives it can be found within thestandard repositories.The build system is entirely configured with Makefiles and does not use the Xilinx GUI forcompilation. It does, however, call the Xilinx tool chain components and hence the dependency.Before building be sure to source the appropriate Xilinx setting file into the terminal, these canbe found within the install directory of ISE and are needed to place the Xilinx tools into thedefault path. The setting file should not be sourced by default as it overwrites certain librarypaths and can break some of the installed programs. To avoid this issue, the Makefile can sourcethese settings for you, however there needs to be an environment variable (XILINX SETTINGS)set pointing to the appropriate shell script for the system. Calling make synth from the top643.4. Processing Boarddirectory will then begin the compilation and synthesis.Make then proceeds to synthesize the hardware, and it follows the standard procedurefor the hardware design. First the Hardware Description Language (HDL) files are compiledinto a basic netlist, this step also preforms the syntax checking on the VHDL files and someoptimizations like eliminating redundant signals. Second is the map stage, this stage takes thevarious logical descriptions from the previous stage and maps them onto the various primitivesfound in the FPGA like the slices, DSP or block ram. Third is place and route. It is thisstage that takes the most time, determining where each item should go and how it should beconnected to meet timing closure. The final step to creating a workable FPGA file is to renderthe final design down into a bitstream. However, in order to fully synthesize the bitstream itrequires the result of the compiled C code. This is because the CPU Read Only Memory (ROM)is implemented in FPGA block ram and the initialization values for that block ram are set bythe Executable and Linkable Format (ELF) file produced during compile. Therefore, at thisstage the FPGA build is halted and waits for the C code to finish compiling. The C code iscompiled with avr-gcc with the use of a custom linker script to describe the memory layoutin the FPGA. The resulting ELF file is then picked back up by the FPGA build system, andconverts the ELF file into the initialization values for the block ram. The result of all this isa bit stream file that can be programmed directly into the FPGA fabric, however, in doing soit would not be persistent and would be lost on a reboot. Therefore, the build system is alsocapable of using the bitstream to create an MCS file that can be used to program the flash chipon the SP605 that can maintain it’s memory between reboots. The makefile build system, likemost build managers, will only rebuild what has changed and those files that are affected bythe changes. By placing the ELF file integration late into the build system, the FPGA doesnot need to be re-synthesized if only the CPU code changes.In order to program the new code into the SP605 dev board, invoke make temp or makeperm to program just the bitstream or the flash respectively. These both use impact (which ispart of the Xilinx tools) and program via the integrated JTAG USB connector on the SP605.653.5. Summary3.5 SummaryLet us conclude this chapter with look back at what we have covered. We covered the individ-ual hardware blocks that make up this novel radar, including the digital and analog buildingblocks. Additionally, we covered the capabilities of the individual pieces. It is at this pointwe can tally an approximate cost of the design, the most expensive component of which is theSP605. Taken together this entire radar is approximately $3000 CDN. When compared to acommercially purchased radar which typically retails for upwards of $20000 CDN [50], this issignificantly cheaper. Moreover, because the core of the radar is a programmable, an FPGA,we can dynamically reconfigure the unit for different codes and frequencies as the need arises.As a research radar, this re-configurability is a valuable property.At this state of the development process we have not fully completed the radar. However,individual items have been validated as working according to specifications. The receiver boardhas been tested and characterized, and is working as expected. Moreover, unit testing of thevarious software elements confirms those portions are working as designed. Yet to be done is afull test of our transmitter circuitry and fibre link. Following this testing, we can perform thefull system integration and test the radar as a completed unit. In the next chapter we shallsimulate this radar’s performance and compare that performance to the design targets we havepreviously set out for ourselves.66Chapter 4SimulationIn this chapter we set up a simulation of the radar system to serve as a proxy for the completeddevice. This simulation is provided in order to validate the physical design as well as to serveas a comparison between some the choices of digital sequence that may be used. In order toverify the design performance against expected theory, we will simulate the device against amock impulse response. This choice of a linear simulation is justified by the fact that mostGPR post processing algorithms already assume a linear medium [51–54]. To be a relevantcomparison, noise sources from the analog front end as well as the expected dynamic rangemust be included.To set up our simulation, it must meet the requirements which would be expected of a typicalGPR. To this end, we will will choose simulated response with an attenuation and spatialresolution which one might find in practice. A typical loss factor is approximately 1 dBm−1of depth, including both spreading losses as well as attenuation. Moreover, we wish to makesure that we have sufficient geometric resolution, and so reflections need to be sufficiently closethat they may interfere. Therefore, we have set up our impulse response to provide a reflectionevery 6m with the amplitude halving each reflection and we will simulate to a depth of 300m.This will provide both sufficient richness to see if we can discriminate between pulses as wellas a large enough dynamic range to be relevant for GPR. The response is normalized to thestrong immediate reflection at x=0. This strong reflection will always exist as there is a directwave which travels from the transmitter antenna across the surface to the receiver through air.Moreover, it is normalized to this figure because the front end can always increase the gain untilthis direct wave becomes the dominate signal. The means that the amplitude of the impulsedecays exponentially from 0dB to a maximum of 300 dB which we shall set as our limit for thepurposes of this simulation. This impulse response is show in figure 4.1.67Chapter 4. Simulation0 50 100 150 200 250 300−400−350−300−250−200−150−100−500Simulated Reflection SignalStrength (dB)Amplitude (m)Figure 4.1: Simulated impulse response used for validationIn order to prevent over ranging of our simulated ADC, the input level is set to 14000 of amaximum of 32767 (signed 16bit number), a level chosen because it provides an input to theADC close its maximum. Furthermore, in reference to the details presented in section 3.3.3, weshall quantize the output of the simulation to a 16bit signed integer and apply a single-endednoise amplitude of 16 levels as a white noise contaminate. This level is in accordance withthe differential value of 8 as well as inline with the ENOB of the ADC. Moreover, to preventany additional noise which may be due to numeric precision, the entire simulation is performedutilizing 128bit integers which are capable of storing the full dynamic range. A flow diagramof the simulation is presented in figure 4.2We now continue on to take the our prepared simulation and apply it to the two forms ofcoded sequences which we have previous introduced, that of the Golay and the M-sequence.We perform the simulation with these two different codes at two different lengths and presentthe results. The minimum sequence length which can be used to acquire this response is 1024due to the fact that the response itself is 600 points long. This corresponds to a code order of10. The results of a single interrogation of 1024 values is provided in figure 4.3.Given our input parameters, one can see that the non-coded impulse response is capable68Chapter 4. SimulationFigure 4.2: A flow diagram of the simulationof recovering the 10th reflection. This is inline with the initial SNR of the amplifier. On theother hand, it is interesting to see that the M-Sequence response is in fact worse than the rawimpulse and can only recover up to the 4th reflection. This is because the 1/N noise floor ofthe M-Sequence is not in addition to the SNR already present but directly on top of the signaland relative to the peak signal level. However, due to the coding gain provided by the Golaysequence, we have access to the 16th response. Also visible is the two noise floors of 95 dBand 30 dB, which agrees nicely with predicted values. With an initial amplitude of 14000 levelsagainst an 8 level noise floor, this gives us an initial input SNR of 65 dB. The coding gainafforded to us by the order 10 sequence is an additional 30 dB. This brings us to a total of95 dB for the Golay code and the original 30 dB for the M-Sequence because it does not gainthe benefit of the initial SNR. The remaining difference between the displayed computed SNRis due to the fact that these GCS come in a pair and therefore an extra 3dB is obtained fromthis. As we apply longer and longer sequences, we shall see the noise floor continues to decreaseby the expected 10*log10(N). We take as an example the result of a 27th order sequence.As can be seen in the figure 4.4, which displays the results of a 27th order Golay Code, thenoise floor has shifted to 120dB, which is consistent with the applied code length of 134217728.This gives us a visibility of approximately 110m into the earth. Indeed, the decrease in noisefloor is log linear with the increase in the sequence order.This decrease in noise floor can be more precisely seen in 4.5. The trend in the noise floorreduction is the expected 3 dB per order. This corresponds to approximately 3m of additional69Chapter 4. Simulation0 50 100 150−200−150−100−500Order 10 Impulse Recovery− Code ComparisonReflection Strength (dB)Position (m)  MseqGolayRaw ImpulseFigure 4.3: Recovered response from a order 10 sequencedepth per increase in order. It should be noted however that this increase in filter order inequivalent to a doubling in duration. However, the duration of this particular sequence at ourexpected 50MHz chip rate is only 2.68 s. Moreover, as any variation within the earth is likelyto proceed on a minimum timescale of 20min, we are free to increase our code length to thisbound. Riding up to this limit would give us a code order of 36. However,it is beyond order27 where simulation becomes prohibitive upon an ordinary CPU, and as such we limit ournumerical simulation to this length. Continuing the existing trend from −150 dB gives us agrand total of −180 dB or 180m of visibility.One final caveat to place on these results is the previously mentioned normalization. Theamplitude values were chosen such that the direct reflection saturated the amplifier, Again, thiscan always be true because we can increase the front end gain until it saturates. The assumptionin this simulation is that there is no isolation between the transmitter and the receiver andtherefore is no attenuation between the two. Indeed, if there were such attenuation, that extradynamic range would be added to the maximum achievable depth.70Chapter 4. Simulation0 50 100 150−200−150−100−500Order 27 Impulse Recovery − Code ComparisonReflection Strength (dB)Position (m)  MSEQGolayRaw ImpulseFigure 4.4: Recovered response from a order 27 sequence71Chapter 4. Simulation5 10 15 20 25 30−200−150−100−500Noise Floor ReductionNoise Level(dB)Sequence Order  MseqGolayFigure 4.5: Noise floor reduction as a function of sequence length and code type72Chapter 5ConclusionsIn chapter 2, we discussed some of the design considerations for building a GPR. This covered,the basic parts contained within a prototypical GPR. The processing steps necessary for GPRof various types was also discussed. Additionally, some of the history and applications for GPRwas covered.In chapter 3, we discussed the specific design and implementation details for the GPR whichis the subject of this treatise. The breakdown of the radar into its constitute components wasdetailed. The major physical components of the radar: the amplifier, the receiver board andthe processing board were described. Specific attention was paid to the form of the radar as itis currently implemented.In chapter 4, we conclude with a simulation of the principles behind the design. Thesimulation presented includes the relevant details of the radar currently under construction,including noise floor and resolution. This simulation was applied against a simulated impulseresponse to provide the relevant details for the capabilities of the radar.For the remainder of this document, we will discuss the accomplishments resulting fromthis project. As well as detail some of the work that is yet to be done in order to create a fullyfunctional prototype.5.1 ResultsThe results of this effort have been two fold. First, we have analyzed the details of the radarin simulation to find its maximum performance. Second, there is a completed set of radarhardware capable of meeting the performance specifications.The performance of GPR is a fluid thing, depending on the time one is willing to wait andthe depth resolution required. The radar’s minimum performance provides a dynamic sensing735.2. Future Workrange of 100dB. As was noted in section 4, this is maximal receiver dynamic range and onecan add to this the isolation factor between the transmitter and receiver. As for maximalperformance, should one choose to wait for the total duration of 30 minutes, it is possible toretrieve and extra 80 dB on top of the base. This makes for a maximum receiver dynamic rangeof 180dB. Both of these figures either meet or exceed our initial target set out in section 1.2.Moreover, this radar can be constructed at a cost that is far less than conventional GPR asstated in section 3.5.It is clear however that there are certain advantages to utilizing Golay codes over both acode less radar as well as one which utilizes M-Sequences. The results show that although onereceives the same performance as averaging when increasing the code length, the Golay codestarts at a superior position due to the fact that its SNR is in addition to the existing SNR.This is in contrast to the M-Sequence, which provides a total SNR equal to its code length.Also completed is a set of hardware required to implement the radar designed in this treatise.The receiver board is both constructed and tested. The transmitter board is both designed andconstructed. Moreover, sufficient code has been written in both hardware and software tobootstrap the system. Also completed is the basic infrastructure the take a set of data with thehardware. However, there is still work yet to be done and this is covered in the next section.5.2 Future WorkDespite all that has been accomplished so far, there is still more work to be completed. Thiswork can be broken down into two separate elements, hardware and code.From a hardware perspective, there are a few elements which must be tested. The fibreoptic link between the receiver board and the transmitter board is yet to be tested. This willconsist of verifying both the amplitude integrity and bandwidth of the link to meet the desiredspecifications. Moreover, the transmitter board itself has not yet been put into service and itsoperation needs to be verified. Once these two remaining hardware pieces are in place, the nextstep will be to perform an overall system validation to ensure that all the elements are workingtogether. Finally, the remaining software needs to be integrated into the device.The software currently on the radar is only capable of gathering a fixed length sample745.2. Future Workand transferring it to a host computer. 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Ndt& E International, 57:74–84, 2013.81Appendix AReceiver Board SchematicsThe schematic design for the receiver board is included below.82AppendixA.ReceiverBoardSchematics1122334455A AB BC CDate: 8 aug 2011KiCad E.D.A.  Rev: Size: A4Id: 1/8Title: File: main.schSheet: /AGNDSIG1GND2J5H9173CT−NTSIG1GND2J4H9173CT−NTFilterfilter.schV+ OutV− InV+ InV− OutDataOut2DataOut.schdigitalAGND12P1 CONN_2DataOutDataOut.schdigitalAnalog Front endAnalog.schVin−Vin+DataCLKLTCHAInVOCMVGA_EnableSW2−SW2+SW1−SW1+PowerPower.schADCADC.schDCS ModeDFSSFDRV+V−OR+OR−DCO+DCO−CLK−CLK+DM[0..15]DP[0..15]VrefBoard ConnectorFMC_Connector.schDM[0..15]DP[0..15]DCO−DCO+CLK−CLK+OR−OR+SFDRDCS_ModeDFSDataCLKLTCHOutputVGA_EnableSW2−SW2+SW1−SW1+Output283AppendixA.ReceiverBoardSchematics1122334455A AB BC CDate: 8 aug 2011KiCad E.D.A.  Rev: Size: A4Id: 5/8Title: File: Analog.schSheet: /Analog Front end/AGNDAGNDR180RSIG1GND2J7H9173CT−NTSIG1GND2J6H9173CT−NTR190RR510RPWR_FLAGPWR_FLAGPWR_FLAGPWR_FLAGC4710uFC5210uFC54100nFAGNDC56100nF+12VL7 1uHAGNDAGNDC59100nF+C6010uFC55100nFAGNDAGNDB1(J3)1GND2B2(J2)3V14A(J1)5V26U11 AS179−92LFC58100nFC57100nFIN1GND2GND3GND4DC5GND6OUT8U9 MAN−1LNSW2− SW2+B1(J3)1GND2B2(J2)3V14A(J1)5V26U10 AS179−92LFIN1GND2GND3GND4DC5GND6OUT8U6MAN−1LN+C4510uFAGNDC49100nFL5 1uHC43100nFL6 1uHC51100nFC53100nFC44100nFC50100nFC48100nFC46100nFVGA_EnableR410RAGND AGNDL41uHAGND AGND+3.3VAGND AGND+12V+3.3VC42100nFVOCMDataCLKLTCHAGNDVin−Vin+SW1−SW1+AGNDAGNDAGNDAGNDAGNDAGNDAGNDR668RAInINHI1ICOM2VCCI3PWUP4VOCM5VCCO6OCOM7OPHI8OPLO9OCOM10VCCO11LTCH12CLK13Data14ICOM15INLO16ICOMEPU7AD8370B1(J3)1GND2B2(J2)3V14A(J1)5V26U8AS179−92LFB1(J3)1GND2B2(J2)3V14A(J1)5V26U5AS179−92LF84AppendixA.ReceiverBoardSchematics1122334455A AB BC CDate: 8 aug 2011KiCad E.D.A.  Rev: Size: A4Id: 2/8Title: File: filter.schSheet: /Filter/L13122nHL15270nH4 pole butterworth with 100 ohm differential source and load Impedance,and a cut off of 50 MHzC7643pFL14270nHL12122nHC7516pFV− OutV+ OutV− InV+ In85AppendixA.ReceiverBoardSchematics1122334455A AB BC CDate: 8 aug 2011KiCad E.D.A.  Rev: Size: A4Id: 7/8Title: File: ADC.schSheet: /ADC/PWR_FLAGPWR_FLAGPWR_FLAGR310RR17100RC1210uFC2010uFC710uFC110uF+5VL1 1uHC11100nFC10100nFC9100nFC8100nFL2 1uHC2910nFC27100nFC25100nFC23100nFC21100nFC19100nFC18100nFC17100nFC16100nFC15100nFC14100nFC13100nFC410uFC3710nFC34100nFC35100nFC33100nFC32100nFC31100nFC30100nFC36100nFC28100nFC26100nFC24100nFC22100nFAGND+3.3VAGNDDGNDVDDC5100nFC6100nFC3100nFR210R+3.3V +3.3VL3 1uHVrefDCS ModeDFSSFDRV+V−OR+OR−DCO+DCO−CLK−CLK+DM[0..15]DP[0..15]DM15 DM14 DM13 DM12 DM11 DM10 DM9 DM8 DM7 DM6 DM5 DM4 DM3 DM2 DM1 DM0DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 DP0DCS_Mode1Output_Mode3DFS4LVDS_Bias5AVDD16Sense7Vref8AGND9REFT10AVDD120AVDD230CLK+40D0+50D5+60D8+70D12+80OR+90REFB11AGND21AVDD231CLK−41D1−51D6−61D9−71D13−81AGND91AVDD212V+22AVDD132AGND42D1+52D6+62D9+72D13+82AVDD192AVDD213V−23AVDD133AVDD143D2−53DRGND63D10−73D14−83AVDD193AVDD214AGND24AVDD134AVDD144D2+54DRVDD64D10+74D14+84AVDD194AVDD215AVDD225AVDD235AVDD145D3−55D7−65DRGND75D15−85AVDD195AVDD216AVDD226AVDD136AGND46D3+56D7+66DRVDD76D15+86AVDD196AVDD217AVDD227AVDD237DRGND47D4−57DCO−67D11−77DRGND87AVDD197AVDD118AVDD228AVDD138DRVDD48D4+58DCO+68D11+78DRVDD88AGND98AVDD119AVDD229AGND39D0−49D5−59D8−69D12−79OR−89AGND99SFDR100AGNDPADU1AD9461AGNDAGNDR13k74RAGNDAGNDC2100nFAGND AGNDDGND86AppendixA.ReceiverBoardSchematics1122334455A AB BC CDate: 8 aug 2011KiCad E.D.A.  Rev: Size: A4Id: 8/8Title: File: FMC_Connector.schSheet: /Board Connector/Output2DM15 DP15SW2− SW2+VGA_Enable+2.5VOutputDataCLKLTCHSW1− SW1+SFDR DCS_ModeDFSOR− OR+DCO− DCO+CLK− CLK+DM[0..15]DP[0..15]DM14DM13 DM12DM11DM10 DM9 DM8DM7 DM6DM5 DM4 DM3DM2 DM1 DM0 DP14DP13 DP12DP11DP10 DP9 DP8DP7 DP6DP5 DP4 DP3DP2 DP1 DP0DGNDVDD+1.2VGNDC1PG_C2MD1GNDG1VREF_A_M2CH1DP0_C2M_PC2GNDD2CLK1_M2C_PG2PRSNT_M2C_LH2DP0_C2M_NC3GNDD3CLK1_M2C_NG3GNDH3GNDC4GBTCLK0_M2C_PD4GNDG4CLK0_M2C_PH4GNDC5GBTCLK0_M2C_ND5GNDG5CLK0_M2C_NH5DP0_M2C_PC6GNDD6LA00_P_CCG6GNDH6DP0_M2C_NC7GNDD7LA00_N_CCG7LA02_PH7GNDC8LA01_P_CCD8GNDG8LA02_NH8GNDC9LA01_N_CCD9LA03_PG9GNDH9LA06_PC10GNDD10LA03_NG10LA04_PH10GNDC20LA17_CC_PD20GNDG20LA15_NH20SCLC30TDI_BUFD30LA29_PG30GNDH30GNDC40VCC3V3D40GNDG40VCC2V5H40LA06_NC11LA05_PD11GNDG11LA04_NH11GNDC21LA17_CC_ND21LA20_PG21GNDH21SCAC31TDOD31LA29_NG31LA28_PH31GNDC12LA05_ND12LA08_PG12GNDH12LA18_P_CCC22GNDD22LA20_NG22LA19_PH22GNDC32VCC3V3D32GNDG32LA28_NH32GNDC13GNDD13LA08_NG13LA07_PH13LA18_N_CCC23LA23_PD23GNDG23LA19_NH23GNDC33TMS_BUFD33LA31_PG33GNDH33LA10_PC14LA09_PD14GNDG14LA07_NH14GNDC24LA23_ND24LA22_PG24GNDH24VCC3V3C34TEST_LD34LA31_NG34LA30_PH34LA10_NC15LA09_ND15LA12_PG15GNDH15GNDC25GNDD25LA22_NG25LA21_PH25VCC12_PC35GNDD35GNDG35LA30_NH35GNDC16GNDD16LA12_NG16LA11_PH16LA27_PC26LA26_PD26GNDG26LA21_NH26GNDC36VCC3V3D36LA33_PG36GNDH36GNDC17LA13_PD17GNDG17LA11_NH17LA27_NC27LA26_ND27LA25_PG27GNDH27VCC12_PC37GNDD37LA33_NG37LA32_PH37LA14_PC18LA13_ND18LA16_PG18GNDH18GNDC28GNDD28LA25_NG28LA24_PH28GNDC38VCC3V3D38GNDG38LA32_NH38LA14_NC19GNDD19LA16_NG19LA15_PH19GNDC29TCK_BUFD29GNDG29LA24_NH29VCC3V3C39GNDD39VCC2V5G39GNDH39J1 SP60587AppendixA.ReceiverBoardSchematics1122334455A AB BC CDate: 8 aug 2011KiCad E.D.A.  Rev: Size: A4Id: 4/8Title: File: DataOut.schSheet: /DataOut/PWR_FLAGC7010uFDGNDA01B02O03A14B15O16GND7O38B39A310O211B212A213Vcc14U1474ACT00R933RR833RVCCC67100nFDGNDC68100nFL10 1uHDGND DGNDC69150pFR733RR1013RR11100RdigitalDGNDANODE2CATHODE3ANODE6ANODE7J2HFBR−1414Z88AppendixA.ReceiverBoardSchematics1122334455A AB BC CDate: 8 aug 2011KiCad E.D.A.  Rev: Size: A4Id: 6/8Title: File: Power.schSheet: /Power/L171uHL161uHPWR_FLAGPWR_FLAG+12VAGND123456P2 CONN_6VCCDGNDC66100uFDGNDVIGNDVOU13V7805−2000C41100uFC40100uFC39100uFC38100uFL91uHAGNDAGNDGNDVOVIU4AP1084GNDVOVIU3AP1084+5VVIGNDVOU2V7806−2000+3.3VAGNDAGNDAGNDAGND AGND+12VAGNDDGND89Appendix BTransmitter Board SchematicSchematic diagram for the power transmitter board.90AppendixB.TransmitterBoardSchematic1122334455A AB BC CDate: 25 jul 2015KiCad E.D.A.  Rev: Size: A4Id: 1/1Title: File: Driver.schSheet: /123 46T1COILTRANS−SEC_CTCoded Sequence Output DriverVee5PWDN16DGND8PWDN09IN10IN11OUT12Vcc13U4BAD8018OUT2IN3IN4Vee5PWDN16DGND8PWDN09Vcc13U4AAD8018C18100nF+C1710uFP22P21P20P19P18R8500RR7500RSDVCCSHDWN0SHDWN11 23 45 67 89 1011 12P8CONN_6X2P10P9R15620RR16620RP12P11R186R25R176R25Amplified+Amplified−R1110kRVrefVrefC14100nF+C1310uFVCCR1310kRVrefVCCC9100nFR4100RR3100RSHDWN1SHDWN0SDC10100nFC12100nFAmplified−Amplified+R9120RR10826R1 2D1LEDR14100RR12100RR63kRR5100RVDDEN1Din2Din3Vref4SDin5GND6SD7Dout8Dout9Vcc10U2SY88813VP17P16P15P14P13Output2GND3Vcc6GND7J1HFBR−24X6ZP4P5P3 P6P7M1PROTOBOARDVCCVDD+C110uFC2100nF+C710uFC8100nFVin1GND2Vout3U1REGULATORDPAKVin1GND2Vout3U3REGULATORDPAK+12V+C1510uF12P1CONN_212P2 CONN_2C16100nF+C1110uFL1INDUCTORL2INDUCTORR14R7C3100nFC6100nFVCC+C410uFR2 4R7C5100nF91


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