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Investigation of high-performance DC-DC converters for plug-in hybrid electric vehicle battery chargers Gautam, Deepak 2014

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INVESTIGATION OF HIGH-PERFORMANCE DC-DC CONVERTERS FOR PLUG-IN HYBRID ELECTRIC VEHICLE BATTERY CHARGERS  by Deepak Gautam  M.A.Sc., University of Victoria, 2007  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF  DOCTOR OF PHILOSOPHY in THE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES (Electrical and Computer Engineering)  THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver)  April 2014  © Deepak Gautam, 2014  ii Abstract Plug-in Hybrid Electric Vehicles (PHEVs) and Electric Vehicles (EVs) are an emerging trend in automotive circles, and consumer interest is growing rapidly. With the development of PHEVs, battery chargers for automotive applications are becoming a large market for the power supply industry. The most common charger power architecture includes an ac-dc converter with power factor correction (PFC) followed by an isolated dc-dc converter. As a key component of a charger system, the dc-dc converter must achieve high efficiency and power density.  This dissertation mainly focuses on the dc-dc converter stage only and in order to meet high efficiency, high power density and a cost-effective solution, various dc-dc topologies have been investigated and proposed for battery charging application. In this research work two new full-bridge dc-dc converter topologies (one with inductive and another with capacitive output filter) operating with a trailing edge pulse width modulation (PWM) gating scheme are investigated. Also for higher power (>2 kW) battery charging application, another two new interleaved dc-dc converter topologies using full-bridge with capacitive output filter (one with bridge rectifier diodes and another with voltage doubler rectifier) are also investigated. Detailed operating principle and steady state analysis for different modes of operation, step-by-step design procedure, simulation, experimental results and performance evaluation with various semiconductor devices for each of these topologies are presented in this thesis. The results show that the performance, in terms of efficiency, size and cost for the full-bridge converter with capacitive output filter is superior to that with inductive output filter. Moreover the dc-dc converter with capacitive output filter overcomes some of the major issues such as high voltage ringing on the rectifier diodes and duty-cycle loss, which are present in the converter with inductive output filter.   iii Preface I am the lead investigator for this research work, responsible for performing literature survey, topology investigation, theoretical analysis, design, simulation and experimentation. This work was done under the guidance of my thesis supervisor Dr. William G. Dunford of UBC, Vancouver and co-supervisor Dr. Wilson Eberle of UBC, Okanagan campus. This work was also supervised by Dr. Fariborz Musavi and Mr. Murray Edington of Delta-Q Technologies Corp. Chapter 1: In this chapter, most of the figures and tables are obtained from various sources and they have been appropriately cited. Some sections of the chapter are also modified from previously written introductory material from my master’s thesis entitled “Soft-Switched DC-to-DC Converters for Power Conditioning of Electrolyzer in a Renewable Energy System” (2006) completed at the University of Victoria. Chapter 2: Content in this chapter has been published in:  [1] D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "An Automotive On-Board 3.3 kW Battery Charger for PHEV application," Proceedings of IEEE Vehicular Power and Propulsion Conference  (VPPC 2011), Chicago, pp. 1-6, Sep. 2011 [2] D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "An Automotive On-Board 3.3 kW Battery Charger for PHEV application," IEEE Transactions on Vehicular Technology, vol. 61, no. 8, pp. 3466-3474, Oct. 2012  [3] D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "A Zero Voltage Switching Full-Bridge DC-DC Converter for an On-Board PHEV  iv Battery Charger," Proceedings of IEEE Transportation Electrification Conference and Expo (ITEC 2012), Dearborn, pp. 1-6, Jun. 2012 Chapter 3: Content in this chapter has been published in: [4] D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "A Zero Voltage Switching Full-bridge DC-DC Converter with Capacitive Output Filter for a Plug-in-Hybrid Electric Vehicle Battery Charger," Proceedings of IEEE Applied Power Electronics Conference and Exposition (APEC 2012), Orlando, pp. 1381-1386, Feb. 2012 [5] D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "A Zero Voltage Switching Full-bridge DC-DC Converter with Capacitive Output Filter for a Plug-in-Hybrid Electric Vehicle Battery Charger," IEEE Transactions on Power Electronics, vol. 28, no. 12, pp. 5728-5735, Dec. 2013 Chapter 4: Content in this chapter has been published in:  [6] D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "An Interleaved Zero Voltage Switching Full-Bridge DC-DC Converter with Capacitive Output Filter for a Plug-in-Hybrid Electric Vehicle Battery Charger," Proceedings of IEEE Energy Conversion Congress and Exposition (ECCE 2012), Raleigh, pp. 2827-2832, September 2012 Chapter 5: Content in this chapter has been published in: [7]  D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, " An Isolated Interleaved DC-DC Converter with Voltage Doubler Rectifier for PHEV Battery Charger, "Proceedings of IEEE Applied Power Electronics Conference and Exposition (APEC 2013), Long Beach, pp. 3067-3072, Mar. 2013  v In all of the publications listed above [1-7], I was the lead investigator, responsible for performing theoretical analysis, design, simulation and experimentation. Dr. Musavi was involved in the early stages of concept formation and contributed to manuscript edits. Dr. Dunford, Dr. Eberle and Mr. Edington were the supervisory authors and were involved throughout the project in concept formation and manuscript composition. The first page of each chapter includes footnotes with references to existing publications on the related work.   vi Table of Contents  Abstract .................................................................................................................................... ii Table of Contents ................................................................................................................... vi List of Tables ......................................................................................................................... xii List of Figures ....................................................................................................................... xiii List of Abbreviations ........................................................................................................... xxi Acknowledgements ............................................................................................................ xxiii Dedication ........................................................................................................................... xxiv Chapter  1: Introduction ........................................................................................................ 1 1.1 Plug-in Hybrid Electric Vehicle ................................................................................ 1 1.1.1 Series Hybrid Electric Vehicle .............................................................................. 3 1.1.2 Parallel Hybrid Electric Vehicle ........................................................................... 4 1.2 Conductive Battery-Charging System Standard (SAE J1772TM) [8] ...................... 5 1.2.1 AC Level 1 Charging ............................................................................................ 6 1.2.2 AC Level 2 Charging ............................................................................................ 7 1.3 On-Board AC-DC Battery Charger .......................................................................... 7 1.4 DC-DC Converter for Battery Charging Application ............................................... 9 1.4.1 Hard-Switched Converter ..................................................................................... 9 1.4.2 Soft-Switched Converter ..................................................................................... 10 1.5 Interleaving of DC-DC Converters ......................................................................... 11 1.6 Literature Review on ZVS Soft-Switched DC-to-DC Converters .......................... 12 1.6.1 Fixed-Frequency Series Resonant Converter (SRC) .......................................... 13  vii 1.6.2 Fixed-Frequency Parallel Resonant Converter (PRC) ........................................ 14 1.6.3 Fixed-Frequency Series-Parallel or LCC Resonant Converter (SPRC) ............. 14 1.6.4 Fixed-Frequency LCL Series Resonant Converter (SRC) with a Capacitive Output Filter .................................................................................................................... 14 1.6.5 Fixed-Frequency LCL SRC with an Inductive Output Filter ............................. 15 1.6.6 Fixed-Frequency Phase-Shifted ZVS PWM Full-Bridge Converter with Inductive Output Filter .................................................................................................... 16 1.6.7 Fixed-Frequency Phase-Shifted ZVS PWM Full-Bridge Converter with Capacitive Output Filter .................................................................................................. 19 1.7 Thesis Motivation ................................................................................................... 20 1.8 Thesis Outline ......................................................................................................... 21 Chapter  2: Full-Bridge DC-DC Converter with Inductive Output Filter Operated with Trailing-Edge PWM Gating ................................................................................................. 23 2.1 Introduction ............................................................................................................. 23 2.2 Operating Principle ................................................................................................. 24 2.2.1 Interval 1 (T0 – T1) .............................................................................................. 28 2.2.2 Interval 2 (T1 – T2) .............................................................................................. 29 2.2.3 Interval 3 (T2 – T3) .............................................................................................. 30 2.2.4 Interval 4 (T3 – T4) .............................................................................................. 31 2.2.5 Interval 5 (T4 – T5) .............................................................................................. 32 2.2.6 Interval 6 (T5 – T6) .............................................................................................. 33 2.3 Design Procedure .................................................................................................... 34 2.3.1 Selection of Switching Frequency (fs) ................................................................ 34  viii 2.3.2 Selection of Transformer Turns Ratio (nt) .......................................................... 35 2.3.3 Selection of Output Filter Inductor (Lo) .............................................................. 35 2.3.4 Selection of Resonant Inductor (Lr) .................................................................... 36 2.3.5 Selection of MOSFETs (Q1 – Q4) ....................................................................... 37 2.3.6 Selection of Rectifier Diodes (DR1 – DR4) ........................................................... 37 2.3.7 Selection of Trailing-edge PWM Controller and MOSFET Gate Driver ........... 38 2.3.8 Selection of Output filter capacitor (Co2) .......................................................... 38 2.4 Experimental Results .............................................................................................. 39 2.5 Performance Evaluation .......................................................................................... 44 2.6 Conclusions ............................................................................................................. 45 Chapter  3: Full-Bridge DC-DC Converter with Capacitive Output Filter Operated with Trailing-Edge PWM Gating ........................................................................................ 47 3.1 Introduction ............................................................................................................. 47 3.2 Operating Principle ................................................................................................. 48 3.2.1 Interval 1 (T0 – T1) .............................................................................................. 53 3.2.2 Interval 2 (T1 – T2) .............................................................................................. 53 3.2.3 Interval 3 (T2 – T3) .............................................................................................. 55 3.2.4 Interval 4 (T3 – T4) through Interval 6 (T5 – T6) ................................................. 56 3.3 Design Procedure .................................................................................................... 57 3.3.1 Selection of Operating Mode .............................................................................. 57 3.3.2 Selection of Switching Frequency (fs) ................................................................ 58 3.3.3 Selection of Transformer Turns Ratio (nt) .......................................................... 59 3.3.4 Selection of Resonant Inductor (Lr) .................................................................... 59  ix 3.3.5 Selection of MOSFETs (Q1 – Q4) ....................................................................... 61 3.3.6 Selection of Rectifier Diodes (DR1 – DR4) ........................................................... 62 3.3.7 Selection of Output filter capacitor (Co2) ............................................................ 62 3.3.8 Selection of Trailing-edge PWM Controller and MOSFET Gate Driver ........... 62 3.4 Simulation and Experimental Results ..................................................................... 63 3.5 Performance Evaluation .......................................................................................... 68 3.6 Conclusions ............................................................................................................. 70 Chapter  4: An Interleaved Full-Bridge DC-DC Converter with Capacitive Output Filter Operated with Trailing-Edge PWM Gating ............................................................ 71 4.1 Introduction ............................................................................................................. 71 4.2 Operating Principle ................................................................................................. 72 4.3 Design Procedure .................................................................................................... 75 4.3.1 HF Transformer Design ...................................................................................... 76 4.3.2 Selection of Output Filter Capacitor (Co2) .......................................................... 76 4.4 Simulation and Experimental Results ..................................................................... 78 4.5 Performance Evaluation .......................................................................................... 83 4.6 Conclusions ............................................................................................................. 84 Chapter  5: An Interleaved, Full-Bridge DC-DC Converter with Voltage-Doubler Rectifier and Capacitive Output Filter Operated with Trailing-Edge PWM Gating .... 86 5.1 Introduction ............................................................................................................. 86 5.2 Operating Principle ................................................................................................. 87 5.3 Design Procedure .................................................................................................... 95 5.3.1 Selection of Transformer Turns Ratio (nt) .......................................................... 96  x 5.3.2 Selection of Resonant Inductor (Lr) .................................................................... 96 5.3.3 Selection of Rectifier Diodes (DR1 – DR2) ........................................................... 98 5.3.4 Selection of Output Filter Capacitors (Co1 and Co2) ........................................... 99 5.4 Simulation and Experimental Results ................................................................... 100 5.5 Performance Evaluation ........................................................................................ 106 5.6 Conclusions ........................................................................................................... 107 Chapter  6: Conclusion and Future Work ........................................................................ 109 6.1 Introduction ........................................................................................................... 109 6.2 Summary of Contributions .................................................................................... 109 6.2.1 DC-DC Converter with Inductive Filter Operated with Trailing-Edge PWM Gating 109 6.2.2 DC-DC Converter with Capacitive Filter Operated with Trailing-Edge PWM Gating 110 6.2.3 Interleaved DC-DC Converter with Capacitive Filter Operated with Trailing-Edge PWM Gating ........................................................................................................ 111 6.2.4 Interleaved DC-DC Converter with Capacitive Filter and Voltage Doubler Rectifier ......................................................................................................................... 111 6.2.5 Comparison of Proposed Topologies ................................................................ 112 6.3 Suggestions for Future Work ................................................................................ 113 6.3.1 Full-Bridge DC-DC Converter with Clamp Diodes to Reduce Rectifier Ringing Issues 113 6.3.2 Full-bridge DC-DC Converter with Lossless Snubber ..................................... 113  xi 6.3.3 Feedback Control Analysis for the Interleaved DC-DC Converter with Capacitive Output Filter ................................................................................................ 114 Bibliography ........................................................................................................................ 115  xii List of Tables Table 1.1    Charge method electrical ratings (North America) [8] .......................................... 5 Table 1.2    Power levels of on-board battery chargers [11] ..................................................... 8 Table 1.3    Major Specifications of dc-dc converter .............................................................. 11 Table 2.1   Design specification of the Trailing-edge PWM Full-bridge dc-dc converter ..... 34 Table 3.1    Design specification of the Trailing-edge PWM Full-bridge dc-dc converter with capacitive filter ........................................................................................................................ 57 Table 3.2    Comparison of various parameters obtained from simulation and analysis at 5.5 A and 0.7 A load current and 400 V input voltage ................................................................. 63 Table 3.3    Components Used In the Benchmark Converter ................................................. 69 Table 4.1    Design specification of the Trailing-edge PWM Full-bridge dc-dc converter .... 76 Table 4.2    Components Selection ......................................................................................... 77 Table 4.3    Components Used In the Benchmark Converter ................................................. 84 Table 5.1    Design specification of the Trailing-edge PWM Full-bridge dc-dc converter .... 96 Table 5.2    Components Selection ......................................................................................... 99 Table 6.1    Performance comparison of the proposed dc-dc converter topologies .............. 112   xiii List of Figures Figure 1.1    Typical diagram of a Plug-in Hybrid Electric Vehicle ......................................... 2 Figure 1.2    Typical layout of a series HEV drive train [4] ..................................................... 3 Figure 1.3    Schematic of a parallel HEV drive train configuration [4] .................................. 4 Figure 1.4    AC Level 1 System Configuration [8] .................................................................. 6 Figure 1.5    AC Level 2 System Configuration [8] .................................................................. 7 Figure 1.6    Simplified block diagram of an ac-dc battery charger ......................................... 8 Figure 1.7    Turn-on and turn-off transition in a hard-switched converter ............................ 10 Figure 1.8    Zero Voltage Switching (ZVS) .......................................................................... 10 Figure 1.9    Zero Current Switching (ZCS) ........................................................................... 11 Figure 1.10    Clamped Mode Series Resonant converter circuit [30] .................................... 13 Figure 1.11    Clamped-Mode Parallel Resonant converter [31] ............................................ 14 Figure 1.12    Fixed-Frequency Series-Parallel Resonant converter ...................................... 14 Figure 1.13    Fixed Frequency LCL SRC with capacitive output filter [33],[34] ................. 15 Figure 1.14    Fixed Frequency LCL SRC with inductive output filter [35] .......................... 15 Figure 1.15    Full-bridge Phase-shifted converter with inductive output filter [36]-[38] ...... 16 Figure 1.16    Trailing-edge PWM gating scheme .................................................................. 18 Figure 1.17    Full-bridge Phase-shifted converter with capacitive output filter [39]-[42] .... 19 Figure 2.1    Trailing-edge PWM Full-bridge dc-dc converter with inductive output filter ... 24 Figure 2.2    Trailing-edge PWM gating scheme .................................................................... 25 Figure 2.3    Typical operating waveforms for an arbitrary pulse width ‘δ’ to illustrate the operation of the trailing-edge PWM full-bridge converter ..................................................... 27 Figure 2.4    Equivalent circuit for Interval 1 (T0 – T1) .......................................................... 28  xiv Figure 2.5    Equivalent circuit for Interval 2 (T1 – T2) .......................................................... 29 Figure 2.6    Equivalent circuit for Interval 3 (T2 – T3) .......................................................... 30 Figure 2.7    Equivalent circuit for Interval 4 (T3 – T4) .......................................................... 31 Figure 2.8    Equivalent circuit for Interval 5 (T4 – T5) .......................................................... 32 Figure 2.9    Equivalent circuit for Interval 6 (T5 – T6) .......................................................... 33 Figure 2.10    Comparison of measured efficiency as a function of output power for different switching frequencies at Vo = 300V and Po = 1.65 kW ......................................................... 35 Figure 2.11    Prototype unit of trailing-edge PWM full-bridge converter with inductive output filter .............................................................................................................................. 39 Figure 2.12    Measured efficiency versus output power at different output voltages with Vin = 400 V ....................................................................................................................................... 39 Figure 2.13    Experimental waveforms of output voltage and current Ch1= Vo 100V/div. Ch4= Io 2A/div. ....................................................................................................................... 40 Figure 2.14    Experimental waveforms obtained for (Ch1) Q3 gating signal, Vg3 (Ch2) Q3 drain to source voltage, VDSQ3 (Ch3) Transformer secondary current, Isec (Ch4) Rectifier output voltage, Vrectout at light-load (150 W) with Vin = 400 V and Vo = 300 V ..................... 41 Figure 2.15    Experimental waveforms of Figure 2.14 repeated for half-load (1.65 kW) with Vin = 400 V and Vo = 300 V .................................................................................................... 41 Figure 2.16    Experimental waveforms of Figure 2.14 repeated for full-load (3.3 kW) with Vin = 400 V and Vo = 300 V .................................................................................................... 42 Figure 2.17    Experimental waveforms of MOSFET Q1 voltage and current during Turn-ON at Vo = 300 V and Io = 11 A .................................................................................................... 43  xv Figure 2.18    Experimental waveforms of MOSFET Q3 voltage and current during Turn-ON at Vo = 300 V and Io = 11 A .................................................................................................... 43 Figure 2.19    Experimental waveforms of MOSFET Q1 voltage and current during Turn-ON at Vo = 300 V and Io = 1 A ...................................................................................................... 44 Figure 2.20    Measured Efficiency comparison with different combination of primary MOSFETs and secondary diodes at Vo = 300 V and Io = 11 A ............................................. 44 Figure 3.1    Trailing-edge PWM Full-bridge dc-dc converter with capacitive output filter . 48 Figure 3.2    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter in DCM mode ............................................................................. 50 Figure 3.3    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter in BCM mode ............................................................................. 51 Figure 3.4    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter in CCM mode ............................................................................. 52 Figure 3.5    Equivalent circuit for Interval 1 (T0-T1) for DCM, BCM and CCM.................. 53 Figure 3.6    Equivalent circuit for Interval 2 (T1 – T2) for DCM, BCM and CCM and Interval 3 (T2 – T3) for BCM ................................................................................................................ 53 Figure 3.7    Equivalent circuit for Interval 3 (T2 – T3) for CCM ........................................... 55 Figure 3.8    Equivalent circuit for Interval 4 (T3 – T4) for DCM, BCM and CCM ............... 56 Figure 3.9    Equivalent circuit for Interval 5 (T4 – T5) DCM, BCM and CCM and Interval 6 (T5 – T6) for BCM ................................................................................................................... 56 Figure 3.10    Equivalent circuit for Interval 6 (T5 – T6) for CCM ......................................... 57 Figure 3.11    Comparison of measured efficiency as a function of output power for different switching frequencies at Vo = 300V and Po = 1.65 kW .......................................................... 59  xvi Figure 3.12    Design Curve obtained for Gain versus Duty cycle for various values of k in DCM and BCM ....................................................................................................................... 60 Figure 3.13    Experimental prototype of 1.65 kW ZVS full-bridge dc-dc converter with capacitive output filter ............................................................................................................ 64 Figure 3.14    Experimental measurement of efficiency of the proposed converter as a function of output power at 400 V input and different output voltages .................................. 64 Figure 3.15    Experimental waveforms of output voltage and current Ch1= Vo 100 V/div. Ch4= Io 2 A/div. ...................................................................................................................... 65 Figure 3.16    Experimental waveforms of the MOSFET Q3 voltage and resonant inductor Lr current at Vin = 400 V, Vo = 300 V, Po = 200 W and fs = 100 kHz. Ch1=VDS-Q3 200 V/div. Ch2= iLr 5 A/div. Ch3= VGS-Q3 10 V/div. Time scale=1.16 µs/div. ........................................ 66 Figure 3.17    Experimental waveforms of Figure 3.16 repeated for half-load (800 W) with Vin = 400 V and Vo = 300 V .................................................................................................... 66 Figure 3.18    Experimental waveforms of Figure 3.16 repeated for full-load (1.65 kW) with Vin = 400 V and Vo = 300 V .................................................................................................... 67 Figure 3.19    Proposed converter experimental waveforms of the diode DR3 voltage and current at Vin = 400 V, Vo = 300 V, Po = 200 W and fs = 100 kHz. Ch1=VDR3 200 V/div. Ch2= IDR3 5 A/div. Time scale=900 ns/div. ............................................................................ 67 Figure 3.20    Experimental waveforms of the diode DR3 voltage and current at Vin = 400 V, Vo = 300 V, Po = 1650 W and fs = 100 kHz. Ch1=VDR3 100 V/div. Ch2= IDR3 5 A/div. Time scale=900 ns/div...................................................................................................................... 68  xvii Figure 3.21    Efficiency comparison for the proposed converter as a function of output power at 400 V input and 300V output voltage for different rectifier diodes and benchmark converter ................................................................................................................................. 69 Figure 3.22    Schematic of the benchmark ZVS full-bridge converter with inductive output filter ......................................................................................................................................... 69 Figure 4.1    A 2-cell interleaved trailing-edge PWM full-bridge converter with capacitive output filter .............................................................................................................................. 72  Figure 4.2    Typical operating waveforms to illustrate the operation of the trailing-edge PWM 2-cell, interleaved, full-bridge converter in DCM mode .............................................. 73 Figure 4.3    Typical operating waveforms to illustrate the operation of the trailing-edge PWM 2-cell, interleaved, full-bridge converter in BCM mode .............................................. 74 Figure 4.4    Simulation results of resonant inductor LrA and LrB with current through the output filter capacitor Co2 at Vin = 400 V and Vo = 300 V and Io = 1 A .................................. 78 Figure 4.5    Simulation results of Figure 4.4 repeated at at Vin = 400 V and Vo = 300 V and Io = 11 A ..................................................................................................................................... 78 Figure 4.6    Experimental prototype of 3.3 kW, 2-cell, interleaved, full-bridge dc-dc converter with capacitive output filter .................................................................................... 79 Figure 4.7    An inner-loop, current-sharing control scheme .................................................. 80 Figure 4.8    Experimental measured efficiency of the proposed converter as a function of output power at 400 V input and different output voltages .................................................... 81 Figure 4.9    Experimental waveforms of the MOSFET Q3B voltage and transformer secondary winding current at Vin = 400 V, Vo = 300 V, Po = 300 W and fs = 100 kHz.  xviii Ch1=VDS-Q3B 200 V/div. Ch2= VGS-Q3 10 V/div. Ch3= Tx. B Sec. current 2 A/div. Ch4= Tx. A Sec. current 2 A/div.Time scale=2 µs/div. .......................................................................... 82 Figure 4.10    Experimental waveforms of Figure 4.10 repeated for Vin = 400 V, Vo = 300 V, Po = 3300 W and fs = 100 kHz. Ch1=VDS-Q3B 200 V/div. Ch2= VGS-Q3 10 V/div. Ch3= Tx. B Sec. current 10 A/div. Ch4= Tx. A Sec. current 10 A/div.Time scale=2 µs/div. ................... 82 Figure 4.11    Efficiency comparison for the proposed converter as a function of output power at 400 V input and 300V output voltage and benchmark converter ............................ 83 Figure 4.12    Benchmark 2-Cell Interleaved PWM ZVS full-bridge converter topology with inductive output filter .............................................................................................................. 84 Figure 5.1    Trailing-edge PWM Full-bridge dc-dc converter with voltage-doubler rectifier and capacitive output filter ...................................................................................................... 87 Figure 5.2    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter with voltage doubler-rectifier in DCM mode ............................. 88 Figure 5.3    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter with voltage-doubler rectifier in BCM mode ............................. 89 Figure 5.4    Equivalent circuit for Interval 1 for DCM and BCM ......................................... 90 Figure 5.5    Equivalent circuit for Interval 2 for DCM and Interval 2 and 3 for BCM ......... 91 Figure 5.6    A 2-cell, interleaved, trailing-edge PWM, full-bridge converter with voltage-doubler rectifier and capacitive output filter ........................................................................... 92 Figure 5.7    Typical operating waveforms to illustrate the operation of the trailing-edge PWM, 2-cell, interleaved, full-bridge converter with voltage-doubler rectifier in DCM mode ................................................................................................................................................. 93  xix Figure 5.8    Typical operating waveforms to illustrate the operation of the trailing-edge PWM, 2-cell, interleaved, full-bridge converter with voltage-doubler rectifier in BCM mode ................................................................................................................................................. 94 Figure 5.9    Design Curve obtained for Gain versus Duty cycle for various values of k in DCM and BCM ....................................................................................................................... 97 Figure 5.10    Output filter capacitor C01 and C02 ................................................................... 99 Figure 5.11    Simulation results of resonant inductor LrA and LrB with current through the output filter capacitors Co1 and Co2 at Vin = 400 V and Vo = 300 V and Io = 1 A ................. 100 Figure 5.12    Simulation results of Figure 5.11 repeated at Vin = 400 V and Vo = 300 V and Io = 11 A ................................................................................................................................... 100 Figure 5.13    Simulation results of voltage across and current through output rectifier diodes DR2A and DR2B at Vin = 400 V and Vo = 300 V and Io = 1 A ............................................ 101 Figure 5.14    Simulation results of Figure 5.13 repeated at Vin = 400 V and Vo = 300 V and Io = 11 A ................................................................................................................................... 101 Figure 5.15    Experimental prototype of 3.3 kW 2-cell interleaved full-bridge dc-dc converter with voltage-doubler rectifier and capacitive output filter ................................... 102 Figure 5.16    An inner-loop current-sharing control scheme ............................................... 102 Figure 5.17    Experimental measured efficiency of the proposed converter as a function of output power at 400 V input and different output voltages .................................................. 103 Figure 5.18    Experimental waveforms of current through resonant inductor LRA and LRB and MOSFET Q3B voltage at Vin = 400 V and Vo = 300 V, Po = 300 W and fs = 100 kHz. Ch1=VDS-Q3B 200 V/div. Ch2= VGS-Q3 10 V/div. Ch3= Resonant inductor LrA current 5 A/div. Ch4= Resonant inductor LrB 5 A/div. Time scale=2 µs/div. ................................................. 104  xx Figure 5.19    Experimental waveforms of Figure 5.18 repeated for Vin = 400 V and Vo = 300 V, Po = 3300 W and fs = 100 kHz. Ch1=VDS-Q3B 200 V/div. Ch2= VGS-Q3 10 V/div. Ch3= Resonant inductor LrA current 10 A/div. Ch4= Resonant inductor LrB 10 A/div. Time scale=2 µs/div. ................................................................................................................................... 105 Figure 5.20    Experimental waveforms of current through resonant inductor LrB and transformer B secondary winding and voltage across diode DR2B at Vin = 400 V and Vo = 300 V, Po = 300 W and fs = 100 kHz. Ch1= VDR2B 100 V/div. Ch3= Tx. B Sec. winding current 5 A/div. Ch4= LRB current 5 A/div. Time scale=2 µs/div. ...................................................... 105 Figure 5.21    Experimental waveforms of Figure 5.20 repeated for Vin = 400 V and Vo = 300 V, Po = 3300 W and fs = 100 kHz. Ch1= VDR2B 100 V/div. Ch3= Tx. B Sec. winding current 20 A/div. Ch4= LRB current 10 A/div. Time scale=2 µs/div. ............................................... 106 Figure 5.22    Efficiency comparison for the proposed converter as a function of output power at 400 V input and 300V output voltage and benchmark converter .......................... 106 Figure 6.1    Trailing-edge PWM Full-bridge dc-dc converter with inductive output filter and clamp diodes ......................................................................................................................... 113   xxi List of Abbreviations AC, ac  Alternating Current    AER  All Electric Range BCM  Boundary Conduction Mode CCM  Continuous Conduction Mode DC, dc  Direct Current DCM  Discontinuous Conduction Mode Div.  Division EMI, emi Electro-Magnetic Interference ESR, esr Equivalent Series Resistance ESS  Energy Storage System EV  Electric Vehicle HF  High Frequency IGBT  Insulated Gate Bipolar Transistor MOSFET Metal Oxide Semiconductor Field Effect Transistor PHEV  Plug-in Hybrid Electric Vehicle PRC  Parallel Resonant Converter PWM  Pulse Width Modulation RC  Resistor Capacitor RMS, rms Root Mean Square SiC  Silicon Carbide SPRC  Series-Parallel Resonant Converter SRC  Series Resonant Converter  xxii VA  Volt-Ampere ZCS  Zero Current Switching ZVS  Zero Voltage Switching ZVT  Zero Voltage Transition Prefixes for SI Units G   Giga (109) k   Kilo (103) M   Mega (106) m   Milli (10-3) n   Nano (10-9) p   Pico (10-12) μ   Micro (10-6) SI Units A   Amperes C   Coulombs F  Farads H   Henries Hz   Hertz s   seconds V   Volts W   Watts Ω   Ohms °   Degrees  xxiii Acknowledgements I would like to thank my supervisors, Dr. William G. Dunford and Dr. Wilson Eberle, for their valuable guidance during the course of this research work, preparation of the thesis and for financial support. I would like to also thank Mr. Murray Edington and Dr. Fariborz Musavi of Delta-Q Technologies Corp. for their valuable guidance and financial support.     I would like to express my sincere appreciation to the members of my supervisory committee for their time and suggestions. I am grateful to Mr. David Mitalpi and Mr. Ryan Truss from Delta-Q Technologies for their help in preparation of boards for building experimental laboratory prototypes. I also appreciate the great support of my colleagues Mr. Jon Stroud, Mr. Marian Craciun, Mr. Dan O’Leary and Mr. Dale Wager at Delta-Q Technologies Corp. Finally, I appreciate the love and wonderful support from my parents, wife, son and friends. This work was supported by grants from NSERC, Canada and Delta-Q Technologies Corp., Canada.   xxiv Dedication This thesis is dedicated to my parents who have supported me all the way since the beginning of my studies. Also, this thesis is dedicated to my wife Annalakshmi, who has been a great source of motivation and inspiration.  And finally I would like to dedicate this dissertation to my son, Akash, who has grown into a wonderful three-and-a-half-year-old kid in spite of his dad’s spending so much time away from him while working on this dissertation.    1 Chapter  1: Introduction1 This chapter presents literature review of soft-switched dc-dc converters used in a two-stage AC-DC on-board battery charger for plug-in hybrid electric vehicle (PHEV) application. The outline of this chapter is as follows. Section 1.1 briefly discusses the powertrain components of a PHEV. Sections 1.2 and 1.3 present the conductive charging system standard (SAE J1772TM) and topology considerations for an on board battery charger. Sections 1.4 and 1.5 briefly discuss High–Frequency (HF) switching and interleaved dc-dc converters for battery charger application. Section 1.6 presents the literature survey on soft-switched dc-to-dc converters suitable for the desired application. Thesis motivation and outline are given in Sections 1.7 and 1.8, respectively. 1.1 Plug-in Hybrid Electric Vehicle A PHEV as shown in Figure 1.1 is a hybrid vehicle that utilizes rechargeable batteries, or another energy storage device, that can be restored to full charge by connecting a plug to an external electric power source (usually a normal electric wall socket). A PHEV shares the characteristics of both a conventional hybrid electric vehicle, having an electric motor and an Internal Combustion Engine (ICE); and of an all-electric vehicle, having a plug to connect to the electrical grid. Most PHEVs on the road today are passenger cars, but there are also PHEV versions of commercial vehicles and vans, utility trucks, buses, trains, motorcycles, scooters, and military vehicles.                                                  1 Most of the figures and tables used in this chapter are obtained from various sources and they have been appropriately cited. Some sections of the chapter are also modified from previously written introductory material from my master’s thesis entitled “Soft-Switched DC-to-DC Converters for Power Conditioning of Electrolyzer in a Renewable Energy System” (2007) completed at the University of Victoria.  2  Source: Argonne National Laboratory Figure 1.1    Typical diagram of a Plug-in Hybrid Electric Vehicle Living in the era of increasing environmental sensibility and rising fuel price makes it necessary to develop a generation of vehicles that are more fuel efficient and environmental friendly. Hybrid electric vehicles could meet these demands [1]. Plug-in hybrid vehicles have recently created interest among leading automotive industry manufactures because of their potential to replace fuel-generated energy with battery-stored electricity in short daily journeys, and also continuing extended range as a HEV afterwards. This feature makes PHEV a very low or zero-emission vehicle during its Charge Depletion or All-Electric Range (AER) [2]. One of the unique advantages of PHEVs is its capability to integrate the transportation and electric power generation sectors in order to improve the efficiency, fuel economy, and reliability of both systems. This goal is performed via integration of the onboard energy storage units of plug-in vehicles with the power grid by power electronic converters and communication systems. Employing energy storage systems improves the efficiency and reliability of the electric power generation, transmission, and distribution. Similarly by combining Energy Storage System (ESS) with the power train of a conventional vehicle can result in a hybrid vehicle with higher fuel efficiency [3].  3 The operational characteristics of various Hybrid Electric Vehicle (HEV) topologies such as series hybrid, parallel hybrid and series-parallel hybrid systems are presented in [4]-[6]. Of these above mentioned topologies the series hybrid and parallel hybrid are the basic types of HEV topologies primarily considered for PHEV application and they are discussed below: 1.1.1 Series Hybrid Electric Vehicle Series HEV known as Extended Range Electric Vehicles is shown in Figure 1.2.  An ICE is generally run at an optimal efficiency point to drive the generator and charge the propulsion batteries on-board the vehicle, as shown in Figure 1.2.  Figure 1.2    Typical layout of a series HEV drive train [4] When the state of charge (SOC) of the battery is at a predetermined minimum, the ICE is turned on to charge the battery. The ICE turns off again when the battery has reached a desirable maximum SOC. It must be noted that, in a series HEV, there is no mechanical connection between the ICE and the wheels. A series hybrid vehicle is more applicable in city driving and can run solely on electricity until the battery needs to be recharged. For shorter trips, these vehicles might not use gasoline at all.    4 1.1.2 Parallel Hybrid Electric Vehicle  Parallel or Blended HEVs has both the ICE and the traction motor mechanically connected to the transmission. A schematic diagram of the parallel hybrid is shown in Figure 1.3.   Figure 1.3    Schematic of a parallel HEV drive train configuration [4] The vehicle can be driven with the ICE, or the electric motor, or both at the same time and, therefore, it is possible to choose the combination freely to feed the required amount of torque at any given time. In parallel HEVs, there are many ways to configure the use of the ICE and the traction motor. The most widely used strategy is to use the motor alone at low speeds, since it is more efficient than the ICE, and then let the ICE work alone at higher speeds. When only the ICE is in use, the traction motor can function as a generator and charge the battery pack. The fuel economy and AER of HEVs are highly dependent on the onboard ESS of the vehicle. Energy-storage devices charge during low power demands and discharge during high power demands, acting as catalysts to provide energy boost. Batteries are the primary energy-storage devices in ground vehicles. Increasing the AER of vehicles by 15% almost doubles the incremental cost of the ESS. This is due to the fact that the ESS of HEVs requires higher peak power while preserving high energy density. Ultra capacitors (UCs) are the options with higher power densities in comparison with batteries. A hybrid ESS composed of batteries,  5 UCs, and/or fuel cells (FCs) could be a more appropriate option for advanced hybrid vehicular ESSs. The state-of-the-art energy-storage topologies for HEVs and plug-in HEVs (PHEVs) along with battery, UC, and FC technologies are discussed and compared in [7]. 1.2 Conductive Battery-Charging System Standard (SAE J1772TM) [8] PHEV motor drive and energy storage technology is developing at a rapid rate in response to expected market demand for PHEVs. Battery chargers are another key component required for the emergence and acceptance of PHEVs. SAE J1772 defines conductive charging methods and electrical interfaces required for EV/PHEV battery charging. Conductive charging is a method for connecting the electric power supply network to the EV/PHEV for the purpose of transferring energy to charge the battery and operate other vehicle electrical systems, establishing a reliable equipment grounding path, and exchanging control information between the EV/PHEV and the supply equipment [8]. Table 1.1    Charge method electrical ratings (North America) [8] Charge Method Nominal Supply Voltage (Volts) Maximum Current (Amps-continuous) Branch Circuit Breaker rating (Amps) AC Level 1 (on-board) 120 V AC, 1-phase 120 V AC, 1-phase 12 A 16A 15 A (minimum) 20 A AC Level 2 (on-board) 208 to 240 V AC, 1-phase ≤ 80 A Per NEC 625 *DC Level 1 (off-board) 200‐450 V DC 80 A (up to 36 kW) - *DC Level 2 (off-board) 200‐450 V DC 200 A (up to 90 kW) - *Not finalized There are three basic functions (2 electrical and 1 mechanical) that must be performed to allow charging of the EV/PHEV battery from the electric supply network. The first electrical function is to convert the AC voltage to DC voltage which is commonly referred to as rectification. The second electrical function is the control or regulation of the supply voltage to a level that permits a managed charge rate based on the battery charge acceptance characteristics – i.e., voltage, capacity, electrochemistry, and other parameters. The  6 mechanical function is the physical coupling or connecting of the EV/PHEV to the EVSE (Electric Vehicle Supply Equipment) and is performed by the user. Thus a conductive charging system consists of a battery charger and a coupler. The conductive system architecture is suitable for use with electrical ratings as specified in Table 1.1. 1.2.1 AC Level 1 Charging  AC level 1 charging is a method of EV/PHEV charging that extends AC power from the most common grounded electrical receptacle to an onboard charger using an appropriate cord set, as shown in Figure 1.4 at the electrical ratings specified in Table 1.1. AC level 1 allows connection to existing electrical receptacles in compliance with the National Electrical Code - Article 625 [9].  Figure 1.4    AC Level 1 System Configuration [8] The level 1 method uses a standard 120 VAC, 15 A (12 A useable) or 20 A (16 A useable) branch circuit that is the lowest common voltage level found in both residential and commercial buildings in the North America. Thus the maximum power supplied by level 1 is  7 1.92 kW and is deemed important due to the availability of 120 VAC outlets in an emergency situation, even if it meant waiting several hours to obtain a charge [10]. 1.2.2 AC Level 2 Charging  AC level 2 charging is a method of EV/PHEV charging that extends AC power from the electric supply to an on-board charger from a dedicated EVSE as shown in Figure 1.5. The electrical ratings are similar to large household appliances and specified in Table 1.1. AC level 2 may be utilized at home, workplace, and public charging facilities; and the maximum power supplied by level 2 is 19.2 kW (available from a 240 VAC and maximum 80 A outlet).  Figure 1.5    AC Level 2 System Configuration [8] 1.3 On-Board AC-DC Battery Charger As presented in the previous section for PHEV’s, the accepted approach involves using an on board battery charger for AC level 1 and level 2 charging systems.  8 Table 1.2 lists the various power levels of on-board battery chargers being considered for level 1 and level 2 charging systems. Table 1.2    Power levels of on-board battery chargers [11] Charge Method Nominal AC Supply Voltage (Volts) Maximum AC Current (Amps-continuous) Charger DC Output Power Rating (W) Level 1 120 12 1200 15 1650 Level 2 240 15 3300 30 6600 50 12000 80 18000 The accepted charger power architecture includes an ac-dc converter [12]-[15] with power factor correction (PFC) [16]-[19] followed by an isolated dc-dc converter as shown in Figure 1.6. AC Input FilterAC-DC PFC Boost ConverterIsolated DC-DC ConverterDC Output FilterDSP/Micro ControllerUniversal AC Input VoltageDC Output for Battery Charging DC Link Bus Capacitors  Figure 1.6    Simplified block diagram of an ac-dc battery charger The ac-dc plus PFC stage rectifies the input ac voltage, boosts it to a regulated intermediate dc link bus (example 400 VDC) and also maintains unity power factor. Galvanic isolation is required in the battery charger for meeting the user safety (UL2202) and regulatory requirements [20]. Isolation is implemented in the dc-dc stage to take advantage of a small-size, high-frequency transformer, which is commonly used in a dc-dc converter to step-up or step-down the output dc voltage for charging batteries. One of the main advantages of this two-stage approach is that the low frequency ac ripple can be easily rejected by the second dc-dc stage, which is very favorable for charging lithium ion batteries.  9 1.4 DC-DC Converter for Battery Charging Application The main purpose of the dc-dc converter stage in an on-board battery charger is listed below: (1) Provide galvanic isolation between the primary ac circuits and secondary side PHEV vehicle components to meet various safety and regulatory requirements. (2) Step-up or step-down the intermediate PFC bus link voltage of 400V as required for charging the PHEV battery pack. (3) Regulate output voltage and current of the battery charger as required by the battery-charging algorithm. A dc-dc converter operating at high switching frequency (> 20 kHz) reduces the size, weight, and cost of the converter [21]. High-frequency (HF) switched dc-dc converters are basically classified as hard-switched and soft-switched converters. 1.4.1 Hard-Switched Converter Typical current, voltage and switching loss power waveforms during the turn-on and turn-off transitions in a hard-switched converter are shown in Figure 1.7. The voltage and current is simultaneously present across the switch during both switching intervals. This results in large a power loss and thus requires large a heatsink. Therefore the switching frequency range is limited, as it is directly proportional to switching losses. At lower switching frequencies, the size of magnetic components and filters become large. Lossy RC snubbers are also needed to protect the switch from large di/dt and dv/dt. Due to the parasitics (inductance and capacitance) of the circuit, EMI (Electro Magnetic Interference) is also generated, which needs additional filtering.  10 Turn-On TransitionTurn-Off TransitionTurn-On Power LossTurn-Off Power LossttvswiswVs Figure 1.7    Turn-on and turn-off transition in a hard-switched converter 1.4.2 Soft-Switched Converter As seen in Figure 1.7, hard-switched converter switching losses occur during the turn-on and turn-off transition of the semiconductor switch (MOSFET or IGBT), and these losses increase with switching frequency. Soft-switching techniques can be used in dc-to-dc converters to reduce switching losses without reducing the switching frequency. Soft-switching techniques usually refer to zero voltage switching (ZVS) (Figure 1.8) and zero current switching (ZCS) (Figure 1.9), which reduces the turn-on losses and turn-off losses respectively. Another advantage is that EMI generated is significantly reduced, which eases filter design and allows the converter to be switched at a higher frequency. VswitchIswitchVgateIswitchVgate+-VswitchCs Figure 1.8    Zero Voltage Switching (ZVS)  11 VgateIswitchVswitch Figure 1.9    Zero Current Switching (ZCS) As shown in Figure 1.8, ZVS can be achieved by forward biasing the anti-parallel diode of the semiconductor switch prior to applying gating signal to turn-on the switch and similarly ZCS can be achieved by reducing the current through the switch to zero prior to turning-off the gating signal. If a converter operates with ZVS, then the turn-off losses can be easily reduced by placing a lossless snubber (capacitor) directly across the switch. By doing this, the switches are naturally protected from large di/dt at turn-on with the help of ZVS and from large dv/dt with lossless snubber capacitor. Therefore ZVS operation is mainly considered in this research. 1.5 Interleaving of DC-DC Converters The dc-dc converter for this application has to be designed for the power levels as presented in Table 1.2. Table 1.3, lists the major specifications to be considered while designing the dc-dc converter stage for the power levels presented in Table 1.2. Table 1.3    Major Specifications of dc-dc converter Input Voltage Range (VDC) Output Voltage Range (VDC) Max. Output Current (A) Max. Output Power at 300 VDC output voltage (W) 380 to 420 150 to 450 4 1200 5.5 1650 11 3300 22 6600 40 12000 60 18000  12 Due to the high power requirement (mainly for 2 kW and higher power levels), an interleaved, multi-cell configuration [22]-[25] that uses ‘n’ number of cells (each cell rated at (maximum output power/n)) in parallel (both at the input and output) with each cell being phase shifted by 360o/n could be adopted. Each cell shares equal power and the thermal losses are distributed uniformly among the cells. Also, the input/output ripple frequency of multi-cell configuration becomes ‘n’ times the input/output ripple frequency of each cell [26]. 1.6 Literature Review on ZVS Soft-Switched DC-to-DC Converters There are three major types of HF transformer isolated soft-switching converter configurations possible [27]: (a) Voltage fed resonant converters [28-35]; (b) current fed resonant converters [28]; and (c) fixed-frequency resonant transition zero-voltage switching (ZVS) PWM bridge converters [36]-[38]. The current fed resonant converters require high frequency switches rated at five to six times the input voltage (reducing the efficiency) in the present application and therefore they are not considered further. Voltage fed resonant converters can be operated either in variable frequency mode or fixed frequency mode. But the operation in variable frequency mode suffers from several disadvantages: wide variation in switching frequency (considering the input and output voltage variation) making the design of filters and control (feedback and protection) circuit difficult and complex. Therefore, fixed frequency operation is adopted in this thesis. From the above discussions, we are left with the following seven soft-switching converter configurations for the PHEV battery charging application. (1) Fixed-frequency series resonant converter (SRC) (Figure 1.10) [30]. (2) Fixed-frequency parallel resonant converter (PRC) (Figure 1.11) [31].  13 (3) Fixed-frequency series-parallel or LCC-type resonant converter (SPRC) (Figure 1.12) [32]. (4) Fixed-frequency LCL series resonant converter (SRC) with a capacitive output filter (Figure 1.13) [33], [34]. (5) Fixed-frequency LCL SRC with an inductive output filter (Figure 1.14) [35]. (6) Fixed-frequency phase-shifted ZVS PWM full-bridge converter with inductive output filter (Figure 1.15) [36]-[38]. (7) Fixed-frequency phase-shifted ZVS PWM full-bridge converter with capacitive output filter (Figure 1.16) [39]-[42]. 1.6.1 Fixed-Frequency Series Resonant Converter (SRC)  Figure 1.10    Clamped Mode Series Resonant converter circuit [30] A fixed-frequency clamped-mode series resonant converter (SRC) (Figure 1.10) is proposed in [30]. This converter configuration can operate in the following switching conditions, depending on the line and load condition: four switches operate with ZVS turn-on; four switches operated with ZCS turn-off; two switches in one leg operate with zero-current turn-off and the other two switches operated with zero-voltage turn-on. The major problems with this converter is that it offers a very narrow range of ZVS for varying line and load condition in the present application, and with ZCS of the full-bridge switches, there is always an issue of shoot-through due to slow reverse recovery of the MOSFETs anti parallel diodes.  14 1.6.2 Fixed-Frequency Parallel Resonant Converter (PRC)  Figure 1.11    Clamped-Mode Parallel Resonant converter [31] A fixed-frequency clamped-mode parallel resonant converter (PRC) (Figure 1.11) is proposed in [31]. The proposed converter offers ZVS from full load to no load, but the inverter peak current does not decrease much with reduction in the load current, and there is no dc blocking coupling capacitor in series to prevent saturation of the HF transformer. 1.6.3 Fixed-Frequency Series-Parallel or LCC Resonant Converter (SPRC)  Figure 1.12    Fixed-Frequency Series-Parallel Resonant converter A fixed-frequency, series-parallel resonant converter (SPRC) (Figure 1.12) is proposed in [32]. This converter also cannot maintain ZVS for all the primary switches for wide variation in line and load condition in the present application. 1.6.4 Fixed-Frequency LCL Series Resonant Converter (SRC) with a Capacitive Output Filter Another fixed-frequency, LCL modified series resonant converter with capacitive output filter (Figure 1.13) is described in [33],[34]. This converter offers ZVS for all the switches  15 for a wider change in load current variation. But one of the major issues with this converter is the very high peak resonant tank current at lower output voltage and maximum high output current.  Figure 1.13    Fixed Frequency LCL SRC with capacitive output filter [33],[34] 1.6.5 Fixed-Frequency LCL SRC with an Inductive Output Filter  Figure 1.14    Fixed Frequency LCL SRC with inductive output filter [35] Fixed-frequency LCL, modified series resonant converter with inductive output filter (Figure 1.14) is discussed in [35]. This converter also offers ZVS for a wide change in load and supply voltage variation. Moreover, the resonant current is clamped approximately to the reflected load current. This converter, on the other hand, suffers from severe voltage overshoot and ringing due to the interaction of the transformer leakage inductance with the junction capacitance of the rectifier diode and loss of duty cycle on the secondary side of the transformer.   16 1.6.6 Fixed-Frequency Phase-Shifted ZVS PWM Full-Bridge Converter with Inductive Output Filter  Figure 1.15    Full-bridge Phase-shifted converter with inductive output filter [36]-[38] All of the above-mentioned resonant converters suffer from high resonant peak stresses on the circuit components and require components with higher current or voltage ratings. The full-bridge phase-shifted converter with inductive output filter topology (Figure 1.15) [36]-[38] provides a much easier solution to the switching loss problem. Its control features are similar to regular PWM converters and it uses parasitic elements (transformer leakage inductance) to control the switching transition for ZVS. Also, the resonant peaks are absent thus limiting the stresses on the converter components. This converter, on the other hand, suffers from severe voltage overshoot and ringing due to the interaction of the transformer leakage inductance with the junction capacitance of the rectifier diode, loss of duty-cycle on the secondary side of the transformer and looses ZVS for wide variation in line and load conditions [36],[38].  Another issue with phase-shifted gating scheme is that it is difficult to achieve a 0% duty-cycle at lighter and no load due to delay mismatch in the duty-cycle generation and gate-drive circuits. The rectifier’s ringing can be damped by using a clamp circuit or by using clamp diodes and commutating inductor in the primary circuit [43]-[45]. The modified full-bridge, phase-shifted converter [43]-[45] reduces the switching losses in rectifier diodes and offers ZVS over a wide range of line and load variation, provided the  17 transformer leakage inductance is very small and the required inductance for achieving ZVS is realized by using an extra commutating inductor plus two clamp diodes and by increasing the magnetizing current of the high frequency transformer. Thus the major issues of this configuration are the increased circulating current in the primary MOSFETs along with reverse recovery losses in the clamp diodes. In [46]-[48] various configurations with additional passive and active auxiliary circuits to overcome the basic issues in the phase-shifted converter mentioned above are presented. None of these converters [46]-[48] solves all of the problems. A novel, hybrid phase-shifted converter is presented in [49]. This configuration uses two transformers and achieves ZVS for all the primary switches over the entire line and load range but still suffers from loss of duty-cycle and high voltage ringing of the output rectifier diodes. Although various other solutions have been suggested for this converter [50]-[62], all of them increase the component count and suffer from one or more disadvantages including limited ZVS range, high-voltage ringing on the secondary side rectifier diodes, or loss of duty-cycle. Wide ZVS range of operation is discussed in [51]-[54]. The high-voltage ringing on the secondary-side rectifier diodes is addressed in [55]-[58]. The loss of duty-cycle is reviewed in [59],[60]. In order to reduce the RMS current in the primary, a new leading-edge PWM control scheme is presented in [61]. Various methods to increase light-load efficiency are discussed in [62],[63].  A new complementary gating scheme for the full-bridge dc-dc PWM converter is presented in [64]. This gating scheme requires an additional ZVT circuit to achieve ZVS for all the switches for a wide variation in the load current.  18 A new full-bridge ZVS converter operating with trailing edge PWM gating scheme was presented in [65]. This converter behaves like a traditional hard-switched topology, but rather than driving the diagonal full-bridge switches simultaneously with PWM, the low-side, full-bridge switches are driven at a fixed 50 % duty cycle and the upper switches are pulse-width modulated on the trailing edge as shown in Figure 1.16. As a result of this gating scheme, all the switches operate with ZVS for a very wide range of load condition. This converter also suffers with similar issues like the phase-shifted converter. The trailing-edge PWM gating scheme can achieve 0% duty-cycle at lighter and no load without any issue since zero duty-cycle can be realized by completely turning-off the upper switches. Vg1Vg2Vg3Vg4Time (µs)Fixed 50% duty cycle controlled (Q3 and Q4)Trailing-edge PWM controlled (Q1 and Q2) Figure 1.16    Trailing-edge PWM gating scheme       19 1.6.7 Fixed-Frequency Phase-Shifted ZVS PWM Full-Bridge Converter with Capacitive Output Filter  Figure 1.17    Full-bridge Phase-shifted converter with capacitive output filter [39]-[42] The full-bridge phase-shifted converter with capacitive output filter (Figure 1.17) inherently minimizes diode rectifier ringing since the transformer leakage inductance is effectively placed in series with the external resonant inductor [39]-[42]. The converter can be operated in continuous conduction mode (CCM), boundary conduction mode (BCM), and discontinuous conduction mode (DCM). When this converter is operated in BCM and DCM all the secondary diodes turn-on and off with ZCS. Due to ZCS turn-on and turn-off of the secondary diodes, there is no reverse recovery loss and the voltage across the diodes is naturally clamped to the output voltage. Another advantage of this configuration is two primary MOSFETs that turn-on with ZVS and the other two MOSFETs turn-on with zero current over a wide range of load current. The major disadvantage is the turn-off current in the primary switches is significantly high which causes high conduction and turn-off switching losses. Another issue with phase-shift control gating scheme is that it is difficult to achieve a 0% duty-cycle at lighter loads due to mismatch of delays in the duty-cycle generation and gate-drive circuits. A complementary gating scheme for the full-bridge dc-to-dc PWM converter with capacitive output filter is presented in [66]. This gating scheme requires an additional ZVT circuit to  20 achieve ZVS for all the switches for a wide variation in the load current. The major disadvantage of this converter is the asymmetry in the resonant inductor peak current which makes it difficult to implement peak current mode control. 1.7 Thesis Motivation As discussed in the previous section, the full-bridge dc-dc converter operating with trailing-edge PWM gating is not completely explored in the literature. Thus in this thesis, the full-bridge dc-dc converter operating with trailing-edge PWM gating will be investigated in detail. Both versions of the converter, with inductive and capacitive output filters are studied in detail, as well. The full-bridge ZVS converter with inductive output filter operating with trailing-edge PWM gating scheme was presented in [65]. There is no detailed analysis and step-by-step design procedure available in literature for this application. Therefore, a detailed mode analysis is performed on this converter for the present application, and the results are presented in [67]-[69] along with detailed design procedure and experimental results for a 3.3 kW PHEV battery charger. The trailing-edge PWM gating scheme could be also applied to the full-bridge ZVS converter with capacitive output filter. There is no detailed analysis and step-by-step design procedure available in literature for this configuration. Therefore a detailed mode analysis is performed on this converter for the present application and the results are presented in [70] and [71] along with detailed design procedure and experimental results for a 1.65 kW PHEV battery charger. As presented in section 1.5, an interleaved, multi-cell configuration approach, for 2 kW and higher power levels offers various advantages such as: each cell shares equal power, the  21 thermal losses are distributed uniformly among the cells, and the input/output ripple is four times the switching frequency which reduces the filter size and cost. A 3.3 kW interleaved (2-cell) full-bridge DC-DC converter with trailing-edge PWM gating scheme is analyzed and designed, and a lab prototype was built and tested for the present application [72]. A 3.3 kW interleaved (2-cell) full-bridge DC-DC converter with capacitive filter and voltage-doubler rectifier operating with trailing-edge PWM gating scheme is also an attractive solution for the present application. The output voltage-doubler rectifier reduces half the number of secondary diodes (resulting in lower cost and overall converter size) as compared to configuration proposed in [72]. There is no detailed analysis and step-by-step design procedure available in literature for this configuration. A 3.3 kW interleaved (2-cell) full-bridge DC-DC converter with voltage-doubler rectifier with trailing-edge PWM gating scheme is analyzed and designed, and a lab prototype was built and tested for the present application [73]. 1.8 Thesis Outline The layout of the thesis is as follows: Chapter 2- In this chapter the ZVS full-bridge dc-dc converter with inductive output filter will be studied along with a detailed operating principle, steady-state analysis, design consideration, and experimental results. Chapter 3- In order to overcome some of the issues like rectifier diode ringing issue, loss of duty cycle, and primary-side circulating current present in full-bridge dc-dc converter with inductive output filter, a ZVS full-bridge dc-dc converter with capacitive output filter is proposed. In this chapter the full-bridge dc-dc converter with capacitive output filter will be  22 studied along with a detailed operating principle, steady-state analysis, step-by-step design procedure, simulation, and experimental results.  Chapter 4- In this chapter, in order to overcome issues with thermal management for high power applications, an interleaved ZVS full-bridge dc-dc converter with capacitive output filter will be presented along with a detailed operating principle, steady-state analysis, design consideration, simulation, and experimental results.  Chapter 5- In order to minimize the number of components, reduce cost and power density of the converter described in chapter 4, an interleaved ZVS full-bridge dc-dc converter with capacitive output filter and voltage-doubler rectifier will be presented along with a detailed operating principle, steady-state analysis, design consideration, simulation, and experimental results. Chapter 6- This chapter summarizes the contributions of the thesis and scope of future work.   23 Chapter  2: Full-Bridge DC-DC Converter with Inductive Output Filter Operated with Trailing-Edge PWM Gating2 2.1 Introduction This chapter presents a full-bridge dc-dc converter with inductive output filter operating with trailing-edge PWM gating for use in the dc-dc converter stage of a PHEV onboard battery charger.  As discussed in chapter 1, soft-switching techniques (i.e. ZVS and ZCS) can be used in dc-dc converters to reduce switching losses without reducing the switching frequency. Operation at high switching frequency aids in mainly reducing the size and weight. Additionally the use of soft-switching increases the conversion efficiency of the converter. All the primary side switches of the trailing-edge, PWM full-bridge converter turn-on with ZVS for a wide range of load conditions. Another major advantage of this converter over a phase-shifted converter is that it can achieve 0% duty-cycle at light and no-load conditions without any extra circuitry since zero duty-cycle can be realized by completely turning-off the PWM controlled upper switches. All the above discussed merits make it suitable for the trailing-edge, PWM full-bridge converter to be used as the dc-dc converter stage of an onboard battery charger. Therefore, this chapter presents a full-bridge dc-dc converter with inductive output filter operating with trailing-edge PWM. Although this topology has been reported in [64], its detailed operation, design and experimental results for an on-board battery charger                                                  2 Content from  this chapter has been published in [D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "An Automotive On-Board 3.3 kW Battery Charger for PHEV application," Proceedings of IEEE Vehicular Power and Propulsion Conference  (VPPC 2011), Chicago, pp. 1-6, Sep. 2011], [D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "An Automotive On-Board 3.3 kW Battery Charger for PHEV application," IEEE Transactions on Vehicular Technology, vol. 61, no. 8, pp. 3466-3474, Oct. 2012] and [D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "A Zero Voltage Switching Full-Bridge DC-DC Converter for an On-Board PHEV Battery Charger," Proceedings of IEEE Transportation Electrification Conference and Expo (ITEC 2012), Dearborn, pp. 1-6, Jun. 2012].  24 application are not available in the literature. The content of this chapter includes the following. Section 2.2 explains the detailed operating principle. Section 2.3 gives the design procedure for selecting various components and devices based on the analysis presented in section 2.2. Based on this design method, a 3.3 kW, 200 kHz, dc-to-dc converter is designed and built in the laboratory, and the experimental results are presented in Sections 2.4. Finally, performance evaluation of this converter with various semiconductor combinations is presented in Section 2.5. 2.2 Operating Principle The circuit diagram of the full-bridge dc-dc converter with inductive output filter operating with trailing-edge PWM gating scheme is shown in Figure 2.1.  Co1 Co2LoCcRcDcDR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformernt:1iLrVabCQ1 CQ2CQ3 CQ4VRec_iniLoVRectoutIsec  Figure 2.1    Trailing-edge PWM Full-bridge dc-dc converter with inductive output filter MOSFETs Q1 – Q4 are the primary-side switches of the full-bridge, and as shown in the circuit diagram, all the MOSFETs are also modeled with parasitic drain-to-source antiparallel diodes, and capacitors CQ1 – CQ4. DR1 – DR4 are the secondary-side rectifier diodes. Primary-side resonant inductor Lr is a combination of the leakage inductance of the transformer reflected to the primary side, and any external inductor connected in series with the transformer. Lo, is the output filter inductor, and its value is very large as compared to that of Lr. Co1, which is the input bulk filter capacitor and is usually also part of the output filter  25 capacitor of the preceding front-end PFC stage (not shown in Figure 2.1). Co2 is the output filter capacitor and is very small in value as compared to Co1. Finally Rc, Cc and Dc, form the RCD voltage clamp circuit to clamp the high voltage ringing across the diodes DR1 – DR4, which is caused by interaction of the transformer leakage inductance with the diode parasitic capacitance [36], [74].  Vg1Vg2Vg3Vg4Time (µs)Fixed 50% duty cycle controlled (Q3 and Q4)Trailing-edge PWM controlled (Q1 and Q2) Figure 2.2    Trailing-edge PWM gating scheme  Fixed-frequency, trailing edge PWM gating control is achieved by driving the lower switches (Q3 and Q4) at a fixed 50% duty cycle and the upper switches (Q1 and Q2) are pulse-width modulated on the trailing edge as shown in Figure 2.2, which creates a potential difference, Vab, across transformer primary winding. Due to this a voltage is induced in the secondary winding of the transformer, which is then rectified by diodes DR1 – DR2, and finally, filtered by Lo and Co2. Inductor Lr resonates with the parasitic capacitance CQ1 – CQ4 in order to facilitate ZVS turn-on for MOSFETs. The operating waveforms are shown in Figure 2.3 for an arbitrary pulse width ‘δ’. To simplify the presentation of the operating principle, all components are assumed to be ideal; input and output filter capacitor Co1 and Co2 is considered equivalent to a constant  26 voltage source (ripple free). All parasitic capacitances in the circuit, including winding and heatsink capacitance, have been lumped together with the switch capacitances CQ1 – CQ4. Diodes DR1 – DR4 are assumed to be ideal, hence the effect of high-voltage ringing, due to resonance of the diode junction capacitance with the transformer leakage inductance, is not discussed here. Also the magnetizing inductance of the transformer is considered to be large, hence the effect of magnetizing current is neglected in the analysis. Figure 2.3 illustrates the detailed operating waveforms of the trailing-edge PWM full-bridge converter with intervals and devices conducting during each interval. The gating signals, Vg1 – Vg2, for all the primary, switches Q1 – Q4, resonant inductor current iLr, the bridge voltage Vab, the output bridge rectifiers voltage VRect_in and output inductor current iLo are also shown. The state in which two diagonally opposite primary switches are conducting is called the active state, and the state in which the primary current freewheels when two switches on the same side of the power bus are conducting is called the passive state. The two sets of switches (Q1, Q2 and Q3, Q4) operate under different conditions. As can be observed from Figure 2.3, the converter moves from the active to the passive state whenever Q1 and Q2 turn-off.  27  Vg1Vg2Vg3Vg4VabiLrVRec_inIntervalsTimeDevices1 2 3 4 5 6 8 9 10DR2,DR3,Q1,Q4DR2,DR3,CQ1,CQ3,Q4DR2,DR3,Q4,DQ3DR1~DR4,CQ2,CQ4,Q3DR1~DR4,DQ2,DQ3DR1~DR4,DQ2,DQ3T0T1T2T3T4T5T6Duty Cycle LossAvailable Duty Cycle on Secondary SideResonant DelayT77DR1,DR4,Q2,Q3Active State Active SatePassive StateActive to Passive StatePassive to Active StateIoiLoI2I1δI3iDQ2+iCQ2iQ2iDQ3+iCQ3iQ3iQ2iQ3VinVin/ntI4I5I1I’1=-I1/ntI’2=-I2/ntI’3=-I3/ntI’1=I1/nt1112t  Figure 2.3    Typical operating waveforms for an arbitrary pulse width ‘δ’ to illustrate the operation of the trailing-edge PWM full-bridge converter  28 2.2.1 Interval 1 (T0 – T1) Co1 Co2LoCcRcDcDR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformernt:1iLrVabCQ1 CQ2CQ3 CQ4VRec_iniLo Figure 2.4    Equivalent circuit for Interval 1 (T0 – T1) During this interval, switches Q1 and Q4 are on and Q2 and Q3 are off. Voltage across node ‘a’ and ‘b’ is vab=-Vin. On the secondary side, the rectifier diodes DR2 and DR3 are conducting. This is a power-transfer mode (active power state) and the primary current flows through Q1, transformer primary winding, resonant inductor Lr and finally, through Q4, as illustrated in Figure 2.4. The initial current in the output inductor iLo(0)=I1. The output inductor current iLo(t) using initial condition iLo(0)=I1 is given by:  𝑖𝐿𝑜(𝑡) = 𝐼1 + [(𝑉𝑖𝑛𝑛𝑡) − 𝑉𝑜𝐿𝑜] (𝑡 − 𝑇0) 2-1 The resonant inductor current iLr(t) is given by:   𝑖𝐿𝑟(𝑡) = −𝑖𝐿𝑜(𝑡)𝑛𝑡 2-2 At the end of this interval iLr reaches the peak resonant inductor current, 𝑰′𝟐 =𝑰𝟐𝒏𝒕 where I2 is the peak output inductor current as shown in Figure 2.3.      29 2.2.2 Interval 2 (T1 – T2) Co1 Co2LoCcRcDcDR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformernt:1iLrVabCQ1 CQ2CQ3 CQ4VRec_iniLo Figure 2.5    Equivalent circuit for Interval 2 (T1 – T2) Interval 1 terminates when switch Q1 turns off as determined by the PWM duty cycle ‘δ’. This is a transition mode from active state to passive state. Since the current flowing through the primary cannot be interrupted instantaneously, it finds an alternate path and flows through the parasitic switch capacitances of CQ1 and CQ3, which discharges the node ‘b’ to 0 V by charging CQ1 and discharging CQ3, as shown in Figure 2.5. During this interval, the resonant inductor current is assumed to be constant iLr = I’2. The voltage across CQ1 and CQ3 is given by:  𝑣𝐶𝑄1(𝑡) =𝐼′2(𝑡 − 𝑇1)(𝐶𝑄1 + 𝐶𝑄3) 2-3   𝑣𝐶𝑄3(𝑡) = 𝑉𝑖𝑛 − 𝑣𝐶𝑄1 2-4 During this switch transition, the energy stored in the output inductor (Lo) and the resonant inductor (Lr) assist in charging and discharging the capacitances CQ1 and CQ3 respectively.       30 2.2.3 Interval 3 (T2 – T3) Co1 Co2LoCcRcDcDR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformernt:1iLrVabCQ1 CQ2CQ3 CQ4VRec_iniLo Figure 2.6    Equivalent circuit for Interval 3 (T2 – T3) At the end of interval 2, CQ3 has completely discharged vCQ3 = 0. During this interval, the primary current freewheels (passive state) through the body diode of Q3, transformer primary winding, resonant inductor Lr, and finally, through Q4, as illustrated in Figure 2.6. Since the body diode of Q3 is conducting, switch Q3 is ready to be turned on under the ZVS condition. In this topology, switches Q3 and Q4 (50% duty-cycle controlled switches) always achieve ZVS with the help of the energy stored in the output inductor (Lo) for nearly the entire load current (Io) range. On the secondary side, the rectifier diodes DR2 and DR3 are still conducting. The output inductor current iLo(t) is given by:  𝑖𝐿𝑜(𝑡) = 𝐼2 − [𝑉𝑜𝐿𝑜] (𝑡 − 𝑇2) 2-5 The resonant inductor current iLr(t) is given by:   𝑖𝐿𝑟(𝑡) = −𝑖𝐿𝑜(𝑡)𝑛𝑡 2-6 At the end of this interval Q3 and Q4 toggle and 𝑖𝐿𝑜 reaches I3, as shown in Figure 2.3.     31  2.2.4 Interval 4 (T3 – T4) Co1 Co2LoCcRcDcDR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformernt:1iLrVabCQ1 CQ2CQ3 CQ4VRec_iniLo Figure 2.7    Equivalent circuit for Interval 4 (T3 – T4) During this interval, after gating signal Vg3 is applied, switch Q3 turns on with ZVS. After Q4 turns off, the current flowing in the resonant inductor resonates with parasitic switch capacitances of CQ2 and CQ4, which charges node ‘a’ to Vin by charging CQ4 and discharging CQ2, as shown in Figure 2.3 and 2.7. During this interval, all secondary diodes DR1 ~ DR4 are free-wheeling and this commences the duty-cycle loss period, as shown in Figure 2.3 and 2.7. The voltage across CQ2 and CQ4 is given by equation 2-7 and 2-8, where Z=√𝐿𝑟𝐶𝑄2+𝐶𝑄4 and 𝜔𝑟 =1√𝐿𝑟(𝐶𝑄2+𝐶𝑄4).  𝑣𝐶𝑄2(𝑡) = 𝑉𝑖𝑛 − 𝑣𝐶𝑄4(𝑡) 2-7   𝑣𝐶𝑄4(𝑡) =𝐼3𝑛𝑡𝑍 sin{𝜔𝑟(𝑡 − 𝑡3)} 2-8 The resonant inductor current iLr(t) using initial condition 𝑖𝐿𝑟(0) = −𝐼3𝑛𝑡 is given by:  𝑖𝐿𝑟(𝑡) = −𝐼3𝑛𝑡cos{𝜔𝑟(𝑡 − 𝑡3)} 2-9 At the end of this interval, node ‘a’ reaches Vin and 𝑖𝐿𝑟 reaches I4 as shown in Figure 2.3.  32 Since ZVS transition of Q1 and Q2 is dependent on the output load current (Io) and energy stored in the resonant inductor LR, the minimum load current required to achieve ZVS turn-on for Q1 and Q2 is given by:  𝐼𝑜𝑚𝑖𝑛 =𝑉𝑖𝑛𝑛𝑡𝑍 2-10 2.2.5 Interval 5 (T4 – T5) Co1 Co2LoCcRcDcDR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformernt:1iLrVabCQ1 CQ2CQ3 CQ4VRec_iniLo Figure 2.8    Equivalent circuit for Interval 5 (T4 – T5) During this interval, after CQ2 is fully discharged, the body diode of Q2 conducts. The primary current freewheels (passive state) through the body diode of Q3, transformer primary winding, resonant inductor Lr and finally through the body diode of Q2, as illustrated in Figure 2.8. All secondary diodes DR1 ~ DR4 are still free-wheeling, and passive state continues. The resonant inductor current iLr(t) using initial condition 𝑖𝐿𝑟(0) = 𝐼4 is given by:  𝑖𝐿𝑟(𝑡) = 𝐼4 +𝑉𝑖𝑛𝐿𝑟(𝑡 − 𝑡4) 2-11 At the end of this interval 𝑖𝐿𝑟 reaches I5, as shown in Figure 2.3. The period from T3 to T5 is the resonant delay time as shown in Figure 2.3. This is the delay time after Q3 and Q4 toggles and before Q2 is turned on. In order to ensure that Q2 turns with ZVS, the required resonant delay should be at least 1/4 of the period of the resonant  33 frequency of the circuit formed by the resonant inductor of the Lr and the parasitic capacitances CQ2 and CQ4. This resonant transition may be estimated by:  𝜏 =𝜋2√𝐿𝑟 + (𝐶𝑄2 + 𝐶𝑄4) 2-12 2.2.6 Interval 6 (T5 – T6) Co1 Co2LoCcRcDcDR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformernt:1iLrVabCQ1 CQ2CQ3 CQ4VRec_iniLo Figure 2.9    Equivalent circuit for Interval 6 (T5 – T6) During this interval, gating signal is applied to switch Q2, and it turns on with ZVS, as shown in Figure 2.9, and polarity of the primary current changes. In addition, all secondary diodes DR1 ~ DR4 are still free-wheeling, and passive state continues. The resonant inductor current iLr(t) using initial condition 𝑖𝐿𝑟(0) = 𝐼5 is given by:  𝑖𝐿𝑟(𝑡) = 𝐼5 +𝑉𝑖𝑛𝐿𝑟(𝑡 − 𝑡5) 2-13 At the end of this interval, the current through the primary of the transformer and resonant inductor Lr reaches I’1 and equals the current through the output inductor Lo, as shown in Figure 2.3. The secondary rectifier diodes DR2 and DR3 completely turns off, and the entire load current flows through DR1 and DR4 only, thus ending the duty-cycle loss period, and the power transfer mode commences again. Operation of the intervals 7 to 12 can be explained in a similar way to intervals 1 to 6.  34 2.3 Design Procedure This section provides the details for designing and selection of various components of the trailing-edge PWM full-bridge converter as discussed in the previous section. Based on the design procedure, a 3.3 kW dc-dc converter stage is designed to meet the specification of a level-2 charger as discussed in Table 1.2. The detailed specifications for designing the dc-dc converter are given in Table 2.1. Table 2.1   Design specification of the Trailing-edge PWM Full-bridge dc-dc converter Parameters Value[Units] Input DC Voltage (from PFC stage) 380 to 420 [V] Output DC Voltage Range 200 to 450 [V] Maximum Output DC Current 11 [A] Maximum Output Power (at 300V output voltage) 3.3 [kW] Output Voltage Ripple < 2 [Vp-p] Efficiency Up to 96 [%] 2.3.1 Selection of Switching Frequency (fs) An experimental efficiency comparison for the trailing-edge PWM full-bridge converter is provided in Figure 2.10 at half-load power, (i.e. 1.65 kW) for switching frequencies between 66 kHz and 250 kHz. At 66 kHz, the converter has maximum overall efficiency. Since the converter components, including the resonant inductor, transformer, and output inductor were optimized for 66 kHz operation, the efficiency is lower at 150, 200 and 250 kHz. However, since the difference in losses at full load is limited to 2.3 %, a 200 kHz switching frequency was selected for the dc-to-dc stage. And finally, the magnetic components were redesigned for the final selected switching frequency of 200 kHz.  35  Figure 2.10    Comparison of measured efficiency as a function of output power for different switching frequencies at Vo = 300V and Po = 1.65 kW 2.3.2 Selection of Transformer Turns Ratio (nt) The transformer turns ratio nt is calculated using equation 2-14, where DCloss includes dead-time and duty-cycle loss.  𝑛𝑡 =𝑉𝑖𝑛(1 − 𝐷𝐶𝐿𝑜𝑠𝑠)𝑉𝑜 2-14 The transformer turns ratio is determined to be 0.75 for an input and output voltage of 400 V, and DCLoss is assumed to be 0.25. An EE55 shape ferrite core (using material R from Mag Inc.) transformer was designed using turns ratio of 12 (number of primary turns):16 (number of secondary turns). Two 18 AWG (65 strands of 36 AWG wire) twisted Litz wires were used for the primary and secondary windings. 2.3.3 Selection of Output Filter Inductor (Lo) The output filter inductor Lo is calculated to be 400 µH using equation 2-15, where ΔIo is the peak-to-peak output inductor ripple current is assumed to be 1 A (10 % of maximum output current).     36  𝐿𝑜 =(𝑉𝑖𝑛𝑛𝑡− 𝑉𝑜)(1 − 𝐷𝐿𝑜𝑠𝑠)∆𝐼𝑜2𝑓𝑠 2-15  A 400 µH inductor was designed using a 125 µ permeability toroidal core (part number: 44738 from Mag Inc.) and by winding 38 turns of 15 AWG copper wire. 2.3.4 Selection of Resonant Inductor (Lr) The resonant inductor Lr is calculated to be 8 µH using equation 2-16.  𝐿𝑟 =𝑛𝑡𝑉𝑖𝑛(𝐷𝐿𝑜𝑠𝑠)4 ∆𝐼𝑜𝑓𝑠 2-16 A 6µH resonant inductor was selected, which is smaller as compared to the value calculated using equation 2-16. By using a 6 µH inductor, ZVS can be achieved for Q1 and Q2 from load current of Io = 11 A down to 5.5 A. Below 5.5 A, Q1 and Q2 will have turn-on switching losses, but the total losses at 5.5 A are 16 W, which are considerably lower than the 20 W of total loss with ZVS at 11 A load. The heatsink around the primary MOSFETs is designed to extract 20W from each primary device, which is sufficient to handle the light-load losses when the MOSFETs lose ZVS. Finally, a lower resonant inductor value reduces the duty-cycle loss and helps achieve higher full-load efficiency by minimizing the circulating current conduction loss. A 6 µH inductor was realized by connecting two 2 µH each external inductors in series (total 4 µH) and an additional 2 µH was obtained using the transformer leakage inductance. Each 2 µH external inductor was designed using a 14 µ permeability toroidal core (part number: 55123A2 from Mag Inc.) and by winding 13 turns of 15 AWG Type 2 Litz wire (3x43 strands of 36 AWG wire).   37  2.3.5 Selection of MOSFETs (Q1 – Q4) Using the analysis presented in section 2.2 (equation 2-1 to 2-13), the RMS current through switches Q1, Q2 and Q3, Q4 is given by equation 2-17 and 2-18 respectively:  𝐼𝑄12(𝑟𝑚𝑠) = √1𝑇∫ 𝑖𝐿𝑅(𝑡)2𝑑𝑡𝑇7𝑇3 2-17   𝐼𝑄34(𝑟𝑚𝑠) = √1𝑇∫ 𝑖𝐿𝑅(𝑡)2𝑑𝑡𝑇9𝑇1 2-18 RMS current through the primary switches was calculated to be 8 A and 10 A using equation 2-17 and 2-18 for full-load condition (Vin = 400 V, Vo = 300 V and Io = 11 A). A 600V, 83 mΩ Rdson (switch ON state resistance), 46 A, 450 pF Cds (parasitic capacitance) MOSFET (part number: SPW47N60CFD from Infineon) with a fast body diode was selected for the four primary switches. 2.3.6 Selection of Rectifier Diodes (DR1 – DR4) The average current through the output rectifier diodes DR1 to DR4, IDR(ave) is given by:  𝐼𝐷𝑅(𝑎𝑣𝑒) =𝐼𝑜2 2-19 Average current through the rectifier diodes was calculated to be 5.5 A using equation 2-19 for Io = 11 A.  A 600 V, 12 A silicon carbide (SiC) schottky diode (part number: IDH12S60C from Infineon) was selected for the four rectifier diodes.  38 2.3.7 Selection of Trailing-edge PWM Controller and MOSFET Gate Driver For implementing the trailing edge PWM gating scheme, ISL6753 PWM controller (from Intersil) was used and for driving the MOSFETs Q1 – Q4, IR2110 gate driver (from International Rectifier) was selected. 2.3.8 Selection of Output filter capacitor (Co2)  The RMS current through the output filter capacitor Co2 is given by equation 2-20 and its capacitance value is determined using equation 2-21.  𝐼𝐶𝑜2(𝑟𝑚𝑠) = √1𝑇7 − 𝑇1∫ (𝑖𝐿𝑜(𝑡) − 𝐼𝑜)2𝑑𝑡𝑇7𝑇1= 0.22 [𝐴] 2-20   𝐶02 =𝐼𝐶𝑜2(𝑟𝑚𝑠)4𝜋𝑓𝑠𝑉𝑟𝑖𝑝𝑝𝑙𝑒= 0.2 [𝜇𝐹] 2-21 A 33 µF, 500V electrolytic capacitor (part number ECST501ELL330MLN from Nippon-Chemi-Con) was selected for the output filter capacitor.            39 2.4 Experimental Results Based on the design presented in section 2.3, a 3.3 kW laboratory prototype was built to the design specifications of Table 2.1, as shown in Figure 2.11.  Figure 2.11    Prototype unit of trailing-edge PWM full-bridge converter with inductive output filter Experimentally measured efficiency curves at Vo = 200, 300, 400 and 450 V output over the entire power range with Vin = 400 V are provided in Figure 2.12.   Figure 2.12    Measured efficiency versus output power at different output voltages with Vin = 400 V  40 It should be noted that the converter achieves a peak efficiency of 96 % at Vo = 400 V, Io = 8.25 A and maximum output power of 3.3 kW. At maximum output current Io = 11 A, Vo = 300 V and output power of 3.3 kW the converter achieves an efficiency of 94.9 %. It should be also noted that below half output power 1.65 kW the efficiency reduces drastically. This is due to switches Q1 and Q2 losing ZVS and loss in the RCD clamp components dominating at lighter load. The experimental waveforms of output voltage and current are shown in Figure 2.13 for Vo = 400 V and Io = 8 A. As seen in Figure 2.13, both output voltage and current are nearly free from low-frequency (120 Hz) ripple. This is one of the important requirements for battery-charging applications to maintain good health of the batteries. Output VoltageCh1 = Vo 100V/div.Output CurrentCh4 = Io 2A/div. Figure 2.13    Experimental waveforms of output voltage and current Ch1= Vo 100V/div. Ch4= Io 2A/div. Figures 2.14, 2.15 and 2.16 demonstrate ZVS turn-on of primary switch Q1, high-voltage ringing across the rectifier diodes DR1 – DR4 and also loss of duty-cycle. As seen in these figures, switch Q3 achieves ZVS from 150 W to 3.3 kW loads since the drain-to-source voltage across Q3, VDSQ3 drops to 0V prior to the gate voltage Vg3 that is applied to turn-on Q3. Thus as discussed in section 2.2.3, these results show that switch Q3 turns on with ZVS  41 over the entire load range since this transition is assisted by the energy stored in the large output filter inductor Lo. Transformer secondary currentCh3 = Isec 2A/div.Rectified VoltageCh4 = Vrectout 100V/div.Gate VoltageCh1 = Vg3 5V/div.Q3 Drain to Source VoltageCh4 = VDSQ3 100V/div. Figure 2.14    Experimental waveforms obtained for (Ch1) Q3 gating signal, Vg3 (Ch2) Q3 drain to source voltage, VDSQ3 (Ch3) Transformer secondary current, Isec (Ch4) Rectifier output voltage, Vrectout at light-load (150 W) with Vin = 400 V and Vo = 300 V Transformer secondary currentCh3 = Isec 2A/div.Rectified VoltageCh4 = Vrectout 100V/div.Gate VoltageCh1 = Vg3 5V/div.Q3 Drain to Source VoltageCh4 = VDSQ3 100V/div.Duty cycle loss Figure 2.15    Experimental waveforms of Figure 2.14 repeated for half-load (1.65 kW) with Vin = 400 V and Vo = 300 V  42 Transformer secondary currentCh3 = Isec 5A/div.Rectified VoltageCh4 = Vrectout 100V/div.Gate VoltageCh1 = Vg3 5V/div.Q3 Drain to Source VoltageCh4 = VDSQ3 100V/div.Duty cycle loss Figure 2.16    Experimental waveforms of Figure 2.14 repeated for full-load (3.3 kW) with Vin = 400 V and Vo = 300 V As discussed in section 1.6.6, this converter suffers from excessive high-voltage ringing due to the interaction of transformer leakage inductance with the junction capacitance of the rectifier diode. Figures 2.14 to 2.16 show the high-voltage ringing across the output of the rectifier diodes, Vrectout. This high-voltage ringing is clamped to 532.5 V with the help of a RCD clamp circuit [74]. The duty-cycle loss period was discussed in section 2.2.4 and 2.2.6. During this period a significant portion of the primary duty cycle is lost due to the freewheeling of the secondary diodes, which results in a higher transformer turns ratio, nt as shown in Equation 2.14.  As shown in Figures 2.15 and 2.16, the duty-cycle becomes very significant at half-load and full-load conditions. As seen in the Figures 2.15 and 2.16 almost 300 ns (13 %) duty-cycle period is lost at half-load and 1.2 µs (25 %) duty-cycle period is lost at full-load respectively. Figure 2.17 and 2.18 show the anti-parallel diodes of Q1 and Q3 conduct current (shown in the grey-shaded area) prior to conducting current through the drain-to-source channel of the MOSFET. It can be also observed that before the current flows through the channel of the  43 MOSFET, the voltage across the drain-to-source of the MOSFET Q1 and Q3 drops to 0 V, thus enabling them to turn-on with ZVS. Q1 Drain to Source Voltage During Turn ONCh1 = VDSQ1 100V/div.Q1 Drain to Source Current During Turn ONCh2 = IDSQ1 5A/div.ZVS Q1 anti-parallel diode conduction  Figure 2.17    Experimental waveforms of MOSFET Q1 voltage and current during Turn-ON at Vo = 300 V and Io = 11 A Q3 Drain to Source Voltage During Turn ONCh1 = VDSQ1 100V/div.Q3 D ain to Source Current During Turn ONCh2 = IDSQ1 5A/div.ZVSQ3 anti-parallel diode conduction  Figure 2.18    Experimental waveforms of MOSFET Q3 voltage and current during Turn-ON at Vo = 300 V and Io = 11 A Figure 2.19 shows that at light load (300 W) the energy stored in the resonant inductor Lr is not sufficient to completely charge and discharge CQ3 and CQ1 completely. The anti-parallel  44 diode of Q1 does not conduct current at all. Thus, after the resonant delay time has elapsed and the gating signal Vg1 is applied, Q1 turns on without ZVS. It was also found that during this transition a total of 5 W dissipated as turn-on switching loss occurred. Q1 Drain to Source Voltage During Turn ONCh1 = VDSQ1 100V/div.Q1 Drain to Source Current During Turn ONCh2 = IDSQ1 1A/div.Loss of ZVSCQ1 Parasitic capacitance conduction  Figure 2.19    Experimental waveforms of MOSFET Q1 voltage and current during Turn-ON at Vo = 300 V and Io = 1 A 2.5 Performance Evaluation 92.5093.0093.5094.0094.5095.00Efficiency (%)Primary MOSFETs and Secondary DiodesInfineon MOSFET and SiC diodeInfineon MOSFET and Hyperfast diodeFairchild MOSFET and SiC diodeFairchild MOSFET and Hyperfast diode Figure 2.20    Measured Efficiency comparison with different combination of primary MOSFETs and secondary diodes at Vo = 300 V and Io = 11 A  45 Figure 2.20 illustrates a performance evaluation of the trailing-edge PWM full-bridge dc-dc converter with inductive output filter for various semiconductor combinations. The various semiconductor devices used were: Infineon MOSFET (SPW47N60CFD), Fairchild MOSFET (FCH47N60F), Infineon Silicon Carbide diode (IDH12S60C), and Fairchild hyperfast diode (ISL9R1560). As shown in Figure 2.20, full-load efficiency was measured to compare their performances. As shown in the comparison, Infineon’s SPW47N60CFD MOSFET and IDH12S60C silicon carbide diode performed the best, as it had the highest efficiency of 94.6 %. It should be also noted that the efficiency of Fairchild’s FCH47N60F and Infineon’s SiC diode combination was almost equally efficient 94.53 %. Also irrespective of the MOSFET type, the SiC diode outperformed the hyperfast diode. It can be also observed that the combination of Fairchild’s MOSFET and diode was the least efficient. One of the main reasons was that the Fairchild MOSFETs were dissipating more power when operated with the hyperfast diode. Thus, it can be concluded that an SiC diode is an attractive solution for this topology, since higher efficiency is achieved as compared to the hyperfast diode.  2.6 Conclusions A new full-bridge dc-dc converter with inductive output filter operating with trailing-edge PWM gating has been presented in this chapter for the dc-dc stage in PHEV battery charger. The proposed converter has been presented with detailed analysis, design and experimental results. It has been shown through experimental results that this converter achieves high efficiency, the output voltage and currents waveforms are free from 120 Hz AC ripple, and all the primary MOSFETs achieve ZVS from full-load to half-load condition. It is also shown that performance with SiC rectifier diode is more superior to hyperfast diode.  46 Some of the drawbacks of the converter such as, duty-cycle loss, high voltage rectifier ringing and circulating currents in primary side switches were also discussed. In the next chapter, a full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM is presented, which overcomes all the above mentioned drawbacks such as, duty-cycle loss, high voltage rectifier ringing and circulating currents in primary-side switches of the converter presented in this chapter.       47 Chapter  3: Full-Bridge DC-DC Converter with Capacitive Output Filter Operated with Trailing-Edge PWM Gating3 3.1 Introduction This chapter presents a full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM gating scheme, as discussed in chapter 1 for use in the dc-dc converter stage of a PHEV onboard battery charger. In chapter 2, the trailing-edge PWM full-bridge dc-dc converter with inductive output filter was presented. As discussed in the last chapter, this converter achieves ZVS for all the switches with the help of energy stored in the resonant inductor Lr and output filter inductor Lo. At lighter loads when sufficient energy is not available in Lr, the PWM controlled switches Q1 and Q2 lose ZVS.  It was also shown through experimental results that the 3.3 kW prototype converter achieved 96 % efficiency. As explained in section 2.2, the duty-cycle loss and high-voltage ringing issues were also demonstrated with experimental results. To overcome these issues a new topology, the full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM gating is proposed in this chapter. It is noted that there is no detailed analysis and step-by step-design procedure available in the literature for this configuration. This proposed converter eliminates all the above-mentioned issues present in the converter with inductive filter and helps significantly to reduce the size and cost of the converter.                                                  3 Content from this chapter has been published in: [D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "A Zero Voltage Switching Full-bridge DC-DC Converter with Capacitive Output Filter for a Plug-in-Hybrid Electric Vehicle Battery Charger," Proceedings of IEEE Applied Power Electronics Conference and Exposition (APEC 2012), Orlando, pp. 1381-1386, Feb. 2012] and [D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "A Zero Voltage Switching Full-bridge DC-DC Converter with Capacitive Output Filter for a Plug-in-Hybrid Electric Vehicle Battery Charger," IEEE Transactions on Power Electronics, vol. 28, no. 12, pp. 5728-5735, Dec. 2013].  48 The layout of the chapter is as follows. Section 3.2 explains the detailed operating principle. Section 3.3 gives the design procedure for selecting various components and devices based on the analysis presented in section 3.2. Based on this design method, a 1.65 kW, 100 kHz, dc-to-dc converter is designed. PSIM simulation and experimental results are presented in Sections 3.4. Finally, performance evaluation of this converter with various semiconductor combinations is presented in Section 3.5.  3.2 Operating Principle The circuit diagram of the full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM gating scheme is shown in Figure 3.1. Co1 Co2DR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformernt:1iLrVabCQ1 CQ2CQ3 CQ4VRec_iniRectIseciCo2 Figure 3.1    Trailing-edge PWM Full-bridge dc-dc converter with capacitive output filter MOSFETs Q1 – Q4 are the primary-side switches of the full-bridge, and as shown in the circuit diagram, all the MOSFETs are also modeled with parasitic drain to source antiparallel diodes and capacitors CQ1 – CQ4. DR1 – DR4 are the secondary-side rectifier diodes. The primary-side resonant inductor Lr is a combination of the leakage inductance of the transformer reflected to the primary side and any external inductor connected in series with the transformer. Co1 is the input bulk filter capacitor and is usually also part of the output filter capacitor of the preceding front-end PFC stage (not shown in Figure 3.1). Co2 is the output filter capacitor and is very small in value as compared to Co1.  49 As presented in section 2.2 and Figure 2.2, fixed-frequency, trailing edge PWM gating control is achieved by driving the lower switches (Q3 and Q4) at a fixed 50 % duty cycle and the upper switches (Q1 and Q2) are pulse-width modulated on the trailing-edge, which creates a potential difference, Vab across transformer primary winding. Due to this, a voltage is induced in the secondary winding of the transformer, which is rectified by diodes DR1 – DR2 and finally filtered by Co2. ZVS and ZCS turn-on for the primary MOSFETs are achieved due to energy stored in inductor Lr during commutation of the MOSFETs Q1 – Q4.  The resonant inductor current (iLr) of the proposed converter can operate in either discontinuous conduction mode (DCM), boundary conduction mode (BCM), or continuous conduction mode (CCM). The detailed circuit operation in all three modes is discussed below: This converter has six operating intervals for DCM, BCM or CCM.  The operating intervals are determined by the on/off states of the four primary switches. Detailed operating waveforms are provided for DCM in Figure 3.2, for BCM in Figure 3.3 and for CCM in Figure 3.4. In the analysis that follows, all components are assumed to be ideal; input and output filter capacitor Co1 and Co2 is considered equivalent to constant voltage source (ripple free). All parasitic capacitances in the circuit including winding and heatsink capacitance have been lumped together with the switch capacitances CQ1 – CQ4. Also the magnetizing inductance of the transformer is considered to be large and hence the effect of magnetizing current is neglected in the analysis. The output rectifiers are considered ideal and the external resonant inductor also includes the transformer leakage inductance.   50 Vg1Vg2Vg3Vg4+400V-400ViLrvabTime (µs)vDR1 & vDR4T0 T1 T2 T3 T4 T5 T6vo1 2 3 4 5 6DevicesIntervalsQ1,Q4, DR1,DR4DQ3,Q4,DR1,DR4DQ4,Q3,DR2,DR3Q2,Q3,DR2,DR3TTPIP1iDR1 & iDR4iQ3iQ2 Figure 3.2    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter in DCM mode   51 Vg1Vg2Vg3Vg4+400V-400ViLRvoTime (µs)T0 T1 T2 T3 T4 T5 T61 2 3 4 5 6DevicesIntervalsQ1,Q4, DR1,DR4DQ3,Q4, DR1,DR4DQ4,Q3,DR2,DR3Q2,Q3,DR2,DR3DQ3,Q4,DR1,DR4DQ4,Q3,DR2,DR3TIP2TPIP1vDR1 & vDR4iDR1 & iDR4iLrvabiQ3iQ2 Figure 3.3    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter in BCM mode  52 Vg1Vg2Vg3Vg4+400V-400ViLRvoTime (µs)T0 T1 T2 T3 T4 T5 T6Intervals1 2 3 4 5 6DevicesQ1,Q4, DR1,DR4DQ3,Q4, DR1,DR4DQ4,Q3,DR2,DR3Q2,Q3, DR2,DR3DQ3,DQ2, DR1,DR4DQ1,DQ4, DR2,DR3TIP2TPIP1vDR1 & vDR4iDR1 & iDR4iLrvabiQ3iQ2 Figure 3.4    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter in CCM mode  53 3.2.1 Interval 1 (T0 – T1) Co1 Co2DR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4abVin VoIo Figure 3.5    Equivalent circuit for Interval 1 (T0-T1) for DCM, BCM and CCM Referring to Figure 3.2 - 3.4, during Interval 1 (T0-T1), switches Q1 and Q4 are on and Q2 and Q3 are off. This is a power transfer interval, and the primary current flows through Q1, resonant inductor (Lr), transformer primary, and Q4, as illustrated in Figure 3.5. The rate of rise of the current (di/dt) through Lr is proportional to the difference between the input voltage Vin and the output voltage Vo. During this mode power flows to the output through rectifier diodes DR1 and DR4 and also energy is stored in Lr. The resonant inductor current, 𝑖𝐿𝑟(𝑡), using initial condition 𝑖𝐿𝑟(0) = 0 is given by:  𝑖𝐿𝑟(𝑡) =(𝑉𝑖𝑛 −𝑉𝑜𝑛)𝐿𝑟(𝑡 − 𝑇𝑜) 3-1 3.2.2 Interval 2 (T1 – T2) Case (a): Operating in DCM Co1 Co2DR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4abVin VoIo Figure 3.6    Equivalent circuit for Interval 2 (T1 – T2) for DCM, BCM and CCM and Interval 3 (T2 – T3) for BCM  54 Referring to Figure 3.2, interval 2 begins after switch Q1 turns off, as determined by the PWM duty cycle. Since the current flowing in the primary side cannot be interrupted instantaneously, it finds an alternate path and flows through the parasitic switch capacitances of Q3 and Q1, which discharges the node ‘a’ to 0V and then forward biases the body diode D3. During this switch transition, the energy stored in the resonant inductor (Lr) assists in transferring energy from the lower to upper bridge MOSFET capacitance. Therefore switches Q3 and Q4 always achieve ZVS with the help of the energy stored in the resonant inductor (Lr) for nearly the entire load current (Io) range. During this interval the energy stored in Lr is transferred to the output. The primary resonant inductor (Lr) maintains the current, which circulates around the path of body diode of Q3, resonant inductor (Lr), transformer primary and Q4, as illustrated in Figure 3.6. The rate of the downslope of the current through Lr is proportionate to the output voltage Vo. At T2 the energy stored in Lr is transferred to the output, the current becomes zero, and the rectifier diodes DR1 and DR4 turn-off. The resonant inductor current, 𝑖𝐿𝑟(𝑡), using initial condition 𝑖𝐿𝑟(0) =  𝐼𝑃1 is given by:  𝑖𝐿𝑟(𝑡) = 𝐼𝑃1 −𝑉𝑜𝑛𝐿𝑟(𝑡 − 𝑇1) 3-2 Case (b): Operating in BCM and CCM Referring to Figures 3.3 and 3.4, the only difference in BCM or CCM as compared to DCM during Interval 2 is that the current through the resonant inductor doesn’t reach zero at T2,and the rectifier diodes DR1 and DR4 are on. At the end of this interval, 𝑖𝐿𝑟(𝑡) = 𝐼𝑃2. Figure 3.6 illustrates the equivalent circuit for this interval.     55 3.2.3 Interval 3 (T2 – T3) Case (a): Operating in DCM Referring to Figure 3.2, during this interval no power is transferred to the secondary. Accordingly, this interval is a passive interval. In this interval, the parasitic capacitances of the rectifier diodes resonate with Lr. This resonance appears across the rectifier diodes DR1 and DR4 as illustrated in Figure 3.2. For this interval, current in the resonant inductor remains zero (𝑖𝐿𝑟 = 0). Case (b): Operating in BCM During this interval, the resonant inductor current continues to circulate around the path of DQ3, resonant inductor (Lr), transformer primary, and Q4, as illustrated in Figure 3.3 and 3.6. The rate of the downslope of the current through Lr is proportionate to the output voltage Vo. At T3,the entire energy stored in Lr is transferred to the output, the current becomes zero, and the rectifier diodes DR1 and DR4 turn-off. The resonant inductor current, 𝑖𝐿𝑟(𝑡), using initial condition 𝑖𝐿𝑟(0) =  𝐼𝑃2 is given by (3).  𝑖𝐿𝑟(𝑡) = 𝐼𝑃2 −𝑉𝑜𝑛𝐿𝑅(𝑡 − 𝑇2) 3-3 Case (c): Operating in CCM Co1 Co2DR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4abVin VoIo Figure 3.7    Equivalent circuit for Interval 3 (T2 – T3) for CCM  56 Referring to Figure 3.4 and Figure 3.7, in CCM at T2, Q3 and Q4 toggle. The timing of this toggle is dependent on the resonant delay that occurs prior to Q2 turning-on. When Q3 and Q4 toggle, the primary resonant inductor current that was flowing through Q4 finds an alternate path by charging/discharging the parasitic capacitances of switches Q4 and Q2 until the body diode of Q2 is forward biased. If the resonant delay is set properly, switch Q2 can be turned on with ZVS. At T3, the entire energy stored in Lr is transferred to the output, the current becomes zero, and the rectifier diodes DR1 and DR4 turn-off. The resonant inductor current, 𝑖𝐿𝑟(𝑡), using initial condition 𝑖𝐿𝑟(0) =  𝐼𝑃2 is given by (4).  𝑖𝐿𝑟(𝑡) = 𝐼𝑃2 −(𝑉𝑖𝑛 +𝑉𝑜𝑛)𝐿𝑟(𝑡 − 𝑇2) 3-4 3.2.4 Interval 4 (T3 – T4) through Interval 6 (T5 – T6) Intervals 4 to 6 are the negative equivalent of Intervals 1 to 3 as shown in Figures 3.8 to 3.10. Co1 Co2DR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4abVin VoIo Figure 3.8    Equivalent circuit for Interval 4 (T3 – T4) for DCM, BCM and CCM Co1 Co2DR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4abVin Vo Figure 3.9    Equivalent circuit for Interval 5 (T4 – T5) DCM, BCM and CCM and Interval 6 (T5 – T6) for BCM  57 Co1 Co2DR1 DR2DR3 DR4LrHVBatteryQ1 Q2Q3 Q4abVin VoIo Figure 3.10    Equivalent circuit for Interval 6 (T5 – T6) for CCM 3.3 Design Procedure This section provides the details for designing and selecting of various components of the trailing-edge, PWM full-bridge converter with capacitive output filter, as discussed in the previous section. Based on the design procedure, a 1.65 kW dc-dc converter stage is designed to meet the specification of a level-1 charger, as discussed in Table 1.2. The detailed specifications for designing the dc-dc converter are given in Table 3.1. Table 3.1    Design specification of the Trailing-edge PWM Full-bridge dc-dc converter with capacitive filter Parameters Value[Units] Input DC Voltage (from PFC stage) 380 to 420 [V] Output DC Voltage Range 200 to 450 [V] Maximum Output DC Current 5.5 [A] Maximum Output Power (at 300V output voltage) 1.65 [kW] Output Voltage Ripple < 4 [Vp-p] Efficiency Up to 96 [%] 3.3.1 Selection of Operating Mode As discussed in the previous section, this converter can operate in DCM, BCM, or CCM. When the converter is operated in DCM, or BCM, the 50% fixed duty-cycle controlled switches (Q3 and Q4) can achieve both ZVS turn-on and ZCS turn-off, and also the PWM controlled switches (Q1 and Q2) can achieve ZCS turn-on. In addition, the secondary-side  58 rectifier diodes can achieve ZCS, which significantly reduces the reverse recovery losses due to the low di/dt. As an additional benefit, the voltage across the diodes is clamped to the output voltage, enabling the use of lower breakdown voltage diodes and eliminating the use of lossy RCD voltage clamps, which are typically required in traditional CCM dc-dc converters with inductive output filters. When operated in BCM, the converter retains the advantages of DCM but also has relatively low RMS currents, decreasing conduction loss. Operation in CCM results in the lowest RMS currents, and ZVS can be achieved for all switches, but the high di/dt results in large reverse-recovery losses in the secondary-side rectifier diodes and high voltage ringing. Moreover, to operate this converter in CCM, it requires a larger resonant inductor which also increases the transformer turns ratio, thus, increases stress on the primary side switches. Thus, this converter should be designed to operate in DCM, or BCM. 3.3.2 Selection of Switching Frequency (fs) An experimental efficiency comparison for the trailing-edge, PWM full-bridge converter is provided in Figure 3.11 at 1.65 kW for switching frequencies of 100 kHz and 200 kHz. At 100 kHz the converter has maximum overall efficiency. Even though the converter components, including the resonant inductor and transformer were optimized for 200 kHz operation, the efficiency at 200 kHz was 2 % lower than at 100 kHz. Thus, a 100 kHz switching frequency was selected. And finally, the magnetic components were redesigned for the selected switching frequency of 100 kHz.  59  Figure 3.11    Comparison of measured efficiency as a function of output power for different switching frequencies at Vo = 300V and Po = 1.65 kW 3.3.3 Selection of Transformer Turns Ratio (nt) The transformer turns ratio nt is calculated using equation 3-5 where Dmax is the maximum duty-cycle.  𝑛𝑡 = 𝑉𝑜𝑚𝑎𝑥𝐷𝑚𝑎𝑥  𝑉𝑖𝑛 3-5 The transformer turns ratio is determined to be 1.17 for Vin = 400 V, Vomax = 450 V at maximum duty cycle of Dmax = 0.96. An EE55 shape ferrite core (using material R from Mag Inc.) transformer was designed using turns ratio of 12(number of primary turns):14(number of secondary turns). Two 18 AWG (65 strands of 36 AWG wire) twisted Litz wires were used for primary and secondary winding. 3.3.4 Selection of Resonant Inductor (Lr) The converter DC gain in DCM (MDCM) is given by equation 3-6, where n is the transformer turns ratio; D is the duty cycle; k is the normalized time constant of the converter; Lr is the resonant inductor, which also includes the leakage inductance of the transformer; Ro is the load resistance; and T is the switching period. 7580859095206 413 825 1238 1650Efficiency (%)DC-DC converter Output Power (W)100 kHz200 kHz 60  𝑀𝐷𝐶𝑀 =𝑉𝑜𝑉𝑖𝑛=2𝑛𝑡1 + √1 +4𝑘𝐷2 3-6 The normalized time constant of the converter is given by:  𝑘 =  4𝑛𝑡2𝐿𝑟𝑅𝑜𝑇 3-7 The converter DC gain in BCM is given by:  𝑀𝐵𝐶𝑀 =𝑉𝑜𝑉𝑖𝑛= 𝐷𝑛𝑡 3-8 Using equations 3-5 to 3-8 the design curves are plotted for Gain versus Duty cycle for various values of k in DCM and BCM as shown in Figure 3.12.  Vo = 300 VDCM Gain k = 0.01Duty Cycle (D)Gain0 0.25 0.5 0.75 100.250.50.7511.25Design Operating PointDCM Gain k = 1Vo = 150 VBCM Gain DCM Gain k = 0.33Vo = 450 V Figure 3.12    Design Curve obtained for Gain versus Duty cycle for various values of k in DCM and BCM  61 To operate the converter in BCM at maximum output current of Io = 5.5 A and Vo = 300 V (Pomax = 1.65 kW), k = 0.33 is selected as shown in Figure 3.2. Finally, using equation 3-7 and k = 0.33, the resonant inductor Lr = 33 µH is selected. The 33 µH inductor was designed using a RM12 ferrite core (Material: N97 from Epcos) with an air gap of 2.1 mm and by winding 18 turns of 19 AWG Type 2 Litz wire (5x46 strands of 42 AWG wire). 3.3.5 Selection of MOSFETs (Q1 – Q4) The RMS current through the switches Q1 and Q2, IQ12(rms) is given by:  𝐼𝑄12(𝑟𝑚𝑠) = √1𝑇∫ 𝑖𝐿𝑟(𝑡)2𝑑𝑡𝑇1𝑇0 3-9 The RMS current through the switches Q3 and Q4, IQ34(rms) is given by:  𝐼𝑄34(𝑟𝑚𝑠) = √1𝑇[∫ 𝑖𝐿𝑟(𝑡)2𝑑𝑡 + ∫ 𝑖𝐿𝑟(𝑡)2𝑑𝑡𝑇3𝑇1]𝑇1𝑇0 3-10 The average current through the anti-parallel diodes of switches Q3 and Q4, IDQ34(ave) is given by:  𝐼𝐷𝑄34(𝑎𝑣𝑒) =1𝑇∫ 𝑖𝐿𝑟(𝑡)𝑑𝑡𝑇3𝑇1= 1.17 [𝐴] 3-11 RMS current through the primary switches was calculated to be 4.35 A and 5.42 A using equation 3-9 and 3-10 for full-load condition (Vin = 400 V, Vo = 300 V and Io = 5.5 A). A 600V, 190 mΩ Rdson (switch ON state resistance), 20 A, MOSFET (part number: FCB20N60F from Fairchild) with a fast body diode was selected for the four primary switches.    62 3.3.6 Selection of Rectifier Diodes (DR1 – DR4) The average current through the output rectifier diodes DR1 to DR4, IDR(ave) is given by:  𝐼𝐷𝑅(𝑎𝑣𝑒) =𝐼𝑜2 3-12 Average current through the rectifier diodes was calculated to be 2.75 A using equation 3-12 for Io = 5.5 A.  A 600 V, 8 A hyperfast diode (part number: ISL9R0860 from Fairchild) was selected for the four rectifier diodes. 3.3.7 Selection of Output filter capacitor (Co2)  The RMS current through the output filter capacitor Co2 is given by equation 3-13 and its capacitance value is determined using equation 3-14.  𝐼𝐶𝑜2(𝑟𝑚𝑠) = √1𝑇𝑃∫ (𝑖𝑅𝐸𝐶(𝑡) − 𝐼𝑜)2𝑑𝑡𝑇𝑃0= 3.4 [𝐴] 3-13    𝐶02 =𝐼𝐶𝑜2(𝑟𝑚𝑠)4𝜋𝑓𝑠𝑉𝑟𝑖𝑝𝑝𝑙𝑒= 5.4 [𝜇𝐹] 3-14 A 10 µF, 630V film capacitor (part number B32676G6106 from Epcos) was selected for the output filter capacitor. 3.3.8 Selection of Trailing-edge PWM Controller and MOSFET Gate Driver For implementing the trailing edge PWM gating scheme, ISL6753 PWM controller (from Intersil) was selected and for driving the MOSFETs Q1 – Q4, IR2110 gate driver (from International Rectifier) was selected.   63 3.4 Simulation and Experimental Results The performance of the converter designed in Section 3.3 was evaluated using PSIM simulation software. Simulations were run for full- and light-load conditions. Circuit parameters, including component stresses, obtained from theoretical analysis and simulation are listed in Tables 3.2 at Vin = 400V and Io = 5.5A and 0.7A. As can be observed, there is a close match between the theoretical prediction and simulation results. Table 3.2    Comparison of various parameters obtained from simulation and analysis at 5.5 A and 0.7 A load current and 400 V input voltage Parameters Analysis Simulation Analysis Simulation Output voltage, Vo (V) 300 300 Output current, Io (A) 5.5 0.7 Duty cycle, D (%) 62 63.3 21.9 19.4 Q1, Q2 RMS current IQ12(rms) (A) 4.35 4.5 0.91 0.9 DQ1, DQ2 average current IDQ12(ave) (A) 0 0 0 0 Q3, Q4 RMS current IQ34(rms) (A) 5.42 5.3 1.13 1.2 DQ3, DQ4 average current IDQ34(ave) (A) 1.17 1 0.16 0.19 Peak current through Lr, ILrp (A) 13.44 13 4.73 4.65 RMS current through Lr, ILrr (A) 7.65 7.5 1.6 1.65 Average current through DR1 – DR4, IDR(ave) (A) 2.75 2.75 0.35 0.35 RMS current through Co, ICo2(rms) (A) 3.4 3.24 1.2 1.2  64 A 1.65 kW experimental prototype was built to verify the operation of the proposed converter. A photo of the prototype is provided in Figure 3.13. OutputCapacitorTransformerResonantInductorControlBoardsOutput Bridge RectifiersPrimary MOSFETs Figure 3.13    Experimental prototype of 1.65 kW ZVS full-bridge dc-dc converter with capacitive output filter Experimentally measured efficiency curves at Vo = 200, 300, 400 and 450 V output over the entire power range with Vin = 400 V are provided in Figure 3.14.  Figure 3.14    Experimental measurement of efficiency of the proposed converter as a function of output power at 400 V input and different output voltages 86878889909192939495960 500 1000 1500 2000Efficiency (%)Output Power (W)Vo = 150VVo = 200VVo = 300VVo = 400 V 65 It should be noted that the converter achieves a peak efficiency of 95.7 % at Vo = 400 V, Io = 3 A and output power of 1.2 kW. At maximum output current Io = 5.5 A, Vo = 300 V and output power of 1.65 kW, the converter achieves an efficiency of 94.9 %. It should be also noted that below 25 % of output power 1.65 kW, the efficiency reduces drastically. This is due to turn-on and turn-off switching losses of Q1 and Q2 dominating at lighter loads. Output Current (Io)Output Voltage (Vo) Figure 3.15    Experimental waveforms of output voltage and current Ch1= Vo 100 V/div. Ch4= Io 2 A/div. The experimental waveforms of output voltage and current are shown in Figure 3.15 for Vo = 300 V and Io = 5.5 A. As seen in Figure 3.15, both output voltage and current are nearly free from low-frequency (120 Hz) ripple. This is one of the important requirements for battery-charging applications. Figure 3.16, 3.17, and 3.18 provide the experimental waveforms for MOSFET Q3 voltage and resonant inductor Lr current. Figure 3.16 and 3.17 shows DCM operation at 10 % and 50 % load condition, and Figure 3.18 shows BCM operation at full load. It is noted that the current in MOSFET Q3 is analyzed using the measured resonant inductor current iLr. The anti-parallel diode of Q3 conduct current (shown in grey shaded area) prior to conducting current through the drain-to-source channel of the MOSFET. It can be also observed that  66 before the current flows through channel of the MOSFET, the voltage across the drain to source of the MOSFET Q3 drops to 0 V, thus enabling it to turn-on with ZVS. As noted, the current through Q3 reduces to 0 A naturally prior to turning-off, thus enabling it to turn-off with ZCS. Drain-SourceVoltage VDS-Q3Gating SignalVGS-Q3ZVS Turn-on of Q3Q3 anti-parallel diode conductionZCS Turn-off of Q3Resonant Current (ILr) Figure 3.16    Experimental waveforms of the MOSFET Q3 voltage and resonant inductor Lr current at Vin = 400 V, Vo = 300 V, Po = 200 W and fs = 100 kHz. Ch1=VDS-Q3 200 V/div. Ch2= iLr 5 A/div. Ch3= VGS-Q3 10 V/div. Time scale=1.16 µs/div. rain-SourceVoltage VDS-Q3Gating SignalVGS-Q3ZVS Turn-on of Q3Q3 anti-parallel diode conduction ZCS Turn-off of Q3Resonant Current (ILr) Figure 3.17    Experimental waveforms of Figure 3.16 repeated for half-load (800 W) with Vin = 400 V and Vo = 300 V  67 Drain-SourceVoltage VDS-Q3Resonant Current (ILr)Gating SignalVGS-Q3ZVS Turn-on of Q3Q3 anti-parallel diode conductionZCS Turn-off of Q3 Figure 3.18    Experimental waveforms of Figure 3.16 repeated for full-load (1.65 kW) with Vin = 400 V and Vo = 300 V Figure 3.19 and 3.20 shows the voltage across and current through rectifier diode DR3 in DCM and BCM, respectively. As seen, the voltage across the diode is clamped to the output voltage, at Vo = 300V, and the di/dt through the diode is low enough to minimize the losses due to reverse-recovery issues inherent with hyperfast diodes. Rectifier Diode Current IDR3Rectifier Diode Voltage VDR3ZCS Turn-off of DR3 Figure 3.19    Proposed converter experimental waveforms of the diode DR3 voltage and current at Vin = 400 V, Vo = 300 V, Po = 200 W and fs = 100 kHz. Ch1=VDR3 200 V/div. Ch2= IDR3 5 A/div. Time scale=900 ns/div.  68 Rectifier Diode Current IDR3Rectifier Diode Voltage VDR3ZCS Turn-off of DR3 Figure 3.20    Experimental waveforms of the diode DR3 voltage and current at Vin = 400 V, Vo = 300 V, Po = 1650 W and fs = 100 kHz. Ch1=VDR3 100 V/div. Ch2= IDR3 5 A/div. Time scale=900 ns/div. Also observed, the current through DR3 reduces to 0 A naturally prior to turning-off, thus enabling it to turn-off with ZCS.  3.5 Performance Evaluation Figure 3.21 provides an efficiency comparison including a benchmark ZVS full-bridge DC-DC converter with inductive output filter and two versions of the proposed converter (with capacitive output filter) using: ISL9R0860 (Hyperfast diodes) and IDH06S60C Silicon Carbide (SiC) secondary rectifier diodes. The benchmark converter circuit is illustrated in Figure 3.22, and a list of its components is provided in Table 3.3. The overall efficiency of the proposed converter, particularly at light-load conditions, is much higher than the benchmark converter. The benchmark converter has lower efficiency due to losses in the secondary-side RCD clamp circuit. The performance of the proposed converter with hyperfast diodes is very similar to that with SiC diodes. Therefore, this converter permits use of inexpensive hyperfast diodes, which are typically one quarter of the cost of SiC diodes.  69  Figure 3.21    Efficiency comparison for the proposed converter as a function of output power at 400 V input and 300V output voltage for different rectifier diodes and benchmark converter Co1 Co2LoCcRcDcDR1 DR2DR3 DR4HVBatteryQ1 Q2Q3 Q4abVin VoIoLLK Figure 3.22    Schematic of the benchmark ZVS full-bridge converter with inductive output filter Table 3.3    Components Used In the Benchmark Converter  Parameters Value [Units] 1 Q1-Q4 FCB20N60F [each] 2 DR1-DR4 IDH06S60C [each] 3 Transformer turns ratio  1.22 4 Transformer Leakage Inductance  1.6 [µH] 5 Output Inductor 600 [µH] 6 DC-DC Switching Frequency 70 [kHz] 788082848688909294960 500 1000 1500 2000Efficiency (%)Output Power (W)Vo = 300V SiC DiodeVo = 300V Hyperfast DiodeVo = 300V Benchmark Converter 70 3.6 Conclusions A new full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM gating has been presented in this chapter for the dc-dc stage in a PHEV battery charger. The proposed converter has been presented with detailed analysis, design and experimental results. It has been shown through analysis and experimental results that this converter overcomes all the major issues such as, duty-cycle loss, high voltage rectifier ringing and circulating currents in primary side switches present in the converter with inductive output filter, as presented in the previous chapter. This converter also achieves high efficiency and the output voltage and currents waveforms are free from 120 Hz AC ripple. All the primary MOSFETs and secondary rectifier operate with soft-switching. This converter also permits use of inexpensive hyperfast diode, since its performance is very similar to that of SiC rectifier diode. For higher power application (> 2 kW), this converter could suffer from high peak current stress in the primary MOSFETs, which may cause thermal management issues and compromise the reliability of the converter. In order to overcome these issues, an interleaved, multi-cell, full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM is presented in the next chapter. This configuration not only reduces the stress on the devices, but also aids in reducing the size of the input and output filter components.     71 Chapter  4: An Interleaved Full-Bridge DC-DC Converter with Capacitive Output Filter Operated with Trailing-Edge PWM Gating4 4.1 Introduction This chapter presents an interleaved full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM gating scheme, as discussed in chapter 1, for use in the dc-dc converter stage of a PHEV onboard battery charger. In chapter 3, the trailing-edge, PWM full-bridge dc-dc converter with capacitive output filter was presented. As discussed in the last chapter, this converter overcomes the main issues of duty-cycle loss, high-voltage ringing on the rectifier diodes and circulating currents in the primary side, which are present in the full-bridge converter with inductive output filter, as discussed in chapter 2. It was also shown in chapter 3 that the full-bridge converter with capacitive filter significantly improved the light-load efficiency and also permitted the use of inexpensive hyperfast rectifier diodes, while reducing the size of the converter by using fewer components. As discussed in section 1.5 of chapter 1, an interleaved, multi-cell configuration that uses ‘n’ number of cells in parallel (both at the input and output) with each cell being phase-shifted by 360o/n for high power application is an interesting approach.  Due to interleaving, each cell shares equal power, and the thermal losses are distributed uniformly among the cells, and also, the input/output ripple frequency of multi-cell configuration becomes ‘2n’ times the switching frequency of each cell, which reduces the                                                  4 Content from this chapter has been published in [D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "An Interleaved Zero Voltage Switching Full-Bridge DC-DC Converter with Capacitive Output Filter for a Plug-in-Hybrid Electric Vehicle Battery Charger," Proceedings of IEEE Energy Conversion Congress and Exposition (ECCE 2012), Raleigh, pp. 2827-2832, September 2012].  72 filter size and cost. Since there is no detailed analysis and step-by-step design procedure available in the literature for this configuration, this chapter presents a 2-cell, interleaved, full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM gating scheme. The layout of the chapter is as follows. Section 4.2 explains the operating principle; section 4.3 gives the design procedure for selecting various components and devices. Based on this design method, a 3.3 kW, 100 kHz, dc-to-dc converter is designed. PSIM simulation and experimental results are presented in Sections 4.4. Finally, performance evaluation of this converter with a benchmark converter is presented in Section 4.5. 4.2 Operating Principle The proposed interleaved, 2-cell, full-bridge dc-dc converter topology is illustrated in Figure 4.1. As shown in Figure 4.1, each cell A and B is the basic full-bridge converter as described in the previous chapter with the inputs and outputs of each cell connected in parallel. In order to obtain higher output power more cells could be connected in parallel in a similar fashion. Co1Co2DR1 DR2DR3 DR4LrHVBatteryQ1Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformer1:ntiLrVabVRec_iniRectIseciCo2DR1 DR2DR3 DR4LrQ1Q2Q3 Q4abVg1Vg3Vg2Vg41:ntiLrVabVRec_iniRectIsecHF TransformerCell-ACell-B Figure 4.1    A 2-cell interleaved trailing-edge PWM full-bridge converter with capacitive output filter  73  Figure 4.2    Typical operating waveforms to illustrate the operation of the trailing-edge PWM 2-cell, interleaved, full-bridge converter in DCM mode Vg1AVg2AVg3AVg4A+400V-400ViLrAvabATime (µs)iCo2Vg1BVg2BVg3BVg4B+400V-400ViLrBvabBiin 74 +400V-400V+400V-400VVg1AVg2AVg3AVg4AvabAiCo2Vg1BVg2BVg3BVg4BvabBiiniLrAiLrBTime (µs) Figure 4.3    Typical operating waveforms to illustrate the operation of the trailing-edge PWM 2-cell, interleaved, full-bridge converter in BCM mode  75  Figure 4.2 and 4.3 shows the operating waveforms of the converter when operated in discontinuous conduction (DCM) and boundary conduction modes (BCM) respectively. The operating principle of the converter individual cells in DCM and BCM modes is same as presented in section 3.2 of chapter 3 and is not discussed here. From Figure 4.2 and 4.3, it can be clearly seen that the input (iin) and output capacitor ripple (iCo2) current frequency is four times the switching frequency. Although the proposed converter can operate in DCM, BCM, or continuous conduction mode (CCM), only the DCM and BCM modes are desirable for the present application, as explained in section 3.3.1. Operation in CCM results in the lowest RMS currents, and ZVS can be achieved for all switches, but the high di/dt results in large reverse-recovery losses in the secondary-side rectifier diodes and high-voltage ringing. Moreover, to operate this converter in CCM requires a larger resonant inductor which also increases the transformer turns ratio and increases stress on the primary-side switches. Hence, this converter should be designed to operate in DCM, or BCM. 4.3 Design Procedure This section provides the details for designing and selection of various components of the trailing-edge PWM, 2-cell, interleaved, full-bridge converter, as discussed in the previous section. Based on the design procedure, a 3.3 kW dc-dc converter stage is designed to meet the specification of a level-2 charger as discussed in Table 1.2. The detailed specifications for designing the dc-dc converter are given in Table 4.1. In order to design a 2-cell interleaved dc-dc converter, it can be treated as two separate ZVS dc-dc converters; each operating at half of the load power rating. With this approach,  76 selection of operating modes, switching frequency (fs), and all equations for selecting the transformer turns ratio (nt), resonant inductor (Lr), MOSFETs (Q1 - Q4), and rectifier diodes (DR1 – DR4) in the full-bridge dc-dc converter with capacitive output filter (as discussed in section 3.3) remains valid, since the stresses are unchanged with the only exception being the reduced ripple current through the input and output filter capacitors. Table 4.1    Design specification of the Trailing-edge PWM Full-bridge dc-dc converter Parameters Value[Units] Input DC Voltage (from PFC stage) 380 to 420 [V] Output DC Voltage Range 200 to 450 [V] Maximum Output DC Current 11 [A] Maximum Output Power (at 300V output voltage) 3.3 [kW] Output Voltage Ripple < 4 [Vp-p] Efficiency Up to 96 [%] 4.3.1 HF Transformer Design An ER16x25x49 shape ferrite core (using material TP4D from TDG Cores) transformer was designed using turns ratio of 12(number of primary turns):14(number of secondary turns) to achieve a turns ratio nt of 1.17, as calculated in section 3.3.3 using Equation 3-5. Two 18 AWG (400 strands of 44 AWG wire) twisted Litz wires were used for primary winding and two 20 AWG (165 strands of 42 AWG wire) twisted Litz wires were used for secondary winding. 4.3.2 Selection of Output Filter Capacitor (Co2)  The worst case scenario of RMS current through the output filter capacitor Co2 is given in equation 4-1, and its capacitance value is determined using equation 4-2.   77  𝐼𝐶𝑜2(𝑟𝑚𝑠) = √1𝑇𝑃∫ (𝑖𝑅𝐸𝐶(𝑡) − 𝐼𝑜)2𝑑𝑡𝑇𝑃0= 3.4 [𝐴] 4-1    𝐶02 =𝐼𝐶𝑜2(𝑟𝑚𝑠)4𝜋𝑓𝑠𝑉𝑟𝑖𝑝𝑝𝑙𝑒= 5.4 [𝜇𝐹] 4-2 A 10 µF, 630V, film capacitor (part number: B32676G6106 from Epcos) was selected for the output filter capacitor. It should be noted here that the capacitor used is the same as the one used in chapter 3, but for 2x output power due to interleaving. The various components selected for the circuit are listed in Table 4.2. Table 4.2    Components Selection Parameters Value [Units] Q1A-Q4A and Q1B-Q4B FCB20N60F [each] DR1A-DR4A and  DR1B-DR4B ISL9R0860 [each] LrA and  LrB 33 [µH] Transformer turns ratio  1.17 Output Capacitor 10 [µF]  78 4.4 Simulation and Experimental Results The 3.3 kW 2-cell interleaved dc-dc converter designed in the previous section was simulated using PSIM software for Vo = 300 V and load current Io = 11 and 1 A. Typical HF waveforms obtained using PSIM simulation for the converter with an input voltage Vin = 400 V at full load and 10% load are shown in Figure 4.4 and 4.5, respectively.  Figure 4.4    Simulation results of resonant inductor LrA and LrB with current through the output filter capacitor Co2 at Vin = 400 V and Vo = 300 V and Io = 1 A  Figure 4.5    Simulation results of Figure 4.4 repeated at at Vin = 400 V and Vo = 300 V and Io = 11 A  79 As seen in Figure 4.4 and 4.5, at lighter load, both the cells operate in DCM and in BCM at full-load condition, respectively. Also both the resonant inductors equally share the currents, and the frequency of the ripple current in the output filter capacitor is four times the switching frequency. A 2-cell 3.3 kW experimental prototype was built to verify the operation of the proposed converter. A photo of the prototype is provided in Figure 4.6. Output CapacitorFull-bridge MOSFETs AFull-bridge MOSFETs BTransformer ATransformer BResonant Inductor AResonant Inductor BRectifier Diodes BControl Board Figure 4.6    Experimental prototype of 3.3 kW, 2-cell, interleaved, full-bridge dc-dc converter with capacitive output filter  80 HV BatteryVcmdIcmdIloopRiCiClampVloopRvCvPeak I Mode PWM #1Peak I Mode PWM #2External Clock Synchronising Circuit Gatedrive signalsGatedrive signalsPrimary current sensePrimary current sense Figure 4.7    An inner-loop, current-sharing control scheme The feedback control scheme for the proposed converter configuration is shown in Figure 4.7. An inner-loop, current-sharing control scheme is used to achieve current sharing among both the cells. Inner-loop current-sharing is inherently peak current-mode control. The output of the current/voltage compensator serves as the current-sharing bus and provides the output current reference for both the cells. For interleaving, an external clock synchronizing circuit is used to phase-shift cell B by 180° with respect to cell A. Experimentally measured efficiency curves at Vo = 200, 300, 400 and 450 V output over the entire power range with Vin = 400 V are provided in Figure 3.14. It should be noted that the converter achieves a peak efficiency of 95.7 % at Vo = 400 V, Io = 6 A and output power of 2.4 kW. At maximum output current Io = 11 A, Vo = 300 V, and output power of 3.3 kW the converter achieves an efficiency of 95 %.   81  Figure 4.8    Experimental measured efficiency of the proposed converter as a function of output power at 400 V input and different output voltages It should be also noted that below 25 % of the output power of 1.65 kW the efficiency reduces drastically. This is due to turn-on and turn-off switching losses of Q1 and Q2 dominating at lighter loads. The light-load efficiency can be significantly improved by completely turning-off a cell below 50% of rated load power. Experimental waveforms of the dc-dc converter in DCM and BCM mode are provided in Figure 4.9 and 4.10. It is noted that the MOSFET Q3B turns on with ZVS and turns off with ZCS, and the current through the transformer secondary winding also has a very low di/dt. It is also noted that both the cells equally share the load current, which aids in distributing thermal losses between the two cells and thus helps in improving efficiency. 86878889909192939495960 1000 2000 3000 4000Efficiency (%)Output Power (W)Vo = 150VVo = 200VVo = 300VVo = 400 V 82 Drain-Source Voltage VDS-Q3BGating Signal VGS-Q3BTransformer A Sec. Winding CurrentTransformer B Sec. Winding CurrentZVS Turn-on of Q3 Figure 4.9    Experimental waveforms of the MOSFET Q3B voltage and transformer secondary winding current at Vin = 400 V, Vo = 300 V, Po = 300 W and fs = 100 kHz. Ch1=VDS-Q3B 200 V/div. Ch2= VGS-Q3 10 V/div. Ch3= Tx. B Sec. current 2 A/div. Ch4= Tx. A Sec. current 2 A/div.Time scale=2 µs/div. Drain-Source Voltage VDS-Q3B Gating Signal VGS-Q3BTransformer A Sec. Winding CurrentTransformer B Sec. Winding CurrentZVS Turn-on of Q3 Figure 4.10    Experimental waveforms of Figure 4.10 repeated for Vin = 400 V, Vo = 300 V, Po = 3300 W and fs = 100 kHz. Ch1=VDS-Q3B 200 V/div. Ch2= VGS-Q3 10 V/div. Ch3= Tx. B Sec. current 10 A/div. Ch4= Tx. A Sec. current 10 A/div.Time scale=2 µs/div.   83 4.5 Performance Evaluation An efficiency comparison of the proposed converter with the benchmark interleaved ZVS full-bridge dc-dc converter with inductive output filter is provided in Figure 4.11. The benchmark converter was also operated with trailing-edge PWM gating. The benchmark converter circuit is illustrated in Figure 4.12, and the list of components used is provided in Table 4.3. The overall efficiency of the proposed converter, particularly at light load conditions, is much higher than the benchmark counterpart. The benchmark converter has lower efficiency due to losses in the secondary-side RCD clamp circuit.  Figure 4.11    Efficiency comparison for the proposed converter as a function of output power at 400 V input and 300V output voltage and benchmark converter 788082848688909294960 1000 2000 3000 4000Efficiency (%)Output Power (W)Vo = 300V Proposed ConverterVo = 300V Benchmark Converter 84 Co1Co2DR1ADR2ALLKAHVBatteryQ1AVoIoabVinLLKBabQ3AQ2AQ4AQ1BQ3BQ2BQ4BDR3ADR4ADR1BDR2BDR3BDR4BCCARCADCACCBRCBDCBLOALOB Figure 4.12    Benchmark 2-Cell Interleaved PWM ZVS full-bridge converter topology with inductive output filter Table 4.3    Components Used In the Benchmark Converter Parameters Value [Units] Q1A-Q4A and Q1B-Q4B FCB20N60F [each] DR1A-DR4A and  DR1B-DR4B ISL9R0860 [each] Transformer turns ratio  1.22 Transformer Leakage Inductance  1.6 [µH] Output Inductor 600 [µH] DC-DC Switching Frequency 70 kHz]  4.6 Conclusions An interleaved, 2-cell, full-bridge dc-dc converter with capacitive output filter operating with trailing-edge PWM gating has been presented in this chapter. The proposed converter has been analyzed in BCM and DCM modes. A 2-cell, 3.3 kW dc-dc converter laboratory prototype was build based on the step-by-step procedure presented in the chapter. It has been shown that both the cells share the total output power equally, thereby equally sharing the power losses between the two cells. It was also shown that by interleaving the ripple  85 frequency in the input and output filter capacitors are doubled which aids in reducing the size of the filter components. In order to reduce the number of rectifier diodes by half (resulting in lower cost and overall lower converter size), a new topology, an interleaved, multi-cell, full-bridge dc-dc converter with voltage-doubler rectifier and capacitive output filter operating with trailing-edge PWM gating is presented in the next chapter.               86 Chapter  5: An Interleaved, Full-Bridge DC-DC Converter with Voltage-Doubler Rectifier and Capacitive Output Filter Operated with Trailing-Edge PWM Gating5 5.1 Introduction This chapter presents an interleaved, full-bridge dc-dc converter with voltage doubler rectifier and capacitive output filter operating with trailing-edge PWM gating scheme, as discussed in chapter 1, for use in the dc-dc converter stage of a PHEV on-board battery charger. In chapter 3, the trailing-edge PWM full-bridge dc-dc converter with capacitive output filter was presented. It was shown in chapter 3 that the full-bridge converter with capacitive filter significantly improved the light-load efficiency and also permitted the use of inexpensive hyperfast rectifier diodes. This reduced the size of the converter by using fewer components. For higher power application, an interleaved, multi-cell configuration that uses two cells in parallel (both at the input and output) was presented in chapter 4. It was shown in chapter 4, that due to interleaving, each cell shares equal power and the thermal losses are distributed uniformly among the cells. The input/output ripple frequency becomes 4 times the switching frequency of each cell which reduces the filter size and cost. In order to further reduce the size and cost of the converter configuration presented in chapter 4, a multi-cell, interleaved, full-bridge DC-DC converter with capacitive filter and voltage-doubler rectifier operated with trailing-edge PWM gating scheme is an attractive solution for                                                  5 Content from this chapter has been published in [D.S. Gautam, Fariborz Musavi, Murray Edington, W. Eberle and W.G. Dunford, "An Isolated Interleaved DC-DC Converter with Voltage Doubler Rectifier for PHEV Battery Charger, "Proceedings of IEEE Applied Power Electronics Conference and Exposition (APEC 2013), Long Beach, pp. 3067-3072, Mar. 2013].  87 the present application. The output voltage-doubler rectifier reduces half the number of secondary diodes (resulting in lower cost and overall lower converter size) as compared to the topology presented in the previous chapter. Since there is no detailed analysis and step-by-step design procedure available in the literature for this configuration, this chapter presents a 2-cell, interleaved, full-bridge dc-dc converter with voltage-doubler rectifier and capacitive output filter operating with trailing-edge PWM gating scheme. The layout of the chapter is as follows. Section 5.2 first explains the operating principle of the basic full-bridge dc-dc converter with voltage-doubler rectifier and later presents the proposed interleaved converter with voltage-doubler rectifier; section 5.3 gives the design procedure for selecting various components and devices. Based on this design method, a 3.3 kW, 100 kHz, dc-to-dc converter is designed. PSIM simulation and experimental results are presented in Sections 5.4. Finally, performance evaluation of this converter with benchmark converters is presented in Section 5.5. 5.2 Operating Principle Co1Co2CinDR1DR2LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformer1:ntiLrVabIseciCo2iCo1 Figure 5.1    Trailing-edge PWM Full-bridge dc-dc converter with voltage-doubler rectifier and capacitive output filter The circuit diagram of the full-bridge dc-dc converter with voltage-doubler rectifier and capacitive output filter operating with trailing-edge PWM gating scheme is shown in Figure  88 5.1. Detailed operating waveforms are provided for DCM in Figure 5.2 and for BCM in Figure 5.3. Vg1Vg2Vg3Vg4+400V-400ViLrvabTime (µs)vDR1T0 T1 T2 T3 T4 T5 T6vo1 2 3 4 5 6DevicesIntervalsQ1,Q4, DR1DQ3,Q4,DR1DQ4,Q3,DR2Q2,Q3,DR2TTPIP1iDR1iCo1 Figure 5.2    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter with voltage doubler-rectifier in DCM mode  89 Vg1Vg2Vg3Vg4+400V-400ViLRvoTime (µs)T0 T1 T2 T3 T4 T5 T61 2 3 4 5 6DevicesIntervalsQ1,Q4, DR1DQ3,Q4, DR1DQ4,Q3,DR2Q2,Q3,DR2DQ3,Q4,DR1DQ4,Q3,DR2TIP2TPIP1vDR1iDR1iLrvabTPiCo1 Figure 5.3    Typical operating waveforms to illustrate the operation of the trailing-edge PWM full-bridge converter with voltage-doubler rectifier in BCM mode  90 The operation of this converter can be explained in the same way as the converter presented in chapter 3; the only exception being the converter in Figure 5.1 has only two rectifier diodes (DR1 and DR2) and two voltage divider output filter capacitors (Co1 and Co2).  Figure 5.4 and 5.5 shows the operation of the circuit for interval 1, 2 and 3 during DCM and BCM operating modes. Co1Co2CinDR1DR3LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformer1:ntiLrVabIseciCo2iCo1 Figure 5.4    Equivalent circuit for Interval 1 for DCM and BCM During Interval 1, switches Q1 and Q4 are on and Q2 and Q3 are off. This is a power transfer interval, and the primary current flows through Q1, resonant inductor (Lr), transformer primary, and Q4, as illustrated in Figure 5.4. The rate of rise of the current (di/dt) through Lr is proportionate to the difference between the input voltage Vin and the output voltage Vo.  On the secondary-side, the current flows out of the secondary winding of the transformer through diode DR1, filter capacitor Co1, and back to the winding of the transformer. Capacitor Co1 and Co2 also supplies the load current Io to the HV battery. Referring to Figure 5.5, interval 2 begins after switch Q1 turns off, as determined by the PWM duty cycle. Since the current flowing in the primary side cannot be interrupted instantaneously, it finds an alternate path and flows through the parasitic switch capacitances of Q3 and Q1, which discharges the node ‘a’ to 0V and then forward biases the body diode DQ3. During this switch transition, the energy stored in the resonant inductor (Lr) assists in transferring energy from the lower to upper bridge MOSFET capacitance. Therefore switches  91 Q3 and Q4 always achieve ZVS with the help of the energy stored in the resonant inductor (Lr) for nearly the entire load current (Io) range.  Co1Co2CinDR1DR2LrHVBatteryQ1 Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformer1:ntiLrVabIseciCo2iCo1 Figure 5.5    Equivalent circuit for Interval 2 for DCM and Interval 2 and 3 for BCM  During interval 2 the energy stored in Lr is transferred to the output. The primary resonant inductor (Lr) maintains the current, which circulates around the path of body diode of Q3, resonant inductor (Lr), transformer primary, and Q4, as illustrated in Figure 5.5. The rate of the downslope of the current through Lr is proportionate to the output voltage Vo. The only difference in DCM is that at T2 the energy stored in Lr is transferred to the output, the current becomes zero, and the rectifier diodes DR1 and DR4 turn-off as illustrated in Figure 5.2. In BCM, the current through the resonant inductor doesn’t reach zero at T2, and the rectifier diode DR1 is still on. Referring to Figure 5.2, in DCM, during interval 3 no power is transferred to the secondary. During this interval, the parasitic capacitances of the rectifier diodes resonate with LR as illustrated in Figure 5.2, and the current in the resonant inductor remains zero (𝑖𝐿𝑟 = 0). Referring to Figure 5.3 and 5.5 in BCM, during interval 3 the resonant inductor current continues to circulate around the path of DQ3, resonant inductor (Lr), transformer primary, and Q4. The rate of the downslope of the current through Lr is proportionate to the output voltage Vo. At T3, the entire energy stored in Lr is transferred to the output, the current becomes zero, and the rectifier diode DR1 turns off.  92 The proposed interleaved, 2-cell, full-bridge dc-dc converter with voltage-doubler rectifier topology is illustrated in Figure 5.6. As shown in Figure 5.6, each cell A and B is the basic full-bridge converter with voltage-doubler rectifier as shown in Figure 5.1, where both the inputs and outputs of each cell are connected in parallel. Co1Co2CinDR1 DR2DR3 DR4LrHVBatteryQ1Q2Q3 Q4VoIoabVinVg1Vg3Vg2Vg4HF Transformer1:ntiLrVabIseciCo2LrQ1Q2Q3 Q4abVg1Vg3Vg2Vg41:ntiLrVabIsecHF TransformerCell-ACell-BiCo1 Figure 5.6    A 2-cell, interleaved, trailing-edge PWM, full-bridge converter with voltage-doubler rectifier and capacitive output filter Figure 5.7 and 5.8 shows the operating waveforms of the converter when operated in discontinuous conduction (DCM) and boundary conduction modes (BCM) respectively. The operating principle of the converter individual cells in DCM and BCM modes is same as presented in beginning of this section 5.2 of this chapter. From Figure 5.7 and 5.8, it can be clearly seen that the input current (iin) frequency is four times of the switching frequency, but the output capacitor ripple (iCo2) is the same as the switching frequency. This interleaving configuration doesn’t offer any benefits for output filter capacitor size reduction.   93 Vg1AVg2AVg3AVg4A+400V-400ViLrAvabATime (µs)iCo2Vg1BVg2BVg3BVg4B+400V-400ViLrBvabBiin Figure 5.7    Typical operating waveforms to illustrate the operation of the trailing-edge PWM, 2-cell, interleaved, full-bridge converter with voltage-doubler rectifier in DCM mode  94 +400V-400V+400V-400VVg1AVg2AVg3AVg4AvabAiCo2Vg1BVg2BVg3BVg4BvabBiiniLrAiLrBTime (µs) Figure 5.8    Typical operating waveforms to illustrate the operation of the trailing-edge PWM, 2-cell, interleaved, full-bridge converter with voltage-doubler rectifier in BCM mode  95 Although the proposed converter can operate in DCM, BCM, or continuous conduction mode (CCM), only the DCM and BCM modes are desirable for the present application, as explained in section 3.3.1. Operation in CCM results in the lowest RMS currents and ZVS can be achieved for all switches, but the high di/dt results in large reverse-recovery losses in the secondary side rectifier diodes and high-voltage ringing. Moreover, to operate this converter in CCM, requires a larger resonant inductor, which also increases the transformer turns ratio and increases stress on the primary-side switches. Thus, this converter should be designed to operate in DCM, or BCM. 5.3 Design Procedure This section provides the details for designing and selection of various components for the trailing-edge PWM 2-cell interleaved full-bridge converter with voltage doubler rectifier. As discussed in the previous section based on the design procedure, a 3.3 kW dc-dc converter stage is designed to meet the specification of a level-2, charger as discussed in Table 1.2 of chapter 1. The detailed specifications for designing the dc-dc converter are given in Table 5.1. In order to design a 3.3 kW 2-cell interleaved dc-dc converter, it can be treated as two separate ZVS dc-dc converters with each operating at half of the load power rating (1.65 kW). With this approach, selection of operating modes, switching frequency (fs), and all equations for selecting the MOSFETs (Q1 - Q4) in the full-bridge dc-dc converter with capacitive output filter (as discussed in section 3.3 of chapter 3) remains valid. The procedure to select the transformer turns ratio (nt), resonant inductor (Lr), rectifier diodes (DR1 – DR2), and output filter capacitor (Co1 – Co2) is presented here.    96 Table 5.1    Design specification of the Trailing-edge PWM Full-bridge dc-dc converter Parameters Value[Units] Input DC Voltage (from PFC stage) 380 to 420 [V] Output DC Voltage Range 200 to 450 [V] Maximum Output DC Current 11 [A] Maximum Output Power (at 300V output voltage) 3.3 [kW] Output Voltage Ripple < 4 [Vp-p] Efficiency Up to 96 [%] 5.3.1 Selection of Transformer Turns Ratio (nt) The transformer turns ratio nt is calculated using equation 5-1 where Dmax is the maximum duty-cycle.  𝑛𝑡 = 𝑉𝑜𝑚𝑎𝑥2𝐷𝑚𝑎𝑥𝑉𝑖𝑛 5-1 The transformer turns ratio is determined to be 0.6 for Vin = 400 V, Vomax = 450 V at maximum duty cycle of Dmax = 0.96. An ER16x25x49 shape ferrite core (using material TP4D from TDG Cores) transformer was designed using turns ratio of 10(number of primary turns):6(number of secondary turns). Two 19 AWG (360 strands of 44 AWG wire) twisted Litz wires were used for primary winding and three 18 AWG (400 strands of 44 AWG wire) Litz wires were used for secondary winding. 5.3.2 Selection of Resonant Inductor (Lr) The converter DC gain in DCM (MDCM) is given by equation 5-2 and 5-3, where nt is the transformer turns ratio; D is the duty cycle; k is the normalized time constant of the converter; Lr is the resonant inductor, which also includes the leakage inductance of the transformer; Ro is the load resistance; and T is the switching period.  97  𝑀𝐷𝐶𝑀 =𝑉𝑜𝑉𝑖𝑛=4𝑛𝑡1 + √1 +16𝑘𝐷2 5-2 The normalized time constant of the converter is given by:  𝑘 =  4𝑛𝑡2𝐿𝑟𝑅𝑜𝑇 5-3 The converter DC gain in BCM is given by:  𝑀𝐵𝐶𝑀 =𝑉𝑜𝑉𝑖𝑛= 2𝐷𝑛𝑡 5-4 Using equations 5-1 to 5-4 the design curves are plotted for Gain versus Duty cycle for various values of k in DCM and BCM, as shown in Figure 3.12.  Vo = 300 VDCM Gain k = 0.0025Duty Cycle (D)Gain0 0.25 0.5 0.75 100.250.50.7511.25Design Operating PointDCM Gain k = 0.25Vo = 150 VBCM Gain DCM Gain k = 0.089Vo = 450 V Figure 5.9    Design Curve obtained for Gain versus Duty cycle for various values of k in DCM and BCM  98 To operate an individual converter cell in BCM at maximum output current of Io = 5.5A and Vo = 300V (Pomax = 1.65kW), k = 0.089 is selected as shown in Figure 5.9. Finally, using Equation 5-3 and k = 0.089, the resonant inductor Lr = 33 µH is selected. The 33 µH inductor was designed using a RM12 ferrite core (Material: N97 from Epcos) with an air gap of 2.1 mm and by winding 18 turns of 19 AWG Type 2 Litz wire (5x46 strands of 42 AWG wire). 5.3.3 Selection of Rectifier Diodes (DR1 – DR2) The average current through the output rectifier diodes DR1 to DR2, IDR(ave) is given by:  𝐼𝐷𝑅(𝑎𝑣𝑒) = 𝐼𝑜 5-5 Average current through the rectifier diodes was calculated to be 5.5 A using equation 5-5 for Io = 5.5 A for individual converter cell. A 600 V, 15 A hyperfast diode (part number: ISL9R1560 from Fairchild) was selected for the four rectifier diodes.  99 5.3.4 Selection of Output Filter Capacitors (Co1 and Co2)  The worst case ripple current through the output filter capacitors Co1 and Co2 is 9A rms, and the maximum voltage across the capacitor is 225 V DC. Four 2.2 µF, 250 V ceramic capacitors from Murata (part number: KC355WD72E225M) are connected in parallel to obtain 8.8 µF. The ripple current rating for this capacitor (part number: KC355WD72E225M) is 5A rms at 100 kHz. A photo showing paralleled capacitors for realizing output filter capacitor Co1 and Co2 is shown in Figure 5.10.  Figure 5.10    Output filter capacitor C01 and C02 The various components selected for the circuit are listed in Table 5.2. Table 5.2    Components Selection Parameters Value [Units] Q1A-Q4A and Q1B-Q4B FCB20N60F [each] DR1A-DR2A and  DR1B-DR2B ISL9R0860 [each] LrA and  LrB 32 [µH] Transformer turns ratio  1.17 Transformer Leakage Inductance  0.7 [µH] Output Capacitor 8.8 [µF]  100 5.4 Simulation and Experimental Results The 3.3 kW 2-cell interleaved dc-dc converter with voltage-doubler rectifier design described in the previous section was simulated using PSIM software for Vo = 300 V and load current Io = 1 and 11 A. Typical HF waveforms obtained using PSIM simulation for the converter with an input voltage Vin = 400 V at full load and 10% load are shown in Figure 5.11 and 5.12, respectively.  Figure 5.11    Simulation results of resonant inductor LrA and LrB with current through the output filter capacitors Co1 and Co2 at Vin = 400 V and Vo = 300 V and Io = 1 A  Figure 5.12    Simulation results of Figure 5.11 repeated at Vin = 400 V and Vo = 300 V and Io = 11 A  101 As seen in Figure 5.11 and 5.12, at lighter load, both the cells operate in DCM and in BCM at full-load condition, respectively. Also, both the resonant inductors equally share the currents, and the frequency of the ripple current in the output filter capacitor is same as the switching frequency. Figure 5.13 and 5.14 shows the simulation results of voltage across and current through rectifier diode DR2A and DR2B in DCM and BCM, respectively. As seen, the voltage across the diode is clamped to the output voltage, at Vo = 300 V, and the di/dt through the diode is low enough to minimize the losses due to reverse-recovery issues inherent with hyperfast diodes. VDR2A         I(DR2A)*20VDR2B         I(DR2B)*20 Figure 5.13    Simulation results of voltage across and current through output rectifier diodes DR2A and DR2B at Vin = 400 V and Vo = 300 V and Io = 1 A VDR2A         I(DR2A)*20VDR2B         I(DR2B)*20 Figure 5.14    Simulation results of Figure 5.13 repeated at Vin = 400 V and Vo = 300 V and Io = 11 A  102 A 2-cell, 3.3 kW experimental prototype was built to verify the operation of the proposed converter. A photo of the prototype is provided in Figure 5.15.  Figure 5.15    Experimental prototype of 3.3 kW 2-cell interleaved full-bridge dc-dc converter with voltage-doubler rectifier and capacitive output filter HV BatteryVcmdIcmdIloopRiCiClampVloopRvCvPeak I Mode PWM #1Peak I Mode PWM #2Gatedrive signalsGatedrive signalsPrimary current sensePrimary current senseExternal Clock Synchronising Circuit  Figure 5.16    An inner-loop current-sharing control scheme  103 The feedback control scheme for the proposed converter configuration is shown in Figure 5.16, and, as can be seen, its implementation is similar to one presented in section 4.4 of the previous chapter. Experimentally measured efficiency curves at Vo = 200, 300, 400 and 450 V output over the entire power range with Vin = 400 V are provided in Figure 5.17. It should be noted that the converter achieves a peak efficiency of 96 % at Vo = 400 V, Io = 7 A and output power of 2.8 kW. At maximum output current Io = 11 A, Vo = 300 V and output power of 3.3 kW, the converter achieves an efficiency of 95.2 %.   Figure 5.17    Experimental measured efficiency of the proposed converter as a function of output power at 400 V input and different output voltages It should be also noted that below 25 % of the output power of 1.65 kW the efficiency reduces drastically; this is due to turn-on and turn-off switching losses of Q1 and Q2 dominates at lighter load. The light-load efficiency can be significantly improved by completely turning-off a cell below 50% of rated load power. 808284868890929496980 1000 2000 3000Efficiency (%)Output Power (W)Vo = 400VVo = 300VVo = 200VVo = 150V 104 Experimental waveforms of the dc-dc converter in DCM and BCM mode are provided in Figure 5.18 and 5.19. It is noted that the MOSFET Q3B turns on with ZVS and turns off with ZCS, and the current through the resonant inductor also has a very low di/dt. It is also noted that both the cells equally share the load current, which aids in distributing thermal losses between the two cells and helps in improving efficiency. Drain-Source Voltage VDS-Q3BGating Signal VGS-Q3BResonant Inductor LRA CurrentResonant Inductor LRB CurrentZVS Turn-on of Q3Q3 anti-parallel diode conductionZCS Turn-off of Q3 Figure 5.18    Experimental waveforms of current through resonant inductor LRA and LRB and MOSFET Q3B voltage at Vin = 400 V and Vo = 300 V, Po = 300 W and fs = 100 kHz. Ch1=VDS-Q3B 200 V/div. Ch2= VGS-Q3 10 V/div. Ch3= Resonant inductor LrA current 5 A/div. Ch4= Resonant inductor LrB 5 A/div. Time scale=2 µs/div. Figure 5.20 and 5.21 show the experimental results of voltage across rectifier diode DR2B and current through transformer B secondary winding in DCM and BCM, respectively. The voltage across the diode is clamped to the output voltage, at Vo = 300V, and the di/dt through the secondary winding (which is same as the rectifier diode current), is low enough to minimize any issues due to reverse recovery inherent with hyperfast diodes. The current through the secondary winding reduces to 0 A naturally prior to turning-off, enabling the diodes to turn-off with ZCS.  105 Drain-Source Voltage VDS-Q3BGating Signal VGS-Q3BResonant Inductor LRA CurrentResonant Inductor LRB CurrentZVS Turn-on of Q3Q3 anti-parallel diode conductionZCS Turn-off of Q3 Figure 5.19    Experimental waveforms of Figure 5.18 repeated for Vin = 400 V and Vo = 300 V, Po = 3300 W and fs = 100 kHz. Ch1=VDS-Q3B 200 V/div. Ch2= VGS-Q3 10 V/div. Ch3= Resonant inductor LrA current 10 A/div. Ch4= Resonant inductor LrB 10 A/div. Time scale=2 µs/div. Transformer B Sec. CurrentRectifier Diode Voltage DR2BResonant Inductor LRB CurrentZCS Turn-off of DR2B Figure 5.20    Experimental waveforms of current through resonant inductor LrB and transformer B secondary winding and voltage across diode DR2B at Vin = 400 V and Vo = 300 V, Po = 300 W and fs = 100 kHz. Ch1= VDR2B 100 V/div. Ch3= Tx. B Sec. winding current 5 A/div. Ch4= LRB current 5 A/div. Time scale=2 µs/div.  106 Transformer B Sec. CurrentRectifier Diode Voltage DR2BResonant Inductor LRB CurrentZCS Turn-off of DR2B Figure 5.21    Experimental waveforms of Figure 5.20 repeated for Vin = 400 V and Vo = 300 V, Po = 3300 W and fs = 100 kHz. Ch1= VDR2B 100 V/div. Ch3= Tx. B Sec. winding current 20 A/div. Ch4= LRB current 10 A/div. Time scale=2 µs/div. 5.5 Performance Evaluation  Figure 5.22    Efficiency comparison for the proposed converter as a function of output power at 400 V input and 300V output voltage and benchmark converter 788082848688909294960 500 1000 1500 2000 2500 3000 3500Efficiency (%)Output Power (W)Vo = 300V Proposed interleaved converter with 4diode voltage doubler rectifier and capacitive filterVo = 300V Benchmark interleaved converter withinductive filterVo = 300V Benchmark Interleaved converter with 4diode bridge rectifier and capacitive filter 107 An efficiency comparison of the proposed converter with the benchmark interleaved ZVS full-bridge DC-DC converter with capacitive output filter of Figure 4.1 and inductive output filter of Figure 4.12 is provided in Figure 5.22. The benchmark converters were also operated with trailing-edge PWM gating scheme.  The overall efficiency of the proposed converter is quite similar to the bench-mark converter with capacitive output filter. The main advantage of the proposed converter with voltage-doubler rectifier is that it requires only half the number of secondary rectifier diodes as compared to the benchmark converters.  The overall efficiency of the proposed converter, particularly at light-load conditions, is much higher than the benchmark counterpart with inductive output filter. The benchmark converter has lower efficiency due to losses in the secondary side RCD clamp circuit.  Thus the proposed interleaved dc-dc converter with voltage-doubler rectifier and capacitive output filter stands out as the best choice in terms of physical size, weight, cost and efficiency for power levels greater than 2 kW. 5.6 Conclusions An interleaved, 2-cell, full-bridge dc-dc converter with voltage-doubler rectifier and capacitive output filter operating with trailing-edge PWM gating has been presented in this chapter. The proposed converter has been analyzed in BCM and DCM modes. A 2-cell, 3.3 kW dc-dc converter laboratory prototype was build based on the step-by-step procedure presented in the chapter. It has been shown that both the cells share the total output power equally, thereby equally sharing the power losses between the two cells. The main advantage of the proposed converter is that, it requires only half the number of secondary rectifier diodes as compared to the converter presented in the previous chapter.   108 The overall efficiency of the proposed converter, particularly at light-load conditions, is much higher than the benchmark converter with inductive as well as capacitive output filter.  Thus this proposed converter with voltage-doubler rectifier stands out as the best choice in terms of physical size, weight, cost and efficiency for power levels greater than 2 kW.                     109 Chapter  6: Conclusion and Future Work 6.1 Introduction With the emergence of PHEV’s and EV’s, one of the main concerns is the increased stress on the existing utility grid infrastructure from the charging of high power battery packs. Another concern for consumers is the increasing utility costs, making it extremely necessary for on-board battery chargers to operate with high efficiency. Other key requirements for chargers include small size, low weight and low cost. As discussed in Chapter 1, the accepted power architecture for a battery charger includes an ac-dc converter with power factor correction (PFC) followed by an isolated dc-dc converter. To meet the above mentioned requirements, four different isolated dc-dc converter topologies have been proposed in this thesis.  Thus this chapter summarizes four different contributions of the thesis in section 6.2 and section 6.3 presents the scope of future work to be carried out. 6.2 Summary of Contributions 6.2.1 DC-DC Converter with Inductive Filter Operated with Trailing-Edge PWM Gating The first contribution is an isolated full-bridge dc-dc converter with inductive output filter operated with trailing-edge PWM gating scheme for level-2 on-board battery charging application. This converter was analyzed for all the operating intervals and based on the analysis a 3.3 kW dc-dc converter prototype was also designed. The proposed converter achieves a full-load efficiency of 96 % at an output of 400 V and 8.25 A and 94.9% at 300 V and 11 A. It is shown that both output voltage and current are nearly free from low-frequency (120 Hz) ripple. This is one of the important requirements for battery charging application. It is also shown that all the primary side switches achieve ZVS resulting in lower losses, which  110 simplifies heatsink design. Another major advantage of this converter over traditional phase-shifted converter is that, it can achieve 0 % duty-cycle at lighter and no load conditions by completely turning-off the PWM controlled switches. Some of the drawback like duty-cycle loss, high voltage rectifier diode ringing and circulating current on the primary side of the converter were also discussed. 6.2.2 DC-DC Converter with Capacitive Filter Operated with Trailing-Edge PWM Gating The second contribution is an isolated full-bridge dc-dc converter with capacitive output filter operated with trailing-edge PWM gating scheme. This converter overcomes all the issues inherent to converter with inductive filter such as duty-cycle loss, high voltage rectifier diode ringing and circulating current on the primary side of the converter. This converter was analyzed for all the operating modes and based on the analysis a 1.65 kW dc-dc converter was also designed to operate in BCM mode at full-load. The proposed converter achieves a peak efficiency of 95.7 % at an output of 400 V and 3 A and 94.9 % at 300 V and 5.5 A. It is shown that both output voltage and current are nearly free from low frequency (120 Hz) ripple. It is also shown that two primary side switches achieve ZVS at turn-on and ZCS at turn-off and other two switches achieve ZCS turn-on resulting in lower losses. All the four rectifier diodes achieve ZCS at turn-off enabling use of inexpensive hyperfast diodes since reverse recovery is no longer an issue with this topology. As compared to the converter with inductive filter, this converter doesn’t require lossy RCD voltage clamp circuit, since this converter doesn’t suffer from high voltage ringing issue. The voltage across the rectifier diode is naturally clamped to the output voltage. It is also shown that light-load efficiency of this converter is significantly higher than its inductive filter counterpart. Finally, this  111 converter can also achieve 0 % duty-cycle at lighter and no-load conditions by completely turning-off the PWM controlled switches. 6.2.3 Interleaved DC-DC Converter with Capacitive Filter Operated with Trailing-Edge PWM Gating As a third contribution a multi-cell, interleaved, isolated full-bridge dc-dc converter with capacitive output filter operated with trailing-edge PWM gating scheme is presented for level-2 (> 2 kW) where thermal management is a challenge with a single cell processing all the power required for battery charging application. To illustrate this concept a 3.3 kW 2-cell interleaved dc-dc converter with each cell operating at a maximum 1.65 kW of output power was designed. It is shown that both the cells shared the total output power equally thus illustrating power losses are also shared and distributed equally between the two cells, which increases the reliability of the converter. It is also shown that by interleaving the ripple frequency in the input and output filter capacitors are doubled which aids in reducing the size of the filter components.     6.2.4 Interleaved DC-DC Converter with Capacitive Filter and Voltage Doubler Rectifier In the fourth contribution a multi-cell, interleaved, isolated full-bridge dc-dc converter with capacitive output filter and voltage-doubler rectifier is presented. Voltage-doubler rectifier configuration reduces the size and cost of the overall converter by using only four diodes for 2-cell configuration without impacting the thermal management concerns.  To illustrate this concept, a 3.3 kW 2-cell interleaved dc-dc converter with each cell operating at a maximum 1.65 kW of output power was designed. The proposed converter achieves a peak efficiency of 96 % at an output of 400 V and 7 A and 95.2 % at 300 V and 11 A.  112  6.2.5 Comparison of Proposed Topologies Table 6.1 summarizes the performance of all the proposed topologies based on the analysis and experimental results presented in chapters 2 to 5. Based on the comparison presented in the Table 6.1, the interleaved dc-dc converter with voltage-doubler rectifier and capacitive output filter stands out as the best choice in terms of physical size, weight, cost and efficiency for power levels greater than 2 kW. For power levels under 2 kW, a single cell full-bridge dc-dc converter with capacitive filter would be a preferred choice. Table 6.1    Performance comparison of the proposed dc-dc converter topologies Topology Full-bridge dc-dc converter with inductive filter Full-bridge dc-dc converter with capacitive filter Interleaved full-bridge dc converter with capacitive filter Interleaved full-bridge dc converter with voltage doubler Power Rating < 3.3 kW < 2 kW > 2 kW > 2 kW EMI / Noise Poor Fair Good Good Output capacitor ripple Medium High Low High Magnetic Size Large Medium Medium Medium Efficiency Poor Fair Fair Best Power Density (W/in3) 232 221 266 338 Cost (W/$) 82 82 96 96 Weight Heavy Medium Medium Light Reliability Low Medium High Very High        113 6.3 Suggestions for Future Work This sub-section outlines the possible future work for the thesis topics. 6.3.1 Full-Bridge DC-DC Converter with Clamp Diodes to Reduce Rectifier Ringing Issues In order to reduce the high voltage ringing issue in full-bridge dc-dc converter with inductive output filter, clamp diodes could be implemented on the primary-side in between the external resonant inductor Lr and transformer winding thus reducing voltage stress on the rectifier diodes and reducing the size of the RCD clamp circuit. The circuit diagram of this configuration is shown in Figure 6.1 below. Co1 Co2LoCcRcDcDR1 DR2DR3 DR4HVBatteryQ1 Q2Q3 Q4abV VoIoLrClamp Diodes Figure 6.1    Trailing-edge PWM Full-bridge dc-dc converter with inductive output filter and clamp diodes 6.3.2 Full-bridge DC-DC Converter with Lossless Snubber In order to reduce turn-off losses in the primary-side PWM controlled switches of the full-bridge dc-dc converter with capacitive output filter (presented in Chapter 3), some form of active or passive lossless snubber could be implemented to increase the efficiency of the converter.     114 6.3.3 Feedback Control Analysis for the Interleaved DC-DC Converter with Capacitive Output Filter A detailed feedback control analysis is required to understand the dynamics of the interleaved dc-dc converter with capacitive output filter as shown in Figure 4.7 for battery charging application.    115 Bibliography [1] M. Ehsani, Y. Gao, S. E. Gay, and A. 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