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Biomedical telemonitoring systems with an emphasis on in-stent restenosis monitoring Keikhosravy, Kamyar 2014

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AbstractAdvances in microelectronic technologies have facilitated implementationof leading-edge circuits particularly in the realm of ultra-low-power circuitsand systems. The focus of this thesis is on the design of reliable integratedsolutions for telemonitoring of biomedical implants. In particular, we focuson diagnosing in-stent restenosis (re-narrowing) of coronary arteries afterangioplasty. To achieve more efficient wireless power delivery, a modifiedversion of conventional medical stent, namely antenna stent or stentenna, isused. In this work, two different systems are designed and fabricated in a0.13-µm complimentary metal-oxide semiconductor (CMOS) process.The first telemonitoring system converts the capacitive changes of the(pressure) sensors directly to a corresponding frequency change which will betransmitted to the external reader. Unique to this design is the alignmentunit which is designed to improve the physical alignment of external induc-tive antenna with the implanted stentenna for the purpose of wireless powertransfer. The system starts operating with the rectified voltage of as lowas 500 mV while consuming 4.15 µW, 3.4 µW of which is consumed by thetransmitter. The system is designed such that, in alignment mode, the fre-quency of the pilot signal is directly proportional to the value of the rectifiedsupply voltage. The monitoring unit, start operating from the supply voltageof 870 mV while drawing 111.25 µA. This system has been successfully testedin an in-vitro setup. The measured sensitivity of the system is 555 kHz/fF.This system is capable of detecting capacitance change of as low as 1.3 fF.The sensor interface circuit of the second system consists of a capacitance-to-voltage converter and the transmitter includes a voltage-to-frequency con-verter. The frequency for the transmitted signal is proportional to thechanges of the capacitance of the sensor. Measurement results of a proof-of-concept prototype show that the system operates from a harvested supplyof as low as 350 mV (from input power of -43.76 dBm at 1.25 GHz) whiledrawing less than 100 nA from its harvested supply. The sensitivity of thesystem is measured to be 55 kHz/fF.iiiPrefaceI, Kamyar Keikhosravy, am the principle contributor of all chapters ofthis dissertation. Professor Shahriar Mirabbasi who supervised the researchhas provided technical consultation and editing assistance on the manuscript.Pouya Kamalinejad provided technical assistance in the design of high-efficiencyrectifiers and reviewed the relative parts of the manuscript. Arash ZargaranYazd also provided technical assistance in simulating the optimum frequencyof transmission and preparing the relative manuscripts. Also, ProfessorKenichi Takahata and Professor Victor Leung provided technical and editingassistance. The material of some of the chapters, as described below, is eitheralready published or is under review:Conference papers:1. K. Keikhosravy, A. Zargaran-Yazd, and S. Mirabbasi, “On the useof smart stents for monitoring in-stent restenosis,” in InternationalConference of the IEEE Engineering in Medicine and Biology Society(EMBC), pp. 3231–3234, Aug. 28–Sept. 1 2012 (Chapter 2).2. K. Keikhosravy, P. Kamalinejad, S. Mirabbasi, K. Takahata, andV. C. Leung, “An ultra-low-power monitoring system for inductivelycoupled biomedical implants,” in IEEE International Symposium onCircuits and Systems (ISCAS), pp. 2283–2286, May 2013 (Chapter 3).3. K. Keikhosravy, P. Kamalinejad, S. Mirabbasi, K. Takahata, andV.C.M. Leung, “A feasibility study of using backscattering for telemon-itoring of in-stent restenosis,” International Conference of the IEEEEngineering in Medicine and Biology Society (EMBC), pp. 5167-5170,2013 (Chapter 6).iv4. K. Keikhosravy, P. Kamalinejad, S. Mirabbasi, and V.C.M. Le-ung, “A Wideband unity-gain buffer in 0.13-mm CMOS,”IEEE Inter-national Conference on Electronics, Circuits, and Systems (ICECS),2013 (Chapter 4).5. P. Kamalinejad, K. Keikhosravy, S. Mirabbasi, and V.C.M. Leung,“An efficiency enhancement technique for CMOS rectifiers with lowstart-up voltage for UHF RFID tags,” Green Computing Conference(IGCC), 2013 International , vol., no., pp.1,6, 27-29 June 2013.6. P. Kamalinejad, K. Keikhosravy, S. Mirabbasi, and V.C.M. Leung,“A CMOS rectifier with an extended high-efficiency region of opera-tion,”IEEE International Conference on RFID Technology and Appli-cations (RFID-TA), September 2013.7. P. Kamalinejad, K. Keikhosravy, M. Magno, S. Mirabbasi, V.C.M.Leung, and L. Benini,” A high-sensitivity fully passive wake-up radiofront-end for wireless sensor nodes,” to be presented in IEEE Interna-tional Conference on Consumer Electronics (ICCE), January 2014.Journal papers1. K. Keikhosravy and S. Mirabbasi, “Monolithic current-sensing topol-ogy for system-on-chip applications,” IET Electronics Letters, vol. 48,no. 21, pp. 1334-1336, October 11, 2012. (Appendix C)2. A. Zargaran-Yazd, K. Keikhosravy, H. Rashtian, and S. Mirabbasi,"Hardware-efficient phase-detection technique for digital clock and datarecovery,”IET Electronics Letters , vol. 49, no. 1, pp. 20-22, January3, 2013.3. K. Keikhosravy and S. Mirabbasi, “A 0.13-mm CMOS ultra-low-power capacitor-less LDO regulator using bulk-modulation technique,”Toappear in IEEE Transactions on Circuits and Systems-I (Appendix B).4. K. Keikhosravy, D. Brox, P. Kamalinejad, S. Mirabbasi, and K.vTakahata, “An ultra-low-power 35-nW wireless monitoring system forbiomedical applications,”submitted (Chapter 5).viTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xivAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiiiDedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Coronary Angioplasty and Stenting . . . . . . . . . . . . . . . 21.3 System Building Blocks and General Telemonitoring Approaches 51.3.1 Passive approach . . . . . . . . . . . . . . . . . . . . . 71.4 Active Telemetry Approach . . . . . . . . . . . . . . . . . . . 111.4.1 Frequency of transmission . . . . . . . . . . . . . . . . 111.4.2 Telemetry based on inductive coupling . . . . . . . . . 141.4.3 Telemetry based on electromagnetic waves propagation 16vii1.4.4 Ultrasonics-based telemetry . . . . . . . . . . . . . . . 171.5 Challenges in Wireless Monitoring of Restenosis in CoronaryArteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.6 Summary of Contributions . . . . . . . . . . . . . . . . . . . . 191.6.1 The proposed capacitance to frequency based telemon-itoring system . . . . . . . . . . . . . . . . . . . . . . . 191.6.2 The proposed capacitance to voltage based telemoni-toring system . . . . . . . . . . . . . . . . . . . . . . . 201.6.3 Study and analysis of telemonitoring based on backscat-tering . . . . . . . . . . . . . . . . . . . . . . . . . . . 211.7 Thesis Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Frequency of Operation . . . . . . . . . . . . . . . . . . . . . 232.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.2 Calculating The Optimum Frequency . . . . . . . . . . . . . 242.3 Modeling Smart Stent’s Environment for EM Simulations . . . 262.4 Experimental and Simulation Results . . . . . . . . . . . . . . 293 Telemonitoring System Based on Capacitance to FrequencyConversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.2 Power Harvesting Unit . . . . . . . . . . . . . . . . . . . . . . 353.2.1 Auxiliary and main transmitters . . . . . . . . . . . . . 403.2.2 Decision circuit . . . . . . . . . . . . . . . . . . . . . . 43viii3.3 Simulation and Measurement Results . . . . . . . . . . . . . . 454 Ultra-Wideband Analog Unity Gain Buffer . . . . . . . . . 574.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . 594.2.1 Circuit implementation . . . . . . . . . . . . . . . . . . 624.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 655 Capacitance-to-Voltage Converter Based Telemonitoring Sys-tem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715.2 The Proposed Telemonitoring Architecture . . . . . . . . . . . 745.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . 815.3.1 Rectifier stage . . . . . . . . . . . . . . . . . . . . . . . 815.3.2 Clock generator . . . . . . . . . . . . . . . . . . . . . . 845.3.3 Current source . . . . . . . . . . . . . . . . . . . . . . 855.3.4 Sample-and-hold circuit . . . . . . . . . . . . . . . . . 875.3.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . 885.4 Simulation and Experimental Results . . . . . . . . . . . . . . 895.4.1 DC performance . . . . . . . . . . . . . . . . . . . . . 915.4.2 Transient response . . . . . . . . . . . . . . . . . . . . 955.4.3 Frequency response . . . . . . . . . . . . . . . . . . . . 965.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101ix6 Feasibility Study on Backscattering Technique . . . . . . . 1026.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 1057 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127.1 Research Contributions . . . . . . . . . . . . . . . . . . . . . . 1127.1.1 Design and implementation of auxiliary systems andcircuit blocks . . . . . . . . . . . . . . . . . . . . . . . 1157.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117A A Monolithic Capacitor-less Wide-Band LDO Voltage Reg-ulator in 0.13-mm CMOS . . . . . . . . . . . . . . . . . . . . 134A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135A.2 LDO Regulator Analysis . . . . . . . . . . . . . . . . . . . . . 137A.2.1 Load regulation and line regulation . . . . . . . . . . . 138A.2.2 Settling time . . . . . . . . . . . . . . . . . . . . . . . 139A.3 The Proposed LDO Architecture . . . . . . . . . . . . . . . . 143A.3.1 Challenges with the conventional error amplifier . . . . 143A.3.2 Analytical background . . . . . . . . . . . . . . . . . . 146A.3.3 EA structure . . . . . . . . . . . . . . . . . . . . . . . 148A.3.4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . 150A.3.5 Opamp schematic . . . . . . . . . . . . . . . . . . . . . 153A.3.6 Band-gap circuit . . . . . . . . . . . . . . . . . . . . . 154xA.4 Experimental and Simulation Results . . . . . . . . . . . . . . 156A.4.1 DC measurements . . . . . . . . . . . . . . . . . . . . . 157A.4.2 Transient measurements . . . . . . . . . . . . . . . . . 159A.5 AC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 163A.6 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . 165B A 0.13-µm CMOS Low-Power Capacitor-less LDO RegulatorUsing Bulk-Modulation Technique . . . . . . . . . . . . . . 167B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168B.2 The Proposed LDO Structure . . . . . . . . . . . . . . . . . . 171B.3 The Proposed Bulk Modulation Technique . . . . . . . . . . . 175B.3.1 Driving capability . . . . . . . . . . . . . . . . . . . . . 175B.3.2 Transient behavior . . . . . . . . . . . . . . . . . . . . 179B.3.3 Stability analysis . . . . . . . . . . . . . . . . . . . . . 183B.4 Simulation and Experimental Results . . . . . . . . . . . . . . 188B.4.1 DC response . . . . . . . . . . . . . . . . . . . . . . . . 189B.4.2 Transient response . . . . . . . . . . . . . . . . . . . . 191B.4.3 Frequency response . . . . . . . . . . . . . . . . . . . . 197B.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201C A monolithic Current-Sensing Topology for System-on-ChipApplications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203C.2 Proposed Technique . . . . . . . . . . . . . . . . . . . . . . . . 205xiC.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212xiiList of Tables2.1 List of parameters of equation (2.2.1) used to predict the complexrelative permittivity of tissues from 10Hz up to 100GHz [1] . . . . 273.1 Performance summary and comparison of the proposed architecturewith the state-of-the-art designs for similar applications. . . . . . . 564.1 Performance summary and comparison with the state-of-the-art ana-log buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665.1 Performance summary and comparison between state-of-the-art de-signs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007.1 The summary of performance of the proposed systems in this work 114A.1 Dimensions of transistors in the architecture shown in Fig. A.3.5 . 154A.2 Transistor Dimensions of Band-gap Circuit . . . . . . . . . . . . . 156A.3 Performance summary and comparison with the state-of-the-art LDOs.166B.1 Performance summary and comparison with the state-of-the-art LDOs.199xiiiList of Figures1.3.1 A generic building block diagram of a biomedical telemonitoringsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3.2 Equivalent electrical schematic diagram of a generic smart stent. . 71.3.3 Electrical schematic diagram of the reader and stent in passive ap-proach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.3.4 The spectrum of input impedance Zinseen from reader side, forthis simulation Csen1 = 1 pF , Csen2 = 0.9 pF, Rstent = 1⌦ ,Lstent1 = Lstent2 = 50 nH , Lext = 1µF , Rrange = 50 ⌦ and k = 0.01 101.4.1 The three-dimensional view of the stentenna [2] . . . . . . . . . . . 111.4.2 Simulated matched power gain versus frequency (different causesof loss has been shown on frequency axes). [3] . . . . . . . . . . . 131.5.1 Efficiency of power transmission with respect to the distance be-tween reader and transponder antenna [3] . . . . . . . . . . . . . . 192.2.1 (a) Anatomical position of heart (side view) [4] demonstrating differ-ent layers of tissue between external reader and stent (b) Coronaryarteries are not covered by lung (front view) [5] . . . . . . . . . . . 25xiv2.3.1 The simulation setup in HFSS. The 2D contour of specified absorp-tion rate (SAR) is shown on the skin surface. This value is keptbelow the maximum allowable of 1.6 W/kg [2] . . . . . . . . . . . . 282.4.1 Experimental setup for measuring deliverable power to a stent an-tenna buried under 40 mm of ground beef. . . . . . . . . . . . . . 312.4.2 Experimental and simulated operational power gain (dB) versus fre-quency [2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.4.3 Power density (PD) of signals transmitted by the stent [2] . . . . . 333.1.1 Building blocks of the proposed embedded telemonitoring system. . 353.2.1 Schematic of the center tapped stentenna and differential rectifier. 373.2.2 Schematic of the second stage of the rectifier and the input capaci-tance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.2.3 Schematic of the proposed telemonitoring system. . . . . . . . . . . 393.3.1 Micrograph of the fabricated telemonitoring system consisting of1. auxiliary transmitter, 2. main transmitter, and the DBC anddecision circuit, and 3. rectifier circuit. . . . . . . . . . . . . . . . . 453.3.2 The micrograph of the chip emphasizing on the wire bond intercon-nect in the CQFP80 package. . . . . . . . . . . . . . . . . . . . . . 463.3.3 Schematic of the measurement setup. . . . . . . . . . . . . . . . . . 463.3.4 The measured output voltage versus the input voltage amplitude ofthe rectifier stage at 2.4 GHz. . . . . . . . . . . . . . . . . . . . . . 483.3.5 Measured response of different blocks of the transponder circuit asa function of the gradual increase of the input voltage level. . . . . 50xv3.3.6 Schematic of the unity gain buffer used for measuring the perfor-mance of the system. . . . . . . . . . . . . . . . . . . . . . . . . . . 513.3.7 Small-signal (in blue) and large-signal (in red) frequency responseof the unity gain buffer designed for testability of proposed system. 523.3.8 TX spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.3.9 The in-vitro measurement setup used in this work. . . . . . . . . . 543.3.10Transmitted signal frequency of alignment unit versus received inputlevel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554.1.1 The architecture of a conventional amplifier based analog buffer. . 594.2.1 Architecture of compound amplifier used in this design. . . . . . . 604.2.2 Pole-zero location of the proposed buffer . . . . . . . . . . . . . . 614.2.3 The overall schematic of analog buffer presented in this work. . . 624.2.4 Frequency response of the opamp and OTA. . . . . . . . . . . . . . 634.2.5 Frequency response of the compound amplifier. . . . . . . . . . . . 634.2.6 Simulated output voltage level of the OTA with and without thecommon-mode feedback circuit. . . . . . . . . . . . . . . . . . . . . 644.2.7 Measured step response of the proposed buffer for (a) 350 mV and(b) 700 mV of input step amplitudes. . . . . . . . . . . . . . . . . 654.3.1 Micrograph of the presented buffer. . . . . . . . . . . . . . . . . . . 674.3.2 Measured magnitude frequency response of the proposed buffer. . . 684.3.3 Output spectrum for a 133.33 mVppinput sinusoid at ⇠100 MHz. 685.1.1 Building blocks of a typical telemonitoring system. . . . . . . . . 735.2.1 Overall configuration of the proposed telemonitoring system. . . . 76xvi5.2.2 The simulated transient response of the CVC block for CSensor =1.9 pF and CRange = 1.4 pF at supply voltage of (a) 0.35 V (b)1.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805.3.1 Schematic of one stage of the three-stage differential rectifier. . . . 825.3.2 The schematic of clock generator current source and biasing circuit. 845.3.3 Example graphs of the simulated output current of the proposedarchitecture for VDD = 0.35V (solid line) and VDD = 1.0V (dashedline). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875.3.4 The architecture of the sample-and-hold used in CVC block . . . . 885.3.5 Schematic of active transmitter used in this design. . . . . . . . . . 885.4.1 Micrograph of the proposed telemonitoring system (a) without (b)with built-in variable capacitor. . . . . . . . . . . . . . . . . . . . 905.4.2 The wire-bond matching used in this work. . . . . . . . . . . . . . 905.4.3 The micrograph of the wire bond interconnects for CQFP80 pack-age. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915.4.4 Simulated and measured quiescent current for different supply voltages 925.4.5 The measure performance of the rectifier for different input signalfrequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935.4.6 The measured generated output voltage of the rectifier, while driv-ing the CVC system, versus different amplitude of the input voltageat 1.250 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955.4.7 Measured sensor and range voltages for CRange = 1.3 pF and (top)CSensor = 7.6 pF and (bottom) CSensor = 2.7 pF. . . . . . . . . . 96xvii5.4.8 Measured frequency spectrum of the proposed telemonitoring sys-tem for differentC at supply voltage of 0.35 V (top) and 1.0 V(bottom). 975.4.9 The simulated and measured output voltage of CVC block andtransmitted frequency of the overall system for different values ofC for (a) 1.0 V of supply voltage and (b) 0.35 V supply voltage(CSensor = CRange +C). . . . . . . . . . . . . . . . . . . . . . . . 986.0.1 Schematic diagram of backscattering telemonitoring system usingstent antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036.0.2 Comparison of the mesh of medical stent and stentenna . . . . . . 1046.1.1 In-vitro measurement setup. . . . . . . . . . . . . . . . . . . . . . . 1076.1.2 Measured backscattered power level versus different load values andinput powers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086.1.3 Backscattered power of stentenna compered to conventional stent. 1096.1.4 The Measured backscattered power from stentenna along verticaland horizontal axes. . . . . . . . . . . . . . . . . . . . . . . . . . . 1106.1.5 The measured normalized backscattered power received from thestentenna versus tissue thickness. . . . . . . . . . . . . . . . . . . . 1106.1.6 Measured backscattered power with/without layers of ground beef. 111A.1.1A generic block diagram of an LDO voltage regulator. . . . . . . . 136xviiiA.2.1Settling time of two conventional LDO regulators with unity-gainfrequencies of 1 GHz (solid line) and 100 MHz (dashed line), for(a) 500 ns (b) 1 ns load current transitions. The fast regulator hasless output change for the same load transition speed. Also, it canbe seen that for a slower load transition time, the output change(vout) is less severe for the faster regulator. . . . . . . . . . . . . 141A.3.1Small signal transconductance of a nMOS in 0.13 µm process versusdrain-source current. In this simulation the drain-source voltagekept constant and the overdrive voltage is swept. . . . . . . . . . 146A.3.2Sample Bode plots of two first-order systems S1, S2 and their par-allel combination S3, calculated in Matlab. In this example, G1 =60 dB, G2 = 20 dB, p1 = 10 rad/s and p2 = 100 k rad/s. . . . . . . 148A.3.3Compound error amplifier structure similar to that of [6] whichconsists of an OTA and an opamp and is used in the proposed LDOregulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149A.3.4Pole/zero locations of the open-loop voltage gain of the proposedLDO regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152A.3.5Schematics of the opamp used in the error amplifier . . . . . . . . 154A.3.6Band-Gap Reference voltage and bias circuit . . . . . . . . . . . . 155A.4.1Micrograph of the test chip which includes an open-loop LDO (LDO1), a close-loop LDO (LDO 2), and some additional test blocks. . 157A.4.2Measured DC line regulation in no-/full-load conditions. . . . . . . 158A.4.3Measured and simulated DC load regulation and quiescent currentof LDO regulator with built-in reference generator. . . . . . . . . . 159xixA.4.4Measured turn-on settling time w/o external reference voltage . . 160A.4.5Regulated ac-coupled output voltage of the regulator for VIN =1.27 + (0.55)⇥ sin((2⇡)38MHz). . . . . . . . . . . . . . . . . . . . . 160A.4.6Measured transient load regulation for: (a) full load to no-load (b)no-load to full-load transitions with CL = 0.7 pF. . . . . . . . . . . 161A.4.7(a) Simulated open-loop gain and phase responses for full load (500 µA)and no load (10 µA) with CL=0.5 pF. (b) Measured gain and phaseresponses for full load (500 µA) and CL ⇠=10 pF. . . . . . . . . . . 162A.5.1Measured PSR of the proposed regulator under full load (500µA). 164B.1.1Block diagram of a generic LDO voltage regulator. . . . . . . . . 169B.1.2Schematic of the proposed LDO regulator. To facilitate testing VBis applied externally. . . . . . . . . . . . . . . . . . . . . . . . . . . 170B.2.1Simulated gmb versus different bulk-source voltages for a typicalpmos pass transistor with (W/L) = (50µm/0.12µm). . . . . . . . 172B.2.2Block digram of the proposed LDO regulator. . . . . . . . . . . . . 174B.3.1Ibulk vs. VSB for VS = Vin = 1.2 V and VG = 800 mV. The sizeof the pmos transistor is the same as the pass transistor used inpresented LDO regulator(50µm/120nm). . . . . . . . . . . . . . . 176B.3.2The simulated ISD versus Vbulk for pass transistor. Note that thevalue of the ISD is normalized for VBS = 0 or Vbulk = 1.2 V. . . . . 178B.3.3Recovery time analysis for LDO regulator with and without bulkmodulation technique in (a) sudden plunge and (b) increase of theload current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180xxB.3.4(top) The phase margin of two regulators in extreme conditions.The proposed regulator in blue remains stable even when the con-ventional regulator is about to experience 180 of phase margin,(bottom) Total parasitic capacitance of the bulk of the pass tran-sistor versus the equivalent load resistance RL. . . . . . . . . . . . 183B.3.5Simulated open-loop bode diagram of the proposed LDO configura-tion with and without bulk modulation technique for load currentsof (a) 3 mA (RL = 0.33 k⌦), (b) 2 mA (RL = 0.5 k⌦), and (c) 0mA (no-load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185B.3.6Micrograph of the overall design including two LDO regulators high-lighted by blue-dashed line. . . . . . . . . . . . . . . . . . . . . . . 188B.4.1Experimental results of load regulation of the proposed regulatorcompared to the conventional one. . . . . . . . . . . . . . . . . . . 189B.4.2Measured DC response of the regulators to different input DC voltage.190B.4.3Measured start-up transition of the two regulators with and withoutbulk modulation technique. . . . . . . . . . . . . . . . . . . . . . . 191B.4.4Simulated line regulation. . . . . . . . . . . . . . . . . . . . . . . . 192B.4.5(a) The worst-case recovery time of both regulators measured from1 mA to 3.2 mA load transition with the 5 ns transition speed(averaged over 32 signals) and (b) the measured performance oftransient load regulation for load transition speed of 200 ns(averagedover 16 signals). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194xxiB.4.6(a) Simulated and (b) measured transient response of regulators,when the load current suddenly changes to 0 mA and (c) simulatedcurrent load change. . . . . . . . . . . . . . . . . . . . . . . . . . . 196B.4.7Measured and post-layout simulated PSR performance of regulatorswhile supplying 1 mA of load current. . . . . . . . . . . . . . . . . 198B.4.8Measurement setup for PSR experiments. . . . . . . . . . . . . . . 198C.1.1Top layout view of the proposed current-sensing technique. Thesensing path, formed by spiral-like path using two different metallayers and vias, is encircling the current path. . . . . . . . . . . . . 204C.1.2The current sheet is broken into several wires carrying equal currentsIk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204C.2.1Skin effect’s depth versus frequency of the passing current. . . . . . 207C.2.2Calculated (n) for different values of n, in 0.13 µm CMOS process. 208C.2.3The measured sensed voltage versus amplitude of current. The fre-quency of the current in this experiment is 7 GHz. . . . . . . . . . 211C.2.4Measured trans-resistance gain versus input current frequency aswell as calculated gain obtained from (C.2.6) and simulation resultsusing Momentum . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211xxiiAcknowledgmentsFirst and foremost, I would like to thank my parents and supportive family;their tremendous support and help have been the driving force of all myachievements.I would also like to thank my advisor, Professor Shahriar Mirabbasi, forhis supervision and guidance during my Ph.D. research. I appreciate hiscountless contributions and advice during the course of this research. He isindeed much more than an academic supervisor, I would always rememberhis altruistic support and valuable advice and will benefit from them in theupcoming stages of my life.I would also like to acknowledge the Natural Sciences and Engineering Re-search Council of Canada (NSERC) and the Canadian Institutes of HealthResearch for funding this project.I would also like to thank Canadian Microelectronics Corporation (CMC Mi-crosystems) for providing CAD tool support and facilitating chip fabrication.All my colleagues working at the System-on-a-Chip (SoC) Research Labora-tory deserve a huge thank you for their kind support.In addition, I would like to especially thank my previous professors, ProfessorParviz Jabedar Maralani at University of Tehran, and Professor Maher Kayalat École Polytechnique Federal de Lausanne (EPFL) for their valuable lessonsthat enlightened my perspective in research and life.xxiiiDedicationTo my parentsxxiv صد5 1234ه /و- , آن د)ت &ی ز#"د“ ”ق یک <=ه ;:1ه وا 7"دBکارخ GH                                                 ادهIماKLی اMNOP  رRSد !! sad-ha fereshte boose bar aan dast mizanand                                                                    kaz kaare khalgh yek gereh-e-baste vaa konad !“Hundreds of Angles are kissing a Hand                               That Opened a tied  Snag of the man  ” Mostafa Etemaadzadeh (M.D.)xxvChapter 1Introduction1.1 MotivationAdvances in Complimentary Metal-Oxide Semiconductor (CMOS) transis-tors technologies have facilitated implementation of leading-edge circuits suchas ultra-low-power systems. Ultra-low-power circuits are essential in manyapplications including biomedical implants particularly when the implant isrequired to operate from a harvested energy source. Many such implantsare used for monitoring ranging from electrocardiogram (ECG) [7] to elec-troencephalogram (EEG) [8], from blood pressure [9–14] to pressure andtemperature monitoring in ophthalmic devices [15] to arterial blood-oxygensaturation [16]. Due to the depth and size of the implanted device somedesigns are more challenging than others [14, 17–19]. Aside from some fullypassive designs [20–22], the majority of the reported monitoring systems rely1on power harvesting from an external reader. As it will be discussed in thefollowing chapters, the depth of the implant plays an important role on thepower budget of the implanted telemonitoring system. Lower power budgetfor deeper implants accompanied by more signal loss for communications be-tween the external reader and the implanted device adds to the design com-plexity of such systems. This work is focused on designing power-efficientimplantable monitoring systems. In particular, we focus on monitoring ofin-stent restenosis using an stent with embedded sensors and associated elec-tronic circuitry. The proposed techniques are general and can be used inother telemonitoring applications.1.2 Coronary Angioplasty and StentingHeart disease management plays a major role in health-care policies for va-riety of reasons including patient wellness as well as high treatment cost.In Canada alone, the cost of heart disease and stroke in physician services,hospital costs, lost wages and decreased productivity is more than $20.9 bil-lion every year [23]. Even with advances in health care, on average 16,000Canadians die each year due to a heart attack [24]. In 2007, approximately1.3 million Canadians (4.8% of the total population) were living with a heartdisease [25] . According to the American Heart Association, in 2008 the esti-mated total cost of heart failure in the United States totaled more than $35billion. The 1.1 million hospitalizations for congestive heart failure (CHF)2amounted to nearly $29 billion in hospital charges . As illustrated by theHome-Care Management Systems study (TEN-HMS), home-based telemoni-toring systems can facilitate more economical and convenient treatments forpatients with heart failure. . This can be attributed to the fact that patientsequipped with such home-care systems spend less time in hospitals result-ing in less hospitalization costs [26,27]. Such telemonitoring systems requireultra-low-power circuits that either harvest energy from the environment orhave an extended battery longevity. Design of such low-power circuits is thefocus of this research.Particularly, we consider the wireless monitoring of the in-stent resteno-sis for patients who had coronary-artery angioplasty. Coronary-artery an-gioplasty is a surgical method for treating narrowed arteries in patients withcoronary artery disease (CAD). A stent is a mesh like tube which is in-serted into the blocked or narrowed artery site to keep the lumen open.Although stent placement significantly decreases the probability of resteno-sis in angioplasty (as compared to balloon-only angioplasty), studies doneon patients with bare-metal stenting (BMS) show 33% of them suffer fromrestenosis within 6 months after the surgery [14]. In recent years, drug-elutedstents (DES) have gained popularity due to their success in reducing in-stentrestenosis. Despite their success, recent studies show that the restenosis oc-currence in DES sites after one year is around 3.5% and after 2 years reachesto 4.9% [28]. The probability of restenosis is higher for the smaller vesselsize, for example, restenosis risk increases by 79% for a vessel of 2.7 mm as3compared to a vessel of 3.4 mm in diameter [29]. Our research is focusedon an alternative wireless system for monitoring restenosis in stented coro-nary arteries for both small and large arteries. The presented system offersboth economical and time-saving benefits achieved by supplementing cur-rent methods of diagnosis with a more convenient wireless technique usingthe proposed“smart stent”systems. The term “Smart” in smart stent refersto the ability of the proposed stent to monitor, sense and report restenosis.The proposed smart stent employs the stentenna, i.e., a special helical stent,reported in [30] to establish an inductive link between the external readerand the implanted stentenna. The presented smart stent (stentenna withembedded sensors and telemonitoring circuits) enables two different wirelessmonitoring approaches. As will be explained later, one approach is to re-motely measure the value of the embedded capacitive sensors, via inductivecoupling between the stentenna and an external inductor (reader); in essence,using the stentenna and its sensor as a passive transponder. An alternativeapproach is to use an active telemetry system by utilizing an embedded tele-monitoring integrated circuit (IC) with the stentenna and using the stent asan transceiver antenna.41.3 System Building Blocks and General Tele-monitoring ApproachesOther than a few exceptions [20–22], most of the reported techniques forwirelessly diagnosing restenosis are based on monitoring the blood pressurein an implanted stent site using integrated capacitive pressure sensors [9,12,14,18,31–37].External ReaderTissueTelemonitoring systemSensor(s)Transceiver Sensor InterfacePower Harvesting Figure 1.3.1: A generic building block diagram of a biomedical telemonitoringsystem.In case of restenosis, the blood pressure difference between the two sidesof the stent will increase. Therefore, by monitoring this pressure differencethe restenosis level can be diagnosed. The reported wireless monitoring med-ical devices working based on this concept generally consist of the followingbuilding blocks (Fig. 1.3.1):Sensor : This component is usually a micro-electromechanical device thatconverts a physical quantity to a parameter that can be observed and5processed by the following stage(s). For example, for measuring pres-sure, capacitive pressure sensors are widely used. These sensors convertthe change of pressure to a corresponding change of capacitance.Sensor interface: This unit interfaces with the sensor and converts thesensory data to a useful signal that can be transmitted to the externalreader via the transceiver.Power Harvesting unit : This block generally consists of an energy har-vesting block that harvests energy for example from an incident RFsignal and then supply power to the rest of units.Transceiver : This unit establishes the communication link between the im-planted biomedical device and the external reader and transmits thesensory data. The communication link is usually a wireless medium.External Reader : This block monitors and processes the sensory informa-tion received from the implant. Depending on the monitoring method,this unit may also transfer power and some command data to the im-planted device through the forward link.Depending on the telemonitoring approach used (passive or active) the struc-ture of these blocks would change.61.3.1 Passive approachIn this approach the impedance of the implanted sensor is passively measured.Typically, the approach is based on inductive coupling between an externalimpedance analyzer (as an external reader) and the implanted device (in thiscase, stentenna). Fig.1.3.2 illustrates the equivalent circuit of a generic smartstent of Fig.1.4.1. In this schematic, Csen represents the capacitance of thepressure sensor, Rstent represents the stent electrical resistance and Rcont isthe equivalent resistance of the interconnects which connect the output ofthe capacitive pressure sensor to the neutral point of the stent (middle ofstent).RcontLstent1RcontLstent2 RstentRstentCsen1 Csen2Figure 1.3.2: Equivalent electrical schematic diagram of a generic smart stent.The capacitive pressure sensors and the stent make an LC band-pass filterwhich can be characterized by an external reader. Assuming coupling factorof k between the external reader with an inductance of Lext and the smartstent with an inductance of Lstent, the mutual inductance M can be writtenas:M = kpLstentLext (1.3.1)7As shown in (1.3.1), the mutual inductance is directly proportional tothe coupling factor k as well as the inductance of the stent and the externalreader. Figure.1.3.3 shows the equivalent circuit schematic of the externalreader and the modified equivalent schematics of the stent.Lstent1Lstent2RstentRstentCsen1Csen2RrangeLextM1M2ZinFigure 1.3.3: Electrical schematic diagram of the reader and stent in passiveapproachIn Fig.1.3.3, Rrange is the series resistance between external reader andthe external inductor. Using nodal analysis, the input impedance seen at theleft hand side of the circuit will be:Zin(j!) = Rrange + j!Lext + (1.3.2)M21!2Rstent + j!Lstent1 + 1/j!Csen1 + M22!2Rstent + j!Lstent2 + 1/j!Csen2Assuming Rstent ⇡ 0, the maximum of Zin(j!) occurs at the frequencieswhere the denominator of each fraction becomes zero. These two frequencies8are in fact the center frequencies of the two LC tank filters, described earlier.To obtain these frequencies, the imaginary parts of the denominators mustequal zero; which gives us:f1 =12⇡!1 =12⇡1pLstent1Csen1 , f2 = 12⇡!2 = 12⇡ 1pLstent2Csen2 (1.3.3)Fig.1.3.4 illustrates the magnitude and phase of Zin(j!) versus frequency.The peaks in magnitude of impedance which corresponds to the dips in phase,drop as the Rstent increases. Therefore, the peak reduces as the electricalresistivity of the stent increases. Equation (1.3.2) also shows that the mutualinductance M , between the external stent and the reader has a second-orderimpact on the phase dips (and magnitude peaks). However, since M is afunction of coupling factor k, therefore, the peaks and dips are a function ofk2. On the other hand, the efficiency of power transfer in any inductivelycoupled link is given by [38]:⌘ =k2QextQstent1 + k2QextQstent (1.3.4)where Qext , Qstent are the quality factors of the external reader and internalinductors . As presented in [39], the coupling factor reduces as differencesbetween the external coil radius and the stent radius increases. This meansthat for any given size of the stent, there is an optimum external inductor sizewhich leads to an optimal coupling factor k. Thus, to achieve the desiredcoupling factor and quality factor a minimum internal inductor is needed.9Figure 1.3.4: The spectrum of input impedance Zinseen from reader side,for this simulation Csen1 = 1 pF , Csen2 = 0.9 pF, Rstent = 1⌦ , Lstent1 =Lstent2 = 50 nH , Lext = 1µF , Rrange = 50 ⌦ and k = 0.01That is why the commercially available stents should be modified to providea better inductance. In addition, It can be shown that the inductive couplingdelivers higher power transmission efficiency than EMWP for the distancesshorter or on the order of rm = prstentrext, where rstent is the radius of theexpanded stent and rext is the radius of the external inductor coil [38].101.4 Active Telemetry ApproachIn the active telemetry, the sensory data is transferred via an active transceiver.To design the internal telemonitoring system, first, the optimum frequencyfor power transmission has to be found. Due to the unique structure of thestentenna, a series of electromagnetic (EM) simulations are done to calculatethe optimum frequency. In the next stage, the maximum deliverable poweris calculated. In the following sections, we briefly review the simulation pro-cedure and results.Figure 1.4.1: The three-dimensional view of the stentenna [2]1.4.1 Frequency of transmissionSimulation results show that transmission losses through tissues are a func-tion of frequency of incident signals. The reported inductively coupled bio-telemetry devices operates in sub-GHz frequencies [12, 31, 32, 40–43]. Thechoice of frequency was mainly due to:11• Tissue’s absorption increases for higher frequency signals and thereforelower frequencies are desired to minimize the absorption loss in tissues.• However, due to the sudden change of medium on the skin surface ofthe patient (air-skin interface) a portion of the signal reflects and asa result reduces the efficiency of transmission. This phenomenon hasmore pronounced for incident fields with lower frequencies.By taking into account the above mentioned factors, it is possible to computean optimum frequency which comprises the losses caused by both phenom-ena. The frequency is in sub-GHz range (10 to 100 MHz) and has beenapplied to almost every design up until very recent years [12, 31, 32, 40–43].However, the efficiency of the implanted antenna have been overlooked. Thisefficiency has a maximum value in GHz frequency range (depending on theshape and the size of the antenna). In the sub-GHz range, the loss due toantenna’s efficiency is quite higher than that of the tissue and reflection loss.Figure.1.4.2 presents simulated losses as a function of frequency [3]. By incor-porating both dielectric loss of tissues and antenna efficiency it is envisionedthat the optimum frequency for a millimeter scale biomedical devices is inthe range of 1 to 5 GHz. A recent study [3] and measurement results [44]confirm that considering the attenuation of antenna, dielectric dispersion intissue begins to play a major role in GHz range frequencies.12Figure 1.4.2: Simulated matched power gain versus frequency (differentcauses of loss has been shown on frequency axes). [3]Generally, the power budget for in-vivo telemonitoring is quite tight.In general, the RF signal used for wireless power delivery has to penetratethrough the tissues of the patient and reach the implanted stent. Since thetissues absorbs a significant portion of the emitted power, there are strictregulations for the maximum radiated power from an external reader. Ac-cording to Federal Communications Commission (FCC) [45] regulations foran averaging time of 6 minutes the radiated power density must not exceed5 mW/cm2 for the frequency range of 1.5 to 100 GHz and f/300 mW/cm213for frequency range of 300 to 1500 MHz where f is the frequency of trans-mission in MHz. The frequency of operation mainly depends on the shape,dimensions, and the depth of the implanted device. Generally, the smallerthe size of the antenna the higher the optimum frequency of operation willbe. However, the absorption of tissues is directly proportional to the fre-quency of transmission. This trade-off is further discussed in [3]. As it willbe discussed in detail, for the proposed smart stent the maximum calculateddeliverable power is about 50 µW, which impose significant challenges on thedesign of a reliable transponder integrated circuit. Aside that the techniquethat is being used for both power delivery and/or transmitting the sensorydata can fall into 4 categories. The following sections review the commonlyused methods for telemetry in biomedical devices.1.4.2 Telemetry based on inductive couplingIn this approach, the telemetry is based on mutual inductance between aninternal transmitter and external reader. Two types of telemetry based oninductive coupling have been reported. In the first type, the implanted ca-pacitive pressure sensor is integrated with a high quality inductor to form anLC tank. The internal inductor which works as an antenna is coupled withan external inductor (reader) establishing a link as shown in Fig.1.3.1). Theinternal inductor which acts as a transmitter introduces a “passive” transpon-der [40, 41] . This technique is usually referred to as the“passive approach”.The impedance seen from the external reader (using a network analyzer)14is a function of the internal inductor and sensor impedance. Therefore, thechanges in sensory variable (e.g., pressure) can be tracked by sensing the cen-ter frequency of the LC tank. To detect the center frequency of the coupledLC filter, the frequency of the phase-dip is usually measured. To measurethe phase-dip of the coupled LC tank, a network analyzer with high reso-lution in phase detection has to be utilized in the reader side which castsdoubt on the low-cost and portability of the wireless monitoring device (e.g.in [40]D < 0.01). However, the main drawback of this method comesfrom the internal inductor Lint. As shown in [38], the size difference be-tween the implanted inductor (Lint) and external inductor (Lext) will effectthe power transmission efficiency of the inductive coupling and has to bekept under a certain threshold. Thus, the internal inductor needs to be bigenough to establish the minimum coupling factor k while serving the min-imum quality factor Qstent ( 2.6 mm x 1.6 mm in [41] and 6 mm x 2 mmin [40] )1. Furthermore, to maintain the minimum coupling, by increasing thedepth of the implant, a larger internal inductor is needed. As a result, themethods introduced in [40,41] cannot meet the geometrical constraints of thecoronary artery. In the second category of monitoring devices an active tele-monitoring system is employed to send the sensory data back to the readerby establishing a backward link as shown in Fig. 1.3.1. This telemonitoringsystem can offer higher sensitivity in a smaller implant size [31, 32, 42, 43] .1It will be shown later, that there is a maximum size for external inductor dictated bythe stent’s size.15In this method, the monitoring resolution will be determined by the internalcapacitance to voltage or frequency converter (CVC or CFC) circuit which isintegrated along with the implanted biomedical device. Due to the proxim-ity of CVC or CFC circuits to the sensors, these systems have less noise andcan lead to higher transducer (detection) sensitivity. The main advantage ofthis method compared to the electromagnetic wave propagation (radiation)technique is higher efficiency in short coupling distances [14, 38]. Similarto the passive approach based designs, the reported designs based on activetelemonitoring system have large inductive transmitters (5 mm diameter and6mm x 6 mm in [31, 42]and [32] respectively) which makes those techniquesimpractical for coronary arteries with average diameter of 2.75 mm [46] .1.4.3 Telemetry based on electromagnetic waves prop-agationThis approach is based on electromagnetic radiation in which the implantedantenna receives a portion of electromagnetic waves propagated by trans-mitting antenna to power up the active internal telemonitoring system. Asshown in the Fig. 1.3.1, the backward link which carries the sensor’s data tothe reader can be based on either electromagnetic propagation [9,14,37,44] orelectromagnetic back-scattering phenomenon [32, 47]. The main advantageof establishing the wireless link based on electromagnetic wave propagation(EMWP) (compared to inductive coupling) is that there is no need for align-16ing the primary and the secondary inductive coils (in order to achieve anexcellent matching and maximum power delivery). In addition, it is pos-sible to achieve higher power transmission efficiency in longer transmittingdistances (compared to the inductive coupling method) [14]. However, asmentioned earlier, for short coupling distances (near field e.g. less than 10cm) the inductive link can deliver more power efficiency, as it becomes anissue for one of the similar designs which utilized an active telemetry systembased on EMWP. Reported measurements in [14] indicate insufficient incom-ing power which lead to inability in powering up the on-chip transducer IC(functionality failure in in-vivo experiment) .1.4.4 Ultrasonics-based telemetryIn this method the ultrasonic transducer harvests the energy of the acous-tic waves and converts them to an electrical form of energy applicable forthe internal telemonitoring system. Although this technique attracts lots ofattention in different bio-medical applications [33], due to the physical geom-etry and structural dimensions of the coronary artery and the cardiovascularstent, this method seems impractical.171.5 Challenges inWireless Monitoring of Resteno-sis in Coronary ArteriesAs stated earlier, the coronary arteries have an average diameter size of ⇠2.75mm which makes the design of an implantable transducer challenging. Thesmall diameter of the coronary artery imposes size limits on the internalantenna which in turn to achieve a reasonable antenna efficiency calls forhigher operating frequency. This will make the design of high-efficiency in-ternal transponder more challenging. The reception of incident signal at thestent site is directly influenced by the tissues electromagnetic (EM) proper-ties and their thickness. As it is explained in more detail in the next chap-ter (Fig.2.2.1), several layers of tissue are between the implanted stent andthe external reader. These layers absorb most of the incoming waves (withelectric or magnetic nature) energy. The results of a recent study which ispresented in Fig.1.5.1 reveals the power gain efficiency in transmitting elec-tromagnetic signals will plunge to 0.1% when the implant depth is around30 mm [3]. These results are in agreement with another in-vivo experimentshowing 47 dB of reduction in received power in EM based implanted an-tenna with the depth of 35 mm [37] . Knowing the average depth of thecoronary artery is 39 mm [48] it can be observed that we should expect lessthan 0.03% power gain delivery. As will be shown further on, there is a max-imum deliverable power due to the existence of a maximum allowable powerdensity exposure to living tissue.18Figure 1.5.1: Efficiency of power transmission with respect to the distancebetween reader and transponder antenna [3]1.6 Summary of ContributionsAs mentioned there are different school of thoughts for designing such tele-metric systems. In this work various techniques for telemonitoring of in-stentrestenosis are presented. The proposed structures are designed and fabricatedin a 0.13 µm CMOS process and successfully tested in in-vitro setups. In thefollowing subsections, we briefly overview these contributions.1.6.1 The proposed capacitance to frequency based tele-monitoring systemHaving simple design in mind, the sensory interface for the first type of tele-monitoring system is a simple capacitance to frequency converter (CFC).19Since in the inductive coupling, maximum power delivery is achieved whenthe reader and the implanted antenna are well aligned, a novel alignmentarchitecture is proposed which ensures the alignment between these two com-ponents. The measurement results and simulation results confirm the excelperformance of this work compare to similar reported designs. Detail archi-tecture and functionality of this system is discussed in the following chapters.The main advantage of this design in comparison to capacitance to voltageconverter based system are higher sensing resolution, simplicity and lack ofneeds of a reference or differential capacitance. Although the power con-sumption of this system (CFC) in comparison to similar reported systemsis about half of the most power efficient one, however, compare to the nextproposed system (CVC) is not of its merits.1.6.2 The proposed capacitance to voltage based tele-monitoring systemTo extend the features and flexibility of the first version of telemonitoringsystem (CFC based system), the sensor interface circuit is formed by a ca-pacitance to voltage converter (CVC) stage followed by a CFC stage. Addingthe CVC stage increased the complexity of the system but by careful designand applying ultra low power design techniques, the overall design providesmore features compare to the first system while consuming much less powerconsumption. The proposed telemonitoring system (embedded integrated20circuit) consumes 35 nW at 350 mV supply voltage.1.6.3 Study and analysis of telemonitoring based onbackscatteringData transmission based on backscattering phenomenon is one of the mostpower efficient method of communication. Use of relaxation oscillator cansignificantly reduce the power consumption compare to conventional activeoscillators [15]. In this method the data transmission can be done by modu-lating the antenna load. To study the feasibility of this method using smartstent (stent as an antenna), a set of experiments are performed which sup-ports the expectations . more detailed explanations are provided in thefollowing chapters.1.7 Thesis OutlinesIn this work, different techniques for wireless monitoring of biomedical datais applied and compared. In total, 6 different prototypes have been designed,laid out, and fabricated. The proposed systems offer power consumptionperformance and resolution that compare favorably with those of reportedstate-of-the-art techniques.The organization of this thesis is as follows. Chapter 2 discuss the opti-mum frequency of transmission for this application using stentenna. Chap-ter 3 Introduce the CFC based telemonitoring system while Chapter 5 provide21in-detail description of proposed CVC based system. Chapter 4 presents thedesign and implementation of a unity-gain buffer specifically developed fortesting the circuits designed in this work. Chapter 6 provides explanation onfeasibility of backscattering technique using smart stent and finally Chapter 7provides concluding remarks and summary of achievements.22Chapter 2Frequency of Operation2.1 IntroductionAs stated in earlier sections the inductive coupling delivers higher powertransmission efficiency as compared to other techniques. Therefore, we havealso chosen inductive coupling for powering up the telemonitoring integratedcircuit (IC) used in this work. In order to establish an inductive link betweenthe implanted antenna and external reader, a relatively large transmittingantenna (compared to the size of the artery) is required. In addition, tomaintain this link for biomedical devices implanted in further depth, evenlarger transmitting inductor (internal antenna) is needed1. In 2003, [30] in-troduced, an inductive stent with minimum modifications in the structure of1In order to deliver the minimum required power to transponder circuit in furtherdepths, the quality of the inductive link has to be increased which leads to a biggerinternal inductor.23conventional medical stent. The experimental results shown in [12] provesthe concept of remote monitoring via proposed inductive stent (stentenna).Having a stent as an inductor facilitates wireless monitoring of the pres-sure in small arteries such as the coronary artery by eliminating an extrabulky transmitting inductor [31,32,40–42]. However, a set of simulation andmeasurements are needed to obtain the optimum frequency range of powertransfer using proposed stentenna [30] . Simulation and measurement resultsprovided in the following sections prove the feasibility and advantages of thepresented stentenna.2.2 Calculating The Optimum FrequencyTo simulate the optimum frequency for this application (having stentenna asan transceiver antenna), first the environment where the stent is located inshould be modeled. Fig. 2.2.1 shows, all different tissues between the externalreader and the smart stent placed inside the coronary artery. Fortunately,about 65% of this space is taken by rib bones (ribs) which have less absorptionloss than live tissues. In addition, as the Fig. 2.2.1(b) demonstrates, thatpart of heart where hosts the coronary arteries is not covered by lung. Thatsimplifies the modeling since we know that the tissues thickness would notchange by patients breathing.In order to model the tissues absorption, the equivalent dielectric lossfor each type of tissue have to be modeled . Therefore following equivalent24(a)(b)Figure 2.2.1: (a) Anatomical position of heart (side view) [4] demonstratingdifferent layers of tissue between external reader and stent (b) Coronaryarteries are not covered by lung (front view) [5]complex permittivity model for dielectric spectrum of tissues has been used[1] :"ˆ(!) = "1 +5Xn=1 "n1 + (j!⌧n)(1↵) + ij!" (2.2.1)where " = "s  "1 and " is the permittivity at field frequencies where!⌧ o 1, "s is the permittivity at !⌧ n 1, i is the static ionic conductivity ,25"0 is the permittivity of free space and ⌧ is time constant of polarization mech-anism. Two key factors for modeling any tissues for electromagnetic (EM)simulation in high frequencies are complex values of dielectric permittivityand permeability. A detail description on these parameters are provided inthe modeling section. Table 1 presents complex permittivity coefficients ineach different tissues between external reader and stent associated with thethickness of each tissues.2.3 Modeling Smart Stent’s Environment forEM SimulationsFor obtaining maximum power delivered series of simulation has been per-formed using Ansys HFSS v.13 and Comsol Multiphysics 4.2. Following arethe summary of tissues between skin and coronary artery.Skin with mean thickness of 1.22 mmAdipose-Layer just below skin Muscle and intercostals muscles Mean thick-ness of 10 mmRibs Thickness varies between 25 mmPericardium Surrounds heart and is 1.15 mm thickCoronary-artery Wall thickness is 1.2 mm26Blood Inside the coronary artery, the diameter of the coronary artery afterstenting can reach up to 5 mmTable 2.1: List of parameters of equation (2.2.1) used to predict the complexrelative permittivity of tissues from 10Hz up to 100GHz [1]TissuedryskinwetskinPericar-diumRibs(concel-lous)BloodvesselwallBloodin thearteryfat(infil-trated)Thickness(mm)1.22 1.22 1.15 20.0 1.2 5 10"1 4.0 4.0 4.0 2.5 4.0 4.0 2.5"1 32.0 39.0 50.0 18.0 48.0 56.0 9.0"2 1100 280 7000 300 2500 5200 35"3 0.03.1⇥1041.2⇥1062.0⇥1042.0⇥1050.003.3⇥104"4 0.03.0⇥1042.5⇥1072.0⇥1075.0⇥1070.001.0⇥107↵1 0.00 0.10 0.10 0.22 0.10 0.10 0.20↵2 0.20 0.00 0.10 0.25 0.15 0.10 0.10↵3 - 0.16 0.10 0.20 0.25 - 0.05↵4 - 0.2 0.00 0.00 0.00 - 0.01⌧1(ps) 7.23 7.96 7.23 13.26 7.96 8.38 7.96⌧2(ns) 32.48 79.58 353.68 79.58 63.66 132.63 15.92⌧3(µs) - 1.59 318.31 159.15 265.26 - 159.15⌧4(ms) - 1.592 2.274 15.915 6.366 - 15.915 0.0002 0.0004 0.2000 0.0700 0.0300 0.7000 0.0350The average distance between heart and skin is 39 mm [48] which is inclose agreement with above geometries. The compositions of intercostalsmuscles and muscles are roughly the same, and thus for the purpose of simu-lations they are considered as one layer of muscle. Furthermore, pericardiumconsists of connective tissue and mesothelium which have similar electromag-27netic properties and thus they are grouped together with coronary arterywall.In order to increase the accuracy of the simulations, the magnetic sus-ceptibility of the blood should be taken into account. Blood magnetic sus-ceptibility is different in case of oxygenated or deoxygenated blood. Forarterial oxygenated blood the value of the magnetic susceptibility has beenmeasured to be −6.6⇥107 while this quantity for the deoxygenated bloodis 3.5⇥10−6 [49]. Thus, the value of relative permeability µr = m + 1 is0.999, 9934 and 1.000, 0035 which is approximately 1 (the default value forall tissues).Figure 2.3.1: The simulation setup in HFSS. The 2D contour of specifiedabsorption rate (SAR) is shown on the skin surface. This value is kept belowthe maximum allowable of 1.6 W/kg [2]282.4 Experimental and Simulation ResultsThe simulation setup in ANSYS HFSS® is presented in Fig. 2.3.1 (and ap-peared in [2]). As expected (and as analyzed in [3]), there is an optimumfrequency for power gain transmission for smart stent at which the powertransmission gain reaches 28 dB. Fig.2.4.2 shows the transmission operat-ing power gain (dB) for different excitation frequencies. According to theseresults the optimum frequency is about 0.8 GHz. To simulate the maximumdeliverable power we have to apply the maximum allowable power Pin to thereader antenna and calculate the received power PL using following formula:PmaxL = GmaxP Pmaxin (2.4.1)The maximum excitation power at the external coil, set by the FederalCommunication Council (FCC), limits the maximum radio-frequency radia-tion exposure (RRE) to lower than 5 mW/cm2 over the frequency range of0.1 to 5 GHz (For frequencies below 1500 MHz the power limit is frequencyin MHz divided by 300) [45]. By applying Pmaxin = 35.58 mW, the maximumpower density on the skin reaches to 2.56 mW/cm2 (which is very close to themaximum allowable of 2.66mW/cm2 at 800 MHz). Therefore, using (2.4.1),the maximum deliverable power is:29PmaxL = 10(2810 ) ⇥ 35.58mW= 56 µW (2.4.2)In order to verify the simulation results obtained from ANSYS HFSS ®and COMSOL Multi Physics ® finite element simulator, a similar experi-mental setup as depicted in Fig. 2.4.1 has been employed. In this experimentto mimic the surrounding tissues around the implanted stent, the inductivestent is surrounded by ground beef with extra fat. The reader coil is the sameas that modeled for EM simulations and is connected to one port of a vectornetwork analyzer (VNA), Anritsu MS2034A. The two sides of the stent areconnected to the other port of the VNA and the scattering parameters ofthe system are measured. To ensure that the returning path is not intro-ducing an unwanted induction loop and a ground plane has been utilized.The ground plane makes the returning signal to travel exactly underneaththe buried stent and therefore it avoids forming a parasitic loop betweenreturning path and stent. The operating power gain is given by:GP = PLPin = |s21|2 (1 |L|2)|1 s22L|2 (1 |in|2) (2.4.3)where s21 and s12 are the forward and reverse gain scattering parametersof the system and L and in are the load and input reflection coefficients.PL is the delivered power on the stent site and Pin is the excitation power atthe reader terminal. Note that in this measurement (and simulation) setup,all system terminals are terminated to a 50 W impedance and therefore,30L = in = 0. In such conditions, Eq. (2.4.3) for operating power gain(GP ) can be simplified to GP = |s21|2. In this experiment, the stent hasbeen surrounded by ground beef of the depth of ⇠ 40 mm and the reader islocated at 4 mm distance from the ground beef surface. The experimentalvalue of power gain versus frequency are also appended in Fig.2.4.2.Figure 2.4.1: Experimental setup for measuring deliverable power to a stentantenna buried under 40 mm of ground beef.EM simulation results for stentenna shown in Fig. 1.4.1 and , estimate56 µW induced power while the skin has been exposed to 2.56 mW/cm2 ofpower density. To compare this result with measured induced power basedon EMWP for 35 mm depth for implanted stentenna, the expected powertransmission gain (⌘) is 0.03% therefore, total received power on the stentsite having exposure power density of Pin is given by:Pr = ⌘PinA31where A represents the area of the stent exposed to the incident waves.Assuming Pin = 2.66 mW/cm2 , A = 20mm ⇥ (2.75mm)⇡ = 1.728 cm2,Pr = 1.37µW. Based on this simple calculation, even if we assume 100%efficiency for the implanted stent as an antenna, with the inductive-coupling-based power delivery approach, one can achieve 56µW1.37 µW (⇠ 55 µW)more power at the implant site. This shows the advantage of using stentennafor small vessels such as coronary artery.106 107 108 109−100−90−80−70−60−50−40−30−20frequency (Hz)Power Gain (dB)  COMSOLMeasurementHFSSFigure 2.4.2: Experimental and simulated operational power gain (dB) versusfrequency [2].Assuming that most of the transferred power will be used for the trans-mission of sensor signals (in this case, 50 mW), we can calculate the power32density of the backward link established by internal IC on the surface of theskin. Fig. 2.4.3 presents the 2D map of observable power density on the skinsurface, transmitted from the smart stent. The observed power which hasthe maximum of 5 pW/cm2 over the simulated skin area can be sensed bycareful design of the reader antenna. Note that the asymmetric power densitymap caused by radiation of the stent can be attributed to the asymmetricgeometry of the stent. As can be seen from stentenna’s diagram (Fig. 1.4.1),to improve the physical strength of the stentenna, two platfroms are addedat each side of the stent which result ina asymmetric radiation pattern of thestent.Figure 2.4.3: Power density (PD) of signals transmitted by the stent [2]33Chapter 3Telemonitoring System Basedon Capacitance to FrequencyConversion3.1 IntroductionIn this section the design and performance analysis of the proposed tele-monitoring system based on direct conversion of capacitance to frequency ispresented. Fig. 3.1 shows the block diagram of the proposed monitoring IC.As shown, the proposed system consists of two main building blocks, a har-vesting unit to provide the required supply voltage to the rest of the system,and alignment and monitoring unit which consists of two transmitters and aDC biasing circuitries and a decision circuit. The decision circuit is placed to34Figure 3.1.1: Building blocks of the proposed embedded telemonitoring sys-tem.improve the reliability of the inductive coupling link between the implantedstentenna and the external reader. The following sections further elaboratethe functionalities and performance of the above-mentioned building blocks.3.2 Power Harvesting UnitTo efficiently convert the received RF power to an stable DC power to supplythe entire monitoring system circuitry, a three stage differential-drive rectifieris used [50]. In standard CMOS technology, the differential-drive rectifieroutperforms conventional Dickson-based rectifier specifically for small inputlevels and is therefore the best candidate to serve as the power conversion unitin the monitoring system. Note that in the alignment mode, the stentennareceives very small input levels (well below the threshold of CMOS transistorsin 0.13µ m CMOS technology) which mandates a high-efficiency rectifierto guarantee that sufficient power is delivered to the succeeding circuitry.The superior power conversion efficiency (PCE) of differential-drive rectifier35(compared to conventional Dickson-based single-input rectifier) justifies theextra complexity imposed by the differential input requirement. In practice,the two differential input (in+ and in- in Fig. 3.2.1) could be extracted fromthe two ends of a center-tapped stentenna, while the its center could be usedas the ground.It should be noted that it is the combined efficiency of the stentenna andthe rectifier that determines the overall performance of the power harvestingunit. That is, a good matching has to be established between the stentennaand the input of the rectifier to guarantee that sufficient power is deliveredfrom the stentenna to the rectifier and subsequently, from the rectifier tothe entire monitoring system. At the frequency of interest (2.4 GHz), thestentenna could be modeled by an inductor and the rectifier is modeled bythe parallel combination of a capacitor Cin and a resistor Rin as shown inFig.3.2.2 [51]. The resistive (real) part of the input impedance represents theaverage DC current drawn from the inputs by the load (succeeding circuitry)and the parasitic losses and is therefore load dependent. The capacitive(imaginary) part of the input impedance accounts for the series combinationof the coupling capacitors (CC in Fig. 3.2.2) and the parasitic capacitanceof the switching transistors MPi, Ni (Cpar). To achieve a good matching be-tween the stentenna and the rectifier, the capacitive (imaginary) componentof the rectifier’s input impedance and the inductance of the stentenna haveto resonate at the frequency of operation (i.e. 2.4 GHz). For this purpose,although the inductance of the stentenna is dictated by its geometry, the36input capacitance of the rectifier could be designed so as to resonate withthe inductance of the stentenna at 2.4 GHz. As shown in Fig.3.2.2, giventhat CC  Cpar, the input capacitance of the rectifier is dominated bythe parasitic capacitance of the switching transistors (Cpar). Note that Cparis composed of the source/drain capacitance of Mp1, n1 and the gate capaci-tance of Mp2, n2 as shown in Fig. 3.2.2. Therefore, by optimizing the size ofswitches, a high PCE and the appropriate input capacitance for the operationfrequency of 2.4 GHz could be achieved simultaneously.stentennain+in-GNDRectifier (differential)loadDCoutin+in-Figure 3.2.1: Schematic of the center tapped stentenna and differentialrectifier.To improve the efficiency of the the system and to ensure that the systemis able to operate with small incoming signal amplitude, a voltage matchingout1 out2Mn1 Mp1Mn2 Mp2in+in-Zin+ = Rin+  +  jXCin+ CCCCCparin+Cin+Zin- = Rin-  +  jXCin-CCCparCparCS/D, n1 CS/D, p1CG, n2 CG, p2Figure 3.2.2: Schematic of the second stage of the rectifier and the inputcapacitance.37circuit is placed between the stentenna and the rectifier stage. The voltagematching circuit consists of a series inductor that will resonate with theinput capacitance of the rectifier stage. However, for transmitting sensorydata through stentenna a power matching circuit is required to ensure thatmost of the available power at transceiver unit is transmitted to the externalreader. Simulation results show that the designed rectifier can provide up to1.0 V of supply voltage from a voltage-matched incoming differential signalof 74.92 mV amplitude (-25.1 dBm). The power efficiency of the rectifieris simulated to be 64% at 1.0V output voltage and 41% at 400 mV outputvoltage.In contrast to typical telemonitoring architecture, the proposed systemdoes not include a voltage regulator stage for three main reasons: firstly, theincident signal received by the rectifier is at 2.4 GHz, thus the fundamentalfrequency of ripples of the rectifier stage will be at 2.4 GHz. A regulator whichis capable of actively rejecting 2.4 GHz ripples should have a high closed-loopbandwidth and therefore is power hungry [52] and is not feasible for this low-power application. Secondly, in the architecture of the monitoring circuit nodigital blocks or clock signals are used and therefore the load variation isnot significant. This relaxes the voltage regulation requirements and somedegree of voltage variations can be tolerated. Thirdly, since the rectifier isdriving an ultra-low power monitoring circuit which could be modeled aslarge equivalent resistance, the combination of the large load resistance andthe rather small smoothing capacitance at the output of the rectifier form a38M2M1M4R2R1Dynamic biasing circuit Decision Circuit VBRBGM10M9M12M11ok okM3aVinM6M5M8M7VDDmainLmainCSensorVB M13M14 M15M16 M17VDDauxLauxCparVB M18M19 M20M21 M22VDDMain TransmitterAuxiliary TransmitterFigure 3.2.3: Schematic of the proposed telemonitoring system.39passive RC filter. This filter sufficiently attenuates the high frequency ripplesat the output of the rectifier.3.2.1 Auxiliary and main transmittersFor relatively short distances between the transmitter and receiver, despitesuperior power transfer efficiency of the inductive link as compared to electro-magnetic wave propagation (EMWP), misalignment in inductive couplingcan significantly deteriorate the power transfer efficiency [53]. To establishan efficient power transfer link between the external reader and the internalIC using inductive coupling, the internal and external antennas have to bereasonably aligned. To achieve such alignment an ultra-low-power auxiliarytransmitter is designed which transmits pilot signals to the external readerdepending on the amplitude of the internal rectified voltage. The alignmentunit transmits a frequency that is directly proportional to the amplitude ofthe received rectified voltage. A low-power complimentary crossed-coupledLC oscillator similar to [54] is used for both auxiliary (alignment) and maintransmitter oscillator circuit (as shown in Fig. 3.2.3), however, as describedbelow, the auxiliary oscillator is designed to have a significantly lower power.As shown in Fig. 3.2.3, the overall small-signal transconductance of theoscillator circuit is given by:gtotm = 2gmn + 2gmp (3.2.1)40where gmn and gmp are the small-signal transconductance of the NMOSand the PMOS transistors, respectively. To have a sustained oscillation thefollowing condition has to be satisfied:gtotm  Gparalel (3.2.2)where Gparallel , is the total equivalent conductance of the passive elementsin the tank circuit and includes the parasitic conductance of the inductor andcapacitor. Note that the combined transconductance of cross-coupled activecomponents is a negative conductance.The total amount of parallel positive (passive) conductance can be cal-culated as follows:Gparallel = Gindpar + Gcappar + gdsn + gdsp (3.2.3)where gdsn and gdsp are the transconductance of NMOS and PMOS tran-sistors, respectively and Gindpar , Gcappar are the equivalent parallel conductanceof inductor and capacitor at the output. The amount of Gindpar and Gcappar aredirectly proportional to the frequency of operation and the quality factor ofthe corresponding energy storage elements (i.e., the series resistance of thoseelements). Assuming, storage elements with quality factors of QL = !L/Rs,Land QC = 1/(Rs,C!C) where Q2  1:Gindpar = 1Rs,L(Q2L + 1) ⇡ Rs,L!2L2 (3.2.4)41and,Gcappar = 1Rs,C(Q2C + 1) ⇡ Rs,C!2C2 (3.2.5)in which Rs,L and Rs,C are the series (parasitic) resistance of the storage ele-ments. To decrease the power consumption in auxiliary transmitter, Gparallelhas to be reduced which in turn decreases the required gtotm (recall 3.2.3).Therefore, less bias current will be needed to achieve the required transcon-ductance. According to (3.2.3), Gparallel, can be reduced by increasing theinductance L and decreasing the capacitance C of the output tank of thetransmitter (Fig. 3.2.3). Note that ! is the resonance frequency of the tank,i.e., the angular frequency of oscillation, and is equal to 1/pLC.Based on the above discussion, one can reduce the capacitance of theLC tank in order to decrease the bias current and consequently, the powerconsumption of the oscillator. At the frequency of interest and for a suffi-ciently large inductor, the capacitor can be reduced to values comparable tothe parasitic capacitors of the NMOS and PMOS transistors. Therefore, theparasitic capacitance of the devices could be used as the main capacitor ofthe LC tank.In addition to the power consumption improvement, relying on the par-asitic capacitance of the devices makes the frequency of operation of the LCoscillator a bias-dependent value. This in turn is useful as the bias valuecan be monitored based on the oscillation frequency, which is one the main42purposes of the alignment unit.In practice, the main transmitter is directly connected to the capacitivepressure sensors which have a base capacitance of 1.6 pF. One such capac-itance that mimics the capacitance of the pressure sensor is integrated onthe chip for test purposes. Note that due to variation of the rectified supplyvoltage (VDDmain in Fig. 3.2.3) the operating point of the main transmittermay change which results in changes in the parasitic capacitance and thusthe frequency of oscillation. Therefore, in order to minimize the variationsof the operating point, the dynamic biasing circuit (DBC) attempts to mini-mize the changes of the bias voltage over the operation range of the rectifiedsupply voltage (i.e., VDDmain from 0.85 to 1.2 V in Fig. 3.3.5).3.2.2 Decision circuitThe operation of the decision circuit is as follows. At the start-up, if thereceived power (induced voltage) is insufficient for the proper operation ofthe monitoring system (i.e., main transmitter), the controller turns the mainoscillator off and switches the auxiliary low-power transmitter on. Switchingoff the main oscillator at the start up reduces the current load of the rectifierwhich in turns helps boosting the rectified output voltage [50,55].By gradually adjusting the relative position of the primary (reader) andsecondary (stentenna) coils towards achieving a perfect alignment, the in-duced voltage level starts to build up at the output of the rectifier. Since thecapacitor of the LC tank of the auxiliary oscillator is formed by the parasitic43capacitances of the transistors, any change in the harvested supply voltageof this oscillator can change the operating point of the transistors and hencethe capacitance of the oscillator. This change in the capacitance can be ob-served by the change in the transmit frequency of the auxiliary transmitter.Note that the frequency of transmission for auxiliary oscillator (alignmenttransmitter) is in a different range as compared to the frequency range of themain oscillator (monitoring transmitter). Therefore, based on the receivedfrequency range, the operator can distinguish which unit is operating. Afterthe required power threshold for proper operation of the monitoring system isachieved, the controller switches off the auxiliary oscillator and turns on themain transmitter. Note that the internal threshold voltage of the inverters(in Fig. 3.2.3) is used as the reference voltage for the decision circuit whichenables the use of a simple chain of inverters as a low power comparator. Onthe other hand, as explained earlier, at the start-up, when the rectified volt-age is low, the DBC, sets the tail current of the auxiliary transmitter at theminimum operational level to guarantee that a link is established between thereader and stent. The proposed alignment unit for monitoring the receivedpower can also be used in non-inductive wireless monitoring systems (e.g.,EMWP-based links). Although both oscillators are sharing the same sten-tenna for transmission and thus their output nodes are connected, when thealignment unit is activated (when Saux in Fig. 3.1 is on) the supply voltage ofthe main transmitter is float ( Smain in Fig. 3.1 is off) and therefore the mainoscillator load the stentenna with a high impedance. Consequently, when the44auxiliary transmitter is active it is not loaded by the main transmitter. Asimilar scenario works when the main oscillator is activated.3.3 Simulation and Measurement ResultsTwo proof-of-concept prototypes of the proposed system are designed andfabricated in a 0.13 µm CMOS process; one is tested using on-chip probing(Fig. 3.3.1) and the other one is packaged and tested (Fig. 3.3.2). The overallchip occupies 0.484 mm2 (1100 µm ⇥ 440 µm). The second prototype ispackaged in a standard 80-pin ceramic quad flat package (CQFP 80). Wefirst present the experiments that are carried to measure the performance ofthe system when a weak input is supplied to the chip directly from a signalgenerator. Then, we present the in-vitro measurements of the overall systemwhile the power is wirelessly delivered to the system.Figure 3.3.1: Micrograph of the fabricated telemonitoring system consistingof 1. auxiliary transmitter, 2. main transmitter, and the DBC and decisioncircuit, and 3. rectifier circuit.45Figure 3.3.2: The micrograph of the chip emphasizing on the wire bondinterconnect in the CQFP80 package.`Cin-Cin- RinTele-monitoring chipRectifier TelemonitoringCQFP-80 package`in+ in-LWBRFinPrinted Circuit BoardAgilent 83732BPicosecond 5310InfiniiMax 1169AInfiniimum DSO81304AWire-bondinterconnectsFigure 3.3.3: Schematic of the measurement setup.The simulated power conversion efficiency (PCE) of the rectifier at 2.4 GHzfor a load current of 178 µA (where the monitoring transmitter start oper-46ating and supply voltage of the monitoring unit is at ⇠850 mV) is ⇠52%.Note that the wire bond inductor in the package is used as the input volt-age matching network. The inductive behavior of the wire bonds that con-nect the IC pads to the package leads have been studied in the literature(e.g., [56]). Given that we had access to the electrical model of the 80-pinCQFP package used in this work (the model was provided to us by CMC Mi-crosystems) and we could estimate the length of the wire bonds connectingthe input signals to the rectifier (by properly positioning the chip inside thepackage), we designed the input capacitance of the rectifier in such a waythat the combination of the wire bond inductance and the input capacitanceof the rectifier resonates at the frequency of interest (i.e., 2.4 GHz). Themicrograph of the associated wire-bond interconnect for CQFP80 package isshown in Fig. 3.3.2. For a wire-bond length of 3.5 mm, the wire-bond induc-tance is estimated (and later verified by measurement) to be LWB=15.5 nH.Thus, the input capacitance of the rectifier is designed to be 280 fF in orderto resonate with 15.5 nH inductance of the wire bonds at 2.4 GHz. Fig. 3.3.3shows the test setup for this measurement. As shown in the figure, the inputvoltage is measured with an Agilent 1169A 12-GHz InfiniiMax active probewhich is connected right at the input pins of the package to avoid the ad-verse effects of the differential balun and PCB traces. The measured outputvoltage versus input voltage of the rectifier block is shown in Fig. 3.3.4.At the rectified voltage of 500 mV (which corresponds to 10 mV inputamplitude level and 30 dBm input power as shown in Fig. 3.3.4) the aux-47iliary transmitter starts to operate reliably while drawing 6.8 µA of current.The decision circuit switches off the auxiliary transmitter when the outputvoltage of the rectifier reaches ⇠870 mV. The monitoring (main) transmitteris turned on when the rectified voltage reaches 880 mV. It should be notedthat there is a small voltage drop across the switch Smain in Fig. 3.1 andtherefore, VDDmain is about 10 mV lower than the rectified voltage. Themonitoring transmitter draws 178.3 µA when it starts to operate. The nom-inal transmission frequency of the monitoring transmitter is expected to be2.12 GHz (since the inductance of the LC tank is 3.53 nH and the sensor basecapacitance is set to 1.6 pF). The measured nominal frequency is 2.031 GHz(see Fig. 3.3.8) which can be attributed to the parasitic capacitance addedby the measurement setup.1 5 10 50 100 20000.511.522.53Input signal amplitude (mV)Rectified supply voltage (DC)−50 −36 −30 −16 −10 −4Input power (dBm)Dynamic bias Constant biasVoutDC = 880 mVVinamp = 69.35 mV  Pin = −13.18 dBmAlign. Mont.Figure 3.3.4: The measured output voltage versus the input voltage ampli-tude of the rectifier stage at 2.4 GHz.As discussed earlier, depending on the amplitude of the induced signal48on the stentenna, the overall system operate either in the alignment mode orthe monitoring mode. To measure the steady-state behavior of the systemand to measure the overall current of the system we have used the HP 4155Asemiconductor parameter analyzer to mimic the gradual increase in the DCvoltage of the rectifier output and measure the current drawn by the system.Fig. 3.3.5 shows the behavior of the system as a function of the rectifiedvoltage.As expected the DBC enables the auxiliary transmitter at 7.5 mV of in-put amplitude signal which corresponds to 300 mV of rectified voltage andwhich makes the auxiliary supply voltage to be at 262 mV. Note that thisvoltage is still not enough for the transmitter to start oscillating. By increas-ing the rectified voltage to 500 mV, the auxiliary voltage reaches to 485 mV.At this supply voltage the auxiliary transmitter starts oscillating and theoverall current drained by the system is only 8.3 µA (yields to total powerconsumption of 4.15 µW). Note that the alignment (auxiliary) transmitterdraws 5.85 µA of total current. At this point the frequency of transmission(as provided in Fig. 3.3.10) is 180 MHz. By Increasing the rectified voltagethe DBC increases the biasing voltage (VB shown in Fig. 3.3.5) of auxiliarytransmitter to mimic the main transmitter’s current load. Meanwhile thealignment transmitter keep increasing the transmission frequency as the rec-tified voltage increases. This Biasing voltage is shown in Fig. 3.3.5 as VB andas shown it will keep raising till input level reaches 700 mV. After this pointthe biasing voltage decreases and remains at 480 mV while DBC disables the49axillary transmitter and enables the monitoring transmitter.0.3 0.4 0.6 0.8 voltage (V)Voltage (V)1.250100150200250300Total current (µA)  Total current drained by systemSupply voltage of monitoring unit (Ok signal)VB (from DBC)Suppy voltage of alignment unit (Okbar signal)~870 mVMonitoring unitoperatesAlignment unitoperatesFigure 3.3.5: Measured response of different blocks of the transponder circuitas a function of the gradual increase of the input voltage level.Simulation results show that the DBC and decision units consume 326 nWand 19.943 nW at their peak of consumption in alignment phase respectively(at 0.87 V of rectified supply voltage). The measurement results reveals thatthe DBC and decision units combined, consume 1.225 µW when the rectifiedvoltage reaches 500 mV and 8.7 µW for the rectified supply voltage of 870 mV(e.g., auxiliary supply voltage of 847 mV). Note that DBC block itself issimulated to consume 669.12 nW in its peak of consumption in monitoringphase (at 1.2 V supply voltage). In addition the decision circuit consumes902.8 nW for maximum rectified voltage of 1.2 V.50VDD_BufferVoutEAVDD_BufferVinFigure 3.3.6: Schematic of the unity gain buffer used for measuring theperformance of the system.The spectrum of the auxiliary and main transmitter are measured usingAgilent PXA signal analyzer (N9030A). Since the transmitter’s output ismatched to the input impedance of the antenna stent (approximately 1 k⌦)and the input impedance of the measurement devices are 50 ⌦ a unity gainbuffer circuit is required to measure the performance of the transmitters(alignments and monitoring).Fig. 3.3.6 illustrates the block-diagram of the unity-gain buffer used in thiscircuit. The buffer has a measured large-signal bandwidth of ⇠2 GHz [57].511M 10M 100M 1G 2G3G−5−30510Frequency (Hz)Voltage gain (dB)  Small signalLarge signal3 dB BW @ 1.65 GHz3 dB BW @ 2.63 GHzFigure 3.3.7: Small-signal (in blue) and large-signal (in red) frequency re-sponse of the unity gain buffer designed for testability of proposed system.Fig. 3.3.8 presents the buffered spectrum of the transmitter when theCSensor = Cbase = 1.6 pF with an extra 230 fF parasitic capacitance addedby adaptors and test setup. Aside from better efficiency of wireless powertransfer, another advantage of transmitting at higher frequencies is the im-proved sensitivity of the overall system as given by the following expression:@f@CC=Cbase = @@C ✓ 12⇡pLC◆C=Cbase= 12·f0Cbase (3.3.1)Where f0 = 1/2⇡pLCbase. For an inductance of 3.353 nH (note that dueto the use of buffer the effect of bond-wire inductance on the inductance ofthe LC tank is negligible) and total base capacitance (including parasitics)52Cbase = 1.83 pF the sensitivity of the monitoring transmitter is 555 kHz/fF.Figure 3.3.8: Measured spectrum of the transmitter. The alignment trans-mitter for the rectified voltage of 650 mV (a), The main transmitter connectedto CSensor = 1.83 pF. (b).The experimental setup for in-vitro measurements is shown in Fig. 3.3.9.As shown in the figure, the prototype IC is mounted on the printed-circuitboard (PCB) and is powered up wirelessly through an external antenna (An-ritsu P/N 2000-1030-R). We used 5 cm of ground beef to mimic the effectof tissue. The received power from antenna, even without matching is suffi-53ciently large to start up the monitoring transmitter. As expected the adapterattached to stentenna adds an extra parasitic capacitance of 0.92 pF and thuslowers the monitoring frequency to 1.731 GHz.Monitoring TX-53 dBm @ 1.731 GHz to PXAFront view External AntennaModeling tissues and lumenPXA signal analyzerIC mounted on the PCBExternalAntennaOverview ofthe test setupSide viewGND StentennaFigure 3.3.9: The in-vitro measurement setup used in this work.Fig. 3.3.10 depicts the frequency sensitivity of auxiliary transmitter ver-sus output voltage of rectifier (received input power). The importance of thealignment unit is further highlighted when the patient’s tissue thickness isabove average and consequently, the received power is very small. The mea-sured results shown in Fig. 3.3.10 confirm the simulated and expected designtargets. Table. 3.1 summarizes the performance of the system and compares54it with relevant state-of-the-art designs.500 600 700 800 900200300400500600Supply voltage (mV)Frequency of TX (MHz)  Measured frequency of the alignment   Quadratic fit∆f/∆V=1.397 (MHz/mV)Figure 3.3.10: Transmitted signal frequency of alignment unit versus re-ceived input level.The summary of performance of this design as well as a comparison be-tween the performance of the proposed telemonitoring system and the state-of-the-art designs for similar applications is presented in Table 3.1.55Table 3.1: Performance summary and comparison of the proposed architecture with the state-of-the-art designsfor similar applications. This work [11] [14] [58] [59] [12]Year 2013 2013 2010 2009 2006 2006CMOS process (µm) 0.13 N.A. 0.13 1.5 3 (BiC-MOS)N.A.Supply voltage (V) from 0.5 operatesat 0.88 N.A. 2.5 2  2.5  N.A.RFsensitivity*(dBm) 13.18 N.A. 8**- 0***   N.A.Power consumption 156.9 µW N.A. ⇠2 mW 300 µW 340 µW N.A.Area (mm2) 0.484 4† 0.49†† 4.84 10 2.52Implant depth (mm) up to 30 4 35 10 0 0Sensitivity (kHz/fF) 555 ††† 7.5 N.A. ‡ N.A. ‡‡ 0.00075 28.7Sensor basecapacitance (pF)1.6 5-10 5.23 2 10 ⇠4.6Measurement setup in-vitro in-vivo in-vivo in-vivo in-vitro in-vitroMethod oftelemonitoringactive passive active active active passive* Minimum input signal power to turn-on the chip based on 50 ⌦ matching. †† Excluding the required off-chip circuits.** Extrapolated from the measured results of the IC. ††† 1.0 V harvested supply.*** Achieved using off-chip components (⇠1 ⇥ 1 cm2). ‡ Resolution of 0.5 mmHg.† Area of the passive sensor. ‡‡ Resolution of 0.125 mmHg.56Chapter 4Ultra-Wideband Analog UnityGain BufferIn this section, an ultra wide-band analog voltage-mode buffer is presentedwhich can drive a load impedance of 50 ⌦. The presented feedback-basedbuffer uses a compound amplifier which is a parallel combination of a high-DC gain operational amplifier and a operation transconductance amplifierto achieve a high unity gain bandwidth. A proof-of-concept prototype isdesigned and fabricated in a 0.13 µm CMOS process. The simulation andmeasurement results of the proposed buffer are in good agreement. The pro-totype buffer circuit consumes 7.34 mW from a 1.3-V supply, while bufferinga 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp) amplitudeand driving an AC-coupled 50-⌦ load.574.1 IntroductionWide-bandwidth unity-gain analog buffers are used in a variety of high-speedand agile applications such as analog-to-digital converters [60], switch capac-itors [61], sample-and-hold circuits [62] and active probes in measurementinstruments. A simple and commonly used architecture for such buffers is asource-follower-based buffer [61–63]. However, achieving high linearity andspurious-free dynamic range (SFDR) as well as an accurate gain in suchbuffers are challenging [63], although different techniques to address theseproblems have been investigated [64]. In cases where the gain accuracy andflatness are not crucial, source-follower architectures are used for driving lowimpedance values such as a 50 ⌦ load (or a large capacitive load). In thesecases, a relatively large driving transistor is required. This large transistorin effect limits the input bandwidth of the circuit. One way to amelioratethis issue is to cascade multiple source-follower stages and gradually increasethe size of the transistors. Each additional stage adds extra pole to thesystem which results in deteriorating the stability and overall bandwidth ofthe system. Furthermore, testing high-frequency circuits typically requiresa buffer since many high-speed integrated circuits are not capable of driv-ing the standard 50-⌦ input impedance of the high-frequency measurementinstruments. Thus, having a monolithic unity-gain buffer (voltage follower)with relatively flat and accurate gain is desirable. To achieve such a mono-lithic analog buffer feedback-based buffers are typically used, e.g, using an58operational amplifier in a unity-gain feedback structure ensures a relativelyaccurate gain in the presence of process, supply voltage, and temperature(PVT) variations. Fig. 4.1.1 shows one possible architecture for such de-signs. The bandwidth of this buffer is mainly limited by the bandwidth ofthe operational amplifier and the size of the driving transistor.+VDD_BufferV_BiasAInOutMDFigure 4.1.1: The architecture of a conventional amplifier based analog buffer.4.2 Proposed ArchitectureTo have an accurate flat gain, the open-loop gain of the buffer has to berelatively large. The overall open-loop gain of the buffer can be written asfollows:A(!) · (!) = G(!)⇥ gm0(!)⇥ Zout(!)⇥ 1 (4.2.1)where G(!) is the voltage gain of the amplifier A and gm0(!) is the small-signal transconductance of the driving transistor (MD in Fig. 4.1.1) at the59input frequency of !, Zout(!) is output impedance seen at the output nodeof the buffer, and (!) is the feedback gain which for the structure shownin Fig. 4.1.1 is equal to 1. The closed-loop voltage gain of the buffer can bewritten as:VoutVin (!) = A(!)1 + A(!) · (!) = A(!)1 + A(!) (4.2.2)From (4.2.2), the overall gain of buffer in approximately 1 over the rangeof frequencies where A(!)  1. Since for the most part the open-loop gainof the buffer is provided by the amplifier A, a wide bandwidth amplifier isneeded. However, designing amplifiers with both high voltage gain and highbandwidth is challenging. One elaborate solution is the compound amplifierintroduced in [6]. The architecture of this amplifier is shown in Fig. 4.2.1.VDDvIN  M2VBias_extOPAMPM1 M3M4M5vIN Figure 4.2.1: Architecture of compound amplifier used in this design.As shown in the figure to achieve high gain at low frequencies, a high DC60gain but low bandwidth amplifier, namely an operational amplifier (opamp),is used. The operational amplifier is in parallel with a high bandwidth oper-ational transconductance amplifier (OTA). The generic magnitude frequencyresponse of the overall buffer along with its typical polezero locations isshown in Fig. 4.2.2. As described in [6], the combination of the OTA andopamp will introduce a zero, namely zOTA , which helps to compensate forthe adverse effects of the dominant pole of the opamp. Although the bufferis generally connected to a small load impedance (e.g., 50 ⌦), to ensure thestability of this architecture a zero (zESR) is also added (using a series com-bination of a resistor and a capacitor, i.e., combination of RESR and Cz inFig. 4.2.3) to the output of the amplifier to compensate for the output load.pOpampzOTAp loadzESRpOTAOpen-loop Voltage Gain (dB)FrequencyFigure 4.2.2: Pole-zero location of the proposed buffer61M2M5M1M4M3R2VCM22M20M19M11M18M17M16M15 VCVBVopampM24 M25M27M26M7 Vbias_OTAVopampOutM10CcR1Biasing circuitMDVDD_BufferOpamp OTAOutInM12 M21M13 M14InOutM9M8M6M23Vbias_OTAOutRESRCzVBVB M28Figure 4.2.3: The overall schematic of analog buffer presented in this work.4.2.1 Circuit implementationThe schematic of the presented buffer is shown in Fig. 4.2.3. To achievea large low-frequency gain a telescopic cascode architecture is used for theopamp. The buffer has an input impedance of ⇠8 G⌦ in parallel with 127 fF(averaged from DC to 1 GHz). For the purpose of driving a low-impedanceload, a relatively large driving transistor, namely, MD, is used. The simulatedfrequency response of the opamp as well as that of the OTA are shown inFig. 4.2.4. Fig. 4.2.5 shows the frequency response of the overall compoundamplifier. The drop in the low-frequency gain of the compound amplifier (ascompared to the opamp low-frequency gain) is due to the loading effect ofthe diode-connected active load of the OTA. This gain drop also results inpushing the dominant pole of the opamp to higher frequencies (as can beseen in Figs. 4.2.4 and 4.2.5).62100 102 104 106 108 1010020406080frequency (Hz)Gain (dB)  100 102 104 106 108 1010050100150200frequency (Hz)Phase margin (degree)OTAOpamp5.9 GHz10.47 MHz72°50°Figure 4.2.4: Frequency response of the opamp and OTA.100 102 104 106 108 101002040frequency (Hz)Gain (dB)  100 102 104 106 108 1010050100150200frequency (Hz)Phase margin (degree)Zero Introduced by OTA 3.5 GHz45°Figure 4.2.5: Frequency response of the compound amplifier.Since the buffer is expected to operate for input signals with relativelylarge voltage swing, and the output of the buffer follows the input signal,special attention should be paid to biasing of the circuit. To put this in63perspective, consider the case that the input is a step with a large amplitude.Since the output follows the input, both input terminals of the OTA willexperience large voltage levels which results in lowering the drain voltageof transistors M24 and M25 of the OTA. In this case, transistors M24 andM25 may enter the triode region of operation. A similar scenario applieswhen the input signal is at a low voltage level, where the voltage level of thedrain terminal of M26 and M27 of the OTA will increase and therefore thesepmos transistors may enter into triode region of operation. To maintain areasonable voltage level at the drain of these transistors a common-modefeedback circuitry shown in Fig. 4.2.3 consisting of an analog inverter (i.e.,transistors M6 to M9) along with biasing circuit is used. This feedback circuitfacilitates the operation of the circuit over a wider input voltage range byproperly adjusting the tail current of the OTA. Fig. 4.2.6 shows the simulatedoutput voltage of the OTA with and without the common-mode feedbackcircuit.0 0.2 0.4 0.6 0.8 common voltage level (V) Output DC voltage of OTA (V)   With common−mode feedbackWithout common−mode feedbackFigure 4.2.6: Simulated output voltage level of the OTA with and withoutthe common-mode feedback circuit.64(a)(b)Figure 4.2.7: Measured step response of the proposed buffer for (a) 350 mVand (b) 700 mV of input step amplitudes.4.3 Experimental ResultsA proof-of-concept prototype of the proposed buffer is designed and fab-ricated in a 0.13-µm CMOS process. Fig. 4.3.1 shows the chip micrographalong with the layout view of the buffer (the inset in the figure). The overall65Table 4.1: Performance summary and comparison with the state-of-the-art analog buffers.YearProcess(µm)Supply(V)Power(mW)Bandwidth(MHz)Slew rate (V/µs) LoadArea(µm2)This work 2013 0.13 1.3 7.34 2000 SR : 185,SR+:254 50 ⌦ || 20 pF 6059[65] 2011 0.35 ±0.75 0.153 1.366  10 pF 55000[61]* 2011 0.5 1.5 0.0585 10  2 pF [66] 2010 0.5 3.3 0.198 13.4SR:35,SR+ :2930 pF 17000[67] 2009 0.35 3.3 4.8 90 200 13 pF 29100* Simulation results.66circuit occupies 6059 µm2. The the chip consumes 7.34 mW from a 1.3 Vsupply voltage while buffering a 2 GHz sinusoidal input signal and drivingan AC-coupled 50-⌦ load.Figure 4.3.1: Micrograph of the presented buffer.Fig. 4.2.7 shows the measured transient step response of the buffer asmall and a relatively large input steps. The simulation results show that thebuffer provides almost the same performance for both small and large inputsteps which can be attributed to the common-mode feedback circuit usedin the OTA. In the transient measurements (Fig. 4.2.7) the load includingthe input impedance of the measurement equipment (Tektronix DPO4054Oscilloscope) is a 20 pF capacitive load in parallel with a 50⌦ resistor. Thepulse generator used in these measurements is HP8110A which can generatepulses with a rise time of 8 ns.67Figure 4.3.2: Measured magnitude frequency response of the proposed buffer.Figure 4.3.3: Output spectrum for a 133.33 mVppinput sinusoid at⇠100 MHz.The frequency response of the buffer is measured in the closed-loop con-figuration. For an input signal of 400 mVpp, the frequency response of the68closed-loop buffer is measure with an Agilent vector network analyzer E5061Band is shown in Fig. 4.3.2. As can be seen from the figure, the 3dB band-width of the buffer is 2 GHz. The total harmonic distortion (THD) of thebuffer is measured using an Anritsu MS2034A for a ⇠100 MHz input signalwith a peak-to-peak amplitude of 133 mVpp . The measured result is shownin Fig. 4.3.3. The buffer achieves a THD of ⇠25.5 dB. For a input signal of1 MHz with a peak-to-peak amplitude of 270 mVppthe THD of the buffer is34 dB.69Chapter 5Capacitance-to-VoltageConverter BasedTelemonitoring SystemIn this chapter an ultra-low-power system for wireless monitoring of capac-itive sensors based on capacitance-to-voltage converters is discussed. Theproposed architecture is designed to consume even less power in compare tothe first system (CFC) and therefore it is particularly suitable for biomed-ical implants where the implanted device is deep inside the body or hasminute dimensions. The proposed telemonitoring system consists of a radio-frequency (RF) power harvesting block providing the supply voltage for therest of the system, a capacitive sensor interface, and an RF transmitter totransfer sensory data to the external reader. The sensor interface consists of70a capacitance-to-voltage converter and the transmitter includes a voltage-to-frequency converter. The frequency for the transmitted signal is proportionalto the change of the capacitance of the sensor. A proof-of-concept prototypeis designed and fabricated in 0.13 µm CMOS. Measurement results show thatthe system operates from a harvested supply of as low as 350 mV (from inputpower of43.76 dBm at 1.25 GHz) while drawing less than 100 nA from itsharvested supply.5.1 IntroductionUltra-low-power circuits are essential in many applications including biomed-ical implants particularly when the implant is required to operate from a har-vested energy source. This class of biomedical implants include implantabletelemonitoring systems for diagnostics such as coronary blood pressure mon-itoring systems [14, 17, 18, 32, 37, 42, 44]. Such devices use a wireless linkto transfer power to the implant as well as to communicate information tooutside the body. One of the main challenges in engineering such devicesis adhering to the regulatory requirements regarding power exposure of livetissues. These geographically segmented regulations are governed by regionalagencies such as the Federal Communications Commission (FCC) in NorthAmerica [45] which limit the strength of the radio-frequency (RF) signalsused to transmit power and/or communicate data to and from the implant.Due to the high absorption coefficient of tissue in the ultra-high-frequency71(UHF) range, these limitations on the RF signal strength restrict the rangeof communication, making the design of ultra-low-power electronics for deepimplants a vital consideration [3, 14]. In this work, an ultra-low-power inte-grated circuit is designed for integration with a custom-made coronary stentacting as an antenna [12]. The device harvests RF power from the antennastent, interface with a micro-electromechanical system (MEMS) pressure sen-sor, and transmit the sensor data to the outside of the body using the sameantenna. This device is of particular interest for monitoring stent occlu-sion (restenosis), which occurs in 4.9% [68] of patients who receive stentswithin a year of surgery, significantly altering the coronary blood pressureand potentially causing heart attacks. Studies have determined the powerrequirements of such wirelessly powered systems for monitoring and trans-mitting blood pressure data [17], and reveal that the power harvested by theimplantable device at a depth of 39 mm from the surface of the body canbe as low as 56 µW. Since the average distance from a coronary stent to thesurface of the patient’s body is about 39 mm [69], this application requiresfurther reduction in the power requirements of previously reported wirelessmonitoring systems [9,14,35,42,44,58,59,70]. Although ultra-low-power sys-tems for intraocular implants have already been proposed [13], they have ashorter read range and larger antennas than the proposed coronary monitor-ing system. Also, in the context of this work, special consideration must begiven to the low efficiency of the stent-based antennas (e.g., antenna stentor stentenna [12]) that make low-power requirements on the electronics even72more stringent.External Reader Matching circuitForward link(power delivery )Backward link(sensory data)Rectifier RegulatorSensor(s)Sensor Interface CircuitTransmitterReference and Biasing CircuitInternal Tele-monitoring System Figure 5.1.1: Building blocks of a typical telemonitoring system.Fig. 5.1.1 illustrates a generic biomedical telemonitoring system that con-sists of a power harvesting unit, a sensor interface circuit, and a transmit-ter block. The power harvesting unit typically includes a rectifier stageand in some cases it also includes a low-dropout (LDO) voltage regula-tor [13,14,34,43,71]. The sensor interface processes the sensory data, whichconsists of one or more environmental/biomedical variables such as pres-sure [12–14, 58, 72, 73], temperature [13], and oxygen level, ... [8, 10, 16]. Inthis work, we interface to capacitive pressure sensors which have been usedfrequently in devices that monitor intraocular or blood pressure. To reducethe power consumption and complexity of the system, the sensor interfacecircuit and transmitter can be merged in an analog capacitance-to-frequencyconverter (CFC) comprised of an LC CMOS oscillator whose capacitor is thatof the capacitive pressure sensor. A drawback of using such a CFC structureis the fixed sensitivity and resolution of the telemonitoring systems [32,58,74].Another issue is that the center frequency of the output signal depends on73the base capacitance of the sensor (i.e., the nominal fixed capacitance of thesensor) which may vary or limit the frequency range of operation. To over-come this problem, an alternative design approach has been proposed wherethe difference between the capacitance of the pressure sensor and a referencecapacitor is used to control the frequency of a transmitter [13,59,75]. Manysuch designs use rather complex circuitry which requires a relatively highsupply voltage or consumes a high power that limits the operating range ofthe overall monitoring system.In this work, we focus on reducing the turn-on voltage of the overalltelemonitoring system. To eliminate the dependency of the transmission fre-quency on the base capacitance of the sensor, an alternative capacitance-to-frequency converter structure is presented. The proposed architecture con-sists of a capacitance-to-voltage converter (CVC) stage followed by a voltage-to-frequency converter, i.e., a voltage-controlled oscillator (VCO) stage. Thetransmission of the data is performed using an ultra-low-power/low-voltageVCO.5.2 The Proposed Telemonitoring Architec-tureOne of the target applications of the proposed system is to monitor restenosisin coronary arteries. The depth of the coronary artery (on average 39 mmfrom the surface of the body) along with relatively small diameter of the74artery (average diameter of 2.74 mm [76]) poses significant challenges to thedesign of such telemonitoring systems. Given the limited amount of receivedpower in such a system (around 56 µW [17]), to have a sufficient currentbudget for all the various building blocks of the system to reliably operateit is necessary that the system operates with a relatively low supply voltage.The proposed system is designed to operate from a supply voltage as low as0.35 V. As will be discussed, this improved current budgeting facilitates theuse of a broader range of capacitive sensors with a larger base capacitance.The architecture of the proposed telemonitoring system is shown in Fig.5.2.1. The first stage consists of a rectifier stage which provides the supplyvoltage for the rest of the circuit. Simulation results show that the rectifieris capable of providing up to 1.0 V from a minimum input power level of 6.3mV input signal amplitude, in differential configuration. We can translatethat input voltage to 34 dBm input power level, if the input impedancewere 50 ⌦. For input power level of 17.8 dB the rectifier supplies 11 µWof output power at 1.0 V output voltage. Since in biomedical telemonitoringapplications, the impedance of the implanted antenna may change dependingon the application, we have not included the matching circuit of the antennainside the IC. In practice, either an application specific matching networkshould be used or ideally an adaptive matching network should be employed.More discussion on this is provided in Section 5.3.The presented configuration uses a CVC stage which generates a voltagerepresenting the change of the capacitance of the capacitive sensor. The75Clock Gen.CSensorCLKRectifierIn+In-VRef CRange AVRef S/H S/HCVC_OUTICh IChOUT+/-Bias and reference voltage CLK CLKCLK & CLKCLKCLKCLKCLKCLK &Figure 5.2.1: Overall configuration of the proposed telemonitoring system.76structure of the CVC system is shown in Fig. 5.2.1. Two identical currentsources are utilized to charge up the sensor’s capacitance and a fixed range(reference) capacitance . A clock generator provides two phases of operationof the CVC circuit. The “charging phase”consists of charging the sensor andthe range capacitors, after which they are discharged to ground during the“resetting phase”. According to Fig. 5.2.1, the voltage across the capacitivesensor is:VSensor = V0 + 1CSensor tˆ iCh(t)dt = V0 + IChtCSensor (5.2.1)where V0 is the voltage of the sensor capacitance at the beginning of thecharging phase, t is the charging time period, and ICh is the constant cur-rent generated by the current source. Because the resetting phase dischargesthe sensor capacitor to ground, V0 is taken to be 0 V in this analysis. Thesymmetric structure of the circuit allows a similar equation to be writtenfor the range voltage, VRange. When VSenso reaches to the level of a referencevoltage, VRef (see Fig. 5.2.1), the circuit turns off the current source chargingthe range capacitor, and the difference between the voltage across the capac-itor and the reference voltage is amplified to improve sensing resolution. Thetime when the range capacitor current source is turned off, namely, tstop, canbe calculated as:tstop = CSensorVRefICh (5.2.2)77Substituting this stop time into (5.2.1), the output of the differentialamplifier A with DC voltage gain A0 is :VCV C = A0( kIChCRange CSensorICh  1)VRef= ✓kCSensor  CRangeCRange ◆ (5.2.3)where  = A0VRef , and k is the current ratio between the sensor and rangecapacitor current sources. Note that for k = 1 , (5.2.3) can be simplified to:VCV C = (/CRange)C (5.2.4)where C = CSensor CRange. To optimize sensitivity of the CVC block,the range capacitance CRange is typically set equal to the base capacitance ofthe sensor. Note that according to (5.2.4), the sensitivity of the CVC blockcan be tuned by adjusting the voltage gain A0, and the reference voltageVRef , but is independent of the charging current ICh.The output voltage of the CVC block is fed to a transmitter and sets thetransmitter’s frequency. To improve the sensing resolution and reduce thetransmitter phase noise caused by fluctuations in this control voltage, themaximum voltage output of the amplifier is sampled and held at the endof each charging phase to achieve a stable DC voltage proportional to C.Implementation is accomplished using two sample and hold blocks cascadedin a complimentary fashion (Fig. 5.2.1) at the output of amplifier A . The78result is that the CVC output voltage tracks changes in the sensor capacitancewith each clock cycle.The simulated performance of the CVC block for 0.35 V and 1.0 V supplyvoltages is shown in Fig. 0.2 0.4 0.6 0.800.  time (ms)Voltage (V)VSensorVRangeCLKCVCOUTVRefVRef=575 mV(a)0 0.5 1 1.5 2 2.5 3 3.5 400. (ms)Voltage (V)  VSensorVRangeCLKCVCOUTVRefVRef=146 mV(b)Figure 5.2.2: The simulated transient response of the CVC block forCSensor = 1.9 pF and CRange = 1.4 pF at supply voltage of (a) 0.35 V(b) 1.0 V.805.3 Circuit ImplementationIn this section, the design and implementation of different building blocksof the proposed telemonitoring system as well as their performance are pre-sented.5.3.1 Rectifier stageTo harvest the incoming energy, a differential rectifier stage is used whichis based on [77]. For the purpose of this work, the rectifier is optimized toprovide a high power efficiency at the operating frequency of 1.25 GHz. Toimprove the efficiency of the the system and to ensure that the system isable to operate with small incoming signal amplitude, a voltage matchingcircuit is placed between the embedded antenna and the rectifier stage. Thevoltage matching circuit consists of a series inductor that will resonate withthe input capacitance of the rectifier stage. However, for transmitting sensorydata through the implanted antenna a power matching circuit is required toensure that most of the available power at transceiver unit is transmitted tothe external reader.In contrast to typical telemonitoring architectures, the proposed systemdoes not include a voltage regulator stage for three main reasons: firstly, theincident signal received by the rectifier is at 1.25 GHz, thus the fundamentalfrequency of ripples of the rectifier stage will be at 1.25 GHz. A regulatorwhich is capable of actively rejecting 1.25 GHz ripples should have a high81out1 out2Mn1 Mp1Mn2 Mp2in+in-Zin+ = ZCin+    Rin+ CCCCCS/DCGin+CG,n2 CG,p2CS/D,n1 CS/D,p1Cin+Zin- = ZCin-    Rin-Figure 5.3.1: Schematic of one stage of the three-stage differential rectifier.closed-loop bandwidth and therefore is power hungry [52] and is not feasiblefor this low-power application. Secondly, in the architecture of the moni-toring circuit no digital blocks or clock signals are used and therefore theload variation is not significant. This relaxes the voltage regulation require-ments and some degree of voltage variations can be tolerated. Thirdly, sincethe rectifier is driving an ultra-low power monitoring circuit which couldbe modeled as a large equivalent resistance, the combination of the largeload resistance and the rather small smoothing capacitance at the output ofthe rectifier form a passive RC filter. This filter sufficiently attenuates thehigh-frequency ripples at the output of the rectifier. Nevertheless, in appli-cations where the power budget permits the use of an additional regulator,the improved regulator structures presented in Appendices A and B can beused.In this work, a three-stage differential rectifier [50] is used to efficientlyconvert the RF energy to DC power in order to supply the entire succeedingcircuitry. The second stage of the rectifier is shown in Fig. 5.3.1. At the82frequency of interest, i.e., 1.25 GHz, where the parasitic inductance valuescould be neglected, the input impedance of the rectifier could be modeledby the parallel combination of a capacitor Cin and a resistor Rin (as shownin Fig. 5.3.1 [51]). Note that the capacitive part of the input impedance ac-counts for the combination of the coupling capacitors CC (which is typicallya linear capacitance) and the parasitic capacitance values of the switchingtransistors MPi,Ni (nonlinear capacitance). The resistive part of the inputimpedance represents the average DC current drawn from the differential in-puts and parasitic losses and therefore varies with the load. Note that in thealignment mode when the input level is small, the effect of nonlinear compo-nent variations are minimal and thus the input impedance could be consid-ered constant. In order to produce a sufficiently high output power/voltageto drive the alignment unit for a small input level, the input of the rectifier ismatched to the impedance of the source (antenna stent). In practice, match-ing could be achieved by optimizing the sizing of the coupling capacitors CCand switching transistors such that the resulting input capacitance of therectifier resonates with the inductance of the stentenna at the frequency ofinterest. Note that as shown in Fig. 5.3.1, given that CC  CG  CS/D,the input capacitance of the rectifier is dominated by the capacitance seenat the source/drain of the PMOS and NMOS switching transistors (CS/D).Although the source/drain parasitic capacitance of the switches is voltagedependent, its value is almost constant for a large range of input levels andtherefore, a single inductor per each differential branch is used to resonate83. . .{x3M32M31M30M29M28M27VDDM26M25M24M23M19M17M20M16M15M22M21M33IChVBCMM2M1 M9M8RM4M3M5M6M10M7M11M12M13M14VBCMVBVCOVRefVBCLKVBCLKCLKCLKCLKVBCMReference Voltage and Biasing Clock Generator Current SourceM18Figure 5.3.2: The schematic of clock generator current source and biasingcircuit.with this capacitor.5.3.2 Clock generatorFig. 5.3.2 presents the schematic of the circuit used for generating the clocksignal. To generate the clock while operating from a low supply voltage,a ring-based oscillator is employed. To decrease the dynamic power con-sumption, the length of the transistors are chosen to be large enough. Thisin turn will reduce the output clock frequency. The clock frequency mustbe low enough so that the voltage across the sensor capacitor in the CVCblock can reach the reference voltage during the charging phase (durationtstop). Assuming a clock with a 50% duty cycle, this requires that the clockfrequency satisfies:1fclock = Tclock > 2 (tstop + tsetup + thold) (5.3.1)84where tsetup and thold are the setup time and hold time of the subsequentsample-and-hold stage. In this design, tstop is much larger than tsetup + tholdand therefore the minimum clock period is approximately 2tstop. Note thatthe factor of 2 is due to the 50% duty-cycle clock. On the other hand, theclock frequency must be high enough such that the change in the voltageacross the range capacitor, VRange, due to the leakage current stays withinan acceptable range. It can be shown that to keep the voltage change acrossthe range capacitance to within 2%, the clock period should satisfy:Tclock < 2⇥ 0.02⇥ (RleakageCRange) (5.3.2)where Rleakage is the total resistance to ground in parallel with the rangecapacitor. Rleakage is primarily due to the reset switch. For adjusting theclock frequency, the tuning circuitry consisting of transistors M15M20 shownin Fig. 5.3.2 is used adjust the frequency of the clock generator. This circuitryallows the clock frequency to be adjusted by setting the voltage V BCLK .5.3.3 Current sourceThe current source architecture along with its associated bias circuitry areshown in Fig. 5.3.2. A voltage-controlled current source stage is implementedusing a cascode stage of NMOS transistors M21M22 and the correspondingcurrent mirror stage is a modified version of [78]. In this design, to decreasethe output current to the pico ampere range, the cascode configurations85consisting of transistors M23M28 are used as active loads for the PMOScurrent mirror consisting of M29M32 which in turn sets the output currentICh. The output current can be adjusted between 150 pA to 800 nA bychanging the bias voltage of the current source stage. The solid and dashedtraces in Fig. 5.3.3 show the simulated output of the current source for supplyvoltages of 0.35 V and 1.0 V, respectively. The simulation results show thatthe current source generates a constant current over an output voltage rangeof 0 to 0.8VDD within 98.8% of the nominal current at 0.35 V and 99.4% of thenominal current at 1.0 V supply. For small values of the sensor capacitance(i.e., 0.1 to 1 pF), the bias voltage and corresponding output current shouldbe lowered to ensure the sensor capacitor charging time is in a reasonablerange for correct operation of the CVC stage. Simulation results of this caseare shown by the two lower traces in Fig. 5.3.3. These to traces correspondto the cases where the circuit delivers 219 pA at 0.35 V and 329 pA at 1.0 V,with 86.3% and 86.76% of nominal current, respectively.860 0.2 0.4 0.6 0.810−1100101102103Output Voltage (xVDD)I Ch (nA)  VBias=35mV @ VDD=0.35 VVBias=185mV @ VDD=0.35 VVBias=55mV @ VDD=1.0 VVBias=805mV @ VDD=1.0 V6.43 nA219 pA328 pA729 nAFigure 5.3.3: Example graphs of the simulated output current of the proposedarchitecture for VDD = 0.35V (solid line) and VDD = 1.0V (dashed line).5.3.4 Sample-and-hold circuitTwo cascaded sample-and-hold stages which in effect form a peak detectorcircuit, are used in the CVC block (Fig. 5.3.4). Each sample-and-hold stagecontains unity gain buffers at its input and output to avoid unwanted loadingeffects [79]. The buffers are implemented using a generic single-stage differen-tial to single-ended amplifier architecture with NMOS input transistors andactive current mirror load [80]. The buffers can operate from a relatively lowsupply voltage, The dummy transistors D1 and D2 are half the size of M1 andM2, respectively, and are added to reduce the effect of charge injection [79].87 AM2M1 D1D2InputOutputCH ACLKCLKCLK CLKFigure 5.3.4: The architecture of the sample-and-hold used in CVC block5.3.5 Transmitter100 nHM10M9 M7M8 M6Monitoring Transmitter100 nHCVC_OUTOUT+OUTVBVCOVDDFigure 5.3.5: Schematic of active transmitter used in this design.As shown in Fig. 5.3.5, a complementary cross-coupled LC CMOS oscillator[54] is used due to its high power efficiency. Same technique that has beenused for alignment transmitter in previous design (see Chapter 3) is also88applied to further reduce the power consumption. In addition, to increasethe frequency sensitivity (!/C) a small variable capacitance is used inthe transmitter LC tank. The value of this variable capacitance (varactor) isadjusted by the output voltage of the CVC block, and thus any change in theCVC output voltage shifts the oscillation frequency of the transmitter. At asupply voltage of 1.0 V, the transmit frequency is 659 MHz. However, at alower supply voltage of 0.35 V the transmit frequency is 85 MHz. Note thatthe drop in the frequency at lower operation voltage can be attributed toparasitic capacitance of the output node as the parasitic capacitance valuesare larger at lower voltages.5.4 Simulation and Experimental ResultsA proof-of-concept prototype is designed and fabricated in a 0.13 µm CMOSprocess. Fig. 5.4.1 shows a micrograph of a test chip that contains twodifferent telemonitoring designs. Both designs (a) and (b) have connectionsto interface with a MEMS capacitive pressure sensor, while design (b) alsohas a variable capacitance (varactor) that can be used instead of a MEMSpressure sensor for testing purposes. The dimensions of each design are1060 µm ⇥ 360 µm (0.381 mm2), and as it is visible in the micrograph,most of the layout area is dedicated to the transmitter inductor (which is theequivalent inductor of two series inductors) . The simulated and measuredperformance of the system is discussed in the following subsections.89Figure 5.4.1: Micrograph of the proposed telemonitoring system (a) without(b) with built-in variable capacitor.Cin RinZin,recRFinWire-bondLWBRectifier Tele-monitoringVDDTele-monitoring chipCQFP-80 packageFigure 5.4.2: The wire-bond matching used in this work.90Figure 5.4.3: The micrograph of the wire bond interconnects for CQFP80package.5.4.1 DC performanceThe overall system consumes 10.4 µW at a supply voltage of 1.0 V. Note thatin this measurement the transmitter output feeds an integrated unity gainbuffer, and thus the loading of an antenna is not accounted for. In practice,when an antenna is used a matching circuit is required for maximum powertransfer to the antenna. When the supply voltage is decreased to 0.35 V,the system draws ⇠100 nA (measured with a HP34401A multimeter) whichcorresponds to an overall power consumption 35 nW. Fig. 5.4.4 shows thetotal quiescent current of the system (excluding the power of the buffer) fordifferent supply voltages.910.35 0.6 0.8 1 1.20.1110100Supply voltage (V)Quiescent current (µA)  MeasuredSimulatedFigure 5.4.4: Simulated and measured quiescent current for different supplyvoltagesTo maximize the performance of the rectifier, the input of the rectifiermust be voltage matched (i.e., resonate) with the signal source at the operat-ing frequency. Although, in practice, this rectifier will receive power from anantenna stent (or similar biomedical implanted antenna), for test purposes,we used a signal generator to emulate the received signal from the antenna.To be able to match the rectifier input stage without using on-boarddiscrete components, as shown in Fig. 5.4.2, the intrinsic inductance of thepackage wire bonds is used. The RF input is supplied by an Agilent 83732Bsignal generator through a Picosecond 5310 balun and the input voltage tothe rectifier is measured at the corresponding package pins using an activeprobe (1169A 12 GHz InfiniiMax). For interconnects with closely spaced wire92bonds, [56] provides a closed form expression for the inductance of the wirebonds as a function of their geometric parameters. We used the wire bondparameters and typical length and spacing used for a 80-pin ceramic quad flatpackage (CQFP80). For a wire-bond length of 4.9 mm ( LWB = 32.78 nH) ,as shown in Fig. 5.4.3, which is typical for the wire-bond length of CQFP80when the pads and the associated pins are located at the corner of the chipand package, the input capacitance of the rectifier is designed to be 457 fF(simulated) in order to resonate with 32.78 nH inductance of the interconnectwire-bonds at 1.25 GHz.0.4 0.6 0.8 1 1.5 2 2.5020406080100frequency (GHz)(Output DC voltage)/(amplitude of input signal)1.25 GHzFigure 5.4.5: The measure performance of the rectifier for different inputsignal frequenciesNote that the capacitive input impedance of the CMOS rectifier facilitatesa simple impedance matching with the inductance of the stentenna. Throughappropriate sizing of the coupling capacitors and switching transistors, the93input capacitance of the rectifier could be arbitrarily optimized to resonatewith the inductance of the stentenna at the frequency of interest which elimi-nates the need for a sophisticated and bulky matching networks. Consideringthe target application and optimum frequency range for power delivery, wehave considered to match the rectifier at ⇠1.30 GHz. After populating theprinted circuit board, the matched frequency turned out to be at 1.25 GHz.Fig. 5.4.5 shows a measure of the performance of the rectifier defined as theratio of the value of the generated supply voltage to the amplitude of theinput signal versus different input-signal frequencies. In this particular ap-plication, since the frequency of the signal transmitted from the implanteddevice to the outside world is around 600 MHz or lower, we have decided touse a ⇠1.3 GHz signal for power transmission to avoid potential interferencebetween power and data transmission. However, depending on the appli-cation, one can adjust the resonant frequency of matching circuit for powertransmission to optimize the performance at the desired frequency. Fig. 5.4.6illustrates the generated supply voltage by the rectifier versus different val-ues of the input signal amplitude. The presented rectifier unit can generaterequired supply voltage of 0.35 V from the input signal amplitude of as lowas 2.05 mV (43.76 dBm). This measurement results also show that therectifier can generate supply voltage of 1.0 V from 18.7 mV (24.74 dBm).942.05 10 20 30 40 50 600.350.511.52Amplitude of the input signal (mV)Output supply voltage (V)  At 1.25 GHzFigure 5.4.6: The measured generated output voltage of the rectifier, whiledriving the CVC system, versus different amplitude of the input voltage at1.250 GHz.5.4.2 Transient responseFor the purpose of testing, the IC is mounted on a custom designed FR4printed circuit board (PCB). For initial testing, a 5 pF capacitor is connectedbetween the sensor nodes of the IC in place of a capacitive pressure sensor,and no capacitor is connected to the range nodes. Because of the additionalparasitic capacitance of the PCB traces and connectors, the sensor and rangecapacitance values are measured to be CSensor = 7.6 pF and CRange = 1.4 pF.A measurement of the voltages across each capacitor at a supply voltage of0.35 V is shown in Fig. 5.4.7 (top). When the 5 pF capacitor is removed,the capacitance values are Csensor ⇠= 2.6 pF and CRange ⇠= 1.4 pF. Fig. 5.4.7(bottom) shows the range and sensor capacitor voltage waveforms for thiscase.950 5 10 15 20 25 3000.10.20.3Voltage (V)  0 5 10 15 20 25 3000.10.20.3time (ms)Voltage (V)RangeSensorVrefVrefFigure 5.4.7: Measured sensor and range voltages for CRange = 1.3 pF and(top) CSensor = 7.6 pF and (bottom) CSensor = 2.7 pF.5.4.3 Frequency responseTo have a measure of the sensitivity of the system, that is, the equivalentfrequency change for a small capacitance difference between sensor and rangecapacitors (e.g., on the order of tens of femto Farad), we used simulation tofind the equivalent capacitance of the integrated varactor for different valuesof the control voltage. After canceling the intrinsic capacitance differencebetween range and sensor capacitors by adding compensation capacitors,for a given C we ran the simulation and read the output voltage of theCVC block and by changing the control voltage of the varactor we adjustedthe CVC_OUT of the circuit till it matches with the simulated value. For96larger C (in lower supply voltage), we added an external capacitance tobuild an offset. In this case, we measured the transmitted frequency andrelate it to the value of C we calculate in the simulation. Fig. 5.4.9(a)shows the simulated output voltage of the CVC stage for different calculatedcapacitance values, C, where CSensor = CRange + C, and the equivalentmeasured transmission frequency at 1.0 V supply voltage.60 70 80 90 100−75−70−65−60−55−50−45−40frequency (MHz)  560 570 580 590 600 610 620−90−80−70−60−50−40−30−20−10frequency (MHz)  ∆C=1 pF∆C=−1 pF∆C=−300 fF∆C=300 fF78.91 MHz 83.36 MHz580.4 MHz 604.5 MHzSupply voltage of 0.35 VSupply voltage of 1.0 VFigure 5.4.8: Measured frequency spectrum of the proposed telemonitoringsystem for different C at supply voltage of 0.35 V (top) and 1.0 V(bottom).97−400 −200 0 200 4000. (V)585590595600605610615620∆C (fF)Frequency (MHz)Supply voltage of 1.0 V(a)−1 −0.5 0 0.5∆C (pF)Frequency (MHz)Supply voltage of 0.35 V∆C= 600 fF∆f= 1.85 MHz(b)Figure 5.4.9: The simulated and measured output voltage of CVC blockand transmitted frequency of the overall system for different values of Cfor (a) 1.0 V of supply voltage and (b) 0.35 V supply voltage (CSensor =CRange +C).98Fig. 5.4.9(b) presents the same scenario for supply voltage of 0.35 V. Notethat for lower supply voltage the reference voltage VRef is lower (almost 4times lower as compared to 1.0 V supply voltage) as well as the DC gain ofamplifier A (see (5.2.4)).Fig. 5.4.8 shows the output spectrum of the transmitter for different val-ues of the sensor capacitance and supply voltage. The frequency spectrumat 0.350 V supply voltage is shown at the top of the figure. The solid red linecorresponds to CSensor ⇠= 2.5 pF and CRange ⇠= 1.4 pF (C = 1.1 pF), whilethe dashed blue line corresponds to CSensor ⇠= 2.5 pF and CRange ⇠= 3.5 pF(C = 1 pF). The spectrum corresponding to a 1.0 V supply voltage isshown at the bottom where the solid red line corresponds to CSensor ⇠= 2.5pF and CRange ⇠= 2.2 pF (C = 300 fF) and the blue dashed line is forCSensor ⇠= 2.5 pF and CRange ⇠= 2.8 pF (C = 300 fF). The measuredsensitivity of the system for supply voltage of 0.35 V and 1.0 V is 3.1 kHz/fFand 55.0 kHz/fF respectively. Since the input impedance of the spectrum an-alyzer used for testing (an Anritsu MS2034A) is 50 ⌦, and thus it requires arelatively large current from the transmitter, the output signal is first bufferedusing a unity gain buffer. The wide-band unity gain buffer used for this pur-pose is also on chip. Note the lower output frequency generated at 0.35 Vsupply voltage. As mentioned in Section III, this is due to the operationof the transistors in the sub-threshold regime where the effects of parasiticcapacitance are increased [80]. Thus, depending on the supply voltage, thereis a range of choices for the output transmission frequency [3, 17] that can99Table 5.1: Performance summary and comparison between state-of-the-art designsThis work [11] [13] [14] [58] [59] [12]Year 2013 2013 2011 2010 2009 2006 2006Process (µm) 0.13 N.A. 0.13 0.13 1.5 3BiCMOSN.A.Supply Voltage (V) 0.35 N.A. 1.5 2.5 2 and 2.5 3 N.A.RFSensitivity*(dBm)43.76 N.A. 10.5 8 to 0   N.A.PowerConsumption35 nW@0.35 V11 µW@1.0 V N.A. 2.3 µW ⇠2 mW 300 µW 340 µW N.A.Area (mm2) 0.381 4† 0.7 0.49 4.84 10 2.52Implant depth(mm)designed for 50 4 4 35 10 0 0Sensitivity3.1@0.35 V55.0@1.0 VkHz/fF7.5kHz/fF1.6fF/mmHg6.64fF/mmHg0.8fF/mmHg0.00075kHz/fF28.7kHz/fFSensor BaseCapacitance (pF)5@0.35 V20@1.0 V 5-10 5.6 5.23 2 10 ⇠12-16Measurement setup in-vitro in-vivo in-vitro in-vivo in-vivo in-vitro in-vitroMethod oftelemonitoringactive‡ passive†† active active active active passive* Minimum input signal power to turn-on the chip based on 50-⌦ matching.Extrapolated from measurement results.Using discrete components (⇠1x1 cm2).Excluding the off-chip rectifier.† Passive sensor area.‡ Uses active components such as transistors.††Uses only passive components such as inductors and capacitors.100be optimized depending on the size and depth of the implanted antenna. Asexplained in [3], for deeper implants (with fixed antenna dimensions), theoptimal output frequency shifts to a lower frequency, since tissue absorptionbecomes a more dominant effect. This conveniently matches the behavior ofthe transmitter output frequency which drops with decreased supply voltage.5.5 DiscussionAs discussed here, the proposed telemonitoring system is able to operatefrom both a low (0.35 V) and a relatively high (1.0 V) harvested supplyvoltage. One way to further improve the efficiency of the circuit is to utilizea rectifier circuit that has optimal efficiency for two different input signalamplitudes. An example of such a rectifier is presented in [74]. Anotherpossible improvement to the design is to replace the simple clock generatorused in this work with a differential clock generator that has a fixed tailcurrent. Designing the clock generator circuit in this way result in savingsin the chip area since it requires a smaller size transistors. Finally, thesimple amplifier A used in CVC design can be replaced by a more elaborateamplifier keeping the low-supply-voltage specification in mind. For example aprogrammable-gain amplifier can be realized by adjusting the feedback gainof a feedback-based amplifier which in turn controls the sensitivity of theoverall design.101Chapter 6Feasibility Study onBackscattering TechniqueIn this section the feasibility of telemonitoring sensory data using stentennabase on modulating the stentenna load is studied. Fig. 6.0.1 illustrates thesystem-level schematic of the proposed backscattering-based in-stent resteno-sis telemonitoring system. Backscattering refers to reflecting of the incidentpower (wave) back to the direction of the transmit power (wave). Backscat-tering can be used as a power-efficient means for communication [15, 81] .As shown in the figure, the external transmitter radiates a radio-frequency(RF) carrier signal that penetrates into the patient’s body. The RF signal isused for harvesting energy to operate the implanted telemonitoring systemembedded on the “smart stent”(i.e., the stent with embedded sensors andIC) [17]. The sensors embedded on each end of the stent (typically capac-102itive sensors) will help monitoring the blood flow through the stent. Thechange of capacitance of these sensors can be used as an indicator of thestatus of restenosis. The stent itself is used for RF energy harvesting as wellas an antenna for transmitting sensory data to the external reader. The taskof the telemonitoring system is to facilitate RF energy harvesting and con-trol data transmission. The data transmission is performed through varyingthe impedance seen by the stent. This is achieved by selectively opening orclosing the switch as shown in Fig. 6.0.1. Backscattering can accommodatevarious modulation schemes including amplitude, frequency and phase shiftkeying [81].Directional Coupler fdata Stent TissueSpectrum Analyzer1/fdatay=-sinx, x∊[0,2π]y=-sinx, x∊[0,2π]y=-sinx, x∊[0,2π]y=-sinx, x∊[0,2π]y=-sinx, x∊[0,2π]y=-sinx, x∊[0,2π]y=-sinx, x∊[0,2π]y=-sinx, x∊[0,2π]Signal Gen.Reader AntennaTransponder IC RLFigure 6.0.1: Schematic diagram of backscattering telemonitoring systemusing stent antennaAs mentioned above, RF power transmission in biomedical implants istypically achieved through one of the following techniques: inductive cou-103Antenna stentConventional stentFigure 6.0.2: Comparison of the mesh of medical stent and stentennapling (near-field), electromagnetic wave propagation (far-field), and ultra-sonic wave propagation. The ultrasonic-based power harvesting has beenused in various biomedical applications [33], however, due to the physicalgeometry and dimensions of the arteries using this method is impractical.Compared to inductive coupling, electromagnetic wave propagation does notrequire exact alignment of the primary and the secondary coils to achievemaximum power delivery. Although electromagnetic based systems providebetter power transmission efficiency for longer telemetry distances [14], forimplants within 4 cm of the skin where most of the transmitted power isabsorbed by tissues, the inductive coupling can be a viable approach [17].The conventional stent is a mesh-like tubular device shown in Fig. 6.0.2which is similar to a coil whose turns are linked together. Although thislinking bridges improve the structural strength of the stent they significantlyreduce its effective inductance. Therefore, to achieve a higher inductance104for the purpose of establishing a better inductive link, stentenna (Fig. 6.0.2)have been proposed [82] which resemble the structure of a helical coil. Inthis work, we will experimentally compare the performance of monitoringsystems based on both conventional and stentenna.From the frequency of operation point of view, a recent study shows thatthe optimum frequency for power transmission through tissues using sten-tenna as an inductive receiver is in the range of 800 MHz to 1.5 GHz [17].This relatively high range of frequency can be attributed to the small dimen-sion of the stent [3]. From the standpoint of data transmission techniques,the up link which transfers sensory data back to the external reader can beestablished either using an active transmitter (e.g., oscillator) [9,14,58,59,70]or electromagnetic back-scattering approach in which a passive transmittersuch as relaxation oscillator [15,32] or a simple LC filter [12,73,83] are used.The active transmitters are relatively power hungry, e.g., more than two orderof magnitude higher in [58] than the backscattering-based counterpart [15].The higher required power can adversely impact the reliability of the teleme-try system.6.1 Experimental ResultsTo investigate the feasibility of backscattering-based telemonitoring approach,a proof-of-concept setup has been used. Fig. 6.1.1 shows the in-vitro exper-imental setup used for measurements. A 100 kHz square-wave clock sig-105nal drives a discreet quadruple bilateral analog switch (Texas Instrument-74HC4066N) which modulates the impedance seen by the stent throughopening and closing the switch across the stent (Fig. 6.0.1). To observe (re-trieve) the backscattered modulated sensory data a spectrum analyzer (An-ritsu MS2034A) has been used along with a directional coupler (Mini Circuits15542 ZFDC-SMA) that separates the received signal from the transmittedsignal. The experiments are performed in a RF enclosure (ETS-LindgrenTable Top Enclosure). Both conventional and stentenna are tested in freespace. The stentenna is also tested while covered by different thicknesses ofground beef to mimic different implant depth.106Figure 6.1.1: In-vitro measurement setup.All experiments are performed at 900 MHz. Fig. 6.1.2 shows the exper-imental backscattered power versus different load resistances. This resultsshow that having a telemonitoring system with lower power consumption canimprove the backscattering reflected power and hence the performance of thetelemonitoring system. In addition, Fig. 6.1.2 verifies that the efficiency oftransmission is independent of the transmitted power level of reader antennaas changing the transmitted power by 10 dB results in approximately 10 dBchange in the received backscattered power. For the rest of experiments, the107antenna is switched between short and 100 k⌦ which is close to the load seenby the stent (e.g., assuming that the telemonitoring system draws a currentof 10 µA from a harvested 1 V supply).0.1 1 10 100 1000−95−90−85−80−75−70−65Load resistance RL (kΩ)Backscattered power (dBm)  Pin=0.0 dBmPin=−10.0 dBmFigure 6.1.2: Measured backscattered power level versus different load valuesand input powers.As shown in Fig. 6.1.3, for a transmission power of 100 µW, the sten-tenna provides better performance as compared to conventional stent fortypical distances between the reader and the stent. This experiment hasbeen performed in air (free space).To analyze the radiation pattern of the stentenna, the backscatteredpower level of the stentenna are measured in two directions (vertical and1081 2 3 4 5 6102030405060Distance (cm)Recieved backscattered power (nW)  Antenna stentConventional stentPTX=100 µWFigure 6.1.3: Backscattered power of stentenna compered to conventionalstent.horizontal directions relative to the stent) as shown in Fig. 6.1.4. The ex-perimental results reveal that the external reader should be positioned abovethe stent in order to achieve a better transmission efficiency.1090 1 2 3 4 5 6−100−90−80−70−60−50Distance (cm)Backscattered power (dBm)  VerticalHorizontalFigure 6.1.4: The Measured backscattered power from stentenna alongvertical and horizontal axes.Figure 6.1.5: The measured normalized backscattered power received fromthe stentenna versus tissue thickness.110Figure 6.1.6: Measured backscattered power with/without layers of groundbeef.Figure. 6.1.5 illustrates the normalized received backscattered power as afunction of implant depths. To calculate the normalized power, the measuredreceived backscattered power of the stentenna in the presence of a layer ofground beef between the stent and the reader antenna is divided by thereceived backscattered power measured for the same geometry without theground beef layer. Fig. 6.1.6 shows the results of the aforementioned twoexperiments (with and without a layer of ground beef). For the experimentwith no layer of ground beef the distance between the antenna and the stentis given on the right axis.111Chapter 7Conclusion7.1 Research ContributionsThe focus of this work is on the design of ultra-low-power telemonitoringsystems that can be powered wirelessly. Such systems are demanded inmany biomedical applications including telemonitoring of restenosis. Sincethis work uses an inductive stent, namely, stentenna, a comprehensive in-vitro simulations and measurements are performed to obtain the optimumfrequency of operation. As discussed in Chapter 2, the results of these ex-periments show that the optimum range of frequency for this particular ap-plication is between 0.5 GHz to 2.5 GHz [17]. In addition, the maximumdeliverable power is estimated (by measurement) to be 56 µW at 800 MHzfor implanted stent with the depth of 39 mm. Having an estimation ofthe power budget for the telemonitoring system, two different systems are112designed and implemented in a 0.13 µm CMOS process. The first systemwhich uses a simple capacitance-to-frequency converter (CFC) unit, benefitsfrom its simple design and alignment feature. The intention behind design-ing an alignment system (which is unique to this work) is to improve theinductive coupling between external antenna and implanted antenna (in thiscase stentenna). This design start monitoring the blood pressure with thesupply voltage of 0.88 V and power consumption of 156.9 µW. This systemtransmits the sensory data at 2.03 GHz, while offering ⇠555 kHz/1fF. Thepower consumption of the first prototype is higher than the second prototype,however it consumes half of the most power efficient state-of-the-art designfor similar application ( [13] has better power consumption performance thanthe first design however is for a different application). The focus of secondarchitecture, is on further reduction of power consumption and improvingadaptability of this system to different capacitive sensors. Experimental re-sults show that the second architecture offers 2.7 mmHg resolution at 1.0 Vsupply voltage while consuming only 11 µW power, which is more than 12times less than the first system. Having ultra-low-power design in mind,the configuration of the second system is based on capacitance-to-voltageconverter (CVC) architecture and low head-room analog and digital blocks,which allows operation of this system for rectified supply voltages as low as350 mV. The total power consumption of system in such low supply volt-age is measured to be only 35 nW. This is almost 4000 times lower thanfirst design and 65 time lower than state-of-the-art design [13]. In addition113to design of above-mentioned systems, telemonitoring using stentenna basedon backscattering phenomena is also studied and experienced. As shown inChapter 6, a preliminary in-vitro measurements are performed for both con-ventional and stentenna. To mimic the real environment of the stent, thestent is covered with different thicknesses of ground beef. As expected, thestentenna provides more efficient link in compare to the conventional stentthanks to its inductive characteristics. The measured results confirm the fea-sibility of the backscattering technique for telemonitoring of restenosis usingsmart stents. This study also shows that the backscarttered data can be ob-served from stentenna which is implanted as deep as 50 mm inside patient’sbody. Table 7.1 summarize the performance of the designs proposed in thiswork.Table 7.1: The summary of performance of the proposed systems in this workFirst system (CFC) Second system (CVC)Area (mm2) 0.484 0.381Power consumption 156.9 µW 35 nW-11µWSensitivity (kH/fF) 555 3.1-55Resolution (mmHg) 1.65 2.7-50Maximum Depth of operation (mm) 30 60RF sensitivity (dBm) -13.18 43.76Supply Voltage 0.87 0.351147.1.1 Design and implementation of auxiliary systemsand circuit blocksIn addition to above-mentioned systems and architectures, we have also de-signed and implemented auxiliary circuits to facilitate development and testof the proposed ultra-low-power systems. The ultra wide-band unity-gainanalog buffer presented in Chapter 4is one example of such designs. Moredetails on designs and performance achievements of these blocks are availableon Appendix A to Appendix C. The experimental results confirm the wide-band performance of the buffer. The bandwidth of this buffer is measuredto be 2.0 GHz while it consumes 7.34 mW from a 1.3-V supply. This designis fully monolithic and can be used in variety of applications, in particular,for testing high-frequency and low-power circuits.To monitor the current in the telemonitoring system and manage thepower consumption a proof-of-concept none-invasive and passive ac currentprobe is also designed and fabricated [84]. This architecture operates basedon electromotive force (emf) phenomenon and is capable of sensing a varyingcurrent over a wide range of frequencies. Simulation and measurement resultsof a proof-of-concept prototype implemented in a 0.13-mm CMOS confirm theperformance of the presented technique for currents with frequencies up to 8GHz. Note that in our experimental results, the high-frequency performancelimit is due to the measurement setup. Furthermore, the presented methodcan be used to sense currents over a wide range of amplitudes and the ampli-115tude detection sensitivity of the technique improves as the frequency of thecurrent signal which is being measured increases.7.2 Future WorksAs the main objective of this work is to monitor the blood pressure throughlive tissues, conducting in-vivo tests are envisioned as a major future goal. Toachieve that, The presented systems has to be embedded on a clinical versionof stentenna and implanted inside live animal test subjects. In such design,the effects of biocompatible coating on the performance of the overall systemneeds to be studied. In the final design, the electronic system requires to haveaccess to both sides of the stentenna as well as the middle part (serves asnatural reference node) and the capacitive sensor. Reliable implementationof these connection is also a subject of future work.In addition, some minor design modifications are also envisioned to im-prove the performance of the circuits. As discussed in Chapter 5, the pro-posed telemonitoring system is able to operate from both a low (0.35 V) totypically (1.0 V) supply voltage. One way to further improve the efficiencyof the circuit is to utilize a rectifier block that has optimal efficiency for twodifferent input signal amplitudes. An example of such a rectifier is presentedin [74]. Another possible improvement to the design is to replace the simpleclock generator used in this work with a differential clock generator that hasa fixed tail current. Designing the clock generator circuit in this way leads116to chip area saving because smaller transistors are required. Finally the am-plifier A in CVC design can be replaced by an amplifier with a negativefeedback configuration. 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Wheeler, “Formulas for the skin effect,” in Proceedings of the IRE, Sept.1942.133Appendix AA Monolithic Capacitor-lessWide-Band LDO VoltageRegulator in 0.13-mm CMOSLow drop out voltage regulators are common block in many applicationsthat are based on energy harvesting. At the beginning of our research westart improving the basic building blocks of our proposed telemonitoring sys-tem. As one of the important building blocks of any power conversion chain(PCC), we first reviewed and modified the conventional LDO regulator ar-chitecture to make it more suitable for our application (we also improved therectifier’s architecture). The main concern in our application is attenuationof the high frequency ripples that are generated by the RF to DC converterwhich requires increasing the bandwidth of the currently used LDO voltage134regulators. Another important concern is the size of the pass transistor andtransient time of regulation. The following two appendices present alterna-tive solutions that can reduce the power consumption, active area and recov-ery/settling time of the conventional regulators with no or little overhead.In this appendix, an ultra wide-bandwidth LDO regulator is presented thatis capable of rejecting high frequency ripples from the unregulated voltagesource and provide a supply voltage with much less noise and fluctuations forsensitive analog and mixed-signal circuits. We believe that the advantagesof such regulator architectures are not limited to this particular applicationand can be adopted by other designs and/or applications.A.1 IntroductionDue to their high power efficiency and simple design, low-dropout (LDO)voltage regulators have become popular in many applications including portabledevices, biomedical implants, and power harvesting structures [85]. In mono-lithic solutions, the power consumption and silicon area of the regulators areof critical importance. Several studies have focused on decreasing the powerconsumption of LDO regulators [6, 86, 87]. Although these studied presentelegant solution to achieve lower power LDOs, in most of them transient re-sponse and accuracy of the regulator have been compromised. Furthermore,to decrease the regulator area, different regulation techniques and architec-tures have been proposed [87–89]. Some of these approaches aim at eliminat-135ing the large output capacitors leading to capacitor-free regulators [90, 91]which in turn result in a smaller chip area. These regulators are typicallymore suitable in regulating low frequency ripples (either from the input volt-age or the output load). However, in many applications, such ripples occurat higher frequencies [92–94].Figure A.1.1: A generic block diagram of an LDO voltage regulator.A generic block diagram of an LDO regulator is shown in Fig. A.1.1. Inhighly integrated systems such as system-on-chip (SoC) designs the load cur-rent will have fluctuations with the clock edges which in turn appear as noiseon the power supply. To eliminate the impact of such high-frequency dis-turbances a wide-bandwidth regulator is needed. In such cases, it is desiredthat the open-loop unity-gain frequency (UGF) of the error amplifier (EA)in the regulator be higher than the highest fundamental frequency of the rip-136ples. Typically, regulator structures that have high-frequency ripple rejectionconsume relatively high power and thus are not suitable for low-power andportable applications [52, 86]. To minimize the effect of such noise on thesensitive analog circuits, designers usually provide additional clean analogsupply voltage, which results in extra wiring and area to accommodate theadditional supplies. These noises, however, can be attenuated using a highUGF regulator.In this design an ultra-wide-bandwidth regulator is presented which isintended for ultra-low-power systems. The design utilizes the compound er-ror amplifier presented in [6]. The proposed regulator offers fast transientresponse, high power-supply rejection (PSR), even at high frequencies, alongwith a low power consumption and a small area. Section A.2 provides abrief analysis of the key performance parameters of regulators. Section A.3presents the proposed regulator structure. Simulation and measurement re-sults are presented in Section A.4 and concluding remarks are provided inSection A.6.A.2 LDO Regulator AnalysisKey performance parameters of an LDO regulator, namely, line regulation,load regulation, settling time, and stability are all affected by the perfor-mance of the the error amplifier. Here, after a brief formulation of theseperformance parameters, analysis and design of the proposed LDO structure137will be presented.A.2.1 Load regulation and line regulationLoad regulation is defined as the ratio of the regulated output voltage change,Vout, to the output load (current) change, Iout, i.e., Vout/Iout. Accord-ing to Fig. A.1.1, the small-signal change in the output current change canbe written as:Iout(!) = ✓✓ R2R2 + R1◆·Vout(j!)◆ · A(!) · gm(!) (A.2.1)where A(!) is the voltage gain transfer function of the error amplifier andgm(!) represents the transconductance of the pass transistor at the angularfrequency !. By rearranging (A.2.1), the following equation for load regula-tion can be obtained:VoutIout (!) = 1A(!) · gm(!) · ✓R2 + R1R2 ◆ (A.2.2)Based on (A.2.2), to minimize output variations caused by the load fluc-tuations with fundamental frequency of !0, A(!0) has to be maximized1.Therefore, to attenuate high-frequency voltage fluctuations a relatively highbandwidth regulator would be needed which can provide a sufficient open-loop voltage gain at the frequency of fluctuations.1Increasing gm increases the settling time of the regulator and is not a feasible option[95].138Line regulation is a measure of the ability of the regulator to maintain itsregulated output voltage level in the presence of variations in the input volt-age level. It is defined as Vout/Vin, where Vout and Vin are changes inthe output and input voltages, respectively. Based on [95], the line regulationcan be calculated as:VoutVin (!) ⇠= Req(R1+R2)rds+ReqR1 + R2 + G(!) · R2 · Req (A.2.3)where, G(!) = A(!) · gm(!) is the open-loop gain, rds is the small-signalequivalent resistance seen between the drain and source of the pass transis-tor, RL is the load resistance, and Req = (R1 + R2)||RL. As expected, lineregulation at any given frequency (e.g., at !0) can be improved by increas-ing the voltage gain of the error amplifier at that frequency (e.g., A(!0)).Since typically the low-frequency changes in the input voltage have largeramplitude, to have appropriate regulation, large low-frequency gain for erroramplifier is desired. Serving both open-loop high DC gain and high band-width is one the main reasons that make use of proposed regulator beneficiaryin RF applications.A.2.2 Settling timeThe settling time (also referred to as the recovery time) is the time that ittakes for the output of the regulator to settle within a given percentage of theregulated output value, when a step change has occurred in the load current.139The settling time is a function of the closed-loop bandwidth of the regulatorand thus it depends on the open-loop bandwidth of the error amplifier. Italso a function of driving capability of error amplifier and pass transistor [96].To illustrate the settling time dependence to the performance of the erroramplifier, following example is served. Fig. A.2.1 shows the settling times oftwo conventional LDO regulators, with two different error amplifiers. The“slow” regulator has an error amplifier with a bandwidth of 6.26 MHz andunity gain frequency of 100 MHz, while the faster regulator uses an erroramplifier with a bandwidth of 51 MHz and unity gain frequency of 1.0 GHz.Both regulators have the same open-loop DC gain of 43.65 dB in the presenceof the maximum load. The settling time of these two regulators has beensimulated for two different load current transitions of 1 ns and 500 ns 2. Aswill be explained shortly, the results in Fig.A.2.1 show that the settling timewill increase for faster output load transitions.2In the 0.13 µm CMOS technology.1400.95 1 1.05 1.1 1.15 1.2 1.25x 10−50.750.80.850.90.9511.051.11.15time (sec)regulated voltage (V)  fast regulatorslow regulator∆ tst1∆ tst2∆ tst1Load transition time= 500 ns∆ tst2(a)1.25 1.3 1.35 1.4 1.45 1.5x 10− (sec)regulated voltage (V)  fast regulatorslow regulator∆ tst2∆ tst1∆ tst1∆ tst2Load transition time= 1 ns(b)Figure A.2.1: Settling time of two conventional LDO regulators with unity-gain frequencies of 1 GHz (solid line) and 100 MHz (dashed line), for (a)500 ns (b) 1 ns load current transitions. The fast regulator has less outputchange for the same load transition speed. Also, it can be seen that for aslower load transition time, the output change (vout) is less severe for thefaster regulator.141The response time of an LDO regulator (shown in Fig.A.1.1) can bewritten as [96]:tsettling ⇠= 1BWcl +tslew1 +tslew2⇠=1UGFol + CparvEAIslew1 + CoutvoutIslew2 (A.2.4)where BWcl and UGFol are the closed-loop bandwidth and open-loop unity-gain frequency of system, respectively. tslew1 and tslew2 represent thecomponents of the settling time due to slewing of the error amplifier andpass transistor, respectively. tslew1 and tslew2 can be written as a functionof Islew1 and Islew2, which are the slew current of error amplifier and passtransistor, respectively. Cpar is the parasitic capacitance of the gate of thepass transistor and Cout is the total capacitance seen at the output node of theregulator. In (A.2.4), vEA = ( R2R1+R2 ) ·A ·vout is the voltage change at theoutput of the error amplifier, where A is the gain of the error amplifier andvout is the voltage change at the output of the regulator, when regulator’sload changes from its full-load to full load. From (A.2.4) it can be seenthat the settling time is related to four main factors: regulator closed-loopbandwidth, vout, capacitance Cpar and Cout, and finally the the drivingcapability of error amplifier and pass transistor.By optimizing the maximum load capability of the regulator for ultra lowpower applications, it is possible to decrease Cpar of the pass transistor and142Cout of the output node remarkably. But in order to further decrease therecovery time, suitable for agile applications, it is necessary to decrease theoutput variations caused by either load or line fluctuations. As it is discussedearlier, decreasing the output variations is only possible by increasing thegain of the error amplifier 3. In this design, the main goal is to increasethe bandwidth of the error amplifier, which, as mentioned earlier, has moreimpacts on the performance of the regulator.A.3 The Proposed LDO ArchitectureThis architecture combines two amplifiers, an opamp and an operationaltransconductance amplifier (OTA) to achieve both high low-frequency gainand high UGF. In the next section the challenges with using conventionalerror amplifier in fulfilling the requirements discussed A.2and proposed onepossible solution using compound error amplifier first introduced in [6].A.3.1 Challenges with the conventional error amplifierNote that one can argue that these ripples can be filtered out using a passivefilter, thus there is no need for such wide-band regulator. Since the equivalentresistance seen from output node of the regulator is normally small (on theorder of ohms to few kilo ohms), to have feasible RC filter, depending onmaximum load of the regulator, a large capacitance at the output is needed3Increasing the open-loop gain of regulator by means of pass transistor is not applicablesince minimum parasitic capacitance on the pass transistor’s gate is desirable.143(e.g., 0.01 to 1 µF ). Consequently, as it will be explained in detail in thefollowing sections, large capacitance at the output of regulator will slow downthe recovery time in load regulation. As mentioned earlier, to filter high-frequency ripples, the UGF of the regulator has to be beyond the fundamentalfrequency of the ripple. This in turn requires a high-UGF error amplifier. Onthe other hand, to improve the precision and speed of the regulator, the low-frequency gain of the EA has to be large. Since there is a trade-off betweenlow-frequency gain and UGF of an amplifier, we are using the architecturefirst introduced in [6]. This architecture combines two amplifiers, an opampand an operational transconductance amplifier (OTA) to achieve both highlow-frequency gain and high UGF.Having a low power design in mind, we use a single-stage error amplifier toalso minimize the parasitic capacitances that result in poles. Based on BISIMmodel ver. 4 [97] for transistors, in saturation region gds = ID where  isthe channel-length modulation parameter. Since in the this case increasinggm will be possible only by increasing source drain current ID 4, the small-signal output resistance rds = 1/gds of output stage transistors will decreaseas well as Rout. Therefore, by increasing gm of a single stage amplifier, theDC gain would converge to some certain value. This maximum gain in 0.13-µm CMOS technology assuming reasonable size and power consumption isabout 30 dB.With a simple single stage OTA amplifier, the dominant pole is at the4Note that the over-drive voltage is fixed by DC operational points144output node and equals pout = 1/ (CoutRout), where Cout and Rout are capac-itance and resistance seen at the output of the amplifier. Assuming a phasemargin larger than 45o (and assuming no zeros before UGF), The unity gainfrequency would be equal to gain bandwidth product of the amplifier:1CoutRout · gmRout = gmCout . (A.3.1)where gm is the small-signal transconductance of input stage transistor (e.g.M1 or M2 in Fig. A.3.3). Based on (A.3.1), to increase UGF, gm has tobe increased. With a feasible amount of gm a very high UGF is achievable.The voltage gain is a product of transconductance and Rout where, Rout =rdsn||rdsp , and rdsn and rdsp are the small signal output resistance of nMOSand pMOS transistors at the output of presumed single stage amplifier. Onecan say by increasing gm the DC gain as well as unity gain frequency shouldimprove. This is not the case, Since gm is inversely related to rdsn and rdspand therefore Rout.145Figure A.3.1: Small signal transconductance of a nMOS in 0.13 µm processversus drain-source current. In this simulation the drain-source voltage keptconstant and the overdrive voltage is swept.A.3.2 Analytical backgroundIn this section the effect of paralleling of two systems is analyzed. As ex-plained in [6], let us assume the amplifiers, S1 and S2, are linear and theirtransfer functions are:S1 = G111 + s/p1 , S2 = G2 11 + s/p2 . (A.3.2)146where G1 and G2 are DC gain, p1, p2 are system’s poles. In a practicalscenario, similar to that used in the proposed LDO, G2⇥ p2o G1⇥ p1 andG1 o G2 and p2 o p1. The parallel combination of the two systems hasthe following transfer function:S3 = (G1 + G2)1 + sz1(1 + sp1 )(1 + sp2 ) . (A.3.3)where z1 =p1p2(G1+G2)p1G1+p2G2 . By simplifying (A.3.3) using the above mentionedassumptions, we have:S3⇠= G11 + sez1(1 + sp1 )(1 + sp2 ) . (A.3.4)where ez1 = p1G1/G2. The introduced zero, ez1 is located at the frequencywhere the gain of the two systems are equal. Fig.A.3.2 shows an examplegain and phase response of each system and those of the combined of theoverall parallel system. In general, S3 benefits from both high DC gain andhigh bandwidth characteristics. In this work, we use a similar concept andfurther modify the structure to achieve ultra-high frequency ripple rejection,fast settling time, and high power supply rejection up to ⇠1 GHz.147Figure A.3.2: Sample Bode plots of two first-order systems S1, S2 andtheir parallel combination S3, calculated in Matlab. In this example, G1 =60 dB, G2 = 20 dB, p1 = 10 rad/s and p2 = 100 k rad/s.A.3.3 EA structureThe structure of the error amplifier is shown in Fig. A.3.3. It consist of asimple single-stage OTA combined with an opamp to provide the high UGFand high DC gain for the EA.To elaborate the relation between OTA and Opamp amplifiers, assumea vIN change in the positive input of error amplifier. This excitation willproduce the change in current iD as shown in Fig. A.3.3 which is equal toiD = iOTAD + iOpampD , in which iOTAD is the current produced by OTA148and iOpampD is the current generated by Opamp. From our small-signalknowledge we know that iOTAD = gmn · vIN and iOpampD = A1 · A2 · A3 ·(1/rOpampout ) ·vIN , where gmn is the small-signal transconductance of the inputstage nMOS transistors (M1 or M2 shown in Fig.A.3.3), A1, A2, A3 are thevoltage gain of the first, second and third stage of the Opamp presentedin Fig. A.3.5, and rOpampout is the equivalent small-signal output resistance ofthe Opamp. Knowing that the small-signal output voltage of the compoundamplifier is given by:vout = iD · ✓gmp3gmp4◆ · rOTAout (A.3.5)Figure A.3.3: Compound error amplifier structure similar to that of [6] whichconsists of an OTA and an opamp and is used in the proposed LDO regulator.149where rOTAout is the small-signal output resistance of OTA and gmp3, gmp4are the small-signal transconductance of pMOS transistors (M3 and M4 inFig. A.3.3). By simplifying above equations: It can be shown that the voltagegain of the compound amplifier can be calculated as:AV = voutvin = AOTAV + AOpampV · ✓ rOTAoutrOpampout ◆ . (A.3.6)In (A.3.6), AOTA and AOpamp are the voltage gain of the OTA and opamp,and rOTAout and rOpampout are the small-signal output resistance of the OTA andopamp, respectively. In addition, (A.3.6)confirms that the presented am-plifier (also can be seen in [6]) is the parallel of high DC gain Opamp andultra high band width OTA amplifiers. Simulation and measurement resultsshown in followed by Section support this argument.A.3.4 StabilitySince the output impedance of LDO regulator with a common-source passtransistor is large (Fig. A.1.1), the overall output impedance of such regu-lators is approximately equal to the load impedance. Assuming a constantload capacitance, variations of the load resistance results in variations of theoutput pole over a wide range of frequency. This is one of the reasons thatmakes the design of stable regulators challenging.The open-loop small- signal output resistance of the regulator can be cal-culated as Rout = RL|| (rpassds || (R1 + R2)) ⇡ RL. Assuming a constant output150capacitance Cout, the output pole of the regulator (which is usually the dom-inant pole) is given by pout = 1/Cout·Rout ⇠= 1/Cout·RL. Since the output pole is afunction of RL, extreme changes of the output load leads to wide frequencyvariations of pout. This is one the challenges in designing such regulators. Ifthe designer doesn’t set this pole as a dominant pole of the regulator, phasemargin of the regulator can drop to negative values (in no-load condition)and brings the regulator to an unstable state. The conventional method toensure that the stability of the regulator is to add a large capacitor (in theorder of few µF ) to the output node of the regulator. This capacitor is typi-cally an off-chip capacitor and it is added to make sure that even in the worsecase (full-load) the output pole remains dominant. In this work, to avoid theuse of such a large capacitor (having a monolithic design in mind), the out-put capacitance is minimized and ensured that the output pole will remainthe third dominant pole of the system. To achieve a high phase margin anextra zero is also added by adding a capacitor in series with a resistor in par-allel with the output of EA (or equivalently the gate of the pass transistor).Since this zero has to be at a frequency lower than the open-loop UGF ofthe regulator, a higher UGF leads to an smaller capacitor.Pole-zero locations in proposed LDOFig. A.3.4 presents a simplified bode diagram of the proposed system. Thedominant pole is introduced by the opamp amplifier described in the abovesection. At fz1 = 1/2⇡ · AOpampV ·p1/AOTAV a zero from paralleling two system is151introduced (as described before as ez1) which increases the phase margin andbandwidth of the regulator.Figure A.3.4: Pole/zero locations of the open-loop voltage gain of the pro-posed LDO regulatorThe next pole belongs to OTA; This is the dominate pole of OTA andsince the OTA is designed to have a phase margin of more than 70, thesecond dominate pole of it would be far enough. Therefore, in this stabilitystudies, we do not need to consider the effect of the second pole of the OTAwhich would be the fourth pole of the overall regulator. In order to maintainthe phase margin of the regulator above 45, the changes of the output poledue to the change in loads should be taken into account . For this reason, anESR zero has been inserted at zESR frequency. This will insure that, even inno-load condition, where the output pole frequency (the last pole shown inFig. A.1.1) is behind the UGF of the regulator, the overall phase margin ofthe regulator will stay above 45.152The third pole of the overall regulator belongs to the output node, namelypout .A.3.5 Opamp schematicSeveral high DC gain opamp has been reported in the articles which most ofthem has cascoded and complex architectures. To maximize the power supplyrejection ratio and to obtain the required DC gain with minimum voltageheadroom, the schematic shown in Fig. A.3.5 is used for the opamp. In thisarchitecture, to benefit from the high DC gain at a low voltage headroom, anstructure called “composite cascode” is utilized in Widlar opamp architecture[98]. We have modified the structure of [98] by self-biasing of M8, i.e., theDC voltage level of M7,8 are generated by using a diode-connected M8.153Figure A.3.5: Schematics of the opamp used in the error amplifierTable A.1: Dimensions of transistors in the architecture shown in Fig. A.3.5Transistor Width (µm) Length(µm)M1,M2 2 0.5M3,M4 20 0.5M5,M6,M8,M11 1 2M7,M8 0.5 2M12,M14,M16 0.2 1M13,M15,M17 2 1M9 0.5 5M10 0.3 5A.3.6 Band-gap circuitTo stabilize the output voltage of the regulator to a designated value andalso to have a built-in biasing circuitry, a band-gap circuit has been designed154along with the Regulator. The schematics of band-gap circuit is shown in Fig.A.3.6 and the transistor dimensions are presented in Table A.2. Accordingto the simulation the band-gap circuit can generate 550 mV reference voltagefor the regulator for the minimum power supply of 700 mV.Figure A.3.6: Band-Gap Reference voltage and bias circuit155Table A.2: Transistor Dimensions of Band-gap CircuitTransistor Width (µm) Length (µm)M1,M2 1 1M3 10 1M4,M11 5 1M5 2 1M6 20 1MM7 1 4M8 1.9 3M9 2 4M10 12 1M12,...,M16 0.5 5M17,M18,M19 0.3 0.12A.4 Experimental and Simulation ResultsThe presented LDO is designed and fabricated in 0.13-µm CMOS. The chipmicrograph is shown in Fig. A.4.1. The chip area is 0.096 mm2, excludingthe test pads, which includes two copies of the regulator (one with a low-passfilter for open-loop testability). The regulator occupies 0.00405 mm2. Unlessotherwise stated, in all measurements VIN = 1.2 V and Ifullload = 500 µA.156Figure A.4.1: Micrograph of the test chip which includes an open-loop LDO(LDO 1), a close-loop LDO (LDO 2), and some additional test blocks.A.4.1 DC measurementsThe total measured quiescent current of the regulator in no-load conditionis 44 µA. The distribution of the bias current to the error amplifier, refer-ence voltage circuit and feedback resistors are about, (36.023+6.729) µA,7.0996 µA and 10.977 µA respectively. The average DC output voltage gen-erated by internal reference voltage, in no-load and full-load conditions are1571.03 V and 1.000 V. The measured DC (steady-state) line regulation for twocases of full load and no load are shown in Fig. A.4.2. The measured line regu-lations in no-load and full-load conditions are 70 mV/0.4 V and 35 mV/0.4 V,respectively. These measurements a performed using HP 4155A semiconduc-tor parameter analyzer.0.4 0.6 0.8 1 1.2 1.4 1.600. voltage Vin (V)Regulated voltage (V)  0 A100 µA500 µAFigure A.4.2: Measured DC line regulation in no-/full-load conditions.1580 0.2 0.4 0.6 0.8 10.80.850.90.9511.05Regulated voltage (V)  0 0.2 0.4 0.6 0.8 140455055Load current (mA)I Q (µA)  MeasuredSimulatedFigure A.4.3: Measured and simulated DC load regulation and quiescentcurrent of LDO regulator with built-in reference generator.A.4.2 Transient measurementsThe turn-on 2% settling time is measured using both internal and externalreference voltage in no-load condition (worse case); The values are 2.7 µs and2 µs, respectively.In this experiment to eliminate the impact of the built-in reference volt-age, an external reference voltage has been applied.As shown in Fig. A.4.4, turn-on settling time for the regulator with built-in voltage band-gap circuit is measured to be 2.7 µs, and the turn-on settlingtime with applied external reference voltage measured to be 2 µs.159Figure A.4.4: Measured turn-on settling time w/o external reference voltageFigure A.4.5: Regulated ac-coupled output voltage of the regulator forVIN = 1.27 + (0.55)⇥ sin((2⇡)38MHz).1600 100 200 300 400 500 6000.80.850.90.9511.05time(ns)Regulated voltage (V) 2%150 ns(a)0 100 200 300 400 500 6000.920.940.960.9811. voltage (V)2%160 ns(b)Figure A.4.6: Measured transient load regulation for: (a) full load to no-load(b) no-load to full-load transitions with CL = 0.7 pF.1611k 10k 100k 1M 10M 100M 1G02040Gain(dB)  1k 10k 100k 1M 10M 100M 1G−150−100−50050100Frequency (Hz)Phase (deg) No load @ 0.5 pFFull load @ 0.5 pFFull load @ 10pFEffect of LP filterEffect of LP filterPM of 47° to 40° UGF of 0.7 to 1 GHzUGF 70 MHzPM 81° Zero introduced by compound amplifer (a)1k 10k 100k 1M 10M 100M0204060Gain (dB)1k 10k 100k 1M 10M 100M−100−50050100150Frequency (Hz)Phase (deg)Opamp’s dominantpole Effect ofLP filterEffect ofLP filter~60 MHz of UGF @ 500µA~80° PM Zero intruduced by compound amplifier Zero introduced by compound amplifier(b)Figure A.4.7: (a) Simulated open-loop gain and phase responses for full load(500 µA) and no load (10 µA) with CL=0.5 pF. (b) Measured gain and phaseresponses for full load (500 µA) and CL ⇠=10 pF.162A.5 AC ResponseTo measure the open-loop frequency response, special attention has to bepaid that all blocks inside the regulator are biased properly. One possibleapproach is to add a low-pass filter (LPF) in series with the positive inputof the error amplifier. In this way, the regulator can obtain its DC operatingpoint (since for low frequencies including DC the low pass filter act as a shortcircuit and the loop is closed) and at the same time we can measure the open-loop frequency response for frequencies higher than the LPF cut-off frequency(since the loop is practically open at frequencies much higher than the LPFcut-off frequency). Fig. A.4.7 (a) shows the simulated frequency responseof the open-loop regulator. As confirmed by these results, the frequencyresponse of the open-loop regulator has a DC gain of about 41 dB for no-loadand 34 dB for full-load condition, while the open-loop unity gain frequencyis 0.73 GHz for no-load and 1.00 GHz for full-load condition. Note that formeasurement results we have to use an interface to derive the 50 ⌦ inputimpedance of the vector network analyzer (Agilent E5061B) and connectthe output of the regulator (which can drive maximum of 2 k⌦ at 1.0 V)to the measurement device. This extra interface circuit adds about 10 pFload capacitance to the output node of the regulator. Due to this extracapacitive load the measured unity gain frequency of the regulator is reducedto ⇠60 MHz while it still shows the existence of the zero introduced bythe compound error amplifier and the corresponding stability improvement.163As mentioned earlier, this regulator is designed for ultra low power agileapplications with the maximum expected capacitive load of 500 fF.100 1k 10k 100k 1M 10M 100M 1G−50−40−30−20−100Frequency (Hz)PSR (dB)  60 Hz−12.62 @ 1MHz−21.3 @ 1GHz−27.1 @ 100 MHzFigure A.5.1: Measured PSR of the proposed regulator under full load(500µA).Experimental results for PSR and load regulation are shown in Figs. A.5.1and A.4.6 respectively. To implement fast load transitions, an externalCMOS low-voltage RF SPST switch (ADG751) with ton ⇠= 9 ns, is usedand is driven by a voltage source with rising and falling time of 1.6 ns. ThePCB with the switch circuit adds ⇠ 0.7 pF to the output of regulator. Mea-sured results show that the settling time of the proposed regulator to reach to98% of its final value is 160 ns in worse case (full load to no load transition)which is in agreement with simulation results. Note that a portion of theoutput’s ripple during load transition is caused by the SPST switch.Table A.3 presents the performance summary of the LDO and compares164it with state-of-the-art LDOs.A.6 Concluding RemarksAn ultra-wide-bandwidth LDO regulator designed for low-power agile appli-cations is presented. Experimental results verify the high-frequency regula-tion capability of the presented regulator along with its fast recovery timefor load and line regulations. Its ultra-low-power and small area makes thisregulator suitable for portable devices and biomedical applications.165Table A.3: Performance summary and comparison with the state-of-the-art LDOs.[99] [100] [101] [6] [86] [102] This WorkYear 2013 2013 2010 2006 2010 2009 2013Technology (µm) 0.18 0.065 0.09 0.8 0.18 0.13 0.13Imax loadQ(µA) 40 0.9 33-145 300⇤ 35 50 44Area ⇤0.00405mm2 10.86 4.20 3.07 585.18 76.54 12.1 1Settling time (µs) 1.172 6  160 100  0.16ILoadmax(mA) 100 100 140 1380 150 2 0.5PSR (dB)  58 @ 10 kHz56 @ 10 MHz30 @ 30 MHz 64.3 @ 1 kHz67 @ 1 MHz56@ 10MHz50 @ 1 kHz, 12.6@ 1 MHz27 @ 100 MHz, 21.3 @ 1 GHzBandwidth 10 MHz    20 kHz  1.57 GHz @ full loadVout(mV )⇤⇤ 100 69 94 110 196 15 150Vdropout(mV ) 200 200 >150 300 541 200 80* Including digital unit for battery charger**from no-load to full-load166Appendix BA 0.13-µm CMOS Low-PowerCapacitor-less LDO RegulatorUsing Bulk-ModulationTechniqueIn this appendix, an alternative method for deceasing the dimensions of thebulky pass-transistors in low-drop-out voltage regulators are presented andanalyzed. The proposed technique can increase the current delivery of theregulator as well as the speed of load and line regulations. This technique canbe used in low-power applications such as biomedical applications and tele-monitoring. To demonstrate the enhancements achieved by this technique,we applied it to a conventional LDO structure and compare the performance167factors of the “enhanced”regulator with the conventional regulator withoutthis technique. In the following sections this technique is more elaboratedand verified by simulation and measurement results.B.1 IntroductionLow-drop-out (LDO) voltage regulators are commonly used in electronic sys-tems particularly in portable or low-power applications. Their main functionis to provide a stable supply voltage by minimizing (ideally eliminating) theripples and noises caused by imperfect power sources and/or variable loadcurrents. In portable devices and many biomedical implants the power con-sumption of the regulator as well as its recovery time are among the impor-tant design considerations. Furthermore, in applications that use a wirelesspower transfer scheme, e.g., radio-frequency (RF) power harvesting, the reg-ulator has to eliminate the high-frequency ripples caused by the first stage ofpower conversion chain (PCC). Typically, low-complexity integrated LDOshave a relatively slow recovery time [103–107]. Therefore, extensive studieshave been and are being pursued to improve the recovery time, as well as loadand line regulation performance of integrated LDOs [103,108–112] . In manyof such designs the improvement in recovery time is achieved by employingadditional and often fairly complex circuitry [110–112] which in turn resultsin higher power consumption and/or larger chip area.168MPassVINVoutEAVrefCLLoadFeedback circuitReference and biasing circuitRLFigure B.1.1: Block diagram of a generic LDO voltage regulator.Fig. B.1.1 illustrates the generic configuration of a conventional LDOvoltage regulator. As shown in the figure, the system consists of an erroramplifier (EA), a reference voltage generator, a feedback circuit and a passelement (i.e., pass transistor). Based on the structure of the pass element,two different LDO categories are recognized: common-drain (CD) structurewhich uses an n-type pass element and common-source (CS) structure whichutilizes a p-type pass element. For a CD LDO regulator, it is desirable touse a low-threshold pass transistor. Using a low-threshold device will alsohave an impact on the fabrication cost, therefore, this type of regulator istypically not suitable for low-cost applications. On the other hand, using aCS pass element may introduce stability issues and thus typically requiresa large external capacitor [86, 108]. To ameliorate this issue particularlyin fully integrated designs, capacitor-free monolithic regulators have been169M2M5M1M3VrefM4Rb2Rb1VCVOTAVBM15M13M12M14M11M10M9M8 VCVBVopampM19 M20M22M21M23VOTAVopampVrefM16CcRb3 R2R1Reference and biasing circuitMPassVINGate Error Amplifier (EA-a) Bulk Error Amplifier (EA-b)Regulated voltageVrefM18 M17M6 M7AFigure B.1.2: Schematic of the proposed LDO regulator. To facilitate testingVB is applied externally.proposed [87, 99, 103, 110]. Usually, these structures utilize left-half plane(LHP) zero which is introduced by the equivalent series resistance (ESR) ofthe output capacitor to stabilize the circuit without the need of using a verylarge external capacitor. However, one of the challenges of this compensationtechnique is that the effective ESR of a capacitor varies with load as well astemperature [105, 110, 113] and thus the frequency of the zero would changeaccordingly.In addition to using relatively large external capacitors, conventional LDOregulators usually use a large pass transistor which not only occupies a largechip area but also introduces a large parasitic capacitance as the load of theerror amplifier. This large load capacitance adversely affects the open-loop170bandwidth of the regulator.In this work, to address the above-mentioned issues, we present an alter-native simple technique that modulates the bulk voltage of the pass elementto enhance the performance of the LDO. The proposed structure improvesline and load regulations as well as the driving capability of the regulatorwhile it reduces the power consumption of the LDO as compared to con-ventional LDOs with similar performance. Furthermore, as compared toconventional approaches, the technique also improves the transition recoverytime for no-load to and from full-load conditions, thus, making it suitable forapplications where load conditions may change rapidly.B.2 The Proposed LDO StructureThe proposed technique takes advantage of body effect to reduce the thresh-old voltage of the pass transistor for any given current load. In this section,after a brief review of the body effect, we present and analyze the proposedLDO structure.The change of threshold voltage of a MOS transistor as a function ofits source to bulk voltage is referred to as “body effect”. For long-channeldevices, the threshold can be approximated by [80,97]:|Vth| = |Vth0| +  ⇣pVSB + 2|F |p2|F |⌘ (B.2.1)171where Vth is the threshold voltage of the device for VSB 6= 0, and Vth0 isthe nominal threshold voltage value for VSB = 0,  is the body-bias coefficientand 2|F | is the surface potential.0 0.2 0.4 0.6 0.8 1 1.200.511.522.5Vbulk (V)g mb (mS)Figure B.2.1: Simulated gmb versus different bulk-source voltages for a typicalpmos pass transistor with (W/L) = (50µm/0.12µm).Given that for pmos transistors  < 0, from (B.2.1), it can be seen thatby decreasing the bulk voltage in pmos transistors the absolute value of thethreshold voltage decreases. For a fixed VSG, this change in the thresholdvoltage will result in an increase in the drain-source current and vice versa.Since the effect of the bulk voltage on the drain-source current is similar tothat of the gate voltage, the body effect is sometimes referred to as “back-gate172effect” [80]. The small-signal bulk transconductance of a pmos transistor canbe derived as:gmb = @ID@VSB = 2⇣pVSB + 2|F |⌘ · gm (B.2.2)where gm is the small-signal transconductance of the device. Using (B.2.1)to replace |Vth| in (B.2.2), one can show that the bulk transconductance(gmb) has a maximum which is a function of VSB. Fig. B.2.1 shows gmb ofthe pmos pass transistor used in this work, as a function of Vbulk . Thissimulation result shows that gmb of a pmos transistor, with the aspect ratioof (W/L) = (50µm/0.12µm) when its source is connected to 1.2 V, reachesits maximum in the vicinity of Vbulk ⇠= 700 mV, or equivalently, VSB ⇠= 500mV. As it will be explained later, this is one of the reasons that the DCoperating point of the bulk error amplifier has been chosen to be 700 mV.Proposed configurationVoltage regulators that are used in low-power RF energy harvesting appli-cations are desired to have a bandwidth greater than the fundamental fre-quency of the ripples of the unregulated supply voltage (i.e., incident RFsignal). Furthermore, a relatively large open-loop DC voltage gain is neededto provide an accurate regulated output voltage. In this work, we presenta voltage regulator architecture that not only satisfies the above-mentioned173criteria but also improves the driving capability of the regulator.MPassVINVoutEA-aVrefCLLoadRLReference and biasing circuitR1R2EA-bVrefFeedbackFigure B.2.2: Block digram of the proposed LDO regulator.The block diagram of the proposed LDO regulator is shown in Fig.B.2.2.The bulk of the pass transistor is connected to the output of an extra erroramplifier, namely, “EA-b”. Since typically gmb is smaller than gm, to achievea higher open-loop DC gain the amplifier with a larger DC gain (i.e., EA-a) isconnected to the gate of the pass transistor while the amplifier with a higherbandwidth (i.e, EA-b) is connected to the bulk terminal. Therefore, the mainerror amplifier will provide the high DC gain for accurate regulation whilethe bulk amplifier provides agile response to the output changes. Fig.B.1.2illustrates the overall schematic of the presented LDO regulator. Detailedanalysis is provided in the next section.174B.3 The Proposed Bulk Modulation TechniqueIn this section, we present different attributes of the proposed bulk modu-lation technique and discuss different performance metrics of the regulator.More specifically, in the time domain, the recovery time of the regulator fordifferent types of line and load regulations are analyzed. Furthermore, thestability of the regulator for different resistive and capacitive loads is inves-tigated through a detailed pole-zero analysis in the frequency domain. Notethat all the presented simulation results are based on post-layout simulations.The results are later verified through measurements of a proof-of-concept pro-totype that includes two LDOs one with and the other without proposed bulkmodulation technique. The prototype is implemented in a 0.13 µm CMOStechnology.Here, we demonstrate the enhancements resulted from the proposed tech-nique by applying it to a conventional LDO regulator, however, one can applythe proposed technique to other LDO architectures as well.B.3.1 Driving capabilityAs will be discussed, one of the main benefits of modulating the bulk ofthe pass transistor is that for a given aspect ratio of the pass transistor,bulk modulation improves the output current delivery. On the same token,using bulk modulation one can achieve the same current delivery with asmaller pass transistor. To improve the current delivery for a given transistor1750.2 0.3 0.4 0.5 0.6 0.710−710−510−3100101102103VSB(V)I Bulk (µA)  127° C−30 ° C27 ° CVBulk=0.7 VFigure B.3.1: Ibulk vs. VSB for VS = Vin = 1.2 V and VG = 800 mV. The sizeof the pmos transistor is the same as the pass transistor used in presentedLDO regulator(50µm/120nm).overdrive voltage, we rely on the fact that one can reduce the thresholdvoltage of the pass transistor by applying a proper voltage (refer to B.2.1)to its bulk. To reduce the threshold voltage, the applied bulk voltage has tobe lower than the source voltage, i.e., VIN of the regulator. Fig. B.3.1 showsa generic plot of the bulk current of a pmos pass transistor (with an aspectratio of (W/L) = (50µm/0.12µm) used in this design) versus its source-bulk voltage VSB = VSVB. As shown, the source-bulk current will increasedrastically when the source-bulk voltage is increased. This is expected,since for positive values of VSB the source-bulk diode will be forward biasedand beyond some threshold voltage will fully turn on. Figure B.3.1 showsthat the bulk current of the pass transistor is negligible as compared to the176total quiescent current over an extended range of temperature, given thatthe overall quiescent current of the circuit is 99 µA. As expected the forwardbiased source-bulk diode drains more current at higher temperatures. Forbulk voltage of 0.7 V (VSB= 0.5 V) the source-bulk leakage current is lessat most around 1µA (at 127 C). Therefore, if the DC voltage of the bulkerror amplifier EA-b is around 0.7 V, the source-bulk diode does not conductexcessive amount of current. Note that we are interested to set the DCvoltage level of the pass transistor bulk as low as possible to maximize thedriving capability of the pass transistor. In this design, we set the DC outputvoltage of EA-b to 0.7 V when the common-mode DC voltage of its inputsare at Vref . As a result when the regulator is at steady state, the bulkvoltage of its pass transistor is at 0.7 V. We designed the EA-b amplifier andsized the transistors in such a way that the output DC voltage has minimumchanges due to process variations and mismatches. Based on the Monte Carlosimulation results (N=100), the DC voltage of EA-b amplifier has a meanvalue of 695.95 mV with the standard deviation of 77.0 mV.1770 0.2 0.4 0.6 0.8 1 1.20.511.522.5VbulkNormalized I SDFigure B.3.2: The simulated ISD versus Vbulk for pass transistor. Note thatthe value of the ISD is normalized for VBS = 0 or Vbulk = 1.2 V.Fig. B.3.2 shows the relation between the Vbulk and the normalized source-drain current of the pass pmos transistor (normalized to the source-drain cur-rent when VBS = 0), for a constant gate-source voltage of 400 mV. Accordingto this figure, the current delivery to the load can be improved by applyinga proper voltage to the bulk. Note that to avoid turning on the source-bulkdiode, the bulk voltage has to be larger than 700 mV (at 127 C) . By choos-ing Vbulk = 0.7 V the current delivery of pass transistor is twice as much asthe current delivery of the conventional structure where the Vbulk of the pmospass transistor is equal to its source voltage (i.e., VBS = 0 V). Therefore, byapplying Vbulk = 0.7 V, we can expect about %100 improvement in the cur-rent delivery of the regulator. Note that this simulation result is obtained178under a constant gate-source voltage, if the gate-source voltage changes, thisimprovement may reduce accordingly. This improvement is verified by bothsimulation and measurement results in the following section (Fig. B.4.1(a)).B.3.2 Transient behaviorThe load-regulation recovery time is an important performance metric ofLDO regulators, in particular, for regulators that are used for supplyingpower to digital or mixed-signal circuits with a high-activity blocks. Referringto Fig. B.2.2, it can be shown that for agile changes in the load current, therecovery time of the output voltage can be written as [111,114]trec t 1BWcl + tslew = 1BWcl + CparVAIslew (B.3.1)where BWcl is the close-loop bandwidth of the regulator and tslew is thetime delay due to the slewing of the error amplifier while driving the passtransistor. In (B.3.1), Cpar is the total parasitic capacitance seen at theoutput of the error amplifier (mainly dominated by the gate capacitance ofthe pass transistor) and VA and Islew are the output voltage change andmaximum slew current of the error amplifier. Furthermore, it can be shownthat the output voltage change due to such agile load current change is alsoa function of the recovery time [114].1797 7.05 7.1 7.15 7.20.9511.051.11.15  X: 7.02Y: 1.116X: 7.054Y: 1.024 X: 7.128Y: 1.024Regulated voltage (V)7 7.05 7.1 7.15 7.20.511.522.53time (us)Load current (mA)w/o bulk modulationwith bulk modulationEA−a correction and slewEA−b correction and slewtrec∆ vout= 0.12trec(a)1.95 2 2.05  X: 2.018Y: 0.9808Regulated voltage (V) X: 2.09Y: 0.98081.95 2 2.05 2.10.511.522.53time (us)Load current (mA)w/o bulk modulationwith bulk modulationEA−b correction and slewtrec∆ vout= 0.3∆ vout= 0.5trecEA−a correction and slew(b)Figure B.3.3: Recovery time analysis for LDO regulator with and withoutbulk modulation technique in (a) sudden plunge and (b) increase of the loadcurrent.180In a conventional regulator (Fig. B.2.2 excluding EA-b), when the loadcurrent suddenly drops, the output of EA-a will increase up to VIN to reducethe pass transistor current as much as required to regulate the output voltage.In the proposed technique, when bulk modulation is applied to the passtransistor, the “faster”error amplifier (EA-b) will sense the change and in-creases the bulk voltage of the pass transistor from its equilibrium voltage 1up to the maximum value of Vin. This will cause an increase of the thresholdvoltage of the pass transistor which further helps to reduce the current ofthe pass transistor and thus shortens the recovery time. The simulated re-covery time of the two LDO regulators (with and without bulk modulation)are compared in Fig. B.3.3.The behavior of the conventional and the proposed regulators when theoutput load current has a sudden increase is different. This load currentchange will cause a voltage drop at the output. In the conventional regula-tor, the error amplifier adjusts the gate voltage of the pass transistor to avery low voltage. Since it is a large signal change at the output of the erroramplifier, it causes a time delay due to slewing, tslew. In addition, due tothe low bandwidth of the error amplifier 2, the amount of the output voltage1The equilibrium bulk voltage is the bulk voltage of pass transistor when the outputof the regulator is set to its designated value. At equilibrium, the inputs of both erroramplifiers are equals to the reference voltage. EA-b is designed to have the equilibriumoutput voltage of 700 mV.2Conventional LDO regulators, typically use a high-DC-gain low-bandwidth amplifieras an error amplifier [87,112,115–117].181change is typically large which results in a slow recovery. In the proposedregulator, using bulk modulation of the pass transistor, the bandwidth of theoverall system is increased. Furthermore, by using the second error amplifier(i.e., EA-b) the overall slew time of the output node, namely, tslew, is de-creased. Thus, as depicted in Fig. B.3.3, both recovery time and the outputvoltage change are decreased. To further elaborate this enhancement, notethat by applying the proposed bulk modulation technique, one can use asmaller aspect ratio pass transistor while achieving the same current deliveryof the conventional regulator. The smaller pass transistor implies a smallerparasitic capacitance and thus a faster operation. In addition, since the bulkamplifier (EA-b) is designed to have a higher bandwidth than the standarderror amplifier (EA-a), it can sense the changes in the output voltage faster,and thus result in a faster operation and less voltage fluctuations.1820.3 0.5 1 2 3 5 10 20 30 50−1000100200Phase margin (deg) 0.5 1 2 3 5 10 20 30 50140160180RL (kΩ)C bulk (fF)Figure B.3.4: (top) The phase margin of two regulators in extreme conditions.The proposed regulator in blue remains stable even when the conventionalregulator is about to experience 180 of phase margin, (bottom) Totalparasitic capacitance of the bulk of the pass transistor versus the equivalentload resistance RL.B.3.3 Stability analysisFor the proposed architecture, the low-frequency small-signal open-loop gainof the regulator can be written as:AV = f · Rout · [(A1dc · gpassm ) + (A2dc · gpassmb )] . (B.3.2)In this equation, f is the feedback gain and is equal to R2R1+R2 , Rout =RL||rpassds ⇠= R is the open-loop output resistance of the regulator, whererpassds is the small-signal drain-source output resistance of the pass transistor,RL is the equivalent resistance of the load which is typically much smaller183than rpassds , A1dc and A2dc are the low-frequency small-signal voltage gainof the main and bulk error amplifiers, respectively, and gpassm and gpassmb arethe small-signal gate and back-gate (body) transconductance of the passtransistor. From (B.3.2), the overall open-loop gain of the regulator is afunction of the sum of the gains of the two error amplifiers. It can be shownthat the open-loop phase response of the regulator at any given frequencywould follow the phase of the error amplifier that has a higher gain at thatfrequency.Referring to the open-loop gain and the phase response of the regulatorshown in Fig. B.3.5, the open-loop structure has a dominant pole whichbelongs to EA-a (namely, the dominant pole of the opamp in EA-a, !opamp).This pole is at node A shown in Fig. B.1.2 and is independent of the loadcurrent of the regulator. The second pole is the dominant pole of the EA-bwhich is given by:!OTA = 1(Cbulk + Cota) · rota (B.3.3)where, Cbulk is the total parasitic capacitance seen at the bulk of the passtransistor, Cota = Cnpar +Cppar is the parasitic capacitance seen at the outputstage of the EA-b and rota is the small-signal output resistance of the EA-b. Note that Cnpar and Cppar are the total parasitic capacitance at the output184102 104 106 108−20020406080100Gain (dB)  102 104 106 108−50050100150frequency (Hz)Phase margin (deg)with BMw/o BMPM improvment UGF=1.75 MHzUGF=17 MHzIntroduced zeroIntroduced zero UGF improvmentILoad= 3 mAPM=132°PM=86°(a)102 104 106 108−20020406080100Gain (dB)  102 104 106 108−50050100150frequency (Hz)Phase margin (deg)with BMw/o BMUGF=3.9 MHzPM= 80°PM=82°Introduced zeroIntroduced zero PM improvment UGF improvmentILoad= 2 mA UGF=110 MHz(b)102 104 106 108050100Gain (dB)  102 104 106 108−1000100200frequency (Hz)Phase  margin (deg)with BMw/o BMPM=11.9°UGF=117.8 MHzPM= −105°UGF=27.33 MHzILoad= 0 mA(c)Figure B.3.5: Simulated open-loop bode diagram of the proposed LDO con-figuration with and without bulk modulation technique for load currents of(a) 3 mA (RL = 0.33 k⌦), (b) 2 mA (RL = 0.5 k⌦), and (c) 0 mA (no-load).185node of the EA-b amplifier, that are introduced by nmos and pmos transistorsconnected to that node respectively. Due to the use of the two amplifiers inparallel, a zero is created in between these two poles. It can be shown thatthis zero is at the frequency !zwhere A1(!z) · gpassm = A2(!z) · gpassmb . Sincethis zero is always in between the above mentioned poles, it compensates thephase drop caused by the first dominant pole. The third pole of the systemis located at the output node of the regulator and is usually at a higherfrequency (compared to the above mentioned two poles) and is given by:!L = 12⇡ · (CL + Cpar) · Rout (B.3.4)where, CL and Cpar are the load and parasitic capacitance at the output nodeof the regulator. The variation of the load current which can be interpretedas the variation of RL may cause an instability in the system. The problemarises when the value of the load current is very small and at the same timelarge capacitive load is attached to the system. In this case !L will be atlower frequencies and may fall below the unity gain frequency (UGF) of theregulator, and therefore may deteriorate the phase margin.In a conventional LDO regulator, any decrease in the output load currentwill lead to an increase in the open-loop voltage gain of the regulator (referto (B.3.2)), and consequently, it will increase the UGF of the conventionalregulator as given by:186UGF⇠= !opamp · Av. (B.3.5)This increase in UGF may jeopardize the phase margin and therefore thestability of the overall system. An illustrative example is shown in Fig. B.3.5(b). The transient response of this case is shown in Fig. B.4.6.In the presented regulator, the frequency of the second dominant pole ofthe regulator depends on the load current. When the load current decreasesthe gain of the regulator will increase but at the same time Cbulk will increaseas well. This increase of Cbulk is a consequence of the change in the passtransistor operating point. Since a part of the parasitic capacitance seenfrom the bulk of the transistor is the parasitic capacitance between bulk anddrain, due to the increase in the bulk-drain voltage gain the Miller equivalentcapacitance seen at the bulk will increase. Fig. B.3.4 illustrates this relation.The increase of Cbulk consequently leads to a decrease of the frequency of!OTA as the second dominant pole of the regulator. Since the effect of the firstdominant pole (!opamp) has been compensated by !z, the unity gain frequencyin the proposed regulator is more robust to changes of the load current. Asa result, the proposed regulator supports a wider output capacitance rangewhile preserving its stable regulation. This robustness is verified by bothsimulation and measurement as shown in Figs. B.3.5 (b) and B.4.6.187Figure B.3.6: Micrograph of the overall design including two LDO regulatorshighlighted by blue-dashed line.B.4 Simulation and Experimental ResultsTo validate the proposed technique, two regulators (one with and one withoutthe proposed bulk modulation technique) are designed and fabricated in a0.13-µm CMOS technology. To study the open-loop frequency response ofthe circuit an open-loop version of the regulator has also been designed andimplemented. Fig. B.3.6 shows the micrograph of the chip which occupies218.9⇥113.0 µm2. The area of the proposed regulator is 66.55⇥36.8 µm2.The simulated and measured steady-state (DC), transient, and frequencyresponse of the regulators are compared to confirm the performance of thepresented structure.1881 2 3 4 5 60.60.650.70.750.80.850.90.9511.05  X: 0.005Y: 0.6555Load current (mA)Regulated voltage (V) X: 0.0028Y: 0.9457 X: 0.005Y: 0.9489With BM measuredW/o BM measuredW/o BM simulatedWith BM simulated46%improvment79% improvmentFigure B.4.1: Experimental results of load regulation of the proposed regu-lator compared to the conventional one.B.4.1 DC responseThe proposed regulator draws 99.04 µA from a 1.2 V supply for ILoad =5 mA,which is 53% more than the conventional regulator due to the use of ad-ditional bulk amplifier. In particular, EA-a draws 38.6 µA, EA-b draws51.01 µA, and reference voltage and biasing circuits draw 9.43 µA from thesupply.Fig. B.4.1 compares two regulators for DC load regulation when the inputvoltage Vin=1.2 V is applied. The experimental results are obtained usingan HP 4155A semiconductor parameter analyzer and are compared withsimulation results. As both measurement and simulation results indicate,the load regulation performance of the bulk modulated regulator is improved189by 79% at 0.95 V output regulated voltage.0 5 1000.51time (ms)Voltage (V)  VinW/o Bulk ModulationWith Bulk ModulationFigure B.4.2: Measured DC response of the regulators to different input DCvoltage.Fig. B.4.2 illustrates the DC line regulation of the proposed regulatorand the conventional one. In this measurement, to obtain the DC responseof the regulators the input voltage (Vin) is varied slowly in the form of a rampfrom 0 to 1.4 V in 7 ms. The presented DC response confirms that usingthe proposed bulk modulator technique the regulator works with a lowersupply voltage. This feature can be attributed to the fact that the thresholdvoltage of the pass transistor at low input voltages is decreased which inturn makes the regulator more responsive to lower input voltages. The lowerturn-on voltage can be very useful in low-power applications, for example inwireless power delivery applications such as biomedical implants and RFID190applications (where a regulator is used in the power conversion-chain). Themagnitude of the measured DC line regulation for the proposed regulator is1.48% while its conventional counterpart shows 2.26% for the input voltagerange of 1.1 to 1.37 V (as shown in Fig. B.4.2).0 5 10 15 2000. (µs)Voltage (V)  VinWith bulk modulationW/o bulk modulationFigure B.4.3: Measured start-up transition of the two regulators with andwithout bulk modulation technique.B.4.2 Transient responseOne of the important performance metrics for any LDO regulator is its start-up time which indicates how fast the regulator can provide the regulatedvoltage. Fig. B.4.3 compares the start-up time in the presence and absence ofthe proposed bulk modulation technique. Note that without bulk modulationthe start-up time is longer than 10 µs. The technique improves the start-191up by a factor of 15. This improvement can be attributed to the widebandbulk error amplifier as well as the lowering of the threshold voltage of thepass transistor. In this experiment a pulse input voltage with raising timeof 5 ns is applied to both regulators at 1 mA of load current. Note thatwe are comparing both regulators for the same load current. Therefore, theload current of 1 mA is chosen since both regulators are able to supply that.Note that using the load current of 2.88 mA, which as shown in Fig. B.4.1is the maximum current load delivery of the regulator without the proposedtechnique, will make the comparison unfair since the conventional regulator isoperating at its maximum load current capacity while the proposed regulatoris operating at almost half of its current capacity (maximum current deliveryof 5 mA).Line regulation is another important performance parameter of LDOs.The simulated line regulation of both regulators are presented in Fig.B.4.4.0 50 100 1500.70.80.911. (V)  with BMw/o BMVINFigure B.4.4: Simulated line regulation.192One may think that bulk modulation of the pass transistor may causemore sensitivity to supply noise, however, having wide bandwidth error am-plifier connected to the bulk node of the pass transistor not only does notworsen the line regulation, but as demonstrated by simulation (Fig. B.4.4)and verified by measurement results (Fig. B.4.7) it slightly enhances the lineregulation performance.1930 0.5 1 1.5 2 2.5 3  X: 2.152Y: 1.003time (µs)Regulated voltage (V) X: 3.605Y: 0.9829X: 3.6Y: 1.007X: 0.06314Y: 0.9874with bulk modulationw/o bulk modulation65 ns2.15 µs(a)0 10 20 30 40 50 600.  X: 60.1Y: 1.019Regulated voltage (V)0 10 20 30 40 50 60123time(µs)Load current (mA)  w/o bulk modulationwith bulk modultiontrec =1.02 µstrec=20.1 µs(b)Figure B.4.5: (a) The worst-case recovery time of both regulators measuredfrom 1 mA to 3.2 mA load transition with the 5 ns transition speed (aver-aged over 32 signals) and (b) the measured performance of transient loadregulation for load transition speed of 200 ns(averaged over 16 signals).As discussed earlier the proposed bulk modulation technique improvesthe recovery time of the regulator as compared to the conventional regulator.Fig. B.4.5 presents the experimental results of the recovery time of both pro-posed and conventional regulators for two load transition speeds of 5 ns and194200 ns. Note that for the 5 ns transition speed the proposed regulator withbulk modulation technique has the recovery time of 65 ns (see Fig. B.4.5(a))as compared to 2.15 µs in the conventional case. The presented waveforms inpart a and b are averaged over 32 and 16 signals, respectively, to reduce theeffect of the unwanted noise. The recovery time of the proposed regulator forthe slower load transition (i.e., 200 ns transition time) is 1.02 µs as comparedto 20.1 µs for the conventional regulator as shown in Fig. B.4.5(b).195−1 −0.5 0 0.5µs)Regulated voltage (V)  With bulk modulationW/o bulk modulation(a)−1 −0.5 0 0.5 10.80.850.90.9511. (µs)Regulated voltage (V)  W/o bulk modulationWith bulk modulation(b)−1 −0.5 0 0.5µs)Load current (mA)(c)Figure B.4.6: (a) Simulated and (b) measured transient response of regu-lators, when the load current suddenly changes to 0 mA and (c) simulatedcurrent load change.Note that the experimental results shown in Fig. B.4.6 (b) contain higher196ripples as compared to the simulation results shown in sub-figure (a). Thelarger ripples can be attributed to the discrete switch that is used to changethe current load of the regulator. The input and output terminals of theswitch are designed based on the assumption of 50 ⌦ source and load impedanceand connecting them to a higher impedance (in this case, 1 V/1 mA=1 k⌦)results in some reflections of voltage (electric field) which can result in ahigher voltage variation (ripple) at the output of the regulator.B.4.3 Frequency responseSimulation results shown in Fig. B.3.5 verify the position of the zero andvalidates the overall voltage gain obtained in (B.3.2). The bandwidth ofthe EA-b is designed to be 129 MHz which corresponds to the unity gainfrequency of 2.0 GHz. For the main error amplifier on the other hand abandwidth of 1.48 kHz is chosen which corresponds to UGF of 105MHz.The EA-a and EA-b have a DC gain of 25.4 and 83.9 dB, respectively.197104 105 106 107 108 109−120−100−80−60−40−20020frequency (Hz)PSRR (dB)  Experimental with BMExperimental w/o BMSimulation with BMSimulation w/o BMPSRR −57.11 @ 1MHzPSRR −41.15 @ 10MHzPSRR −93.56 @ 1kHzFigure B.4.7: Measured and post-layout simulated PSR performance ofregulators while supplying 1 mA of load current.ENA- Vector Network AnalyzerVinVoutRegulatorP250RsP150Figure B.4.8: Measurement setup for PSR experiments.Fig. B.4.7 illustrates the effect of the parallel EA-b on power supplyrejection (PSR) of the regulator. As expected, the improvement in the line198Table B.1: Performance summary and comparison with the state-of-the-art LDOs.[101] [86] [87] [118] [119] [99] [100]This workw/o BMThis workwith BMYear 2010 2010 2010 2011 2012 2013 2013 2013 2013Technology(µm)0.09 0.18 0.13 0.13 0.18 0.18 0.065 0.13 0.13ImaxloadQ(µ)A 33  145 35 45 1.33 120 40 0.9 44.03 99.04Areanormalized to0.00245 mm25.075 126.53 10.20 12.42 65.3 17.95 6.94 ⇠1 1Settling time(µs)† N/A 100 0.07 28 4.8 1.172 6 2.15 0.065Full load:ILoadmax(mA)140 150 2 50 5 100 100 3 5PSR(dB)-56@10 MHz,-30@30 MHz -64.3@1 kHz -55@1 MHz N/A -65@1 kHz N/A -58@10 kHz -93.8@1 kHz,-58.23@1 MHz,-41.15@10 Hz†† -93.6@1 kHz,-57.11@1 MHz,-41.15@10MHz††Closed-loopbandwidthN/A 20 kHz 100 kHz 80-200 kHz 680 kHz 10 MHz N/A 74 MHz 121 MHzVout(mV)††† 94 196 120 ⇠250 0.61 100 69 50 50† Worst-case settling time.†† Post-layout simulation PSR.††† Load regulation from no-load to full-load transition.199regulation is achieved by adding the extra bulk error amplifier, EA-b. Tofurther investigate the line regulation performance of the proposed circuitat different frequencies, a PSR measurement is conducted. Since the mea-surement instrument has an input resistance of 50⌦, as shown in Fig. B.4.8,the series resistance RS of 1 k⌦ is added to ensure that the total current ofboth regulators during this measurement is limited to 1 mA. The adverseeffects of this additional resistance are removed using proper calibration andde-embedding. Note that port 1 (shown in Fig. B.4.8 as P1) is sending aninterference signal with a designated frequency to the input of the regulatorwhile port 2 measures the regulated (attenuated) signal. To measure thePSR, we should multiply the scattered parameter s21 by the ratio of thevoltage divider at P2 (i.e., 1050/50=26.44 dB).As can be seen from the figure, the measured and simulated PSR perfor-mances of the bulk-modulated regulator confirm that not only the PSR ofthe proposed bulk-modulated regulator is not adversely affected, but also itis slightly better than the conventional regulator. As shown in Table B.1 theproposed regulator achieves superior PSR. However, this PSR performancecan be attributed to the following reasons. The main reason is the relativelysmall full load current of the proposed regulator as compared to the similardesigns which in turn facilitates larger loop-gain and thus better power sup-ply rejection ratio. Secondly, the wide bandwidth error amplifier EA-b offers200a better PSR at higher frequencies. The last reason is due to the carefullayout design of the regulators to make sure that the input voltage paths arenot close to any sensitive nodes of the regulator.B.5 ConclusionsThis work presents a bulk-modulation technique for LDO regulators. Sim-ulation and measurement results confirm the performance improvements inload driving capability and recovery time when the technique is applied to aconventional LDO regulator. The improvement of the stability of the regula-tor, specially in no load condition is also studied and presented. As comparedto a conventional LDO, the extra error amplifier used to drive the bulk ofthe pass transistor draws an additional 51 µA current while it improves theload delivery capability by 79% and the recovery time by more than 10 folds.Table B.1 presents the performance summary of the proposed LDO and com-pares it with a conventional LDO regulator without bulk modulation as wellas other state-of-the-art LDOs. It should be noted that the proposed tech-nique can also be applied to other LDO structures.201Appendix CA monolithic Current-SensingTopology for System-on-ChipApplicationsIt is important to be able to have a sense of the power consumption of anytelemonitoring systems, specially for those applications that have very lim-ited power budget. The initiative idea of the following design came fromthe need of measure the received power to the telemonitoring system withminimum cost of power consumption. Due to our limited area for embed-ded integrated circuit only a monolithic structure would be an option. Sincethe nature of the induced current in any telemonitoring system with energyharvesting technique is an alternative current, we decided to design a mono-lithic, none-invasive AC current sensor to achieve our goal. In the following202sections, the motivation for designing such sensors for broader applications,as well as, analytical discussion about proposed architecture is presented.Simulation and measurement results are provided to verify the performanceof the presented current sensor.C.1 IntroductionSensing current has a wide range of applications in many integrated circuit(IC) and system-on-chip (SoC) designs. The applications of current sensingextend from fault diagnosing in complex ICs [120, 121] to monitoring cur-rent in switching DC-DC converters [122, 123], to protecting confidentialityof cryptosystems [124], to testing and analyzing the performance of mixed-signal and RF circuits [121]. In many such applications it is desirable to use anon-invasive current-sensing technique, i.e., the sensing circuit virtually doesnot disturb the test circuit current. In particular, many present and emergingapplications require a high-bandwidth current sensing circuit. State-of-the-art monolithic current-sensing schemes have bandwidths in the range of a fewMHz up to 3.4 GHz [120]- [124]. Although a current-sensing technique thatuses exotic material and is based on giant magneto impedance (GMI) effectwith bandwidths up to 30 GHz has been previously discussed (refer to [125]for an overview of this and other techniques), such techniques require a rela-tively large foot-print as well as use of exotic materials and are not amenableto implementation in standard CMOS processes. Given that emerging appli-203cations are operating at increasingly higher frequencies, having an efficienthigh-bandwidth current-sensing technique suitable for integration in low-costCMOS technologies is desirable. In this work, a simple electromotive-force-based technique that operates over a wide frequency range and requires asmall foot print for non-invasive current-sensing in CMOS ICs and SoCs ispresented.Figure C.1.1: Top layout view of the proposed current-sensing technique.The sensing path, formed by spiral-like path using two different metal layersand vias, is encircling the current path.…... ........................................................................ ........................Pxmr. . . . . . . .... . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . mntWBBBtBxyFigure C.1.2: The current sheet is broken into several wires carrying equalcurrents Ik204C.2 Proposed TechniqueThe proposed technique is based on Faraday’s law, where a variable magneticfield caused by a varying current (I), induces a voltage difference betweenany two points on a neighbouring loop (e.g., V1 and V2 in Fig. C.1.1). Theamplitude of the induced voltage is proportional to the amplitude as wellas the frequency of the varying input current. Thus given the frequency ofthe input current, by monitoring the induced voltage the amplitude of theinput current can be deduced. The layout view of the proposed monolithiccurrent-sensing device is shown in Fig. C.1.1. The metal plate in the centrecarries the current I that is to be measured. The varying current (I) inducesa voltage difference between two terminals V1 and V2 of the rectangular helixstructure surrounding the central current path. This voltage difference isgiven by:V1  V2 = " = dBdt(C.2.1)where " is the induced emf, and dB/dt is the rate of change of the total flux.The total flux, B, is the overall flux passing through all of the individualloops. Assuming there are total of N individual loops and the passing fluxthrough each individual loop is B, then B = NB. As shown in Fig. C.1.1,the horizontal spacing between the top and bottom traces of each loop isdesigned to be much shorter than the length of the path carrying the current205that is to be measured (i.e., l ⌧ L). Given that l ⌧ L, one can makea simplifying assumption that the magnetic field (B) in the vicinity of thecurrent path edge is only a function of the distance x from the edge of thecurrent path (refer to Fig. C.1.2).To obtain an expression forB(x) let us assume that the current path is formedby n·(2m+1) wires (Fig. C.1.2) each carrying a current of Ik = I/[n(2m+1)].Since we intend to measure high-frequency current, the skin effect [126] hasto be taken into account. The skin depth (i.e., the depth below the surfaceof the conductor at which the current density has fallen to e1 (about 0.37)of the surface current density) is given by [126]: =r2!µ(C.2.2)where  is the skin depth,  and µ are the electrical conductivity andthe magnetic permeability of the conductor, respectively, and ! is the an-gular frequency of the current. For the prototype design considered in thiswork, this skin depth at 20 GHz is 0.56 µm (see Fig. C.2.1). Given that thethickness of the current path is less than 0.3 µm, we can assume that overallcurrent I is uniformly distributed along the cross section of the path (thethickness of the path is smaller than the skin depth).206100M 1G 10G0.1110100frequency(Hz)Skin effect’s Depth (µm)Figure C.2.1: Skin effect’s depth versus frequency of the passing current.Given the simplifying assumption that B in the vicinity of a long current-carrying wire is only a function of distance from the wire, i.e., x, the overallB at point P in the vicinity of the current path (as shown in Fig. C.1.2),can be calculated by applying the superposition principle. In this context,one can show that at point P the magnetic field components along the xdirection cancel each other and the overall B is along the y direction and canbe written as:Bn(x) = µIk2⇡ [Pni=0 ⇣ 1x+r(2i+1)⌘+Pni=0Pmj=0 ⇣ 2(x+r(2i+1))(x+r(2i+1))2+(r(2j+1))2⌘] (C.2.3)207where r is the radius of each wire and is given by r = W/2n, and m is thenumber of virtual wires forming the thickness of the current path (Fig. C.1.2).m is calculated from 2m + 1 = floor(l/(2r)).100 150 200 250 300 350 400 45058101520nγ (x10−12 )Figure C.2.2: Calculated (n) for different values of n, in 0.13 µm CMOSprocess.Furthermore, µ = µ0µr where µ0 is the magnetic permeability of thevacuum and µr is the relative magnetic permeability of the medium (forsilicon dioxide µr ⇠= 1). In (C.2.3), the first term is the magnetic field causedby the middle row of wires, and the second term is the magnetic field causedby the rest of the wires. Therefore, the magnetic flux B can be written as:208B = ¨S B · ds = ˆ w0 ˆ l0 Bn(x)dxdy = w ˆ l0 Bn(x)dx (C.2.4)where S is the closed surface of the loop through which B(x) is passing.In the prototype integrated current sensor the dimensions of each loop arew = 700 nm and l = 400 nm (Fig. C.1.1). The induced electromotive forceis:"(t) = 2⇥RTRpath [Ii(n)] fcos(2⇡ft) (C.2.5)where Ip is the peak of the input current I = Ipsin(2⇡ft) and (n) =2⇡Nl´ w0 Bn(x)dx/I. Taking into account that in practice the two sides of thesensing path are typically terminated to an impedance (in this work, the ter-mination impedance on each side of the sensing path is the input impedanceof the measurement instrument, i.e., oscilloscope, which is RT = 50 ⌦), thesensing system can be modelled with the equivalent circuit shown in theinset of Fig. C.1.1. Note that this model is based on the fact that ideallythe induced emf generated across the sensing path is independent of the ter-mination impedance. Therefore, one can model the induced voltage acrosssensing path with an ideal current source in series with the equivalent lumpedresistance of the sensing path, i.e., Rpath. This induced current source canbe intuitively justified since the induction path can be considered as the209secondary winding of a current transformer, where the input (i.e., primary)winding has one turn. Note that voltage across this fictitious current sourceviolates the kirchhoff voltage law as the Kirchhoff voltage law is not valid fornon-conservative electric field. Therefore, the voltage difference V1  V2 canbe written as: V1  V2 = (2⇥RT/Rpath)⇥ emf.The trans-resistance gain of the overall current sensor can be derived as:|"||I|=2⇥ 50Rpath · (n) · f (C.2.6)Fig. C.2.2 shows the results of calculating (n) for different values of n in0.13 µm CMOS process. We expect that by increasing the number of divisions(n) we will get closer to the actual answer. This assumption is supported bythe results shown in Fig. C.2.2; As shown, for n > 300, (n) ! 8 ⇥ 1012.In this case, assuming n = 450, and for l = 0.2624µm and W = 3µm wewill have (450) = 7.99 ⇥ 1012. Furthermore, given the geometry of thedesign and the fact that in this proto-type design there are 23 series sets of6 parallel vias and the resistance of those vias account for most of the pathresistance, we can calculate the overall resistance of the path as follows:Rpath ⇠= Rvias = (Rvia/6) · 23⌦ (C.2.7)Note that in 0.13 µ CMOS process Rvia = 1.799 ⌦. Given that from(C.2.7), Rpath ⇠= 6.90 ⌦.2100 1 2 3 4 5 6 705101520253035I (mA)Induced voltage (mV)  Figure C.2.3: The measured sensed voltage versus amplitude of current. Thefrequency of the current in this experiment is 7 GHz.Figure C.2.4: Measured trans-resistance gain versus input current frequencyas well as calculated gain obtained from (C.2.6) and simulation results usingMomentum211As (C.2.6) shows, contrary to other methods of sensing current, by in-creasing the frequency of the sensed current I the magnitude of the trans-resistance gain increases (Fig.C.2.4). This is the main advantage of thismethod as compared to previously reported techniques. In addition, thesensing of the current is non-invasive and is done passively with no extrapower consumption, thus, makes the proposed approach suitable for ultra lowpower applications. Fig.C.2.4, compares the analytical expression of trans-resistance gain (V1  V2)/I stated in (C.2.6) with simulated and measuredresults in different frequencies. As expected, by increasing the frequency, thetrans-resistance gain increases up toll a frequency at which the parasitic ca-pacitance shorts the current path and sensing path together. Note that themeasured trans-resistance has less bandwidth than the simulated one, whichcan be attributed to the limited bandwidth of the measurement instrumentsused in this experiment.Fig. C.2.3 presents the measured induced voltage V1V2 versus amplitudeof the current. The red curve represents the best linear fit of the measuredresults. As expected from (C.2.5) and is verified by measured results thereis a linear relation between sensed voltage and the amplitude of the current.C.3 ConclusionA simple monolithic non-invasive passive current-sensing method for ultra-low-power applications is presented. A detailed analytical treatment of the212technique is provided. The method can be used to sense varying currents upto several GHz (8 GHz in the presented prototype). The measured resultsare inline with the analytical and simulation results.213


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