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Modelling and application of spiral inductors in CMOS LC-VCOs

University of British Columbia

Communication systems are essential components of our everyday lives and they facilitate accessing and using the ever-increasing amounts of data that have surrounded us. The main objective of this research is to present solutions at the device, circuit, and system levels for key passive and active circuit building blocks of communication systems, namely, monolithic passive inductors and inductor-based voltage-controlled oscillators (LC-VCOs). These components are almost ubiquitously used in integrated wireless and wireline communication transceivers, as well as other computing devices. Key contributions of this work are as follows: In the context of monolithic inductors, we have studied different inductor structures such as doubly-stacked inductors, vertical inductors, and coupled-rings. We have developed circuit models to accurately estimate their inductance and quality factor. The proposed analytical expressions provide designers with a reasonable estimate of their circuit performance and layout constraints. The result of proposed analyses is verified by the measurement results of test structures implemented in CMOS technology. Regarding LC-VCOs, we have studied the effect of large signal oscillations on such VCOs by developing a mathematical model to solve the non-linear differential equation governing the LC tank circuit. The study shows that the VCO frequency and the amplitude of higher order harmonics are functions of circuit parameters such as the C-V characteristics of the varactor and the oscillation amplitude. Also, a low- power technique to boost the output amplitude of push-push VCOs is introduced. Measurement results of a proof-of-concept prototype test chip in 90-nm CMOS confirm the usefulness of the proposed technique. Finally, at the system level, we present an analytical model to study the effect of coupling between adjacent LC-VCOs closely integrated on the same chip. This is usually the case in high-speed wireline transceivers such as those used in serial links. The proposed model explains the behavior of spurious sidebands as observed in the frequency spectrum of closely-running adjacent links. A redundant frequency mapping scheme is proposed that significantly reduces this coupling effect. Measurement results of a highly packable clock synthesizer in a 65-nm CMOS confirm the validity of the analytical model and the effectiveness of the proposed mapping technique.

Text

2013-10-24

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/45377

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/