Open Collections

UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

On the use of body biasing to improve the performance of CMOS RF front-end building blocks Rashtian, Hooman 2013

Your browser doesn't seem to have a PDF viewer, please download the PDF to view this item.

Item Metadata

Download

Media
24-ubc_2013_fall_rashtian_hooman.pdf [ 7.51MB ]
Metadata
JSON: 24-1.0074003.json
JSON-LD: 24-1.0074003-ld.json
RDF/XML (Pretty): 24-1.0074003-rdf.xml
RDF/JSON: 24-1.0074003-rdf.json
Turtle: 24-1.0074003-turtle.txt
N-Triples: 24-1.0074003-rdf-ntriples.txt
Original Record: 24-1.0074003-source.json
Full Text
24-1.0074003-fulltext.txt
Citation
24-1.0074003.ris

Full Text

On the Use of Body Biasing to Improvethe Performance of CMOS RFFront-End Building BlocksbyHooman RashtianM.A.Sc., Isfahan University of Technology, 2008B.A.Sc., Isfahan University of Technology, 2006A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHYinThe Faculty of Graduate Studies(Electrical and Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)July 2013© Hooman Rashtian 2013AbstractBody biasing is commonly used in digital and low-power analog integrated circuits to adjust thethreshold voltage of complementary metal-oxide-semiconductor (CMOS) transistors and to lowerthe supply voltage. In this work, the application of body biasing to improve the performance offour of the main building blocks of CMOS radio-frequency (RF) front-ends is explored. Here,the body-biasing technique is used in conjunction with other design techniques and providesan extra degree of freedom in the design of CMOS RF front-end building blocks including low-noise amplifiers (LNAs), active down-conversion mixers, voltage-controlled oscillators (VCOs),and power amplifiers (PAs). The performance improvements are mainly related to noise andlinearity of these building blocks and have been achieved through adjusting the values of thebulk-source transconductance, the source-bulk capacitance, and the threshold voltage of theMOS transistors. Body biasing is applied in multi-stage LNAs to improve their noise figure andlinearity as well as to adjust the gain. Body biasing is used to improve the linearity of activedown-conversion mixers with gradual LO switching by enhancing the linearity of the LO stage.Body biasing is used in cross-coupled LC VCOs to improve their phase noise performanceby forward body biasing of core transistors which lowers the duty cycle in class-C mode ofoperation. In active-inductor-based LC VCOs, body biasing is used to increase the tuningrange of active inductors and thus the oscillation frequency. Finally, body biasing is in thepredistortion stage of class-AB PAs to improve the linearity by compensating for the voltage-dependent nonlinear gate-source capacitance of the input transistor of the PA. In all cases,these improvements are achieved with minimal overhead on circuit-level complexity and powerconsumption of the overall system. The proposed applications of body-biasing technique arevalidated through measurements on different proof-of-concept prototypes fabricated in 0.13-µm,90-nm, and 65-nm CMOS technologies.iiPrefaceI, Hooman Rashtian, am the first author and principle contributor of all the chapters of thisdissertation. All chapters are co-authored with Professor Shahriar Mirabbasi, who supervisedthe research and provided technical consultation and editing assistance on the manuscript. Thefollowing publications describe the work completed in this dissertation. Chapter 3 is based on[SJ3]. There is also some overlap with [C1] and [J2] which focus on application of the proposedtechnique in mm-wave low-noise amplifiers. [C1] is co-authored with Cedric Majek, ProfessorThierry Taris, Professor Yann Deval, and Professor Jean-Baptiste Begueret from University ofBordeaux, Bordeaux, France, who provided technical input on electromagnetic simulations ofpassive components at mm-wave frequencies. [J2] is the extension of [C1]. Chapter 4 is basedon [SJ5] and [C2] which have been co-authored with Amir Hossein Masnadi Shirazi who helpedwith the design and layout of the proof-of-concept prototype mixers. Chapter 5 includes theresults of [J1]. Chapter 6 is based on [C3]. Appendix A is based on the [SJ4] and also overlapswith [J2].Journal Papers:[J1] H. Rashtian and S. Mirabbasi, Using body biasing to control phase-noise of CMOS LCoscillators, Electronics Letters, vol. 48, no. 3, pp. 168-169, February 2012.[J2] H. Rashtian, S. Mirabbasi, T. Taris, Y. Deval, and J. B. Begueret, A 4-stage 60-GHzlow-noise amplifier in 65-nm CMOS with body-biasing to control gain, linearity, and inputmatching, Analog Integrated Circuits and Signal Processing, Springer, vol. 73, no. 3, pp.757-768, December 2012.[SJ3] H. Rashtian and S. Mirabbasi, Applications of body biasing in multi-stage CMOS low-noise amplifiers, submitted on April 27, 2013.iii[SJ4] H. Rashtian and S. Mirabbasi, Design and layout techniques for a mm-wave body-biasedvariable-gain amplifier, submitted on April 19, 2013.[SJ5] H. Rashtian, A. H. Masnadi Shirazi, and S. Mirabbasi, On the use of body biasing toimprove linearity in low LO-power CMOS active mixers, submitted on May 27, 2013.Conference Papers:[C1] H. Rashtian, C. Majek, S. Mirabbasi, T. Taris, Y. Deval, and J. B. Begueret, On theuse of body biasing to control gain, linearity and noise figure of a mm-wave CMOS LNA,in Proceeding of 8th IEEE International New Circuits and Systems Conference (NEWCAS),Montreal, Canada, June 2010. (Best Student Paper, Third Place)[C2] H. Rashtian, A. H. Masnadi Shirazi, and S. Mirabbasi, Improving linearity of CMOSGilbert-cell mixers using body biasing, in Proceeding of 55th IEEE International Midwest Sym-posium on Circuits and Systems (MWSCAS), Boise, Idaho, USA, August 2012.[C3] H. Rashtian, and S. Mirabbasi, Improving linearity in class-AB power amplifiers usinga body-biased NMOS predistortion stage, in Proceeding of International Green ComputingConference (IGCC), Arlington, Virginia, USA, June 2013.ivTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 RF Front-Ends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 CMOS Technology for RF Front-Ends . . . . . . . . . . . . . . . . . . . . . . . . 41.4 MOS Transistor Physics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4.1 Body Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 RF Front-End Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1 Low Noise Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1.1 LNA Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . 112.1.2 LNA Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.2 Down-Conversion Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.2.1 Mixer Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . 242.2.2 Mixer Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27v2.3 Voltage-Controlled Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.3.1 Oscillator Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.3.2 VCO Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . 362.4 Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.4.1 PA Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 412.4.2 PA Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Body Biasing in Low-Noise Amplifiers (LNAs) . . . . . . . . . . . . . . . . . . 443.1 Multipurpose Application of Body Biasing in LNAs . . . . . . . . . . . . . . . . 443.2 3-Stage LNA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463.3 Body Biasing for Improving Noise Figure . . . . . . . . . . . . . . . . . . . . . . 493.3.1 Noise Parameters of MOS Transistors . . . . . . . . . . . . . . . . . . . . 513.3.2 Effect of Bulk Resistance on Noise of MOS Transistors . . . . . . . . . . 533.4 Body Biasing for Gain Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.4.1 Body Biasing for Reducing the Gain . . . . . . . . . . . . . . . . . . . . . 583.4.2 Body Biasing for Gain Boosting . . . . . . . . . . . . . . . . . . . . . . . 593.5 Body Biasing for Linearity Enhancement . . . . . . . . . . . . . . . . . . . . . . 613.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 Body Biasing in Active Down-Conversion Mixers . . . . . . . . . . . . . . . . 734.1 Current-Commutating Active Down-Conversion Mixers . . . . . . . . . . . . . . 744.2 Non-Ideal Switching in Active Down-Conversion Mixers . . . . . . . . . . . . . . 764.3 Nonlinearity Analysis in Mixers with Non-Ideal Switching . . . . . . . . . . . . . 774.4 Body Biasing for Linearity Enhancement . . . . . . . . . . . . . . . . . . . . . . 804.5 Effect of Body Biasing on Conversion Gain . . . . . . . . . . . . . . . . . . . . . 824.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 Body Biasing in Voltage Controlled Oscillators (VCOs) . . . . . . . . . . . . 915.1 Application of Body Biasing to Improve the Phase Noise in CMOS LC VCOs . . 91vi5.1.1 Linear, Time-Invariant (LTI) Analysis of Phase Noise . . . . . . . . . . . 935.1.2 Linear, Time-Variant (LTV) Analysis of Phase Noise . . . . . . . . . . . 975.1.3 Phase Noise in Cross-Coupled CMOS LC Oscillators . . . . . . . . . . . 1015.1.4 Tail Capacitance; Advantages and Disadvantages . . . . . . . . . . . . . . 1065.1.5 Class-C Operation of CMOS Cross-Coupled LC Oscillators . . . . . . . . 1105.1.6 Application of Body Biasing To Improve Phase Noise . . . . . . . . . . . 1165.1.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205.1.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245.2 Application of Body Biasing to Increase the Tuning Range in Active-InductorBased CMOS LC VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265.2.1 Active Inductor Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275.2.2 Active-Inductor-Based CMOS LC VCOs . . . . . . . . . . . . . . . . . . 1305.2.3 Body Biasing to Increase the Tuning Range in AI-LC VCOs . . . . . . . 1315.2.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336 Body Biasing in Class-AB Power Amplifiers (PAs) . . . . . . . . . . . . . . . . 1366.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366.2 Sources of Nonlinearity in Class-AB Power Amplifiers . . . . . . . . . . . . . . . 1376.3 Predistortion to Cancel Nonlinearity in Input Capacitance . . . . . . . . . . . . 1406.4 Body-Biasing of the NMOS Predistortion Device for Improving Linearity . . . . 1426.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517.1 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537.1.1 Automatic Control Scheme for Body Biasing . . . . . . . . . . . . . . . . 1537.1.2 Application of Body Biasing to other Building Blocks of RF Front-ends . 1547.1.3 Body Biasing in SOI Technologies . . . . . . . . . . . . . . . . . . . . . . 155Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156viiAppendicesA Design and Layout Techniques for a mm-Wave Body-Biased Variable-GainAmplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168A.2 Finite-Ground CPW and Odd Mode of Propagation . . . . . . . . . . . . . . . . 169A.3 Self-Resonance-based Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . 172A.4 Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173A.5 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174A.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180viiiList of Tables3.1 Performance summary and comparison of the prototype LNA with other pub-lished works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.1 Performance summary and comparison of the prototype mixers with other pub-lished works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905.1 Comparison of the prototype VCO with the state-of-the-art low-power VCOs . . 124A.1 Comparison of the prototype mm-wave VGA with several other published works . 180ixList of Figures1.1 Block diagram of generic RF transceivers . . . . . . . . . . . . . . . . . . . . . . . 21.2 The trend for improving the maximum operation frequency (fmax) and transitfrequency (fT ) of CMOS technology with scaling of gate length . . . . . . . . . . 41.3 (a) MOS transistor structure (b) circuit symbol . . . . . . . . . . . . . . . . . . . 61.4 Formation of channel in MOS transistors (a) depletion (b) inversion . . . . . . . . 71.5 MOS transistor with isolated p-well in a CMOS technology triple-well option . . 81.6 (a) Probe station (b) on-wafer probing. . . . . . . . . . . . . . . . . . . . . . . . . 92.1 The focus of this work among different blocks of RF front-ends. . . . . . . . . . . 122.2 LNA-antenna interface and its equivalent model . . . . . . . . . . . . . . . . . . . 132.3 Inter-modulation of two interferer signals and its adverse effect on the desiredsignal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4 (a) Graphical definition of IIP3 (b) main and third order plots in presence of gaincompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.5 Graphical definition of 1-dB compression point . . . . . . . . . . . . . . . . . . . 182.6 Leakage of PA to the input of LNA in a full-duplex system . . . . . . . . . . . . . 192.7 Spectrum of (a) base-band and (b) up-converted data . . . . . . . . . . . . . . . 222.8 Down-conversion and resulting spectra . . . . . . . . . . . . . . . . . . . . . . . . 242.9 (a) Heterodyne receiver (b) direct-conversion receiver with quadrature down-conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.10 (a) SSB and (b) DSB noise figure in mixers . . . . . . . . . . . . . . . . . . . . . 272.11 Schematic of a single MOS transistor Mixer . . . . . . . . . . . . . . . . . . . . . 282.12 General structure of Gilbert mixers . . . . . . . . . . . . . . . . . . . . . . . . . . 292.13 Schematic of (a) single-balanced (b) double-balanced Gilbert mixers . . . . . . . 30x2.14 Block diagram of type-II frequency-multiplying PLL . . . . . . . . . . . . . . . . 312.15 Negative feedback system and required phase shift for oscillation (a) in open-loopsystem (b) around the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.16 One-port view of oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.17 Schematic of a ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.18 One-port model for three-point oscillators . . . . . . . . . . . . . . . . . . . . . . 342.19 Colpitts oscillator circuitry (a) single-ended (b) differential . . . . . . . . . . . . . 342.20 (a) Cross-coupled LC oscillator (b) one-port model equivalent . . . . . . . . . . . 352.21 Feedback representation of cross-coupled oscillators . . . . . . . . . . . . . . . . . 362.22 Distributed oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.23 spectrum of (a) ideal oscillator (b) noisy oscillator . . . . . . . . . . . . . . . . . 372.24 Reciprocal mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.25 Capacitance-voltage curve in (a) regular MOS varactors (b) accumulation-modeMOS varactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.26 Accumulation-mode MOS varactor (a) Cmin (b) Cmax . . . . . . . . . . . . . . . 392.27 Schematic of a CMOS LC VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.28 Power amplifier position in generic diagram of transmitters . . . . . . . . . . . . 412.29 (a) Typical schematic of a power amplifier (b) drain voltage and current wave-forms of transistor in class-A (c) in class-AB power amplifiers . . . . . . . . . . . 423.1 The Block-diagram of a 3-stage LNA with body-biasing for NF improvement,gain variation and linearity enhancement . . . . . . . . . . . . . . . . . . . . . . 463.2 Common-source amplifier with degeneration and series-gate inductance . . . . . . 463.3 Cascode amplifier with inductive degeneration . . . . . . . . . . . . . . . . . . . . 473.4 (a) Circuit model for noise of cascode device (b) magnitude of noise due to thecascode device versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.5 Circuit diagram of the 3-stage LNA with body biasing . . . . . . . . . . . . . . . 493.6 Input-referred noise source of a noisy two-port network . . . . . . . . . . . . . . . 503.7 MOS noise model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523.8 The distance between bulk terminal and actual bulk node . . . . . . . . . . . . . 54xi3.9 MOS noise model including the bulk resistance noise . . . . . . . . . . . . . . . . 543.10 Cascode amplifier as cascade of CS and CG stages . . . . . . . . . . . . . . . . . 563.11 Common-source amplifier with inductor degeneration (a) voltage-biased (b) current-biased . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.12 Gain reduction by steering the current to the bulk terminal . . . . . . . . . . . . 583.13 Reducing the channel current in NMOS transistor by forward biasing of bulk-source junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603.14 The negative effect of the middle node parasitic capacitance on gain . . . . . . . 613.15 (a) cascode amplifier (b) the first order model with the common-source transistorreplaced by its Norton equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . 633.16 Variation of the zero point in gm3 by changing the bulk voltage . . . . . . . . . . 663.17 The micrograph of the prototype 3-stage body biased LNA in 0.13-µm CMOS . . 673.18 Noise figure measurement results of the prototype body-biased LNA . . . . . . . 683.19 Variation of NF at 4.4. GHz with bulk voltage of CS transistor in first stage . . . 683.20 Gain measurement results of the prototype body-biased LNA . . . . . . . . . . . 693.21 S11 for three cases of high, moderate and low gain . . . . . . . . . . . . . . . . . 703.22 Measured IIP3 of the LNA versus bulk voltage of CG device in the third stage . 714.1 (a) Schematic of a single-balanced mixer, (b) current-commutation in LO stage . 754.2 Non-ideal switching in LO stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764.3 Half-circuit of single-balanced mixer . . . . . . . . . . . . . . . . . . . . . . . . . 784.4 Variation of the zero point in gm3 by changing the bulk voltage . . . . . . . . . . 814.5 Effect of parasitic capacitance at the drain of RF stage on the conversion gain . . 824.6 The chip micrographs of the fabricated prototypes in 0.13-µm CMOS technology 844.7 Schematic of the fabricated body-biased double-balanced mixer . . . . . . . . . . 844.8 Test setup for measuring conversion gain. . . . . . . . . . . . . . . . . . . . . . . 854.9 Measured IF spectrum of the first prototype mixer . . . . . . . . . . . . . . . . . 864.10 Harmonic content of the IF signal (a) VB,LO = 0V (b) VB,LO = 0.8V . . . . . . . 874.11 Plot of variation of IIP3 and conversion gain versus bulk voltage of LO stagetransistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88xii4.12 The schematic of second prototype with RF transistors in subthreshold region . . 884.13 Plot of variation of IIP3 and conversion gain versus bulk voltage of LO stagetransistors for the second prototype . . . . . . . . . . . . . . . . . . . . . . . . . . 895.1 Decomposition of additive noise component into phase noise and amplitude noise 955.2 LC tank and equivalent noise current source . . . . . . . . . . . . . . . . . . . . . 965.3 Generic phase noise plot based on Leeson's equation . . . . . . . . . . . . . . . . 975.4 Time-variance in LC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985.5 Examples of impulse sensitivity functions (a) LC oscillators (b) ring oscillators . 995.6 Conversion of noise components at harmonics of oscillation to phase noise . . . . 1005.7 Cyclostationary noise and noise modulating function [1] . . . . . . . . . . . . . . 1015.8 Non-ideal switching in cross-coupled transistors . . . . . . . . . . . . . . . . . . . 1025.9 Sampling of thermal noise of cross-coupled transistors by large-signal oscillation . 1035.10 Waveform of core transistor currents voltage-limited and current-limited regimes 1045.11 Noise-shifting property of Colpitts oscillators . . . . . . . . . . . . . . . . . . . . 1065.12 Comparison between NMF of Colpitts and cross-coupled LC oscillators . . . . . 1065.13 Tail capacitance; second harmonic flow and noise filtering . . . . . . . . . . . . . 1085.14 LC noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095.15 Current-shaping in cross-coupled LC oscillators . . . . . . . . . . . . . . . . . . . 1105.16 Modified class-C cross-coupled oscillators . . . . . . . . . . . . . . . . . . . . . . . 1115.17 Voltage and current waveforms of a class-C CMOS LC oscillator (a) single-endedoutput voltage (b) gate-source voltage (c), (d) core transistors' currents (e) tailcapacitance current (f) tail voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.18 Operation phases of class-C CMOS LC oscillator in one cycle. . . . . . . . . . . . 1145.19 Simulated current pulses of core transistors for optimum body bias and no bodybias cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195.20 (a) Micrograph and (b) the schematic of fabricated prototype (c) measured outputspectrum of the fabricated body-biased VCOs in 0.13-μm CMOS process . . . . . 120xiii5.21 (a) Phase noise variation versus bulk voltage of core transistors, (b) measuredphase noise plots of the prototype oscillator with and without forward bodybiasing of core transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215.22 (a) Micrograph of the second fabricated prototype VCOs with LC noise filter (b)the schematic of the fabricated prototype . . . . . . . . . . . . . . . . . . . . . . 1225.23 (a) Die micrograph of a 90-nm CMOS oscillator test chip and (b) the measuredoutput spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.24 Plot of measured phase-noise at 1-MHz offset versus bulk voltage of cross-coupledtransistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.25 (a) Corner simulation results (at room temperature of 27 ºC), (b) representativePVT variation plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255.26 Dependence of MOS varactor's quality factor on length of channel . . . . . . . . 1265.27 Block diagram of a gyrator-C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275.28 A basic gyrator-C active inductors . . . . . . . . . . . . . . . . . . . . . . . . . . 1285.29 (a) Schematic and (b) equivalent circuit model of the active inductor used in thiswork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295.30 Simple active inductor with an PMOS transistor and a gate resistance . . . . . . 1305.31 Active-inductor of Fig. 5.29 (a) with gate resistance realized by a triode transistor1315.32 Schematic of active-inductor-based LC VCO used in this work . . . . . . . . . . 1325.33 Chip micrograph of the prototype AI-LC VCO in 90-nm CMOS . . . . . . . . . . 1335.34 Increasing the tuning range of the prototype active inductor with body biasing. 1345.35 Phase noise plot for f0 =3GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346.1 Nonlinear model of MOS transistors . . . . . . . . . . . . . . . . . . . . . . . . . 1376.2 Nonlinearity in Cgs and effect of bias point . . . . . . . . . . . . . . . . . . . . . . 1396.3 Linearizing power amplifiers through using a predistortion stage . . . . . . . . . . 1416.4 Linearization with PMOS predistortion device . . . . . . . . . . . . . . . . . . . . 1416.5 (a) Schematic of a PA with an NMOS predistortion device (b) simplified diagramof Cgs variations and the resulting compensated input capacitance. . . . . . . . . 143xiv6.6 (a) Schematic of a PA with the proposed body-biased NMOS predistortion device(b) simplified diagram of Cgs variations and the resulting compensated inputcapacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446.7 Schematic of the designed class-AB power amplifier. . . . . . . . . . . . . . . . . 1456.8 Input series inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456.9 (a) Layout (b) chip micrograph of the proof-of-concept 2.4-GHz class-AB PA withbody-biased NMOS predistortion device. Active area is 475-µm×350-µm. . . . . . 1466.10 Simulation results for the capacitance of PA transistor, NMOS predistortion de-vice and the total compensated input capacitance. . . . . . . . . . . . . . . . . . 1476.11 Variations of IIP3 versus bulk voltage of the NMOS predistortion device. . . . . . 1476.12 (a) generic diagram of a bias-Tee (b) bias-Tee including the inside circuitry. . . . 1486.13 PA output with two possible configuration for using a bias-Tee as the RF choke. . 1497.1 The practical implementation of biasing the bulk terminals . . . . . . . . . . . . 154A.1 Magnetic (dashed lines) and electric (solid lines) fields of a CPW in (a) evenmode (b) odd mode of propagation . . . . . . . . . . . . . . . . . . . . . . . . . . 171A.2 Layout showing surface current density of (a) a fully symmetric CPW with openand short stubs (b) an asymmetric CPW with open and short stubs . . . . . . . 172A.3 Schematic diagram of the proposed 2-stage variable-gain amplifier . . . . . . . . . 174A.4 (a) Chip micrograph of the proof-of-concept prototype in 65-nm CMOS (b) Lay-out showing surface current distribution simulated in Agilent Momentum . . . . . 175A.5 (a) Micrograph of two equivalent CPW short stubs; a physically shorted shortstub (top), a short stub shorted with the proposed decoupling capacitor (bottom),(b) S-parameters of the two stubs: ideal short stub (dotted red) and short stubwith the proposed capacitor (solid blue) . . . . . . . . . . . . . . . . . . . . . . . 176A.6 Measurement (solid blue) and simulation (dashed red) results for gain of theamplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177A.7 Measurement results for S11 and S12 of the amplifier. . . . . . . . . . . . . . . . . 178A.8 The cross section of the interconnection of transmission lines to the cascodestages: (a) the implemented structure, (b) the preferred tapered solution . . . . . 179xvA.9 Measurement (solid blue) and revised simulation (dashed red) results for gain ofthe amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179A.10 S21 of the body-biased amplifier with bulk-source voltage varying from 0 to 1 V . 180xviAcknowledgmentsI would like to express my gratitude to my advisor, Professor Shahriar Mirabbasi for his un-conditional support during my Ph.D. studies at the University of British Columbia. His greatpersonality and patience as well as his technical guidance were always an invaluable help forme. I appreciate his assistance and contributions to my work and I wish him the best in hispersonal and professional life.I would also like to thank Professor Thierry Taris from the University of Bordeaux, Bordeaux,France who I got the inspiration of my research from his Ph.D. research. I enjoyed technicaldiscussions and collaboration with him and also appreciate his comments on my work. I wouldalso like to thank Dr. Roberto Rosales, the Test Lab Manager of the System-On-Chip (SoC)laboratory at UBC, for his assistance with test and his time for technical discussions we had. Ialso thank Mr. Roozbeh Mehrabadi for his technical assistance in computer-aided design (CAD)tools. I also thank my colleagues at the SoC Lab for their friendship and technical support.I acknowledge funding support from the Natural Sciences and Engineering Research Councilof Canada (NSERC). I also appreciate access to fabrication as well as CAD tool support providedby the Canadian Microelectronics Corporation (CMC Microsystems).My special thanks goes to my parents for the endless love they gave me during my life andspecially these years of my Ph.D. studies. Without their encouragements and support, I woulddefinitely not be able to overcome the obstacles and difficulties that I encountered during theseyears. I also would like to specially thank my wife, Lili. Without a doubt, she is my greatestreason to finish this thesis and I appreciate all her extraordinary support, love, and patience. Ialso thank my brother, Hootan, who has always been a great help for me in my life and I wishhim all the best in his studies at UBC and in his personal life.xviiChapter 1Introduction1.1 RF Front-EndsIn RF communication systems, the main task of the RF transceiver or RF front-end is totransmit and receive the desired signal. The transceiver consists of a receive path or receiver(RX) and a transmit path or transmitter (TX). Fig. 1.1 shows the typical block diagram ofintegrated RF front-ends. Such front-ends generally use direct conversion or low-intermediate-frequency (low-IF) conversion, i.e., they translate the RF channel of interest either directlyto baseband or to a low-frequency close to baseband. The first band-pass filter (BPF) in thereceive path selects the frequency band of interest and filters out the out-of-band componentsreceived by the antenna. To minimize the signal loss while maintaining a high selectivity, thisBPF is typically an off-chip component. The rest of the blocks in the RX are amenable tointegration, namely, the low-noise amplifier (LNA), the down-conversion mixer, and the localoscillator (LO). The main task of the down-conversion mixer is to translate the frequencyspectrum of the received signal to either a low frequency close to DC or directly to baseband.This frequency translation is accomplished by the mixer which typically multiplies the receivedsignal by the LO signal. Translating the signal to low frequency or baseband simplifies thetask of channel selection and makes it possible to use integrated channel-selection filters. Notethat in most communication systems, quadrature modulation [2] is incorporated to increase thespectral efficiency of the adopted modulation scheme. Therefore, the down-conversion occursin two paths using the in-phase (I) and the quadrature (Q) components of the (LO) signal.After the down conversion, the signal passes through a channel-select filter which in this caseis typically a low-pass filter and then is applied to an analog-to-digital converter (ADC) whichconverts the analog baseband signal into a digital signal.The digitized signal is then processed1Figure 1.1: Block diagram of generic RF transceiversby the digital baseband (DBB) processor unit of the system.In the transmit path, the reverse procedure of the receive path is performed. That is, thedigital I and Q components of data are first converted to an analog signal by using digital-to-analog converters (DAC). The output of the DACs is typically low-pass filtered to remove theunwanted components of the signal. Then, this baseband signal is upconverted by the carriersignal using the up-conversion mixers. Finally, the upconverted I and Q signals are combinedtogether (added) and applied to the input of the power amplifier (PA). Power amplifiers boostthe power of the signal delivered to the antenna to achieve the transmission range specified bythe communication standard.1.2 MotivationThe performance and reliability of RF transceivers can be quantified with the bit-error-rate(BER) at the system level. However, for electronic circuit designers, BER is translated toquantities such as dynamic range that is often considered as a quantity that bridges the gap2between system performance parameters and circuit performance parameters. The definition ofthe dynamic range is the ratio of the maximum signal level that a circuit or system can toleratebefore it gets distorted by the nonlinearities of the system, to the minimum signal level that itcan detect before the signal is lost in the noise. Thus, in the context of wireless transceivers,increasing the dynamic range is equivalent to having lower BERs and better functionality. Toimprove the dynamic range, performance parameters such as gain variation, noise and linearityof the RF transceiver building blocks such as LNAs, mixers, PAs and oscillators should beimproved. During past decades, many different circuit-level techniques and ideas have beenapplied to each of the building blocks of RF transceivers to improve their performance andconsequently to improve the overall performance of the system. At the same time, a hugeamount of efforts has been spent on device-level analysis and improvement of metal-oxide-semiconductor (MOS) transistors for RF applications.The main objective of this thesis is to investigate the application of and to utilize the bulkterminal of MOS transistors for improving the performance of different RF front-end buildingblocks. Body biasing has been used since 1994 in digital circuits to make dynamic thresholdvoltage MOS transistor (DTMOS) [3, 4]. The basic idea of DTMOS is the connection of thebulk to gate of the transistor. In this way, if a high voltage is applied to the gate, since bulk isalso very positive, the threshold voltage is lowered and thus the transistor turns on faster. Onthe other hand, if a low voltage is applied to the gate, since the same voltage is applied to thebulk, the threshold voltage would be large, and transistor would have a lower leakage. Differentvariants of DTMOS and their application have been studied in the literature (e.g., see [5]).The use of body biasing in analog and RF circuits has also been reported in the literature(for example see [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]).However, an overview of these published works reveals that similar to the idea of DTMOS indigital designs, the main idea behind many of these designs is to adjust the threshold voltagemainly to cope with the lower supply voltage and/or to reduce the power consumption. Whileoperation at a lower supply voltage and/or lower power are clear advantages, in this researchwe focus on alternative effects of body biasing on improving the performance parameters. Inparticular, we focus on the design parameters such as gain, linearity and noise and investigatethe possibility of using body biasing to improve these important performance parameters of3Figure 1.2: The trend for improving the maximum operation frequency (fmax) and transitfrequency (fT ) of CMOS technology with scaling of gate length [27]wireless transceivers which in turn directly impact the performance of the overall system. Inthis path, we are more focused on the effect of body biasing on small-signal parameters of MOStransistor through gmb and Csb.1.3 CMOS Technology for RF Front-EndsWireless communication technology has been steadily growing during the past decades and hasbecome a ubiquitous part of our lives with applications ranging from short-range communicationsuch as Bluetooth and WiFi to long range communication such as cellular and satellite networks.The ever-increasing demand for higher data rates has pushed many design efforts in industryand academia to design wireless transceivers that support higher data rates, are lower cost, andhave enhanced functionalities. However, one of the main reasons for the success of the wirelessindustry is the adoption of silicon-based technologies. In the past, silicon-based technologywas not the first choice for high frequency circuit design as other technologies would provide abetter high-speed performance. GaAs metal-semiconductor field-effect transistors (MESFETs),pseudomorphic high electron mobility transistors (PHEMTs), InP HEMTs, GaAs metamor-phic HEMTs (MHEMTs), GaAs hetero-junction bipolar transistors (HBTs) and InP HBTs aresome of these technologies which were used in RF and microwave applications. However, thesetechnologies are relatively expensive when compared to silicon. Silicon technology and comple-4mentary metal-oxide-semiconductor (CMOS) technology in particular, are now mainstream andare widely used for the design of digital circuits including microprocessors and memories andtherefore they benefit from lower manufacturing cost and higher yield as compared to the abovementioned technologies. Furthermore, due to the scaling, CMOS technology offers higher levelof integration and also the speed performance of the CMOS transistors has been continuallyimproved and, thus, in the recent past, even mm-wave CMOS designs have been taking overthe application domains of more exotic non-silicon-based technologies [27]. Fig. 1.2 shows theprogress in scaling as well as speed performance of the CMOS technologies.Despite the continued speed improvements, designing CMOS radio-frequency (RF) and mi-crowave circuits still imposes many challenges. The main reason is that the scaling and advancesin CMOS technology are motivated and intended by their dominance in the digital world (e.g.,processors and memories). Although, recently, dedicated RF design kits are being providedby the foundries, the core device of transistors is still tailored for digital applications. Thedrawbacks of scaling for analog and RF designs include the low output resistance of transistorswhich limit the gain of transistors, and scaling of the supply voltage which reduces the signalheadroom. It should be noted that the supply voltage scaling seem to have leveled off around1V. However, this value is still relatively small for some of the building blocks of systems suchas power amplifiers. Also, the transistor threshold voltage has not scaled at same rate of thesupply voltage which results in the reduced analog signal swing. The other disadvantage ofCMOS technology for RF and microwave circuits is the high conductivity of the standard sili-con substrate which makes the design of passive component very challenging as a lossy substratetranslates into more losses in passive components such as inductors and transmission lines.1.4 MOS Transistor PhysicsMOS transistor is the core of any circuit and system implemented in CMOS technology. Herewe briefly overview the physics of its operation. Fig. 1.3 (a) shows the structure of an n-typeMOS transistor (NMOS). Note that while we choose to work with NMOS transistor, the similarconclusions will apply to p-type MOS (PMOS) transistors although some polarity changes maybe necessary. As can be seen from this figure, NMOS transistor is composed of two highly5Figure 1.3: (a) MOS transistor structure (b) circuit symboldoped n-type silicon regions, namely drain and source, built on a p-type silicon substrateknown as bulk or body. There is also a heavily-doped poly-silicon region, named as gate,which is separated from the substrate by a thin silicon dioxide. Therefore, MOS transistor isa four-terminal device as shown in Fig. 1.3 (b). The operation principles of MOS transistorsis through creating a channel between drain and source terminal whose resistance is controlledthrough the gate voltage. More specifically, if a positive voltage is applied to the gate terminalof NMOS transistor in Fig. 1.4, the first effect is that in the region under the gate, the majoritycarriers of substrate, i.e. holes, are repelled and the channel is depleted of charges (Fig. 1.4 (a)).As gate voltage increases more, electrons from two n+ regions (drain and source) are attractedunder the gate and they form a channel of electrons between drain and source which is capableof carrying current between these two terminals of MOS transistor (Fig. 1.4 (b)). The voltageat which the channel is formed is named as threshold voltage and is shown by Vth. The valueof this voltage is given by the following equation [28]:Vth = ΦMS + 2ΦF +QdepCox(1.1)in which Cox is the gate oxide capacitance per unit area, ΦF is the Fermi potential of the bulk[28], ΦMS is the difference between the Fermi potential of the poly-silicon gate and the p-typesilicon substrate and Qdep is the charge in the depletion region. The equation for current ofchannel is given by [29]:ID = µnCoxWL(VGS − Vth)2 (1.2)6Figure 1.4: Formation of channel in MOS transistors (a) depletion (b) inversionwhere µn is the electron mobility, W and L are width and length of channel and VGS is thegate-source voltage.1.4.1 Body EffectUsing of bulk or body terminal has not been fully explored as compared to the other terminals ofMOS transistors. In fact, in many analyses and designs, it is simply assumed that bulk terminalis tied down to the source terminal or one of the supply rails. The reason for this connection,as seen in Fig. 1.3 (a) for NMOS transisors, is that the p-type substrate and n-type source anddrain form two back-to-back diodes. Since, these diodes are considered as parasitic devices forthe MOS transistor, it is commonly desired to bias them in the reverse region to limit theireffect on the performance of the MOS transistor. However, if their potential is set to any valuedifferent from the potential of source terminal, the bulk terminal would have some effect onoperation of MOS transistors as well. In fact, bulk terminal acts like a second gate for MOStransistors and that is why it is sometimes called as back-gate terminal [29]. If the value ofbulk voltage is positive, the positive voltage of bulk works in harmony with the gate voltageand thus the depletion and inversion of channel occurs at a lower gate voltage. In other words,the threshold voltage of transistor is lowered. If bulk voltage is negative, then the gate voltageshould go larger to compensate for the reverse effect of bulk potential. Therefore the thresholdvoltage is increased. This effect is quantitatively expressed by the following equation [29]:Vth = Vth0 + γ(√|2ΦF | − VBS −√|2ΦF |)(1.3)where γ is the body effect coefficient given by:7Figure 1.5: MOS transistor with isolated p-well in a CMOS technology triple-well optionγ =√2qSiNsub/Cox (1.4)in which q is the electron charge, Nsub is the doping concentration of substrate, Si is thedielectric constant of silicon.Body effect also affects the small-signal model of MOS transistors. This is due to the factthat ID is a function of Vth (Eq. 1.2) and Vth itself is a function of VBS (Eq. 1.3). Thus,gmb =∂ID∂VBSis defined as the bulk-source transconductance of MOS transistors and its value isgiven by:gmb = gm.γ2√|2ΦF | − VBS (1.5)where gm =∂ID∂VGSis the gate-source transconductance of MOS transistor.Another parameter related to the body effect is the source-bulk capacitance (Csb). Asmentioned before, source and bulk terminal of MOS transistor form a p-n junction and thusthere is a depletion region between these two terminals. Therefore a capacitance is associatedbetween these two terminal whose value is given by [30]:Csb =Csb0√1− VBSΦ0(1.6)where Φ0 is the built-in potential of the source-bulk p-n junction and Csb0 is the value ofsource-bulk capacitance at zero bias voltage.8(a) (b)Figure 1.6: (a) Probe station (b) on-wafer probing.It should be noted that the assumption in this work is that the CMOS technology has theisolated p-well or triple-well option (which is the case on almost all advanced processes). Asdepicted in Fig. 1.5, such structure is obtained by using a deep N-well layer and surroundingN-well side walls which provide the option to create a local substrate. Triple-well option isavailable in most of the modern analog and RF design kits.1.5 Thesis OrganizationIn Chapter 2, we overview the basic of operation of four important building blocks of RFtransceivers which are the focus of the thesis. These four building blocks are low-noise amplifiers(LNAs), down-conversion mixers, voltage-controlled oscillators (VCOs) and power amplifiers(PAs). Then in Chapter 3, application of body biasing in multistage LNAs is investigated andits effect on improving the noise figure, enhancing the linearity and providing gain variation arediscussed. Chapter 4 investigates the linearity enhancement in active down-conversion mixersand Chapter 5 presents the effects of body biasing on improving the phase noise of class-C LCVCOs. In this chapter, body biasing is also introduced as a technique to increase the tuningrange of an active-inductor-based LC VCO. Finally, in Chapter 6, the idea of body biasing inpredistortion stage of class-AB power amplifiers is introduced. In Appendix A, the proposedapproach of Chapter 3 is extended from RF LNAs to mm-wave variable-gain amplifiers (VGAs)and layout and design techniques for a mm-wave body-biased VGA are presented.The proposed techniques are confirmed by measurement results of proof-of-concept pro-9totypes which are fabricated in different CMOS technologies, namely, IBM 0.13-µm, TaiwanSemiconductor Manufacturing Company (TSMC) 90-nm, and TSMC 65-nm CMOS processes.In total nine different chips have been designed, laid-out and taped-out in this thesis seven ofwhich have worked as expected. The problems with the other two chips have been investigatedin detail and the potential reasons for their partial or full failure are presented. Measurementsof all chips have been performed using probe station (Fig. 1.6 (a)) and on-wafer probing onloose dies (Fig. 1.6 (b)).10Chapter 2RF Front-End Building BlocksIn this chapter, the basic operation of four of the blocks of RF front-ends (shown in red dottedcircles in Fig. 2.1), namely low-noise amplifiers, down-conversion mixers, voltage controlledoscillators and power amplifiers, which are the focus of this thesis, are explained. Also, theoperation of these building blocks of RF front-ends are discussed in the context of CMOStechnology. For each of the above-mentioned blocks, the principles of operation along withdifferent categories and important performance parameters are briefly overviewed.2.1 Low Noise AmplifiersLow-noise amplifiers (LNAs) are one of the important building blocks of wireless receivers.LNA design parameters such as gain, noise figure, linearity, input matching, and stability areimportant metrics and typically affect the overall performance of the receiver. The strong trade-offs among these design parameters often necessitate several design iterations. In the section,we briefly overview these design parameters as well as some of the most important existingtrade-offs in design of LNAs. Also, different categories of CMOS LNAs are shortly discussed.2.1.1 LNA Performance ParametersIn this section some of important performance parameters of LNAs including noise, linearity,gain (and gain variation), stability and input matching are discussed.NoiseNoise is one of the main performance limiting factors in RF front-ends. The importance of noisecan be better understood if one considers the well-known Shannon's equation [2]:11					Figure 2.1: The focus of this work among different blocks of RF front-ends.C = B · log2 (1 + SNR) (2.1)in which C is the maximum possible data rate of communication channel, B is the bandwidthof channel, and SNR is the signal-to-noise ratio. From this equation, to increase the data rateof a channel, there are two options: increasing the bandwidth or decreasing the noise (increas-ing signal-to-noise ratio). However, there are limits on how much we can increase bandwidthor decrease the noise of a communication system since all practical communication channelssuffer from noise and limited bandwidth. Unfortunately, the operation of electronic circuitry ofthe communication system further limits the bandwidth and/or increases the noise of the sys-tem. This is mainly because electronic circuits by their nature produce noise and have limitedbandwidth.There are two different ways to model noise in electronic circuits; first, modeling the noiseat circuit level by two input referred noise sources [31] and modeling the noise by its effect onsignal-to-noise ratio [32]. While the former is very popular in analog designs, the measurement12		Figure 2.2: LNA-antenna interface and its equivalent model [33]of input-referred noise sources at high frequencies is very difficult as there is a need for makingshort and open connections at the input terminal of the circuit under the test. Due to this fact,noise figure (NF ) is widely used by RF and microwave designers as it provides more practicalway of quantifying the noise. The definition of NF is [32]:NF = 10 · log SNRinSNRout(2.2)which quantifies the amount of degradation in SNR as the signal travels through a system.For the specific case of low-noise amplifiers that are driven by the impedance of antenna (asshown in Fig. 2.2), there are other alternative forms for Eq. 2.2. As shown in [33], for such aconfiguration, NF can be expressed by the following equation:NF = 10 · log( 14kTRS· V2n,outA20) (2.3)in which, RS is the source impedance or antenna impedance and typically has the value of 50Ω,k is the Boltzmann's factor and T is the temperature. Also, A0 is the voltage gain from inputvoltage (Vin) to the output voltage (Vout). Note that the gain from the input of LNA to itsoutput has a different value shown by (Av).As shown in Fig. 2.1, the receive path of RF front-ends is consisted of several building blocksin cascade. To find out the weight of contribution of each of these blocks on the overall noisefigure of receiver, the general noise figure equation for a chain of blocks should be calculated.It can be shown that by using Eq. 2.3 and considering the fact that for the middle stages, the13output impedance of the i-th stage works as the source impedance in Eq. 2.3 for (i+ 1)-thstage, the equation for noise factor (F ) 1 of a chain of blocks in cascade can be written as [34]:Ftot = 1 + (F1 − 1) + F2 − 1G1+ · · ·+ Fn − 1G1 · · ·G(n−1)(2.4)in which Gi is the available power gain of the i-th stage. A very useful interpretation of theabove equation (known as Friis' equation) is that, as the blocks get farther from antenna, theircontribution to the overall noise figure is attenuated by the gain of their preceding stages. Thedirect result of this statement is that low-noise amplifier has the main contribution to noisefigure as it is the closest block to the antenna. Also, one may conclude that the higher the gainof low-noise amplifier, the stronger the attenuation of noise contribution of proceeding blockswill be. From this, if only noise figure of the system is to be improved, the gain of LNA shouldbe chosen very large. However, as shown in the next section, if the linearity of the system shouldalso be taken into account the gain of LNA can not be arbitrarily large.LinearityLinearity is another important performance limiting factor in receive path of RF front-ends andalong with noise figure defines the dynamic range of the receiver. In RF receivers, the signalgoes through a large gain after the antenna (typically 70 to 100 dB) before being processedby the digital base-band circuits. The large gain of receive path, boosts the signal level as thesignal is traveling through LNA, mixer and base-band amplifiers and therefore the assumptionof small-signal is no longer valid. Thus, all the non-ideal terms in the input-output equationof building blocks of receiver can no longer be neglected and they contribute to the outputsignal of each block. Among the different orders of nonlinearity, usually second and third ordernonlinearity have the dominant effect. Thus, the output of a nonlinear system (y(t)) versus itsinput (x(t)) can be expressed as:y(t) ≈ α1x(t) + α2x2(t) + α3x3(t) (2.5)1NF = 10 logF14in which α1 is the linear coefficient and α2 and α3 are the second-, and third-order nonlinearcoefficients. Typically the values of α2 and α3 are much smaller than α1 and all of them arefunctions of bias points. It should also pointed out here that the larger the input signal level(x(t)), the more pronounced will be the effect of nonlinear terms.Different problems may arise when the nonlinear terms of Eq. 2.5 become comparable to thelinear term. Some of the possible problems are harmonic distortion, gain compression, cross-modulation and inter-modulation [33]. The root of most of these problems is the fact that anonlinear behavior produces new frequencies in the system. For example, if a sinusoid withangular frequency of ω0 is assumed as the input of a nonlinear system, based on Eq. 2.5, thesecond and third terms lead to generation of new components at 2ω0 and 3ω0. Fortunately, inRF systems, due to the essential frequency band selectivity, the second and third harmonicsare automatically filtered by the limited bandwidth of system. However, in practice, due tothe existence of multiple systems operating at different communication standards while sharingone frequency channel, multiple signals rather than the desired signal (known as interferer)are sensed at the receiver antenna by each system. As an example, the second harmonic of900-MHz GSM signal, although attenuated by the limited bandwidth of GSM transmitter,can be still large enough to be considered as an interferer for another GSM band (GSM1800)receiver operating at 1.8 GHz [33]. Also, note that even in a single communication standard,there are multiple channels operating at adjacent frequency bands which can be considered asinterferer for each other. The nonlinearity of receivers and the existence of interferer signalsare the roots for cross-modulation and inter-modulation effects. While cross-modulation onlyhappens in the systems with many independent signal channels (such as orthogonal frequencydivision multiplexing (OFDM) systems) that use amplitude of carriers for carrying data, inter-modulation is a more common problem in receive path of RF front-ends and therefore we brieflyexplain it here.Inter-modulation To understand the adverse effect of inter-modulation in receivers, considerthat the antenna senses two strong interferer signals close to the desired signal along with thedesired signal as shown in Fig. 2.3. Usually there is a band-pass filter between LNA andantenna, however our assumption that interferer signals are closely spaced with the desired15   Figure 2.3: Inter-modulation of two interferer signals and its adverse effect on the desired signal[33]signal results that the interferer signals can pass through the band-pass filter. Thus, thesetwo interferer signals are sensed at the input of LNA. To calculate the output components, asimplified equation of x(t) = A1 cosω1t+ A2 cosω2t is used to model the input signal of LNA.If this equation is replaced in Eq. 2.5, new frequency components appear at ω1 ± ω2, 2ω1 ± ω2and 2ω2 ± ω1 while the main components at ω1 and ω2 also exist. The limited bandwidth ofsystem, filters the components at ω1 ± ω2, 2ω1 + ω2 and 2ω2 + ω1 but components at 2ω1 − ω2and 2ω2 − ω1, known as inter-modulation products as well as components around ω1, ω2, areclosed enough to the the desired signal to pass through the limited frequency bandwidth of theLNA. If by any chance, any of the inter-modulation products falls onto ω0 (i.e., 2ω1 − ω2 = ω0or 2ω2 − ω1 = ω0), signal gets corrupted and therefore SNR decreases.The most common approach to quantify how strong the inter-modulation components areand how they degrade the performance of system is a quantity named as third-order inter-modulation input intercept point (IIP3). Note that the in-band inter-modulation components(i.e., 2ω1−ω2 and 2ω2−ω1) are arisen due to the third order nonlinearity of Eq. 2.5. ThereforeIIP3 is called a third-order nonlinearity metric and is defined as the input voltage amplitude (orpower) at which the magnitude of third-order inter-modulation nonlinearity becomes equal tothe fundamental component when two identical sinusoid signals are applied at the input of thesystem. This test is known as two-tone test and is commonly utilized to quantify the linearityof systems and circuits. It can be shown [33] that if the amplitude of the two interferer signalsare assumed equal (A), the amplitude of inter-modulation terms is equal to 34α3A3while theresulting component at ω1, ω2 can be considered to have amplitude of α1A2. Therefore theamplitude at which these two components become equal can be obtained as shown in Fig. 2.42This is not an accurate statement as the precise equation for amplitude of components at ω1 and ω2 isα1A+94α3A3[33]. However, the two-tone test is performed at small amplitudes for the sinusoid signals and theinterception point is derived by interpolation.16Figure 2.4: (a) Graphical definition of IIP3 (b) main and third order plots in presence of gaincompression(a) and is equal to:AIIP3 =√43∣∣∣∣α1α3∣∣∣∣ (2.6)As it is shown in Fig. 2.4 (b), as the amplitude of input signals increases, both the fun-damental gain and third order gain start to compress. Therefore, the two-tone test should beperformed at small input signal magnitudes and interpolation should be used for finding thevalue of third-order intercept point. Also, please note that the larger the value of AIIP3, themore linear the system is.The compression of gain as can be seen in Fig. 2.4 (b) can be used as another metric forquantifying the nonlinearity of a system. If a single sinusoid with amplitude of A frequency ofω0 is applied as the input to Eq. 2.5, the amplitude of the resultant component at the samefrequency at the output is equal to(α1A+3α3A34)[33]. This suggests that depending on thepolarity of α1 ·α3, by increasing the input amplitude of signal, the gain will decrease or increase.In most of the cases, α1 · α3 is negative and gain decreases or in other words it compresses. Agood example of this situation is in circuits which use MOSFET transistors operating in theirstrong inversion region of operation3. Based on this, another quantity is defined as 1-dBcompression point and as depicted in Fig. 2.5 corresponds to the point at which the gain dropsby 1-dB. The formula for 1-dB compression point can be calculated as [33]:3Less commonly, transistors show an expansive behavior as the input amplitude increases (α1 · α3 > 0). Anexample for this case is bipolar transistors or MOSFET transistor in their weak inversion mode of operation.17Figure 2.5: Graphical definition of 1-dB compression pointAin,1dB =√0.145∣∣∣∣α1α3∣∣∣∣ (2.7)From Eq. 2.6 and Eq. 2.7, one may easily observe that these two figures of nonlinearity arerelated to each other by [33]:AIIP3A1dB≈ 9.6dB (2.8)So far we have reviewed the importance of nonlinearity in the receive path of RF front-ends.But as explained before and as can be seen from Fig. 2.1, there is a chain of cascaded blocksin the receive path which includes LNA, mixer(s) and base-band amplifiers. Similar to Friis'equation for noise figure (Eq. 2.4), the contribution of each of the blocks in a cascade on theoverall nonlinearity can be computed. As shown in [33], if we show the gain at fundamentalharmonic of the blocks in the cascade as α1, β1, γ1, ... and their corresponding IIP3 as AIIP3,1,AIIP3,2, AIIP3,3, ... the following equation can be written for the overall IIP3 of the system:1A2IIP3,tot≈ 1A2IIP3,1+α21A2IIP3,2+α21β21A2IIP3,3+α21β21γ21A2IIP3,4+ ... (2.9)This is a very interesting result which is completely in opposite direction of what we ob-served for noise figure. Based on this equation, the IIP3 of each block in the chain is divided bythe aggregated gain of its preceding blocks. As the minimum IIP3 is the bottleneck and definesthe overall linearity, one may conclude that the effect of last blocks in the chain is much morepronounced in the overall linearity of the system as they experience a larger gain in their pre-ceding blocks. The direct result of this argument is that generally LNAs are not very important18	Figure 2.6: Leakage of PA to the input of LNA in a full-duplex system [33]when it comes to the linearity of receivers as they are typically the first active block in receivepath of RF front-ends. However, in some situation such as full-duplex systems of Fig. 2.6(e.g. code-division multiple access (CDMA) systems) which transmit and receive signals at thesame time, the leakage of the signal at the output of power amplifier (PA) to the the input ofLNA may be large enough to cause nonlinear terms at the output of LNA [33].Gain and Gain VariationAs explained before, the main task of the LNA as the first active block of receivers is to amplifythe noisy and weak signal received by the antenna while adding the minimum possible amountof noise to it. From this, the first impression is that the gain of LNA should be as large aspossible to boost the signal level. This statement is confirmed by taking the Friis' equationfor noise figure into account (Eq. 2.4). Based on this equation, the higher the gain of LNA,the lower the contribution of subsequent blocks on the overall noise figure of receiver will be.Moreover, Eq. 2.4 suggests that LNA is the most critical building block of receivers in termsof noise figure. However, Eq. 2.9 for linearity suggests the reverse trend for the gain of LNA.Based on Eq. 2.9, the larger the gain of LNA, the lower the overall linearity will be or at leastthe requirements on the linearity of the final stages will be more strict. Therefore, there is atrade-off between gain of low noise amplifier versus linearity and noise figure of receiver. Typicalvalue for gain of LNA is 15 to 20 dB.Another factor which limits the gain of LNA is the stability of LNA. This is essentiallyimportant if we notice that source/load impedance of circuits in a wireless device may change19depending on how the user is using the device [33]. Therefore, LNA should be unconditionallystable for all the values of source and load impedance such that source/load impedance changecannot make it unstable. Moreover, the stability should be ensured at all frequencies sinceeven if the LNA becomes unstable and oscillates at another frequency rather than its frequencyof operation, the large signal oscillation still may compresses the gain of LNA and thereforecorrupts its performance. To ensure the stability, the following two criteria should be met [32]:K =1 + |∆|2 − |S11|2 − |S22|22 |S21| |S12| > 1 (2.10)∆ = S11S22 − S12S21 < 1 (2.11)in which Sij(i, j = 1, 2) are the scattering parameters of the LNA. If the LNA has a sufficientlygood amount of reverse isolation (S12 ≈ 0), and considering the fact that in modern RFICdesign, the output of LNA is not matched to 50Ω and is connected to the input of mixerwithout any power matching network, S22 ≈ 1. Therefore in such a case, as shown in [33] Eq.2.10 can be simplified to:K ≈ 1− |S22|22 |S21| |S12| > 1 (2.12)Also Eq. 2.11 is simplified to S11 < 1. Eq. 2.12 puts an upper limit on S21:|S21| < 1− |S22|22 |S12| (2.13)As the value of S21 is directly related to the gain of LNA, this equation also shows that forreasonable values of S12 and S22, there is an upper bound for the magnitude of the forward gainof a stable LNA.Another gain-related characteristic of the LNA is its gain variation range. This is speciallyimportant in wireless devices where the level of the signal detected by antenna fluctuates a lot asthe user changes his/her location in respect to the transmitter. For example, in cellular mobilephone networks, it is very common that the difference between the maximum and the minimumlevel of detected signal be as large as 100 dB. Therefore, based on the distance of the user to20the base station, gain of the receive path of system should be adjustable. One of the buildingblocks in which the gain variation or gain switching of the receive path can be implemented, isthe LNA.Input MatchingAnother important feature of low-noise amplifiers is that they should exhibit a low return lossof the power delivered to them by the antenna. Usually, the antenna dimensions is comparableto the wavelength of the transmitted and received signals and therefore it is considered as adistributed element in the system. The interconnection between the LNA as the first integratedblock of system and the antenna4is through printed circuit board (PCB) tracks which areusually long enough to be considered as microstrip transmission lines at the operating frequency.Therefore if the input of LNA is not power matched to the antenna impedance and transmissionlines characteristic impedance, part of the delivered power is reflected back to the antennaand is re-transmitted by the antenna. Therefore input of LNA is designed to be matched tothe antenna impedance which is usually 50Ω (real, with no imaginary part). This essentialinput power matching sets restrictions on the choice of the amplifier configuration for low-noiseamplifiers.2.1.2 LNA CategoriesThe three common configurations of MOS amplifiers are common-source (CS), common-gate(CG) and source-follower. Due to the fact that we need a considerable amount of gain forLNAs, source-followers are not considered as a good option. However, CS and CG amplifierscan be considered as appropriate candidates since they both can provide high gain. Due tothe lower input impedance of common-gate amplifiers and considering the fact that 50Ω is avery small input resistance, common-gate amplifiers are superior in terms of input matching.However, there is another trade-off which keeps common-source amplifiers as an appealing choiceand that is their lower noise figure. For common-gate amplifiers, as shown in [33] noise figureis at best 3 dB while lower noise figures can be achieved using common-source configuration.Fortunately, adding a degeneration inductor into common-source amplifier can facilitate the4There may be an band-pass filter in between which is also off the chip.21    	Figure 2.7: Spectrum of (a) base-band and (b) up-converted datainput matching to 50Ω and results in broad usage of common-source amplifier with inductordegeneration as the low-noise amplifier in RF front-ends.2.2 Down-Conversion MixersIn wireless systems, based on the allocated spectrum of the standard, a relatively narrow band-width is assigned to each user. Therefore the base-band signal at transmitter should be trans-lated to its specific assigned frequency band. This procedure known as up-conversion is realizedthrough multiplication of the modulated signal by a high frequency signal known as carrier.We show this carrier as a sinusoid (A0 cos 2pifct). The multiplication takes place in time do-main and in frequency domain is equivalent to convolution of the spectrum of base-band databy two impulses at ±fc. The frequency spectrum of the result of multiplication is two replicasof the base-band spectrum at ±fc (Fig. 2.7). This carrier frequency can be a fixed frequencyor a variable frequency in wireless standards which assign different bands to the same user atdifferent times. An example of the latter is GSM standard during the hand-off process in whicha mobile unit goes from one cell to another. Similarly in the receive path of RF front-ends,adjacent channels belonging to the wireless standard of interest are located at different carrierfrequencies and are passed through the band-pass filter (BPF) after the antenna and are sensedat the input of the low-noise amplifier. In order to detect and demodulate the desired signal, thereceiver should be able to select the desired channel while it attenuates the adjacent channelssignificantly. To achieve this, a bandpass filter with very large quality factor (Q) is required.For a bandpass filter, Q is defined as [33]:Q ≈ ω0ω3dB(2.14)in which ω0 is the center frequency of the band-pass filter and ω3dB is the 3-dB bandwidth22of the filter. From this equation, it can be concluded that for a given 3-dB bandwidth, thehigher the center frequency of the filter is, the larger the Q should be. The direct relation of Qto the center frequency results in an unreasonably large values for the quality factor speciallyin standards with narrow-band signals. However, if the received spectrum can be translatedto a lower frequency, the tight requirements of large Q will be relaxed as smaller values isrequired for the quality factor of the band-pass filter at lower frequencies [33]. Similar to the up-conversion procedure, the frequency translation is achieved by multiplying the sensed spectrumby a sinusoid shown by A0 cos 2pifLOt and the procedure is called as down-conversion. Thesinusoidal signal utilized for down-conversion is named local oscillator (LO) and its frequency isdenoted by fLO. If the center frequency of desired channel, i.e., radio frequency (RF) signal, isshown as fRF , the spectrum after down-conversion will be the replica of the spectrum of desiredchannel shifted to ± (fRF ± fLO) as shown in Fig. 2.8. The components at ± (fRF + fLO) areat very higher frequencies and can be filtered by a low-pass filter. This leaves only the down-converted components at ± (fRF − fLO) behind. The fRF−fLO frequency is called intermediatefrequency (IF) and in most wireless transceivers has a fixed value. However, as different carrierfrequencies can be assigned at different times in the transmitter, the center frequency of thedesired channel (fRF ) changes with time. This necessitates a variable frequency for the localoscillator in a way that the difference between RF and LO frequencies is kept constant andequal to IF frequency. It should be noted here that if fLO = fRF , the receiver is called a direct-conversion receiver which directly converts the RF signal to a base-band signal and if fLO 6= fRF ,the receiver is called a Heterodyne receiver. Block-diagram of a typical Hetrerodyne receiverand a direct-conversion receiver is shown in Fig. 2.9.Mixer as a building block with three terminals, namely, RF port, LO port and IF port, hasits own custom-defined set of design performance metrics. The main performance parametersfor a mixer are conversion gain, linearity, noise figure, and port isolation. Although some ofthese performance parameters, e.g. noise and linearity, seem similar to performance parametersof LNAs, due to the three-port nature of mixers, the definition for each of these parametersis different from the one in LNAs. Here, we briefly overview each of the above-mentionedperformance parameters with emphasis on down-conversion mixers.23	  			  		Figure 2.8: Down-conversion and resulting spectra2.2.1 Mixer Performance ParametersConversion GainUnlike amplifiers, conversion gain for mixers is not defined at a single frequency which in caseof amplifiers is the center frequency of the amplifier. Instead, conversion gain (CG) is definedas the ratio of the amplitude of down-converted signal at IF frequency, to the amplitude of theinput RF signal:CGV =VIFVRF(2.15)Equivalently, conversion gain can be defined in terms of the ratio of the power of IF signalto the power of RF signal. This definition of conversion gain is more common in microwaveengineering where the blocks before and after the mixer are power matched to the RF and IFport of the mixer. In modern integrated systems, there is no power matching between differentbuilding blocks of systems and voltage is the quantity of interest. It should also be noted herethat depending on whether mixer is an active mixer or a passive mixer, it may provide eitherconversion gain or conversion loss. This means that in case of passive mixers, Eq. 2.15 has avalue smaller than one.Conversion gain also play an important role in contribution of noise of subsequent base-bandstages of the receivers on the overall noise figure of receiver. As can be seen in Fig. 2.9, down-conversion mixers are placed right after the LNA. Therefore, the noise of later stages, namelybase-band amplifiers, are divided by the cumulative gain of LNA and mixer. Thus, based on24				(a)				(b)Figure 2.9: (a) Heterodyne receiver (b) direct-conversion receiver with quadrature down-conversionEq. 2.4, the higher the conversion gain of the mixer, the lower will be the effect of noise of thebase-band amplifiers on the overall noise figure. On the other hand, increasing the gain willboost the signal level at the input of base-band amplifiers, and thus results in production ofmore nonlinear term by the base-band amplifiers. In other words, increasing the conversion gainof mixer, decreases the overall linearity of the system as predicted by Eq. 2.9. From this, onemay observe that similar to LNAs, linearity and noise figure of the overall receiver are traded-offas the conversion gain of mixer is changed.LinearityLinearity is one of the most important features of mixers due to its pronounced effect on theoverall linearity and thus dynamic range of the receiver. The definition of linearity in mixers isalso slightly different from the definition of linearity in amplifiers. This is mainly because of thedifference in the frequency of the IF signal as the output of the mixer and the frequency of theRF input signal. Therefore, for measuring the nonlinearity of mixers, the amount of harmonics25in IF signal for a given amplitude of RF signal is considered. For example, the two-tone testin a mixer for measuring the value of IIP3 is performed by applying two tones at ωRF1 andωRF2 to RF port of mixer. Ideally these two tones should be transferred to the IF band, leadingto two components around ωRF1 − ωLO and ωRF2 − ωLO. However, due to the nonlinearity,other components including the third-order intermodulation components 2ωRF1 ± ωRF2 − ωLOwill appear at the IF port. Thus, IIP3 is defined as the input RF power at which the ratio ofmagnitude of the components around 2ωRF1 ± ωRF2 − ωLO at IF port becomes equal to themagnitude of the desired IF component.Noise FigureNoise figure is the metric used for quantifying the noise performance of mixers. As discussed,in LNAs, noise figure (NF ) is defined as the ratio of SNR at the input to the SNR at theoutput of amplifier. However, given the fact that mixers have three ports, the definition of NFin mixers should also be slightly modified. Here, the NF is defined as the ratio of SNR ofdown-converted signal at the RF port to the SNR of input signal at IF port. Thus, the twoSNRs are calculated at two different frequencies. Moreover, depending whether the mixer isa zero-IF mixer or not, two different types of noise figure are defined for mixers. As shown inFig. 2.10 (a), If the IF frequency of the mixer is not zero, the spectrum of signal is located atone side of the LO frequency only. Therefore, after down-conversion, white noise around bothωRF and ωRF − 2ωIF frequencies are folded back to the IF frequency band. The band aroundωRF −2ωIF is often known as the image band. Based on this, twice the noise around RF bandis down-converted to the IF band. This in turns mean that even if the mixer circuitry generatesabsolutely no noise, the noise figure is 3-dB. This type of noise figure is known as single-side-band (SSB) noise figure. On the other hand, Fig, 2.10 (b) shows the signal and noise spectrumfor a zero-IF down-conversion mixer. From this, it is observed that only the noise around RFband is down-converted to the IF band. As in this case the RF signal appears at both sides ofthe LO frequency (ωRF = ωLO), this type of noise figure is known as double-side-band (DSB)noise figure.26Figure 2.10: (a) SSB and (b) DSB noise figure in mixersPort IsolationIdeally signals at each port of the mixer should be totally isolated from the other two ports.However, due to the existence of transistor intrinsic capacitances, a portion of signal at eachport is leaked to other ports of mixer. While some of these leakages such as LO-RF leakage canbe attenuated by the adoption of fully differential circuitry, others such as RF-IF feed-throughin direct-conversion receivers may cause saturation in base-band stages and can totally corruptthe performance of the whole receiver [33]. Another example of troublesome feed-through isLO-IF in Heterodyne receivers.2.2.2 Mixer CategoriesAs mentioned before, ideal mixers can be considered as multipliers (Fig. 2.8). Therefore,multiplication is at the core of any mixer circuitry. However, some mixer architectures mayutilize the multiplication directly while others work on the basis of multiplication that aregenerated among nonlinear intermodulation terms. An example of the latter is a single MOStransistor with the sum of RF and LO signals applied as its input (Fig. 2.11) [1]. This simplestructure take advantage of the nonlinearity in square-law current equation of MOS transistors,i.e., ID =12µnCoxWL (VGS − Vth)2 (µn is the electron mobility, Cox is the gate oxide per unitarea and W and L are width and length of channel of MOS transistor). Moreover, the equation27Figure 2.11: Schematic of a single MOS transistor Mixerfor drain current is equal to:id(t) = gm(t)vgs(t) (2.16)where:vgs(t) = VRF cosωRF t (2.17)g(t) = gmQ(1 +VLOVGS − Vth cosωLOt)(2.18)and VGS is the gate-source voltage and gmQ =∂ID∂VGS= µnCoxWL (VGS − Vth) is the transconduc-tance of the MOS transistor at its bias point. Therefore the equation for the IF component ofdrain current is equal to:id(t) = gmQVLOVRFVGS − Vth cos (ωRF − ωLO) t (2.19)These type of mixers which rely on the nonlinearity of active devices for generating thedesired multiplication, suffer from several drawbacks. The first drawback is that the nonlinearityof active devices usually generate many intermodulation products which many of them areundesired in case of mixers. The other disadvantage of using this category of mixers is the poorisolation between the RF and LO signals. As it can be seen in Fig. 2.11, both the RF and LOsignals are applied to a single input terminal of the mixer. This weak isolation is the source28Figure 2.12: General structure of Gilbert mixersof many problems especially in direct-conversion receivers [33]. Due to these problems, anothertype of mixers, i.e., direct multiplication mixers are more commonly used in modern receivers.In this type of mixers, RF, LO, and IF signals have their own dedicated terminal.The typical structure of of direct-multiplication mixers are shown in Fig. 2.12. As can beseen from this figure, the mixer is composed of three different stages, namely, transconductance,current switch and resistive load. Based on this, the input RF voltage is converted to currentsignal by the transconductance stage. Then, the RF current signal is switched on and off tothe load. Finally, the current is converted back to the voltage domain by being passed througha resistive load. The most famous direct-multiplication mixers are Gilbert mixers. Fig. 2.13shows two different variants of Gilbert mixer, namely, single-balanced and double-balanced.In both of these configurations, the LO signal is assumed to be large enough to steer the RFcurrent signal (generated by the transconductance stage) from one branch to another branch ofthe differential pair at the LO frequency. Thus, the RF current (tail current) is multiplied by aperiodic square wave with frequency of fLO and thus the IF current in each of the branches isgiven by:iIF (t) = |cosωLOt| . (IRF cosωRF t) (2.20)29(a) (b)Figure 2.13: Schematic of (a) single-balanced (b) double-balanced Gilbert mixersand thus:iIF (t) =[12+2picosωLOt− 2pi.13cos 3ωLOt+ · · ·]. (IRF cosωRF t) (2.21)which clearly generates a component around ωRF − ωLO.Note that while in single-balanced mixer (Fig. 2.13 (a)) only LO port is differential, indouble-balanced mixer of Fig, 2.13 (b), both RF and LO ports are differential. The maindrawback of single-balanced mixers is a large LO-IF feedthrough [33]. Moreover, the conversiongain of double-balanced mixer is larger comparing to its single-balance counterpart.2.3 Voltage-Controlled OscillatorsAs discussed before, in RF front-ends, for performing the frequency translation, i.e. up-conversion in transmitters and down-conversion in receivers, there is a need for LO signal (withvariable frequency) and a multiplier. While the latter is realized by mixers, for implementationof the former, a frequency synthesizer is required. Most synthesizers are realized by phase-locked loops (PLLs) [29]. Fig. 2.14 shows the block-diagram of a frequency-multiplying PLL.The output of the PLL in Fig. 2.14 can be applied as the LO signal in the receiver or as the30	Figure 2.14: Block diagram of type-II frequency-multiplying PLLcarrier in the transmitter.As can be seen from Fig. 2.14, one of the blocks of the PLL is a voltage-controlled oscillator(VCO). By definition, VCO is an oscillator whose output frequency varies by changing a controlvoltage (Vcont). Moreover, a linear dependence of oscillation frequency on control voltage isdesired:ωout = KV CO · Vcont + ω0 (2.22)where KV CO is the gain of VCO with unit of rad/Hz/V and ω0 is the free-running frequency(Vcont = 0) and ωout is the instantaneous frequency of VCO. The value of instantaneous fre-quency can be converted to instantaneous phase through:φ =ˆωout · dt+ φ0 (2.23)in which φ0 is an unimportant initial phase and φ is the total instantaneous phase of the VCO.Based on Eq. 2.23, the time-domain output signal of VCO can be written as:Vout(t) = V0 cos(ˆωoutdt)= V0 cos(ω0t+KV COˆVcontdt)(2.24)31Figure 2.15: Negative feedback system and required phase shift for oscillation (a) in open-loopsystem (b) around the loop [29]Oscillator Operation PrinciplesWe start our discussion about design principles of VCOs by a brief overview on operationprinciples of oscillators. An oscillator can be considered as a feedback system in which theconditions of negative feedback is lost. In another words, oscillator is an unstable closed loopsystem which generates a strong output signal while it does not have any signal at its input.From control theory, in the negative feedback system of Fig. 2.15 (a), the boundary betweenstability and instability is defined by Barkhausen's criteria [35]:|H (jω0)| = 1 (2.25)]H(jω0) = 180◦ (2.26)in which ω0 is the frequency at which the feedback system starts to oscillate. Note that theabove equations are for the cases that the feedback gain is unity and otherwise the feedbackgain should also be included. Also, note that considering the subtraction sign in the negativefeedback of Fig. 2.15 (a), one can equivalently express Eq. 2.26 as phase shift of 360◦aroundthe loop as shown in Fig. 2.15 (b). It is intuitively understood that any loop gain larger thanone will cause the oscillation to grow at even higher speed.The positive feedback in Fig. 2.15 can alternatively been considered as a one-port networkin which the loss component of a resonator is canceled by a negative resistance created by anactive circuit [33]. This view of oscillators (Fig. 2.16) is equivalent to the feedback model of32	  Figure 2.16: One-port view of oscillatorsFigure 2.17: Schematic of a ring oscillatorFig. 2.15 and is sometimes used for analysis.2.3.1 Oscillator CategoriesWhile different types of circuits satisfying the oscillation criteria of Eq. 2.25 and Eq. 2.26 canbe found in the literature, almost all of them fall into one of the three main oscillator categories:ring oscillators, resonator-based (LC ) oscillators, and distributed oscillators. Ring oscillatorsare consisted of several inverting amplifiers in a cascade while the output of the cascade is fedback to its input. Fig. 2.17 shows the typical configuration for a ring oscillator in which anumber of inverters are utilized as the inverting amplifiers. While ring oscillators are widelyused for generation of digital clocks in based-band signal processors of wireless systems, theiruse in the RF front-end, i.e. the part between antenna and the digital base-band processor, isless common due to their higher phase noise compared to other types of oscillators [1].The most popular solution for (voltage-controlled) oscillators in front-end of wireless systems,are resonator-based or LC oscillators. LC oscillators are very robust and exhibit an excellentphase noise performance [1]. The two main types of LC oscillators are cross-coupled oscillatorsand three-point oscillators. Operation principle of three-point has been depicted in Fig. 2.18and can be explained using the one-port model of Fig. 2.16. The derivation of the equationsfor equivalent resistance and capacitance seen between gate and drain of the transistor in Fig.2.18(a) can be found in [1]. The equivalent circuit in Fig. 2.18 is valid regardless of which node is33 	 Figure 2.18: One-port model for three-point oscillators [29]		 Figure 2.19: Colpitts oscillator circuitry (a) single-ended (b) differentialthe ground node. Therefore three different types of oscillators can be constructed by connectingdrain, source, and gate of the transistor into the ground. The most famous configuration knownas Colpitts is the one with gate node as the reference node and is depicted in Fig. 2.19 (a). Sincein most of the applications, a differential output is required for the oscillator, the oscillator inFig. 2.19 (a) can be converted into a differential oscillator of Fig. 2.19 (b).The most popular category of LC oscillators are cross-coupled oscillators. Depicted in Fig.2.20 their operation can be explained by one-port model as a lossy LC tank in parallel witha negative conductance generated by the cross-coupled transistors. It can be shown that thenegative resistance created by the cross-coupled transistors has a value equal to − (2/gm) and thecondition for cancellation of the loss of the tank is gmRP ≥ 1 [29]. Equivalently, a cross-coupledoscillator can be assumed as cascade of two common-source amplifiers with an LC tanks asthe load of amplifiers (Fig. 2.21). If the Bode plots of this configuration is plotted, one cannotice that at the resonance frequency of the tank, the total phase shift around the loop is 360◦,satisfying Eq. 2.26. Therefore the sufficient condition (Eq. 2.25) for oscillation is a loop gain34      Figure 2.20: (a) Cross-coupled LC oscillator (b) one-port model equivalent [29]larger than unity or equivalently (gmRP )2 ≥ 1 [29]. The resonance frequency of the tank f0 willbe the oscillation frequency.Both Colpitts and cross-coupled LC oscillator, by their nature, need at least one inductor5.This inductor is usually realized by integrated spiral inductors. While there are many advancesin design and modeling of on-chip spiral inductors, there are still considered as the bottleneck ofdesign in many high frequency integrated circuits due to their low quality factors and large area.To address this issue, active circuits have been used to create an inductive impedance. Known asactive-inductors, this kind of inductors have inspired designers toward a active-inductor basedLC oscillators. While the principles of oscillation is similar to the cross-coupled LC oscillators,these oscillators benefit from larger quality factor in their tank, tunable tank inductance, largertank inductance and smaller area [36]. In chapter 5, we investigate this type of oscillators inmore detail.The last category of oscillators are distributed oscillators. The idea of distributed oscillatorsis based on the propagation of signal through a transmission line [27]. As depicted in Fig. 2.22,in a distributed oscillators, a number of amplifiers are placed at positions which are physicallyapart from each other by a fraction of wavelength. One transmission line connects the inputsand another transmission lines connects the outputs of all of the amplifiers. By connecting the5Please note that the two inductors in differential Colpitts (Fig. 2.19(b)) and cross-coupled oscillator (Fig.2.20(a)) can be combined to one differential inductor with center tap35Figure 2.21: Feedback representation of cross-coupled oscillators [29]  …Figure 2.22: Distributed oscillator [27]output and input transmission lines together, a positive feedback is created and output wavestarts to circulate in the two transmission lines. Therefore at any point along the transmissionlines, there is an oscillation. Loss of transmission lines are compensated by the gain stages alongthe transmission lines. As it is clear from the above explanations, the nature of operation ofthese oscillators necessitates that the physical dimensions of the circuit are comparable with thewavelength. This condition is not met at mid-GHz frequencies where most of available wirelessstandards are allocated bandwidth. However, with emergence of new wireless standards atmm-wave frequencies, such as IEEE802.15.3, the idea of distributed circuits seems an appealingoption as the wavelength becomes comparable with the dimension of the integrated circuits(λ = 2.5mm at 60 GHz).2.3.2 VCO Performance ParametersPerformance of voltage-controlled oscillators has a pronounced impact on the overall perfor-mance of the RF front-end they are being used in. This is due to the fact that VCO as the coreof frequency synthesizer of the system plays an important role in specifying the purity of the LO36   Figure 2.23: spectrum of (a) ideal oscillator (b) noisy oscillatorFigure 2.24: Reciprocal mixing [33]signal as well as the frequency range that the transceiver can cover. Here, we briefly overview,the most important performance metrics of VCOs, namely, phase noise, and tuning range. Theinterface of VCO to other blocks of the system imposes additional performance requirements onthe design of this important building block of the system such as output voltage swing, drivecapability, and supply sensitivity [33].Phase NoisePhase noise is one of the most performance metrics of VCOs and its importance is steadilygrowing as the spectrum of standards is getting more populated to use the bandwidth moreefficiently. Starting from definition of phase noise, we again refer to Fig. 2.8. In this figure,we expressed the LO signal mathematically by an ideal sinusoid, A0 cos 2pifLOt. In frequencydomain, the spectrum of such signal is ideal impulses at±fLO as shown in Fig. 2.23(a). However,in practice due to the presence of noise in the circuit elements, the output of oscillator circuitsis in the form of A0 cos (2pifLOt+ ϕn(t)) in which ϕn(t) is a random phase variation. In anotherwords, in a real oscillator, the period of oscillation does not have a fixed value and is changed37 	 Figure 2.25: Capacitance-voltage curve in (a) regular MOS varactors (b) accumulation-modeMOS varactorsrandomly from one period to the other. Assuming that ϕn(t)  1rad, the output of oscillatorcan be approximated by:x (t) = A0 cos (2pifLOt+ ϕn(t))≈ A0 cos (2pifLOt)−A0ϕn(t) sin (2pifLOt) (2.27)in frequency domain, the resulting spectra is the impulse functions at ±fLO plus the up-converted spectrum of ϕn(t) as depicted in Fig. 2.23(b).The phase noise phenomenon described above has negative impact on performance of wirelesssystems. Two of the most famous adverse effects of phase noise are reciprocal mixing andincreasing the bit-error-rate (BER) of the system. Starting from the former effect, consider thedown-conversion process of Fig. 2.8 in presence of an interferer signal (e.g. adjacent channel)and a noisy LO signal. As illustrated in Fig. 2.24, the convolution of the noisy LO signal withthe interferer may decrease the signal to noise ratio on the IF band to the extent that the desiredchannel can not be recovered. Also, almost all of the base-band modulations which carry theinformation in the phase of carrier suffer strongly form phase noise of carrier or LO signal asdata directly mixes with the noise of oscillator. This effect in turn, increases the BER as itincrease the likelihood of error in demodulator [33].38 	 		 Figure 2.26: Accumulation-mode MOS varactor (a) Cmin (b) CmaxTuning RangeAs explained in the previous section, LC VCOs are widely used in RF front-end of wirelesssystems due to their low phase noise comparing to other categories of CMOS oscillators. Ratherthan phase noise, there is another important performance metric for VCOs and that is tuningrange. As explained in Section 2.2, voltage controlled oscillators (VCOs) are typically used asone of the blocks in phase locked loops (PLLs) which acts the role of frequency synthesizer inreceivers. Thus, their frequency of oscillation should be varied linearly with a control voltage(Eq. 2.22). The larger this variation range is, the wider portion of the spectrum is covered by thefrequency synthesizer (PLL) and thus more channels can be down-converted to the base-bandto be demodulated.In order to change the frequency of an LC oscillator, as the frequency of oscillation is equalto the resonance frequency of the LC -tank, i.e. ωres = 1/√LC, the values of L and/or C of thetank should be varied. Although tuning the inductance of the LC tank to tune the frequencyof oscillation in LC oscillators has been reported in the literature (e.g., see [37]), it wouldcomplicate the oscillator design due to the required low-resistance switches or transformers andthus, in practice, tunable inductors are not commonly used. On the other hand, tuning of avariable capacitor (varactor) of the LC tank is performed using a control voltage and thereforethe use of such capacitors for tuning the frequency of the oscillator is typically the preferredchoice. There are different types of variable capacitors or varactors in CMOS technology suchas p-n junction varactors and MOS varactors. MOS varactors are used more extensively as39	Figure 2.27: Schematic of a CMOS LC VCOthey can provide more tuning range and higher quality factor. It should be noted here thatalthough the gate-source capacitance of a regular NMOS (or PMOS) transistor is dependent onits gate-source voltage, the variations of capacitance with voltage is not monotonic (as shownin Fig. 2.25 (a)) and thus is not suitable to be used as the varactor in an LC VCO. The reasonis that with such a varactor the performance of the PLL in which the VCO is used is corrupted.In fact a monotonic relation between capacitance and control voltage is desired for varactors.For this reason, accumulated-mode MOS varactors are alternatively used. The main differenceof accumulated-mode varactors is that NMOS transistor is placed inside an n-well (rather thanp-well). With such a modification, the monotonic capacitance-voltage relation of Fig. 2.25 (b)is achieved. Cmin in this figure is obtained for negative gate-source voltages when the channel isdepleted of charges and its value is equal to the series equivalent of gate-oxide capacitance withcapacitance of depleted channel (Fig. 2.26 (a)). Cmax happens at positive gate-source voltagesand its value is roughly equal to the gate-oxide capacitance (Fig. 2.26 (b)). Fig. 2.27 showsthe schematic of a CMOS cross-coupled LC VCO using MOS varactors to tune the oscillationfrequency.40	Figure 2.28: Power amplifier position in generic diagram of transmitters2.4 Power AmplifiersPower amplifiers (PAs) are one of the essential and most challenging building blocks of thetransmit path of RF front-ends. As can be seen in Fig, 2.28, PAs are the last active blockbefore the antenna in transmitters and their main role is boosting the power level of the signalbefore being transmitted by the antenna.2.4.1 PA Performance ParametersPower amplifiers typically impose tight design constraints and trade-offs among linearity, effi-ciency and output power. Especially, in low-power wireless transceivers, efficiency of the PA, asone the most power-hungry blocks of the system is of great importance. Improving the efficiencyof the PA results in less DC power consumption for the same amount of output power deliveredto the antenna:η =PLPsupply(2.28)where, η is the drain efficiency, PL is the output (load) power, and Psupply is the DC powerdrawn form the supply. However, the trade-off between linearity and efficiency in power ampli-fiers usually results in lower linearity when higher efficiencies are targeted [33]. The importanceof the linearity of the PA is mainly dependent on the modulation scheme used in the system. Ingeneral, in the context of linearity of PAs, two categories of modulation schemes are defined, i.e.,constant-envelope and variable-envelope modulation schemes [33]. While in constant-envelopemodulations such as Guassian minimum shift keying (GMSK), no information is carried in41(a)(b) (c)Figure 2.29: (a) Typical schematic of a power amplifier (b) drain voltage and current waveformsof transistor in class-A (c) in class-AB power amplifiersthe amplitude of the modulated signal, a variable-envelope signal such as quadrature ampli-tude modulation (QAM) signal, carries the data both in its amplitude and phase, and thusresults in a better spectral efficiency. Since nonlinearity affects the gain compression, nonlinearamplification of a variable-envelop signal and the resulting compressed output results in datadistortion. In contrast, constant envelope modulations where the information is carried in thephase of the modulated signal are immune to this undesired effect. Therefore, the efficiency-linearity trade-off in PAs is extremely important in wireless systems which use variable-envelopmodulation schemes to achieve higher spectral efficiency.2.4.2 PA CategoriesPower amplifiers are usually categorized into different classes in terms of their linearity andefficiency. The most linear class of PAs is a class-A amplifier [1] in which the transistors arebiased in their active region and thus they operate linearly. In fact the main difference betweena classic small-signal amplifier and a class-A power amplifier is the larger output voltage andcurrent swing of the class-A PA [1]. However, it can be shown that the maximum theoreticaldrain efficiency for class-A PAs is 50% [33, 1] and in practice the efficiency is much lower than42this maximum. This low efficiency is due to the fact that drain current and drain-source voltageof the PA main transistor both have nonzero values over the entire signal cycle (Fig. 2.29 (b)).If by changing the bias of transistor, either voltage or current becomes zero for a portion of eachcycle, the efficiency is increased. For example, if a MOS transistor is biased right at the edge ofits threshold voltage (Vth), at a positive swing of its input voltage, it conducts the current intothe output load while it will turn off for the negative swing portion of the input voltage. Thismeans that the conduction duty cycle is 50%. This category of power amplifiers is known as aclass-B PA. The drain current in a class-B PA is largely nonlinear as compared to its class-Acounterpart. Although by filtering the current and extracting its main harmonic, a sinusoidaloutput can be obtained, if the input of a class-B PA is a variable-envelope modulated signal,the information is distorted due to the clipping of the negative portions of the drain currentsignal. However, as compared to class-A PAs, the efficiency is theoretically improved to 78.5%[1]. It should be noted that class-B PAs are not commonly used in practice as it is challengingto accurately control the conduction angle of the drain current to 180◦(or 50% duty cycle).Two practical variants of class-B PAs are class-AB and class-C PAs. In class-C, the conductionangle of current (Φ) is between zero and 180◦ (0◦ < Φ < 180◦) while in class-AB (Fig. 2.29(c)), Φ is between 180◦ and 360◦(180◦ < Φ < 360◦). In general, as compared to class-B PAs,class-C PAs are more efficient and less linear and class-AB PAs are more linear and less efficient.Although other classes of PAs with higher efficiency exist, e.g., class-E and class-F [33], they arenot suitable for systems with variable-envelope modulation schemes due to their poor linearity.43Chapter 3Body Biasing in Low-Noise Amplifiers(LNAs)Low-noise amplifier (LNA) is typically the first active block in the receive path of communicationtransceivers. Since the signal received by the antenna is usually a weak signal, prior to anysubsequent signal processing, it has to be amplified. To maintain the signal integrity, theamount of noise that is introduced by the amplifier should be as low as possible. Thus, twomain characteristics of any LNA are its gain and its noise performance. Other importantdesign parameters are input return loss, stability, frequency of operation, bandwidth, and insome systems linearity. Similar to any analog circuit, there are different trade-offs among theseperformance parameters which complicate the design of an LNA. In this chapter, we proposea multipurpose use of body-biasing to improve the performance of this important block. Thethree design parameters that we focus on are noise figure, gain variation and linearity.3.1 Multipurpose Application of Body Biasing in LNAsAs shown in Section 2.1.1 of Chapter 2, in a receiver which is composed of several blocks incascade, the first block has the dominant role on the noise performance of the systems and forthe blocks that are farther from the antenna, their noise contribution is attenuated by the gainof their preceding stages (Friis' equation [34]). Similar to Friis' equation (Eq. 2.4) for noiseperformance, for the overall IIP3 of cascade of blocks, the IIP3 of each block is divided by thecumulative gain of its preceding blocks (Eq. 2.9). As the minimum IIP3 is the bottleneck anddefines the overall linearity, one may conclude that the effect of blocks following the LNA inthe chain is more pronounced in the overall linearity of the system as they experience a largerinput signal. Based on this, it can be argued that LNA is the most important block for noise44figure performance of a receiver and in many receivers it is not an important block in terms oflinearity performance. However, as explained in Section 2.1.1, there are some systems whichdo require a good linearity performance for LNA due to their full-duplex architecture such ascode-division multiple access (CDMA) systems [33].To amplify the weak signal received by the antenna as well as ameliorating the noise contri-bution of subsequent stages, the LNA should have a considerable gain, however, the gain cannotbe arbitrarily large as a large gain would decrease the linearity of the receiver. Thus, there is atrade-off among the LNA gain, receiver linearity, and noise figure. For typical LNA gain of 15 to20 dB, depending on the CMOS technology, usually 2 to 3 stages of amplification are required.Assuming that a 3-stage LNA with a high linearity is required, the best place for applying thelinearity enhancement technique would be the third stage. Also, for improving the noise figure,noise performance enhancing technique are more effective if they are applied to the first stage.Gain variation is another important feature which is essential in many communication systemsspecially in wireless transceivers. The reason being that the received signal level can fluctuatea lot depending on the location of the receiver with respect to the transmitter. Therefore, thegain of the receiver path should be ideally adjustable to be able to adapt to the received signalstrength. In the context of our example 3-stage LNA, the best place for applying the gainvarying method is the middle stage, i.e., the second stage. Since gain variation should ideallynot have any effect on the input impedance matching [33], the first stage is not a good placeto apply gain variation. Also, to preserve the LNA and its load interaction (typically LNA andmixer), applying the gain varying method to the last (third) stage is not preferred.In this chapter, we investigate the application of body biasing in various stages of a multi-stage LNA to improve noise figure, enhance linearity, and provide gain variation. We presentour approach in the context of a 3-stage LNA (as depicted in Fig. 3.1) in which body biasingis applied to the first, second and thrid stage of the LNA to improve the overall noise figure,provide gain variation, and enhance the linearity, respectively. In the following sections, we firstoverview the configuration of the 3-stage LNA used in this research. Then, Sections 3.3, 3.4,and 3.5, explain the application of body biasing to control noise figure, gain and linearity inmore details. Section 3.6 presents the experimental results. Concluding remarks are presentedin Section 3.7.45											Figure 3.1: The Block-diagram of a 3-stage LNA with body-biasing for NF improvement, gainvariation and linearity enhancementFigure 3.2: Common-source amplifier with degeneration and series-gate inductance3.2 3-Stage LNA ConfigurationAs explained in Section 2.1.2, CS and CG configurations are usually used in low-noise ampli-fiers. While CG configuration provides a lower input impedance which facilitates the inputimpedance matching of the LNA, CS configuration is more commonly used due its better noiseperformance. Moreover, adding a degeneration inductor to the common-source amplifier (Fig.3.2) can facilitate the input matching to 50 Ω. In the presence of such degeneration inductor,the input impedance of the LNA is equal to [33]:Zin(jω) =1jωCgs+ jωLs +gmLsCgs(3.1)The third term in the above equation can be simplified to LsωT since for a MOS transistorωT ≈ gmCgs . Note that ωT = 2pifT and fT is the transit frequency of the transistor. fT isa technology-dependent parameter and is a function of transistor channel length. Therefore,46Figure 3.3: Cascode amplifier with inductive degenerationas long as the channel length is constant, the value of fT is a fixed value. By choosing anappropriate value for Ls the third term in (3.1) (which is a real term) can be chosen to be50 Ω6. As shown in [38], the presence of degeneration inductor will also provide the optionfor simultaneous noise and power matching. To cancel the imaginary terms in (3.1), usually aseries inductance (LG) is added in series with the gate of the transistor to cancel out the effectof gate-source capacitance as Ls is usually not large enough to cancel the effect of Cgs. Notethat this configuration is only needed at the first stage of a multistage LNA since there is noneed for power matching between the LNA stages nor the LNA-mixer interface.Stability is another important property of any amplifier. It can be shown that if an amplifierhas a good amount of reverse isolation (S12 ≈ 0), the stability can be achieved by limiting thegain of the amplifier [33]. Therefore, it is desirable that an LNA has a good reverse isolation.An alternative for a common-source amplifier which shows a better reverse isolation is a cascodeamplifier. Therefore, in this work we use a cascode structure for the first stage of the LNA asshown in Fig. 3.3.The reason for using inductive load is that it provides more voltage headroom for twotransistors of cascode amplifier than a resistive load. Moreover, the inductor along with theoutput node parasitic capacitance provide a filtering behavior which can be used to adjust thebandwidth of the LNA [33]. A concern about this configuration is the effect of noise of cascode6In very advance technology nodes, since fT is very large, the required degeneration inductance is too smallto be fabricated on-chip. Bond wire inductance may be used as the degeneration inductance in such cases [33].47Figure 3.4: (a) Circuit model for noise of cascode device (b) magnitude of noise due to thecascode device versus frequency [33]transistor (M2) on the overall noise figure. It should be noted that the noise of the cascodedevice is only important at very high frequencies [33]. This statement can be justified if thetransfer function from gate-referred noise of M2 to the output noise is calculated[33]:Vn,outVn2(s) =2rO1CXs+ 12rO1CXs+ 2gm2rO1 + 1gm2R1 (3.2)in which rO1 is the output resistance of the common-source device, CX is the parasitic capaci-tance in the middle point and gm2 is the transconductance of the cascode device. The magnitudeof the equation has been plotted in Fig. 3.4. As it can be seen, due to existence of a zero in thetransfer function, up to a certain frequency(12rO1CX), the effect of cascode device is nonexistentand after this frequency it starts to increase the total output noise and thus the noise figure.Based on this one can conclude that adding the cascode device does not significantly increasethe noise figure if the operation frequency is not very high and any slight increase in noise figureis in trade-off with better stability.In summary, as shown in Fig. 3.5, the 3-stage amplifier in this work is composed of threecascode amplifiers in cascade. A source degeneration and a series-gate inductor has been utilizedin the first stage for input and noise impedance matching. The only modification is that thefirst stage is biased by a current source and a capacitor has been added in parallel with thecurrent source to attenuate its noise. The reason for such biasing scheme is explained in the48 	Figure 3.5: Circuit diagram of the 3-stage LNA with body biasingnext section. Note that the we have chosen this 3-stage configuration as a vehicle to presentour proposed body-biasing techniques. In general, the proposed body-biasing techniques can beapplied to other structures as well.3.3 Body Biasing for Improving Noise FigureAs explained before, one of the most important parameters of a low-noise amplifier is its noiseperformance, i.e., the amount of noise that it adds to the noisy received signal detected bythe antenna. A common figure of merit for noise performance is the noise figure defined as:NF = 10 log SNRinSNRout where SNRin and SNRout refer to input and output signal-to-noise ratio,respectively. From circuit-level point of view, the noise of any two-port network can be modeledby using two input-referred noise sources [31] shown in Fig. 3.6. e2n is the input-referred voltagenoise when the input is short circuited and i2n is the input-referred current noise when theinput is open circuited. In general, e2n and i2n are correlated and to model this correlation, in isassumed to have two components, correlated component (ic) and uncorrelated component (iu).The correlation between ic and en is modeled by a correlation admittance (ic = Yc.en) [1].Both NF and input-referred noise sources can fully describe the noise performance of the49				Figure 3.6: Input-referred noise source of a noisy two-port networktwo-port network. However, since it is rather challenging to measure e2n and i2n due to the needfor having open circuit and short circuit conditions at the input of the device under the test(DUT), NF is usually preferred for high frequency measurements. It should be noted that thenoise factor (F ) can be written in terms of e2n and i2n [1]:F = Fmin +RnGs[(Gs −Gopt)2 + (Bs −Bopt)2](3.3)where parameters Fmin (minimum noise factor), Rn (noise equivalent resistance), Gopt and Bopt(real and imaginary parts of optimal-noise source admittance) describe the noise performanceof the corresponding two-port network and can be expressed in terms of e2n, i2n and Yc (note thatYc = Gc+jBc, where Gc and Bc are the real and imaginary parts of the correlation admittance)[1]:Bopt = −Bc (3.4)Gopt =√GuRn+G2c (3.5)Rn =e2n4kT∆f(3.6)Fmin = 1 + 2Rn[√GuRn+G2c +Gc](3.7)where in Eq. 3.5, the value of Gu is given by [1]:50Gu =i2u4kT∆f(3.8)Eq. 3.3 shows that the noise factor can be minimized by using a specific choice of sourceimpedance. If Gs = Gopt and Bs = Bopt (Gs and Bs real and imaginary parts of the sourceadmittance), the noise factor will be minimized. Since the impedance of the antenna is typically50 Ω, an impedance transformation network between the antenna and the LNA input is neededto minimize the noise.3.3.1 Noise Parameters of MOS TransistorsA MOS transistor has various sources of noise including the channel thermal noise, the gate-induced noise, the gate resistance thermal noise, and the flicker noise [1, 39]. Neglecting theeffect of the flicker noise which is only significant at low frequencies, the channel thermal noise,the gate-induced noise, and the gate resistance thermal noise are the main noise sources whichcontribute to the total noise generated by a MOS transistor.The equation for thermal noise of MOS transistor can be obtained as:i2nd = 4kTγgd0∆f (3.9)where γ is a technology-dependent constant and its value is equal to 2/3 for long-channeltransistors and close to 2 in short-channel devices [1]. Furthermore, gd0 is the conductance ofchannel for a transistor in triode region of operation. Note that some references use gm ratherthan gd0 in Eq. 3.9 which may not be a good approximation for short-channel devices.The thermal noise of the resistance of the gate terminal is another noise contributor in MOStransistors. In typical CMOS processes the gate of a MOS transistor is made of a poly siliconmaterial. The gate resistance, which is due to the limited conductivity of the poly silicon, isusually modeled by a series resistance (RG). The higher the doping of the poly silicon, the lowerthe value of RG will be. Similar to any other resistor, RG generates thermal noise. The powerspectral density (PSD) of its associated noise is given by [40]:v2ng = 4kTRG3∆f (3.10)51     		Figure 3.7: MOS noise modelwhere the factor of 1/3 is due to the fact that the gate resistance is distributed over the widthof the transistor.The other significant noise source of MOS transistors especially in short channel technologiesis the gate-induced noise. This noise is again due to the thermal noise of channel but here thethermal noise is coupled capacitively to the gate and creates a noise at the gate. This noisesource is correlated to the channel thermal noise. To model this effect, a gate resistance isconsidered in parallel with the gate-source terminals of the device. The derivation of the PSDof this noise source can be found in [39] and the equation is:i2ng = 4kTδgg∆f (3.11)where:gg =ω2C2gs5gd0(3.12)and δ is another technology-dependent constant whose value is almost twice γ [39].Taking into account all these noise sources, the noise model in Fig. 3.7 (a) can be used fora MOS transistor. The input-referred noise model of the MOS transistor can be obtained bydividing the value of i2nd in Eq. 3.9 by the square of the transconductance of the transistor, i.e.,52gm, and adding it to that of the gate resistance noise (Fig. 3.7 (b)). If the source terminal ofthe transistor in Fig. 3.7 is grounded, it becomes a two-port network. Therefore, by comparingthe input-referred two-port noise model of Fig. 3.6 with the MOS noise model in Fig. 3.7 (b),e2n can be calculated as:e2n = 4kT (γgd0g2m+RG3)∆f (3.13)The value of i2n in the input-referred two-port noise model of Fig. 3.6 is equal to i2ng givenby Eq. 3.11.3.3.2 Effect of Bulk Resistance on Noise of MOS TransistorsThe bulk resistance is another source of noise in MOS transistors. Note that the noise associatedwith this resistance can not be avoided even if the bulk and source terminals of the MOS deviceare shorted together [41]. This is due to the fact that there is a distance between the bulkcontacts and the physical bulk node (Fig. 3.8). Similar to the gate resistance, this resistance isa distributed resistance and it is typically difficult to quantitatively calculate its contributionto the noise of the MOS transistor [41]. Fig. 3.9 shows the noise equivalent model of the MOStransistor when bulk resistance noise is taken into account. As can be seen from this figure, if wedenote the equivalent noise resistance of the distributed bulk resistance as RB, its PSD wouldbe v2nb = 4kTRB∆f which appears as a noise voltage source at the bulk terminal. It shouldbe noted here that due to existance of the source-bulk depletion capacitance between bulk andsource terminals (as shown in Fig. 3.9), the bulk resistance thermal noise which appears acrossthe bulk-source terminal of MOS transistor has dependency on frequency [42]. More specifically,the transfer function of noise appearing at the bulk-source terminal has a pole at1RBCsbandtherefore the amount of noise decreases as the frequency of operation is increased:v2bs,n =4kTRB∆f1 + (ωRBCsb)2 (3.14)Typically, the pole of this transfer function is at a very large frequency. Hence, in this analysiswe neglect its effect and we assume that v2bs,n ≈ v2nb at the frequency of operation of the LNA.Based on Fig. 3.9 (a), to refer v2nb to the drain terminal of the MOS transistor (Fig. 3.9 (a)),53Figure 3.8: The distance between bulk terminal and actual bulk node [41]  						  				Figure 3.9: MOS noise model including the bulk resistance noiseits PSD is multiplied by g2mb:i2nb = 4kTRBg2mb4f (3.15)Finally, for referring this equivalent noise component to the gate terminal of the MOStransistor, Eq. 3.15 should be divided by g2m. Thus, the total input-referred voltage noise (e2n), including the effect of bulk resistance, is calculated as:e2n = 4kT (γgd0g2m+RG3+RBg2mbg2m)∆f (3.16)54Therefore, to decrease the contribution of the bulk resistance noise component on the overallnoise performance of the MOS transistor, it is desirable to decrease the value of gmb in Eq. 3.16.The equation for gmb is:gmb =∂ID∂VBS= gm · γB2√|2ΦF |+ VSB = ηgm (3.17)where γB =√2qSiNsub/Cox (Si is the dielectric constant of silicon, Nsub is the doping concen-tration of the substrate, ΦF is the Fermi potential of the bulk, γB is the body-effect coefficient,and Cox is the gate oxide capacitance per unit area). Thus, the value of e2n can be reduced bydecreasing gmb of the input stage transistor. Based on Eq. 3.17, gmb is decreased if the valueVSB increases or equivalently if the value of VB is decreased.Another important point here is that the above equations are based on the assumption thatthe source-bulk p-n junction is reverse biased. If the source-bulk parasitic diode of the MOStransistor is turned on, another noise source, namely, the shot noise of such forward bias diodewould also contribute to the noise of the transistor. The shot noise is a white noise and existsin any p-n junction that carries current and is independent of temperature. The PSD of theshot noise is proportional to the current of the p-n junction and is given by:i2nD = 2qID∆f (3.18)in which q is the charge of electron and ID is the current in the p-n junction. However, as longas the p-n junction is reverse-biased or mildly forward biased, then the contribution of the shotnoise of the source-bulk p-n junction diode can be neglected.As shown in Fig. 3.5, body biasing at the first stage of LNA which is reserved for improve-ment of noise figure, is applied to the CS transistor and not to the CG transistor. The reasonfor this is the fact that cascode amplifier is a cascade combination of a CS and a CG amplifier(Fig. 3.10). As discussed before, in a cascade configuration, the effect of noise figure of the firststage is dominant over that of the other stages. Therefore, here in a cascode configuration, theeffect of noise figure of the CS stage is dominant over that of the CG stage and body biasing isonly applied to the CS stage.However, if the bulk voltage of the CS transistor is varied, its DC parameters will also change55Figure 3.10: Cascode amplifier as cascade of CS and CG stagesFigure 3.11: Common-source amplifier with inductor degeneration (a) voltage-biased (b)current-biased(Fig. 3.11(a)). This is because by changing the bulk voltage, threshold voltage of the transistorchanges according to:Vth = Vth0 + γB(√|2ΦF | − VBS −√|2ΦF |)(3.19)where Vth0 is the threshold voltage of the transistor when its bulk-source voltage is zero, i.e.,VBS = 0V . This in turn means that, changing the bulk voltage to control the noise figure resultsin changing the operation point of the LNA, an effect which is not desirable. As a solution tothis problem, the first stage is biased with a current source (rather than a voltage source).In order to minimize any leakage of noise of the current source devices into the LNA, a largecapacitor is added in parallel with the current source to provide a low-impedance path for thenoise to ground (Fig. 3.11(b)).563.4 Body Biasing for Gain VariationAmong various specifications of a wireless receiver, a wide dynamic range is one of the importantones. Its importance comes from the fact that the level of input signal detected by the antennacan have a broad range depending on the relative distance of the user from the transmittingantenna. For example, in a cellular transmission, if the user is close to the base station, thepower level of its input signal can be as large as −10 dBm while when the user is at the boundaryof the cell, the input signal can be as weak as −110 dBm [33]. To cover such a wide dynamicrange, the gain of the receiver should be adjusted in accordance with the power level of theinput signal. In other words, for a small input signal the gain should be large and for a largeinput signal the gain should be small to avoid the saturation of the subsequent receiver chainblocks. An amplifier with an adjustable gain is often referred to as a variable-gain amplifier(VGA).In a VGA, a gain variation technique should be incorporated into a standard amplifierstructure. There are several parameters which define the quality of the gain variation technique.Ideally, as the gain of amplifier is changing, other design parameters should not be compromised.For example, if the VGA also acts as an LNA, the gain variation should not increase the noisefigure or sacrifice the input impedance matching of the LNA. To address this important point,in the proposed 3-stage LNA of Fig. 3.5, we apply the gain variation technique (body biasing)to the second stage to isolate the changes from the first stage which is the main contributor tothe input impedance and the overall noise figure of the LNA. Furthermore, the gain variationtechnique should not compromise the speed of the amplifier. A figure of merit for the operationspeed is the ωT of the transistors. The equation for ωT is:ωT =gmCgs(3.20)Assuming constant physical dimensions for the transistor, the value of gate-source capaci-tance (Cgs) is fixed. Thus, to keep ωT constant, gm should not be changed. This shows that,in order to change the gain of an amplifier, if the gm of main amplifying transistor is changed,the ωT is also varied which is not desirable as it affects the frequency response of the amplifier.Therefore, to change the gain, it is preferred to keep the gm constant and to change the gain57Figure 3.12: Gain reduction by steering the current to the bulk terminalby other techniques. To keep the gm constant, care should be taken to keep the current of theamplifying transistor constant, since:gm =√2µnCoxWLID (3.21)Therefore, in the proposed 3-stage LNA of Fig. 3.5, we apply body biasing (as the gainvariation technique) to the CG stage of the cascode such that when the bulk bias of the CGtransistor is varied, the current passing through the main amplifying transistor (.i.e., the CSstage) remains virtually unchanged.3.4.1 Body Biasing for Reducing the GainAs explained, the gain of a VGA should be decreased in case that the power level of inputsignal is large enough to saturate the receiver chain blocks. Given the structure of the cascodeamplifier, the input voltage is converted to a current signal by the CS stage in Fig. 3.10 andthe CG stage carries the same current to the output load. The main task of CG transistor is toincrease the output impedance which increases the output resistance and the thus the gain.As shown in Fig. 3.12, if the potential of the bulk terminal of CG device is within anappropriate range, some portion of the drain-source current of the CG transistor is directedto its bulk terminal, and thus the load current as well as the overall gain are decreased. Note58that this gain reduction is achieved while the gm of the CS transistor is remained practicallyconstant. This is because, with careful design, changing the threshold voltage of CG device doesnot have any significant effect on the bias current of the CS transistor and it mainly changesthe DC voltage level of the source node of the CG transistor. Also, as body biasing for gainvariation is applied at the second stage, its impact on the noise figure and the input impedancematching (which are mainly set by the first stage) as well as output impedance (which is mainlydecided by the last stage) is negligible.To further explain the mechanism for gain variation, consider the simplified device-leveldiagram of Fig. 3.13. The current in an NMOS transistor is carried through a channel formedbetween the drain and the source terminals of the device (assuming that the gate voltage is highenough such that the channel is formed). The bulk terminal can be thought of as the secondgate terminal and its voltage level works similar to that of the gate terminal, i.e., depletingand inverting the channel carriers. However, there is a difference between the gate and thebulk terminals. While the gate is coupled to the channel through a capacitor (WLCox), thebulk interface to the channel is through semiconductor p-n junctions. Typically, in an NMOStransistor the bulk terminal is tied down to the lowest supply voltage (e.g., ground) and ina PMOS transistor the bulk is tied to the highest supply voltage, e.g., VDD, so that the p-njunction diodes that interface the channel and the bulk are reverse biased. In this case, since thediodes are reversed biased, the bulk coupling to the channel can still be considered capacitive.However, if bulk terminal is forward biased, the bulk becomes capable of carrying DC currentsand the positive potential of bulk, if large enough, would absorb some of the electrons of thechannel and thus reduces the channel current. This current reduction would in turn decreasethe gain.3.4.2 Body Biasing for Gain BoostingThe key point for the purpose of this discussion is the parasitic capacitance which is seen at themiddle point of the cascode structure, i.e., the node at which the drain terminal of CS transistoris connected to the source terminal of CG transistor. This parasitic capacitance (CX) is thesum of various device capacitances including the drain-bulk capacitance (Cdb) and the gate-drain capacitance (Cgd) of the CS transistor as well as the gate-source capacitance (Cgs) and59Figure 3.13: Reducing the channel current in NMOS transistor by forward biasing of bulk-sourcejunctionsource-bulk capacitance (Csb) of the CG device. This parasitic capacitance introduces a polewhich limits the speed of the amplifier. To reduce its effect both layout solutions to minimizethis capacitance [29] and circuit techniques to cancel it through adding an inductance betweenthe CS and CG stages [43] have been introduced in the literature.The effect of the middle-node parasitic capacitance can alternatively be considered as asource of gain reduction. Using Fig. 3.14 we can intuitively explain the reason for this gainreduction. As can be seen in this figure, the current generated by the CS device, is split betweenCX and the impedance seen at the source terminal of the CG device (this impedance in theabsence of body effect is typically around 1/gm2). Therefore, due to this current split, the overallgain magnitude is reduced by the factor ofgm2√g2m2+ω2C2X, where ω is the angular frequency. Ifbody effect is taken into account, the gain reduction factor will change togm2+gmb2√(gm2+gmb2)2+ω2C2X.Note that this factor is higher than the factor in the absence of the body effect and furthermore,its value can be further increased by increasing gmb2. Considering Eq. 3.17, increasing gmb2 canbe achieved by forward bulk-source biasing of the bulk of the CG transistor.To summarize, forward body biasing can result in increasing the gain. In the previoussubsection, we argued that forward body biasing can decrease the gain. It should be noted thatwhen the bulk terminal voltage (VB2) is zero, due to the fact that source of the CG transistorhas some DC voltage, the bulk-source voltage (VBS2) is reversed biased. By increasing thebulk voltage, VBS2 become less negative. If increasing the bulk terminal continues, bulk-sourcejunction is gradually forward biased. As long as the bulk-source terminal is not strongly forwardbiased, i.e., the p-n diodes between bulk and the device terminals are not on, increasing the60Figure 3.14: The negative effect of the middle node parasitic capacitance on gainbulk terminal (VB2) increases gmb2 and thus the gain is increased. However, further increasingthe bulk voltage results in turning on of the source-bulk diode and the process of gain reductiondescribed in the previous section starts to take effect. Thus, by increasing the bulk terminalvoltage from zero, the gain increases at first and then starts decreasing.3.5 Body Biasing for Linearity EnhancementAs explained in Section. 3.1, in the proposed 3-stage LNA of Fig. 3.5, body biasing is used inthe last stage to enhance the linearity. The reason for this choice is the dominant effect of thelast stage of a chain of gain blocks on the overall linearity. Also, we advocate that applying bodybiasing to the CG transistor of the third cascode stage has a more pronounced effect on theoverall linearity of the LNA. To further elaborate on this choice, note that a cascode amplifieris a cascade of a CS and a CG amplifier (Fig. 3.10). In a cascade of stages, the effect of thelatter stages is more dominant on the overall linearity. Thus we can conclude that the effect ofCG transistor on the linearity is more pronounced.In order to investigate the dependence of the linearity of the proposed LNA on the bulk-source bias voltage, Volterra-series analysis can be used. The advantage of the Volterra-seriesanalysis over other nonlinearity analysis methods is its effectiveness in including dynamic non-linearities and providing more design insights. This is due to the fact that the Volterra-series61equations are in terms of the circuit parameters. The linearity analysis by Volterra-series hasbeen performed in detail for common-source and common-gate amplifiers (for example, see [44]and [45]). Similar to those analyses, the Voltera-series analysis for a cascode amplifier can beperformed. Fig. 3.15 (a) shows the cascode amplifier and Fig. 3.15 (b) shows the first-orderequivalent model of the cascode amplifier with the common-source transistor replaced by itsNorton equivalent. Neglecting, the dependence of the drain current on drain-source voltage andbulk-source voltage, the expansion of small-signal drain current of common-gate transistor as afunction of its gate-source voltage can be approximated as:iout = gm1vgs + gm2v2gs + gm3v3gs (3.22)where gm1 = gm, gm2 =12∂gm∂vgsand gm3 =16∂2gm∂v2gs.At the same time, vgs can be written as a function of iin, which is the Norton current sourcerepresenting the common-source amplifier. To write the Volterra series which describes theirnonlinear dependence, only second and third order nonlinearities are considered here. Thus, iinis assumed to be:iin(t) = I0 exp(jω1t) + I0 exp(jω2t) + I0 exp(jω3t) (3.23)and the associated Volterra series is equal to:vgs(t) =3∑k=1A1(ωk)I0 exp(jωkt)+3∑m=13∑k=1A2(ωm,±ωk)I20 exp [j (ωm ± ωk) t]+3∑n=13∑m=13∑k=1A3(ωn,±ωm,±ωk)I30 exp [j (ωn ± ωm ± ωk) t] (3.24)in this equation Ai is a complex number and is called as i-th Volterra kernel. The magnitudeand phase of i-th kernel defines the magnitude and phase of all of i-th order harmonics. Inter-estingly, the i-th Volterra kernel (Ai) can be computed if lower order kernels (A1, A2, ...., Ai−1)62Figure 3.15: (a) cascode amplifier (b) the first order model with the common-source transistorreplaced by its Norton equivalentare known.A similar Volterra series can be written to describe the nonlinear dependence of iout to iin.If Eq. 3.24 is replaced in Eq. 3.22, the Volterra kernels of iout-iin relationship can be calculatedin terms of Volterra kernels of vgs-iin:B1(ω) = gm1A1(ω) (3.25)B2(ω1, ω2) = gm1A2(ω1, ω2) + gm2A1(ω1)A1(ω2) (3.26)B3(ω1, ω2, ω3) =gm1A3(ω1, ω2, ω3) + {23A1(ω1)A2(ω2, ω3)+A1(ω2)A2(ω1, ω3)A1(ω3)A2(ω1, ω2)}+gm3A1(ω1)A1(ω2)A1(ω3) (3.27)To calculate the value of IIP3, a two-tone excitation is applied to the cascode amplifier.Based on our previous discussion that nonlinearity of the cascode is dominated by the nonlin-earity of CG device, we neglect the nonlinearity of CS device and we assume that the two-toneis appeared in iin without addition of intermodulation products resulting from nonlinearity of63CS device. Thus:iin(t) = I[cosωat+ cosωbt] (3.28)Then as shown in [46], the input voltage amplitude at intercept point (AIP3) is given by:AIP3(2ωb − ωa) =√43∣∣∣∣ B1(ωb)B3(ωb, ωb,−ωa)∣∣∣∣ (3.29)Based on this, the equation for input power at intercept point (IIP3) can be calculated similarto the one obtained in [46] for a CS amplifier:IIP3(2ωb − ωa) = AIP3(2ωb − ωa)28× 1Re{YT (jω)}=16∣∣∣∣ B1(ωb)B3(ωb, ωb,−ωa)∣∣∣∣× 1Re{YT (jω)} (3.30)in which YT (jω) is the output admittance of CS device in the cascode. As shown in [45], byreplacing Eq. 3.25 to Eq. 3.27 in Eq. 3.30 the following expressions can be obtained:IIP3(2ωb − ωa) = gm161∣∣∣(1 + gm1A1(ω)) |A1(ω)|2K(ωb, ωa)∣∣∣× 1Re{YT (jω)} (3.31)where [45]:K(ωb, ωa) =gm3 +23g2m2[1YT (j2ωb) + gm1+ 21YT (j(ωb − ωa)) + gm1](3.32)As can be seen from Eq. 3.31 and Eq. 3.32, IIP3 is a strong function of K(ωb, ωa) whichincludes the second-order (gm2) and third-order (gm3) nonlinearity coefficients of the CG device.64In the ideal case of gm2 = gm3 = 0, K(ωb, ωa) would be equal to zero and IIP3 would be equalto infinity. In practical cases, however, the contribution weight of the second-order and third-order nonlinearity coefficients of the CG transistor to the IIP3 of the overall cascode amplifier isdetermined by Eq. 3.32. Eq. 3.32 is a function of the output admittance of the CS transistor andthe transconductance of the common-gate transistor. The output admittance of a CS amplifieris:YT (jω) = jω(Cgd + Cdb) +1rO(3.33)By replacing Eq. 3.33 in Eq. 3.32, the following equation is obtained for K(ωb, ωa) :K(ωb, ωa) =gm3+23g2m2[12jωb(Cgd + Cdb) +1rO+ gm1+21j(ωb − ωa)(Cgd + Cdb) + 1rO+ gm1] (3.34)Due to the small value of (ωb − ωa) as compared to 2ωb in a typical two tone test, Eq. 3.34 canbe approximated by:K(ωb, ωa) ≈ gm3+23g2m2[2j(ωb − ωa)(Cgd + Cdb) + 1rO+ gm1](3.35)in which Cgd, Cdb and rO are gate-drain, drain-bulk and output resistance of the CS device andgm1, gm2 and gm3 are first-, second-, and third-order transconductance of the CG device.The dependence of the IIP3 of the cascode amplifier on the bulk bias voltage of the CGtransistor is through decreasing the value of gm3, referring to Eq. 3.35. While for a long-channel device with the simplistic square-law current equation, the value of gm3 is zero, in thecase of a short-channel device, gm3 has a nonzero value. Interestingly, when gm3 is plottedversus the gate-source voltage of the transistor, it has a zero at moderate gate-source voltages65Figure 3.16: Variation of the zero point in gm3 by changing the bulk voltage(Fig. 3.16). The existence of such a zero in gm3, results in a sweet-spot for the overdrive voltagethat improves the IIP3. The sweet-spot is between the weak inversion and the strong inversionregions. This sweet-spot biasing has been the focus of prior work for enhancing the linearity(e.g., see [44, 47, 48, 49]). The idea of using body biasing to improve the linearity of LNAs isbased on adjusting the location of this zero such that at the operating point, the gm3 of thetransistors that have dominant effects on the linearity of the the LNA is zero. Note that theoperating point of the cascode amplifier is defined by the CS device. However, as depicted inFig, 3.16, changing the threshold voltage of CG transistor results in changing its gate-sourcevoltage which in turn changes the gate-source voltage at which gm3 becomes zero. Since thegate bias voltage of the CG transistor is typically fixed, changing the threshold voltage willalso change the bias voltage of the source terminal of the CG transistor. This change willalso affect the drain-source voltage of the CS transistor which in turn slightly changes the biascurrent provided by the CS device due to channel-length modulation. These two mechanisms,i.e., shifting the bias voltage at which the gm3 of the CG transistor is zero and slightly changingthe bias current of the CG transistor, makes it possible to utilize body biasing to adjust thesweet-spot bias for nonlinearity and match it to the desired operating point of the circuit.Note that instead of changing the bulk voltage, the gate voltage can be alternatively adjustedto achieve the maximum IIP3. Although, IIP3 can be controlled by controlling the gate-sourcevoltage, however the peak in IIP3 will be too sharp and narrow due to the sharp variations ingm3 around its zero crossover. In contrast, when bulk-source voltage is utilized as the controlscheme, due to the fact that VBS appears under the square root in Vth equation (Vth = Vth0 +66Figure 3.17: The micrograph of the prototype 3-stage body biased LNA in 0.13-µm CMOSγ(√|2ΦF | − VBS −√|2ΦF |)), the change in Vth with respect to VBS is smoother [50]. Thisin turn results in a wider peak in IIP3 which makes the use of bulk voltage for sweet spotbiasing a more attractive technique which is less sensitive to process, voltage, temperature(PVT) variations.3.6 Experimental ResultsIn order to validate the idea of using body biasing to control gain, linearity and noise figure ina 3-stage LNA (Fig. 3.5), a prototype 3-stage LNA has been fabricated in IBM 0.13-µm CMOSprocess. The chip micrograph of the prototype is shown in Fig. 3.17. The center frequencyof the LNA is 4.4 GHz and is intended for UWB applications. The active area of the LNA isabout 750-µmÖ680-µm. The LNA consumes the power consumption of 3.6 mW from a 1.2Vsupply voltage. To test noise figure and linearity of LNA, Agilent N9010A EXA 26.5 GHzsignal analyzer is utilized. S-parameter measurements are performed by HP 8510C 40 GHzvector network analyzer. The noise source for noise figure measurement is Agilent N4001A withexcess noise ratio (ENR) of 15 dB.Fig. 3.18 shows the plot of the noise figure of the LNA as the bulk-source voltage of the CSdevice in the first stage is varied from −1 V to +1 V. As it can be seem from the figure, whenVBS1 = +1 V, the noise figure is around 5.1 dB at 4.4 GHz while with VBS1 = −1 V, the noisefigure is about 3.8 dB, i.e., an improvement of 1.3 dB. These measurements confirm that theoverall noise figure can be controlled through body biasing of the input transistor in the LNA.67	 	 	 	 	 	 		  	 	Figure 3.18: Noise figure measurement results of the prototype body-biased LNA	 	 	    	 	Figure 3.19: Variation of NF at 4.4. GHz with bulk voltage of CS transistor in first stageFig. 3.19 shows the variations of NF of the overall LNA with bulk voltage of CS device in thefirst stage at 4.4 GHz. Note that for VBS1 values beyond +0.6V, the bulk-source p-n junctionis turned on and therefore the shot noise of these diodes contribute to NF and thus part of theincrease in the value of NF beyond +0.6V can be attributed to the effect of shot noise of thebulk-source diode.Fig. 3.20 shows the gain of the overall LNA when bulk-source voltage of the CG device inthe second stage of the LNA is increased from −0.5 V to +0.7 V. Note the difference betweenthe values of VB (bulk voltage) and VBS (bulk-source voltage) of the CG transistor of the secondstage. In the case of no body biasing, VB is zero since the substrate is normally tied down toground. However, at VB = 0 V, the bulk-source voltage (VBS) has a negative value as the sourceof the CG device is at some positive DC bias. Based on the simulation results, the DC voltageof this source is 0.5 V, thus VB = 0 V corresponds to VBS = −0.5 V. As it can be observed68     	 		  Figure 3.20: Gain measurement results of the prototype body-biased LNAfrom this figure, the gain of the overall LNA is around 15.2 dB when no body biasing is applied,i.e., when VB2 = 0 V, VBS2 = −0.5 V (moderate gain mode). The gain increases by about 5dB to 20.2 dB when the bulk-source junction is forward biased to +0.5 V (high gain mode). Ifthe bulk voltage is further increased, the gain starts to fall. (This gain drop can be attributedto the mechanism shown in Fig. 3.12). The gain reduction can be observed in Fig. 3.20 asthe low-gain mode with gain of about 5 dB when VB2 is increased to +1.2 V or equivalentlyVBS2 = +0.7 V. To reach the low-gain mode which corresponds to VBS2 = 0.7 V, i.e., aroundthe turn-on voltage of the bulk-source p-n junction, the bulk voltage should be increased toaround +1.2 V.As mentioned before, it is desired that the gain variation technique does not affect othercircuit performance parameters. Input return loss is one of such important metrics which shouldideally remain unchanged. Fig. 3.21 plots the S11 of the LNA for three different gain modes.As it can be observed, S11 is almost the same for the high-gain and moderate-gain modes andit slightly shifts for the low-gain mode. The noise figure of the overall LNA shows the sametrend, and the gain variation has a minimal impact on the noise figure.It should be noted here that the gain variation technique explained in this chapter is ap-plicable to higher frequencies as well. To illustrate this a body-biased mm-wave variable-gainamplifier has been designed and laid out. More information about design and measurementresults of the mm-wave body-biased VGA can be found in Appendix. A.Finally, Fig. 3.22 shows the variation of IIP3 of the LNA with respect to the bulk voltage69     	 	  Figure 3.21: S11 for three cases of high, moderate and low gainof the CG device in the third stage of the LNA for two of the gain modes, i.e., high-gain mode(VB2 = 1 V) and moderate-gain mode (VB2 = 0 V). As it can be seen from the plot of IIP3versus VB3, the IIP3 peak is relatively wide and is not as sharp compared to the case wherethe bulk voltage is fixed and the gate-source is used for IIP3 sweet-spot biasing [51]. Two-tonetesting is performed for measuring the IIP3. As it can be seen from figure, IIP3 is improved byalmost 4 dB when VB3 is increased from 0 V to 1 V (VBS3 from −0.5V to +0.5V).An important point to note is that, when body biasing is utilized in the third stage for im-proving the linearity, the gain of the third cascode stage also changes. Similar to what explainedbefore for gain variation in the second stage, increasing the VB3 up to around +1 V results inincreasing the gain. Since peak of IIP3 also happens around +1 V (Fig. 3.22), increasing thelinearity of the third stage, increases its gain too which relaxes the gain requirement of thesecond stage. Thus, the designer may want to start by optimizing the linearity and then changethe body bias in the second stage to reach the target gain. It should be mentioned here that thegain plots in Fig. 3.20 are for the maximum linearity, i.e., the gain-linearity has been optimizedtogether.3.7 ConclusionBody biasing is presented as a technique for optimization of the performance in a 3-stage cascodeLNA. The technique is based on providing appropriate bias voltage for bulk terminals of specifictransistor in the LNA. The proposed body biasing technique is a multipurpose optimization70 	 	 	 	  		 Figure 3.22: Measured IIP3 of the LNA versus bulk voltage of CG device in the third stagemethod. Body biasing is applied in the CS transistor of the first stage for improving noisefigure, to the CG transistor of the second stage for gain variation control and to the CG deviceof the third stage for linearity enhancement. Table. 3.1 summarizes the performance andcompares the LNA in this work with other state-of-the-art works.71Table 3.1: Performance summary and comparison of the prototype LNA with other published worksf0 CMOS Supply NF S11 Gain IIP3 Pdc Area(GHz) Process (V) (dB) (dB) (dB) (dBm) (mW) (mm2)This Work14.4 0.13-µm 1.2 3.9 −33 20.2 −17.8 3.6 0.51This Work24.4 0.13-µm 1.2 3.8 −27 15.2 −14 3.6 0.51[52] 0.1∼10 65-nm 1.2 2.59∼4.92 −23∼−11.7 17∼ 24 −15∼ −12 8.64 0.012[53] 2.6 ∼ 10.2 90-nm 1.2 3 ∼ 7 −9 12.5 −2.4∗ 7.2 0.64[54] 3 ∼ 7.4 0.18-µm 1.8 3.56 < −10 20.7 −13.2 12.8 0.93[55] 0.2 ∼ 3.8 0.13-µm 1 2.8 ∼ 3.4 < −9 19 −4.4 ∼ −8 5.7 0.025[56] 3.1 ∼ 10.6 0.18-µm 1.8 4.5 ∼ 6.2 < −9.5 13.2 −1.4 23 1.42[12] 5.1 0.13-µm 0.4 5.3 −17.7 10.3 −12.4∗ 1.03 1.151High gain mode (VB2 = +1V )2Moderate gain mode (VB2 = 0V )∗Only P1−dB is given. IIP3 is estimated based on the equation: PIIP3 = P1−dB + 9.6dB [33].72Chapter 4Body Biasing in ActiveDown-Conversion MixersAs explained in Section 2.2, in wireless receivers, down-conversion mixers are commonly used totranslate the frequency spectrum of the radio-frequency (RF) received signal of the antenna to alower or zero intermediate frequency (IF). Important design specifications of a down-conversionmixer include gain, noise figure, linearity, power, and port-to-port isolation. Similar to the caseof low-noise amplifiers explained before in Chapter 3, there is a trade-off between gain, noisefigure and linearity in down-conversion mixers as well. For the building blocks of the receivepath, as the blocks get farther from the antenna, their contribution to the noise figure would belowered by the aggregated gain of their preceding stages (Friis' equation [34]). Thus, the higherthe gain of the down-conversion mixer, the lower the noise contribution of the stages after themixer e.g., baseband amplifiers in the generic integrated receiver of Fig. 2.9 will be. However,the larger the gain of mixer, the more pronounced would be the nonlinearity distortions of thesebase-band amplifiers. This is due to the fact that in the receiver chain of blocks, the IIP3 ofeach block in the chain is divided by the comulative gain of its preceding blocks (Eq. 2.9).Due to the relatively high noise figure of active mixers, the gain of the LNA is typicallychosen to be large enough to keep the overall noise figure at an acceptable level. However, thisleads to more restrictions on the linearity of the mixer as its IIP3 is scaled down by the gainof the LNA. Thus, it is important to enhance the linearity of the mixer such that the largegain of LNA does not limit the linearity of the whole receiver. Unfortunately, the scaling ofCMOS technology which results in lower supply voltages, makes the design of highly linearactive mixers challenging.Power consumption is another performance metric which is of great importance in low-power73as well as portable wireless receivers. Thus, in low-power designs, it is desirable to reduce, asmuch as possible, the power consumption of each single block in the receiver including down-conversion mixers. However, it is challenging to decrease the power without compromising thenoise figure and linearity. To keep the power consumption of the receiver to the minimum, it isalso desired that the mixer operates with small LO signal levels. This is due to the fact that thelower the amplitude of LO signal, the less power would be required in the VCO or frequencysynthesizer to generate the LO signal.In this chapter, we propose the idea of enhancing the linearity of down-conversion mixersthrough incorporating body biasing in the LO-stage transistors. Conventionally, for large LOsystems, linearization techniques are commonly applied to the RF stage of the mixer (e.g., see[57, 58, 59, 60, 61]) due to the fact that with the abrupt switching of LO stage, most of thedistortion of the mixer is from the RF stage [59, 62, 63]. However, if the LO power is low andthe transistors in the LO stage are not instantaneously switched on and off, the LO stageremains in active region for a considerable amount of time during the LO period, and thus thenonlinearity contribution of the LO stage on the mixer distortion should be investigated. To dothis, we first overview the structure of the conventional current-commutating mixers in Section4.1. Section 4.2 discusses the linearity of mixers with low-power LO which in turn have non-idealswitching in their LO stage. Section 4.4 and Section 4.5 present the application of body biasingto improve linearity and conversion gain in this type of mixers. In order to validate the proposedidea, two proof-of-concept prototypes have been designed and fabricated in 0.13-µm CMOS; oneis a standard double-balanced mixer and the other one is a current-bleeding double-balancedmixer. Measurement results of these two prototypes are presented in Section 4.6. Conclusionremarks as well as comparison with the state-of-the-art mixers are presented in Section 4.7.4.1 Current-Commutating Active Down-Conversion MixersThe most commonly used structure for active CMOS mixers is the current-commutating ar-chitecture [33, 1]. The simplified single-balanced version of such mixer is shown in Fig. 4.1(a). We will use this simplified structure to briefly overview the operation of such mixers. Inthis mixer, transistor M1, which is typically referred to as the RF stage transistor, operates as74Figure 4.1: (a) Schematic of a single-balanced mixer, (b) current-commutation in LO stagea transconductance stage (gm stage) which converts the RF input voltage signal to a currentsignal. Assuming that LO signal has a large enough amplitude, transistors M2 and M3 act asdifferential current switches and steer the RF current into one of the branches of the differen-tial pair as depicted in Fig. 4.1 (b). This switching behavior is usually referred to as currentcommutation. The output IF current signal defined as difference of the currents in each branch,can be written as:iIF (t) = p(t).iRF (t) (4.1)in which iRF (t) is the RF current generated by the gm stage and p(t) is a periodic square pulsetrain switching between −1 and +1 with frequency of fLO and the Fourier series representationof:p(t) =[4picosωLOt− 4pi.13cos 3ωLOt+ · · ·](4.2)The value of iRF (t) is given by:iRF (t) = gm,RF .vRF (t) (4.3)where gm,RF is the small-signal transconductance of the RF stage transistor (M1). By replacingEq. 4.3 and Eq. 4.2 in Eq. 4.1, one may notice that the spectrum of vRF (t) is replicated at all75Figure 4.2: Non-ideal switching in LO stage [64]of the odd harmonics of fLO and in the presence of a low-pass filter, all of them except the onearound ωRF − ωLO are sufficiently attenuated.4.2 Non-Ideal Switching in Active Down-Conversion MixersFor the mixer shown in Fig. 4.1, ideal current commutation happens if the LO signal is largeenough to fully divert the tail current between the branches. Under this condition, LO-stagetransistors operate in either off or triode region and produce a current with a square-shapewaveform. However, in practice in many applications, the LO signal does not abruptly switchthe entire tail current between the differential branches. For example, in low-power wirelesstransceivers where the power level of the signals including the LO signal are kept as low aspossible, the current commutating in the LO stage is not as abrupt. In such cases, p(t) in Eq.4.1 can no longer be considered as a periodic square-wave pulse signal. Moreover, due to theexistence of a nonzero switching time (∆), higher-order nonlinear terms (specially second- andthird-order terms) appear in the equation for iIF (t) [64]:iIF (t) = p1(t).iRF (t) + p2(t).i2RF (t) + p3(t).i3RF (t) (4.4)where p1(t), p2(t), and p3(t) are the first-, second-, and third-order coefficients of the Taylorseries expansion of iIF (t) versus iRF (t) around the operating point of the circuit. Fig. 4.276shows a symbolic diagram for a non-ideal switching and the corresponding p1(t), p2(t), andp3(t) [64]. The appearance of these nonlinear terms can also be justified if one considers thatwhen switching of LO stage is not abrupt, the transistors in the LO stage remain in their activeregion of operation during the switching time (∆) and thus their nonlinearity plays a role inthe overall performance of the circuit. Note that the value of p2(t) and p3(t) is zero outside theswitching transition (∆) and they only have value when M2 and M3 are operating in the activeregion. The time-variant relation of iIF (t) and iRF (t) given by Eq. 4.4 can be simplified to thefollowing time-invariant equation if only components which lead to a term around ωRF − ωLOand its multiples (i.e., the down-converted IF band) are considered [64]:iIF = β1.iRF + β2.i2RF + β3.i3RF (4.5)Here, βi is given by [64]:βi =1TLOTLOˆ0pi(t) sin (2pifLOt) dt (4.6)and TLO and fLO are the period and the frequency of the LO signal, respectively. For the caseof abrupt switching, p1(t) is given by Eq. 4.2 and p2(t) = p3(t) = 0 and thus only β1 has anonzero value. In fact by replacing Eq. 4.2 in Eq. 4.6, the value of β1 is equal to2pi . ConsideringEq. 4.3, then one may notice that the conversion gain of the mixer (namely,vIFvRF) with idealLO switching is equal to:CG = β1.gm,RFRD =2pigm,RFRD (4.7)In all other cases, where the switching in the LO stage is not abrupt, the nonlinear terms in Eq.4.5 causes saturation in conversion gain and thus the conversion gain is lowered.4.3 Nonlinearity Analysis in Mixers with Non-Ideal SwitchingAs mentioned before, in many practical cases, especially in mixers with low LO power, theLO-stage transistors do not switch abruptly and are operating in their active region for a77Figure 4.3: Half-circuit of single-balanced mixerconsiderable portion of the LO period. The larger the value of ∆ in Fig. 4.2, the longer theLO-stage transistors operate in their active region and the lower will be the conversion gain ofthe mixer due to the saturation of conversion gain imposed by the nonlinearities shown in Eq.4.4. During the time that LO-stage transistors (M2 andM3) are in their active region, each LO-stage transistor can be considered as the common-gate transistor in a cascode configuration (ifwe consider the RF stage transistor as the common source stage of the cascode). This is shownin Fig. 4.3 in which only one of the branches of a single-balanced mixer is drawn. Based on Eq.2.9, in a cascade of stages, the final stages of the cascade have stronger impact on the linearity.Therefore, it can be argued that in a cascode configuration (cascade of a common-source (CS)followed by a common-gate (CG) stage) the effect of the common-gate stage on the linearity isdominant.The dominance of the LO stage on the overall linearity of the mixer can also be shownanalytically. To do the linearity analysis for such mixers with non-ideal LO switching, similarto the LO stage, the nonlinearity of RF stage should be taken into account. The followingequation can be written for the RF stage:iRF = gm1,RF vRF + gm2,RF v2RF + gm3,RF v3RF (4.8)where gm1,RF , gm2,RF , and gm3,RF are the first-, second-, and third-order transconductance ofthe RF-stage transistor. Note that the value of gm1,RF in Eq. 4.8 is the same as gm,RF in Eq.4.3. By replacing Eq. 4.8 in Eq. 4.5, and by only considering the terms that will lead to the78components at the down-converted IF band, the following equation for iIF can be achieved:iIF = a1vRF + a2v2RF + a3v3RF (4.9)where [33]:a1 = β1.gm1,RFa2 = (β1.gm2,RF + β2.g2m1,RF )a3 = (β1.gm3,RF + 2β2.gm1,RF .gm2,RF + β3.g3m1,RF )(4.10)The third-order intermodulation distortion in mixers can be calculated by applying a two-tone test at the RF port of the mixer [33]. Thus, assuming:vRF (t) = VRF [cos (2pif1t) + cos (2pif2t)] (4.11)the ratio of amplitude of the corresponding IF components around 2f1 ± f2 − fLO and 2f2 ±f1 − fLO to the amplitude of the desired IF components at f1 − fLO and f2 − fLO are given by[65]:IM3 =34a3a1V 2RF (4.12)Substituting Eq. 4.10 in Eq. 4.12, and after some manipulations, the following equation can bewritten for mixers with non-ideal LO switching [64]:IM3 ≈ 34(gm3,RFgm1,RF.V 2RF +β3β1.g2m1,RF .V2RF)(4.13)As can be seen from this equation, coefficient related to the LO stage, namely,β3β1, is ampli-fied by the square of the first-order transconductance of the RF stage. This in turn means that,depending on the value of gm1,RF , the LO stage nonlinearity may dominate the overall nonlin-earity of the mixer. Note that while in the derivation of the above equations, we assumed that79the structure of the mixer is single-balanced, the results can be extended to the double-balancedmixers.4.4 Body Biasing for Linearity EnhancementFrom Eq. 4.13, to decrease the nonlinearity in a mixer with a non-ideal switching signal, thethird-order nonlinear term of the current of transistors in both RF and LO stages, namely,gm3,RF and β3, should be minimized. Moreover, as the contribution of the nonlinearity of theLO stage is magnified by the gain of the RF stage, special attention should be paid to the ratioof third-order and first-order terms of the current of the transistors of the LO stage, namely,β3β1.Note that while in the derivation of equations in previous section, the nonlinearity of LO-stagetransistors are expressed in terms of β1, β2, and β3, they can be equivalently related to gm1,gm2, and gm3 of the corresponding transistors. In fact, p1(t), p2(t), and p3(t) are due to thenonlinearity in ID-VGS curve of the MOS transistors which can alternatively and equivalentlyexpressed in terms of gm1, gm2, and gm3 of the respective transistors. Thus, decreasing thethird-order nonlinearity of the LO-stage transistors can be achieved by reducing gm3 of thosetransistors.While for a long-channel device with the simplistic square-law current equation, the valueof gm3 is zero, in the case of short-channel devices, gm3 has a nonzero value. Interestingly, whengm3 is plotted versus gate-source voltage of the transistor, it has a zero at moderate gate-sourcebias voltages (Fig. 4.4) [51]. The existence of such a zero in gm3, results in a sweet-spot biasfor the IM3 (or equivalently IIP3) in the transition of weak-/moderate-inversion region to thestrong-inversion region. This sweet-spot biasing has been the focus of many recent works forenhancing the linearity (e.g., see [48, 59, 60, 66]). The idea of using body biasing to improvethe linearity of mixers is based on adjusting the location of this zero such that at the desiredoperating point the gm3 of the transistors that have dominant effects on the linearity of themixer approaches zero. As discussed before, in mixers with non-ideal (realistic) switching of theLO stage, transistors in the LO stage may strongly affect the overall linearity of the circuit dueto the fact that they are closer to the output. Note that the operating point of the LO-stagetransistors is typically set by the bias current of the RF stage. However, as depicted in Fig,80Figure 4.4: Variation of the zero point in gm3 by changing the bulk voltage4.4, changing the threshold voltage of LO-stage transistors results in changing the gate-sourcevoltage of those transistors which in turn changes the gate-source voltage at which gm3 becomeszero. Since the gate bias voltage of the transistor in the LO stage is typically fixed, changingthe threshold voltage will also change the bias voltage of the source terminal of the LO-stagetransistors. This change will also affect the drain-source voltage of the RF stage transistorwhich in turn slightly changes the bias current provided by the RF stage due to channel-lengthmodulation. These two mechanisms, i.e., shifting the bias voltage at which the gm3 of the LO-stage transistors is zero and slightly changing the bias current of the LO-stage transistor, makesit possible to utilize body biasing to adjust the sweet-spot bias for nonlinearity and match it tothe desired operating point of the circuit.One may question the advantage of changing the bulk bias voltage over changing the gatebias voltage. In fact, instead of bulk voltage, gate voltage can be alternatively changed in orderto achieve the maximum IIP3. Although IIP3 can be controlled by controlling the gate-sourcevoltage, however, the peak in IIP3 will be too sharp and narrow [51] due to the sharp variationsin gm3 around its zero crossover. In contrast, when bulk-source voltage is utilized as the controlscheme, due to the fact that Vth is a function of the square-root of VBS as shown in Eq. 4.14[30], the change in Vth with respect to VBS is much slower. Note that in the presence of bodyeffectVth = Vth0 + γ(√|2ΦF | − VBS −√|2ΦF |)(4.14)81Figure 4.5: Effect of parasitic capacitance at the drain of RF stage on the conversion gainwhere γ =√2qSiNsub/Cox, Si is the dielectric constant of silicon, Nsub is the doping concen-tration of the substrate, ΦF is the Fermi potential of the bulk, γ is the body-effect coefficient,and Cox is the gate oxide capacitance per unit area. This results in a wider peak in IIP3 [50]which in turn makes the sweet-spot biasing more practical and also less sensitive to process,supply voltage, and temperature (PVT) variations.4.5 Effect of Body Biasing on Conversion GainIn addition to linearity enhancement, depending on the type of the mixer, body biasing at theLO stage can also improve the conversion gain of the mixer. To further explain this potentialconversion-gain enhancement, we first review one of the gain degradation sources in mixers,namely, the total capacitance seen at the drain of the RF stage transistor(s). Fig. 4.5 depictsthis capacitance, namely, CX , which is the sum of gate-source capacitance (Cgs) and source-bulkcapacitance (Csb) of LO-stage transistors as well as drain-bulk (Cdb) and gate-darin capacitance(Cgd) of RF stage transistor(s). The output RF current of the RF stage is split between theCX and the impedance seen at the source of the LO-stage transistors. Since the parasiticcapacitances of the LO transistors are accounted for in CX , the impedance looking into sourceof LO transistors, which also provides an indication of how much current flows through the82channel of transistor, is approximately1gm,LO. Neglecting the effect of nonlinear terms, theconversion gain of the mixer is [33]:CG =2pigm,RFRDgm,LO√C2Xω2RF + g2m,LO(4.15)Comparing this equation with Eq. 4.7, one may notice that the conversion gain is lowered bya factor ofgm,LO√C2Xω2RF+g2m,LO. The larger the value of CX and the higher the RF frequency, thelarger will be the degradation in conversion gain.In the presence of body effect, the bulk-source transconductance of the LO-stage transistorswill decrease the input impedance seen at the source of these transistors. This is due to the factthat the transconductance of the device changes from gm,LO to gm,LO+gmb,LO. This increase inthe overall transconductance due to the body effect is in favor of conversion gain as it reducesthe sensitivity to CX :CG =2pigm,RFRD(gm,LO + gmb,LO)√C2Xω2RF + (gm,LO + gmb,LO)2(4.16)Moreover, as the value of gmb,LO is increased the conversion gain is also improved. Increasingthe value of gmb,LO can be achieved through forward biasing of the bulk-source p-n junction inthe LO-stage transistors. This can be explained using the equation for gmb [30]:gmb =∂ID∂VBS= gm · γ2√|2ΦF | − VBS = ηgm (4.17)Note that at the same time that gmb,LO is increased through forward biasing of the bulk-source junction, the value of Csb of the LO transistors are also increased which in turn increasesthe value of CX . Thus, the effect of body biasing of LO stage on the conversion gain depends onthe relative improvement on the resistance seen at the source terminal of the LO-stage transistorsand the increase in the value of CX . In other word, if the Csb of LO transistors contributes to asignificant percentage of CX , body biasing may not be very useful in improving the conversiongain. However, typically, the value of CX is dominated by other parasitic capacitances such asgate-source capacitance of the LO stage, and therefore, body biasing will improve the conversiongain.83(a) (b)Figure 4.6: The chip micrographs of the fabricated prototypes in 0.13-µm CMOS technologyFigure 4.7: Schematic of the fabricated body-biased double-balanced mixer4.6 Experimental ResultsTo verify the validity of the proposed body-biasing technique, two proof-of-concept double-balanced mixers are designed and implemented in a 0.13-µm CMOS process. The micrograph ofthe fabricated body-biased mixers are shown in Fig. 4.6. The schematic of the first prototypemixer (Fig. 4.6 (a)) is presented in Fig. 4.7. The mixer uses degeneration inductors (Ls) inorder to improve the linearity of the RF stage. Note that the mixer is intended to operate witha low LO power. Having the test setup in mind, since the LO signal is applied externally (andnot from an integrated VCO with an optimized matching), the external RF source has a 50Ωinternal resistance. Given that the LO port impedance is mainly capacitive, with a low LO84Figure 4.8: Test setup for measuring conversion gain.power (-10 dBm here), the amplitude of the voltage at the gate of the LO-stage transistors willbe too low to even overcome the threshold voltage and turn on the transistors. To compensatefor this effect in the test setup, two resonance inductors (Lres) are incorporated at the gatesof the LO transistors (one inductor per gate). The added inductors create a series resonancewith the input capacitance of the LO stage devices. The magnitude of the current phasor inthe vicinity of this resonance frequency is increased which in turn leads to an increase in themagnitude of the voltage at the gate of the LO transistors, i.e.,M3 toM6. Note that simulationresults confirm that even in the presence of the two Lres, the amplitude of the voltage signal atthe gates of M3 to M6 is not large enough to abruptly switch the RF tail current and the LOtransistors operate in their active region during the switching time.Fig. 4.8 shows the test-setup for measuring the conversion gain of the prototype mixers. Ascan be seen from this figure, the need for differential input signals at the RF port necessitatesthe use of a 180◦power splitter as a balun. Power splitter as well as bias-Tees, cables and on-wafer probes are passive components and will introduce conversion loss which should be takeninto account when calculating the conversion gain of the mixer. Also, the noise figure of mixeris degraded due to the loss of these components. The reason is that as shown in [33], whena component with loss of L (dB) is placed at the input of a system, the noise figure will beNF = NF0 + L in which NF0 is the noise figure in the absence of the lossy component.85Figure 4.9: Measured IF spectrum of the first prototype mixerFig. 4.9 shows the IF spectrum of mixer for RF signal of 2.4 GHz and LO signal of 2.45 GHz.The conversion gain of circuit after de-embedding the loss of test setup components is 12.3 dB.For noise figure measurement Agilent N4001A noise source with excess noise ratio (ENR) of 15dB is used. After de-embedding the noise of test setup components, double-sideband (DSB)noise figure of 16.5 dB is achieved.For linearity measurements, the third-harmonic distortion (HD3) is utilized [65]:HD3 =14a3a1V 2RF (4.18)The value of HD3 can be converted to IM3 and IIP3 through the following equations [65]:IM3 = 3HD3 (4.19)IIP3dB = VRF,in |dB − 12IM3dB (4.20)Fig. 4.10 shows the measurement results for harmonic content of the first prototype mixer.As can be seen from the figure, the third-order nonlinearity is decreased by around 8.2 dB whenthe body bias of the LO stage is changed from 0 V to 0.8 V. Based on Eq. 4.20, this in turnresults in 4.1 dB improvement in IIP3. Fig. 4.11 shows the plot for IIP3 and conversion gain of86(a) (b)Figure 4.10: Harmonic content of the IF signal (a) VB,LO = 0V (b) VB,LO = 0.8Vthe mixer. As it can be observed from the figure, there is a relatively wide peak in IIP3 (widewith respect to the bulk voltage of the LO-stage transistors) for the double-balanced mixer ofFig. 4.7. The maximum value of IIP3 for positive bulk voltages is about 4.1 dB higher than thecorresponding value when there is no body biasing. Note the difference between the values of VB(bulk voltage) and VBS (bulk-source voltage). In the case of no body biasing, VB is zero sincethe substrate is normally tied down to ground. However, at VB = 0 V, bulk-source voltage (VBS)has a negative value as the source of the LO device has some positive DC bias. Based on thesimulation results, the DC voltage of the this node is around 0.6 V, thus VB = 0 V correspondsto VBS = −0.6 V. Interestingly, as the bulk voltage is increased and the bulk-source junction ispushed toward the forward-bias region, there is a maximum in conversion gain. Based on Fig.4.11, the conversion gain increases from 10.6 dB to 13.2 dB, when body voltage is varied from0 V to 1 V (VBS from −0.6V to +0.4V). This increase in the gain can be attributed to themechanisms explained in the previous section. The increase in the conversion gain by changingthe bulk voltage continues up to the point where the bulk source junction becomes stronglyforward biased for which the gain starts to decrease.To examine the effectiveness of the body biasing technique in other types of mixers, a secondprototype with current bleeding RF stage [33, 67] is also designed and fabricated in the same87				      				 Figure 4.11: Plot of variation of IIP3 and conversion gain versus bulk voltage of LO stagetransistorsFigure 4.12: The schematic of second prototype with RF transistors in subthreshold region0.13-µm CMOS technology (Fig. 4.6 (b)). The schematic of this prototype is shown in Fig.4.12. In this mixer, the RF stage is composed of an NMOS and a PMOS transconductancein parallel while both of them are biased in their subthreshold region. One of the importantfeatures of the subthreshold region, aside from the low power consumption, is the resemblanceof the MOS transistor behavior to that of the bipolar transistors. This type of exponentialcurrent-voltage dependance will typically result in a higher nonlinearity.The measurement results of the second prototype are shown in Fig. 4.13. As can be seenfrom the figure, IIP3 can be controlled by the bulk bias of the transistors in the LO stage andthere is a maximum for IIP3 around VB = 0.35 V. Moreover, although the value of IIP3 is lower88		        	  				 Figure 4.13: Plot of variation of IIP3 and conversion gain versus bulk voltage of LO stagetransistors for the second prototype(due to operating of the RF-stage transistors in the subthrshold), the variation range in IIP3versus the bulk voltage is still around the same as that of the first prototype. As shown inFig. 4.13, the peak of IIP3 is achieved at a smaller value for the bulk voltage. The reason forthis is that the important parameter in determining the place of the peak of IIP3 is the bulk-source voltage (rather than the bulk voltage). As RF stage operates in subthreshold region andalso there is no DC tail current source, the DC voltage of the source terminal of the LO-stagetransistors is small. Thus, smaller bulk voltage results in the bulk-source voltage at which IIP3is maximized.The conversion gain however, does not benefit from the forward body biasing in the secondprototype. Based on Fig. 4.13, as the bulk voltage of LO transistors increases, the conversiongain decreases. This can be justified by noticing that the gain of the current-bleeding stageis very sensitive to the DC bias voltage of the drain voltage of M1-M4 or equivalently sourceterminals in the LO-stage transistors. Therefore, when the threshold voltage of LO transistorand thus their source terminal voltage changes, the gain of current-bleeding stage is also dropped.4.7 ConclusionBy adjusting the body voltage of the LO-stage transistors of an active mixer one can improvethe linearity of the mixer. The technique is particularly suitable for low-power mixers with lowLO power. This improvement in linearity is achieved without degrading the conversion gain (in89Table 4.1: Performance summary and comparison of the prototype mixers with other publishedworksCMOS fRF CG IIP3 PLO NF Pdc FoM1 FoM2 AreaProcess (GHz) (dB) (dBm) (dBm) (dB) (mW) (dB) (dB) (mm2)This Work10.13-µm 2.4 13.1 2.7 −10 16.5 2.4 16.4 21.4 0.28This Work20.13-µm 2.4 16 −4.9 −10 18.7 0.78 16.7 21.7 0.18[59] 0.18-µm 2.4 11.2 15 − 13.8 14.8 16.4 − 0.67[60] 0.13-µm 0.93 10.3 12.4 − 11.5 8 15.5 − −[61] 0.18-µm 2∼11 6.9±1.5 6.5 −5 18.5 25.7 8.9∗ 15.9∗ 0.48[63] 0.13-µm 2.4 10.1 3.8 − 21.7 7.2 5.4 − 0.32∗FoMs are calculated based on CG = 6.9 dB and fRF = 11 GHzthe conventional double-balanced mixers as shown in first prototype). Table 4.1 summarizesthe performance parameters of the designed mixers and compares them to the state-of-the-artmixers. To compare the performance of the mixers the following commonly used figures of merit(FoMs) are considered [68, 69]:FoM1 = 10 log(10(CG+IIP3−2NF−10)20P.fRF1GHz)(4.21)FoM2 = 10 log10 (CG+IIP3−2NF−PLO−10)20P.fRF1GHz(4.22)where NF is the double-side band noise figure, PLO is the power of LO signal and P is the DCpower consumption of circuit. These two FoMs are very similar except that FoM2 takes theLO power into account.90Chapter 5Body Biasing in Voltage ControlledOscillators (VCOs)As explained in Section 2.3, voltage-controlled oscillators (VCOs) are used as a part of frequencysenthesizers which provide the local oscillator of the system in RF fornt-ends. There are differentperformance parameters for VCOs such as drive capability, output waveform, supply sensitivityand power consumption. However, the most challenging performance parameters of a VCO aretuning range and phase noise. Unfortunately, these two parameters are in direct trade-off andthus (voltage-controlled) oscillators with large tuning range such as ring oscillators suffer fromlow phase noise while low phase noise oscillators such as resonator-based oscillators have lim-ited tuning range. However, due to the vital importance of phase noise in wireless transceivers,resonator-based VCOs are usually utilized in such applications and tuning enhancement tech-niques are incorporated to them. In the following two sections of this chapter, we overview theproblem of phase noise and tuning range in cross-coupled LC VCOs. Moreover, body biasingis introduced as the technique that can be utilized to improve these two performance metricsin cross-coupled LC VCOs.5.1 Application of Body Biasing to Improve the Phase Noise inCMOS LC VCOsPhase noise is one of the most important performance metrics of voltage-controlled oscilla-tors (VCOs) and its importance is steadily growing as the spectrum of standards is gettingmore populated to use the bandwidth more efficiently. The most popular solution for (voltage-controlled) oscillators in front-end of wireless transceivers, are resonator-based or LC oscillators.91Phase noise study of CMOS LC oscillators has been one of the hot research topics for a longtime (e.g., see [70, 71, 72, 73, 74, 75, 76, 77, 78, 79]), specially after the emergence of the linear,time-variant (LTV) phase noise model introduced in [71]. A new category of LC oscillators,namely class-C LC oscillators, has been introduced more recently [76] and has been consideredas an attractive alternative to conventional cross-coupled LC -tank oscillators for low-power ap-plications as they use the tail current more efficiently to provide higher oscillation amplitudeat the same tail current. This is due to the fact that the core transistors in a class-C oscillatorconduct short current pulses within less than half a cycle of oscillation with a peak currentamplitude that can be larger than the tail current [76]. Class-C LC oscillators also show abetter phase noise performance comparing to conventional cross-coupled LC oscillators due totheir noise shifting property which can be explained by the LTV model of [71].One of the most ambiguous issues in phase noise analysis of cross-coupled LC oscillators isthe effect of capacitance at the common source of its core transistors. This issue has attracted aconsiderable amount of attention in the literature and has resulted in different conclusions whichsometimes seem contradictory. For example, while in [72, 75], the addition of a large capacitor atthe tail node of oscillator has been advised, the work in [73] finds this capacitance as performancelimitation factor and tries to cancel the effect of parasitic capacitance at this node by includingan extra LC filter at the tail which resonates this capacitance out. Interestingly, as shown in[76], by applying a small change to regular LC -tank oscillator of Fig. 2.20, such oscillator canbehave as a class-C oscillator, i.e., conduct a short and tall current pulse in each core transistorwhen the transistor is turned on. Based on this study, if a relatively large capacitor is addedat the tail node of an LC -tank oscillator, the circuit could be equivalent to a class-C oscillator.As class-C oscillators are known for better phase noise comparing to conventional cross-coupledLC oscillators, this observation seems to be in harmony with [72, 75] and in contrast with [73].In this section, we first briefly overview the phase noise model of conventional cross-coupledLC oscillators in Sections 5.1.1 and 5.1.2. In Section 5.1.4, the effect of tail capacitance and itsrelation to class-C mode of operation will be explained in more detail and the above-mentionedcontradiction about its advantage and disadvantage is discussed. Section 5.1.5, is devoted to adeveloped model for class-C mode of operation in cross-coupled LC oscillators in the originalform of Fig. 2.27 and with no circuit-level modification in their structure. It is shown that class-92C mode can be achieved only when the amplitude of oscillation is small which is the case forultra low power, low voltage oscillators. Using the developed model of Section 5.1.5, in Section5.1.6 the positive effect of increasing the tail capacitance on phase noise performance class-CLC oscillators is explained. Moreover, it is shown that the increase in the tail capacitance canbe achieved through forward biasing of the bulk terminals in cross-coupled core transistors ofthe oscillator. Section 5.1.7, includes the experimental results on three fabricated prototypes.Based on the measurement results, it is shown that the achieved improvement in phase noisethrough increasing the tail capacitance by forward body biasing is on the same order of addingthe LC noise filter of [73] which is a considerable save in silicon area. Concluding remarks canbe found in Section 5.1.8.5.1.1 Linear, Time-Invariant (LTI) Analysis of Phase NoiseThe most famous phase noise analysis model is known as Leeson's theory [80]. This theoryof phase noise is based on the simple feedback model of Fig. 2.15 or its equivalent one-portmodel (Fig. 2.16) and considers the process of creation of phase noise in oscillators as a linear,time-invariant (LTI) process. Before explaining the Leeson's analysis of phase noise, we firstexplain about the additive noise and its conversion to phase and amplitude noise. Let usrewrite the Eq. 2.27 by adding the total noise term (n(t)) to the output of the ideal oscillator:x(t) = A0 cos 2pif0t+ n(t) (5.1)in which f0 is the oscillation frequency (resonance frequency of the tank in LC oscillators). Itcan be shown [81] that for narrow-band noise, n(t) can be divided into two components, namely,in-phase (nI(t)) and quadrature (nQ(t)) components or in other words amplitude modulated(AM) and phase modulated (PM) noise signals:n(t) = nI(t) cos 2pif0t− nQ(t) sin 2pif0t (5.2)Note that if n(t) is a narrow-band noise in vicinity of f0, nI(t) and nQ(t) are base-bandnoise (around DC) and their power spectral density (PSD) is the same as n(t) multiplied bytwo in the amplitude [33]. Therefore Eq. 5.1 can be written as:93x(t) = (A0 + nI(t)) cos 2pif0t− nQ(t) sin 2pif0t (5.3)or equivalently [33]:x(t) =√[A0 + nI(t)]2 + n2Q(t) cos(2pif0t+ arctannQ(t)A0 + nI(t))(5.4)which clearly shows the presence of both amplitude and phase modulation of x(t) by n(t).However, for phase noise, we are only interested in phase modulation term and by assumingnQ(t) A0, we can approximate phase noise in Eq. 2.27 (ϕn(t)) by:ϕn(t) ≈ nQ(t)A0(5.5)substituting this in Eq. 2.27:x(t) ≈ A0 cos 2pif0t− nQ(t) sin 2pif0t (5.6)Note that the amplitude noise variations in Eq. 5.4 is neglected here, assuming that am-plitude noise is deleted by passing the signal through a limiter [33]. It can be proved thateach of the in-phase and quadrature noise components carry half of the additive noise power[33, 1, 81]. Therefore from the above equation, it can be concluded that half of additive noisen(t) is converted to phase noise while the rest of the power is converted to amplitude noise.This conclusion can also be intuitively understood if the diagram in Fig. 5.1 is considered. Inthis phasor diagram, the noise component at f0 + ∆f has been modeled with small rotatingphasor with relative rotation frequency of ∆f , added to the end of the phasor of the main com-ponent (A0 cos 2pif0t). This rotating phasor can be decomposed into two in-phase phasors withrelative frequency of +∆f and two anti-phase phasors with relative frequency of −∆f to themain component. Grouping these four phasors to two groups, each containing a pair with ±∆frelative rotation frequency, it results in having one phasor which only modulates the phase andone phasor which only modulates the amplitude.Understanding the difference between amplitude and phase noise, the Leeson's model can beinvestigated. Here similar to [1], the one-port model (Fig. 2.16) is chosen to show the Leeson's94					Figure 5.1: Decomposition of additive noise component into phase noise and amplitude noise[70]approach to analyze phase noise. Alternatively, negative feedback model can be used [33]. Ifone-sided power spectral density of thermal noise of the tank resistance (RP ) is modeled by anoise current source, the value of current source is given by:i2n4f =4kTRP(5.7)This noise component is filtered by the frequency response of the impedance of LC -tank whichat ∆ω offset form the oscillation frequency can be approximated by:|Ztank (ω0 + ∆ω)| ≈ RP · ω02Q∆ω(5.8)Thus, the PSD of the resulting noise voltage at ∆ω offset form the oscillation frequency thetank would be equal to:v2n4f =4kTRP· |Ztank|2 = 4kTRP(ω02Q∆ω)2(5.9)Since only half of additive noise is converted to phase noise, Eq. 5.9 is divided by two andafter normalizing the phase noise power into the signal power (A20/2), the following equation isobtained for the relative phase noise power:L (∆ω) = 10 log[4kTRpA20·(ω02Q∆ω)2](5.10)95 		Figure 5.2: LC tank and equivalent noise current sourceThis equation has the unit of dBc/Hz (decibels below carrier per hertz) and is specified atparticular offset frequency (∆ω) from the carrier frequency (ω0). As can be seen from thisequation, Q of the resonator has a very strong effect on phase noise and the higher the Q is,the lower the phase noise will be at a given offset frequency (∆ω). This effect can also bepredicted by noticing that larger Q values, results in sharper fall in frequency response of theLC tank which further attenuates the thermal noise of the tank. This filtering property of LCoscillators (Fig. 5.2) can be considered as the reason for their superiority in terms of phasenoise performance over ring oscillators [1, 33]. Also, note that Eq. 5.10 show a 1/f2 frequencydependent behavior and the value of phase noise power decreases with slope of -20 dB/decadeas the offset frequency increases. Another point in Eq. 5.10, is that increasing the amplitude ofoscillation (A0) improves the phase noise performance.Eq. 5.10 does not provide a complete view of phase noise as it does not take the noise ofactive devices of oscillator into the account. Noise of active components always include a 1/fFlicker noise which when multiplied by the 1/f2 frequency behavior of Eq. 5.10, introduces anew region with 1/f3 frequency behavior at low offset frequencies. Moreover, the 1/f2 frequencybehavior of Eq. 5.10 does not continue without limit and at some point it eventually reachesthe thermal noise floor of the system. Considering all of these factors, the more complete formof Eq. 5.10, known as the Leeson's equation can be written as [80]:L (∆ω) = 10 log[4FkTRpA20·{1 +(ω02Q∆ω)2}(1 +∆ω1/f3|∆ω|3)](5.11)in which F is a fitting parameter which includes the effect of thermal noise of active componentsof the oscillator of Fig. 2.27 after translation into the tank of oscillator. ∆ω1/f3 is the frequencyat which1/f3 behavior of Eq. 5.11, switches to 1/f2 behavior and is considered to be equal to96	Figure 5.3: Generic phase noise plot based on Leeson's equationcorner frequency of Flicker noise of active devices. Based on this model, the phase noise plot ofa generic LC oscillator looks as the one in Fig. 5.3.5.1.2 Linear, Time-Variant (LTV) Analysis of Phase NoiseThe analysis in previous section is based on concepts such as transfer functions and filteringand assumes the phase noise process as an LTI process. While the Leeson model has been usedextensively to the date due to the insights that it provides for designers, it can not provideaccurate predictions for quantitative value of phase noise [1, 33]. To address this issue, morerecently, a time-variant model has been introduced in [71] and has provided a significant im-provement in our knowledge on how phase noise is created in an oscillator. The the followingexperiment forms the base of this phase noise model. Suppose that an ideal impulse is appliedto the LC tank of an oscillator (Fig. 5.4). The amount of phase shift in the output voltageof the oscillator, is dependent on the impulse amplitude and more interestingly on the instantat which the impulse is applied. In other words, if the impulse is applied at the instant thatvoltage of oscillation is at its maximum (or minimum), there will be no change in the oscillationphase and only amplitude of oscillation increases. On the other hand, if the impulse is appliedwhen oscillation is at its zero-crossings, the impact of the applied impulse will be pure phaseshift and amplitude of oscillation stays the same. While the amount of phase shift dependson time, at any specific time, the resultant phase shift is linearly related to the amplitude of97Figure 5.4: Time-variance in LC oscillators [71]applied impulse [71]. Therefore, one may consider the oscillator as a linear, time-variant (LTV)system [71]7. Since oscillator is still a linear system in this model, an impulse response can fullydescribe it. However as the system is not time-invariant, the impulse response is a function ofboth time (t) and the instant at which the impulse is applied (τ). It is proven in [71] that theimpulse response of the system is in the form of:hφ(t, τ) =Γ(ω0τ)qmaxu(t− τ) (5.12)in which Γ(x) is a dimensionless periodic function with period of 2pi and is called the impulsesensitivity function (ISF) and qmax is the maximum charge swing across the tank.For example, in LC oscillators, if the output voltage is shown with A0 cosω0t, then ISFwill be sinx to show the fact that the sensitivity of oscillator to an injected perturbation ismaximum when the output voltage is crossing zero and is minimum when the output voltage isin maximum (Fig. 5.5 (a)). Another example has been shown in Fig. 5.5 (b). Using Eq. 5.12,the total phase shift of the oscillator, resulting from perturbations including any injected noiseat the tank can be calculated using the convolution integral:7Note that the input of system is current injected to the tank and the output is the resultant phase-shift (nottank voltage).98   Figure 5.5: Examples of impulse sensitivity functions (a) LC oscillators (b) ring oscillators [71]φ(t) =+∞ˆ−∞hφ(t, τ)i(τ)dτ =1qmaxtˆ−∞Γ(ω0τ)i(τ)dτ (5.13)As ISF is a periodic function, it can be expressed by a Fourier series:Γ(ω0τ) =c02+∞∑n=1cn cos (nω0τ + θn) (5.14)in which cn are real coefficients and θn are phase shift at n-th harmonic. Neglecting these phaseshifts (θn)8, Eq. 5.13 can be rewritten as:φ(t) =1qmaxc02tˆ−∞i(τ)dτ +∞∑n=1cntˆ−∞cos (nω0τ) i(τ)dτ(5.15)The direct result of Eq. 5.15 is that the total phase noise, is a sum of input noise components(injected to the tank) at nω0 which are down-converted and weighted by the coefficients ofFourier series of corresponding ISF as shown in Fig. 5.6. This equation shows the importanteffect of ISF function on the phase noise equation of oscillators. The power spectrum equationfor phase noise can be derived as follows [1, 71]:L (∆ω) = 10 log i2n∆f ∑∞m=0 c2m2q2max∆ω2 = 10 log i2n∆f Γ2rms2q2max∆ω2(5.16)8Noise components at different harmonics are assumed uncorrelated [1].99   	Figure 5.6: Conversion of noise components at harmonics of oscillation to phase noise [71]where Γrms is the rms value of ISF.It is also very insightful to include the cyclostationary behavior of noise sources into the ISF.To illustrate this issue, consider that rather than the time-variance of the response of oscillatorto the input noise, the value of noise itself also changes with time. An example for this isthe channel-noise of cross-coupled transistor in the LC oscillator of Fig. 2.27. The channelnoise of transistors (4kTγgm) is a function of their transconductance (gm) which in turn is afunction of bias current. In the LC oscillator of Fig. 2.27, with the large signal operation ofoscillator, the bias currents periodically and significantly change, making the noise of transistorsa cyclostationary process [33, 1]. To quantify this, a cyclostationary noise in(t), is sometimesassumed as the production of a stationary noise in0(t) and a noise modulating function (NMF),shown by α(ω0t):in(t) = in0(t) · α(ω0t) (5.17)Based on this equation, Eq. 5.16, can be rewritten as:100Figure 5.7: Cyclostationary noise and noise modulating function [1]L (∆ω) = 10 log i2n0∆f Γ2eff,rms2q2max∆ω2(5.18)in which Γeff (x) = Γ(x) · α(x) and is a function that captures all of the time-dependencies,including those associated with oscillator's output waveform and cyclostationary noise sourcesof the oscillator. Also, Γeff,rms is the rms value of Γeff (x). An example of cyclostationarynoise and NMF is depicted in Fig. 5.7.5.1.3 Phase Noise in Cross-Coupled CMOS LC OscillatorsPhase noise study of CMOS LC oscillators has attracted a lot of attention during past decade(e.g., see [70, 71, 72, 73, 74, 75, 76, 77, 78, 79]), specially after the emergence of phase noisemodel in [71]. Despite the more accuracy that the LTV model provides, many designers feelmore comfortable to work with the simple Leeson's equation (5.11) rather than more complexconcepts such as ISF and NMF described in previous section. In this section, we try to brieflyoverview the analysis of phase noise in CMOS LC oscillators, trying to include useful insightsfrom both the LTI and LTV theories of phase noise.The noise sources in the oscillator of Fig. 2.27 are divided to the noise of the resistive lossof LC -tank, noise of cross-coupled transistors and noise of the tail current source transistor. InSection 5.1.1, the noise of one of the tanks of the oscillator was included into analysis and the101 Figure 5.8: Non-ideal switching in cross-coupled transistorseffect of the rest of noise sources was shown as a fitting parameter (F ) in Eq. 5.11. Based onEq. 5.11, one can claim that if the unknown F factor is calculated for a specific oscillator, itsphase noise is completely predictable9.We first start with the contribution of noise of cross-coupled transistors to the phase noise.In the cross-coupled LC oscillator of Fig. 2.27, ideally the tail current is switched abruptlybetween the two branches of the oscillator. However, as the differential pair I-V characteristicis not ideal, there will be a switching period (Ts) each time the tail current is switched betweenthe branches as depicted in Fig. 5.8. Outside the switching period, the tail current is fullycarried by one of the cross-coupled transistors while the other one is in cut-off. If the transistorcarrying the tail current stays in saturation, its noise current can not be flown in the circuit asit is in series with tail current source [70, 73]. However, during the switching period, both ofthe cross-coupled transistors are on and they both operate in saturation region [70, 73] andtherefore the noise of transistors in saturation region is circulated in the differential path fromone of the tanks to the other one. In another words, as noise of cross-coupled transistors canflow in the circuit only during the switching periods, the thermal noise of them is sampled by atrain of pulses with duration of (Ts)10and frequency of second harmonic of oscillation (there aretwo switching in each period of oscillation). The sampled noise looks as in Fig. 5.9. Since, theequation for PSD of thermal noise of channel is given by 4kTγgm [29], the equivalent equationfor this sampled noise, appearing across the LC tank is:9Neglecting other limitations and inaccuracies in Leeson's equation as described in [1].10Here square sampling pulses are assumed. In reality the pulses are not square and they are in sinusoidalform.102Figure 5.9: Sampling of thermal noise of cross-coupled transistors by large-signal oscillationi2n∆f= 4kTγgm2TsT0(5.19)in which T0 is the oscillation period and Gm = gm2TsT0is the average value of large-signalvariations of transconductance of cross-coupled transistors.Eq. 5.19 is derived based on the assumption that outside the switching time, the ontransistors stays in saturation. While this may be a valid assumption in some applications, inmany of them the on transistor enters deep triode region if oscillation amplitude is beyonda limit. This region named as voltage-limited regime [72] is known as the region in which theamplitude of oscillation is no longer depends linearly on the tail current [72]. In this regime, thedrain-source voltage of cross-coupled transistors drops significantly and therefore a large dropappears in core transistor currents (Fig. 5.10). From another perspective, this new waveformfor oscillator core transistors currents can be considered as the emergence of second harmoniccurrent components in the oscillator [33, 73]. In such cases, similar to the approach for obtainingEq. 5.19, the average value of large signal variations of transconductance (Gm) of cross-coupledtransistors should be calculated and replaced in 4kTγGm. This has been done in [33] and it isshown that the equivalent PSD of the thermal noise of core transistors is equal to:i2n∆f=38kTγgm (5.20)103  	 	Figure 5.10: Waveform of core transistor currents voltage-limited and current-limited regimesNote that Eq. 5.20 has a larger value than Eq. 5.19 as38 is generally larger than8TsT0in Eq. 5.19.Writing the above equation in the phase noise format of Eq. 5.10 and considering gm = 1/RP(oscillation criteria), we will have:L (∆ω) = 10 log[4kTRp(332γ)A20·(ω02Q∆ω)2](5.21)The only remaining noise source whose effect on phase noise should be investigated is thenoise of tail current source in Fig. 2.27. For the noise of tail current source transistor, theswitching action of cross-coupled transistors due to the oscillation, seems like switching of LOstage transistors in a single-balanced mixer [33, 70, 73]. Therefore, noise spectrum of the tailtransistor is up-converted and down-converted by oscillation frequency (f0). Most importantly,the noise components of tail transistor around second harmonic of oscillation(2f0) are down-converted to f0 and noise components around DC including the Flicker noise of tail transistor,are up-converted to f0. Interestingly, similar to the analysis in Section 5.1.1, it can be shownthat noise components around zero frequency do not have any effect on phase noise and areconverted to amplitude noise only [70]. However, the noise components around the secondharmonic of oscillation is down-converted to f0 by first and third harmonic of the square wave.Considering that gain of a single-balanced mixer is one third at the third harmonic, the resulting104noise components translated across the LC tank is equal to:i2n∆f=((1 +13)× 2pi)2· 4kTγgm,bias (5.22)Rewriting this equation into the format of Eq. 5.10, phase noise power equation can be writtenas:L (∆ω) = 10 log[4kTRp(1289pi2γ · gm,bias ·RP)A20·(ω02Q∆ω)2](5.23)The F coefficient in Eq. 5.11 for cross-coupled LC oscillators can be calculated by addingequations 5.10, 5.21 and 5.22:F = 2 +332γ +1289pi2γ · gm,bias ·RP (5.24)in which the first term is to consider both the resonators into the account. Looking into Eq.5.24, one may notice due to the conversion gain of mixing behavior, i.e.2pi · gm,bias · RP , thethird term in this equation has a very strong effect on overall phase noise.Another important point about phase noise in cross-coupled LC oscillators is that, althoughthey exhibit a very good phase noise performance due to the filtering of the noise at their output,the value of Γeff,rms for core transistors is not the smallest comparing to other LC oscillators,especially Colpitts oscillators. To illustrate this point, one may notice that the noise of cross-coupled transistors are injected to the tank during the switching of core transistors as depictedin Fig. 5.9. This is the worst moment for injection of noise as the value of Γ(x) is maximumat zero-crossings of output voltage for sinusoidal output oscillation waveform. In other words,the peaks of noise modulating function (NMF) and impulse sensitivity function Γ(x) coincidein cross-coupled LC oscillators and therefore Γeff (x) has a large rms value. In contrast, inColpitts oscillators, core transistors are biased below threshold voltage (Vth) and therefore theyonly conduct for a fraction of oscillation period during the peak of oscillation voltage, i.e. themoments which oscillator has the least sensitivity to the applied noise (or equivalently whenΓ(x) is minimum) (Fig. 5.11).In another words, NMF and ISF cancel the effect of each other, leading to a small value for105Figure 5.11: Noise-shifting property of Colpitts oscillators [1]Figure 5.12: Comparison between NMF of Colpitts and cross-coupled LC oscillators [82]rms for Γeff (x). This comparison between Colpitts and cross-coupled LC oscillators has beenstudied in more detail in [82, 83]. Fig. 5.12 form [82] illustrates this issue. The fact that inColpitts oscillators transistors are biased below threshold voltage has caused Colpitts oscillatorsto be considered as class-C oscillators. We return to this issue in Section 5.1.5.5.1.4 Tail Capacitance; Advantages and DisadvantagesOne of the most ambiguous issues in phase noise analysis of cross-coupled LC oscillators isthe effect of capacitance at the common source of its core transistors. This issue has attracteda considerable amount of attention in the literature and has resulted in different conclusions106which sometimes seem contradictory. For example, while in [72, 75], the addition of a largecapacitor at the tail node of oscillator has been advised, the work in [73] finds this capacitanceas performance limitation factor and tries to cancel the effect of parasitic capacitance at thisnode. Here, we try to clarify this issue which in turn forms the base of the idea of body biasingto improve phase noise.In Section 5.1.3, by inspecting Eq. 5.24, we came to the conclusion that the term arisingform the down-conversion of thermal noise of current source transistor, has a pronounced effecton the overall phase noise. Therefore it is very important to attenuate this noise componentin LC oscillators. A very straightforward solution for attenuation of this noise component isadding a large capacitor (CT ) in parallel with the current source such that the noise componentaround 2f0 is short-circuited to the ground (Fig. 5.13). However, this will lead to a problem inconventional cross-coupled LC oscillators in which at each half cycle, the on transistor entersinto deep triode region. If a large capacitor is added at the tail node of such oscillators, theamount of drop in core transistors current (shown in Fig. 5.10) is increased and therefore moresecond harmonic component is produced. This effect is shown in Fig. 5.13. Larger CT values,produces more drop in current of M2 as the drain-source of the transistor is decreasing or inanother words a larger CT results in a stronger path for second harmonics of the core transistorscurrent as it is located in the common-path of the differential pair. It can be shown that thelarger drop in current of core transistors (second harmonic variations), increases the rms of itscorresponding Γeff (x) [76] or from another point of view, the equivalent PSD of Eq. 5.20 isincreased, which vanishes the improvements gained by filtering the thermal noise around 2f0 ofcurrent source. Other justification for deterioration of phase noise after adding CT is loading ofthe quality factor (Q) of the tank by the resistance of the transistor in triode region, connectedto the ground through a large CT [73].In order to solve this problem, two solution approaches are possible. First, removing thepath for second harmonic variations of core transistors currents to flow in, and second, stoppingthe transistors to enter deep triode region. The work in [73], uses the first idea. Shown in Fig.5.14, this technique decouples the large CT from the common source of transistors by placingan inductor (LT ) in between. Moreover, to remove the path for second harmonic flow, the valueof LT is chosen in a way to resonate the parasitic capacitance at the common-source node out.107	Figure 5.13: Tail capacitance; second harmonic flow and noise filteringThe noise filter composed of CT and LT has a pronounced effect in reducing the phase noise.The main disadvantage of this approach is utilization of an extra inductor and capacitor whichsignificantly increases the die area.The alternative approach to address the issue of tail capacitance, is keeping the core tran-sistors out of triode region and keep the large capacitor at the tail. Keeping core transistors outof triode region necessitates:vGD1,2 ≤ Vth (5.25)However, inspecting the circuit diagram of cross-coupled LC oscillator reveals that vGD,max =2A0 where A0 is the single-ended amplitude of oscillation. Therefore to ensure operation insaturation for core transistors:A0 ≤ Vth2(5.26)which means a small oscillation amplitude. According to Eq. 5.11, larger oscillation amplituderesults in a better phase noise. Therefore, keeping transistors in saturation region is at the108		Figure 5.14: LC noise filter in [73]expense of increasing the phase noise by reducing the oscillation amplitude. However, anotherobservation keeps this idea as a an appealing approach.First time reported by [72, 75], adding a large capacitor at the tail of cross-coupled LC oscil-lators can be used as a current-shaping approach. More specifically, adding a large capacitor atthe tail results in current pulses in the core transistors which are taller and narrower comparingto the original case. This is an absolutely interesting observation since narrowing the currentpulses, decreases the value of NMF at zero-crossings of voltage and therefore rms value Γeff (x)is decreased. Fig. 5.15 shows the idea of current-shaping. Based on the analysis in [75, 76], dueto taller current pulses in the core transistor, amplitude of oscillation is increased by a factorof 57% for a same tail current source. In another words, to achieve a specific amplitude ofoscillation, a a 57% smaller tail current source is needed and therefore the power consumptionof the oscillator is decreased too. This current-shaping approach makes the performance ofcross-coupled oscillators close to that of the Colpitts oscillator depicted in Fig. 5.11, i.e. coretransistors conduct during the time that output voltage waveform is at its maximum (or min-imum). Therefore we can say that by increasing the tail capacitance, similar to their Colpittscounterpart, cross-coupled LC oscillators could operate in class-C mode.109   	Figure 5.15: Current-shaping in cross-coupled LC oscillators5.1.5 Class-C Operation of CMOS Cross-Coupled LC OscillatorsAlthough [72, 75] have predicted the effect of large tail capacitor in cross-coupled LC oscillators,their theoretical explanations about the reason for improving the phase noise as well as thetransition to the class-C operation does not seem accurate enough. For example [75] usesan approximate small-signal model to derive the equations which is not accurate at large-signal operation of oscillators. Also the work in [72] explains the effect of the tail capacitancequalitatively . The best class-C oscillator theory can be found in [76]. In this work, the authorsstart from a differential Colpitts oscillator (as the classic class-C oscillators) and explain itsevolution to a cross-coupled oscillator. However, to prevent small oscillation amplitude, thegate of core transistors are biased at a voltage different from VDD and the output voltage iscoupled to the gate through coupling capacitors or transformers (Fig. 5.16). More recently,dynamic biasing scheme of core transistors has been introduced in [84].In this section a new theoretical explanation for class-C operation of cross-coupled LC oscil-lators in their original form (i.e., that in Fig. 2.27) is presented11. To understand how class-C11Note that more advanced structures such as push-pull class-C CMOS LC VCOs have also been recentlyreported in [85].110 Figure 5.16: Modified class-C cross-coupled oscillatorscross-coupled CMOS LC oscillators operate, the simplified voltage and current waveforms ofcross-coupled core transistors are depicted in Fig. 5.17. If the amplitude of single-ended outputof the oscillator is denoted as A0, the output voltage (which is the same as the cross-coupledtransistor gate voltage) can be written as (refer to Fig. 5.17 (a)):vO,+ = vG = VDD +A0 cos 2pif0t (5.27)Since the structure of oscillator is differential, the source terminal of the cross-coupled coretransistors can be considered as a virtual ground (i.e., AC ground with a DC value of VS).Therefore, the gate-source voltage of core transistors can be written as (Fig. 5.17 (b)):vGS = (VDD − VS) +A0 cos 2pif0t (5.28)If the value VS of is large enough (e.g., Itail is small enough), the DC component of the gate-source voltage of cross-coupled transistors, i.e., (VDD − VS), can be smaller than the thresholdvoltage of the core transistors (Vth). This in turn means that cross-coupled transistors conductonly during a fraction of each half-cycle (namely, during ton) and they are off for the rest ofthe half cycle (namely, for toff ), as depicted in Fig. 5.17 (c). T0 denotes the period. Assuming111a small amplitude of oscillation, the transistor is in the saturation region and thus its currentcan be approximated by the square-law current equation. Therefore, M1 and M2 generatetall and narrow square sinusoidal currents during ton. However, for the sake of simplicity, weapproximate these pulses by square-wave pulses as shown in Fig. 5.17 (c). Once again, Thefact that in class-C oscillators, the core transistors only conduct outside of the output voltagezero-crossing points is one of the key points in justifying their lower phase noise (as compared toconventional cross-coupled LC oscillators where both core transistors are on at the zero-crossingpoints of the output voltage).Inspecting the core transistor currents in Fig. 5.17 (c) and 5.17 (d), one may question whatis happening to the tail current when both core transistors are off. To answer this question,the operation phases of a class-C cross-coupled LC oscillator have been shown in Fig. 5.18. Inthis figure, when the core transistors are on (phases 1 or 3), their Cgs is shown as C1. Notethat the Cgs of transistors when they are off is typically small as compared to other capacitorsin the circuit and thus is not included in this model. The sum of parasitic capacitance at thetail node of oscillator is shown as C2. As shown in Fig. 5.18, during toff and when both coretransistors are off (phases 2 and 4), the only path for the tail current to flow is through thetail capacitance, i.e., C2. This means that C2 is being discharged during toff . However, theconservation of charge suggests that C2 has to be charged during ton. As shown in Fig. 5.18,in phases 1 and 3 the current of each core transistor (M1 and M2) provides the tail current andthe rest is divided between C1 and C2. This means that during ton, the transistor current hasto be larger than Itail. We denote this current by K · Itail (K > 1). As discussed before, thislarger amplitude of the core transistors' currents is another benefit of class-C oscillators as itleads to a higher oscillation amplitude for the same Itail or smaller Itail for the same oscillationamplitude as compared to conventional cross-coupled LC oscillators. The current of C2 durington can be written as:iC2 = (K − 1)× Itail × n (5.29)in which:112Figure 5.17: Voltage and current waveforms of a class-C CMOS LC oscillator (a) single-endedoutput voltage (b) gate-source voltage (c), (d) core transistors' currents (e) tail capacitancecurrent (f) tail voltage113    		  Figure 5.18: Operation phases of class-C CMOS LC oscillator in one cycle.114n =C2C1 + C2(5.30)Therefore, the waveform of iC2 is as shown in Fig. 5.17 (e). Also, if the voltage of C2is plotted (Fig. 5.17 (f)), it will results in voltage fluctuations at the tail node. Althoughwe started the analysis by assuming a constant voltage (VS) at the tail, if the value of C2 isrelatively large and the value of tail current is small, the amplitude of these fluctuations wouldbe small enough to be considered negligible as compared to VS . It should also be noted thatthese variation of the voltage as well as the current in C2 are second-harmonic variations asexpected from the differential nature of the circuit.If the Fourier series expansion of iM1 (or iM2) is written, the following expression is obtained:iM1 (ω0t) = K · Itail[tonT0+2tonT0sinc(pitonT0)cosω0t+ · · ·](5.31)Based on this equation, and considering the fact that the amplitude of oscillation is equal toamplitude of first harmonic of core transistors current times the tank resistance, the followingequation can be written:Adiff = 2× 2tonT0sinc(pitonT0)·K · Itail ·RP (5.32)in which the factor of two is added to calculate the differential oscillation amplitude. Anotheruseful result of Eq. 5.31 is the DC value of iM1 (or iM2) :(iM1,2)DC= K · Itail · tonT0(5.33)Considering the fact that Itail is the current supplying this DC current in each core transistor,one can conclude that:Itail = 2×K · Itail · tonT0⇒ 2K · tonT0= 1 (5.34)Eq. 5.34 is suggesting that the product of K and ton is a constant value. Also, if this constantvalue is replaced in Eq. 5.32, the differential amplitude of oscillation would be:115Adiff = 2sinc(pitonT0)Itail ·RP (5.35)For very small ton values, i.e. very narrow pulses, the argument of sinc function will be verysmall and can be approximated by one. Therefore for very narrow current pulses in the coretransistor:Adiff ≈ 2Itail ·RP (5.36)which is 57% larger than4pi Itail ·RP [29] in conventional cross-coupled LC oscillators.It should be pointed out, the necessary condition for the above equations is the presence ofa large C2 at the tail node. If such a large capacitor does not exist, the AC second harmonicfluctuations at the tail node (Fig. 5.17 (f)) will no longer be negligible comparing to theDC value of tail voltage. In fact, large second harmonic variations at the tail will enter thecore transistors into the deep triode region which in turn vanishes the excellent phase noiseperformance of class-C oscillators.5.1.6 Application of Body Biasing To Improve Phase NoiseIn the context of cross-coupled LC oscillators, body biasing of core devices has been utilizedbefore ([25, 86, 87]), however, it is used in oscillators that do not have any current sourceat their tail nodes. LC oscillators which do not use a tail current source suffer from negativeeffects of process-voltage-temperature (PVT) variations and their bias current is not well-defined[33]. Moreover, in these works, by using body biasing, the threshold voltage of the cross-coupled transistors is reduced and therefore the oscillation amplitude is increased. The resultingimprovement in phase noise comes at the cost of increasing the power consumption of theoscillator, which is not desirable at very low-power applications. In contrast to [25, 86, 87],the approach which is introduced in this thesis, adjusts the ratio of intrinsic capacitance of theoscillator and virtually does not affect the power consumption of the oscillator. Furthermore,to show the effectiveness of the body-biasing approach, the phase noise performance of a proof-of-concept body-biased VCO is compared with that of a similar proof-of-concept VCO, whichincorporates an LC noise filter described in [73].116Effect of Body Biasing on Current Shaping and Class-C PerformanceLet us discuss how body biasing would affect the shape of current of the core transistors andhow this effect can be used to improve the phase noise performance in class-C mode of operationof cross-coupled LC oscillators. The main idea, is increasing the parasitic capacitance at tailnode of cross-coupled LC oscillator with small amplitude of oscillation and core transistors insaturation, and creating taller and narrower current pulses in core transistors of the oscillator.More specifically, if the bulk voltage of cross coupled transistors is increased, the source-bulkcapacitance of each device, which is a p-n junction capacitance, will also increase as suggestedby the following equation [28]:Csb =Csb0(1− VBSφB)m (5.37)in which Csb0 is the zero-bias capacitance, VBS is the source-bulk bias voltage and φB is thebuilt-in potential of the junction. Also, m is a constant approximately between 0.3 to 0.4. Thischange in Csb is confirmed by simulation where the results show 400% increase in the value ofCsb of cross-coupled transistors when the bulk voltage of these transistors is swept from =0.7 Vto +0.7 V12. This increase in Csb will lead to an increase in C2 in the circuit diagrams shownin Fig. 5.18 and thus based on Eq. 5.30, n increases. If the charge balance equation for C2 iswritten, the area (1) in Fig. 5.17 (e) should be equal to area (2) or equivalently:(K − 1) · n · Itail × ton = Itail × toff (5.38)Based on this equation, increasing n will increase the left-hand side of Eq. 5.38. To keep thecharge balance, toff should increase. However, the sum of ton and toff is constant since basedon Fig. 5.17:ton + toff =T02(5.39)Combining Eq. 5.38 and Eq. 5.39, the following equation is obtained:12Note that 0.7 V is the supply voltage used in this work. Also, note that for proper operation of the oscillatorcore, the source voltage of the core transistors has to be biased at a positive voltage and thus when the bulkvoltage is +0.7 V the bulk-source diode is not strongly forward biased.117ton =T0/2(K − 1) · n+ 1 (5.40)Based on Eq. 5.40, increasing n results in decreasing ton, i.e., shorter conduction time for coretransistors. However, from Eq. 5.34, if ton is decreased K should increase. This in turn meansthat increasing n results in larger value for K, i.e., taller current pulses in the core transistors.Thus, properly adjusting body bias will result in narrower (smaller ton) and taller (largerK) current pulses in the core transistors. While one may think that by increasing the height ofcurrent pulses in the core transistors, amplitude of oscillation is also increased at the same rate;this is not true if one takes Eq. 5.32 into account. Based on this equation, the amplitude ofoscillation is also a function of the product of K · ton. Although by increasing n, the height ofcurrent pulses, i.e., K, increases, since ton decreases at the same time, the product may remainconstant. This effect has already been considered in Eq. 5.35. As it can be seen from thisequation, increasing n does increases the amplitude but at a much slower rate as ton decreasesin the argument of sinc function. Also, as discussed before, the shorter the ton, the lower theNMF associated to the noise source in sore transistors, which in turn results in improving thephase noise performance.Note that although simulated current pulses for various body biasing seems to be interestingplots here, the drain current of the transistors reported by typical simulators includes drain-source channel current as well as the charging and discharging currents for the intrinsic deviceparasitic capacitors such as Cgs, Cdb, Cgd and etc.; we are interested in the channel currentas it is this current that needs to be taken into account in the noise analysis [75]. Withthe available models the drain-source and capacitive currents cannot be separated. However,simulation results show that by increasing the body bias (up to a limit), the peak of the devicecurrent (which includes both the drain-source channel current as well as parasitic capacitancescurrents) increases; this is in agreement with the expected results. For example, Fig. 5.19 showsthe simulated device current for two different values of Vbulk (0 V and 0.6 V).118Figure 5.19: Simulated current pulses of core transistors for optimum body bias and no bodybias cases.Effect of Body Biasing on Attenuation of Tail Current Source NoiseAs explained in Section 5.1.4, to attenuate the dominant effect of thermal noise of current sourcetransistor, a large capacitor can be added in parallel to the tail current source to filter this noisecomponent. It is clear that the larger this added capacitance is, the better will be the filteringof the noise. Therefore, forward body biasing of core transistors, is in favor of this filtering asit increases the tail parasitic capacitance.In previous section, we explained that having a large C2 is a necessary condition for class-Coperation as in its absence large second harmonic variations at the tail node will bring the coretransistors into triode region and oscillator will no longer be in class-C mode. Here, we areshowing that, larger C2, not only results in a better phase noise performance through class-Coperation (narrower and taller current pulses in the core transistor), but it also improves thephase noise through stronger attenuation of dominant (see (5.24)) thermal noise of tail currentsource transistor around 2f0 to phase noise.Limits on the Bulk VoltageWhile based on the above justifications, forward body biasing of cross-coupled transistors resultsin improvement in phase noise performance through adjusting the value of intrinsic capacitance119		(a) (b) (c)Figure 5.20: (a) Micrograph and (b) the schematic of fabricated prototype (c) measured outputspectrum of the fabricated body-biased VCOs in 0.13-μm CMOS processof core transistors, there is a limit on how high the bulk voltage can be. To understand thislimit, note that the above analysis is based on class-C operation of LC oscillators. As mentionedbefore, a very important condition for the class-C behavior is small amplitude of oscillation(small gate-drain voltage) so that the core transistors ideally do not operate in the trioderegion, that is their gate-drain voltage is less than Vth or equivalently as in Eq. 5.26, A0 ≤ Vth2 .However, as the bulk voltage is increased, the threshold voltage is decreased and thus the coretransistors are pushed toward the triode region. Once again, if core transistors enter the trioderegion, the benefits of class-C operation are vanished mainly due to a large drop in the currentof the core transistors and the impulse-like current waveforms are no longer observed. In theabsence of the impulse-like currents, the noise shifting property of class-C oscillators is disturbedand Γeff,rms is increased which in turn results in increased phase noise.Also, as explained in Section 3.3, the bulk resistance noise of MOS transistors is proportionalto the square of the bulk-source transconductance (gmb) as predicted by Eq. 3.15. Therefore,increasing the bias of the bulk terminal of the cross-coupled transistor will introduce a new noisesource into the circuit which slows down the phase noise improvements achieved by forward bodybiasing of the cross-coupled transistors.5.1.7 Experimental ResultsTo validate the proposed technique, a proof-of-concept prototype LC oscillator is implementedin a 0.13-μm CMOS process. A micrograph of the prototype chip is shown in Fig. 5.20 (a).120  	   	   !"#!$#% &!' '()% &!'*( !)%&!' '()%&!'*( !)(a)(b)Figure 5.21: (a) Phase noise variation versus bulk voltage of core transistors, (b) measuredphase noise plots of the prototype oscillator with and without forward body biasing of coretransistorsThe oscillator draws 800 μA from a 0.7 V supply while operating at the nominal frequency of3.6 GHz. The schematic of the oscillator and its output spectrum are shown in Fig. 5.20 (b)and (c). The phase noise measurements have been performed at 1 MHz offset from the centerfrequency. As shown in Fig. 5.21, the phase noise is a strong function of the bulk voltage ofthe cross-coupled core transistors. The measured phase noise of the oscillator for two cases ofno body bias and forward body bias is shown in Fig. 5.21. Based on the measurement results,a phase noise improvement of more than 12 dB is achieved as compared to the situation whenthe bulk of cross-coupled transistors is biased at 0 V (no body biasing). In this prototype, thebest phase noise performance is achieved at Vbulk = 0.6 V with the corresponding phase noiseof -108.2 dBc/Hz at 1 MHz offset.121		(a) (b)Figure 5.22: (a) Micrograph of the second fabricated prototype VCOs with LC noise filter (b)the schematic of the fabricated prototypeTo compare the performance of the proposed body biasing technique with that of the tailfiltering approach [73], a second prototype is also implemented that uses the same oscillatoras the first prototype along with an LC noise filter added to the tail as shown in Fig. 5.14.Fig. 5.22 shows the micrograph and schematic of the second prototype. When the tail noisefilter is used, we expect that the phase noise would not be a strong function of the value ofintrinsic parasitic capacitance (and thus the bulk voltage of core transistors) because the tailfilter inductor resonates with the capacitance seen at the common tail node. Also, it is interestingto note that about the same phase noise improvement achieved from using the tail filter hasbeen achieved with the proposed body biasing technique, without using the filter. Although theproof-of-concept chip was not optimized for phase noise performance and was meant to validatethe effects of body biasing on the phase noise of cross-coupled CMOS oscillators, it achieves afigure of merit (FoM) of 182 dBc/Hz which still compares favorably with state-of-the-art designs.The FoM used here is a commonly used FoM for oscillators (e.g. see [33, 73, 75, 76, 79]) andis defined as:FoM = −L(∆ω) + 20 log( ω0∆ω)− 10 logP (5.41)Note that, although this FoM is a good measure for comparing the performance of various122(a) (b)Figure 5.23: (a) Die micrograph of a 90-nm CMOS oscillator test chip and (b) the measuredoutput spectrumFigure 5.24: Plot of measured phase-noise at 1-MHz offset versus bulk voltage of cross-coupledtransistors.VCOs, if low power and low voltage of the design are important, then the FoM by itself maynot be sufficient measure to evaluate the performance of the oscillator.To show the independence of the body biasing benefits from the technology node, a thirdprototype has been fabricated in 90-nm CMOS technology. Fig. 5.23 shows the chip micrographas well as the measured spectrum of the oscillator. Three chips have been measured and eachphase noise measurement has been repeated at least 10 times. The centre frequency of theoscillator is 2.54 GHz and without bulk biasing, the oscillator has a phase-noise of -94 dBc/Hzat 1 MHz offset from the carrier. Fig. 5.24 shows the measured phase-noise of the oscillatoragainst the bulk voltage of cross-coupled transistors. In this Figure, the error bars represent±σ (i.e. ±1 standard deviation) of the mean value of the measured phase-noise at each bulkvoltage. As can be seen from the Figure, the body biasing improves the phase noise from -94dBc/Hz (when Vbulk= 0 V) to -101 dBc/Hz (when Vbulk= 0.5 V) at 1 MHz offset. This is a 7123Table 5.1: Comparison of the prototype VCO with the state-of-the-art low-power VCOs[9] [18] [76] [88] [89] [90] This WorkProcess (nm) 130 90 130 180 90 65 130Supply (V) 0.4 0.22 1.0 0.2∗1.2 0.65 0.7Power (mW) 0.7 0.33 1.3 0.11 0.53 8.71 0.56f0(GHz) 2.38 3.55 4.9 4.5 2.16 5.49 3.6L(4ω) (dBc/Hz) -106 -113 -130 -104 -106.2 -113.3 -108.24ω (MHz) 1 1 3 1 0.4 1 1FoM (dBc/Hz) 175.1 188.8 196 187 183.6 178.7 182Area (mm2) ∗∗ 0.76 0.5 0.29 0.175 0.33 0.2∗A separate supply is used to bias the gate-source voltage at 0.45 V.∗∗Area of the VCO is not reported. The transceiver die area is 4.41 mm2.dB improvement in phase noise as well as the FoM. Also one may notice that the variations ofphase noise versus bulk voltage in the plot in Fig. 5.24 is similar to the plot in Fig. 5.21. Whilebody biasing approach has been tested here for only two technology nodes, namely 0.13-μmand 90-nm CMOS processes, the promising results of Fig. 5.21 and Fig. 5.24 can be a goodindication for concluding the benefits gained by body biasing approach is not dependent on thetechnology node.5.1.8 ConclusionClas-C operation mode of cross-coupled CMOS LC oscillators is modeled. A technique to adjustthe phase-noise performance of low-power cross-coupled CMOS LC oscillators by lowering theduty cycle in class-C mode of operation is presented. The approach relies on the effects ofbody biasing on the intrinsic capacitances and does not include any additional capacitors. Itis shown that by changing the bias voltage of the bulk of the cross-coupled core transistorsof the VCO, the ratio of intrinsic capacitances which in turn affects the phase noise can beadjusted. Moreover, it is shown that the phase-noise improvement obtained from body-biasingcan be used in lieu of using LC filtering approach reported in [73] and thus results in savingarea. Table I provides performance summary of the proposed body-biased 0.13-µm CMOS LCVCO (without noise filter) and compares it with recent low-power VCOs.By reviewing Table. 5.1, one may notice that other references such as [76] have reportedhigher values for their FoM. As mentioned before, given the low voltage and low power of thedesign (supply of 0.7 V and power of 560 µW) the phase noise performance is expected to be124	 	 	 	 		  (a) 	 	 	 	  	 	 	 	 			 	 	(b)Figure 5.25: (a) Corner simulation results (at room temperature of 27 ºC), (b) representativePVT variation plotsworse than other designs that have a higher supply and/or a higher power such as the designpresented in [76]. Although FoM is a good measure for evaluating the performance of variousVCOs, if low power and low voltage of the design are important, then the FoM by itself maynot be sufficient to evaluate the low-power and low-voltage performance of the oscillator. Also,note that, the proposed technique (adjusting phase noise with body biasing) can be used asan additional control to adjust the performance of a chip (for example, compensate for adverseeffects of process, supply voltage and temperature (PVT) variations) after it is fabricated. Infact, the body-biasing approach can be utilized in parallel with other phase noise reductionapproaches in order to compensate for process variations. Some example corner and PVTsimulations are shown in Fig. 5.25. As can be seen from the figure, by proper choice of body125 		Figure 5.26: Dependence of MOS varactor's quality factor on length of channel [33]bias voltage of the core transistors, one can adjust the phase noise performance. Also, in thepresence of process variations, the optimum phase noise performance varies by about 1 dB andin the presence of PVT variations the optimum phase noise performance varies by about 3 dB.5.2 Application of Body Biasing to Increase the Tuning Rangein Active-Inductor Based CMOS LC VCOsAs explained in Section 2.3.2, to tune the oscillation frequency of an LC oscillator, usuallyMOS varactors are incorporated into the oscillators. Moreover, to increase the tuning range ofLC VCOs, it is desirable to increaseCmaxCminratio of MOS varactors. However, when the channellength is small, the effect of overlap capacitors between gate and source/drain terminals, limitsthis ratio. The limiting effect of overlap capacitors is in in form of adding a constant capacitance(2WCov) to both Cmax and Cmin. In order to reduce this undesired effect of overlap capacitors,the channel length may be increased. However, this would results in lowering of the qualityfactor of the varactor. The reason is that quality factor in MOS varactors is defined by theresistance of channel between source and drain terminals (Fig. 5.26). Therefore, the longer thechannel, the larger the varactor's resistance and thus the lower the quality factor. As shown in[33], in an LC -tank, if quality factor of capacitor is shown by QC , and quality factor of inductorby QL, the overall quality factor (Q) will be equal to:1Q=1QL+1QC(5.42)126	Figure 5.27: Block diagram of a gyrator-C [36]Therefore one may conclude that although increasing the channel length increases theCmaxCminofthe varactor, it decreases the quality factor of the LC-tank which based on Eq. 5.11 increasesthe phase noise. In other words, in CMOS LC VCOs with passive components, tuning range isin trade-off with phase noise [33].5.2.1 Active Inductor TheoryFrequency tuning of LC VCOs can alternatively be achieved through changing the value ofinductance. While having a variable inductance is not an available option for VCOs with passiveinductors, it would be a possible option if active circuits are used to implement the inductanceof the tank. Such an inductor is called an active-inductor and has several advantages overthe conventional passive inductors. The first advantage is the huge saving in area as passiveon-chip inductors usually occupy a very large area. Other advantages of active-inductors overpassive inductors are large and tunable self-resonance frequency, large and tunable inductance,large and tunable quality factor and compatibility with digital CMOS technologies [36]. Thedrawbacks of using active inductors are limited dynamic range, a high level of noise, and a highsensitivity to process, supply voltage and temperature (PVT) variations [36].A typical circuitry which can realize the idea of active inductors is consisted of two back-to-back transconductance stages often called as a gyrator. When one of the ports of a gyratoris connected to a capacitor, the structure is called gyrator-C. Fig. 5.27 shows the diagram127	Figure 5.28: A basic gyrator-C active inductorsof a gyrator-C structure. It can be shown that port 2 of the gyrator-C structure in Fig. 5.27generates an inductance to the ground with value of :L =CGm1Gm2(5.43)Different transconductance stages can be replaced as the gm-stage in gyrator-C. Common-source amplifier, common-gate amplifier or even differential amplifiers are few examples. Fig.5.28 shows one possible realization of gyrator-C active inductors in which two common-sourceamplifiers have been used as gm stages of the gyrator-C. Here the parasitic gate-source capac-itance of M2 (Cgs2) acts as the capacitor of the gyrator-C. As shown in [36], the followingequations can be derived for parallel RLC model of this active inductor:Cp = Cgs1 (5.44)RP =1gm1(5.45)L =Cgs2gm1gm2(5.46)Another structure for active inductors is reported in [91, 92] and is chosen to work with inthe rest of this chapter (Fig. 5.29). Although this active inductor is very similar to that of128Figure 5.29: (a) Schematic and (b) equivalent circuit model of the active inductor used in thisworkFig. 5.28, it works with smaller voltage headroom. To analysis its performance, we first startwith the simpler version of this active inductor (shown in Fig. 5.30) which construct the coreof active inductor in Fig. 5.29. For the active inductor of Fig. 5.30, if the values of componentsin equivalent circuit model of Fig. 5.29 (b) is calculated, the following equations are obtained[91, 92]:L =RGCgs1rds+ gm(5.47)Rs =11rds+ gm(5.48)CP = Cds (5.49)where gm is the transconductance, rds is the output resistance and Cds is the parasitic drain-source capacitance of of PMOS transistor.Equations 5.47 to 5.49 are only valid if the PMOS transistor in Fig. 5.30 stays in saturationregion. This in turn results that the voltage of node X should be kept smaller than VDD−|Vth,P |.To reduce this headroom requirement, a level shifter is incorporated into the active inductor.Transistor M1 and M3 in Fig. 5.29 (a) build a source-follower stage which performs the task oflevel shifting. In this case the voltage of node X should be kept smaller than VDD+VGS1−|Vth,P |.129Figure 5.30: Simple active inductor with an PMOS transistor and a gate resistanceTherefore the headroom is increased by one VGS . For the active inductor of Fig. 5.29 (a) thefollowing equations are obtained for the parameters in its equivalent circuit model [91, 92]:L =Cgd1RGgm1gm2gm1+gm3+ 1rds2(5.50)Rs =1gm1gm2gm1+gm3+ 1rds2(5.51)CP = Cds2 (5.52)It should be noted here that resistor RG can be implemented by a MOS transistor in trioderegion. A MOS transistor in triode region shows a resistance between its source and drainterminal which is given by the following equation:Rtriode =1µnCoxWL (VGS − Vth)(5.53)Thus the schematic in Fig. 5.29 (a) can be replaced with the one in Fig. 5.31.5.2.2 Active-Inductor-Based CMOS LC VCOsIf the passive inductor in LC VCOs is substituted with an active inductor, an active-inductor-based LC VCO (AI-LC VCO) is obtained. In terms of principles of operation, there is almostno difference between LC VCOs with passive or active inductors and they both operate based130Figure 5.31: Active-inductor of Fig. 5.29 (a) with gate resistance realized by a triode transistoron the same oscillation principles discussed in Section 2.3.1. The only difference is that thelimit on amplitude of oscillation is tighter in AI-LC VCOs to provide the sufficient headroomfor transistors in the active inductor. Fig. 5.32 shows an AI-LC VCO in which the activeinductor of Fig. 5.31 has been incorporated to realize the inductance of the LC -tank of VCO.As discussed before the most important advantage of AI-LC VCOs is that they can offermore tuning range by changing the value of their inductance. By inspecting Eq. 5.50 and Fig.5.32, one may notice that in order to change the value of inductance of the active inductor,there are two options; first changing the transconductance of M1 to M6 through changing thevalue of Vtune1 control voltage, and second, changing the value of RG through changing the gatevoltage of transistors in triode, i.e. MG1 and MG2, through changing the value of Vtune2 controlvoltage. As will be shown in the experimental results section, these two control mechanism canprovide large tuning range for the VCO which is much larger comparing to a typical LC VCOswith passive components.5.2.3 Body Biasing to Increase the Tuning Range in AI-LC VCOsGenerally AI-LC VCOs have large tuning range comparing to the VCOs with passive inductors.In order to even increase the tuning range further, body biasing technique can be utilized asa tuning range enhancement technique. AI-LC VCO of Fig. 5.32 is used here to verify theeffect of proposed technique (i.e., body biasing) on increasing the tuning range. To understandhow body biasing can increase the tuning range, note that transistor M1 and M4 in Fig. 5.32,131Figure 5.32: Schematic of active-inductor-based LC VCO used in this workexperience the body effect as their source terminal is not tied down to ground. Therefore themore exact form of Eq. 5.50 can be written as:L =Cgd1RG(gm1+gmb1).gm2(gm1+gmb1)+gm3+ 1rds2(5.54)in which gmb1 is the bulk-source transconductance of M1 and M4. As discussed before, thebulk-source transconductance (gmb) is a function of bulk-source bias voltage (VBS):gmb =∂ID∂VBS= gm · γ2√|2ΦF |+ VSB = ηgm (5.55)Thus a third tuning control scheme in VCO of Fig. 5.32 would be through changing the bulkvoltage of M1 and M4 (VBulk1) which in turn changes the value of VBS1 (and VBS4) and thusgmb1 (and gmb4) in Eq. 5.54.There is a fourth method for changing the inductance as well and that is through changingthe bulk voltage of PMOS transistor, i.e. M2 and M5. The justification behind this tuningmechanism is that by changing the bulk voltage of M2 (and M5), i.e. VBulk2, the threshold132Figure 5.33: Chip micrograph of the prototype AI-LC VCO in 90-nm CMOSvoltage of PMOS transistor is changed. As the current passing through this transistor is set bythe tail current source of oscillator and is relatively fixed, changing the threshold voltage of M2(and M5) would change its gate-source voltage. Since the source terminal is tied up to VDD,the gate voltage of M2 (and M5) should change which in turn changes the bulk-source voltageof M1 (and M4) and thus its bulk-source transconductance, i.e., gmb1 (and gmb4).5.2.4 Experimental ResultsTo verify the idea of increasing the tuning range of an AI-LC VCO through applying bodybiasing to the transistors in the active inductor of Fig. 5.31, a prototype AI-LC VCO has beendesigned and fabricated in a 90-nm CMOS technology. Fig. 5.33 shows the chip micrograph ofthe fabricated proof-of-concept prototype. The VCO consumes 24 mW power while drawing 20mA from a 1.2 V supply. If value of Vtune1 as the conventional tuning voltage of the VCO inFig. 5.32 is changed from 0.8 V to 1.2 V, oscillation frequency varies from 2.2 GHz to 3.2 GHz,i.e., the tuning range of 1 GHz. Thus, the AI-LC VCO in its original form achieves a two-sidedtuning range of %37 around 2.7 GHz. Moreover, based on the measurement results, VCO hasphase noise of -72 dBc/Hz at 1MHz offset.Body biasing has been incorporated to the transistors M1 and M2 (and M4 and M5) of theactive inductor in the prototype AI-LC VCO to further increase the tuning range. Measurementresults confirms that if bulk voltage of M1 (and M4) is varied, the oscillation frequency is alsochanged. Moreover, increasing the value of VBulk1 from zero (forward body biasing) increasesthe oscillation frequency and applying a negative VBulk1 results in decreasing the oscillation133Figure 5.34: Increasing the tuning range of the prototype active inductor with body biasing.Figure 5.35: Phase noise plot for f0 =3GHzfrequency. Therefore, if the value of Vtune1 is chosen such that the oscillation frequency becomes2.2 GHz (lower end of tuning range), by applying a negative bulk voltage to transistors M1 andM4, the oscillation frequency can be further decreased. Based on the measurement result, ifVBulk1 = −1.2V , oscillation frequency as low as 1.8 GHz can be achieved.The effect of changing the bulk bias (VBulk2) of PMOS transistor, i.e.,M2 andM5 is in reversedirection comparing to changing the VBulk1 in M1 and M4. Here, if source-bulk junction isreverse biased, the oscillation frequency increases and if it is forward biased, oscillation frequencydecreases. If the source-bulk p-n junction is reverse biased in a PMOS transistor, Vth is increased.Increasing the threshold voltage in turn results in a larger source-gate voltage (VSG) forM2 andM5. Thin in turn means that the gate voltage of M2 and M5 is lowered. However, as gate134of M2 and M5 is connected to source terminal of M1 and M4, the bulk-source voltage of M1and M4 is increased which in turn increases the value of gmb1. Larger gmb1 will decrease theinductance given by Eq. 5.54 and therefore the oscillation frequency is increased. Note thatas M2 and M5 are PMOS transistors, for reverse biasing of source-bulk junction, the value ofVBulk2 should be larger than VDD, i.e., 1.2 V. Therefore, if Vtune is set for oscillation frequencyof 3.2 GHz (upper end of the tuning range), by increasing the value of VBulk2 form 1.2V, theoscillation frequency will further increases. For example if VBulk2 = 1.7V is applied to the bulkof M2 and M5 (VSB = +0.5V ), an oscillation frequency as high as 4.1 GHz is obtained. Insummary, applying body biasing to the active inductor of the prototype AI-LC VCO, increasethe tuning range from %37 around 2.7GHz to %78 around 2.9 GHz which is an improvement bya factor of two. Fig. 5.34 shows the measured covering spectrum of the AI-LC VCO prototypein presence of body biasing. Fig. 5.35 shows the plot of phase noise at oscillation frequency of 3GHz. Note that, generally, AI-LC VCOs suffer from larger phase noise comparing to LC VCOswith passive components. This is mainly due to the large noise of active inductor used in thetank of AI-LC VCOs. These active inductors are usually composed of multiple active deviceswhich carry considerable amount of noise while passive inductor only carry the thermal noiseof their series resistance.135Chapter 6Body Biasing in Class-AB PowerAmplifiers (PAs)6.1 IntroductionAs mentioned in Section 2.4 of Chapter 2, power amplifiers are typically the most challengingblock in transmit path of RF front-ends. These challenges are due to the trade-offs that ex-ist among their main performance parameters such as linearity, efficiency and output power.The importance of these trade-offs are even more sensed in systems which work with variable-envelope modulation schemes such as quadrature amplitude modulation (QAM). In such sys-tems, since data is carried partially in phase and partially in amplitude of the carrier, linearityof the power amplifier is extremely important. This is due to the fact that power amplifiersare the last block of the system and they deal with the largest signal level at their input andoutput comparing to all other blocks of the transceiver shown in Fig. 2.1. This is also verifiedby Eq. 2.9 which predicts that linearity of the overall system is mainly defined by the linearityof the last block in the system. However, as explained in Section 2.4 of Chapter 2, linearity isin direct trade-off with efficiency of the power amplifier. Defined by Eq. 2.28, efficiency is oneof the critical parameters of PAs specially when used in a low power transceiver. Ideally, it isdesired to maximize the amount of PA output power for a given DC power. However, it turnsout that the higher the efficiency in PAs, the lower would be the linearity. Based on this, poweramplifiers are categorized in different classes. Among the more linear classes of PAs, class-ABPAs are more commonly used. Therefore, in this chapter, we focus on the linearity of this classof power amplifiers. An overview of the nonlinearity sources of this class of PAs is presentedin Section 6.2. Then in Section 6.3, application of predistortion stage to cancel the effect of136  	Figure 6.1: Nonlinear model of MOS transistorsnonlinear input capacitance is overviewed. The proposed technique, namely, using body bias-ing to increase the effectiveness of predistortion stage is explained in Section 6.4. Post-layoutsimulation results are discussed in Section 6.5. Concluding remarks are presented in Section6.6.6.2 Sources of Nonlinearity in Class-AB Power AmplifiersTo overview the sources of nonlinearity in class-AB power amplifiers, we first investigate thesources of nonlinearity in a MOS transistor. Fig. 6.1 shows a model of a MOS transistor that istypically used for nonlinearity analysis. In this case, it is assumed that there is no body effect,i.e., the bulk of the transistor is connected to its source terminal. The main nonlinear elementin this equivalent circuit is the id current source which models the channel current of the device.The equation for channel current in an NMOS can be written as [93]:Id = Id0{[ln(1 + e(VGS−Vth)(2nφt))]2−[ln(1 + e(VGS−Vth−nVDS)(2nφt))]2} (6.1)where Id0 = µnCox2nφ2tWL and Cox is the gate-oxide capacitance per unit area, µn is the electronmobility, φt = kT/q is the thermal voltage, Vth is the threshold voltage, and n is a technologydependent factor whose typical value is between 1 and 2 for long-channel devices.137If the transistor is operating in the strong inversion region, then Eq. 6.1 can be approximatedwith the following equation which is commonly known as the square-law formula:Id = µnCoxWL(VGS − Vth)22n(6.2)In the presence of short-channel effects such as velocity saturation and mobility degradation,Eq. 6.2 is modified to [64]:Id =µnCox2nWLX21 + αX(6.3)where:X = 2nφt ln(1 + e(VGS−Vth)(2nφt))(6.4)From Eq. 6.3, one can see that the channel current has a nonlinear dependence on gate-source voltage (VGS) of the transistor. For a small-signal current, this nonlinear relation can berepresented by a Taylor series expansion around the bias point:id = gm1vgs + gm2v2gs + gm3v3gs + ... (6.5)In a class-AB PA, this nonlinearity is even stronger since the operation mode of the transistorswitches between saturation and cut-off regions (as explained in Section 2.4). The channelcurrent is not the only source of nonlinearity in a MOSFET and as it can be seen in Fig. 6.1,some MOS capacitors are also nonlinear. Particularly, Cdb and Cgs in the model of Fig. 6.1 arenonlinear capacitors. Cdb (drain-bulk capacitance), is a p-n junction capacitance whose value isdependent on the voltage across the p-n junction, i.e., VDB and it can be written as [28]:Cdb =Cdb0(1 + VDBφB)m (6.6)where Cdb0 is the capacitance at zero VDB bias, φB is the built-in potential of the junction, andm is a constant with a value of around 0.3.More importantly, Cgs (gate-source capacitance) in MOS transistors is a highly nonlinear138		 	Figure 6.2: Nonlinearity in Cgs and effect of bias pointcapacitor. If a negative voltage is applied to the gate terminal of an NMOS transistor, itattracts the holes in the substrate toward the oxide interface. This region of operation is calledaccumulation mode and the value of Cgs would be approximately equal to WLCox. As theapplied voltage at the gate increases, the channel is depleted of mobile charges and the gate-source capacitance decreases as the capacitance of depletion region (Cdep) will appear in serieswith WLCox. If gate voltage becomes positive, the channel once again gets filled but this timewith electrons coming from the source region of the device. This again increases the value ofCgs towards WLCox when the transistor enters into the strong inversion region of operation.Here, we are particularly interested in the variations of Cgs for positive values of vGS as theamplitude of input signal of PA in any of the classes is usually not large enough to exceed thegate-source bias voltage and create a negative vGS . Fig. 6.2 shows the variations of Cgs withvGS for positive vGS values. For the sake of simplicity, the variations of Cgs from Cmin to Cmaxhas been modeled with a step function with the step happening around the threshold voltage(Vth).Although as can be observed in Fig. 6.2, Cgs is a nonlinear capacitance, whether thisnonlinearity is sensed by the power amplifier or not depends on the bias point of the transistor.For example, if the power amplifier is biased in class-A, i.e., in strong inversion region, as shownin Fig. 6.2, the nonlinearity of Cgs does not play a major role as vGS is always larger than Vthand the value of Cgs is approximately constant and is ∼ Cmax. However, in all other classes ofPAs, as vGS goes smaller than Vth for a portion of the input cycle, the value of Cgs switches139from Cmax to Cmin for the same portion of the cycle. This nonlinearity is specifically sensed inclass-AB and class-C PAs. Since Cgs in such cases is a time-varying capacitance and assumingthat the input signal is periodic with carrier frequency of ω0, Cgs can be expressed using thefollowing Fourier series expansion:Cgs(t) = Cgs0 +∞∑n=0cn cosnω0t (6.7)Typically the average value of Cgs(t), i.e., Cgs0, is used in calculating the input impedanceof transistor (Zin =1jωCgs0). However, based on Fig. 6.2, Cgs0 is a function of bias point as wellas the amplitude of the vgs signal.The dependence of input impedance on the amplitude of vgs (AC component of vGS), makesthe input impedance a nonlinear impedance. The negative effect of this nonlinear impedance isthat vgs will no longer be a linear function of input voltage of the PA, i.e., vs in Fig. 2.29 (a)as:Vgs =Z˜in(Vgs)Z˜in(Vgs) + ZsVs (6.8)in which Vgs and Vs are phasors of vgs(t) and vs(t) and Z˜in(Vgs) is the nonlinear input impedancewhich is dependent on the amplitude of Vgs phasor. This in turn means that the informationin the amplitude of the input signal is distorted as it reaches to the gate of PA.6.3 Predistortion to Cancel Nonlinearity in Input CapacitanceDifferent PA linearization techniques such as feedforward [94], Cartesian feedback [95], enve-lope feedback [96] and predistortion [97], have been reported in literature. Among the above-mentioned approaches, predistortion technique is used to compensate for the adverse effects ofthe nonlinear gate-source capacitance [98, 99]. Fig. 6.3 shows the basic concept of the predis-tortion technique. The main idea is that if the PA input-output relation is a nonlinear functionof input x (e.g., f(x)), by predistorting the input signal by the inverse function of f(x), i.e.,f−1(x), a linear behavior can be obtained.For the specific case of nonlinearity of Cgs = f(vGS), if any circuitry with capacitance140 				 Figure 6.3: Linearizing power amplifiers through using a predistortion stageFigure 6.4: The predistortion linearizing technique in [99]variation in the form of Ccomp = f−1(vGS) is added in parallel to the input transistor, thenonlinearity of Cgs can be compensated. An important point here is that the added circuitryideally should not affect the main signal and it only should change the input capacitance withoutconsuming additional power. Two possible solutions are introduced in [98, 99]. The basic ideaof these two approaches have been depicted in Fig. 6.4. This linearization technique worksbased on the fact that in a PMOS transistor the variations of Cgs versus vGS is complementaryto that of NMOS transistor, i.e., as vGS of the input transistor increases the value of Cgs of thePMOS transistor changes from Cmax to Cmin (rather than Cmin to Cmax in the case of NMOS).Therefore, if as shown in Fig. 6.4 a PMOS transistor is added in parallel with the input deviceof PA, the overall input capacitance would be Cgs,n+Cgs,p. Ideally, by proper sizing and choiceof the bias voltages, the overall input capacitance of the PA would no longer be nonlinear.141Although the technique shown in Fig. 6.4 reduces the nonlinearity of the input capacitance,there are some issues which can further be improved. The first issue is that in order to properlyalign the transition point of Cgs,n and Cgs,p, there is a need for a DC voltage to properlybias the gate of the PMOS transistor. Assuming that the NMOS transistor is biased at theedge of threshold, i.e., for class-B PAs, this voltage is VP = Vth,n + |Vth,p|, which is sensitiveto process and temperature variations. Also, as shown in [99] relative sizing of the PMOStransistor with respect to the NMOS transistor depends on the ratio of gate oxide capacitancein NMOS and PMOS transistors (Cox,n and Cox,p). As Cox,n and Cox,p, in particular in deepsubmicron processes, are slightly technology-dependent parameters, using a PMOS transistoras a predistortion capacitor makes the design even more sensitive to the process.Based on the above observations, it is desired to replace the PMOS device with its NMOScounterpart. To be able to create the complementary behavior of Cgs of the PA transistor inthe NMOS predistortion device, as shown in Fig. 6.5 (a) the shorted drain/source terminalsof NMOS gate diode are connected to the gate of the input device of PA and the gate of thepredistortion device is tied up to VDD. This linearization technique has been previously pro-posed in a GaN HEMT power amplifier in [100]. However, as shown in Fig. 6.5 (b), using suchconfiguration, the input capacitance nonlinearity may not be fully compensated. In this config-uration, the gate-source voltage of predistortion device is equal to VDD − vGS (note that vGSis the gate-source voltage of the PA device). Therefore, the Cgs variations of the predistortionNMOS device is complementary to that of the PA transistor. As shown in Fig. 6.5 (b) whilethe transition point for Cgs variation of PA transistor occurs around Vth, for the predistortiondevice it happens around VDD − Vth. However, since in general VDD is not equal to 2Vth, inthe region where both predistortion and PA transistors are in moderate inversion, nonlinearityis not fully canceled.6.4 Body-Biasing of the NMOS Predistortion Device forImproving LinearityTo fully compensate the Cgs nonlinearity of a class-AB power amplifier, body biasing can beincorporated in the NMOS predistortion device of Fig. 6.5 (a). The main idea is to control the142(a) (b)Figure 6.5: (a) Schematic of a PA with an NMOS predistortion device (b) simplified diagramof Cgs variations and the resulting compensated input capacitance.threshold voltage of predistortion device through the bulk-source voltage using:Vth = Vth0 + γ(√|2ΦF | − VBS −√|2ΦF |)(6.9)where Vth0 is the nominal threshold voltage of the transistor when its bulk-source voltage iszero, i.e., VBS = 0 V, γ is the body-effect coefficient, and ΦF is the Fermi potential of thebulk. In the presence of body biasing, the threshold voltage of the predistortion device (Vth2)can be increased to the extent that the value of VDD − Vth2 becomes equal to the threshold ofinput transistor (Vth1). Based on Eq. 6.9, for increasing the threshold voltage, the bulk-sourcevoltage should be decreased or equivalently the p-n junction between bulk and source terminalsshould be reverse biased. Note that as the source of the predistortion device is connected tothe gate terminal of the PA input device, this terminal has a positive bias voltage equal tothe gate-source bias of the PA input device. Therefore, when the bulk of the predistortiondevice is zero biased, the bulk-source voltage is already negative. However, the more negativethis voltage is, the larger the threshold voltage of the device will be. Note that after reachingsufficiently large Vth2, more negative bulk voltages will again deteriorate the compensation ofthe overall Cgs. The proposed application of body biasing to the predistortion device is depictedin Fig. 6.6. As can be seen from the figure, by applying proper bias voltage to the bulk of thepredistortion device, the nonlinearity of input capacitance could be ideally compensated. Also,143(a) (b)Figure 6.6: (a) Schematic of a PA with the proposed body-biased NMOS predistortion device(b) simplified diagram of Cgs variations and the resulting compensated input capacitance.note that due to the fact that in Eq. 6.9 we have the square root of Vth, the use of body biasingprovides smoother control of Cgs curve of the predistortion device as compared to using VP inthe PMOS-based predistortion circuit in Fig. 6.4. More importantly, in the proposed technique,both PA device and predistortion device are NMOS and thus there is less sensitivity to process.However, both techniques require an additional bias voltage to either bias the gate of the PMOSor the body of the NMOS predistortion device.6.5 Simulation ResultsTo verify the validity of the proposed body-biased NMOS predistortion circuit, a 2.4-GHz class-AB power amplifier is designed and laid-out in a 0.13-µm CMOS technology. The schematicof the PA including its input and output matching networks is shown in Fig. 6.7. The PAis biased through a choke which is assumed to be off-chip. The output matching network isan impedance transformation network which converts the output impedance of the PA to 50-Ωimpedance of the subsequent stage, namely, the antenna. However, the input inductor in Fig.6.7 is part of a voltage matching network rather than a power matching network. The reasonfor this is that in practice the input signal of the PA either comes from a pre-amplifier stage ordirectly from the upconversion mixer. In interaction between different blocks of an integratedcircuit, assuming that wavelength is much larger than the circuit dimensions, power matching144Figure 6.7: Schematic of the designed class-AB power amplifier.Figure 6.8: Input series inductoris irrelevant and the voltage is the parameter of interest [33] since MOS transistor operate withvoltage rather than power. When power amplifier is designed and tested as an individual block,the input signal comes from a signal generator with a 50-Ω output impedance. In such cases,to increase the magnitude the of voltage at the gate of the input device of the PA, a resonancecircuit can be used. The effect of this resonance circuit can be explained through Fig. 6.8. Ascan be seen in this figure, the added inductor creates a series resonance with the total inputcapacitance of the PA. Thus, the impedance seen by the RF source is minimized. As a result,the magnitude of the phasor of the current is increased which in turn leads into an increase inthe magnitude of the voltage at gate of the PA transistor.Fig. 6.9 (a) shows the layout of the proof-of-concept prototype circuit. The designed PAachieves a maximum unsaturated peak-to-peak output voltage swing of 6 V over a 50 Ω loadwhich is equivalent to almost 20-dBm or 100-mW output power. The bias current of the PAis 125 mA and the supply voltage is 1.2 V. Therefore, the drain efficiency is equal to 66%145(a) (b)Figure 6.9: (a) Layout (b) chip micrograph of the proof-of-concept 2.4-GHz class-AB PA withbody-biased NMOS predistortion device. Active area is 475-µm×350-µm.(based on Eq. 2.28). Fig. 6.10 shows the simulation result for the input capacitance of thePA after applying body biasing to the NMOS predistortion device. By sweeping the body biasof the predistortion device, it turns out that at VB = −0.6 V, the nonlinearity of the overallinput capacitance is approximately compensated. To show the effect of this compensation onthe overall linearity of the PA, the variation of IIP3 of the PA versus bulk voltage of thepredistortion device is plotted in Fig. 6.11. The IIP3 values have been obtained using two-tonetesting with tones at 2.4-GHz and 2.45-GHz. As can be seen from the figure, IIP3 is maximizedwhen VB = −0.6 V. The amount of improvement in IIP3 is roughly equal to 3 dB. Note thatthis 3 dB improvement is solely related to the body biasing technique while even without usingbody biasing the predistortion linearizer improves the linearity.Fabricated PrototypeAs can be seen in Fig. 6.9 (b), a prototype has also been fabricated to verify the proposedlinearity enhancement technique experimentally. However, due to an unpredicted problem, thefabricated prototype does not operate properly. In fact, the PA itself is not able to provide aconsiderable amount of power at its output, although the DC current of the prototype PA is atthe same value as it is designed for, i.e., 125 mA. Obviously with PA not working properly, thereis no chance for verifying the idea of body-biased NMOS predistortion stage experimentally.To find out the reason for malfunction of the chip, several possible reasons has been in-vestigated. The first possible reason for the malfunction of the chip, is the incorrect design of146	   				  Figure 6.10: Simulation results for the capacitance of PA transistor, NMOS predistortion deviceand the total compensated input capacitance.	 	 	 	 	      		Figure 6.11: Variations of IIP3 versus bulk voltage of the NMOS predistortion device.output matching network (although it has been carefully designed) at the output of the PA(shown in red dotted square in Fig. 6.7) such that the PA can not drive the 50 Ω impedanceof the measurement instrument. To verify the validity of this assumption, active probes havebeen used to measure the output voltage of the prototype PA. The main advantage of activeprobes is that they include an active amplifier which loads the 50 Ω impedance of measurementinstrument without loading the circuit by the 50 Ω. However, using the active probes doesnot boost the power level of the PA and thus the assumption of incorrect output impedancematching is rejected.147Figure 6.12: (a) generic diagram of a bias-Tee (b) bias-Tee including the inside circuitry.The next possible reason is the off-chip inductor used to bias the PA. Power amplifiers arecommonly biased with an RF choke. RF choke is a very large inductor which supplies the DCbias current to the PA while acting as an open circuit to the AC signal of PA. If by any reason,the impedance of RF choke is not very large at the operation frequency of PA (2.4 GHz inthis prototype), the output matching network operation is corrupted. The main task of outputmatching network is converting the 50 Ω impedance of the antenna to resistive value smallerthan 50 Ω to have the maximum possible swing of the drain-source voltage and drain currentof the PA transistor.As integrating a large inductor as the RF choke takes a huge area on the chip, the inductanceof a bias-Tee is intended to be used as the RF choke. Fig. 6.12 (a) shows the generic schematicof a bias-Tee. Bias-Tees are typically used to couple DC and RF signal to the input of RFcircuits or systems. However, the real schematic of a bias-Tee looks as in Fig. 6.12 (b). As canbe seen in this figure both the RF port and RF+DC port of the bias-Tees are matched to 50 Ω.This is mainly because bias-Tees are usually used in microwave systems in which all of the portsand cables have impedance of 50Ω. Therefore, using the bias-Tee in the configuration showed inFig. 6.13 (a) will introduced an undesired 50 Ω impedance at the drain of PA transistor. Thisin turn will totally corrupt the output matching. The other possibility was using the bias-Teein configuration showed in Fig. 6.13 (b). However, it turns out that, at the DC port of thebias-Tee, there is a large decoupling capacitor to short any possible noise on the DC supply148Ω Ω		Ω 		Ω Ω	 	Figure 6.13: PA output with two possible configuration for using a bias-Tee as the RF choke.voltage that is ordinarily applied to the DC port of a bias-Tee. This large capacitance will alsochange the impedance at the drain of PA transistor and thus the output matching.In summary, using bias-Tees as the RF choke is not a good option for integrated circuitswhich work with voltage signals (not power signals) and are not matched to 50 Ω. This ismainly because of the presence of matching circuits and large decoupling capacitors inside thestructure of bias-Tees. Our search to find an RF choke with no 50 Ω matching did not result ina solution. Thus, the best option is integrating a sufficiently large RF choke with PA.6.6 ConclusionA body-biased NMOS predistortion device is used in a class-AB power amplifier to improve thelinearity of the circuit and compensate for the nonlinearity in the input capacitance. The mainidea is creating the complementary behavior of the nonlinear capacitance in a similar device149whose drain and source are shorted together and does not consume extra power. Moreover,body biasing is applied to the NMOS predistortion device to enhance the linearity. Post-layoutsimulation results on a proof-of-concept class-AB power amplifier confirms the validity of theproposed linearization technique.150Chapter 7ConclusionWe have demonstrated that body biasing can be used to improve the performance of four of themain building blocks of CMOS RF front-ends, i.e., low-noise amplifiers, active down-conversionmixers, voltage-controlled oscillators, and power amplifiers. The body-biasing technique pro-vides an additional degree of freedom in the design of different building blocks of RF front-endsand can be used either by itself or in conjunction with other design techniques to improve theperformance of RF front-end building blocks. The performance improvements are mainly re-lated to noise and linearity of these building blocks and have been achieved through adjustingthe values of both small signal parameters such as bulk-source transconductance (gmb), source-bulk capacitance (Csb), and DC parameters such as threshold voltage (Vth) of MOS transistors.More specifically, body biasing can be used to:ˆ Improve the performance of multi-stage LNAs. The proposed body biasing technique is amultipurpose optimization method and its effectiveness is verified through measurementresults on a proof-of-concept 3-stage cascode LNA. Body biasing is applied in the CStransistor of the first stage to improve the noise figure, to the CG transistor of the secondstage to adjust the gain and to the CG device of the third stage to enhance linearity.Noise figure adjustment and gain boosting are achieved by changing the value of the gmbin appropriate transistors while linearity enhancement is achieved by changing the valueof the threshold voltage (Vth) and the third-order gate-source transconductance (gm3).Gain reduction is achieved by weakening the channel in MOS transistors through forwardbiasing of the bulk-source junction.ˆ Enhance the linearity of active down-conversion mixers through body biasing of LO stagetransistors. The technique is particularly suitable for low-power mixers with low power LOdrive signals and gradual LO switching. This improvement in linearity is achieved without151degrading the conversion gain in standard mixer structures. The linearity enhancementmechanism is similar to that of LNAs and is achieved by changing the value of the thresholdvoltage (Vth) and the third-order gate-source transconductance (gm3).ˆ Adjust the phase-noise performance of cross-coupled LC VCOs by lowering the duty cyclein class-C mode of operation. The approach relies on the effects of body biasing onthe intrinsic capacitances (mainly Csb) and does not include any additional capacitors.We have shown that by changing the bias voltage of the bulk of the cross-coupled coretransistors of the VCO, the ratio of intrinsic capacitances which in turn affects the phasenoise can be adjusted.ˆ Increase the tuning range of active-inductor-based LC VCOs. We have shown that bodybiasing can be added as an extra tuning voltage for the inductance of active-inductors.The effect of body biasing is through adjusting the value of gmb.ˆ Improve the linearity in class-AB PAs. Body biasing is applied to the NMOS predistortionto achieve a higher compensation of the nonlinear Cgs capacitance of the input deviceof PA. The technique is based on changing the value of threshold voltage (Vth) in thepredistortion device.The proposed body biasing technique is based on providing appropriate bias voltage to the bodyof MOS transistors and only has minimal overhead in terms of power and circuit complexity(in the form of required bias circuitry). Moreover, as explained in Chapter 5, in the caseof application of body biasing to improve phase noise of voltage-controlled oscillators, bodybiasing can be used to save the area of passive components such as integrated inductors in thecommonly used LC phase noise filter reported in [73]. Also as shown in Chapter 3 and Chapter 4,application of body biasing to enhance linearity provides a more reliable tool for biasing of MOStransistors to their sweet-spot bias point at which the third-order transconductance becomeszero. In fact, the wider peak in IIP3 makes the use of bulk voltage for sweet spot biasing a moreattractive technique which is less sensitive to process, voltage, temperature (PVT) variations.Due to the importance of reducing power consumption in portable wireless devices, specialattention is paid to ensure that the achieved improvements are not at the cost of substantial152increase in the power consumption of the building blocks and thus the overall wireless device inwhich they are used. The proposed applications of body biasing technique are validated throughmeasurements of proof-of-concept prototype integrated circuits fabricated in 0.13-µm, 90-nm,and 65-nm CMOS technologies.7.1 Future Works7.1.1 Automatic Control Scheme for Body BiasingWhile based on the discussions and analyses provided in the previous chapters, body-biasingis an attractive approach to control different performance parameters of RF font-end buildingblocks; practical implementation of such biasing should be considered as well. This is specificallyimportant when there is a maximum or minimum in one of the performance metrics (e.g., IIP3)of the circuit when the body voltage is varied. In such situations one should be able to providethe required bias voltage to the bulk of transistors in order to achieve the desired operatingpoint. While in this research, we applied the body bias voltage manually to the prototypecircuits, a digital control circuit and a feedback loop can be designed to control the bias of bulkterminal automatically.Fig. 7.1 shows two possible approaches for providing the bias voltage to the bulk terminals.In Fig. 7.1(a), there is a current-mirror structure in which by changing the current that ismirrored, different gate-source voltages can be generated and then be applied to the bulk of thedesired transistor. In order to have 2n different voltages, n control bits are required to switch inor out the control current sources. Fig. 7.1 (b) shows an alternative approach in which a resistiveladder with 2n resistors and a 2n to 1 multiplexer are used to select the appropriate voltageproduced by the resistive ladder. Furthermore, note that typically in a wireless communicationsystem, there is a power management unit (PMU) that provides the required voltages. The PMUof the system usually generates both positive and negative voltages. Therefore, to generate thebody-biasing voltage one can use both positive or negative supply along with a bias generatorsimilar to those suggested in Fig. 7.1. Therefore, designing a fully automatic control schemewhich accepts input from the digital baseband processor (DBB) of the system and adjust thebulk voltages in the various building blocks of the RF front-end is the next step in realizing an1531biasV0I 2I nI1I2n2biasV(a)n1biasV2biasV(b)Figure 7.1: The practical implementation of biasing the bulk terminalsRF front-end with adjustable performance based on body biasing.7.1.2 Application of Body Biasing to other Building Blocks of RFFront-endsWhile in this work body biasing has been applied to four main building blocks of RF front-ends,application of body biasing can be extended to other building blocks of such front-ends. Forexample, body biasing can be utilized to change the bandwidth or quality factor of an integratedactive filter. As another example, body biasing can be applied to passive mixers to reduce thethreshold voltage of the transistors and thus improve their switching speed.1547.1.3 Body Biasing in SOI TechnologiesSilicon-on-insulator (SOI) technology and its variants such as fully-depleted silicon-on-insulator(FD-SOI) are considered as excellent candidates to further scale the CMOS technology at tech-nology nodes smaller than 28-nm [101]. The main difference of SOI technologies from conven-tional bulk CMOS technology is the use of buried oxide (BOx) as an insulator to form a partiallyor fully depleted body which is float and isolated from the global substrate. This in turn resultsin interesting characteristic for transistor including less parasitic device capacitance, excellentelectrostatic control of the transistor, less transistor threshold variability, low leakage and goodcontrol of short channel effects [101].Interestingly, body biasing still can be applied to SOI technologies in the form of back planebiasing [101]. Considering the emergence of SOI in advanced CMOS technology nodes, inves-tigating the application of body biasing in SOI RF integrated circuits would be an importantfuture work.155Bibliography[1] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge universitypress, 2003.[2] J. G. Proakis, M. Salehi, N. Zhou, and X. Li, Communication Systems Engineering. Pren-tice Hall New Jersey, 1994.[3] F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, A dynamic thresh-old voltage MOSFET (DTMOS) for ultra-low voltage operation, in Technical Digest ofInternational Electron Devices Meeting, 1994, pp. 809812.[4] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, Dynamicthreshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI, IEEE Transactionson Electron Devices, vol. 44, no. 3, pp. 414422, 1997.[5] N. Lindert, T. Sugii, S. Tang, and C. Hu, Dynamic threshold pass-transistor logic forimproved delay at lower power supply voltages, IEEE Journal of Solid-State Circuits,vol. 34, no. 1, pp. 8589, 1999.[6] C. Wann, J. Harrington, R. Mih, S. Biesemans, K. Han, R. Dennard, O. Prigge, C. Lin,R. Mahnkopf, and B. Chen, CMOS with active well bias for low-power and RF/analogapplications, in IEEE Symposium on VLSI Technology, Digest of Technical Papers.,,2000, pp. 158159.[7] T. Taris, J.-B. Begueret, H. Lapuyade, and Y. Deval, A differential implementation ofthe CMOS active-load body-effect mixer, in IEEE Radio Frequency Integrated Circuits(RFIC) Symposium, 2003, pp. 465468.[8] M. H. Kazemeini, M. J. Deen, and S. Naseh, Phase noise in a back-gate biased low-voltage156VCO, in IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, 2003,pp. I701.[9] B. Cook, A. Berny, A. Molnar, S. Lanzisera, and K. Pister, Low-power 2.4-GHztransceiver with passive RX front-end and 400-mV supply, IEEE Journal of Solid-StateCircuits, vol. 41, no. 12, pp. 27572766, 2006.[10] D. Park and S. Cho, An adaptive body-biased VCO with voltage-boosted switched tuningin 0.5-V supply, in European Solid-State Circuits Conference (ESSCIRC), 2006, pp. 444447.[11] L. Geynet, E. De Foucauld, P. Vincent, and G. Jacquemod, Fully-integrated multi-standard VCOs with switched LC tank and power controlled by body voltage in 130nmCMOS/SOI, in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006, pp.4pp.[12] D. Wu, R. Huang, W. Wong, and Y. Wang, A 0.4-V low noise amplifier using forwardbody bias technology for 5 GHz application, IEEE Microwave and Wireless ComponentsLetters, vol. 17, no. 7, pp. 543545, 2007.[13] Z. Wang, H. S. Savci, J. Griggs, and N. S. Dogan, 1-V ultra-low-power CMOS LC VCOwith dynamic body biasing, in IEEE International Symposium on Signals, Circuits andSystems (ISSCS), vol. 1, 2007, pp. 14.[14] H.-H. Hsieh and L.-H. Lu, A high-performance CMOS voltage-controlled oscillator forultra-low-voltage operations, IEEE Transactions on Microwave Theory and Techniques,vol. 55, no. 3, pp. 467473, 2007.[15] H.-H. Hsieh, J.-H. Wang, and L.-H. Lu, Gain-enhancement techniques for CMOS foldedcascode LNAs at low-voltage operations, IEEE Transactions on Microwave Theory andTechniques, vol. 56, no. 8, pp. 18071816, 2008.[16] O. Schmitz, S. Hampel, C. Orlob, M. Tiebout, and I. Rolfes, Low-voltage bulk-drivenmixers in 45nm CMOS for ultra-wideband TX and RX, in NORCHIP, 2008, pp. 119122.157[17] D. Van Vorst and S. Mirabbasi, Low-power 1V 5.8 GHz bulk-driven mixer with on-chip balun in 0.18 µm CMOS, in IEEE Radio Frequency Integrated Circuits Symposium(RFIC), 2008, pp. 197200.[18] S. Jang, C. Huang, C. Liu, and C. Hsue, A 0.22 V quadrature VCO in 90 nm CMOSprocess, IEEE Microwave and Wireless Components Letters, vol. 19, no. 9, pp. 566568,2009.[19] S. Lim, W. Badalawa, and M. Fujishima, A 110GHz inductor-less CMOS frequencydivider, in IEEE Asian Solid-State Circuits Conference (A-SSCC), 2009, pp. 6164.[20] S. Kim and H. Shin, An E-TSPC divide-by-2 circuit with forward body biasing in 0.25 µmCMOS, IEEE Microwave and Wireless Components Letters, vol. 19, no. 10, pp. 656658,2009.[21] A. Mabrouki, T. Taris, Y. Deva, and J.-B. Begueret, A variable gain 2.4-GHz CMOSlow noise amplifier employing body biasing, in Ph. D. Research in Microelectronics andElectronics (PRIME), 2009, pp. 168171.[22] W.-H. Lin, J.-H. Tsai, Y.-N. Jen, T.-W. Huang, and H. Wang, A 0.7-V 60-GHz low-powerLNA with forward body bias technique in 90 nm CMOS process, in European MicrowaveConference (EuMC), 2009, pp. 393396.[23] C.-Y. Wang and J.-H. Tsai, A 51 to 65 GHz low-power bulk-driven mixer using 0.13 µmCMOS technology, IEEE Microwave and Wireless Components Letters, vol. 19, no. 8,pp. 521523, 2009.[24] C.-M. Li, M.-T. Li, K.-C. He, and J.-H. Tarng, A low-power self-forward-body-biasCMOS LNA for 36.5-GHz UWB receivers, IEEE Microwave and Wireless ComponentsLetters, vol. 20, no. 2, pp. 100102, 2010.[25] P. Sun, G. Wang, and W. Woods, An adaptive body-bias low voltage low power LCVCO, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 11211124,2010.158[26] Y.-T. Chen, M.-W. Li, T.-H. Huang, and H.-R. Chuang, A V-band CMOS directinjection-locked frequency divider using forward body bias technology, IEEE Microwaveand Wireless Components Letters, vol. 20, no. 7, pp. 396398, 2010.[27] A. Niknejad and H. Hashemi, mm-Wave silicon technology: 60GHz and beyond. Springer,2008.[28] B. Streetman and S. Banerjee, Solid State Electronic Devices. Prentice Hall, 2009.[29] B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed. New York, NY, USA:McGraw-Hill, Inc., 2001.[30] T. Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Design. Wiley, 2011.[31] P. R. Gray, P. J. Hurst, R. G. Meyer, and S. H. Lewis, Analysis and Design of AnalogIntegrated Circuits. John Wiley & Sons, 2008.[32] D. M. Pozar, Microwave Engineering. John Wiley & Sons, 2009.[33] B. Razavi, RF Microelectronics. Prentice Hall, 2011.[34] H. T. Friis, Noise figures of radio receivers, Proceedings of the Institute of Radio Engi-neers (IRE), vol. 32, no. 7, pp. 419422, July 1944.[35] K. Ogata, Modern Control Engineering. Prentice Hall, 2009.[36] F. Yuan, CMOS Active Inductors and Transformers: Principle, Implementation, andApplications. Springer, 2008.[37] A. El Gouhary and N. M. Neihart, Inductor-based tuning in LC-quadrature oscillators:A comparative study, IEEE Transactions on Circuits and Systems II-Express Briefs,vol. 59, no. 9, pp. 548552, 2012.[38] S. T. Nicolson and S. Voinigescu, Methodology for simultaneous noise and impedancematching in W-band lnas, in IEEE Compound Semiconductor Integrated Circuit Sympo-sium (CSIC 2006), 2006, pp. 279282.[39] A. Van Der Ziel, Noise in Solid State Devices and Circuits. Wiley, 1986.159[40] B. Razavi, R.-H. Yan, and K. F. Lee, Impact of distributed gate resistance on the per-formance of MOS devices, IEEE Transactions on Circuits and Systems I: FundamentalTheory and Applications, vol. 41, no. 11, pp. 750754, 1994.[41] W. M. Sansen, Analog Design Essentials. Springer, 2006.[42] J.-S. Goo, S. Donati, C.-H. Choi, Z. Yu, T. H. Lee, and R. W. Dutton, Impact of substrateresistance on drain current noise in MOSFETs, in Simulation of Semiconductor Processesand Devices 2001. Springer, 2001, pp. 182185.[43] C. Zhang, D. Huang, and D. Lou, Optimization of cascode CMOS low noise amplifier us-ing inter-stage matching network, in IEEE International Conference of Electron Devicesand Solid-State Circuits (EDSSC), 2003, pp. 465468.[44] T. H. Jin and T. W. Kim, A 6.75 mW +12.45 dBm IIP3 1.76 dB NF 0.9 GHz CMOSLNA employing multiple gated transistors with bulk-bias control, IEEE Microwave andWireless Components Letters, vol. 21, no. 11, pp. 616 618, Nov. 2011.[45] T. W. Kim, A common-gate amplifier with transconductance nonlinearity cancellationand its high-frequency analysis using the volterra series, IEEE Transactions on Mi-crowave Theory and Techniques, vol. 57, no. 6, pp. 14611469, 2009.[46] V. Aparin and L. E. Larson, Modified derivative superposition method for linearizing FETlow-noise amplifiers, IEEE Transactions on Microwave Theory and Techniques, vol. 53,no. 2, pp. 571581, 2005.[47] V. Aparin, G. Brown, and L. E. Larson, Linearization of CMOS LNA's via optimum gatebiasing, in Proceeding of International Symposium on Circuits and Systems (ISCAS),vol. 4, 2004, pp. IV74851.[48] T. W. Kim, B. Kim, and K. Lee, Highly linear receiver front-end adopting MOSFETtransconductance linearization by multiple gated transistors, IEEE Journal of Solid-StateCircuits, vol. 39, no. 1, pp. 223229, 2004.160[49] T. H. Jin and T. W. Kim, A 5.5-mW + 9.4-dBm IIP3 1.8-dB NF CMOS LNA employ-ing multiple gated transistors with capacitance desensitization, IEEE Transactions onMicrowave Theory and Techniques, vol. 58, no. 10, pp. 25292537, Oct. 2010.[50] T. Taris and A. Mabrouki, Optimization of linearity in CMOS low noise amplifier, inWireless Radio-Frequency Standards and System Design: Advanced Techniques, D. J. S.Gianluca Cornetta and J. M. Vazquez, Eds. Hershey: IGI Global, 2012.[51] B. Toole, C. Plett, and M. Cloutier, RF circuit implications of moderate inversion en-hanced linear region in MOSFETs, IEEE Transactions on Circuits and Systems I: RegularPapers, vol. 51, no. 2, pp. 319328, 2004.[52] J. W. Park and B. Razavi, A harmonic-rejecting CMOS LNA for broadband radios, in2012 Symposium on VLSI Circuits (VLSIC), 2012, pp. 8081.[53] G. Sapone and G. Palmisano, A 3-10-GHz low-power CMOS low-noise amplifier for ultra-wideband communication, IEEE Transactions on Microwave Theory and Techniques,vol. 59, no. 3, pp. 678686, 2011.[54] J.-H. Ham, J.-Y. Lee, and T.-Y. Yun, 21-dB gain ultra-wideband complementary metal-oxide semiconductor low-noise amplifier with current-reuse technique, IET Microwaves,Antennas & Propagation, vol. 5, no. 12, pp. 14951501, 2011.[55] H. Wang, L. Zhang, and Z. Yu, A wideband inductorless LNA with local feedback andnoise cancelling for low-power low-voltage applications, IEEE Transactions on Circuitsand Systems I: Regular Papers, vol. 57, no. 8, pp. 19932005, 2010.[56] B. Park, S. Choi, and S. Hong, A low-noise amplifier with tunable interference rejectionfor 3.1- to 10.6-GHz UWB systems, IEEE Microwave and Wireless Components Letters,,vol. 20, no. 1, pp. 4042, Jan. 2010.[57] K. Wang, K. Ma, W. Ye, K. S. Yeo, H. Zhang, and Z. Wang, A low voltage low powerhighly linear CMOS quadrature mixer using transconductance cancellation technique, inIEEE International Microwave Symposium Digest, 2012, pp. 13.161[58] M.-F. Huang and C. J. Kuo, A CMOS dual class-AB technique for highly linear evenharmonic mixer, in IEEE Asian Solid-State Circuits Conference (A-SSCC), 2006, pp.367370.[59] K.-H. Liang, C.-H. Lin, H.-Y. Chang, and Y.-J. Chan, A new linearization technique forCMOS RF mixer using third-order transconductance cancellation, IEEE Microwave andWireless Components Letters, vol. 18, no. 5, pp. 350352, 2008.[60] S. Hu, Y. Huang, and Z. Hong, Improved Gilbert mixer with high-precision automaticsweet-spot biasing and active-inductor-based harmonic suppression, Electronics letters,vol. 48, no. 1, pp. 3335, 2012.[61] P.-Z. Rao, T.-Y. Chang, C.-P. Liang, and S.-J. Chung, An ultra-wideband high-linearityCMOS mixer with new wideband active baluns, IEEE Transactions on Microwave Theoryand Techniques, vol. 57, no. 9, pp. 21842192, 2009.[62] B. Gilbert, The MICROMIXER: A highly linear variant of the Gilbert mixer using abisymmetric class-AB input stage, IEEE Journal of Solid-State Circuits, vol. 32, no. 9,pp. 14121423, 1997.[63] J. Yoon, H. Kim, C. Park, J. Yang, H. Song, S. Lee, and B. Kim, A new RF CMOS Gilbertmixer with improved noise figure and linearity, IEEE Transactions on Microwave Theoryand Techniques, vol. 56, no. 3, pp. 626631, 2008.[64] M. T. Terrovitis and R. G. Meyer, Intermodulation distortion in current-commutatingCMOS mixers, IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 14611473, 2000.[65] W. Sansen, Distortion in elementary transistor circuits, IEEE Transactions on Circuitsand Systems II: Analog and Digital Signal Processing, vol. 46, no. 3, pp. 315325, 1999.[66] T. W. Kim, B. Kim, and K. Lee, Highly linear RF CMOS amplifier and mixer adoptingMOSFET transconductance linearization by multiple gated transistors, in IEEE RadioFrequency Integrated Circuits (RFIC) Symposium, 2003, pp. 107110.[67] S.-G. Lee and J.-K. Choi, Current-reuse bleeding mixer, Electronics letters, vol. 36, no. 8,pp. 696697, 2000.162[68] H. Lee and S. Mohammadi, A 500µw 2.4 GHz CMOS subthreshold mixer for ultra lowpower applications, in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,2007, pp. 325328.[69] V. Vidojkovic, J. Van Der Tang, A. Leeuwenburgh, and A. H. Van Roermund, A low-voltage folded-switching mixer in 0.18-µm CMOS, IEEE Journal of Solid-State Circuits,vol. 40, no. 6, pp. 12591264, 2005.[70] J. Rael and A. A. Abidi, Physical processes of phase noise in differential LC oscillators,in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2000, pp.569572.[71] A. Hajimiri and T. Lee, A general theory of phase noise in electrical oscillators, IEEEJournal of Solid-State Circuits, vol. 33, no. 2, pp. 179194, 1998.[72] a. Hajimiri and T. Lee, Design issues in CMOS differential LC oscillators, IEEE Journalof Solid-State Circuits, vol. 34, no. 5, pp. 717724, May 1999.[73] E. Hegazi, H. Sjoland, and A. Abidi, A filtering technique to lower LC oscillator phasenoise, IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 19211930, 2001.[74] P. Andreani, X. Wang, L. Vandi, and A. Fard, A study of phase noise in Colpitts andLC-tank CMOS oscillators, IEEE Journal of Solid-State Circuits, vol. 40, no. 5, pp.11071118, 2005.[75] B. Soltanian and P. Kinget, Tail current-shaping to improve phase noise in LC voltage-controlled oscillators, IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 17921802,2006.[76] A. Mazzanti and P. Andreani, Class-C harmonic CMOS VCOs, with a general result onphase noise, IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 27162729, 2008.[77] P. Andreani and X. Wang, On the phase-noise and phase-error performances of mul-tiphase LC CMOS VCOs, IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp.18831893, 2004.163[78] A. Mazzanti and P. Andreani, A time-variant analysis of fundamental1/f3 phase noisein CMOS parallel LC-tank quadrature oscillators, IEEE Transactions on Circuits andSystems I: Regular Papers, vol. 56, no. 10, pp. 21732180, 2009.[79] P. Andreani and A. Fard, More on the1/f2 phase noise performance of CMOS differential-pair LC-tank oscillators, IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 27032712, 2006.[80] D. Leeson, A simple model of feedback oscillator noise spectrum, Proceedings of theIEEE, vol. 54, no. 2, pp. 329330, 1966.[81] L. Couch, H. Shao, X. Li, and L. Liu, Digital and analog communication systems. Macmil-lan, 1993.[82] R. Aparicio and A. Hajimiri, A noise-shifting differential Colpitts VCO, IEEE Journalof Solid-State Circuits, vol. 37, no. 12, pp. 17281736, 2002.[83] , A CMOS differential noise-shifting Colpitts VCO, in IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 1, 2002, pp. 288289.[84] L. Fanori and P. Andreani, Dynamic bias schemes for class-C VCOs, in NORCHIP,2011, pp. 14.[85] A. Mazzanti and P. Andreani, A push-pull class-C CMOS VCO, IEEE Journal of Solid-State Circuits, vol. 48, no. 3, pp. 724732, 2013.[86] H. Hsieh and L. Lu, A high-performance CMOS voltage-controlled oscillator for ultra-low-voltage operations, IEEE Transactions on Microwave Theory and Techniques, vol. 55,no. 3, pp. 467473, 2007.[87] S. Jang and C. Huang, A 0.3 V cross-coupled VCO using dynamic threshold MOSFET,IEEE Microwave and Wireless Component Letters, vol. 20, no. 3, pp. 166168, 2010.[88] K. Okada, Y. Nomiyama, R. Murakami, and A. Matsuzawa, A 0.114-mW dual-conductionclass-C CMOS VCO with 0.2-V power supply, in 2009 IEEE Symposium on VLSI Cir-cuits, 2009, pp. 228229.164[89] R. Fiorelli, E. Peralias, and F. Silveira,  LC-VCO design optimization methodology basedon thegm/ID ratio for nanometer CMOS technologies, IEEE Transactions on MicrowaveTheory and Techniques, vol. 59, no. 7, pp. 18221831, 2011.[90] E. Kytonaki and Y. Papananos, A low-voltage differentially tuned current-adjusted 5.5-GHz quadrature VCO in 65-nm CMOS technology, IEEE Transactions on Circuits andSystems II: Express Briefs, vol. 58, no. 5, pp. 254258, 2011.[91] Y.-S. Lee and S. Mirabbasi, Design of an active-inductor-based termination circuit forhigh-speed I/O, in IEEE International Symposium on Circuits and Systems (ISCAS),2008, pp. 30613064.[92] Y.-S. Lee, S. Sheikhaei, and S. Mirabbasi, A 10Gb/s active-inductor structure with peak-ing control in 90nm CMOS, in IEEE Asian Solid-State Circuits Conference (A-SSCC),2008, pp. 229232.[93] Y. Tsividis, K. Suyama, and K. Vavelidis, Simple 'reconciliation' MOSFET model validin all regions, Electronics letters, vol. 31, no. 6, pp. 506508, 1995.[94] E. E. Eid, F. M. Ghannouchi, and F. Beauregard, Optimal feedforward linearizationsystem design, Microwave Journal, vol. 38, no. 11, pp. 7887, 1995.[95] F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F.Sevic, and N. O. Sokal, Power amplifiers and transmitters for RF and microwave, IEEETransactions on Microwave Theory and Techniques, vol. 50, no. 3, pp. 814826, 2002.[96] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Artech House, Inc.,2006.[97] J. Yi, Y. Yang, M. Park, W. Kang, and B. Kim, Analog predistortion linearizer for high-power RF amplifiers, IEEE Transactions on Microwave Theory and Techniques, vol. 48,no. 12, pp. 27092713, 2000.[98] C. Wang, L. E. Larson, and P. M. Asbeck, A nonlinear capacitance cancellation techniqueand its application to a CMOS class AB power amplifier, in IEEE Radio FrequencyIntegrated Circuits (RFIC) Symposium, 2001, pp. 3942.165[99] C. Wang, M. Vaidyanathan, and L. E. Larson, A capacitance-compensation techniquefor improved linearity in CMOS class-AB power amplifiers, IEEE Journal of Solid-StateCircuits, vol. 39, no. 11, pp. 19271937, 2004.[100] S. Xie, V. Paidi, S. Heikman, L. Shen, A. Chini, U. K. Mishra, M. J. Rodwell, and S. I.Long, High linearity GaN HEMT power amplifier with pre-linearization gate diode,International Journal of High Speed Electronics and Systems, vol. 14, no. 03, pp. 847852,2004.[101] X. Cauchy and A. Francois, Questions and answers on fully depleted SOI technology fornext generation CMOS nodes, SOI Industry Consortium, pp. 117, 2010.[102] T. M. Weller, R. M. Henderson, K. J. Herrick, S. Robertson, R. Kihm, and L. P. Katehi,Three-dimensional high-frequency distribution networks. I. Optimization of CPW dis-continuities, IEEE Transactions on Microwave Theory and Techniques, vol. 48, no. 10,pp. 16351642, 2000.[103] M. C. Scardelletti, G. E. Ponchak, and N. C. Varaljay, Ka-band, MEMS switched linephase shifters implemented in finite ground coplanar waveguide, in 32nd European Mi-crowave Conference (EuMC), 2002, pp. 14.[104] D. Sandstrom, M. Varonen, M. Karkkainen, and K. Halonen, W-band CMOS amplifiersachieving +10dBm saturated output oower and 7.5 dB NF, in IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 2009, pp. 486487.[105] T. Chang and Y.-H. Shiu, Coplanar waveguide filters with floating strips, IEEProceedings-Microwaves, Antennas and Propagation, vol. 147, no. 1, pp. 5862, 2000.[106] R. N. Simons and G. E. Ponchak, Modeling of some coplanar waveguide discontinuities,IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 12, pp. 17961803,1988.[107] N. I. Dib, M. Gupta, G. E. Ponchak, and L. P. Katehi, Characterization of asymmet-ric coplanar waveguide discontinuities, IEEE Transactions on Microwave Theory andTechniques, vol. 41, no. 9, pp. 15491558, 1993.166[108] M. Ribó and L. Pradell, Circuit model for mode conversion in coplanar waveguide asym-metric shunt impedances, Electronics Letters, vol. 35, no. 9, pp. 713715, 1999.[109] M. Ribó, J. De la Cruz, and L. Pradell, Circuit model for mode conversion in coplanarwaveguide asymmetric series-impedances, Electronics Letters, vol. 35, no. 21, pp. 18511853, 1999.[110] G. E. Ponchak, J. Papapolymerou, and M. M. Tentzeris, Excitation of coupled slotlinemode in finite-ground CPW with unequal ground-plane widths, IEEE Transactions onMicrowave Theory and Techniques, vol. 53, no. 2, pp. 713717, 2005.[111] E. Rius, J. P. Coupez, S. Toutain, C. Person, and P. Legaud, Theoretical and experimentalstudy of various types of compensated dielectric bridges for millimeter-wave coplanarapplications, IEEE Transactions on Microwave Theory and Techniques, vol. 48, no. 1,pp. 152156, 2000.[112] A. Mebarki and H. Baudrand, Odd-mode filtering by asymmetrical via-hole in coplanarwaveguide, Electronics Letters, vol. 36, no. 17, pp. 14671468, 2000.[113] A. Natarajan, S. Nicolson, M.-D. Tsai, and B. Floyd, A 60GHz variable-gain LNA in65nm CMOS, in IEEE Asian Solid-State Circuits Conference (A-SSCC), 2008, pp. 117120.[114] Y.-K. Hsieh, J.-L. Kuo, H. Wang, and L.-H. Lu, A 60 GHz broadband low-noise amplifierwith variable-gain control in 65 nm CMOS, IEEE Microwave and Wireless ComponentsLetters, vol. 21, no. 11, pp. 610612, 2011.[115] C.-C. Kuo, Z.-M. Tsai, J.-H. Tsai, and H. Wang, A 7176 GHz CMOS variable gainamplifier using current steering technique, in IEEE Radio Frequency Integrated CircuitsSymposium (RFIC), 2008, pp. 609612.[116] S. Kim, H.-C. Kim, D.-H. Kim, S. Jeon, M. Kim, and J.-S. Rieh, 58-72 GHz CMOSwideband variable gain low-noise amplifier, Electronics letters, vol. 47, no. 16, pp. 904906, 2011.167Appendix ADesign and Layout Techniques for amm-Wave Body-Biased Variable-GainAmplifierA.1 IntroductionThere has been a recent surge in design and implementation of mm-wave wireless transceiverspartly because of the availability of 7 GHz of bandwidth in the relatively less populated unli-censed band from 57 to 64 GHz [27]. Although microwave specialized technologies such as GaAsor InP seems to be the appropriate candidates for implementation of mm-wave transceivers, thelower cost, advances, and mass volume production of CMOS technology has made it a compellingchoice for mm-wave design. However, this choice comes at the expense of more difficulties in thedesign process as advances in CMOS technology are mainly driven by digital circuits. One ofthe most challenging design steps and one of the most important performance limiting factorsin mm-wave CMOS circuits is the design of passive components. The reason is mainly the highloss of silicon substrate and low quality-factor (Q) of such passive devices. Special attentionhas to be paid to this limitation of CMOS process, since at mm-wave frequencies, the gain ofthe transistors are already low and any additional loss in the circuit would excessively impairthe performance and reduce the gain of the circuit. Inductors and transmission lines are widelyused in matching networks in mm-wave designs and each have their own advantages and dis-advantages as compared to the other one. At mm-wave frequencies, inductors have complexbehavior which increases the difficulty of the design. Indeed, frequency-dependent loss of thesubstrate and metal tracks make it difficult to accurately model the electromagnetic (EM) cou-168pling effects in inductors, especially for broadband applications. However, designing circuitswith transmission lines avoids ambiguities in return current path as well as modeling such com-ponents because of the proximity of the signal path to the ground plane in such structures [27].Thus, the frequency response of transmission lines can be more accurately characterized over awide operating frequency range, i.e., from DC to well beyond 60 GHz. Moreover, their behavioris frequency scalable, and they exhibit high electromagnetic field isolation among neighboringcomponents, and thus they are more suited to high-frequency designs. These advantages comeat the price of larger area; however, as the size of such transmission lines is inversely proportionalto the frequency of operation, at mm-wave frequencies their excess size may be tolerated. One ofthe popular options for realizing transmission lines is the use of finite-ground co-planar waveg-uides (CPWs). Unfortunately, using CPWs has the disadvantage of an unwanted odd mode ofpropagation. In this appendix, we first overview the challenges of designing such CPWs andpossible solutions for removing the odd mode of propagation (also referred to as coupled slot-linemode). To attenuate the odd mode of propagation, a fully symmetric layout technique is used.In addition to transmission lines, in Section A.3 a new design technique for decoupling capaci-tors at mm-wave frequencies is also introduced. In Section A.4, the symmetric layout approachis applied to a body-biased two-stage variable-gain amplifier. The gain variation technique isthe same as that explained in Section of chapter . In Section A.5, measurement results of afabricated prototype in 65-nm CMOS are presented. Section A.6 contains concluding remarksas well as comparison with previous work.A.2 Finite-Ground CPW and Odd Mode of PropagationFor mm-wave integrated circuits, there are several advantages in using CPW transmission lineswhich make them superior to their microstrip counterpart. First of all, since CPWs are uni-planar, the connection of series and shunt elements does not need via-holes. Another advantageof CPW compared to microstrips is that their characteristic impedance and phase velocity isless dependent on the thickness of the substrate as these characteristic are mainly dependenton the aspect ratio of the CPW on the same geometrical (typically, horizontal) plane. Alsosince almost the entire field is confined to the surface interface, there is more control over169leakage and unwanted parasitic couplings. In contrast to CPWs, in microstrip lines, the level ofparasitic radiation is influenced by the thickness of substrate as the fields penetrate in the wholesubstrate. In addition, CPW structure is more compatible with the wafer probing and on-chiptesting of microwave integrated circuits. Therefore, CPWs are usually used in microwave andmm-wave integrated circuits. However, it should be noted that in practice finite-ground CPWsare used as having a large (ideally infinite) ground plane is not feasible and/or in compliancewith the design rules of almost all CMOS processes. The use of finite-ground CPWs has beenreported in Wilkinson power dividers (e.g., in [102]) and phase shifters (e.g., in [103]), as well asmatching circuits (e.g., in [104]). A CPW transmission line is composed of two ground planesand a center conductor on the same geometrical plane. Since CPW has three conductors, thereare two possible mode of propagation. In the first one which is the main mode, the centerplane carries the signal and the two side planes carry the return signal and a magnetic wall isformed at the symmetry line of the structure. This mode is a quasi-transverse electromagnetic(quasi-TEM) mode and is called even mode or coplanar mode of propagation. However, thereis another mode of propagation in which two 180 phase shifted signals are carried in the sideplanes and the return path goes through the middle plane and an electrical wall is formed atthe symmetry line of the CPW structure. This mode is called an odd mode or coupled slot-linemode of propagation. While a few works have taken advantage of the odd mode (e.g., see [105]),this mode of propagation is generally considered as an unwanted mode [106, 107, 108, 109]. Fig.A.1 shows the magnetic and electric fields of a CPW in even and odd modes.It is known that the unwanted coupled slot-line mode is triggered when there is a discon-tinuity or asymmetry in the transmission line [106, 107, 108, 109]. Right-angle bends andT-junctions are examples of discontinuities which can initiate the odd mode. Placing shuntstubs at one side of the transmission line is a common cause of asymmetry in CPWs. It shouldbe mentioned that while the asymmetry in infinite-ground CPW is localized at discontinuities,the asymmetry in finite-ground CPWs is continuous along the transmission line [110]. There-fore, finite-ground CPWs may cause higher loss compared to the ideal infinite-ground CPW ifthere is an asymmetry in the line.A common approach to reduce the odd mode of propagation is to use air-bridges [111] whileother elaborate solutions such as adding asymmetric via holes in the CPW ground planes has also170 (a) (b)Figure A.1: Magnetic (dashed lines) and electric (solid lines) fields of a CPW in (a) even mode(b) odd mode of propagationbeen reported in the literature [112]. By using an air-bridge, the potential of the two groundplanes are kept (almost) equal which helps the suppression of the odd mode. However, thisoption is costly and may not be available in every technology. However, in a CMOS technology,such ground equalization could be achieved by using an underpass through a lower metal layer.Fig. A.2 (a) shows the use of underpass for suppressing the odd mode of propagation. As it canbe seen in the figure, at the point of asymmetry, both transverse and longitudinal underpassesare used. Although the use of air-bridges and/or underpasses can reduce the adverse effectsof asymmetry in the CPWs, if the structure is symmetric, the suppression of the odd modewould be much stronger (theoretically, there should not be any odd mode if the layout is fullysymmetric). Fig. A.2 (b) shows the surface current distribution of an asymmetric CPW withan open stub and a physically shorted short stub. As it can be seen in this figure, the currentdistribution in ground planes is asymmetric which in turn indicates the existence of odd modeof propagation in this CPW.To achieve this, wherever there should be a short or an open stub, it is sufficient to divideit into two parallel stubs and place the stubs at the two side of the CPW transmission line. Inthis way, the path seen by the two ground planes of the CPW are equal. In a study in [107],it is shown that although using air-bridges or underpasses can significantly attenuate the oddmode, the symmetric stub structure will lead to a higher quality factor (Q). It is also shownthat the higher Q of symmetric stub structure is not due to lower losses but rather due to a171 								(a) (b)Figure A.2: Layout showing surface current density of (a) a fully symmetric CPW with openand short stubs (b) an asymmetric CPW with open and short stubsmore stored energy. This means that in the symmetric stubs the coupled slot-line mode (oddmode) is not triggered as strongly as in an asymmetric stub which uses an underpass or airbridge. One potential drawback of using symmetric stubs is the need for larger area. Note thatdividing a short stub to two symmetric short stubs results in stubs whose collective size is largerthan that of the original single stub. However, dividing an open stub into two symmetric openstubs results in smaller area as the length of the two stubs together is still shorter than thatof the original stub. In an asymmetric design if one puts all of the stubs on one side of theCPW, the overall area of the design would be much smaller. However, having all the stubs atone side of the CPW, creates a very strong odd mode that even by using air-bridges may not besufficiently attenuated. However, if in an asymmetric design, some stubs are placed at one sideand some on the other side of the CPW, the total area would be about the same or perhaps abit smaller than the area of a corresponding fully symmetric design.A.3 Self-Resonance-based Decoupling CapacitorsAnother important passive component is a decoupling capacitor. Here, we propose an approachfor design and implementation of such capacitors for mm-wave applications. A popular approach172for realizing decoupling capacitors is to use metal-insulator-metal (MiM) capacitors. However,these capacitors exhibit a self-resonance frequency (SRF) which is not large enough for mm-wave frequencies. The available foundry models for the 65-nm CMOS technology used in thiswork predict an SRF of lower than 20 GHz for such MiM capacitors. Note that MiM capacitorsact as inductors at frequencies higher than their SRF. To address this problem, we propose touse a metal-oxide-metal (MoM) capacitor whose SRF can be accurately controlled. As the DCbias of circuit is supplied through short stubs, the proposed decoupling capacitors are connectedto the end of short stubs. Note that if the SRF of the decoupling capacitor is set to coincidewith the operating frequency, the impedance of the capacitor will be minimized at the operatingfrequency (even if the size of the capacitor is small). Beyond the SRF, when the capacitor actsas an inductor, as long as the overall impedance of the structure is relatively small, it can stillact as an AC short circuit. In case of decoupling a short stub, setting the SRF of decouplingcapacitor slightly below the operating frequency would help to have a shorter stub since theinductive behavior of the capacitor helps to reduce the inductance of the stub. The capacitorwhich is employed in this design consists of the two top metal layers and its frequency behaviorhas been carefully modeled using Agilent Momentum®. Please note that although use of MoMcapacitors for decoupling has been applied before in many designs, aligning the self-resonancefrequency of MoM capacitor with operating frequency in order to minimize the impedance isthe new feature of the capacitor in this design. The performance and measurement results ofthis capacitor will be presented in Section A.5.A.4 Amplifier DesignIn this work, a variable-gain amplifier is used as a proof-of-concept for showing the effectivenessof the proposed decoupling capacitor structure as well as symmetric layout technique. Thearchitecture of the presented amplifier is shown in Fig. A.3 and is a cascade of two cascode stages.The advantages of cascode amplifier over other types of amplifiers are explained in Chapter 3.To cover the desired band of 57 to 64 GHz, the well-known staggered-tuning technique is used,i.e., the two stages are tuned to different center frequencies within the band of interest. Inthis particular design, the first stage is tuned to the lower end of the band while the second173Figure A.3: Schematic diagram of the proposed 2-stage variable-gain amplifierstage is tuned to upper end of the band. If more stages were to be used, one could tune to fewmore frequencies staggered within the band too. For the gain variation technique, body-biasingapproach is utilized as explained in Chapter 3. There are various structures for designing thematching circuits. Among wideband matching techniques we have chosen a version of double-balanced matching structure that requires a shorter stub length. All the TLs are 50 Ω and toachieve this impedance in CPW in the 65nm CMOS technology used for this work, signal linewidth of 10 µm and gap of 15 µm are used. Short stubs are constructed by using the decouplingcapacitors explained in Section III. Open stubs are made by simply leaving the end of the TLopen.A.5 Measurement ResultsFig. A.4 (a) shows a micrograph of the fabricated 65-nm CMOS amplifier and Fig. A.4 (b) showsthe distribution of surface current based on simulations in Agilent Momentum EM simulator.The chip including the pads occupies 1.5 mm Ö 0.7 mm. As it can be seen from Fig. A.4,the layout is fully symmetric and wherever there is a stub, either a short or an open, there aretwo of them, one on each side of the TL such that ground planes see an equal path. Due tothis symmetry, the odd mode of propagation in the circuit is almost zero as confirmed by thesymmetric surface current distributions shown in Fig. A.4(b).As discussed in Section A.3, in this design we have aligned the self-resonance frequency ofthe decoupling capacitors with the center of the band (~ 60 GHz), such that the impedance174(a)(b)Figure A.4: (a) Chip micrograph of the proof-of-concept prototype in 65-nm CMOS (b) Layoutshowing surface current distribution simulated in Agilent Momentum175(a) (b)Figure A.5: (a) Micrograph of two equivalent CPW short stubs; a physically shorted short stub(top), a short stub shorted with the proposed decoupling capacitor (bottom), (b) S-parametersof the two stubs: ideal short stub (dotted red) and short stub with the proposed capacitor (solidblue)of the capacitors remains small enough to be considered as a short circuit. To confirm thefunctionality of the proposed decoupling capacitor structure, two CPW short stubs have beenfabricated and their S-parameters have been measured. The first one, shown in Fig. A.5 (a)(top), is an ideal short stub in which the signal line is physically shorted to the ground lines.Note that this structure cannot be utilized in this design, since gate bias of transistors are alsoprovided through short stubs and thus the AC short circuit has to be provided by a capacitor.Fig. A.5 (a) (bottom), shows the short stub with exactly the same length as that of the idealone but with the capacitor which has the self-resonance frequency of ~60 GHz. Fig. A.5 (b),plots the S-parameter of the two short stubs shown in Fig. A.5 (a). The S-parameters havevery close values around 60 GHz (0.86∠118◦ and 0.82∠117◦) which confirms the functionalityof the designed capacitor to operate at mm-wave frequencies.Fig. A.6 shows the measurement results of the gain of the amplifier as well as the simulationresults. Also, Fig. A.7 shows the measurement results for other S-parameters of the amplifier.As can be seen from this figure, the measured centre frequency of the amplifier is at 52 GHzwhile the simulated value was 60 GHz. Moreover, the simulated bandwidth of the amplifier islarger than that of the measured results. To find possible reasons for these discrepancies, webriefly overview the design flow. As explained in Section A.4, the input matching circuit, theinter-stage matching circuit and the output matching circuit are realized through double-stub176Figure A.6: Measurement (solid blue) and simulation (dashed red) results for gain of the am-plifiermatching circuits which incorporate symmetric CPW TLs as their short and open stubs. Thelength of each of these matching stubs is calculated based on the S-parameters of the cascodeamplifier that is used in the design as well as the target gain and stability factor for each stage.After calculating the required electrical and physical length for each stub or interconnect TLs,the matching circuits have been carefully modeled using Agilent Momentum EM simulator. Itshould be noted that in the 65-nm CMOS used in this work, back-end of line (BEOL) has morethan 20 dielectrics stacked in a height of ~4 μm. In this design, the size of each dielectric layeris much lower than the wave-length of the signal. Therefore, for the purpose of EM simulations,it is not necessary to separately define each layer in the simulation setup. Instead, to reducethe memory requirements of simulations, the BEOL is divided into three different equivalentdielectric layers. The first one combines the dielectric layers surrounding thin metal layerstogether. The second one combines the dielectric of two thick top metal layers together, andthe last one is the passivation layer. This is a common approach used by many designers. Inour investigations on the discrepancies between the simulations and measurement results, theshift in the centre frequency and the reduction in the bandwidth of the implemented amplifiercan be attributed to the layout as well as simplifications that were applied for the purpose ofEM simulations. By careful inspection of the layout (Fig. A.4), we believe that the problemis related to the lateral parasitics associated with the interconnection of matching circuits and177	 	 	 	 	 	 	 Figure A.7: Measurement results for S11 and S12 of the amplifier.transistors. To clarify this point, the cross section of a typical such interconnect is shown in Fig.A.8. Note that to save area, we have used an approximately vertical stack of vias to connectthe top metal to the transistors. As shown in the figure, in this case, the distance betweenthe vertical interconnect lines that connect the terminals of the input and output matchingcircuits to each cascode stage is fairly short (about 8 µm in this layout). This relatively shortdistance is the source of a relatively large lateral parasitic capacitance between the interconnectlines (see Fig. A.8) which is in parallel with input-output terminals of each cascode stage. Itshould be noted that to have the minimum resistive loss and minimum capacitive coupling tothe substrate, the top ultra-thick metal (UTM) layer of the 65-nm CMOS is used to constructCPW TLs. Due to the thickness of this metal layer, the lateral parasitic capacitance formedbetween the two interconnects can have a noticeable effect at mm-wave frequencies. Also, itshould be noted that connecting the top metal layer to the transistors in a technology that has 9metal layers, requires 8 via levels. If a large number of vias are used for each level of connectionbetween metal layers, one may consider these vias as two side walls on the two sides of cascodestages which adds to the overall lateral parasitic capacitor.To show that the lateral parasitic capacitance in the interconnects has been the source ofdiscrepancies between the simulation and measurement results, we have manually added the178biasV1M2MbiasV1M2M(a) (b)Figure A.8: The cross section of the interconnection of transmission lines to the cascode stages:(a) the implemented structure, (b) the preferred tapered solutionFigure A.9: Measurement (solid blue) and revised simulation (dashed red) results for gain ofthe amplifierestimated parasitic capacitance in parallel to each cascode stage. Based on the values for lateralparasitic capacitances for different metal layers and also by calculating the lateral parasiticcapacitances between different via levels, a parasitic capacitance of 8 fF is estimated. Fig. A.9shows the results of the revised simulations. As it can be observed the simulation results are nowin harmony with the measurement results. Fig. A.8 (b) shows the cross section of a preferredinterconnection of matching circuits and transistors. As shown in this figure, the interconnectstacks for the input and output of the stage are tapered and thus the lateral distance betweenthem is gradually increased. Hence, the lateral parasitic capacitance between the two matchingcircuits at the two sides of each cascade device will be smaller. This improvement can beachieved at the cost of slightly more area. Finally, Fig. A.10, shows the gain of the designed179Figure A.10: S21 of the body-biased amplifier with bulk-source voltage varying from 0 to 1 VTable A.1: Comparison of the prototype mm-wave VGA with several other published works[113] [114] [115] [116] This WorkProcess (nm) 65 65 90 65 65Number of Stages 3 3 3 3 2Frequency (GHz) 60 61.2 71-76 58.5-73 52Peak Gain (dB) 15 18.9 14 21.5 10Gain Control (dB) 10 11 30 9 25Power (mW) 30.8 45 36 36 12Area (mm2) 1.05 0.25 0.66 0.487 1amplifiers when bulk-source bias voltage of the cascode transistors are varied. As can be seenfrom the figure, the variable gain amplifier achieves a gain variation of about 25 dB (rangingfrom -15 dB to 0 dB of attenuation and from 0 dB to 10 dB of amplification). This gainvariation is obtained with a negligible change in the power consumption. The reason is thatonly the bulk voltage of the common-gate transistor (cascode device) is manipulated and sincein each cascode stage the bias current is set by the gate-source voltage of the common-sourcetransistor (input device), changing the bulk-source voltage of the common-gate transistor doesnot have any significant effect on the bias current. Thus the power consumption of the circuitstays relatively constant.A.6 ConclusionA fully symmetric layout approach for the design of matching circuits using coplanar waveguidesis utilized. A new technique for designing decoupling capacitors at mm-wave frequencies is also180introduced. A variable gain amplifier whose gain is controlled by changing the body voltage of itscascade transistors is designed and fabricated in a 65-nm CMOS technology. The gain variationin this mm-wave amplifier is achieved with no significant change in the power consumption ofthe amplifier. Table 1 summarizes the performance of the designed amplifier and compares itto other mm-wave variable-gain amplifiers reported in the literature.181

Cite

Citation Scheme:

        

Citations by CSL (citeproc-js)

Usage Statistics

Share

Embed

Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                        
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:
http://iiif.library.ubc.ca/presentation/dsp.24.1-0074003/manifest

Comment

Related Items