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On the design of low-voltage power-efficient CMOS active down-conversion mixers Masnadi Shirazi Nejad, Amir Hossein 2013

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ON THE DESIGN OF LOW-VOLTAGE POWER-EFFICIENT CMOS ACTIVE DOWN-CONVERSION MIXERS  by AMIR HOSSEIN MASNADI SHIRAZI NEJAD  B.Sc., University of Tehran, Iran, 2011  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in The Faculty of Graduate Studies (Electrical and Computer Engineering)  THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver) April 2013 © Amir Hossein Masnadi Shirazi Nejad 2013  ABSTRACT The scaling of CMOS technologies has a great impact on analog and radio-frequency (RF) circuit design. In particular, as technology advances the available voltage headroom is decreased due to the use of lower supply voltage. In addition to design challenges due to the headroom limitation, the power consumption is also becoming more important, in particular, in wireless communication applications and portable devices. In this work, we investigate several design techniques for achieving ultra-low-voltage (< 0.5 V), ultra-lowpower (< 500 µW), and ultra-wideband (DC to 8 GHz) wireless receiver building blocks with a specific focus on the active CMOS mixers. Mixers are important building blocks of almost all modern transceivers and they are primarily used for frequency translation. In this work, we briefly review many state-of-the-art design techniques, discuss the advantages and drawbacks of currently used methods, and then we introduce design techniques to improve performances of different receiver building blocks, namely, mixers and LNAs. As a proof-of-concept three different RF active CMOS mixers are designed, have been fabricated in 0.13-µm and 90-nm CMOS processes, and are successfully tested. We have also proposed a linearization method, which is specifically applicable to mixers and low-noise-amplifiers (LNAs). A proof-of-concept circuit for the proposed linearization technique is also designed and implemented in a 0.13-µm CMOS process and is successfully tested.  iii  TABLE OF CONTENTS  Abstract .............................................................................................................................. ii  Table of Contents ............................................................................................................. iii  List of Tables ..................................................................................................................... v  List of Figures ................................................................................................................... vi  List of Abbreviations ........................................................................................................ x  Acknowledgements .......................................................................................................... xi  Chapter 1.   Introduction ............................................................................................... 1   1.1.  1.2.  1.3.  1.3.1.   Motivation ................................................................................................... 1  Objective ..................................................................................................... 3  Contributions............................................................................................... 4  Design techniques for Ultra-Low-Voltage/Power ...................................... 4   1.3.2.   Design techniques for a Highly Linear system ........................................... 7   1.3.3.   Design techniques for low LO power ......................................................... 8   1.3.4.   Design techniques for Ultra-Wide-Band (UWB) ....................................... 8   1.4.  Chapter 2.   Outline....................................................................................................... 10  Background Information and Mixer Fundamentals ........................... 12   2.1.  2.1.1.   Figure of Merit (FoM) Parameters for Mixers .......................................... 14  Conversion Gain/Loss:.............................................................................. 14   2.1.2.   LO Power .................................................................................................. 15   2.1.3.   Linearity and 1-dB Compression point ..................................................... 16   2.1.4.   Noise Figure .............................................................................................. 19   2.1.5.   Port Isolation ............................................................................................. 20   2.1.6.   Standard FoM and Typical Values in Active Mixers ............................... 21   2.2.  2.2.1.   Balanced and Unbalanced Architectures .................................................. 22  Unbalanced Method: ................................................................................. 22   2.2.2.   Single-Balanced Method:.......................................................................... 23   2.2.3.   Double-Balanced Method: ........................................................................ 24   2.3.  Chapter 3.  3.1.   Conclusion and Outline of the Next Chapter ............................................ 25  Active Down-Conversion CMOS Mixer Architectures ....................... 26  Conventional Active CMOS mixer ........................................................... 26   iv  3.1.1.   Unbalanced current commutating mixer:.................................................. 26   3.1.2.   Single-Balanced Current-Commutating Mixer: ........................................ 33   3.1.3.   Double-Balanced Current-Commutating Mixer ....................................... 35   3.1.4.   Linearity in Conventional Active Mixers ................................................. 39   3.1.5.   Power Consumption in Conventional Active Mixers ............................... 41   3.2.  3.2.1.   Improved Active CMOS mixer ................................................................. 42  Design Techniques for Voltage Headroom and Power Improvement: ..... 43   3.2.2.   Design Techniques for Linearity Improvement: ....................................... 54   3.2.3.   Conclusion and Outline of the Next Chapter ............................................ 57   Chapter 4.   Proposed Techniques for a Highly Efficient Mixer ............................. 58   4.1.1.   Proposed Design Techniques for Low Power Consumption: ................... 60   4.1.2.   Proposed Design Techniques for High Linearity: .................................... 72   4.1.3.   Proposed Ultra Low Voltage/Power Double-Balanced Mixer ................. 80   4.1.4.   The Proposed Highly Linear, Ultra-Wide-Band Low-Noise Amplifier ... 92   4.1.5.   Conclusion and Outline of Next Chapter .................................................. 96   Chapter 5.   Implementation and Measurements ...................................................... 97   5.1.1.   Implementation of Proposed Low- Power/Voltage CMOS Mixer ........... 97   5.1.2.   Implementation of Proposed Linearization Technique ........................... 104   Chapter 6.   Conclusion ............................................................................................. 108   6.1.  6.2.  6.2.1.   Introduction ............................................................................................. 108  Achievements .......................................................................................... 108  Ultra-Low-Power and Low-Supply-Voltage Operation ......................... 108   6.2.2.   Wide-Band Switching ............................................................................. 109   6.2.3.   Phase-Shift Linearization Technique ...................................................... 109   6.3.  6.3.1.   Future Work ............................................................................................ 110  Using Proposed Low Power Mixer in a Full Receiver Front-End .......... 110   Bibliography .................................................................................................................. 111  Appendix ........................................................................................................................ 115   v  LIST OF TABLES Table 2 - 1 Typical FoM values for high performance active mixer ................................ 22  Table 4 - 1 Performance of implemented conventional mixer ......................................... 59  Table 4 - 2 Performance of implemented current bleeding mixer .................................... 64  Table 4 - 3 Harmonic cancellation factor for different phase shifts ................................. 77  Table 4 - 4 Component values in a 0.13µm process ......................................................... 83  Table 4 - 5 Post layout results ........................................................................................... 90  Table 4 - 6 Components value for proposed LNA ............................................................ 94  Table 4 - 7 Performance summary and comparison.......................................................... 95  Table 5 - 1 Mixer core component values ......................................................................... 98  Table 5 - 2 Mixer core component values ......................................................................... 99  Table 5 - 3 Measured IIP3 versus supply voltage ........................................................... 103  Table 5 - 4 Performance of implemented 90nm Mixer in 2.5 GHz and IF of 50 MHz .. 104  Table 5 - 5 Performance of implemented 90nm Mixer in 7.5 GHz and IF of 50 MHz .. 104  Table 5 - 6 Measurement result summary....................................................................... 107   vi  LIST OF FIGURES Figure 1 - 1 Simplified schematic of transmitter ................................................................ 2  Figure 1 - 2 Weaver architecture, at least 2 mixers needed ................................................ 2  Figure 1 - 3 Hartley architecture, at least 4 mixers needed ................................................ 3  Figure 1 - 4 General idea of active mixing ......................................................................... 4  Figure 1 - 5 Power consumption of reported active mixers, from 1997 to 2012. Slope of reduction is around 0.8 mW per year but it is leveling off around 1 mW .......................... 5  Figure 1 - 6 Supply voltage of reported active mixers, from 1997 to 2012. Slope of reduction is around 70 mV per year. ................................................................................... 6  Figure 1 - 8 Data-rate for different standards, UWB has the highest data-rate .................. 9  Figure 1 - 9 Intuitive comparison between wideband and narrowband responses. As can be seen narrowband consumes more power since more pulses is required for sending 0 and 1 symbols ..................................................................................................................... 9  Figure 1 - 10 General applications of UWB system ......................................................... 10  Figure 1 - 11 Brief overview of thesis outline .................................................................. 11  Figure 2 - 1 Mixer Symbol ............................................................................................... 12  Figure 2 - 2 Mixing with sampling method ...................................................................... 13  Figure 2 - 3 Concept of Mixing in Time and Frequency domain. .................................... 13  Figure 2 - 4 Conversion gain in Mixer versus LO amplitude ........................................... 15  Figure 2 - 5 Output amplitude versus input amplitude ..................................................... 16  Figure 2 - 6 Nonlinear model of transistor known as Volterra Series .............................. 17  Figure 2 - 7 Concept of 2-tone testing, S4 and S3 are generated due to third order nonlinearity. As can be seen it is very close to fundamental harmonic so it is very easy to measure it by spectrum analyzer. ...................................................................................... 18  Figure 2 - 8 Output amplitudes of fundamental and third order harmonics versus input amplitude, red lines presents actual lab measurements .................................................... 19  Figure 2 - 9 Spectrum of SSB noise figure ....................................................................... 20  Figure 2 - 10 Spectrum of DSB noise figure .................................................................... 20  Figure 2 - 11 Different methods of feedthrough in mixer ................................................ 21  Figure 2 - 12 Symbol of Unbalance Mixer ....................................................................... 23  Figure 2 - 13 Implementing a single-balanced Mixer with 2 unbalanced Mixer.............. 24  Figure 2 - 14 Implementing a double-balanced Mixer form single-balanced Mixer ........ 25  Figure 3 - 1 Unbalanced current commutating mixer ....................................................... 26  Figure 3 - 2 Simplified model for unbalanced current commutating mixer ..................... 27  Figure 3 - 3 For unbalanced current commutating mixer with considering nonideal switch and input impedance of transconductance stage ............................................................... 28  Figure 3 - 4 Required voltage for turning switching stage ON and OFF ......................... 30  Figure 3 - 5 Effect of parasitic capacitances in available RF current ............................... 32  Figure 3 - 6 Conventional single balanced mixer ............................................................. 33  Figure 3 - 8 Conventional double-balanced mixer ........................................................... 35  Figure 3 - 9 Model of double-balanced mixer for finding conversion gain...................... 37   vii  Figure 3 - 10 Effect of mixing architecture in port isolation for a) unbalanced b) single balanced c) double-balanced ............................................................................................. 38 Figure 3 - 11Conventional double-balanced mixer with current source. 4 stages of stacked transistor and resistive load make it difficult to reach high conversion gain while having low supply voltage ................................................................................................ 38 Figure 3 - 12 Single transistor amplifier ........................................................................... 40  Figure 3 - 14 FoM versus DC current and different load resistors ................................... 42  Figure 3 - 15 Conventional Single-Balanced Mixer ......................................................... 43  Figure 3 - 16 Improved mixer with current bleeding technique ....................................... 44  Figure 3 - 17 Adding current bleeding causes to have worsen frequency response ......... 45  Figure 3 - 18 Current bleeding with improved frequency response. LB in intended to resonance with CT and C is large enough to short node Y in frequency of interest ......... 45  Figure 3 - 19 Current reusing technique for improving headroom and transconductance 46  Figure 3 - 20 Relaxing load current by an auxiliary current source ................................. 47  Figure 3 - 21 Stack reduction approach, A) conventional mixing B) two different stacked reduction techniques, folded and body injecting mixer are two examples of top and bottom architectures .......................................................................................................... 48  Figure 3 - 22 Mixer with folded switching stage .............................................................. 49  Figure 3 - 23 Small signal equivalent of folded mixer ..................................................... 49  Figure 3 - 24 Folded mixer with inductor biasing ............................................................ 51  Figure 3 - 25 Folded mixer for with RL biasing. This method is suitable for wide band applications ....................................................................................................................... 52  Figure 3 - 26 Conversion gain versus frequency for hybrid folded mixer........................ 52  Figure 3 - 27 Body-injection mixer .................................................................................. 53  Figure 3 - 28 Figure of gm1, gm2 , and gm3 for a typical NMOS transistor ........................ 55  Figure 3 - 29 A) General DS method concept B) Implementation of DC method with two stages, M1 is biased in strong inversion and M2 is operating in weak inversion .............. 55  Figure 3 - 30 As shown gm3, M1+M2 is zero in a voltage wider range ................................. 56  Figure 3 - 31 Improved conventional double-balanced mixer by applying DS technique in transconductance-stage ..................................................................................................... 56  Figure 3 - 32 IIP3 simulation for mixer of Figure 3 – 30 with and without DS method. In both case power consumption is in range of 2.5-2.7 watts. .............................................. 57  Figure 4 - 1 Implemented double-double-balanced mixer in 0.13µm .............................. 59  Figure 4 - 2 Layout and chip prototype of a conventional double-balanced mixer. Measurement setup is shown in appendix – 2 .................................................................. 59  Figure 4 - 3 Drain current versus Gate-Source voltage behavior in subthreshold and superthreshold ................................................................................................................... 61  Figure 4 - 4 Transconductance efficiency versus inversion coefficient ........................... 62  Figure 4 - 5 Transistor’s fT versus inversion coefficient .................................................. 62  Figure 4 - 6 FOM of NMOS transistor versus inversion coefficient ................................ 63  Figure 4 - 7 Proposed double-balanced current bleeding mixer operating in subthreshold, measurement setup is shown in appendix – 2 ................................................................... 64  Figure 4 - 9 Transconductance of proposed unbalanced-mixer versus time .................... 66  Figure 4 - 10 Gm-stage acts as a buffer to isolate LO from IF .......................................... 67  Figure 4 - 11 Implementation of switching stage with inverter ........................................ 68   viii  Figure 4 - 12 Threshold Voltage versus Body-Source Voltage ........................................ 70  Figure 4 - 13 RON×CParasitic versus NMOS size and in different supply voltages ............. 70  Figure 4 - 14 (a) Inverter with dynamic-threshold-voltage NMOS (DTMOS) and (b) conventional inverter. ....................................................................................................... 71  Figure 4 - 15 Output voltage of the inverter with Wp=200 µm, Wn=100 µm, CL=1pF, PLO= −8 dBm, 2.45 GHz LO signal and DC value of LO is 0.3 V, (a) with dynamic threshold (DTMOS) inverter (b) without dynamic threshold voltage. ............................................. 71  Figure 4 - 16 Comparison of gm2 and gm3 in conventional DS method with current-reuse. As shown, conventional DS method suffers from a high gm2. .......................................... 73  Figure 4 - 17 Complementary operation of PMOS and NMOS causes current reuse to achieve higher linearity ..................................................................................................... 74  Figure 4 - 18 Basic concept of nonlinear system, due to intrinsic feedback other intermodulations can be mixed by input signal and create IM3. ...................................... 74  Figure 4 - 19 Block diagram of the proposed harmonic cancellation technique. ............. 75  Figure 4 - 20 PSHC concept in phasor domain. Each vector is normalized by itself so all vectors have a same size. .................................................................................................. 76  Figure 4 - 21 Proposed phase-shifter circuit using lump components (excluding biasing) ........................................................................................................................................... 77  Figure 4 - 22 Phase response and of the proposed RLC networks; The components of the second network are adjusted to cancel the 3rd harmonic at 2.4 GHz. ......................... 79  Figure 4 - 23 Plot of terms in Equation (10) versus frequency from 1 to 9. ..... 80  Figure 4 - 24 Different configurations in Gm-stage ......................................................... 81  Figure 4 - 25 Simplified model of inverters and their load during turning ON the Gmstage .................................................................................................................................. 82  Figure 4 - 26 Model of generated Gm in NMOS or PMOS device versus time ............... 82  Figure 4 - 27 Schematic of the proposed mixer, VBP and VBN are bias voltages. Note that LC input matching networks (not shown in the figure) are used at both LO and RF terminals. ........................................................................................................................... 83  Figure 4 - 28 Simple model for output voltage of inverters at switching stage (Node A or B in Figure 4 - 24). ............................................................................................................ 85  Figure 4 - 29 gmtotal	 versus time ................................................................................... 85  Figure 4 - 30 Simulation results in a 0.13 µm process for power consumption of proposed mixer, versus supply voltage and in different frequencies ............................................... 87  Figure 4 - 31 (a) Conventional inverter, (b) wideband inverter ........................................ 88  Figure 4 - 32 Resonance passive-gain (| | ) versus frequency. .............................. 89  Figure 4 - 33 	 	1 and 12π versus C and in fixed L, R, and ......................................................................................................................... 89  Figure 4 - 34 Conversion Gain versus LO power and supply Voltage ............................. 90  Figure 4 - 35 Layout of proposed Mixer in 0.13 m CMOS ............................................ 91  Figure 4 - 36 Conversion gain in subthreshold mode versus LO power for different supply voltages from 0.4V to 0.2V. Conversion gain (in dB) is positive for supply voltages larger than 0.25V ................................................................................................ 91  Figure 4 - 37 Conversion gain versus LO power with and without dynamic threshold voltage ............................................................................................................................... 92  Figure 4 - 38 Schematic of proposed LNA ....................................................................... 93  Figure 4 - 39 Layout of proposed LNA in IBM 0.13µm process. .................................... 93   ix  Figure 4 - 40 Post-Layout simulation for S21 and NF ....................................................... 94  Figure 4 - 41 IIP3 versus R2 resistance at 1.5GHz, peak value is for R=70.3 Ω .............. 95  Figure 5 - 1 Schematic of proposed mixer ........................................................................ 97  Figure 5 - 2 Layout and chip photograph of proposed mixer in a 90nm process ............. 98  Figure 5 - 3 Conversion gain versus supply voltage ......................................................... 99  Figure 5 - 4 Conversion gain versus frequency. IF is 50 MHz ....................................... 100  Figure 5 - 5 Conversion Gain versus LO power ............................................................. 100  Figure 5 - 6 Power consumption versus supply voltage ................................................. 101  Figure 5 - 7 Power consumption versus input frequency ............................................... 102  Figure 5 - 8 Tow tone measurement, in this VDD is 0.55V, VBP is 0V, and PMOS transistor operates in strong inversion ............................................................................ 103  Figure 5 - 9 Tow tone measurement, in this VDD is 0.55V, VBP is 0.1V, and PMOS transistor operates in weak inversion .............................................................................. 103  Figure 5 - 10 Chip photograph of proposed Low Noise Amplifier ................................ 105  Figure 5 - 11 Measured and Post-Layout Simulation Results of S21 .............................. 105  Figure 5 - 12 Measured Result of S11.............................................................................. 106  Figure 5 - 13 Two tone measurement of proposed LNA ................................................ 107  Figure 6 - 1 Layout of 2.5 GHz receiver suitable for cellular application ..................... 110   x  LIST OF ABBREVIATIONS  RF  Radio Frequency  LO  Local Oscillator  IF  Intermediate Frequency  CG  Conversion Gain  CMOS  Complementary Metal-Oxide Semiconductor  RL  Load Resistor  VGS  Gate-to-Source voltage  Vth  Threshold Voltage  VOV  Overdrive Voltage  gm  Transconductance  PLO  Local Oscillator Power  xi  ACKNOWLEDGEMENTS  I would not have completed this thesis without the significant help of many great people who have made my life at UBC a pleasant and productive experience. First and foremost, I would like to express my sincere gratitude to my supervisor, Dr. Shahriar Mirabbasi, for his continuous support and patience during my stay at UBC. I consider myself very fortunate for having the opportunity to work with him. This work is dedicated to my wonderful parents for all their love and support. I always felt them near me, even though they were living far away during my period of study in Canada. They have been my main motivation throughout my studies. Also I would like to thank my dear brothers, Mostafa, and Mohammad Sadegh for paving the way for me and enormously helped me to finish my Masters in less than expected time. This research is supported by the Natural Sciences and Engineering Research Council of Canada (NSERC). Access to technology and chip fabrication is facilitated by CMC Microsystems.  xii  TO MY PARENTS  CHAPTER 1. INTRODUCTION  Chapter 1.  1  INTRODUCTION  1.1. MOTIVATION Wireless communication systems have experienced major advances over the past decades. For example, communicating data to and from spacecrafts operating at the edge of the solar system, e.g., Voyager1 and Curiosity2 are not science fiction anymore. However, we should keep in mind that in most cases in wireless communication, higher performance and sensitivity are achieved at the cost of higher power consumption. This fact has motivated a tremendous amount of research over recent years to minimize power consumption. As a result, today many radio-frequency integrated-circuits (RFICs) (e.g., smart phones, and global positioning system (GPS) and cellular devices) operate from a small battery and have a relatively long life-time, and their power consumption is in the range of few milli-watts (mWs). Although mW-level power consumption is suitable for many wireless applications, this level is still high for applications such as wireless biomedical implants or radio-frequency identification (RFID) circuits in which using a reasonable size battery is not feasible. Such demands have motivated exploration of new design methodologies for wireless building blocks to target micro-watt (µW) power levels. Note that lowering the power consumption should not sacrifice the system’s performance, in other words, despite consuming ultra low power (µW level), the performance requirements of the system should still be satisfied. In studying of different architectures for wireless transceivers, 4 main building blocks can be identified. Figure 1-1 shows a simplified architecture for a receiver and a transmitter. In the receiver side, after getting a signal from antenna, low-noise amplifier (LNA) is responsible for amplifying the weak received signal so it can be distinguished from noise. Next, the RF signal is typically down-converted by a mixer and a local oscillator (LO) to baseband or intermediate frequency (IF). The LO signal is typically generated by a voltage-controlled oscillator (VCO) and frequency conversion is being 1  Voyager 1 is now sending data with 160 bits per second, its distance from sun is 1.8003×1010 km, weekly reports for sent data are available in [1] 2 Successfully landed on Mars on August 5th, 2012.  CHAPTER 1. INTRODUCTION  2  performed by RF mixer. In the transmitter side, first, digital (or occasionally analog) signal is up-converted using an LO and a mixer. Next, based on the standard, the signal is amplified to a certain level by a power amplifier (PA), and finally the signal is propagated in the space using an antenna.  Figure 1 - 1 Simplified schematic of transmitter  To achieve low-power consumption for the overall wireless system, one needs to optimise or choose a proper architecture for these main building blocks (i.e., LNA, Mixer, VCO, and PA). For three reasons that we explain shortly, the main focus of this thesis is on mixer design. First, since LO port of the mixer is fed by the VCO, reducing sensitivity of mixer to level of LO power (PLO) can results in reduction of the power of the VCO. This is due to fact that by reducing the required PLO for mixer, a smaller amplitude for LO is required and thus one can operate the VCO with a lower current and hence a lower power. Secondly, considering popular architectures for wireless transceivers (e.g., Weaver and Hartley image-rejection methods, Figures 1-2 and 1-3), generally a few mixers are required in the transceiver. Therefore, since many mixers are used in the system, they can play an important role in the overall power consumption of the systems.  Figure 1 - 2 Weaver architecture, at least 2 mixers needed  CHAPTER 1. INTRODUCTION  3  Figure 1 - 3 Hartley architecture, at least 4 mixers needed  Thirdly, based on published work on mixers, the power consumption of low-power mixers is typically in the range of 1 to 5 mW. Hence, to achieve a µW-level wireless transceiver further attention should be paid to mixers (better optimization or redesign).  1.2. OBJECTIVE The objective of this work is to design an ultra-low-voltage (less than 0.5 V), ultra-lowpower (less than 500 µW), ultra-wide-band (UWB, DC to 8 GHz) CMOS active mixer. To achieve these three main goals we first conduct a survey on reported mixer designs. Through this step, we also set our performance goals based on those of commonly used active mixer architectures. Secondly, as will be discussed further in Chapters 3 and 4, mixers with conventional architectures are not quite suitable for our power-consumption and supply-voltage targets, and thus we propose a new design methodology which can resolve the performance bottlenecks of previous approaches. As a proof-of-concept the proposed mixer core is designed and laid out in a 0.13-µm CMOS process. Post-layout simulation results confirm the feasibility of the proposed method (for achieving ultralow-voltage and power) while achieving the desired performance. Moreover, a main part of the mixer core is fabricated and successfully tested. Finally to verify the proposed mixing technique and also verify its applicability to different process technologies, another test-chip is designed, fabricated, and successfully tested in a 90-nm CMOS process.  CHAPTER 1. INTRODUCTION  4  1.3. CONTRIBUTIONS 1.3.1. Design techniques for Ultra-Low-Voltage/Power The scaling of CMOS technology has a great impact on analog and RF systems. In particular as technology advances available voltage headroom is decreased due to use of a lower supply voltage. Therefore, special attention should be paid to biasing the analog circuits so that their active devices operate in their proper region of operations (i.e., strong or moderate inversion). Among RF building blocks, mixers are more vulnerable than other blocks. This is because they consist of two main stages. As shown in Figure 4, typically in mixers, RF signal is first converted to RF current using the transconductance stage (Gm -Stage), and next this RF current is switched by LO signal in switching-stage (LO-Stage). In most architectures, these two blocks have to be stacked above each other which further reduces the available voltage headroom for each stage.  Figure 1 - 4 General idea of active mixing  Among the popular active mixer architectures, Gilbert-type designs are widely used due to their reasonable conversion gain, noise figure, and linearity. However, Gilberttype structures are not amenable to low-voltage operation because of using stacked transistors. For mixers to operate from a lower supply voltage, several techniques have been proposed. An elegant approach as presented in [2] is to separate the switching stage  5  CHAPTER 1. INTRODUCTION  from the transconductance (Gm) stage and use switched transconductance technique instead of current commutating. This approach reduces the required power supply. However, as discussed in [2], due to the transient time of switching signal, i.e., rise/fall time, τsw, and corresponding change of operating point during this transition, special attention has to be paid to achieve reasonable linearity and conversion gain. Furthermore, the conversion gain of such mixers depends on τsw. An alternative approach to lower the power consumption and supply voltage is to operate the circuit in the subthreshold region [3]. Despite the ultra-low-power consumption, due to using stacked transistors the required supply voltage is still relatively high. Moreover, the linearity and noise figure performance are compromised. To reduce the number of stacked transistors, folded arch itectures have been proposed [4]. Such architectures are interesting due to their wideband response as well as robustness to mismatch; however, they use RF chokes for biasing and provide a low conversion gain at low supply voltages. Figures 1-5 and 1-6 show the trend in power consumption and supply voltage of mixers over the past 16 years (From 1996 to 2012, from published literature). As can be seen from these figures, power consumption is leveling-off around 1 mW and supply voltage is reduced to around 0.5 V.  Power Consumption (mW)  30 25 20 15 10 5 0 1995  1998  2001  2004  Year  2007  2010  2013  Figure 1 - 5 Power consumption of reported active mixers, from 1997 to 2012. Slope of reduction  is around 0.8 mW per year but it is leveling off around 1 mW  6  CHAPTER 1. INTRODUCTION  Supply Voltage (V)  4  3  2  1  0 1996  1998  2000  2002  2004  2006  2008  2010  2012  2014  Year Figure 1 - 6 Supply voltage of reported active mixers, from 1997 to 2012. Slope of reduction is  around 70 mV per year.  These improvements in power consumption and supply voltage are mostly at the cost of system’s performance. In particular, they result in having a lower conversion gain and a worse noise figure. In this thesis, a low-voltage low-power mixer structure is proposed that combines several techniques to improve the performance of the circuit. More specifically, to lower the required supply voltage, the number of stacked transistors is reduced by separating the LO stage and Gm stage. Furthermore, the switched transconductance technique [2] (switching the supply voltage of Gm stages) is used instead of conventional current commutating to reduce both supply and power. To further decrease supply voltage and improve the conversion gain, dynamic-threshold-voltage technique [5] is used in the switching blocks. Moreover, to improve linearity and conversion gain the Gm stage uses current reuse technique [6].  CHAPTER 1. INTRODUCTION  7  1.3.2. Design techniques for a Highly Linear system The increasing demand for wireless communication has resulted in many communication standards. In these systems the receiver has to be able to process the desired signal while minimizing the adverse effects of interferences due to undesired signals within the same standard and/or those from other standards. Such interference minimization/cancellation requires diligent design considerations. Among different design specifications, linearity plays an important role in most of RF systems. Typically, in a wireless transceiver design, special attention has to be paid to the linearity performance of the low-noise amplifier (LNA), mixer, and power amplifier. Note that the improvement in linearity should not compromise the desired gain or noise performance of the system [7]. To improve the linearity in radio frequency (RF) amplifiers, a common technique is to bias transistors at or in the vicinity of their linear “sweet-spot” [8] at which the third derivative of the device transconductance is zero. This is an interesting approach, however, it is sensitive to the circuit biasing condition since the region over which the linearity is boosted is typically narrow and furthermore the bias point is likely to change due to temperature and process variations leading to a sensitive and limited improvement [7]. Another interesting technique for linearization is based on negative-feedback approach, which compromises the gain to boost linearity. However, applying negativefeedback- based techniques at RF frequencies is challenging and requires special attention to stability [7]. Derivative superposition (DS) technique and modified DS methods have also been proposed to improve linearity. In these exciting methods, an auxiliary transistor is employed which is biased in weak or moderate inversion to cancel the nonlinear components of the main transistor and extend the linearity sweet-spot [1, 9, 10]. These techniques improve the linearity without sacrificing the gain, however, they typically result in increased second-order intermodulation (IM2) component [10]. As a side note, most of the abovementioned approaches focus on minimizing the third-order intermodulation (IM3) component.  CHAPTER 1. INTRODUCTION  8  In this thesis, an alternative idea is proposed that attenuates (and ideally cancels) undesired harmonics (and therefore intermodulation distortion terms (IM2, IM3, …)) by combining two phase-shifted replicas of the input signal. Proposed conceptual idea has been implemented and successfully tested in a low noise amplifier.  1.3.3. Design techniques for low LO power In most cellular applications, local oscillator signal is being implemented with on-chip VCO. In mixers, the local oscillator is responsible to down- or up-convert the input RF signal. Typically for frequency conversion, in switching stage of the mixer, certain amplitude threshold is required which dictates required voltage swing to VCO designers. In VCOs, voltage swing is proportional to bias current and thus power consumption. Thus, it is desired to have a mixer with low switching threshold amplitude. In this thesis two different techniques are proposed to reduce switching threshold voltage. 1.3.4. Design techniques for Ultra-Wide-Band (UWB) Ultra-Wideband (UWB) techniques have been developed since 1960’s, e.g., time-domain electromagnetics (TDE) [12]. UWB technology is becoming more and more popular, particularly for short/mid range wireless personal area networks (WPANs). The main purpose of UWB is to increase available bandwidth so data such as video can be sent with higher data-rate. Also multitude of standards can be covered which allows the users to benefit from different wireless services such as WiFi and WiMAX. As a result of multi-standard capability and availability of high band-width, UWB wireless is becoming more popular [13]. Figure 1-8 shows available data rate for different IEEE standards [14].  CHAPTER 1. INTRODUCTION  Figure 1 - 7 Data-rate for different standards, UWB has the highest data-rate  Another interesting advantage of UWB systems is that they are intrinsically low power since the system operates by sending short pulses in time domain [13],[15].  Figure 1 - 8 Intuitive comparison between wideband and narrowband responses. As can be seen  narrowband consumes more power since more pulses is required for sending 0 and 1 symbols  9  10  CHAPTER 1. INTRODUCTION In summary, UWB is suitable for: 1. Low power data transmission. 2. Secure communication since spectral power per frequency is very low. 3. High band-width and multi-standard coverage, suitable for cellular networks or High-Definition (HD) video transmission (Figure 1-10).  Phone to PC  integration  Large Screen  Communication  Handset and Car  Audio  Audio  Figure 1 - 9 General applications of UWB system  In this work, a design procedure for implementing UWB (DC-8 GHz) CMOS mixer and LNA is presented. The proposed technique is general and can be applied to other RF building blocks. As a proof-of-concept, a 90-nm CMOS mixer and a 130-nm CMOS LNA are designed, implemented and successfully tested.  1.4. OUTLINE This thesis is organized as follows. In Chapter 2 some principles and background information about RF transceivers and mixers are reviewed. Chapter 3 focuses on RF mixers and addresses bottlenecks of conventional design techniques. Chapter 4 discusses some design techniques to improve mixer performance while reducing power  CHAPTER 1. INTRODUCTION  11  consumption. Proposed techniques are supported by post-layout simulations. In addition, different techniques for linearity improvement in RF systems are discussed. Chapter 5 presents measurement and simulation results of the prood0of-concept prototypes and finally, Chapter 6 concludes the thesis. Figure 1-11 briefly shows the structure of this thesis.  Figure 1 - 10 Brief overview of thesis outline  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  Chapter 2.  12  BACKGROUND INFORMATION AND MIXER  FUNDAMENTALS Mixer is a three port element and, as shown in Figure 2-1, it has two inputs for radio frequency (RF) and local oscillator (LO) signals and one output for intermediate frequency (IF) signal. Depending on which part of transceiver (transmitter or receiver) the mixer is being used, IF and RF can be replaced with each other. In the receiver side, RF signal is captured from antenna, goes into mixer and is down converted to an IF signal. This IF signal can be filtered for image rejection and then be sampled by an analog-to-digital converter (ADC). In the transmitter side, the baseband (or some occasions IF) signal, is up-converted and modulated by the LO signal to an RF signal. This RF signal is then radiated into space (after amplification by a power amplifier (PA)) by an antenna. In the rest of this thesis, it is assumed that RF signal is the input and is mixed with an LO signal.  Figure 2 - 1 – Mixer Symbol  Regardless of place of use, mixing process can be implemented by two main methods, using sampling or nonlinearity. The sampling approach can be explained both in the frequency-domain and time-domain. In the frequency domain, frequency conversion from one band to another band is due to the convolution of the desired signal with an impulse train. Although this convolution creates different replicas of the main signal, by using a proper filter the undesired signal components can be removed. The impulse train in the frequency domain represents sampling in the time-domain and the convolution in the frequency domain is the equivalent of the multiplication in the time-domain.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  13  Figure 2 - 2 Mixing with sampling method Amplitude  Amplitude Data  Amplitude Sampled Signal  Sampling   * FRF  =  Frequency  FLO Amplitude  Amplitude  IF Data Filtering  Data  Frequency  Frequency  Frequency FIF Amplitude Sampled Signal  FIF IF Data  Sampling  Filtering  = Time  TLO  Time  Time  Time  Figure 2 - 3 Concept of Mixing in Time and Frequency domain.  Nonlinear mixing method is similar to the sampling approach and it can be understood from time-domain analysis:      ⋯  => 2  	 …  (2-1)  Mixing (through switching, sampling, multiplying, …) of signals can be implemented with either passive and active circuits. In passive methods switching is done by using a nonlinear passive element, such as a diode, or a MOS transistor (operating in the triode region). Since in passive mixers, the DC power consumption is zero, and no active  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  14  amplification is used, generally the converted signal has a lower amplitude as compared to the input signal; this is referred to as the conversion loss of the mixer. Conversion loss can be minimized by using a more nonlinear device. Due to conversion loss, and higher noise figure, passive mixers are mostly used in microwave and measurement applications rather than cellular applications. In active methods, mixing is being implemented by sampling. In contrast to passive methods where the mixing process is done in one stage (e.g., RF signal mixed with LO signal in a diode), in an active approach, first the RF signal, which is typically a voltage signal, is converted to an RF current in a transconductance stage. Second, the generated RF current is sampled in the switching-stage by an LO frequency. In this approach signal can be amplified in the transconductance stage as well as the switching stage. This results in a conversion gain which in turn can reduce the overall noise figure (NF) of the system. The focus of this thesis is on this type of mixers as they are more popular in cellular application and integrated transceivers. Regardless of the type of the mixer, the performance of the mixer can be evaluated using different figure of merit (FoM) parameters. In this chapter, we present these parameters and also briefly review the commonly used mixer architectures.  2.1. FIGURE OF MERIT (FOM) PARAMETERS FOR MIXERS 2.1.1. Conversion Gain/Loss: Based on the mixer topology, the conversion-gain or conversion-loss of the mixer can be defined. The voltage conversion gain/loss is the ratio of the root-mean-square (rms) voltage of input signal (RF or IF) to the rms voltage of output signal (IF or RF). Power conversion gain of mixer is defined as ratio of the power delivered to the load and the available power at the input. In case that input source impedance and output load impedance become equal (e.g., 50 ohm), voltage and power gain can easily be translated to each other.   																																																																																 2  2  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  20  ,    ,  10  10    												 2  15  3    2.1.2. LO Power The local oscillator is typically used in the switching stage. Ideally, it is desired that the LO signal be sufficiently high power so that it can fully turn the switches ON or OFF in order to maximize the gain of the system. Figure 2-4 shows a typical plot for conversion gain (CG) versus LO power (PLO). It is desired to reach the flat area in the conversion gain while using a low PLO. This issue is very important for low-power applications for two reasons. First and foremost, in integrated transceiver architectures LO is generated with an on chip VCO. Based on Equation 2-4 peak-to-peak amplitude of VCO is typically proportional to VCO bias current, therefore, lower PLO for mixer side means lower power consumption for the VCO and the overall transceiver. ∝  ∝  																																																																																																							 2  4  Figure 2 - 4 Conversion gain in Mixer versus LO amplitude  Secondly, as will be discussed in Chapter 4, depending on the mixer, a lower PLO can lead to a lower power consumption in the mixer.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  16  2.1.3. Linearity and 1-dB Compression point Although frequency translation in mixers is being implemented with a highly nonlinear circuit, linearity is one the most important design considerations of the mixers. The definition of the linearity is a little different in mixer as input and output signals are at different frequencies. Let us consider Equation 2-5 as a typical nonlinear model for the system where y(t) is the output signal (e.g., IF signal) and x(t) is a single tone with frequency of  and amplitude of .   ⋯      3 2  ⋯    4  2   Now, looking at  2    4    ⋯	 2  5  term, in a physical system α1 is nominal system gain and  α3 is negative and casues reduction in the total gain as  increases. The point at which the  fundamental amplitude of the output decreases by 1 dB is referred to as 1-dB compression point. In addition to gain reduction, power sharing in undesired harmonics (especially in 3rd and 2nd harmonics) is problematic since it theoretically can create infinite number of harmonics in the desired band, which can in turn cause blocking effect [16].  Output  Amplitude,  1dB  Nominal Gain, Input Amplitude, A  Figure 2 - 5 Output amplitude versus input amplitude  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  17  For a single transistor, the Taylor series expansion of the drain current versus gate-source voltage up to its third-order term can be expressed as:  Figure 2 - 6 Nonlinear model of transistor known as Volterra Series    ⋯																																													 2  6  Where gm1, gm2 , gm3 are the first, second, and third-order transconductance of the transistor. Thus the linearity of a single transistor, e.g., a common-source amplifier can be controlled through adjusting the values of the gm2 and gm3 in above equation. 2.1.3.1. Measuring Linearity in a Real Circuit Evaluating the nonlinearity of a real circuit is done by different metrics such as total harmonic distortion (THD). However, there is a specific method in RF systems known as 2-tone testing which measures input-referred third-order intercept point (IIP3) [17]. One reason for using IIP3 measurement instead of THD in RF systems is that since fundamental frequency can be high (e.g., in the range of GHz or beyond), it can be difficult to measure its harmonics with a typical lab instruments. For understanding 2tone measurement, consider the equation below as a nonlinear model where input signal is composed of 2 tones.  where  is:  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  18       2   4         2  3  3    3  4        3      3    4 2  2    3  4  2 2 2    3  4    2  	 … 	2  7  To simplify Equation 2 – 7, consider Figure 2-7. Amplitude  Amplitude Spectrum  Analyzer Nonlinear System  S2 S1 S3 S4 ω1 ω2  ω1 ω2  Frequency  Spectrum  Analyzer  2ω1+ω2 2ω2+ω1  Frequency  Figure 2 - 7 Concept of 2-tone testing, S4 and S3 are generated due to third order nonlinearity. As can be seen it is very close to fundamental harmonic so it is very easy to measure it by spectrum analyzer.  As can be seen from this figure, in addition to ω1 and ω2, different harmonics are being generated due to system’s nonlinearity which their amplitude is proportional to  . So by taking into account that the input amplitude of the two tones is known, can be readily calculated. The input amplitude for which the amplitude of S1  (fundamental) becomes equal to that of S4 (generated due to third-order nonlinearity) is known as IIP3 and can be calculated as:  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  3  20 log  4  																																																																											 2  19  8  Figure 2 - 8 Output amplitudes of fundamental and third order harmonics (S1 and S2 in Figure 2 - 7) versus input amplitude, red lines present actual lab measurements  2.1.4. Noise Figure The noise figure of down-conversion mixers is often a source of great confusion. For simplicity, let us consider a noiseless mixer with unity conversion gain. As shown in Figure 2-9, the spectrum sensed by the RF port consists of a signal component and the thermal noise of Rs in both the signal band and the image band. Upon down-conversion, the signal, the noise in the signal band, and the noise in the image band are translated to the IF band. Thus, the output SNR is half of that of the input SNR if the noise components have equal power, i.e., the mixer exhibits a flat frequency response at its input from the image band to the signal band. Therefore, if CG is assumed to be 0, NF is 3-dB. This quantity is called single-sideband (SSB) noise [18].  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  20  Amplitude Data  RF  IF  RRS LO  Cos(ωLOt)  Spectrum at RF  FRF FLO FImage Frequency Amplitude Data Spectrum at IF  FIF  Frequency  Figure 2 - 9 Spectrum of SSB noise figure  Now consider a frequency conversion which has zero IF, known as direct-conversion mixer. In this method RF frequency is exactly the same as LO signal so down-converted noise becomes half the SSB noise and hence considering unity gain for mixer, NF is equal to 0dB. Thus, in summary, SSB noise is 3 dB higher than the DSB NF.  Figure 2 - 10 Spectrum of DSB noise figure  2.1.5. Port Isolation In an RF system, isolation is a parameter to measure amount of leakage from one port to another. It is desired to have infinite port isolation, that is, a zero crosstalk between the ports. However, in a physical circuit, due to parasitic capacitances and paths between any  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  21  two ports, the isolation between the ports is not infinite. As the mixer has three ports, 6 isolations can be defined. RF signal would have leakage to IF and LO ports (IF-RF and LO-RF isolations), LO signal would have leakage to IF and RF ports (IF-LO and RF-LO isolations), and IF signal could have leakage to LO and RF port (RF-IF and LO-IF isolations). Any leakage to input ports would cause additional signal modulation and hence wider frequency response at the output. Also, any leakage to the output would cause additional frequency components. Generally, in mixers, undesired frequency components at the output can be filtered since frequency difference between the output and the input is relatively large and a reasonable lowpass filter can filter out the undesired components.  Figure 2 - 11 Different methods of feedthrough in mixer  2.1.6. Standard FoM and Typical Values in Active Mixers Different FoMs have been defined and used in the literature to include the effects of all or some of the abovementioned parameters. FoM is typically used to compare the performance of different mixers. Equations (2-8) and (2-9) show two different popular FoMs for mixers [19]. The first FoM emphasizes on effect of supply voltage while the second one is a standard FoM widely used for mixers.    10	log  10   .  .  1	GHz  																																																							 2  8  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES    10	log  10  .  1	GHz  22  																																																								 2  9  For a typical active CMOS mixer FoM1 is in range of 1 to 30 and FoM2 is around 0 to 25. To get a better idea about the performance of a typical active CMOS mixer, FoMs of different mixers are listed in Table 2-1. Table 2 - 1 Typical FoM values for high performance active mixer Reference  [20]  [21]  [22]  [23]  [24]  RF (GHz)  2.01  2.4  2.4  5.3  8.6  IF (MHz)  10  60  1  1  4350  PLO(dBm)  −4  −9  −2.0  −3.6  −3.3  VDD(V)  1  1 Subthreshold  1.8  0.9  0.6  PDC(mW)  0.49  0.5  8.1  6.6  0.6  NF (dB)  23.7  18.3  12.9  24  15.9  IIP3(dBm)  7  −9  1  −11.6  −8  Conversion Gain (dB)  9.8  15.7  15.7  8.9  6  CMOS Technology (µm)  0.18  0.13  0.13  0.13  0.13  FOM1 / FOM2  18.62 / 17.83  22.15/ 21.36  14.41 / 16.17  1.75 / 0.50  24.32 /21.31  2.2. BALANCED AND UNBALANCED ARCHITECTURES Generally mixers can be classified into 3 categories, unbalanced, single-balanced and double-balanced architectures. Reason for this classification is that in reality RF signal can be mixed to LO signal in 3 ways as follow. 2.2.1. Unbalanced Method: In this method of mixing RF and LO signals are mixed together including their DC values. As will be shown in Chapter 3, in physical mixers, this DC component is due to circuit bias and switch model  Undesired  Desired .  .    .    	.  	.  				 2  10  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  As can be seen, in addition to mixture of RF and LO in  23  , due to DC values of RF and  LO, each of those signals can be seen in the output. As discussed, any leakage from one port to another is undesired, so unbalanced method suffers from low IF-RF and IF-LO port isolations. We show unbalanced mixer as Figure 2-12 for further analysis.  Figure 2 - 12 Symbol of Unbalance Mixer  2.2.2. Single-Balanced Method: The single-balanced method is referred to an architecture in which DC component in one of the input signals is omitted:  . .  .    	.      																														 	2  11  .    	.      																														 	2  12  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  24  As can be seen, this architecture can eliminate either IF-RF leakage (LO balanced) or IFLO leakage (RF balanced). Practically, single-balanced method can be implemented by using two unbalanced mixers as shown in Figure 2 - 13.  Figure 2 - 13 Implementing a single-balanced Mixer with 2 unbalanced Mixer  2.2.3. Double-Balanced Method: The double-balanced method is referred to an architecture in which DC value in both of the input signals is canceled: .  .      														 	2  13  This is the most popular architecture in cellular applications since there is no need for further output filtering and hence requires less area in comparison to unbalanced and single balanced methods. Practically, as can be seen from Figure 2-14, double-balanced method can be implemented by using two single balanced mixers.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  25  Figure 2 - 14 Implementing a double-balanced Mixer form single-balanced Mixer  The double-balanced architecture can theoretically suppress undesired high-frequency harmonics in its output and this it provides high port isolation. However, this achievement will be at the cost of higher power consumption and area.  2.3. CONCLUSION AND OUTLINE OF THE NEXT CHAPTER Similar to any other systems, ultimate goal in designing mixer is to achieve higher performance or equivalently increase the Mixer’s FoM. However, achieving this goal can be difficult as all performance parameters have tight correlation with each other. For example, increasing CG can severely impact linearity but it improves NF. On the other hand, decreasing LO power can reduce CG and reducing power will impact all system parameters. Thus, to design a state-of-the-art mixer first we should have deeper understanding about the trade offs. Chapter 3 provides detailed analysis for conventional and modern mixer architectures and will address their performance bottlenecks.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  Chapter 3.  26  ACTIVE DOWN-CONVERSION CMOS  MIXER ARCHITECTURES This chapter overviews different mixer architectures. First, conventional mixing methods will be discussed followed by improved topologies for low power, low supply voltage, and high linearity.  3.1. CONVENTIONAL ACTIVE CMOS MIXER 3.1.1.  Unbalanced current commutating mixer:  Figure 3-1 shows the simplest active mixer. It consists of two main blocks, transconductance stage known as Gm-stage which converts RF voltage to RF current, and switching stage known as LO-stage for switching current between path 1 and path 2. Due to this type of current switching between two branches, these mixer families are known as current commutating architecture. It is important to note that in unbalanced and singlebalanced mixers bias current of LO-stage is being generated from transconductance stage and hence there is no independent current source in circuit.  Figure 3 - 1 Unbalanced current commutating mixer  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  27  3.1.1.1. Conversion Gain To find the conversion gain of the unbalanced current-commutating mixer shown in Figure 3-1, Let us assume Figure 3-2 as its simplified model. In this figure, Gm-stage is modeled by a current source and LO-stage is modeled by an ideal switch.  Figure 3 - 2 Simplified model for unbalanced current commutating mixer  We can write VIF and CG as follow:    2  ⋯  3  ⋯ 				 3  1  																																																																																																						 3  2  1 2   | |  | |    2  2 3  The above procedure is suitable for understanding the method for calculating the conversion gain. To have a more precise calculation, let us assume input impudence of transconductance-stage and non-ideal switching as represented in Figure 3-3.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  28  Figure 3 - 3 for unbalanced current commutating mixer with considering nonideal switch and input impedance of transconductance stage  In this case, we can write VIF and CG as follows:    .  .    .  .  .  .  .  .  .  | |  where  | |    .  .  .  2 .  1 2  2    ≪  ⋯ ⋯ 		 3  3  																														 3  4  is voltage transfer coefficient form matching network to transconductance-  stage (Gate of M2 in Figure 3-1).  can be ideally one for non-resonance matching  networks, or higher than one for resonance matching. However in resistive matching is less than one. Also  is switching time which can be function of bias (region of  operation), LO power, and transistor sizes in switching stage.     ,  ,    																																																																																												 3  5  Equation 3 – 4 reveals two important points. First it is necessary to have a proper matching network with maximum voltage transferability, and second LO power should be high enough to have the lowest  in a certain bias and transistor size.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  29  3.1.1.2. Systematic Isolation Systematic port isolation (ignoring coupling caps) can be given from equation 3 – 3 and can be written as fallow: . .  .  . .  2 2  .  .  .  .  1 2  2  ⋯  																																																																																 3  6  																																																																			 3  7  .  Therefore, as shown in 3-7 VLO-IF can be decreased by controlling bias current, however we should take in mind that this will be in cost of lower Gm and conversion gain respectively. 3.1.1.3. Headroom and Supply Voltage Constraints Equation 3 – 4 for the conversion-gain in unbalanced mixers can be misleading! Based on this equation, the conversion gain can be increased linearly by increasing the transconductance stage as well as load resistance in a physical design as both  	and  of the  . However, this may not be practical  are limited by the headroom constraints and  supply voltage. Therefore, it is very insightful to write the CG in terms of headroom. To do this, consider a typical unbalanced mixer of Figure 3 - 4. Our goal is to find the minimum required supply voltage for which the circuit operates in a correct operating point. In general, the transconductance stage should be biased in the saturation region and the value of  remain in saturation, the voltage of node X should be at least and  	 to  should be selected based on linearity constraints of system. For .    	are also operating in saturation, however for a good switching performance they  need to be biased close to triode. Assuming that the common-mode voltage of the switching stage is  	 and to have a complete current switching between each branch, we  need a differential voltage change of ∆  for each  	 and  . Then, the minimum  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES voltage of node Y becomes  ∆  ,  30  . Considering  , the  maximum DC current of each branch can be calculated as:  ∆  ,       ∆  ,  																																							 3    8  Figure 3 - 4 Required voltage for turning switching stage ON and OFF  To further simplify the last equation, ∆  can be written as a portion of overdrive  voltage [25]. ∆  √    ∆  √    ,  ,  																																																										 3  Substituting (3 – 8) to (3 – 9) and considering that  2  9  , maximum  bias current can be found as : √  2 Or maximum load can be:    (3 – 10)  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  1 2   31  √2 2    2  																																																																									 3	– 	11    Substituting (3 – 11) in (3 – 4), new form of conversion gain can be written:  .   . .  . .  	.  4    ≪  			 	3  12  As can be seen from (3 – 12), CG in this type of mixer can be quite sensitive to supply voltage, hence operating from a low supply voltage requires special measures.  3.1.1.4. Effect of Parasitics on the Gain Parasitic capacitances and resistances can severely impact the performance of CMOS mixers, especially the conversion gain. Although Equation 3 – 4 considers the effects of input parasitics through the (  term for the RF stage and  term for LO stage  can be increased by parasitics), it does not take into account interconnection  parasitics, especially those between Gm-stage and LO-stage. To see their effect, consider Figure 3 – 5. Total parasitic capacitances at node X are represented by CT which includes wire, gate-to-source, drain-to-body, and source-to-body capacitances. CT creates frequency dependent impedance at node X hence RF current generated by Gm-stage will be divided between CT and source terminals of the LO stage.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  32  Figure 3 - 5 Effect of parasitic capacitances in available RF current  In an ideal case it is desired that all RF current goes into switching stage and dissipated current , IRF-D becomes zero, but based on equation 3 – 13 as frequency increases current in CT goes higher and hence available current, IRF-A , and CG decrease. 1 ≅  1  1    1  1   1    |  1  |  |  |  				 3  13  																															 3  14  Considering (3 – 13), (3 – 12), and (3 – 4) CG can be written as:   .  	 .  .  .  Or in terms of available headroom : .  .  .  	.  	 				 	3  15  We conclude this type of mixer by equations (3 – 14) and (3 – 15). The first parantez adds effect of input matching and Gm-stage input parasitic. Second parantez shows effect of nonideal switching which can be resulted by LO-stage parasitics and size of switches.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  33  Third parantez considers internal parasitics. And last parantez is for theoretical CG yields from the ideal model. 3.1.2.  Single-Balanced Current-Commutating Mixer:  For improving the gain and isolation in the unbalanced active mixers, a single-balanced architecture can be considered as shown in Figure 3 – 6. As can be seen in this type of mixers, the switching stage and the output are differential. This differential structure results in cancelling DC component of the switching stage and hence improves the RF-IF isolation. Also, as the output is differential, typically the conversion gain is doubled that of a single-ended output.  Figure 3 - 6 Conventional single balanced mixer  3.1.2.1. Conversion Gain Similar to an unbalanced circuit, the conversion gain can be found by multiplying RF current and the equation that models the switch. Figure 3 – 7 shows this multiplication graphically. As can be seen the switching-stage model is balanced and without any DC value. Also, in terms of input matching and parasitic this single-balanced method is same as unbalanced structure.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  34  Figure 3 - 7 Simplified model for finding conversion gain  2   2  2 8 3  4   | |  | |    2  3  ⋯  3  ⋯ 												 3  16  																																																																																																			 3  17  Similar to equation 3 – 14 effect of parasitics, input matching network, and nonideal switching can be added as follow:   .  	 .  .  																															 3  3.1.2.2. Systematic Isolation Systematic port isolation can be defined from equation 3 – 16: 4 4   .  .  .  .  ⋯   18  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  35  0 As predicted RF-IF isolation is completely suppressed in single balanced mixer. 3.1.2.3. Headroom and Supply Voltage Constraint Same as unbalanced procedure and equations 3 – 8 and 3 – 15 for finding maximum achievable conversion gain we can write: .  3.1.3.  .  .    	 			 	3  19  Double-Balanced Current-Commutating Mixer  If the RF is available in differential format, we can benefit from a double-balanced architecture. Technically, the double-balanced mixer is composed of two single-balanced mixers as shown in Figure 3 – 8. As will be shown, compared to a single-balanced structure, the CG will be doubled, and the  component will be canceled at the output.  However, this improvement does not come for free and it is at the cost of higher power consumption and lower headroom.  Figure 3 - 8 Conventional double-balanced mixer  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  36  3.1.3.1. Conversion Gain To find the conversion gain of a double-balanced mixer, consider node X in Figure 3 – 9. To find the voltage at node X, let us first find Iout1. To do that, I1 and I2 should be added up together, however, based on the value of the LO each of those currents is nonzero in half a LO clock cycle and zero in the other half cycle. In other words, I out1 is equal to IDC+I+RF in half of the LO period and changes to IDC+I-RF in the other half of the period. As I+RF and I-RF are 180 degrees out of phase with respect to each other, we can equivalently say that I  out1  = IDC+ I+RF×S′(t) where S′(t) is a fully balanced pulse train  which has the same frequency as LO. Thus, the voltage of node X, which is RL times this current, becomes exactly the same as that of a single-balanced mixer output. Note that in single-balanced mixers, the differential output has this shape and here single-ended signal is considered. With the same approach I out2 = IDC+I-RF×S′(t) and hence for differential output can be written as : ′   2  .  . ′  2   .  ′ .  4  ′  ′ ⋯ 				 3  20  And hence CG can be written as: | |  | |    4  																																																																																																		 3  21  Similar to equation 3 – 14 effect of parasitics, input matching network, and nonideal switching can be added as follow:   .  	 .  .  																															 3  22  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  37  Figure 3 - 9 Model of double-balanced mixer for finding conversion gain  3.1.3.2. Systematic Isolation From equation 3 – 20 it can be seen that systematic RF and LO leakage to IF is zero. However we should take into account that in a real design due to parasitic capacitances between Gm-stage to LO-stage and LO-stage to IF-stage port leakage is inevitable. 2  4  ⋯  0 0  Figure 3 – 10 shows IF voltage at output of unbalanced, single-balanced and doublebalanced mixers. As can be seen choosing a correct architecture can significantly improves isolation and quality of IF signal .  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  38  Figure 3 - 10 Effect of mixing architecture in port isolation for a) unbalanced b) single balanced c) doublebalanced  3.1.3.3. Headroom and Supply Voltage Constraints Effect of supply voltage in conversion gain of double-balanced mixer presented in Figure 3 – 9 is same as unbalanced and single balanced as number of stack transistors are equal however this mixer is not practical and in most cases circuit bias is being provided by a current source as shown in Figure 3 – 11. Assuming  as the minimum possible voltage  at node X which grantees that current source remains in saturation, maximum achievable CG can be written as: .  .  .    16  	 						 	3  23  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  39  Figure 3 – 11 Conventional double-balanced mixer with current source. 4 stages of stacked transistor and resistive load make it difficult to reach high conversion gain while having low supply voltage  3.1.4. Linearity in Conventional Active Mixers To study linearity in the conventional active mixers, we assume two different configurations, a single transistor and a differential pair, and will calculate the ratio of the first term (first harmonic) of the signal to the first nonlinear term (e.g., 2nd harmonic). For a single-transistor amplifier consider Figure 3 – 12 where Vm is the amplitude of the small-signal input source and VGS is the bias voltage, for this transistor we can write : V  I  R  K    K  W L  V  W L  V  V  V  V Sin ωt  V Sin ωt  V Sin ωt  2V Sin ωt V  V    Hence, by finding the amplitude of the second harmonic, we have:  A A  V 4 V  V    																																																																											 3  24  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  40  Figure 3 - 11 Single-transistor amplifier  Secondly, for a differential pair consider Figure 3 – 13. ΔI and output differential voltage can be easily found as:  ∆I  I    2K  2K  I  K  W V L  4I K  W Vm Sin ωt V L  W L  V  V  V Sin ωt  1  V  K  Vm Sin ωt  8 V  W V L  4 V  V  V Sin ωt  2  V  Vm Sin ωt  Vm Sin ωt  8 V  V  Hence by finding the amplitude of the third-harmonic, we have:  A A  Vm 2  32 V  V    																																																																																	 3  Figure 3 - 12 Differential amplifier  25  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  41  Equations 3 – 24 and 3 – 25 reveal two things. First linearity can be improved by increasing VGS of transistors. However as mentioned we should take into account that increasing VGS will be limited by headroom and it will require higher power consumption. Secondly, by comparing two equations we can see that differential pair has high capability to suppress nonlinear terms as its second harmonic is zero and third harmonic is suppressed by square power of overdrive voltage.  3.1.5. Power Consumption in Conventional Active Mixers Power consumption in congenital active mixers can be studied in two ways. First in all architectures for biasing Gm-stage and LO-stage a DC bias current is required, this contributes in DC power consumptions. To classify these types of mixers we call them as class A active mixers. Increasing current in class A CMOS mixers results in: 1. Improving linearity 2. Increasing DC power 3. Reducing headroom 4. Increasing Gain (as long as transistors remain in correct operating points) 5. Improving NF To make the best of this trade-off, DC current versus Mixer’s FoM (equation 2 – 8) can be plotted in different load resistances. To have better understanding Figure 3 – 14 shows intuitive change in FoM by increasing current. As can be seen there is an optimum point for FoM and this point can be shifted to lower DC currents by having a larger load resistance. By further studying, this can be found that IDC×RL have a very same values in optimum points. In other world by increasing load resistance (increasing size), IDC should decrease to remain in correct operating point and constant gain (headroom constraints). In addition, reducing IDC will cause in lower power consumption but worsen linearity and lower IIP3, hence as a result of this trade-off it is expected that FoMMax remains in same level.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  42  RL1>RL2>RL3 IDC1×RL1≈IDC2×RL2≈IDC3×RL3 FoM  From Low load  Resistance to High  load Resistor RL3  RL2  RL1  IDC3 IDC2 IDC1  IDC  Figure 3 - 13 FoM versus DC current and different load resistors  Secondly, considering unbalanced, single-balanced, and double-balanced structures, double-balanced has the best conversion gain in constant current consumption. To prove that lets assume DC current in an unbalanced architecture is IDC-Ref, then as mentioned conversion gain in each architecture can be written as:  ∝  ∝    ∝  2  2  4  4  2  Hence theoretically and in constant power consumption, conversion gain of doublebalanced mixer can be  √  times higher than unbalanced and  √  times higher than single  balanced.  3.2. IMPROVED ACTIVE CMOS MIXER In this section, we will briefly study different design techniques to improve figure of merits in CMOS active mixers. The main focus of this part is on presenting techniques  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  43  for reducing the power consumption, lowering the supply voltage and boosting the linearity of the circuit. 3.2.1.  Design Techniques for Voltage Headroom and Power Improvement:  From presented conventional mixers, one can observe a close correlation between the conversion gain, the bias current, and the voltage headroom. In summary, for improving conversion gain, linearity, and noise figure, Gm-stage should be biased in the stronginversion region with a high bias current. However, having a high bias current is in contrast with headroom constraints due to the use of a resistive load at the output. In this part, we present design techniques to increase the bias current independent from the headroom limitations. 3.2.1.1. Transconductance Current Bleeding Gm Booster Figures 3 – 15 and 3 – 16 show conventional single-balanced mixer and improved current bleeding single-balanced. The idea of current bleeding is also known as current steering or charge injection. By this technique DC current of Gm-stage can be increased independently from load DC current and hence it results in higher transconductance and conversion gain respectively. As mentioned IIP3 has relation to square root of overdrive voltage at Gm-stage, so by current bleeding IIP3 can be improved as well.  Figure 3 - 15 Conventional Single-Balanced Mixer  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  44  Figure 3 - 14 Improved mixer with current bleeding technique  However, current bleeding is higher sensitive to frequency than conventional mixer as it is adding more capacitance at intercept node (node X in Figure 3 – 16). Modifying equation 3 – 18, conversion gain can be written as:    .  	 .  2  .  										 3  26  where CB is parasitic capacitor added at node X due to bleeding circuitry. In constant load current, CG ratio of conventional and modified version with bleeding technique can be defined as improve factor and can be written as:     .  .  1 .    . √  1 								 3  27  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  45  Figure 3 - 15 Adding current bleeding causes to have worsen frequency response  3.2.1.2. Current Bleeding with Inductive Decoupling To cancel the effect of  and noise of the bleeding circuitry, an inductor can be  used in the path of bleeding current. This inductor has a zero DC value and can be tuned to resonate with parasitic capacitances at node X. To make the node Y a virtual ground at high frequency, a large capacitance can be put at node Y. This capacitance will have two major roles; first, it stabilizes the DC voltage of node X. Second, in the frequency range of interest it becomes shorted to ground, making the inductor in parallel with the parasitic capacitor  and hence results in a parallel resonance (open circuit) between  and  .  The main trade-off here takes place between a higher transconductance, NF, and area.  Figure 3 - 16 Current bleeding with improved frequency response. LB in intended to resonance with CT and C is large enough to short node Y in frequency of interest  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  46  3.2.1.3. Current Bleeding with Gm Double Booster Figure 3 – 19 presents another interesting technique which can boost transconductance of mixer. This technique is known as modified current bleeding or current-reusing. The idea behind this method is that M2 can also contribute in small signal analysis and can generate additional transconductance, gm2. gm2 then will be added with main transconductance, gm1, and then being switched in LO-stage. As a result total transconductance boosts to gm1+ gm2. Same as previous section, improvement factor can be written as:   .  	 .  .  2  									 3  28       .  .    																																																																				 3  Figure 3 - 17 Current reusing technique for improving headroom and transconductance  29  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  47  As will be discussed, in addition to current bleeding and Gm boosting, this technique results in improving linearity and higher IIP3. However, since bleeding transistor contributes in transconductance, it is not possible to cancel parasitic capacitances at intercept point by inductor (Node X), so special design attention, such as choosing a proper size for bleeding transistor, should be paid for high frequency application.  3.2.1.4. Load Current Bleeding Headroom Booster: Another similar approach to suck some current out of the load path is to put a bleeding circuitry at the output as shown in Figure 3 – 20. As a result, the load resistor can have higher value which results in a higher gain. However, as discussed in [26], MB will have significant impact on NF and it can be written as:   ,      ,  	4  		 2    	4  1  2  	4  																																																						 3  30  1 																																																																																				 3  31  Figure 3 - 20 Relaxing load current by an auxiliary current source  Another drawback is linearity degradation. Since IF amplitude is around 20dB larger than RF signal, this can result in high channel length modulation of MB and consequently  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  48  adding nonlinear components. In addition, due to increasing headroom, MB is biased at the edge of its saturation region so having a large IF signal can change the region to triode and adding nonlinearity respectively.  3.2.1.5. Stack Reduction Approach - Folded Mixer Another effective way to increase voltage headroom is reducing number of stacked transistors. As shown, in conventional approaches supply voltage is being shared between 3 to 4 stages of transistors and load. The idea of stack reduction is to share supply voltage with smaller stages. Figure 3 – 21 shows basic idea of stack reduction. A) Conventional Active Mixing  B) Two Different Stacked reduction Techniques  VDD  VDD RL RL  Load  IF  IBias-Gm  IF  Load LO  LO  RF  LO  LO  Gm  Combined  Gm-LO-Stage  Switching Stage  IBias RF  Gm  IBias-Gm Gm-Stage  VDD  VDD  Gm  RF Gm-Stage  IBias-Switch  LO  LO  Switching Stage RL  IF  Load  Figure 3 - 18 Stack reduction approach, A) conventional mixing B) two different stacked reduction techniques, folded and body injecting mixer are two examples of top and bottom architectures  To get an idea how to reduce number of stacked transistors, assume folded mixer in Figure 3 – 22. In this method with folding switching-stage and using PMOS transistors instead of NMOS, supply voltage can be applied at intercept point. Based on desired transconductance in Gm-stage, bias current, R1, and R2 can be selected.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  49  Figure 3 - 19 Mixer with folded switching stage  This question can be raised that why we don’t put zero value for R1 and R2 as in ideal case we want to maximize voltage of node X. To answer this question Let us assume conversion gain of presented folded mixer. Figure 3 – 23 shows small signal of this mixer, for first approximation of conversion gain we can write:  Figure 3 - 20 Small signal equivalent of folded mixer    .  	.  | |  1||  1|| 1  1  | 1  |  																																																																																																	 3  Hence conversion gain can be written as:  32  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES    Or if  .  	 .  .  .  	 .  .  | |  1  1||  1||  |  1  1  2  .  |  50  		 3  33  																								 3  34  ≪1:    1  .  1  1  2  Equation 3 – 33 shows that higher R1 results in higher conversion gain. We should keep in mind that by increasing R1 we will face with headroom problem. So in order to increase R1 without impacting voltage headroom, bias current of Gm-stage can be lowered, however as mentioned before this will in cost of scarifying linearity in Gm-stage. In next section we will show one solution to solve mentioned challenge. 3.2.1.6. Stack Reduction Approach – Folded with Choke Biasing Figure 3 – 24 shows folded technique with inductive biasing. This idea can be interesting in two ways. First and foremost, since inductor impedance can be represented as  , at  DC, voltage of node X is always VDD, this helps Gm-stage and switching-stage to operate in desired region and as a result supply voltage can be reduced significantly. Modifying equation 3 – 33 conversion gain can be written as:   Or if  .  	 .  |  .  |  || ||  1  1  | 1  .  |  2  				 3  35  ≪1:    .  	 .  .  . 1  2  								 3  36  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES VDD  This part can be very bulky  and it may be implemented  off-chip   L1  L2  51  CT  X  VRF,+  VRF,-  CT  VLO,VLO,+ Vbias  VLO,+ IF-  IF+ RL  RL  Mixer Core  Figure 3 - 21 Folded mixer with inductor biasing  Let us assume that for alleviating effect of current diving between inductor and choose inductor in a way that  ≫  , we  at frequency of interest. For example we can  consider: 1  ≫ Assume  10      10 																																																											 	3 .  37  is around 1mA/V in low power application and frequency of interest is 2.5  GHz, from 3 – 34 calculated inductor is around 63nH!! This value is way off from practical on-chip applications hence for implementing that we need a bulky off-chip RF chokes. However if we increase frequency from 2.5GHz to 60GHz inductor can be chosen as low as 2.5nH. To avoid using large inductors in low frequencies, hybrid approach can be presented where a series resistor is being added to inductor as in Figure 3 – 25. In this method we change 3 – 35 to:    Or if  .  	 .  .  	 .  |  .  |  1  1 ||  |  1  1 ||  1  |  .  2  	 3  38  				 3  39  ≪1:    1  . 1  . 1  2  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  52  From 3 – 39, R1 can be chosen based on practical value of on-chip inductor, we should keep in mind that in this case our trade-off is between area and voltage headroom.  Figure 3 - 22 Folded mixer for with RL biasing. This method is suitable for wide band applications  Secondly, from 3 – 36 another very important feature can be understood which is very important for wide band applications. L in this equation can be chosen to make resonance with CT at frequency of interest, then effect of parasitic cap at intercept point will be canceled and in resonance frequency CG can be written as:    Where  .  	 .  1  .  .  2  																													 3  40  is equivalent parallel resistor of LC filter and can be calculated by Q factor.  CG  Resonance peaking  F  Figure 3 - 23 Conversion gain versus frequency for hybrid folded mixer  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  53  3.2.1.7. Stacked Reduction Approach – Body Injecting Mixer Another way to reduce number of stacked transistors is utilizing from body terminal as shown in Figure 3 – 27. We know that in a typical NMOS transistor threshold voltage can be written as: 2  2  																																																																	 3  41  And ID can be written as: 2  2  						 3  42  																																																																																														 3  43  By writing Taylor series of 3 – 42, first estimation for CG can be written as:  4  2  Although with this technique supply voltage can be reduced significantly and it can reduce amount of parasitics (better frequency response), gain and NF can be very low due to high dependence of CG to LO power, Vs, and  . Moreover, if body injecting is being  performed through NMOS transistor, process should support triple well NMOS devices.  Figure 3 - 24 Body-injection mixer  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES 3.2.2.  54  Design Techniques for Linearity Improvement:  As discussed linearity in transistors is proportion to bias current and overdrive voltage. So in order to have higher linear transistor higher current or equally higher power consumption is required. In this section two alternate solutions are presented to have comparably higher linearity while consuming lower power. 3.2.2.1. Derivative Superposition (DS) Technique Derivative Superposition Technique or DS method is a very popular method for increasing linearity in any RF block, including LNA, Mixer, and PA. This technique is around since 1996 [27]. Here we briefly explain this technique. Consider a common-source NMOS which is biased in saturation. In small signal analysis, output current can be modeled as:  ,  ,  Where , calculated as :   ,  ,  	,  ,  ⋯																																																			 3  44  	are first , second and third order transconductance and can be    1 2  	,  1  6  																																							 3  45  Considering 3 – 44, IIP3 can be found as: 3    4 | 3  |																																																																																																									 3  Figure 3 – 28 shows  ,  , and  46  for a typical NMOS. From this figure it can be  understood why by increasing over drive voltage in MOSFET linearity improves. In other words, as we increase transistor’s bias,  gets smaller value and ideally in point X,  is zero. However, reaching this point required high current. In addition to high power consumption,  has only one zero crossing which makes this point very  sensitive to process variation and amplitude of input signal.  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  55  Figure 3 - 25 Figure of gm1, gm2 , and gm3 for a typical NMOS transistor  As an alternate solution, in DS technique we use number of transistors (minimum of two) to flatten zero crossing region in  curve. To make it more clear, if transistor , M1, is  biased in a region where it has positive a different bias to provide negative ,  , another transistor can be employed with  , ,  . Then by adding  ,  to  ,  ,total  can be very close to zero in a wide range and hence IIP3 can improve  significantly. Figure 3 – 29 shows a simple configuration for implementing DS method with two transistors, here Voff is used to make a shift in VGS and Figure 3 – 30 shows  ,  ,  ,  , and  ,  ,  respectively.  .  Figure 3 - 26 A) General DS method concept B) Implementation of DC method with two stages, M1 is biased in strong inversion and M2 is operating in weak inversion  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  56  Figure 3 - 30 As shown gm3, M1+M2 is zero in a voltage wider range  Figure 3 – 31 shows a double-balanced conventional mixer that uses the DS method. Based on simulation results, with this technique linearity can be improved as high as 7 dBm while consuming same power consumption. Reason why power consumption remains same is that sweet spot for gm3 is when M1 operates in strong inversion and M2 in weak inversion; as a result M2 current does not contribute significantly total current.  Figure 3 - 27 Improved conventional double-balanced mixer by applying DS technique in transconductance-stage  CHAPTER 3. ACTIVE DOWN-CONVERSION CMOS MIXER ARCHITECTURES  57  Figure 3 - 28 IIP3 simulation for mixer of Figure 3 – 30 with and without DS method. In both case power consumption is in range of 2.5-2.7 watts.  3.2.3. Conclusion and Outline of the Next Chapter Conventional active mixers and their bottlenecks in low power and low voltage applications discussed. To improve conventional mixers different effective design techniques such as current bleeding, stacked reduction, and derivative superposition were proposed. In next chapter first we bring measurement results of two different CMOS mixers, one with a conventional architecture and the other after applying improved techniques. Bottlenecks of each design will be briefly discussed and a new class of CMOS active mixers suitable for low power applications will be proposed.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  Chapter 4.  58  PROPOSED TECHNIQUES FOR A HIGHLY  EFFICIENT MIXER In Chapter 3, we briefly discussed about the conventional CMOS mixers and some improvement techniques. In conventional double-balanced current commutating mixer we saw that supply voltage should be high enough to bias four stages of stacked transistors and load in a correct operating point. To have more practical insight, in a standard CMOS process which provides an NMOS transistor with threshold of around 0.4 V, supply voltage should be at least 1.2V. In this case we assumed a minimum of 0.3V voltage drop for each stage (0.3V overdrive voltage for transistors and 0.3 voltage drop across resistive load). These values can be very matched with a standard 0.13µm process which supports up to 1.2V breakdown voltage. However as technology advances breakdown voltage drops significantly and hence implementing conventional methods become severely hard. In addition to breakdown issue, DC power consumption which yields from  .  cannot be lowered from a certain level. To have a practical  guess about this minimum level, a double-balanced conventional down-conversion mixer as shown in Figures 4 – 1 and 4 – 2 is designed, optimised at 2.5 GHz, and implemented in a standard 0.13µm process. To increase linearity and save headroom inductor LS is used in source of transconductance-stage. Also this inductor is being used to facilitate input matching at frequency of interest. LR is responsible to resonate with gate capacitance of switching-stage at LO frequency to provide some passive amplification; this resonance can reduce required PLO significantly. In this design Gm-stage transistors are biased close to strong inversion and switching transistors are in moderate region. RL is optimised for having a maximum conversion gain and CL is for capturing IF signal at 50 MHz. Finally, the common-drain buffer is used for measurement purposes and it can drive 50 Ω external load (input impedance of measurement devices). Table 4 – 1 shows the measurement results of this mixer.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  59  Figure 4 - 1 Implemented double-double-balanced mixer in 0.13µm  Figure 4 - 2 Layout and chip prototype of a conventional double-balanced mixer. Measurement setup is shown in appendix – 2 Table 4 - 1 Performance of implemented conventional mixer  VDD(V) PLO(dBm) NF(dB) CG(dB) IIP3(dBm) PDC(mW) RF(GHz) IF (MHz)  Case 1 1.2 -12 8.3 13.8 -9 2.8 2.4 50  Case 2 1 -10 10 10.2 -11.4 2.1 2.4 50  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  60  As can be seen from table 4 – 1 maximum conversion gain is achievable with 2.7mW power consumption. This power consumption was quiet predictable with considering mentioned 0.3V maximum voltage drop across load resistor. Considering RL to be chosen around 100-300Ω, predictable power consumption will be in range of 7.2mW to 2.4mW, or more generally power consumption is mW level. In this chapter different design techniques is proposed to achieve µW level power consumption in CMOS mixers while maintaining a high performance. 4.1.1.  Proposed Design Techniques for Low Power Consumption:  Considering simple equation of DC power consumption  for class A  active mixers, we have two possible ways to reduce power in circuits. First by lowering DC current and second by reducing supply voltage, as mentioned both of which have bottlenecks and can impact performance of mixer. Below first we propose different design techniques to reach comparably lower supply and bias current and will introduce a new class of active mixers which have dominant dynamic power consumption. As will be shown this methodology can reach power consumptions in range of 50-300 µW and supply voltage of as low as technology threshold voltage, while maintaining a very high performance. 4.1.1.1. Weak Inversion and Subthreshold Operation Main challenge in any Analog and RF block is to provide required gm. Almost all figures of merit in any Analog block are directly or indirectly correlated with generated gm. So it is always desired to have comparably higher gm while consuming lesser power. Subthreshold and weak inversion circuit design has been used for many years as a strong tool in reducing power consumption. Figure 4 – 3 shows variation of drain current of a typical MOSFET versus Gate-Source voltage. As can be seen, despite the conventional MOSFET current equation1 which recommends a square relation between current and voltage, in subthreshold and weak inversion current is not zero and interestingly IDS-VGS chart provides a same slope as superthreshold. Having a same slope means transistor can provide a same gm with comparably much lower power consumption. Reason behind this  1  Conventional MOSFET equation :  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  61  behaviour is that in subthreshold, charge transport mechanism is more due to diffusion that drift and hence it has exponential relation with Gate-Source voltage and hence it provides a high slope. For achieving high transconductance efficiency1, weak inversion circuit biasing has been used for years in low frequency Analog blocks [28]. However, in higher frequencies RF applications it was not a proper solution since lowering current impacts transistor’s fT significantly. It is been a few years that with advancing technology and continues improvement in fTs of transistors, operating in subthreshold and weak inversion has become quite possible for designing RF blocks in VHF, UHF and SHF bands.  Subthreshold Diffusion Current  Large transistor  IDS  Small transistor IDS α (VGS)2  IDS IDS α EXP(VGS)  Superthreshold Drift Current Vth  VGS  Figure 4 - 3 Drain current versus Gate-Source voltage behavior in subthreshold and superthreshold  To monitor relative channel inversion independently from transistor size, Inversion Coefficient (IC) can be defended as function of transistor process parameters and operating point:  2  1  																																																																																																		 	4  1  Transcendence efficiency is the ratio of generated transconductance to required bias current (  )  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER Where n is subthreshold slope factor,  62  and Id is drain current. Figure 4 – 4 and 4  – 5 show transconductance efficiency and fT of a MOSFET in a standard 0.13 process. To achieve high transconductance efficiency Figure 4 – 4 recommends operation in low inversion coefficients. However, as can be seen from 4 – 5 by reducing channel inversion (operating in subthreshold) we are significantly being limited by transistor’s fT.  Figure 4 - 4 Transconductance efficiency versus inversion coefficient  Figure 4 - 5 Transistor’s fT versus inversion coefficient  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  63  To find a sweat-spot to get a maximum benefit from high transconductance efficiency and a minimum impact from the transistor’s fT, a new figure-of-merit (FoM) can be defined for transistors, namely,: .  																																																																															 	4  2  Figure 4 – 6 shows this FOM versus IC for a typical NMOS in a 0.13 process.  Figure 4 - 6 FOM of NMOS transistor versus inversion coefficient  As can be seen from 4 – 6, the optimum bias point for a transistor is when it is biased in IC of around 7, where the transistor is operating in moderate inversion. Throughout the rest of the next mixer designs we have applied this technique and in order to get lowest possible supply voltage and high transconductance efficiency Gm-stage is biased in moderate to weak inversion regions. To study possibility of subthreshold technique in RF mixers, a 2.4 GHz double-balanced mixer with Gm-booster current bleeding headroom helper (See 3.2.1.3) is designed and implemented in a standard 0.13-µm CMOS process. Figure 4 – 7 shows circuit and chip prototype of proposed mixer.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  64  Figure 4 - 7 Proposed double-balanced current bleeding mixer operating in subthreshold, measurement setup is shown in appendix – 2  Here transconductance stage has optimized to operate in subthreshold. Since in subthreshold bias current is comparably much lower than strong-inversion (2-3 times lower), load resistor can be chosen 1.5 to 2 order higher. In other worlds, one advantage of subthreshold mixer design is that not only we can achieve same CG with lower power consumption but also we can boost CG by increasing load resistor.Practically as mentioned in strong-inversion operation, RL is in range of 100-300Ω, and in subthreshold it can be increased to 1- 4KΩ. Table 4 – 2 shows performance of implemented mixer. Table 4 - 2 Performance of implemented current bleeding mixer  Case 1 : Case 2 : Case 3 : Case 4 : Sub Super Sub Super Threshold Threshold Threshold Threshold 0.7 0.8 1 1.2 VDD(V) 0.35 0.40 0.47 0.5 VBN(V) 0.35 0.4 0.5 0.6 VBP(V) -5.5 -6 -5 -5.6 PLO(dBm) 10.7 9.2 9.5 9.3 NF(dB) 18.2 19.01 21 24.7 CG(dB) -8.7 -7.54 -5.4 -3.5 IIP3(dBm) 0.78 0.95 2.1 4 PDC(mW) 2.5 2.5 2.5 2.5 RF(GHz) 50 50 50 50 IF(MHz)  Comparing with table 4 – 1, power consumption dropped from 2.8mW to 800µW while having 8 dB higher conversion gain. Also Supply voltage is reduced from 1.2V to 0.8V.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  65  To conclude this part, we showed that bias current can be reduced by operating in weakinversion, however as mentioned special attention should be paid for transistor’s fT. Also by operating in subthreshold, in a same supply voltage, load resistor can be chosen higher to boost conversion gain, or equally in a same conversion gain, supply voltage can be reduced to have lower power consumption.  4.1.1.2. Stacked Reduction and Sleep-Mode Techniques Digital CMOS systems are very interesting in power consumption point of view. They have almost zero DC power consumption and main power is switching power also known as dynamic power. Also it is interesting that we can easily turn-off a section of circuit when it is not necessary to operate, this can significantly reduce power consumption. Inspiring from these two simple concepts and the fact that we exactly need switching in RF mixers, a new mixing methodology suitable for low power consumption can be proposed as shown Figure 4 – 8. Based on LO value, each Gm-stage is being waked up in half a LO period, pumps RF signal to load resistor and being shut down in another half. Comparing to conventional active mixers which Gm-stage has constant bias current, as will be shown in most cases this technique does not require any DC bias in Gm-stage and it is expected that the main power consumption takes happen in switching stage which is dynamic power.  Figure 4 - 8 Proposed low power switching. (a) Unbalanced architecture. (b) Double-balanced version.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  66  To find conversion gain of proposed mixer, consider unbalanced mixer in Figure 4 – 8 – a. The Gm(t) created in transconductance stage is dependent on LO value and state of switches. When Gm-stage is off Gm(t) is zero and when Gm-stage is on Gm(t) starts to rise to reach its maximum value. Figure 4 – 9 shows gm versus time for this mixer.  Figure 4 - 9 Transconductance of proposed unbalanced-mixer versus time  To find output voltage and conversion gain easily we can write:       .  Where Si is Fourier coefficient of gain we have:  0  1  2  2  ⋯ 			 4  2  . Hence for the first approximation of conversion  1.  																																																																																							 4  3  If we consider matching network in RF stage CG can be written as:    .  	 .  .  																																																															 4  4  Comparing 4 – 4 with equation 3 – 14 we can see that both equations are same except in one important term and that is  which cares about intercept parasitics in  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  67  conventional mixer, however in recent presented mixer this term shows itself in rise and fall times of gm(t) (  in equation 4 – 4 ) . In addition to that parasitic capacitances at  node X can be beneficial and act as low pass filter for extracting IF signal. In terms of power consumption, we should note that in comparison with Figure 3 – 5 for conventional unbalanced-mixer which wastes current in half a clock cycle, here we can save it by turning of the whole Gm-stage. We call this type of mixer as class B active mixers. In addition to power consumption improvement which can be theoretically half of that of the conventional mixer, as shown in Figure 4 – 10 LO-IF port isolation due to parasitics and coupling (note that this is different from systematic isolation) improves. This is because of the fact that here large swing LO signal is being isolated from IF-stage by GmStage, however this can be asked that it is in cost of scarifying RF-IF isolation. Although this claim is true, we should keep in mind that LO signal is much larger than RF signal hence improving LO-IF isolation has higher priority than RF-IF isolation.  Figure 4 - 10 Gm-stage acts as a buffer to isolate LO from IF  Another benefit of this type of mixer is that by choosing a proper switching-stage, number of stacked transistors can reduce significantly. For example consider a case same as Figure 4 – 11 in which switching-stage is implemented by a simple inverter, these inverters are toggling node X and Y to VDD and GND with LO frequency and cause Gmstage to turn on and off. Since inverters have their own supply terminal, they can be  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  68  optimised and perform almost independent from Gm-stage. As will be mentioned in next section, for full swing operation of these inverters it is quite possible to reduce supply voltage to as low as threshold voltage of transistors.  Figure 4 - 11 Implementation of switching stage with inverter  Considering Figure 4-11, and the fact that Gm-stage is well independent from LO-stage, power consumption can be written as:       																								 4  5  And with taking into account that DC power consumption in a CMOS inverter can be negligible and Gm-stage consumes only static power we have:     	 .  . .    	.  										 4  6  Equation 4 – 6 reveals that in contrast with conventional mixers, this type of mixers consumes dynamic power and hence in order to reduce power in a certain frequency we should have higher attention to switching capacitance as well as supply voltage. In next section we propose a technique for achieving a low supply voltage in inverters.  4.1.1.3. Dynamic Threshold MOS for Ultra-Low-Voltage Inverter For fast switching a PMOS or NMOS transistor in an inverter input voltage should be high enough to overcome the threshold voltage. Equally for an inverter to operate in low voltage supply and low input swing, it is required for the PMOS transistor to have low threshold voltage when input signal is low, and NMOS transistors to have low  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  69  threshold voltage when input signal is high. In other words, when PMOS transistor gets on and output signal starts rising to VDD, NMOS transistor should be prepared to toggle back output to GND and vice versa. This preparation can be facilitated by temporarily threshold adjustment of NMOS transistor. Dynamic threshold is one popular way for doing that, similar to the approach proposed in [29]. In dynamic threshold approach body effect is used for adjusting threshold of transistors. Threshold voltage of a typical NMOS and PMOS transistor can be expressed as:   2∅    2∅  2∅ 2∅  																																																																 4  7  Figure 4 – 12 shows threshold voltage of a NMOS device versus its VBS voltage in a 0.13µm process. The point where VBS equals to threshold can be considered as the minimum possible supply voltage which is required to change state of NMOS from off to on, we call this point as VDD-min. However for applications in which input is a high frequency signal, we should take into account that for providing a good rise and fall times at the output, on-resistance of the device should be low enough to toggle output in less than half-period of signal. To find the best size for inverter, VDD-min can be chosen as supply voltage and input being tied up to supply voltage, then by sweeping of the transistor and monitoring Ron×Cout , optimum size can be found as shown in Figure 4 – 13. So In order to have a fast switching, period of input signal should be much higher than 2.  2.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  70  Figure 4 - 12 Threshold Voltage versus Body-Source Voltage  Figure 4 - 13 RON×CParasitic versus NMOS size and in different supply voltages  Dynamic threshold adjustment is applied to the NMOS device of the inverter by connecting the output of the inverter to the body of the NMOS. Figure 4 - 14 shows the basic concept of dynamic-threshold-voltage MOS (DTMOS) approach for a NMOS device. When node A toggles to VDD, the threshold voltage of the NMOS transistor is lowered due to the body effect and therefore it facilitates toggling of the output to ground (if the input goes high). Note that it is assumed that a technology with triple-well option is available so that we can have NMOS devices with local substrate. In effect, this lowering of the threshold voltage improves the switching transient of the circuit. With the  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  71  same method for PMOS transistor, for having a proper DTPMOS in inverter its body can be connected to gate terminal of transistor.  Figure 4 - 14 (a) Inverter with dynamic-threshold-voltage NMOS (DTMOS) and (b) conventional inverter.  Figure 4 – 15 compares the transient performance of a standard CMOS inverter (graph B) with that of a DTMOS inverter (graph A). The switching transient of the output of the circuits in Figure 4 – 15 (a) and (b) for a supply voltage of 0.8 V is shown. As expected dynamic-threshold-voltage adjustment is effective in improving the transient times (rise/fall times) as well as extending the voltage swing. Improving the switching transient and voltage swing in proposed mixer will improve the effective transconductance of the Gm-stage and thus improves the conversion gain of the circuit. Output Voltage of Inverter 0.9 0.8 0.7  Voltage (V)  0.6 0.5 B 0.4 0.3 0.2 0.1  Without Dynamic Threshold Voltage With Dynamic Threshold Voltage  0 0  0.2  0.4  A 0.6  0.8  Time(Sec)  1  1.2  1.4 -9  x 10  Figure 4 - 15 Output voltage of the inverter with Wp=200 µm, Wn=100 µm, CL=1pF, PLO= −8 dBm, 2.45 GHz LO signal and DC value of LO is 0.3 V, (a) with dynamic threshold (DTMOS) inverter (b) without dynamic threshold voltage.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  72  4.1.2. Proposed Design Techniques for High Linearity: As mentioned having a higher linearity in most cases is cost of burning more power hence it is important to pay more attention to linearity in a low power design. In addition, conventional techniques such as DS method that we discussed earlier are not effective enough in canceling even harmonics. In this section two different design techniques are presented to boost linearity. First idea is used further in Gm-stage of proposed low-power mixer and it is very similar to DS method with this significant improvement that in addition to third harmonic cancelation, it is capable to attenuate second harmonic. Second, a novel conceptual idea which is different from conventional linearity improvement methods is being discussed in details and further of this section it is implemented in a low noise amplifier. In contrast with other methods, this technique can be used for a simultaneous cancelling or attenuating of different harmonics 4.1.2.1. Current-Reusing with Derivative Superposition Technique As mentioned in chapter 3, in DS method we try to cancel third order harmonic of a transistor by using a same auxiliary device which has a different bias. For example as shown and discussed in Figure 3 – 29,  of NMOS transistor is canceled with  ,  another NMOS device. However main drawback of conventional DS method is that since of both devices are being added with a same positive sign, this contributes in a large second order distortion. As an alternative solution and to cancel  ,  in an NMOS  device, an auxiliary PMOS device can be used which generates complementary transconductance. Figure 4 – 16 compares  ,  	,  and  	 of  a NMOS and PMOS  transistors. As can be seen PMOS and NMOS transistors have complementary characteristics. So they can be employed together for simultaneous attenuation of and  	.    CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  73  Figure 4 - 16 Comparison of gm2 and gm3 in conventional DS method with current-reuse. As shown, conventional DS method suffers from a high gm2.  Figure 4 – 17 shows a tangible time domain explanation for linearity in current-reuse. In other words, current-reuse acts like class AB power amplifiers. When input signal goes low PMOS enters to linear region and NMOS becomes more nonlinear and when signal raises NMOS acts more linear and will compensate PMOS nonlinearity. In addition to linearity improvement, as mentioned in chapter 3 current reusing can boost results in a higher gain.  which  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  74  VDD  VDD  VDD  Nonlinear Terms  Cd  Cd  Cd  Nonlinear Terms  VRF  VRF  Figure 4 - 17 Complementary operation of PMOS and NMOS causes current reuse to achieve higher linearity  4.1.2.2. Phase-Shift Harmonic Cancellation Technique Although the adverse effect of IM3 on gain and linearity are typically significant, other intermodulation components, especially IM2 can have an impact on performance. For example, as shown in Figure 4 – 18, IM2 component can cause IM3 after feeding back (e.g., via parasitic coupling) to the input and recombining with the input signal (i.e., fundamental component).  g  m1  X (t ) + g  m2  X (t ) 2 + g  m3  X (t )3 +  Figure 4 - 18 Basic concept of nonlinear system, due to intrinsic feedback other intermodulations can be mixed by input signal and create IM3.  In this section, an alternative technique is proposed that attenuates (and ideally cancels) undesired harmonics (and therefore intermodulation distortion terms (IM2, IM3, …)) by combining two phase-shifted replicas of the input signal. For example, as will be discussed, adding two signals which are 60˚ out-of-phase, results in cancellation of IM3 component. The method can achieve a wideband response and high gain which compare favorably with state-of-the-art approaches such as DS method. Depending on the  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  75  frequency range of interest, the phase shifter can be implemented using passive lumped components (for low to mid-range RF frequencies) and with transmission line (for millimeter-wave (mm-wave) frequencies and beyond). A passive phase shifter network provides a phase shift that is function of the frequency of operation, i.e., the phase shift can be represented as Φ(ω) where ω is the frequency. Keeping this in mind, the proposed phase-shift-based harmonic cancellation (PSHC) technique can be explained using the block diagram shown in Figure 4 - 19.  Figure 4 - 19 Block diagram of the proposed harmonic cancellation technique.  In this architecture, this input signal is first amplified by amplifier A0 (amplified signal is referred to as S0). In the context of an LNA, this first amplification stage can be optimized for input matching, gain and low noise. Next, two phase shifters are used to generate two phase-shifted replicas of S0, namely, S1 and S2. The phase difference of signals S1 and S2 is Φ1(ω) – Φ2(ω). Note that since Φ1(ω) and Φ2(ω) are different phase shifts, in general the harmonic components of S1 and S2 have different amplitudes. Also, since the phase shift is a function of frequency, different frequency components of S1 and S2 have different phase shifts. As shown in Figure 4 – 19, S1 and S2 are again amplified and then combined to construct the overall output of the system which is applied to the output load. By proper choice of phase-shifters one can cancel and/or attenuate undesired harmonics. For example, suppose the fundamental frequency of interest of the input signal is ω0. Then if Φ1(ω0)–Φ2(ω0)= 60˚, one can show that the third harmonic (3ω0) of S1 and S2 are antiphased (i.e., 180˚ out of phase). This means that with proper combination of the two intermediate signals the third harmonic can be cancelled or  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  76  attenuated (depending on the relative amplitude of the third harmonic component in S1 and S2) at the output. Figure 4 – 20 represents this concept in the phasor domain. Here it is assumed that S1 is the reference signal (its phase is zero). Therefore, all harmonics of S1, i.e., S1,n where n=1, 2, 3, … represents the nth harmonic of S1, have a zero phase.  Figure 4 - 20 PSHC concept in phasor domain. Each vector is normalized by itself so all vectors have a same size.  Referring to Figure 4 – 20 , as long as the undesired harmonics of S2 fall within the shaded region (with ±120˚ from S1 signal), with proper choice of gain of A1 and A2, after combining the signals these undesired harmonics will be attenuated (by more than 50%) or canceled. For example in this case, since Φ1(ω0)–Φ2(ω0)= 60˚, then harmonics of the order of 6n–3 (n=1, 2, 3, …) will be canceled. Without loss of generality, we assume that the gain of amplifiers A1 and A2 is chosen such that the signals at the output of A1 and A2 have the same swing. Let us define the harmonic cancellation factor (HCF) as:  1    |  |  0|  	harmonic	of	the	output	when	Φ ω – Φ ω | 	harmonic	of	the	output	when	Φ ω – Φ ω  1  2 2  2  																																																													 4  8  where |∙| refers to the amplitude nth harmonic of the output. Table 1 shows the value of HCF for various harmonics and phase differences  Φ ω  Φ ω .  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  77  . Table 4 - 3 Harmonic cancellation factor for different phase shifts  2rd  3rd  4th  5th  HCF  HCF  HCF  HCF  45˚  30%  61%  100%  61%  60˚  50%  100%  50%  13%  75˚  74%  61%  13%  .01%  90˚  100%  30%  0%  30%  Φ1(ω0)–Φ2(ω0)  Phase-shifters can be implemented using different ways such as all-pass-filters. Here, we use RLC circuits due to their simplicity of implementation. Figure 4 - 21 shows the overall structure of the proposed PSHC technique. In this circuit, each phase-shifter is composed of a series RLC circuit. As will be discussed, in addition to providing proper phase-shift for harmonic cancelation, this architecture can dually serve for extending the operation frequency bandwidth of the circuit.  Figure 4 - 21 Proposed phase-shifter circuit using lump components (excluding biasing)  Considering the transfer function of the RLC network:   	 .   .  1  	 . 1  The phase of VGS1 and VGS2 can be written as:    1,2																														 4  9  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER ∠  tan  ∠  tan  1  1  78  																																																																																		 4  10  																																																																																		 4  11  Thus, the phase difference between the inputs of the two amplifiers is given by:  tan  tan  1  1  																																											 4  12  																																	 4  13  or: tan      1 1  1  1 1    1  1  To simplify the use of Equation 4 – 13 in finding the values of the components in the two RLC phase shifting networks, we make the following practical assumptions: First, in the proposed structure, instead of using explicit capacitors C1 and C2, we will use the gate capacitances of M1 and M2. Note that, in general, introducing additional capacitance in the signal path limits the operation bandwidth and also occupies additional area. Here, we assume both transistors M1 and M2 have the same size, and therefore, C1=C2. In this case, the value of the capacitance depends on the transistor sizing and is typically around a few hundred fF. Next, to facilitate finding the values for the inductors and resistors, while also providing a wide frequency band of operation, we will use one of the RLC networks, for example, the top one, for bandwidth extension using inductive peaking. Therefore, L1 needs to be a high-Q inductor and this sets a limit on how large R1 can be. The bandwidth specification of the circuits helps us determine the value of L1. Next, we use the second RLC circuit, namely, L2 and R2 (as C2 is already set by M2) to achieve the desired phase shift. Cadence Virtuoso and MATLAB simulations for 3rd harmonic cancellation show  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  79  that an L2 in the range of 4 to 9 nH with R2 in the range of 30 to 150 Ω would serve the purpose. Figure 4 – 22 shows MATLAB simulation results for RLC networks. L2 and R2 are tuned to have a full 3rd-harmonic cancellation at 2.4 GHz (  60˚)  Figure 4 - 22 Phase response and of the proposed RLC networks; The components of the second network are adjusted to cancel the 3rd harmonic at 2.4 GHz.  Assuming transistors M1 and M2 have a same size and using Equation 4 – 14 as a nonlinear model of transistor’s current:  ,  ,  ,  ,  ⋯  1,2																																			 4  	14  and assuming perfect combining at the output, we have: ⋯		 4          1,2,3, …																									 4  15  16  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  Figure 4 - 23 Plot of terms in equation (10) versus frequency from  80  to  .  Figure 4 – 23 shows the plot of the summation terms of Equation (10). There are a few interesting observations. First, as predicted VGS1+VGS2 has a wideband response (bandwidth from DC to 8.38 GHz) which can be attributed to resonance peaking of the top RLC circuit. Secondly, 6  3  harmonics (n=1, 2, 3,…) are attenuated over a  wide range of frequency (from 1 to 4.5 GHz, with a full cancellation at 2.4 GHz). Thirdly, in the bandwidth of interest higher-order harmonics have two local minimums, and the higher the order of harmonic the lower the frequency of the first minimum (due to higher angular speed of higher harmonic phasors). 4.1.3. Proposed Ultra Low Voltage/Power Double-Balanced Mixer With considering all discussed techniques for boosting linearity, reducing supply voltage, and decreasing power consumption, in this section we put together all of them for achieving the desired high performance mixer .  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  81  4.1.3.1. Transconductance and Switching Stage Considering Figure 4 – 8 and ideal full swing switching in inverters, Gm–stage should be chosen properly for maximizing conversion gain and linearity. Figure 4 – 24 shows 3 main different possible circuits for Gm–stage.  Figure 4 - 24 Different configurations in Gm-stage  As mentioned current reusing, same as Figure 4 – 24 – d, can boost total transconductance from gmn or gmp to gmn + gmp. In addition, it contributes in lowering supply voltage and increasing headroom by current-bleeding technique, and boosting linearity by suppressing second and third harmonics according to modified DS method. So in comparison to 4 – 24 – b and 4 – 24 – c current-reusing has more advantages and is considered as Gm-stage of proposed mixer. Switching stage consists of two inverters as shown in Figure 4 – 24 – d. To further reducing supply voltage and lowering required LO power for a full swing switching, dynamic threshold technique is used in switches and sizes are optimized to operate in the fastest region, exactly with same approach presented early in Figure 4 – 13. One very important issue in this type of mixer is to find a correct size in Gm-stage. Having a large transistor in this part can increase load capacitance of inverters which results in consuming higher dynamic power. In addition, considering Figure 4 – 25 as a simplified model of mixer and Figure 4 – 26 as generated transconductance in Gm-stage  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER versus time, gm,max should be low enough that  ,  82  becomes comparably much higher  than RON of inverters otherwise it affects voltage swing of inverter’s output. As a good approximation we can choose RON to be 10 times lower than maximum generated gm . 1 10  																																																																																									 	4  17  Figure 4 - 25 Simplified model of inverters and their load during turning ON the Gm-stage  Figure 4 - 26 Model of generated Gm in NMOS or PMOS device versus time  Figure 4 – 27 shows the schematic diagram of the proposed double-balanced mixer. Table 4 – 4 presents the component values and transistor sizing in a 0.13 µm process.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  Figure 4 - 27 Schematic of the proposed mixer, VBP and VBN are bias voltages. Note that LC input matching networks (not shown in the figure) are used at both LO and RF terminals.  Table 4 - 4 Component values in a 0.13µm process Component  Value  RL (kΩ)  1.4  Wp, Gm-Stage (µm)  150  Wn, Gm-Stage (µm)  180  Cd (pF)  0.7  Wp, Inverter (µm)  200  Wn, Inverter (µm)  100  L, All transistors (nm)  130  83  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  84  4.1.3.2. Conversion Gain Here we bring a detailed calculation of conversion gain in proposed double-balanced mixer. Due to the variation of the source voltage of the transistors in the Gm-stage, current may have two components, drift (strong inversion) and diffusion (sub-threshold). To be pessimistic and for ease of calculation we assume that gm in subthreshold is negligible. If VGS of transistors become higher than threshold-voltage, then the current is mainly due to drift. To find gmn and gmp, let’s consider the typical waveform of the source voltage of transistors (Node A or B in Figure 4 - 27). A representative (though simplified) waveform is shown in Figure 4 – 28. In one LO period before t1 and after t2 we can assume gmn is zero because VGS is less than threshold voltage (ignoring subthreshold effect). Based on Figure 4 – 28, between t1 and t2, VS(t) can be approximated with a parabolic function. Thus, for the current-reuse (CR) block, we can write gmn as:     4      2  																											 	4    18  Hence, over one period of LO signal, gmn can be expressed as:  t        0  												 	4  19  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  85  Figure 4 - 28 Simple model for output voltage of inverters at switching stage (Node A or B in Figure 4 - 24).  With the same approximation for PMOS transistors and considering the double-balanced architecture (both current-reuse blocks), output voltage can be approximated as:   gm Vout    t  gmn  R 2  gm      t  gmn  t 																			 	4  20  t . V 																																																																																											 	4  21    t  Figure 4 - 29  gmp      t  gmp  versus time    CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  86  By writing Fourier transform of the overall gm(t) (which has parabolic shape in this approximation) conversion gain can be found in terms of LO period (TLO), and rise/fall time (∆Toff ). 1 T  a  gm  gm T πT    T    ∆T  ∆T  CG  a1.  gm .  α 1  π T  Cos  T  π T  βSin  ∆T  T  ∆T  																																																																																																		 	4  f T , ∆T  πT  2π t dt  T  t 	cos  22  R 2  R T . 2π  ∆T  f T , ∆T  T  																																																																									 	4  23  Therefore, by improving ∆Toff (Rise/Fall time of the inverters) the conversion gain can be increased. As mentioned dynamic threshold technique can improve this parameter.  4.1.3.3. Power Consumption in the Proposed Double-Balanced Mixer Here we bring a detailed calculation of power consumption in proposed mixer. As mentioned earlier dynamic power consumption contributes significantly in total powerconsumption of this type of mixers (Class B). To find an expression for power consumption consider Figure 4 – 24 – d. In a full swing switching, output voltage of each , hence by denoting  inverter has DC value equal to  and  as gate voltages of  NMOS and PMOS transistors and considering that based on current-bleeding design methodology  ,  , power consumption in this block can be written as:  ,     	 .  . .    	2.  . .      ,  .  	 .  . .  	.    	.  ,  2  .  ,  ,        CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER    	 .  . . . 2.   . .  ,  87  	. 2  ,  	 4  24  Figure 4 - 30 – Simulation results in a 0.13 µm process for power consumption of proposed mixer, versus supply voltage and in different frequencies  Figure 4 – 30 shows power consumption versus supply voltage for the mixer shown in Figure 4 – 27. Note that here VBN and VBP have been tuned to get maximum conversion gain in each supply voltage. As can be seen in superthreshold mode slope of figure increases due to static power whereas in subthreshold static power is negligible and dynamic power has main contribution. Also one main disadvantage of class B mixer can be understood form this figure and that is dependency of power consumption to frequency, however as shown this mixer can operate with a very low power consumption up to SHF band.  4.1.3.4. Wideband Switching Technique using Inductive Peaking For wide band applications, it is required that inverters have capability to switch in wide range of frequency with same LO power. However as frequency increases due to gate  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  88  capacitance, effective LO amplitude decreases. As a result, by increasing frequency, LO power should increase proportionally for a proper switching. To compensate impact of high frequency in switching-stage, LO signal can be passively amplified by utilizing resonance technique. Figure 4 – 31 shows concept of resonance amplification for wideband switching. To find a proper value for inductor let us find gate voltage as a function of frequency:   |  1 |  | 1        |  |  √  1 1  | |  	| 1  1  .    												 4     1  																										 4  	25 	26  Figure 4 - 31 (a) Conventional inverter, (b) wideband inverter  As shown in Figure 4 – 32 √  reaches its maximum value at resonance frequency of  	 and it is ideally infinity if  0 , however in practical applications R cannot  be zero since in that case at resonance frequency To find a practical value for  let us draw  0 which impacts LO generator.   simultaneously versus C and with a fixed values for L,    	 and , and  √  50Ω. The  intercept point of these graphs gives us the required C (C is gate capacitance and can be converted easily to size of inverter) and frequency of resonance (or approximately maximum switching frequency). As can be seen from Figure 4 – 33, approximately for  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  89  frequencies less than 10 GHz, it is quite possible to achieve a passive gain of around 1 to 4, while having a practical on chip values for L (less than 10nH) and C (less than 1pF) .  Figure 4 - 32 Resonance passive-gain (  |  |  Figure 4 - 33      and  √  |  ) versus frequency.  |  versus C and in fixed L, R, and  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  90  4.1.3.5. Post-Layout Simulation Results To test feasibility and performance of the proposed mixer, the mixer shown in Figure 4 – 27 is laid out in a 0.13 m CMOS process as shown in Figure 4–35(Further of this thesis measurement results of a same mixer is presented in a 90nm CMOS process). The total area is 380 m× 450 m. Moreover, Monte Carlo simulations for the conversion gain have been done (process & mismatch). Table 4–5 shows different operating points of the mixer. Based on simulations, 13 dB conversion gain can be achieved while operating from a 0.35 V supply and consuming 0.48 mW. Figure 4 – 34 shows the graph of conversion gain versus LO power (PLO) for different supply voltages. Figure 4 – 36 shows different subthreshold operating points from supply voltages between 0.4 V and 0.2 V. Based on this figure, the conversion gain is positive for supply voltages above 0.25 V. Case 4 : Super-Threshold 0.8 0.4 0.4 -6.6 12 15.2 -7.04 2.67  20  15  Conversion Gain (dB)  VDD(V) VBN(V) VBP(V) PLO(dBm) NF(dB) CG(dB) IIP3(dBm) PDC(mW)  Table 4 - 5 Post layout results Case 2 : Case 3 : Sub-Threshold Super-Threshold 0.4 0.5 0.40 0.47 0.00 0.00 -4.00 - 4.1 11.2 10.56 14.7 15.8 -5.54 -8.6 0.6 1.12  Case 1 : Sub-Threshold 0.35 0.35 0.00 -3.75 12.7 13 -3.08 0.48  10  5  0  -5 VDD=1.2 VDD=0.8 VDD=0.5 VDD=0.4 VDD=0.35  -10  -15 -10  -9  -8  -7  -6  -5  -4  -3  -2  -1  PLO(dBm) Figure 4 - 34 Conversion Gain versus LO power and supply Voltage  0  Case 5 : Super-Threshold 1.2 0.75 0.6 -7.5 11.1 17.3 -8.1 8.9  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  91  Figure 4 - 35 Layout of proposed Mixer in 0.13 m CMOS  Figure 4 – 36 shows the effect of dynamic-threshold-voltage technique for two different values of VDD. As expected, by using DTMOS, the same peak in conversion gain occurs at a lower PLO. 15  VDD from 0.4V to 0.2V  Conversion Gain(dB)  10  5 VDD=0.25Volt 0  -5  -10  -15 -5  -4.5  -4  -3.5  -3  PLO(dBm)  -2.5  -2  -1.5  -1  Figure 4 - 35 Conversion gain in subthreshold mode versus LO power for different supply voltages from 0.4V to 0.2V. Conversion gain (in dB) is positive for supply voltages larger than 0.25V  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  92  20  Conversion Gain(dB)  10  0  -10  -20 VDD=0.5 VDD=0.5 VDD=1.2 VDD=1.2  -30  -40 -10  -9  -8  -7  -6  -5  -4  -3  With DTNMOS Without DTNMOS With DTNMOS Without DTNMOS -2  -1  0  PLO(dBm) Figure 4 - 36 Conversion gain versus LO power with and without dynamic threshold voltage  4.1.4. The Proposed Highly Linear, Ultra-Wide-Band Low-Noise Amplifier In this section to check feasibility of proposed phase-shift based linearization technique in a CMOS process, we attempt to apply that in one of the RF blocks. For simplicity we choose low-noise amplifier (LNA) since in comparison to other RF blocks (PA and mixer), LNA deals with smaller signals so implementing current combiner is much easier. Figure 4 – 38 shows the schematic view of the proposed wideband LNA. L0 is utilized to facilitate input matching. L3 and R3 generate a zero in the transfer function (at 2 GHz) and thus extend the bandwidth [30]. As discussed earlier, L1 is responsible for bandwidth extension and its resonance frequency with gate capacitance is 7 GHz which is much higher than that of the zero generated by L3 and R3. Thus the overall LNA achieves a high bandwidth. L1 and R1 are responsible for creating the desired phase difference. Finally phase shifted currents in output stage are being added to each other. A proof-ofconcept LNA is designed and laid out in a 0.13µm process. Figure 4 - 39 shows the layout of the proposed LNA. The total area is 890 m× 490 m. Table 4 - 6 shows component values.  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  93  Figure 4 - 37 Schematic of proposed LNA  Figure 4 - 38 Layout of proposed LNA in IBM 0.13µm process.  4.1.4.1. Post-Layout Simulation Results Figure 4 – 40 shows post layout simulation for S21 and for noise figure (NF) of the proofof-concept LNA.As discussed two peaks can be observed in a wide range of frequency (0.07-0.8 GHz). The first one is due to the zero created by L3 and R3 and the second one is due to inductive peaking due to L1. Figure 4 – 41 shows the variation of the inputreferred third-order intercept point (IIP3) of the LNA at 1.5 GHz versus R2. Based on this figure, the IIP3 has a peak when R2 is equal to 70.3 Ω which corresponds to 60˚ phase difference between the currents of the two branches (before they are combined).  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER Table 4 - 6 Components value for proposed LNA  Component  Value  L0nH  Responsibility  2.4  Matching  (Rf KΩ, Cf fF)  (3,700)  Stability  (R3 Ω,L3 nH)  (91,8.8)  BW extension (0.07-5GHz)  (R1 Ω,L1 nH)  (6.5,4.2)  BW extension (5-7.5GHz)  (R2 Ω,L2 nH)  (70.3,9)  Phase-Tuner  (M0, M1, M3) (µm)  (65,34,77)  Gain – Current Combiner  (M2, M4) (µm)  (130,285)  Gain - Current Combiner  50  -  (1.2,0.6,0.6)  Biasing  RL (Ω) (VDD,VBN,VBP) (V)  Figure 4 - 39 Post-Layout simulation for S21 and NF  94  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  95  Figure 4 - 40 IIP3 versus R2 resistance at 1.5GHz, peak value is for R=70.3 Ω Table 4 - 7 Performance summary and comparison Parameters  This Work*  [31]**  [32]**  [33]**  [34]**  Harmonic Cancellation  Phase-Shift  WBDS  Modified DS  Modified  NA  DS  Method 0.07-7.5  2.3-5.3  1.5-8.1  0.9  0.2-5.2  3.4 @ 2.4GHz , 2.3 @  4.9  3.6-6  2.95  3.5  Operating Frequency (GHz) NF (dB)  7GHz S21 (dB)  17.9  12.4  8.6-11.7  11  13-15.6  Maximum IIP3 (dBm)  13.08 @ 1.5GHz  15.6 @ 4GHz  14.1 @ 5GHz  21  0  PDC(mW)  15.6  8.3  2.62  22.5  21  Process  0.13 µm  0.13 µm  0.13µm  0.35µm  65nm  541.16  109.1  313.25  102.3  5.17  FOM *: Post-Layout Simulation Results  ** Measurement Results  Table 4 - 7 summarizes the performance of the proposed LNA and compares it with that of the estate-of-the-art designs. For the purpose of comparison and to account for the tradeoffs among gain, bandwidth, linearity, and noise performance we use the following figure of merit (FoM) as defined in [32]. (Note that this FoM is very sensitive to gain and IIP3) FoM  																																																																																								 4  27  CHAPTER 4. PROPOSED TECHNIQUES FOR A HIGHLY EFFICIENT MIXER  96  where IIP3 is the peak value in mW, G is the average power gain, PDC is the power consumption in mW, BW is bandwidth in GHz, and F is the average noise figure of the block. Based on Table 3, the proposed LNA performance compares favorably with that of the state-of-the-art designs.  4.1.5. Conclusion and Outline of Next Chapter Different techniques such as subthreshold design, stacked reduction, dynamic threshold switching, and current reusing were used in conjunction with each other to achieve an ultra low power and ultra low voltage CMOS mixer while maintaining a high performance. As discussed due to frequency dependency of power consumption in this class of mixer, they are more suitable up to SHF band. Presented mixer can operate in voltages as low as threshold voltage of technology and can reach µW level power consumption. In addition, a novel phase-shift linearization method was presented which can compete with state of art. As a proof of concept this technique was implemented in an LNA but can be extended to other building blocks such as mixers. Thus far the proposed ideas were supported by post-layout simulation. In the next chapter, we will focus on measurement results.  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  97  Chapter 5. IMPLEMENTATION AND MEASUREMENTS In the previous section we proposed two designs for ultra-low-power/voltage CMOS mixer and highly-linear low noise amplifier. The designs were supported by post layout simulation. In this section we bring measurement results. 5.1.1.  Implementation of Proposed Low- Power/Voltage Class-B CMOS Mixer  Figure 5 – 1 shows schematic of implemented mixer in a 90-nm CMOS process. To make the measurement steps easier (especially for IIP3 measurements), two active baluns have been designed in input-stage which have different supply voltage terminal than mixer core. Finally in output stage two common-drain buffers are designed to be able to load 50 Ω load. This load is being set by the input impedance of the measurement instrument (e.g., spectrum analyzer), which in most cases is 50 Ω.  Figure 5 - 1 Schematic of proposed mixer  To have a fair judgment about performance of mixer gain of RF active balun in 1GHz is set to cancel loss of common-drain buffer, however since measured IF is always in 50MHz, in RF frequencies higher than 1GHz gain+loss becomes negative so it should be compensated in conversion gain measurement of mixer core. In addition to that,  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  98  differential gain of LO balun is set to be 0dB in 1GHz so in frequencies higher than 1GHz differential gain is less than 0dB and hence should be considered in measurement. To have a wideband switching LRES is used in LO-stage to resonate with gate capacitance of inverters at 8.5 Ghz. Table 5 – 1 shows component values of mixer core. Measurement setup is as shown in appendix – 1. Figure 5 – 2 shows layout and chip photograph of proposed mixer in TSMC 90nm process.  Table 5 - 1 Mixer core component values Component Value RL (kΩ)  5  Wp, Gm-Stage (µm)  24  Wn, Gm-Stage (µm)  18  Cd (pF)  2  Wp, Inverter (µm)  20  Wn, Inverter (µm)  14  L, Gm-Stage (nm)  100  L, Inverter (nm)  200  Figure 5 - 2 Layout and chip photograph of proposed mixer in a 90nm process  5.1.1.1. Conversation Gain In all CG measurements, IF is set to be 50 MHz. Figure 5 – 3 shows CG of proposed mixer versus different supply voltages (Maximum allowable voltage for preventing break down in this process is 1 V). In this figure frequency of operation is 2.5 GHz and differential LO power at the input of inverters is -5 dBm. Table 5 – 2 shows bias  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  99  configuration in Gm –stage. As can be seen it is quite possible to achieve a very high conversion gain (>10dB) while having a very low supply voltage. One interesting feature about this mixer is that for voltages less than 0.45 V, there is no need for any additional bias-voltage in Gm-stage as VBN is equal to VDD and VBP is zero. This issue makes implementation process very easy and there is no need for designing any control loop to adjust VBP and VBN. Table 5 - 2 Mixer core component values VDD-2 VLO VBN VBP 0.2  0.1  0.2  0  0.35  0.1  0.35  0  0.45  0.2  0.45  0  0.55  0.2  0.5  0.1  0.65  0.3  0.5  0.2  0.8  0.4  0.4  0.4  0.9  0.45  0.45  0.45  1  0.5  0.5  0.6  Figure 5 - 3 Conversion gain versus supply voltage  Figure 5 – 4 shows conversion versus different frequency. Here mixer core supply voltage is set to be 0.35V and diffrential LO power is between -6 dB to -8.5 dB . As predicted conversion gain drops strongly after resosance frequency of tunde to be at 8.5 Ghz .  .  which  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  100  Figure 5 - 4 Conversion gain versus frequency. IF is 50 MHz  Figure 5 – 5 shows conversion gain versus differential LO power at 2.5 GHz and 0.35 V supply.  Figure 5 - 5 Conversion Gain versus LO power  5.1.1.2. Power Consumption Figure 5 – 6 shows conversion gain of mixer core versus supply voltage, input frequency is 2.5 GHz and IF is in 50MHz. VBP and VBN are same as Table 5 – 2. Same as simulation results in Chapter 4, power consumption has a parabolic relation to supply voltage. As  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  101  mentioned this is mainly due to dynamic power of inverters. As shown, interestingly for voltages less than 0.65 V power consumption is less than 1mW and for 0.35 V supply it only consumes as low as 110 µW. Considering Figure 5 – 3 at this supply voltage gain is around 18.3 dB which is comparably higher than state-of-art.  Figure 5 - 6 Power consumption versus supply voltage  Figure 5 – 7 shows power consumption versus frequency. In this case supply voltage is 0.35 V. VBN is equal to supply voltage and VBP is zero. Also LO power is -8dB. As can be seen power consumption is linear with frequency.  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  102  Figure 5 - 7 Power consumption versus input frequency  5.1.1.3. Two Tone Test and Linearity Two tone test setup is shown in Appendix – 3. Table 5 – 3 shows the measured IIP3 in different supply voltages. As can be seen IIP3 improves in higher supply voltages. This is mainly due to two significant effects. First as mentioned earlier IIP3 is directly proportional to overdrive voltage and hence higher supply voltage provides higher linearity. However this is not main effect in this mixer. As discussed, in Gm-stage, if PMOS transistor operates in a complementary operating point than NMOS transistor (Complementary operating point is achievable when pMOS operates in weak inversion) then it can significantly suppress third and second harmonics. So supply voltage should be high enough to let us change VBP and VBN for finding a correct point. Figure 5 – 8 shows two tone measurement of the mixer with a 0.55 V supply. In this figure VBP is 0V and PMOS operates in strong inversion. Figure 5 – 9 shows a same measurement when VBP is 0.1 V. As can be seen when the PMOS transistor operates in the weak-inversion region, the third harmonic can be significantly suppressed.  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  103  Figure 5 - 8 Tow tone measurement, in this VDD is 0.55V, VBP is 0V, and PMOS transistor operates in strong inversion  Figure 5 - 9 Tow tone measurement, in this VDD is 0.55V, VBP is 0.1V, and PMOS transistor operates in weak inversion Table 5 - 3 Measured IIP3 versus supply voltage Supply Voltage (V) IIP3 Without DS (dBm) IIP3 With DS (dBm) 0.35  -4.4  NA  0.55  -2.3  6.3  0.65  -2.5  7.6  0.9  -0.3  8  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  104  Table 5 – 4 and 5 – 5 present summary of measurement results in 2.5 GHz and 7.5 GHz.  VDD(V) VBN(V) VBP(V) PLO(dBm) NF(dB) CG(dB) IIP3(dBm) PDC(mW)  Table 5 - 4 Performance of implemented 90nm Mixer in 2.5 GHz and IF of 50 MHz Case 1 : Case 2 : Case 3 : Case 4 : Case 5 : Sub-Threshold Sub-Threshold Weak Inversion Super-Threshold Super-Threshold 0.35 0.45 0.5 0.8 1 0.35 0.45 0.47 0.4 0.45 0.00 0.00 0.00 0.4 0.6 -7 -6.2 - 7.3 -7.5 -9 10.4 10.2 11.2 10 8.45 18.3 19.6 21.2 25.2 23.9 -4.4 -3.3 3.4 7.4 8.1 0.11 0.279 0.37 1.84 5.1  VDD(V) VBN(V) VBP(V) PLO(dBm) NF(dB) CG(dB) IIP3(dBm) PDC(mW)  Table 5 - 5 Performance of implemented 90nm Mixer in 7.5 GHz and IF of 50 MHz Case 1 : Case 2 : Case 3 : Case 4 : Case 5 : Sub-Threshold Sub-Threshold Weak Inversion Super-Threshold Super-Threshold 0.35 0.45 0.5 0.8 1 0.35 0.45 0.47 0.4 0.45 0.00 0.00 0.00 0.4 0.6 -6.1 -6.2 -7 -7 -7.2 9.2 9.1 10.2 12 9.2 15.2 16.2 18 20.1 19.4 -8.4 -4.4 1.2 5.25 6.1 0.265 0.4 0.5 2.1 6.2  5.1.2.  Implementation of Proposed Linearization Technique  For testing the proposed phase-shift linearization technique, LNA in Figure 4 – 36 has been implemented in a 0.13-µm CMOS process, as shown in Figure 5 – 10 (Same as Figure 4 – 37). First of all, for measuring S21, S11, and NF, all probes, cables , and network analyser (HP8510) have been calibrated with standard “short”, “open”, “load”, “thru” test [35].  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  105  Figure 5 - 10 Chip photograph of proposed Low Noise Amplifier  5.1.2.1. S21 and S11 Measurement Figure 5 – 11 shows S21 measurement of 3 different DUTs and compare them with postlayout simulations. As can be seen they are in close agreement with each other and confirms accuracy of calibration.  Figure 5 - 11 Measured and Post-Layout Simulation Results of S21  Figure 5 – 12 shows measured S11. Same as simulation results, S11 reaches its minimum value in the middle of the bandwidth  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  106  Figure 5 - 12 Measured Result of S11  5.1.2.2. Linearity and IIP3 Appendix – 3 shows setup for IIP3 measurement. Figure 5 – 13 shows tow tone measurement of proposed linear LNA at 3 GHz. Since noise floor of spectrum analyzer is around -80dB and the fact that the system is very linear, input signal should be high enough that third harmonic becomes higher than noise floor. With considering cable, probes, and power combiner looses input signal of LNA is set to be -23.5dBm. So IIP3 can be found by:  3  ∆  Where ∆  =  .  .  23.5  6.6 dB  is power-difference between third and main harmonic in output, and  input power of LNA.  is  CHAPTER 5. IMPLEMENTATION AND MEASUREMENTS  107  Figure 5 - 13 Two tone measurement of proposed LNA  Table 5 – 5 shows performance summary of proposed LNA. Table 5 - 6 Measurement result summary Parameters Operating Frequency (GHz) NF (dB) Maximum S21 (dB) Maximum IIP3 (dBm) PDC(mW) Process  Value 0.1-7.5 3.9 @ 2.5 GHz 17.2 6.5 @ 3 GHz 17.42 0.13 µm  CHAPTER 6. CONCLUSION  Chapter 6.  108  CONCLUSION  6.1. INTRODUCTION This thesis discussed some bottlenecks of conventional as well as state-of-art active CMOS mixers. Different design techniques such as subthreshold operation, dynamic threshold switching, inductive peaking and current-reusing were used in conjunction of each other for making a highly efficient CMOS mixer. This chapter summarizes main achievements of this work and will end by future works.  6.2. ACHIEVEMENTS 6.2.1. Ultra-Low-Power and Low-Supply-Voltage Operation As discussed due to different stages of stacked-transistor in current commutating mixers, lowering supply voltage can be considered as one of the main design bottlenecks. Minimum achievable supply voltage in each design discussed and as rule of thumb this minimum is in range of 3 to 4 times of threshold voltage. In addition to that by a practical measurement we showed that minimum achievable power consumption in a conventional design is higher than 1mW. Four main techniques were proposed to reduce supply voltage and power consumption in mixers:   Subthreshold design was discussed as a strong tool for reducing bias current and power consumption. As shown by a practical measurement this technique can reduce power in a conventional design up to 2 to 3 times while maintaining a same performance. Briefly design procedure discussed based on inversion coefficient and finding a sweet-spot where the trade off between transconductance efficiency and transistor’s speed (equally transistor’s fT) becomes optimum.    A novel methodology for stacked reduction proposed which can reduce supply voltage to as low as threshold of process. In this technique instead of conventional current commutating switching-stage, transconductance of Gm-stage is being switched by turning this block ON and OFF. As shown this method can reduce or  CHAPTER 6. CONCLUSION  109  ideally eliminate DC power consumption and instead of that Dynamic-Power contributes as a main part of power. Because of this fundamental change in method of power consumption we named this mixer as Class-B CMOS mixers. Due to dependency of power to frequency, proposed technique is suitable up to mid SHF (<10GHz) band.   Complementary Current-reusing with PMOS and NMOS device was discussed as a strong candidate for Gm-stage. This pair is interesting since it can : o Increase available headroom (Or equally reduces minimum required supply-voltage) by current-bleeding technique. o Boosts overall transconductance to from  (or  ) to  o Suppress third and second harmonics by Derivative Superposition (DS) method   Application of Dynamic Threshold switching presented. By applying this technique switching stage can operate more efficient and in a lower supply voltage. In addition to that required LO power can be reduced significantly  6.2.2. Wide-Band Switching Wideband switching-stage was proposed by utilizing from resonance technique. As discussed in addition to bandwidth extension, by choosing a proper resonance network a reasonable passive gain is achievable.  6.2.3. Phase-Shift Linearization Technique One key challenge in any linearization technique is to suppress different harmonics (especially second and third) simultaneously. However, in most approaches only a certain harmonic is being considered and that can be in cost of increasing other undesired harmonics. As an alternate solution, a conceptual harmonic cancellation technique was presented which can attenuate group of harmonics is a same time. As a proof of concept proposed technique was implemented in a Low Noise Amplified and successfully tested.  CHAPTER 6. CONCLUSION  110  6.3. FUTURE WORK  6.3.1. Using Proposed Low Power Mixer in a Full Receiver Front-End In a collaborative work, proposed mixer has been implemented in a 2.5 GHz receiver front-end as shown in figure 6 – 1. This work is being fabricated in a 0.13 µm process and will be measured as a next step for achieving µW level wireless transmitter.  Figure 6 - 1 Layout of 2.5 GHz receiver suitable for cellular application  BIBLIOGRAPHY  111  BIBLIOGRAPHY Chapter 1: [1] Jet Propulsion Laboratory, “ Voyager Project ”, Retrieved from : http://voyager.jpl.nasa.gov/mission/weekly-reports/index.htm [2] E.A.M. Klumperink, S.M. Louwsma, G.J.M. Wienk, and B. Nauta, “A CMOS switched transconductor mixer,” IEEE Journal of  Solid-State Circuits, vol.39, no.8, pp. 1231- 1240, Aug. 2004. [3] Hanil Lee; Mohammadi, S., “A 500μW 2.4GHz CMOS Subthreshold Mixer for Ultra Low Power Applications,“ IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp.325-328, 3-5 June 2007. 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