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A low-power 10-bit 50 MS/s CMOS successive approximation register ADC

University of British Columbia

An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to a few tens of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for data communication, imaging, and video systems. With the rapid growth in the number of portable devices, low-power design with higher performance is desired to increase the battery longevity as well as meeting the ever increasing performance requirement, which impose significant challenges to the ADC design. Successive approximation register (SAR) ADCs are one of the candidate structures for low power ADCs, and due to the advancements in the fabrication technologies they have been able to achieve medium sampling rates with a resolution of 10 bit. In this work, an ultra low-power 10-bit 50-MS/s SAR ADC is presented. To reduce the power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor digital-to-analog converter (DAC) that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is improved by modifying the capacitor bank so that the bridge capacitor is an integer multiple of the unit capacitor (as opposed to fractional multiple in the conventional circuits) and by including two dummy unit capacitors connected to ground. The proposed 10-bit ADC is designed and simulated using a 90-nm CMOS technology. Post-layout simulation results show that at 1.0-V supply and 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB and consumes 0.32 mW with an input capacitance of 0.48 pF, resulting in a figure of merit (FoM) of 8.44 fJ/conversion-step. A proof-of-concept prototype is fabricated in 90-nm CMOS technology and is tested. The ADC core occupies an active area of 215×215 μm². Due to an unexpected problem with the measurement setup, at-speed testing was not possible and the test was done at 1 MS/s. The ADC achieves an ENOB of 7.51 with a power consumption of 51 μW. The reasons for subpar performance of the prototype design and potential solutions to improve it are discussed in detail.

Text

2012-09-11

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/43200

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/