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A low-power 10-bit 50 MS/s CMOS successive approximation register ADC Guo, Wei 2012

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A Low-Power 10-bit 50 MS/s CMOS Successive Approximation Register ADC  by Wei Guo B.Sc., Tsinghua University, 2010  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF  MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES (Electrical and Computer Engineering)  THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver) September 2012 c Wei Guo, 2012  Abstract An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to a few tens of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for data communication, imaging, and video systems. With the rapid growth in the number of portable devices, low-power design with higher performance is desired to increase the battery longevity as well as meeting the ever increasing performance requirement, which impose significant challenges to the ADC design. Successive approximation register (SAR) ADCs are one of the candidate structures for low power ADCs, and due to the advancements in the fabrication technologies they have been able to achieve medium sampling rates with a resolution of 10 bit. In this work, an ultra low-power 10-bit 50-MS/s SAR ADC is presented. To reduce the power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor digital-to-analog converter (DAC) that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is improved by modifying the capacitor bank so that the bridge capacitor is an integer multiple of the unit capacitor (as opposed to fractional multiple in the conventional circuits) and by including two dummy unit capacitors connected to ground. The proposed 10-bit ADC is designed and simulated using a 90-nm CMOS technology. Post-layout simulation results show that at 1.0-V supply and 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB and consumes 0.32 mW with an input capacitance of 0.48 pF, resulting in a figure of merit (FoM) of 8.44 fJ/conversion-step.  A  proof-of-concept prototype is fabricated in 90-nm CMOS technology and is tested. The ADC core occupies an active area of 215 ⇥ 215 µm2 . Due to an ii  unexpected problem with the measurement setup, at-speed testing was not possible and the test was done at 1 MS/s. The ADC achieves an ENOB of 7.51 with a power consumption of 51 µW. The reasons for subpar performance of the prototype design and potential solutions to improve it are discussed in detail.  iii  Preface This work is conducted in the Electrical and Computer Engineering Department of the University of British Columbia (UBC), under the supervision of Dr. Shahriar Mirabbasi. Part of Chapter 4 has been published as the following conference paper, Wei Guo and Shahriar Mirabbasi, “A Low-Power 10-Bit 50-Ms/S SAR ADC Using a Parasitic-Compensated Split-Capacitor DAC”, in the International Symposium of Circuit and System (ISCAS), South Korea, Seoul, May 2012. I have transferred my copyright to the organizer of the conference above, the Institute of Electrical and Electronics Engineers (IEEE). However, I maintain the right to write this thesis. I am the primary author of the publication and performed the majority of the work, including but not limited to literature review, circuit design and layout, and chip testing. Dr. Mirabbasi supervised the circuit theory and the realization of project.  iv  Table of Contents Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ii  Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  iv  Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  v  List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  viii  List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ix  Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  xii  1  2  Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1  1.1  Motivation of the Work . . . . . . . . . . . . . . . . . . . . . . .  1  1.2  Organization of the Thesis . . . . . . . . . . . . . . . . . . . . .  3  Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4  2.1  Ideal ADCs and Characterizations . . . . . . . . . . . . . . . . .  4  2.1.1  Quantization Noise . . . . . . . . . . . . . . . . . . . . .  6  2.1.2  Output Code . . . . . . . . . . . . . . . . . . . . . . . .  7  2.1.3  Characterizations . . . . . . . . . . . . . . . . . . . . . .  7  Types of ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . .  11  2.2.1  ADC Architectures . . . . . . . . . . . . . . . . . . . . .  12  2.2.2  State-of-the-Art Designs . . . . . . . . . . . . . . . . . .  17  Performance Limitations . . . . . . . . . . . . . . . . . . . . . .  17  2.3.1  17  2.2  2.3  Clock Jitter . . . . . . . . . . . . . . . . . . . . . . . . . v  3  2.3.2  Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20  2.3.3  Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . .  22  SAR ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . .  24  3.1  Conventional Charge-redistribution Architectures . . . . . . . . .  24  3.1.1  Binary-weighted Charge-redistribution . . . . . . . . . .  27  3.1.2  Split-capacitor Charge-redistribution . . . . . . . . . . . .  31  Modifications on Conventional Architectures . . . . . . . . . . .  32  3.2.1  Switching Procedures for Charge-redistribution . . . . . .  33  3.2.2  Calibration for Split-capacitor Architecture . . . . . . . .  39  The Proposed SAR Architecture . . . . . . . . . . . . . . . . . . . .  44  4.1  Matching Improvement of the Bridge Capacitor . . . . . . . . . .  46  4.2  Compensation of the Parasitic Capacitance . . . . . . . . . . . . .  47  4.3  Reduced Power Consumption of the DAC . . . . . . . . . . . . .  49  Circuit Design & Layout . . . . . . . . . . . . . . . . . . . . . . . .  51  5.1  Boot-strapped Sampling Switch . . . . . . . . . . . . . . . . . .  51  5.2  Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  52  5.3  Digital Control Logic . . . . . . . . . . . . . . . . . . . . . . . .  55  5.4  Capacitor Array . . . . . . . . . . . . . . . . . . . . . . . . . . .  56  Post-Layout Simulation Results and Measurement Results . . . . .  59  6.1  ADC Test Methods . . . . . . . . . . . . . . . . . . . . . . . . .  59  6.2  Post-Layout Simulation Results . . . . . . . . . . . . . . . . . .  60  6.2.1  Differential and Integral Nonlinearity . . . . . . . . . . .  60  6.2.2  SNDR, SFDR and ENOB . . . . . . . . . . . . . . . . .  62  6.2.3  Power Consumption . . . . . . . . . . . . . . . . . . . .  62  Measurement Results . . . . . . . . . . . . . . . . . . . . . . . .  64  6.3.1  Measurement Setup . . . . . . . . . . . . . . . . . . . . .  64  6.3.2  Static Performance . . . . . . . . . . . . . . . . . . . . .  67  6.3.3  Dynamic Performance . . . . . . . . . . . . . . . . . . .  68  6.3.4  Measurement Results Analysis . . . . . . . . . . . . . . .  69  3.2  4  5  6  6.3  vi  7  Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  76  7.1  Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . .  76  7.2  Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77  Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  78  vii  List of Tables Table 2.1  Digital output codes for ADCs . . . . . . . . . . . . . . . . .  7  Table 2.2  State-of-the-art designs . . . . . . . . . . . . . . . . . . . . .  18  Table 6.1  Post-layout simulation summary . . . . . . . . . . . . . . . .  64  Table 6.2  Pads and usage . . . . . . . . . . . . . . . . . . . . . . . . . .  65  Table 6.3  Test equipments . . . . . . . . . . . . . . . . . . . . . . . . .  66  Table 6.4  Comparison to state-of-the-art designs . . . . . . . . . . . . .  75  viii  List of Figures Figure 1.1  ADC used in an image sensor . . . . . . . . . . . . . . . . .  2  Figure 2.1  Block diagram of an ADC . . . . . . . . . . . . . . . . . . .  4  Figure 2.2  ADC is a sampled-data system . . . . . . . . . . . . . . . . .  5  Figure 2.3  2-bit quantizer’s transfer curve . . . . . . . . . . . . . . . . .  5  Figure 2.4  Model of quantization noise . . . . . . . . . . . . . . . . . .  6  Figure 2.5  Probability density function of Verr . . . . . . . . . . . . . . .  6  Figure 2.6  Example of offset, gain error, INL and DNL . . . . . . . . . .  8  Figure 2.7  Architectures of ADCs . . . . . . . . . . . . . . . . . . . . .  11  Figure 2.8  Successive approximation register ADC . . . . . . . . . . . .  12  Figure 2.9  Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . .  14  Figure 2.10 Voltage transfer curve of stagei in pipelined ADCs . . . . . .  14  Figure 2.11 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . .  15  Figure 2.12 Block diagram of time-interleaved ADCs . . . . . . . . . . .  16  Figure 2.13 Block diagram of S  D ADCs . . . . . . . . . . . . . . . . .  17  Figure 2.14 Aperture jitter in an ADC . . . . . . . . . . . . . . . . . . . .  19  Figure 2.15 Noise in a low-pass filter . . . . . . . . . . . . . . . . . . . .  21  Figure 2.16 Noise of a transistor when connected to a capacitor . . . . . .  21  Figure 2.17 SNR vs C assuming Vpp = 1 V . . . . . . . . . . . . . . . . .  22  Figure 3.1  Block diagram of a SAR ADC . . . . . . . . . . . . . . . . .  26  Figure 3.2  Binary search algorithm for SAR ADCs . . . . . . . . . . . .  26  Figure 3.3  Voltage transfer curve of a SAR ADC . . . . . . . . . . . . .  27  Figure 3.4  Charge redistribution SAR ADCs . . . . . . . . . . . . . . .  27  ix  Figure 3.5  A SAR ADC with S/H merged into the capacitor DAC . . . .  28  Figure 3.6  Transfer curve when S/H circuit is merged into DAC . . . . .  29  Figure 3.7  Switching procedure with differential configuration [23] . . .  30  Figure 3.8  Split-capacitor SAR ADCs . . . . . . . . . . . . . . . . . . .  31  Figure 3.9  Waveform of the conventional switching procedure . . . . . .  33  Figure 3.10 Differential architecture with conventional switching procedure  34  Figure 3.11 Differential architecture with monotonic switching procedure  34  Figure 3.12 Flow diagram of the monotonic switching . . . . . . . . . . .  36  Figure 3.13 Monotonic switching procedure [23] . . . . . . . . . . . . . .  36  Figure 3.14 Waveform of monotonic switching . . . . . . . . . . . . . . .  37  Figure 3.15 Flow diagram of VCM -based switching . . . . . . . . . . . . .  38  Figure 3.16 A waveform of VCM -based switching . . . . . . . . . . . . . .  38  Figure 3.17 Switching of a SAR ADC with VCM -based switching . . . . .  39  Figure 3.18 A split-capacitor SAR ADC with parasitic capacitance . . . .  39  Figure 3.19 ENOB vs CP for a 10-bit SAR ADC . . . . . . . . . . . . . .  40  Figure 3.20 ENOB vs DCbri for a 10-bit SAR ADC . . . . . . . . . . . . .  41  Figure 3.21 Modified split-capacitor SAR ADC [3] . . . . . . . . . . . .  41  Figure 3.22 Modified split-capacitor SAR ADC [35] . . . . . . . . . . . .  42  Figure 3.23 Modified split-capacitor SAR ADC [7] . . . . . . . . . . . .  43  Figure 4.1  Proposed split-capacitor architecture . . . . . . . . . . . . . .  44  Figure 4.2  Variation of the ratio from two . . . . . . . . . . . . . . . . .  47  Figure 4.3  ENOB considering the bridge capacitor mismatch . . . . . . .  47  Figure 4.4  ENOB improvement in the proposed architecture . . . . . . .  48  Figure 4.5  ENOB vs reference Vre f /16 accuracy . . . . . . . . . . . . .  49  Figure 4.6  Voltage divider for Vre f /16 . . . . . . . . . . . . . . . . . . .  50  Figure 4.7  Switching energy in different architectures . . . . . . . . . .  50  Figure 5.1  Boot-strapped switch for S/H . . . . . . . . . . . . . . . . . .  52  Figure 5.2  Dynamic comparator . . . . . . . . . . . . . . . . . . . . . .  53  Figure 5.3  Offset of the comparator . . . . . . . . . . . . . . . . . . . .  54  Figure 5.4  Layout of the comparator . . . . . . . . . . . . . . . . . . . .  55  Figure 5.5  Synchronous control logic and timing diagram . . . . . . . .  55  x  Figure 5.6  Control logic and timing diagram . . . . . . . . . . . . . . .  56  Figure 5.7  Floorplan of the capacitor array . . . . . . . . . . . . . . . .  57  Figure 5.8  Layout of the whole chip and a zoomed-in view . . . . . . . .  58  Figure 6.1  Test for static performance . . . . . . . . . . . . . . . . . . .  60  Figure 6.2  Test for dynamic performance . . . . . . . . . . . . . . . . .  61  Figure 6.3  Post-layout simulation result of INL/DNL . . . . . . . . . . .  61  Figure 6.4  Spectrum with the input frequency of 22.75 MHz . . . . . . .  62  Figure 6.5  SNDR, SFDR and ENOB vs input frequency . . . . . . . . .  63  Figure 6.6  Power vs sampling rate . . . . . . . . . . . . . . . . . . . . .  63  Figure 6.7  Label of each pad . . . . . . . . . . . . . . . . . . . . . . . .  65  Figure 6.8  Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . .  66  Figure 6.9  Test with probe landed . . . . . . . . . . . . . . . . . . . . .  67  Figure 6.10 Test setup for static performance measurement . . . . . . . .  67  Figure 6.11 Measured INL . . . . . . . . . . . . . . . . . . . . . . . . .  67  Figure 6.12 Measured DNL . . . . . . . . . . . . . . . . . . . . . . . . .  68  Figure 6.13 Test setup for dynamic performance measurement . . . . . . .  68  Figure 6.14 Output spectrum when input frequency is 55 kHz . . . . . . .  69  Figure 6.15 SNDR, SFDR and ENOB vs input frequency . . . . . . . . .  69  Figure 6.16 SNDR, SFDR and ENOB vs sampling rate . . . . . . . . . .  70  Figure 6.17 Transfer curve . . . . . . . . . . . . . . . . . . . . . . . . .  71  Figure 6.18 Eyepass probe and suss probe . . . . . . . . . . . . . . . . .  71  Figure 6.19 PCB with package . . . . . . . . . . . . . . . . . . . . . . .  72  Figure 6.20 Test setup with PCB . . . . . . . . . . . . . . . . . . . . . .  73  Figure 6.21 SFDR, SNDR and ENOB vs second reference . . . . . . . . .  74  xi  Acknowledgments I would like to express my gratitude to my supervisor, Dr. Shahriar Mirabbasi for his guidance and support during this process. It was an honor to work with him and I appreciate very much for giving me the opportunity to join his group. I have gained a lot from not only his profound knowledge but also his great character. I would also like to thank my colleagues, Hooman Rashtian, Pouya Kamali Nejad and Roberto Rosales. Their kind help and technical discussions play an important role in my research. Hooman Rashrian and Pouya Kamali Nejad gave me a lot of useful suggestions and help on the circuit design. Technical assistance and advice from Dr. Roberto Rosales made me familiar with the test equipments. Finally, I would like to express my deepest appreciation to my parents. Their love and support make me who I am today. They have always been my inspiration and I dedicate this thesis to them. This work is supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) and the CAD tools and access to technology are provided by Canadian Microelectronics Corporation (CMC Microsystems).  xii  Chapter 1  Motivation 1.1  Motivation of the Work  An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to hundreds of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for many applications including data communication, imaging and video systems. With the rapid increasing of portal devices powered by battery, lowpower design with higher performance is desired to increase the battery life as well as meeting the ever increasing performance requirement. For example, Figure 1.1 shows an ADC as a key block in an image sensor. Up to hundreds of mega samples are required to enable real-time high definition video capture (720p or higher) in modern cellphones or digital cameras. High power consumption of these high performance ADCs not only reduce the battery life but also degrade the image quality due to higher noise and leakage as a result of higher temperature. When the total pixel number doubles, the sampling rate of the ADC needs to be doubled, bringing significant challenge in low-power ADC design. Pipelined analog-to-digital converters (ADCs) used to dominate in these applications. However pipelined ADCs have been facing significant challenges in modern advanced CMOS technology and have improved slightly with the scaling of the feature size in each generation of fabrication technology. Intrinsic gain of short channel MOS transistor has been decreasing due to reduced drain barrier while high gain operational amplifiers are essential in high performance pipelined 1  Pixel Array S/H  ADC  VGA  Processor  Figure 1.1: ADC used in an image sensor ADCs. Techniques like gain-boosting have been adopted to boost the gain to meet the accuracy requirement, however this increases the total power consumption [4, 6, 31]. Low supply voltage around 1.0 V also limits the signal swing that an operational amplifier can achieve, further increasing pipelined ADC design difficulty. On the contrary, successive-approximation-register (SAR) ADCs have benefited a lot from the scaling of device dimensions since most of them are opampless.  Though necessary building blocks like boot-strapped switches,  capacitor arrays and comparator deal with analog signals, their operations are quite digital. Comparing to operational amplifiers, comparators are more robust and have a larger rail-to-rail swing. Performance of SAR ADCs usually rely on the matching of capacitors and improved metal implementation increases this matching, resulting in smaller unit capacitor needed and better performance. Setting time of switched-capacitor circuits is decreased due to reduced capacitance and smaller transistor on-resistance, achieving a higher sampling speed. Active area and total power consumption are reduced in each generation as a consequence of smaller capacitors which still keep the same matching. 10-bit SAR ADCs with a few tens of MS/s has been developed recently with a very low power consumption of just a few mW [8, 10, 24, 33, 36]. Active research on low-power SAR ADCs are still ongoing to further reduce the power of SAR ADCs. However, few ADCs with 12 to 14 bit resolution and sampling rate of a few tens of MS/s using SAR ADC architecture have been reported [25]. For charge  2  redistribution SAR ADCs having a resolution better than 10 bit, matching requirement of the capacitors instead of thermal noise requirement dominates in the design. Higher bit ADCs require better capacitor matching resulting in larger unit capacitor and more bits increase the total number of capacitors needed exponentially. These two requirements cost large active area and high power because of the exponentially increasing total capacitance. For example, a 12-bit conventional binary-weighted charge redistribution SAR ADC with a unit capacitor of 20 fF will have a total capacitance of 82 pF at input node with single-ended configuration, unacceptable silicon cost and total power. So solving this conflict is very important for optimizing the best power and area efficiency of higher resolution SAR ADCs comparing to pipelined ADCs. This research is intended to propose a new charge-redistribution SAR ADC architecture to further reduce the power of a SAR ADC and make it suitable for designing a medium-speed 10-to-14 bit SAR ADC with a reasonable cost and power.  1.2  Organization of the Thesis  This thesis is organized as follows: Chapter 2 gives an overview of ADCs and discusses the specifications used to represent the performance of an ADC. Chapter 3 overviews the conventional charge-redistribution SAR ADC architecture. Chapter 4 presents the proposed architecture. Advantages of the proposed structure as compared to the conventional architecture are discussed. Chapter 5 shows the detailed design of each individual block and layout considerations since matching is important in SAR ADC design.  Chapter 6  presents the post-layout simulation results and measurement results. Chapter 7 concludes this work and summarizes future work.  3  Finally,  Chapter 2  Introduction 2.1  Ideal ADCs and Characterizations  Naturally occurring signals are all analog signals which are continuous both in amplitude and time. An analog-to-digital converter (ADC or A/D converter) is a device that samples and converts these continuous signals into digital codes for further processing by a digital signal processor (DSP). An ADC can be represented using the block diagram in Figure 2.1, where Vin , Vre f and Bout are the analog input signal, voltage reference, and the converted digital output code, respectively. Though a few ADCs use current signal as input, most ADCs use input voltage signals. Since it is not possible to convert the input analog signal to digital codes continuously, an ADC is a sampled-data system, as shown in Figure 2.2 [12]. The sample-and-hold circuit maintains the value of the sampled signal while it is converted to a digital code by the quantizer and encoder. An ideal 2-bit quantizer’s input-output transfer curve is shown in Figure 2.3. Ideal A / D  Vin  converter  Bout  Vref Figure 2.1: Block diagram of an ADC  4  Dgital Control Vin Quantizer  Sample / Hold  Bout  Encoder  Figure 2.2: ADC is a sampled-data system  D igital O utput C ode  11  10  Infinite Resolution 01  00  0 8  1 8  2 8  3 8  4 8  5 8  6 8  Vin Vref  7 8  Figure 2.3: 2-bit quantizer’s transfer curve Input signal within the range of 0 to Vre f is converted to four discrete codes: 00, 01, 10 and 11. A range of input values result in the same digital output code and this ambiguous representation is called quantization error. This quantization error exists even in an ideal ADC and it is a result of using finite resolution digital codes to represent a continuous value. The input signal can then be written as Equation 2.1,  Vin = Vre f · (b1 · 2  1 +b ·2 2 +···+b 2 N  ·2  N)  VLSB /2  Verr  VLSB /2, VLSB = Vre f · 2  5  Verr (2.1) N  Vin  Ideal N  bit Bout  Ideal N  bit  A/ D  D/ A  Verr  Figure 2.4: Model of quantization noise  1  f err ( x)  VLSB  VLSB / 2  VLSB / 2  X  Figure 2.5: Probability density function of Verr  2.1.1  Quantization Noise  As mentioned before, the inherent uncertainty in digitizing an analog value with a finite resolution converter which is known as quantization error exists in every ADC. It is instructive to analyze how this error affects the ADC’s dynamic range. The error is modelled as an additive noise source Verr since it varies with the input signal randomly. Modelling of Verr is shown in Figure 2.4 [16]. Assume the input signal varies within the input range for a long period of time, the quantization error Verr can be considered as a random variable with a uniform distribution between  VLSB /2 and VLSB /2 and the probability density  function (PDF) ferr (x) is shown in Figure 2.5. To calculate the best possible signal-to-noise ratio (SNR), assume Vin is a sinusoidal waveform with the maximum allowable amplitude of Vre f /2. Power of the quantization noise is shown in Equation 2.2 and the SNR is calculated in Equation 2.3. Pnoise =  2 R +• 2 VLSB 1 R +LSB/2 2 • x · f err (x)dx = VLSB LSB/2 x dx = 12  p Verr (rms) = Pnoise = VpLSB 12  6  (2.2)  Table 2.1: Digital output codes for ADCs Decimal 3 2 1 0 -1 -2 -3 -4  Offset Bin 111 110 101 100 011 010 001 000  Signed Bin 011 010 001 000 101 110 111  Thermometer 1111111 0111111 0011111 0001111 0000111 0000011 0000001 0000000  Gray 100 101 111 110 010 011 001 000  Two’s Compl 011 010 001 000 111 110 101 100  P  SNR = 10 · log10 ( Psignal ) noise =  in (rms) 20 · log10 ( VVerr (rms)  =  p Vre f /2 2 p 20 · log10 ( V / 12 ) LSB  (2.3)  = 6.02N + 1.76 dB The equation gives the best possible SNR that an N-bit ADC can achieve.  2.1.2  Output Code  Popular digital codes used for ADC outputs are shown in Table 2.1, including offset binary, signed binary, thermometer, Gray and Two’s complement. Binary code is the most widely used digital output code while some others have their own advantages. In offset binary code, 0 is assigned to the most negative number and others are counted up. Gray code and thermometer code only change by 1 bit from one code to its adjacent code which can help minimize errors happening during transition. Two’s complement code can perform both addition and subtraction by simply using straightforward addition. As long as the final result is within the code range, no overflow hardware is needed [16].  2.1.3  Characterizations  In this section,  some commonly used characterizations describing the  performance of an ADC are introduced. The characterizations can be divided into 7  111  110  110  110 Egain = 1 LSB  101  101  D igital O utput C ode  D igital O utput C ode  Nonmonotonicity  100 Infinite Resolution  011  010 001  DNL=1LSB  100 Missing Code  011  INL=1LSB  Infinite Resolution  010 001  EOS = 0.3 LSB  000  000 0 8  1 8  2 8  3 8  4 8  5 8  6 8  7 8  Vin Vref  0 8  1 8  (a)  2 8  3 8  4 8  5 8  6 8  7 8  Vin Vref  (b)  Figure 2.6: Example of offset, gain error, INL and DNL two categories:  static performance and dynamic performance.  The static  performance is based on the input-output transfer curve like Figure 2.6 and can be described by offset error, gain error, integral non-linearity (INL), differential non-linearity (DNL) and monotonicity. Dynamic performance is described by signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR). Resolution Resolution refers to the number of distinct analog levels corresponding to the digital codes. An ADC with N-bit resolution implies that the converter can resolve 2N distinct analog values. For simplicity, it is usually given in the number of bits. Offset Offset is defined as the deviation of V0...01 from 12 LSB in units of LSBs. V0...01 refers to the analog input value when the digital output transits from 0..00 to 0...01, since transition point is easy to measure. In the transfer curve in Figure 2.6, the offset has a value of 0.3 LSB.  Eos =  V0...01 VLSB 8  1 LSB 2  (2.4)  Gain error Gain error is defined as the full-scale difference between the ideal transfer curve and actual transfer curve in units of LSBs after offset error has been removed. In the transfer curve in Figure 2.6, the gain error is 1 LSB after the offset is removed. It can be considered as the difference between the slope of the actual transfer curve and the slope of the ideal transfer curve. Egain =  V1..1 V0...01 VLSB  (2N  2)  (2.5)  Differential nonlinearity (DNL) DNL is defined as the variation of the difference of two adjacent vertical steps in the transfer curve away from 1 LSB after offset and gain error are removed. Figure 2.6 (b) is the transfer carve of Figure 2.6 (a) after offset and gain error are removed. DNL with a value of 1 LSB is shown in Figure 2.6 (b). With this definition, each output digital code has a DNL. However, some other people [12] define DNL as the maximum of all the DNL values. DNL =  Vb1 ...bN +1 Vb1 ...bN VLSB  1, bi = 0 or 1  (2.6)  Integral nonlinearity (INL) Integral nonlinearity (INL) is defined as the deviation from an ideal infinite transfer curve after the offset and gain error are removed. It can be calculated as the integral of DNL and is measured in units of LSBs. INL with a value of 1 LSB is shown in Figure 2.6 (b). Same as DNL, INL is defined as the maximum of all the INL values in [12]. INL =  Vb1 ...bN VLSB  i  1 , i = 0...N 2  1, bi = 0 or 1  (2.7)  Monotonicity and Missing code If one of the vertical jumps in the transfer curve is less than 0 LSB, the ADC is not 9  monotonic, meaning certain digital output code decreases when the input value increases as shown in Figure 2.6. Non-monotonicity usually occurs when the most significant bit (MSB) does not have sufficient accuracy since it is difficult to make MSB have an accuracy better than ± 0.5 LSB. If the vertical jump is larger than 2 LSBs, certain digital output code will be missing as shown in Figure 2.6. An ADC does not have missing code if its maximum DNL is less than 1 LSB. Convention time The convention time of an ADC is the time needed for generating one digital output code responding to the input. Though some converters have a large latency due to pipelining, they still have a short convention time and can operate at a high sampling rate like the pipelined ADCs. SNDR and SFDR SNDR short for signal to noise-and-distortion ratio describes the dynamic performance of an ADC. It is defined as the ratio of rms value of the sinusoidal output to the rms value of output noise plus the distortion when the maximum input sinusoidal amplitude is applied. An ideal N-bit ADC has no distortion and as discussed in Equation 2.3, it has a SNDR of 6.02N + 1.76 dB. SNDR = 10 · log10 (  Psignal ) PNoise + Pdistortion  (2.8)  SFDR is short for the strength ratio of the fundamental signal to the most strongest spurious signal in the output. SFDR = 10 · log10 (  Psignal ) Pspur  (2.9)  Effective number of bits (ENOB) ENOB is another specification used to describe the dynamic performance which is directly related to SNDR. ENOB is defined in Equation 2.10 and is the actual resolution of an ADC.  10  20  Â-D  18  [*] [*] [*]  14  [∆]  [∆]  10  [▲]  ved rlea Inte ed  SAR  12  [▲]  in Pipel  Resolution (bits)  16  [∆]  8  [■]  Flash [♦]  6 10  100  1k  10k  100k  1M  10M  100M 1G  [■]  10G  Sampling Rate (Hz)  Figure 2.7: Architectures of ADCs  ENOB =  SNDR 1.76 6.02  (2.10)  2.2 Types of ADCs There are many different architectures currently used for realizing ADCs, such as sigma-delta (S  D) ADC, successive-approximation-register (SAR) ADC,  pipelined ADC, flash ADC and time-interleaved ADC. Resolution and sampling frequency of different architectures are drawn in Figure 2.7. Though various architectures have overlap on their specifications, it is critical to choose the proper ADC architecture for a particular application. A poor choice would lead to a sub-optimal result, no matter how well the design is optimized.  11  S/H  comparator  clock  Digital Control  Vref  N-bit D/A converter  Bout  Figure 2.8: Successive approximation register ADC  2.2.1  ADC Architectures  Successive Approximation Register ADCs Figure 2.8 illustrates the architecture of a successive-approximation-register (SAR) ADC. Each bit of the digital output Bout is determined in sequential at each clock cycle based on the output of the comparator and the converted bits. The analog output of the DAC approximates the sampled input while each bit is determined. As a consequence, an N-bit SAR ADC needs at least N clock cycles to accomplish one conversion, which limits the speed it can achieve. The high speed clock needed can either be external or internal generated which separates the SAR ADCs into two categories: synchronous SAR ADCs and asynchronous SAR ADCs. With an external high speed clock, the clock cycle has to be larger than the worst case setting time to ensure proper functioning. This loses potential time savings when the signal is settled beforehand. In the asynchronous SAR ADCs, this problem is solved because as soon as each comparison resolves one bit, it triggers the operation of next bit thereby saving time. SAR ADCs are widely used for data-acquisition system, especially when multiple channels are used by multiplexing the input. The SAR ADC architecture was first utilized in pulse-code-modulation (PCM) systems at Bell Labs in the 1940s. The first commercial SAR ADC was introduced by Bernard Gordon at Epsco in 1954 which had a resolution of 11 bits, a sampling rate of 50 KS/s and a power consumption of 500 W [18]. However, modern SAR ADCs are available in 12  resolution from 8 to 16 bit with sampling rates up to a few tens of MS/s with just a few mW [10, 23, 24, 33, 36]. It is extremely popular in lower power design since its static power can be minimized compared to other architectures [3, 8].  Pipelined ADCs An N-bit pipelined ADC has N stages, which all have the identical function. Each stage has two phases: sampling phase and evaluation phase, and works in turn as shown in Figure 2.9. At sampling phase, stagei samples the output Vi stagei the ith  ith  1  1  of previous  which works in evaluation phase. At evaluation phase, stagei determines  bit by comparing the sampled voltage Vi to ground and then according to the  bit, the reference voltage Vre f is added or subtracted from 2Vi . At the same time,  stagei+1 samples the output of stagei . A voltage transfer curve of each stage is shown in Figure 2.10. The actual voltage vertical jump in Figure 2.10 occurs at the comparator offset value, so the comparator offset needs to be minimized to avoid saturation of the operational amplifier. Although each sampled input signal needs N cycles to process, a new sample is performed in each clock cycle, achieving a high sampling rate comparing to SAR ADCs. Since at each cycle one digital output can be achieved, pipelined ADCs can achieve a very high speed. Pipelined architectures are widely utilized for realizing 8 to 14 bit ADCs with sampling rate of a few MS/s to hundreds of MS/s [5, 29]. These ADCs are widely used for oscilloscope, medical imaging, video, IF sampling, digital cameras, HD TV, etc.  Flash ADCs High speed ADCs are achieved by using flash architectures [21, 28]. The input signal of an N-bit flash ADC is fed to 2N  1 comparators at the same time as  shown in Figure 2.11. The other input of each comparator is connected to a predefined voltage. Voltage difference of two adjacent nodes is 1 VLSB . Within one clock cycle, the input is both sampled by the S/H circuit and compared with the reference voltages. Any comparator connected a reference voltage higher than Vin 13  b1 b2 b3  Vin  xxx  xxx  FF  xxx  FF  FF  FF  FF  stage 1  stage 2  xxx  FF  bN xxx  stage 3  sample  evaluation  sample  (evaluation)  ( sample)  (evaluation)  stage N  xxx  Figure 2.9: Pipelined ADC  Vi +1 out  Vi+1 = 2Vi - Vref ,b i = 1  Vref  Vi+1 = 2Vi + Vref ,b i = 0  Vref  -Vref  Vref  Voffset Vref  Vi  in  -Vref  -Vref  stagei  -Vref  stagei +1  Figure 2.10: Voltage transfer curve of stagei in pipelined ADCs will have an output of 1 and comparator connected to a reference voltage lower than Vin will have an output of 0. Output of all the comparators is a thermometer code shown in Table 2.1 which can be converted to a binary one by an encoder. Flash ADCs are fast comparing to other architectures since they finish one conversion within one clock cycle, but require a large number of comparators. This increases the input load and results in a large area and a big power consumption especially when the number of bit is high. As a result, resolution of a flash ADC is usually no more than 6 bits.  14  Vref  Vin  S/H  R  R  R  R/2  comparator  Encoder    comparator      R/2  Bout  comparator  comparator  Figure 2.11: Flash ADC Time-interleaved ADCs High-speed ADCs can also be realized by operating many ADCs in parallel like in Figure 2.12 – time interleaving. By using M channels in parallel, each channel can operate at a lower frequency by a factor of M. The S/H circuits consecutively sample the input signal and feed it to different sub-ADCs. A multiplexer is used to choose the output digital codes from M sub-ADCs. Time-interleaved ADCs are able to achieve a higher sampling rate with a higher resolution comparing to flash ADCs [11, 14]. Clock jitter is critical in all high-speed ADCs and it is also essential that all channels are well matched.  Sigma-delta ADCs The ADC architectures previous discussed are all Nyquist rate ADCs because they are based on the direct quantization of the input sampled signal. Their Nyquist rate is equal to the sampling rate. Though Nyquist rate ADCs can operate at a fast sampling rate, their resolution is limited to 16 bits due to device matching and 15  S/H  N-bit ADC 1  T1 S/H  M U X  N-bit ADC 2  T2  Bout  Vin S/H  N-bit ADC M  TM  T1  out1  T2 T M  out 2  TM  out M  0  T Figure 2.12: Block diagram of time-interleaved ADCs  circuit non-linearities. Different from the Nyquist rate ADC architectures, a sigma-delta (S  D)  ADC is an oversampling ADC which can achieve a much higher resolution. Oversampling and noise shaping are two key techniques adopted to improve the accuracy. Sampling rate of a sigma-delta ADC is much higher than the Nuquist rate and the ratio is called oversampling ratio (OSR). The idea of a sigma-delta ADC is to trade time for accuracy in amplitude. Each output code is obtained from a series of coarsely quantized values.  It takes advantage of the  high-speed/high-density digital circuits in modern CMOS technologies and relief the requirements on accurate analog circuits. Figure 2.13 shows a block diagram of a sigma-delta ADC and it consists of a sigma-delta modulator and a digital processing part. Over sampling reduces the quantization noise power within the frequency we are interested in and the modulator acts as a low-pass filter for the signal and a high-pass filter for the quantization noise.  More theory of the  sigma-delta modulator can refer to the references [20] and [27]. S D ADCs can achieve a resolution up to 24 bits with a relatively low Nyquist rate and are widely used in audio and instrumentation applications.  16  fs  01001 101  H(Z)  Vin Loop Filter  Quantizer Sigma-Delta Modulator  01001 101  Digital Filter  Decimator  Bout  Digital Processing  Figure 2.13: Block diagram of S  2.2.2  D ADCs  State-of-the-Art Designs  A few state-of-the-art designs are marked in Figure 2.7 and some detailed specifications are listed in Table 2.2. The dashed line approximately represents the state-of-the-art designs. SAR ADCs achieve the best power-efficiency among all the architectures based on the FoM values.  2.3 2.3.1  Performance Limitations Clock Jitter  Sampling clock precision is very important for an ADC since it is a sampled-data system. Precision of the sampling clock determines the accuracy of the sampled value. The clock precision is measured by aperture jitter Dt which is shown in Figure 2.14. Input voltage signal is usually sampled at the rising or falling edge of the clock, so the aperture jitter will bring an uncertainty DV to the sampled value V . DV can be treated as a noise on the input signal which reduces the dynamic range. Assume the input signal is a sinusoid as Vin (t) = 12 Vre f sin(wt). The maximum voltage change rate is equal to  1 2 Vre f w.  17  As a result, DV is calculated in  Table 2.2: State-of-the-art designs  18  Reference NO.  [25]  [3]  Type  SAR  SAR  Jou/Con Time Technology (um) Supply (V) Input range (V) Resolution (bits) Sampling Rate (S/s) ENOB (bits) SNDR (dB) SFDR (dB) Power (mW) FoM (pj-con) Area (mm2 )  JSSC 2011  [29]  [5]  [21]  [28]  [14]  [11]  ISSCC 2008  Pipelined JSSC 2011  Pipelined JSSC 2010  Flash  Flash  VLSI 2010  0.13  0.18  0.04  0.18  1.2  0.6  1  2.4  0.6  12  [19]  [32]  TCASII 2011  Interleaved JSSC 2011  Interleaved JSSC 2011  S  S  CICC 2008  JSSC 2009  0.13  0.09  0.065  0.065  0.18  0.18  1.8  1.2  1.2  1.5  1.2  1.5  3.3  1.2  2.5  0.4  0.6  0.813  1.4  1.44  3.25  10  12  16  5  7  6  10  16  18  45M  100k  800M  250M  3.2G  1.5G  16G  2.6G  60M  8M  10.9  9.3  9.5  12.4  4.54  6.05  4.9  7.8  13.2  17.3  67.1  57.7  59  76.5  29.1  38.2  30.8  48.5  81  105.9  84.7  -  -  100+  -  46.6  37.8  53.8  -  -  3.05  0.0013  105  850  120  204  435  480  8.1  14.7  0.037  0.021  0.18  0.63  4.30  2.05  2.6  0.83  0.25  1.44  0.09  0.125  0.88  -  0.18  1.2  1.47  5.1  1.27  -  D  D  V  clk  Vin =1/2Vref sin(ωt)  ΔV2  ΔV1 S/H  Δt  T  Figure 2.14: Aperture jitter in an ADC Equation 2.11, DV = |  dvin 1 | · Dt = wVre f Dt dt 2  (2.11)  wVre f Dt dvin p |(rms) · Dt = dt 2 2  (2.12)  The rms value of this noise is, DV (rms) = |  Taking this noise into consideration, SNR in Equation 2.3 of an N-bit ADC is recalculated as, V  SNR = 10 · log10 (  2V  ( pre2f )2  f ( 2N pre12 )2 + (  wDtVre f 2 p ) 2 2  )  (2.13)  For example, if a 10-bit ADC wants to achieve an ENOB of 9 bits considering only aperture jitter of the sampling clock, the aperture jitter needs to be smaller than 440 ps if the input signal is a full scale sinusoid at 1 MHz. The aperture jitter  19  sets a limitation to the dynamic range of an ADC can achieve. The faster the sampling rate is and the more bits the converter has, the smaller the jitter will be required.  2.3.2  Noise  Device noise is another important limiting factor in designing an ADC since it sets the minimum noise floor an ADC can achieve. It trades with both speed and power dissipation. Thermal noise and flicker noise are two most important kinds of noise in concern. Since the amplitude of the noise voltage or current in time-domain is random, power spectral density (PSD) Sx ( f ) in frequency domain is usually used to model a noise source. Thermal noise is the consequence of random motion of electronics in a conductor, so it is proportional to the absolute temperature T . The thermal noise of a resistor R is modeled as a series voltage source in Equation 2.14 and is accurate up to 100 THz. One interesting thing is the total output noise power of a resistor is independent of the resistor value when it is connected to a capacitor forming a low-pass filter as in Figure 2.15. SR ( f ) = 4kT R, 0  f  100 T Hz  (2.14)  Modeling the noise of R by a series voltage source VR and we can compute the total output noise power. The transfer function of the low-pass filter is, Vout 1 (s) = VR RC · s + 1  (2.15)  The output power spectral density is, Sout = SR ( f ) · |  Vout 1 (s)|2 = 4kT R · 2 2 2 2 VR 4p R C f + 1  (2.16)  The total output noise power is, Pnoise,out =  Z • 0  4kT R kT df = 4p 2 R2C2 f 2 + 1 C 20  (2.17)  R  R  Vout  Vout  VR 2  C  C  Figure 2.15: Noise in a low-pass filter  M1  C  I 2n  Ro  C  Figure 2.16: Noise of a transistor when connected to a capacitor MOS transistors also exhibit thermal noise and main source of the noise is from the channel. For long channel devices operating in saturation region, the channel noise is modeled by a current source connected between the source and drain. The spectral density of the current source is shown in Equation 2.18 [34]. In2 = 4kT ggm  (2.18)  If the transistor is connected to an capacitor as shown in Figure 2.16, the total output noise power is calculated as, Pnoise,out =  Z • 0  4kT ggm ro2 ·  1 ggm ro kT df = 4p 2 ro2C2 f 2 + 1 C  (2.19)  gm ro is the intrinsic gain of a transistor and is almost constant in a certain technology, so in both situation the total output noise power is mainly determined by the capacitance C. This kT/C noise sets a minimum noise floor that an ADC can achieve without adopting noise shaping method. The total noise power is mainly determined by the capacitance as shown in Equation 2.17 and Equation 2.19 and increasing the capacitance will decrease the total output noise power. However, larger capacitance results in slower speed or larger power consumption. Taking the kT /C noise into consideration, signal-to-noise ration (SNR) is recalculated as, 21  85 80  SNR (dB) @Vpp=1 V  75 70 65 60 55 50 45 40 −3 10  −2  10  −1  10 C (pF)  0  10  1  10  Figure 2.17: SNR vs C assuming Vpp = 1 V  SNR = 10 · log10 (  Vp2C Psignal ) = 10 · log10 ( ) Pnoise 2 · kT  (2.20)  Assume in room temperature (300 K) with Vpp = 1 V , the SNR in relation to C is plotted in Figure 2.17. To achieve a higher SNR, either a larger C or a larger Vpp is needed. In both cases, power increases.  2.3.3  Mismatch  In reality, two identical devices in schematic suffer from a mismatch due to manufacturing process variations and gradients in the working environment. Dimension and doping level of resistors, transistors and diodes suffer random variations during manufacturing. Gradients like temperature on a chip also cause variations of two nominally-indentical devices.  Mismatch causes offset,  non-lineaity, etc, which limits the ADC accuracy. For example in a pipelined ADC, an accurate gain of 2 is needed and it is achieved by two identical capacitors forming a negative feedback with an operational amplifier. Accuracy of 22  this gain is determined by matching of this two capacitors when gain of the operational amplifier is sufficient. In modern technology, 0.1% mismatch of two closed placed capacitors is achievable. Mismatch of a capacitor is considered inversely proportional to its area [13]. In order to achieve high SNR, larger capacitors are used. Larger capacitance results in larger area, larger power and lower speed. A calibration method can be used to reduce the requirement of the matching. Typically, in medium-to-high accuracy Nyquist ADCs, matching of devices instead of thermal noise determines the value of the capacitors being used.  23  Chapter 3  SAR ADC Architectures 3.1  Conventional Charge-redistribution Architectures  Successive-approximation-register (SAR) ADCs dominate the market of medium-resolution (8 to 14 bits) with medium-speed (up to a few MS/s) ADCs, such as AD7277, AD7278, AD7625, and AD7298. Though some SAR ADCs use operational amplifiers [17, 26], most of them are opamp-less which makes SAR ADCs benefit a lot from the advance of fabrication technologies. The feature size scaling has enabled the SAR ADCs to achieve a higher sampling speed up to a few hundreds of MS/s [22, 24, 36] while on the other hand makes it more difficult to design pipelined ADCs due to low intrinsic gain of short channel devices and low supply voltage. With no operational amplifier inside, SAR ADCs can easily achieve a rail-to-rail signal swing, which releases the requirement of the sampling capacitance value. Recently, SAR ADCs have been trying to take the place of the pipelined ADCs running at a few tens of MS/s which are extensively used in wireless networks and video applications since SAR ADCs consume less power and have a smaller area [24, 25, 33, 36]. A SAR ADC is typically made of four building blocks: a sample-hold (S/H) circuit,  a  digital-to-analog  converter  (DAC),  a  comparator  and  successive-approximation register (SAR) as illustrated in Figure 3.1.  a The  continuous input signal Vin is first sampled by the S/H circuit and later the sampled value VSH is converted to digital codes shown in Table 2.1. The sampled 24  value VSH is converted to digital code as the output of the DAC: VDAC approximates the sampled value VSH under the control of the SAR logic. Binary search algorithm is used in this approximation procedure because it is most time efficient in searching and easiest to implement. As we know, a voltage within the range of ground to Vre f can be written as Equation 3.1. VSH = (b1 · 12 + b2 · 212 + . . . + bN · 21N ) ·Vre f +Verr 1 2N+1  0  |Verr |   ·Vre f  (3.1)  The binary search algorithm is used to determine b1 to bN one by one. The flow-diagram of a basic try-and-correct binary search algorithm is shown in Figure 3.2 and works in the following way, 1. Input voltage Vin is sampled by the S/H circuit as VSH . All output bits are reset to zero. 2. Try b1 to be 1 and compare the output of the DAC with the sampled value VSH . Comparison result is sent to the SAR logic. 3. Correct bi to be 1 or 0 according to the last comparison result and try bi+1 to be 1 1. VDAC is adjusted to Vi + 2i+1 Vre f or Vi  1 V 2i+1 re f  to approximate VSH .  4. Repeat step3 N-1 times for a N-bit SAR ADC and finally the input digital code of the DAC is the converted output code of the SAR ADC. A transfer waveform of a 4-bit SAR ADC that shows how this procedure works is drawn in Figure 3.3. The black line is the input sampled value VSH and the red line is the output of DAC: VDAC , approximating the sampled value at each clock cycle.  Each bit of output digital code is determined according to the  comparison result. For example in Figure 3.3, the converted output digital code is 1010.  25  Vin  VSH  S/H  CS  comparator  VDAC  Bout SAR Logic  N-bits DAC Vref  Shift Register  Clock Generator  clock  Figure 3.1: Block diagram of a SAR ADC  START  i = 1, b1 = 1, b2  b VDAC = ( 1 + 2  N +1  =0  bN bN +1 + )Vref 2N 2N  VDAC > VSH  NO  YES  bi +1 = 1  VDAC = (  b1 + 2  bN bN +1 + )Vrref 2N 2N  bi = 0, bi +1 = 1 VDAC = (  b1 + 2  bN bN +1 + )Vrref 2N 2N  i = i +1  NO  i>N YES  STOP Figure 3.2: Binary search algorithm for SAR ADCs 26  15 /16  VDAC  Vref  7/8 13 /16  3/ 4  1  Vref 2  VSH  1/ 2  11/16  5 / 81  0  0  9 /16  7 /16  3/8  5 /16  1/ 4  3 /16  1/ 8  1/16  0  1  2  3  4  T  Figure 3.3: Voltage transfer curve of a SAR ADC  S/H  Vin Q C  CS  VDAC C  2  2C  SAR N- 2  C 2  N-1  C  switches  bN +1 bN  bN -1  b2  b1  Vref  Figure 3.4: Charge redistribution SAR ADCs  3.1.1  Binary-weighted Charge-redistribution  Among all different kinds of SAR ADCs, the charge redistribution SAR ADC is most welcome because of its simplicity and low-power characteristic. Figure 3.4 illustrates a simple N-bit charge redistribution SAR ADC where the DAC in Figure 3.1 is made of a binary-weighted capacitor array and a series of switches. Due to charge sharing and redistribution of the binary-ratioed capacitors, this binary-ratioed capacitor array works as a N-bit DAC and that’s why it is called 27  Q C  C  VDAC  SAR  2N- 2 C  2C  2  N-1  C  switches  bN +1 bN  bN -1  b2  Vref  b1  Vin  Figure 3.5: A SAR ADC with S/H merged into the capacitor DAC binary-weighted architecture. The output voltage of the DAC: VDAC is calculated in Equation 3.2. (VDAC  b1 ·Vre f ) · 2N 1C + · · · + (VDAC  bN+1 ·Vre f ) ·C = 0  VDAC = (b1 · 12 + b2 · 212 + · · · + bN · 21N + bN+1 · 21N ) ·Vre f  (3.2)  In real design, the S/H circuit can be merged into the capacitor DAC as in Figure 3.5, using the capacitor array as the sampling capacitor CS . This is how it works: in the sampling phase, the bottom plates of all the capacitors are connected to the input signal while the top plates are connected to ground; then in the conversion phase, the top plates are left floating and the bottom plates are switched to either ground or Vre f according to the control bit bi . Since the internal node Q is left floating, total charge at Q keeps constant during the whole convention phase. The output of the DAC is then calculated as Equation 3.3. Instead of being compared to the sampled value VSH , VDAC is compared to ground. Voltage transfer curve of this SAR ADC is modified in Figure 3.6.  28  Vref 2 1/ 4 1/ 8 1/16  0  -  Vref 2 0  1  0  1  0  1  2  VDAC  3  4  T  Figure 3.6: Transfer curve when S/H circuit is merged into DAC  N  Â (VDAC  i=1  bi ·Vre f ) · 2N iC + (VDAC = (0  bN+1 ·Vre f ) ·C  Vin ) · (C +C + · · · + 2N 1C)  VDAC = (b1 · 12 + b2 · 212 + · · · + bN · 21N + bN+1 · 21N ) ·Vre f  (3.3) Vin  For SAR ADCs with a resolution higher than 8-bit, differential circuits are extensively used to suppress the noise from supply and substrate.  Power  consumption of the DAC is determined by how much energy is consumed from the Vre f during the switching procedure.  Figure 3.7 shows the switching  procedure and energy consumption of a 3-bit SAR ADC with differential configuration and binary-search algorithm in Figure 3.2. Switches in the two branches are fully symmetric, so analysis of single-ended circuit is adequate for simplicity. The energy consumed for each bit is marked in the figure and for a N-bit SAR ADC having the similar configuration, the energy consumed in calculated in Equation 3.4.  29  S/H energy wasted  energy wasted on wrong trial  Figure 3.7: Switching procedure with differential configuration [23]  Qtotal = ÂNi=1 (2N i ·C + bi · 2N i ·C) ·Vre f Etotal = Qtotal ·Vre f = ÂNi=1 (2N i ·C + bi · 2N i ·C) ·Vre2 f  (3.4)  Accuracy of the SAR ADCs is determined by the sampling accuracy, comparator accuracy, settling accuracy, noise, matching of the capacitors, etc. And usually matching of the capacitors dominates since other factors can be reduced with proper design while matching is limited by manufacturing.  In  modern technology, matching of two close spaced and well layout capacitors can be better than 0.1%. To improve matching, either larger capacitor area has to be used or better technology has to be chosen. However better technology like mixed-signal process with metal-insulator-metal (MIM) capacitor is more expensive than simple digital process which only has metal-oxide-metal (MOM) capacitor. Larger capacitor area results in bigger input load, longer settling time and larger active area. Binary-weighted architecture is most welcome because all the capacitors have an integral multiple of unit capacitor and are all connected straightforward, which results in a good matching between each other. For a N-bit differential conventional binary-weighted SAR ADC, the total number of unit capacitor needed and total input capacitance are calculated in Equation 3.5. This exponential increased number of capacitors limits its use in 30  P  LSB array C  Cbri =  C  2  N/ 2-1  2N/ 2 C 2N/ 2 - 1  Q C  C  2C  MSB array 2N/ 2-1 C  SAR  switches  bN +1 bN  bk  bj  Vref  b1  Vin  Figure 3.8: Split-capacitor SAR ADCs ADCs with a higher resolution. Ctotal = 2 · (C +C + 2 ·C + · · · + 2N Cin = C +C + 2 ·C + · · · + 2N  3.1.2  1 ·C) 1 ·C  = 2N+1 ·C  (3.5)  = 2N ·C  Split-capacitor Charge-redistribution  As you can see from Equation 3.5, both the total capacitance and the input capacitance increase exponentially with the number of bits N, which costs area and power and limits the speed. To decrease the total capacitance and reduce the power, the split-capacitor architecture in Figure 3.8 was invented. By splitting one binary-weighted capacitor array in Figure 3.5 into two or more sub-arrays and connecting them by the bridge capacitor Cbri , the total capacitance are significantly reduced while keeping it have the same function. Figure 3.8 shows a split-capacitor SAR ADC with two sub-arrays (MSB array and LSB array) and has a similar try-and-correct switching procedure in Figure 3.2. Though all the capacitors are not binary-ratioed, voltage change at node Q due to the switching of each capacitor are still binary-weighted with the attenuation help from the bridge capacitor Cbri . Voltage value at node Q can be calculated as Equation 3.6. As you can see, it has exactly the same function as the binary-weighted architecture shown in Figure 3.5.  31  N  Vin · (C + · · · + 2 2 (VP  1C) N  VQ ) ·Cbri = Â (VP i=k  j  = Â (VQ i=1  N  bi ·Vre f ) · 2 2 iC + (VQ N  bi ·Vre f ) · 2 2  1+k iC + (V P  Vp ) ·Cbri  bN+1 ·Vre f ) ·C  ) VQ = (b1 · 12 + b2 · 212 + · · · + bN · 21N + bN+1 · 21N ) ·Vre f N  (3.6)  Vin N  Total capacitance and input capacitance are 2 2 +2 · C and 2 2 · C respectively,  instead of 2N+1 · C and 2N · C in Equation 3.5. However, the bridge capacitor Cbri  has a fractional multiple of the unit capacitor, resulting in bad matching with other capacitors. Also parasitic capacitance at node P brings in mismatch between the LSB array and the MSB array, which does not exist in binary-weighted architecture. Parasitic capacitance at node Q in split-capacitor architecture or binary-weighted architecture only causes gain error. For example, if there is a equivalent parasitic capacitance CQ connected between node Q and ground in Figure 3.5, the output voltage of the DAC is modified as Equation 3.7. However, the split-capacitor architecture having the same function as the binary-weighted architecture relies on fact that the equivalent capacitance of the bridge capacitor in series with the left capacitor array equals to one unit capacitor. However, bad matching of the fractional bridge capacitor and the parasitic capacitance at node P make the split-capacitor architecture’s function varies from the original one, resulting in non-linearity and limiting the accuracy the ADC can achieve. VDAC = K · [(b1 · 12 + · · · + bN · 21N + bN+1 · 21N ) ·Vre f K=  3.2  Vin ] (3.7)  2N C 2N C+CQ  Modifications on Conventional Architectures  The binary-weighted SAR ADC and split-capacitor SAR ADC discussed forgoing are two conventional architectures. A lot of modifications have been proposed on this two architectures to further reduce cost and power.  32  sample  Phase1 Phase2 Phase3 Phase4 Phase5  V+  VREF 4  Vcm VREF 4  V-  1  11100->11010 00011->00101  1  0  1  0  Figure 3.9: Waveform of the conventional switching procedure  3.2.1  Switching Procedures for Charge-redistribution  Primary sources of the power consumption of a SAR ADC are the SAR digital control logic, comparator, reference generator and the capacitor DAC. Since total capacitance in the binary-weighted architecture is exponential to the number of bits, dynamic power of the DAC usually dominates the total ADC power. In terms of energy, the conventional switching procedure in Figure 3.3 is not very efficient. Figure 3.9 is a waveform of the comparator two inputs in a fully differential SAR ADC like Figure 3.7 with the convenetional switching procedure. Switches on both sides are fully symmetric and can be either upward(switch from 0 to Vre f ) or downward(switch from Vre f to 0).  As explained forgoing, the conventional  switching procedure is based on a try-and-correct binary search, which means it may not be energy-efficient when the trial is unsuccessful. For example, trial is not correct at the red circle in Figure 3.9, meaning the previous bit assumption has to be corrected before continuing with the next bit. Two capacitors have to be switched from Vre f to 0 and two other capacitors have to be switched from 0 to Vre f in this situation as the red arrow shows in Figure 3.7, wasting energy. In order to further reduce the power of a SAR ADC, different kinds of energy-efficient architectures and switching procedures have been proposed. Among those, two switching procedure: monotonic switching also known as set-and-down method from [23] and VCM -based method from [36] stand out. The monotonic switching procedure claims to reduce the power consumption of the  33  Vin Vref SN .11  VCM  SN .10  SN .9  SN .7  SN .8  SN .5  SN .6  SN .4  SN .3  SN .2  SN .1  C  C  2C  2 2 C 2 3 C 24 C 25 C 26 C 27 C 28 C  29 C  C  C  2C  2 2 C 2 3 C 24 C 25 C 26 C 27 C 28 C  29 C  SP.11  SP.10  SP.5  SP.1  S N .1  S N .11  b1  b10  SAR VCM  SP.9  SP.8  SP.7  SP.6  SP.3  SP.4  SP.2  S P.1  S P.11  Vref Vip  Figure 3.10: Differential architecture with conventional switching procedure Vref  Vin  SN .2  SN .1  SN .9  SN .8  C  C  2C  2 2 C 2 3 C 24 C 25 C 26 C 27 C 28 C  C  C  2C  2 2 C 2 3 C 24 C 25 C 26 C 27 C 28 C  SN .7  SN .6  SN .5  SN .4  SN .3  S N .1  S N .9  b1  b10  SAR Vip  SP.9  SP.8  SP.7  SP.6  SP.5  SP.4  SP.3  SP.2  SP.1  S P.1  S P.9  Vref  Figure 3.11: Differential architecture with monotonic switching procedure DAC by 81% without adding switches or capacitors and reduce the total capacitance by 50%. The VCM -based method claims to reduce the power even more by 30% comparing to the monotonic switching and also reduce the capacitance by 50%.  No price is paid for these two switching procedures  comparing to the conversional switching procedure shown in Figure 3.2. Monotonic Switching (Set-and-down Method) Configuration of a binary-weighted SAR ADC with monotonic switching has a little difference from a conventional one. Figure 3.10 shows a fully differential  34  conventional binary-weighted SAR ADC while Figure 3.11 shows another one with the monotonic switching procedure. With monotonic switching, input is sampled at the top plates of the capacitors while all the bottom plates are connected to Vre f and only downward transition is used with a n-type transistor. Since with the same transistor size, n-type transistor has a smaller on-resistance only about one third of a p-type transistor due to higher mobility of electrons. This speeds up the settling of the DAC, increasing the speed. Further more, the first comparison is done without switching of any capacitor. This allows the SAR ADC only need nine times of capacitor switching, making the total capacitance only half of the conventional one as shown in Figure 3.11. The modified switching flow diagram is drawn in Figure 3.12 and a switching procedure of 3-bit showing how it works is shown in Figure 3.13. Each time, only one capacitor is switched from Vre f to ground according to last comparison result, saving energy. Waveform of the monotonic switching procedure is drawn in Figure 3.14. The common-mode voltage of the two comparator inputs V+ and V gradually decreased from VCM to ground, requiring the comparator have a larger input common range while in conventional architecture, the common-mode value keeps constant. The total energy consumed in calculated in Equation 3.8. N 1  Qtotal = Â [ b2ii · (b1 · 2N i=1  + b2ii · (b1 · 2N  1 +···+b  1 +···+b  i ·2  N 1 i + 2N 2 i + · · · + 1) ·CV i ·2 re f  N 1 i + 2N 2 i + · · · + 1) ·CV ] re f  (3.8)  Etotal = Qtotal ·Vre f VCM -based Switching Method The idea of the monotonic switching method is to do the first comparison without any switchings and foresees the switching of next bit according to the last comparison result. Capacitors are switched to ground only when it is necessary.  35  START i = 1, b1 N = 0 V+ = Vip ,V- = Vin  V+ > V-  NO  YES  bi = 1 V+ = V+ - Vref / 2i , V- = V-  bi = 0 V- = V- - Vref / 2i , V+ = V+  i = i +1  NO  i>N YES  STOP  Figure 3.12: Flow diagram of the monotonic switching  S/H  Figure 3.13: Monotonic switching procedure [23]  36  sample  Phase1 Phase2 Phase3 Phase4 Phase5  V+ VREF 2  11000->11000 00000->00100  Vcm  VREF 4  V1  1  1  0  0  Figure 3.14: Waveform of monotonic switching Only downward or upward transition is needed in the monotonic switching. If the same idea applies to the convention architecture in Figure 3.10, that results in the VCM -based switching method. In the sampling phase, the input is sampled on the bottom plates while the top plates are connected to the common-mode voltage VCM . After the sampling phase, top plates are left floating and the bottom plates are switched to the common-mode voltage, leaving V+ = Vip and V = Vin at the comparator input nodes. The most significant bit (MSB) is determined by directly comparing  Vip and  Vin . This comparison result foresees the switching  of the next bit, so energy is consumed only what is needed to drive the bottom plates from common-mode voltage to Vre f or ground. Since the MSB capacitor is not required any more, it can be removed. The next N an N  1 bits are determined with  1-bit capacitor array, reducing the total capacitance by half. Comparing to  the conventional binary-search, it only needs N  1 more switches to reset the  bottom plates of all the capacitors to the common-mode voltage after the sampling phase. The flow diagram of this switching method is shown in Figure 3.15 and a waveform of the switching method is shown in Figure 3.16.  A switching  procedure of a 3-bit SAR ADC with VCM -based method is shown in Figure 3.17.  37  START i = 1, b1 i = 0 V+ = -Vin , V- = -Vip  V+ > V-  NO  YES  bi = 0  bi = 1  1 1 V+ = V+ - i +1 Vref ,V- = V- + i +1 Vref 2 2  1 1 V+ = V+ + i +1 Vref ,V- = V- - i +1 Vref 2 2  i = i +1  NO  i>N YES  STOP  Figure 3.15: Flow diagram of VCM -based switching  sample  Phase1 Phase2 Phase3 Phase4 Phase5  Vip  VREF 4  Vcm VREF 4  Vin  1  11000->11010 00011->00001  1  0  1  0  Figure 3.16: A waveform of VCM -based switching  38  VCM 2C  C  C  2C  C  C  Vip -Vin >3Vref /4?  VCM VCM C  2C  2 (1 / 8)CVref  Yes  C  Vref Vref VCM Vref VCM  Vip -Vin > Vref / 2? 2C  Vin Vin Vin 2C  VCM VCM  2C  C  VCM VCM VCM  C  C  2C  S/H  C  C  Vref VCM VCM  2 (5 / 8)CVref  Yes  C  2C  C  2 (1 / 2)CVref  C  C  2C  C  C  Vip -Vin > Vref / 4?  Vref Vref  C  VCM VCM VCM  2C  No  Vip > Vin?  C  Vip Vip Vip  C  2 (1 / 2)CVref  VCM VCM  2C  C  C  2C  C  C  No  Vref VCM VCM 2C  2C  C  C  C  C  VCM VCM  Vip -Vin >-Vref / 4?  2 (5 / 8)CVref  Yes  Vref VCM Vip -Vin >-Vref / 2?Vref Vref VCM 2 (1 / 8)CVref  No  2C  C  C  2C  C  C  Vip -Vin >-3Vref / 4?  VCM  Figure 3.17: Switching of a SAR ADC with VCM -based switching Ceq = C CP  LSB array C  C  2  S 2,m  bN +1 bN  Cbri  P  N/ 2-1  S 2,1  bk  MSB array Q  CQ  C  C  S1, j  bj  SAR  2N/ 2-1 C  2C  S1,1  b1  Vref  Vin  Figure 3.18: A split-capacitor SAR ADC with parasitic capacitance  3.2.2  Calibration for Split-capacitor Architecture  Though the split-capacitor architecture significantly reduces the total capacitance, mismatch of the bridge capacitor Cbri and parasitic capacitance CP at the LSB array limit its accuracy. Usually split-capacitor SAR ADCs need calibration to achieve the same accuracy comparing to a binary-weighted one, which will consume extra power. Some recent published calibration methods [3, 7, 35] are discussed here. Figure 3.18 shows a single-ended split-capacitor SAR ADC including parasitic capacitance at node P and Q. Major source of the parasitic capacitance is the capacitor between the top plates, metal routings and the substrate, so the parasitic capacitance can be modeled as CP and CQ directly connected to ground. If we use  39  10.5  10  ENOB  9.5  9  8.5  8  7.5  0  0.5  1 1.5 2 Parasitic capacitance (C)  2.5  3  Figure 3.19: ENOB vs CP for a 10-bit SAR ADC CsumM and CsumL as a representative of the total capacitance of the MSB array and LSB array respectively. The output of the DAC: VDAC can be recalculated as, j  VDAC =  Cbri ( Â S1,i ·2i i=1  1+  m  Â S2,i ·2i  i=1  1 )C+(C sumL +CP )  m  Â S2,i ·2i 1C  i=1  Cbri (CsumL +CsumM +CP +CQ )+(CsumL +CP )(CsumM +CQ )  ·Vre f  (3.9)  CQ and CP in the denominator only cause a gain error and the error is equally distributed between the quantization intervals of the DAC. However, CP in the numerator results in code-dependent error and variation of Cbri from results in nonlinearity.  2N/2 C 2N/2 1  also  Parasitic capacitance If only the parasitic capacitance CP is considered and everything else is ideal for a 10-bit split-capacitor SAR ADC, the ENOB value verses CP value is drawn in Figure 3.19.  40  10.5 10 9.5  ENOB  9 8.5 8 7.5 7 6.5 6  0  5  10 15 20 Accuracy of Bridge Capacitor (%)  25  30  Figure 3.20: ENOB vs DCbri for a 10-bit SAR ADC  LSB array  VCM  Compara  Vin Vref  MSB array  comparator  VCM  Figure 3.21: Modified split-capacitor SAR ADC [3] Mismatch of the bridge capacitor If only the variation of Cbri is considered and everything else is ideal for a 10-bit split-capacitor SAR ADC, the ENOB value in relation of DCbri is shown in Figure 3.20.  41  P  P Cp  Cp  Figure 3.22: Modified split-capacitor SAR ADC [35] Calibration I: Bridge capacitor being unit capacitance [3] In Figure 3.21, the bridge capacitor Cbri is implemented by a unit capacitor instead of a fractional multiple value and the last unit capacitor C in the LSB array is removed. When the MSB array operates, the top plates of the LSB array are connected to the common-mode voltage. When the LSB array starts to operate, the top plates are left floating. Voltage change due to switching of the first bit in the LSB array is exactly half of that of the last bit in the MSB array. This configuration improves the matching of the bridge capacitor Cbri by having a unit value, however it is still vulnerable to the parasitic capacitance CP and also it causes 1 LSB gain error [3]. Calibration II: Voltage feedback charge compensation [35] In Figure 3.22, a voltage feedback charge compensation is implemented to cancel the conversion nonlinearity due to the parasitic capacitance CP in a splitcapacitor SAR ADC. With parasitic capacitance at node P, voltage change due to switching of the capacitors in the LSB array reduces because certain charge is stolen by CP . The stolen charge can be represented by (DVideal,P  DVreal,P ) ·CP , so  a positive charge feedback is applied at node P to compensate for the stolen charge. However, the feedback loop introduces an amplifier which we try to avoid in the  42  CP  LSB array C  P  Cbri > (16 / 15)C  MSB array Q  C  8C  C  CC  b8  bk  bj  C  SAR  8C  b1  Vref  Vin  Figure 3.23: Modified split-capacitor SAR ADC [7] low-power SAR ADC design and this extra circuit consumes an extra static power. Cablibration III: Tunable capacitor for compensation [7] In Figure 3.23, the bridge capacitor Cbri is slightly larger than  2N/2 C 2N/2 1  and a  tunable capacitor Cc is added in the LSB array. Calibration is done in foreground by tuning the variable capacitor Cc until the equivalent capacitance of the bridge capacitor in series with the LSB array equals unit capacitance. This calibration method relies on the accuracy of the comparator and there is a conflict between the tuning range and the step value of the variable capacitor Cc .  43  Chapter 4  The Proposed SAR Architecture The binary-weighted architecture in Figure 3.10 has a good linearity but is limited by the total capacitance with resolution higher than 10-bit.  Ideally the  split-capacitor architecture in Figure 3.8 is suitable for higher resolution SAR ADCs with optimized power consumption and active area. However in reality, the poor accuracy of the bridge capacitor and the parasitic capacitance effect destroy the defined binary-scaled charge redistribution and lead to nonlinearity. Even with the compensation methods proposed in [3, 7, 35], the design resolution is limited to 10-bit. This work presents a new split-capacitor architecture where the matching of the bridge capacitor is significantly improved and the the parasitic capacitance has a way to be compensated. To further reduce the power, the monotonic switching Vref / 16  C - CP  S9N  C  S8N  S7N  S6N  2C 4C 8C  S5N  16C  Vref  CQ  C  S4N  C  S3N  2C  S2N  4C  S1N, S2N ~ S9N  S1N  8C  clkc  CP  CP  C9  C - CP  C S9  C8  Cbri = 32C  P  LSB array  C7  C6  2C 4C 8C S8  S7  S6  S5  Switch  MSB array  Q C4  C3  C2  C1  C  C  2C  4C  8C  S4  S3  S2  C5  16C  Vin  Bootstrapped  CQ  SAR  Vip S1, S2 ~ S9  S1  CP , CQ are parasitic  Vref / 16  Vref  Figure 4.1: Proposed split-capacitor architecture  44  capacitors  method in [23] is adopted. Figure 4.1 shows the proposed split-capacitor SAR ADC architecture. Equivalent capacitance of the LSB array in series with the bridge capacitor Cbri is 16C, two times the largest capacitor 8C in the MSB array. To keep the original binary-weighted function, the reference voltage of the LSB array is accordingly adjusted such that the weight of the first bit in the LSB array is half that of the last bit in the MSB array during the charge redistribution. Bottom plates of all the capacitors in the MSB and LSB arrays are connected to either ground or reference voltages. In what follows, for simplicity a single-ended version of the DAC is discussed, however, note that the DAC is fully differential. Assuming one capacitor of the DAC is switched from the reference voltage to ground while all the other capacitors are kept connected to references, voltage change at node Q would be, 8 24 iC > < C+C+2C+4C+8C+16C ·Vre f 1  i  4 DV = > : Vre f 29 iC 5i9 C+C+2C+4C+8C+16C · 25  (4.1)  The input signal is sampled at node Q while all the bottom plates of the  capacitors are connected to reference voltages. After the sampling switch is off, bottom plate of the capacitor in the MSB array and LSB array is switched to ground if its control bit Si (bi ) is 1, the voltage at node Q will be, Vre f 1 1 1 VQ = VDAC = (b1 · + b2 · 2 + · · · + b10 · 10 ) · 2 2 2 2  Vin  (4.2)  In this way, the split-capacitor DAC in Figure 4.1 works just like the binaryweighted capacitor array in Figure 3.11, except the reference voltage Vre f is halved which means the input range is halved. The proposed architecture with monotonic switching procedure [23] operates as follows. In the sampling phase, the input signal is first sampled on the top plates of the MSB array while all the bottom plates in MSB and LSB arrays are connected to reference voltages.  Boot-strapped switch is used to reduce the  settling time and increase the accuracy. After the sampling switch is turned off, the conversion phase begins. The first comparison is performed to find out the sign (MSB) of the difference of the input Vip and Vin . Based on the comparison 45  result, only the highest value capacitor in the MSB array (on the higher voltage side in the differential circuit) is switched to ground and all the others remain unchanged. Then the comparator preforms the second comparison to determine the second most significant bit. This time the second highest capacitor in the MSB array (on the higher voltage side in the differential circuit) is switched from reference voltage to ground. This procedure repeats for N-1 times until the last bit bN is determined. For each bit, only one capacitor is switched from reference voltage to ground and the capacitors in the LSB array have a much smaller reference voltage value which significantly reduces the power.  4.1  Matching Improvement of the Bridge Capacitor  Ideally, the voltage change at node Q determined by the least significant bit in MSB array should be exactly two times that of the most significant bit in the LSB array. However, taking the mismatch of the bridge capacitor into account, this ratio is not exactly 2. To calculate the amount of the variation in the conventional split-capacitor architecture and in the proposed architecture, mismatch of a capacitor is considered inversely proportional to its area [13]. It should be noted that capacitors which are integer multiple of the unit capacitor are less prone to mismatch as compared to those that are a fractional multiple of a unit capacitor. For a 10-bit split-capacitor SAR ADC, the bridge capacitor value is the conventional one and 32C in the proposed one. If we assume the mismatch of d % then the 32C capacitor has a mismatch of Cbri1 =  32 31 C · (1 + d %)  Cbri2 = 32C · (1 +  pd %, 32  32 31  32 31 C  C in has a  (4.3)  pd %) 32  Variation of this ratio in the conventional one and the proposed one are compared in Figure 4.2. A Gaussian distribution of the mismatch is assumed, and an average ENOB out of 20 is drawn in Figure 4.3. As is shown, mismatch of the bridge capacitor has significantly smaller impact in the proposed architecture.  46  2.06 Conventional Proposed Ideal  Voltage Change Ratio  2.04  2.02  2  1.98  1.96  1.94 −0.025 −0.02 −0.015 −0.01 −0.005 0 0.005 Mismatch Factor δ %  0.01  0.015  0.02  0.025  Figure 4.2: Variation of the ratio from two 10 9.8  Average ENOB out of 20  9.6 9.4 9.2 9 8.8 8.6 8.4  1  2  3  4  5  6 δ value  7  8  9  10 −3  x 10  Figure 4.3: ENOB considering the bridge capacitor mismatch  4.2  Compensation of the Parasitic Capacitance  Conventional split-capacitor SAR ADC is sensitive to parasitic capacitance CP at node P as shown in Figure 3.19. However, in the proposed architecture there are two ways that can be used to compensate the parasitic capacitance CP . As you can see from Figure 4.1, there is a unit capacitor C directly connected to ground in the LSB array which needs to be able to switch to ground or reference in the conventional architecture. If the parasitic capacitance is not bigger than the unit capacitance, the parasitic capacitance CP can be subtracted from the unit capacitor, 47  10.4  Proposed Conventional  10.2  10  Accuracy = 0.1 CP  ENOB (bit)  9.8  9.6  Parasitic Value = CP  9.4  9.2  9  8.8 0.1  0.2  0.3  0.4  0.5 0.6 Parasitic Value CP (C)  0.7  0.8  0.9  1  Figure 4.4: ENOB improvement in the proposed architecture adjusting it to be C C  CP . The parasitic capacitance and the adjusted capacitor  CP together act as the last unit capacitor. If the parasitic capacitance value is  equal to one unit capacitance, the last capacitor connected to ground can just be eliminated. If the parasitic capacitance is larger than the unit capacitance, it can not be subtracted. However, an extra capacitor Cc can be added in the LSB array with its bottom plate connected to the ground and the reference voltage of the LSB array can be then adjusted to be sightly bigger to keep the voltage change still binary-ratioed. The value of Cc can be calculated according to the reference voltage change in the LSB array. Since the adjusted or added capacitor has an fractional multiple value, its accuracy is assumed to be only 10% of the original value CP . Its improvement on the ENOB in a 10-bit split-capacitor SAR ADC is shown in Figure 4.4. Since in the proposed architecture an extra voltage reference with a value of Vre f 16  is needed, its accuracy is important to guarantee the performance of the SAR  ADC. ENOB versers the reference  Vre f 16  accuracy is drawn in Figure 4.5. For this  10-bit SAR ADC, an accuracy better than 3% is needed. The voltage reference accurate resistor ladder.  Vre f 16  can be generated by a voltage divider made of an  The resistor ladder shown in Figure 4.6 made of  48  10.2 10 9.8 9.6  ENOB  9.4 9.2 9 8.8 8.6 8.4 8.2  0  0.5  1  1.5  2 2.5 3 Reference Accuracy (%)  3.5  4  4.5  5  Figure 4.5: ENOB vs reference Vre f /16 accuracy polysilicon [30] is verified to have an accuracy of 11-bit which is higher than the requirement of this design. To guarantee the accuracy, three considerations on designing the resistor ladder are taken. First, non-silicided poly is preferred because the thin layer of silicide deposited on polysilicon experiences a relatively big thickness variation from one end to the other. Second, metal contacts over the resistor ladder are avoided since resistance of a contact is poor defined. Third, contacts need to be well aligned to minimized the disturbance of the flow of the current.  4.3  Reduced Power Consumption of the DAC  Switching energy of the conventional binary-weighted architecture,  the  monotonic-switching architecture and the proposed architecture are calculated using the equation derived and are compared in Figure 4.7. The switching energy of each conversion is code-dependent, assuming that output codes are evenly distributed, the proposed DAC consumes only 1% of the energy of the DAC of the conventional binary-weighted structure and 5% of that of the DAC with the monotonic switching procedure.  49  Vref  Vref R16=R  R15=R  Vref 16 R1=R  Vref 16 ground  Figure 4.6: Voltage divider for Vre f /16  2000 Conventinal Monotonic Proposed  Switching Energy [CV2]  1600  1200  800  400  0  0  100  200  300  400  500 600 Output Code  700  800  900  Figure 4.7: Switching energy in different architectures  50  1000  Chapter 5  Circuit Design & Layout Circuit level design of building blocks like boot-strapped switch, comparator, digital control logic and capacitor array are discussed in this chapter. Since matching is very important for SAR ADCs, some layout considerations to guarantee matching are also discussed.  5.1  Boot-strapped Sampling Switch  The boot-strapped switch in Figure 5.1 [2] is implemented to perform the S/H function. During ’on’ state, the gate-source voltage of the sampling transistor M10 is fixed at the supply voltage VDD in dependent of the input signal, which makes the on-resistance a small constant value. Although the absolute voltage at some nodes may exceed VDD , no device’s terminal-to-terminal voltage is larger than that. Here is how it works. M10 and M11 are the two transistors used as the switching devices which are controlled by signal clks. M11 is just a simple p-type transistor used for charge injection compensation, which will be explained later. M10 is the transistor whose gate-source voltage is fixed at VDD during ’on’ state. When clks is high, M11 is ’off’. M7 and M8 discharge the gate of M10 to ground. At the same time, CS is charged to be VDD since M3 and M4 are ’on’. M5 and M9 isolate the switching device M10 from CS while it is being charged. CS tries to hold the voltage between the top and bottom plates during the ’on’ phase. When clks goes low, M2 pulls down the gate voltage of M5 , applying the voltage over CS between  51  M1  clks  M3  Μ5  Μ7  Μ8  Μ6  clks  Cs Μ9  M2 clks  Μ10  VSH  VIN  M4  Μ11  clks Figure 5.1: Boot-strapped switch for S/H M9 gate and source. This turns on both M9 and M10 . The charge holding between CS enables the gate of M10 to track the input voltage VIN shifted by VDD . Body of M5 has to be tied to the top plate of CS , avoiding latch-up. M6 and M7 are used to make sure the terminal-to-terminal voltage will not exceed VDD . M6 ensures the gate-source voltage of M5 does not exceed VDD and M7 ensures the drain voltage of M8 does not go over VDD . When M10 is turned off, the negative charge in its channel is injected to the source and drain. Since its gate-source voltage is fixed at VDD despite of the input, total charge injected to the drain and source is constant. However, charge injected to the drain and source does not equal which causes the charge injected to the sampling capacitor is not constant when the drain and source are reversed. Current direction of M10 is opposite when VIN is rising or falling, which means source and drain of M10 are reversed in these two situations. M11 is added to compensate this uncertainty in charge injection since its source and drain are opposite compared to M10 .  5.2  Comparator  A dynamic comparator is adopted in this design for energy efficiency because it has no static power. Figure 5.2 shows the schematic of the comparator. P-type input 52  M9  Vbias  M12  clkc  M11  M10  V+  VM2  M1  OP  ON  M7  M8  clkc M5  M3  M4  M6  clkc  Figure 5.2: Dynamic comparator pair is used for proper function because the input common-mode voltage gradually reduces from VCM to ground. The comparator works under the control of signal clkc. When clkc is high, the comparator outputs OP and ON are reset to high by M5 and M6 . When clkc goes low, the input pair M1 and M2 compare the two input voltage V+ and V and convert the voltage difference to current difference. The regenerative positive feedback made of M3 and M4 forces one of their gate voltages to be high and the other to be low. Then the two inverters made by M7 ⇠ M10 recover the voltages to be rail-to-rail.  Offset voltage of this type comparator is expressed as Equation 5.1 [15]. DVth1,2 is the threshold voltage difference of the input pair M1 and M2 and (Vgs  Vth )1,2 is  the overdrive voltage of the input pair. DS1,2 is the physical dimension mismatch of the input pair and DR is the loading resistance mismatch caused by M3 ⇠ M6 .  In Equation 5.1, the first term DVth1,2 is constant, resulting in a static offset which does not affect the performance of the SAR ADC. However, the second term is signal-dependent and relies on the overdrive voltage. Since the common-mode voltage gradually changes from VCM to ground, this dynamic offset value changes in different cycles within one conversion and will degrade the performance.  53  Figure 5.3: Offset of the comparator  VOS = DVth1,2 +  (Vgs  Vth )1,2 DS1,2 DR ·( + ) 2 S1,2 R  (5.1)  To reduce the dynamic offset, several methods can be adopted. Large size transistors can be used to reduce both the input pair dimension mismatch DS1,2 and the load mismatch DR. However, this burns more power. The overdrive voltage of the input pair Vgs1,2  Vth can be minimized at the cost of lowering speed. A  simple and reliable way to ensure the dynamic comparator suitable for this design is to add an extra current tail by M12 . By biasing M12 in the saturation region, the current flow through M1 and M2 are almost constant. Overdrive voltage of M1 and M2 has a sightly change even when the input common-mode voltage changes a lot. A monta-carlo simulation shows the offset of this dynamic comparator. Layout of the comparator is shown in Figure 5.4. Commom-centroid layout is adopted and dummy transistor are added to improve matching. Also guard-rings are used to isolated this sensitive analog circuit from the noisy digital circuits.  54  INPUT PAIR  BUFFER  LOAD  Figure 5.4: Layout of the comparator clks clk VDD  DFF  clk1  DFF  clk2  DFF  clk3  DFF  clk4  DFF  clk5  DFF  clk6  DFF  clk7  DFF  clk8  DFF  DFF  clk9  clk10  OR  clkc  clk clks clkc clk1 clk2  clk3  clk8 clk9 clk10  Figure 5.5: Synchronous control logic and timing diagram  5.3 Digital Control Logic The schematic and timing diagram of the SAR control logic is shown in Figure 5.5. SAR operation is synchronous with an external clock clk and twelve clock cycles are needed for one conversion. Two clock cycles are used for sampling which is controlled by an external signal clks. The other ten clock cycles are used for 10-bit conversation, since each bit decision needs one clock cycle. External signal clks controls the sampling switch and the input signal Vin and 55  clki  BUFF  clki OP  OP AND  DFF  S p ,i  bi BUFF  DFF  bi  clki  clki OP  S p ,i  AND  S n ,i  OP S n ,i  Figure 5.6: Control logic and timing diagram Vip are sampled when clks is high. As shown in Figure 5.5, the boot-strapped switch is turned on to track the input for one and a half cycles and is turned off after that. Another half cycle is used for the sampled voltage to settle within the accuracy needed for 10-bit. clkc controls the operation of the dynamic comparator. Comparator is turned off when clkc is high and turned on when clkc goes low. When the sampled voltage settles after half a cycle, the dynamic comparator does the first comparison. At the rising edge of clk1 , output of the comparator is sampled by a D-flipflop, resulting in the most significant bit (MSB). Signal S p,1 or Sn,1 which controls the capacitors associated with the MSB changes to high according to the sampled result. Bottom plate of the capacitor on the higher voltage side is switched to ground under the control of S p,1 or Sn,1 . The voltage V+ or V settles within required accuracy in the same half clock cycle. When the falling edge of the clock comes, the comparator does the second comparison. This procedure repeat for N-1 times. The rising edge of clki samples the i-th comparison result of the comparator and the sampled value is the i-th bit as shown in Figure 5.6. Capacitor associated with this bit is switched to ground according to S p,i or Sn,i .  5.4  Capacitor Array  Performance of the SAR ADC depends on the matching of the capacitors. Metal-insulator-metal (MIM) capacitor is used here since it has a large unit 56  D  D  D  D  D  D  D  D  D  D  D  D  D  D  D  D  D  32  32  32  32 M16 M16 M16 M16 32  32  32  32  D  D  D  D  D  32  32 M16 M8 M8 M4 M4 L4  L4  L8  L8 M16 32  32  D  D  D  D  32  32 M16 M8 M8 M2 M1  X  L2  L8  L8 M16 32  32  D  D  D  D  32  32 M16 L8  L8  L2  X  L1 M2 M8 M8 M16 32  32  D  D  D  D  32  32 M16 L8  L8  L4  L4 M4 M4 M8 M8 M16 32  32  D  D  D  D  D  32  32  32  32 M16 M16 M16 M16 32  D  D  D  D  D  D  D  D  D  D  D  D  D  D  D  D  32  32  32  D  D  D  D  D  D  D  D  D  Figure 5.7: Floorplan of the capacitor array capacitance which means smaller area for the same capacitance value. Larger unit capacitor will have better matching but results in larger area, higher power and lower speed. The unit capacitor value is chosen to be 15 fF for a good matching and at the same time result in a reasonable total capacitance. Unit capacitor is much larger comparing to that 5 fF in [23]. Dimensiton of the unit capacitor is 2.5µm ⇥ 2.5µm. When size of the unit capacitor is determined, matching relies  on the layout. Common-centroid layout method is adopted and results in the layout in Figure 5.7.  The dummy capacitors are actually used as the CS in  boot-strapped switch in Figure 5.1. The unit sharing the same name are connected together acting as the capacitors shown in Figure 4.1. Layout of the whole chip and a zoomed-in view is shown in Figure 5.8. Total active area occupied is 215µ m ⇥ 215µ m.  57  Capacitor Array 215um  Switching network COM  SAR  S/H Switching network  Capacitor Array Figure 5.8: Layout of the whole chip and a zoomed-in view  58  BUFFER  215um  S/H  Chapter 6  Post-Layout Simulation Results and Measurement Results In this chapter, commonly used ADC test methods are discussed and are applied to the test chip. Both the post-layout simulation results and measurement results of the chip are presented.  6.1  ADC Test Methods  Testing of an ADC is done to verify the static and dynamic performance, thus the testing it typically conducted in two steps. Usually the first step it to test the static performance which is done by finding the input-output transfer curve. The second step, i.e., the dynamic performance is done by analyzing the frequency spectrum of the ADC output when a given input signal is applied to ADC. Figure 6.1 shows the setup for testing of the static performance [12]. A ramp input signal rising from the minimum voltage to the maximum voltage is applied. Output of the ADC under test is either fed to a fine DAC or recorded by a logic analyzer. Further analysis of the voltage difference in Figure 6.1 (a) or the digital codes in Figure 6.1 (b) will provide the information on offset value, gain error, INL and DNL. Figure 6.2 shows the setup for testing of the dynamic performance [12]. A sinusoidal signal is applied at the input after an anti-aliasing filter and output is fed to a fine DAC or a RAM buffer. A spectrum analyzer can be used following 59  N-bit ADC  N+2-bit DAC Bout  Vin  DUT  Vin  Fine DAC  +  t (a) N-bit ADC  Vin  Bout  t Vin  DUT  Logic Analizer  (b)  Figure 6.1: Test for static performance the DAC to show the frequency spectrum. Fast Fourier Transform (FFT) can be carried out with the stored digital codes to find the frequency spectrum of the output.  SFDR, SNDR and ENOB can be calculated from the output power  spectrum. Further details on the ADC testing can be found in the IEEE Standard document for ADC testing [1].  6.2  Post-Layout Simulation Results  As discussed in Chapter 2, specifications like DNL, INL, SNDR, SFDR and ENOB are used to evaluate the performance of an ADC. DNL/INL represent the static performance of an ADC while SFDR/SNDR and ENOB are representing the dynamic performance of an ADC. In this chapter, we first use the post-layout simulation to evaluate the performance of the designed ADC and then will present the corresponding measurement results of the test chip.  6.2.1  Differential and Integral Nonlinearity  DNL and INL show the linearity of the ADC and are defined in Chapter 2. To simulate the INL and DNL, a ramp input of full-swing is applied to the ADC. Simulation results of the DNL/INL are shown in Figure 6.3. Note that the offset 60  H  DUT  Bout  f Signal Generator  N-bit ADC  Anti-alissing Filter  Fine DAC  Spec trum  N+2-bit DAC  Spectrum Analyzer  RAM buffer  FFT  (a) H  DUT f  Signal Generator  Anti-alissing Filter  N-bit ADC  Bout  N+2-bit Processor DAC  (b)  Figure 6.2: Test for dynamic performance  DNL (LSB)  1 0 −1  0  200  400 600 Output Code  800  1000  0  200  400 600 Output Code  800  1000  INL (LSB)  1 0 −1  Figure 6.3: Post-layout simulation result of INL/DNL  61  ADC Output Spectrum 0 −10 SNDR=60.10dB SFDR=72.59dB ENOB=9.69  −20  Power (dB)  −30 −40 −50 −60 −70 −80 −90 −100  0  5  10 15 Frequency (MHz)  20  25  Figure 6.4: Spectrum with the input frequency of 22.75 MHz and gain error are already removed. INL/DNL are within the range of  0.6 LSB⇠  0.7 LSB and there is no missing code in this SAR ADC.  6.2.2  SNDR, SFDR and ENOB  To simulate the SNDR/SFDR, a differential sinusoidal signal of full-swing is applied and spectrum of the output codes is analyzed by using Matlab. SNDR is the fundamental signal power divided by the total distortion and noise power and SFDR is the ratio of the fundamental signal power to the strongest spurious signal power. ENOB calculated as Equation 2.10. Figure 6.4 shows the spectrum of the output codes when a 22.75 MHz input sinusoidal is sampled at the rate of 50 MS/s by the SAR ADC. SNDR of 60.1 dB, SFDR of 72.6 dB and ENOB of 9.69 bit are achieved. SNDR, SFDR and ENOB in terms of different input frequencies are plotted in Figure 6.5.  6.2.3  Power Consumption  The total power consumption of the SAR ADC running at a sampling rate of 50 MS/s is 0.32 mW, of which the digital part consumes 0.23 mW and the analog 62  80 SNDR SFDR ENOB  SFDR SNDR (dB)  75  70  10  65  9.5  60  9  55  0  5  10 15 Input Frequency (MHz)  20  25  Figure 6.5: SNDR, SFDR and ENOB vs input frequency 0.35 0.3  Power (mW)  0.25 0.2 0.15 0.1 0.05 0  0  5  10  15  20 25 30 Sampling Rate (MS/s)  35  40  45  50  Figure 6.6: Power vs sampling rate part uses 0.09 mW. Note that the reduction in the power of the analog part (which otherwise dominates the total power) is due to the use of the proposed split-capacitor DAC. Since the dynamic power of the digital control part dominates, power of the SAR ADC is roughly proportional to the sampling frequency. Figure 6.6 shows the total power versus the sampling frequency, which is almost linear. Table 6.1 provides a summary of the post-layout simulation results of the SAR ADC. In Table 6.4, the design is compared to the state-of-the-art designs. The proposed SAR ADC has a favorable FoM due to the use of the proposed split63  Table 6.1: Post-layout simulation summary Technology (nm) Supply voltage (V) Sampling speed (MS/s) Resolution (bit) Input common-mode (V) Input range (Vpp ) Input capacitance (pF) Unit capaictance (fF) Unit capacitor size (um2 ) SNDR (dB) SFDR (db) ENOB (bit) INL (LSB) DNL (LSB) Total power (mW) Analog power (mW) Digital power (mW) Area (mm2 )  TSMC 90 1.0 50 10 0.5 1 0.48 15 2.5x2.5 60.1 @ 22.75 MHz 72.6 9.69 0.6 0.7 0.32 @ 50 MS/s 0.088 0.229 0.046  capacitor DAC.  6.3  Measurement Results  As a proof of concept, a chip is fabricated in a 90-nm CMOS technology. The core area of the chip is 215µm ⇥ 215µm. The fabricated chip includes the proposed  split-capacitor DAC, switch arrays, comparator, bootstrapped switches, and SAR logic, however, it does not include the voltage reference and the divider. Figure 6.7 shows the SAR ADC layout with pads labeled and Table 6.2 summarizes the pads.  6.3.1  Measurement Setup  Both the static performance and the dynamic performance of the ADC are tested. The equipments used during the testing are listed in Table 6.3. The setup is shown in Figures 6.8 and 6.9.  64  DGND  DGND  DVDD  BVDD  AGND  SAMPLE  AVDD  DGND  INP  DGND  INN  OUT  REF2  CLOCK  AGND  DGND  REF1  DGND  Figure 6.7: Label of each pad  Table 6.2: Pads and usage Name CLOCK SAMPLE DGND REF1 REF2 INN INP AVDD DVDD AGND BVDD OUT  Function Clock signal, N+2 times faster than sampling rate Sampling clock signal Digital ground Reference voltage Vre f Reference voltage Vre f /16 Negative end of the differential input Positive end of the differential input Analog part voltage supply Digital part voltage supply Analog ground Output buffer voltage supply Output of the ADC in series  65  Table 6.3: Test equipments Quantities 1 1 1 1 1 1 1 1 1 4 10 6 4 5  Function Probe Station Probe Probe Probe Clock generator Signal generator Signal generator Multimeter Oscilloscope Power supply Cables Cables Cables Connector  Equipment Cascade RF-1 Cascade DCQ-5 Suss |Z| Cascade Eyepass HP E1401B Agilent 3325A HP 3326A two channel synthesizer HP 34401A Tecktronix DPO4054 Xantrk LXQ-30-2 Banana cables SMA cables SMA-BNC cables BNC-SMA connector  Figure 6.8: Test setup  66  SUSS  DCQ-5  SUSS  DCQ-5 EYEPASS  EYEPASS  Figure 6.9: Test with probe landed DCQ-5 Probe  Clock Generator (HP E1401B)  Suss |Z| Probe  ADC on probe station  Oscilloscope (Tektronix DPO4054)  (Cascade RF-1)  Eyepass Probe Ramp Signal Generator  Reference Voltage  Voltage Supply  (Agilent 3325A)  (Xantrek LXQ-30-2)  (Xantrek LXQ-30-2)  Figure 6.10: Test setup for static performance measurement  6.3.2  Static Performance  To measure the INL/DNL, the test method in Figure 6.1 (b) is used and the test setup is shown in Figure 6.10. After removing the offset and gain error, the INL and DNL are shown in Figures 6.11 and 6.12, respectively. The INL is in the range of -4.7 and 4.7 and the DNL is between -0.8 and 1.7. 6 4  INL (LSB)  2 0 −2 −4 −6  0  100  200  300  400  500 600 Output Code  700  Figure 6.11: Measured INL  67  800  900  1000  2 1.5  DNL (LSB)  1 0.5 0 −0.5 −1 −1.5 −2  0  100  200  300  400  500 600 Output Code  700  800  900  1000  Figure 6.12: Measured DNL Clock Generator  DCQ-5 Probe  (HP E1401B)  ADC on probe station (Cascade RF-1)  Suss |Z| Probe  Oscilloscope (Tektronix DPO4054)  Eyepass Probe Sinewave Generator  Reference Voltage  Voltage Supply  (HP 3326A)  (Xantrek LXQ-30-2)  (Xantrek LXQ-30-2)  Figure 6.13: Test setup for dynamic performance measurement  6.3.3  Dynamic Performance  The test setup for the dynamic performance measurement is shown in Figure 6.13. Ideally, two Suss |Z| probes should have been used for both input high speed clock  signals and high speed output digital signal. However, due to fact that the two Suss |Z| probes were not identical (which was a surprise), only one Suss |Z| probe can  fit with the Cascade eyepass probe. Thus, instead of the Suss |Z| probe, a Cascade  DCQ-5 DC probe is used for the input. Since DCQ-5 is a low-frequency probe, it can handle square-wave signals up to 10 MHz and higher frequency squarewave signals would look like a sinusoidal signal due to being filtered by the probe. Thus in out test, the sampling rate is only up to 1 MS/s instead of 50 MS/s. The output power spectrum of a 55 kHz sinusoidal input signal sampled at 1 MS/s is shown in Figure 6.14 and the SNDR, SFDR and ENOB versus input frequency are plotted in Figure 6.15. SNDR, SFDR and ENOB versus sampling rate is shown in Figure 6.16. 68  ADC Output Spectrum 0  −20  SFDR = 59.41 dB SNDR = 46.99 dB ENOB = 7.51  Power (dB)  −40  −60  −80  −100  −120  0  0.05  0.1  0.15  0.2  0.25  0.3  0.35  0.4  0.45  0.5  fi/fs ( fs=1 MS/s fin=55 kHz)  Figure 6.14: Output spectrum when input frequency is 55 kHz 80 SFDR SNDR ENOB  SFDR and SNDR (dB)  70 60  ENOB  50  8  40  7  30 6 20 10 0  0  50  100  150  200 250 300 Input frequency (kHz)  350  400  450  500  Figure 6.15: SNDR, SFDR and ENOB vs input frequency  6.3.4  Measurement Results Analysis  The measurement results are not as good as the post-layout simulation results. In addition to the problem that the two high-frequency probes had a different size and thus we were not able to use both at the same time, some other possible reasons for the discrepancies between simulations and measurements are discussed here.  69  80 ENOB SFDR SNDR  70  SNDR and SFDR (dB)  60 50  ENOB  40  8  30  7  20  6  10 0  0  100  200  300  400 500 600 700 Sampling Fequency (KS/s)  800  900  1000  1100  Figure 6.16: SNDR, SFDR and ENOB vs sampling rate INL/DNL INL and DNL are calculated based on the static voltage transfer curve shown in Figure 2.6. As can be seen from Figure 6.11, there is a big jump in INL value around code 512. The reason for this can be attributed to the mismatch (DC) of the largest capacitor in the MSB array. Since mismatch of the largest capacitor in the MSB array has the biggest weight during the charge redistribution, it has the biggest contribution to the INL value. Also, the variation of the second reference for the LSB array from the ideal value adds to the INL. This is verified by using a model of the ADC in Matlab. With a 1% mismatch of the MSB capacitor and 3% inaccuracy in the second reference, the transfer curve is drawn in Figure 6.17. Probe limitation As explained above, the original test plan was to use to two Suss |Z| probes (RF  probe) to handle the high-speed signal and a Cascade eyepass probe to provide the DC signals. For sampling rate of 50 MS/s, the input clock frequency is 600 MHz. However, surprisingly the two Suss |Z| probes were not identical in physical dimensions. As you can see from Figure 6.18, one Suss |Z| probe does not fit  closely with the Cascade eyepass probe while the other one fits well. To test the performance, a DCQ-5 DC probe with the same configuration is used to replace 70  Code Time  Figure 6.17: Transfer curve DCQ-5 EYEPASS  EYEPASS  600um  SUSS 1  250um  SUSS 2  Figure 6.18: Eyepass probe and suss probe one of the Suss |Z| probes. However, the DCQ-5 probe can only handle squarewave signals up to 10 MHz, so only up to 1 MS/s sampling rate can be tested.  71  Figure 6.19: PCB with package ESD protection To test the performance of the ADC running at 50MS/s, the loose die was packaged in a surface-mount CFP-24 package. The test PCB was designed with bypass capacitor and anti-aliasing filter. Test PCB with the package is shown in Figure 6.19 and test setup is shown in Figure 6.20. However, when we tested the packaged chips, eight out of ten outputs were always stuck at high or low. The other two samples worked at first but after a few times operation, they stopped working. There is a static current in the reference voltage around 10 mA which should be zero when sampling clock is low. Since all the loose dies tested work, the reason that the packaged chips do not work can be attributed to the lack of ESD protection on the chip and thus packaging has possibly damaged the chip. Ground and reference noise Noise of the voltage reference is very important since it directly affects the decision result of the comparator. It can be reduced by using bypass capacitor and/or using stable reference generator(e.g., battery). Analog ground is used as a reference voltage in this design. It is separated from the noisy digital ground within the chip and they were supposed to be connected far from the chip with a ferrite bead. However, with the eyepass probe, they are directly connected in the close proximity of the chip which introduces the noise from the digital circuit directly to the DAC, and thus deteriorating the performance. This is verified by simulation. When the digital ground and analog ground are connected together before they are connected 72  Figure 6.20: Test setup with PCB to the ideal ground through a 10 W resistor, the SNDR reduces by 5.4 dB. Second voltage reference accuracy There is a second voltage reference for the LSB array in this design. Its value is Vre f /16 which is chosen based on the assumption that the parasitic capacitance at node P is equal to one unit capacitance. However, the actual parasitic capacitance may vary from the value the extraction tools give, so the value of the second voltage reference should be adjusted. The ENOB versus this accuracy of this value is shown in Figure 4.5. During the testing, this voltage reference was adjusted to see if its non-ideality limits the performance. A measured ENOB versus second reference value is shown in Figure 6.21. As you can see, the ENOB doesn’t change too much with the reference voltage, thus this may not be the reason for the limited performance of the ADC. Comparator dynamic offset To achieve a low power, a dynamic comparator is used and to increase the speed, it is implemented using small size devices. However, smaller size means worse 73  -3.33  0 1.67 -1.67 Reference Accuracy (%)  3.33  Figure 6.21: SFDR, SNDR and ENOB vs second reference matching and worsens the dynamic offset. In the post-layout simulations, we were not able to simulate the device mismatch and thus this problem was not captured. A manually added 5% mismatch in the schematic reduces the SNDR by 5.5 dB and 10 % mismatch reduces the SNDR by 16.7 dB. The reason that this prototype is measured to only achieve an ENOB of 7.5 bit can thus be attributed to the comparator performance.  To elevate this problem, either larger size devices  should be used (thus compromising the speed) or a pre-amplifier should be added (at the cost of increased power) to improve the accuracy of the comparator.  74  Table 6.4: Comparison to state-of-the-art designs Specifications Journal/Conf Pubish time Architecture Technology Supply (V) Sampling (MS/s) Resolution (bit) ENOB (bit) Power (mW) FoM (fJ/con.) Area (mm2 )  [24]* ISSCC 2010 Binary 65nm 1.2 100 10 9.51 1.13 15.5 0.026  [33]* ISSCC 2010 Binary 65nm 1.0 50 10 9.11 0.82 30 0.039  [23]* JSSC 2010 Binary 130nm 1.2 50 10 9.18 0.826 29 0.052  [7]* CICC 2009 Split 65nm 1.2 50 8 7.3 1.83 232 0.03  [9]** ASICON 2011 Split 130nm 1.2 50 10 9.17 1.58 55 0.154  FoM = Power/(min(2·fin ,fs )·2ENOB ) *Measured results, **Post-layout simulation results  75  This** ISCAS 2012 Split 90nm 1.0 50 10 9.69 0.317 8.44 0.046  This* NA NA Split 90nm 1.0 1 10 7.51 0.051 279 0.046  Chapter 7  Conclusions 7.1  Concluding Remarks  A modified split-capacitor SAR ADC architecture for low-power medium resolution applications is proposed. To verify the idea, a 10-bit 50 MS/s SAR ADC is designed and implemented in a 90 nm CMOS technology. Post-layout simulation results show that the ADC achieves an ENOB of 9.69 for a 22.75 MHz input signal at the sampling rate of 50 MS/s while consuming only 0.032 mW from a 1 V supply. FoM of 8.44 fJ/conversion-step is achieved. The first prototype is measured to achieve an ENOB of 7.51 at 1 MS/s with a power consumption of 51 µW . The performance of the ADC is mainly limited by the dynamic offset of the comparator. This architecture improves the accuracy of the conventional split-capacitor SAR ADC and further reduces the power as compared to the binary-weighted SAR ADCs by having a smaller total capacitance. Smaller capacitors make it suitable for designing charge redistribution ADCs with a resolution higher than 10-bits (up to 14-bits) and a sampling rate of a few tens MS/s. A proof of concept prototype is tested. The prototype achieves an ENOB of 7.51 at 1 MS/s with a power consumption of 51 µW . The measured performance was lower than expected. The reasons for lower performance are investigated and presented. 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