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A programmable-gain amplifier and an active inductor for in-vehicle power line communications Zhang, Xiaolang 2011

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A Programmable-Gain Amplifier and an Active Inductor for In-Vehicle Power Line Communications by Xiaolang Zhang B.Eng, Southeast University, 2008  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF  MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES (Electrical and Computer Engineering)  THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver)  August 2011 © Xiaolang Zhang, 2011  Abstract In-vehicle power-line communication (VPLC) is a communication technique that uses the power lines of the vehicle for data transmission. Based on the measurements of the power line communication channel, the channel response is characterized as frequency selective, time and location dependent with high signal attenuation. Also, the access impedance changes a lot in different frequency ranges. These properties impose design challenges at both system level and circuit levels of a VPLC system. This thesis presents the design of two critical building blocks of a VPLC system, namely, a variable gain amplifier (VGA) and an active inductor. VGAs are used to amplify the signal to a predefined level without introducing too much distortion. The presented VGA design targets a 0.13μm CMOS technology. The VGA design is discussed in detail. Gm-boosting technique is used to both increases the linearity and provide a programmable 0 dB to 60 dB gain over a broadband. Furthermore, the gain is stable over a wide range of temperatures. The circuit is fabricated and tested, and the measured results are in good agreement with the simulation results. Inductors are commonly used in impedance matching networks. In this work, an active inductor circuit is designed which provides a wide tuning range for VPLC LC matching networks. Active inductor is a good candidate to replace the passive inductor in the LC matching network since it has a smaller area, wider tuning range, and a higher quality-factor. The designed active inductor is a fully differential grounded Gyrator-C active inductor. Simulation results confirm that the inductor has wide tuning range with linear tuning ability; however, its bandwidth is limited.  ii  The circuit design for this VPLC system is challenging, the preliminary results of the proposed circuits show some promise; however, further work is still needed to improve the performance.  iii  Preface The work in this thesis is conducted in the Electrical and Computer Engineering Department at UBC, under the guidance and supervision of Dr. Shahriar Mirabbasi and Dr. Lutz Lampe. A version of Chapter 4 has been published in the following conference paper. Xiaolang Zhang, Shahriar Mirabbasi, and Lutz Lampe, “A Temperature-stable 60-dB programmable-gain amplifier in 0.13-µm CMOS,” in International Symposium of Circuit and System (ISCAS), Rio De Janeiro, Brazil, May, 2011. I have transferred my copyright to the organizers of the conferences above. However, I have retained my copyright for writing this thesis. I am the primary author for the publication listed above. I have performed the majority of the work. Tasks include but are not limited to literature review, schematic design, circuit layout, performing chip testing and debugging. Dr. Mirabbasi contributed on the circuit level theory review and conducting the project and Dr. Lampe performed the system level consideration and communication theory review of the paper. Dr. Roberto Rosales from the SoC lab in UBC helped make the printed-circuit-board, test and debug the chips, and also provided some backgrounds and measurements results on the project on power line communications in vehicles.  iv  Table of Contents Abstract .................................................................................................................................... ii  Preface ..................................................................................................................................... iv  Table of Contents .................................................................................................................... v  List of Tables ........................................................................................................................ viii  List of Figures ......................................................................................................................... ix  Chapter 1: Introduction ........................................................................................................ 1  1.1   Motivation ................................................................................................................. 1   1.2   Objectives ................................................................................................................. 3   1.3   Thesis Organization .................................................................................................. 3   Chapter 2: In-Vehicle PLC ................................................................................................... 5  2.1   Introduction ............................................................................................................... 5   2.2   Transfer Function and Impedance Characteristic ..................................................... 6   2.3   Noise Characteristic .................................................................................................. 7   2.4   System-Level Consideration of the VGA and Active Inductor ................................ 8   Chapter 3: VGA Structures Review ................................................................................... 10  3.1   Source Degeneration VGA ..................................................................................... 10   3.2   VGA with Feedback ............................................................................................... 16   3.3   Multi-tanh VGA ...................................................................................................... 20   3.4   Linear Current Mode Amplifier .............................................................................. 24   3.5   Temperature-stable Techniques .............................................................................. 27   3.6   Summary ................................................................................................................. 29   Chapter 4: A 60 dB Digitally Programmable Gain Amplifier for PLC Application..... 31   v  4.1   Design Consideration .............................................................................................. 31   4.1.1  Gain Variation Range ......................................................................................... 31  4.1.2  Power Dissipation ............................................................................................... 32  4.1.3  Linearity and Noise Performance ....................................................................... 32  4.1.4  Temperature Stability.......................................................................................... 38  4.2   Circuit Implementation ........................................................................................... 38   4.2.1  The First Stage: Low Noise, High Gain Amplifier ............................................. 38  4.2.2  The Gm-Boosting Technique ............................................................................... 42  4.2.3  The Second and Third Stages Design ................................................................. 46  4.2.4  The Fourth Stage Design .................................................................................... 49  4.2.5  CMFB Circuit Design ......................................................................................... 55  4.2.6  The Bias Voltage Design .................................................................................... 56  4.3   Simulation Results of VGA .................................................................................... 58   4.3.1  The Frequency Response of the VGA ................................................................ 58  4.3.2  The Linearity of the VGA ................................................................................... 58  4.3.3  The Dependence of the Gain upon the Temperature .......................................... 59  4.3.4  Summary ............................................................................................................. 60  Chapter 5: Experimental Setup and Measurement Results ............................................ 61  5.1   Circuit and Layout Characteristics.......................................................................... 61   5.2   Measurement Setup ................................................................................................. 62   5.2.1  Time Domain Characteristic Measurement ........................................................ 64  5.2.2  Frequency-Domain Characteristic Measurement ............................................... 66  5.2.2.1   AC Response............................................................................................... 66   vi  5.2.2.2  5.3   Linearity Measurement ............................................................................... 67   Performance Summary and Comparison ................................................................ 69   Chapter 6: Active Inductor for VPLC ............................................................................... 71  6.1   Introduction ............................................................................................................. 71   6.2   Active Inductor Review .......................................................................................... 72   6.2.1  Active Inductor Theory ....................................................................................... 72  6.2.1.1   Ideal Single-Ended Gyrator-C Active Inductor .......................................... 72   6.2.1.2   Ideal Floating Gyrator-C Active Inductor................................................... 72   6.2.1.3   Grounded Gyrator-C Active Inductor with Loss ........................................ 73   6.2.2  Previous Work .................................................................................................... 75  6.3   Active Inductor Design for VPLC .......................................................................... 76   6.4   Simulation Results .................................................................................................. 80   6.5   Summary ................................................................................................................. 82   Chapter 7: Conclusion ......................................................................................................... 84  7.1   Design Conclusion .................................................................................................. 84   7.2   Future Work ............................................................................................................ 84   Bibliography .......................................................................................................................... 86   vii  List of Tables Table 4.1 Switch operations and the gain settings .................................................................. 37  Table 4.2 Fine gain settings .................................................................................................... 52  Table 4.3 Parameters for switched resistors ........................................................................... 55  Table 4.4 Simulation results summary.................................................................................... 60  Table 5.1 Pins and the usage ................................................................................................... 62  Table 5.2 Test equipments ...................................................................................................... 63  Table 5.3 Transient response result ........................................................................................ 64  Table 5.4 P1dB measurement results summary ........................................................................ 68  Table 5.5 Performance summary and comparison .................................................................. 69   viii  List of Figures Fig 1.1 A generic AFE for wire-line communication system ................................................... 1  Fig 2.1 A simplified digital communication system for PLC (this is taken from Figure 1.3 in [14])........................................................................................................................................... 5  Fig 2.2 Measurement setup using a VNA with Zs = 50 Ω and the PLC network as device under test (DUT) (this is taken from Fig. 1 in [2]) ................................................................... 6  Fig 3.1 Common-source amplifier with resistive degeneration (this is take from Figure 13.10 in [23]) .................................................................................................................................... 10  Fig 3.2 Differential pair with source degeneration resistor .................................................... 11  Fig 3.3 Differential pair degenerated by MOSFET(s) operating in deep triode region .......... 12  Fig 3.4 Complementary differential pairs with source degeneration ...................................... 13  Fig 3.5 Operations of complementary differential pairs with source degeneration ................ 15  Fig 3.6 Basic topologies of VGA employing feedback .......................................................... 16  Fig 3.7 A generic switched VGA block diagram and its clock phases ................................... 18  Fig 3.8 Gain characteristics of n-bit SC VGA (this is taken from Fig 2 in [28]) ................... 20  Fig 3.9 Generalized multi-tanh system (this is taken from Fig. 1 in [30]) ............................. 21  Fig 3.10 Bipolar transistor doublet ......................................................................................... 22  Fig 3.11 Doublets with different voltage skew (this is taken from Figure 3.14 in [31]) ........ 22  Fig 3.12 Cascode LNA with multi-tanh doublet..................................................................... 24  Fig 3.13 Modified programmable current mirror ................................................................... 25  Fig 3.14 Programming current mirror to get gain programmability ....................................... 27  Fig 3.15 Bias circuit and amplifier for which gain is insensitive to temperature ................... 29   ix  Fig 4.1 S21 for three different paths. Car electronics turned on, including low-beam front lights (this is taken from Figure 5 in [2]) ................................................................................ 31  Fig 4.2 IP3 and IP3 Calculation .............................................................................................. 33  Fig 4.3 Cascaded noisy stages (this is taken from Figure 2.32 in [37]) .................................. 34  Fig 4.4 Block Diagram of VGA .............................................................................................. 36  Fig 4.5 Two options for the first fixed gain stage ................................................................... 39  Fig 4.6 Adding current sources to improve the gain ............................................................... 41  Fig 4.7 Simulation performance of the first stage................................................................... 42  Fig 4.8 Gm-boosting technique concept ................................................................................. 43  Fig 4.9 Signal flowing direction in a Gm-boosting stage ....................................................... 45  Fig 4.10 Differential source degeneration stage with Gm-boosting techniques ..................... 46  Fig 4.11 A full schematic of 2nd and 3rd stage......................................................................... 47  Fig 4.12 Simulation of the temperature dependence of the 2nd and 3rd stage ......................... 49  Fig 4.13 The 4th stage with programmable current ratio......................................................... 49  Fig 4.14 A 4th stage with programmable resistance ................................................................ 51  Fig 4.15 Switched resistor and the model ............................................................................... 53  Fig 4.16 The modified switched resistors for gain control in the 4th stage ............................. 54  Fig 4.17 CMFB circuit for the VGA ....................................................................................... 55  Fig 4.18 Frequency response of CMFB circuit ....................................................................... 56  Fig 4.19 Temperature-stable voltage reference ...................................................................... 57  Fig 4.20 Bias voltage versus temperature variation ................................................................ 57  Fig 4.21 Frequency response of the VGA for some gain settings .......................................... 58  Fig 4.22 P1dB for minimum gain setting and maximum gain setting ...................................... 59   x  Fig 4.23 VGA gain versus temperature at different gain settings........................................... 59  Fig 5.1 VGA layout................................................................................................................. 61  Fig 5.2 PCB for test of VGA .................................................................................................. 63  Fig 5.3 Transient response test setup ...................................................................................... 64  Fig 5.4 Function verification for each stage in the VGA ........................................................ 65  Fig 5.5 Test setup for AC response of VGA ........................................................................... 66  Fig 5.6 Measured gain settings ............................................................................................... 67  Fig 5.7 Linearity measurement of the VGA ........................................................................... 68  Fig 5.8 P1dB measurement results for different gains and input signal frequencies .............. 70  Fig 6.1 Lossless single-ended Gyrator-C active inductor ...................................................... 72  Fig 6.2 Lossless floating Gyrator-C active inductors ............................................................. 73  Fig 6.3 Grounded Gyrator-C active inductor with loss........................................................... 73  Fig 6.4 Equivalent circuit for the grounded active inductor with loss .................................... 74  Fig 6.5 Different structures as Gyrators (this is taken from Figure 2.8 in [48]) ..................... 75  Fig 6.6 The active inductor architecture (a) and its simplified model (b) .............................. 76  Fig 6.7 Small-signal for the active inductor............................................................................ 77  Fig 6.8 Equivalent circuit for the active inductor topology for this design ............................ 77  Fig 6.9 Placing a negative resistance for compensation ......................................................... 78  Fig 6.10 Proposed ways to tuning the inductance................................................................... 79  Fig 6.11 tunable transistors and current sources ..................................................................... 80  Fig 6.12 Maximum inductance achievable for this design ..................................................... 81  Fig 6.13 Minimum achievable inductance for this design ...................................................... 81  Fig 6.14 Resistive part and the quality factor for a maximum inductance ............................. 82   xi  Fig 6.15 Linearity simulation for the active inductor ............................................................. 82   xii  Acknowledgements I would like to express my gratitude to my supervisors, Dr. Lutz Lampe and Dr. Shahriar Mirabbasi for their enthusiasms, guidance, and unconditional supports. I thank deeply for them giving me the opportunity to join this research group two years ago. I am truly inspired by Dr. Lampe’s keen and dedication on the PLC project and Dr. Mirabbasi’s patience and his great character. I have learned a lot from these two professors and I am grateful to be their student. I would also like to thank my committee members, Dr. Wilton, Dr. Lampe, Dr. Mirabbasi, for reviewing my thesis and providing me invaluable feedback which improved the quality of the thesis. I am also thankful to my colleagues, Dr. Roberto Rosales and Nima Taherinejad, for all their support and the technical discussions that made this project move forward smoothly. Also, I would like to acknowledge Mr. Roozbeh Mehrabadi for his help with the CAD tools and Dr. Roberto Rosales for his technical assistance and willingness to help. I would like to thank Jack Chih-Chieh Shiah, Ge (Grace) Yu to read though my thesis and give me the feedbacks. I would also like to extend my gratitude to my friends here in the SoC lab; I enjoyed the friendly environment a lot. Finally I would like to thank my family for the unconditional love, support, and encouragement throughout my journey of education. This work is funded by Auto21, the Natural Sciences and Engineering Research Council of Canada (NSERC), and the Institute for Computing, Information, and Cognitive Systems (ICICS) at UBC. The CAD tool support is provided by CMC Microsystems.  xiii  Chapter 1: Introduction 1.1  Motivation The traditional power-line communication (PLC) system has been developed mainly for  home and office applications [1]. This PLC utilizes the power line infrastructures in various buildings, such as a house, in both indoor and outdoor, for communication purpose, so that we can reduce the difficulties in routing wires or antenna-based networks, which can be an expensive and cumbersome process. The in-vehicle PLC (VPLC) is gaining popularity as it uses the required power lines for different blocks (e.g., sensors and actuators) dually as a communication medium to exchange data among these blocks to improve safety and comfort [2]. A modern car is a complex and smart mechanical and electronic system. The average dimension of the power lines has reached several kilometers [3]. The VPLC system is a wire-line communication system. Fig 1.1 shows a generic block diagram of the analog front end (AFE) of the transceiver for a typical wire-line communication system.  Fig 1.1 A generic AFE for wire-line communication system  The receiver blocks consist of filters, VGA, and analog to digital converter (ADC). A coupling circuit is shared by the transmitter and receiver.  1  Considering the time and location dependent high signal attenuation [2] in the VPLC links, the VGA plays an important role in this receiver end to adjust the amplitude of the received signal to a certain level. The design of a VGA involves dealing with tradeoffs between several performance parameters such as linearity, noise, power, and bandwidth. Several VGA structures have been implemented to target different applications. In [6], a temperature-stable VGA for code-division multiple-access (CDMA) system is proposed. Transistors in this VGA are biased in sub-threshold exponential region and controlled in the form of master-slave and the VGA achieves an 80 dB gain range. In [7], to achieve a high linearity, a novel pre-distortion compression technique is utilized to compensate the distortion introduced by the transistors, however the bandwidth is limited to 10 MHz. A temperature-stable VGA is implemented by designing a proportional to absolute temperature (PTAT) bias circuit to compensate the gain stage with negative temperature coefficient (NTC) in [8]. Current amplifier is also investigated to change the gain by adjusting the signal current ratios to realize gain variation [9]. This VGA usually targets the ultra wideband (UWB) receiver system to explore its broadband property. To maximally deliver the power to the load, impedance should be matched between the channel and the load. Since the impedance is changing in different frequency ranges and also affected dramatically by the inductive loads, the tuning range for such an impedance matching network is much wider comparing with the conventional one, hence the active inductor is used to replace the passive one to tune the impedance of a LC network accordingly. Works have been published on the active inductors that were used in voltage controlled oscillator (VCO) [11], radio frequency (RF) filter with wide tuning range [12], and  2  low noise amplifier (LNA) [13]. To the author’s knowledge, this is the first time to use an active inductor to realize an inductor for LC impedance network. 1.2  Objectives The VPLC presents a significant challenging environment as compared to other PLC  systems, such as PLC for home application [10]. The communication protocols, frequency response in the channel, and noise characteristic in the VPLC are still under investigation, and are drawing more and more attention from both academia and industry. The objectives/contributions of this work are: •  Design and experimental validation of a VGA circuit that decouples the tradeoffs between high gain and wide bandwidth, low noise figure and high linearity. The VGA achieves a high linearity, and has a temperature-stable gain  • 1.3  Design an active inductor with wide tuning range and linear tuning ability Thesis Organization The remainder of the thesis is organized as follows: Chapter 2 provides a background  review of the VPLC and addresses the challenges of the circuit design for such systems. Some important conclusions are summarized based on the measurement results from previous work, including frequency response in the channel and noise characteristic. Chapter 3 introduces several design methodologies of various VGA targeting different applications, including source degeneration VGA, VGA with feedback, multi-tanh VGA, and linear current mode VGA. Also in this chapter, a gain stabilization technique over the temperature variation is presented. Chapter 4 discusses the design considerations of the VGA for VPLC application and presents the details of design implementation of a four-stage 60 dB digitally programmable VGA, annotated schematics, as well as simulation results. Chapter 5 details  3  the measurement and silicon validation of the VGA. Chapter 6 presents an active inductor design based on the grounded Gyrator-C principle. The simulation results confirm that the active inductor has wide tuning range in inductance and linear tuning ability. Chapter 7 concludes the thesis and discusses future work.  4  Chapter 2: In-Vehicle PLC In this chapter, a brief introduction to VPLC is given to reveal important characteristics of the VPLC to impose the design challenges and specifications of the VGA and the reason that we utilize an active inductor to design an impedance network for VPLC. 2.1  Introduction Fig 2.1 shows a simplified digital communication system for a power line channel [14].  Fig 2.1 A simplified digital communication system for PLC (this is taken from Figure 1.3 in [14])  A coupling circuit is used to connect the communication system to the power line. There are two purposes of the coupling circuits. Firstly, it prevents the large DC signal over the power lines to saturate the equipments in the transmitter or receiver. Secondly, it adjusts the input impedance (transmitter end) or the output impedance (receiver end) of the channel to match the source or load impedance to maximize the power delivery. Such an approach increases the dynamic range of the PLC system. Various vehicle wires are used for different tasks of communications between Electronic Control Unit (ECU) today. These embedded networks have increased the functionality and decreased the amount of wires. The three most common networks that are used to build the communication between those ECUs are the local interconnect network (LIN) [16], the control area network (CAN) [17], and the FlexRay [18]. The possible 5  applications of VPLC are very broad, extending from low data rate for activating actuators to high-speed multimedia and plug and play applications. The VPLC is much different from the PLC for home application due to its complicated wiring topologies, special channel characteristic (transfer function) of the power lines, attenuation and noise. The VPLC channels are also affected by the actions at the load end, such as braking, turning on/off the lamp, etc. [2]. These load end actions produce dramatic changes of the load impedance of the communication channel in a short time, imposing design challenge on the circuit that adjusts the impedance accordingly in a short time to increase signal power transmission. Therefore, it is important the find out the transfer function of the PLC channels and the noise characteristics of such a system. It is also imperative to design a system to achieve matching of impedance adaptively. 2.2  Transfer Function and Impedance Characteristic The power lines are tested using the two-port theory, and the power lines are treated as  the two-port network. This two-port network is characterized by the S-parameters in works [2] and [15] as shown in Fig 2.2.  Fig 2.2 Measurement setup using a VNA with Zs = 50 Ω and the PLC network as device under test (DUT) (this is taken from Fig. 1 in [2])  The PLC network is considered as the device under test (DUT), where the S-parameters are measured by a vector network analyzer (VNA) to generate the transfer function (Sparameter S21) and the input impedance of the channel (S-parameter S11). In order to obtain a 6  complete picture of the different possible connections in this vehicle, measurements within and across the different compartments are setup and conducted in the (sub) range of 300 KHz to 100 MHz. To measure the noise, a data acquisition card (DAC) is added in the system. Some important conclusions can be drawn from these measurements in [2], [4], [15], [19], [20], [21], and [22]. a. The channel response is frequency-selective and varies with time. To reduce the distortion introduced on the signal and increase the transmitted signal power, an adaptive coupling circuit with wide tuning range (both in frequency and impedance value) is essential and critical. b. The direct paths in the same vehicle show less attenuation and frequency selectivity than the indirect paths in the same system. The indirect paths go through the DC battery and experience multiple reflections caused by the mismatched branches. c. The access impedance changes a lot in different frequency ranges. However, in contrast to the frequency response, the impedance is time-independent. One important observation is that the impedance gets flattened over the range of 30 MHz to 60 MHz and 80 MHz to 100 MHz. Therefore, in order to guarantee good performance, a challenge here is to design an adaptively controlled impedance-matching network for even all the other frequency ranges. 2.3  Noise Characteristic Intensive measurements of the impulse noise show an increasing background noise in  the frequency ranges from 0 to 100 MHz. For higher frequencies, i.e. 30 MHz to 100 MHz, the noise floor is between −140 dBm/Hz and −120 dBm/Hz, and for lower frequencies, the  7  noise floor is higher, especially at frequencies less than 10 MHz, the peaks of the noise could be in the range between -90 dBm/Hz and -40 dBm/Hz [20]. In summary, the PLC channel is frequency-selective, time and location dependent, and the noise floor is high. The statistical characteristic of the measured channel is developed in numerous works, one recent work can be found in [20]. 2.4  System-Level Consideration of the VGA and Active Inductor Based on the above conclusions, the following design specifications are derived for the  VGA and active inductor. Since the frequency ranges used in different work varied as shown in above, to be conserved, the VGA targets a broadband one, i.e. at least covers the frequency range from 30 MHz to 100 MHz. The variable gain range is from 0 dB to 60 dB, no signal attenuation is required because the signal in the PLC channel has already attenuated a lot. A gain step is chosen as 2 dB to minimize the amplitude discrepancy at the output for all the input signals. Considering the special working environment, the VGA should be robust over a wide temperature range, -55ºC to 125ºC, called an extended temperature range. The noisy environment, especially at low frequency range, requires a high sensitivity of the circuit, so the VGA should show a high linearity and low noise. The power consumption for this design is not critical because of the existing DC battery in vehicles. Considering the unpredictable input impedance of the VPLC, a wide impedance value of a LC impedance matching network is required to match all possible impedance from the load. A passive inductor is impractical to realize this network due to its limitation on area, inductance and tuning range. Active inductor is a plausible substitution to achieve such a  8  wide inductance. The active inductor is also required to be linearly tunable to get a good matching, and also will relive the design of an automatically impedance-control algorithm.  9  Chapter 3: VGA Structures Review This chapter will cover various existing digitally controlled VGA structures. The gain control scheme and the linearization technique are discussed, and their advantages and disadvantages are compared between different structures. The tracking ability of the process, temperature and supply voltage (PVT) variations is also discussed for some typical structures in the latter half of this chapter. 3.1  Source Degeneration VGA A circuit is said to be linear if the circuit is designed into that the gain is less dependent  on the bias condition and the input level. A simple way to realize this principle is called source degeneration [23]. A resistor is inserted at the source of the transistor in a common-source amplifier, as shown in Fig 3.1. Due to the feedback in this circuit, the voltage difference between the gate and the source is reduced, so that, even the input voltage is large, we can still get a linear current at the output.  Rs=0  Rs ≠ 0  Fig 3.1 Common-source amplifier with resistive degeneration (this is take from Figure 13.10 in [23])  The overall transconductance of such a stage is given by equation (3.1) Gm =  gm 1 + gmRs  (3.1)  which shows the linear range of the transconductance is extended by (1+gmRs).  10  The source degeneration VGA is often used in open-loop system. The most common differential structure is shown in Fig 3.2.  Fig 3.2 Differential pair with source degeneration resistor  The basic idea is the same as that in the single-ended case. With larger source degeneration resistor, the circuit is more linear. The high linearity is achieved at the expense of decreasing the transconductance of the amplifier, which essentially reduces the gain. The transconductance of the differential pair with source degeneration is determined by Gm =  gm 1 + gmRs / 2  (3.2)  where Rs is the source degeneration resistor and gmRs/2 is the source degeneration factor. If the source degeneration factor is much larger than 1, equation (3.2) is simplified to Gm =  2 Rs  (3.3)  under this condition, the transconductance of this configuration is simply determined by the source degeneration resistor. By changing the value of Rs, the amplifier gain is tuned. However, the gain of the amplifier decreases dramatically, and the stage becomes noisier. A linear and accurate resistor is required to maintain the linearity and keep the gain accurate for this topology. Such a high quality passive element sometimes is not available in the digital CMOS technology. A MOS transistor working in a deep-triode region functions as 11  a resistor, and the resistance linearly depends on the bias voltage. Such a transistor can be used to replace the resistor, as depicted in Fig 3.3 (a).  Fig 3.3 Differential pair degenerated by MOSFET(s) operating in deep triode region  However, for large swing inputs, the transistor M3 might not remain in deep triode region, thereby experiencing substantial change in the on-resistance. On the other hand, Vb must track the input common-mode voltage level so that on-resistance of M3 can be defined accurately. Fig 3.3 (b) [24] is a modification to cope with the large input swing situation. Two NMOS transistors, M3, M4 are connected in parallel. The gates are connected to the differential inputs: when the inputs are 0, both transistors are in deep triode region. If the gate voltage of M1 keeps increasing, transistor M3 stays in the triode region, transistor M4 will eventually enter into the saturation region. This is because the drain voltage of M4 follows Vin+, and source voltage follows Vin-, if the differential inputs reach a certain level, M4 finally goes into saturation. In this case, the overall on-resistance keeps relatively linear; hence the overall stage keeps relatively linear regardless of the input swings. The proper sizes of (W/L)1,2 are about seven times larger than (W/L)3,4 for maximum linear range as suggested in [24].  12  Compared to the Gm of a simple differential pair, the effective Gm of differential pairs with source degeneration decreases by a 1/(1+gmRs) factor, to keep a reasonable gain, the load resistors has to be inevitably large, which will cause a large voltage drop over it, therefore decreases the output swing. This motivates us to find an approach to boost effective transconductance of differential pairs with source degeneration. One plausible topology to boost the transconductance of the VGA to keep the same gain as a simple differential pair while still making the similarly linearity performance is using complementary input differential pair, which is shown in Fig 3.4. In this structure, the outputs of two common-source amplifiers, i.e. a common-source amplifier with NMOS input, and a common-source amplifier with PMOS input, are connected together, and the output current is then delivered to the load resistor. Two identical pairs of current sources are needed to bias the PMOS pair and NMOS pair respectively. In each differential pair, source degeneration resistors are used to improve the linearity, the same as stated above.  Fig 3.4 Complementary differential pairs with source degeneration  13  The effective transconductance of this structure is described by the following equation  Gm =  gmn gmp + gmnRs1 gmpRs 2 1+ 1+ 2 2  (3.4)  By proper sizing the PMOS and NMOS pairs so that gmnRs1 = gmpRs2, the transconductance turns into  Gm =  gmn + gmp gmnRs1 1+ 2  (3.5)  noting that both differential pairs are biased with the same DC current. Compared with the simple source degeneration differential pair case, the power consumption is the same for both topologies while the complementary configuration has a larger effective transconductance. Actually with the complementary differential pairs, the effective transconductance can be boosted by approximately 60% compared to that in Fig 3.2. One drawback of a complementary differential pair is that it can only accommodate a lower level input common mode, for large swing input signal, this structure would introduce substantial distortion on the signal since the PMOS part would be periodically turned off. This means that highest input common mode voltage is limited by the PMOS while there is no lower input level limitation. Based on the input signal amplitude, three possible operations are shown in Fig 3.5.  14  Fig 3.5 Operations of complementary differential pairs with source degeneration  •  If a large positive input signal goes into the gate of the transistors, the upper PMOS pair is turned off, and lower half of the VGA works in the deep triode region, with no signal amplification. Overall the circuit is ineffective, as is shown in Fig 3.5 (a).  •  If a large negative input signal goes into the gate of transistors, the upper half of the VGA is still valid, the NMOS input differential is cut off, as shown in Fig 3.5 (b). The linearity is determined mainly by the input PMOS differential pair, the structure is now equivalent to that in Fig 3.2.  •  If moderate signals come to the gates of the transistors, both differential pairs of the VGA are valid, which is shown in Fig 3.5 (c). The overall transconductance is determined by equation (3.4). In summary the VGA with source degeneration resistor and complementary pairs has  better power efficiency, and it boosts the transconductance to a large value to get a high gain while still sustaining the similar linearity compared to the conventional VGA with source degeneration.  15  3.2  VGA with Feedback VGAs can also utilize resistor or capacitor arrays in the feedback path of a closed loop  system. A negative feedback employing linear feedback elements, such as resistors or capacitors, can suppress the distortion introduced by the feed forward amplifier to a very low value (depends on the loop gain and also the bandwidth), however, the distortion introduced by the switches for digitally gain control (usually in series with the resistor or capacitor) is not suppressed [25], so the size of the switches need to be carefully sized by simulation. The gain is adjusted by changing the resistance or capacitance in the feedback path, i.e. adjusting the amount of feedback factor, which potentially is a drawback regarding the stability of the feedback loop. If a large gain range is desired, a large change of the feedback factor is also needed, and might drive the feedback loop into oscillation. On the other hand, there is often a tradeoff of the bandwidth and gain. The dependence of bandwidth on gain is very undesirable for some applications. Basic topologies for the VGA that employs feedback generally can be categorized into the following three types [25]: • Basic inverting feedback configuration in Fig 3.6 (a), • Non-inverting feedback configuration in Fig 3.6 (b), • Inverting feedback configuration with buffered inputs in Fig 3.6 (c).  Fig 3.6 Basic topologies of VGA employing feedback  16  Fig 3.6 (a) shows a voltage-current feedback amplifier topology. The voltage gain of the closed-loop amplifier is –Rf1 / Rs1, so the gain can be varied by changing the value of the resistors. High linearity is guaranteed as long as the loop-gain is high to keep the feedback valid, and the resistor is linearly tuned. For broadband application, the bandwidth of the operational amplifier (Opamp) is also required large enough so as not to slow the feedback loop. In this particular case, the Opamp design with a high gain and a high bandwidth is a great challenge, especially regarding the advancement of the technology and the decrease of the power supply. If the conventional Opamp is used [26], changing the gain by changing the feedback factor inevitably leads to a variation on the bandwidth of the Opamp, and also introduces distortions on the input signals. The power consumption of the Opamp is usually optimized at a given bandwidth. If the feedback factor varies, it is hard to get an optimized design of the Opamp regarding the power consumption due to the change of its bandwidth. Fig 3.6 (b) shows a non-inverting feedback configuration. If the gain of the feed forward amplifier is large enough, then the voltage gain approximately equal to 1+Rf1/Rs1. The overall voltage gain is varied by changing Rs1. One drawback of this configuration is that the voltage gain is always larger than one. When signal attenuation is necessary, this configuration is not suitable any longer. Fig 3.6 (c) presents a VGA with buffered inverting configuration. The overall voltage gain is equal to the ratios of Rf1/Rs1, thus, signal attenuation is obtainable compared with Fig 3.6 (b). Two voltage buffers with high input impedance are placed before the variable resistors in this configuration. If the input resistance of Opamp is designed low and Rf1 is fixed when gain is changing, then the feedback factor of this loop is constant, thus design technique can be used to optimize the power consumption with a certain feedback factor.  17  Considering the linearity, if the VGA is put in an AGC loop, a constant average current can be achieved if only Rs1 is designed to be able to adjust accordingly, guaranteeing a good linearity performance. In [25], a super source follower is used to implement the buffers inserted between input and the resistor Rs1. This super source follower provides high input impedance and low output impedance. In order to get very low input impedance, a current amplifier is used instead of voltage amplifier as the feed forward amplifier. This current amplifier also provides high output impedance. In the analog front end where the VGA is preceding to the ADC directly, and clock signals are available, in order to achieve high accuracy and low distortion in VGA design, switched-capacitor (SC) circuits with well-matched capacitors are used. To reduce the distortion, highly matched capacitors are required, and also the circuit should be carefully laid out to keep symmetry as well as reduce parasitic from wiring. The match between capacitors is much higher than resistors, and nowadays, the accuracy can be higher than 10 bits resolution. A SC VGA is depicted in [27].Two clock phases, sampling and holding in φ1, amplifying in φ2, are needed, the clock waveforms are non-over lapped as depicted in (b).  Fig 3.7 A generic switched VGA block diagram and its clock phases  18  In φ1, the input of the Opamp is connected to the common mode voltage, and the input signal is sampled and held on the bottom plate of capacitor C1. Capacitor C2 is reset in this phase. When it comes to φ2, the bottom plate of capacitor C1 is switched to ground, and the input of Opamp disconnects from the common mode voltage; capacitor C2 is now connected in the feedback loop, and the charge on C1 is transferred to C2. If the Opamp is ideal, there is no residue of charge on C1, hence signal voltage is amplified by C1/C2 at the output. The communication systems generally require a SC VGA with linear-in-dB gain control characteristic. Therefore, the ratios of capacitor arrays in the feedback path are required to change exponentially based on the gain requirements, complicating the design and layout. Several techniques were proposed to alleviate this problem. In [28] an approach using a first order approximation of the exponential function was introduced. The basic idea is presented here. It is known that, to the first order approximation, equation (3.6) holds. e2 x =  1+ x 1− x  (3.6)  So, if capacitance of C1 and C2 is set as follows  C 1 = C 0 + Cx C 2 = C 0 − Cx  (3.7)  where Cx/C0 = x. Then the overall gain variation of the SC VGA is exponential (i.e. linear-indB). The gain control characteristic is show in Fig 3.8.  19  Fig 3.8 Gain characteristics of n-bit SC VGA (this is taken from Fig 2 in [28])  k is the control signal that changes from 0 to maximum allowed value. Assuming the capacitor arrays are perfectly matched, and then the gain G will follow Gmis in Fig 3.8, however, due to the mismatch and parasitic capacitance, the gain would deviate from the ideal value. For an N-bit resolution capacitor, a LSB can be defined as A0 / (2 N − 1) , where A0 is the full gain range of the VGA. By defining the LSB, we can find out the linearity (INL and DNL) of the SC VGA with linear-in-dB characteristic. In summary, the feedback can be used to suppress the distortion introduced by the feed forward Opamp, gain can be adjusted by changing the resistance or capacitance in the feedback path. Gain variation changes the feedback factor that causes stability problem, and the power consumption of the Opamp cannot be optimized by design. The gain accuracy is heavily dependent on the accuracy of the resistor or capacitor, which is determined by the technology and layout. 3.3  Multi-tanh VGA This linearity enhancement technique was first proposed in [29] which is called  transistor-doublet, and then summarized and developed in bipolar technology [30] as multi tanh technique. It uses parallel connected sets of differential pairs of transistors whose inputs 20  and outputs are connected in parallel. If a set of differential pairs are biased with differently skewed DC voltage, then each pair shows a good linearity within a certain input voltage range. Combining all the pairs together, the overall nonlinearity will be averaged out, and a linear performance is achieved in a wide input range. A general multi-tanh system is shown in Fig 3.9, and the N differential pairs are offset by Vi. The output current is N Vin + Vj } I out = ∑ Ij tanh{ 2VT j =1  (3.8)  where Ij is the tail current to the jth stage and Vj is the base offset voltage associated with that stage. For very large N the tail currents are usually set equal, and the offset voltages are spaced uniformly in the given input range.  Fig 3.9 Generalized multi-tanh system (this is taken from Fig. 1 in [30])  the total gm of these N stages is  Ij Vin + Vj sec h2{ } 2VT j =1 2VT N  gm = ∑  (3.9)  We can expect that the linearity of the stage improves with the order of N. Regarding the noise performance of this muti-tanh system, since each of these pairs contributes noise to the output only in the input voltage range where that differential pair works properly, higher 21  order multi-tanh cell potentially can achieve noise performance that is comparable to that of a basic differential pair while having a better linearity performance. Another doublet is shown in Fig 3.10. The doublet consists of two skewed differential pairs, the skew is generated by using differently sized transistors in each pair, in Fig 3.10 the sizes of the transistors in the differential pair are k : 1. The normalized gm curves of each pairs as well as the normalized gm of the doublet structure are shown in Fig 3.11.  Fig 3.10 Bipolar transistor doublet  Fig 3.11 Doublets with different voltage skew (this is taken from Figure 3.14 in [31])  22  A large skew will result in a gm similar to the one in the leftmost of the figure. There is a noticeable dead area in the total gm curve, this is undesirable. A small a skew will cause peaking in the response, reducing the linearity range. The optimum size ratio of the differential pair, as depicted in the center curve of Fig 3.11, can be obtained by carefully simulation of the gm function of the doublet, the details are presented in [30]. The multi-tanh principle is also applicable to CMOS technology. [32] proposed a low noise amplifier (LNA) with variable gain and achieved an acceptable linearity over a wide gain variation range. The core of the LNA in [32] is depicted here in Fig 3.12. A two-stage cascaded topology is chosen to get both low input-referred noise and wide gain variation range. The multi-tanh doublet consists of {M1, M2} and {M3, M4}, which are biased at the same currents. Assuming that the size ratio of M1 (M4) is x, then the size ratios for the other transistors in the two pairs are Ax, which is pretty much the same as that in Fig 3.10. For these CMOS NMOS pairs, the equivalent offset voltage applied to the gate is Vos =  Ib 1 (1 − ) 2β x A  (3.10)  where Ib is the tail current of the LNA, and β = unCox, depending on the technology.  23  Fig 3.12 Cascode LNA with multi-tanh doublet  The operation of the doublets is shown in detail in [32]. We should keep in mind that the principle behind this doublet is the same as the doublet in bipolar technology. 3.4  Linear Current Mode Amplifier Small-signal transconductance is getting limited with the advancement of the  technology; therefore it prevents the circuit from achieving high gain and high bandwidth at the same time. A current-mode circuit can be used for the application where high frequency signal and wide bandwidth are needed [33], the input voltage can be converted into current by a linear Opamp, and the signal current is amplified using current mirrors. An advantage of this circuit is that all internal nodes present low impedance, which means that this topology is able to operate at high frequencies. This structure is also suitable for low-voltage application regarding of that the signals are currents, so the voltages in the internal nodes can be small. No common mode feedback is required in the differential case, because the diode-connected current mirror actually well define the output common-mode voltage.  24  A modified current source with programmability is shown in Fig 3.13 (a). The programmability is achieved when Vgs changes by inserting a variable resistor at the source of M1. If M1 and M2 are identical, then the current gain is given by  iout (Vgs 2 − Vth)2 = iin (Vgs 2 − RbIb − Vth)2  (3.11)  Fig 3.13 Modified programmable current mirror  If a MOS transistor operates in the triode region then its on-resistance can be easily changed by changing the bias voltage Vb, as shown in Fig 3.13 (b). Obviously, the onresistance is linearly controlled by its gate-source voltage as long as it works in triode region. To generate the required bias voltage Vb, a diode-connected transistor Mb can be used to convert IREF into Vb. this is shown in Fig 3.13 (c). If the current mirror Mb is programmable, then the gain of this current amplifier is programmable. For the transistor M3 working in (deep) triode region, the following relation holds  Vds 3 ≈  Id 3  (3.12)  W L  β 3( )3(Vgs 3 − Vth)  hence equation (3.11) then can be rearranged into  25  iout = iin  1 W )b(Vgs 3 − Vth) 2 L (1 − )2 2β 3(Vgs 3 − Vth )(Vgs 2 − Vth)  β b(  =  1 W β b( )bVdsat 3 L (1 − )2 W 2β 3( )3Vsat 2 L  (3.13)  In general case, we can set IREF = K·Ib, where K is a programmable integer number. Note that in all cases, transistor M3 should be working in the triode region; otherwise, the onresistance of this transistor is no longer variable. To keep power dissipation on the current source small, a large K is avoided to minimize IREF. Let M= (W/L) 1/ (W/L) 3, N= (W/L) 1/ (W/L) b, then equation (3.13) can be simplified into iout = ( NK + 1 − NK − M ) 2 iin  (3.14)  As of the gain programmability, i.e. implementation of the programmable current mirror, M usually is set fixed, which leaves K and N to be variable. If a wide gain variation range is required, then a large K range is also required, which results in wasting power. However, if gain variation is obtained by varying N, then an array of diode-connected transistors biased with optimal currents can be used to obtain a variable gain. Work in [5] gives the detail way to find out the N to derive an optimal current. By connecting or disconnecting these N current mirrors to the gate of M3, different gains can be obtained. Thus, restricted by the low power requirement, this approach is used to implement the programmable current mirror. A bias circuit that can achieve such ability is shown in Fig 3.14.  26  Fig 3.14 Programming current mirror to get gain programmability  the effective width of the current mirror is controlled by an array of digital control signals S1S2…SN, hence changing the bias voltage to generate a programmable output current, and N  this current is converted into a voltage. The total width of the current mirror is Wb = ∑Wbj . j =1  As we can see, in the signal path, there are two poles, and the dominant pole is usually at the output. If the parasitic gate source capacitance of M1 is comparable with the gate drain capacitance of M3, then the second pole is usually cancelled out by a zero due to the feed forward signal path. So this kind of structure will result in a wide frequency response, the detail derivation of the frequency response can be found in [5]. In summary, a current mode amplifier employs the property of low impedance of a diode-connected transistor, i.e. current mirror, to achieve high bandwidth in a VGA. On the other hand, the current can be easily programmed by the switches; it is popular for a broadband application. 3.5  Temperature-stable Techniques  In VGA design, the gain is required to be temperature insensitive in a wide range. For example, for military application, the gain should have a minimal deviation over a 27  temperature range from -30ºC to 80ºC, and for automotives application, the requirement is more stringent, sometimes an extended temperature range, -55ºC to 125ºC [34], is required. Two common design techniques are used when designing a temperature-stable VGA. The first one is to investigate the temperature-dependence of the transistor parameters, and then design a VGA that consists of a PTAT part and a part with NTC. By properly biasing the circuit and sizing the transistors, these two parts will compensate each other regarding the temperature dependence [8]. The disadvantage is that it is usually very complicated to find such a bias or sizing to completely cancel out the temperature dependence of the process parameters, and the accuracy is heavily dependent on the model provided by the foundry. So the temperature stability of such a technique is valid in a relative smaller temperature range. Another easier and more effective way is to design the circuit so that the gain variation is independent of those temperature-dependent process parameters [6]. By employing some special circuit design techniques, the overall gain only depends on the ratio of the currents and/or the ratio of the resistors; hence the gain is independent of transistor parameters. In [6], a gain-control ratio stabilization technique is proposed to get a linear-in-dB control scheme over the required temperature range. By employing this technique, if the reference voltage is temperature-stable, then the relevant coefficient, thus the gain is temperature-stable. The other technique is to design the VGA so that the gain is only dependent on the ratio of resistors, the key idea is shown in Fig 3.15.  28  Fig 3.15 Bias circuit and amplifier for which gain is insensitive to temperature  In this technique, a bias circuit generates a bias current, and this current is mirrored out and converted into a bias voltage to bias a differential common-source amplifier. The amplifier consists of a common-source stage and a transimpedance output buffer. No matter what kinds of regions the input differential pair, M7 and M8, is biased in, the following linearin-dB relationship between the transconductance and the reference current holds: log( g m ) ∝ log( I REF )  (3.15)  The transimpedance output buffer is designed with low input and output impedance to achieve a high frequency response. The gain of the overall VGA is gmRL. It can be verified that, for such a structure, no matter what kind of region that the input differential pairs work in, the transconductance is only related to the resistor Rs in the bias circuit. We can see that the overall gain of the VGA only depends on the resistor ratio, which is temperature independent [6]. 3.6  Summary  The characteristic of a PLC system imposes the design challenges of the VGA on high linearity, low noise, and wide temperature-independent gain stability, very large bandwidth, and large variable gain range. The linearity of the differential pair with source degeneration 29  is dependent on the gmRS and VDSAT. By increasing these values, its linear range also increases. But at the same time, the effective transconductance is attenuated dramatically, thus impose tradeoffs between the gain, noise, and power dissipation. Some other available VGA structures cannot meet all these requirements, either. A new approach has to be proposed.  30  Chapter 4: A 60 dB Digitally Programmable Gain Amplifier for PLC Application The VGA design involves the design considerations of linearity, noise performance, power dissipation, temperature stability, and gain variation range. Several popular VGA structures are discussed in detail in Chapter 3, and also the advantages and disadvantages are compared. This chapter will focus on the VGA design for our VPLC application. 4.1  Design Consideration  4.1.1  Gain Variation Range  Based on the preliminarily measurement of the channel response in our group [2], on a specific compact car, the input signal into the power line can be attenuated as large as 60 dB. No signal attenuation is needed in such a channel. A sample measurement result is shown in Fig 4.1.  Fig 4.1 S21 for three different paths. Car electronics turned on, including low-beam front lights (this is taken from Figure 5 in [2])  To well amplify the input signal into a predefined level at the output of VGA, a 2 dB gain variation for each step is desired. The gain is controlled digitally by the control signals 31  coming from the flowing DSP system, which is incorporated with the analog system to save power as well as the silicon area. If analogue control scheme is employed, then additional analog control circuit is needed to sense the amplitude of the output signal and then generate relevant control voltage/current to adjust the gain of the VGA. 4.1.2  Power Dissipation  Power consumption is usually one of the most important specifications for mobile or portable systems. Low power design is still an actively researched topic. The advancement of CMOS technology is also driven by the low power dissipation requirement in a system-on-achip (SoC) (some other factors are high speed, small size, etc.). For the VPLC system, there is an existing power supply, e.g. 12V or 42V DC, which can be potentially the supply voltage for the SoC (has to be regulated into the appropriate value before it can be applied to a certain CMOS technology). The power consumption requirement should not be problematic in this specific application, however, as a design target, we are still trying to optimize the power consumption in this VGA block. 4.1.3  Linearity and Noise Performance  Linearity and noise performance of a system actually determines the sensitivity of the system. Linearity performance is an indication of the maximum signal that this system can process without introducing too much distortion on the signal; noise performance determines the minimum signal that this system can detect in a noisy environment. IP3 (OIP3 and IIP3) and P1dB points are usually used to describe the linearity, and noise figure (NF) determines the noise performance of the circuit or the system. If a system is nonlinear then it will introduce harmonic distortions over the input signals. The signal corruption due to the third order inter-modulation (IM) of two interferers would  32  be troublesome. IP3 is a parameter used to describe this phenomenon. IP3 point is the intersection of the first order components and the IM3, as shown in Fig 4.2 (a). Fig 4.2 (b) is the logarithmic-scale presentation of (a).  20 log(α 1A) ΔP  α 1A  3 20 log( α 3A 3 ) 4 ΔP 2  3 α 3A 3 4  ΔP  ω1 ω 2 2ω1 − ω 2  20 log( Pin )  2ω 2 − ω1  Fig 4.2 IP3 and IP3 Calculation  On the other hand, we can derive the IIP3 from Fig4.2 (b) and (c), which is shown in equation 4(4.1) [37]. IIP3 |dbm =  ΔP |dB + Pin | dBm 2  (4.1)  The way to find out IIP3 of a system by simulation/test is called Two-Tone test. By applying two signals with close enough frequency and sufficiently small amplitude (avoiding saturation to the system) to the input and finding out the first order and IM3 intersection point at the output, the input power at this point is called IIP3. P1dB means 1 dB gain compression point, which describes the gain deviation by 1 dB from the ideal value when input amplitude to an amplifier increases and the amplifier starts stepping into saturation. The following equation can be used to calculate the P1dB point  P1dB = 20log( 0.145 |  α1 | α3  (4.2)  33  where α1 and α3 are the gains of the first and third harmonics. The relation between IIP3 and P1dB is shown in equation (4.3)  IIP3 ≈ P1dB + 9.6dB  (4.3)  One thing that is important and worth mentioning is the linearity of the cascaded amplifier or system. Assuming N stages are cascaded, the gain for each stage is Gi, and the IIP3 (OIP3) for the ith stage is IIP3i (OIP3i), then the total IIP3 (OIP3) follows the following equations [38]. G G1G2 G1G2...GN − 1 1 1 = + 1 + + .... + IIP3total IIP31 IIP32 IIP33 IIP3N  (4.4)  1 1 1 1 1 = + + + .... + OIP3total G2G3...GNOIP31 G3G4...GNOIP32 G4...GNOIP33 OIP3N  Observing the above equations, we can find out that different stages contribute different nonlinearity when it is referred to the input and is related to the gain of the following stages. Usually the latter stages determine the IIP3 of the overall system, which means that the optimization of the linearity performance of the latter stages is very important. The most common way to define the noise figure (NF) is NF =  SNRin SNRout  (4.5)  The overall NF of a cascaded system can be obtained based on the NF and gain of each stage in the system. A cascaded system is shown in Fig 4.3. VR2S  Vn21  I n21  Vn22  I n22  Fig 4.3 Cascaded noisy stages (this is taken from Figure 2.32 in [37])  34  where the input referred noise sources and input and output resistance of each stage is shown. Note that reactive components of the impedance are ignored. Then the total NF of such a system can be described by the following equation [37]. NFtotal = 1 + ( NF 1 − 1) +  NF 2 − 1 NFN − 1 + ... + G1 G1G 2...GN − 1  (4.6)  This equation is called Friis equation. It can be seen that the noise contribution from the latter stages are suppressed by the front stages, so the noise performance for the front stages are critical to the system. If the NF of the cascaded system needs to be optimized, then the gain of the first stages should be increased. The above discussion of linearity and noise performance of a cascade system reveals a conflict when it comes to optimization of linearity and noise performance simultaneously. To decrease the NF, the gain of the first stages of the system should be large, which will amplify the input signal to a larger value when it comes to the last few stages, imposing a high requirement on the linearity performance of the last few stages; on the other hand, if the linearity requirement is high, it is usually trying to avoid to adopt a high gain stage, which inevitably leads to a higher input-referred noise contribution. Based on the above observation, we propose the following structure (Fig 4.4) of the overall VGA for our application [39]. This structure essentially decouples the above conflicts, and it is easy the make tradeoffs between the linearity and the noise requirements by carefully selecting the gain of each stage in the VGA.  35  Fig 4.4 Block Diagram of VGA  The VGA is divided into 4 stages based on the following considerations: •  The noise performance is mainly decided by the first stage, so the first stage is  characterized by higher gain and lower noise performance. The gain is 18dB for this stage. The transistors in this stage are carefully sized, and also the power dissipation for this stage is higher in order to increase the transconductance of the input differential transistors to reduce the input-referred thermal noise and flicker noise •  The linearity heavily depends on the last stage. This stage avoids using the  high gain stage. Taking into account the gain variation, a full range of 14 dB for the gain is assigned to this stage. The linearity is optimized by utilizing a special technique called Gm-boosting which will be introduced soon •  For design simplicity, the last three stages are identical except there are some  extra switches in the last stage to implement a fine gain control, i.e. 2 dB/step •  Switches S0~S7 are important and used to decouple the tradeoff between noise  and linearity requirement. The on/off operations of the switches are determined according to the amplitude/power of the input signal. If the input signal is very large then the signal is routed to the latter stages by those switches and the front stages are bypassed, guaranteeing that these stages will not introduce any distortion on the 36  incoming signal. A small-signal will go directly from the first stage to the last stage. In order to detect such a small-signal, NF should be low for the first stage. On the other hand, since the input to this stage is small the linearity requirement is not high. •  Switches will also introduce distortions since they are on the signal path. To  reduce the distortion, a transmission gate can be used, and also transistor sizes should be optimized. Another technique called “bootstrapped switches” [40] can be a good replacement for the transmission gates, but since there are many switches this will complicate the design •  In summary, the first stage only handles small-signals, so NF but not linearity  is critical. The last stages have to accommodate larger input signals without introducing much distortion, so linearity is important but noise will be suppressed by the front higher gain stages. The switch operations and also the relevant gain settings are listed in Table 4.1. Table 4.1 Switch operations and the gain settings  A B C S0 S1 S2 S3 S4 S5 S6 S7 VGA1 VGA2 VGA3 VGA4 Anom(dB) 0  0  0  1  0  0  0  0  0  1  0  off  off  off  on  0~14  0  0  1  0  0  0  0  1  0  0  1  off  off  on  on  14~28  0  1  0  0  1  1  1  0  0  1  0  on  off  off  on  28~32  0  1  1  1  0  1  0  1  1  1  0  on  on  off  on  32~46  1  X X  0  1  0  1  0  1  0  1  on  on  on  on  46~60  The 60 dB gain is divided into 5 sections. A three-input digital circuit generates the 5 control signals so that the entire gain scenarios from 0 dB to 60 dB are covered.  37  4.1.4  Temperature Stability  The temperature stability requirement for vehicular application is very high. The circuit is required to function over a wide temperature range of -55ºC to 125ºC. To design such a circuit without involving too many process related transistor parameters, the VGA in this project is designed so that the gain is the production of resistor ratio and current ratio. The Gm-boosting technique that will be discussed soon in this chapter reduces the transconductance dependence on the parameters of the transistors. In the proposed circuit, the input voltage is converted into a linear current flowing through a source-degeneration resistor. This current is then copied to the output stage by a current mirror. A resistor is connected as the load at the output stage to achieve high linearity and also make the gain be the ratio of the load resistor and the source degeneration resistor. A simple temperature-stable reference voltage circuit is designed to properly bias the circuit. If a transistor is biased so that the Vgs is below the zero temperature coefficients (ZTC) point for a certain technology, then it is easy to make the Vgs temperature independent by only properly sizing the transistors; this Vgs can be used as the reference voltage. The design target is to minimize the gain deviation over the temperature variation range to be less than 1 dB if the gain step is set to 2 dB so as not introduce too much error on the amplitudes of the output signal. 4.2 4.2.1  Circuit Implementation The First Stage: Low Noise, High Gain Amplifier  As is analyzed above, the first stage should be optimized on noise performance. The linearity is not a challenge since this stage only receives small-signal. To optimize the noise performance, the thermal noise and flicker noise of the transistors in the stage itself is  38  optimized. On the other hand, the gain is designed to be high to suppress the noise coming from the following cascaded stages. Note that this stage is also asked to be temperaturestable. There are two options for this, as shown in Fig 4.5.  Fig 4.5 Two options for the first fixed gain stage  In Fig 4.5 (a), assuming the circuit is perfectly symmetric and the intrinsic output impedance of a transistor is very large, the gain of this stage is approximately depicted as  Av =  g m1 μn (W / L)1 = g m3 μ p (W / L)3  (4.7)  In PMOS and NMOS transistors, the relationship between the carrier mobility and the temperature can be simply described as  μn , p ∝ T − m  (4.8)  where m is about -1.5 in silicon. Both transistors are set with very large length in order to reduce the flicker noise at low frequency. To the first order, the gain is only affected by the size of the PMOS and NMOS transistors, irrelevant to the temperature variation.  39  Since the output nodes are relatively low impedance nodes, there is no need to design a CMFB circuit to fix the output common mode to a certain value, and this will simplify the design a lot. Fig 4.5 (b) presents a more intuitively stage regarding the temperature-stability. The gain is determined only by the size ratio of the input NMOS and the diode-connected NMOS transistors, as shown in equation (4.9)  Av =  g m1 (W / L)1 = (W / L)3 g m3  (4.9)  This topology indeed has less gain deviation over the temperature variation. However, this structure employs two branches, and each will consume a lot of power, especially considering that one of the design targets is to optimize the noise performance, the power consumption has to be large. Based on the above discuss, the circuit in Fig 4.5 (a) is employed in this design. Some modifications are needed to accommodate the low supply voltage and high output swing. Equation (4.7) can be rearranged into Av =  g m1 Vgs 3 − Vth = g m 3 Vgs1 − Vth  (4.10)  Equation (4.10) reveals that the overdrive voltage required for transistor M3 is much higher than that of M1 if this stage is designed into a higher gain. For example, if the overdrive voltage for M1 is 100mV, then the overdrive voltage for M3 has to be about 800mV for an 18dB gain. This will severely limit the output swing and might not get such a high overdrive voltage if the supply voltage is low. This is true for nowadays advanced technologies. To alleviate this stress, a pair of current source can be put in parallel with the diode connected PMOS transistors to take up some current, as shown in Fig 4.6 (a). 40  VDD  VDD  Vp M3 Vin+  M2  M1 Vb  M3  M4  kIb  Vin-  Vin+  M5  M6 M2  M1 Vb  Ib  M4 Vin-  Ib  (b)  (a)  Fig 4.6 Adding current sources to improve the gain  Now the gain is  Av =  g m1 1 Vgs 3 − Vth = g m 3 1 − k Vgs1 − Vth  (4.11)  If k is 0.8, then 80% of the DC current is routed into the PMOS current source and the overdrive voltage of the PMOS transistor is only 60% percent higher than that of the NMOS. Fig 4.6 (b) shows the implementation of the current sources using PMOS transistors. The total input referred noise of the circuit in Fig 4.6 (b) is determined by all the active elements in the circuit except the bottom current source, whose contribution is negligible. The noise is described by 2 n,in  V  g m3 g m5 KN gm2 5 1 8kT γ 1 KP 1 gm2 3 1 ={ + + + [1 + ]+ [ ]}Δf gm1 gm1 gm1 Cox (WL)1 f Cox f gm2 1 (WL)3 gm2 1 (WL)5  (4.12)  where γ, KN, KP are technology dependent constants. The transconductance of the input stage should be large while keep that of the PMOS current source and the diode-connected PMOS pair small in order to reduce the input referred noise. On the hand, to reduce the flicker noise, the transistor area should be increased, so the 41  transistor length is usually much larger than the minimum length that the technology can provide. The simulation results of the DC gain versus the temperature, and the input referred noise performance are presented in Fig 4.7.  Fig 4.7 Simulation performance of the first stage  From this figure, we can find out the DC gain deviation is less than 0.5dB, so the temperature stability is verified. The flicker noise dominates the performance of this stage at low frequency, for high frequency, the thermal noise will limit the circuit performance. The Gm-Boosting Technique  4.2.2  The gain of the amplifier with source degeneration resistor can be enhanced by using of floating gm-boosting amplifiers [41] or grounded gm-boosting amplifiers [42]. Grounded gmboosting amplifier is preferred regarding its simplicity in implementation and adapting to low-distortion switched technique [43]. Fig 4.8 shows the concept of gm-boosting technique [44].  42  Fig 4.8 Gm-boosting technique concept  Fig 4.8 (a) is a conventional source degeneration amplifier, which has been discussed in Chapter 3, and the transconductance of this circuit heavily depends on the transistor-related parameters. Fig 4.8 (b) is the gm-boosted circuit, where a feedback loop is added into the source degeneration amplifier. The input voltage is first converted into a current flowing through M1, and part of the current is then converted back to voltage at the drain of M1 and M2. The signal voltage at the drain of M1 is shifted by Mf3, and then applied to the gate of M3, which converts the voltage signal into a current. The current is subtracted from the signal current in M1 at the source, and the left current flows to the resistor. It will be shown that this current is quite linear based on the following analysis. The details in calculating the relationship between Vin and Vs; the current io and input voltage Vin are presented here The current flowing through transistor M1 is  i1 = g m1 (Vin − Vs )  (4.13)  vx = −i1 ⋅ (ro1 || ro 2 ) = − g m1 (ro1 || ro 2 ) ⋅ (Vin − Vs )  (4.14)  This current generates a voltage  The small-signal voltage is the same as the voltage at the gate of Mf3 43  v y = vx  (4.15)  i2 = g m 2 v y = − g m 2 g m1 ( ro1 || ro 2 ) ⋅ (Vin − Vs )  (4.16)  thus  Then we can get the current flowing through the source degeneration resistor Rs  io = i1 − i2 = g m1[1 + g m 2 (ro1 || ro 2 )] ⋅ (Vin − Vs )  (4.17)  noting that the voltage Vs is also determined by  Vs = io Rs  (4.18)  Re-arrange the above equations, we can find out io, Vs, i2 io =  g m1[1 + g m 2 ( ro1 || ro 2 )] Vin = g m1[1 + g m 2 ( ro1 || ro 2 )]Rs + 1 Rs +  Vs = io Rs =  1 1  (4.19)  g m1[1 + g m 2 ( ro1 || ro 2 )]  Rs Rs +  Vin  1  Vin  (4.20)  g m1[1 + g m 2 ( ro1 || ro 2 )]  g m1 g m 2 (ro1 || ro 2 ) g m1[1 + g m 2 (ro1 || ro 2 )] i2 = i1 − io = Vin 1 Rs + g m1[1 + g m 2 (ro1 || ro 2 )]  (4.21)  Define the transconductance of such a stage as Gm=io/Vin, with the output shorted to ground, then  Gm = [1 + g m 2 (ro1 || ro3 )]g m1  (4.22)  It shows the transconductance of this source degeneration stage is boosted by a factor of [1+gm2 (ro1||ro3)], which is a quite large value compare to1. If Gm is much smaller than 1/Rs (which can be easily met by proper design), then the above equations are simplified into  44  Vin Rs  (4.23)  Vs ≈ Vin  (4.24)  Vin Rs  (4.25)  io ≈  i2 ≈  From equation (4.24) the input signal is directly copied from the gate of the input transistor to the source. This voltage generates a current, which is depicted by equation (4.23), flowing throw the source degeneration resistor. This current is quite linear since it is flowing throwing a resistor. Due to the feedback, most of this current is stopped from flowing into the source of the input transistor M1 but is forced to flowing into transistor M2. The signal flows are annotated in the following figure.  Fig 4.9 Signal flowing direction in a Gm-boosting stage  In summary, gm-boosting actually copies the input voltage from the gate to the source, without introducing too much distortion over the signal. This copied voltage generates a linear current by a resistor. The overall transconductance of such a stage is 1/Rs, independent of the transistor -related parameters as long as the feedback loop is valid.  45  4.2.3  The Second and Third Stages Design  The second and third stages employ the gm-boosting technique and both are with a 14 dB fixed DC gain over the wide temperature range. The benefits are two-folded, the first one is the circuit can achieve a high linearity. The other is that these stages can be easily developed into a two-stage structure that the gain is temperature-stable. Modify the single ended gm-boosting stage into a differential one, as shown in Fig 4.10 (a). Fig 4.10 (b) shows the conventional differential pair with source degeneration for comparison purpose. In (a) and (b), the signal current will flow through the resistor Rs, however, the input voltage will mostly be copied to the source directly and then changed into a linear current by a resistor in (a) due to the gm-boosting technique. This current then will be injected into transistor M5 and M6 with relatively high linearity.  Fig 4.10 Differential source degeneration stage with Gm-boosting techniques  On the other hand, in Fig 4.10 (b), only a small portion of the voltage, VinRs/(1+gmRs), is copied into the source. This voltage is converted into a current by the resistor, and most of the current is then directed into the source of the transistor M1 since it sees low impedance at this node, therefore only a small portion of linear current is flowing to the transistor M5. 46  Now we have got a very linear signal current, if we can propose a way to copy the current to the output stage, and then convert it back to a voltage through another linear device, e.g. a resistor, then the output voltage turns out to be a very linear one. Keeping this in mind, the following circuit is proposed.  Fig 4.11 A full schematic of 2nd and 3rd stage  Since most of the signal current is also flowing through transistor M7 and M8, the current can be copied out by a pair of current source M7 and M9 (or M8 and M10). The current ratio is related to the size of transistors in these two pairs. To make the working environment more identical, another cascode transistor M11 is inserted on the top of the M9, the bias voltage is set to be the same as that of the nominal common mode voltage of M1 and M2. M11 will stabilize the voltage change at the drain of transistor M9. M9 and M11 will have the same bias condition as M7 and M1 to reduce the current mismatch between M7 and M9 due to the channel length modulation and other second order effects. The PMOS current sources are divided into two identical pairs; one is biased by a fixed voltage, the other by a voltage from the CMFB circuit. Splitting the current sources into two parts and one part being controlled by the CMFB circuit will speed up the common mode response. The CMFB circuit will be introduced latter. 47  The overall gain of the two-stage Opamp can be easily derived, as shown in (4.26) Av = N ⋅  RL Rs  (4.26)  where RL1=RL2=RL is the output resistive load, and the output impedance of the cascode structure is ignored since it will be quite larger than RL (800Ω here in this design). N stands for the current ratio of M9 and M7. As long as the transistors M7 and M9 work in saturation region, and the length is a bit larger, the current ratio N is relatively constant. In this design, N is about 2.5. Since the resistor ratio RL/Rs is accurate and linear, the overall gain is quite linear. The gain of these stages is relatively independent of temperature because the gain is affected by the current ratio and the resistor ratio. In our design, the resistors are all poly silicon resistors (the resistors with same materials have the same temperature characteristic), so the ratio of these two resistors is independent of temperature variation. As for the current ratio, the following equation can be easily derived N=  I 9,10 I 7,8  =β  {Vgs − Vth 0[1 + k 1(T − T 0)]} + α1Vds 9,10  (4.27)  {Vgs − Vth 0[1 + k 1(T − T 0)]} + α 2Vds 7,8  where β is the transistor aspect ratio, Vth0 is the nominal threshold voltage in the room temperature, and k1 is temperature coefficient of the threshold voltage. The discrepancy between α1 and α2 due to the temperature variation can be ignored. The critical parameter that will affect the accuracy is the Vds of transistor M7 and M9. This effect can be reduced to a minimal degree by employing a cascode structure as shown in Fig 4.11. At the room temperature, the Vds9,10 is set the same as Vds7,8. Another design method is to set the length of M7 and M9 to be a large value to reduce the impact on the current accuracy due to the channel  48  length modulation. The simulation result proves the temperature stability of the gain, as shown in Fig 4.12.  Fig 4.12 Simulation of the temperature dependence of the 2nd and 3rd stage  The gain over temperature range is very stable. The deviation is less than 0.2 dB, which shows little temperature-dependence. 4.2.4  The Fourth Stage Design  The core of the fourth stage is the same as the previous two stages. From equation (4.26), to achieve a gain variation, two plausible gain variation methods can be derived. The first one is to programming the current ratio N, as shown in Fig 4.13.  Fig 4.13 The 4th stage with programmable current ratio  49  The current of the output stage is programmable, the current value in each branch and the number of branches are determined by the gain steps and gain setting for each step. Since each branch accommodates different current value, in order to keep the output common mode voltage the same, the resistors RL1,i and RL2,i should be carefully chosen and laid-out. For small gain, the resistor will be large, since the current is small, and for large gain, the resistor is small due to the large current flowing through the resistor. The gain of this stage is Av = N i ⋅  RL Rs  (4.28)  where i=1,2,…k However, this gain variation methodology has several drawbacks: •  Limited bandwidth. There are an array of switches in the output signal paths, and an array of transistors will introduce substantial parasitic capacitance  •  Signal distortion due to the switches. These switches are usually implemented by the MOS transistors. The switches are at the output, where the switches experience a large signal swing, so if the switches are not properly design, they will severely distort the signal. A transmission gate can be a plausible way to relieve this problem  •  An array of resistors with different value is used, and they will occupy more chip area.  •  A complicated and accurate bias circuit is needed to generate a lot of bias voltages, Vb1, Vb2, …Vbk, so this will complicate the overall design  •  Gain accuracy is not high, and also output common mode voltage is actually not easy to control if there is any mismatch between the resistors in an array  50  We observe that in the equation (4.26), there is another factor that is changeable, i.e. the equivalent source degeneration resistor or the equivalent output resistor RL. This way is shown in Fig 4.14. Two arrays of switched resistors are used in this gain variation scheme. The first one contains only Sw0, which is connected in parallel with the source degeneration resistor Rs. This switch divides the overall stage gain into 0-6 dB and 8-14 dB sections. When Sw0 is high, the gain can be changed from 8-14 dB, otherwise, the gain changes from 0-6 dB. The other array is connected between the differential outputs, and contains 3 switched resistors.  Fig 4.14 A 4th stage with programmable resistance  The gain of this stage is depicted in equation (4.29) Av = N ⋅  R L ,i  (4.29)  Rs , j  51  where i=1, 2, 3 and j=0 or 1. The switching operations and the accordingly gain settings are shown in Table 4.2 Table 4.2 Fine gain settings  SW0  0  0  0  0  1  1  1  1  SW2  0  1  1  1  0  1  1  1  SW3  0  0  1  1  0  0  1  1  SW3  0  0  0  1  0  0  0  1  Gain (dB)  0  2  4  6  8  10  12  14  The advantage of this gain variation scheme is •  Large bandwidth. There are no switches directly appear in the output signal path. The bandwidth is only limited by resistor RL1 (RL2)  •  Lower signal distortion. Since for some gain steps, there is no switch appears in the signal path to limit the swing  •  Well defined common mode voltage at output. The switched resistors do not affect the output common mode voltage, so the output common mode voltage can be accurately controlled by a CMFB circuit  •  No additional bias voltage is needed to bias these switches However, there are still some problems when using the above switching scheme:  •  Gain accuracy is limited by the switches. The switches are not ideal, and they will present some resistance in parallel with the resistors used to control the gain. A MOS transistor with a large width could be used as such a switch. However, the large parasitic capacitance of the switch will limit the bandwidth  52  •  For some gains, the switches will still introduce distortion to the signals, because when the switched resistors are used to control the gain, a portion of the signal current will flow through the switches, introducing distortion. The origin of the above issue is due to the non-ideality of the switch. It is essential to  analysis the switched resistors in details to find out the design methodologies to reduce the distortion. Fig 4.15 shows the switched resistor and its model of the switched resistor [25].  Fig 4.15 Switched resistor and the model  where rds is the equivalent on-resistance of the switch, the capacitors are the parasitic capacitors related the bandwidth. The small-signal that flows through the switched resistor can be described by [25] I d = g dsVds + α 2Vds2 + α 3Vds3  (4.30)  where gds is the drain-source conductance, α2 and α3 are the second- and third-order nonlinear coefficients. In our design the operation is differential, the even order distortion can be ignored, i.e. α2=0. The HD3 is described by the following equation [25] HD3 =  2 2 Vout Vov Vout RL 1 γ γ − + [ ] [ + ]2 3 3 4 2 3/2 4 3 5 1/2 4Rt β Vov 2( L ⋅ Ec ) 24(φ0 + Vsb ) 2Rt β Vov 2 4(φ0 + Vsb )  (4.31)  where Rt=RL+rds is a fixed value that is determined by the gain, and Vov is the overdrive voltage of the transistor functioning as a switch, and the production of L and Ec is to describe the carrier velocity saturation, φ0 + Vsb is to describe the body effect.  53  From the above description, the following optimization methods can be adopted: •  Using PMOS to substitute NMOS. Each PMOS has its own NWell, so the source and bulk can be connect together to eliminate the distortion introduced by the body effect  •  Trying to increase the overdrive voltage as much as possible  •  Using a larger transistor to get a larger β. Avoid using the minimum transistor length to reduce the distortion originated from velocity saturation. However, large length will increase the parasitic capacitance, therefore limits the bandwidth Another optimization method that is not indicated in equation (4.31) is to make one end  of switch be connected to the (virtual) ground. The above techniques are applied to the switched resistors, the size of the transistors are determined by simulation. The final structures of the switched resistors are shown in Fig 4.16, the value of the resistors and the sizes of the transistors used as switches are shown in Table 4.3.  Fig 4.16 The modified switched resistors for gain control in the 4th stage  On the other hand, in Fig 4.16, we can find out that the common-drain of the transistors functioning as switches is virtual ground, and this node can also be used to extract the output common mode voltage.  54  Table 4.3 Parameters for switched resistors  Components  Value  Components  Size  Rw0  160Ω  Sw0  4μm/0.16μm  Rw1  605Ω  Sw1  4μm/0.20μm  Rw2  1130Ω  Sw2  4μm/0.20μm  Rw3  2600Ω  Sw3  4μm/0.20μm  4.2.5  CMFB Circuit Design  A CMFB circuit is needed for the latter three stages in the VGA to well define the output common mode voltage. The way to sense the output common mode voltage is shown in Fig 4.16. There is another pair of large resistors connected between the differential outputs directly to sense the output common mode voltage if the switched resistors at the output are not used for certain gains. The CMFB circuit structure used in this design is a two-stage Opamp with Miller compensation [23]. The circuit is shown in Fig 4.17. VDD M4  M3  M6 M1  Rc Cc  M2  VCMFB  Vin-  Vin+ Vb  Vb  M5  Fig 4.17 CMFB circuit for the VGA  The frequency response is shown in Fig 4.18.  55  Fig 4.18 Frequency response of CMFB circuit  4.2.6  The Bias Voltage Design  Bandgap reference in the CMOS technology is usually implemented using the parasitic bipolar transistors [23]. However, with the decreasing of the supply voltage towards 1V (in this design the supply voltage is 1.2V); the performance of the conventional bandgap reference degrades. A circuit with complicated design technique is usually proposed to maintain the comparable performance. The presence of the zero temperature coefficient (ZTC) point can be used for design of a low-voltage reference circuit, and the performance can be maintained to be comparable of a bandgap reference. In [45], a simple voltage reference is designed which is suitable for low voltage application, and the circuit is shown in Fig 4.19.  56  Fig 4.19 Temperature-stable voltage reference  The circuit contains a PTAT current source that is used to bias a diode-connected NMOS transistor, which operates below the ZTC point. In such a way, by proper sizing and biasing, the drain voltage (also the same as Vgs) will have a zero temperature coefficient. The details to derive such a relationship are shown in [45]. To get a zero temperature coefficient, the following constraint has to meet  αV (  (  W )4 L  (4.32)  W )5 = m L ( − α Rb )( K 6 I ref ) T0 th  The simulation result of the bias voltage versus the temperature variation over the required temperature range is shown in Fig 4.20.  Fig 4.20 Bias voltage versus temperature variation  57  The simulation result reveals the bias voltage is very stable regarding the temperature variation. The voltage deviates from the nominal value less than 4mV. 4.3 4.3.1  Simulation Results of VGA The Frequency Response of the VGA  The frequency response of the proposed PGA is shown in Fig 4.21. At the maximum gain of 60 dB, the simulated -3dB bandwidth is 90 MHz, and at the minimum gain of 0 dB, the bandwidth increases to 210 MHz (assuming a 2 pF capacitive load).  Fig 4.21 Frequency response of the VGA for some gain settings  4.3.2  The Linearity of the VGA  To characterize the linearity of the VGA, P1dB is simulated at two special gain points, 0 dB and 60 dB respectively. For a 0 dB gain, the input signal is large, and the signal will go to the last stage directly, which means the linearity is mainly determined by the last stage (other distortion comes from the switches on the signal paths). For the 60 dB gain, all the stages are now used, the linearity will also be affected by the front stages, however, since the amplitude of the signals go into the front stages are relatively small, the distortion generated by these front stages is relatively small, the linearity then still decided by the last stages. The P1dB is shown in Fig 4.22.  58  Fig 4.22 P1dB for minimum gain setting and maximum gain setting  4.3.3  The Dependence of the Gain upon the Temperature  The simulation result of the gain versus temperature variation is shown in Fig 4.23. The gain step is 2 dB. Each gain step is simulated over an extended temperature range, and then the gain deviation from their nominal value is found out.  Fig 4.23 VGA gain versus temperature at different gain settings.  59  4.3.4  Summary  The simulation results are summarized in Table 4.4. Table 4.4 Simulation results summary  Parameters Bandwidth (MHz)  Simulation result 90-210  Parameters Gain range (dB)  P1dB at 0 dB gain (dBm)  2.25  P1dB at 60 dB gain (dBm)  Gain deviation (dB)  ≤ 0.3  Gain deviation (dB)  (-30ºC to 80ºC)  Simulation result 0~60 -53 ≤ 0.9  (-55ºC to 125ºC)  60  Chapter 5: Experimental Setup and Measurement Results This chapter provides the experimental setup and test procedures to test the individual stages in the VGA and also the overall VGA. Section 5.1 gives the technique descriptions of the circuit and layout to properly characterize the VGA. Section 5.2 lists the required equipment, as well as test schematics and procedures for testing that are feasible with the available equipment. Section 5.3 summarizes the test results. 5.1  Circuit and Layout Characteristics  As a proof of concept, a chip is fabricated in IBM 0.13-μm CMOS technology. The core area of the chip is 300μm × 400μm, and the chip is pad limited. The fabricated chip includes the proposed VGA and its control signal generating circuit, biasing circuit, and other switches for testing purpose. Fig 5.1 shows the VGA layout with names of the pads.  Fig 5.1 VGA layout  Table 5.1 lists all the names of the pads, mappings, and the usages. 24 pins are used for this chip. Most pins are used as switches for the gain control purpose. 61  Table 5.1 Pins and the usage  Pin  Pin Name  Pin Usage  1, 2, 4, 23  SW3 ,SW2, SW1, SW0  Switches for fine gain control (2 dB/step); the switching operations are shown in Table 4.2.  3, 5  Vout-, Vout+  Differential outputs from buffer (with 50 Ω load)  6  Vbuffer  Bias voltage applied to buffer from external  7, 9  Vin+, Vin-  Differential input signal, from 100 KHz to 30 MHz  8, 11, 16, 19  GND  0V  10, 15,24  VDD  1.2V DC (there is ±10% variation)  12, 13, 14  A, B, C  The control signals to route the input signals to different stages based on the signal amplitudes  18, 20  E, D  Control switches for test purpose, DE=00, the 1st stage under test, DE=01, the 2nd stage under test, DE=10, the third stage under test, DE=11, the fourth stage under test  17,21  Tout+, Tout-  Un-buffered differential outputs  22  ESD_VDD  High voltage for ESD protection purpose  5.2  Measurement Setup  The characteristic of the VGA is tested in both time and frequency domains. The bias points of the circuit are checked first, and then the circuit is tested beginning from the last stage to the front stages, and finally the overall VGA is tested. The equipments required for the test are listed in Table 5.2.  62  Table 5.2 Test equipments  Quantities  Equipment  1  Agilent 8648D 9 KHz-4 GHz Signal Generator  2  XANTREX LXQ30-2 DC Power Supply  1  HP 8753E 30 KHz-3GHz VNA  1  Anritsu MS2034A Spectrum Analyzer  1  Lecroy 9310A Dual 400 MHz Oscilloscope  2  Power Splitter  2  0-6GHz Bias Tee  4  0-12GHz Attenuator (-20 dB and -6 dB)  >10 1  6GHz Cables Fluke 79 Series II Multi-Meter  The print circuit board (PCB) for the test is shown in Fig 5.2.  Fig 5.2 PCB for test of VGA  63  5.2.1  Time Domain Characteristic Measurement  To observe the waveforms in the time domain, the following test bench is setup to get the amplitude of the output waveforms at different gain settings.  Fig 5.3 Transient response test setup  There are four stages in cascading, and each stage is tested to make sure it is functional. The test procedure is shown in Table 5.3, and the results are in Fig 5.4. Table 5.3 Transient response result  Input  Stage (s) to  signal  verify  5 mVp-p  4  5 mVp-p  Nominal DC gain  Measured DC  Results shown in  gain  Fig 5.4  14 dB  14 dB  (a)  3,4  28 dB  27.2 dB  (b)  1 mVp-p  1,3,4  42 dB  42 dB  (c)  1 mVp-p  1,2,3,4  46 dB  45 dB  (d) 64  Fig 5.4 Function verification for each stage in the VGA  The sensitivity of the signal generator is 1 mVp-p in this test. The supply voltage of the circuit is 1.2 V, input common mode voltage for the VGA is set to 800mV, and the voltage to bias the buffer is 500mV. The overall DC current drawn by the chip is 9.2 mA which is close to the simulation result. Limited by the instrument sensitivity, the test for the high gain is done only by setting the fourth stage into 0 dB gain scheme to avoid saturation. The nominal gain is 46 dB (that is the sum of 18 dB, 14 dB, and 14 dB for the first three stages). The above test can be used to verify that each stage works properly. However, we observe that the 65  circuit suffers a severe offset between the two differential channels, and the offset is as large as 120 mV. For high gain settings, this offset will limit the swing of the VGA, and inevitably drives the following stages into saturation. This offset can be due to the process variation, and special technique should be adopted to cancel out the offset on chip. 5.2.2  Frequency-Domain Characteristic Measurement  In this section the circuit characteristic in frequency domain will be presented. 5.2.2.1  AC Response  The test setup is shown in Fig 5.5 Attenuator RF DC  Bias T Power Splitter  Bias T  DC Source  RF+DC  Attenuator  800mV  1.2V  DC Source  DUT(VGA) 500mV  Sw0 ...Sw3 D,E A,B,C VNA  Fig 5.5 Test setup for AC response of VGA  The VNA is calibrated with the output signal power of -40 dBm. The attenuators are only used when the gain setting is higher than 44 dB, i.e. the four stages are used in the VGA. An attenuator with -20 dB attenuation is used for 46 dB to 52 dB gain range, an additional  66  attenuator with -6 dB attenuation is cascaded to the previous attenuator to measure the gain when the VGA is set to vary the gain from 54 dB to 60 dB. The test starts at the last stage, configuring the gain in the last stage by Sw0~Sw3 into different settings. The test results for the AC response are shown in Fig 5.6. The data for the last two gain steps (58 dB and 60 dB) cannot be obtained due to limitation of the calibration accuracy from the VNA, the data recorded is invalid.  Fig 5.6 Measured gain settings  5.2.2.2  Linearity Measurement  To find out the linearity of the VGA, P1dB is measured for different gain settings and also different input signal frequencies. The test setup is shown in Fig 5.7. The test procedure is shown in Table 5.4, and it covers the gains of 0 dB, 30 dB, and 52 dB. The input signals are chosen at frequencies of 10 MHz, 30 MHz, and 80 MHz, respectively. The test results are shown in Fig 5.8 and summarized in Table 5.4. 67  Table 5.4 P1dB measurement results summary  Frequency  Gain  P1dB  Frequency  Gain  P1dB  Frequency  Gain  P1dB  (MHz)  (dB)  (dBm)  (MHz)  (dB)  (dBm)  (MHz)  (dB)  (dBm)  10  0  -7  30  0  -8  80  0  -8  10  44  -50  30  44  -51  80  44  -53  10  52  -56  30  52  -55.5  80  52  -59  Signal Generator RF+DC RF DC  Bias T Power Splitter  DC Source 800mV  Bias T 1.2V  DC Source  DUT(VGA) 500mV  Sw0 ...Sw3 D,E A,B,C Spectrum Analyzer  Fig 5.7 Linearity measurement of the VGA  The linearity at low gain decreases a lot compared to the simulation result. Two possible factors are, for one, the mismatch between the resistors, since the gain heavily depends on the matching of the resistors, however, the accuracy of the absolute value of the resistor is not guaranteed during fabrication, even though special layout technique is used (dummy, 68  common-centroid layout, etc.), the symmetry deviates from the ideal situation; for another, the offset, several stages are cascaded without offset cancellation, the offset from the previous stages will be amplified and presented at output of the latter stages, this will make some circuits in the latter stages saturate. 5.3  Performance Summary and Comparison  The performance of the VGA and comparison between some other published works are shown in Table 5.5. Table 5.5 Performance summary and comparison  Parameters  This work  [8]  [6]  CMOS technology  0.13μm  0.18μm  0.25μm  Bandwidth (MHz)  80~210  32~1050  30~210  Power consumption (mW)  11  6.5  ≤ 27.5  Supply (V)  1.2  1.8  2.5  Gain Range (dB)  0.67~56  -52~43  -35~55  Gain Stages  4  2  4  Gain Control  Digital  Analogue  Analogue  P1dB @ small Gain (dBm)  -7 @0.67 dB  -17@-52 dB  -8@-35 dB  P1dB @ large Gain (dBm)  -56 @52 dB  -48@-43 dB  -40@-55 dB  69  Fig 5.8 P1dB measurement results for different gains and input signal frequencies  70  Chapter 6: Active Inductor for VPLC 6.1  Introduction  A VPLC has the potential of replacing abundant of wires dedicated for the data communication systems by the power lines in the vehicles. However, replacing the dedicated communication channels by the power lines brings out numerous challenges. One is the dependence of the input impedance of the network upon the frequency, time, and location. Based on the measurement work in our group [46], the inductive loads in the vehicles dominate the shape of the input impedance of the network, making the total input impedance change a lot in different frequency ranges and with different loads. Therefore, to maximize the signal power delivery, a compacted adaptive impedance matching network with wide tuning range is essential. An LC network is usually used for the purpose of impedance matching (conversion). A high-quality passive inductor sometimes is not available for a certain digital CMOS technology. On the other hand, an on-chip passive inductor occupies a large silicon area. The choice of an inductor is limited by the area (inductance), parasitic and quality factor. The quality factor is limited to a low value by the design and technology. Another drawback is that a precise model for a passive inductor sometimes is hard to get, resulting in a bad design. Active inductor can be a replacement for a passive inductor. Active inductor provides the following advantages over the passive one: much less silicon area with an area that is almost independent of the inductance, high quality factor, and a wide tuning range. However, as compared to their passive counterpart, active inductors will present higher noise since they are based on active transistors, and they also consume power. The drawbacks can be minimized in a given design.  71  6.2  Active Inductor Review  6.2.1  Active Inductor Theory  A Gyrator-C network consists of two back-to-back transconductors with a capacitor connecting to either port of the transconductors. A Gyrator-C network is said to be ideal when both the input and output impedance of the transconductors of the network is infinite. 6.2.1.1  Ideal Single-Ended Gyrator-C Active Inductor  An ideal grounded Gyrator-C active inductor is shown in Fig 6.1, and the input impedance of such a network is shown in equation (6.1).  Z in =  Vin C =s iin Gm1Gm 2  (6.1)  Fig 6.1 Lossless single-ended Gyrator-C active inductor  Hence the equivalent inductance is  Leq =  C Gm1Gm 2  (6.2)  We should notice that the ideal Gyrator-C network keeps inductive impedance over the entire frequency range. 6.2.1.2  Ideal Floating Gyrator-C Active Inductor  If both the equivalent terminals of a differential active inductor are not grounded or powered by power supply directly then the active inductor is said to be a floating inductor. 72  Fig 6.2 shows the principle for an ideal floating Gyrator-C active inductor. Based on the depiction shown in the figure, the following equation is met  Z in =  Vin 2C =s iin Gm1Gm 2  (6.3)  Fig 6.2 Lossless floating Gyrator-C active inductors  An equivalent inductance presented in this structure is  Leq =  2C Gm1Gm 2  (6.4)  From equation (6.4), we can also find out that the inductance is twice of that can get in a grounded active inductance. 6.2.1.3  Grounded Gyrator-C Active Inductor with Loss  If the input or output impedance of the transconductors in the Gyrator is not infinite, then loss will be introduced by the resistance or conductance at the input or output. A grounded Gyrator-C active inductor including the parasitic output impedance is shown in Fig 6.3, where Rout1 and Rout2 are the output impedance of transconductor 2 and 1 respectively.  Fig 6.3 Grounded Gyrator-C active inductor with loss  73  The input conductance of this active inductor is described by [47] Y=  iin 1 = sC1 + + vin Rout1 s  1  (6.5)  C2 1 1 + Gm1Gm 2 Rout 2 Gm1Gm 2  We define R p = Rout 2  (6.6)  C p = C2 Ls =  C2 Gm1Gm 2  Rs =  1 1 Rout1 Gm1Gm 2  Hence the following equivalent circuit is obtained based on the above equation.  Fig 6.4 Equivalent circuit for the grounded active inductor with loss  The parallel resistance Rp should be maximized, while the series Rs should be minimized to avoid the decrease of the quality factor of the active inductor. From the other hand, we can find out the resonant frequency of this active inductor. The equation is shown as  ωo = ωt ,i =  Gm1 Gm 2 1 = = ωt1ωt 2 C1 C2 Ls C p  (6.7)  Gm ,i Ci  where i=1 or 2. ωt is the cut-off frequency of the transconductors. ωo is the self resonant frequency of the Gyrator-C active inductor. This ωo is typically the maximum frequency at  74  which the active inductor can operate properly. The ωo of an active inductor is set by the ωt of the transconductors in the active inductor. 6.2.2  Previous Work  In Fig 6.5 the core of several previous works is presented [12]. Since the Gyrator involves both a positive transconductance and a negative transconductance, the basic idea is to construct the above structure, then place a capacitor at the proper position in the circuit.  Fig 6.5 Different structures as Gyrators (this is taken from Figure 2.8 in [48])  There are other four possibilities to change the NMOS to PMOS and vice versa. The bias requirement for the common drain (CD) structure is higher and not easy to reach when the supply voltage is low, thus the tuning range of the inductance is limited, for the other topologies, a wider tuning range can be achieved. Extra circuit is needed to compensate the parasitic resistance maintain a high quality factor. A work that realized this idea is shown in [49].  75  6.3  Active Inductor Design for VPLC  The active inductor designed for VPLC impedance matching network should have the following properties: limited current draw and current branches to keep the power as low as possible, low‐voltage headroom to allow for low supply voltage applications, a wide tuning range of inductance through a simple tuning mechanism, and a low loss resistance. A topology of active inductor that is suitable for VPLC application is shown in Fig 6.6 [12].  Fig 6.6 The active inductor architecture (a) and its simplified model (b)  It is straightforward to verify that the equivalent inductance of this active inductor is the same as that stated in the grounded active inductor. Cp here is the parasitic at the gate of transistor M2. Cp includes the gate source capacitance of M2, gate drain capacitance and drain-bulk capacitance of M1. The small-signal model of the above circuit is shown in Fig 6.7, where go in this model means the output conductance of the transistor or the current source.  76  Fig 6.7 Small-signal for the active inductor  The input impedance of this circuit in the rectangle is described by Z in =  g o1,i + g o1 + s (Cgs 2 + Cgd 1 + Cgd 2 ) vin ≅ iin g m1 g m 2 + g m1 g o1,i + g o1,i g o1 + g m 2 g o1 + s ( g m1Cgs 2 + g m1Cgd 1 + g m 2Cgd 2 )  (6.8)  Some terms in the denominator of equation (6.8) will only be dominant when the frequency is higher than the resonant frequency. Since our circuit is designed to work below such a frequency, we can be certain that the product of gm1gm2 will dominate the denominator. Now the input impedance for the circuit in the rectangle is simplified into Z in = s  (Cgs 2 + Cgd 1 + Cgd 2 ) g m1 g m 2  +  go1,i + g o1  (6.9)  g m1 g m 2  Combining the left circuits in Fig 6.7, the overall equivalent circuit is simplified into  Fig 6.8 Equivalent circuit for the active inductor topology for this design  where  77  C p = C gs1 Rp = Rs = Ls =  (6.10)  1 1 1 || || g m1 g 02 g o1,i g o1 + g o1,i g m1 g m 2 C gs 2 + C gd 1 + C gd 2 g m1 g m 2  The resonant frequency and the cut-off frequency is the same as that is shown in equation (6.7). To get a wide frequency range, both cut off frequencies should be high enough, and to keep the quality factor, the cut-off frequency of M2 should be kept higher. To compensate the parasitic resistor Rs in series with the inductor, a circuit presenting negative impedance can be used so that it can generate the power to compensate the power consumed by the parasitic resistor. The structure for this design is shown in Fig 6.9.  Fig 6.9 Placing a negative resistance for compensation  From Equation (6.10), to tune the inductance of the circuit, one can change the transconductance of both transistors by changing the bias current only. The sizes of the transistors can also be changed, however, the parasitic will also changed accordingly, and this will actually sometimes gains no inductance change. Here we proposed another way to tune the equivalent inductance, which is shown in Fig 6.10.  78  Fig 6.10 Proposed ways to tuning the inductance  A capacitor is added to the gate of transistor M2, and it is also set tunable. The unity capacitance used here is set as the minimum capacitance obtainable in this technology. The unity capacitance is about 60 fF, and the total capacitance of C is about 0.8 pF. On the other hand, in order not to decrease the quality factor, the transistor M2, but not M1, is also set tunable. Transistor M2 consists of five pairs of transistors, the size of which increases in a binary format. In order to keep the bias points unchanged, the top current source is also changed accordingly to make sure this current source provides the extra current to the extra M2 transistors. As shown in Fig 6.11, four switches, S1~S4, are used to route the transistors and current sources to connect or disconnect to the active inductor, therefore the transconductance of M2 is changed. For the test purpose, the capacitors are also split into an array of smaller capacitors. The combinations of the capacitors are shown in the equation (6.11). The total capacitance for each step is changed by d0d2…d7, and the capacitance changes by 20 fF (about 0.33C0) between two adjacent control signals. (Note this is just for test purpose, there are definitely other optimized combinations of the capacitors considering the tuning simplicity).  79  VDD  VDD  vin  M2  Vb  (W/L)p  VDD  Vb1  VDD  VDD  VDD  VDD  VDD  S1  S2  S3  S4  (W/L)p  2(W/L)p  S1  (W/L)n  Vb  VDD  VDD  (W/L)n S1  8(W/L)p  4(W/L)p  S3  S2  2(W/L)n S2  S1  vin  8(W/L)n S4  4(W/L)n S3  S2  S4  S3  S4  Fig 6.11 tunable transistors and current sources  C = d 0 ⋅ C0 + d1 ⋅ C0 + d 2 ⋅ C0 + d3 ⋅1.33C0  (6.11)  + d 4 ⋅1.33C0 + d5 ⋅1.67C0 + d 6 ⋅1.67C0 + d 7 ⋅ 4C0 where C0 is the unity capacitor of 60 fF, by changing the control signals d0~d7, C can change from C0 to 13C0. A wide tuning range can be achieved by using the above tuning scheme. The maximum inductance is achieved when only one branch of M2 and the current source is connected in active inductor, and the minimum inductance is achieved when all the M2 are connected to the active inductor but only one unity capacitor is connected to the gate of M2. 6.4  Simulation Results  The frequency range that we target in is 100 KHz to 30 MHz, however, the cut off frequency of this proposed active inductor is severely limited by the added capacitor at the gate of transistor M2. This limits our circuit to present inductive characteristics only below the frequency range of 50 MHz. The frequency range in which the inductance keeps constant is even smaller, e.g. smaller than 20 MHz. The maximum inductance can be achieved is plotted in Fig 6.12.  80  Fig 6.12 Maximum inductance achievable for this design  Fig 6.12 (a) shows the magnitude of the reactance, and Fig 6.12 (b) shows the equivalent inductance. From the simulation, the maximum achievable inductance is 6.27 mH. Fig 6.13 shows the minimum achievable inductance is about 0.3 μH.  Fig 6.13 Minimum achievable inductance for this design  The resistance for the maximum inductance is shown in Fig 6.14 (a), and (b) is the calculated quality factor. The quality factor of this inductor is very large for frequencies from 500 KHz to 50 MHz.  81  Fig 6.14 Resistive part and the quality factor for a maximum inductance  Fig 6.15 shows the linearly tuning ability of the inductor. By changing the switches, the inductance can be varied linearly. When the capacitance connected to the gate of transistor M2 is large (i.e. larger inductance), the linearity is better, because the nonlinear parasitic capacitance at this node is negligible, and when only smaller capacitors are employed, the nonlinear capacitance becomes dominant, the linearity decreases.  Fig 6.15 Linearity simulation for the active inductor  6.5  Summary  An active inductor is designed based on the grounded Gyrator-C structure. A negative impedance network is included in the inductor to compensate the parasitic resistance. The 82  inductance is tunable by both switching the transistors and the capacitors. The inductance can vary from 0.3 μH to 6.27 mH, and the linearity is good at high inductance. The drawback is the limited bandwidth caused by the added capacitance at the gate of transistor M2.  83  Chapter 7: Conclusion 7.1  Design Conclusion  A VGA and an active inductor that are suitable for VPLC application are designed, fabricated, also the VGA is tested. Though some temperature-stable VGA have been published, in this thesis, a VGA employing a Gm-boosting technique is presented whose performance is stable over a wide temperature range. On the other hand, the linearity is also guaranteed and verified by testing. The test results reveal a good gain setting for each step and wide bandwidth. Due to the facility limitation and time limitation, the dependence of the gain on temperature variation is not verified for this moment. The active inductor is designed based on the grounded Gyrator-C structure, and it is characterized with wide inductance range and linear tuning ability by simulation. The inductance can vary from 0.3 µH to 6.27 mH. The linearity is good at high inductance. However, the bandwidth of this inductor is just limited to about 20 MHz. 7.2  Future Work  Although the temperature stability of the proposed VGA is validated using simulations, the gain dependence on temperature needs to be tested and to be compared with the simulation results. An offset cancellation circuit is also necessary to take care of the offset in such a cascaded system for the next design of the VGA. A circuit that can detect the amplitude of the input signal should be designed so that it can generate control signals to adjust the gain of the VGA automatically. For the active inductor, the future step is to design the PCB for the test. If the idea is verified by the test, then the active inductor should be incorporated into an impedance  84  matching network to find out the impedance range that this circuit can cover. The way to increase bandwidth should also be investigated. The noise performance of such an active inductor is also an interesting topic.  85  Bibliography [1] Okazima, N., “Propagation characteristics of power line communication signals along a power cable having semiconducting layers”, IEEE transactions on electromagnetic compatibility, Aug. 2010, pp.756-769 [2] M. Mohammadi, L. Lampe, M. Lok, S. Mirabbasi, M. Mirvakili, R. Rosales, and P. van Veen, “Measurement study and transmission for in-vehicle power line communication,” in IEEE International Symposium on Power Line Communications (ISPLC), Apr. 2009, pp. 73–78 [3] S. Barmada, M. Raugi, M. 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                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
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                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
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